On gate stack scalability of double-gate negative-capacitance FET with ferroelectric HfO2 for energy efficient sub-0.2 V operation

NASA Astrophysics Data System (ADS)

Jang, Kyungmin; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2018-02-01

We have investigated the gate stack scalability and energy efficiency of double-gate negative-capacitance FET (DGNCFET) with a CMOS-compatible ferroelectric HfO2 (FE:HfO2). Analytic model-based simulation is conducted to investigate the impacts of ferroelectric characteristic of FE:HfO2 and gate stack thickness on the I on/I off ratio of DGNCFET. DGNCFET has wider design window for the gate stack where higher I on/I off ratio can be achieved than DG classical MOSFET. Under a process-induced constraint with sub-10 nm gate length (L g), FE:HfO2-based DGNCFET still has a design point for high I on/I off ratio. With an optimized gate stack thickness for sub-10 nm L g, FE:HfO2-based DGNCFET has 2.5× higher energy efficiency than DG classical MOSFET even at ultralow operation voltage of sub-0.2 V.

Junctionless tri-gate InGaAs MOSFETs

NASA Astrophysics Data System (ADS)

Zota, Cezar B.; Borg, Mattias; Wernersson, Lars-Erik; Lind, Erik

2017-12-01

We demonstrate and characterize junctionless tri-gate InGaAs MOSFETs, fabricated using a simplified process with gate lengths down to L g = 25 nm at a nanowire dimension of 7 × 16 nm2. These devices use a single 7-nm-thick In0.80Ga0.20As (N D = 1 × 1019 cm-3) layer as both channel and contacts. The devices show SSsat = 76 mV/dec, peak g m = 1.6 mS/µm and I ON = 160 µA/µm (at I OFF = 100 nA/µm and V DD = 0.5 V), the latter which is the highest reported value for a junctionless FET. We also show that device performance is mainly limited by high parasitic access resistance due to the narrow and thin contact layer.

Quasi-free-standing bilayer epitaxial graphene field-effect transistors on 4H-SiC (0001) substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yu, C.; Li, J.; Song, X. B.

2016-01-04

Quasi-free-standing epitaxial graphene grown on wide band gap semiconductor SiC demonstrates high carrier mobility and good material uniformity, which make it promising for graphene-based electronic devices. In this work, quasi-free-standing bilayer epitaxial graphene is prepared and its transistors with gate lengths of 100 nm and 200 nm are fabricated and characterized. The 100 nm gate length graphene transistor shows improved DC and RF performances including a maximum current density I{sub ds} of 4.2 A/mm, and a peak transconductance g{sub m} of 2880 mS/mm. Intrinsic current-gain cutoff frequency f{sub T} of 407 GHz is obtained. The exciting DC and RF performances obtained in the quasi-free-standingmore » bilayer epitaxial graphene transistor show the great application potential of this material system.« less

Atomic layer deposited Ta2O5 gate insulation for enhancing breakdown voltage of AlN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Deen, D. A.; Storm, D. F.; Bass, R.; Meyer, D. J.; Katzer, D. S.; Binari, S. C.; Lacis, J. W.; Gougousi, T.

2011-01-01

AlN/GaN heterostructures with a 3.5 nm AlN cap have been grown by molecular beam epitaxy followed by a 6 nm thick atomic layer deposited Ta2O5 film. Transistors fabricated with 150 nm length gates showed drain current density of 1.37 A/mm, transconductance of 315 mS/mm, and sustained drain-source biases up to 96 V while in the off-state before destructive breakdown as a result of the Ta2O5 gate insulator. Terman's method has been modified for the multijunction capacitor and allowed the measurement of interface state density (˜1013 cm-2 eV-1). Small-signal frequency performance of 75 and 115 GHz was obtained for ft and fmax, respectively.

Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

NASA Astrophysics Data System (ADS)

Chinnappan, U.; Sanudin, R.

2017-08-01

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.

Self-Aligned van der Waals Heterojunction Diodes and Transistors.

PubMed

Sangwan, Vinod K; Beck, Megan E; Henning, Alex; Luo, Jiajia; Bergeron, Hadallia; Kang, Junmo; Balla, Itamar; Inbar, Hadass; Lauhon, Lincoln J; Hersam, Mark C

2018-02-14

A general self-aligned fabrication scheme is reported here for a diverse class of electronic devices based on van der Waals materials and heterojunctions. In particular, self-alignment enables the fabrication of source-gated transistors in monolayer MoS 2 with near-ideal current saturation characteristics and channel lengths down to 135 nm. Furthermore, self-alignment of van der Waals p-n heterojunction diodes achieves complete electrostatic control of both the p-type and n-type constituent semiconductors in a dual-gated geometry, resulting in gate-tunable mean and variance of antiambipolar Gaussian characteristics. Through finite-element device simulations, the operating principles of source-gated transistors and dual-gated antiambipolar devices are elucidated, thus providing design rules for additional devices that employ self-aligned geometries. For example, the versatility of this scheme is demonstrated via contact-doped MoS 2 homojunction diodes and mixed-dimensional heterojunctions based on organic semiconductors. The scalability of this approach is also shown by fabricating self-aligned short-channel transistors with subdiffraction channel lengths in the range of 150-800 nm using photolithography on large-area MoS 2 films grown by chemical vapor deposition. Overall, this self-aligned fabrication method represents an important step toward the scalable integration of van der Waals heterojunction devices into more sophisticated circuits and systems.

Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach

NASA Astrophysics Data System (ADS)

Molaei Imen Abadi, Rouzbeh; Sedigh Ziabari, Seyed Ali

2016-11-01

In this paper, a first qualitative study on the performance characteristics of dual-work function gate junctionless TFET (DWG-JLTFET) on the basis of energy band profile modulation is investigated. A dual-work function gate technique is used in a JLTFET in order to create a downward band bending on the source side similar to PNPN structure. Compared with the single-work function gate junctionless TFET (SWG-JLTFET), the numerical simulation results demonstrated that the DWG-JLTFET simultaneously optimizes the ON-state current, the OFF-state leakage current, and the threshold voltage and also improves average subthreshold slope. It is illustrated that if appropriate work functions are selected for the gate materials on the source side and the drain side, the JLTFET exhibits a considerably improved performance. Furthermore, the optimization design of the tunnel gate length ( L Tun) for the proposed DWG-JLTFET is studied. All the simulations are done in Silvaco TCAD for a channel length of 20 nm using the nonlocal band-to-band tunneling (BTBT) model.

Impact of Lateral Straggle on the Analog/RF Performance of Asymmetric Gate Stack Double Gate MOSFET

NASA Astrophysics Data System (ADS)

Sivaram, Gollamudi Sai; Chakraborty, Shramana; Das, Rahul; Dasgupta, Arpan; Kundu, Atanu; Sarkar, Chandan K.

2016-09-01

This paper presents a systematic comparative study of Analog and RF performances of an underlapped double gate (U-DG) NMOSFET with Gate Stack (GS) for varying straggle lengths. Asymmetric underlap devices (A-U-DG) have been proposed as one of the remedies for reducing Short Channel Effects (SCE's) with the underlap being present towards the source for sub 20 nm devices. However, the Source to Drain (S/D) implant lateral diffusion leads to a variation in the effective underlap length. This paper investigates the impact of variation of straggle length on the Analog and RF parameters of the device. The RF performance is analyzed by considering the intrinsic capacitances (Cgd, Cgs), intrinsic resistances (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillations (fmax). The circuit performance of the devices are also studied. It is seen that the Analog and RF performances of the devices are improved by optimizing the S/D lateral straggle.

Simulation study of short-channel effects of tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Fukuda, Koichi; Asai, Hidehiro; Hattori, Junichi; Mori, Takahiro; Morita, Yukinori; Mizubayashi, Wataru; Masahara, Meishoku; Migita, Shinji; Ota, Hiroyuki; Endo, Kazuhiro; Matsukawa, Takashi

2018-04-01

Short-channel effects of tunnel field-effect transistors (FETs) are investigated in detail using simulations of a nonlocal band-to-band tunneling model. Discussion is limited to silicon. Several simulation scenarios were considered to address different effects, such as source overlap and drain offset effects. Adopting the drain offset to suppress the drain leakage current suppressed the short channel effects. The physical mechanism underlying the short-channel behavior of the tunnel FETs (TFETs) was very different from that of metal-oxide-semiconductor FETs (MOSFETs). The minimal gate lengths that do not lose on-state current by one order are shown to be 3 nm for single-gate structures and 2 nm for double gate structures, as determined from the drain offset structure.

Intermodulation distortion and linearity performance assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC design

NASA Astrophysics Data System (ADS)

Chaujar, Rishu; Kaur, Ravneet; Saxena, Manoj; Gupta, Mridula; Gupta, R. S.

2008-08-01

The distortion and linearity behaviour of MOSFETs is imperative for low-noise applications and RFICs design. In this paper, an extensive study on the RF-distortion and linearity behaviour of Laterally Amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET is performed and the influence of technology variations such as gate length, negative junction depth (NJD), substrate bias, drain bias and gate material workfunction is explored using ATLAS device simulator. Simulation results reveal that L-DUMGAC MOSFET significantly enhances the linearity and intermodulation distortion performance in terms of figure of merit (FOM) metrics: V, V, IIP3, IMD3 and higher order transconductance coefficients: gm1, gm2, gm3, proving its efficacy for RFIC design. The work, thus, optimize the device's bias point for RFICs with higher efficiency and better linearity performance.

Sub-10 nm Gate Length Graphene Transistors: Operating at Terahertz Frequencies with Current Saturation

PubMed Central

Zheng, Jiaxin; Wang, Lu; Quhe, Ruge; Liu, Qihang; Li, Hong; Yu, Dapeng; Mei, Wai-Ning; Shi, Junjie; Gao, Zhengxiang; Lu, Jing

2013-01-01

Radio-frequency application of graphene transistors is attracting much recent attention due to the high carrier mobility of graphene. The measured intrinsic cut-off frequency (fT) of graphene transistor generally increases with the reduced gate length (Lgate) till Lgate = 40 nm, and the maximum measured fT has reached 300 GHz. Using ab initio quantum transport simulation, we reveal for the first time that fT of a graphene transistor still increases with the reduced Lgate when Lgate scales down to a few nm and reaches astonishing a few tens of THz. We observe a clear drain current saturation when a band gap is opened in graphene, with the maximum intrinsic voltage gain increased by a factor of 20. Our simulation strongly suggests it is possible to design a graphene transistor with an extraordinary high fT and drain current saturation by continuously shortening Lgate and opening a band gap. PMID:23419782

High-frequency graphene voltage amplifier.

PubMed

Han, Shu-Jen; Jenkins, Keith A; Valdes Garcia, Alberto; Franklin, Aaron D; Bol, Ageeth A; Haensch, Wilfried

2011-09-14

While graphene transistors have proven capable of delivering gigahertz-range cutoff frequencies, applying the devices to RF circuits has been largely hindered by the lack of current saturation in the zero band gap graphene. Herein, the first high-frequency voltage amplifier is demonstrated using large-area chemical vapor deposition grown graphene. The graphene field-effect transistor (GFET) has a 6-finger gate design with gate length of 500 nm. The graphene common-source amplifier exhibits ∼5 dB low frequency gain with the 3 dB bandwidth greater than 6 GHz. This first AC voltage gain demonstration of a GFET is attributed to the clear current saturation in the device, which is enabled by an ultrathin gate dielectric (4 nm HfO(2)) of the embedded gate structures. The device also shows extrinsic transconductance of 1.2 mS/μm at 1 V drain bias, the highest for graphene FETs using large-scale graphene reported to date.

Influence of 2D electrostatic effects on the high-frequency noise behavior of sub-100-nm scaled MOSFETs

NASA Astrophysics Data System (ADS)

Rengel, Raul; Pardo, Daniel; Martin, Maria J.

2004-05-01

In this work, we have performed an investigation of the consequences of dowscaling the bulk MOSFET beyond the 100 nm range by means of a particle-based Monte Carlo simulator. Taking a 250 nm gate-length ideal structure as the starting point, the constant field scaling rules (also known as "classical" scaling) are considered and the high-frequency dynamic and noise performance of transistors with 130 nm, 90 nm and 60 nm gate-lengths are studied in depth. The analysis of internal quantities such as electric fields, velocity and energy of carriers or conduction band profiles shows the increasing importance of electrostatic two-dimensional effects due to the proximity of source and drain regions even when the most ideal bias conditions are imposed. As a consequence, a loss of the transistor action for the smallest MOSFET and the degradation of the most important high-frequency figures of merit is observed. Whereas the comparative values of intrinsic noise sources (SID, SIG) are improved when reducing the dimensions and the bias voltages, the poor dynamic performance yields an overall worse noise behaviour than expected (especially for Rn and Gass), limiting at the same time the useful bias ranges and conditions for a proper low-noise configuration.

AlGaN/GaN-HEMTs with a breakdown voltage higher than 100 V and maximum oscillation frequency f{sub max} as high as 100 GHz

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mokerov, V. G., E-mail: vgmokerov@yandex.ru; Kuznetsov, A. L.; Fedorov, Yu. V.

2009-04-15

The N-Al{sub 0.27}Ga{sub 0.73}N/GaN High Electron Mobility Transistors (HEMTs) with different gate lengths L{sub g} (ranging from 170 nm to 0.5 {mu}m) and gate widths W{sub s} (ranging from 100 to 1200 {mu}m) have been studied. The S parameters have been measured; these parameters have been used to determine the current-gain cutoff frequency f{sub t}, the maximum oscillation frequency f{sub max}, and the power gain MSG/MAG and Mason's coefficients were investigated in the frequency range from 10 MHz to 67 GHz in relation to the gate length and gate width. It was found that the frequencies f{sub t} and f{submore » max} attain their maximum values of f{sub t} = 48 GHz and f{sub max} = 100 GHz at L{sub g} = 170 nm and W{sub g} = 100 {mu}m. The optimum values of W{sub g} and output power P out of the basic transistors have been determined for different frequencies of operation. It has also been demonstrated that the 170 nm Al{sub 0.27}Ga{sub 0.73}N/GaN HEMT technology provides both good frequency characteristics and high breakdown voltages and is very promising for high-frequency applications (up to 40 GHz)« less

Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability

NASA Astrophysics Data System (ADS)

Navlakha, Nupur; Kranti, Abhinav

2017-11-01

The work reports on the use of a planar tri-gate tunnel field effect transistor (TFET) to operate as dynamic memory at 85 °C with an enhanced sense margin (SM). Two symmetric gates (G1) aligned to the source at a partial region of intrinsic film result into better electrostatic control that regulates the read mechanism based on band-to-band tunneling, while the other gate (G2), positioned adjacent to the first front gate is responsible for charge storage and sustenance. The proposed architecture results in an enhanced SM of ˜1.2 μA μm-1 along with a longer retention time (RT) of ˜1.8 s at 85 °C, for a total length of 600 nm. The double gate architecture towards the source increases the tunneling current and also reduces short channel effects, enhancing SM and scalability, thereby overcoming the critical bottleneck faced by TFET based dynamic memories. The work also discusses the impact of overlap/underlap and interface charges on the performance of TFET based dynamic memory. Insights into device operation demonstrate that the choice of appropriate architecture and biases not only limit the trade-off between SM and RT, but also result in improved scalability with drain voltage and total length being scaled down to 0.8 V and 115 nm, respectively.

The fundamental downscaling limit of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mamaluy, Denis, E-mail: mamaluy@sandia.gov; Gao, Xujiao

2015-05-11

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increasemore » in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.« less

The fundamental downscaling limit of field effect transistors

DOE PAGES

Mamaluy, Denis; Gao, Xujiao

2015-05-12

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increasemore » in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.« less

Analytical model of nanoscale junctionless transistors towards controlling of short channel effects through source/drain underlap and channel thickness engineering

NASA Astrophysics Data System (ADS)

Roy, Debapriya; Biswas, Abhijit

2018-01-01

We develop a 2D analytical subthreshold model for nanoscale double-gate junctionless transistors (DGJLTs) with gate-source/drain underlap. The model is validated using well-calibrated TCAD simulation deck obtained by comparing experimental data in the literature. To analyze and control short-channel effects, we calculate the threshold voltage, drain induced barrier lowering (DIBL) and subthreshold swing of DGJLTs using our model and compare them with corresponding simulation value at channel length of 20 nm with channel thickness tSi ranging 5-10 nm, gate-source/drain underlap (LSD) values 0-7 nm and source/drain doping concentrations (NSD) ranging 5-12 × 1018 cm-3. As tSi reduces from 10 to 5 nm DIBL drops down from 42.5 to 0.42 mV/V at NSD = 1019 cm-3 and LSD = 5 nm in contrast to decrement from 71 to 4.57 mV/V without underlap. For a lower tSiDIBL increases marginally with increasing NSD. The subthreshold swing reduces more rapidly with thinning of channel thickness rather than increasing LSD or decreasing NSD.

Experimental determination of the impact of polysilicon LER on sub-100-nm transistor performance

NASA Astrophysics Data System (ADS)

Patterson, Kyle; Sturtevant, John L.; Alvis, John R.; Benavides, Nancy; Bonser, Douglas; Cave, Nigel; Nelson-Thomas, Carla; Taylor, William D.; Turnquest, Karen L.

2001-08-01

Photoresist line edge roughness (LER) has long been feared as a potential limitation to the application of various patterning technologies to actual devices. While this concern seems reasonable, experimental verification has proved elusive and thus LER specifications are typically without solid parametric rationale. We report here the transistor device performance impact of deliberate variations of polysilicon gate LER. LER magnitude was attenuated by more than a factor of 5 by altering the photoresist type and thickness, substrate reflectivity, masking approach, and etch process. The polysilicon gate LER for nominally 70 - 150 nm devices was quantified using digital image processing of SEM images, and compared to gate leakage and drive current for variable length and width transistors. With such comparisons, realistic LER specifications can be made for a given transistor. It was found that subtle cosmetic LER differences are often not discernable electrically, thus providing hope that LER will not limit transistor performance as the industry migrates to sub-100 nm patterning.

Thermally stable In0.7Ga0.3As/In0.52Al0.48As pHEMTs using thermally evaporated palladium gate metallization

NASA Astrophysics Data System (ADS)

Ian, Ka Wa; Zawawiand, Mohamad Adzhar Md; Missous, Mohamed

2014-03-01

This work described the fabrication and performances of strained channel In0.52Al0.47As/In0.7Ga0.3As/InP pHEMTs with thermally evaporated Pd/Ti/Au gate metallization. The electrical characteristics of these Pd-gate devices are studied to investigate the effects of changing the Pd metal thickness, annealing temperature and annealing time. Following annealing at 200 °C for 35 min, a 10 nm Pd-gate device displays a VTH of -0.25 V, which is significantly smaller compared to those with Ti/Au gate schemes showing VTH = -0.75 V. A 1 um gate length device exhibits an improved Gm of 580 mS mm-1 (from 500 mS mm-1), a high IDSmax of 400 mA mm-1 (from 330 mA mm-1) and good fT and fmax of 24.5 and 49 GHz commensurate with the 1 µm gate length. All these enhancements are attributed to the controllable gate sinking of Pd. The device shows no significant degradation even after annealing at 230 °C for more than 5 h, which implies that the reliability of these Pd-gate structures is excellent.

Study of fully-depleted Ge double-gate n-type Tunneling Field-Effect Transistors for improvement in on-state current and sub-threshold swing

NASA Astrophysics Data System (ADS)

Liu, Xiangyu; Hu, Huiyong; Wang, Meng; Zhang, Heming; Cui, Shimin; Shu, Bin; Wang, Bin

2018-01-01

In this paper, a fully-depleted (FD) Ge double-gate (DG) n-type Tunneling Field-Effect Transistors (TFET) structure is studied in detail by two-dimensional numerical simulation. The simulation results indicated that the on-state current Ion and on-off ratio of the FD Ge DG-TFET increases about 1 order of magnitude comparing with the Conventional Ge DG-TFET, and Ion=3.95×10-5 A/μm and the below 60 mV/decade subthreshold swing S=26.4 mV/decade are achieved with the length of gate LD=20 nm, the workfuntion of metal gate Φm=0.2 eV and the doping concentration of n+-type-channel ND=1×1018 cm-3. Moreover, the impacts of Φm, ND and LD are investigated. The simulation results indicated that the off-state current Ioff includes the tunneling current at the middle of channel IB the gated-induced drain leakage (GIDL) current IGIDL. With optimized Φm and ND, Ioff is reduced about 2 orders of magnitude to 2.5×10-13 A/μm with LD increasing from 40 nm to 100 nm, and on-off ratio is increased to 1.58×107.

Submillimeter-Wave Amplifier Module with Integrated Waveguide Transitions

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Chattopadhyay, Goutam; Pukala, David; Gaier, Todd; Soria, Mary; ManFung, King; Deal, William; Mei, Gerry; Radisic, Vesna; Lai, Richard

2009-01-01

To increase the usefulness of monolithic millimeter-wave integrated circuit (MMIC) components at submillimeter-wave frequencies, a chip has been designed that incorporates two integrated, radial E-plane probes with an MMIC amplifier in between, thus creating a fully integrated waveguide module. The integrated amplifier chip has been fabricated in 35-nm gate length InP high-electron-mobility-transistor (HEMT) technology. The radial probes were mated to grounded coplanar waveguide input and output lines in the internal amplifier. The total length of the internal HEMT amplifier is 550 m, while the total integrated chip length is 1,085 m. The chip thickness is 50 m with the chip width being 320 m. The internal MMIC amplifier is biased through wire-bond connections to the gates and drains of the chip. The chip has 3 stages, employing 35-nm gate length transistors in each stage. Wire bonds from the DC drain and gate pads are connected to off-chip shunt 51-pF capacitors, and additional off-chip capacitors and resistors are added to the gate and drain bias lines for low-frequency stability of the amplifier. Additionally, bond wires to the grounded coplanar waveguide pads at the RF input and output of the internal amplifier are added to ensure good ground connections to the waveguide package. The S-parameters of the module, not corrected for input or output waveguide loss, are measured at the waveguide flange edges. The amplifier module has over 10 dB of gain from 290 to 330 GHz, with a peak gain of over 14 dB at 307 GHz. The WR2.2 waveguide cutoff is again observed at 268 GHz. The module is biased at a drain current of 27 mA, a drain voltage of 1.24 V, and a gate voltage of +0.21 V. Return loss of the module is very good between 5 to 25 dB. This result illustrates the usefulness of the integrated radial probe transition, and the wide (over 10-percent) bandwidth that one can expect for amplifier modules with integrated radial probes in the submillimeter-regime (>300 GHz).

Design and analysis of 30 nm T-gate InAlN/GaN HEMT with AlGaN back-barrier for high power microwave applications

NASA Astrophysics Data System (ADS)

Murugapandiyan, P.; Ravimaran, S.; William, J.; Meenakshi Sundaram, K.

2017-11-01

In this article, we present the DC and microwave characteristics of a novel 30 nm T-gate InAlN/AlN/GaN HEMT with AlGaN back-barrier. The device structure is simulated by using Synopsys Sentaurus TCAD Drift-Diffusion transport model at room temperature. The device features are heavily doped (n++ GaN) source/drain regions with Si3N4 passivated device surface for reducing the contact resistances and gate capacitances of the device, which uplift the microwave characteristics of the HEMTs. 30 nm gate length D-mode (E-mode) HEMT exhibited a peak drain current density Idmax of 2.3 (2.42) A/mm, transconductance gm of 1.24(1.65) S/mm, current gain cut-off frequency ft of 262 (246) GHz, power gain cut-off frequency fmax of 246(290) GHz and the three terminal off-state breakdown voltage VBR of 40(38) V. The preeminent microwave characteristics with the higher breakdown voltage of the proposed GaN-based HEMT are the expected to be the most optimistic applicant for future high power millimeter wave applications.

Analysis and optimization of RC delay in vertical nanoplate FET

NASA Astrophysics Data System (ADS)

Woo, Changbeom; Ko, Kyul; Kim, Jongsu; Kim, Minsoo; Kang, Myounggon; Shin, Hyungcheol

2017-10-01

In this paper, we have analyzed short channel effects (SCEs) and RC delay with Vertical nanoplate FET (VNFET) using 3-D Technology computer-aided design (TCAD) simulation. The device is based on International Technology Road-map for Semiconductor (ITRS) 2013 recommendations, and it has initially gate length (LG) of 12.2 nm, channel thickness (Tch) of 4 nm, and spacer length (LSD) of 6 nm. To obtain improved performance by reducing RC delay, each dimension is adjusted (LG = 12.2 nm, Tch = 6 nm, LSD = 11.9 nm). It has each characteristic in this dimension (Ion/Ioff = 1.64 × 105, Subthreshold swing (S.S.) = 73 mV/dec, Drain-induced barrier lowering (DIBL) = 60 mV/V, and RC delay = 0.214 ps). Furthermore, with long shallow trench isolation (STI) length and thick insulator thickness (Ti), we can reduce RC delay from 0.214 ps to 0.163 ps. It is about a 23.8% reduction. Without decreasing drain current, there is a reduction of RC delay as reducing outer fringing capacitance (Cof). Finally, when source/drain spacer length is set to be different, we have verified RC delay to be optimum.

Highly efficient X-range AlGaN/GaN power amplifier

NASA Astrophysics Data System (ADS)

Tural'chuk, P. A.; Kirillov, V. V.; Osipov, P. E.; Vendik, I. B.; Vendik, O. G.; Parnes, M. D.

2017-09-01

The development of microwave power amplifiers (PAs) based on transistors with an AlGaN/GaN heterojunction are discussed in terms of the possible enhancement of their efficiency. The main focus is on the synthesis of the transforming circuits, which ensure the reactive load at the second- and third-harmonic frequencies and complex impedance at the fundamental frequency. This makes it possible to optimize the complex operation mode of a PA; i.e., to reduce the scattering power and enhance the efficiency. A microwave PA based on the Schottky-barrier-gate field-effect transistor with 80 electrodes based on the GaN pHEMT transistor with a gate length of 0.25 nm and a gate width of 125 nm is experimentally investigated. The amplifier has a pulse output power of 35 W and a power-added efficiency of at least 50% at a working frequency of 9 GHz.

Scaling behavior of fully spin-coated TFT

NASA Astrophysics Data System (ADS)

Mondal, Sandip; Kumar, Arvind; Rao, K. S. R. Koteswara; Venkataraman, V.

2017-05-01

We studied channel scaling behavior of fully spin coated, low temperature solution processed thin film transistor (TFT) fabricated on p++ - Si (˜1021 cm-3) as bottom gate. The solution processed, spin coated 40 nm thick amorphous Indium Gallium Zinc Oxide (a-IGZO) and 50 nm thick amorphous zirconium di-oxide (a-ZrO2) has been used as channel and low leakage dielectric at 350°C respectively. The channel scaling effect of the TFT with different width/length ratio (W/L= 2.5, 5 and 15) for same channel length (L = 10 μm) has been demonstrated. The lowest threshold voltage (Vth) is 6.25 V for the W/L=50/10. The maximum field effect mobility (μFE) has been found to be 0.123 cm2/Vs from W/L of 50/10 with the drain to source voltage (VD) of 10V and 20V gate to source voltage (VG). We also demonstrated that there is no contact resistance effect on the mobility of the fully sol-gel spin coated TFT.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mamaluy, Denis; Gao, Xujiao; Tierney, Brian David

We created a highly efficient, universal 3D quant um transport simulator. We demonstrated that the simulator scales linearly - both with the problem size (N) and number of CPUs, which presents an important break-through in the field of computational nanoelectronics. It allowed us, for the first time, to accurately simulate and optim ize a large number of realistic nanodevices in a much shorter time, when compared to other methods/codes such as RGF[%7EN 2.333 ]/KNIT, KWANT, and QTBM[%7EN 3 ]/NEMO5. In order to determine the best-in-class for different beyond-CMOS paradigms, we performed rigorous device optimization for high-performance logic devices at 6-,more » 5- and 4-nm gate lengths. We have discovered that there exists a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs). We have found that, at room temperatures, all FETs, irre spective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths.« less

Dual-Gated Active Metasurface at 1550 nm with Wide (>300°) Phase Tunability.

PubMed

Kafaie Shirmanesh, Ghazaleh; Sokhoyan, Ruzan; Pala, Ragip A; Atwater, Harry A

2018-05-09

Active metasurfaces composed of electrically reconfigurable nanoscale subwavelength antenna arrays can enable real-time control of scattered light amplitude and phase. Achievement of widely tunable phase and amplitude in chip-based active metasurfaces operating at or near 1550 nm wavelength has considerable potential for active beam steering, dynamic hologram rendition, and realization of flat optics with reconfigurable focal lengths. Previously, electrically tunable conducting oxide-based reflectarray metasurfaces have demonstrated dynamic phase control of reflected light with a maximum phase shift of 184° ( Nano Lett. 2016 , 16 , 5319 ). Here, we introduce a dual-gated reflectarray metasurface architecture that enables much wider (>300°) phase tunability. We explore light-matter interactions with dual-gated metasurface elements that incorporate two independent voltage-controlled MOS field effect channels connected in series to form a single metasurface element that enables wider phase tunability. Using indium tin oxide (ITO) as the active metasurface material and a composite hafnia/alumina gate dielectric, we demonstrate a prototype dual-gated metasurface with a continuous phase shift from 0 to 303° and a relative reflectance modulation of 89% under applied voltage bias of 6.5 V.

Meeting critical gate linewidth control needs at the 65 nm node

NASA Astrophysics Data System (ADS)

Mahorowala, Arpan; Halle, Scott; Gabor, Allen; Chu, William; Barberet, Alexandra; Samuels, Donald; Abdo, Amr; Tsou, Len; Yan, Wendy; Iseda, Seiji; Patel, Kaushal; Dirahoui, Bachir; Nomura, Asuka; Ahsan, Ishtiaq; Azam, Faisal; Berg, Gary; Brendler, Andrew; Zimmerman, Jeffrey; Faure, Tom

2006-03-01

With the nominal gate length at the 65 nm node being only 35 nm, controlling the critical dimension (CD) in polysilicon to within a few nanometers is essential to achieve a competitive power-to-performance ratio. Gate linewidths must be controlled, not only at the chip level so that the chip performs as the circuit designers and device engineers had intended, but also at the wafer level so that more chips with the optimum power-to-performance ratio are manufactured. Achieving tight across-chip linewidth variation (ACLV) and chip mean variation (CMV) is possible only if the mask-making, lithography, and etching processes are all controlled to very tight specifications. This paper identifies the various ACLV and CMV components, describes their root causes, and discusses a methodology to quantify them. For example, the site-to-site ACLV component is divided into systematic and random sub-components. The systematic component of the variation is attributed in part to pattern density variation across the field, and variation in exposure dose across the slit. The paper demonstrates our team's success in achieving the tight gate CD tolerances required for 65 nm technology. Certain key challenges faced, and methods employed to overcome them are described. For instance, the use of dose-compensation strategies to correct the small but systematic CD variations measured across the wafer, is described. Finally, the impact of immersion lithography on both ACLV and CMV is briefly discussed.

Examining kinesin processivity within a general gating framework

PubMed Central

Andreasson, Johan OL; Milic, Bojan; Chen, Geng-Yuan; Guydosh, Nicholas R; Hancock, William O; Block, Steven M

2015-01-01

Kinesin-1 is a dimeric motor that transports cargo along microtubules, taking 8.2-nm steps in a hand-over-hand fashion. The ATP hydrolysis cycles of its two heads are maintained out of phase by a series of gating mechanisms, which lead to processive runs averaging ∼1 μm. A key structural element for inter-head coordination is the neck linker (NL), which connects the heads to the stalk. To examine the role of the NL in regulating stepping, we investigated NL mutants of various lengths using single-molecule optical trapping and bulk fluorescence approaches in the context of a general framework for gating. Our results show that, although inter-head tension enhances motor velocity, it is crucial neither for inter-head coordination nor for rapid rear-head release. Furthermore, cysteine-light mutants do not produce wild-type motility under load. We conclude that kinesin-1 is primarily front-head gated, and that NL length is tuned to enhance unidirectional processivity and velocity. DOI: http://dx.doi.org/10.7554/eLife.07403.001 PMID:25902401

2D Quantum Transport Modeling in Nanoscale MOSFETs

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, Bryan

2001-01-01

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density- gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions, oxide tunneling and phase-breaking scattering are treated on equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. Quantum simulations are focused on MIT 25, 50 and 90 nm "well- tempered" MOSFETs and compared to classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. These results are quantitatively consistent with I D Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and sub-threshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit

NASA Astrophysics Data System (ADS)

Al-Ameri, Talib; Georgiev, Vihar P.; Sadi, Toufik; Wang, Yijiao; Adamu-Lema, Fikru; Wang, Xingsheng; Amoroso, Salvatore M.; Towie, Ewan; Brown, Andrew; Asenov, Asen

2017-03-01

In this work we investigate the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future CMOS applications at the scaling limit. For the purpose of this paper, we created Si NWTs with two channel crystallographic orientations <1 1 0> and <1 0 0> and six different cross-section profiles. In the first part, we study the impact of quantum corrections on the gate capacitance and mobile charge in the channel. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic performance of the NWTs, is also investigated. The influence of the rotating of the NWTs cross-sectional geometry by 90° on charge distribution in the channel is also studied. We compare the correlation between the charge profile in the channel and cross-sectional dimension for circular transistor with four different cross-sections diameters: 5 nm, 6 nm, 7 nm and 8 nm. In the second part of this paper, we expand the computational study by including different gate lengths for some of the Si NWTs. As a result, we establish a correlation between the mobile charge distribution in the channel and the gate capacitance, drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All calculations are based on a quantum mechanical description of the mobile charge distribution in the channel. This description is based on the solution of the Schrödinger equation in NWT cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions.

Design Optimization of Ge/GaAs-Based Heterojunction Gate-All-Around (GAA) Arch-Shaped Tunneling Field-Effect Transistor (A-TFET).

PubMed

Seo, Jae Hwa; Yoon, Young Jun; Kang, In Man

2018-09-01

The Ge/GaAs-based heterojunction gate-all-around (GAA) arch-shaped tunneling field-effect transistor (A-TFET) have been designed and optimized using technology computer-aided design (TCAD) simulations. In our previous work, the silicon-based A-TFET was designed and demonstrated. However, to progress the electrical characteristics of A-TFET, the III-V compound heterojunction structures which has enhanced electrical properties must be adopted. Thus, the germanium with gallium arsenide (Ge/GaAs) is considered as key materials of A-TFET. The proposed device has a Ge-based p-doped source, GaAs-based i-doped channel and GaAs-based n-doped drain. Due to the critical issues of device performances, the doping concentration of source and channel region (Dsource, Dchannel), height of source region (Hsource) and epitaxially grown thickness of channel (tepi) was selected as design optimization variables of Ge/GaAs-based GAA A-TFET. The DC characteristics such as on-state current (ion), off-state current (ioff), subthreshold-swing (S) were of extracted and analyzed. Finally, the proposed device has a gate length (LG) of 90 nm, Dsource 5 × 1019 cm-3, Dchannel of 1018 cm-3, tepi of 4 nm, Hsource of 90 nm, R of 10 nm and demonstrate an ion of 2 mA/μm, S of 12.9 mV/dec.

Control of short-channel effects in InAlN/GaN high-electron mobility transistors using graded AlGaN buffer

NASA Astrophysics Data System (ADS)

Han, Tiecheng; Zhao, Hongdong; Peng, Xiaocan; Li, Yuhai

2018-04-01

A graded AlGaN buffer is designed to realize the p-type buffer by inducing polarization-doping holes. Based on the two-dimensional device simulator, the effect of the graded AlGaN buffer on the direct-current (DC) and radio-frequency (RF) performance of short-gate InAlN/GaN high-electron mobility transistors (HEMTs) are investigated, theoretically. Compared to standard HEMT, an enhancement of electron confinement and a good control of short-channel effect (SCEs) are demonstrated in the graded AlGaN buffer HEMT. Accordingly, the pinched-off behavior and the ability of gate modulation are significantly improved. And, no serious SCEs are observed in the graded AlGaN buffer HEMT with an aspect ratio (LG/tch) of about 6.7, much lower than that of the standard HEMT (LG/tch = 13). In addition, for a 70-nm gate length, a peak current gain cutoff frequency (fT) of 171 GHz and power gain cutoff frequency (fmax) of 191 GHz are obtained in the grade buffer HEMT, which are higher than those of the standard one with the same gate length.

2D Quantum Mechanical Study of Nanoscale MOSFETs

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, B.; Kwak, Dochan (Technical Monitor)

2000-01-01

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density-gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions and oxide tunneling are treated on an equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. We present the results of our simulations of MIT 25, 50 and 90 nm "well-tempered" MOSFETs and compare them to those of classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. Surprisingly, the self-consistent potential profile shows lower injection barrier in the channel in quantum case. These results are qualitatively consistent with ID Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and subthreshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

1/F Noise in Indium Phosphide Transistors

DTIC Science & Technology

1992-04-01

Zn/5 nm Au. The gate length and width were 1 Pm and 400 gm, respectively. The device was annealed at 375"C in argon for 1 minute to simultaneously...evaporation, defined by lift-off, and annealed at 375°C for 10 minutes. The gate region was recessed until a source-drain current of 35 mA was obtained...considerations for the signal Sn V,2/R, at the network input from the amplifier output show that vo2 4RoR,, s - 4 nR 2 = So •Mo. (6) 4Ro (Ro + R,) 2

Breaking Through the Multi-Mesa-Channel Width Limited of Normally Off GaN HEMTs Through Modulation of the Via-Hole-Length.

PubMed

Chien, Cheng-Yen; Wu, Wen-Hsin; You, Yao-Hong; Lin, Jun-Huei; Lee, Chia-Yu; Hsu, Wen-Ching; Kuan, Chieh-Hsiung; Lin, Ray-Ming

2017-12-01

We present new normally off GaN high-electron-mobility transistors (HEMTs) that overcome the typical limitations in multi-mesa-channel (MMC) width through modulation of the via-hole-length to regulate the charge neutrality screen effect. We have prepared enhancement-mode (E-mode) GaN HEMTs having widths of up to 300 nm, based on an enhanced surface pinning effect. E-mode GaN HEMTs having MMC structures and widths as well as via-hole-lengths of 100 nm/2 μm and 300 nm/6 μm, respectively, exhibited positive threshold voltages (V th ) of 0.79 and 0.46 V, respectively. The on-resistances of the MMC and via-hole-length structures were lower than those of typical tri-gate nanoribbon GaN HEMTs. In addition, the devices not only achieved the E-mode but also improved the power performance of the GaN HEMTs and effectively mitigated the device thermal effect. We controlled the via-hole-length sidewall surface pinning effect to obtain the E-mode GaN HEMTs. Our findings suggest that via-hole-length normally off GaN HEMTs have great potential for use in next-generation power electronics.

Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2

NASA Astrophysics Data System (ADS)

Martin, Dominik; Yurchuk, Ekaterina; Müller, Stefan; Müller, Johannes; Paul, Jan; Sundquist, Jonas; Slesazeck, Stefan; Schlösser, Till; van Bentum, Ralf; Trentzsch, Martin; Schröder, Uwe; Mikolajick, Thomas

2013-10-01

Throughout the 22 nm technology node HfO2 is established as a reliable gate dielectric in contemporary complementary metal oxide semiconductor (CMOS) technology. The working principle of ferroelectric field effect transistors FeFET has also been demonstrated for some time for dielectric materials like Pb[ZrxTi1-x]O3 and SrBi2Ta2O9. However, integrating these into contemporary downscaled CMOS technology nodes is not trivial due to the necessity of an extremely thick gate stack. Recent developments have shown HfO2 to have ferroelectric properties, given the proper doping. Moreover, these doped HfO2 thin films only require layer thicknesses similar to the ones already in use in CMOS technology. This work will show how the incorporation of Si induces ferroelectricity in HfO2 based capacitor structures and finally demonstrate non-volatile storage in nFeFETs down to a gate length of 100 nm. A memory window of 0.41 V can be retained after 20,000 switching cycles. Retention can be extrapolated to 10 years.

30 nm T-gate enhancement-mode InAlN/AlN/GaN HEMT on SiC substrates for future high power RF applications

NASA Astrophysics Data System (ADS)

Murugapandiyan, P.; Ravimaran, S.; William, J.

2017-08-01

The DC and RF performance of 30 nm gate length enhancement mode (E-mode) InAlN/AlN/GaN high electron mobility transistor (HEMT) on SiC substrate with heavily doped source and drain region have been investigated using the Synopsys TCAD tool. The proposed device has the features of a recessed T-gate structure, InGaN back barrier and Al2O3 passivated device surface. The proposed HEMT exhibits a maximum drain current density of 2.1 A/mm, transconductance {g}{{m}} of 1050 mS/mm, current gain cut-off frequency {f}{{t}} of 350 GHz and power gain cut-off frequency {f}\\max of 340 GHz. At room temperature the measured carrier mobility (μ), sheet charge carrier density ({n}{{s}}) and breakdown voltage are 1580 cm2/(V \\cdot s), 1.9× {10}13 {{cm}}-2, and 10.7 V respectively. The superlatives of the proposed HEMTs are bewitching competitor or future sub-millimeter wave high power RF VLSI circuit applications.

Single-fabrication-step Ge nanosphere/SiO2/SiGe heterostructures: a key enabler for realizing Ge MOS devices

NASA Astrophysics Data System (ADS)

Liao, P. H.; Peng, K. P.; Lin, H. C.; George, T.; Li, P. W.

2018-05-01

We report channel and strain engineering of self-organized, gate-stacking heterostructures comprising Ge-nanosphere gate/SiO2/SiGe-channels. An exquisitely-controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials was effectively exploited to simultaneously create these heterostructures in a single oxidation step. Process-controlled tunability of the channel length (5–95 nm diameters for the Ge-nanospheres), gate oxide thickness (2.5–4.8 nm), as well as crystal orientation, chemical composition and strain engineering of the SiGe-channel was achieved. Single-crystalline (100) Si1‑x Ge x shells with Ge content as high as x = 0.85 and with a compressive strain of 3%, as well as (110) Si1‑x Ge x shells with Ge content of x = 0.35 and corresponding compressive strain of 1.5% were achieved. For each crystal orientation, our high Ge-content, highly-stressed SiGe shells feature a high degree of crystallinity and thus, provide a core ‘building block’ required for the fabrication of Ge-based MOS devices.

Strain and deformations engineered germanene bilayer double gate-field effect transistor by first principles

NASA Astrophysics Data System (ADS)

Meher Abhinav, E.; Chandrasekaran, Gopalakrishnan; Kasmir Raja, S. V.

2017-10-01

Germanene, silicene, stanene, phosphorene and graphene are some of single atomic materials with novel properties. In this paper, we explored bilayer germanene-based Double Gate-Field Effect Transistor (DG-FET) with various strains and deformations using Density Functional Theory (DFT) and Green's approach by first-principle calculations. The DG-FET of 1.6 nm width, 6 nm channel length (Lch) and HfO2 as gate dielectric has been modeled. For intrinsic deformation of germanene bilayer, we have enforced minute mechanical deformation of wrap and twist (5°) and ripple (0.5 Å) on germanene bilayer channel material. By using NEGF formalism, I-V Characteristics of various strains and deformation tailored DG-FET was calculated. Our results show that rough edge and single vacancy (5-9) in bilayer germanene diminishes the current around 47% and 58% respectively as compared with pristine bilayer germanene. In case of strain tailored bilayer DG-FET, multiple NDR regions were observed which can be utilized in building stable multiple logic states in digital circuits and high frequency oscillators using negative resistive techniques.

Single-fabrication-step Ge nanosphere/SiO2/SiGe heterostructures: a key enabler for realizing Ge MOS devices.

PubMed

Liao, P H; Peng, K P; Lin, H C; George, T; Li, P W

2018-05-18

We report channel and strain engineering of self-organized, gate-stacking heterostructures comprising Ge-nanosphere gate/SiO 2 /SiGe-channels. An exquisitely-controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials was effectively exploited to simultaneously create these heterostructures in a single oxidation step. Process-controlled tunability of the channel length (5-95 nm diameters for the Ge-nanospheres), gate oxide thickness (2.5-4.8 nm), as well as crystal orientation, chemical composition and strain engineering of the SiGe-channel was achieved. Single-crystalline (100) Si 1-x Ge x shells with Ge content as high as x = 0.85 and with a compressive strain of 3%, as well as (110) Si 1-x Ge x shells with Ge content of x = 0.35 and corresponding compressive strain of 1.5% were achieved. For each crystal orientation, our high Ge-content, highly-stressed SiGe shells feature a high degree of crystallinity and thus, provide a core 'building block' required for the fabrication of Ge-based MOS devices.

2-D Modeling of Nanoscale MOSFETs: Non-Equilibrium Green's Function Approach

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, Bryan

2001-01-01

We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions and oxide tunneling are treated on an equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. Electron-electron interaction is treated within Hartree approximation by solving NEGF and Poisson equations self-consistently. For the calculations presented here, parallelization is performed by distributing the solution of NEGF equations to various processors, energy wise. We present simulation of the "benchmark" MIT 25nm and 90nm MOSFETs and compare our results to those from the drift-diffusion simulator and the quantum-corrected results available. In the 25nm MOSFET, the channel length is less than ten times the electron wavelength, and the electron scattering time is comparable to its transit time. Our main results are: (1) Simulated drain subthreshold current characteristics are shown, where the potential profiles are calculated self-consistently by the corresponding simulation methods. The current predicted by our quantum simulation has smaller subthreshold slope of the Vg dependence which results in higher threshold voltage. (2) When gate oxide thickness is less than 2 nm, gate oxide leakage is a primary factor which determines off-current of a MOSFET (3) Using our 2-D NEGF simulator, we found several ways to drastically decrease oxide leakage current without compromising drive current. (4) Quantum mechanically calculated electron density is much smaller than the background doping density in the poly silicon gate region near oxide interface. This creates an additional effective gate voltage. Different ways to. include this effect approximately will be discussed.

An analytic current-voltage model for quasi-ballistic III-nitride high electron mobility transistors

NASA Astrophysics Data System (ADS)

Li, Kexin; Rakheja, Shaloo

2018-05-01

We present an analytic model to describe the DC current-voltage (I-V) relationship in scaled III-nitride high electron mobility transistors (HEMTs) in which transport within the channel is quasi-ballistic in nature. Following Landauer's transport theory and charge calculation based on two-dimensional electrostatics that incorporates negative momenta states from the drain terminal, an analytic expression for current as a function of terminal voltages is developed. The model interprets the non-linearity of access regions in non-self-aligned HEMTs. Effects of Joule heating with temperature-dependent thermal conductivity are incorporated in the model in a self-consistent manner. With a total of 26 input parameters, the analytic model offers reduced empiricism compared to existing GaN HEMT models. To verify the model, experimental I-V data of InAlN/GaN with InGaN back-barrier HEMTs with channel lengths of 42 and 105 nm are considered. Additionally, the model is validated against numerical I-V data obtained from DC hydrodynamic simulations of an unintentionally doped AlGaN-on-GaN HEMT with 50-nm gate length. The model is also verified against pulsed I-V measurements of a 150-nm T-gate GaN HEMT. Excellent agreement between the model and experimental and numerical results for output current, transconductance, and output conductance is demonstrated over a broad range of bias and temperature conditions.

Nanoscience and Nanotechnology

DTIC Science & Technology

1992-05-05

Stanford has fabricated gate lengths down to 65 nm, and are entering into consortia to fabricate modulation doped field effect transistors (MODFETs...and from the substrate exposes the resist over a greater area than the beam xpot size. Correcting for these effects (where possible) is computationally...the lithographic pattern (proximity effects ). The push to smaller dimensions is concentrated on controlling and understanding these phenomena rather

A novel low temperature soft reflow process for the fabrication of deep-submicron (<0.35 μm) T-gate pseudomorphic high electron mobility transistor structures

NASA Astrophysics Data System (ADS)

Ian, Ka Wa; Exarchos, Michael; Missous, Mohamed

2013-02-01

We report a new and simple low temperature soft reflow process using solvent vapour. The combination of this soft reflow and conventional i-line lithography enables low cost, highly efficient fabrication at the deep-submicron scale. Compared to the conventional thermal reflow process, the key benefits of the new soft reflow process are its low temperature operation (<50 °C), greater shrinkage of the structure size (up to 75%) and better controllability. Gate openings reflowed from 1 μm to 250 nm have been routinely and reproducibly achieved by utilizing the saturation characteristics of the process. The feasibility of this soft reflow process is demonstrated in the fabrication of a 350 nm T-gate pseudomorphic high electron mobility transistor. By shrinking the gate length by a factor of three (from a 1 μm initial opening), the output current is improved by 60% (500 mA mm-1 from 300 mA mm-1) and fT and fMAX are increased to 70 GHz (from 20 GHz) and 120 GHz (from 40 GHz) respectively. The proposed soft reflow could potentially be applied on other compatible substrates such as polymer based material for organic or thin film devices, potentially leading to many new possible applications.

Non-Volatile High Speed & Low Power Charge Trapping Devices

NASA Astrophysics Data System (ADS)

Kim, Moon Kyung; Tiwari, Sandip

2007-06-01

We report the operational characteristics of ultra-small-scaled SONOS (below 50 nm gate width and length) and SiO2/SiO2 structural devices with 0.5 um gate width and length where trapping occurs in a very narrow region. The experimental work summarizes the memory characteristics of retention time, endurance cycles, and speed in SONOS and SiO2/SiO2 structures. Silicon nitride has many defects to hold electrons as charge storage media in SONOS memory. Defects are also incorporated during growth and deposition in device processing. Our experiments show that the interface between two oxides, one grown and one deposited, provides a remarkable media for electron storage with a smaller gate stack and thus lower operating voltage. The exponential dependence of the time on the voltage is reflected in the characteristic energy. It is ˜0.44 eV for the write process and ˜0.47 eV for the erase process in SiO2/SiO2 structural device which is somewhat more efficient than those of SONOS structure memory.

Improved scatterer property estimates from ultrasound backscatter for small gate lengths using a gate-edge correction factor

NASA Astrophysics Data System (ADS)

Oelze, Michael L.; O'Brien, William D.

2004-11-01

Backscattered rf signals used to construct conventional ultrasound B-mode images contain frequency-dependent information that can be examined through the backscattered power spectrum. The backscattered power spectrum is found by taking the magnitude squared of the Fourier transform of a gated time segment corresponding to a region in the scattering volume. When a time segment is gated, the edges of the gated regions change the frequency content of the backscattered power spectrum due to truncating of the waveform. Tapered windows, like the Hanning window, and longer gate lengths reduce the relative contribution of the gate-edge effects. A new gate-edge correction factor was developed that partially accounted for the edge effects. The gate-edge correction factor gave more accurate estimates of scatterer properties at small gate lengths compared to conventional windowing functions. The gate-edge correction factor gave estimates of scatterer properties within 5% of actual values at very small gate lengths (less than 5 spatial pulse lengths) in both simulations and from measurements on glass-bead phantoms. While the gate-edge correction factor gave higher accuracy of estimates at smaller gate lengths, the precision of estimates was not improved at small gate lengths over conventional windowing functions. .

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Mizubayashi, Wataru; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Masahara, Meishoku

2014-01-01

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (Vt) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal-oxide-nitride-oxide-silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial Vt roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (Lg) is scaled down to 46 nm or less.

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

Influence of gate recess on the electronic characteristics of β-Ga2O3 MOSFETs

NASA Astrophysics Data System (ADS)

Lv, Yuanjie; Mo, Jianghui; Song, Xubo; He, Zezhao; Wang, Yuangang; Tan, Xin; Zhou, Xingye; Gu, Guodong; Guo, Hongyu; Feng, Zhihong

2018-05-01

Gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 110 nm and 220 nm, respectively. The gate recess was formed by dry plasma etching with Cr metal as the mask. The fabricated devices with a 25-nm HfO2 gate dielectric both showed a low off-state drain current of about 1.8 × 10-10 A/mm. The effects of recess depth on the electronic characteristics of Ga2O3 MOSFETs were investigated. Upon increasing the recess depth from 110 nm to 220 nm, the saturated drain current decreased from 20.7 mA/mm to 2.6 mA/mm, while the threshold voltage moved increased to +3 V. Moreover, the breakdown voltage increased from 122 V to 190 V. This is mainly because the inverted-trapezoidal gate played the role of a gate-field plate, which suppressed the peak electric field close to the gate.

Atomic layer deposition of sub-10 nm high-K gate dielectrics on top-gated MoS2 transistors without surface functionalization

NASA Astrophysics Data System (ADS)

Lin, Yu-Shu; Cheng, Po-Hsien; Huang, Kuei-Wen; Lin, Hsin-Chih; Chen, Miin-Jang

2018-06-01

Sub-10 nm high-K gate dielectrics are of critical importance in two-dimensional transition metal dichalcogenides (TMDs) transistors. However, the chemical inertness of TMDs gives rise to a lot of pinholes in gate dielectrics, resulting in large gate leakage current. In this study, sub-10 nm, uniform and pinhole-free Al2O3 high-K gate dielectrics on MoS2 were achieved by atomic layer deposition without surface functionalization, in which an ultrathin Al2O3 layer prepared with a short purge time at a low temperature of 80 °C offers the nucleation cites for the deposition of the overlaying oxide at a higher temperature. Conductive atomic force microscopy reveals the significant suppression of gate leakage current in the sub-10 nm Al2O3 gate dielectrics with the low-temperature nucleation layer. Raman and X-ray photoelectron spectroscopies indicate that no oxidation occurred during the deposition of the low-temperature Al2O3 nucleation layer on MoS2. With the high-quality sub-10 nm Al2O3 high-K gate dielectrics, low hysteresis and subthreshold swing were demonstrated on the normally-off top-gated MoS2 transistors.

High performance multi-finger MOSFET on SOI for RF amplifiers

NASA Astrophysics Data System (ADS)

Adhikari, M. Singh; Singh, Y.

2017-10-01

In this paper, we propose structural modifications in the conventional planar metal-oxide-semiconductor field-effect transistor (MOSFET) on silicon-on-insulator by utilizing trenches in the epitaxial layer. The proposed multi-finger MOSFET (MF-MOSFET) has dual vertical-gates placed in separate trenches to form multiple channels in the p-base which carry the drain current in parallel. The proposed device uses TaN as gate electrode and SiO2 as gate dielectric. Simultaneous conduction of multiple channels enhances the drain current (ID) and provides higher transconductance (gm) leading to significant improvement in cut-off frequency (ft). Two-dimensional simulations are performed to evaluate and compare the performance of the MF-MOSFET with the conventional MOSFET. At a gate length of 60 nm, the proposed device provides 4 times higher ID, 3 times improvement in gm and 1.25 times increase in ft with better control over the short channel effects as compared with the conventional device.

Sub-THz Imaging Using Non-Resonant HEMT Detectors.

PubMed

Delgado-Notario, Juan A; Velazquez-Perez, Jesus E; Meziani, Yahya M; Fobelets, Kristel

2018-02-10

Plasma waves in gated 2-D systems can be used to efficiently detect THz electromagnetic radiation. Solid-state plasma wave-based sensors can be used as detectors in THz imaging systems. An experimental study of the sub-THz response of II-gate strained-Si Schottky-gated MODFETs (Modulation-doped Field-Effect Transistor) was performed. The response of the strained-Si MODFET has been characterized at two frequencies: 150 and 300 GHz: The DC drain-to-source voltage transducing the THz radiation (photovoltaic mode) of 250-nm gate length transistors exhibited a non-resonant response that agrees with theoretical models and physics-based simulations of the electrical response of the transistor. When imposing a weak source-to-drain current of 5 μA, a substantial increase of the photoresponse was found. This increase is translated into an enhancement of the responsivity by one order of magnitude as compared to the photovoltaic mode, while the NEP (Noise Equivalent Power) is reduced in the subthreshold region. Strained-Si MODFETs demonstrated an excellent performance as detectors in THz imaging.

Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET.

PubMed

Dutta, Sangya; Kumar, Vinay; Shukla, Aditya; Mohapatra, Nihar R; Ganguly, Udayan

2017-08-15

Neuro-biology inspired Spiking Neural Network (SNN) enables efficient learning and recognition tasks. To achieve a large scale network akin to biology, a power and area efficient electronic neuron is essential. Earlier, we had demonstrated an LIF neuron by a novel 4-terminal impact ionization based n+/p/n+ with an extended gate (gated-INPN) device by physics simulation. Excellent improvement in area and power compared to conventional analog circuit implementations was observed. In this paper, we propose and experimentally demonstrate a compact conventional 3-terminal partially depleted (PD) SOI- MOSFET (100 nm gate length) to replace the 4-terminal gated-INPN device. Impact ionization (II) induced floating body effect in SOI-MOSFET is used to capture LIF neuron behavior to demonstrate spiking frequency dependence on input. MHz operation enables attractive hardware acceleration compared to biology. Overall, conventional PD-SOI-CMOS technology enables very-large-scale-integration (VLSI) which is essential for biology scale (~10 11 neuron based) large neural networks.

Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

NASA Astrophysics Data System (ADS)

Guerfi, Youssouf; Larrieu, Guilhem

2016-04-01

Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.

Current-voltage characteristics of molecular conductors: two versus three terminal

NASA Astrophysics Data System (ADS)

Damle, P.; Rakshit, T.; Paulsson, M.; Datta, S.

2002-09-01

This paper addresses the question of whether a ``rigid molecule'' (one which does not deform in an external field) used as the conducting channel in a standard three-terminal MOSFET configuration can offer any performance advantage relative to a standard silicon MOSFET. A self-consistent solution of coupled quantum transport and Poisson's equations shows that even for extremely small channel lengths (about 1 nm), a ``well-tempered'' molecular FET demands much the same electrostatic considerations as a ``well-tempered'' conventional MOSFET. In other words, we show that just as in a conventional MOSFET, the gate oxide thickness needs to be much smaller than the channel length (length of the molecule) for the gate control to be effective. Furthermore, we show that a rigid molecule with metallic source and drain contacts has a temperature independent subthreshold slope much larger than 60 mV/decade, because the metal-induced gap states in the channel prevent it from turning off abruptly. However, this disadvantage can be overcome by using semiconductor contacts because of their band-limited nature.

SLD-MOSCNT: A new MOSCNT with step-linear doping profile in the source and drain regions

NASA Astrophysics Data System (ADS)

Tahne, Behrooz Abdi; Naderi, Ali

2017-01-01

In this paper, a new structure, step-linear doping MOSCNT (SLD-MOSCNT), is proposed to improve the performance of basic MOSCNTs. The basic structure suffers from band to band tunneling (BTBT). We show that using SLD profile for source and drain regions increases the horizontal distance between valence and conduction bands at gate to source/drain junction which reduces BTBT probability. SLD performance is compared with other similar structures which have recently been proposed to reduce BTBT such as MOSCNT with lightly-doped drain and source (LDDS), and with double-light doping in source and drain regions (DLD). The obtained results using a nonequilibrium Green’s function (NEGF) method show that the SLD-MOSCNT has the lowest leakage current, power consumption and delay time, and the highest current ratio and voltage gain. The ambipolar conduction in the proposed structure is very low and can be neglected. In addition, these structures can improve short-channel effects. Also, the investigation of cutoff frequency of the different structures shows that the SLD has the highest cutoff frequency. Device performance has been investigated for gate length from 8 to 20 nm which demonstrates all discussions regarding the superiority of the proposed structure are also valid for different channel lengths. This improvement is more significant especially for channel length less than 12 nm. Therefore, the SLD can be considered as a candidate to be used in the applications with high speed and low power consumption.

Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

NASA Astrophysics Data System (ADS)

Jain, Neeraj; Raj, Balwinder

2017-12-01

Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects (SCEs), leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs), because of its more effective gate-controlling capabilities. In this paper, our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope (SS), ON current (I on), OFF current (I off) and I on/I off ratio. The potential benefits of SOI FinFET at drain-to-source voltage, V DS = 0.05 V and V DS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (A V), output conductance (g d), trans-conductance (g m), gate capacitance (C gg), and cut-off frequency (f T = g m/2πC gg) with spacer region variations.

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

NASA Astrophysics Data System (ADS)

Yu, Jie; Chen, Kun-ji; Ma, Zhong-yuan; Zhang, Xin-xin; Jiang, Xiao-fan; Wu, Yang-qing; Huang, Xin-fan; Oda, Shunri

2016-09-01

Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration. Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

Vertical InAs nanowire wrap gate transistors with f(t) > 7 GHz and f(max) > 20 GHz.

PubMed

Egard, M; Johansson, S; Johansson, A-C; Persson, K-M; Dey, A W; Borg, B M; Thelander, C; Wernersson, L-E; Lind, E

2010-03-10

In this letter we report on high-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors). The nanowire transistors are fabricated from InAs nanowires that are epitaxially grown on a semi-insulating InP substrate. All three terminals of the MOSFETs are defined by wrap around contacts. This makes it possible to perform high-frequency measurements on the vertical InAs MOSFETs. We present S-parameter measurements performed on a matrix consisting of 70 InAs nanowire MOSFETs, which have a gate length of about 100 nm. The highest unity current gain cutoff frequency, f(t), extracted from these measurements is 7.4 GHz and the maximum frequency of oscillation, f(max), is higher than 20 GHz. This demonstrates that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires.

Three-photon excitation source at 1250 nm generated in a dual zero dispersion wavelength nonlinear fiber

DOE PAGES

Domingue, Scott R.; Bartels, Randy A.

2014-12-04

Here, we demonstrate 1250 nm pulses generated in dual-zero dispersion photonic crystal fiber capable of three-photon excitation fluorescence microscopy. The total power conversion efficiency from the 28 fs seed pulse centered at 1075 nm to pulses at 1250 nm, including coupling losses from the nonlinear fiber, is 35%, with up to 67% power conversion efficiency of the fiber coupled light. Frequency-resolved optical gating measurements characterize 1250 nm pulses at 0.6 nJ and 2 nJ, illustrating the change in nonlinear spectral phase accumulation with pulse energy even for nonlinear fiber lengths < 50 mm. The 0.6 nJ pulse has a 26more » fs duration and is the shortest nonlinear fiber derived 1250 nm pulse yet reported (to the best of our knowledge). The short pulse durations and energies make these pulses a viable route to producing light at 1250 nm for multiphoton microscopy, which we we demonstrate here, via a three-photon excitation fluorescence microscope.« less

155- and 213-GHz AlInAs/GaInAs/InP HEMT MMIC oscillators

NASA Technical Reports Server (NTRS)

Rosenbaum, Steven E.; Kormanyos, Brian K.; Jelloian, Linda M.; Matloubian, Mehran; Brown, April S.; Larson, Lawrence E.; Nguyen, Loi D.; Thompson, Mark A.; Katehi, Linda P. B.; Rebeiz, Gabriel M.

1995-01-01

We report on the design and measurement of monolithic 155- and 213-GHz quasi-optical oscillators using AlInAs/GaInAs/InP HEMTs (high-electron mobility transistors). These results are believed to be the highest frequency three-terminal oscillators reported to date. The indium concentration in the channel was 80% for high sheet charge and mobility. The HEMT gates were fabricated with self-aligned sub-tenth-micrometer electron-beam techniques to achieve gate lengths on the order of 50 nm and drain-source spacing of 0.25 micron. Planar antennas were integrated into the fabrication process resulting in a compact and efficient quasi-optical Monolithic Millimeter-wave Integrated Circuit (MMIC) oscillator.

Monte Carlo simulations of spin transport in a strained nanoscale InGaAs field effect transistor

NASA Astrophysics Data System (ADS)

Thorpe, B.; Kalna, K.; Langbein, F. C.; Schirmer, S.

2017-12-01

Spin-based logic devices could operate at a very high speed with a very low energy consumption and hold significant promise for quantum information processing and metrology. We develop a spintronic device simulator by combining an in-house developed, experimentally verified, ensemble self-consistent Monte Carlo device simulator with spin transport based on a Bloch equation model and a spin-orbit interaction Hamiltonian accounting for Dresselhaus and Rashba couplings. It is employed to simulate a spin field effect transistor operating under externally applied voltages on a gate and a drain. In particular, we simulate electron spin transport in a 25 nm gate length In0.7Ga0.3As metal-oxide-semiconductor field-effect transistor with a CMOS compatible architecture. We observe a non-uniform decay of the net magnetization between the source and the gate and a magnetization recovery effect due to spin refocusing induced by a high electric field between the gate and the drain. We demonstrate a coherent control of the polarization vector of the drain current via the source-drain and gate voltages, and show that the magnetization of the drain current can be increased twofold by the strain induced into the channel.

Slowing DNA Translocation in a Nanofluidic Field-Effect Transistor.

PubMed

Liu, Yifan; Yobas, Levent

2016-04-26

Here, we present an experimental demonstration of slowing DNA translocation across a nanochannel by modulating the channel surface charge through an externally applied gate bias. The experiments were performed on a nanofluidic field-effect transistor, which is a monolithic integrated platform featuring a 50 nm-diameter in-plane alumina nanocapillary whose entire length is surrounded by a gate electrode. The field-effect transistor behavior was validated on the gating of ionic conductance and protein transport. The gating of DNA translocation was subsequently studied by measuring discrete current dips associated with single λ-DNA translocation events under a source-to-drain bias of 1 V. The translocation speeds under various gate bias conditions were extracted by fitting event histograms of the measured translocation time to the first passage time distributions obtained from a simple 1D biased diffusion model. A positive gate bias was observed to slow the translocation of single λ-DNA chains markedly; the translocation speed was reduced by an order of magnitude from 18.4 mm/s obtained under a floating gate down to 1.33 mm/s under a positive gate bias of 9 V. Therefore, a dynamic and flexible regulation of the DNA translocation speed, which is vital for single-molecule sequencing, can be achieved on this device by simply tuning the gate bias. The device is realized in a conventional semiconductor microfabrication process without the requirement of advanced lithography, and can be potentially further developed into a compact electronic single-molecule sequencer.

Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance

NASA Astrophysics Data System (ADS)

Tayal, Shubham; Nandi, Ashutosh

2018-06-01

This paper for the first time investigates the effect of temperature variation on analog/RF performance of SiO2 as well as high-K gate dielectric based junctionless silicon nanotube FET (JL-SiNTFET). It is observed that the change in temperature does not variate the analog/RF performance of junctionless silicon nanotube FET by substantial amount. By increasing the temperature from 77 K to 400 K, the deterioration in intrinsic dc gain (AV) is marginal that is only ∼3 dB. Furthermore, the variation in cut-off frequency (fT), maximum oscillation frequency (fMAX), and gain-frequency product (GFP) with temperature is also minimal in JLSiNT-FET. More so, the same trend is observed even at scaled gate length (Lg = 15 nm). Furthermore, we have observed that the use of high-K gate dielectric deteriorates the analog/RF performance of JLSiNT-FET. However, the use of high-K gate dielectric negligibly changes the effect of temperature variation on analog/RF performance of JLSINT-FET device.

Sub-THz Imaging Using Non-Resonant HEMT Detectors

PubMed Central

Delgado-Notario, Juan A.; Meziani, Yahya M.; Fobelets, Kristel

2018-01-01

Plasma waves in gated 2-D systems can be used to efficiently detect THz electromagnetic radiation. Solid-state plasma wave-based sensors can be used as detectors in THz imaging systems. An experimental study of the sub-THz response of II-gate strained-Si Schottky-gated MODFETs (Modulation-doped Field-Effect Transistor) was performed. The response of the strained-Si MODFET has been characterized at two frequencies: 150 and 300 GHz: The DC drain-to-source voltage transducing the THz radiation (photovoltaic mode) of 250-nm gate length transistors exhibited a non-resonant response that agrees with theoretical models and physics-based simulations of the electrical response of the transistor. When imposing a weak source-to-drain current of 5 μA, a substantial increase of the photoresponse was found. This increase is translated into an enhancement of the responsivity by one order of magnitude as compared to the photovoltaic mode, while the NEP (Noise Equivalent Power) is reduced in the subthreshold region. Strained-Si MODFETs demonstrated an excellent performance as detectors in THz imaging. PMID:29439437

93-133 GHz Band InP High-Electron-Mobility Transistor Amplifier with Gain-Enhanced Topology

NASA Astrophysics Data System (ADS)

Sato, Masaru; Shiba, Shoichi; Matsumura, Hiroshi; Takahashi, Tsuyoshi; Nakasha, Yasuhiro; Suzuki, Toshihide; Hara, Naoki

2013-04-01

In this study, we developed a new type of high-frequency amplifier topology using 75-nm-gate-length InP-based high-electron-mobility transistors (InP HEMTs). To enhance the gain for a wide frequency range, a common-source common-gate hybrid amplifier topology was proposed. A transformer-based balun placed at the input of the amplifier generates differential signals, which are fed to the gate and source terminals of the transistor. The amplified signal is outputted at the drain node. The simulation results show that the hybrid topology exhibits a higher gain from 90 to 140 GHz than that of the conventional common-source or common-gate amplifier. The two-stage amplifier fabricated using the topology exhibits a small signal gain of 12 dB and a 3-dB bandwidth of 40 GHz (93-133 GHz), which is the largest bandwidth and the second highest gain reported among those of published 120-GHz-band amplifiers. In addition, the measured noise figure was 5 dB from 90 to 100 GHz.

100 nm AlSb/InAs HEMT for ultra-low-power consumption, low-noise applications.

PubMed

Gardès, Cyrille; Bagumako, Sonia; Desplanque, Ludovic; Wichmann, Nicolas; Bollaert, Sylvain; Danneville, François; Wallart, Xavier; Roelens, Yannick

2014-01-01

We report on high frequency (HF) and noise performances of AlSb/InAs high electron mobility transistor (HEMT) with 100 nm gate length at room temperature in low-power regime. Extrinsic cut-off frequencies fT/f max of 100/125 GHz together with minimum noise figure NF(min) = 0.5 dB and associated gain G(ass) = 12 dB at 12 GHz have been obtained at drain bias of only 80 mV, corresponding to 4 mW/mm DC power dissipation. This demonstrates the great ability of AlSb/InAs HEMT for high-frequency operation combined with low-noise performances in ultra-low-power regime.

Field-Effect Transistors Based on Networks of Highly Aligned, Chemically Synthesized N = 7 Armchair Graphene Nanoribbons.

PubMed

Passi, Vikram; Gahoi, Amit; Senkovskiy, Boris V; Haberer, Danny; Fischer, Felix R; Grüneis, Alexander; Lemme, Max C

2018-03-28

We report on the experimental demonstration and electrical characterization of N = 7 armchair graphene nanoribbon (7-AGNR) field effect transistors. The back-gated transistors are fabricated from atomically precise and highly aligned 7-AGNRs, synthesized with a bottom-up approach. The large area transfer process holds the promise of scalable device fabrication with atomically precise nanoribbons. The channels of the FETs are approximately 30 times longer than the average nanoribbon length of 30 nm to 40 nm. The density of the GNRs is high, so that transport can be assumed well-above the percolation threshold. The long channel transistors exhibit a maximum I ON / I OFF current ratio of 87.5.

Molecule counting with alkanethiol and DNA immobilized on gold microplates for extended gate FET.

PubMed

Cao, Zhong; Xiao, Zhong-Liang; Zhang, Ling; Luo, Dong-Mei; Kamahori, Masao; Shimoda, Maki

2013-04-01

Several molecule counting methods based on electrochemical characterization of alkanethiol and thiolated single-stranded oligonucleotide (HS-ssDNA) immobilized on gold microplates, which were used as extended gates of field effect transistors (FETs), have been investigated in this paper. The surface density of alkanethiol and DNA monolayers on gold microplates were quantitatively evaluated from the reductive desorption charge by using cyclic voltammetry (CV) and fast CV (FCV) methods in strong alkali solution. Typically, the surface density of 6-hydroxy-1-hexanethiol (6-HHT) was evaluated to be 4.639 molecules/nm(2), and the 28 base-pair dsDNA about 1.226-4.849 molecules/100 nm(2) on Au microplates after post-treatment with 6-HHT. The behaviors on surface potential and capacitance of different aminoalkanethiols on Au microplates were measured in 0.1 mol/L Na2SO4 and 10 mmol/L Tris-HCl (pH=7.4) solutions, indicating that the surface potential increases and the double-layer capacitance decreases with the length of carbon chain increased for the thiol monolayers, which obey a physics relationship for a capacitor. Comparably, a simple sensing method based on the electronic signals of biochemical reaction events on DNA immobilization and hybridization at the Au surface of the extended gate FET (EGFET) was developed, with which the surface density of the hybridized dsDNA on the gold surface of the EGFET was evaluated to be 1.36 molecules per 100 nm(2), showing that the EGFET is a promising sensing biochip for DNA molecule counting. Copyright © 2012 Elsevier B.V. All rights reserved.

Effects of HfO2/Al2O3 gate stacks on electrical performance of planar In x Ga1- x As tunneling field-effect transistors

NASA Astrophysics Data System (ADS)

Ahn, Dae-Hwan; Yoon, Sang-Hee; Takenaka, Mitsuru; Takagi, Shinichi

2017-08-01

We study the impact of gate stacks on the electrical characteristics of Zn-diffused source In x Ga1- x As tunneling field-effect transistors (TFETs) with Al2O3 or HfO2/Al2O3 gate insulators. Ta and W gate electrodes are compared in terms of the interface trap density (D it) of InGaAs MOS interfaces. It is found that D it is lower at the W/HfO2/Al2O3 InGaAs MOS interface than at the Ta/HfO2/Al2O3 interface. The In0.53Ga0.47As TFET with a W/HfO2 (2.7 nm)/Al2O3 (0.3 nm) gate stack of 1.4-nm-thick capacitance equivalent thickness (CET) has a steep minimum subthreshold swing (SS) of 57 mV/dec, which is attributed to the thin CET and low D it. Also, the In0.53Ga0.47As (2.6 nm)/In0.67Ga0.33As (3.2 nm)/In0.53Ga0.47As (96.5 nm) quantum-well (QW) TFET supplemented with this 1.4-nm-thick CET gate stack exhibits a steeper minimum SS of 54 mV/dec and a higher on-current (I on) than those of the In0.53Ga0.47As TFET.

Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

NASA Astrophysics Data System (ADS)

Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

2009-11-01

We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgOx and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgOx gate operates under low voltage write-erase (WR-ER) pulse of ±20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of ±70 V for WR and ER states. Both devices stably operated under visible illuminations.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE Office of Scientific and Technical Information (OSTI.GOV)

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

ALD Al2O3 passivation of Lg = 100 nm metamorphic InAlAs/InGaAs HEMTs with Si-doped Schottky layers on GaAs substrates

NASA Astrophysics Data System (ADS)

Sun, Bing; Chang, Hudong; Wang, Shengkai; Niu, Jiebin; Liu, Honggang

2017-12-01

In0.52Al0.48As/In0.7Ga0.3As metamorphic high-electron-mobility transistors (mHEMTs) on GaAs substrates have been demonstrated. The devices feature an epitaxial structure with Si-doped InP/In0.52Al0.48As Schottky layers, together with an atomic layer deposition (ALD) Al2O3 passivation process. In comparison to the GaAs mHEMTs with plasma enhanced chemical vapor deposition (PECVD) SiN passivation, the devices with ALD Al2O3 passivation exhibit more than one order of magnitude lower gate leakage current (Jg) and much lower contact resistance (RC) and specific contact resistivity (ρC). 100-nm gate length (Lg) In0.52Al0.48As/In0.7Ga0.3As mHEMTs with Si-doped InP/In0.52Al0.48As Schottky layers and ALD Al2O3 passivation exhibit excellent DC and RF characteristics, such as a maximum oscillation frequency (fmax) of 388.2 GHz.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE PAGES

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; ...

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

Ion/Ioff ratio enhancement and scalability of gate-all-around nanowire negative-capacitance FET with ferroelectric HfO2

NASA Astrophysics Data System (ADS)

Jang, Kyungmin; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2017-10-01

We have investigated the energy efficiency and scalability of ferroelectric HfO2 (FE:HfO2)-based negative-capacitance field-effect-transistor (NCFET) with gate-all-around (GAA) nanowire (NW) channel structure. Analytic simulation is conducted to characterize NW-NCFET by varying NW diameter and/or thickness of gate insulator as device structural parameters. Due to the negative-capacitance effect and GAA NW channel structure, NW-NCFET is found to have 5× higher Ion/Ioff ratio than classical NW-MOSFET and 2× higher than double-gate (DG) NCFET, which results in wider design window for high Ion/Ioff ratio. To analyze these obtained results from the viewpoint of the device scalability, we have considered constraints regarding very limited device structural spaces to fit by the gate insulator and NW channel for aggresively scaled gate length (Lg) and/or very tight NW pitch. NW-NCFET still has design point with very thinned gate insulator and/or narrowed NW. Therefore, FE:HfO2-based NW-NCFET is applicable to the aggressively scaled technology node of sub-10 nm Lg and to the very tight NW integration of sub-30 nm NW pitch for beyond 7 nm technology. From 2011 to 2014, he engaged in developing high-speed optical transceiver module as an alternative military service in Republic of Korea. His research interest includes the development of steep slope MOSFETs for high energy-efficient operation and ferroelectric HfO2-based semiconductor devices, and fabrication of nanostructured devices. He joined the IBM T.J. Watson Research Center, Yorktown Heights, NY, in 2010, where he worked on advanced CMOS technologies such as FinFET, nanowire FET, SiGe channel and III-V channel. He was also engaged in launching 14 nm SOI FinFET and RMG technology development. Since 2014, he has been an Associate Professor in Institute of Industrial Science, University of Tokyo, Tokyo, Japan, where he has been working on ultralow power transistor and memory technology. Dr. Kobayashi is a member of IEEE and the Japan Society of Applied Physics. Dr. Hiramoto is a fellow of Japan Society of Applied Physics and a member of IEEE and IEICE. He served as the General Chair of Silicon Nanoelectronics Workshop in 2003 and the Program Chair in 1997, 1999, and 2001. He was on Committee of IEDM from 2003 to 2009. He was the Program Chair of Symposium on VLSI Technology in 2013 and was the General Chair in 2015. He is the Program Chair of International Conference on Solid-State Devices and Materials (SSDM) in 2016.

180-GHz I-Q Second Harmonic Resistive Mixer MMIC

NASA Technical Reports Server (NTRS)

Kangaslahti, Pekka P.; Lai, Richard; Mei, Xiaobing

2010-01-01

An indium phosphide MMIC (monolithic microwave integrated circuit) mixer was developed, processed, and tested in the NGC 35-nm-gate-length HEMT (high electron mobility transistor) process. This innovation is very compact in size and operates with very low LO power. Because it is a resistive mixer, this innovation does not require DC power. This is an enabling technology for the miniature receiver modules for the GeoSTAR instrument, which is the only viable option for the NRC decadal study mission PATH.

Linear Distributed GaN MMIC Power Amplifier with Improved Power-added Efficiency

DTIC Science & Technology

2017-03-01

Laboratories, 3011 Malibu Canyon Road, Malibu, CA 90265 Abstract: We report on a multi-octave (100 MHz ‒ 8 GHz), linear nonuniform distributed...amplifier (NDPA) in a MMIC architecture using scaled 120-nm short-gate- length GaN HEMTs. The linear NDPAs were built with six sections in a nonuniform ...MHz ‒ 8 GHz) GaN MMIC nonuniform distributed amplifier (NDPA) with built-in linearization and a gm3 cancellation method in class A and class C

The effect of split gate dimensions on the electrostatic potential and 0.7 anomaly within one-dimensional quantum wires on a modulation doped GaAs/AlGaAs heterostructure

NASA Astrophysics Data System (ADS)

Smith, L. W.; Al-Taie, H.; Lesage, A. A. J.; Thomas, K. J.; Sfigakis, F.; See, P.; Griffiths, J. P.; Farrer, I.; Jones, G. A. C.; Ritchie, D. A.; Kelly, M. J.; Smith, C. G.

We use a multiplexing scheme to measure the conductance properties of 95 split gates of 7 different gate dimensions fabricated on a GaAs/AlGaAs chip, in a single cool down. The number of devices for which conductance is accurately quantized reduces as the gate length increases. However, even the devices for which conductance is accurately quantized in units of 2e2 / h show no correlation between the length of electrostatic potential barrier in the channel and the gate length, using a saddle point model to estimate the barrier length. Further, the strength of coupling between the gates and the 1D channel does not increase with gate length beyond 0.7 μm. The background electrostatic profile appears as significant as the gate dimension in determining device behavior. We find a clear correlation between the curvature of the electrostatic barrier along the channel and the strength of the ``0.7 anomaly'' which identifies the electrostatic length of the channel as the principal factor governing the conductance of the 0.7 anomaly. Present address: Wisconsin Institute for Quantum Information, University of Wisconsin-Madison, Madison, WI.

Electronic Cortisol Detection Using an Antibody-Embedded Polymer Coupled to a Field-Effect Transistor.

PubMed

Jang, Hyun-June; Lee, Taein; Song, Jian; Russell, Luisa; Li, Hui; Dailey, Jennifer; Searson, Peter C; Katz, Howard E

2018-05-16

A field-effect transistor-based cortisol sensor was demonstrated in physiological conditions. An antibody-embedded polymer on the remote gate was proposed to overcome the Debye length issue (λ D ). The sensing membrane was made by linking poly(styrene- co-methacrylic acid) (PSMA) with anticortisol before coating the modified polymer on the remote gate. The embedded receptor in the polymer showed sensitivity from 10 fg/mL to 10 ng/mL for cortisol and a limit of detection (LOD) of 1 pg/mL in 1× PBS where λ D is 0.2 nm. A LOD of 1 ng/mL was shown in lightly buffered artificial sweat. Finally, a sandwich ELISA confirmed the antibody binding activity of antibody-embedded PSMA.

Design and Performance Analysis of Depletion-Mode InSb Quantum-Well Field-Effect Transistor for Logic Applications

NASA Astrophysics Data System (ADS)

Islam, R.; Uddin, M. M.; Hossain, M. Mofazzal; Matin, M. A.

The design of a 1μm gate length depletion-mode InSb quantum-well field-effect transistor (QWFET) with a 10nm-thick Al2O3 gate dielectric has been optimized using a quantum corrected self-consistent Schrödinger-Poisson (QCSP) and two-dimensional drift-diffusion model. The model predicts a very high electron mobility of 4.42m2V-1s-1 at Vg=0V, a small pinch off gate voltage (Vp) of -0.25V, a maximum extrinsic transconductance (gm) of ˜4.85mS/μm and a drain current density of more than 3.34mA/μm. A short-circuit current-gain cut-off frequency (fT) of 374GHz and a maximum oscillation frequency (fmax) of 645GHz are predicted for the device. These characteristics make the device a potential candidate for low power, high-speed logic electronic device applications.

Nanofabrication of 10-nm T-shaped gates using a double patterning process with electron beam lithography and dry etch

NASA Astrophysics Data System (ADS)

Shao, Jinhai; Deng, Jianan; Lu, W.; Chen, Yifang

2017-07-01

A process to fabricate T-shaped gates with the footprint scaling down to 10 nm using a double patterning procedure is reported. One of the keys in this process is to separate the definition of the footprint from that for the gate-head so that the proximity effect originated from electron forward scattering in the resist is significantly minimized, enabling us to achieve as narrow as 10-nm foot width. Furthermore, in contrast to the reported technique for 10-nm T-shaped profile in resist, this process utilizes a metallic film with a nanoslit as an etch mask to form a well-defined 10-nm-wide foot in a SiNx layer by reactive ion etch. Such a double patterning process has demonstrated enhanced reliability. The detailed process is comprehensively described, and its advantages and limitations are discussed. Nanofabrication of InP-based high-electron-mobility transistors using the developed process for 10- to 20-nm T-shaped gates is currently under the way.

Fabrication of 80-nm T-gate high indium In0.7Ga0.3As/In0.6Ga0.4As composite channels mHEMT on GaAs substrate with simple technological process

NASA Astrophysics Data System (ADS)

Xian, Ji; Xiaodong, Zhang; Weihua, Kang; Zhili, Zhang; Jiahui, Zhou; Wenjun, Xu; Qi, Li; Gongli, Xiao; Zhijun, Yin; Yong, Cai; Baoshun, Zhang; Haiou, Li

2016-02-01

An 80-nm gate length metamorphic high electron mobility transistor (mHEMT) on a GaAs substrate with high indium composite compound-channels In0.7Ga0.3 As/In0.6Ga0.4 As and an optimized grade buffer scheme is presented. High 2-DEG Hall mobility values of 10200 cm2/(V·s) and a sheet density of 3.5 × 1012 cm-2 at 300 K have been achieved. The device's T-shaped gate was made by utilizing a simple three layers electron beam resist, instead of employing a passivation layer for the T-share gate, which is beneficial to decreasing parasitic capacitance and parasitic resistance of the gate and simplifying the device manufacturing process. The ohmic contact resistance Rc is 0.2 ω·mm when using the same metal system with the gate (Pt/Ti/Pt/Au), which reduces the manufacturing cycle of the device. The mHEMT device demonstrates excellent DC and RF characteristics. The peak extrinsic transconductance of 1.1 S/mm and the maximum drain current density of 0.86 A/mm are obtained. The unity current gain cut-off frequency (fT) and the maximum oscillation frequency (fmax) are 246 and 301 GHz, respectively. Project supported by the Key Laboratory of Nano-Devices and Applications, Nano-Fabrication Facility of SINANO, Chinese Academy of Sciences, the National Natural Science Foundation of China (Nos. 61274077, 61474031, 61464003), the Guangxi Natural Science Foundation (Nos. 2013GXNSFGA019003, 2013GXNSFAA019335), the National Basic Research Program of China (Nos. 2011CBA00605, 2010CB327501), the Project (No. 9140C140101140C14069), and the Innovation Project of GUET Graduate Education (Nos. GDYCSZ201448, GDYCSZ201449, YJCXS201529).

Electron density and currents of AlN/GaN high electron mobility transistors with thin GaN/AlN buffer layer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bairamis, A.; Zervos, Ch.; Georgakilas, A., E-mail: alexandr@physics.uoc.gr

2014-09-15

AlN/GaN high electron mobility transistor (HEMT) structures with thin GaN/AlN buffer layer have been analyzed theoretically and experimentally, and the effects of the AlN barrier and GaN buffer layer thicknesses on two-dimensional electron gas (2DEG) density and transport properties have been evaluated. HEMT structures consisting of [300 nm GaN/ 200 nm AlN] buffer layer on sapphire were grown by plasma-assisted molecular beam epitaxy and exhibited a remarkable agreement with the theoretical calculations, suggesting a negligible influence of the crystalline defects that increase near the heteroepitaxial interface. The 2DEG density varied from 6.8 × 10{sup 12} to 2.1 × 10{sup 13} cm{sup −2} as themore » AlN barrier thickness increased from 2.2 to 4.5 nm, while a 4.5 nm AlN barrier would result to 3.1 × 10{sup 13} cm{sup −2} on a GaN buffer layer. The 3.0 nm AlN barrier structure exhibited the highest 2DEG mobility of 900 cm{sup 2}/Vs for a density of 1.3 × 10{sup 13} cm{sup −2}. The results were also confirmed by the performance of 1 μm gate-length transistors. The scaling of AlN barrier thickness from 1.5 nm to 4.5 nm could modify the drain-source saturation current, for zero gate-source voltage, from zero (normally off condition) to 0.63 A/mm. The maximum drain-source current was 1.1 A/mm for AlN barrier thickness of 3.0 nm and 3.7 nm, and the maximum extrinsic transconductance was 320 mS/mm for 3.0 nm AlN barrier.« less

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

NASA Astrophysics Data System (ADS)

Okamoto, Shin-ichi; Maekawa, Kei-ichi; Kawashima, Yoshiyuki; Shiba, Kazutoshi; Sugiyama, Hideki; Inoue, Masao; Nishida, Akio

2015-04-01

High quality static random access memory (SRAM) for 40-nm embedded MONOS flash memory with split gate (SG-MONOS) was developed. Marginal failure, which results in threshold voltage/drain current tailing and outliers of SRAM transistors, occurs when using a conventional SRAM structure. These phenomena can be explained by not only gate depletion but also partial depletion and percolation path formation in the MOS channel. A stacked poly-Si gate structure can suppress these phenomena and achieve high quality SRAM without any defects in the 6σ level and with high affinity to the 40-nm SG-MONOS process was developed.

Ultraclean single, double, and triple carbon nanotube quantum dots with recessed Re bottom gates

NASA Astrophysics Data System (ADS)

Jung, Minkyung; Schindele, Jens; Nau, Stefan; Weiss, Markus; Baumgartner, Andreas; Schoenenberger, Christian

2014-03-01

Ultraclean carbon nanotubes (CNTs) that are free from disorder provide a promising platform to manipulate single electron or hole spins for quantum information. Here, we demonstrate that ultraclean single, double, and triple quantum dots (QDs) can be formed reliably in a CNT by a straightforward fabrication technique. The QDs are electrostatically defined in the CNT by closely spaced metallic bottom gates deposited in trenches in Silicon dioxide by sputter deposition of Re. The carbon nanotubes are then grown by chemical vapor deposition (CVD) across the trenches and contacted using conventional electron beam lithography. The devices exhibit reproducibly the characteristics of ultraclean QDs behavior even after the subsequent electron beam lithography and chemical processing steps. We demonstrate the high quality using CNT devices with two narrow bottom gates and one global back gate. Tunable by the gate voltages, the device can be operated in four different regimes: i) fully p-type with ballistic transport between the outermost contacts (over a length of 700 nm), ii) clean n-type single QD behavior where a QD can be induced by either the left or the right bottom gate, iii) n-type double QD and iv) triple bipolar QD where the middle QD has opposite doping (p-type). Research at Basel is supported by the NCCR-Nano, NCCR-QIST, ERC project QUEST, and FP7 project SE2ND.

Graphene field effect transistor without an energy gap.

PubMed

Jang, Min Seok; Kim, Hyungjun; Son, Young-Woo; Atwater, Harry A; Goddard, William A

2013-05-28

Graphene is a room temperature ballistic electron conductor and also a very good thermal conductor. Thus, it has been regarded as an ideal material for postsilicon electronic applications. A major complication is that the relativistic massless electrons in pristine graphene exhibit unimpeded Klein tunneling penetration through gate potential barriers. Thus, previous efforts to realize a field effect transistor for logic applications have assumed that introduction of a band gap in graphene is a prerequisite. Unfortunately, extrinsic treatments designed to open a band gap seriously degrade device quality, yielding very low mobility and uncontrolled on/off current ratios. To solve this dilemma, we propose a gating mechanism that leads to a hundredfold enhancement in on/off transmittance ratio for normally incident electrons without any band gap engineering. Thus, our saw-shaped geometry gate potential (in place of the conventional bar-shaped geometry) leads to switching to an off state while retaining the ultrahigh electron mobility in the on state. In particular, we report that an on/off transmittance ratio of 130 is achievable for a sawtooth gate with a gate length of 80 nm. Our switching mechanism demonstrates that intrinsic graphene can be used in designing logic devices without serious alteration of the conventional field effect transistor architecture. This suggests a new variable for the optimization of the graphene-based device--geometry of the gate electrode.

Investigation of thermal effects on FinFETs in the quasi-ballistic regime

NASA Astrophysics Data System (ADS)

Yin, Longxiang; Shen, Lei; Di, Shaoyan; Du, Gang; Liu, Xiaoyan

2018-04-01

In this work, the thermal effects of FinFETs in the quasi-ballistic regime are investigated using the Monte Carlo method. Bulk Si nFinFETs with the same fin structure and two different gate lengths L g = 20 and 80 nm are investigated and compared to evaluate the thermal effects on the performance of FinFETs in the quasi-ballistic regime. The on current of the 20 nm FinFET with V gs = 0.7 V does not decrease with increasing lattice temperature (T L) at a high V ds. The electrostatic properties in the 20 nm FinFET are more affected by T L than those in the 80 nm FinFET. However, the electron transport in the 20 nm FinFET is less affected by T L than that in the 80 nm FinFET. The electrostatic properties being more sensitive and the electron transport being less sensitive to thermal effects in the quasi-ballistic regime than in the diffusive regime should be considered for effective device modeling and design.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons.

PubMed

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; Shi, Wu; Lee, Kyunghoon; Wu, Shuang; Yong Choi, Byung; Braganza, Rohit; Lear, Jordan; Kau, Nicholas; Choi, Wonwoo; Chen, Chen; Pedramrazi, Zahra; Dumslaff, Tim; Narita, Akimitsu; Feng, Xinliang; Müllen, Klaus; Fischer, Felix; Zettl, Alex; Ruffieux, Pascal; Yablonovitch, Eli; Crommie, Michael; Fasel, Roman; Bokor, Jeffrey

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch  ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on  > 1 μA at V d  = -1 V) and high I on /I off  ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.Graphene nanoribbons show promise for high-performance field-effect transistors, however they often suffer from short lengths and wide band gaps. Here, the authors use a bottom-up synthesis approach to fabricate 9- and 13-atom wide ribbons, enabling short-channel transistors with 10 5 on-off current ratio.

100 nm AlSb/InAs HEMT for Ultra-Low-Power Consumption, Low-Noise Applications

PubMed Central

Bagumako, Sonia; Desplanque, Ludovic; Wichmann, Nicolas; Bollaert, Sylvain; Danneville, François; Wallart, Xavier

2014-01-01

We report on high frequency (HF) and noise performances of AlSb/InAs high electron mobility transistor (HEMT) with 100 nm gate length at room temperature in low-power regime. Extrinsic cut-off frequencies f T/f max of 100/125 GHz together with minimum noise figure NFmin = 0.5 dB and associated gain G ass = 12 dB at 12 GHz have been obtained at drain bias of only 80 mV, corresponding to 4 mW/mm DC power dissipation. This demonstrates the great ability of AlSb/InAs HEMT for high-frequency operation combined with low-noise performances in ultra-low-power regime. PMID:24707193

Kerr-gated picosecond Raman spectroscopy and Raman photon migration of equine bone tissue with 400-nm excitation

NASA Astrophysics Data System (ADS)

Morris, Michael D.; Goodship, Allen E.; Draper, Edward R. C.; Matousek, Pavel; Towrie, Michael; Parker, Anthony W.

2004-07-01

We show that Raman spectroscopy with visible lasers, even in the deep blue is possible with time-gated Raman spectroscopy. A 4 picosec time gate allows efficient fluorescence rejection, up to 1000X, and provides almost background-free Raman spectra with low incident laser power. The technology enables spectroscopy with better than 10X higher scattering efficiency than is possible with the NIR (785 nm and 830 nm) lasers that are conventionally used. Raman photon migration is shown to allow depth penetration. We show for the first time that Kerr-gated Raman spectra of bone tissue with blue laser excitation enables both fluorescence rejection and depth penetration.

Field effect transistor and method of construction thereof

NASA Technical Reports Server (NTRS)

Fletner, W. R. (Inventor)

1978-01-01

A field effect transistor is constructed by placing a semi-conductor layer on an insulating substrate so that the gate region is separated from source and drain regions. The gate electrode and gate region of the layer are of generally reduced length, the gate region being of greatest length on its surface closest to the gate electrode. This is accomplished by initially creating a relatively large gate region of one polarity, and then reversing the polarity of a central portion of this gate region by ion bombardment, thus achieving a narrower final gate region of the stated configuration.

Material Synthesis and Device Aspects of Monolayer Tungsten Diselenide.

PubMed

Yao, Zihan; Liu, Jialun; Xu, Kai; Chow, Edmond K C; Zhu, Wenjuan

2018-03-27

In this paper, we investigate the synthesis of WSe 2 by chemical vapor deposition and study the current transport and device scaling of monolayer WSe 2 . We found that the device characteristics of the back-gated WSe 2 transistors with thick oxides are very sensitive to the applied drain bias, especially for transistors in the sub-micrometer regime. The threshold voltage, subthreshold swing, and extracted field-effect mobility vary with the applied drain bias. The output characteristics in the long-channel transistors show ohmic-like behavior, while that in the short-channel transistors show Schottky-like behavior. Our investigation reveals that these phenomena are caused by the drain-induced barrier lowering (short-channel effect). For back-gated WSe 2 transistors with 280 nm oxide, the short-channel effect appears when the channel length is shorter than 0.4 µm. This extremely long electrostatic scaling length is due to the thick back-gate oxides. In addition, we also found that the hydrogen flow rate and the amount of WO 3 precursor play an important role in the morphology of the WSe 2 . The hole mobility of the monolayer WSe 2 is limited by Columbic scattering below 250 K, while it is limited by phonon scattering above 250 K. These findings are very important for the synthesis of WSe 2 and accurate characterization of the electronic devices based on 2D materials.

Power efficient, clock gated multiplexer based full adder cell using 28 nm technology

NASA Astrophysics Data System (ADS)

Gupta, Ashutosh; Murgai, Shruti; Gulati, Anmol; Kumar, Pradeep

2016-03-01

Clock gating is a leading technique used for power saving. Full adders is one of the basic circuit that can be found in maximum VLSI circuits. In this paper clock gated multiplexer based full adder cell is implemented on 28 nm technology. We have designed a full adder cell using a multiplexer with a gated clock without degrading its performance of the cell. We have negative latch circuit for generating gated clock. This gated clock is used to control the multiplexer based full adder cell. The circuit has been synthesized on kintex FPGA through Xilinx ISE Design Suite 14.7 using 28 nm technology in Verilog HDL. The circuit has been simulated on Modelsim 10.3c. The design is verified using System Verilog on QuestaSim in UVM environment. The total power of the circuit has been reduced by 7.41% without degrading the performance of original circuit. The power has been calculated using XPower Analyzer tool of XILINX ISE DESIGN SUITE 14.3.

Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100 nm MOSFET's with Ultrathin Gate Oxide

NASA Technical Reports Server (NTRS)

Asenov, Asen; Saini, Subhash

2000-01-01

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFET's with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3-D) "atomistic" simulation technique described else-where. MOSFET's with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled-in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide-thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect or the polysilicon grain boundaries on the threshold voltage variation are also presented.

Effect of Split Gate Size on the Electrostatic Potential and 0.7 Anomaly within Quantum Wires on a Modulation-Doped GaAs /AlGaAs Heterostructure

NASA Astrophysics Data System (ADS)

Smith, L. W.; Al-Taie, H.; Lesage, A. A. J.; Thomas, K. J.; Sfigakis, F.; See, P.; Griffiths, J. P.; Farrer, I.; Jones, G. A. C.; Ritchie, D. A.; Kelly, M. J.; Smith, C. G.

2016-04-01

We study 95 split gates of different size on a single chip using a multiplexing technique. Each split gate defines a one-dimensional channel on a modulation-doped GaAs /AlGaAs heterostructure, through which the conductance is quantized. The yield of devices showing good quantization decreases rapidly as the length of the split gates increases. However, for the subset of devices showing good quantization, there is no correlation between the electrostatic length of the one-dimensional channel (estimated using a saddle-point model) and the gate length. The variation in electrostatic length and the one-dimensional subband spacing for devices of the same gate length exceeds the variation in the average values between devices of different lengths. There is a clear correlation between the curvature of the potential barrier in the transport direction and the strength of the "0.7 anomaly": the conductance value of the 0.7 anomaly reduces as the barrier curvature becomes shallower. These results highlight the key role of the electrostatic environment in one-dimensional systems. Even in devices with clean conductance plateaus, random fluctuations in the background potential are crucial in determining the potential landscape in the active device area such that nominally identical gate structures have different characteristics.

Fully industrialised single photon avalanche diodes

NASA Astrophysics Data System (ADS)

Pellegrini, S.; Rae, B.

2017-05-01

Single Photon Avalanche diodes (SPADs) were first realized more than five decades ago[1][1], and have now been industrialized for mass production in the 130 nm CMOS technology node by STMicroelectronics (STM). In this paper we present the latest STM SPAD with an excellent NIR photon detection probability (>5% at 850nm), a dark count rate median of 100 cps at room temperature and a low breakdown voltage of 14.2V. The dead time of the SPAD is approximately 25 ns, leading to a maximum count rate of 40 Mcps. Thanks to the 130 nm gate length of the CMOS technology used and the associated high digital gate density, complex digital signal processing can be implemented allowing fully integrated systems to be realized. The low bias required by the SPAD makes it possible for voltage generation to be achieved on-chip (e.g. charge pumped). We introduce our first generation time-of-flight system (VL6180) based on the STM SPAD technology, which is capable of ranging up to 60 cm in 60 ms. Ranging capabilities and accuracy are measured using a set of moving targets with reflectance of 5%, 17% and 88% in a fully automated test bed. To the best of our knowledge this was the first high volume SPAD-based device. To our knowledge this is the first time details of SPAD performance over production volumes and lifetime have been presented.

Indium arsenide-on-SOI MOSFETs with extreme lattice mismatch

NASA Astrophysics Data System (ADS)

Wu, Bin

Both molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD) have been used to explore the growth of InAs on Si. Despite 11.6% lattice mismatch, planar InAs structures have been observed by scanning electron microscopy (SEM) when nucleating using MBE on patterned submicron Si-on-insulator (SOI) islands. Planar structures of size as large as 500 x 500 nm 2 and lines of width 200 nm and length a few microns have been observed. MOCVD growth of InAs also generates single grain structures on Si islands when the size is reduced to 100 x 100 nm2. By choosing SOI as the growth template, selective growth is enabled by MOCVD. Post-growth pattern-then-anneal process, in which MOCVD InAs is deposited onto unpatterned SOI followed with patterning and annealing of InAs-on-Si structure, is found to change the relative lattice parameters of encapsulated 17/5 nm InAs/Si island. Observed from transmission electron diffraction (TED) patterns, the lattice mismatch of 17/5 nm InAs/Si island reduces from 11.2 to 4.2% after being annealed at 800°C for 30 minutes. High-k Al2O3 dielectrics have been deposited by both electron-beam-enabled physical vapor deposition (PVD) and atomic layer deposition (ALD). Films from both techniques show leakage currents on the order of 10-9A/cm2, at ˜1 MV/cm electric field, breakdown field > ˜6 MV/cm, and dielectric constant > 6, comparable to those of reported ALD prior arts by Groner. The first MOSFETs with extreme lattice mismatch InAs-on-SOI channels using PVD Al2O3 as the gate dielectric are characterized. Channel recess was used to improve the gate control of the drain current.

High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2017-03-01

In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (˜17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (˜87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH-1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

Analysis of source/drain engineered 22nm FDSOI using high-k spacers

NASA Astrophysics Data System (ADS)

Malviya, Abhishek Kumar; Chauhan, R. K.

2018-04-01

While looking at the current classical scaling of devices there are lots of short channel effects come into consideration. In this paper, a novel device structure is proposed that is an improved structure of Modified Source(MS) FDSOI in terms of better electrical performance, on current and reduced off state leakage current with a higher Ion/Ioff ratio that helps in fast switching of low power nano electronic devices. Proposed structure has Modified drain and source regions with two different type to doping profile at 22nm gate length. In the upper part of engineered region (MD and MS) the doping concentration is kept high and less in the lower region. The purpose was to achieve low parasitic capacitance in source and drain region by reducing doping concentration [1].

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

NASA Astrophysics Data System (ADS)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

Study on effective MOSFET channel length extracted from gate capacitance

NASA Astrophysics Data System (ADS)

Tsuji, Katsuhiro; Terada, Kazuo; Fujisaka, Hisato

2018-01-01

The effective channel length (L GCM) of metal-oxide-semiconductor field-effect transistors (MOSFETs) is extracted from the gate capacitances of actual-size MOSFETs, which are measured by charge-injection-induced-error-free charge-based capacitance measurement (CIEF CBCM). To accurately evaluate the capacitances between the gate and the channel of test MOSFETs, the parasitic capacitances are removed by using test MOSFETs having various channel sizes and a source/drain reference device. A strong linear relationship between the gate-channel capacitance and the design channel length is obtained, from which L GCM is extracted. It is found that L GCM is slightly less than the effective channel length (L CRM) extracted from the measured MOSFET drain current. The reason for this is discussed, and it is found that the capacitance between the gate electrode and the source and drain regions affects this extraction.

Compact modeling of nanoscale triple-gate junctionless transistors covering drift-diffusion to quasi-ballistic carrier transport

NASA Astrophysics Data System (ADS)

Oproglidis, T. A.; Karatsori, T. A.; Barraud, S.; Ghibaudo, G.; Dimitriadis, C. A.

2018-04-01

In this work, we extend our analytical compact model for nanoscale junctionless triple-gate (JL TG) MOSFETs, capturing carrier transport from drift-diffusion to quasi-ballistic regime. This is based on a simple formulation of the low-field mobility extracted from experimental data using the Y-function method, taking into account the ballistic carrier motion and an increased carrier scattering in process-induced defects near the source/drain regions. The case of a Schottky junction in non-ideal ohmic contact at the drain side was also taken into account by modifying the threshold voltage and ideality factor of the JL transistor. The model is validated with experimental data for n-channel JL TG MOSFETs with channel length varying from 95 down to 25 nm. It can be easily implemented as a compact model for use in Spice circuit simulators.

High mobility bottom gate InGaZnO thin film transistors with SiOx etch stopper

NASA Astrophysics Data System (ADS)

Kim, Minkyu; Jeong, Jong Han; Lee, Hun Jung; Ahn, Tae Kyung; Shin, Hyun Soo; Park, Jin-Seong; Jeong, Jae Kyeong; Mo, Yeon-Gon; Kim, Hye Dong

2007-05-01

The authors report on the fabrication of thin film transistors (TFTs), which use an amorphous indium gallium zinc oxide (a-IGZO) channel, by rf sputtering at room temperature and for which the channel length and width are patterned by photolithography and dry etching. To prevent plasma damage to the active channel, a 100-nm-thick SiOx layer deposited by plasma enhanced chemical vapor deposition was adopted as an etch stopper structure. The a-IGZO TFT (W /L=10μm/50μm) fabricated on glass exhibited a high field-effect mobility of 35.8cm2/Vs, a subthreshold gate swing value of 0.59V/decade, a thrseshold voltage of 5.9V, and an Ion/off ratio of 4.9×106, which is acceptable for use as the switching transistor of an active-matrix TFT backplane.

High performance Ω-gated Ge nanowire MOSFET with quasi-metallic source/drain contacts.

PubMed

Burchhart, T; Zeiner, C; Hyun, Y J; Lugstein, A; Hochleitner, G; Bertagnolli, E

2010-10-29

Ge nanowires (NWs) about 2 µm long and 35 nm in diameter are grown heteroepitaxially on Si(111) substrates in a hot wall low-pressure chemical vapor deposition (LP-CVD) system using Au as a catalyst and GeH(4) as precursor. Individual NWs are contacted to Cu pads via e-beam lithography, thermal evaporation and lift-off techniques. Self-aligned and atomically sharp quasi-metallic copper-germanide source/drain contacts are achieved by a thermal activated phase formation process. The Cu(3)Ge segments emerge from the Cu contact pads through axial diffusion of Cu which was controlled in situ by SEM, thus the active channel length of the MOSFET is adjusted without any restrictions from a lithographic process. Finally the conductivity of the channel is enhanced by Ga(+) implantation leading to a high performance Ω-gated Ge-NW MOSFET with saturation currents of a few microamperes.

Resonant tunneling of 1-dimensional electrons across an array of 3-dimensionally confined potential wells

NASA Astrophysics Data System (ADS)

Allee, D. R.; Chou, S. Y.; Harris, J. S.; Pease, R. F. W.

A lateral resonant tunneling field effect transistor has been fabricated with a gate electrode in the form of a railway such that the two rails form a lateral double barrier potential at the GaAs/AlGaAs interface. The ties confine the electrons in the third dimension forming an array of potential boxes or three dimensionally confined potential wells. The width of the ties and rails is 50nm; the spacings between the ties and between the two rails are 230nm and 150nm respectively. The ties are 750nm long and extend beyond the the two rails forming one dimensional wires on either side. Conductance oscillations are observed in the drain current at 4.2K as the gate voltage is scanned. Comparison with devices with a solid gate, and with a monorail gate with ties fabricated on the same wafer suggest that these conductance oscillations are electron resonant tunneling from one dimensional wires through the quasi-bound states of the three dimensionally confined potential wells. Comparison with a device with a two rail gate without ties (previously published) indicates that additional confinement due to the ties enhances the strength of the conductance oscillations.

Low voltage operation of GaN vertical nanowire MOSFET

NASA Astrophysics Data System (ADS)

Son, Dong-Hyeok; Jo, Young-Woo; Seo, Jae Hwa; Won, Chul-Ho; Im, Ki-Sik; Lee, Yong Soo; Jang, Hwan Soo; Kim, Dae-Hyun; Kang, In Man; Lee, Jung-Hee

2018-07-01

GaN gate-all-around (GAA) vertical nanowire MOSFET (VNWMOSFET) with channel length of 300 nm and diameter of 120 nm, the narrowest GaN-based vertical nanowire transistor ever achieved from the top-down approach, was fabricated by utilizing anisotropic side-wall wet etching in TMAH solution and photoresist etch-back process. The VNWMOSFET exhibited output characteristics with very low saturation drain voltage of less than 0.5 V, which is hardly observed from the wide bandgap-based devices. Simulation results indicated that the narrow diameter of the VNWMOSFET with relatively short channel length is responsible for the low voltage operation. The VNWMOSFET also demonstrated normally-off mode with threshold voltage (VTH) of 0.7 V, extremely low leakage current of ∼10-14 A, low drain-induced barrier lowering (DIBL) of 125 mV/V, and subthreshold swing (SS) of 66-122 mV/decade. The GaN GAA VNWMOSFET with narrow channel diameter investigated in this work would be promising for new low voltage logic application. He has been a Professor with the School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu, Korea, since 1993

Modeling of Nano-Scale Transistors and Memory Devices for Low Power Applications

NASA Astrophysics Data System (ADS)

Cao, Xi

As the featuring size of transistors scaled down to sub-20 nm, the continuous scaling of power has become one of the main challenges of the semiconductor industry. The power issue is raised by the barely scalable supply voltage and a limitation on the subthreshold swing (SS) of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, self-consistent quantum transport device simulators are developed to examine the nanoscale transistors based on black phosphorus (BP) materials. The scaling limit of double-gated BP MOSFETs is assessed. To reduce the SS below the thermionic limit for ultra-steep switching, tunnel FETs (TFETs) and vertical ballistic impact ionization FETs based on BP and its heterojunctions are investigated. Furthermore, the ferroelectric tunneling junction (FTJ) is modeled and examined for potential low power memory applications. For BP MOSFETs, the device physics at the ultimate scaling limit are examined. The performance of monolayer BP MOSFETs is projected to sub-10 nm and compared with the International Technology Roadmap for Semiconductors (ITRS) requirements. And the interplay of quantum mechanical effects and the highly anisotropic bandstructure of BP at this scale is investigated. By choice of layer number and crystalline direction, BP materials can offer a range of bandgap and effective mass values, which is attractive for TFET applications. Therefore, scaling behaviors of BP TFETs near and below the 10 nm scale are studied. The gate oxide thickness scaling and the effect of high-k dielectric are compared between the TFETs and the MOSFETs. For the TFETs with the gate lengths beyond 10 nm and at the sub-10 nm scale, the direct-source-to-drain tunneling issues are evaluated, and different strategies to achieve ultra-steep switching are specified. In a sub-10 nm graphene-BP-graphene heterojunction transistor, the sharp turnon behavior was observed, under a small source-drain bias of 0.1 V. The fast switch is attributed to a ballistic energy-dependent impact ionization mechanism. A device model is developed, which shows agreement with experiment results. The model is applied to explore the gate oxide scaling behavior and the effect of graphene doping, and to optimize the device for low power applications. Finally, to keep the integrity of the computing system, the FTJ is studied for its possible use as a low power memory device. A compact model for FTJ, dealing with both static and dynamic behaviors, is developed and compared with experimental data. The write energy consumed by the memory cell, comprising one transistor and one FTJ, is estimated by applying the compact model to circuit simulation. And a way to reduce the write energy is suggested.

Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

NASA Astrophysics Data System (ADS)

Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

2015-04-01

In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on-off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10-13-10-11 µm2/Hz for n-type and 10-12-10-10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

MOCVD of HfO2 and ZrO2 high-k gate dielectrics for InAlN/AlN/GaN MOS-HEMTs

NASA Astrophysics Data System (ADS)

Abermann, S.; Pozzovivo, G.; Kuzmik, J.; Strasser, G.; Pogany, D.; Carlin, J.-F.; Grandjean, N.; Bertagnolli, E.

2007-12-01

We apply metal organic chemical vapour deposition (MOCVD) of HfO2 and of ZrO2 from β-diketonate precursors to grow high-k gate dielectrics for InAlN/AlN/GaN metal oxide semiconductor (MOS)-high electron mobility transistors (HEMTs). High-k oxides of about 12 nm-14 nm are deposited for the MOS-HEMTs incorporating Ni/Au gates, whereas as a reference, Ni-contact-based 'conventional' Schottky-barrier (SB)-HEMTs are processed. The processed dielectrics decrease the gate current leakage of the HEMTs by about four orders of magnitude if compared with the SB-gated HEMTs and show superior device characteristics in terms of IDS and breakdown.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

PubMed

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2

NASA Astrophysics Data System (ADS)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-01

Top-gated and bottom-gated transistors with multilayer MoS2 channel fully encapsulated by stacked Al2O3/HfO2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on–off current ratio of 108, high field-effect mobility of 102 cm2 V‑1 s‑1, and low subthreshold swing of 93 mV dec–1. Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10‑3–10‑2 V MV–1 cm–1 after 6 MV cm‑1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS2 channel fully encapsulated by stacked Al2O3/HfO2 is a promising way to fabricate high-performance ML MoS2 field-effect transistors for practical electron device applications.

Study of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) transistor including source drain depletion length: Model for sub-threshold behavior

NASA Astrophysics Data System (ADS)

Kumari, Vandana; Kumar, Ayush; Saxena, Manoj; Gupta, Mridula

2018-01-01

The sub-threshold model formulation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) FET including source/drain depletion length is reported in the present work under the assumption that the ungated regions are fully depleted. To provide deeper insight into the device performance, the impact of gaussian straggle, channel length, oxide and channel thickness and high-k gate dielectric has been studied using extensive TCAD device simulation.

TDR method for determine IC's parameters

NASA Astrophysics Data System (ADS)

Timoshenkov, V.; Rodionov, D.; Khlybov, A.

2016-12-01

Frequency domain simulation is a widely used approach for determine integrated circuits parameters. This approach can be found in most of software tools used in IC industry. Time domain simulation approach shows intensive usage last years due to some advantages. In particular it applicable for analysis of nonlinear and nonstationary systems where frequency domain is inapplicable. Resolution of time domain systems allow see heterogeneities on distance 1mm, determine it parameters and properties. Authors used approach based on detecting reflected signals from heterogeneities - time domain reflectometry (TDR). Field effect transistor technology scaling up to 30-60nm gate length and 10nm gate dielectric, heterojunction bi-polar transistors with 10-30nm base width allows fabricate digital IC's with 20GHz clock frequency and RF-IC's with tens GHz bandwidth. Such devices and operation speed suppose transit signal by use microwave lines. There are local heterogeneities can be found inside of the signal path due to connections between different parts of signal lines (stripe line-RF-connector pin, stripe line - IC package pin). These heterogeneities distort signals that cause bandwidth decrease for RF-devices. Time domain research methods of transmission and reflected signals give the opportunities to determine heterogeneities, it properties, parameters and built up equivalent circuits. Experimental results are provided and show possibility for inductance and capacitance measurement up to 25GHz. Measurements contains result of signal path research on IC and printed circuit board (PCB) used for 12GHz RF chips. Also dielectric constant versus frequency was measured up to 35GHz.

New designs of a complete set of Photonic Crystals logic gates

NASA Astrophysics Data System (ADS)

Hussein, Hussein M. E.; Ali, Tamer A.; Rafat, Nadia H.

2018-03-01

In this paper, we introduce new designs of all-optical OR, AND, XOR, NOT, NOR, NAND and XNOR logic gates based on the interference effect. The designs are built using 2D square lattice Photonic Crystal (PhC) structure of dielectric rods embedded in air background. The lattice constant, a, and the rod radius, r, are designed to achieve maximum operating range of frequencies using the gap map. We use the Plane Wave Expansion (PWE) method to obtain the band structure and the gap map of the proposed designs. The operating wavelengths achieve a wide band range that varies between 1266.9 nm and 1996 nm with center wavelength at 1550 nm. The Finite-Difference Time-Domain (FDTD) method is used to study the field behavior inside the PhC gates. The gates satisfy their truth tables with reasonable power contrast ratio between logic '1' and logic '0'.

Saving Moore’s Law Down To 1 nm Channels With Anisotropic Effective Mass

NASA Astrophysics Data System (ADS)

Ilatikhameneh, Hesameddin; Ameen, Tarek; Novakovic, Bozidar; Tan, Yaohua; Klimeck, Gerhard; Rahman, Rajib

2016-08-01

Scaling transistors’ dimensions has been the thrust for the semiconductor industry in the last four decades. However, scaling channel lengths beyond 10 nm has become exceptionally challenging due to the direct tunneling between source and drain which degrades gate control, switching functionality, and worsens power dissipation. Fortunately, the emergence of novel classes of materials with exotic properties in recent times has opened up new avenues in device design. Here, we show that by using channel materials with an anisotropic effective mass, the channel can be scaled down to 1 nm and still provide an excellent switching performance in phosphorene nanoribbon MOSFETs. To solve power consumption challenge besides dimension scaling in conventional transistors, a novel tunnel transistor is proposed which takes advantage of anisotropic mass in both ON- and OFF-state of the operation. Full-band atomistic quantum transport simulations of phosphorene nanoribbon MOSFETs and TFETs based on the new design have been performed as a proof.

Comprehensive analysis of sub-20 nm black phosphorus based junctionless-recessed channel MOSFET for analog/RF applications

NASA Astrophysics Data System (ADS)

Kumar, Ajay; Tripathi, M. M.; Chaujar, Rishu

2018-04-01

In this work, a comprehensive analog and RF performance of a novel Black Phosphorus-Junctionless-Recessed Channel (BP-JL-RC) MOSFET has been explored at 45 nm technology node (Gate length = 20 nm). The integration of black phosphorus with junctionless recessed channel MOSFET, leads to higher drain current of about 0.3 mA and excellent switching ratio (of the order of 1011) due to reduced off-current which leads to improvement in sub-threshold slope (SS) (67mV/dec). Further, RF performance metrics have also been studied with an aim to analyze high-frequency performance. The following FOMs have been evaluated: cut-off frequency (fT), maximum oscillator frequency (fMAX), stern stability factor, various power gains and parasitic capacitances at THz frequency range. Thus, in addition to the high packing density offered by RC MOSFET, the proposed design finds numerous application at THz frequency making it a promising candidate at wafer scale integration level.

Capacitorless 1T-DRAM on crystallized poly-Si TFT.

PubMed

Kim, Min Soo; Cho, Won Ju

2011-07-01

The single-transistor dynamic random-access memory (1T-DRAM) using a polycrystalline-silicon thin-film transistor (poly-Si TFT) was investigated. A 100-nm amorphous silicon thin film was deposited onto a 200-nm oxidized silicon wafer via low-pressure chemical vapor deposition (LPCVD), and the amorphous silicon layer was crystallized via eximer laser annealing (ELA) with a KrF source of 248 nm wavelength and 400 mJ/cm2 power. The fabricated capacitor less 1T-DRAM on the poly-Si TFT was evaluated via impact ionization and gate-induced drain leakage (GIDL) current programming. The device showed a clear memory margin between the "1" and "0" states, and as the channel length decreased, a floating body effect which induces a kink effect increases with high mobility. Furthermore, the GIDL current programming showed improved memory properties compared to the impact ionization method. Although the sensing margins and retention times in both program methods are commercially insufficient, it was confirmed the feasibility of the application of 1T-DRAM operation to TFTs.

High Performance 50 nm InAlAs/In0.75GaAs Metamorphic High Electron Mobility Transistors with Si3N4 Passivation on Thin InGaAs Layer

NASA Astrophysics Data System (ADS)

Yeon, Seongjin; Seo, Kwangseok

2008-04-01

We fabricated 50 nm InAlAs/InGaAs metamorphic high electron mobility transistors (HEMTs) with a very thin barrier. Through the reduction of the gate-channel distance (dGC) in the epitaxial structure, a channel aspect ratio (ARC) of over three was achieved when Lg was 50 nm. We inserted a thin InGaAs layer as a protective layer, and tested various gate structures to reduce surface problems induced by barrier shrinkage and to optimize the device characteristics. Through the optimization of the gate structure with the thin InGaAs layer, the fabricated 50 nm metamorphic HEMT exhibited high DC and RF characteristics, Gm of 1.5 S/mm, and fT of 490 GHz.

High transconductance zinc oxide thin-film transistors on flexible plastic substrates

NASA Astrophysics Data System (ADS)

Kimura, Yuta; Higaki, Tomohiro; Maemoto, Toshihiko; Sasa, Shigehiko; Inoue, Masataka

2012-02-01

We report the fabrication and characterization on high-performance ZnO based TFTs on unheated plastic substrate. ZnO films were grown by pulsed laser deposition (PLD) on polyethylene napthalate (PEN) substrates. Top-gate ZnO-TFTs were fabricated by photolithography and wet chemical etching. The source and drain contacts were formed by lift-off of e-beam deposited Ti(20 nm)/Au(200 nm). An HfO2 with thickness 100 nm was selected as the gate insulator, and top gate electrode Ti(20 nm)/Au(200 nm) was deposited by e-beam evaporation. We prepared a set of the structure with SiO2/TiO2 to investigate the characteristic changes that appear in the film characteristics in response to bending. From the ID-VDS and the transfer characteristics which are affected by bending and return for the ZnO-TFT with SiO2/TiO2 buffers, the TFTs were bent to a curvature radius of 8.5 mm. The transconductance, gm is obtained 1.7 mS/mm on flat, 1.4 mS/mm on bending and 1.3 mS/mm on returning the film, respectively. The ID-VDS characteristics were therefore not changed by bending. All of the devices exhibited a clear pinch-off behavior and a high on/off current ratio of ˜10^6. The threshold voltages, Vth were not changed drastically. Furthermore, TFT structures were changed from a conventional top-gate type to a bottom-gate type. A high transconductance of 95.8 mS/mm was achieved in the bottom-gate type TFT by using Al2O3 oxide buffer.

Enhancing Photoresponsivity of Self-Aligned MoS2 Field-Effect Transistors by Piezo-Phototronic Effect from GaN Nanowires.

PubMed

Liu, Xingqiang; Yang, Xiaonian; Gao, Guoyun; Yang, Zhenyu; Liu, Haitao; Li, Qiang; Lou, Zheng; Shen, Guozhen; Liao, Lei; Pan, Caofeng; Lin Wang, Zhong

2016-08-23

We report high-performance self-aligned MoS2 field-effect transistors (FETs) with enhanced photoresponsivity by the piezo-phototronic effect. The FETs are fabricated based on monolayer MoS2 with a piezoelectric GaN nanowire (NW) as the local gate, and a self-aligned process is employed to define the source/drain electrodes. The fabrication method allows the preservation of the intrinsic property of MoS2 and suppresses the scattering center density in the MoS2/GaN interface, which results in high electrical and photoelectric performances. MoS2 FETs with channel lengths of ∼200 nm have been fabricated with a small subthreshold slope of 64 mV/dec. The photoresponsivity is 443.3 A·W(-1), with a fast response and recovery time of ∼5 ms under 550 nm light illumination. When strain is introduced into the GaN NW, the photoresponsivity is further enhanced to 734.5 A·W(-1) and maintains consistent response and recovery time, which is comparable with that of the mechanical exfoliation of MoS2 transistors. The approach presented here opens an avenue to high-performance top-gated piezo-enhanced MoS2 photodetectors.

A new methodological approach to assess cardiac work by pressure-volume and stress-length relations in patients with aortic valve stenosis and dilated cardiomyopathy.

PubMed

Alter, P; Rupp, H; Rominger, M B; Klose, K J; Maisch, B

2008-01-01

In experimental animals, cardiac work is derived from pressure-volume area and analyzed further using stress-length relations. Lack of methods for determining accurately myocardial mass has until now prevented the use of stress-length relations in patients. We hypothesized, therefore, that not only pressure-volume loops but also stress-length diagrams can be derived from cardiac volume and cardiac mass as assessed by cardiac magnetic resonance imaging (CMR) and invasively measured pressure. Left ventricular (LV) volume and myocardial mass were assessed in seven patients with aortic valve stenosis (AS), eight with dilated cardiomyopathy (DCM), and eight controls using electrocardiogram (ECG)-gated CMR. LV pressure was measured invasively. Pressure-volume curves were calculated based on ECG triggering. Stroke work was assessed as area within the pressure-volume loop. LV wall stress was calculated using a thick-wall sphere model. Similarly, stress-length loops were calculated to quantify stress-length-based work. Taking the LV geometry into account, the normalization with regard to ventricular circumference resulted in "myocardial work." Patients with AS (valve area 0.73+/-0.18 cm(2)) exhibited an increased LV myocardial mass when compared with controls (P<0.05). LV wall stress was increased in DCM but not in AS. Stroke work of AS was unchanged when compared with controls (0.539+/-0.272 vs 0.621+/-0.138 Nm, not significant), whereas DCM exhibited a significant depression (0.367+/-0.157 Nm, P<0.05). Myocardial work was significantly reduced in both AS and DCM when compared with controls (129.8+/-69.6, 200.6+/-80.1, 332.2+/-89.6 Nm/m(2), P<0.05), also after normalization (7.40+/-5.07, 6.27+/-3.20, 14.6+/-4.07 Nm/m(2), P<0.001). It is feasible to obtain LV pressure-volume and stress-length diagrams in patients based on the present novel methodological approach of using CMR and invasive pressure measurement. Myocardial work was reduced in patients with DCM and noteworthy also in AS, while stroke work was reduced in DCM only. Most likely, deterioration of myocardial work is crucial for the prognosis. It is suggested to include these basic physiological procedures in the clinical assessment of the pump function of the heart.

In2O3 nanowire based field effect transistor for biological sensors.

NASA Astrophysics Data System (ADS)

Zeng, Zhongming; Wang, Kai; Zhou, Weilie

2008-03-01

Semiconductor nanowires (NWs) are attracting considerable attention due to their nanoscale dimensions and enormous surface-to-volume ratios. Many applications have been demonstrated in toxic gas, protein, small molecule and viruses sensing because of their superior sensing performances. Indium oxide (In2O3) NWs have been successfully applied for toxic gas and small organic molecule sensing. In our experiment, In2O3 NWs based field effect transistors (FET) are fabricated for virus (Ricin) detections. Single-crystalline In2O3 NWs with diameters around 100 nm were synthesized by the thermal evaporation. The nanodevice based on In2O3 NWs bridges the source/drain electrodes with a channel length of ˜5 μm. Basic transport properties of devices were measured before biological detection. The I-V curves with the gate voltage Vg=0 shows good ohmic contact and the resistance is about 10 Mφ. The back-gate effect on the conductivity showed that In2O3 NW is working as n-type channel with obvious back-gate effect, which is much stronger than the reported results. The nanodevices used as virus detection will be also discussed.

Impact of strain on electronic and transport properties of 6 nm hydrogenated germanane nano-ribbon channel double gate field effect transistor

NASA Astrophysics Data System (ADS)

Meher Abhinav, E.; Sundararaj, Anuraj; Gopalakrishnan, Chandrasekaran; Kasmir Raja, S. V.; Chokhra, Saurabh

2017-11-01

In this work, chair like fully hydrogenated germanane (CGeH) nano-ribbon 6 nm short channel double gate field effect transistor (DG-FET) has been modeled and the impact of strain on the I-V characteristics of CGeH channel has been examined. The bond lengths, binding and formation energies of various hydrogenated geometries of buckled germanane channel were calculated using local density approximation (LDA) with Perdew-Zunger (PZ) and generalized gradient approximation (GGA) with Perdew Burke Ernzerhof (PBE) parameterization. From four various geometries, chair like structure is found to be more stable compared to boat like obtuse, stiruup structure and table like structure. The bandgap versus width, bandgap versus strain characteristics and I-V characteristics had been analyzed at room temperature using density functional theory (DFT). Using self consistent calculation it was observed that the electronic properties of nano-ribbon is independent of length and band structure, but dependent on edge type, strain [Uni-axial (ɛ xx ), bi-axial (ɛ xx   =  ɛ yy )] and width of the ribbon. The strain engineered hydrogenated germanane (GeH) showed wide direct bandgap (2.3 eV) which could help to build low noise electronic devices that operates at high frequencies. The observed bi-axial compression has high impact on the device transport characteristics with peak to valley ratio (PVR) of 2.14 and 380% increase in peak current compared to pristine CGeH device. The observed strain in CGeH DG-FET could facilitate in designing novel multiple-logic memory devices due to multiple negative differential resistance (NDR) regions.

A two-dimensional (2D) analytical subthreshold swing and transconductance model of underlap dual-material double-gate (DMDG) MOSFET for analog/RF applications

NASA Astrophysics Data System (ADS)

Narendar, Vadthiya; Rai, Saurabh; Tiwari, Siddharth; Mishra, R. A.

2016-12-01

The double-gate (DG) metal-oxide-semiconductor field effect transistors (MOSFETs) are the choice of technology in sub -100 nm regime of leading microelectronics industry. To enhance the analog and RF performance of DG MOSFET, an underlap dual-material (DM) DG MOSFET device structure has been considered because, it has the advantages of both underlap as well as that of dual-material gate (DMG). A 2D analytical surface potential, subthreshold current, subthreshold swing as well as transconductance modelling of underlap DMDG MOSFET has been done by solving the Poisson's equation. It has also been found that, numerically simulated data approves the analytically modelled data with commendable accuracy. As underlap length (Lun) increases, a substantial reduction of subthreshold current due to enhanced gate control over channel regime is observed. DMG structure facilitates to improve the average velocity of carriers which leads to superior drive current of the device. The underlap DMDG MOSFET device structure demonstrates an ameliorated subthreshold characteristic. The analog figure of merits (FOMs) such as transconductance (gm), transconductance generation factor (TGF), output conductance (gd), early voltage (VEA), intrinsic gain (AV) and RF FOMs namely cut-off frequency (fT), gain frequency product (GFP), transconductance frequency product (TFP) and gain transconductance frequency product (GTFP) have been evaluated. The aforesaid analysis revels that, the device is best suited for communication related Analog/RF applications.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Technical Reports Server (NTRS)

Sewell, James S.; Bozada, Christopher A.

1994-01-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Astrophysics Data System (ADS)

Sewell, James S.; Bozada, Christopher A.

1994-02-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Design and optimization analysis of dual material gate on DG-IMOS

NASA Astrophysics Data System (ADS)

Singh, Sarabdeep; Raman, Ashish; Kumar, Naveen

2017-12-01

An impact ionization MOSFET (IMOS) is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope (SS) of conventional MOSFET at room temperature. In this work, first, the device performance of the p-type double gate impact ionization MOSFET (DG-IMOS) is optimized by adjusting the device design parameters. The adjusted parameters are ratio of gate and intrinsic length, gate dielectric thickness and gate work function. Secondly, the DMG (dual material gate) DG-IMOS is proposed and investigated. This DMG DG-IMOS is further optimized to obtain the best possible performance parameters. Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS, shows better I ON, I ON/I OFF ratio, and RF parameters. Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS, optimized performance is achieved including I ON/I OFF ratio of 2.87 × 109 A/μm with I ON as 11.87 × 10-4 A/μm and transconductance of 1.06 × 10-3 S/μm. It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.

Tuning the gate-opening pressure and particle size distribution of the switchable metal-organic framework DUT-8(Ni) by controlled nucleation in a micromixer.

PubMed

Miura, Hiroki; Bon, Volodymyr; Senkovska, Irena; Ehrling, Sebastian; Watanabe, Satoshi; Ohba, Masaaki; Kaskel, Stefan

2017-10-17

Controlled nucleation in a micromixer and further crystal growth were used to synthesize Ni 2 (2,6-ndc) 2 dabco (2,6-ndc - 2,6-naphthalenedicarboxylate, dabco - 1,4-diazabicyclo[2.2.2]octane), also termed DUT-8(Ni) (DUT = Dresden University of Technology), with narrow particle size distribution in a range of a few nm to several μm. The crystal size was found to significantly affect the switching characteristics, in particular the gate opening pressure in nitrogen adsorption isotherms at 77 K for this highly porous and flexible network. Below a critical size of about 500 nm, a type Ia isotherm typical of rigid MOFs is observed, while above approximately 1000 nm a pronounced gating behaviour is detected, starting at p/p 0 = 0.2. With increasing crystal size this transition gate becomes steeper indicating a more uniform distribution of activation energies within the crystal ensemble. At an intermediate size (500-1000 nm), the DUT-8(Ni) crystals close during activation but cannot be reopened by nitrogen at 77 K possibly indicating monodomain switching.

Monolithic barrier-all-around high electron mobility transistor with planar GaAs nanowire channel.

PubMed

Miao, Xin; Zhang, Chen; Li, Xiuling

2013-06-12

High-quality growth of planar GaAs nanowires (NWs) with widths as small as 35 nm is realized by comprehensively mapping the parameter space of group III flow, V/III ratio, and temperature as the size of the NWs scales down. Using a growth mode modulation scheme for the NW and thin film barrier layers, monolithically integrated AlGaAs barrier-all-around planar GaAs NW high electron mobility transistors (NW-HEMTs) are achieved. The peak extrinsic transconductance, drive current, and effective electron velocity are 550 μS/μm, 435 μA/μm, and ~2.9 × 10(7) cm/s, respectively, at 2 V supply voltage with a gate length of 120 nm. The excellent DC performance demonstrated here shows the potential of this bottom-up planar NW technology for low-power high-speed very-large-scale-integration (VLSI) circuits.

A new FIB fabrication method for micropillar specimens for three-dimensional observation using scanning transmission electron microscopy.

PubMed

Fukuda, Muneyuki; Tomimatsu, Satoshi; Nakamura, Kuniyasu; Koguchi, Masanari; Shichi, Hiroyasu; Umemura, Kaoru

2004-01-01

A new method to prepare micropillar specimens with a high aspect ratio that is suitable for three-dimensional scanning transmission electron microscopy (3D-STEM) was developed. The key features of the micropillar fabrication are: first, microsampling to extract a small piece including the structure of interest in an IC chip, and second, an ion-beam with an incident direction of 60 degrees to the pillar's axis that enables the parallel sidewalls of the pillar to be produced with a high aspect ratio. A memory-cell structure (length: 6 microm; width: 300 x 500 nm) was fabricated in the micropillar and observed from various directions with a 3D-STEM. A planiform capacitor covered with granular surfaces and a solid crossing gate and metal lines was successfully observed threedimensionally at a resolution of approximately 5 nm.

Field emitter arrays and displays produced by ion tracking lithography

NASA Astrophysics Data System (ADS)

Felter, T. E.; Musket, R. G.; Bernhardt, A. F.

2005-12-01

When ions of sufficient electronic energy loss traverse a dielectric film or foil, they alter the chemical bonding along their nominally straight path within the material. A suitable etchant can quickly dissolve these so-called latent tracks leaving holes of small diameter (∼10 nm) but long length - several microns. Continuing the etching process gradually increases the diameter reproducibly and uniformly. The trackable medium can be applied as a uniform film onto large substrates. The small, monodisperse holes produced by this track etching can be used in conjunction with additional thin film processing to create functional structures attached to the substrate. For example, Lawrence Livermore National Laboratory and Candescent Technologies Corporation (CTC) co-developed a process to make arrays of gated field emitters (∼100 nm diameter electron guns) for CTC's Thin CRTTM displays, which have been fabricated to diagonal dimensions >13 in. Additional technological applications of ion tracking lithography will be briefly covered.

Kink effect in ultrathin FDSOI MOSFETs

NASA Astrophysics Data System (ADS)

Park, H. J.; Bawedin, M.; Choi, H. G.; Cristoloveanu, S.

2018-05-01

Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (<10 nm) and/or very short transistors (L < 50 nm), the kink is totally absent as a consequence of super-coupling effect. For the first time, thanks to the availability of body contacts, the body potential is probed to evidence the impact of majority carrier accumulation and drain pulse duration on the kink effect onset. He is currently working toward the Ph.D. degree in FDSOI device characterization and simulation at a laboratory of IMEP-lahc, Université Grenoble Alpes, Minatec, Grenoble, France. His research interests include residual floating body effects, electrical characterization, and device simulation for ultra FDSOI MOSFETs.

Ballistic Josephson junctions based on CVD graphene

NASA Astrophysics Data System (ADS)

Li, Tianyi; Gallop, John; Hao, Ling; Romans, Edward

2018-04-01

Josephson junctions with graphene as the weak link between superconductors have been intensely studied in recent years, with respect to both fundamental physics and potential applications. However, most of the previous work was based on mechanically exfoliated graphene, which is not compatible with wafer-scale production. To overcome this limitation, we have used graphene grown by chemical vapour deposition (CVD) as the weak link of Josephson junctions. We demonstrate that very short, wide CVD-graphene-based Josephson junctions with Nb electrodes can work without any undesirable hysteresis in their electrical characteristics from 1.5 K down to a base temperature of 320 mK, and their gate-tuneable critical current shows an ideal Fraunhofer-like interference pattern in a perpendicular magnetic field. Furthermore, for our shortest junctions (50 nm in length), we find that the normal state resistance oscillates with the gate voltage, consistent with the junctions being in the ballistic regime, a feature not previously observed in CVD-graphene-based Josephson junctions.

Improved performance of graphene transistors by strain engineering.

PubMed

Nguyen, V Hung; Nguyen, Huy-Viet; Dollfus, P

2014-04-25

By means of numerical simulation, in this work we study the effects of uniaxial strain on the transport properties of strained graphene heterojunctions and explore the possibility of achieving good performance of graphene transistors using these hetero-channels. It is shown that a finite conduction gap can open in the strain junctions due to strain-induced deformation of the graphene bandstructure. These hetero-channels are then demonstrated to significantly improve the operation of graphene field-effect transistors (FETs). In particular, the ON/OFF current ratio can reach a value of over 10(5). In graphene normal FETs, the transconductance, although reduced compared to the case of unstrained devices, is still high, while good saturation of current can be obtained. This results in a high voltage gain and a high transition frequency of a few hundreds of GHz for a gate length of 80 nm. In graphene tunneling FETs, subthreshold swings lower than 30 mV /dec, strong nonlinear effects such as gate-controllable negative differential conductance, and current rectification are observed.

Nanocrystal floating gate memory with solution-processed indium-zinc-tin-oxide channel and colloidal silver nanocrystals

NASA Astrophysics Data System (ADS)

Hu, Quanli; Ha, Sang-Hyub; Lee, Hyun Ho; Yoon, Tae-Sik

2011-12-01

A nanocrystal (NC) floating gate memory with solution-processed indium-zinc-tin-oxide (IZTO) channel and silver (Ag) NCs embedded in thin gate dielectric layer (SiO2(30 nm)/Al2O3(3 nm)) was fabricated. Both the IZTO channel and colloidal Ag NC layers were prepared by spin-coating and subsequent annealing, and dip-coating process, respectively. A threshold voltage shift up to ~0.9 V, corresponding to the electron density of 6.5 × 1011 cm-2, at gate pulsing <=10 V was achieved by the charging of high density NCs. These results present the successful non-volatile memory characteristics of an oxide-semiconductor transistor fabricated through solution processes.

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

NASA Astrophysics Data System (ADS)

Aleksandrova, P. V.; Gueorguiev, V. K.; Ivanov, Tz. E.; Kaschieva, S.

2006-08-01

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×1013 el/cm2, a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×1014 el/cm2 was observed.

Simulation study of reticle enhancement technology applications for 157-nm lithography

NASA Astrophysics Data System (ADS)

Schurz, Dan L.; Flack, Warren W.; Karklin, Linard

2002-03-01

The acceleration of the International Technology Roadmap for Semiconductors (ITRS) is placing significant pressure on the industry's infrastructure, particularly the lithography equipment. As recently as 1997, there was no optical solution offered past the 130 nm design node. The current roadmap has the 65 nm node (reduced from 70 nm) pulled in one year to 2007. Both 248 nm and 193 nm wavelength lithography tools will be pushed to their practical resolution limits in the near term. Very high numerical aperture (NA) 193 nm exposure tools in conjunction with resolution enhancement techniques (RET) will postpone the requirement for 157 nm lithography in manufacturing. However, ICs produced at 70 nm design rules with manufacturable k 1 values will require that 157 nm wavelength lithography tools incorporate the same RETs utilized in 248nm, and 193 nm tools. These enhancements will include Alternating Phase Shifting Masks (AltPSM) and Optical Proximity Correction (OPC) on F 2 doped quartz reticle substrates. This study investigates simulation results when AltPSM is applied to sub-100 nm test patterns in 157 nm lithography in order to maintain Critical Dimension (CD) control for both nested and isolated geometries. Aerial image simulations are performed for a range of numerical apertures, chrome regulators, gate pitches and gate widths. The relative performance for phase shifted versus binary structures is also compared. Results are demonstrated in terms of aerial image contrast and process window changes. The results clearly show that a combination of high NA and RET is necessary to achieve usable process windows for 70 nm line/space structures. In addition, it is important to consider two-dimensional proximity effects for sub-100 nm gate structures.

Impact of metal gates on remote phonon scattering in titanium nitride/hafnium dioxide n-channel metal-oxide-semiconductor field effect transistors-low temperature electron mobility study

NASA Astrophysics Data System (ADS)

Maitra, Kingsuk; Frank, Martin M.; Narayanan, Vijay; Misra, Veena; Cartier, Eduard A.

2007-12-01

We report low temperature (40-300 K) electron mobility measurements on aggressively scaled [equivalent oxide thickness (EOT)=1 nm] n-channel metal-oxide-semiconductor field effect transistors (nMOSFETs) with HfO2 gate dielectrics and metal gate electrodes (TiN). A comparison is made with conventional nMOSFETs containing HfO2 with polycrystalline Si (poly-Si) gate electrodes. No substantial change in the temperature acceleration factor is observed when poly-Si is replaced with a metal gate, showing that soft optical phonons are not significantly screened by metal gates. A qualitative argument based on an analogy between remote phonon scattering and high-resolution electron energy-loss spectroscopy (HREELS) is provided to explain the underlying physics of the observed phenomenon. It is also shown that soft optical phonon scattering is strongly damped by thin SiO2 interface layers, such that room temperature electron mobility values at EOT=1 nm become competitive with values measured in nMOSFETs with SiON gate dielectrics used in current high performance processors.

Characteristics of 0.8- and 0.2-microns gate length In(x)Ga(1-x) As/In(0.52)Al(0.48)As/InP (0.53 less than or equal to x less than or equal to 0.70) modulation-doped field-effect transistors at cryogenic temperatures

NASA Technical Reports Server (NTRS)

Lai, Richard; Bhattacharya, Pallab K.; Yang, David; Brock, Timothy L.; Alterovitz, Samuel A.; Downey, Alan N.

1993-01-01

The performance characteristics of InP-based In(x)Ga(1-x)As/In(0.52)Al(0.48)As (0.53 is less than or equal to x is less than or equal to 0.70) pseudomorphic modulation-doped field-effect transistors (MODFET's) as a function of strain in the channel, gate, length, and temperature were investigated analytically and experimentally. The strain in the channel was varied by varying the In composition x. The temperature was varied in the range of 40-300 K and the devices have gate lengths L(sub g) of 0.8 and 0.2 microns. Analysis of the device was done using a one-dimensional self consistent solution of the Poisson and Schroedinger equations in the channel, a two-dimensional Poisson solver to obtain the channel electric field, and a Monte Carlo simulation to estimate the carrier transit times in the channel. An increase in the value of the cutoff frequency is predicted for an increase in In composition, a decrease in temperature, and a decrease in gate length. The improvements seen with decreasing temperature, decreasing gate length, and increased In composition were smaller than those predicted by analysis. The experimental results on pseudomorphic InGaAs/InAlAs MODFET's showed that there is a 15-30 percent improvement in cutoff frequency in both the 0.8- and 0.2-micron gate length devices when the temperature is lowered from 300 to 40 K.

Low-Power and High-Speed Technique for logic Gates in 20nm Double-Gate FinFET Technology

NASA Astrophysics Data System (ADS)

Priydarshi, A.; Chattopadhyay, M. K.

2016-10-01

The FinFET is the leading example of multigate MOSFETS to substitute conventional single gate MOSFETs for ultimate scaling [1], The FinFET structure is a combination of a thin channel region and a double gate to suppress the short channel effects (SCEs) and Vthvariation [2], By using FinFET,figure of merits viz, ION, IOFF, output resistance, propagation delay, noise margin and leakage power, can be improved for ultra low power and high performance applications[3]. In this paper, a new high speed low power dynamic circuit design technique has been proposed using 20nm FinFETs. By applying the appropriate clock and sleep signal to the back gates of the FinFETs, the proposed circuit can efficiently control the dynamic power, During the pre-charging period, Vth of PMOS is controlled low so that a fast precharging can occur;

Low electron mobility of field-effect transistor determined by modulated magnetoresistance

NASA Astrophysics Data System (ADS)

Tauk, R.; Łusakowski, J.; Knap, W.; Tiberj, A.; Bougrioua, Z.; Azize, M.; Lorenzini, P.; Sakowicz, M.; Karpierz, K.; Fenouillet-Beranger, C.; Cassé, M.; Gallon, C.; Boeuf, F.; Skotnicki, T.

2007-11-01

Room temperature magnetotransport experiments were carried out on field-effect transistors in magnetic fields up to 10 T. It is shown that measurements of the transistor magnetoresistance and its first derivative with respect to the gate voltage allow the derivation of the electron mobility in the gated part of the transistor channel, while the access/contact resistances and the transistor gate length need not be known. We demonstrate the potential of this method using GaN and Si field-effect transistors and discuss its importance for mobility measurements in transistors with nanometer gate length.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

NASA Astrophysics Data System (ADS)

Maheran, A. H. Afifah; Menon, P. S.; Ahmad, I.; Shaari, S.; Faizah, Z. A. Noor

2015-04-01

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (ILEAK) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO2) and tungsten silicide (WSix). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum ILEAK where the maximum predicted ILEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in ILEAK mean value of 3.96821 nA/µm where is far lower than the predicted value.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maheran, A. H. Afifah; Menon, P. S.; Shaari, S.

2015-04-24

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I{sub LEAK}) onmore » PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO{sub 2}) and tungsten silicide (WSi{sub x}). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I{sub LEAK} where the maximum predicted I{sub LEAK} value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device’s leakage current. The absolute process parameters combination results in I{sub LEAK} mean value of 3.96821 nA/µm where is far lower than the predicted value.« less

Addressing FinFET metrology challenges in 1X node using tilt-beam CD-SEM

NASA Astrophysics Data System (ADS)

Zhang, Xiaoxiao; Zhou, Hua; Ge, Zhenhua; Vaid, Alok; Konduparthi, Deepasree; Osorio, Carmen; Ventola, Stefano; Meir, Roi; Shoval, Ori; Kris, Roman; Adan, Ofer; Bar-Zvi, Maayan

2014-04-01

At 1X node, 3D FinFETS raise a number of new metrology challenges. Gate height and fin height are two of the most important parameters for process control. At present there is a metrology gap in inline in-die measurement of these parameters. In order to fill this metrology gap, in-column beam tilt has been developed and implemented on Applied Materials V4i+ top-down CD-SEM for height measurement. A low tilt (5°) beam and a high tilt (14°) beam have been calibrated to obtain two sets of images providing measurement of sidewall edge width to calculate height in the host. Evaluations are done with applications in both gate height and fin height. TEM correlation with R2 being 0.89 and precision of 0.81nm have been achieved on various in-die features in gate height application. Fin height measurement shows less accuracy (R2 being 0.77) and precision (1.49 nm) due to challenges brought by fin geometry, yet still promising as first attempt. Sensitivity to DOE offset, die-to-die and in-die variation is demonstrated in both gate height and fin height. Process defect is successfully captured from inline wafers with gate height measurement implemented in production. This is the first successful demonstration of inline in-die gate height measurement for 14nm FinFET process control.

Thickness engineering of atomic layer deposited Al2O3 films to suppress interfacial reaction and diffusion of Ni/Au gate metal in AlGaN/GaN HEMTs up to 600 °C in air

NASA Astrophysics Data System (ADS)

Suria, Ateeq J.; Yalamarthy, Ananth Saran; Heuser, Thomas A.; Bruefach, Alexandra; Chapin, Caitlin A.; So, Hongyun; Senesky, Debbie G.

2017-06-01

In this paper, we describe the use of 50 nm atomic layer deposited (ALD) Al2O3 to suppress the interfacial reaction and inter-diffusion between the gate metal and semiconductor interface, to extend the operation limit up to 600 °C in air. Suppression of diffusion is verified through Auger electron spectroscopy (AES) depth profiling and X-ray diffraction (XRD) and is further supported with electrical characterization. An ALD Al2O3 thin film (10 nm and 50 nm), which functions as a dielectric layer, was inserted between the gate metal (Ni/Au) and heterostructure-based semiconductor material (AlGaN/GaN) to form a metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). This extended the 50 nm ALD Al2O3 MIS-HEMT (50-MIS) current-voltage (Ids-Vds) and gate leakage (Ig,leakage) characteristics up to 600 °C. Both, the 10 nm ALD Al2O3 MIS-HEMT (10-MIS) and HEMT, failed above 350 °C, as evidenced by a sudden increase of approximately 50 times and 5.3 × 106 times in Ig,leakage, respectively. AES on the HEMT revealed the formation of a Ni-Au alloy and Ni present in the active region. Additionally, XRD showed existence of metal gallides in the HEMT. The 50-MIS enables the operation of AlGaN/GaN based electronics in oxidizing high-temperature environments, by suppressing interfacial reaction and inter-diffusion of the gate metal with the semiconductor.

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE PAGES

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.; ...

2014-10-15

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Ellipticity dependence of high harmonics generated using 400 nm driving lasers

NASA Astrophysics Data System (ADS)

Cheng, Yan; Khan, Sabih; Zhao, Kun; Zhao, Baozhen; Chini, Michael; Chang, Zenghu

2011-05-01

High order harmonics generated from 400 nm driving pulses hold promise of scaling photon flux of single attosecond pulses by one to two orders of magnitude. We report ellipticity dependence and phase matching of high order harmonics generated from such pulses in Neon gas target and compared them with similar measurements using 800 nm driving pulses. Based on measured ellipticity dependence, we predict that double optical gating (DOG) and generalized double optical gating (GDOG) can be employed to extract intense single attosecond pulses from pulse train, while polarization gating (PG) may not work for this purpose. This material is supported by the U.S. Army Research Office under grant number W911NF-07-1-0475, and by the Chemical Sciences, Geosciences and Biosciences Division, Office of Basic Energy Sciences, Office of Science, U.S. Department of Energy.

Characterization of ultrathin SOI film and application to short channel MOSFETs.

PubMed

Tang, Xiaohui; Reckinger, Nicolas; Larrieu, Guilhem; Dubois, Emmanuel; Flandre, Denis; Raskin, Jean-Pierre; Nysten, Bernard; Jonas, Alain M; Bayot, Vincent

2008-04-23

In this study, a very dilute solution (NH(4)OH:H(2)O(2):H(2)O 1:8:64 mixture) was employed to reduce the thickness of commercially available SOI wafers down to 3 nm. The etch rate is precisely controlled at 0.11 Å s(-1) based on the self-limited etching speed of the solution. The thickness uniformity of the thin film, evaluated by spectroscopic ellipsometry and by high-resolution x-ray reflectivity, remains constant through the thinning process. Moreover, the film roughness, analyzed by atomic force microscopy, slightly improves during the thinning process. The residual stress in the thin film is much smaller than that obtained by sacrificial oxidation. Mobility, measured by means of a bridge-type Hall bar on 15 nm film, is not significantly reduced compared to the value of bulk silicon. Finally, the thinned SOI wafers were used to fabricate Schottky-barrier metal-oxide-semiconductor field-effect transistors with a gate length down to 30 nm, featuring state-of-the-art current drive performance.

A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond

NASA Astrophysics Data System (ADS)

Yasutake, Nobuaki; Azuma, Atsushi; Ishida, Tatsuya; Ohuchi, Kazuya; Aoki, Nobutoshi; Kusunoki, Naoki; Mori, Shinji; Mizushima, Ichiro; Morooka, Tetsu; Kawanaka, Shigeru; Toyoshima, Yoshiaki

2007-11-01

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe-source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved compared with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe-S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451 μA/μm at ∣ Vdd∣ of 0.9 V and Ioff of 100 nA/μm (552 μA/μm at ∣ Vdd∣ of 1.0 V). Furthermore, by combining with Vdd scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation.

How small can MOSFETs get?

NASA Astrophysics Data System (ADS)

Risch, Lothar

2001-10-01

Scaling of CMOS technology made possible the key appliances of our information technology society, like the PC, mobile communication, and the internet. Reduction of feature sizes for semiconductor devices continued according to Moore's law for the last 25 years in order to achieve higher integration densities, higher speed, lower power consumption, and lower costs. But now, as we approach the sub 100 nm regime, several roadblocks have been predicted for the next generations down to 35 nm. The latest ITRS roadmap 99 describes in detail the challenges which have to be addressed for the future CMOS technology nodes, regarding lithography, metallization, power dissipation, and circuit design. Also for the MOSFET, performance degradation is a big issue. Because this is not a limitation from basic physical laws, novel architectures for MOSFETs will be needed to improve again the electrical characteristics and thus pave the way to much smaller transistors than expected in the past. 25 nm CMOS seems to be feasible using very thin silicon substrates on insulator. Further improvements down to 10 nm are very likely with two gates for the control of the charge carriers. So, it is very likely that CMOS will not end with today's roadmap at 35 nm or even before, but may continue with non bulk devices and fully depleted channels. Finally, tunnelling from source to drain will set an end to the reduction of channel length, which is estimated to be below 5 nm.

High sensitivity pH sensing on the BEOL of industrial FDSOI transistors

NASA Astrophysics Data System (ADS)

Rahhal, Lama; Ayele, Getenet Tesega; Monfray, Stéphane; Cloarec, Jean-Pierre; Fornacciari, Benjamin; Pardoux, Eric; Chevalier, Celine; Ecoffey, Serge; Drouin, Dominique; Morin, Pierre; Garnier, Philippe; Boeuf, Frederic; Souifi, Abdelkader

2017-08-01

In this work we demonstrate the use of Fully Depleted Silicon On Insulator (FDSOI) transistors as pH sensors with a 23 nm silicon nitride sensing layer built in the Back-End-Of-Line (BEOL). The back end process to deposit the sensing layer and fabricate the electrical structures needed for testing is detailed. A series of tests employing different pH buffer solutions has been performed on transistors of different geometries, controlled via the back gate. The main findings show a shift of the drain current (ID) as a function of the back gate voltage (VB) when different pH buffer solutions are probed in the range of pH 6 to pH 8. This shift is observed at VB voltages swept from 0 V to 3 V, demonstrating the sensor operation at low voltage. A high sensitivity of up to 250 mV/pH unit (more than 4-fold larger than Nernstian response) is observed on FDSOI MOS transistors of 0.06 μm gate length and 0.08 μm gate width. She is currently working as a Postdoctoral researcher at Institut des nanotechnologies de Lyon in collaboration with STMicroelectronics and Université de Sherbrook (Canada) working on ;Integration of ultra-low-power gas and pH sensors with advanced technologies;. Her research interest includes selection, machining, optimisation and electrical characterisation of the sensitive layer for a low power consumption gas sensor based on advanced MOS transistors.

Detection beyond Debye's length with an electrolyte-gated organic field-effect transistor.

PubMed

Palazzo, Gerardo; De Tullio, Donato; Magliulo, Maria; Mallardi, Antonia; Intranuovo, Francesca; Mulla, Mohammad Yusuf; Favia, Pietro; Vikholm-Lundin, Inger; Torsi, Luisa

2015-02-04

Electrolyte-gated organic field-effect transistors are successfully used as biosensors to detect binding events occurring at distances from the transistor electronic channel that are much larger than the Debye length in highly concentrated solutions. The sensing mechanism is mainly capacitive and is due to the formation of Donnan's equilibria within the protein layer, leading to an extra capacitance (CDON) in series to the gating system. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Practical implementation, characterization and applications of a multi-colour time-gated luminescence microscope.

PubMed

Zhang, Lixin; Zheng, Xianlin; Deng, Wei; Lu, Yiqing; Lechevallier, Severine; Ye, Zhiqiang; Goldys, Ewa M; Dawes, Judith M; Piper, James A; Yuan, Jingli; Verelst, Marc; Jin, Dayong

2014-10-13

Time-gated luminescence microscopy using long-lifetime molecular probes can effectively eliminate autofluorescence to enable high contrast imaging. Here we investigate a new strategy of time-gated imaging for simultaneous visualisation of multiple species of microorganisms stained with long-lived complexes under low-background conditions. This is realized by imaging two pathogenic organisms (Giardia lamblia stained with a red europium probe and Cryptosporidium parvum with a green terbium probe) at UV wavelengths (320-400 nm) through synchronization of a flash lamp with high repetition rate (1 kHz) to a robust time-gating detection unit. This approach provides four times enhancement in signal-to-background ratio over non-time-gated imaging, while the average signal intensity also increases six-fold compared with that under UV LED excitation. The high sensitivity is further confirmed by imaging the single europium-doped Y₂O₂S nanocrystals (150 nm). We report technical details regarding the time-gating detection unit and demonstrate its compatibility with commercial epi-fluorescence microscopes, providing a valuable and convenient addition to standard laboratory equipment.

Practical Implementation, Characterization and Applications of a Multi-Colour Time-Gated Luminescence Microscope

NASA Astrophysics Data System (ADS)

Zhang, Lixin; Zheng, Xianlin; Deng, Wei; Lu, Yiqing; Lechevallier, Severine; Ye, Zhiqiang; Goldys, Ewa M.; Dawes, Judith M.; Piper, James A.; Yuan, Jingli; Verelst, Marc; Jin, Dayong

2014-10-01

Time-gated luminescence microscopy using long-lifetime molecular probes can effectively eliminate autofluorescence to enable high contrast imaging. Here we investigate a new strategy of time-gated imaging for simultaneous visualisation of multiple species of microorganisms stained with long-lived complexes under low-background conditions. This is realized by imaging two pathogenic organisms (Giardia lamblia stained with a red europium probe and Cryptosporidium parvum with a green terbium probe) at UV wavelengths (320-400 nm) through synchronization of a flash lamp with high repetition rate (1 kHz) to a robust time-gating detection unit. This approach provides four times enhancement in signal-to-background ratio over non-time-gated imaging, while the average signal intensity also increases six-fold compared with that under UV LED excitation. The high sensitivity is further confirmed by imaging the single europium-doped Y2O2S nanocrystals (150 nm). We report technical details regarding the time-gating detection unit and demonstrate its compatibility with commercial epi-fluorescence microscopes, providing a valuable and convenient addition to standard laboratory equipment.

Random dopant fluctuations and statistical variability in n-channel junctionless FETs

NASA Astrophysics Data System (ADS)

Akhavan, N. D.; Umana-Membreno, G. A.; Gu, R.; Antoszewski, J.; Faraone, L.

2018-01-01

The influence of random dopant fluctuations on the statistical variability of the electrical characteristics of n-channel silicon junctionless nanowire transistor (JNT) has been studied using three dimensional quantum simulations based on the non-equilibrium Green’s function (NEGF) formalism. Average randomly distributed body doping densities of 2 × 1019, 6 × 1019 and 1 × 1020 cm-3 have been considered employing an atomistic model for JNTs with gate lengths of 5, 10 and 15 nm. We demonstrate that by properly adjusting the doping density in the JNT, a near ideal statistical variability and electrical performance can be achieved, which can pave the way for the continuation of scaling in silicon CMOS technology.

Naphthalenetetracarboxylic diimide layer-based transistors with nanometer oxide and side chain dielectrics operating below one volt.

PubMed

Jung, Byung Jun; Martinez Hardigree, Josue F; Dhar, Bal Mukund; Dawidczyk, Thomas J; Sun, Jia; See, Kevin Cua; Katz, Howard E

2011-04-26

We designed a new naphthalenetetracarboxylic diimide (NTCDI) semiconductor molecule with long fluoroalkylbenzyl side chains. The side chains, 1.2 nm long, not only aid in self-assembly and kinetically stabilize injected electrons but also act as part of the gate dielectric in field-effect transistors. On Si substrates coated only with the 2 nm thick native oxide, NTCDI semiconductor films were deposited with thicknesses from 17 to 120 nm. Top contact Au electrodes were deposited as sources and drains. The devices showed good transistor characteristics in air with 0.1-1 μA of drain current at 0.5 V of V(G) and V(DS) and W/L of 10-20, even though channel width (250 μm) is over 1000 times the distance (20 nm) between gate and drain electrodes. The extracted capacitance-times-mobility product, an expression of the sheet transconductance, can exceed 100 nS V(-1), 2 orders of magnitude higher than typical organic transistors. The vertical low-frequency capacitance with gate voltage applied in the accumulation regime reached as high as 650 nF/cm(2), matching the harmonic sum of capacitances of the native oxide and one side chain and indicating that some gate-induced carriers in such devices are distributed among all of the NTCDI core layers, although the preponderance of the carriers are still near the gate electrode. Besides demonstrating and analyzing thickness-dependent NTCDI-based transistor behavior, we also showed <1 V detection of dinitrotoluene vapor by such transistors.

Gate-controlled topological conducting channels in bilayer graphene

NASA Astrophysics Data System (ADS)

Li, Jing; Wang, Ke; McFaul, Kenton J.; Zern, Zachary; Ren, Yafei; Watanabe, Kenji; Taniguchi, Takashi; Qiao, Zhenhua; Zhu, Jun

2016-12-01

The existence of inequivalent valleys K and K‧ in the momentum space of 2D hexagonal lattices provides a new electronic degree of freedom, the manipulation of which can potentially lead to new types of electronics, analogous to the role played by electron spin. In materials with broken inversion symmetry, such as an electrically gated bilayer graphene (BLG), the momentum-space Berry curvature Ω carries opposite sign in the K and K‧ valleys. A sign reversal of Ω along an internal boundary of the sheet gives rise to counterpropagating 1D conducting modes encoded with opposite-valley indices. These metallic states are topologically protected against backscattering in the absence of valley-mixing scattering, and thus can carry current ballistically. In BLG, the reversal of Ω can occur at the domain wall of AB- and BA-stacked domains, or at the line junction of two oppositely gated regions. The latter approach can provide a scalable platform to implement valleytronic operations, such as valves and waveguides, but it is technically challenging to realize. Here, we fabricate a dual-split-gate structure in BLG and present evidence of the predicted metallic states in electrical transport. The metallic states possess a mean free path (MFP) of up to a few hundred nanometres in the absence of a magnetic field. The application of a perpendicular magnetic field suppresses the backscattering significantly and enables a junction 400 nm in length to exhibit conductance close to the ballistic limit of 4e2/h at 8 T. Our experiment paves the way to the realization of gate-controlled ballistic valley transport and the development of valleytronic applications in atomically thin materials.

5. AVALON DAM GATE KEEPER'S COMPLEX: HOUSE (LEFT), WAREHOUSE ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

5. AVALON DAM - GATE KEEPER'S COMPLEX: HOUSE (LEFT), WAREHOUSE (RIGHT), AND CCC LANDSCAPING (FOREGROUND). VIEW TO SOUTHEAST - Carlsbad Irrigation District, Avalon Dam, On Pecos River, 4 miles North of Carlsbad, Carlsbad, Eddy County, NM

Fabrication of resistively-coupled single-electron device using an array of gold nanoparticles

NASA Astrophysics Data System (ADS)

Huong, Tran Thi Thu; Matsumoto, Kazuhiko; Moriya, Masataka; Shimada, Hiroshi; Kimura, Yasuo; Hirano-Iwata, Ayumi; Mizugaki, Yoshinao

2017-08-01

We demonstrated one type of single-electron device that exhibited electrical characteristics similar to those of resistively-coupled SE transistor (R-SET) at 77 K and room temperature (287 K). Three Au electrodes on an oxidized Si chip served as drain, source, and gate electrodes were formed using electron-beam lithography and evaporation techniques. A narrow (70-nm-wide) gate electrode was patterned using thermal evaporation, whereas wide (800-nm-wide) drain and source electrodes were made using shadow evaporation. Subsequently, aqueous solution of citric acid and 15-nm-diameter gold nanoparticles (Au NPs) and toluene solution of 3-nm-diameter Au NPs chemisorbed via decanethiol were dropped on the chip to make the connections between the electrodes. Current-voltage characteristics between the drain and source electrodes exhibited Coulomb blockade (CB) at both 77 and 287 K. Dependence of the CB region on the gate voltage was similar to that of an R-SET. Simulation results of the model based on the scanning electron microscopy image of the device could reproduce the characteristics like the R-SET.

Ads' click-through rates predicting based on gated recurrent unit neural networks

NASA Astrophysics Data System (ADS)

Chen, Qiaohong; Guo, Zixuan; Dong, Wen; Jin, Lingzi

2018-05-01

In order to improve the effect of online advertising and to increase the revenue of advertising, the gated recurrent unit neural networks(GRU) model is used as the ads' click through rates(CTR) predicting. Combined with the characteristics of gated unit structure and the unique of time sequence in data, using BPTT algorithm to train the model. Furthermore, by optimizing the step length algorithm of the gated unit recurrent neural networks, making the model reach optimal point better and faster in less iterative rounds. The experiment results show that the model based on the gated recurrent unit neural networks and its optimization of step length algorithm has the better effect on the ads' CTR predicting, which helps advertisers, media and audience achieve a win-win and mutually beneficial situation in Three-Side Game.

Polycrystalline diamond RF MOSFET with MoO3 gate dielectric

NASA Astrophysics Data System (ADS)

Ren, Zeyang; Zhang, Jinfeng; Zhang, Jincheng; Zhang, Chunfu; Chen, Dazheng; Quan, Rudai; Yang, Jiayin; Lin, Zhiyu; Hao, Yue

2017-12-01

We report the radio frequency characteristics of the diamond metal-oxide-semiconductor field effect transistor with MoO3 gate dielectric for the first time. The device with 2-μm gate length was fabricated on high quality polycrystalline diamond. The maximum drain current of 150 mA/mm at VGS = -5 V and the maximum transconductance of 27 mS/mm were achieved. The extrinsic cutoff frequency of 1.2 GHz and the maximum oscillation frequency of 1.9 GHz have been measured. The moderate frequency characteristics are attributed to the moderate transconductance limited by the series resistance along the channel. We expect that the frequency characteristics of the device can be improved by increasing the magnitude of gm, or fundamentally decreasing the gate-controlled channel resistance and series resistance along the channel, and down-scaling the gate length.

Surface stoichiometry modification and improved DC/RF characteristics by plasma treated and annealed AlGaN/GaN HEMTs

NASA Astrophysics Data System (ADS)

Upadhyay, Bhanu B.; Takhar, Kuldeep; Jha, Jaya; Ganguly, Swaroop; Saha, Dipankar

2018-03-01

We demonstrate that N2 and O2 plasma treatment followed by rapid thermal annealing leads to surface stoichiometry modification in a AlGaN/GaN high electron mobility transistor. Both the source/drain access and gate regions respond positively improving the transistor characteristics albeit to different extents. Characterizations indicate that the surface show the characteristics of that of a higher band-gap material like AlxOy and GaxOy along with N-vacancy in the sub-surface region. The N-vacancy leads to an increased two-dimensional electron gas density. The formation of oxides lead to a reduced gate leakage current and surface passivation. The DC characteristics show increased transconductance, saturation drain current, ON/OFF current ratio, sub-threshold swing and lower ON resistance by a factor of 2.9, 2.0, 103.3 , 2.3, and 2.1, respectively. The RF characteristics show an increase in unity current gain frequency by a factor of 1.7 for a 500 nm channel length device.

On-chip surface modified nanostructured ZnO as functional pH sensors

NASA Astrophysics Data System (ADS)

Zhang, Qing; Liu, Wenpeng; Sun, Chongling; Zhang, Hao; Pang, Wei; Zhang, Daihua; Duan, Xuexin

2015-09-01

Zinc oxide (ZnO) nanostructures are promising candidates as electronic components for biological and chemical applications. In this study, ZnO ultra-fine nanowire (NW) and nanoflake (NF) hybrid structures have been prepared by Au-assisted chemical vapor deposition (CVD) under ambient pressure. Their surface morphology, lattice structures, and crystal orientation were investigated by scanning electron microscopy (SEM), x-ray diffraction (XRD), and transmission electron microscopy (TEM). Two types of ZnO nanostructures were successfully integrated as gate electrodes in extended-gate field-effect transistors (EGFETs). Due to the amphoteric properties of ZnO, such devices function as pH sensors. We found that the ultra-fine NWs, which were more than 50 μm in length and less than 100 nm in diameter, performed better in the pH sensing process than NW-NF hybrid structures because of their higher surface-to-volume ratio, considering the Nernst equation and the Gouy-Chapman-Stern model. Furthermore, the surface coating of (3-Aminopropyl)triethoxysilane (APTES) protects ZnO nanostructures in both acidic and alkaline environments, thus enhancing the device stability and extending its pH sensing dynamic range.

Performance limits of tunnel transistors based on mono-layer transition-metal dichalcogenides

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jiang, Xiang-Wei, E-mail: xwjiang@semi.ac.cn; Li, Shu-Shen; Synergetic Innovation Center of Quantum Information and Quantum Physics, University of Science and Technology of China, Hefei, Anhui 230026

2014-05-12

Performance limits of tunnel field-effect transistors based on mono-layer transition metal dichalcogenides are investigated through numerical quantum mechanical simulations. The atomic mono-layer nature of the devices results in a much smaller natural length λ, leading to much larger electric field inside the tunneling diodes. As a result, the inter-band tunneling currents are found to be very high as long as ultra-thin high-k gate dielectric is possible. The highest on-state driving current is found to be close to 600 μA/μm at V{sub g} = V{sub d} = 0.5 V when 2 nm thin HfO{sub 2} layer is used for gate dielectric, outperforming most of the conventional semiconductor tunnelmore » transistors. In the five simulated transition-metal dichalcogenides, mono-layer WSe{sub 2} based tunnel field-effect transistor shows the best potential. Deep analysis reveals that there is plenty room to further enhance the device performance by either geometry, alloy, or strain engineering on these mono-layer materials.« less

Oxide-based platform for reconfigurable superconducting nanoelectronics.

PubMed

Veazey, Joshua P; Cheng, Guanglei; Irvin, Patrick; Cen, Cheng; Bogorin, Daniela F; Bi, Feng; Huang, Mengchen; Bark, Chung-Wung; Ryu, Sangwoo; Cho, Kwang-Hwan; Eom, Chang-Beom; Levy, Jeremy

2013-09-20

We report quasi-1D superconductivity at the interface of LaAlO3 and SrTiO3. The material system and nanostructure fabrication method supply a new platform for superconducting nanoelectronics. Nanostructures having line widths w ~ 10 nm are formed from the parent two-dimensional electron liquid using conductive atomic force microscope lithography. Nanowire cross-sections are small compared to the superconducting coherence length in LaAlO3/SrTiO3, placing them in the quasi-1D regime. Broad superconducting transitions versus temperature and finite resistances in the superconducting state well below Tc ≈ 200 mK are observed, suggesting the presence of fluctuation- and heating-induced resistance. The superconducting resistances and V-I characteristics are tunable through the use of a back gate. Four-terminal resistances in the superconducting state show an unusual dependence on the current path, varying by as much as an order of magnitude. This new technology, i.e., the ability to 'write' gate-tunable superconducting nanostructures on an insulating LaAlO3/SrTiO3 'canvas', opens possibilities for the development of new families of reconfigurable superconducting nanoelectronics.

6. AVALON DAM GATE KEEPER'S COMPLEX: GARAGE AND WAREHOUSE ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

6. AVALON DAM - GATE KEEPER'S COMPLEX: GARAGE AND WAREHOUSE (LEFT), HOUSE (RIGHT), AND CCC LANDSCAPING (FOREGROUND). VIEW TO NORTH - Carlsbad Irrigation District, Avalon Dam, On Pecos River, 4 miles North of Carlsbad, Carlsbad, Eddy County, NM

7. McMILLAN DAM GATE KEEPER'S HOUSE WITH CCC LANDSCAPING ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

7. McMILLAN DAM - GATE KEEPER'S HOUSE WITH CCC LANDSCAPING IN THE FOREGROUND. VIEW TO SOUTHEAST - Carlsbad Irrigation District, McMillan Dam, On Pecos River, 13 miles North of Carlsbad, Carlsbad, Eddy County, NM

Leakage and field emission in side-gate graphene field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Di Bartolomeo, A., E-mail: dibant@sa.infn.it; Iemmo, L.; Romeo, F.

We fabricate planar graphene field-effect transistors with self-aligned side-gate at 100 nm from the 500 nm wide graphene conductive channel, using a single lithographic step. We demonstrate side-gating below 1 V with conductance modulation of 35% and transconductance up to 0.5 mS/mm at 10 mV drain bias. We measure the planar leakage along the SiO{sub 2}/vacuum gate dielectric over a wide voltage range, reporting rapidly growing current above 15 V. We unveil the microscopic mechanisms driving the leakage, as Frenkel-Poole transport through SiO{sub 2} up to the activation of Fowler-Nordheim tunneling in vacuum, which becomes dominant at higher voltages. We report a field-emission current densitymore » as high as 1 μA/μm between graphene flakes. These findings are important for the miniaturization of atomically thin devices.« less

Mushroom-free selective epitaxial growth of Si, SiGe and SiGe:B raised sources and drains

NASA Astrophysics Data System (ADS)

Hartmann, J. M.; Benevent, V.; Barnes, J. P.; Veillerot, M.; Lafond, D.; Damlencourt, J. F.; Morvan, S.; Prévitali, B.; Andrieu, F.; Loubet, N.; Dutartre, D.

2013-05-01

We have evaluated various Cyclic Selective Epitaxial Growth/Etch (CSEGE) processes in order to grow "mushroom-free" Si and SiGe:B Raised Sources and Drains (RSDs) on each side of ultra-short gate length Extra-Thin Silicon-On-Insulator (ET-SOI) transistors. The 750 °C, 20 Torr Si CSEGE process we have developed (5 chlorinated growth steps with four HCl etch steps in-between) yielded excellent crystalline quality, typically 18 nm thick Si RSDs. Growth was conformal along the Si3N4 sidewall spacers, without any poly-Si mushrooms on top of unprotected gates. We have then evaluated on blanket 300 mm Si(001) wafers the feasibility of a 650 °C, 20 Torr SiGe:B CSEGE process (5 chlorinated growth steps with four HCl etch steps in-between, as for Si). As expected, the deposited thickness decreased as the total HCl etch time increased. This came hands in hands with unforeseen (i) decrease of the mean Ge concentration (from 30% down to 26%) and (ii) increase of the substitutional B concentration (from 2 × 1020 cm-3 up to 3 × 1020 cm-3). They were due to fluctuations of the Ge concentration and of the atomic B concentration [B] in such layers (drop of the Ge% and increase of [B] at etch step locations). Such blanket layers were a bit rougher than layers grown using a single epitaxy step, but nevertheless of excellent crystalline quality. Transposition of our CSEGE process on patterned ET-SOI wafers did not yield the expected results. HCl etch steps indeed helped in partly or totally removing the poly-SiGe:B mushrooms on top of the gates. This was however at the expense of the crystalline quality and 2D nature of the ˜45 nm thick Si0.7Ge0.3:B recessed sources and drains selectively grown on each side of the imperfectly protected poly-Si gates. The only solution we have so far identified that yields a lesser amount of mushrooms while preserving the quality of the S/D is to increase the HCl flow during growth steps.

Direct current performance and current collapse in AlGaN/GaN insulated gate high-electron mobility transistors on Si (1 1 1) substrate with very thin SiO2 gate dielectric

NASA Astrophysics Data System (ADS)

Lachab, M.; Sultana, M.; Fatima, H.; Adivarahan, V.; Fareed, Q.; Khan, M. A.

2012-12-01

This work reports on the dc performance of AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) grown on Si (1 1 1) substrate and the study of current dispersion in these devices using various widely adopted methods. The MOSHEMTs were fabricated using a very thin (4.2 nm) SiO2 film as the gate insulator and were subsequently passivated with about 30 nm thick Si3N4 layer. For devices with 2.5 µm long gates and a 4 µm drain-to-source spacing, the maximum saturation drain current density was 822 mA mm-1 at + 4 V gate bias and the peak external transconductance was ˜100 mS mm-1. Furthermore, the oxide layer successfully suppressed the drain and gate leakage currents with the subthreshold current and the gate diode current levels exceeding by more than three orders of magnitude the levels found in their Schottky gate counterparts. Capacitance-voltage and dynamic current-voltage measurements were carried out to assess the oxide quality as well as the devices’ surface properties after passivation. The efficacy of each of these characterization techniques to probe the presence of interface traps and oxide charge in the nitride-based transistors is also discussed.

Sub-1-V-60 nm vertical body channel MOSFET-based six-transistor static random access memory array with wide noise margin and excellent power delay product and its optimization with the cell ratio on static random access memory cell

NASA Astrophysics Data System (ADS)

Ogasawara, Ryosuke; Endoh, Tetsuo

2018-04-01

In this study, with the aim to achieve a wide noise margin and an excellent power delay product (PDP), a vertical body channel (BC)-MOSFET-based six-transistor (6T) static random access memory (SRAM) array is evaluated by changing the number of pillars in each part of a SRAM cell, that is, by changing the cell ratio in the SRAM cell. This 60 nm vertical BC-MOSFET-based 6T SRAM array realizes 0.84 V operation under the best PDP and up to 31% improvement of PDP compared with the 6T SRAM array based on a 90 nm planar MOSFET whose gate length and channel width are the same as those of the 60 nm vertical BC-MOSFET. Additionally, the vertical BC-MOSFET-based 6T SRAM array achieves an 8.8% wider read static noise margin (RSNM), a 16% wider write margin (WM), and an 89% smaller leakage. Moreover, it is shown that changing the cell ratio brings larger improvements of RSNM, WM, and write time in the vertical BC-MOSFET-based 6T SRAM array.

Doped bottom-contact organic field-effect transistors

NASA Astrophysics Data System (ADS)

Liu, Shiyi; Billig, Paul; Al-Shadeedi, Akram; Kaphle, Vikash; Lüssem, Björn

2018-07-01

The influence of doping on doped bottom-gate bottom-contact organic field-effect transistors (OFETs) is discussed. It is shown that the inclusion of a doped layer at the dielectric/organic semiconductor layer leads to a significant reduction in the contact resistances and a fine control of the threshold voltage. Through varying the thickness of the doped layer, a linear shift of threshold voltage V T from ‑3.1 to ‑0.22 V is observed for increasing thickness of doped layer. Meanwhile, the contact resistance at the source and drain electrode is reduced from 138.8 MΩ at V GS = ‑10 V for 3 nm to 0.3 MΩ for 7 nm thick doped layers. Furthermore, an increase of charge mobility is observed for increasing thickness of doped layer. Overall, it is shown that doping can minimize injection barriers in bottom-contact OFETs with channel lengths in the micro-meter regime, which has the potential to increase the performance of this technology further.

Graphene and PbS quantum dot hybrid vertical phototransistor

NASA Astrophysics Data System (ADS)

Song, Xiaoxian; Zhang, Yating; Zhang, Haiting; Yu, Yu; Cao, Mingxuan; Che, Yongli; Dai, Haitao; Yang, Junbo; Ding, Xin; Yao, Jianquan

2017-04-01

A field-effect phototransistor based on a graphene and lead sulfide quantum dot (PbS QD) hybrid in which PbS QDs are embedded in a graphene matrix has been fabricated with a vertical architecture through a solution process. The n-type Si/SiO2 substrate (gate), Au/Ag nanowire transparent source electrode, active layer and Au drain electrode are vertically stacked in the device, which has a downscaled channel length of 250 nm. Photoinduced electrons in the PbS QDs leap into the conduction band and fill in the trap states, while the photoinduced holes left in the valence band transfer to the graphene and form the photocurrent under biases from which the photoconductive gain is evaluated. The graphene/QD-based vertical phototransistor shows a photoresponsivity of 2 × 103 A W-1, and specific detectivity up to 7 × 1012 Jones under 808 nm laser illumination with a light irradiance of 12 mW cm-2. The solution-processed vertical phototransistor provides a new facile method for optoelectronic device applications.

Dependence of Pentacene Crystal Growth on Dielectric Roughness for Fabrication of Flexible Field-Effect Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, H.; Yang, C; Kim, S

2010-01-01

The dependence of pentacene nanostructures on gate dielectric surfaces were investigated for flexible organic field-effect transistor (OFET) applications. Two bilayer types of polymer/aluminum oxide (Al{sub 2}O{sub 3}) gate dielectrics were fabricated on commercial Al foils laminated onto a polymer back plate. Some Al foils were directly used as gate electrodes, and others were smoothly polished by an electrolytic etching. These Al surfaces were then anodized and coated with poly({alpha}-methyl styrene) (PAMS). For PAMS/Al{sub 2}O{sub 3} dielectrics onto etched Al foils, surface roughness up to 1 nm could be reached, although isolated dimples with a lateral diameter of several micrometers weremore » still present. On PAMS/Al{sub 2}O{sub 3} dielectrics (surface roughness >40 nm) containing mechanical grooves of Al foil, average hole mobility ({mu}FET) of 50 nm thick pentacene-FETs under the low operating voltages (|V| < 6 V) was {approx}0.15 cm{sup 2} V{sup -1} s{sup -1}. In contrast, pentacene-FETs employing the etched Al gates exhibited {mu}FET of 0.39 cm{sup 2} V{sup -1} s{sup -1}, which was comparable to that of reference samples with PAMS/Al{sub 2}O{sub 3} dielectrics onto flat sputtered Al gates. Conducting-probe atomic force microscopy and two-dimensional X-ray diffraction of pentacene films with various thicknesses revealed different out-of-plane and in-plane crystal orderings of pentacene, depending on the surface roughness of the gate dielectrics.« less

Investigation of aluminum gate CMP in a novel alkaline solution

NASA Astrophysics Data System (ADS)

Cuiyue, Feng; Yuling, Liu; Ming, Sun; Wenqian, Zhang; Jin, Zhang; Shuai, Wang

2016-01-01

Beyond 45 nm, due to the superior CMP performance requirements with the metal gate of aluminum in the advanced CMOS process, a novel alkaline slurry for an aluminum gate CMP with poly-amine alkali slurry is investigated. The aluminum gate CMP under alkaline conditions has two steps: stock polishing and fine polishing. A controllable removal rate, the uniformity of aluminum gate and low corrosion are the key challenges for the alkaline polishing slurry of the aluminum gate CMP. This work utilizes the complexation-soluble function of FA/O II and the preference adsorption mechanism of FA/O I nonionic surfactant to improve the uniformity of the surface chemistry function with the electrochemical corrosion research, such as OCP-TIME curves, Tafel curves and AC impedance. The result is that the stock polishing slurry (with SiO2 abrasive) contains 1 wt.% H2O2,0.5 wt.% FA/O II and 1.0 wt.% FA/O I nonionic surfactant. For a fine polishing process, 1.5 wt.% H2O2, 0.4 wt.% FA/O II and 2.0 wt.% FA/O I nonionic surfactant are added. The polishing experiments show that the removal rates are 3000 ± 50 Å/min and 1600 ± 60 Å/min, respectively. The surface roughnesses are 2.05 ± 0.128 nm and 1.59 ± 0.081 nm, respectively. A combination of the functions of FA/O II and FA/O I nonionic surfactant obtains a controllable removal rate and a better surface roughness in alkaline solution.

Effect of Environment on the Fidelity of Control and Measurements of Solid-State Quantum Devices

DTIC Science & Technology

2013-07-22

space vs. thickness of the film a for a DQD charge qubit in one dimension with dot geometry d = 30 nm and l = 60 nm at 0 K...constitute a conducting half- space , rather than the more sparse gate geometry used in [134]. It is also instructive to compare our results with the ...40 ms [134]. However, it must be kept in mind that we have so far considered the simpler top gate geometry of a conducting half-

Terahertz signal detection in a short gate length field-effect transistor with a two-dimensional electron gas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vostokov, N. V., E-mail: vostokov@ipm.sci-nnov.ru; Shashkin, V. I.

2015-11-28

We consider the problem of non-resonant detection of terahertz signals in a short gate length field-effect transistor having a two-dimensional electron channel with zero external bias between the source and the drain. The channel resistance, gate-channel capacitance, and quadratic nonlinearity parameter of the transistor during detection as a function of the gate bias voltage are studied. Characteristics of detection of the transistor connected in an antenna with real impedance are analyzed. The consideration is based on both a simple one-dimensional model of the transistor and allowance for the two-dimensional distribution of the electric field in the transistor structure. The resultsmore » given by the different models are discussed.« less

9. BLACK RIVER CANAL CANAL (RIGHT), DISCHARGE GATE (BACKGROUND), ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

9. BLACK RIVER CANAL - CANAL (RIGHT), DISCHARGE GATE (BACKGROUND), FARMER'S TURNOUT (LEFT), AND LATERAL NO. 14 (FOREGROUND). VIEW TO SOUTHEAST - Carlsbad Irrigation District, Black River Canal, 15 miles Southeast of Carlsbad near Malaga, Carlsbad, Eddy County, NM

Back-gated Nb-doped MoS2 junctionless field-effect-transistors

NASA Astrophysics Data System (ADS)

Mirabelli, Gioele; Schmidt, Michael; Sheehan, Brendan; Cherkaoui, Karim; Monaghan, Scott; Povey, Ian; McCarthy, Melissa; Bell, Alan P.; Nagle, Roger; Crupi, Felice; Hurley, Paul K.; Duffy, Ray

2016-02-01

Electrical measurements were carried out to measure the performance and evaluate the characteristics of MoS2 flakes doped with Niobium (Nb). The flakes were obtained by mechanical exfoliation and transferred onto 85 nm thick SiO2 oxide and a highly doped Si handle wafer. Ti/Au (5/45 nm) deposited on top of the flake allowed the realization of a back-gate structure, which was analyzed structurally through Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM). To best of our knowledge this is the first cross-sectional TEM study of exfoliated Nb-doped MoS2 flakes. In fact to date TEM of transition-metal-dichalcogenide flakes is extremely rare in the literature, considering the recent body of work. The devices were then electrically characterized by temperature dependent Ids versus Vds and Ids versus Vbg curves. The temperature dependency of the device shows a semiconductor behavior and, the doping effect by Nb atoms introduces acceptors in the structure, with a p-type concentration 4.3 × 1019 cm-3 measured by Hall effect. The p-type doping is confirmed by all the electrical measurements, making the structure a junctionless transistor. In addition, other parameters regarding the contact resistance between the top metal and MoS2 are extracted thanks to a simple Transfer Length Method (TLM) structure, showing a promising contact resistivity of 1.05 × 10-7 Ω/cm2 and a sheet resistance of 2.36 × 102 Ω/sq.

Transport properties of silicon complementary-metal-oxide semiconductor quantum well field-effect transistors

NASA Astrophysics Data System (ADS)

Naquin, Clint Alan

Introducing explicit quantum transport into silicon (Si) transistors in a manner compatible with industrial fabrication has proven challenging, yet has the potential to transform the performance horizons of large scale integrated Si devices and circuits. Explicit quantum transport as evidenced by negative differential transconductances (NDTCs) has been observed in a set of quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors fabricated using industrial silicon complementary MOS processing. The QW potential was formed via lateral ion implantation doping on a commercial 45 nm technology node process line, and measurements of the transfer characteristics show NDTCs up to room temperature. Detailed gate length and temperature dependence characteristics of the NDTCs in these devices have been measured. Gate length dependence of NDTCs shows a correlation of the interface channel length with the number of NDTCs formed as well as with the gate voltage (VG) spacing between NDTCs. The VG spacing between multiple NDTCs suggests a quasi-parabolic QW potential profile. The temperature dependence is consistent with partial freeze-out of carrier concentration against a degenerately doped background. A folding amplifier frequency multiplier circuit using a single QW NMOS transistor to generate a folded current-voltage transfer function via a NDTC was demonstrated. Time domain data shows frequency doubling in the kHz range at room temperature, and Fourier analysis confirms that the output is dominated by the second harmonic of the input. De-embedding the circuit response characteristics from parasitic cable and contact impedances suggests that in the absence of parasitics the doubling bandwidth could be as high as 10 GHz in a monolithic integrated circuit, limited by the transresistance magnitude of the QW NMOS. This is the first example of a QW device fabricated by mainstream Si CMOS technology being used in a circuit application and establishes the feasibility of scalable CMOS circuits that exploit explicit quantum transport. Ongoing quantum transport simulations based off of the spatial dopant distribution suggests a quasi-parabolic potential profile. Energy spacings between resonant transmission states are not consistent with experimental data, suggesting that either the assumed transport model is incomplete, or scattering mechanisms significantly mix the quasi-bound states and broaden the energy spacings.

Guiding gate-etch process development using 3D surface reaction modeling for 7nm and beyond

NASA Astrophysics Data System (ADS)

Dunn, Derren; Sporre, John R.; Deshpande, Vaibhav; Oulmane, Mohamed; Gull, Ronald; Ventzek, Peter; Ranjan, Alok

2017-03-01

Increasingly, advanced process nodes such as 7nm (N7) are fundamentally 3D and require stringent control of critical dimensions over high aspect ratio features. Process integration in these nodes requires a deep understanding of complex physical mechanisms to control critical dimensions from lithography through final etch. Polysilicon gate etch processes are critical steps in several device architectures for advanced nodes that rely on self-aligned patterning approaches to gate definition. These processes are required to meet several key metrics: (a) vertical etch profiles over high aspect ratios; (b) clean gate sidewalls free of etch process residue; (c) minimal erosion of liner oxide films protecting key architectural elements such as fins; and (e) residue free corners at gate interfaces with critical device elements. In this study, we explore how hybrid modeling approaches can be used to model a multi-step finFET polysilicon gate etch process. Initial parts of the patterning process through hardmask assembly are modeled using process emulation. Important aspects of gate definition are then modeled using a particle Monte Carlo (PMC) feature scale model that incorporates surface chemical reactions.1 When necessary, species and energy flux inputs to the PMC model are derived from simulations of the etch chamber. The modeled polysilicon gate etch process consists of several steps including a hard mask breakthrough step (BT), main feature etch steps (ME), and over-etch steps (OE) that control gate profiles at the gate fin interface. An additional constraint on this etch flow is that fin spacer oxides are left intact after final profile tuning steps. A natural optimization required from these processes is to maximize vertical gate profiles while minimizing erosion of fin spacer films.2

Gigahertz-gated InGaAs/InP single-photon detector with detection efficiency exceeding 55% at 1550 nm

DOE Office of Scientific and Technical Information (OSTI.GOV)

Comandar, L. C.; Engineering Department, Cambridge University, 9 J J Thomson Ave, Cambridge CB3 0FA; Fröhlich, B.

We report on a gated single-photon detector based on InGaAs/InP avalanche photodiodes (APDs) with a single-photon detection efficiency exceeding 55% at 1550 nm. Our detector is gated at 1 GHz and employs the self-differencing technique for gate transient suppression. It can operate nearly dead time free, except for the one clock cycle dead time intrinsic to self-differencing, and we demonstrate a count rate of 500 Mcps. We present a careful analysis of the optimal driving conditions of the APD measured with a dead time free detector characterization setup. It is found that a shortened gate width of 360 ps together with anmore » increased driving signal amplitude and operation at higher temperatures leads to improved performance of the detector. We achieve an afterpulse probability of 7% at 50% detection efficiency with dead time free measurement and a record efficiency for InGaAs/InP APDs of 55% at an afterpulse probability of only 10.2% with a moderate dead time of 10 ns.« less

Near-IR squaraine dye–loaded gated periodic mesoporous organosilica for photo-oxidation of phenol in a continuous-flow device

PubMed Central

Borah, Parijat; Sreejith, Sivaramapanicker; Anees, Palapuravan; Menon, Nishanth Venugopal; Kang, Yuejun; Ajayaghosh, Ayyappanpillai; Zhao, Yanli

2015-01-01

Periodic mesoporous organosilica (PMO) has been widely used for the fabrication of a variety of catalytically active materials. We report the preparation of novel photo-responsive PMO with azobenzene-gated pores. Upon activation, the azobenzene gate undergoes trans-cis isomerization, which allows an unsymmetrical near-infrared squaraine dye (Sq) to enter into the pores. The gate closure by cis-trans isomerization of the azobenzene unit leads to the safe loading of the monomeric dye inside the pores. The dye-loaded and azobenzene-gated PMO (Sq-azo@PMO) exhibits excellent generation of reactive oxygen species upon excitation at 664 nm, which can be effectively used for the oxidation of phenol into benzoquinone in aqueous solution. Furthermore, Sq-azo@PMO as the catalyst was placed inside a custom-built, continuous-flow device to carry out the photo-oxidation of phenol to benzoquinone in the presence of 664-nm light. By using the device, about 23% production of benzoquinone with 100% selectivity was achieved. The current research presents a prototype of transforming heterogeneous catalysts toward practical use. PMID:26601266

20-nm enhancement-mode metamorphic GaAs HEMT with highly doped InGaAs source/drain regions for high-frequency applications

NASA Astrophysics Data System (ADS)

Ajayan, J.; Nirmal, D.

2017-03-01

In this article, the DC and RF performance of a SiN passivated 20-nm gate length metamorphic high electron mobility transistor (MHEMT) on GaAs substrate with highly doped InGaAs source/drain (S/D) regions have investigated using the Synopsys TCAD tool. The 20-nm enhancement-mode (E-mode) MHEMT device also features δ-doped sheets on either side of the In0.53Ga0.47As/InAs/In0.53Ga0.47As channel which exhibits a transconductance of 3100 mS/mm, cut-off frequency (fT) of 740 GHz and a maximum oscillation frequency (fmax) of 1040 GHz. The threshold voltage of the device is found to be 0.07 V. The room temperature Hall mobilities of the 2-dimensional sheet charge density are measured to be over 12,600 cm2/Vs with a sheet charge density larger than 3.6 × 1012 cm-2. These high-performance E-mode MHEMTs are attractive candidates for sub-millimetre wave applications such as high-resolution radars for space research, remote atmospheric sensing, imaging systems and also for low noise wide bandwidth amplifier for future communication systems.

Thin film three-dimensional topological insulator metal-oxide-semiconductor field-effect-transistors: A candidate for sub-10 nm devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Akhavan, N. D., E-mail: nima.dehdashti@uwa.edu.au; Jolley, G.; Umana-Membreno, G. A.

2014-08-28

Three-dimensional (3D) topological insulators (TI) are a new state of quantum matter in which surface states reside in the bulk insulating energy bandgap and are protected by time-reversal symmetry. It is possible to create an energy bandgap as a consequence of the interaction between the conduction band and valence band surface states from the opposite surfaces of a TI thin film, and the width of the bandgap can be controlled by the thin film thickness. The formation of an energy bandgap raises the possibility of thin-film TI-based metal-oxide-semiconductor field-effect-transistors (MOSFETs). In this paper, we explore the performance of MOSFETs basedmore » on thin film 3D-TI structures by employing quantum ballistic transport simulations using the effective continuous Hamiltonian with fitting parameters extracted from ab-initio calculations. We demonstrate that thin film transistors based on a 3D-TI structure provide similar electrical characteristics compared to a Si-MOSFET for gate lengths down to 10 nm. Thus, such a device can be a potential candidate to replace Si-based MOSFETs in the sub-10 nm regime.« less

High-performance silicon nanowire field-effect transistor with silicided contacts

NASA Astrophysics Data System (ADS)

Rosaz, G.; Salem, B.; Pauc, N.; Gentile, P.; Potié, A.; Solanki, A.; Baron, T.

2011-08-01

Undoped silicon nanowire (Si NW) field-effect transistors (FETs) with a back-gate configuration have been fabricated and characterized. A thick (200 nm) Si3N4 layer was used as a gate insulator and a p++ silicon substrate as a back gate. Si NWs have been grown by the chemical vapour deposition method using the vapour-liquid-solid mechanism and gold as a catalyst. Metallic contacts have been deposited using Ni/Al (80 nm/120 nm) and characterized before and after an optimized annealing step at 400 °C, which resulted in a great decrease in the contact resistance due to the newly formed nickel silicide/Si interface at source and drain. These optimized devices show a good hole mobility of around 200 cm2 V-1 s-1, in the same range as the bulk material, with a good ON current density of about 28 kA cm-2. Finally, hysteretic behaviour of NW channel conductance is discussed to explain the importance of NW surface passivation.

Gate-controlled quantum collimation in nanocolumn resonant tunneling transistors.

PubMed

Wensorra, J; Lepsa, M I; Trellenkamp, S; Moers, J; Indlekofer, K M; Lüth, H

2009-11-18

Nanoscaled resonant tunneling transistors (RTT) based on MBE-grown GaAs/AlAs double-barrier quantum well (DBQW) structures have been fabricated by a top-down approach using electron-beam lithographic definition of the vertical nanocolumns. In the preparation process, a reproducible mask alignment accuracy of below 10 nm has been achieved and the all-around metal gate at the level of the DBQW structure has been positioned at a distance of about 20 nm relative to the semiconductor nanocolumn. Due to the specific doping profile n++/i/n++ along the transistor nanocolumn, a particular confining potential is established for devices with diameters smaller than 70 nm, which causes a collimation effect of the propagating electrons. Under these conditions, room temperature optimum performance of the nano-RTTs is achieved with peak-to-valley current ratios above 2 and a peak current swing factor of about 6 for gate voltages between -6 and +6 V. These values indicate that our nano-RTTs can be successfully used in low power fast nanoelectronic circuits.

Electrical characterization of vertically stacked p-FET SOI nanowires

NASA Astrophysics Data System (ADS)

Cardoso Paz, Bruna; Cassé, Mikaël; Barraud, Sylvain; Reimbold, Gilles; Vinet, Maud; Faynot, Olivier; Antonio Pavanello, Marcelo

2018-03-01

This work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S&R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with [1 1 0]- and [1 0 0]-oriented channels, as a function of both fin width (WFIN) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15 nm gate length, for both orientations. Effective mobility is found around two times higher for [1 1 0]- in comparison to [1 0 0]-oriented NWs due to higher holes mobility contribution in (1 1 0) plan. Improvements obtained on ION/IOFF by reducing WFIN are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for [1 1 0]- and [1 0 0]-oriented NWs, respectively.

Evaluation of biasing and protection circuitry components for cryogenic MMIC low-noise amplifiers

NASA Astrophysics Data System (ADS)

Lamb, James W.

2014-05-01

Millimeter-wave integrated circuits with gate lengths as short as 35 nm are demonstrating extremely low-noise performance, especially when cooled to cryogenic temperatures. These operate at low voltages and are susceptible to damage from electrostatic discharge and improper biasing, as well as being sensitive to low-level interference. Designing a protection circuit for low voltages and temperatures is challenging because there is very little data available on components that may be suitable. Extensive testing at low temperatures yielded a set of components and a circuit topology that demonstrates the required level of protection for critical MMICs and similar devices. We present a circuit that provides robust protection for low voltage devices from room temperature down to 4 K.

T-gate geometric (solution for submicrometer gate length) HEMT: Physical analysis, modeling and implementation as parasitic elements and its usage as dual gate for variable gain amplifiers

NASA Astrophysics Data System (ADS)

Gupta, Ritesh; Rathi, Servin; Kaur, Ravneet; Gupta, Mridula; Gupta, R. S.

2009-03-01

In order to achieve superior RF performance, short gate length is required for the compound semiconductor field effect transistors, but the limitation in lithography for submicrometer gate lengths leads to the formation of various metal-insulator geometries like T-gate [Sandeep R. Bahl, Jesus A. del Alamo, Physics of breakdown in InAlAs/ n +-InGaAs heterostructure field-effect transistors, IEEE Trans. Electron Devices 41 (12) (1994) 2268-2275]. These geometries are the combination of various Metal-Semiconductor (MS)/Metal-Air-Semiconductor (MAS) contacts. Moreover, field plates [S. Karmalkar, M.S. Shur, G. Simin, M. Asif Khan, Field-plate engineering for HFETs, IEEE Trans. Electron Devices 52 (2005) 2534-2540] are also being fabricated these days, mainly at the drain end ( Γ-gate) having Metal-Insulator-Semiconductor (MIS) instead of MAS contact with the intention of increasing the breakdown voltage of the device. To realize the effect of upper gate electrode in the T-gate structure and field plates, an analytical model has been proposed in the present article by dividing the whole structure into MS/MIS contact regions, applying current continuity among them and solving iteratively. The model proposed for Metal-Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) [R. Gupta, S.K. Aggarwal, M. Gupta, R.S. Gupta, Analytical model for metal insulator semiconductor high electron mobility transistor (MISHEMT) for its high frequency and high power applications, J. Semicond. Technol. Sci. 6 (3) (2006) 189-198], is equally applicable to High Electron Mobility Transistors (HEMT) and has been used to formulate this model. In this paper, various structures and geometries have been compared to anticipate the need of T-gate modeling. The effect of MIS contacts has been implemented as parasitic resistance and capacitance and has also been studied to control the middle conventional gate as in dual gate technology by applying separate voltages across it. The results obtained using the proposed analytical scheme has been compared with simulated and experimental results, to prove the validity of our model.

33 CFR 401.48 - Turning basins.

Code of Federal Regulations, 2011 CFR

2011-07-01

.... 1—Opposite Brossard. (b) Turning Basin No. 2—Between Lock 7 and the Guard Gate Cut for vessels up to... vessels up to 107 m in overall length. (b) Turning Basin No. 2—Between Lock 7 and the Guard Gate Cut for...). (d) Turning Basin No. 4—North of Lock No. 8 for vessels up to 170 m in overall length. (e) For...

33 CFR 401.48 - Turning basins.

Code of Federal Regulations, 2010 CFR

2010-07-01

.... 1—Opposite Brossard. (b) Turning Basin No. 2—Between Lock 7 and the Guard Gate Cut for vessels up to... vessels up to 107 m in overall length. (b) Turning Basin No. 2—Between Lock 7 and the Guard Gate Cut for...). (d) Turning Basin No. 4—North of Lock No. 8 for vessels up to 170 m in overall length. (e) For...

Novel method for measurement of transistor gate length using energy-filtered transmission electron microscopy

NASA Astrophysics Data System (ADS)

Lee, Sungho; Kim, Tae-Hoon; Kang, Jonghyuk; Yang, Cheol-Woong

2016-12-01

As the feature size of devices continues to decrease, transmission electron microscopy (TEM) is becoming indispensable for measuring the critical dimension (CD) of structures. Semiconductors consist primarily of silicon-based materials such as silicon, silicon dioxide, and silicon nitride, and the electrons transmitted through a plan-view TEM sample provide diverse information about various overlapped silicon-based materials. This information is exceedingly complex, which makes it difficult to clarify the boundary to be measured. Therefore, we propose a simple measurement method using energy-filtered TEM (EF-TEM). A precise and effective measurement condition was obtained by determining the maximum value of the integrated area ratio of the electron energy loss spectrum at the boundary to be measured. This method employs an adjustable slit allowing only electrons with a certain energy range to pass. EF-TEM imaging showed a sharp transition at the boundary when the energy-filter’s passband centre was set at 90 eV, with a slit width of 40 eV. This was the optimum condition for the CD measurement of silicon-based materials involving silicon nitride. Electron energy loss spectroscopy (EELS) and EF-TEM images were used to verify this method, which makes it possible to measure the transistor gate length in a dynamic random access memory manufactured using 35 nm process technology. This method can be adapted to measure the CD of other non-silicon-based materials using the EELS area ratio of the boundary materials.

Double gate impact ionization MOS transistor: Proposal and investigation

NASA Astrophysics Data System (ADS)

Yang, Zhaonian; Zhang, Yue; Yang, Yuan; Yu, Ningmei

2017-02-01

In this paper, a double gate impact ionization MOS (DG-IMOS) transistor with improved performance is proposed and investigated by TCAD simulation. In the proposed design, a second gate is introduced in a conventional impact ionization MOS (IMOS) transistor that lengthens the equivalent channel length and suppresses the band-to-band tunneling. The OFF-state leakage current is reduced by over four orders of magnitude. At the ON-state, the second gate is negatively biased in order to enhance the electric field in the intrinsic region. As a result, the operating voltage does not increase with the increase in the channel length. The simulation result verifies that the proposed DG-IMOS achieves a better switching characteristic than the conventional is achieved. Lastly, the application of the DG-IMOS is discussed theoretically.

Effects of HfO2 encapsulation on electrical performances of few-layered MoS2 transistor with ALD HfO2 as back-gate dielectric.

PubMed

Xu, Jingping; Wen, Ming; Zhao, Xinyuan; Liu, Lu; Song, Xingjuan; Lai, Pui-To; Tang, Wing-Man

2018-08-24

The carrier mobility of MoS 2 transistors can be greatly improved by the screening role of high-k gate dielectric. In this work, atomic-layer deposited (ALD) HfO 2 annealed in NH 3 is used to replace SiO 2 as the gate dielectric to fabricate back-gated few-layered MoS 2 transistors, and good electrical properties are achieved with field-effect mobility (μ) of 19.1 cm 2 V -1 s -1 , subthreshold swing (SS) of 123.6 mV dec -1 and on/off ratio of 3.76 × 10 5 . Furthermore, enhanced device performance is obtained when the surface of the MoS 2 channel is coated by an ALD HfO 2 layer with different thicknesses (10, 15 and 20 nm), where the transistor with a 15 nm HfO 2 encapsulation layer exhibits the best overall electrical properties: μ = 42.1 cm 2 V -1 s -1 , SS = 87.9 mV dec -1 and on/off ratio of 2.72 × 10 6 . These improvements should be associated with the enhanced screening effect on charged-impurity scattering and protection from absorption of environmental gas molecules by the high-k encapsulation. The capacitance equivalent thickness of the back-gate dielectric (HfO 2 ) is only 6.58 nm, which is conducive to scaling of the MoS 2 transistors.

Demonstration of a Sub-Millimeter Wave Integrated Circuit (S-MMIC) using InP HEMT with a 35-nm Gate

NASA Technical Reports Server (NTRS)

Deal, W. R.; Din, S.; Padilla, J.; Radisic, V.; Mei, G.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.; Gaier, T.;

Design of a scanning gate microscope for mesoscopic electron systems in a cryogen-free dilution refrigerator.

PubMed

Pelliccione, M; Sciambi, A; Bartel, J; Keller, A J; Goldhaber-Gordon, D

2013-03-01

We report on our design of a scanning gate microscope housed in a cryogen-free dilution refrigerator with a base temperature of 15 mK. The recent increase in efficiency of pulse tube cryocoolers has made cryogen-free systems popular in recent years. However, this new style of cryostat presents challenges for performing scanning probe measurements, mainly as a result of the vibrations introduced by the cryocooler. We demonstrate scanning with root-mean-square vibrations of 0.8 nm at 3 K and 2.1 nm at 15 mK in a 1 kHz bandwidth with our design. Using Coulomb blockade thermometry on a GaAs/AlGaAs gate-defined quantum dot, we demonstrate an electron temperature of 45 mK.

Device optimization and scaling properties of a gate-on-germanium source tunnel field-effect transistor

NASA Astrophysics Data System (ADS)

Chattopadhyay, Avik; Mallik, Abhijit; Omura, Yasuhisa

2015-06-01

A gate-on-germanium source (GoGeS) tunnel field-effect transistor (TFET) shows great promise for low-power (sub-0.5 V) applications. A detailed investigation, with the help of a numerical device simulator, on the effects of variation in different structural parameters of a GoGeS TFET on its electrical performance is reported in this paper. Structural parameters such as κ-value of the gate dielectric, length and κ-value of the spacer, and doping concentrations of both the substrate and source are considered. A low-κ symmetric spacer and a high-κ gate dielectric are found to yield better device performance. The substrate doping influences only the p-i-n leakage floor. The source doping is found to significantly affect performance parameters such as OFF-state current, ON-state current and subthreshold swing, in addition to a threshold voltage shift. Results of the investigation on the gate length scaling of such devices are also reported in this paper.

Porous Diblock Copolymer Thin Films in High-Performance Semiconductor Microelectronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, C.T.

2011-02-01

The engine fueling more than 40 years of performance improvements in semiconductor integrated circuits (ICs) has been industry's ability to pattern circuit elements at ever-higher resolution and with ever-greater precision. Steady advances in photolithography - the process wherein ultraviolet light chemically changes a photosensitive polymer resist material in order to create a latent image - have resulted in scaling of minimum printed feature sizes from tens of microns during the 1980s to sub-50 nanometer transistor gate lengths in today's state-of-the-art ICs. The history of semiconductor technology scaling as well as future technology requirements is documented in the International Technology Roadmapmore » for Semiconductors (ITRS). The progression of the semiconductor industry to the realm of nanometer-scale sizes has brought enormous challenges to device and circuit fabrication, rendering performance improvements by conventional scaling alone increasingly difficult. Most often this discussion is couched in terms of field effect transistor (FET) feature sizes such as the gate length or gate oxide thickness, however these challenges extend to many other aspects of the IC, including interconnect dimensions and pitch, device packing density, power consumption, and heat dissipation. The ITRS Technology Roadmap forecasts a difficult set of scientific and engineering challenges with no presently-known solutions. The primary focus of this chapter is the research performed at IBM on diblock copolymer films composed of polystyrene (PS) and poly(methyl-methacrylate) (PMMA) (PS-b-PMMA) with total molecular weights M{sub n} in the range of {approx}60K (g/mol) and polydispersities (PD) of {approx}1.1. These materials self assemble to form patterns having feature sizes in the range of 15-20nm. PS-b-PMMA was selected as a self-assembling patterning material due to its compatibility with the semiconductor microelectronics manufacturing infrastructure, as well as the significant body of existing research on understanding its material properties.« less

Progress in long scale length laser plasma interactions

NASA Astrophysics Data System (ADS)

Glenzer, S. H.; Arnold, P.; Bardsley, G.; Berger, R. L.; Bonanno, G.; Borger, T.; Bower, D. E.; Bowers, M.; Bryant, R.; Buckman, S.; Burkhart, S. C.; Campbell, K.; Chrisp, M. P.; Cohen, B. I.; Constantin, C.; Cooper, F.; Cox, J.; Dewald, E.; Divol, L.; Dixit, S.; Duncan, J.; Eder, D.; Edwards, J.; Erbert, G.; Felker, B.; Fornes, J.; Frieders, G.; Froula, D. H.; Gardner, S. D.; Gates, C.; Gonzalez, M.; Grace, S.; Gregori, G.; Greenwood, A.; Griffith, R.; Hall, T.; Hammel, B. A.; Haynam, C.; Heestand, G.; Henesian, M.; Hermes, G.; Hinkel, D.; Holder, J.; Holdner, F.; Holtmeier, G.; Hsing, W.; Huber, S.; James, T.; Johnson, S.; Jones, O. S.; Kalantar, D.; Kamperschroer, J. H.; Kauffman, R.; Kelleher, T.; Knight, J.; Kirkwood, R. K.; Kruer, W. L.; Labiak, W.; Landen, O. L.; Langdon, A. B.; Langer, S.; Latray, D.; Lee, A.; Lee, F. D.; Lund, D.; MacGowan, B.; Marshall, S.; McBride, J.; McCarville, T.; McGrew, L.; Mackinnon, A. J.; Mahavandi, S.; Manes, K.; Marshall, C.; Menapace, J.; Mertens, E.; Meezan, N.; Miller, G.; Montelongo, S.; Moody, J. D.; Moses, E.; Munro, D.; Murray, J.; Neumann, J.; Newton, M.; Ng, E.; Niemann, C.; Nikitin, A.; Opsahl, P.; Padilla, E.; Parham, T.; Parrish, G.; Petty, C.; Polk, M.; Powell, C.; Reinbachs, I.; Rekow, V.; Rinnert, R.; Riordan, B.; Rhodes, M.; Roberts, V.; Robey, H.; Ross, G.; Sailors, S.; Saunders, R.; Schmitt, M.; Schneider, M. B.; Shiromizu, S.; Spaeth, M.; Stephens, A.; Still, B.; Suter, L. J.; Tietbohl, G.; Tobin, M.; Tuck, J.; Van Wonterghem, B. M.; Vidal, R.; Voloshin, D.; Wallace, R.; Wegner, P.; Whitman, P.; Williams, E. A.; Williams, K.; Winward, K.; Work, K.; Young, B.; Young, P. E.; Zapata, P.; Bahr, R. E.; Seka, W.; Fernandez, J.; Montgomery, D.; Rose, H.

2004-12-01

The first experiments on the National Ignition Facility (NIF) have employed the first four beams to measure propagation and laser backscattering losses in large ignition-size plasmas. Gas-filled targets between 2 and 7 mm length have been heated from one side by overlapping the focal spots of the four beams from one quad operated at 351 nm (3ω) with a total intensity of 2 × 1015 W cm-2. The targets were filled with 1 atm of CO2 producing up to 7 mm long homogeneously heated plasmas with densities of ne = 6 × 1020 cm-3 and temperatures of Te = 2 keV. The high energy in an NIF quad of beams of 16 kJ, illuminating the target from one direction, creates unique conditions for the study of laser-plasma interactions at scale lengths not previously accessible. The propagation through the large-scale plasma was measured with a gated x-ray imager that was filtered for 3.5 keV x-rays. These data indicate that the beams interact with the full length of this ignition-scale plasma during the last ~1 ns of the experiment. During that time, the full aperture measurements of the stimulated Brillouin scattering and stimulated Raman scattering show scattering into the four focusing lenses of 3% for the smallest length (~2 mm), increasing to 10-12% for ~7 mm. These results demonstrate the NIF experimental capabilities and further provide a benchmark for three-dimensional modelling of the laser-plasma interactions at ignition-size scale lengths.

Development of InSb charge-coupled infrared imaging devices: Linear imager

NASA Technical Reports Server (NTRS)

Phillips, J. D.

1976-01-01

The following results were accomplished in the development of charge coupled infrared imaging devices: (1) a four-phase overlapping gate with 9 transfers (2-bits) and 1.0-mil gate lengths was successfully operated, (2) the measured transfer efficiency of 0.975 for this device is in excellent agreement with predictions for the reduced gate length device, (3) mask revisions of the channel stop metal on the 8582 mask have been carried out with the result being a large increase in the dc yield of the tested devices, (4) partial optical sensitivity to chopped blackbody radiation was observed for an 8582 9-bit imager, (5) analytical consideration of the modulation transfer function degradation caused by transfer inefficiency in the CCD registers was presented, and (6) for larger array lengths or for the insertion of isolated bits between sensors, improvements in InSb fabrication technology with corresponding decrease in the interface state density are required.

Anomalous annealing of floating gate errors due to heavy ion irradiation

NASA Astrophysics Data System (ADS)

Yin, Yanan; Liu, Jie; Sun, Youmei; Hou, Mingdong; Liu, Tianqi; Ye, Bing; Ji, Qinggang; Luo, Jie; Zhao, Peixiong

2018-03-01

Using the heavy ions provided by the Heavy Ion Research Facility in Lanzhou (HIRFL), the annealing of heavy-ion induced floating gate (FG) errors in 34 nm and 25 nm NAND Flash memories has been studied. The single event upset (SEU) cross section of FG and the evolution of the errors after irradiation depending on the ion linear energy transfer (LET) values, data pattern and feature size of the device are presented. Different rates of annealing for different ion LET and different pattern are observed in 34 nm and 25 nm memories. The variation of the percentage of different error patterns in 34 nm and 25 nm memories with annealing time shows that the annealing of FG errors induced by heavy-ion in memories will mainly take place in the cells directly hit under low LET ion exposure and other cells affected by heavy ions when the ion LET is higher. The influence of Multiple Cell Upsets (MCUs) on the annealing of FG errors is analyzed. MCUs with high error multiplicity which account for the majority of the errors can induce a large percentage of annealed errors.

81. AVALON DAM Photographic copy of construction drawing c1908 ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

81. AVALON DAM - Photographic copy of construction drawing c1908 (from aperture card located at Bureau of Reclamation, Salt Lake City) UNTITLED DRAWING OF AUTOMATIC FLOOD GATES. GATE DETAILS - Carlsbad Irrigation District, Avalon Dam, On Pecos River, 4 miles North of Carlsbad, Carlsbad, Eddy County, NM

Effects of dc bias on the kinetics and electrical properties of silicon dioxide grown in an electron cyclotron resonance plasma

NASA Astrophysics Data System (ADS)

Carl, D. A.; Hess, D. W.; Lieberman, M. A.; Nguyen, T. D.; Gronsky, R.

1991-09-01

Thin (3-300-nm) oxides were grown on single-crystal silicon substrates at temperatures from 523 to 673 K in a low-pressure electron cyclotron resonance (ECR) oxygen plasma. Oxides were grown under floating, anodic or cathodic bias conditions, although only the oxides grown under floating or anodic bias conditions are acceptable for use as gate dielectrics in metal-oxide-semiconductor technology. Oxide thickness uniformity as measured by ellipsometry decreased with increasing oxidation time for all bias conditions. Oxidation kinetics under anodic conditions can be explained by negatively charged atomic oxygen, O-, transport limited growth. Constant current anodizations yielded three regions of growth: (1) a concentration gradient dominated regime for oxides thinner than 10 nm, (2) a field dominated regime with ohmic charged oxidant transport for oxide thickness in the range of 10 nm to approximately 100 nm, and (3) a space-charge limited regime for films thicker than approximately 100 nm. The relationship between oxide thickness (xox), overall potential drop (Vox) and ion current (ji) in the space-charge limited transport region was of the form: ji ∝ V2ox/x3ox. Transmission electron microscopy analysis of 5-60-nm-thick anodized films indicated that the silicon-silicon dioxide interface was indistinguishable from that of thermal oxides grown at 1123 K. High-frequency capacitance-voltage (C-V) and ramped bias current-voltage (I-V) studies performed on 5.4-30-nm gate thickness capacitors indicated that the as-grown ECR films had high levels of fixed oxide charge (≳1011 cm-2) and interface traps (≳1012 cm-2 eV-1). The fixed charge level could be reduced to ≊4×1010 cm-2 by a 20 min polysilicon gate activation anneal at 1123 K in nitrogen; the interface trap density at mid-band gap decreased to ≊(1-2)×1011 cm-2 eV-1 after this process. The mean breakdown strength for anodic oxides grown under optimum conditions was 10.87±0.83 MV cm-1. Electrical properties of the 5.4-8-nm gates compared well with thicker films and control dry thermal oxides of similar thicknesses.

Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications.

PubMed

Jeon, Sanghun; Park, Sungho; Song, Ihun; Hur, Ji-Hyun; Park, Jaechul; Kim, Hojung; Kim, Sunil; Kim, Sangwook; Yin, Huaxiang; Chung, U-In; Lee, Eunha; Kim, Changjung

2011-01-01

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

MoS2 Negative-Capacitance Field-Effect Transistors with Subthreshold Swing below the Physics Limit.

PubMed

Liu, Xingqiang; Liang, Renrong; Gao, Guoyun; Pan, Caofeng; Jiang, Chunsheng; Xu, Qian; Luo, Jun; Zou, Xuming; Yang, Zhenyu; Liao, Lei; Wang, Zhong Lin

2018-05-21

The Boltzmann distribution of electrons induced fundamental barrier prevents subthreshold swing (SS) from less than 60 mV dec -1 at room temperature, leading to high energy consumption of MOSFETs. Herein, it is demonstrated that an aggressive introduction of the negative capacitance (NC) effect of ferroelectrics can decisively break the fundamental limit governed by the "Boltzmann tyranny". Such MoS 2 negative-capacitance field-effect transistors (NC-FETs) with self-aligned top-gated geometry demonstrated here pull down the SS value to 42.5 mV dec -1 , and simultaneously achieve superior performance of a transconductance of 45.5 μS μm and an on/off ratio of 4 × 10 6 with channel length less than 100 nm. Furthermore, the inserted HfO 2 layer not only realizes a stable NC gate stack structure, but also prevents the ferroelectric P(VDF-TrFE) from fatigue with robust stability. Notably, the fabricated MoS 2 NC-FETs are distinctly different from traditional MOSFETs. The on-state current increases as the temperature decreases even down to 20 K, and the SS values exhibit nonlinear dependence with temperature due to the implementation of the ferroelectric gate stack. The NC-FETs enable fundamental applications through overcoming the Boltzmann limit in nanoelectronics and open up an avenue to low-power transistors needed for many exciting long-endurance portable consumer products. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Field effect transistor with HfO2/Parylene-C bilayer hybrid gate insulator

NASA Astrophysics Data System (ADS)

Kumar, Neeraj; Kito, Ai; Inoue, Isao

2015-03-01

We have investigated the electric field control of the carrier density and the mobility at the surface of SrTiO3, a well known transition-metal oxide, in a field effect transistor (FET) geometry. We have used a Parylene-C (8 nm)/HfO2 (20 nm) double-layer gate insulator (GI), which can be a potential candidate for a solid state GI for the future Mott FETs. So far, only examples of the Mott FET used liquid electrolyte or ferroelectric oxides for the GI. However, possible electrochemical reaction at the interface causes damage to the surface of the Mott insulator. Thus, an alternative GI has been highly desired. We observed that even an ultra thin Parylene-C layer is effective for keeping the channel surface clean and free from oxygen vacancies. The 8 nm Parylene-C film has a relatively low resistance and consequentially its capacitance does not dominate the total capacitance of the Parylene-C/HfO2 GI. The breakdown gate voltage at 300 K is usually more than 10 V (~ 3.4 MV/cm). At gate voltage of 3 V the carrier density measured by the Hall effect is about 3 ×1013 cm-2, competent to cause the Mott transition. Moreover, the field effect mobility reaches in the range of 10 cm2/Vs indicating the Parylene-C passivated surface is actually very clean.

Electrical control of antiferromagnetic metal up to 15 nm

NASA Astrophysics Data System (ADS)

Zhang, PengXiang; Yin, GuFan; Wang, YuYan; Cui, Bin; Pan, Feng; Song, Cheng

2016-08-01

Manipulation of antiferromagnetic (AFM) spins by electrical means is on great demand to develop the AFM spintronics with low power consumption. Here we report a reversible electrical control of antiferromagnetic moments of FeMn up to 15 nm, using an ionic liquid to exert a substantial electric-field effect. The manipulation is demonstrated by the modulation of exchange spring in [Co/Pt]/FeMn system, where AFM moments in FeMn pin the magnetization rotation of Co/Pt. By carrier injection or extraction, the magnetic anisotropy of the top layer in FeMn is modulated to influence the whole exchange spring and then passes its influence to the [Co/Pt]/FeMn interface, through a distance up to the length of exchange spring that fully screens electric field. Comparing FeMn to IrMn, despite the opposite dependence of exchange bias on gate voltages, the same correlation between carrier density and exchange spring stiffness is demonstrated. Besides the fundamental significance of modulating the spin structures in metallic AFM via all-electrical fashion, the present finding would advance the development of low-power-consumption AFM spintronics.

Extended design window of resonant plasma-wave transistor for terahertz emitter by considering degenerate carrier velocity model with Fermi-Dirac distribution

NASA Astrophysics Data System (ADS)

Park, Jong Yul; Kim, Sung-Ho; Rok Kim, Kyung

2015-06-01

In this work, we propose extended design window which is helpful to judge whether the plasma-wave transistor (PWT) operates as a resonant terahertz (THz) electromagnetic (EM) wave emitter. When metal-oxide-semiconductor field-effect transistor (MOSFET) is on strong inversion which is believed to be an operation regime of PWT THz emitter, Boltzmann statistics is no longer valid and degenerate Fermi-Dirac distribution should be considered. Based on degenerate carrier velocity model, we report the increased maximum channel length (Lmax) to 17 nm for strained silicon (s-Si) PWT with assuming μ = 500 cm2·V-1·s-1. As mobility is enhanced, it is possible to observe two emission spectrums [fundamental (N = 1) and third (N = 3) harmonics] in a specific operation range. Theoretically, increment of Lmax for enhanced μ is limited to near 35 nm by the Pauli’s principle in the case of s-Si PWT. This theoretical value of Lmax should be compromised by considering actual PWT operation voltage for gate oxide breakdown.

Influence of hydropower dams on the composition of the suspended and riverbank sediments in the Danube.

PubMed

Klaver, Gerard; van Os, Bertil; Negrel, Philippe; Petelet-Giraud, Emmanuelle

2007-08-01

Large hydropower dams have major impacts on flow regime, sediment transport and the characteristics of water and sediment in downstream rivers. The Gabcikovo and Iron Gate dams divide the studied Danube transect (rkm 1895-795) into three parts. In the Gabcikovo Reservoir (length of 40km) only a part of the incoming suspended sediments were deposited. Contrary to this, in the much larger Iron Gate backwater zone and reservoir (length of 310km) all riverine suspended sediments were deposited within the reservoir. Subsequently, suspended sediments were transported by tributaries into the Iron Gate backwater zone. Here they were modified by fractional sedimentation before they transgressed downstream via the dams. Compared with undammed Danube sections, Iron Gate reservoir sediment and suspended matter showed higher clay contents and different K/Ga and Metal/Ga ratios. These findings emphasize the importance of reservoir-river sediment-fractionation.

The prospects of transition metal dichalcogenides for ultimately scaled CMOS

NASA Astrophysics Data System (ADS)

Thiele, S.; Kinberger, W.; Granzner, R.; Fiori, G.; Schwierz, F.

2018-05-01

MOSFET gate length scaling has been a main source of progress in digital electronics for decades. Today, researchers still spend considerable efforts on reducing the gate length and on developing ultimately scaled MOSFETs, thereby exploring both new device architectures and alternative channel materials beyond Silicon such as two-dimensional TMDs (transition metal dichalcogenide). On the other hand, the envisaged scaling scenario for the next 15 years has undergone a significant change recently. While the 2013 ITRS edition required a continuation of aggressive gate length scaling for at least another 15 years, the 2015 edition of the ITRS suggests a deceleration and eventually a levelling off of gate length scaling and puts more emphasis on alternative options such as pitch scaling to keep Moore's Law alive. In the present paper, future CMOS scaling is discussed in the light of emerging two-dimensional MOSFET channel, in particular two-dimensional TMDs. To this end, the scaling scenarios of the 2013 and 2015 ITRS editions are considered and the scaling potential of TMD MOSFETs is investigated by means of quantum-mechanical device simulations. It is shown that for ultimately scaled MOSFETs as required in the 2013 ITRS, the heavy carrier effective masses of the Mo- and W-based TMDs are beneficial for the suppression of direct source-drain tunneling, while to meet the significantly relaxed scaling targets of the 2016 ITRS heavy-effective-mass channels are not needed.

Planarized thick copper gate polycrystalline silicon thin film transistors for ultra-large AMOLED displays

NASA Astrophysics Data System (ADS)

Yun, Seung Jae; Lee, Yong Woo; Son, Se Wan; Byun, Chang Woo; Reddy, A. Mallikarjuna; Joo, Seung Ki

2012-08-01

A planarized thick copper (Cu) gate low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) is fabricated for ultra-large active-matrix organic light-emitting diode (AMOLED) displays. We introduce a damascene and chemical mechanical polishing process to embed a planarized Cu gate of 500 nm thickness into a trench and Si3N4/SiO2 multilayer gate insulator, to prevent the Cu gate from diffusing into the silicon (Si) layer at 550°C, and metal-induced lateral crystallization (MILC) technology to crystallize the amorphous Si layer. A poly-Si TFT with planarized thick Cu gate exhibits a field effect mobility of 5 cm2/Vs and a threshold voltage of -9 V, and a subthreshold swing (S) of 1.4 V/dec.

Stand-off detection of explosives vapors by resonance-enhanced Raman spectroscopy

NASA Astrophysics Data System (ADS)

Johansson, Ida; Ceco, Ema; Ehlerding, Anneli; Östmark, Henric

2013-06-01

This paper describes a system for stand-off vapor detection based on Resonant Raman spectroscopy, RRS. The system is a step towards a RRS LIDAR (Light Detection And Ranging) system, capable of detecting vapors from explosives and explosives precursors at long distances. The current system was used to detect the vapor of nitromethane and mononitrotoluene outdoors in the open air, at a stand-off distance of 11-13 meters. Also, the signal dependence upon irradiation wavelength and sample concentration was studied in controlled laboratory conditions. A tunable Optical Parametric Oscillator pumped by an Nd:YAG laser, with a pulse length of 6 ns, was operated in the UV range of interest, 210-400 nm, illuminating the sample vapor. The backscattered Raman signal was collected by a telescope and a roundto- slit optical fiber was used to transmit collected light to the spectrometer with minimum losses. A gated intensified charge-coupled device (ICCD) registered the spectra. The nitromethane cross section was resonance enhanced more than a factor 30 700, when measured at 220 nm, compared to the 532 nm value. The results show that a decrease in concentration can have a positive effect on the sensitivity of the system, due to a decrease in absorption and selfabsorption in the sample.

Boundary-based cellwise OPC for standard-cell layouts

NASA Astrophysics Data System (ADS)

Pawlowski, David M.; Deng, Liang; Wong, Martin D. F.

2007-03-01

Model based optical proximity correction (OPC) has become necessary at 90nm technology node. Cellwise OPC is an attractive technique to reduce the mask data size as well as the prohibitive runtime of full-chip OPC. As feature dimensions have gotten smaller, the radius of influence for edge features has extended further into neighboring cells such that it is no longer sufficient to perform cellwise OPC independent of neighboring cells, especially for the critical layers. The methodology described in this work accounts for features in neighboring cells and allows a cellwise approach to be applied to cells with a printed gate length of 45nm with the projection that it can also be applied to future technology nodes. OPC-ready cells are generated at library creation (independent of placement) using a boundary-based technique. Each cell has a tractable number of OPC-ready versions due to an intelligent characterization of standard cell layout features. Results are very promising: the average edge placement error (EPE) for all metal1 features in 100 layouts is 0.731nm which is less than 1% of metal1 width; the maximum EPE for poly features reduced to 1/3, compared to cellwise OPC without considering boundaries, creating similar levels of lithographic accuracy while obviating any of the drawbacks inherent in layout specific full-chip model-based OPC.

Smart Adsorbents with Photoregulated Molecular Gates for Both Selective Adsorption and Efficient Regeneration.

PubMed

Cheng, Lei; Jiang, Yao; Yan, Ni; Shan, Shu-Feng; Liu, Xiao-Qin; Sun, Lin-Bing

2016-09-07

Selective adsorption and efficient regeneration are two crucial issues for adsorption processes; unfortunately, only one of them instead of both is favored by traditional adsorbents with fixed pore orifices. Herein, we fabricated a new generation of smart adsorbents through grafting photoresponsive molecules, namely, 4-(3-triethoxysilylpropyl-ureido)azobenzene (AB-TPI), onto pore orifices of the support mesoporous silica. The azobenzene (AB) derivatives serve as the molecular gates of mesopores and are reversibly opened and closed upon light irradiation. Irradiation with visible light (450 nm) causes AB molecules to isomerize from cis to trans configuration, and the molecular gates are closed. It is easy for smaller adsorbates to enter while difficult for the larger ones, and the selective adsorption is consequently facilitated. Upon irradiation with UV light (365 nm), the AB molecules are transformed from trans to cis isomers, promoting the desorption of adsorbates due to the opened molecular gates. The present smart adsorbents can consequently benefit not only selective adsorption but also efficient desorption, which are exceedingly desirable for adsorptive separation but impossible for traditional adsorbents with fixed pore orifices.

Electrical characteristic fluctuation of 16-nm-gate high-κ/metal gate bulk FinFET devices in the presence of random interface traps

NASA Astrophysics Data System (ADS)

Hsu, Sheng-Chia; Li, Yiming

2014-11-01

In this work, we study the impact of random interface traps (RITs) at the interface of SiO x /Si on the electrical characteristic of 16-nm-gate high-κ/metal gate (HKMG) bulk fin-type field effect transistor (FinFET) devices. Under the same threshold voltage, the effects of RIT position and number on the degradation of electrical characteristics are clarified with respect to different levels of RIT density of state ( D it). The variability of the off-state current ( I off) and drain-induced barrier lowering (DIBL) will be severely affected by RITs with high D it varying from 5 × 1012 to 5 × 1013 eV-1 cm-2 owing to significant threshold voltage ( V th) fluctuation. The results of this study indicate that if the level of D it is lower than 1 × 1012 eV-1 cm-2, the normalized variability of the on-state current, I off, V th, DIBL, and subthreshold swing is within 5%.

Dry dock gate stability modelling

NASA Astrophysics Data System (ADS)

Oktoberty; Widiyanto; Sasono, E. J.; Pramono, S.; Wandono, A. T.

2018-03-01

The development of marine transportation needs in Indonesia increasingly opens national shipyard business opportunities to provide shipbuilding services to the shipbuilding vessels. That emphasizes the stability of prime. The ship's decking door becomes an integral part of the efficient place and the specification of the use of the asset of its operational ease. This study aims to test the stability of Dry Dock gate with the length of 35.4 meters using Maxsurf and Hydromax in analyzing the calculation were in its assessment using interval per 500 mm length so that it can get detail data toward longitudinal and transverse such as studying Ship planning in general. The test result shows dry dock gate meets IMO standard with ballast construction containing 54% and 68% and using fix ballast can produce GMt 1,924 m, tide height 11,357m. The GMt value indicates dry dick gate can be stable and firmly erect at the base of the mouth dry dock. When empty ballast produces GMt 0.996 which means dry dock date is stable, but can easily be torn down. The condition can be used during dry dock gate treatment.

Electro-optical logic gates based on graphene-silicon waveguides

NASA Astrophysics Data System (ADS)

Chen, Weiwei; Yang, Longzhi; Wang, Pengjun; Zhang, Yawei; Zhou, Liqiang; Yang, Tianjun; Wang, Yang; Yang, Jianyi

2016-08-01

In this paper, designs of electro-optical AND/NAND, OR/ NOR, XOR/XNOR logic gates based on cascaded silicon graphene switches and regular 2×1 multimode interference combiners are presented. Each switch consists of a Mach-Zehnder interferometer in which silicon slot waveguides embedded with graphene flakes are designed for phase shifters. High-speed switching function is achieved by applying an electrical signal to tune the Fermi levels of graphene flakes causing the variation of modal effective index. Calculation results show the crosstalk in the proposed optical switch is lower than -22.9 dB within a bandwidth from 1510 nm to 1600 nm. The designed six electro-optical logic gates with the operation speed of 10 Gbit/s have a minimum extinction ratio of 35.6 dB and a maximum insertion loss of 0.21 dB for transverse electric modes at 1.55 μm.

Large electron concentration modulation using capacitance enhancement in SrTiO{sub 3}/SmTiO{sub 3} Fin-field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Verma, Amit, E-mail: averma@cornell.edu; Nomoto, Kazuki; School of Electrical and Computer Engineering, Cornell University, Ithaca, New York 14853

2016-05-02

Solid-state modulation of 2-dimensional electron gases (2DEGs) with extreme (∼3.3 × 10{sup 14 }cm{sup −2}) densities corresponding to 1/2 electron per interface unit cell at complex oxide heterointerfaces (such as SrTiO{sub 3}/GdTiO{sub 3} or SrTiO{sub 3}/SmTiO{sub 3}) is challenging because it requires enormous gate capacitances. One way to achieve large gate capacitances is by geometrical capacitance enhancement in fin structures. In this work, we fabricate both Au-gated planar field effect transistors (FETs) and Fin-FETs with varying fin-widths on 60 nm SrTiO{sub 3}/5 nm SmTiO{sub 3} thin films grown by hybrid molecular beam epitaxy. We find that the FinFETs exhibit higher gate capacitance comparedmore » to planar FETs. By scaling down the SrTiO{sub 3}/SmTiO{sub 3} fin widths, we demonstrate further gate capacitance enhancement, almost twice compared to the planar FETs. In the FinFETs with narrowest fin-widths, we demonstrate a record 2DEG electron concentration modulation of ∼2.4 × 10{sup 14 }cm{sup −2}.« less

Electro-optical graphene plasmonic logic gates.

PubMed

Ooi, Kelvin J A; Chu, Hong Son; Bai, Ping; Ang, Lay Kee

2014-03-15

The versatile control of graphene's plasmonic modes via an external gate-voltage inspires us to design efficient electro-optical graphene plasmonic logic gates at the midinfrared wavelengths. We show that these devices are superior to the conventional optical logic gates because the former possess cut-off states and interferometric effects. Moreover, the designed six basic logic gates (i.e., NOR/AND, NAND/OR, XNOR/XOR) achieved not only ultracompact size lengths of less than λ/28 with respect to the operating wavelength of 10 μm, but also a minimum extinction ratio as high as 15 dB. These graphene plasmonic logic gates are potential building blocks for future nanoscale midinfrared photonic integrated circuits.

A MODFET dc model with improved pinchoff and saturation characteristics

NASA Astrophysics Data System (ADS)

Rohdin, Hans; Roblin, Patrick

1986-05-01

An improved analytical dc model for the MODFET is proposed which uses a new approximation of the two-dimensional electron gas concentration versus gate-to-channel voltage, a ratio which models both the subthreshold region and the gradual saturation of carriers due to the onset of AlGaAs charge modulation. A two-region Grebene-Ghandi model with a floating boundary is used for the channel. A maximum transconductance and a finite intrinsic output conductance in the saturated region are predicted, in agreement with experimental observations. The model is shown to approach the saturated velocity model in the limit of very short gate lengths, and to approach the classical gradual channel model in the limit of very long gate lengths.

Top-gate pentacene-based organic field-effect transistor with amorphous rubrene gate insulator

NASA Astrophysics Data System (ADS)

Hiroki, Mizuha; Maeda, Yasutaka; Ohmi, Shun-ichiro

2018-02-01

The scaling of organic field-effect transistors (OFETs) is necessary for high-density integration and for this, OFETs with a top-gate configuration are required. There have been several reports of damageless lithography processes for organic semiconductor or insulator layers. However, it is still difficult to fabricate scaled OFETs with a top-gate configuration. In this study, the lift-off process and the device characteristics of the OFETs with a top-gate configuration utilizing an amorphous (α) rubrene gate insulator were investigated. We have confirmed that α-rubrene shows an insulating property, and its extracted linear mobility was 2.5 × 10-2 cm2/(V·s). The gate length and width were 10 and 60 µm, respectively. From these results, the OFET with a top-gate configuration utilizing an α-rubrene gate insulator is promising for the high-density integration of scaled OFETs.

Observation of ambipolar switching in a silver nanoparticle single-electron transistor with multiple molecular floating gates

NASA Astrophysics Data System (ADS)

Yamamoto, Makoto; Shinohara, Shuhei; Tamada, Kaoru; Ishii, Hisao; Noguchi, Yutaka

2016-03-01

Ambipolar switching behavior was observed in a silver nanoparticle (AgNP)-based single-electron transistor (SET) with tetra-tert-butyl copper phthalocyanine (ttbCuPc) as a molecular floating gate. Depending on the wavelength of the incident light, the stability diagram shifted to the negative and positive directions along the gate voltage axis. These results were explained by the photoinduced charging of ttbCuPc molecules in the vicinity of AgNPs. Moreover, multiple device states were induced by the light irradiation at a wavelength of 600 nm, suggesting that multiple ttbCuPc molecules individually worked as a floating gate.

Photo-electronic current transport in back-gated graphene transistor

NASA Astrophysics Data System (ADS)

Srivastava, Ashok; Chen, Xinlu; Pradhan, Aswini K.

2017-04-01

In this work, we have studied photo-electronic current transport in a back-gated graphene field-effect transistor. Under the light illumination, band bending at the metal/graphene interface develops a built-in potential which generates photonic current at varying back-gate biases. A typical MOSFET type back-gated transistor structure uses a monolayer graphene as the channel layer formed over the silicon dioxide/silicon substrate. It is shown that the photo-electronic current consists of current contributions from photovoltaic, photo-thermoelectric and photo-bolometric effects. A maximum external responsivity close to 0.0009A/W is achieved at 30μW laser power source and 633nm wavelength.

Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

NASA Astrophysics Data System (ADS)

Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

2018-04-01

In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

Electro-optic modulator based gate transient suppression for sine-wave gated InGaAs/InP single photon avalanche photodiode

NASA Astrophysics Data System (ADS)

Zhang, Yixin; Zhang, Xuping; Shi, Yuanlei; Ying, Zhoufeng; Wang, Shun

2014-06-01

Capacitive gate transient noise has been problematic for the high-speed single photon avalanche photodiode (SPAD), especially when the operating frequency extends to the gigahertz level. We proposed an electro-optic modulator based gate transient noise suppression method for sine-wave gated InGaAs/InP SPAD. With the modulator, gate transient is up-converted to its higher-order harmonics that can be easily removed by low pass filtering. The proposed method enables online tuning of the operating rate without modification of the hardware setup. At 250 K, detection efficiency of 14.7% was obtained with 4.8×10-6 per gate dark count and 3.6% after-pulse probabilities for 1550-nm optical signal under 1-GHz gating frequency. Experimental results have shown that the performance of the detector can be maintained within a designated frequency range from 0.97 to 1.03 GHz, which is quite suitable for practical high-speed SPAD applications operated around the gigahertz level.

High fluence swift heavy ion structure modification of the SiO2/Si interface and gate insulator in 65 nm MOSFETs

NASA Astrophysics Data System (ADS)

Ma, Yao; Gao, Bo; Gong, Min; Willis, Maureen; Yang, Zhimei; Guan, Mingyue; Li, Yun

2017-04-01

In this work, a study of the structure modification, induced by high fluence swift heavy ion radiation, of the SiO2/Si structures and gate oxide interface in commercial 65 nm MOSFETs is performed. A key and novel point in this study is the specific use of the transmission electron microscopy (TEM) technique instead of the conventional atomic force microscope (AFM) or scanning electron microscope (SEM) techniques which are typically performed following the chemical etching of the sample to observe the changes in the structure. Using this method we show that after radiation, the appearance of a clearly visible thin layer between the SiO2 and Si is observed presenting as a variation in the TEM intensity at the interface of the two materials. Through measuring the EDX line scans we reveal that the Si:O ratio changed and that this change can be attributed to the migration of the Si towards interface after the Si-O bond is destroyed by the swift heavy ions. For the 65 nm MOSFET sample, the silicon substrate, the SiON insulator and the poly-silicon gate interfaces become blurred under the same irradiation conditions.

Fabrication of Ta2O5/GeNx gate insulator stack for Ge metal-insulator-semiconductor structures by electron-cyclotron-resonance plasma nitridation and sputtering deposition techniques

NASA Astrophysics Data System (ADS)

Otani, Yohei; Itayama, Yasuhiro; Tanaka, Takuo; Fukuda, Yukio; Toyota, Hiroshi; Ono, Toshiro; Mitsui, Minoru; Nakagawa, Kiyokazu

2007-04-01

The authors have fabricated germanium (Ge) metal-insulator-semiconductor (MIS) structures with a 7-nm-thick tantalum pentaoxide (Ta2O5)/2-nm-thick germanium nitride (GeNx) gate insulator stack by electron-cyclotron-resonance plasma nitridation and sputtering deposition. They found that pure GeNx ultrathin layers can be formed by the direct plasma nitridation of the Ge surface without substrate heating. X-ray photoelectron spectroscopy revealed no oxidation of the GeNx layer after the Ta2O5 sputtering deposition. The fabricated MIS capacitor with a capacitance equivalent thickness of 4.3nm showed excellent leakage current characteristics. The interface trap density obtained by the modified conductance method was 4×1011cm-2eV-1 at the midgap.

88. AVALON DAM Photographic copy of construction drawing dated ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

88. AVALON DAM - Photographic copy of construction drawing dated February 9, 1912 (from Record Group 115, Box 17, Denver Branch of the National Archives, Denver) METHOD OF CLOSING UP OLD GATE OPENINGS IN SPILLWAY AND ARRANGEMENT OF TURBINES, OPERATING CYLINDER GATES - Carlsbad Irrigation District, Avalon Dam, On Pecos River, 4 miles North of Carlsbad, Carlsbad, Eddy County, NM

Two stage dual gate MESFET monolithic gain control amplifier for Ka-band

NASA Technical Reports Server (NTRS)

Sokolov, V.; Geddes, J.; Contolatis, A.

1987-01-01

A monolithic two stage gain control amplifier has been developed using submicron gate length dual gate MESFETs fabricated on ion implanted material. The amplifier has a gain of 12 dB at 30 GHz with a gain control range of over 30 dB. This ion implanted monolithic IC is readily integrable with other phased array receiver functions such as low noise amplifiers and phase shifters.

Optical DC overlay measurement in the 2nd level process of 65 nm alternating phase shift mask

NASA Astrophysics Data System (ADS)

Ma, Jian; Han, Ke; Lee, Kyung; Korobko, Yulia; Silva, Mary; Chavez, Joas; Irvine, Brian; Henrichs, Sven; Chakravorty, Kishore; Olshausen, Robert; Chandramouli, Mahesh; Mammen, Bobby; Padmanaban, Ramaswamy

2005-11-01

Alternating phase shift mask (APSM) techniques help bridge the significant gap between the lithography wavelength and the patterning of minimum features, specifically, the poly line of 35 nm gate length (1x) in Intel's 65 nm technology. One of key steps in making APSM mask is to pattern to within the design tolerances the 2nd level resist so that the zero-phase apertures will be protected by the resist and the pi-phase apertures will be wide open for quartz etch. The ability to align the 2nd level to the 1st level binary pattern, i.e. the 2nd level overlay capability is very important, so is the capability of measuring the overlay accurately. Poor overlay could cause so-called the encroachment after quartz etch, producing undesired quartz bumps in the pi-apertures or quartz pits in the zero-apertures. In this paper, a simple, low-cost optical setup for the 2nd level DC (develop check) overlay measurements in the high volume manufacturing (HVM) of APSM masks is presented. By removing systematic errors in overlay associated with TIS and MIS (tool-induced shift and Mask-process induced shift), it is shown that this setup is capable of supporting the measurement of DC overlay with a tolerance as small as +/- 25 nm. The outstanding issues, such as DC overlay error component analysis, DC - FC (final check) overlay correlation and the overlay linearity (periphery vs. indie), are discussed.

Giant Faraday Rotation of High-Order Plasmonic Modes in Graphene-Covered Nanowires.

PubMed

Kuzmin, Dmitry A; Bychkov, Igor V; Shavrov, Vladimir G; Temnov, Vasily V

2016-07-13

Plasmonic Faraday rotation in nanowires manifests itself in the rotation of the spatial intensity distribution of high-order surface plasmon polariton (SPP) modes around the nanowire axis. Here we predict theoretically the giant Faraday rotation for SPPs propagating on graphene-coated magneto-optically active nanowires. Upon the reversal of the external magnetic field pointing along the nanowire axis some high-order plasmonic modes may be rotated by up to ∼100° on the length scale of about 500 nm at mid-infrared frequencies. Tuning the carrier concentration in graphene by chemical doping or gate voltage allows for controlling SPP-properties and notably the rotation angle of high-order azimuthal modes. Our results open the door to novel plasmonic applications ranging from nanowire-based Faraday isolators to the magnetic control in quantum-optical applications.

Vacuum field-effect transistor with a deep submicron channel fabricated by electro-forming

NASA Astrophysics Data System (ADS)

Wang, Xiao; Shen, Zhihua; Wu, Shengli; Zhang, Jintao

2017-06-01

Vacuum field-effect transistors (VFETs) with channel lengths down to 500 nm (i.e., the deep submicron scale) were fabricated with the mature technology of the surface conduction electron emitter fabrication process in our former experiments. The vacuum channel of this new VFET was generated by using the electro-forming process. During electro-forming, the joule heat cracks the conductive film and then generates the submicron scale gap that serves as the vacuum channel. The gap separates the conductive film into two plane-to-plane electrodes, which serve as a source (cathode) electrode and a drain (anode) electrode of the VFET, respectively. Experimental results reveal that the fabricated device demonstrates a clear triode behavior of the gate modulation. Fowler-Nordheim theory was used to analyze the electron emission mechanism and operating principle of the device.

Temperature dependence of ballistic mobility in a metamorphic InGaAs/InAlAs high electron mobility transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Jongkyong; Gang, Suhyun; Jo, Yongcheol

We have investigated the temperature dependence of ballistic mobility in a 100 nm-long InGaAs/InAlAs metamorphic high-electron-mobility transistor designed for millimeter-wavelength RF applications. To extract the temperature dependence of quasi-ballistic mobility, our experiment involves measurements of the effective mobility in the low-bias linear region of the transistor and of the collision-dominated Hall mobility using a gated Hall bar of the same epitaxial structure. The data measured from the experiment are consistent with that of modeled ballistic mobility based on ballistic transport theory. These results advance the understanding of ballistic transport in various transistors with a nano-scale channel length that is comparable tomore » the carrier's mean free path in the channel.« less

Towards a portable Raman spectrometer using a concave grating and a time-gated CMOS SPAD.

PubMed

Li, Zhiyun; Deen, M Jamal

2014-07-28

A low-cost, compact Raman spectrometer suitable for the on-line water monitoring applications is explored. A custom-designed concave grating for wavelength selection was fabricated and tested. The detection of the Raman signal is accomplished with a time-gated single photon avalanche diode (TG-SPAD). A fixed gate window of 3.5ns is designed and applied to the TG-SPAD. The temporal resolution of the SPAD was ~60ps when tested with a 7ps, 532nm solid-state laser. To test the efficiency of the gating in fluorescence signal suppression, different detection windows (3ns-0.25ns) within the 3.5ns gate window are used to measure the Raman spectra of Rhodamine B. Strong Raman peaks are resolved with this low-cost system.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-01

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

PubMed

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-17

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Pulse oximeter using a gain-modulated avalanche photodiode operated in a pseudo lock-in light detection mode

NASA Astrophysics Data System (ADS)

Miyata, Tsuyoshi; Iwata, Tetsuo; Araki, Tsutomu

2006-01-01

We propose a reflection-type pulse oximeter, which employs two pairs of a light-emitting diode (LED) and a gated avalanche photodiode (APD). One LED is a red one with an emission wavelength λ = 635 nm and the other is a near-infrared one with that λ = 945 nm, which are both driven with a pulse mode at a frequency f (=10 kHz). Superposition of a transistor-transistor-logic (TTL) gate pulse on a direct-current (dc) bias, which is set so as not exceeding the breakdown voltage of each APD, makes the APD work in a gain-enhanced operation mode. Each APD is gated at a frequency 2f (=20 kHz) and its output signal is fed into a laboratory-made lock-in amplifier that works in synchronous with the pulse modulation signal of each LED at a frequency f (=10 kHz). A combination of the gated APD and the lock-in like signal detection scheme is useful for the reflection-type pulse oximeter thanks to the capability of detecting a weak signal against a large background (BG) light.

Helical prospective ECG-gating in cardiac computed tomography: radiation dose and image quality.

PubMed

DeFrance, Tony; Dubois, Eric; Gebow, Dan; Ramirez, Alex; Wolf, Florian; Feuchtner, Gudrun M

2010-01-01

Helical prospective ECG-gating (pECG) may reduce radiation dose while maintaining the advantages of helical image acquisition for coronary computed tomography angiography (CCTA). Aim of this study was to evaluate helical pECG-gating in CCTA in regards to radiation dose and image quality. 86 patients undergoing 64-multislice CCTA were enrolled. pECG-gating was performed in patients with regular heart rates (HR) < 65 bpm; with the gating window set at 70-85% of the cardiac cycle. All patients received oral and some received additional IV beta-blockers to achieve HR < 65 bpm. In patients with higher or irregular HR, or for functional evaluation, retrospective ECG-gating (rECG) was performed. The average X-ray dose was estimated from the dose length product. Each arterial segment (modified AHA/ACC 17-segment-model) was evaluated on a 4-point image quality scale (4 = excellent; 3 = good, mild artefact; 2 = acceptable, some artefact, 1 = uninterpretable). pECG-gating was applied in 57 patients, rECG-gating in 29 patients. There was no difference in age, gender, body mass index, scan length or tube output settings between both groups. HR in the pECG-group was 54.7 bpm (range, 43-64). The effective radiation dose was significantly lower for patients scanned with pECG-gating with mean 6.9 mSv +/- 1.9 (range, 2.9-10.7) compared to rECG with 16.9 mSv +/- 4.1 (P < 0.001), resulting in a mean dose reduction of 59.2%. For pECG-gating, out of 969 coronary segments, 99.3% were interpretable. Image quality was excellent in 90.2%, good in 7.8%, acceptable in 1.3% and non-interpretable in 0.7% (n = 7 segments). For patients with steady heart rates <65 bpm, helical prospective ECG-gating can significantly lower the radiation dose while maintaining high image quality.

Photon-triggered nanowire transistors

NASA Astrophysics Data System (ADS)

Kim, Jungkil; Lee, Hoo-Cheol; Kim, Kyoung-Ho; Hwang, Min-Soo; Park, Jin-Sung; Lee, Jung Min; So, Jae-Pil; Choi, Jae-Hyuck; Kwon, Soon-Hong; Barrelet, Carl J.; Park, Hong-Gyu

2017-10-01

Photon-triggered electronic circuits have been a long-standing goal of photonics. Recent demonstrations include either all-optical transistors in which photons control other photons or phototransistors with the gate response tuned or enhanced by photons. However, only a few studies report on devices in which electronic currents are optically switched and amplified without an electrical gate. Here we show photon-triggered nanowire (NW) transistors, photon-triggered NW logic gates and a single NW photodetection system. NWs are synthesized with long crystalline silicon (CSi) segments connected by short porous silicon (PSi) segments. In a fabricated device, the electrical contacts on both ends of the NW are connected to a single PSi segment in the middle. Exposing the PSi segment to light triggers a current in the NW with a high on/off ratio of >8 × 106. A device that contains two PSi segments along the NW can be triggered using two independent optical input signals. Using localized pump lasers, we demonstrate photon-triggered logic gates including AND, OR and NAND gates. A photon-triggered NW transistor of diameter 25 nm with a single 100 nm PSi segment requires less than 300 pW of power. Furthermore, we take advantage of the high photosensitivity and fabricate a submicrometre-resolution photodetection system. Photon-triggered transistors offer a new venue towards multifunctional device applications such as programmable logic elements and ultrasensitive photodetectors.

Photon-triggered nanowire transistors.

PubMed

Kim, Jungkil; Lee, Hoo-Cheol; Kim, Kyoung-Ho; Hwang, Min-Soo; Park, Jin-Sung; Lee, Jung Min; So, Jae-Pil; Choi, Jae-Hyuck; Kwon, Soon-Hong; Barrelet, Carl J; Park, Hong-Gyu

2017-10-01

Photon-triggered electronic circuits have been a long-standing goal of photonics. Recent demonstrations include either all-optical transistors in which photons control other photons or phototransistors with the gate response tuned or enhanced by photons. However, only a few studies report on devices in which electronic currents are optically switched and amplified without an electrical gate. Here we show photon-triggered nanowire (NW) transistors, photon-triggered NW logic gates and a single NW photodetection system. NWs are synthesized with long crystalline silicon (CSi) segments connected by short porous silicon (PSi) segments. In a fabricated device, the electrical contacts on both ends of the NW are connected to a single PSi segment in the middle. Exposing the PSi segment to light triggers a current in the NW with a high on/off ratio of >8 × 10 6 . A device that contains two PSi segments along the NW can be triggered using two independent optical input signals. Using localized pump lasers, we demonstrate photon-triggered logic gates including AND, OR and NAND gates. A photon-triggered NW transistor of diameter 25 nm with a single 100 nm PSi segment requires less than 300 pW of power. Furthermore, we take advantage of the high photosensitivity and fabricate a submicrometre-resolution photodetection system. Photon-triggered transistors offer a new venue towards multifunctional device applications such as programmable logic elements and ultrasensitive photodetectors.

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

PubMed

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

3-D Observation of dopant distribution at NAND flash memory floating gate using Atom probe tomography

NASA Astrophysics Data System (ADS)

Lee, Ji-hyun; Chae, Byeong-Kyu; Kim, Joong-Jeong; Lee, Sun Young; Park, Chan Gyung

2015-01-01

Dopant control becomes more difficult and critical as silicon devices become smaller. We observed the dopant distribution in a thermally annealed polysilicon gate using Transmission Electron Microscopy (TEM) and Atom probe tomography (APT). Phosphorus was doped at the silicon-nitride-diffusion-barrier-layer-covered polycrystalline silicon gate. Carbon also incorporated at the gate for the enhancement of operation uniformity. The impurity distribution was observed using atom probe tomography. The carbon atoms had segregated at grain boundaries and suppressed silicon grain growth. Phosphorus atoms, on the other hand, tended to pile-up at the interface. A 1-nm-thick diffusion barrier effectively blocked P atom out-diffusion. [Figure not available: see fulltext.

Photo-induced persistent inversion of germanium in a 200-nm-deep surface region.

PubMed

Prokscha, T; Chow, K H; Stilp, E; Suter, A; Luetkens, H; Morenzoni, E; Nieuwenhuys, G J; Salman, Z; Scheuermann, R

2013-01-01

The controlled manipulation of the charge carrier concentration in nanometer thin layers is the basis of current semiconductor technology and of fundamental importance for device applications. Here we show that it is possible to induce a persistent inversion from n- to p-type in a 200-nm-thick surface layer of a germanium wafer by illumination with white and blue light. We induce the inversion with a half-life of ~12 hours at a temperature of 220 K which disappears above 280 K. The photo-induced inversion is absent for a sample with a 20-nm-thick gold capping layer providing a Schottky barrier at the interface. This indicates that charge accumulation at the surface is essential to explain the observed inversion. The contactless change of carrier concentration is potentially interesting for device applications in opto-electronics where the gate electrode and gate oxide could be replaced by the semiconductor surface.

Effect of strained Ge-based NMOSFETs with Ge0.93Si0.07 stressors on device layout

NASA Astrophysics Data System (ADS)

Hsu, Hung-Wen; Lee, Chang-Chun

2017-12-01

This research proposes a germanium (Ge)-based n-channel MOSFET with Ge0.93Si0.07 S/D stressor. A simulation technique is utilized to understand the layout effect of shallow trench isolation (STI) length, gate width, dummy active of diffusion (OD) length, and extended poly width on stress distribution in a channel region. Stress distribution in a channel region was simulated by ANSYS software based on finite element analysis. Furthermore, carrier mobility gain was evaluated by a second-order piezoresistance model. The piezoresistance coefficient of Ge nMOSFET varies from that of Si nMOSFET. The piezoresistance coefficient shows that longitudinal and transverse stresses are the dominant factors affecting the change in electron mobility in the channel region. For Ge-based nMOSFET, longitudinal stress tends to be tensile, whereas transverse stress tends to be compressive. Stress along channel length becomes more tensile when STI length decreases. By contrast, stress along the channel width becomes more compressive when gate width or extended poly width decreases. Electron mobility in Ge-based nMOSFET could be enhanced under the aforementioned conditions. The enhanced electron mobility becomes more significant as the device combines with a contact etching stop layer stressor. Moreover, the mobility can be improved by changing the STI length, gate width, dummy OD length, or extended poly width. This investigation systematically analyzed the relationship between layout factor and stress distribution.

III-V HEMTs: low-noise devices for high-frequency applications

NASA Astrophysics Data System (ADS)

Mateos, Javier

2003-05-01

With the recent development of broadband and satellite communications, one of the main engines for the advance of modern Microelectronics is the fabrication of devices with increasing cutoff frequency and lowest possible level of noise. Even if heterojunction bipolar devices (HBTs) have reached a good frequency performance, the top end of high frequency low-noise applications is monopolized by unipolar devices, mainly HEMTs (High Electron Mobility Transistors). In particular, within the vast family of heterojunction devices, the best results ever reported in the W-band have been obtained with InP based HEMTs using the AlInAs/InGaAs material system, improving those of usual GaAs based pseudomorphic HEMTs. In field effect devices, the reduction of the gate length (Lg) up to the technological limit is the main way to achieve the maximum performances. But the design of the devices is not so simple, when reducing the gate length it is convenient to keep constant the aspect ratio (gate length over gate-to-channel distance) in order to limit short channel effects. This operation can lead to the appearance of other unwanted effects, like the depletion of the channel due to the surface potential or the tunneling of electrons from the channel to the gate. Therefore, in order to optimize the high frequency or the low-noise behavior of the devices (that usually can not be reached together) not only the gate-to-channel distance must be chosen carefully, but also many other technological parameters (both geometrical and electrical): composition of materials, width of the device, length, depth and position of the recess, thickness and doping of the different layers, etc. Historically, these parameters have been optimized by classical simulation techniques or, when such simulations are not physically applicable, by the expensive 'test and error' procedure. With the use of computer simulation, the design optimization can be made in a short time and with no money spent. However, classical modelling of electronic devices meets important difficulties when dealing with advanced transistors, mainly due to their small size, and the Monte Carlo technique appears as the only possible choice

Ion transport by gating voltage to nanopores produced via metal-assisted chemical etching method

NASA Astrophysics Data System (ADS)

Van Toan, Nguyen; Inomata, Naoki; Toda, Masaya; Ono, Takahito

2018-05-01

In this work, we report a simple and low-cost way to create nanopores that can be employed for various applications in nanofluidics. Nano sized Ag particles in the range from 1 to 20 nm are formed on a silicon substrate with a de-wetting method. Then the silicon nanopores with an approximate 15 nm average diameter and 200 μm height are successfully produced by the metal-assisted chemical etching method. In addition, electrically driven ion transport in the nanopores is demonstrated for nanofluidic applications. Ion transport through the nanopores is observed and could be controlled by an application of a gating voltage to the nanopores.

Two-color detection with charge sensitive infrared phototransistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Sunmi, E-mail: kimsunmi@iis.u-tokyo.ac.jp; Kajihara, Yusuke; Komiyama, Susumu

2015-11-02

Highly sensitive two-color detection is demonstrated at wavelengths of 9 μm and 14.5 μm by using a charge sensitive infrared phototransistor fabricated in a triple GaAs/AlGaAs quantum well (QW) crystal. Two differently thick QWs (7 nm- and 9 nm-thicknesses) serve as photosensitive floating gates for the respective wavelengths via intersubband excitation: The excitation in the QWs is sensed by a third QW, which works as a conducting source-drain channel in the photosensitive transistor. The two spectral bands of detection are shown to be controlled by front-gate biasing, providing a hint for implementing voltage tunable ultra-highly sensitive detectors.

Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high-κ oxide/tungsten nitride gate stacks

NASA Astrophysics Data System (ADS)

Kim, Kyoung H.; Gordon, Roy G.; Ritenour, Andrew; Antoniadis, Dimitri A.

2007-05-01

Atomic layer deposition (ALD) was used to deposit passivating interfacial nitride layers between Ge and high-κ oxides. High-κ oxides on Ge surfaces passivated by ultrathin (1-2nm) ALD Hf3N4 or AlN layers exhibited well-behaved C-V characteristics with an equivalent oxide thickness as low as 0.8nm, no significant flatband voltage shifts, and midgap density of interface states values of 2×1012cm-1eV-1. Functional n-channel and p-channel Ge field effect transistors with nitride interlayer/high-κ oxide/metal gate stacks are demonstrated.

Ultra-small, self-holding, optical gate switch using Ge2Sb2Te5 with a multi-mode Si waveguide.

PubMed

Tanaka, Daiki; Shoji, Yuya; Kuwahara, Masashi; Wang, Xiaomin; Kintaka, Kenji; Kawashima, Hitoshi; Toyosaki, Tatsuya; Ikuma, Yuichiro; Tsuda, Hiroyuki

2012-04-23

We report a multi-mode interference-based optical gate switch using a Ge(2)Sb(2)Te(5) thin film with a diameter of only 1 µm. The switching operation was demonstrated by laser pulse irradiation. This switch had a very wide operating wavelength range of 100 nm at around 1575 nm, with an average extinction ratio of 12.6 dB. Repetitive switching over 2,000 irradiation cycles was also successfully demonstrated. In addition, self-holding characteristics were confirmed by observing the dynamic responses, and the rise and fall times were 130 ns and 400 ns, respectively. © 2012 Optical Society of America

Ion transport by gating voltage to nanopores produced via metal-assisted chemical etching method.

PubMed

Van Toan, Nguyen; Inomata, Naoki; Toda, Masaya; Ono, Takahito

2018-05-11

In this work, we report a simple and low-cost way to create nanopores that can be employed for various applications in nanofluidics. Nano sized Ag particles in the range from 1 to 20 nm are formed on a silicon substrate with a de-wetting method. Then the silicon nanopores with an approximate 15 nm average diameter and 200 μm height are successfully produced by the metal-assisted chemical etching method. In addition, electrically driven ion transport in the nanopores is demonstrated for nanofluidic applications. Ion transport through the nanopores is observed and could be controlled by an application of a gating voltage to the nanopores.

Selective area deposited n-Al0.5Ga0.5N channel field effect transistors with high solar-blind ultraviolet photo-responsivity

NASA Astrophysics Data System (ADS)

Muhtadi, S.; Hwang, S.; Coleman, A.; Asif, F.; Lunev, A.; Chandrashekhar, M. V. S.; Khan, A.

2017-04-01

We report on AlGaN field effect transistors over AlN/sapphire templates with selective area grown n-Al0.5Ga0.5N channel layers for which a field-effect mobility of 55 cm2/V-sec was measured. Using a pulsed plasma enhanced chemical vapor deposition deposited 100 A thick SiO2 layer as the gate-insulator, the gate-leakage currents were reduced by three orders of magnitude. These devices with or without gate insulators are excellent solar-blind ultraviolet detectors, and they can be operated either in the photoconductive or the photo-voltaic modes. In the photo-conductive mode, gain arising from hole-trapping in the depletion region leads to steady-state photoresponsivity as high as 1.2 × 106A/W at 254 nm, which drops sharply below 290 nm. A hole-trapping limited detector response time of 34 ms, fast enough for real-time flame-detection and imaging applications, was estimated.

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

NASA Astrophysics Data System (ADS)

Ishii, Yuichiro; Tanaka, Miki; Yabuuchi, Makoto; Sawada, Yohei; Tanaka, Shinji; Nii, Koji; Lu, Tien Yu; Huang, Chun Hsien; Sian Chen, Shou; Tse Kuo, Yu; Lung, Ching Cheng; Cheng, Osbert

2018-04-01

We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (I read) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (V min) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

An Ultrathin Single Crystalline Relaxor Ferroelectric Integrated on a High Mobility Semiconductor.

PubMed

Moghadam, Reza M; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar; Grimley, Everett D; Bowden, Mark; Ong, Phuong-Vu; Chambers, Scott A; Lebeau, James M; Hong, Xia; Sushko, Peter V; Ngai, Joseph H

2017-10-11

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, the integration of gate materials that enable nonvolatile or hysteretic functionality in field-effect transistors could lead to device technologies that consume less power or allow for novel modalities in computing. Here we present electrical characterization of ultrathin single crystalline SrZr x Ti 1-x O 3 (x = 0.7) films epitaxially grown on a high mobility semiconductor, Ge. Epitaxial films of SrZr x Ti 1-x O 3 exhibit relaxor behavior, characterized by a hysteretic polarization that can modulate the surface potential of Ge. We find that gate layers as thin as 5 nm corresponding to an equivalent-oxide thickness of just 1.0 nm exhibit a ∼2 V hysteretic window in the capacitance-voltage characteristics. The development of hysteretic metal-oxide-semiconductor capacitors with nanoscale gate thicknesses opens new vistas for nanoelectronic devices.

Does the low hole transport mass in <110> and <111> Si nanowires lead to mobility enhancements at high field and stress: A self-consistent tight-binding study

NASA Astrophysics Data System (ADS)

Kotlyar, R.; Linton, T. D.; Rios, R.; Giles, M. D.; Cea, S. M.; Kuhn, K. J.; Povolotskyi, Michael; Kubis, Tillmann; Klimeck, Gerhard

2012-06-01

The hole surface roughness and phonon limited mobility in the silicon <100>, <110>, and <111> square nanowires under the technologically important conditions of applied gate bias and stress are studied with the self-consistent Poisson-sp3d5s*-SO tight-binding bandstructure method. Under an applied gate field, the hole carriers in a wire undergo a volume to surface inversion transition diminishing the positive effects of the high <110> and <111> valence band nonparabolicities, which are known to lead to the large gains of the phonon limited mobility at a zero field in narrow wires. Nonetheless, the hole mobility in the unstressed wires down to the 5 nm size remains competitive or shows an enhancement at high gate field over the large wire limit. Down to the studied 3 nm sizes, the hole mobility is degraded by strong surface roughness scattering in <100> and <110> wires. The <111> channels are shown to experience less surface scattering degradation. The physics of the surface roughness scattering dependence on wafer and channel orientations in a wire is discussed. The calculated uniaxial compressive channel stress gains of the hole mobility are found to reduce in the narrow wires and at the high field. This exacerbates the stressed mobility degradation with size. Nonetheless, stress gains of a factor of 2 are obtained for <110> wires down to 3 nm size at a 5×1012 cm-2 hole inversion density per gate area.

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE PAGES

King, M. P.; Wu, X.; Eller, Manfred; ...

2016-12-07

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

The flash memory battle: How low can we go?

NASA Astrophysics Data System (ADS)

van Setten, Eelco; Wismans, Onno; Grim, Kees; Finders, Jo; Dusa, Mircea; Birkner, Robert; Richter, Rigo; Scherübl, Thomas

2008-03-01

With the introduction of the TWINSCAN XT:1900Gi the limit of the water based hyper-NA immersion lithography has been reached in terms of resolution. With a numerical aperture of 1.35 a single expose resolution of 36.5nm half pitch has been demonstrated. However the practical resolution limit in production will be closer to 40nm half pitch, without having to go to double patterning alike strategies. In the relentless Flash memory market the performance of the exposure tool is stretched to the limit for a competitive advantage and cost-effective product. In this paper we will present the results of an experimental study of the resolution limit of the NAND-Flash Memory Gate layer for a production-worthy process on the TWINSCAN XT:1900Gi. The entire gate layer will be qualified in terms of full wafer CD uniformity, aberration sensitivities for the different wordlines and feature-center placement errors for 38, 39, 40 and 43nm half pitch design rule. In this study we will also compare the performance of a binary intensity mask to a 6% attenuated phase shift mask and look at strategies to maximize Depth of Focus, and to desensitize the gate layer for lens aberrations and placement errors. The mask is one of the dominant contributors to the CD uniformity budget of the flash gate layer. Therefore the wafer measurements are compared to aerial image measurements of the mask using AIMSTM 45-193i to separate the mask contribution from the scanner contribution to the final imaging performance.

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

King, M. P.; Wu, X.; Eller, Manfred

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

1030-nm diode-laser-based light source delivering pulses with nanojoule energies and picosecond duration adjustable by mode locking or pulse gating operation

NASA Astrophysics Data System (ADS)

Klehr, A.; Liero, A.; Wenzel, H.; Bugge, F.; Brox, O.; Fricke, J.; Ressel, P.; Knigge, A.; Heinrich, W.; Tränkle, G.

2017-02-01

A new compact 1030 nm picosecond light source which can be switched between pulse gating and mode locking operation is presented. It consists of a multi-section distributed Bragg reflector (DBR) laser, an ultrafast multisection optical gate and a flared power amplifier (PA), mounted together with high frequency electronics and optical elements on a 5×4 cm micro bench. The master oscillator (MO) is a 10 mm long ridge wave-guide (RW) laser consisting of 200 μm long saturable absorber, 1500 μm long gain, 8000 μm long cavity, 200 μm long DBR and 100 μm long monitor sections. The 2 mm long optical gate consisting of several RW sections is monolithically integrated with the 4 mm long gain-guided tapered amplifier on a single chip. The light source can be switched between pulse gating and passive mode locking operation. For pulse gating all sections of the MO (except of the DBR and monitor sections) are forward biased and driven by a constant current. By injecting electrical pulses into one section of the optical gate the CW beam emitted by the MO is converted into a train of optical pulses with adjustable widths between 250 ps and 1000 ps. Peak powers of 20 W and spectral linewidths in the MHz range are achieved. Shorter pulses with widths between 4 ps and 15 ps and peak powers up to 50 W but larger spectral widths of about 300 pm are generated by mode locking where the saturable absorber section of the MO is reversed biased. The repetition rate of 4.2 GHz of the pulse train emitted by the MO can be reduced to values between 1 kHz and 100 MHz by utilizing the optical gate as pulse picker. The pulse-to-pulse distance can be controlled by an external trigger source.

Assembly and stoichiometry of the core structure of the bacterial flagellar type III export gate complex.

PubMed

Fukumura, Takuma; Makino, Fumiaki; Dietsche, Tobias; Kinoshita, Miki; Kato, Takayuki; Wagner, Samuel; Namba, Keiichi; Imada, Katsumi; Minamino, Tohru

2017-08-01

The bacterial flagellar type III export apparatus, which is required for flagellar assembly beyond the cell membranes, consists of a transmembrane export gate complex and a cytoplasmic ATPase complex. FlhA, FlhB, FliP, FliQ, and FliR form the gate complex inside the basal body MS ring, although FliO is required for efficient export gate formation in Salmonella enterica. However, it remains unknown how they form the gate complex. Here we report that FliP forms a homohexameric ring with a diameter of 10 nm. Alanine substitutions of conserved Phe-137, Phe-150, and Glu-178 residues in the periplasmic domain of FliP (FliPP) inhibited FliP6 ring formation, suppressing flagellar protein export. FliO formed a 5-nm ring structure with 3 clamp-like structures that bind to the FliP6 ring. The crystal structure of FliPP derived from Thermotoga maritia, and structure-based photo-crosslinking experiments revealed that Phe-150 and Ser-156 of FliPP are involved in the FliP-FliP interactions and that Phe-150, Arg-152, Ser-156, and Pro-158 are responsible for the FliP-FliO interactions. Overexpression of FliP restored motility of a ∆fliO mutant to the wild-type level, suggesting that the FliP6 ring is a functional unit in the export gate complex and that FliO is not part of the final gate structure. Copurification assays revealed that FlhA, FlhB, FliQ, and FliR are associated with the FliO/FliP complex. We propose that the assembly of the export gate complex begins with FliP6 ring formation with the help of the FliO scaffold, followed by FliQ, FliR, and FlhB and finally FlhA during MS ring formation.

Assembly and stoichiometry of the core structure of the bacterial flagellar type III export gate complex

PubMed Central

Fukumura, Takuma; Makino, Fumiaki; Dietsche, Tobias; Kinoshita, Miki; Kato, Takayuki; Wagner, Samuel; Namba, Keiichi; Imada, Katsumi

2017-01-01

The bacterial flagellar type III export apparatus, which is required for flagellar assembly beyond the cell membranes, consists of a transmembrane export gate complex and a cytoplasmic ATPase complex. FlhA, FlhB, FliP, FliQ, and FliR form the gate complex inside the basal body MS ring, although FliO is required for efficient export gate formation in Salmonella enterica. However, it remains unknown how they form the gate complex. Here we report that FliP forms a homohexameric ring with a diameter of 10 nm. Alanine substitutions of conserved Phe-137, Phe-150, and Glu-178 residues in the periplasmic domain of FliP (FliPP) inhibited FliP6 ring formation, suppressing flagellar protein export. FliO formed a 5-nm ring structure with 3 clamp-like structures that bind to the FliP6 ring. The crystal structure of FliPP derived from Thermotoga maritia, and structure-based photo-crosslinking experiments revealed that Phe-150 and Ser-156 of FliPP are involved in the FliP–FliP interactions and that Phe-150, Arg-152, Ser-156, and Pro-158 are responsible for the FliP–FliO interactions. Overexpression of FliP restored motility of a ∆fliO mutant to the wild-type level, suggesting that the FliP6 ring is a functional unit in the export gate complex and that FliO is not part of the final gate structure. Copurification assays revealed that FlhA, FlhB, FliQ, and FliR are associated with the FliO/FliP complex. We propose that the assembly of the export gate complex begins with FliP6 ring formation with the help of the FliO scaffold, followed by FliQ, FliR, and FlhB and finally FlhA during MS ring formation. PMID:28771466

Current saturation and voltage gain in bilayer graphene field effect transistors.

PubMed

Szafranek, B N; Fiori, G; Schall, D; Neumaier, D; Kurz, H

2012-03-14

The emergence of graphene with its unique electrical properties has triggered hopes in the electronic devices community regarding its exploitation as a channel material in field effect transistors. Graphene is especially promising for devices working at frequencies in the 100 GHz range. So far, graphene field effect transistors (GFETs) have shown cutoff frequencies up to 300 GHz, while exhibiting poor voltage gains, another important figure of merit for analog high frequency applications. In the present work, we show that the voltage gain of GFETs can be improved significantly by using bilayer graphene, where a band gap is introduced through a vertical electric displacement field. At a displacement field of -1.7 V/nm the bilayer GFETs exhibit an intrinsic voltage gain up to 35, a factor of 6 higher than the voltage gain in corresponding monolayer GFETs. The transconductance, which limits the cutoff frequency of a transistor, is not degraded by the displacement field and is similar in both monolayer and bilayer GFETs. Using numerical simulations based on an atomistic p(z) tight-binding Hamiltonian we demonstrate that this approach can be extended to sub-100 nm gate lengths. © 2012 American Chemical Society

Multi-Dimensional Quantum Tunneling and Transport Using the Density-Gradient Model

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Yu, Zhi-Ping; Ancona, Mario; Rafferty, Conor; Saini, Subhash (Technical Monitor)

1999-01-01

We show that quantum effects are likely to significantly degrade the performance of MOSFETs (metal oxide semiconductor field effect transistor) as these devices are scaled below 100 nm channel length and 2 nm oxide thickness over the next decade. A general and computationally efficient electronic device model including quantum effects would allow us to monitor and mitigate these effects. Full quantum models are too expensive in multi-dimensions. Using a general but efficient PDE solver called PROPHET, we implemented the density-gradient (DG) quantum correction to the industry-dominant classical drift-diffusion (DD) model. The DG model efficiently includes quantum carrier profile smoothing and tunneling in multi-dimensions and for any electronic device structure. We show that the DG model reduces DD model error from as much as 50% down to a few percent in comparison to thin oxide MOS capacitance measurements. We also show the first DG simulations of gate oxide tunneling and transverse current flow in ultra-scaled MOSFETs. The advantages of rapid model implementation using the PDE solver approach will be demonstrated, as well as the applicability of the DG model to any electronic device structure.

Structured back gates for high-mobility two-dimensional electron systems using oxygen ion implantation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berl, M., E-mail: mberl@phys.ethz.ch; Tiemann, L.; Dietsche, W.

2016-03-28

We present a reliable method to obtain patterned back gates compatible with high mobility molecular beam epitaxy via local oxygen ion implantation that suppresses the conductivity of an 80 nm thick silicon doped GaAs epilayer. Our technique was optimized to circumvent several constraints of other gating and implantation methods. The ion-implanted surface remains atomically flat which allows unperturbed epitaxial overgrowth. We demonstrate the practical application of this gating technique by using magneto-transport spectroscopy on a two-dimensional electron system (2DES) with a mobility exceeding 20 × 10{sup 6} cm{sup 2}/V s. The back gate was spatially separated from the Ohmic contacts of the 2DES,more » thus minimizing the probability for electrical shorts or leakage and permitting simple contacting schemes.« less

High-Sensitivity GaN Microchemical Sensors

NASA Technical Reports Server (NTRS)

Son, Kyung-ah; Yang, Baohua; Liao, Anna; Moon, Jeongsun; Prokopuk, Nicholas

2009-01-01

Systematic studies have been performed on the sensitivity of GaN HEMT (high electron mobility transistor) sensors using various gate electrode designs and operational parameters. The results here show that a higher sensitivity can be achieved with a larger W/L ratio (W = gate width, L = gate length) at a given D (D = source-drain distance), and multi-finger gate electrodes offer a higher sensitivity than a one-finger gate electrode. In terms of operating conditions, sensor sensitivity is strongly dependent on transconductance of the sensor. The highest sensitivity can be achieved at the gate voltage where the slope of the transconductance curve is the largest. This work provides critical information about how the gate electrode of a GaN HEMT, which has been identified as the most sensitive among GaN microsensors, needs to be designed, and what operation parameters should be used for high sensitivity detection.

Static Noise Margin Enhancement by Flex-Pass-Gate SRAM

NASA Astrophysics Data System (ADS)

O'Uchi, Shin-Ichi; Masahara, Meishoku; Sakamoto, Kunihiro; Endo, Kazuhiko; Liu, Yungxun; Matsukawa, Takashi; Sekigawa, Toshihiro; Koike, Hanpei; Suzuki, Eiichi

A Flex-Pass-Gate SRAM, i.e. a fin-type-field-effect-transistor- (FinFET-) based SRAM, is proposed to enhance noise margin during both read and write operations. In its cell, the flip-flop is composed of usual three-terminal- (3T-) FinFETs while pass gates are composed of four-terminal- (4T-) FinFETs. The 4T-FinFETs enable to adopt a dynamic threshold-voltage control in the pass gates. During a write operation, the threshold voltage of the pass gates is lowered to enhance the writing speed and stability. During the read operation, on the other hand, the threshold voltage is raised to enhance the static noise margin. An asymmetric-oxide 4T-FinFET is helpful to manage the leakage current through the pass gate. In this paper, a design strategy of the pass gate with an asymmetric gate oxide is considered, and a TCAD-based Monte Carlo simulation reveals that the Flex-Pass-Gate SRAM based on that design strategy is expected to be effective in half-pitch 32-nm technology for low-standby-power (LSTP) applications, even taking into account the variability in the device performance.

An in situ Measurement of Extracellular Cysteamine, Homocysteine and Cysteine Concentrations in Organotypic Hippocampal Slice Cultures by Integration of Electroosmotic Sampling and Microfluidic Analysis

PubMed Central

Wu, Juanfang; Xu, Kerui; Landers, James P.; Weber, Stephen G.

2013-01-01

We demonstrate an all-electric sampling/derivatization/separation/detection system for the quantitation of thiols in tissue cultures. Extracellular fluid collected from rat organotypic hippocampal slice cultures (OHSCs) by electroosmotic flow through an11 cm (length) × 50 μm (ID) sampling capillary is introduced to a simple microfluidic chip for derivatization, continuous flow-gated injection, separation and detection.With the help of a fluorogenic, thiol-specific reagent, ThioGlo-1, we have successfully separated and detected the extracellular levels of free reduced cysteamine, homocysteineand cysteinefrom OHSCs within 25 s in a 23 mm separation channel with a confocal laser induced fluorescence (LIF) detector. Attention to the conductivities of the fluids being transported is required for successful flow-gated injections.When the sample conductivity is much higher than the run buffer conductivities, the electroosmotic velocities are such that there is less fluid coming by electroosmosis into the cross from the sample/reagent channel than is leaving by electroosmosis into the separation and waste channels. The resulting decrease in the internal fluid pressure in the injection cross pulls flow from the gated channel. This process may completely shut down the gated injection. Using a glycylglycine buffer with physiological osmolarity but only 62% of physiological conductivity and augmenting the conductivity of the run buffers solved this problem. Quantitation is by standard additions. Concentrations of cysteamine, homocysteine and cysteine in the extracellular space of OHSCs are10.6±1.0 nM (n=70), 0.18±0.01 μM (n=53) and 11.1±1.2 μM (n=70), respectively. This is the first in situquantitative estimation of endogenous cysteamine in brain. Extracellular levels of homocysteine and cysteine are comparable with other reported values. PMID:23330713

Modeling and analysis of sub-surface leakage current in nano-MOSFET under cutoff regime

NASA Astrophysics Data System (ADS)

Swami, Yashu; Rai, Sanjeev

2017-02-01

The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in nano-MOSFET circuits as threshold voltage, channel length, and gate oxide thickness are scaled down to nano-meter range. Precise leakage current valuation and meticulous modeling of the same at nano-meter technology scale is an increasingly a critical work in designing the low power nano-MOSFET circuits. We present a specific compact model for sub-threshold regime leakage current in bulk driven nano-MOSFETs. The proposed logical model is instigated and executed into the latest updated PTM bulk nano-MOSFET model and is found to be in decent accord with technology-CAD simulation data. This paper also reviews various transistor intrinsic leakage mechanisms for nano-MOSFET exclusively in weak inversion, like drain-induced barricade lowering (DIBL), gate-induced drain leakage (GIDL), gate oxide tunneling (GOT) leakage etc. The root cause of the sub-surface leakage current is mainly due to the nano-scale short channel length causing source-drain coupling even in sub-threshold domain. Consequences leading to carriers triumphing the barricade between the source and drain. The enhanced model effectively considers the following parameter dependence in the account for better-quality value-added results like drain-to-source bias (VDS), gate-to-source bias (VGS), channel length (LG), source/drain junction depth (Xj), bulk doping concentration (NBULK), and operating temperature (Top).

Study of proton radiation effects among diamond and rectangular gate MOSFET layouts

NASA Astrophysics Data System (ADS)

Seixas, L. E., Jr.; Finco, S.; Silveira, M. A. G.; Medina, N. H.; Gimenez, S. P.

2017-01-01

This paper describes an experimental comparative study of proton ionizing radiation effects between the metal-oxide-semiconductor (MOS) Field Effect Transistors (MOSFETs) implemented with hexagonal gate shapes (diamond) and their respective counterparts designed with the classical rectangular ones, regarding the same gate areas, channel widths and geometrical ratios (W/L). The devices were manufactured by using the 350 nm bulk complementary MOS (CMOS) integrated circuits technology. The diamond MOSFET with α angles higher or equal to 90° tends to present a smaller vulnerability to the high doses ionizing radiation than those observed in the typical rectangular MOSFET counterparts.

Ultra-low contact resistance in graphene devices at the Dirac point

NASA Astrophysics Data System (ADS)

Anzi, Luca; Mansouri, Aida; Pedrinazzi, Paolo; Guerriero, Erica; Fiocco, Marco; Pesquera, Amaia; Centeno, Alba; Zurutuza, Amaia; Behnam, Ashkan; Carrion, Enrique A.; Pop, Eric; Sordan, Roman

2018-04-01

Contact resistance is one of the main factors limiting performance of short-channel graphene field-effect transistors (GFETs), preventing their use in low-voltage applications. Here we investigated the contact resistance between graphene grown by chemical vapor deposition (CVD) and different metals, and found that etching holes in graphene below the contacts consistently reduced the contact resistance, down to 23 Ω \\cdot μ m with Au contacts. This low contact resistance was obtained at the Dirac point of graphene, in contrast to previous studies where the lowest contact resistance was obtained at the highest carrier density in graphene (here 200 Ω \\cdot μ m was obtained under such conditions). The ‘holey’ Au contacts were implemented in GFETs which exhibited an average transconductance of 940 S m-1 at a drain bias of only 0.8 V and gate length of 500 nm, which out-perform GFETs with conventional Au contacts.

Enhancing the noise performance of monolithic microwave integrated circuit-based low noise amplifiers through the use of a discrete preamplifying transistor

NASA Astrophysics Data System (ADS)

McCulloch, Mark A.; Melhuish, Simon J.; Piccirillo, Lucio

2015-01-01

An approach to enhancing the noise performance of an InP monolithic microwave integrated circuit (MMIC)-based low noise amplifiers (LNA) through the use of a discrete 100-nm gate length InP high electron mobility transistor is outlined. This LNA, known as a transistor in front of MMIC (T + MMIC) LNA, possesses a gain in excess of 40 dB and an average noise temperature of 9.4 K across the band 27 to 33 GHz at a physical temperature of 8 K. This compares favorably with 14.5 K for an LNA containing an equivalent MMIC. A simple advanced design system model offering further insights into the operation of the LNA is also presented and the LNA is compared with the current state-of-the-art Planck LFI LNAs.

Electron transport in the two-dimensional channel material - zinc oxide nanoflake

NASA Astrophysics Data System (ADS)

Lai, Jian-Jhong; Jian, Dunliang; Lin, Yen-Fu; Ku, Ming-Ming; Jian, Wen-Bin

2018-03-01

ZnO nanoflakes of 3-5 μm in lateral size and 15-20 nm in thickness are synthesized. The nanoflakes are used to make back-gated transistor devices. Electron transport in the ZnO nanoflake channel between source and drain electrodes are investigated. In the beginning, we argue and determine that electrons are in a two-dimensional system. We then apply Mott's two-dimensional variable range hopping model to analyze temperature and electric field dependences of resistivity. The disorder parameter, localization length, hopping distance, and hopping energy of the electron system in ZnO nanoflakes are obtained and, additionally, their temperature behaviors and dependences on room-temperature resistivity are presented. On the other hand, the basic transfer characteristics of the channel material are carried out, as well, and the carrier concentration, the mobility, and the Fermi wavelength of two-dimensional ZnO nanoflakes are estimated.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.

PubMed

Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

2012-08-19

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

Submicron Silicon MOSFET

NASA Technical Reports Server (NTRS)

Daud, T.

1986-01-01

Process for making metal-oxide/semiconductor field-effect transistors (MOSFET's) results in gate-channel lengths of only few hundred angstroms about 100 times as small as state-of-the-art devices. Gates must be shortened to develop faster MOSFET's; proposed fabrication process used to study effects of size reduction in MOS devices and eventually to build practical threedimensional structures.

DC and analog/RF performance optimisation of source pocket dual work function TFET

NASA Astrophysics Data System (ADS)

Raad, Bhagwan Ram; Sharma, Dheeraj; Kondekar, Pravin; Nigam, Kaushal; Baronia, Sagar

2017-12-01

We investigate a systematic study of source pocket tunnel field-effect transistor (SP TFET) with dual work function of single gate material by using uniform and Gaussian doping profile in the drain region for ultra-low power high frequency high speed applications. For this, a n+ doped region is created near the source/channel junction to decrease the depletion width results in improvement of ON-state current. However, the dual work function of the double gate is used for enhancement of the device performance in terms of DC and analog/RF parameters. Further, to improve the high frequency performance of the device, Gaussian doping profile is considered in the drain region with different characteristic lengths which decreases the gate to drain capacitance and leads to drastic improvement in analog/RF figures of merit. Furthermore, the optimisation is performed with different concentrations for uniform and Gaussian drain doping profile and for various sectional length of lower work function of the gate electrode. Finally, the effect of temperature variation on the device performance is demonstrated.

Recessed Slant Gate AlGaN/GaN High Electron Mobility Transistors with 20.9 W/mm at 10 GHz

NASA Astrophysics Data System (ADS)

Pei, Yi; Chu, Rongming; Fichtenbaum, Nicholas A.; Chen, Zhen; Brown, David; Shen, Likun; Keller, Stacia; DenBaars, Steven P.; Mishra, Umesh K.

2007-12-01

A recessed slant gate processing has been used in AlGaN/GaN high electron mobility transistors (HEMTs) to mitigate the electric field, minimize the dispersion and increase the breakdown voltage. More than one order of magnitude of decrease in gate leakage has been observed by recessing the slant gate. For a 0.65 μm gate-length device, an extrinsic fT of 18 GHz and extrinsic fMAX of 52 GHz at a drain bias of 25 V were achieved. At 10 GHz, a state-of-the-art power density of 20.9 W/mm, with a power-added efficiency (PAE) of 40% at a drain bias of 83 V, was demonstrated.

Memory in a fractional-order cardiomyocyte model alters properties of alternans and spontaneous activity

NASA Astrophysics Data System (ADS)

Comlekoglu, T.; Weinberg, S. H.

2017-09-01

Cardiac memory is the dependence of electrical activity on the prior history of one or more system state variables, including transmembrane potential (Vm), ionic current gating, and ion concentrations. While prior work has represented memory either phenomenologically or with biophysical detail, in this study, we consider an intermediate approach of a minimal three-variable cardiomyocyte model, modified with fractional-order dynamics, i.e., a differential equation of order between 0 and 1, to account for history-dependence. Memory is represented via both capacitive memory, due to fractional-order Vm dynamics, that arises due to non-ideal behavior of membrane capacitance; and ionic current gating memory, due to fractional-order gating variable dynamics, that arises due to gating history-dependence. We perform simulations for varying Vm and gating variable fractional-orders and pacing cycle length and measure action potential duration (APD) and incidence of alternans, loss of capture, and spontaneous activity. In the absence of ionic current gating memory, we find that capacitive memory, i.e., decreased Vm fractional-order, typically shortens APD, suppresses alternans, and decreases the minimum cycle length (MCL) for loss of capture. However, in the presence of ionic current gating memory, capacitive memory can prolong APD, promote alternans, and increase MCL. Further, we find that reduced Vm fractional order (typically less than 0.75) can drive phase 4 depolarizations that promote spontaneous activity. Collectively, our results demonstrate that memory reproduced by a fractional-order model can play a role in alternans formation and pacemaking, and in general, can greatly increase the range of electrophysiological characteristics exhibited by a minimal model.

Role of Oxygen in Ionic Liquid Gating on Two-Dimensional Cr2Ge2Te6: A Non-oxide Material.

PubMed

Chen, Yangyang; Xing, Wenyu; Wang, Xirui; Shen, Bowen; Yuan, Wei; Su, Tang; Ma, Yang; Yao, Yunyan; Zhong, Jiangnan; Yun, Yu; Xie, X C; Jia, Shuang; Han, Wei

2018-01-10

Ionic liquid gating can markedly modulate a material's carrier density so as to induce metallization, superconductivity, and quantum phase transitions. One of the main issues is whether the mechanism of ionic liquid gating is an electrostatic field effect or an electrochemical effect, especially for oxide materials. Recent observation of the suppression of the ionic liquid gate-induced metallization in the presence of oxygen for oxide materials suggests the electrochemical effect. However, in more general scenarios, the role of oxygen in the ionic liquid gating effect is still unclear. Here, we perform ionic liquid gating experiments on a non-oxide material: two-dimensional ferromagnetic Cr 2 Ge 2 Te 6 . Our results demonstrate that despite the large increase of the gate leakage current in the presence of oxygen, the oxygen does not affect the ionic liquid gating effect on  the channel resistance of Cr 2 Ge 2 Te 6 devices (<5% difference), which suggests the electrostatic field effect as the mechanism on non-oxide materials. Moreover, our results show that ionic liquid gating is more effective on the modulation of the channel resistances compared to the back gating across the 300 nm thick SiO 2 .

Frequency-doubled passively Q-switched microchip laser producing 225  ps pulses at 671  nm.

PubMed

Nikkinen, Jari; Korpijärvi, Ville-Markus; Leino, Iiro; Härkönen, Antti; Guina, Mircea

2016-11-15

We report a 671 nm laser source emitting 225 ps pulses with an average power of 55 mW and a repetition rate of 444 kHz. The system consists of a 1342 nm SESAM Q-switched Nd:YVO₄ microchip master oscillator and a dual-stage Nd:YVO₄ power amplifier. The 1342 nm signal was frequency-doubled to 671 nm using a periodically poled lithium niobate crystal. This laser source provides a practical alternative for applications requiring high energy picosecond pulses, such as time-gated Raman spectroscopy.

Double-gated Si NW FET sensors: Low-frequency noise and photoelectric properties

NASA Astrophysics Data System (ADS)

Gasparyan, F.; Khondkaryan, H.; Arakelyan, A.; Zadorozhnyi, I.; Pud, S.; Vitusevich, S.

2016-08-01

The transport, noise, and photosensitivity properties of an array of silicon nanowire (NW) p+-p-p+ field-effect transistors (FETs) are investigated. The peculiarities of photosensitivity and detectivity are analyzed over a wide spectrum range. The absorbance of p-Si NW shifts to the short wavelength region compared with bulk Si. The photocurrent and photosensitivity reach increased values in the UV range of the spectrum at 300 K. It is shown that sensitivity values can be tuned by the drain-source voltage and may reach record values of up to 2-4 A/W at a wavelength of 300 nm at room temperature. Low-frequency noise studies allow calculating the photodetectivity values, which increase with decreasing wavelength down to 300 nm. We show that the drain current of Si NW biochemical sensors substantially depends on pH value and the signal-to-noise ratio reaches the high value of 105. Increasing pH sensitivity with gate voltage is revealed for certain source-drain currents of pH-sensors based on Si NW FETs. The noise characteristic index decreases from 1.1 to 0.7 with the growth of the liquid gate voltage. Noise behavior is successfully explained in the framework of the correlated number-mobility unified fluctuation model. pH sensitivity increases as a result of the increase in liquid gate voltage, thus giving the opportunity to measure very low proton concentrations in the electrolyte medium at certain values of the liquid gate voltage.

Field ion source development for neutron generators

NASA Astrophysics Data System (ADS)

Bargsten Johnson, B.; Schwoebel, P. R.; Holland, C. E.; Resnick, P. J.; Hertz, K. L.; Chichester, D. L.

2012-01-01

An ion source based on the principles of electrostatic field desorption is being developed to improve the performance of existing compact neutron generators. The ion source is an array of gated metal tips derived from field electron emitter array microfabrication technology. A comprehensive summary of development and experimental activities is presented. Many structural modifications to the arrays have been incorporated to achieve higher tip operating fields, while lowering fields at the gate electrode to prevent gate field electron emission which initiates electrical breakdown in the array. The latest focus of fabrication activities has been on rounding the gate electrode edge and surrounding the gate electrode with dielectric material. Array testing results have indicated a steady progression of increased array tip operating fields with each new design tested. The latest arrays have consistently achieved fields beyond those required for the onset of deuterium desorption (˜20 V/nm), and have demonstrated the desorption of deuterium at fields up to 36 V/nm. The number of ions desorbed from an array has been quantified, and field desorption of metal tip substrate material from array tips has been observed for the first time. Gas-phase field ionization studies with ˜10,000 tip arrays have achieved deuterium ion currents of ˜50 nA. Neutron production by field ionization has yielded ˜10 2 n/s from ˜1 mm 2 of array area using the deuterium-deuterium fusion reaction at 90 kV.

AC signal characterization for optimization of a CMOS single-electron pump

NASA Astrophysics Data System (ADS)

Murray, Roy; Perron, Justin K.; Stewart, M. D., Jr.; Zimmerman, Neil M.

2018-02-01

Pumping single electrons at a set rate is being widely pursued as an electrical current standard. Semiconductor charge pumps have been pursued in a variety of modes, including single gate ratchet, a variety of 2-gate ratchet pumps, and 2-gate turnstiles. Whether pumping with one or two AC signals, lower error rates can result from better knowledge of the properties of the AC signal at the device. In this work, we operated a CMOS single-electron pump with a 2-gate ratchet style measurement and used the results to characterize and optimize our two AC signals. Fitting this data at various frequencies revealed both a difference in signal path length and attenuation between our two AC lines. Using this data, we corrected for the difference in signal path length and attenuation by applying an offset in both the phase and the amplitude at the signal generator. Operating the device as a turnstile while using the optimized parameters determined from the 2-gate ratchet measurement led to much flatter, more robust charge pumping plateaus. This method was useful in tuning our device up for optimal charge pumping, and may prove useful to the semiconductor quantum dot community to determine signal attenuation and path differences at the device.

High-sensitivity pH sensor using separative extended-gate field-effect transistors with single-walled carbon-nanotube networks

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2018-04-01

We fabricate high-sensitivity pH sensors using single-walled carbon-nanotube (SWCNT) network thin-film transistors (TFTs). The sensing and transducer parts of the pH sensor are composed of separative extended-sensing gates (ESGs) with SnO2 ion-sensitive membranes and double-gate structure TFTs with thin SWCNT network channels of ∼1 nm and AlO x top-gate insulators formed by the solution-deposition method. To prevent thermal process-induced damages on the SWCNT channel layer due to the post-deposition annealing process and improve the electrical characteristics of the SWCNT-TFTs, microwave irradiation is applied at low temperatures. As a result, a pH sensitivity of 7.6 V/pH, far beyond the Nernst limit, is obtained owing to the capacitive coupling effect between the top- and bottom-gate insulators of the SWCNT-TFTs. Therefore, double-gate structure SWCNT-TFTs with separated ESGs are expected to be highly beneficial for high-sensitivity disposable biosensor applications.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate

NASA Astrophysics Data System (ADS)

Ahmad, Nabihah; Hakimi Mokhtar, Ahmad; Othman, Nurmiza binti; Fhong Soon, Chin; Rahman, Ab Al Hadi Ab

2017-08-01

Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2×2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160μm x 420.3μm (67.25 mm2). This design achieved a low power consumption of 122.85μW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.

Disturb-Free Three-Dimensional Vertical Floating Gate NAND with Separated-Sidewall Control Gate

NASA Astrophysics Data System (ADS)

Seo, Moon-Sik; Endoh, Tetsuo

2012-02-01

Recently, the three-dimensional (3D) vertical floating gate (FG) type NAND cell arrays with the sidewall control gate (SCG) structure are receiving attention to overcome the reliability issues of charge trap (CT) type 3D NAND. In order to achieve the multilevel cell (MLC) operation for lower bit cost in 3D NAND, it is important to eliminate reliability issues, such as the Vth distribution with interference and disturbance problems and Vth shift with retention issues. In this paper, we intensively investigated the disturbance problems of the 3D vertical FG type NAND cell with separated-sidewall control gate (S-SCG) structure for the reliable MLC operation. Above all, we successfully demonstrate the fully suppressed disturbance problems, such as indirect programming of the unselected cells, hot electron injection of the edge cells and direct influence to the neighboring passing cells, by using the S-SCG with 30 nm pillar size.

Local gate control in carbon nanotube quantum devices

NASA Astrophysics Data System (ADS)

Biercuk, Michael Jordan

This thesis presents transport measurements of carbon nanotube electronic devices operated in the quantum regime. Nanotubes are contacted by source and drain electrodes, and multiple lithographically-patterned electrostatic gates are aligned to each device. Transport measurements of device conductance or current as a function of local gate voltages reveal that local gates couple primarily to the proximal section of the nanotube, hence providing spatially localized control over carrier density along the nanotube length. Further, using several different techniques we are able to produce local depletion regions along the length of a tube. This phenomenon is explored in detail for different contact metals to the nanotube. We utilize local gating techniques to study multiple quantum dots in carbon nanotubes produced both by naturally occurring defects, and by the controlled application of voltages to depletion gates. We study double quantum dots in detail, where transport measurements reveal honeycomb charge stability diagrams. We extract values of energy-level spacings, capacitances, and interaction energies for this system, and demonstrate independent control over all relevant tunneling rates. We report rf-reflectometry measurements of gate-defined carbon nanotube quantum dots with integrated charge sensors. Aluminum rf-SETs are electrostatically coupled to carbon nanotube devices and detect single electron charging phenomena in the Coulomb blockade regime. Simultaneous correlated measurements of single electron charging are made using reflected rf power from the nanotube itself and from the rf-SET on microsecond time scales. We map charge stability diagrams for the nanotube quantum dot via charge sensing, observing Coulomb charging diamonds beyond the first order. Conductance measurements of carbon nanotubes containing gated local depletion regions exhibit plateaus as a function of gate voltage, spaced by approximately 1e2/h, the quantum of conductance for a single (non-degenerate) mode. Plateau structure is investigated as a function of bias voltage, temperature, and magnetic field. We speculate on the origin of this surprising quantization, which appears to lack band and spin degeneracy.

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers

PubMed Central

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Abstract Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlOx), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers. PMID:28634499

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

PubMed

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

Recombinant Production, Reconstruction in Lipid-Protein Nanodiscs, and Electron Microscopy of Full-Length α-Subunit of Human Potassium Channel Kv7.1.

PubMed

Shenkarev, Z O; Karlova, M G; Kulbatskii, D S; Kirpichnikov, M P; Lyukmanova, E N; Sokolova, O S

2018-05-01

Voltage-gated potassium channel Kv7.1 plays an important role in the excitability of cardiac muscle. The α-subunit of Kv7.1 (KCNQ1) is the main structural element of this channel. Tetramerization of KCNQ1 in the membrane results in formation of an ion channel, which comprises a pore and four voltage-sensing domains. Mutations in the human KCNQ1 gene are one of the major causes of inherited arrhythmias, long QT syndrome in particular. The construct encoding full-length human KCNQ1 protein was synthesized in this work, and an expression system in the Pichia pastoris yeast cells was developed. The membrane fraction of the yeast cells containing the recombinant protein (rKCNQ1) was solubilized with CHAPS detergent. To better mimic the lipid environment of the channel, lipid-protein nanodiscs were formed using solubilized membrane fraction and MSP2N2 protein. The rKCNQ1/nanodisc and rKCNQ1/CHAPS samples were purified using the Rho1D4 tag introduced at the C-terminus of the protein. Protein samples were examined using transmission electron microscopy with negative staining. In both cases, homogeneous rKCNQ1 samples were observed based on image analysis. Statistical analysis of the images of individual protein particles solubilized in the detergent revealed the presence of a tetrameric structure confirming intact subunit assembly. A three-dimensional channel structure reconstructed at 2.5-nm resolution represents a compact density with diameter of the membrane part of ~9 nm and height ~11 nm. Analysis of the images of rKCNQ1 in nanodiscs revealed additional electron density corresponding to the lipid bilayer fragment and the MSP2N2 protein. These results indicate that the nanodiscs facilitate protein isolation, purification, and stabilization in solution and can be used for further structural studies of human Kv7.1.

Study of drain-extended NMOS under electrostatic discharge stress in 28 nm and 40 nm CMOS process

NASA Astrophysics Data System (ADS)

Wang, Weihuai; Jin, Hao; Dong, Shurong; Zhong, Lei; Han, Yan

2016-02-01

Researches on the electrostatic discharge (ESD) performance of drain-extended NMOS (DeNMOS) under the state-of-the-art 28 nm and 40 nm bulk CMOS process are performed in this paper. Three distinguishing phases of avalanche breakdown stage, depletion region push-out stage and parasitic NPN turn on stage of the gate-grounded DeNMOS (GG-DeNMOS) fabricated under 28 nm CMOS process measured with transmission line pulsing (TLP) test are analyzed through TCAD simulations and tape-out silicon verification detailedly. Damage mechanisms and failure spots of GG-DeNMOS under both CMOS processes are thermal breakdown of drain junction. Improvements based on the basic structure adjustments can increase the GG-DeNMOS robustness from original 2.87 mA/μm to the highest 5.41 mA/μm. Under 40 nm process, parameter adjustments based on the basic structure have no significant benefits on the robustness improvements. By inserting P+ segments in the N+ implantation of drain or an entire P+ strip between the N+ implantation of drain and polysilicon gate to form the typical DeMOS-SCR (silicon-controlled rectifier) structure, the ESD robustness can be enhanced from 1.83 mA/μm to 8.79 mA/μm and 29.78 mA/μm, respectively.

An Optoelectronics Research Center

DTIC Science & Technology

2006-03-08

compared with a -2 mm wide slab, -200 nrn thick silicon (SOl) top-only-gate planar MOSFET with otherwise similar doping profiles, gate length and...acoustic phonons, impurity doping profile and surface roughness influences the transport process in the channel regions. The electron mobility in the...application areas including: nanoscale epitaxial growth for semiconductor heterostructures; nanofluidics for biological separations; nanomagnetics for

A Cu2+-selective fluorescent chemosensor based on BODIPY with two pyridine ligands and logic gate

NASA Astrophysics Data System (ADS)

Huang, Liuqian; Zhang, Jing; Yu, Xiaoxiu; Ma, Yifan; Huang, Tianjiao; Shen, Xi; Qiu, Huayu; He, Xingxing; Yin, Shouchun

2015-06-01

A novel near-infrared fluorescent chemosensor based on BODIPY (Py-1) has been synthesized and characterized. Py-1 displays high selectivity and sensitivity for sensing Cu2+ over other metal ions in acetonitrile. Upon addition of Cu2+ ions, the maximum absorption band of Py-1 in CH3CN displays a red shift from 603 to 608 nm, which results in a visual color change from pink to blue. When Py-1 is excited at 600 nm in the presence of Cu2+, the fluorescent emission intensity of Py-1 at 617 nm is quenched over 86%. Notably, the complex of Py-1-Cu2+ can be restored with the introduction of EDTA or S2-. Consequently, an IMPLICATION logic gate at molecular level operating in fluorescence mode with Cu2+ and S2- as chemical inputs can be constructed. Finally, based on the reversible and reproducible system, a nanoscale sequential memory unit displaying "Writing-Reading-Erasing-Reading" functions can be integrated.

A chemosensor showing discriminating fluorescent response for highly selective and nanomolar detection of Cu²⁺ and Zn²⁺ and its application in molecular logic gate.

PubMed

Fegade, Umesh A; Sahoo, Suban K; Singh, Amanpreet; Singh, Narinder; Attarde, Sanjay B; Kuwar, Anil S

2015-05-04

A fluorescent based receptor (4Z)-4-(4-diethylamino)-2-hydroxybenzylidene amino)-1,2dihydro-1,5-dimethyl-2-phenylpyrazol-3-one (receptor 3) was developed for the highly selective and sensitive detection of Cu(2+) and Zn(2+) in semi-aqueous system. The fluorescence of receptor 3 was enhanced and quenched, respectively, with the addition of Zn(2+) and Cu(2+) ions over other surveyed cations. The receptor formed host-guest complexes in 1:1 stoichiometry with the detection limit of 5 nM and 15 nM for Cu(2+) and Zn(2+) ions, respectively. Further, we have effectively utilized the two metal ions (Cu(2+) and Zn(2+)) as chemical inputs for the manufacture of INHIBIT type logic gate at molecular level using the fluorescence responses of receptor 3 at 450 nm. Copyright © 2015 Elsevier B.V. All rights reserved.

III-V Ultra-Thin-Body InGaAs/InAs MOSFETs for Low Standby Power Logic Applications

NASA Astrophysics Data System (ADS)

Huang, Cheng-Ying

As device scaling continues to sub-10-nm regime, III-V InGaAs/InAs metal- oxide-semiconductor ?eld-e?ect transistors (MOSFETs) are promising candidates for replacing Si-based MOSFETs for future very-large-scale integration (VLSI) logic applications. III-V InGaAs materials have low electron effective mass and high electron velocity, allowing higher on-state current at lower VDD and reducing the switching power consumption. However, III-V InGaAs materials have a narrower band gap and higher permittivity, leading to large band-to-band tunneling (BTBT) leakage or gate-induced drain leakage (GIDL) at the drain end of the channel, and large subthreshold leakage due to worse electrostatic integrity. To utilize III-V MOSFETs in future logic circuits, III-V MOSFETs must have high on-state performance over Si MOSFETs as well as very low leakage current and low standby power consumption. In this dissertation, we will report InGaAs/InAs ultra-thin-body MOSFETs. Three techniques for reducing the leakage currents in InGaAs/InAs MOSFETs are reported as described below. 1) Wide band-gap barriers: We developed AlAs0.44Sb0.56 barriers lattice-match to InP by molecular beam epitaxy (MBE), and studied the electron transport in In0.53Ga0.47As/AlAs 0.44Sb0.56 heterostructures. The InGaAs channel MOSFETs using AlAs0.44Sb0.56 bottom barriers or p-doped In0.52 Al0.48As barriers were demonstrated, showing significant suppression on the back barrier leakage. 2) Ultra-thin channels: We investigated the electron transport in InGaAs and InAs ultra-thin quantum wells and ultra-thin body MOSFETs (t ch ~ 2-4 nm). For high performance logic, InAs channels enable higher on-state current, while for low power logic, InGaAs channels allow lower BTBT leakage current. 3) Source/Drain engineering: We developed raised InGaAs and recessed InP source/drain spacers. The raised InGaAs source/drain spacers improve electrostatics, reducing subthreshold leakage, and smooth the electric field near drain, reducing BTBT leakage. With further replacement of raised InGaAs spacers by recessed, doping-graded InP spacers at high field regions, BTBT leakage can be reduced ~100:1. Using the above-mentioned techniques, record high performance InAs MOSFETs with a 2.7 nm InAs channel and a ZrO2 gate dielectric were demonstrated with Ion = 500 microA/microm at Ioff = 100 nA/microm and VDS =0.5 V, showing the highest on-state performance among all the III-V MOSFETs and comparable performance to 22 nm Si FinFETs. Record low leakage InGaAs MOSFETs with recessed InP source/drain spacers were also demonstrated with minimum I off = 60 pA/microm at 30 nm-Lg , and Ion = 150 microA/microm at I off = 1 nA/microm and VDS =0.5 V. This recessed InP source/drain spacer technique improves device scalability and enables III-V MOSFETs for low standby power logic applications. Furthermore, ultra-thin InAs channel MOSFETs were fabricated on Si substrates, exhibiting high yield and high transconductance gm ~2.0 mS/microm at 20 nm- Lg and VDS =0.5 V. With further scaling of gate lengths, a 12 nm-Lg III-V MOSFET has shown maximum Ion/Ioff ratio ~8.3x105 , confirming that III-V MOSFETs are scalable to sub-10-nm technology nodes.

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Synthesis and electron storage characteristics of isolated silver nanodots on/embedded in Al 2O 3 gate dielectric

NASA Astrophysics Data System (ADS)

Wang, Q.; Song, Z. T.; Liu, W. L.; Lin, C. L.; Wang, T. H.

2004-05-01

Monolayer-isolated silver (Ag) nanodots with the average diameter down to 7 nm are synthesized on Al 2O 3/Si substrate by vacuum electron-beam evaporation followed by annealing at 400 °C in N 2 ambient. Metal-insulator-silicon (MIS) structures with Ag nanodots embedded in Al 2O 3 gate dielectric are fabricated. Clear electron storage effect with the flatband voltage shift of 1.3 eV is observed through capacitance-conductance and conductance-voltage measurements. Our results demonstrate the feasibility of applying Ag nanodots for nanocrystal floating-gate memory devices.

Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

NASA Astrophysics Data System (ADS)

Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

2018-01-01

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

All-Aluminum Thin Film Transistor Fabrication at Room Temperature.

PubMed

Yao, Rihui; Zheng, Zeke; Zeng, Yong; Liu, Xianzhe; Ning, Honglong; Hu, Shiben; Tao, Ruiqiang; Chen, Jianqiu; Cai, Wei; Xu, Miao; Wang, Lei; Lan, Linfeng; Peng, Junbiao

2017-02-23

Bottom-gate all-aluminum thin film transistors with multi conductor/insulator nanometer heterojunction were investigated in this article. Alumina (Al₂O₃) insulating layer was deposited on the surface of aluminum doping zinc oxide (AZO) conductive layer, as one AZO/Al₂O₃ heterojunction unit. The measurements of transmittance electronic microscopy (TEM) and X-ray reflectivity (XRR) revealed the smooth interfaces between ~2.2-nm-thick Al₂O₃ layers and ~2.7-nm-thick AZO layers. The devices were entirely composited by aluminiferous materials, that is, their gate and source/drain electrodes were respectively fabricated by aluminum neodymium alloy (Al:Nd) and pure Al, with Al₂O₃/AZO multilayered channel and AlO x :Nd gate dielectric layer. As a result, the all-aluminum TFT with two Al₂O₃/AZO heterojunction units exhibited a mobility of 2.47 cm²/V·s and an I on / I off ratio of 10⁶. All processes were carried out at room temperature, which created new possibilities for green displays industry by allowing for the devices fabricated on plastic-like substrates or papers, mainly using no toxic/rare materials.

Layer-by-layer charging in non-volatile memory devices using embedded sub-2 nm platinum nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ramalingam, Balavinayagam; Zheng, Haisheng; Gangopadhyay, Shubhra, E-mail: gangopadhyays@missouri.edu

In this work, we demonstrate multi-level operation of a non-volatile memory metal oxide semiconductor capacitor by controlled layer-by-layer charging of platinum nanoparticle (PtNP) floating gate devices with defined gate voltage bias ranges. The device consists of two layers of ultra-fine, sub-2 nm PtNPs integrated between Al{sub 2}O{sub 3} tunneling and separation layers. PtNP size and interparticle distance were varied to control the particle self-capacitance and associated Coulomb charging energy. Likewise, the tunneling layer thicknesses were also varied to control electron tunneling to the first and second PtNP layers. The final device configuration with optimal charging behavior and multi-level programming was attainedmore » with a 3 nm Al{sub 2}O{sub 3} initial tunneling layer, initial PtNP layer with particle size 0.54 ± 0.12 nm and interparticle distance 4.65 ± 2.09 nm, 3 nm Al{sub 2}O{sub 3} layer to separate the PtNP layers, and second particle layer with 1.11 ± 0.28 nm PtNP size and interparticle distance 2.75 ± 1.05 nm. In this device, the memory window of the first PtNP layer saturated over a programming bias range of 7 V to 14 V, after which the second PtNP layer starts charging, exhibiting a multi-step memory window with layer-by-layer charging.« less

Unusual instability mode of transparent all oxide thin film transistor under dynamic bias condition

NASA Astrophysics Data System (ADS)

Oh, Himchan; Hwang, Chi-Sun; Pi, Jae-Eun; Ki Ryu, Min; Ko Park, Sang-Hee; Yong Chu, Hye

2013-09-01

We report a degradation behavior of fully transparent oxide thin film transistor under dynamic bias stress which is the condition similar to actual pixel switching operation in active matrix display. After the stress test, drain current increased while the threshold voltage was almost unchanged. We found that shortening of effective channel length is leading cause of increase in drain current. Electrons activate the neutral donor defects by colliding with them during short gate-on period. These ionized donors are stabilized during the subsequent gate-off period due to electron depletion. This local increase in doping density reduces the channel length.

Spatial distribution of calcium-gated chloride channels in olfactory cilia.

PubMed

French, Donald A; Badamdorj, Dorjsuren; Kleene, Steven J

2010-12-30

In vertebrate olfactory receptor neurons, sensory cilia transduce odor stimuli into changes in neuronal membrane potential. The voltage changes are primarily caused by the sequential openings of two types of channel: a cyclic-nucleotide-gated (CNG) cationic channel and a calcium-gated chloride channel. In frog, the cilia are 25 to 200 µm in length, so the spatial distributions of the channels may be an important determinant of odor sensitivity. To determine the spatial distribution of the chloride channels, we recorded from single cilia as calcium was allowed to diffuse down the length of the cilium and activate the channels. A computational model of this experiment allowed an estimate of the spatial distribution of the chloride channels. On average, the channels were concentrated in a narrow band centered at a distance of 29% of the ciliary length, measured from the base of the cilium. This matches the location of the CNG channels determined previously. This non-uniform distribution of transduction proteins is consistent with similar findings in other cilia. On average, the two types of olfactory transduction channel are concentrated in the same region of the cilium. This may contribute to the efficient detection of weak stimuli.

Method and Apparatus for Reducing the Vulnerability of Latches to Single Event Upsets

NASA Technical Reports Server (NTRS)

Shuler, Robert L., Jr. (Inventor)

2002-01-01

A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause the voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. The method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.

Method and Apparatus for Reducing the Vulnerability of Latches to Single Event Upsets

NASA Technical Reports Server (NTRS)

Shuler, Robert L., Jr. (Inventor)

2002-01-01

A delay circuit includes a first network having an input and an output node, a second network having an input and an output, the input of the second network being coupled to the output node of the first network. The first network and the second network are configured such that: a glitch at the input to the first network having a length of approximately one-half of a standard glitch time or less does not cause tile voltage at the output of the second network to cross a threshold, a glitch at the input to the first network having a length of between approximately one-half and two standard glitch times causes the voltage at the output of the second network to cross the threshold for less than the length of the glitch, and a glitch at the input to the first network having a length of greater than approximately two standard glitch times causes the voltage at the output of the second network to cross the threshold for approximately the time of the glitch. A method reduces the vulnerability of a latch to single event upsets. The latch includes a gate having an input and an output and a feedback path from the output to the input of the gate. The method includes inserting a delay into the feedback path and providing a delay in the gate.

Carbon-Nanotube-Confined Vertical Heterostructures with Asymmetric Contacts.

PubMed

Zhang, Jin; Zhang, Kenan; Xia, Bingyu; Wei, Yang; Li, Dongqi; Zhang, Ke; Zhang, Zhixing; Wu, Yang; Liu, Peng; Duan, Xidong; Xu, Yong; Duan, Wenhui; Fan, Shoushan; Jiang, Kaili

2017-10-01

Van der Waals (vdW) heterostructures have received intense attention for their efficient stacking methodology with 2D nanomaterials in vertical dimension. However, it is still a challenge to scale down the lateral size of vdW heterostructures to the nanometer and make proper contacts to achieve optimized performances. Here, a carbon-nanotube-confined vertical heterostructure (CCVH) is employed to address this challenge, in which 2D semiconductors are asymmetrically sandwiched by an individual metallic single-walled carbon nanotube (SWCNT) and a metal electrode. By using WSe 2 and MoS 2 , the CCVH can be made into p-type and n-type field effect transistors with high on/off ratios even when the channel length is 3.3 nm. A complementary inverter was further built with them, indicating their potential in logic circuits with a high integration level. Furthermore, the Fermi level of SWCNTs can be efficiently modulated by the gate voltage, making it competent for both electron and hole injection in the CCVHs. This unique property is shown by the transition of WSe 2 CCVH from unipolar to bipolar, and the transition of WSe 2 /MoS 2 from p-n junction to n-n junction under proper source-drain biases and gate voltages. Therefore, the CCVH, as a member of 1D/2D mixed heterostructures, shows great potentials in future nanoelectronics and nano-optoelectronics. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Investigation of impact of post-metallization annealing on reliability of 65 nm NOR floating-gate flash memories

NASA Astrophysics Data System (ADS)

Chiu, Shengfen; Xu, Yue; Ji, Xiaoli; Yan, Feng

2016-12-01

This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65 nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.

Electrically Tunable Energy Bandgap in Dual-Gated Ultra-Thin Black Phosphorus Field Effect Transistors

NASA Astrophysics Data System (ADS)

Yan, Shi-Li; Xie, Zhi-Jian; Chen, Jian-Hao; Taniguchi, Takashi; Watanabe, Kenji

2017-03-01

The energy bandgap is an intrinsic character of semiconductors, which largely determines their properties. The ability to continuously and reversibly tune the bandgap of a single device during real time operation is of great importance not only to device physics but also to technological applications. Here we demonstrate a widely tunable bandgap of few-layer black phosphorus (BP) by the application of vertical electric field in dual-gated BP field-effect transistors. A total bandgap reduction of 124 meV is observed when the electrical displacement field is increased from 0.10V/nm to 0.83V/nm. Our results suggest appealing potential for few-layer BP as a tunable bandgap material in infrared optoelectronics, thermoelectric power generation and thermal imaging.

Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation

NASA Astrophysics Data System (ADS)

Koike, Hiroki; Ohsawa, Takashi; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2015-04-01

A spintronic-based power-gated micro-processing unit (MPU) is proposed. It includes a power control circuit activated by the newly supported power-off instruction for the deep-sleep mode. These means enable the power-off procedure for the MPU to be executed appropriately. A test chip was designed and fabricated using 90 nm CMOS and an additional 100 nm MTJ process; it was successfully operated. The guideline of the energy reduction effects for this MPU was presented, using the estimation based on the measurement results of the test chip. The result shows that a large operation energy reduction of 1/28 can be achieved when the operation duty is 10%, under the condition of a sufficient number of idle clock cycles.

The effects of transistor source-to-gate bridging faults in complex CMOS gates

NASA Astrophysics Data System (ADS)

Visweswaran, G. S.; Ali, Akhtar-Uz-Zaman M.; Lala, Parag K.; Hartmann, Carlos R. P.

1991-06-01

A study of the effect of gate-to-source bridging faults in the pull-up section of a complex CMOS gate is presented. The manifestation of these faults depends on the resistance value of the connection causing the bridging. It is shown that such faults manifest themselves either as stuck-at or stuck-open faults and can be detected by tests for stuck-at and stuck-open faults generated for the equivalent logic current. It is observed that for transistor channel lengths larger than 1 microns there exists a range of values of the bridging resistance for which the fault behaves as a pseudo-stuck-open fault.

Double-gated Si NW FET sensors: Low-frequency noise and photoelectric properties

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gasparyan, F.; Forschungszentrum Jülich, Peter Grünberg Institute; Khondkaryan, H.

2016-08-14

The transport, noise, and photosensitivity properties of an array of silicon nanowire (NW) p{sup +}-p-p{sup +} field-effect transistors (FETs) are investigated. The peculiarities of photosensitivity and detectivity are analyzed over a wide spectrum range. The absorbance of p-Si NW shifts to the short wavelength region compared with bulk Si. The photocurrent and photosensitivity reach increased values in the UV range of the spectrum at 300 K. It is shown that sensitivity values can be tuned by the drain-source voltage and may reach record values of up to 2–4 A/W at a wavelength of 300 nm at room temperature. Low-frequency noise studies allow calculatingmore » the photodetectivity values, which increase with decreasing wavelength down to 300 nm. We show that the drain current of Si NW biochemical sensors substantially depends on pH value and the signal-to-noise ratio reaches the high value of 10{sup 5}. Increasing pH sensitivity with gate voltage is revealed for certain source-drain currents of pH-sensors based on Si NW FETs. The noise characteristic index decreases from 1.1 to 0.7 with the growth of the liquid gate voltage. Noise behavior is successfully explained in the framework of the correlated number-mobility unified fluctuation model. pH sensitivity increases as a result of the increase in liquid gate voltage, thus giving the opportunity to measure very low proton concentrations in the electrolyte medium at certain values of the liquid gate voltage.« less

Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement

NASA Astrophysics Data System (ADS)

Raad, Bhagwan Ram; Nigam, Kaushal; Sharma, Dheeraj; Kondekar, P. N.

2016-06-01

This script features a study of bandgap, gate material work function and gate dielectric engineering for enhancement of DC and Analog/RF performance, reduction in the hot carriers effect (HCEs) and drain induced barrier lowering (DIBL) for better device reliability. In this concern, the use of band gap and gate material work function engineering improves the device performance in terms of the ON-state current and suppressed ambipolar behaviour with maintaining the low OFF-state current. With these advantages, the use of gate material work function engineering imposes restriction on the high frequency performance due to increment in the parasitic capacitances and also introduces the hot carrier effects. Hence, the gate dielectric engineering with bandgap and gate material work function engineering are used in this paper to overcome the cons of the gate material work function engineering by obtaining a superior performance in terms of the current driving capability, ambipolar conduction, HCEs, DIBL and high frequency parameters of the device for ultra-low power applications. Finally, the optimization of length for different work function is performed to get the best out of this.

Direct detector for terahertz radiation

DOEpatents

Wanke, Michael C [Albuquerque, NM; Lee, Mark [Albuquerque, NM; Shaner, Eric A [Albuquerque, NM; Allen, S James [Santa Barbara, CA

2008-09-02

A direct detector for terahertz radiation comprises a grating-gated field-effect transistor with one or more quantum wells that provide a two-dimensional electron gas in the channel region. The grating gate can be a split-grating gate having at least one finger that can be individually biased. Biasing an individual finger of the split-grating gate to near pinch-off greatly increases the detector's resonant response magnitude over prior QW FET detectors while maintaining frequency selectivity. The split-grating-gated QW FET shows a tunable resonant plasmon response to FIR radiation that makes possible an electrically sweepable spectrometer-on-a-chip with no moving mechanical optical parts. Further, the narrow spectral response and signal-to-noise are adequate for use of the split-grating-gated QW FET in a passive, multispectral terahertz imaging system. The detector can be operated in a photoconductive or a photovoltaic mode. Other embodiments include uniform front and back gates to independently vary the carrier densities in the channel region, a thinned substrate to increase bolometric responsivity, and a resistive shunt to connect the fingers of the grating gate in parallel and provide a uniform gate-channel voltage along the length of the channel to increase the responsivity and improve the spectral resolution.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Proctor, Timothy; Rudinger, Kenneth; Young, Kevin

Randomized benchmarking (RB) is widely used to measure an error rate of a set of quantum gates, by performing random circuits that would do nothing if the gates were perfect. In the limit of no finite-sampling error, the exponential decay rate of the observable survival probabilities, versus circuit length, yields a single error metric r. For Clifford gates with arbitrary small errors described by process matrices, r was believed to reliably correspond to the mean, over all Clifford gates, of the average gate infidelity between the imperfect gates and their ideal counterparts. We show that this quantity is not amore » well-defined property of a physical gate set. It depends on the representations used for the imperfect and ideal gates, and the variant typically computed in the literature can differ from r by orders of magnitude. We present new theories of the RB decay that are accurate for all small errors describable by process matrices, and show that the RB decay curve is a simple exponential for all such errors. Here, these theories allow explicit computation of the error rate that RB measures (r), but as far as we can tell it does not correspond to the infidelity of a physically allowed (completely positive) representation of the imperfect gates.« less

Selected area growth integrated wavelength converter based on PD-EAM optical logic gate

NASA Astrophysics Data System (ADS)

Bin, Niu; Jifang, Qiu; Daibing, Zhou; Can, Zhang; Song, Liang; Dan, Lu; Lingjuan, Zhao; Jian, Wu; Wei, Wang

2014-09-01

A selected area growth wavelength converter based on a PD-EAM optical logic gate for WDM application is presented, integrating an EML transmitter and a SOA-PD receiver. The design, fabrication, and DC characters were analyzed. A 2 Gb/s NRZ signal based on the C-band wavelength converted to 1555 nm with the highest extinction ratio of 7 dB was achieved and wavelength converted eye diagrams with eyes opened were presented.

Gating electrical transport through DNA molecules that bridge between silicon nanogaps.

PubMed

Takagi, Shogo; Takada, Tadao; Matsuo, Naoto; Yokoyama, Shin; Nakamura, Mitsunobu; Yamana, Kazushige

2012-03-21

DNA electronic devices were prepared on silicon-based three-terminal electrodes. Both ends of DNA molecules (400 bp long, mixed sequences) were bridged via chemical bonds between the source-drain nanogap (120 nm) electrodes. S-Shaped I-V curves were obtained and the electric current can be modulated by the gate voltage. The DNA molecules act as semiconducting p-type nanowires in the three-terminal device. This journal is © The Royal Society of Chemistry 2012

Partial hyperbolicity and attracting regions in 3-dimensional manifolds

NASA Astrophysics Data System (ADS)

Potrie, Rafael

The need for reliable, fiber-based sources of entangled and paired photons has intensified in recent years because of potential uses in optical quantum communication and computing. In particular, indistinguishable photon sources are an inherent part of several quantum communication protocols and are needed to establish the viability of quantum communication networks. This thesis is centered around the development of such sources at telecommunication-band wavelengths. In this thesis, we describe experiments on entangled photon generation and the creation of quantum logic gates in the C-band, and on photon indistinguishability in the O-band. These experiments utilize the four-wave mixing process in fiber which occurs as a result of the Kerr nonlinearity, to create paired photons. To begin, we report the development of a source of 1550-nm polarization entangled photons in fiber. We then interface this source with a quantum Controlled-NOT gate, which is a universal quantum logic gate. We set experimental bounds on the process fidelity of the Controlled-NOT gate. Next, we report a demonstration of quantum interference between 1310-nm photons produced in independent sources. We demonstrate high quantum interference visibility, a signature of quantum indistinguishability, while using distinguishable pump photons. Together, these efforts constitute preliminary steps toward establishing the viability of fiber-based quantum communication, which will allow us to utilize existing infrastructure for implementing quantum communication protocols.

Impact of SiNx capping on the formation of source/drain contact for In-Ga-Zn-O thin film transistor with self-aligned gate

NASA Astrophysics Data System (ADS)

Oh, Himchan; Pi, Jae-Eun; Hwang, Chi-Sun; Kwon, Oh-Sang

2017-12-01

Self-aligned gate structures are preferred for faster operation and scaling down of thin film transistors by reducing the overlapped region between source/drain and gate electrodes. Doping on source/drain regions is essential to fabricate such a self-aligned gate thin film transistor. For oxide semiconductors such as In-Ga-Zn-O, SiNx capping readily increases their carrier concentration. We report that the SiNx deposition temperature and thickness significantly affect the device properties, including threshold voltage, field effect mobility, and contact resistance. The reason for these variations in device characteristics mainly comes from the extension of the doped region to the gated area after the SiNx capping step. Analyses on capacitance-voltage and transfer length characteristics support this idea.

Structural Characterization and Impedance Spectroscopy of Substituted, Fused-Ring Organic Semiconductors

NASA Astrophysics Data System (ADS)

Shaw, Charles Michael

Organic materials present a number of advantages over silicon that make them ideal candidates for modest performance devices like active matrix backplanes and RFID tags. The work detailed here describes both structural characterization of promising new materials, as well as the adaptation of impedance spectroscopy techniques to the study of organic transistors. Unit cells and solution casting behavior for dioctyl- and didodecyl-pentathienoacene are presented. Dioctyl pentathienoacene has an orthorhombic lattice with parameters a = 1.15 nm, b = 0.43 nm and c = 3.05 nm. Didodecyl pentathienoacene has an monoclinic lattice with parameters gamma = 92.2°, a = 1.10 urn, b = 0.42 nm and c = 3.89 nm. Additionally, thermotropic phase behavior is detailed. Both materials exhibit a "side chain melting" transition---characterized by a dramatic unit cell contraction of more than 20%---and smectic C liquid crystal phases. The side chain melting transition shows similarity to phase transitions elicited by exposing these materials to high energy electron flux. In both cases, disorder in the substitutions results in new phases for these materials. Dioctyl-pentathienoacene also exhibits a unique phase, which is intermediately ordered and shows a threefold increase in critical dose over the as-cast phase. Impedance spectroscopy of triisopropylsilyl pentacene transistors suggests these devices are well fit by a Voigt model equivalent circuit. The gate bias dependent resistor represents the channel conductance and the capacitor represents the drain-gate and source-gate capacitances. This in turn suggests that conduction occurs through delocalized states available in ordered regions, with disordered regions contributing localized, immobile states. Impedance spectroscopy of poly(2,5-bis(3-alkylthiophen-2-yl)thieno[3,2-b]thiophene) shows similar behavior. The use of variable temperature impedance spectroscopy is also demonstrated. This technique is used to measure the reduction in trap energy---from 200 meV to 140 meV---produced by annealing the material in its liquid crystal phase.

Using the Secondary Electrons (SE) of scanning electron microscope with NIST`s MONSEL-II program to obtain improved linewidth measurements and slope angles of line edges on a MMIC GaAs device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sartore, R.G.

1996-12-31

In the evaluation of GaAs devices from the MMIC (Monolithic Microwave Integrated Circuits) program for Army applications, there was a requirement to obtain accurate linewidth measurements on the nominal 0.5 micrometer gate lengths used to fabricate these devices. Preliminary measurements indicated a significant variation (typically 10% to 30% but could be more) in the critical dimensional measurements of the gate length, gate to source distance and gate to drain distance. Passivation introduced a margin of error, which was removed by plasma etching. Additionally, the high aspect ratio (4-5) of the thick gold (Au) conductors also introduced measurement difficulties. The finalmore » measurements were performed were performed after the thick gold conductor was removed and only the barrier metal remained, which was approximately 250 nanometer thick platinum on GaAs substrate. The thickness was measured using the penetration voltage method. Linescan of the secondary electron signal as it scans across the gate is shown in Figure 1. This linescan is an average of 5 linescans in the immediate vicinity to reduce noise levels. A SEM image of the area is shown in Figure 2. To obtain a rough estimate of the slopes of the gate lines at the edges, the sample was tilted to 75 degrees and the image in Figure 3 was obtained. From this figure a rough estimate of the sloped edges, using a protractor, was obtained, approximately 27 degrees, +/-5 degrees.« less

Epitaxial GeSn film formed by solid phase epitaxy and its application to Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor capacitors with sub-nm equivalent oxide thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Ching-Wei; Wu, Yung-Hsien; Hsieh, Ching-Heng

2014-11-17

Through the technique of solid phase epitaxy (SPE), an epitaxial Ge{sub 0.955}Sn{sub 0.045} film was formed on a Ge substrate by depositing an amorphous GeSn film followed by a rapid thermal annealing at 550 °C. A process that uses a SiO{sub 2} capping layer on the amorphous GeSn film during SPE was proposed and it prevents Sn precipitation from occurring while maintaining a smooth surface due to the reduced surface mobility of Sn atoms. The high-quality epitaxial GeSn film was observed to have single crystal structure, uniform thickness and composition, and tiny surface roughness with root mean square of 0.56 nm. Withmore » a SnO{sub x}-free surface, Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor (MOS) capacitors with equivalent oxide thickness (EOT) of 0.55 nm were developed. A small amount of traps inside the Yb{sub 2}O{sub 3} was verified by negligible hysteresis in capacitance measurement. Low leakage current of 0.4 A/cm{sup 2} at gate bias of flatband voltage (V{sub FB})-1 V suggests the high quality of the gate dielectric. In addition, the feasibility of using Yb{sub 2}O{sub 3} to well passivate GeSn surface was also evidenced by the small interface trap density (D{sub it}) of 4.02 × 10{sup 11} eV{sup −1} cm{sup −2}, which can be attributed to smooth GeSn surface and Yb{sub 2}O{sub 3} valency passivation. Both leakage current and D{sub it} performance outperform other passivation techniques at sub-nm EOT regime. The proposed epitaxial GeSn film along with Yb{sub 2}O{sub 3} dielectric paves an alternative way to enable high-performance GeSn MOS devices.« less

Nanowire systems: technology and design

PubMed Central

Gaillardon, Pierre-Emmanuel; Amarù, Luca Gaetano; Bobba, Shashikanth; De Marchi, Michele; Sacchetto, Davide; De Micheli, Giovanni

2014-01-01

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this study, we consider double independent gate, vertically stacked nanowire field effect transistors (FETs) with gate-all-around structures and typical diameter of 20 nm. These devices, which we have successfully fabricated and evaluated, control the ambipolar behaviour of the nanostructure by selectively enabling one type of carriers. These transistors work as switches with electrically programmable polarity and thus realize an exclusive or operation. The intrinsic higher expressive power of these FETs, when compared with standard complementary metal oxide semiconductor technology, enables us to realize more efficient logic gates, which we organize as tiles to realize nanowire systems by regular arrays. This article surveys both the technology for double independent gate FETs as well as physical and logic design tools to realize digital systems with this fabrication technology. PMID:24567471

Visible to short wavelength infrared In2Se3-nanoflake photodetector gated by a ferroelectric polymer

NASA Astrophysics Data System (ADS)

Wu, Guangjian; Wang, Xudong; Wang, Peng; Huang, Hai; Chen, Yan; Sun, Shuo; Shen, Hong; Lin, Tie; Wang, Jianlu; Zhang, Shangtao; Bian, Lifeng; Sun, Jinglan; Meng, Xiangjian; Chu, Junhao

2016-09-01

Photodetectors based on two-dimensional (2D) transition-metal dichalcogenides have been studied extensively in recent years. However, the detective spectral ranges, dark current and response time are still unsatisfactory, even under high gate and source-drain bias. In this work, the photodetectors of In2Se3 have been fabricated on a ferroelectric field effect transistor structure. Based on this structure, high performance photodetectors have been achieved with a broad photoresponse spectrum (visible to 1550 nm) and quick response (200 μs). Most importantly, with the intrinsic huge electric field derived from the polarization of ferroelectric polymer (P(VDF-TrFE)) gating, a low dark current of the photodetector can be achieved without additional gate bias. These studies present a crucial step for further practical applications for 2D semiconductors.

SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

NASA Astrophysics Data System (ADS)

Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

Simulation of temperature dependent dielectric breakdown in n{sup +}-polySi/SiO{sub 2}/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias

DOE Office of Scientific and Technical Information (OSTI.GOV)

Samanta, Piyas, E-mail: piyas@vcfw.org; Mandal, Krishna C., E-mail: mandalk@cec.sc.edu

2016-08-14

We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7–25 nm) silicon dioxide (SiO{sub 2}) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n{sup +}-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV belowmore » the SiO{sub 2} conduction band. Holes were generated in the n{sup +}-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness t{sub ox} and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields E{sub ox} ranging from 5 to 10 MV/cm. Our simulated time-to-breakdown (t{sub BD}) results are in excellent agreement with those obtained from time consuming TDDB measurements. It is observed that irrespective of stress temperatures, the t{sub BD} values estimated in the field range between 5 and 9 MV/cm better fit to reciprocal field (1/E) model for the thickness range studied here. Furthermore, for a 10 year projected device lifetime, a good reliability margin of safe operating field from 8.5 to 7.5 MV/cm for 7 nm and 8.1 to 6.9 MV/cm for 25 nm thick SiO{sub 2} was observed between 27 and 225 °C.« less

3D super resolution range-gated imaging for canopy reconstruction and measurement

NASA Astrophysics Data System (ADS)

Huang, Hantao; Wang, Xinwei; Sun, Liang; Lei, Pingshun; Fan, Songtao; Zhou, Yan

2018-01-01

In this paper, we proposed a method of canopy reconstruction and measurement based on 3D super resolution range-gated imaging. In this method, high resolution 2D intensity images are grasped by active gate imaging, and 3D images of canopy are reconstructed by triangular-range-intensity correlation algorithm at the same time. A range-gated laser imaging system(RGLIS) is established based on 808 nm diode laser and gated intensified charge-coupled device (ICCD) camera with 1392´1040 pixels. The proof experiments have been performed for potted plants located 75m away and trees located 165m away. The experiments show it that can acquire more than 1 million points per frame, and 3D imaging has the spatial resolution about 0.3mm at the distance of 75m and the distance accuracy about 10 cm. This research is beneficial for high speed acquisition of canopy structure and non-destructive canopy measurement.

Rewritable ghost floating gates by tunnelling triboelectrification for two-dimensional electronics

PubMed Central

Kim, Seongsu; Kim, Tae Yun; Lee, Kang Hyuck; Kim, Tae-Ho; Cimini, Francesco Arturo; Kim, Sung Kyun; Hinchet, Ronan; Kim, Sang-Woo; Falconi, Christian

2017-01-01

Gates can electrostatically control charges inside two-dimensional materials. However, integrating independent gates typically requires depositing and patterning suitable insulators and conductors. Moreover, after manufacturing, gates are unchangeable. Here we introduce tunnelling triboelectrification for localizing electric charges in very close proximity of two-dimensional materials. As representative materials, we use chemical vapour deposition graphene deposited on a SiO2/Si substrate. The triboelectric charges, generated by friction with a Pt-coated atomic force microscope tip and injected through defects, are trapped at the air–SiO2 interface underneath graphene and act as ghost floating gates. Tunnelling triboelectrification uniquely permits to create, modify and destroy p and n regions at will with the spatial resolution of atomic force microscopes. As a proof of concept, we draw rewritable p/n+ and p/p+ junctions with resolutions as small as 200 nm. Our results open the way to time-variant two-dimensional electronics where conductors, p and n regions can be defined on demand. PMID:28649986

Rewritable ghost floating gates by tunnelling triboelectrification for two-dimensional electronics

NASA Astrophysics Data System (ADS)

Kim, Seongsu; Kim, Tae Yun; Lee, Kang Hyuck; Kim, Tae-Ho; Cimini, Francesco Arturo; Kim, Sung Kyun; Hinchet, Ronan; Kim, Sang-Woo; Falconi, Christian

2017-06-01

Gates can electrostatically control charges inside two-dimensional materials. However, integrating independent gates typically requires depositing and patterning suitable insulators and conductors. Moreover, after manufacturing, gates are unchangeable. Here we introduce tunnelling triboelectrification for localizing electric charges in very close proximity of two-dimensional materials. As representative materials, we use chemical vapour deposition graphene deposited on a SiO2/Si substrate. The triboelectric charges, generated by friction with a Pt-coated atomic force microscope tip and injected through defects, are trapped at the air-SiO2 interface underneath graphene and act as ghost floating gates. Tunnelling triboelectrification uniquely permits to create, modify and destroy p and n regions at will with the spatial resolution of atomic force microscopes. As a proof of concept, we draw rewritable p/n+ and p/p+ junctions with resolutions as small as 200 nm. Our results open the way to time-variant two-dimensional electronics where conductors, p and n regions can be defined on demand.

Long Coherence Length 193 nm Laser for High-Resolution Nano-Fabrication

DTIC Science & Technology

2008-06-27

in the non-linear optical up-converter, as well as specifying their interaction lengths, phase -matching angles, coatings, temperatures of operation...when optical path differences between interfering beams become comparable to the temporal coherence length of the source, the fringe contrast diminishes...switched, intracavity frequency doubled Nd:YAG laser drives an optical parametric oscillator (OPO) running at 710 nm. A portion of the 532 nm light

Novel technique of source and drain engineering for dual-material double-gate (DMDG) SOI MOSFETS

NASA Astrophysics Data System (ADS)

Yadav, Himanshu; Malviya, Abhishek Kumar; Chauhan, R. K.

2018-04-01

The dual-metal dual-gate (DMDG) SOI has been used with Dual Sided Source and Drain Engineered 50nm SOI MOSFET with various high-k gate oxide. It has been scrutinized in this work to enhance its electrical performance. The proposed structure is designed by creating Dual Sided Source and Drain Modification and its characteristics are evaluated on ATLAS device simulator. The consequence of this dual sided assorted doping on source and drain side of the DMDG transistor has better leakage current immunity and heightened ION current with higher ION to IOFF Ratio. Which thereby vesting the proposed device appropriate for low power digital applications.

Application of high-quality SiO2 grown by multipolar ECR source to Si/SiGe MISFET

NASA Technical Reports Server (NTRS)

Sung, K. T.; Li, W. Q.; Li, S. H.; Pang, S. W.; Bhattacharya, P. K.

1993-01-01

A 5 nm-thick SiO2 gate was grown on an Si(p+)/Si(0.8)Ge(0.2) modulation-doped heterostructure at 26 C with an oxygen plasma generated by a multipolar electron cyclotron resonance source. The ultrathin oxide has breakdown field above 12 MV/cm and fixed charge density about 3 x 10 exp 10/sq cm. Leakage current as low as 1/micro-A was obtained with the gate biased at 4 V. The MISFET with 0.25 x 25 sq m gate shows maximum drain current of 41.6 mA/mm and peak transconductance of 21 mS/mm.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Choi, Hyun-Sik; Jeon, Sanghun, E-mail: jeonsh@korea.ac.kr

Upon light exposure, an indium-zinc-oxide (IZO) thin-film transistor (TFT) presents higher photoconductivity by several orders of magnitude at the negative gate bias region. Among various device geometrical factors, scaling down the channel length of the photo-transistor results in an anomalous increase in photoconductivity. To probe the origin of this high photoconductivity in short-channel device, we measured transient current, current–voltage, and capacitance–voltage characteristics of IZO–TFTs with various channel lengths and widths before and after illumination. Under the illumination, the equilibrium potential region which lies far from front interface exists only in short-channel devices, forming the un-depleted conducting back channel. This regionmore » plays an important role in carrier transport under the illumination, leading to high photoconductivity in short-channel devices. Photon exposure coupled with gate-modulated band bending for short-channel devices leads to the accumulation of V{sub o}{sup ++} at the front channel and screening negative gate bias, thereby generating high current flow in the un-depleted back-channel region.« less

Structure and symmetry inform gating principles of ionotropic glutamate receptors.

PubMed

Zhu, Shujia; Gouaux, Eric

2017-01-01

Ionotropic glutamate receptors (iGluRs) transduce signals derived from release of the excitatory neurotransmitter glutamate from pre-synaptic neurons into excitation of post-synaptic neurons on a millisecond time-scale. In recent years, the elucidation of full-length iGluR structures of NMDA, AMPA and kainate receptors by X-ray crystallography and single particle cryo-electron microscopy has greatly enhanced our understanding of the interrelationships between receptor architecture and gating mechanism. Here we briefly review full-length iGluR structures and discuss the similarities and differences between NMDA receptors and non-NMDA iGluRs. We focus on distinct conformations, including ligand-free, agonist-bound active, agonist-bound desensitized and antagonist-bound conformations as well as modulator and auxiliary protein-bound states. These findings provide insights into structure-based mechanisms of iGluR gating and modulation which together shape the amplitude and time course of the excitatory postsynaptic potential. This article is part of the Special Issue entitled 'Ionotropic glutamate receptors'. Copyright © 2016 Elsevier Ltd. All rights reserved.

Flash lamp-excited time-resolved fluorescence microscope suppresses autofluorescence in water concentrates to deliver an 11-fold increase in signal-to-noise ratio.

PubMed

Connally, Russell; Veal, Duncan; Piper, James

2004-01-01

The ubiquity of naturally fluorescing components (autofluorophores) encountered in most biological samples hinders the detection and identification of labeled targets through fluorescence-based techniques. Time-resolved fluorescence (TRF) is a technique by which the effects of autofluorescence are reduced by using specific fluorescent labels with long fluorescence lifetimes (compared with autofluorophores) in conjunction with time-gated detection. A time-resolved fluorescence microscope (TRFM) is described that is based on a standard epifluorescence microscope modified by the addition of a pulsed excitation source and an image-intensified time-gateable CCD camera. The choice of pulsed excitation source for TRFM has a large impact on the price and performance of the instrument. A flash lamp with rapid discharge characteristics was selected for our instrument because of the high spectral energy in the UV region and short pulse length. However, the flash output decayed with an approximate lifetime of 18 micros and the TRFM required a long-lived lanthanide chelate label to ensure that probe fluorescence was visible after decay of the flash plasma. We synthesized a recently reported fluorescent chelate (BHHCT) and conjugated it to a monoclonal antibody directed against the waterborne parasite Giardia lamblia. For a 600-nm bandpass filter set and a gate delay of 60 micros, the TRFM provided an 11.3-fold improvement in the signal-to-noise ratio (S/N) of labeled Giardia over background. A smaller gain in an SNR of 9.69-fold was achieved with a 420-nm longpass filter set; however, the final contrast ratio between labeled cyst and background was higher (11.3 versus 8.5). Despite the decay characteristics of the light pulse, flash lamps have many practical advantages compared with optical chopper wheels and modulated lasers for applications in TRFM.

Electrical Characteristics of Organic Field Effect Transistor Formed by Gas Treatment of High-k Al2O3 at Low Temperature

NASA Astrophysics Data System (ADS)

Lee, Sunwoo; Yoon, Seungki; Park, In-Sung; Ahn, Jinho

2009-04-01

We studied the electrical characteristics of an organic field effect transistor (OFET) formed by the hydrogen (H2) and nitrogen (N2) mixed gas treatment of a gate dielectric layer. We also investigated how device mobility is related to the length and width variations of the channel. Aluminum oxide (Al2O3) was used as the gate dielectric layer. After the treatment, the mobility and subthreshold swing were observed to be significantly improved by the decreased hole carrier localization at the interfacial layer between the gate oxide and pentacene channel layers. H2 gas plays an important role in removing the defects of the gate oxide layer at temperatures below 100 °C.

Structure of the full-length TRPV2 channel by cryo-EM

NASA Astrophysics Data System (ADS)

Huynh, Kevin W.; Cohen, Matthew R.; Jiang, Jiansen; Samanta, Amrita; Lodowski, David T.; Zhou, Z. Hong; Moiseenkova-Bell, Vera Y.

2016-03-01

Transient receptor potential (TRP) proteins form a superfamily Ca2+-permeable cation channels regulated by a range of chemical and physical stimuli. Structural analysis of a `minimal' TRP vanilloid subtype 1 (TRPV1) elucidated a mechanism of channel activation by agonists through changes in its outer pore region. Though homologous to TRPV1, other TRPV channels (TRPV2-6) are insensitive to TRPV1 activators including heat and vanilloids. To further understand the structural basis of TRPV channel function, we determined the structure of full-length TRPV2 at ~5 Å resolution by cryo-electron microscopy. Like TRPV1, TRPV2 contains two constrictions, one each in the pore-forming upper and lower gates. The agonist-free full-length TRPV2 has wider upper and lower gates compared with closed and agonist-activated TRPV1. We propose these newly revealed TRPV2 structural features contribute to diversity of TRPV channels.

Structure of the full-length TRPV2 channel by cryo-EM

PubMed Central

Huynh, Kevin W.; Cohen, Matthew R.; Jiang, Jiansen; Samanta, Amrita; Lodowski, David T.; Zhou, Z. Hong; Moiseenkova-Bell, Vera Y.

2016-01-01

Transient receptor potential (TRP) proteins form a superfamily Ca2+-permeable cation channels regulated by a range of chemical and physical stimuli. Structural analysis of a ‘minimal' TRP vanilloid subtype 1 (TRPV1) elucidated a mechanism of channel activation by agonists through changes in its outer pore region. Though homologous to TRPV1, other TRPV channels (TRPV2–6) are insensitive to TRPV1 activators including heat and vanilloids. To further understand the structural basis of TRPV channel function, we determined the structure of full-length TRPV2 at ∼5 Å resolution by cryo-electron microscopy. Like TRPV1, TRPV2 contains two constrictions, one each in the pore-forming upper and lower gates. The agonist-free full-length TRPV2 has wider upper and lower gates compared with closed and agonist-activated TRPV1. We propose these newly revealed TRPV2 structural features contribute to diversity of TRPV channels. PMID:27021073

Structure of the full-length TRPV2 channel by cryo-EM.

PubMed

Huynh, Kevin W; Cohen, Matthew R; Jiang, Jiansen; Samanta, Amrita; Lodowski, David T; Zhou, Z Hong; Moiseenkova-Bell, Vera Y

2016-03-29

Transient receptor potential (TRP) proteins form a superfamily Ca(2+)-permeable cation channels regulated by a range of chemical and physical stimuli. Structural analysis of a 'minimal' TRP vanilloid subtype 1 (TRPV1) elucidated a mechanism of channel activation by agonists through changes in its outer pore region. Though homologous to TRPV1, other TRPV channels (TRPV2-6) are insensitive to TRPV1 activators including heat and vanilloids. To further understand the structural basis of TRPV channel function, we determined the structure of full-length TRPV2 at ∼5 Å resolution by cryo-electron microscopy. Like TRPV1, TRPV2 contains two constrictions, one each in the pore-forming upper and lower gates. The agonist-free full-length TRPV2 has wider upper and lower gates compared with closed and agonist-activated TRPV1. We propose these newly revealed TRPV2 structural features contribute to diversity of TRPV channels.

Device and circuit analysis of a sub 20 nm double gate MOSFET with gate stack using a look-up-table-based approach

NASA Astrophysics Data System (ADS)

Chakraborty, S.; Dasgupta, A.; Das, R.; Kar, M.; Kundu, A.; Sarkar, C. K.

2017-12-01

In this paper, we explore the possibility of mapping devices designed in TCAD environment to its modeled version developed in cadence virtuoso environment using a look-up table (LUT) approach. Circuit simulation of newly designed devices in TCAD environment is a very slow and tedious process involving complex scripting. Hence, the LUT based modeling approach has been proposed as a faster and easier alternative in cadence environment. The LUTs are prepared by extracting data from the device characteristics obtained from device simulation in TCAD. A comparative study is shown between the TCAD simulation and the LUT-based alternative to showcase the accuracy of modeled devices. Finally the look-up table approach is used to evaluate the performance of circuits implemented using 14 nm nMOSFET.

A films based approach to intensity imbalance correction for 65nm node c:PSM

NASA Astrophysics Data System (ADS)

Cottle, Rand; Sixt, Pierre; Lassiter, Matt; Cangemi, Marc; Martin, Patrick; Progler, Chris

2005-11-01

Intensity imbalance between the 0 and π phase features of c:PSM cause gate CD control and edge placement problems. Strategies such as undercut, selective biasing, and combinations of undercut and bias are currently used in production to mitigate these problems. However, there are drawbacks to these strategies such as space CD delta through pitch, gate CD control through defocus, design rule restrictions, and reticle manufacturability. This paper investigates the application of an innovative films-based approach to intensity balancing known as the Transparent Etch Stop Layer (TESL). TESL, in addition to providing a host of reticle quality and manufacturability benefits, also can be tuned to significantly reduce imbalance. Rigorous 3D vector simulations and experimental data compare through pitch and defocus performance of TESL and conventional c:PSM for 65nm design rules.

A Pearson Effective Potential for Monte Carlo Simulation of Quantum Confinement Effects in nMOSFETs

NASA Astrophysics Data System (ADS)

Jaud, Marie-Anne; Barraud, Sylvain; Saint-Martin, Jérôme; Bournel, Arnaud; Dollfus, Philippe; Jaouen, Hervé

2008-12-01

A Pearson Effective Potential model for including quantization effects in the simulation of nanoscale nMOSFETs has been developed. This model, based on a realistic description of the function representing the non zero-size of the electron wave packet, has been used in a Monte-Carlo simulator for bulk, single gate SOI and double-gate SOI devices. In the case of SOI capacitors, the electron density has been computed for a large range of effective field (between 0.1 MV/cm and 1 MV/cm) and for various silicon film thicknesses (between 5 nm and 20 nm). A good agreement with the Schroedinger-Poisson results is obtained both on the total inversion charge and on the electron density profiles. The ability of an Effective Potential approach to accurately reproduce electrostatic quantum confinement effects is clearly demonstrated.

An Al₂O₃ Gating Substrate for the Greater Performance of Field Effect Transistors Based on Two-Dimensional Materials.

PubMed

Yang, Hang; Qin, Shiqiao; Zheng, Xiaoming; Wang, Guang; Tan, Yuan; Peng, Gang; Zhang, Xueao

2017-09-22

We fabricated 70 nm Al₂O₃ gated field effect transistors based on two-dimensional (2D) materials and characterized their optical and electrical properties. Studies show that the optical contrast of monolayer graphene on an Al₂O₃/Si substrate is superior to that on a traditional 300 nm SiO₂/Si substrate (2.4 times). Significantly, the transconductance of monolayer graphene transistors on the Al₂O₃/Si substrate shows an approximately 10-fold increase, due to a smaller dielectric thickness and a higher dielectric constant. Furthermore, this substrate is also suitable for other 2D materials, such as WS₂, and can enhance the transconductance remarkably by 61.3 times. These results demonstrate a new and ideal substrate for the fabrication of 2D materials-based electronic logic devices.

Placement of clock gates in time-of-flight optoelectronic circuits

NASA Astrophysics Data System (ADS)

Feehrer, John R.; Jordan, Harry F.

1995-12-01

Time-of-flight synchronized optoelectronic circuits capitalize on the highly controllable delays of optical waveguides. Circuits have no latches; synchronization is achieved by adjustment of the lengths of waveguides that connect circuit elements. Clock gating and pulse stretching are used to restore timing and power. A functional circuit requires that every feedback loop contain at least one clock gate to prevent cumulative timing drift and power loss. A designer specifies an ideal circuit, which contains no or very few clock gates. To make the circuit functional, we must identify locations in which to place clock gates. Because clock gates are expensive, add area, and increase delay, a minimal set of locations is desired. We cast this problem in graph-theoretical form as the minimum feedback edge set problem and solve it by using an adaptation of an algorithm proposed in 1966 [IEEE Trans. Circuit Theory CT-13, 399 (1966)]. We discuss a computer-aided-design implementation of the algorithm that reduces computational complexity and demonstrate it on a set of circuits.

Tuning the allosteric regulation of artificial muscarinic and dopaminergic ligand-gated potassium channels by protein engineering of G protein-coupled receptors

PubMed Central

Moreau, Christophe J.; Revilloud, Jean; Caro, Lydia N.; Dupuis, Julien P.; Trouchet, Amandine; Estrada-Mondragón, Argel; Nieścierowicz, Katarzyna; Sapay, Nicolas; Crouzy, Serge; Vivaudou, Michel

2017-01-01

Ligand-gated ion channels enable intercellular transmission of action potential through synapses by transducing biochemical messengers into electrical signal. We designed artificial ligand-gated ion channels by coupling G protein-coupled receptors to the Kir6.2 potassium channel. These artificial channels called ion channel-coupled receptors offer complementary properties to natural channels by extending the repertoire of ligands to those recognized by the fused receptors, by generating more sustained signals and by conferring potassium selectivity. The first artificial channels based on the muscarinic M2 and the dopaminergic D2L receptors were opened and closed by acetylcholine and dopamine, respectively. We find here that this opposite regulation of the gating is linked to the length of the receptor C-termini, and that C-terminus engineering can precisely control the extent and direction of ligand gating. These findings establish the design rules to produce customized ligand-gated channels for synthetic biology applications. PMID:28145461

Determination of carrier diffusion length in p- and n-type GaN

NASA Astrophysics Data System (ADS)

Hafiz, Shopan; Metzner, Sebastian; Zhang, Fan; Monavarian, Morteza; Avrutin, Vitaliy; Morkoç, Hadis; Karbaum, Christopher; Bertram, Frank; Christen, Jürgen; Gil, Bernard; Özgür, Ümit

2014-03-01

Diffusion lengths of photo-excited carriers along the c-direction were determined from photoluminescence (PL) measurements in p- and n-type GaN epitaxial layers grown on c-plane sapphire by metal-organic chemical vapor deposition. The investigated samples incorporate a 6 nm thick In0.15Ga0.85N active layer capped with either 500 nm p- GaN or 1300 nm n-GaN. The top GaN layers were etched in steps and PL from the InGaN active region and the underlying layers was monitored as a function of the top GaN thickness upon photogeneration near the surface region by above bandgap excitation. Taking into consideration the absorption in the active and underlying layers, the diffusion lengths at 295 K and at 15 K were measured to be about 92 ± 7 nm and 68 ± 7 nm for Mg-doped p-type GaN and 432 ± 30 nm and 316 ± 30 nm for unintentionally doped n-type GaN, respectively. Cross-sectional cathodoluminescence line-scan measurement was performed on a separate sample and the diffusion length in n-type GaN was measured to be 280 nm.

Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory; Edmonds, Larry D.; Swift, Gary; Carmichael, Carl; Tseng, Chen Wei; Heldt, Kevin; Anderson, Scott Arlo; Coe, Michael

2010-01-01

We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilins Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.

Switches from pi- to sigma-bonding complexes controlled by gate voltages.

PubMed

Matsui, Eriko; Harnack, Oliver; Matsuzawa, Nobuyuki N; Yasuda, Akio

2005-10-01

A conjugated polymer/metal ion/liquid-crystal molecular system was set between source and drain electrodes with a 100 nm gap. When gate voltage (Vg) increases, the current between source and drain electrodes increases. Infrared spectra show this system to be composed of pi and sigma complexes. At Vg = 0, the pi complex dominates the sigma complex, whereas the sigma complex becomes dominant when Vg is switched on. Calculations found that the pi complex has lower conductivity than the sigma complex.

Hierarchical roughness of sticky and non-sticky superhydrophobic surfaces

NASA Astrophysics Data System (ADS)

Raza, Muhammad Akram; Kooij, Stefan; van Silfhout, Arend; Zandvliet, Harold; Poelsema, Bene; Physics Of Interfaces; Nanomaterials Team

2011-03-01

The importance of superhydrophobic substrates (contact angle > 150 r withslidingangle 10 r) inmoderntechnologyisundeniable . Wepresentasimplecolloidalroutetomanufacturesuperstructuredarrayswithsingle - andmulti - length - scaledroughnesstoobtainstickyandnon - stickysuperhydrophobicsurfaces . Thelargestlengthscaleisprovidedby (multi -) layersofsilicaspheres (1 μ m, 500nm and 150nm diameter). Decoration with gold nanoparticles (14nm, 26nm and 47nm) gives rise to a second length scale. To lower the surface energy, gold nanoparticles are functionalized with dodecanethiol and the silica spheres by perfluorooctyltriethoxysilane. The morphology was examined by helium ion microscopy (HIM), while wettability measurements were performed by using the sessile drop method. We conclude that wettability can be controlled by changing the surface chemistry and/or length scales of the structures. To achieve truly non-sticky superhydrophobic surfaces, hierarchical roughness plays a vital role.

Voltage tunable plasmon propagation in dual gated bilayer graphene

NASA Astrophysics Data System (ADS)

Farzaneh, Seyed M.; Rakheja, Shaloo

2017-10-01

In this paper, we theoretically investigate plasmon propagation characteristics in AB and AA stacked bilayer graphene (BLG) in the presence of energy asymmetry due to an electrostatic field oriented perpendicularly to the plane of the graphene sheet. We first derive the optical conductivity of BLG using the Kubo formalism incorporating energy asymmetry and finite electron scattering. All results are obtained for room temperature (300 K) operation. By solving Maxwell's equations in a dual gate device setup, we obtain the wavevector of propagating plasmon modes in the transverse electric (TE) and transverse magnetic (TM) directions at terahertz frequencies. The plasmon wavevector allows us to compare the compression factor, propagation length, and the mode confinement of TE and TM plasmon modes in bilayer and monolayer graphene sheets and also to study the impact of material parameters on plasmon characteristics. Our results show that the energy asymmetry can be harnessed to increase the propagation length of TM plasmons in BLG. AA stacked BLG shows a larger increase in the propagation length than AB stacked BLG; conversely, it is very insensitive to the Fermi level variations. Additionally, the dual gate structure allows independent modulation of the energy asymmetry and the Fermi level in BLG, which is advantageous for reconfiguring plasmon characteristics post device fabrication.

Hierarchical roughness of sticky and non-sticky superhydrophobic surfaces

NASA Astrophysics Data System (ADS)

Raza, Muhammad; Kooij, Stefan; van Silfhout, Arend; Zandvliet, Harold; Poelsema, Bene

2011-11-01

The importance of superhydrophobic substrates (contact angle >150° with sliding angle <10°) in modern technology is undeniable. We present a simple colloidal route to manufacture superstructured arrays with single- and multi-length-scaled roughness to obtain sticky and non-sticky superhydrophobic surfaces. The largest length scale is provided by (multi-)layers of silica spheres (1 μm, 500nm and 150nm diameter). Decoration with gold nanoparticles (14nm, 26nm and 47nm) gives rise to a second length scale. To lower the surface energy, gold nanoparticles are functionalized with dodecanethiol and the silica spheres by perfluorooctyltriethoxysilane. The morphology was examined by helium ion microscopy (HIM), while wettability measurements were performed by using the sessile drop method. We conclude that wettability can be controlled by changing the surface chemistry and/or length scales of the structures. To achieve truly non-sticky superhydrophobic surfaces, hierarchical roughness plays a vital role.

A smart temperature and magnetic-responsive gating carbon nanotube membrane for ion and protein transportation

PubMed Central

Cong, Hailin; Xu, Xiaodan; Yu, Bing; Yang, Zhaohui; Zhang, Xiaoyan

2016-01-01

Carbon nanotube (CNT) nanoporous membranes based on pre-aligned CNTs have superior nano-transportation properties in biological science. Herein, we report a smart temperature- and temperature-magnetic-responsive CNT nanoporous membrane (CNM) by grafting thermal-sensitive poly(N-isopropylacrylamide) (PNIPAM) and Fe3O4 nanoparticles (Fe3O4-NPs) on the open ends of pre-aligned CNTs with a diameter around 15 nm via surface-initiated atom transfer radical polymerization (SI-ATRP) method. The inner cavity of the modified CNTs in the membrane is designed to be the only path for ion and protein transportation, and its effective diameter with a variation from ~5.7 nm to ~12.4 nm can be reversible tuned by temperature and magnetic field. The PNIPAM modified CNM (PNIPAM-CNM) and PNIPAM magnetic nanoparticles modified CNM (PNIPAM-MAG-CNM) exhibit excellent temperature- or temperature-magnetic-responsive gating property to separate proteins of different sizes. The PNIPAM-CNMs and PNIPAM-MAG-CNMs have potential applications in making artificial cells, biosensors, bioseparation and purification filters. PMID:27535103

A Cu²⁺-selective fluorescent chemosensor based on BODIPY with two pyridine ligands and logic gate.

PubMed

Huang, Liuqian; Zhang, Jing; Yu, Xiaoxiu; Ma, Yifan; Huang, Tianjiao; Shen, Xi; Qiu, Huayu; He, Xingxing; Yin, Shouchun

2015-06-15

A novel near-infrared fluorescent chemosensor based on BODIPY (Py-1) has been synthesized and characterized. Py-1 displays high selectivity and sensitivity for sensing Cu(2+) over other metal ions in acetonitrile. Upon addition of Cu(2+) ions, the maximum absorption band of Py-1 in CH3CN displays a red shift from 603 to 608 nm, which results in a visual color change from pink to blue. When Py-1 is excited at 600 nm in the presence of Cu(2+), the fluorescent emission intensity of Py-1 at 617 nm is quenched over 86%. Notably, the complex of Py-1-Cu(2+) can be restored with the introduction of EDTA or S(2-). Consequently, an IMPLICATION logic gate at molecular level operating in fluorescence mode with Cu(2+) and S(2-) as chemical inputs can be constructed. Finally, based on the reversible and reproducible system, a nanoscale sequential memory unit displaying "Writing-Reading-Erasing-Reading" functions can be integrated. Copyright © 2015 Elsevier B.V. All rights reserved.

The active modulation of drug release by an ionic field effect transistor for an ultra-low power implantable nanofluidic system.

PubMed

Bruno, Giacomo; Canavese, Giancarlo; Liu, Xuewu; Filgueira, Carly S; Sacco, Adriano; Demarchi, Danilo; Ferrari, Mauro; Grattoni, Alessandro

2016-11-10

We report an electro-nanofluidic membrane for tunable, ultra-low power drug delivery employing an ionic field effect transistor. Therapeutic release from a drug reservoir was successfully modulated, with high energy efficiency, by actively adjusting the surface charge of slit-nanochannels 50, 110, and 160 nm in size, by the polarization of a buried gate electrode and the consequent variation of the electrical double layer in the nanochannel. We demonstrated control over the transport of ionic species, including two relevant hypertension drugs, atenolol and perindopril, that could benefit from such modulation. By leveraging concentration-driven diffusion, we achieve a 2 to 3 order of magnitude reduction in power consumption as compared to other electrokinetic phenomena. The application of a small gate potential (±5 V) in close proximity (150 nm) of 50 nm nanochannels generated a sufficiently strong electric field, which doubled or blocked the ionic flux depending on the polarity of the voltage applied. These compelling findings can lead to next generation, more reliable, smaller, and longer lasting drug delivery implants with ultra-low power consumption.

UV-light-induced one-color and two-color photorefractive effects in congruent and near-stoichiometric LiNbO 3:Mg crystals

NASA Astrophysics Data System (ADS)

Qiao, Haijun; Xu, Jingjun; Tomita, Yasuo; Zhu, Dengsong; Fu, Bo; Zhang, Guoquan; Zhang, Guangyin

2007-03-01

We describe the ultraviolet-light one-color photorefraction (UV-OPR) at 351 nm in LiNbO3 crystals with different Mg-doping concentrations and [Li]/[Nb] ratios. It is shown that as the Mg-doping concentration and/or the [Li]/[Nb] ratio increase, the refractive index change and the two-beam coupling gain increase but the response time decreases. It is also shown that the recording sensitivity as large as ∼27 cm/J is obtainable at a recording intensity of ∼1 W/cm2 in near-stoichiometric LiNbO3 doped with 2 mol% Mg. This sensitivity is approximately one order of magnitude higher than those for other LiNbO3 crystals. We also describe the ultraviolet-light-gating two-color photorefraction (UV-TPR) using 365 nm gating and 633 nm recording beams in LiNbO3 crystals with different Mg-doping concentrations and [Li]/[Nb] ratios. It is shown that UV-TPR is only observed in near-stoichiometric crystals and the grating-formation dynamics strongly depend on the Mg concentration.

Driving qubit phase gates with sech shaped pulses

NASA Astrophysics Data System (ADS)

Long, Junling; Ku, Hsiang-Sheng; Wu, Xian; Lake, Russell; Barnes, Edwin; Economou, Sophia; Pappas, David

As shown in 1932 by Rozen and Zener, the Rabi model has a unique solution whereby, for a given pulse length or amplitude, a sech(t/sigma) shaped pulse can be used to drive complete oscillations around the Bloch sphere that are independent of detuning with only a resultant detuning-dependent phase accumulation. Using this property, single qubit phase gates and two-qubit CZ gates have been proposed. In this work we explore the effect of different drive pulse shapes, i.e. square, Gaussian, and sech, as a function of detuning for Rabi oscillations of a superconducting transmon qubit. An arbitrary, single-qubit phase gate is demonstrated with the sech(t/sigma) pulse, and full tomography is performed to extract the fidelity. This is the first step towards high fidelity, low leakage two qubit CZ gates, and illustrates the efficacy of using analytic solutions of the qubit drive prior to optimal pulse shaping.

Gate-driven pure spin current in graphene

NASA Astrophysics Data System (ADS)

Lin, Xiaoyang; Su, Li; Zhang, Youguang; Bournel, Arnaud; Zhang, Yue; Klein, Jacques-Olivier; Zhao, Weisheng; Fert, Albert

An important challenge of spin current based devices is to realize long-distance transport and efficient manipulation of pure spin current without frequent spin-charge conversions. Here, the mechanism of gate-driven pure spin current in graphene is presented. Such a mechanism relies on the electrical gating of conductivity and spin diffusion length in graphene. The gate-driven feature is adopted to realize the pure spin current demultiplexing operation, which enables gate-controllable distribution of the pure spin current into graphene branches. Compared with Elliot-Yafet spin relaxation mechanism, D'yakonov-Perel spin relaxation mechanism results in more appreciable demultiplexing performance, which also implies a feasible strategy to characterize the spin relaxation mechanisms. The unique feature of the pure spin current demultiplexing operation would pave a way for ultra-low power spin logic beyond CMOS. Supported by the NSFC (61627813, 51602013) and the 111 project (B16001).

Analysis of e-beam impact on the resist stack in e-beam lithography process

NASA Astrophysics Data System (ADS)

Indykeiwicz, K.; Paszkiewicz, B.

2013-07-01

Paper presents research on the sub-micron gate, AlGaN /GaN HEMT type transistors, fabrication by e-beam lithography and lift-off technique. The impact of the electron beam on the resists layer and the substrate was analyzed by MC method in Casino v3.2 software. The influence of technological process parameters on the metal structures resolution and quality for paths 100 nm, 300 nm and 500 nm wide and 20 μm long was studied. Qualitative simulation correspondences to the conducted experiments were obtained.

Single layer of Ge quantum dots in HfO2 for floating gate memory capacitors.

PubMed

Lepadatu, A M; Palade, C; Slav, A; Maraloiu, A V; Lazanu, S; Stoica, T; Logofatu, C; Teodorescu, V S; Ciurea, M L

2017-04-28

High performance trilayer memory capacitors with a floating gate of a single layer of Ge quantum dots (QDs) in HfO 2 were fabricated using magnetron sputtering followed by rapid thermal annealing (RTA). The layer sequence of the capacitors is gate HfO 2 /floating gate of single layer of Ge QDs in HfO 2 /tunnel HfO 2 /p-Si wafers. Both Ge and HfO 2 are nanostructured by RTA at moderate temperatures of 600-700 °C. By nanostructuring at 600 °C, the formation of a single layer of well separated Ge QDs with diameters of 2-3 nm at a density of 4-5 × 10 15 m -2 is achieved in the floating gate (intermediate layer). The Ge QDs inside the intermediate layer are arranged in a single layer and are separated from each other by HfO 2 nanocrystals (NCs) about 8 nm in diameter with a tetragonal/orthorhombic structure. The Ge QDs in the single layer are located at the crossing of the HfO 2 NCs boundaries. In the intermediate layer, besides Ge QDs, a part of the Ge atoms is segregated by RTA at the HfO 2 NCs boundaries, while another part of the Ge atoms is present inside the HfO 2 lattice stabilizing the tetragonal/orthorhombic structure. The fabricated capacitors show a memory window of 3.8 ± 0.5 V and a capacitance-time characteristic with 14% capacitance decay in the first 3000-4000 s followed by a very slow capacitance decrease extrapolated to 50% after 10 years. This high performance is mainly due to the floating gate of a single layer of well separated Ge QDs in HfO 2 , distanced from the Si substrate by the tunnel oxide layer with a precise thickness.

Twenty Years of Rad-Hard K14 SPAD in Space Projects

PubMed Central

Michálek, Vojtěch; Procházka, Ivan; Blažej, Josef

2015-01-01

During last two decades, several photon counting detectors have been developed in our laboratory. One of the most promising detector coming from our group silicon K14 Single Photon Avalanche Diode (SPAD) is presented with its valuable features and space applications. Based on the control electronics, it can be operated in both gated and non-gated mode. Although it was designed for photon counting detection, it can be employed for multiphoton detection as well. With respect to control electronics employed, the timing jitter can be as low as 20 ps RMS. Detection efficiency is about 40 % in range of 500 nm to 800 nm. The detector including gating and quenching circuitry has outstanding timing stability. Due to its radiation resistivity, the diode withstands 100 krad gamma ray dose without parameters degradation. Single photon detectors based on K14 SPAD were used for planetary altimeter and atmospheric lidar in MARS92/96 and Mars Surveyor ’98 space projects, respectively. Recent space applications of K14 SPAD comprises LIDAR and mainly time transfer between ground stations and artificial satellites. These include Laser Time Transfer, Time Transfer by Laser Link, and European Laser Timing projects. PMID:26213945

All-Aluminum Thin Film Transistor Fabrication at Room Temperature

PubMed Central

Yao, Rihui; Zheng, Zeke; Zeng, Yong; Liu, Xianzhe; Ning, Honglong; Hu, Shiben; Tao, Ruiqiang; Chen, Jianqiu; Cai, Wei; Xu, Miao; Wang, Lei; Lan, Linfeng; Peng, Junbiao

2017-01-01

Bottom-gate all-aluminum thin film transistors with multi conductor/insulator nanometer heterojunction were investigated in this article. Alumina (Al2O3) insulating layer was deposited on the surface of aluminum doping zinc oxide (AZO) conductive layer, as one AZO/Al2O3 heterojunction unit. The measurements of transmittance electronic microscopy (TEM) and X-ray reflectivity (XRR) revealed the smooth interfaces between ~2.2-nm-thick Al2O3 layers and ~2.7-nm-thick AZO layers. The devices were entirely composited by aluminiferous materials, that is, their gate and source/drain electrodes were respectively fabricated by aluminum neodymium alloy (Al:Nd) and pure Al, with Al2O3/AZO multilayered channel and AlOx:Nd gate dielectric layer. As a result, the all-aluminum TFT with two Al2O3/AZO heterojunction units exhibited a mobility of 2.47 cm2/V·s and an Ion/Ioff ratio of 106. All processes were carried out at room temperature, which created new possibilities for green displays industry by allowing for the devices fabricated on plastic-like substrates or papers, mainly using no toxic/rare materials. PMID:28772579

Dual-gate photo thin-film transistor: a “smart” pixel for high- resolution and low-dose X-ray imaging

NASA Astrophysics Data System (ADS)

Wang, Kai; Ou, Hai; Chen, Jun

2015-06-01

Since its emergence a decade ago, amorphous silicon flat panel X-ray detector has established itself as a ubiquitous platform for an array of digital radiography modalities. The fundamental building block of a flat panel detector is called a pixel. In all current pixel architectures, sensing, storage, and readout are unanimously kept separate, inevitably compromising resolution by increasing pixel size. To address this issue, we hereby propose a “smart” pixel architecture where the aforementioned three components are combined in a single dual-gate photo thin-film transistor (TFT). In other words, the dual-gate photo TFT itself functions as a sensor, a storage capacitor, and a switch concurrently. Additionally, by harnessing the amplification effect of such a thin-film transistor, we for the first time created a single-transistor active pixel sensor. The proof-of-concept device had a W/L ratio of 250μm/20μm and was fabricated using a simple five-mask photolithography process, where a 130nm transparent ITO was used as the top photo gate, and a 200nm amorphous silicon as the absorbing channel layer. The preliminary results demonstrated that the photocurrent had been increased by four orders of magnitude due to light-induced threshold voltage shift in the sub-threshold region. The device sensitivity could be simply tuned by photo gate bias to specifically target low-level light detection. The dependence of threshold voltage on light illumination indicated that a dynamic range of at least 80dB could be achieved. The "smart" pixel technology holds tremendous promise for developing high-resolution and low-dose X-ray imaging and may potentially lower the cancer risk imposed by radiation, especially among paediatric patients.

Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

NASA Astrophysics Data System (ADS)

Dentoni Litta, E.; Hellström, P.-E.; Östling, M.

2015-06-01

High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

Radiation sensors based on the generation of mobile protons in organic dielectrics.

PubMed

Kapetanakis, Eleftherios; Douvas, Antonios M; Argitis, Panagiotis; Normand, Pascal

2013-06-26

A sensing scheme based on mobile protons generated by radiation, including ionizing radiation (IonR), in organic gate dielectrics is investigated for the development of metal-insulator-semiconductor (MIS)-type dosimeters. Application of an electric field to the gate dielectric moves the protons and thereby alters the flat band voltage (VFB) of the MIS device. The shift in the VFB is proportional to the IonR-generated protons and, therefore, to the IonR total dose. Triphenylsulfonium nonaflate (TPSNF) photoacid generator (PAG)-containing poly(methyl methacrylate) (PMMA) polymeric films was selected as radiation-sensitive gate dielectrics. The effects of UV (249 nm) and gamma (Co-60) irradiations on the high-frequency capacitance versus the gate voltage (C-VG) curves of the MIS devices were investigated for different total dose values. Systematic improvements in sensitivity can be accomplished by increasing the concentration of the TPSNF molecules embedded in the polymeric matrix.

Formation of nanofilament field emission devices

DOEpatents

Morse, Jeffrey D.; Contolini, Robert J.; Musket, Ronald G.; Bernhardt, Anthony F.

2000-01-01

A process for fabricating a nanofilament field emission device. The process enables the formation of high aspect ratio, electroplated nanofilament structure devices for field emission displays wherein a via is formed in a dielectric layer and is self-aligned to a via in the gate metal structure on top of the dielectric layer. The desired diameter of the via in the dielectric layer is on the order of 50-200 nm, with an aspect ratio of 5-10. In one embodiment, after forming the via in the dielectric layer, the gate metal is passivated, after which a plating enhancement layer is deposited in the bottom of the via, where necessary. The nanofilament is then electroplated in the via, followed by removal of the gate passification layer, etch back of the dielectric, and sharpening of the nanofilament. A hard mask layer may be deposited on top of the gate metal and removed following electroplating of the nanofilament.

Electro-Optic Frequency Beam Splitters and Tritters for High-Fidelity Photonic Quantum Information Processing

DOE PAGES

Lu, Hsuan-Hao; Lukens, Joseph M.; Peters, Nicholas A.; ...

2018-01-18

In this paper, we report the experimental realization of high-fidelity photonic quantum gates for frequency-encoded qubits and qutrits based on electro-optic modulation and Fourier-transform pulse shaping. Our frequency version of the Hadamard gate offers near-unity fidelity (0.99998±0.00003), requires only a single microwave drive tone for near-ideal performance, functions across the entire C band (1530–1570 nm), and can operate concurrently on multiple qubits spaced as tightly as four frequency modes apart, with no observable degradation in the fidelity. For qutrits, we implement a 3×3 extension of the Hadamard gate: the balanced tritter. This tritter—the first ever demonstrated for frequency modes—attains fidelitymore » 0.9989±0.0004. Finally, these gates represent important building blocks toward scalable, high-fidelity quantum information processing based on frequency encoding.« less

Electro-Optic Frequency Beam Splitters and Tritters for High-Fidelity Photonic Quantum Information Processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Hsuan-Hao; Lukens, Joseph M.; Peters, Nicholas A.

In this paper, we report the experimental realization of high-fidelity photonic quantum gates for frequency-encoded qubits and qutrits based on electro-optic modulation and Fourier-transform pulse shaping. Our frequency version of the Hadamard gate offers near-unity fidelity (0.99998±0.00003), requires only a single microwave drive tone for near-ideal performance, functions across the entire C band (1530–1570 nm), and can operate concurrently on multiple qubits spaced as tightly as four frequency modes apart, with no observable degradation in the fidelity. For qutrits, we implement a 3×3 extension of the Hadamard gate: the balanced tritter. This tritter—the first ever demonstrated for frequency modes—attains fidelitymore » 0.9989±0.0004. Finally, these gates represent important building blocks toward scalable, high-fidelity quantum information processing based on frequency encoding.« less

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

NASA Astrophysics Data System (ADS)

Suarez, Ernesto; Chan, Pik-Yiu; Lingalugari, Murali; Ayers, John E.; Heller, Evan; Jain, Faquir

2013-11-01

This paper describes the use of II-VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II-VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

Use of laser drilling in the manufacture of organic inverter circuits.

PubMed

Iba, Shingo; Kato, Yusaku; Sekitani, Tsuyoshi; Kawaguchi, Hiroshi; Sakurai, Takayasu; Someya, Takao

2006-01-01

Inverter circuits have been made by connecting two high-quality pentacene field-effect transistors. A uniform and pinhole-free 900 nm thick polyimide gate-insulating layer was formed on a flexible polyimide film with gold gate electrodes and partially removed by using a CO2 laser drilling machine to make via holes and contact holes. Subsequent evaporation of the gold layer results in good electrical connection with a gold gate layer underneath the gate-insulating layer. By optimization of the settings of the CO2 laser drilling machine, contact resistance can be reduced to as low as 3 ohms for 180 microm square electrodes. No degradation of the transport properties of the organic transistors was observed after the laser-drilling process. This study demonstrates the feasibility of using the laser drilling process for implementation of organic transistors in integrated circuits on flexible polymer films.

What Randomized Benchmarking Actually Measures

DOE PAGES

Proctor, Timothy; Rudinger, Kenneth; Young, Kevin; ...

2017-09-28

Randomized benchmarking (RB) is widely used to measure an error rate of a set of quantum gates, by performing random circuits that would do nothing if the gates were perfect. In the limit of no finite-sampling error, the exponential decay rate of the observable survival probabilities, versus circuit length, yields a single error metric r. For Clifford gates with arbitrary small errors described by process matrices, r was believed to reliably correspond to the mean, over all Clifford gates, of the average gate infidelity between the imperfect gates and their ideal counterparts. We show that this quantity is not amore » well-defined property of a physical gate set. It depends on the representations used for the imperfect and ideal gates, and the variant typically computed in the literature can differ from r by orders of magnitude. We present new theories of the RB decay that are accurate for all small errors describable by process matrices, and show that the RB decay curve is a simple exponential for all such errors. Here, these theories allow explicit computation of the error rate that RB measures (r), but as far as we can tell it does not correspond to the infidelity of a physically allowed (completely positive) representation of the imperfect gates.« less

Identification and Functional Expression of a Glutamate- and Avermectin-Gated Chloride Channel from Caligus rogercresseyi, a Southern Hemisphere Sea Louse Affecting Farmed Fish

PubMed Central

Niemeyer, María Isabel; Marabolí, Vanessa; González-Nilo, F. Danilo; Teulon, Jacques; Sepúlveda, Francisco V.; Cid, L. Pablo

2014-01-01

Parasitic sea lice represent a major sanitary threat to marine salmonid aquaculture, an industry accounting for 7% of world fish production. Caligus rogercresseyi is the principal sea louse species infesting farmed salmon and trout in the southern hemisphere. Most effective control of Caligus has been obtained with macrocyclic lactones (MLs) ivermectin and emamectin. These drugs target glutamate-gated chloride channels (GluCl) and act as irreversible non-competitive agonists causing neuronal inhibition, paralysis and death of the parasite. Here we report the cloning of a full-length CrGluClα receptor from Caligus rogercresseyi. Expression in Xenopus oocytes and electrophysiological assays show that CrGluClα is activated by glutamate and mediates chloride currents blocked by the ligand-gated anion channel inhibitor picrotoxin. Both ivermectin and emamectin activate CrGluClα in the absence of glutamate. The effects are irreversible and occur with an EC50 value of around 200 nM, being cooperative (nH = 2) for ivermectin but not for emamectin. Using the three-dimensional structure of a GluClα from Caenorabditis elegans, the only available for any eukaryotic ligand-gated anion channel, we have constructed a homology model for CrGluClα. Docking and molecular dynamics calculations reveal the way in which ivermectin and emamectin interact with CrGluClα. Both drugs intercalate between transmembrane domains M1 and M3 of neighbouring subunits of a pentameric structure. The structure displays three H-bonds involved in this interaction, but despite similarity in structure only of two these are conserved from the C. elegans crystal binding site. Our data strongly suggest that CrGluClα is an important target for avermectins used in the treatment of sea louse infestation in farmed salmonids and open the way for ascertaining a possible mechanism of increasing resistance to MLs in aquaculture industry. Molecular modeling could help in the design of new, more efficient drugs whilst functional expression of the receptor allows a first stage of testing of their efficacy. PMID:25255455

Identification and functional expression of a glutamate- and avermectin-gated chloride channel from Caligus rogercresseyi, a southern Hemisphere sea louse affecting farmed fish.

PubMed

Cornejo, Isabel; Andrini, Olga; Niemeyer, María Isabel; Marabolí, Vanessa; González-Nilo, F Danilo; Teulon, Jacques; Sepúlveda, Francisco V; Cid, L Pablo

2014-09-01

Parasitic sea lice represent a major sanitary threat to marine salmonid aquaculture, an industry accounting for 7% of world fish production. Caligus rogercresseyi is the principal sea louse species infesting farmed salmon and trout in the southern hemisphere. Most effective control of Caligus has been obtained with macrocyclic lactones (MLs) ivermectin and emamectin. These drugs target glutamate-gated chloride channels (GluCl) and act as irreversible non-competitive agonists causing neuronal inhibition, paralysis and death of the parasite. Here we report the cloning of a full-length CrGluClα receptor from Caligus rogercresseyi. Expression in Xenopus oocytes and electrophysiological assays show that CrGluClα is activated by glutamate and mediates chloride currents blocked by the ligand-gated anion channel inhibitor picrotoxin. Both ivermectin and emamectin activate CrGluClα in the absence of glutamate. The effects are irreversible and occur with an EC(50) value of around 200 nM, being cooperative (n(H) = 2) for ivermectin but not for emamectin. Using the three-dimensional structure of a GluClα from Caenorabditis elegans, the only available for any eukaryotic ligand-gated anion channel, we have constructed a homology model for CrGluClα. Docking and molecular dynamics calculations reveal the way in which ivermectin and emamectin interact with CrGluClα. Both drugs intercalate between transmembrane domains M1 and M3 of neighbouring subunits of a pentameric structure. The structure displays three H-bonds involved in this interaction, but despite similarity in structure only of two these are conserved from the C. elegans crystal binding site. Our data strongly suggest that CrGluClα is an important target for avermectins used in the treatment of sea louse infestation in farmed salmonids and open the way for ascertaining a possible mechanism of increasing resistance to MLs in aquaculture industry. Molecular modeling could help in the design of new, more efficient drugs whilst functional expression of the receptor allows a first stage of testing of their efficacy.

Measurements of slip length for flows over graphite surface with gas domains

NASA Astrophysics Data System (ADS)

Li, Dayong; Wang, Yuliang; Pan, Yunlu; Zhao, Xuezeng

2016-10-01

We present the measurements of slip lengths for the flows of purified water over graphite surface covered with surface nanobubbles or nano/micropancakes, which can be produced after using high temperature water to replace low temperature water. The slip length values measured on bare graphite surface, nano/micropancake or nanobubble covered graphite surfaces are about 8 nm, 27 nm, and 63 nm, respectively. Our results indicate that the gaseous domains formed at the solid-liquid interface, including surface nanobubbles and nano/micropancakes, could act as a lubricant and significantly increase slip length.

Direct Evidence of Conformational Changes Associated with Voltage Gating in a Voltage Sensor Protein by Time-Resolved X-ray/Neutron Interferometry

PubMed Central

2015-01-01

The voltage sensor domain (VSD) of voltage-gated cation (e.g., Na+, K+) channels central to neurological signal transmission can function as a distinct module. When linked to an otherwise voltage-insensitive, ion-selective membrane pore, the VSD imparts voltage sensitivity to the channel. Proteins homologous with the VSD have recently been found to function themselves as voltage-gated proton channels or to impart voltage sensitivity to enzymes. Determining the conformational changes associated with voltage gating in the VSD itself in the absence of a pore domain thereby gains importance. We report the direct measurement of changes in the scattering-length density (SLD) profile of the VSD protein, vectorially oriented within a reconstituted phospholipid bilayer membrane, as a function of the transmembrane electric potential by time-resolved X-ray and neutron interferometry. The changes in the experimental SLD profiles for both polarizing and depolarizing potentials with respect to zero potential were found to extend over the entire length of the isolated VSD’s profile structure. The characteristics of the changes observed were in qualitative agreement with molecular dynamics simulations of a related membrane system, suggesting an initial interpretation of these changes in terms of the VSD’s atomic-level 3-D structure. PMID:24697545

Increased foot-stretcher height improves rowing performance: evidence from biomechanical perspectives on water.

PubMed

Liu, Yang; Gao, Binghong; Li, Jiru; Ma, Zuchang; Sun, Yining

2018-06-07

The aim of this study was to investigate whether changes on foot-stretcher height were associated with characteristics of better rowing performance. Ten male rowers performed a 200 m rowing trial at their racing rate at each of three foot-stretcher heights. A single scull was equipped with an accelerometer to collect boat acceleration, an impeller with embedded magnets to collect boat speed, specially designed gate sensors to collect gate force and angle, and a compact string potentiometer to collect leg drive length. All sensor signals were sampled at 50 Hz. A one-way repeated measures ANOVA showed that raising foot-stretcher position had a significant reduction on total gate angle and leg drive length. However, a raised foot-stretcher position had a deeper negative peak of boat acceleration at the catch, a lower boat fluctuation, a faster leg drive speed, a larger gate force for the port and starboard side separately. This could be attributed to the optimisation of the magnitude and direction of the foot force with a raised foot-stretcher position. Although there was a significant negative influence of a raised foot-stretcher position on two kinematic variables, biomechanical evidence suggested that a raised foot-stretcher position could contribute to the improvement of rowing performance.

Atomic Scale Dynamics of Contact Formation in the Cross-Section of InGaAs Nanowire Channels

DOE PAGES

Chen, Renjie; Jungjohann, Katherine L.; Mook, William M.; ...

2017-03-23

In the alloyed and compound contacts between metal and semiconductor transistor channels we see that they enable self-aligned gate processes which play a significant role in transistor scaling. At nanoscale dimensions and for nanowire channels, prior experiments focused on reactions along the channel length, but the early stage of reaction in their cross sections remains unknown. We report on the dynamics of the solid-state reaction between metal (Ni) and semiconductor (In 0.53Ga 0.47As), along the cross-section of nanowires that are 15 nm in width. Unlike planar structures where crystalline nickelide readily forms at conventional, low alloying temperatures, nanowires exhibit amore » solid-state amorphization step that can undergo a crystal regrowth step at elevated temperatures. Here, we capture the layer-by-layer reaction mechanism and growth rate anisotropy using in situ transmission electron microscopy (TEM). Our kinetic model depicts this new, in-plane contact formation which could pave the way for engineered nanoscale transistors.« less

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

PubMed Central

2012-01-01

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. PMID:22901374

Fast photomultiplier tube gating system for underwater laser detector

NASA Astrophysics Data System (ADS)

Lei, Xuanhua; Yang, Kecheng; Rao, Jionghui; Zhang, Xiaohui; Xia, Min; Zheng, Yi; Li, Wei

2007-01-01

Laser will attenuate during its propagation in water and also be backward scattered by water when it is used to detect bubbles in the ocean. Meanwhile backward scattering intensity of the bubbles is feeble, its dynamic range reaches to the order of 6, which saturates PMT and its post-treatment circuit. Timely gating system is used to solve the problem. The system contains pulsed laser and gating PMT receiver. The wavelength of the laser is 532nm, with pulse width of several nanometers. Its operational delay is matched with the time period between laser traveling forward and back after scattered by the target. By doing this, the light scattered by other object is eliminated, dynamic range of the signal reduces, and consequently SNR increases. In order to avoid Signal Induced Noise(SIN), we choose PMT R1333 having no HA coating. TTL logical level, which is used as gating signal, controls the first dynode voltage of PMT to implement gating. Gating speed is about 100ns, of which the width is tunable. By carefully designing the electronic system, SNR is eliminated to a level as low as possible, and the output signal of PMT is fast integrated in order to reduce the influences of signal induced by opening the gate.

Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

NASA Astrophysics Data System (ADS)

Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

The pathway for CMOS technology beyond the 5-nm technology node remains unclear for both physical and technological reasons. A new transistor paradigm is required. A LET (Marmon et. al., Front. Phys. 2016, 4, No. 8) offers electronic-optical hybridization at the component level, and is capable of continuing Moore's law to the quantum scale. A LET overcomes a FET's fabrication complexity, e.g., physical gate and doping, by employing optical gating and photoconductivity, while multiple independent, optical gates readily realize unique functionalities. We report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs, incorporating an M-S-M structure, show output and transfer characteristics resembling advanced FETs, e.g., on/off ratios up to 106 with a source-drain voltage of 1.43V, gate-power of 260nW, and a subthreshold swing of 0.3nW/decade (excluding losses). A LET has potential for high-switching (THz) speeds and extremely low-switching energies (aJ) in the ballistic transport region. Our work offers new electronic-optical integration strategies for high speed and low energy computing approaches, which could potentially be extended to other materials and devices.

Experimental study on high-power all-fiber superfluorescent source operating near 980 nm

NASA Astrophysics Data System (ADS)

Ren, Yankun; Cao, Jianqiu; Ying, Hanyuan; Chen, Heng; Pan, Zhiyong; Du, Shaojun; Chen, Jinbao

2018-07-01

A high-power all-fiber superfluorescent source operating near 980 nm is experimentally studied with the help of a large-core distributed side-coupled cladding-pumped Yb-doped fiber. By optimizing the active fiber length and the angle cleaving of the output fiber facet, a 10 W all-fiber superfluorescent source operating near 980 nm is demonstrated for the first time, to the best of our knowledge. An 11.4 W combined 980 nm ASE power is obtained with a 9.3% slope efficiency and an 18 dB suppression of the ASE around 1030 nm. The output spectrum spans 973 nm to 982 nm with the 3 dB bandwidth around 3.5 nm. A 10.5 W output power with 13.1% slope efficiency is also obtained by changing the length of the active fiber. The variations of the output power and spectrum with the active fiber length and pump power are also investigated in the experiment.

Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Yoon, Jun-Sik; Rim, Taiuk; Kim, Jungsik; Kim, Kihyun; Baek, Chang-Ki; Jeong, Yoon-Ha

2015-03-01

Random dopant fluctuation effects of gate-all-around inversion-mode silicon nanowire field-effect transistors (FETs) with different diameters and extension lengths are investigated. The nanowire FETs with smaller diameter and longer extension length reduce average values and variations of subthreshold swing and drain-induced barrier lowering, thus improving short channel immunity. Relative variations of the drain currents increase as the diameter decreases because of decreased current drivability from narrower channel cross-sections. Absolute variations of the drain currents decrease critically as the extension length increases due to decreasing the number of arsenic dopants penetrating into the channel region. To understand variability origins of the drain currents, variations of source/drain series resistance and low-field mobility are investigated. All these two parameters affect the variations of the drain currents concurrently. The nanowire FETs having extension lengths sufficient to prevent dopant penetration into the channel regions and maintaining relatively large cross-sections are suggested to achieve suitable short channel immunity and small variations of the drain currents.

Design Architecture of field-effect transistor with back gate electrode for biosensor application

NASA Astrophysics Data System (ADS)

Fathil, M. F. M.; Arshad, M. K. Md.; Hashim, U.; Ruslinda, A. R.; Gopinath, Subash C. B.; M. Nuzaihan M., N.; Ayub, R. M.; Adzhri, R.; Zaki, M.; Azman, A. H.

2016-07-01

This paper presents the preparation method of photolithography chrome mask design used in fabrication process of field-effect transistor with back gate biasing based biosensor. Initially, the chrome masks are designed by studying the process flow of the biosensor fabrication, followed by drawing of the actual chrome mask using the AutoCAD software. The overall width and length of the device is optimized at 16 mm and 16 mm, respectively. Fabrication processes of the biosensor required five chrome masks, which included source and drain formation mask, the back gate area formation mask, electrode formation mask, front gate area formation mask, and passivation area formation mask. The complete chrome masks design will be sent for chrome mask fabrication and for future use in biosensor fabrication.

High kappa Dielectrics on InGaAs and GaN - Growth, Interfacial Structural Studies, and Surface Fermi Level Unpinning

DTIC Science & Technology

2011-04-20

ALD-Al2O3 and in-situ MBE-Al2O3/ Ga2O3 (Gd2O3) [GGO] as the gate dielectrics. The advances of the InGaAs MOSFETs achieved will enable future CMOS...and GaN MOSFETs:  High-performance self-aligned inversion-channel In0.53Ga0.47As and In0.75Ga0.25As MOSFET’s with Al2O3/ Ga2O3 (Gd2O3) as gate... Ga2O3 (Gd2O3) as gate dielectrics Key accomplishments in devices of 1m gate length: High drain current of 1.23 mA/m High transcoductance of 714

Air-gating and chemical-gating in transistors and sensing devices made from hollow TiO2 semiconductor nanotubes

NASA Astrophysics Data System (ADS)

Alivov, Yahya; Funke, Hans; Nagpal, Prashant

2015-07-01

Rapid miniaturization of electronic devices down to the nanoscale, according to Moore’s law, has led to some undesirable effects like high leakage current in transistors, which can offset additional benefits from scaling down. Development of three-dimensional transistors, by spatial extension in the third dimension, has allowed higher contact area with a gate electrode and better control over conductivity in the semiconductor channel. However, these devices do not utilize the large surface area and interfaces for new electronic functionality. Here, we demonstrate air gating and chemical gating in hollow semiconductor nanotube devices and highlight the potential for development of novel transistors that can be modulated using channel bias, gate voltage, chemical composition, and concentration. Using chemical gating, we reversibly altered the conductivity of nanoscaled semiconductor nanotubes (10-500 nm TiO2 nanotubes) by six orders of magnitude, with a tunable rectification factor (ON/OFF ratio) ranging from 1-106. While demonstrated air- and chemical-gating speeds were slow here (˜seconds) due to the mechanical-evacuation rate and size of our chamber, the small nanoscale volume of these hollow semiconductors can enable much higher switching speeds, limited by the rate of adsorption/desorption of molecules at semiconductor interfaces. These chemical-gating effects are completely reversible, additive between different chemical compositions, and can enable semiconductor nanoelectronic devices for ‘chemical transistors’, ‘chemical diodes’, and very high-efficiency sensing applications.

Optimization of fluorescent imaging in the operating room through pulsed acquisition and gating to ambient background cycling

PubMed Central

Sexton, Kristian J.; Zhao, Yan; Davis, Scott C.; Jiang, Shudong; Pogue, Brian W.

2017-01-01

The design of fluorescence imaging instruments for surgical guidance is rapidly evolving, and a key issue is to efficiently capture signals with high ambient room lighting. Here, we introduce a novel time-gated approach to fluorescence imaging synchronizing acquisition to the 120 Hz light of the room, with pulsed LED excitation and gated ICCD detection. It is shown that under bright ambient room light this technique allows for the detection of physiologically relevant nanomolar fluorophore concentrations, and in particular reduces the light fluctuations present from the room lights, making low concentration measurements more reliable. This is particularly relevant for the light bands near 700nm that are more dominated by ambient lights. PMID:28663895

Biomimetic glass nanopores employing aptamer gates responsive to a small molecule†

PubMed Central

Abelow, Alexis E.; Schepelina, Olga; White, Ryan J.; Vallée-Bélisle, Alexis

2011-01-01

We report the preparation of 20 and 65 nm radii glass nanopores whose surface is modified with DNA aptamers controlling the molecular transport through the nanopores in response to small molecule binding. PMID:20865192

Wavelength dependence and multiple-induced states in photoresponses of copper phthalocyanine-doped gold nanoparticle single-electron device

NASA Astrophysics Data System (ADS)

Yamamoto, Makoto; Ueda, Rieko; Terui, Toshifumi; Imazu, Keisuke; Tamada, Kaoru; Sakano, Takeshi; Matsuda, Kenji; Ishii, Hisao; Noguchi, Yutaka

2014-01-01

We have proposed a gold nanoparticle (GNP)-based single-electron transistor (SET) doped with a dye molecule, where the molecule works as a photoresponsive floating gate. Here, we examined the source-drain current (I_{\\text{SD}}) at a constant drain voltage under light irradiation with various wavelengths ranging from 400 to 700 nm. Current change was enhanced at the wavelengths of 600 and 700 nm, corresponding to the optical absorption band of the doped molecule (copper phthalocyanine: CuPc). Moreover, several peaks appear in the histograms of I_{\\text{SD}} during light irradiation, indicating that multiple discrete states were induced in the device. The results suggest that the current change was initiated by the light absorption of CuPc and multiple CuPc molecules near the GNP working as a floating gate. Molecular doping can activate advanced device functions in GNP-based SETs.

High-Performance InGaAs/InP Composite-Channel High Electron Mobility Transistors Grown by Metal-Organic Vapor-Phase Epitaxy

NASA Astrophysics Data System (ADS)

Sugiyama, Hiroki; Kosugi, Toshihiko; Yokoyama, Haruki; Murata, Koichi; Yamane, Yasuro; Tokumitsu, Masami; Enoki, Takatomo

2008-04-01

This paper reports InGaAs/InP composite-channel (CC) high electron mobility transistors (HEMTs) grown by metal-organic vapor-phase epitaxy (MOVPE) with excellent breakdown and high-speed characteristics. Atomic force microscopy (AFM) reveals high-quality heterointerfaces between In(Ga,Al)As and In(Al)P. Fabricated 80-nm-gate CC HEMTs exhibit on- and off-state breakdown (burnout) voltages estimated at higher than 3 and 8 V. An excellent current-gain cutoff frequency ( fT) of 186 GHz is also obtained in the CC HEMTs. The on-wafer uniformity of CC-HEMT characteristics is comparable to those of our mature 100-nm-gate InGaAs single-channel HEMTs. Bias-stress aging tests reveals that the lifetime of CC HEMTs is expected to be comparable to that of our conventional InGaAs single-channel HEMTs.

Reduced distribution of threshold voltage shift in double layer NiSi2 nanocrystals for nano-floating gate memory applications.

PubMed

Choi, Sungjin; Lee, Junhyuk; Kim, Donghyoun; Oh, Seulki; Song, Wangyu; Choi, Seonjun; Choi, Eunsuk; Lee, Seung-Beck

2011-12-01

We report on the fabrication and capacitance-voltage characteristics of double layer nickel-silicide nanocrystals with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO2 interlayer, the use of Si3N4 interlayer separation reduced the average size (4 nm) and distribution (+/- 2.5 nm) of NiSi2 nanocrystal (NC) charge traps by more than 50% and giving a two fold increase in NC density to 2.3 x 10(12) cm(-2). The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C-V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50% on average to less than 0.7 V demonstrating possible multi-level-cell operation.

Adhesion layer for etching of tracks in nuclear trackable materials

DOEpatents

Morse, Jeffrey D.; Contolini, Robert J.

2001-01-01

A method for forming nuclear tracks having a width on the order of 100-200 nm in nuclear trackable materials, such as polycarbonate (LEXAN) without causing delamination of the LEXAN. The method utilizes an adhesion film having a inert oxide which allows the track to be sufficiently widened to >200 nm without delamination of the nuclear trackable materials. The adhesion film may be composed of a metal such as Cr, Ni, Au, Pt, or Ti, or composed of a dielectric having a stable surface, such as silicon dioxide (SiO.sub.2), silicon nitride (SiN.sub.x), and aluminum oxide (AlO). The adhesion film can either be deposited on top of the gate metal layer, or if the properties of the adhesion film are adequate, it can be used as the gate layer. Deposition of the adhesion film is achieved by standard techniques, such as sputtering or evaporation.

An Al2O3 Gating Substrate for the Greater Performance of Field Effect Transistors Based on Two-Dimensional Materials

PubMed Central

Zheng, Xiaoming; Wang, Guang; Tan, Yuan; Zhang, Xueao

2017-01-01

We fabricated 70 nm Al2O3 gated field effect transistors based on two-dimensional (2D) materials and characterized their optical and electrical properties. Studies show that the optical contrast of monolayer graphene on an Al2O3/Si substrate is superior to that on a traditional 300 nm SiO2/Si substrate (2.4 times). Significantly, the transconductance of monolayer graphene transistors on the Al2O3/Si substrate shows an approximately 10-fold increase, due to a smaller dielectric thickness and a higher dielectric constant. Furthermore, this substrate is also suitable for other 2D materials, such as WS2, and can enhance the transconductance remarkably by 61.3 times. These results demonstrate a new and ideal substrate for the fabrication of 2D materials-based electronic logic devices. PMID:28937619

Excitation wavelength dependence of excited state intramolecular proton transfer reaction of 4'-N,N-diethylamino-3-hydroxyflavone in room temperature ionic liquids studied by optical Kerr gate fluorescence measurement.

PubMed

Suda, Kayo; Terazima, Masahide; Sato, Hirofumi; Kimura, Yoshifumi

2013-10-17

Excited state intramolecular proton transfer reactions (ESIPT) of 4'-N,N-diethylamino-3-hydroxyflavone (DEAHF) in ionic liquids have been studied by steady-state and time-resolved fluorescence measurements at different excitation wavelengths. Steady-state measurements show the relative yield of the tautomeric form to the normal form of DEAHF decreases as excitation wavelength is increased from 380 to 450 nm. The decrease in yield is significant in ionic liquids that have cations with long alkyl chains. The extent of the decrease is correlated with the number of carbon atoms in the alkyl chains. Time-resolved fluorescence measurements using optical Kerr gate spectroscopy show that ESIPT rate has a strong excitation wavelength dependence. There is a large difference between the spectra at a 200 ps delay from different excitation wavelengths in each ionic liquid. The difference is pronounced in ionic liquids having a long alkyl chain. The equilibrium constant in the electronic excited state obtained at a 200 ps delay and the average reaction rate are also correlated with the alkyl chain length. Considering the results of the steady-state fluorescence and time-resolved measurements, the excitation wavelength dependence of ESIPT is explained by state selective excitation due to the difference of the solvation, and the number of alkyl chain carbon atoms is found to be a good indicator of the effect of inhomogeneity for this reaction.

Concentric-electrode organic electrochemical transistors: case study for selective hydrazine sensing

NASA Astrophysics Data System (ADS)

Pecqueur, S.; Lenfant, S.; Guérin, D.; Alibart, F.; Vuillaume, D.

2017-12-01

We report on hydrazine-sensing organic electrochemical transistors (OECTs) with a design consisting in concentric annular electrodes. The design engineering of these OECTs was motivated by the great potential of using OECT sensing arrays in fields such as bioelectronics. In this work, PEDOT:PSS-based OECTs have been studied as aqueous sensors, specifically sensitive to the lethal hydrazine molecule. These amperometric sensors have many relevant features for the development of hydrazine sensors, such as a sensitivity down to 10-5 M of hydrazine in water, an order of magnitude higher selectivity for hydrazine than for 9 other water soluble common analytes, the capability to recover entirely its base signal after water flushing and a very low voltage operation. The specificity for hydrazine to be sensed by our OECTs is caused by its catalytic oxidation at the gate electrode and enables increasing the output current modulation of the devices. This has permitted the device-geometry study of the whole series of 80 micrometric OECT devices with sub-20-nm PEDOT:PSS layers, channel lengths down to 1 μm and a specific device geometry of coplanar and concentric electrodes. The numerous geometries unravel new aspects of the OECT mechanisms governing the electrochemical sensing behaviours of the device, more particularly the effect of the contacts which are inherent at the micro-scale. By lowering the device cross-talking, micrometric gate-integrated radial OECTs shall contribute to the diminishing of the readout invasiveness and therefore promotes further the development of OECT biosensors.

Laser-Induced Incandescence Calibration via Gravimetric Sampling

NASA Technical Reports Server (NTRS)

VanderWal, R. L.; Zhou, Z.; Choi, M. Y.

1995-01-01

Various beam imaging and/or sheet forming optics delivered light at 1064 nm from a pulsed Nd:YAG laser for use either as a beam of 3 mm radius or as a laser sheet. Imaging measurements were performed with a grated intensified array camera equipped with an ultraviolet f4.5 lens and a 40 mm extension tube. Point measurements were performed using an ultraviolet 250 mm focal length lens to collect and focus the laser induced incandescence (LII) signal into a 1 meter long quartz optical fiber which directed the LII signal to a 1/4 meter monochromator. An aperture preceding the lens restricted the signal collection region to 1 cm along the laser beam at the center of the gravimetric chimney. Signals from the PMT were processed by a boxcar integrator whereas the images were captured digitally using a frame-grabber with 16 MByte of on-board memory. Both 'point' and planar measurements were made with detector gates of 250 ns to minimize possible morphology bias in collection of the LII signal. Additionally, the imaging measurements were performed with broadband spectral collection of the LII signal to maximize the signal and again minimize any potential effects of morphology dependent heating and/or cooling rates. Digital delay generators controlled the firing of he laser, detector gates and data acquisition. Neutral density filters were used for both sets of measurements to maintain signal levels within linear dynamic ranges of the detectors, the range being determined prior to experiments.

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

NASA Astrophysics Data System (ADS)

Yuan, Shoucai; Liu, Yamei

2016-08-01

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

Mathematical Models of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field effect Transistor

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2013-01-01

Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.

ZnO-based multiple channel and multiple gate FinMOSFETs

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Huang, Hung-Lin; Tseng, Chun-Yen; Lee, Hsin-Ying

2016-02-01

In recent years, zinc oxide (ZnO)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted much attention, because ZnO-based semiconductors possess several advantages, including large exciton binding energy, nontoxicity, biocompatibility, low material cost, and wide direct bandgap. Moreover, the ZnO-based MOSFET is one of most potential devices, due to the applications in microwave power amplifiers, logic circuits, large scale integrated circuits, and logic swing. In this study, to enhance the performances of the ZnO-based MOSFETs, the ZnObased multiple channel and multiple gate structured FinMOSFETs were fabricated using the simple laser interference photolithography method and the self-aligned photolithography method. The multiple channel structure possessed the additional sidewall depletion width control ability to improve the channel controllability, because the multiple channel sidewall portions were surrounded by the gate electrode. Furthermore, the multiple gate structure had a shorter distance between source and gate and a shorter gate length between two gates to enhance the gate operating performances. Besides, the shorter distance between source and gate could enhance the electron velocity in the channel fin structure of the multiple gate structure. In this work, ninety one channels and four gates were used in the FinMOSFETs. Consequently, the drain-source saturation current (IDSS) and maximum transconductance (gm) of the ZnO-based multiple channel and multiple gate structured FinFETs operated at a drain-source voltage (VDS) of 10 V and a gate-source voltage (VGS) of 0 V were respectively improved from 11.5 mA/mm to 13.7 mA/mm and from 4.1 mS/mm to 6.9 mS/mm in comparison with that of the conventional ZnO-based single channel and single gate MOSFETs.

Enhanced Performance of Gate-First p-Channel Metal-Insulator-Semiconductor Field-Effect Transistors with Polycrystalline Silicon/TiN/HfSiON Stacks Fabricated by Physical Vapor Deposition Based In situ Method

NASA Astrophysics Data System (ADS)

Kitano, Naomu; Horie, Shinya; Arimura, Hiroaki; Kawahara, Takaaki; Sakashita, Shinsuke; Nishida, Yukio; Yugami, Jiro; Minami, Takashi; Kosuda, Motomu; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2007-12-01

We demonstrated the use of an in situ metal/high-k fabrication method for improving the performance of metal-insulator-semiconductor field-effect transistors (MISFETs). Gate-first pMISFETs with polycrystalline silicon (poly-Si)/TiN/HfSiON stacks were fabricated by techniques based on low-damage physical vapor deposition, in which high-quality HfSiON dielectrics were formed by the interface reaction between an ultrathin metal-Hf layer (0.5 nm thick) and a SiO2 underlayer, and TiN electrodes were continuously deposited on the gate dielectrics without exposure to air. Gate-first pMISFETs with high carrier mobility and a low threshold voltage (Vth) were realized by reducing the carbon impurity in the gate stacks and improving the Vth stability against thermal treatment. As a result, we obtained superior current drivability (Ion = 350 μA/μm at Ioff = 200 pA/μm), which corresponds to a 13% improvement over that of conventional chemical vapor deposition-based metal/high-k devices.

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

NASA Astrophysics Data System (ADS)

Deen, David A.; Storm, David F.; Scott Katzer, D.; Bass, R.; Meyer, David J.

2016-08-01

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics ft/fmax of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with ft/fmax of 48/60 GHz.

Submicron Structures and Various Technology

DTIC Science & Technology

1990-06-01

Replication in PMMA of a 30 nm-wide gold focused-ion-beam lithography alone. We are absorber line with (a) CK (A = 4.5 nm), ( b ) developing a new generation of...into soft x-ray spectroscopy and atom beam contact with the substrate b electrostatic interferometry, and to fabricate new classes means. A variety of...Professor Dimitri A. Antonaidis, Stuart B . Field, drain resistances and gate-source overlaps. Professor Marc A. Kastner, Udi Meirav, Samuel L. This will

Studies on output characteristics of stable dual-wavelength ytterbium-doped photonic crystal fiber laser

NASA Astrophysics Data System (ADS)

Tian, Hongchun; Zhang, Sa; Hou, Zhiyun; Xia, Changming; Zhou, Guiyao; Zhang, Wei; Liu, Jiantao; Wu, Jiale; Fu, Jian

2016-06-01

A stable dual-wavelength ytterbium-doped photonic crystal fiber laser pumped by a 976 nm laser diode has been demonstrated at room temperature. Single-wavelength, dual-wavelength laser oscillations are observed when the fiber laser operates under different pump power by using different length of fibers. Stable dual-wavelength radiation around 1045 nm and 1075 nm has been generated simultaneously at a high pump power directly from an ytterbium-doped fiber laser without using any spectral control mechanism. A small core ytterbium-doped PCF fabricated by the powder sinter direction drawn rod technology is used as gain medium. The pump power and fiber length which can affect the output characteristics of dual-wavelength fiber laser are analyzed in the experiment. Experiments confirm that higher pump power and longer fiber length favors 1075 nm output; lower pump power and shorter fiber length favors 1045 nm output. Those results have a good reference in multi-wavelength fiber laser.

Scaling effects of a graphene field effect transistor for radiation detection

NASA Astrophysics Data System (ADS)

Shollar, Zachary Frank

Radiation detectors based on graphene is a burgeoning research topic within the immense field of graphene research. Although papers continue to parse out their mysteries, the devices remain simplistic and small. New fabrication techniques have allowed for millimeter scale and larger monolayer graphene sheets to be grown with increasingly better quality. It is the goal of this thesis to investigate the scaling effects of millimeter scale graphene for radiation detection purposes. To this end, chemical vapor deposition grown monolayer graphene was purchased and transferred to Si/SiO2 substrates. The devices were patterned into simple rectangular strips varying in size from 3000 x 500 mum, 600 x 100 mum, 300 x 50 mum, and 60 x 11 mum. Four metal contacts were patterned onto each strip for electrical characterization. Two probe resistance measurements were performed on all four sizes, at three different lengths along the graphene. Using the field effect, the graphene resistance response was measured at 0 V back-gate voltage to obtain graphene resistivity on SiO2, which showed an increase in resistivity as the graphene strip size increased. Further, the response was measured for varying back-gate sweep ranges and speeds. This lead to the conclusion that strong p-doping was inherent in the graphene strips, as evidenced by charge neutral points located above +50 V. Strong hysteresis observed in those tests alluded to trapped charge having a major effect on voltage sweeps. Mobility values for the graphene strips were extracted from the back-gate voltage sweeps and fixed gate voltage stabilization curves. Mobility values overall were less than 400 cm2 V-1 s-1, and showed a modest increase in mobility as graphene length increased. Lastly, the largest graphene strip had a light response and radiation response measured. Light response showed a dependence on gate voltage magnitude that favored positive gate voltages, on an n-type Silicon substrate. A saturation effect above +15 V seemed apparent with a resistance increase of only 0.61% +/- 0.062% for +15 V to 0.69% +/- 0.097% for the +50 V back-gate. Response of the largest graphene strip size to forward facing alpha irradiation showed a modest 0.32% +/- 0.082% increase in response, for a -15 V back- gate. Overall, millimeter scale graphene field effect devices showed a light and radiation response, proving their viability. However, results showed fabricated samples had numerous defects and were far from pristine. Fabrication of pristine graphene strips at millimeter scales is of concern. Further work into large scale GFET patterning, testing at more length and width dimensions, and further investigating metal contact and carrier transport in millimeter scales is needed.

Structure of a prokaryotic sodium channel pore reveals essential gating elements and an outer ion binding site common to eukaryotic channels

PubMed Central

Shaya, David; Findeisen, Felix; Abderemane-Ali, Fayal; Arrigoni, Cristina; Wong, Stephanie; Nurva, Shailika Reddy; Loussouarn, Gildas; Minor, Daniel L.

2013-01-01

Voltage-gated sodium channels (NaVs) are central elements of cellular excitation. Notwithstanding advances from recent bacterial NaV (BacNaV) structures, key questions about gating and ion selectivity remain. Here, we present a closed conformation of NaVAe1p, a pore-only BacNaV derived from NaVAe1, a BacNaV from the arsenite oxidizer Alkalilimnicola ehrlichei found in Mono Lake, California, that provides insight into both fundamental properties. The structure reveals a pore domain in which the pore-lining S6 helix connects to a helical cytoplasmic tail. Electrophysiological studies of full-length BacNaVs show that two elements defined by the NaVAe1p structure, an S6 activation gate position and the cytoplasmic tail ‘neck’, are central to BacNaV gating. The structure also reveals the selectivity filter ion entry site, termed the ‘outer ion’ site. Comparison with mammalian voltage-gated calcium channel (CaV) selectivity filters, together with functional studies shows that this site forms a previously unknown determinant of CaV high affinity calcium binding. Our findings underscore commonalities between BacNaVs and eukaryotic voltage-gated channels and provide a framework for understanding gating and ion permeation in this superfamily. PMID:24120938

Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

NASA Astrophysics Data System (ADS)

Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

2018-04-01

We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

The randomized benchmarking number is not what you think it is

NASA Astrophysics Data System (ADS)

Proctor, Timothy; Rudinger, Kenneth; Blume-Kohout, Robin; Sarovar, Mohan; Young, Kevin

Randomized benchmarking (RB) is a widely used technique for characterizing a gate set, whereby random sequences of gates are used to probe the average behavior of the gate set. The gates are chosen to ideally compose to the identity, and the rate of decay in the survival probability of an initial state with increasing length sequences is extracted from a set of experiments - this is the `RB number'. For reasonably well-behaved noise and particular gate sets, it has been claimed that the RB number is a reliable estimate of the average gate fidelity (AGF) of each noisy gate to the ideal target unitary, averaged over all gates in the set. Contrary to this widely held view, we show that this is not the case. We show that there are physically relevant situations, in which RB was thought to be provably reliable, where the RB number is many orders of magnitude away from the AGF. These results have important implications for interpreting the RB protocol, and immediate consequences for many advanced RB techniques. Sandia National Laboratories is a multi-mission laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.

Semi-transparent a-IGZO thin-film transistors with polymeric gate dielectric.

PubMed

Hyung, Gun Woo; Wang, Jian-Xun; Li, Zhao-Hui; Koo, Ja-Ryong; Kwon, Sang Jik; Cho, Eou-Sik; Kim, Young Kwan

2013-06-01

We report the fabrication of semi-transparent a-IGZO-based thin-film transistors (TFTs) with crosslinked poly-4-vinylphenol (PVP) gate dielectric layers on PET substrate and thermally-evaporated Al/Ag/Al source and drain (S&D) electrodes, which showed a transmittance of 64% at a 500-nm wavelength and sheet resistance of 16.8 omega/square. The semi-transparent a-IGZO TFTs with a PVP layer exhibited decent saturation mobilities (maximum approximately 5.8 cm2Ns) and on/off current ratios of approximately 10(6).

Enhanced ν-optical time domain reflectometry using gigahertz sinusoidally gated InGaAs/InP single-photon avalanche detector

NASA Astrophysics Data System (ADS)

Zhang, Xuping; Shi, Yuanlei; Shan, Yuanyuan; Sun, Zhenhong; Qiao, Weiyan; Zhang, Yixin

2016-09-01

Optical time domain reflectometry (OTDR) is one of the most successful diagnostic tools for nondestructive attenuation measurement of a fiber link. To achieve better sensitivity, spatial resolution, and avoid dead-zone in conversional OTDR, a single-photon detector has been introduced to form the photon-counting OTDR (ν-OTDR). We have proposed a ν-OTDR system using a gigahertz sinusoidally gated InGaAs/InP single-photon avalanche detector (SPAD). Benefiting from the superior performance of a sinusoidal gated SPAD on dark count probability, gating frequency, and gate duration, our ν-OTDR system has achieved a dynamic range (DR) of 33.4 dB with 1 μs probe pulse width after an equivalent measurement time of 51 s. This obtainable DR corresponds to a sensing length over 150 km. Our system has also obtained a spatial resolution of 5 cm at the end of a 5-km standard single-mode fiber. By employing a sinusoidal gating technique, we have improved the ν-OTDR spatial resolution and significantly reduced the measurement time.

The effects of TGG crystal length on output power and beam quality of a unidirectional ring Nd:YVO4 laser with and without second harmonic generation

NASA Astrophysics Data System (ADS)

Ahmadi, A.; Avazpour, A.; Nadgaran, H.; Mousavi, M.

2018-04-01

The effect of terbium gallium garnet (TGG ) crystal length on 1064 and 532 nm output powers and beam quality of a unidirectional ring Nd:YVO4 laser is investigated. In the case of 1064 nm (without nonlinear crystal), the laser output power without considerating the effect of TGG crystal was computed theoretically. Then three TGG crystals with different lengths were placed in the laser setup one by one. A systematic decrease in output power was observed by increasing the TGG crystal length. The experiment was repeated in the case of 532 nm. It was found that in a 532 nm laser, higher laser efficiency and small beam quality degradation can be achieved by increasing the TGG crystal length leading to a 5.7 W green laser with 27 W pump power. The power stability and beam quality were 0.8% for 30 min and less than 1.3, respectively.

Free-breathing 3D Cardiac MRI Using Iterative Image-Based Respiratory Motion Correction

PubMed Central

Moghari, Mehdi H.; Roujol, Sébastien; Chan, Raymond H.; Hong, Susie N.; Bello, Natalie; Henningsson, Markus; Ngo, Long H.; Goddu, Beth; Goepfert, Lois; Kissinger, Kraig V.; Manning, Warren J.; Nezafat, Reza

2012-01-01

Respiratory motion compensation using diaphragmatic navigator (NAV) gating with a 5 mm gating window is conventionally used for free-breathing cardiac MRI. Due to the narrow gating window, scan efficiency is low resulting in long scan times, especially for patients with irregular breathing patterns. In this work, a new retrospective motion compensation algorithm is presented to reduce the scan time for free-breathing cardiac MRI that increasing the gating window to 15 mm without compromising image quality. The proposed algorithm iteratively corrects for respiratory-induced cardiac motion by optimizing the sharpness of the heart. To evaluate this technique, two coronary MRI datasets with 1.3 mm3 resolution were acquired from 11 healthy subjects (7 females, 25±9 years); one using a NAV with a 5 mm gating window acquired in 12.0±2.0 minutes and one with a 15 mm gating window acquired in 7.1±1.0 minutes. The images acquired with a 15 mm gating window were corrected using the proposed algorithm and compared to the uncorrected images acquired with the 5 mm and 15 mm gating windows. The image quality score, sharpness, and length of the three major coronary arteries were equivalent between the corrected images and the images acquired with a 5 mm gating window (p-value>0.05), while the scan time was reduced by a factor of 1.7. PMID:23132549

New MBE buffer for micron- and quarter-micron-gateGaAs MESFETs

NASA Technical Reports Server (NTRS)

1988-01-01

A new buffer layer has been developed that eliminates backgating in GaAs MESFETs and substantially reduces short-channel effects in GaAs MESFETs with 0.27-micron-long gates. The new buffer is grown by molecular beam epitaxy (MBE) at a substrate temperature of 200 C using Ga and As sub 4 beam fluxes. The buffer is crystalline, highly resistive, optically inactive, and can be overgrown with high quality GaAs. GaAs MESFETs with a gate length of 0.27 microns that incorporate the new buffer show improved dc and RF properties in comparison with a similar MESFET with a thin undoped GaAs buffer. To demonstrate the backgating performance improvement afforded by the new buffer, MESFETs were fabricated using a number of different buffer layers and structures. A schematic cross section of the MESFET structure used in this study is shown. The measured gate length, gate width, and source-drain spacing of this device are 2,98, and 5.5 microns, respectively. An ohmic contact, isolated from the MESFET by mesa etching, served as the sidegate. The MESFETs were fabricated in MBE n-GaAs layers grown on the new buffer and also in MBE n-GaAs layers grown on buffer layers of undoped GaAs, AlGaAs, and GaAs/AlGaAs superlattices. All the buffer layers were grown by MBE and are 2 microns thick. The active layer is doped to approximately 2 x 10 to the 17th/cu cm with silicon and is 0.3 microns thick.

New positive Ca2+-activated K+ channel gating modulators with selectivity for KCa3.1.

PubMed

Coleman, Nichole; Brown, Brandon M; Oliván-Viguera, Aida; Singh, Vikrant; Olmstead, Marilyn M; Valero, Marta Sofia; Köhler, Ralf; Wulff, Heike

2014-09-01

Small-conductance (KCa2) and intermediate-conductance (KCa3.1) calcium-activated K(+) channels are voltage-independent and share a common calcium/calmodulin-mediated gating mechanism. Existing positive gating modulators like EBIO, NS309, or SKA-31 activate both KCa2 and KCa3.1 channels with similar potency or, as in the case of CyPPA and NS13001, selectively activate KCa2.2 and KCa2.3 channels. We performed a structure-activity relationship (SAR) study with the aim of optimizing the benzothiazole pharmacophore of SKA-31 toward KCa3.1 selectivity. We identified SKA-111 (5-methylnaphtho[1,2-d]thiazol-2-amine), which displays 123-fold selectivity for KCa3.1 (EC50 111 ± 27 nM) over KCa2.3 (EC50 13.7 ± 6.9 μM), and SKA-121 (5-methylnaphtho[2,1-d]oxazol-2-amine), which displays 41-fold selectivity for KCa3.1 (EC50 109 nM ± 14 nM) over KCa2.3 (EC50 4.4 ± 1.6 μM). Both compounds are 200- to 400-fold selective over representative KV (KV1.3, KV2.1, KV3.1, and KV11.1), NaV (NaV1.2, NaV1.4, NaV1.5, and NaV1.7), as well as CaV1.2 channels. SKA-121 is a typical positive-gating modulator and shifts the calcium-concentration response curve of KCa3.1 to the left. In blood pressure telemetry experiments, SKA-121 (100 mg/kg i.p.) significantly lowered mean arterial blood pressure in normotensive and hypertensive wild-type but not in KCa3.1(-/-) mice. SKA-111, which was found in pharmacokinetic experiments to have a much longer half-life and to be much more brain penetrant than SKA-121, not only lowered blood pressure but also drastically reduced heart rate, presumably through cardiac and neuronal KCa2 activation when dosed at 100 mg/kg. In conclusion, with SKA-121, we generated a KCa3.1-specific positive gating modulator suitable for further exploring the therapeutical potential of KCa3.1 activation. Copyright © 2014 by The American Society for Pharmacology and Experimental Therapeutics.

Electronic Holography with a Broad Spectrum Laser for Time Gated Imaging Through Highly Scattering Media.

NASA Astrophysics Data System (ADS)

Shih, Marian Pei-Ling

The problem of optical imaging through a highly scattering volume diffuser, in particular, biological tissue, has received renewed interest in recent years because of a search for alternative imaging diagnostics in the optical wavelengths for the early detection of human breast cancer. This dissertation discusses the optical imaging of objects obscured by diffusers that contribute an otherwise overwhelming degree of multiple scatter. Many optical imaging techniques are based on the first-arriving light principle. These methods usually combine a transilluminating optical short pulse with a time windowing gate in order to form a flat shadowgraph image of absorbing objects either embedded within or hidden behind a scattering medium. The gate selectively records an image of the first-arriving light, while simultaneously rejecting the later-arriving scattered light. One set of the many implementations of the first -arriving light principle relies on the gating property of holography. This thesis presents several holographic optical gating experiments that demonstrate the role that the temporal coherence function of the illumination source plays in the imaging of all objects with short coherence length holography, with special emphasis on the application to image through diffusers and its resolution capabilities. Previous researchers have already successfully combined electronic holography, holography in which the recording medium is a two dimensional detector array instead of photographic film, with light-in-flight holography into a short coherence length holography method that images through various types of multiply scattering random media, including chicken breast tissue and wax. This thesis reports further experimental exploration of the short coherence holography method for imaging through severely scattering diffusers. There is a study on the effectiveness of spatial filtering of the first-arriving light, as well as a report of the imaging, by means of the short coherence holographic method, of an absorber through a living human hand. This thesis also includes both theoretical analyses and experimental results of a spectral dispersion holography system which, instead of optically synthesizing the broad spectrum illumination source that is used for the short coherence holography method, digitally synthesizes a broad spectrum hologram from a collection of single frequency component holograms. This system has the time gating properties of short coherence length holography, as well as experimentally demonstrated applications for imaging through multiply scattering media.

Design considerations and emerging challenges for nanotube-, nanowire-, and negative capacitor-field effect transistors

NASA Astrophysics Data System (ADS)

Wahab, Md. Abdul

As the era of classical planar metal-oxide-semiconductor field-effect transistors (MOSFETs) comes to an end, the semiconductor industry is beginning to adopt 3D device architectures, such as FinFETs, starting at the 22 nm technology node. Since physical limits such as short channel effect (SCE) and self-heating may dominate, it may be difficult to scale Si FinFET below 10 nm. In this regard, transistors with different materials, geometries, or operating principles may help. For example, gate has excellent electrostatic control over 2D thin film channel with planar geometry, and 1D nanowire (NW) channel with gate-all-around (GAA) geometry to reduce SCE. High carrier mobility of single wall carbon nanotube (SWNT) or III-V channels may reduce VDD to reduce power consumption. Therefore, as channel of transistor, 2D thin film of array SWNTs and 1D III-V multi NWs are promising for sub 10 nm technology nodes. In this thesis, we analyze the potential of these transistors from process, performance, and reliability perspectives. For SWNT FETs, we discuss a set of challenges (such as how to (i) characterize diameter distribution, (ii) remove metallic (m)-SWNTs, and (iii) avoid electrostatic cross-talk among the neighboring SWNTs), and demonstrate solution strategies both theoretically and experimentally. Regarding self-heating in these new class of devices (SWNT FET and GAA NW FET including state-of-the-art FinFET), higher thermal resistance from poor thermal conducting oxides results significant temperature rise, and reduces the IC life-time. For GAA NW FETs, we discuss accurate self-heating evaluation with good spatial, temporal, and thermal resolutions. The introduction of negative capacitor (NC), as gate dielectric stack of transistor, allows sub 60 mV/dec operation to reduce power consumption significantly. Taken together, our work provides a comprehensive perspective regarding the challenges and opportunities of sub 10 nm technology nodes.

Determination of carrier diffusion length in GaN

NASA Astrophysics Data System (ADS)

Hafiz, Shopan; Zhang, Fan; Monavarian, Morteza; Avrutin, Vitaliy; Morkoç, Hadis; Özgür, Ümit; Metzner, Sebastian; Bertram, Frank; Christen, Jürgen; Gil, Bernard

2015-01-01

Diffusion lengths of photo-excited carriers along the c-direction were determined from photoluminescence (PL) and cross-sectional cathodoluminescence (CL) measurements in p- and n-type GaN epitaxial layers grown on c-plane sapphire by metal-organic chemical vapor deposition. The investigated samples incorporate a 6 nm thick In0.15Ga0.85N active layer capped with either 500 nm p-GaN or 1500 nm n-GaN. The top GaN layers were etched in steps and PL from the InGaN active region and the underlying layers was monitored as a function of the top GaN thickness upon photo-generation near the surface region by above bandgap excitation. Taking into consideration the absorption in the top GaN layer as well as active and underlying layers, the diffusion lengths at 295 K and at 15 K were measured to be 93 ± 7 nm and 70 ± 7 nm for Mg-doped p-type GaN and 432 ± 30 nm and 316 ± 30 nm for unintentionally doped n-type GaN, respectively, at photogenerated carrier densities of 4.2 × 1018 cm-3 using PL spectroscopy. CL measurements of the unintentionally doped n-type GaN layer at much lower carrier densities of 1017 cm-3 revealed a longer diffusion length of 525 ± 11 nm at 6 K.

Magnetic roller gas gate employing transonic sweep gas flow to isolate regions of differing gaseous composition or pressure

DOEpatents

Doehler, Joachim

1994-12-20

Disclosed herein is an improved gas gate for interconnecting regions of differing gaseous composition and/or pressure. The gas gate includes a narrow, elongated passageway through which substrate material is adapted to move between said regions and inlet means for introducing a flow of non-contaminating sweep gas into a central portion of said passageway. The gas gate is characterized in that the height of the passageway and the flow rate of the sweep gas therethrough provides for transonic flow of the sweep gas between the inlet means and at least one of the two interconnected regions, thereby effectively isolating one region, characterized by one composition and pressure, from another region, having a differing composition and/or pressure, by decreasing the mean-free-path length between collisions of diffusing species within the transonic flow region. The gas gate preferably includes a manifold at the juncture point where the gas inlet means and the passageway interconnect.

Measurement of transverse emittance and coherence of double-gate field emitter array cathodes

PubMed Central

Tsujino, Soichiro; Das Kanungo, Prat; Monshipouri, Mahta; Lee, Chiwon; Miller, R.J. Dwayne

2016-01-01

Achieving small transverse beam emittance is important for high brightness cathodes for free electron lasers and electron diffraction and imaging experiments. Double-gate field emitter arrays with on-chip focussing electrode, operating with electrical switching or near infrared laser excitation, have been studied as cathodes that are competitive with photocathodes excited by ultraviolet lasers, but the experimental demonstration of the low emittance has been elusive. Here we demonstrate this for a field emitter array with an optimized double-gate structure by directly measuring the beam characteristics. Further we show the successful application of the double-gate field emitter array to observe the low-energy electron beam diffraction from suspended graphene in minimal setup. The observed low emittance and long coherence length are in good agreement with theory. These results demonstrate that our all-metal double-gate field emitters are highly promising for applications that demand extremely low-electron bunch-phase space volume and large transverse coherence. PMID:28008918

Diffusive transport in the presence of stochastically gated absorption

NASA Astrophysics Data System (ADS)

Bressloff, Paul C.; Karamched, Bhargav R.; Lawley, Sean D.; Levien, Ethan

2017-08-01

We analyze a population of Brownian particles moving in a spatially uniform environment with stochastically gated absorption. The state of the environment at time t is represented by a discrete stochastic variable k (t )∈{0 ,1 } such that the rate of absorption is γ [1 -k (t )] , with γ a positive constant. The variable k (t ) evolves according to a two-state Markov chain. We focus on how stochastic gating affects the attenuation of particle absorption with distance from a localized source in a one-dimensional domain. In the static case (no gating), the steady-state attenuation is given by an exponential with length constant √{D /γ }, where D is the diffusivity. We show that gating leads to slower, nonexponential attenuation. We also explore statistical correlations between particles due to the fact that they all diffuse in the same switching environment. Such correlations can be determined in terms of moments of the solution to a corresponding stochastic Fokker-Planck equation.

Influence of gate overlap engineering on ambipolar and high frequency characteristics of tunnel-CNTFET

NASA Astrophysics Data System (ADS)

Shaker, Ahmed; Ossaimee, Mahmoud; Zekry, A.; Abouelatta, Mohamed

2015-10-01

In this paper, we have investigated the effect of gate overlapping-on-drain on the ambipolar behavior and high frequency performance of tunnel CNTFET (T-CNTFET). It is found that gate overlapping-on-drain suppresses the ambipolar behavior and improves OFF-state current. The simulation results show that there is an optimum choice for the overlapped length. On the other hand, this overlap deteriorates the high frequency performance. The high frequency figure of merit is analyzed in terms of the unit-gain cutoff frequency (fT). Further, we propose two different approaches to improve the high frequency performance of the overlapped T-CNTFET. The first one is based on inserting a high-dielectric constant material below the overlapped part of the gate and the second is based on depositing a different work function gate metal for the overlapped region. The two solutions show very good improvement in the high frequency performance with maintaining the suppression of the ambipolar characteristics.

Measurement of transverse emittance and coherence of double-gate field emitter array cathodes

NASA Astrophysics Data System (ADS)

Tsujino, Soichiro; Das Kanungo, Prat; Monshipouri, Mahta; Lee, Chiwon; Miller, R. J. Dwayne

2016-12-01

Achieving small transverse beam emittance is important for high brightness cathodes for free electron lasers and electron diffraction and imaging experiments. Double-gate field emitter arrays with on-chip focussing electrode, operating with electrical switching or near infrared laser excitation, have been studied as cathodes that are competitive with photocathodes excited by ultraviolet lasers, but the experimental demonstration of the low emittance has been elusive. Here we demonstrate this for a field emitter array with an optimized double-gate structure by directly measuring the beam characteristics. Further we show the successful application of the double-gate field emitter array to observe the low-energy electron beam diffraction from suspended graphene in minimal setup. The observed low emittance and long coherence length are in good agreement with theory. These results demonstrate that our all-metal double-gate field emitters are highly promising for applications that demand extremely low-electron bunch-phase space volume and large transverse coherence.

Flow monitoring and control system for injection wells

DOEpatents

Corey, John C.

1993-01-01

A system for monitoring and controlling the injection rate of fluid by an injection well of an in-situ remediation system for treating a contaminated groundwater plume. The well is fitted with a gated insert, substantially coaxial with the injection well. A plurality of openings, some or all of which are equipped with fluid flow sensors and gates, are spaced along the insert. The gates and sensors are connected to a surface controller. The insert may extend throughout part of, or substantially the entire length of the injection well. Alternatively, the insert may comprise one or more movable modules which can be positioned wherever desired along the well. The gates are opened part-way at the start of treatment. The sensors monitor and display the flow rate of fluid passing through each opening on a controller. As treatment continues, the gates are opened to increase flow in regions of lesser flow, and closed to decrease flow in regions of greater flow, thereby approximately equalizing the amount of fluid reaching each part of the plume.

Flow monitoring and control system for injection wells

DOEpatents

Corey, J.C.

1993-02-16

A system for monitoring and controlling the injection rate of fluid by an injection well of an in-situ remediation system for treating a contaminated groundwater plume. The well is fitted with a gated insert, substantially coaxial with the injection well. A plurality of openings, some or all of which are equipped with fluid flow sensors and gates, are spaced along the insert. The gates and sensors are connected to a surface controller. The insert may extend throughout part of, or substantially the entire length of the injection well. Alternatively, the insert may comprise one or more movable modules which can be positioned wherever desired along the well. The gates are opened part-way at the start of treatment. The sensors monitor and display the flow rate of fluid passing through each opening on a controller. As treatment continues, the gates are opened to increase flow in regions of lesser flow, and closed to decrease flow in regions of greater flow, thereby approximately equalizing the amount of fluid reaching each part of the plume.

Gate-Driven Pure Spin Current in Graphene

NASA Astrophysics Data System (ADS)

Lin, Xiaoyang; Su, Li; Si, Zhizhong; Zhang, Youguang; Bournel, Arnaud; Zhang, Yue; Klein, Jacques-Olivier; Fert, Albert; Zhao, Weisheng

2017-09-01

The manipulation of spin current is a promising solution for low-power devices beyond CMOS. However, conventional methods, such as spin-transfer torque or spin-orbit torque for magnetic tunnel junctions, suffer from large power consumption due to frequent spin-charge conversions. An important challenge is, thus, to realize long-distance transport of pure spin current, together with efficient manipulation. Here, the mechanism of gate-driven pure spin current in graphene is presented. Such a mechanism relies on the electrical gating of carrier-density-dependent conductivity and spin-diffusion length in graphene. The gate-driven feature is adopted to realize the pure spin-current demultiplexing operation, which enables gate-controllable distribution of the pure spin current into graphene branches. Compared with the Elliott-Yafet spin-relaxation mechanism, the D'yakonov-Perel spin-relaxation mechanism results in more appreciable demultiplexing performance. The feature of the pure spin-current demultiplexing operation will allow a number of logic functions to be cascaded without spin-charge conversions and open a route for future ultra-low-power devices.

The LER/LWR metrology challenge for advance process control through 3D-AFM and CD-SEM

NASA Astrophysics Data System (ADS)

Faurie, P.; Foucher, J.; Foucher, A.-L.

2009-12-01

The continuous shrinkage in dimensions of microelectronic devices has reached such level, with typical gate length in advance R&D of less than 20nm combine with the introduction of new architecture (FinFET, Double gate...) and new materials (porous interconnect material, 193 immersion resist, metal gate material, high k materials...), that new process parameters have to be well understood and well monitored to guarantee sufficient production yield in a near future. Among these parameters, there are the critical dimensions (CD) associated to the sidewall angle (SWA) values, the line edge roughness (LER) and the line width roughness (LWR). Thus, a new metrology challenge has appeared recently and consists in measuring "accurately" the fabricated patterns on wafers in addition to measure the patterns on a repeatable way. Therefore, a great effort has to be done on existing techniques like CD-SEM, Scatterometry and 3D-AFM in order to develop them following the two previous criteria: Repeatability and Accuracy. In this paper, we will compare the 3D-AFM and CD-SEM techniques as a mean to measure LER and LWR on silicon and 193 resist and point out CD-SEM impact on the material during measurement. Indeed, depending on the material type, the interaction between the electron beam and the material or between the AFM tip and the material can vary a lot and subsequently can generate measurements bias. The first results tend to show that depending on CD-SEM conditions (magnification, number of acquisition frames) the final outputs can vary on a large range and therefore show that accuracy in such measurements are really not obvious to obtain. On the basis of results obtained on various materials that present standard sidewall roughness, we will show the limit of each technique and will propose different ways to improve them in order to fulfil advance roadmap requirements for the development of the next IC generation.

Synchrotron Radiation Lithography for Manufacturing Integrated Circuits Beyond 100 nm.

PubMed

Kinoshita, H; Watanabe, T; Niibe, M

1998-05-01

Extreme ultraviolet lithography is a powerful tool for printing features of 0.1 micro m and below; in Japan and the USA there is a growing tendency to view it as the wave of the future. With Schwarzschild optics, replication of a 0.05 micro m pattern has been demonstrated in a 25 micro m square area. With a two-aspherical-mirror system, a 0.15 micro m pattern has been replicated in a ring slit area of 20 mm x 0.4 mm; a combination of this system with illumination optics and synchronized mask and wafer stages has enabled the replication of a 0.15 micro m pattern in an area of 10 mm x 12.5 mm. Furthermore, in the USA, the Sandia National Laboratory has succeeded in fabricating a fully operational NMOS transistor with a gate length of 0.1 micro m. The most challenging problem is the fabrication of mirrors with the required figure error of 0.28 nm. However, owing to advances in measurement technology, mirrors can now be made to a precision that almost satisfies this requirement. Therefore, it is time to move into a rapid development phase in order to obtain a system ready for practical use by the year 2004. In this paper the status of individual technologies is discussed in light of this situation, and future requirements for developing a practical system are considered.

CFD simulation of hemodynamics in sequential and individual coronary bypass grafts based on multislice CT scan datasets.

PubMed

Hajati, Omid; Zarrabi, Khalil; Karimi, Reza; Hajati, Azadeh

2012-01-01

There is still controversy over the differences in the patency rates of the sequential and individual coronary artery bypass grafting (CABG) techniques. The purpose of this paper was to non-invasively evaluate hemodynamic parameters using complete 3D computational fluid dynamics (CFD) simulations of the sequential and the individual methods based on the patient-specific data extracted from computed tomography (CT) angiography. For CFD analysis, the geometric model of coronary arteries was reconstructed using an ECG-gated 64-detector row CT. Modeling the sequential and individual bypass grafting, this study simulates the flow from the aorta to the occluded posterior descending artery (PDA) and the posterior left ventricle (PLV) vessel with six coronary branches based on the physiologically measured inlet flow as the boundary condition. The maximum calculated wall shear stress (WSS) in the sequential and the individual models were estimated to be 35.1 N/m(2) and 36.5 N/m(2), respectively. Compared to the individual bypass method, the sequential graft has shown a higher velocity at the proximal segment and lower spatial wall shear stress gradient (SWSSG) due to the flow splitting caused by the side-to-side anastomosis. Simulated results combined with its surgical benefits including the requirement of shorter vein length and fewer anastomoses advocate the sequential method as a more favorable CABG method.

Gate oxide thickness dependence of the leakage current mechanism in Ru/Ta2O5/SiON/Si structures

NASA Astrophysics Data System (ADS)

Ťapajna, M.; Paskaleva, A.; Atanassova, E.; Dobročka, E.; Hušeková, K.; Fröhlich, K.

2010-07-01

Leakage conduction mechanisms in Ru/Ta2O5/SiON/Si structures with rf-sputtered Ta2O5 with thicknesses ranging from 13.5 to 1.8 nm were systematically studied. Notable reaction at the Ru/Ta2O5 interface was revealed by capacitance-voltage measurements. Temperature-dependent current-voltage characteristics suggest the bulk-limited conduction mechanism in all metal-oxide-semiconductor structures. Under gate injection, Poole-Frenkel emission was identified as a dominant mechanism for 13.5 nm thick Ta2O5. With an oxide thickness decreasing down to 3.5 nm, the conduction mechanism transforms to thermionic trap-assisted tunnelling through the triangular barrier. Under substrate injection, the dominant mechanism gradually changes with decreasing thickness from thermionic trap-assisted tunnelling to trap-assisted tunnelling through the triangular barrier; Poole-Frenkel emission was not observed at all. A 0.7 eV deep defect level distributed over Ta2O5 is assumed to be responsible for bulk-limited conduction mechanisms and is attributed to H-related defects or oxygen vacancies in Ta2O5.

Efficient Multi-Dimensional Simulation of Quantum Confinement Effects in Advanced MOS Devices

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Ancona, Mario G.; Rafferty, Conor S.; Yu, Zhiping

2000-01-01

We investigate the density-gradient (DG) transport model for efficient multi-dimensional simulation of quantum confinement effects in advanced MOS devices. The formulation of the DG model is described as a quantum correction ot the classical drift-diffusion model. Quantum confinement effects are shown to be significant in sub-100nm MOSFETs. In thin-oxide MOS capacitors, quantum effects may reduce gate capacitance by 25% or more. As a result, the inclusion of quantum effects may reduce gate capacitance by 25% or more. As a result, the inclusion of quantum effects in simulations dramatically improves the match between C-V simulations and measurements for oxide thickness down to 2 nm. Significant quantum corrections also occur in the I-V characteristics of short-channel (30 to 100 nm) n-MOSFETs, with current drive reduced by up to 70%. This effect is shown to result from reduced inversion charge due to quantum confinement of electrons in the channel. Also, subthreshold slope is degraded by 15 to 20 mV/decade with the inclusion of quantum effects via the density-gradient model, and short channel effects (in particular, drain-induced barrier lowering) are noticeably increased.

Scaling of graphene integrated circuits.

PubMed

Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

2015-05-07

The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

Genotyping of single nucleotide polymorphism by probe-gated silica nanoparticles.

PubMed

Ercan, Meltem; Ozalp, Veli C; Tuna, Bilge G

2017-11-15

The development of simple, reliable, and rapid approaches for molecular detection of common mutations is important for prevention and early diagnosis of genetic diseases, including Thalessemia. Oligonucleotide-gated mesoporous nanoparticles-based analysis is a new platform for mutation detection that has the advantages of sensitivity, rapidity, accuracy, and convenience. A specific mutation in β-thalassemia, one of the most prevalent inherited diseases in several countries, was used as model disease in this study. An assay for detection of IVS110 point mutation (A > G reversion) was developed by designing probe-gated mesoporous silica nanoparticles (MCM-41) loaded with reporter fluorescein molecules. The silica nanoparticles were characterized by AFM, TEM and BET analysis for having 180 nm diameter and 2.83 nm pore size regular hexagonal shape. Amine group functionalized nanoparticles were analysed with FTIR technique. Mutated and normal sequence probe oligonucleotides)about 12.7 nmol per mg nanoparticles) were used to entrap reporter fluorescein molecules inside the pores and hybridization with single stranded DNA targets amplified by PCR gave different fluorescent signals for mutated targets. Samples from IVS110 mutated and normal patients resulted in statistically significant differences when the assay procedure were applied. Copyright © 2017 Elsevier Inc. All rights reserved.

Characterization of Plasma-Induced Damage of Selectively Recessed GaN/InAlN/AlN/GaN Heterostructures Using SiCl4 and SF6

NASA Astrophysics Data System (ADS)

Ostermaier, Clemens; Pozzovivo, Gianmauro; Basnar, Bernhard; Schrenk, Werner; Carlin, Jean-François; Gonschorek, Marcus; Grandjean, Nicolas; Vincze, Andrej; Tóth, Lajos; Pécz, Bela; Strasser, Gottfried; Pogany, Dionyz; Kuzmik, Jan

2010-11-01

We have investigated an inductively coupled plasma etching recipe using SiCl4 and SF6 with a resulting selectivity >10 for GaN in respect to InAlN. The formation of an etch-resistant layer of AlF3 on InAlN required about 1 min and was noticed by a 4-times-higher initial etch rate on bare InAlN barrier high electron mobility transistors (HEMTs). Comparing devices with and without plasma-treatment below the gate showed no degradation in drain current and gate leakage current for plasma exposure durations shorter than 30 s, indicating no plasma-induced damage of the InAlN barrier. Devices etched longer than the required time for the formation of the etch-resistant barrier exhibited a slight decrease in drain current and an increase in gate leakage current which saturated for longer etching-time durations. Finally, we could prove the quality of the recipe by recessing the highly doped 6 nm GaN cap layer of a GaN/InAlN/AlN/GaN heterostructure down to the 2 nm thin InAlN/AlN barrier layer.

Periodic structure formation and surface morphology evolution of glassy carbon surfaces applying 35-fs-200-ps laser pulses

NASA Astrophysics Data System (ADS)

Csontos, J.; Toth, Z.; Pápa, Z.; Budai, J.; Kiss, B.; Börzsönyi, A.; Füle, M.

2016-06-01

In this work laser-induced periodic structures with lateral dimensions smaller than the central wavelength of the laser were studied on glassy carbon as a function of laser pulse duration. To generate diverse pulse durations titanium-sapphire (Ti:S) laser (center wavelength 800 nm, pulse durations: 35 fs-200 ps) and a dye-KrF excimer laser system (248 nm, pulse durations: 280 fs, 2.1 ps) were used. In the case of Ti:S laser treatment comparing the central part of the laser-treated areas a striking difference is observed between the femtoseconds and picoseconds treatments. Ripple structure generated with short pulse durations can be characterized with periodic length significantly smaller than the laser wavelength (between 120 and 165 nm). At higher pulse durations the structure has a higher periodic length (between 780 and 800 nm), which is comparable to the wavelength. In case of the excimer laser treatment the different pulse durations produced similar surface structures with different periodic length and different orientation. One of the structures was parallel with the polarization of the laser light and has a higher periodic length (~335 nm), and the other was perpendicular with smaller periodic length (~78-80 nm). The possible mechanisms of structure formation will be outlined and discussed in the frame of our experimental results.

Super-resolution imaging of ciliary microdomains in isolated olfactory sensory neurons using a custom two-color stimulated emission depletion microscope

NASA Astrophysics Data System (ADS)

Meyer, Stephanie A.; Ozbay, Baris N.; Potcoava, Mariana; Salcedo, Ernesto; Restrepo, Diego; Gibson, Emily A.

2016-06-01

We performed stimulated emission depletion (STED) imaging of isolated olfactory sensory neurons (OSNs) using a custom-built microscope. The STED microscope uses a single pulsed laser to excite two separate fluorophores, Atto 590 and Atto 647N. A gated timing circuit combined with temporal interleaving of the different color excitation/STED laser pulses filters the two channel detection and greatly minimizes crosstalk. We quantified the instrument resolution to be ˜81 and ˜44 nm, for the Atto 590 and Atto 647N channels. The spatial separation between the two channels was measured to be under 10 nm, well below the resolution limit. The custom-STED microscope is incorporated onto a commercial research microscope allowing brightfield, differential interference contrast, and epifluorescence imaging on the same field of view. We performed immunolabeling of OSNs in mice to image localization of ciliary membrane proteins involved in olfactory transduction. We imaged Ca2+-permeable cyclic nucleotide gated (CNG) channel (Atto 594) and adenylyl cyclase type III (ACIII) (Atto 647N) in distinct cilia. STED imaging resolved well-separated subdiffraction limited clusters for each protein. We quantified the size of each cluster to have a mean value of 88±48 nm and 124±43 nm, for CNG and ACIII, respectively. STED imaging showed separated clusters that were not resolvable in confocal images.

Design architecture of double spiral interdigitated electrode with back gate electrode for biosensor application

NASA Astrophysics Data System (ADS)

Fathil, M. F. M.; Arshad, M. K. Md.; Hashim, U.; Ruslinda, A. R.; Gopinath, Subash C. B.; M. Nuzaihan M., N.; Ayub, R. M.; Adzhri, R.; Zaki, M.; Azman, A. H.

2016-07-01

This paper presents the preparation method of photolithography chrome mask design used in fabrication process of double spiral interdigitated electrode with back gate biasing based biosensor. By learning the fabrication process flow of the biosensor, the chrome masks are designed through drawing using the AutoCAD software. The overall width and length of the device is optimized at 7.0 mm and 10.0 mm, respectively. Fabrication processes of the biosensor required three chrome masks, which included back gate opening, spiral IDE formation, and passivation area formation. The complete chrome masks design will be sent for chrome mask fabrication and for future use in biosensor fabrication.

Gate-tunable gigantic lattice deformation in VO{sub 2}

DOE Office of Scientific and Technical Information (OSTI.GOV)

Okuyama, D., E-mail: okuyama@riken.jp, E-mail: nakano@imr.tohoku.ac.jp, E-mail: iwasa@ap.t.u-tokyo.ac.jp; Hatano, T.; Nakano, M., E-mail: okuyama@riken.jp, E-mail: nakano@imr.tohoku.ac.jp, E-mail: iwasa@ap.t.u-tokyo.ac.jp

2014-01-13

We examined the impact of electric field on crystal lattice of vanadium dioxide (VO{sub 2}) in a field-effect transistor geometry by in-situ synchrotron x-ray diffraction measurements. Whereas the c-axis lattice parameter of VO{sub 2} decreases through the thermally induced insulator-to-metal phase transition, the gate-induced metallization was found to result in a significant increase of the c-axis length by almost 1% from that of the thermally stabilized insulating state. We also found that this gate-induced gigantic lattice deformation occurs even at the thermally stabilized metallic state, enabling dynamic control of c-axis lattice parameter by more than 1% at room temperature.

Photo-Patterned Ion Gel Electrolyte-Gated Thin Film Transistors

NASA Astrophysics Data System (ADS)

Choi, Jae-Hong; Gu, Yuanyan; Hong, Kihyun; Frisbie, C. Daniel; Lodge, Timothy P.

2014-03-01

We have developed a novel fabrication route to pattern electrolyte thin films in electrolyte-gated transistors (EGTs) using a chemically crosslinkable ABA-triblock copolymer ion gel. In the self-assembly of poly[(styrene-r-vinylbenzylazide)-b-ethylene oxide-b-(styrene-r-vinylbenzylazide)] (SOS-N3) triblock copolymer and the ionic liquid, 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ([EMI][TFSI]), the azide groups of poly(styrene-r-vinylbenzylazide) (PS-N3) end-blocks in the cores can be chemically cross-linked via UV irradiation (λ = 254 nm). Impedance spectroscopy and small-angle X-ray scattering confirmed that ion transport and microstructure of the ion gel are not affected by UV cross-linking. Using this chemical cross-linking strategy, we demonstrate a photo-patterning of ion gels through a patterned mask and the fabricated electrolyte-gated thin film transistors with photo-patterned ion gels as high-capacitance gate insulators exhibited high device performance (low operation voltages and high on/off current ratios).

Comparative Study of HfTa-based gate-dielectric Ge metal-oxide-semiconductor capacitors with and without AlON interlayer

NASA Astrophysics Data System (ADS)

Xu, J. P.; Zhang, X. F.; Li, C. X.; Chan, C. L.; Lai, P. T.

2010-04-01

The electrical properties and high-field reliability of HfTa-based gate-dielectric metal-oxide-semiconductor (MOS) devices with and without AlON interlayer on Ge substrate are investigated. Experimental results show that the MOS capacitor with HfTaON/AlON stack gate dielectric exhibits low interface-state/oxide-charge densities, low gate leakage, small capacitance equivalent thickness (˜1.1 nm), and high dielectric constant (˜20). All of these should be attributed to the blocking role of the ultrathin AlON interlayer against interdiffusions of Ge, Hf, and Ta and penetration of O into the Ge substrate, with the latter effectively suppressing the unintentional formation of unstable poor-quality low- k GeO x and giving a superior AlON/Ge interface. Moreover, incorporation of N into both the interlayer and high- k dielectric further improves the device reliability under high-field stress through the formation of strong N-related bonds.

Artificial neuron synapse transistor based on silicon nanomembrane on plastic substrate

NASA Astrophysics Data System (ADS)

Liu, Minjie; Huang, Gaoshan; Feng, Ping; Guo, Qinglei; Shao, Feng; Tian, Ziao; Li, Gongjin; Wan, Qing; Mei, Yongfeng

2017-06-01

Silicon nanomembrane (SiNM) transistors gated by chitosan membrane were fabricated on plastic substrate to mimic synapse behaviors. The device has both a bottom proton gate (BG) and multiple side gates (SG). Electrical transfer properties of BG show hysteresis curves different from those of typical SiO2 gate dielectric. Synaptic behaviors and functions by linear accumulation and release of protons have been mimicked on this device: excitatory post-synaptic current (EPSC) and paired pulse facilitation behavior of biological synapses were mimicked and the paired-pulse facilitation index could be effectively tuned by the spike interval applied on the BG. Synaptic behaviors and functions, including short-term memory and long-term memory, were also experimentally demonstrated in BG mode. Meanwhile, spiking logic operation and logic modulation were realized in SG mode. Project supported by the National Natural Science Foundation of China (No. 51322201), the Specialized Research Fund for the Doctoral Program of Higher Education (No. 20120071110025), and Science and Technology Commission of Shanghai Municipality (No. 14JC1400200).

Image averaging of flexible fibrous macromolecules: the clathrin triskelion has an elastic proximal segment.

PubMed

Kocsis, E; Trus, B L; Steer, C J; Bisher, M E; Steven, A C

1991-08-01

We have developed computational techniques that allow image averaging to be applied to electron micrographs of filamentous molecules that exhibit tight and variable curvature. These techniques, which involve straightening by cubic-spline interpolation, image classification, and statistical analysis of the molecules' curvature properties, have been applied to purified brain clathrin. This trimeric filamentous protein polymerizes, both in vivo and in vitro, into a wide range of polyhedral structures. Contrasted by low-angle rotary shadowing, dissociated clathrin molecules appear as distinctive three-legged structures, called "triskelions" (E. Ungewickell and D. Branton (1981) Nature 289, 420). We find triskelion legs to vary from 35 to 62 nm in total length, according to an approximately bell-shaped distribution (mu = 51.6 nm). Peaks in averaged curvature profiles mark hinges or sites of enhanced flexibility. Such profiles, calculated for each length class, show that triskelion legs are flexible over their entire lengths. However, three curvature peaks are observed in every case: their locations define a proximal segment of systematically increasing length (14.0-19.0 nm), a mid-segment of fixed length (approximately 12 nm), and a rather variable end-segment (11.6-19.5 nm), terminating in a hinge just before the globular terminal domain (approximately 7.3 nm diameter). Thus, two major factors contribute to the overall variability in leg length: (1) stretching of the proximal segment and (2) stretching of the end-segment and/or scrolling of the terminal domain. The observed elasticity of the proximal segment may reflect phosphorylation of the clathrin light chains.

Dielectric collapse at the LaAlO 3/SrTiO 3 (001) heterointerface under applied electric field

DOE Office of Scientific and Technical Information (OSTI.GOV)

Minohara, M.; Hikita, Y.; Bell, C.

The fascinating interfacial transport properties at the LaAlO 3/SrTiO 3 heterointerface have led to intense investigations of this oxide system. Exploiting the large dielectric constant of SrTiO 3 at low temperatures, tunability in the interfacial conductivity over a wide range has been demonstrated using a back-gate device geometry. In order to understand the effect of back-gating, it is crucial to assess the interface band structure and its evolution with external bias. In this study, we report measurements of the gate-bias dependent interface band alignment, especially the confining potential profile, at the conducting LaAlO 3/SrTiO 3 (001) heterointerface using soft andmore » hard x-ray photoemission spectroscopy in conjunction with detailed model simulations. Depth-profiling analysis incorporating the electric field dependent dielectric constant in SrTiO 3 reveals that a significant potential drop on the SrTiO 3 side of the interface occurs within ~2 nm of the interface under negative gate-bias. These results demonstrate gate control of the collapse of the dielectric permittivity at the interface, and explain the dramatic loss of electron mobility with back-gate depletion.« less

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors.

PubMed

Gluschke, J G; Seidl, J; Lyttleton, R W; Carrad, D J; Cochrane, J W; Lehmann, S; Samuelson, L; Micolich, A P

2018-06-27

We report the development of nanowire field-effect transistors featuring an ultrathin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally coated nanowires, which we used to produce functional Ω-gate and gate-all-around structures. These give subthreshold swings as low as 140 mV/dec and on/off ratios exceeding 10 3 at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically treated nanowire surfaces, a feature generally not possible with oxides produced by atomic layer deposition due to the surface "self-cleaning" effect. Our results highlight the potential for parylene as an alternative ultrathin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties.

Dielectric collapse at the LaAlO 3/SrTiO 3 (001) heterointerface under applied electric field

DOE PAGES

Minohara, M.; Hikita, Y.; Bell, C.; ...

2017-08-25

The fascinating interfacial transport properties at the LaAlO 3/SrTiO 3 heterointerface have led to intense investigations of this oxide system. Exploiting the large dielectric constant of SrTiO 3 at low temperatures, tunability in the interfacial conductivity over a wide range has been demonstrated using a back-gate device geometry. In order to understand the effect of back-gating, it is crucial to assess the interface band structure and its evolution with external bias. In this study, we report measurements of the gate-bias dependent interface band alignment, especially the confining potential profile, at the conducting LaAlO 3/SrTiO 3 (001) heterointerface using soft andmore » hard x-ray photoemission spectroscopy in conjunction with detailed model simulations. Depth-profiling analysis incorporating the electric field dependent dielectric constant in SrTiO 3 reveals that a significant potential drop on the SrTiO 3 side of the interface occurs within ~2 nm of the interface under negative gate-bias. These results demonstrate gate control of the collapse of the dielectric permittivity at the interface, and explain the dramatic loss of electron mobility with back-gate depletion.« less

Programmable Schottky Junctions Based on Ferroelectric Gated MoS2 Transistors

NASA Astrophysics Data System (ADS)

Xiao, Zhiyong; Song, Jingfeng; Drcharme, Stephen; Hong, Xia

We report a programmable Schottky junction based on MoS2 field effect transistors with a SiO2 back gate and a ferroelectric copolymer poly(vinylidene-fluoride-trifluorethylene) (PVDF) top gate. We fabricated mechanically exfoliated single layer MoS2 flakes into two point devices via e-beam lithography, and deposited on the top of the devices ~20 nm PVDF thin films. The polarization of the PVDF layer is controlled locally by conducting atomic force microscopy. The devices exhibit linear ID-VD characteristics when the ferroelectric gate is uniformly polarized in one direction. We then polarized the gate into two domains with opposite polarization directions, and observed that the ID-VD characteristics of the MoS2 channel can be modulated between linear and rectified behaviors depending on the back gate voltage. The nonlinear ID-VD relation emerges when half of the channel is in the semiconductor phase while the other half is in the metallic phase, and it can be well described by the thermionic emission model with a Schottky barrier of ~0.5 eV. The Schottky junction can be erased by re-write the entire channel in the uniform polarization state. Our study facilitates the development of programmable, multifunctional nanoelectronics based on layered 2D TMDs..

Analysis of power gating in different hierarchical levels of 2MB cache, considering variation

NASA Astrophysics Data System (ADS)

Jafari, Mohsen; Imani, Mohsen; Fathipour, Morteza

2015-09-01

This article reintroduces power gating technique in different hierarchical levels of static random-access memory (SRAM) design including cell, row, bank and entire cache memory in 16 nm Fin field effect transistor. Different structures of SRAM cells such as 6T, 8T, 9T and 10T are used in design of 2MB cache memory. The power reduction of the entire cache memory employing cell-level optimisation is 99.7% with the expense of area and other stability overheads. The power saving of the cell-level optimisation is 3× (1.2×) higher than power gating in cache (bank) level due to its superior selectivity. The access delay times are allowed to increase by 4% in the same energy delay product to achieve the best power reduction for each supply voltages and optimisation levels. The results show the row-level power gating is the best for optimising the power of the entire cache with lowest drawbacks. Comparisons of cells show that the cells whose bodies have higher power consumption are the best candidates for power gating technique in row-level optimisation. The technique has the lowest percentage of saving in minimum energy point (MEP) of the design. The power gating also improves the variation of power in all structures by at least 70%.

Evaluation of left ventricular function using electrocardiographically gated myocardial SPECT with (123)I-labeled fatty acid analog.

PubMed

Nanasato, M; Ando, A; Isobe, S; Nonokawa, M; Hirayama, H; Tsuboi, N; Ito, T; Hirai, M; Yokota, M; Saito, H

2001-12-01

Electrocardiographically (ECG) gated myocardial SPECT with (99m)Tc-tetrofosmin has been used widely to assess left ventricular (LV) function. However, the accuracy of variables using ECG gated myocardial SPECT with beta-methyl-p-(123)I-iodophenylpentadecanoic acid (BMIPP) has not been well defined. Thirty-six patients (29 men, 7 women; mean age, 61.6 +/- 15.6 y) with ischemic heart disease underwent ECG gated myocardial SPECT with (123)I-BMIPP and with (99m)Tc-tetrofosmin and left ventriculography (LVG) within 1 wk. LV ejection fraction (LVEF), LV end-diastolic volume (LVEDV), and LV end-systolic volume (LVESV) were determined on gated SPECT using commercially available software for automatic data analysis. These volume-related items on LVG were calculated with an area-length method and were estimated by 2 independent observers to evaluate interobserver validity. The regional wall motion with these methods was assessed visually. LVEF was 41.1% +/- 12.5% on gated SPECT with (123)I-BMIPP, 44.5% +/- 13.1% on gated SPECT with (99m)Tc-tetrofosmin, and 46.0% +/- 12.7% on LVG. Global LV function and regional wall motion between both gated SPECT procedures had excellent correlation (LVEF, r = 0.943; LVEDV, r = 0.934; LVESV, r = 0.952; regional wall motion, kappa = 0.92). However, the correlations of global LV function and regional wall motion between each gated SPECT and LVG were significantly lower. Gated SPECT with (123)I-BMIPP showed the same interobserver validity as gated SPECT with (99m)Tc-tetrofosmin. Gated SPECT with (123)I-BMIPP provides high accuracy with regard to LV function and is sufficiently applicable for use in clinical SPECT. This technique can simultaneously reveal myocardial fatty acid metabolism and LV function, which may be useful to evaluate various cardiac diseases.

SU-E-T-350: Verification of Gating Performance of a New Elekta Gating Solution: Response Kit and Catalyst System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xie, X; Cao, D; Housley, D

2014-06-01

Purpose: In this work, we have tested the performance of new respiratory gating solutions for Elekta linacs. These solutions include the Response gating and the C-RAD Catalyst surface mapping system.Verification measurements have been performed for a series of clinical cases. We also examined the beam on latency of the system and its impact on delivery efficiency. Methods: To verify the benefits of tighter gating windows, a Quasar Respiratory Motion Platform was used. Its vertical-motion plate acted as a respiration surrogate and was tracked by the Catalyst system to generate gating signals. A MatriXX ion-chamber array was mounted on its longitudinal-movingmore » platform. Clinical plans are delivered to a stationary and moving Matrix array at 100%, 50% and 30% gating windows and gamma scores were calculated comparing moving delivery results to the stationary result. It is important to note that as one moves to tighter gating windows, the delivery efficiency will be impacted by the linac's beam-on latency. Using a specialized software package, we generated beam-on signals of lengths of 1000ms, 600ms, 450ms, 400ms, 350ms and 300ms. As the gating windows get tighter, one can expect to reach a point where the dose rate will fall to nearly zero, indicating that the gating window is close to beam-on latency. A clinically useful gating window needs to be significantly longer than the latency for the linac. Results: As expected, the use of tighter gating windows improved delivery accuracy. However, a lower limit of the gating window, largely defined by linac beam-on latency, exists at around 300ms. Conclusion: The Response gating kit, combined with the C-RAD Catalyst, provides an effective solution for respiratorygated treatment delivery. Careful patient selection, gating window design, even visual/audio coaching may be necessary to ensure both delivery quality and efficiency. This research project is funded by Elekta.« less

Characterization and metrology implications of the 1997 NTRS

NASA Astrophysics Data System (ADS)

Class, W.; Wortman, J. J.

1998-11-01

In the Front-end (transistor forming) area of silicon CMOS device processing, several NTRS difficult challenges have been identified including; scaled and alternate gate dielectric materials, new DRAM dielectric materials, alternate gate materials, elevated contact structures, engineered channels, and large-area cost-effective silicon substrates. This paper deals with some of the characterization and metrology challenges facing the industry if it is to meet the projected needs identified in the NTRS. In the areas of gate and DRAM dielectric, scaling requires that existing material layers be thinned to maximize capacitance. For the current gate dielectric, SiO2 and its nitrided derivatives, direct tunneling will limit scaling to approximately 1.5nm for logic applications before power losses become unacceptable. Low power logic and memory applications may limit scaling to the 2.0-2.2nm range. Beyond these limits, dielectric materials having higher dielectric constant, will permit continued capacitance increases while allowing for the use of thicker dielectric layers, where tunneling may be minimized. In the near term silicon nitride is a promising SiO2 substitute material while in the longer term "high-k" materials such as tantalum pentoxide and barium strontium titanate (BST) will be required. For these latter materials, it is likely that a multilayer dielectric stack will be needed, consisting of an ultra-thin (1-2 atom layer) interfacial SiO2 layer and a high-k overlayer. Silicon wafer surface preparation control, as well as the control of composition, crystal structure, and thickness for such stacks pose significant characterization and metrology challenges. In addition to the need for new gate dielectric materials, new gate materials will be required to overcome the limitations of the current doped polysilicon gate materials. Such a change has broad ramifications on device electrical performance and manufacturing process robustness which again implies a broad range of new characterization and metrology requirements. Finally, the doped structure of the MOS transistor must scale to very small lateral and depth dimensions, and thermal budgets must be reduced to permit the retention of very abrupt highly doped drain and channel engineered structures. Eventually, the NTRS forecasts the need for an elevated contact structure. Here, there are significant challenges associated with three-dimensional dopant profiling, measurement of dopant activity in ultra-shallow device regions, as well as point defect metrology and characterization.

Validation of New Process Models for Large Injection-Molded Long-Fiber Thermoplastic Composite Structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nguyen, Ba Nghiep; Jin, Xiaoshi; Wang, Jin

2012-02-23

This report describes the work conducted under the CRADA Nr. PNNL/304 between Battelle PNNL and Autodesk whose objective is to validate the new process models developed under the previous CRADA for large injection-molded LFT composite structures. To this end, the ARD-RSC and fiber length attrition models implemented in the 2013 research version of Moldflow was used to simulate the injection molding of 600-mm x 600-mm x 3-mm plaques from 40% glass/polypropylene (Dow Chemical DLGF9411.00) and 40% glass/polyamide 6,6 (DuPont Zytel 75LG40HSL BK031) materials. The injection molding was performed by Injection Technologies, Inc. at Windsor, Ontario (under a subcontract by Oakmore » Ridge National Laboratory, ORNL) using the mold offered by the Automotive Composite Consortium (ACC). Two fill speeds under the same back pressure were used to produce plaques under slow-fill and fast-fill conditions. Also, two gating options were used to achieve the following desired flow patterns: flows in edge-gated plaques and in center-gated plaques. After molding, ORNL performed measurements of fiber orientation and length distributions for process model validations. The structure of this report is as follows. After the Introduction (Section 1), Section 2 provides a summary of the ARD-RSC and fiber length attrition models. A summary of model implementations in the latest research version of Moldflow is given in Section 3. Section 4 provides the key processing conditions and parameters for molding of the ACC plaques. The validations of the ARD-RSC and fiber length attrition models are presented and discussed in Section 5. The conclusions will be drawn in Section 6.« less

Structure of a prokaryotic sodium channel pore reveals essential gating elements and an outer ion binding site common to eukaryotic channels.

PubMed

Shaya, David; Findeisen, Felix; Abderemane-Ali, Fayal; Arrigoni, Cristina; Wong, Stephanie; Nurva, Shailika Reddy; Loussouarn, Gildas; Minor, Daniel L

2014-01-23

Voltage-gated sodium channels (NaVs) are central elements of cellular excitation. Notwithstanding advances from recent bacterial NaV (BacNaV) structures, key questions about gating and ion selectivity remain. Here, we present a closed conformation of NaVAe1p, a pore-only BacNaV derived from NaVAe1, a BacNaV from the arsenite oxidizer Alkalilimnicola ehrlichei found in Mono Lake, California, that provides insight into both fundamental properties. The structure reveals a pore domain in which the pore-lining S6 helix connects to a helical cytoplasmic tail. Electrophysiological studies of full-length BacNaVs show that two elements defined by the NaVAe1p structure, an S6 activation gate position and the cytoplasmic tail "neck", are central to BacNaV gating. The structure also reveals the selectivity filter ion entry site, termed the "outer ion" site. Comparison with mammalian voltage-gated calcium channel (CaV) selectivity filters, together with functional studies, shows that this site forms a previously unknown determinant of CaV high-affinity calcium binding. Our findings underscore commonalities between BacNaVs and eukaryotic voltage-gated channels and provide a framework for understanding gating and ion permeation in this superfamily. © 2013. Published by Elsevier Ltd. All rights reserved.

Probabilistic Description of Fatigue Crack Growth Under Constant-and Variable-Amplitude Loading

DTIC Science & Technology

1989-03-01

plane, see figure 14. The length of the defected crack component and its angle, b and q, respectively, in Figure 15 were found to depend on the crack...length at which the defection occurs; as the crack length increases, b increases while q decreases. Due to the orientation of the deflected component...Breakpoint Voltage to Fun. Generator Output Setpoint Voltage Take Function Generator Gate High Start Test LNext page 153 Q! ~From last ag lastr DMAe 70

The GaN trench gate MOSFET with floating islands: High breakdown voltage and improved BFOM

NASA Astrophysics Data System (ADS)

Shen, Lingyan; Müller, Stephan; Cheng, Xinhong; Zhang, Dongliang; Zheng, Li; Xu, Dawei; Yu, Yuehui; Meissner, Elke; Erlbacher, Tobias

2018-02-01

A novel GaN trench gate (TG) MOSFET with P-type floating islands (FLI) in drift region, which can suppress the electric field peak at bottom of gate trench during the blocking state and prevent premature breakdown in gate oxide, is proposed and investigated by TCAD simulations. The influence of thickness, position, doping concentration and length of the FLI on breakdown voltage (BV) and specific on-resistance (Ron_sp) is studied, providing useful guidelines for design of this new type of device. Using optimized parameters for the FLI, GaN FLI TG-MOSFET obtains a BV as high as 2464 V with a Ron_sp of 3.0 mΩ cm2. Compared to the conventional GaN TG-MOSFET with the same structure parameters, the Baliga figure of merit (BFOM) is enhanced by 150%, getting closer to theoretical limit for GaN devices.

Toward spin-based Magneto Logic Gate in Graphene

NASA Astrophysics Data System (ADS)

Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Zutic, Igor; Krivorotov, Ilya; Sham, Lu; Kawakami, Roland

Graphene has emerged as a leading candidate for spintronic applications due to its long spin diffusion length at room temperature. A universal magnetologic gate (MLG) based on spin transport in graphene has been recently proposed as the building block of a logic circuit which could replace the current CMOS technology. This MLG has five ferromagnetic electrodes contacting a graphene channel and can be considered as two three-terminal XOR logic gates. Here we demonstrate this XOR logic gate operation in such a device. This was achieved by systematically tuning the injection current bias to balance the spin polarization efficiency of the two inputs, and offset voltage in the detection circuit to obtain binary outputs. The output is a current which corresponds to different logic states: zero current is logic `0', and nonzero current is logic `1'. We find improved performance could be achieved by reducing device size and optimizing the contacts.

Indium gallium arsenide microwave power transistors

NASA Technical Reports Server (NTRS)

Johnson, Gregory A.; Kapoor, Vik J.; Shokrani, Mohsen; Messick, Louis J.; Nguyen, Richard

1991-01-01

Depletion-mode InGaAs microwave power MISFETs with 1-micron gate lengths and up to 1-mm gate widths have been fabricated using an ion-implantation process. The devices employed a plasma-deposited silicon/silicon dioxide gate insulator. The dc I-V characteristics and RF power performance at 9.7 GHz are presented. The output power, power-added efficiency, and power gain as a function of input power are reported. An output power of 1.07 W with a corresponding power gain and power-added efficiency of 4.3 dB and 38 percent, respectively, was obtained. The large-gate-width devices provided over twice the previously reported output power for InGaAs MISFETs at X-band. In addition, output power stability within 1.2 percent over 24 h of continuous operation was achieved. In addition, a drain current drift of 4 percent over 10,000 sec was obtained.

The voltage-sensing domain of a phosphatase gates the pore of a potassium channel.

PubMed

Arrigoni, Cristina; Schroeder, Indra; Romani, Giulia; Van Etten, James L; Thiel, Gerhard; Moroni, Anna

2013-03-01

The modular architecture of voltage-gated K(+) (Kv) channels suggests that they resulted from the fusion of a voltage-sensing domain (VSD) to a pore module. Here, we show that the VSD of Ciona intestinalis phosphatase (Ci-VSP) fused to the viral channel Kcv creates Kv(Synth1), a functional voltage-gated, outwardly rectifying K(+) channel. Kv(Synth1) displays the summed features of its individual components: pore properties of Kcv (selectivity and filter gating) and voltage dependence of Ci-VSP (V(1/2) = +56 mV; z of ~1), including the depolarization-induced mode shift. The degree of outward rectification of the channel is critically dependent on the length of the linker more than on its amino acid composition. This highlights a mechanistic role of the linker in transmitting the movement of the sensor to the pore and shows that electromechanical coupling can occur without coevolution of the two domains.

Surface characterization of carbon fiber reinforced polymers by picosecond laser induced breakdown spectroscopy

NASA Astrophysics Data System (ADS)

Ledesma, Rodolfo; Palmieri, Frank; Connell, John; Yost, William; Fitz-Gerald, James

2018-02-01

Adhesive bonding of composite materials requires reliable monitoring and detection of surface contaminants as part of a vigorous quality control process to assure robust and durable bonded structures. Surface treatment and effective monitoring prior to bonding are essential in order to obtain a surface which is free from contaminants that may lead to inferior bond quality. In this study, the focus is to advance the laser induced breakdown spectroscopy (LIBS) technique by using pulse energies below 100 μJ (μLIBS) for the detection of low levels of silicone contaminants in carbon fiber reinforced polymer (CFRP) composites. Various CFRP surface conditions were investigated by LIBS using ∼10 ps, 355 nm laser pulses with pulse energies below 30 μJ. Time-resolved analysis was conducted to optimize the gate delay and gate width for the detection of the C I emission line at 247.9 nm to monitor the epoxy resin matrix of CFRP composites and the Si I emission line at 288.2 nm for detection of silicone contaminants in CFRP. To study the surface sensitivity to silicone contamination, CFRP surfaces were coated with polydimethylsiloxane (PDMS), the active ingredient in many mold release agents. The presence of PDMS was studied by inspecting the Si I emission lines at 251.6 nm and 288.2 nm. The measured PDMS areal densities ranged from 0.15 to 2 μg/cm2. LIBS measurements were performed before and after laser surface ablation. The results demonstrate the successful detection of PDMS thin layers on CFRP using picosecond μLIBS.

Electrical overstress in AlGaN/GaN HEMTs: study of degradation processes

NASA Astrophysics Data System (ADS)

Kuzmík, J.; Pogany, D.; Gornik, E.; Javorka, P.; Kordoš, P.

2004-02-01

We study degradation mechanisms in 50 μm gate width/0.45 μm length AlGaN/GaN HEMTs after electrical overstresses. One hundred nanosecond long rectangular current pulses are applied on the drain contact keeping either both of the source and gate grounded or the source grounded and gate floating. Source-drain pulsed I- V characteristics show similar shape for both connections. After the HEMT undergoes the source-drain breakdown, a negative differential resistance region transits into a low voltage/high current region. Changes in the Schottky contact dc I- V characteristics and in the source and drain ohmic contacts are investigated as a function of the current stress level and are related to the HEMT dc performance. Catastrophic HEMT degradation was observed after Istress=1.65 A in case of the 'gate floating' connection due to ohmic contacts burnout. In case of the 'gate grounded' connection, Istress=0.45 A was sufficient for the gate failure showing a high gate susceptibility to overstress. Backside transient interferometric mapping technique experiment reveals a current filament formation under both HEMT stress connections. Infrared camera observations lead to conclusion that the filament formation together with a consequent high-density electron flow is responsible for a dark spot formation and gradual ohmic contact degradation.

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

NASA Astrophysics Data System (ADS)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

A quantum wave based compact modeling approach for the current in ultra-short DG MOSFETs suitable for rapid multi-scale simulations

NASA Astrophysics Data System (ADS)

Hosenfeld, Fabian; Horst, Fabian; Iñíguez, Benjamín; Lime, François; Kloes, Alexander

2017-11-01

Source-to-drain (SD) tunneling decreases the device performance in MOSFETs falling below the 10 nm channel length. Modeling quantum mechanical effects including SD tunneling has gained more importance specially for compact model developers. The non-equilibrium Green's function (NEGF) has become a state-of-the-art method for nano-scaled device simulation in the past years. In the sense of a multi-scale simulation approach it is necessary to bridge the gap between compact models with their fast and efficient calculation of the device current, and numerical device models which consider quantum effects of nano-scaled devices. In this work, an NEGF based analytical model for nano-scaled double-gate (DG) MOSFETs is introduced. The model consists of a closed-form potential solution of a classical compact model and a 1D NEGF formalism for calculating the device current, taking into account quantum mechanical effects. The potential calculation omits the iterative coupling and allows the straightforward current calculation. The model is based on a ballistic NEGF approach whereby backscattering effects are considered as second order effect in a closed-form. The accuracy and scalability of the non-iterative DG MOSFET model is inspected in comparison with numerical NanoMOS TCAD data for various channel lengths. With the help of this model investigations on short-channel and temperature effects are performed.

Non-equilibrium Green's functions study of discrete dopants variability on an ultra-scaled FinFET

DOE Office of Scientific and Technical Information (OSTI.GOV)

Valin, R., E-mail: r.valinferreiro@swansea.ac.uk; Martinez, A., E-mail: a.e.Martinez@swansea.ac.uk; Barker, J. R., E-mail: john.barker@glasgow.ac.uk

In this paper, we study the effect of random discrete dopants on the performance of a 6.6 nm channel length silicon FinFET. The discrete dopants have been distributed randomly in the source/drain region of the device. Due to the small dimensions of the FinFET, a quantum transport formalism based on the non-equilibrium Green's functions has been deployed. The transfer characteristics for several devices that differ in location and number of dopants have been calculated. Our results demonstrate that discrete dopants modify the effective channel length and the height of the source/drain barrier, consequently changing the channel control of the charge. Thismore » effect becomes more significant at high drain bias. As a consequence, there is a strong effect on the variability of the on-current, off-current, sub-threshold slope, and threshold voltage. Finally, we have also calculated the mean and standard deviation of these parameters to quantify their variability. The obtained results show that the variability at high drain bias is 1.75 larger than at low drain bias. However, the variability of the on-current, off-current, and sub-threshold slope remains independent of the drain bias. In addition, we have found that a large source to drain current by tunnelling current occurs at low gate bias.« less

Nanoprobe studies: Electrical transport in carbon nanotubes and crystal structure of aluminum nitride surfaces

NASA Astrophysics Data System (ADS)

Biswas, Sujit Kumar

Nanoprobes are an extraordinary set of experimental tools that allow fabrication, manipulation, and measurement in nano-scale systems. The primary use of a nanoprobe for imaging tiny objects is supplemented by powerful electrical techniques, namely scanning surface potential microscopy and current sensing atomic force microscopy. They allow us to measure potential, and current in carbon nanotube circuits. Nanoprobes are superior to conventional two- or four-probe measurements because they can provide spatial information of local electronic properties. This makes them highly attractive in studying junctions and contacts with carbon nanotubes. We have studied single-walled carbon nanotube circuits, forming junctions to other nanotubes. The experimental results indicate that these junctions act like potential barriers of about 50 meV that can confine electrons with an effective mass of 0.003 me , within nanotube channels of length 0.5 mum lying in-between two such potential barriers. This leads to quantization of the channel, forming a resonant tunneling structure. We have also found that single-walled nanotubes have phase coherence lengths of the order of 1 mum. This leads to situations where the electron interference effects at scattering centers need to be considered. We have seen direct evidence of this, in the non-linear resistance increase within nanotubes with few defects. Ambipolar transistor behavior was measured in a p-type single-walled nanotube circuit that showed electron injection across the Schottky junction at high positive bias. We have also studied multi-walled carbon nanotube circuits using scanning potential microscopy, and found that a back gate potential can vary the resistance of the channel. Vertical nanotube arrays, suitable for interconnects, were also measured. These hollow multi-walled nanotube channels were about 45 nm in diameter, and 50 mum in length, fabricated in an anodized alumina template. We found that these structures could sustain current densities greater than 105 A/cm2. Conventional use of nanoprobes in imaging aluminum nitride surfaces displayed curious step bunching structures. We have used an innovative analysis technique with which the bulk lattice constant of the crystal was measured to an accuracy of about 4% of X-ray crystallography value of 0.497 nm. In addition, this technique showed that there were regions on the surface that had a larger lattice parameter of 0.64 nm, which we interpreted to be due to a variation in the chemical composition of the surface such as oxide formation. We believe that this technique may prove useful as a study of chemical-composition variations on a surface as well as relaxation of the surface layer.

Advanced optical simulation of scintillation detectors in GATE V8.0: first implementation of a reflectance model based on measured data

NASA Astrophysics Data System (ADS)

Stockhoff, Mariele; Jan, Sebastien; Dubois, Albertine; Cherry, Simon R.; Roncali, Emilie

2017-06-01

Typical PET detectors are composed of a scintillator coupled to a photodetector that detects scintillation photons produced when high energy gamma photons interact with the crystal. A critical performance factor is the collection efficiency of these scintillation photons, which can be optimized through simulation. Accurate modelling of photon interactions with crystal surfaces is essential in optical simulations, but the existing UNIFIED model in GATE is often inaccurate, especially for rough surfaces. Previously a new approach for modelling surface reflections based on measured surfaces was validated using custom Monte Carlo code. In this work, the LUT Davis model is implemented and validated in GATE and GEANT4, and is made accessible for all users in the nuclear imaging research community. Look-up-tables (LUTs) from various crystal surfaces are calculated based on measured surfaces obtained by atomic force microscopy. The LUTs include photon reflection probabilities and directions depending on incidence angle. We provide LUTs for rough and polished surfaces with different reflectors and coupling media. Validation parameters include light output measured at different depths of interaction in the crystal and photon track lengths, as both parameters are strongly dependent on reflector characteristics and distinguish between models. Results from the GATE/GEANT4 beta version are compared to those from our custom code and experimental data, as well as the UNIFIED model. GATE simulations with the LUT Davis model show average variations in light output of  <2% from the custom code and excellent agreement for track lengths with R 2  >  0.99. Experimental data agree within 9% for relative light output. The new model also simplifies surface definition, as no complex input parameters are needed. The LUT Davis model makes optical simulations for nuclear imaging detectors much more precise, especially for studies with rough crystal surfaces. It will be available in GATE V8.0.

Crystalline ZrTiO{sub 4} gated p-metal–oxide–semiconductor field effect transistors with sub-nm equivalent oxide thickness featuring good electrical characteristics and reliability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Chao-Yi; Hsieh, Ching-Heng; Lee, Ching-Wei

2015-02-02

ZrTiO{sub 4} crystallized in orthorhombic (o-) phase was stacked with an amorphous Yb{sub 2}O{sub 3} interfacial layer as the gate dielectric for Si-based p-MOSFETs. With thermal annealing after gate electrode, the gate stack with equivalent oxide thickness (EOT) of 0.82 nm achieves high dielectric quality by showing a low interface trap density (D{sub it}) of 2.75 × 10{sup 11 }cm{sup −2}eV{sup −1} near the midgap and low oxide traps. Crystallization of ZrTiO{sub 4} and post metal annealing are also proven to introduce very limited amount of metal induced gap states or interfacial dipole. The p-MOSFETs exhibit good sub-threshold swing of 75 mV/dec which is ascribedmore » to the low D{sub it} value and small EOT. Owing to the Y{sub 2}O{sub 3} interfacial layer and smooth interface with Si substrate that, respectively, suppress phonon and surface roughness scattering, the p-MOSFETs also display high hole mobility of 49 cm{sup 2}/V-s at 1 MV/cm. In addition, I{sub on}/I{sub off} ratio larger than 10{sup 6} is also observed. From the reliability evaluation by negative bias temperature instability test, after stressing with an electric field of −10 MV/cm at 85 °C for 1000 s, satisfactory threshold voltage shift of 12 mV and sub-threshold swing degradation of 3% were obtained. With these promising characteristics, the Yb{sub 2}O{sub 3}/o-ZrTiO{sub 4} gate stack holds the great potential for next-generation electronics.« less

Heralded Quantum Gate between Remote Quantum Memories

DTIC Science & Technology

2009-06-25

emission fre- quency. Second, the geometrical modes from the two fibers are matched to better than 98% as characterized with laser light. Third, the...remains in the trap for several weeks. Doppler-cooling by laser light slightly red detuned from the 2S1=2 $ 2P1=2 transition at 369.5 nm localizes the ions...state decays to the metastable 2D3=2 level. This level is depopulated with a laser near 935.2 nm to maintain efficient cooling and state detection. We

A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience

NASA Astrophysics Data System (ADS)

Li, Y.-Q.; Wang, H.-B.; Liu, R.; Chen, L.; Nofal, I.; Shi, S.-T.; He, A.-L.; Guo, G.; Baeg, S. H.; Wen, S.-J.; Wong, R.; Chen, M.; Wu, Q.

2017-06-01

A flip-flop circuit hardened against soft errors is presented in this paper. This design is an improved version of Quatro for further enhanced soft-error resilience by integrating the guard-gate technique. The proposed design, as well as reference Quatro and regular flip-flops, was implemented and manufactured in a 65-nm CMOS bulk technology. Experimental characterization results of their alpha and heavy ions soft-error rates verified the superior hardening performance of the proposed design over the other two circuits.

Comparison of excitation wavelengths for in vivo deep imaging of mouse brain

NASA Astrophysics Data System (ADS)

Wang, Mengran; Wu, Chunyan; Li, Bo; Xia, Fei; Sinefeld, David; Xu, Chris

2018-02-01

The attenuation of excitation power reaching the focus is the main issue that limits the depth penetration of highresolution imaging of biological tissue. The attenuation is caused by a combination of tissue scattering and absorption. Theoretical model of the effective attenuation length for in vivo mouse brain imaging has been built based on the data of the absorption of water and blood and the Mie scattering of a tissue-like phantom. Such a theoretical model has been corroborated at a number of excitation wavelengths, such as 800 nm, 1300 nm , and 1700 nm ; however, the attenuation caused by absorption is negligible when compared to tissue scattering at all these wavelength windows. Here we performed in vivo three-photon imaging of Texas Red-stained vasculature in the same mouse brain with different excitation wavelengths, 1700 nm, 1550 nm, 1500 nm and 1450 nm. In particular, our studies include the wavelength regime where strong water absorption is present (i.e., 1450 nm), and the attenuation by water absorption is predicted to be the dominant contribution in the excitation attenuation. Based on the experimental results, we found that the effective attenuation length at 1450 nm is significantly shorter than those at 1700 nm and 1300 nm. Our results confirm that the theoretical model based on tissue scattering and water absorption is accurate in predicting the effective attenuation lengths for in vivo imaging. The optimum excitation wavelength windows for in vivo mouse brain imaging are at 1300 nm and 1700 nm.

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

NASA Astrophysics Data System (ADS)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

Design and implementation of low power clock gated 64-bit ALU on ultra scale FPGA

NASA Astrophysics Data System (ADS)

Gupta, Ashutosh; Murgai, Shruti; Gulati, Anmol; Kumar, Pradeep

2016-03-01

64-bit energy efficient Arithmetic and Logic Unit using negative latch based clock gating technique is designed in this paper. The 64-bit ALU is designed using multiplexer based full adder cell. We have designed a 64-bit ALU with a gated clock. We have used negative latch based circuit for generating gated clock. This gated clock is used to control the multiplexer based 64-bit ALU. The circuit has been synthesized on kintex FPGA through Xilinx ISE Design Suite 14.7 using 28 nm technology in Verilog HDL. The circuit has been simulated on Modelsim 10.3c. The design is verified using System Verilog on QuestaSim in UVM environment. We have achieved 74.07%, 92. 93% and 95.53% reduction in total clock power, 89.73%, 91.35% and 92.85% reduction in I/Os power, 67.14%, 62.84% and 74.34% reduction in dynamic power and 25.47%, 29.05% and 46.13% reduction in total supply power at 20 MHz, 200 MHz and 2 GHz frequency respectively. The power has been calculated using XPower Analyzer tool of Xilinx ISE Design Suite 14.3.

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deen, David A., E-mail: david.deen@alumni.nd.edu; Storm, David F.; Scott Katzer, D.

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain currentmore » after bias stressed in subthreshold. These structures additionally achieved small signal metrics f{sub t}/f{sub max} of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with f{sub t}/f{sub max} of 48/60 GHz.« less

The gating mechanism of the large mechanosensitive channel MscL

NASA Technical Reports Server (NTRS)

Sukharev, S.; Betanzos, M.; Chiang, C. S.; Guy, H. R.

2001-01-01

The mechanosensitive channel of large conductance, MscL, is a ubiquitous membrane-embedded valve involved in turgor regulation in bacteria. The crystal structure of MscL from Mycobacterium tuberculosis provides a starting point for analysing molecular mechanisms of tension-dependent channel gating. Here we develop structural models in which a cytoplasmic gate is formed by a bundle of five amino-terminal helices (S1), previously unresolved in the crystal structure. When membrane tension is applied, the transmembrane barrel expands and pulls the gate apart through the S1-M1 linker. We tested these models by substituting cysteines for residues predicted to be near each other only in either the closed or open conformation. Our results demonstrate that S1 segments form the bundle when the channel is closed, and crosslinking between S1 segments prevents opening. S1 segments interact with M2 when the channel is open, and crosslinking of S1 to M2 impedes channel closing. Gating is affected by the length of the S1-M1 linker in a manner consistent with the model, revealing critical spatial relationships between the domains that transmit force from the lipid bilayer to the channel gate.

Comparative analysis of full-gate and short-gate dielectric modulated electrically doped Tunnel-FET based biosensors

NASA Astrophysics Data System (ADS)

Sharma, Dheeraj; Singh, Deepika; Pandey, Sunil; Yadav, Shivendra; Kondekar, P. N.

2017-11-01

In this work, we have done a comprehensive study between full-gate and short-gate dielectrically modulated (DM) electrically doped tunnel field-effect transistor (SGDM-EDTFET) based biosensors of equivalent dimensions. However, in both the structures, dielectric constant and charge density are considered as a sensing parameter for sensing the charged and non-charged biomolecules in the given solution. In SGDM-EDTFET architecture, the reduction in gate length results a significant improvement in the tunneling current due to occurrence of strong coupling between gate and channel region which ensures higher drain current sensitivity for detection of the biomolecules. Moreover, the sensitivity of dual metal SGDM-EDTFET is compared with the single metal SGDM-EDTFET to analyze the better sensing capability of both the devices for the biosensor application. Further, the effect of sensing parameter i.e., ON-current (ION), and ION/IOFF ratio is analysed for dual metal SGDM-EDTFET in comparison with dual metal SGDM-EDFET. From the comparison, it is found that dual metal SGDM-EDTFET based biosensor attains relatively better sensitivity and can be utilized as a suitable candidate for biosensing applications.

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11,000 cm(2)/V·s.

PubMed

Smith, Casey; Qaisi, Ramy; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

2013-07-23

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11,000 cm(2)/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low tox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance.

Looking for Speed!! Go Optical Ultra-Fast Photonic Logic Gates for the Future Optical Communication and Computing

NASA Technical Reports Server (NTRS)

Abdeldayem, Hossin; Frazier, Donald O.; Penn, Benjamin; Paley, Mark S.

2003-01-01

Recently, we developed two ultra-fast all-optical switches in the nanosecond and picosecond regimes. The picosecond switch is made of a polydiacetylene thin film coated on the interior wall of a hollow capillary of approximately 50 micron diameter by a photo-polymerization process. In the setup a picosecond Nd:YAG laser at 10 Hz and at 532 nm with a pulse duration of approximately 40 ps was sent collinearly along a cw He-Ne laser beam and both were waveguided through the hollow capillary. The setup functioned as an Exclusive OR gate. On the other hand, the material used in the nanosecond switch is a phthalocyanine thin film, deposited on a glass substrate by a vapor deposition technique. In the setup a nanosecond, 10 Hz, Nd:YAG laser of 8 ns pulse duration was sent collinearly along a cw He-Ne laser beam and both were wave-guided through the phthalocyanine thin film. The setup in this case functioned as an all-optical AND logic gate. The characteristic table of the ExOR gate in polydiacetylene film was attributed to an excited state absorption process, while that of the AND gate was attributed to a saturation process of the first excited state. Both mechanisms were thoroughly investigated theoretically and found to agree remarkably well with the experimental results. An all-optical inverter gate has been designed but has not yet been demonstrated. The combination of all these three gates form the foundation for building all the necessary gates needed to build a prototype of an all-optical system.

Charge transfer efficiency improvement of 4T pixel for high speed CMOS image sensor

NASA Astrophysics Data System (ADS)

Jin, Xiangliang; Liu, Weihui; Yang, Hongjiao; Tang, Lizhen; Yang, Jia

2015-03-01

The charge transfer efficiency improvement method is proposed by optimizing the electrical potential distribution along the transfer path from the PPD to the FD. In this work, we present a non-uniform doped transfer transistor channel, with the adjustments to the overlap length between the CPIA layer and the transfer gate, and the overlap length between the SEN layer and transfer gate. Theory analysis and TCAD simulation results show that the density of the residual charge reduces from 1e11 /cm3 to 1e9 /cm3, and the transfer time reduces from 500 ns to 143 ns, and the charge transfer efficiency is about 77 e-/ns. This optimizing design effectively improves the charge transfer efficiency of 4T pixel and the performance of 4T high speed CMOS image sensor.

Suspended sub-50 nm vanadium dioxide membrane transistors: fabrication and ionic liquid gating studies

NASA Astrophysics Data System (ADS)

Sim, Jai S.; Zhou, You; Ramanathan, Shriram

2012-10-01

We demonstrate a robust lithographic patterning method to fabricate self-supported sub-50 nm VO2 membranes that undergo a phase transition. Utilizing such self-supported membranes, we directly observed a shift in the metal-insulator transition temperature arising from stress relaxation and consistent opening of the hysteresis. Electric double layer transistors were then fabricated with the membranes and compared to thin film devices. The ionic liquid allowed reversible modulation of channel resistance and distinguishing bulk processes from the surface effects. From the shift in the metal-insulator transition temperature, the carrier density doped through electrolyte gating is estimated to be 1 × 1020 cm-3. Hydrogen annealing studies showed little difference in resistivity between the film and the membrane indicating rapid diffusion of hydrogen in the vanadium oxide rutile lattice consistent with previous observations. The ability to fabricate electrically-wired, suspended VO2 ultra-thin membranes creates new opportunities to study mesoscopic size effects on phase transitions and may also be of interest in sensor devices.

Numerical analysis of the reverse blocking enhancement in High-K passivation AlGaN/GaN Schottky barrier diodes with gated edge termination

NASA Astrophysics Data System (ADS)

Bai, Zhiyuan; Du, Jiangfeng; Xin, Qi; Li, Ruonan; Yu, Qi

2018-02-01

We conducted a numerical analysis on high-K dielectric passivated AlGaN/GaN Schottky barrier diodes (HPG-SBDs) with a gated edge termination (GET). The reverse blocking characteristics were significantly enhanced without the stimulation of any parasitic effect by varying the dielectric thickness dge under the GET, thickness TP, and dielectric constant εr of the high-K passivation layer. The leakage current was reduced by increasing εr and decreasing dge. The breakdown voltage of the device was enhanced by increasing εr and TP. The highest breakdown voltage of 970 V and the lowest leakage current of 0.5 nA/mm were achieved under the conditions of εr = 80, TP = 800 nm, and dge = 10 nm. C-V simulation revealed that the HPG-SBDs induced no parasitic capacitance by comparing the integrated charges of the devices with different high-K dielectrics and different dge.

Electrical in-situ characterisation of interface stabilised organic thin-film transistors

PubMed Central

Striedinger, Bernd; Fian, Alexander; Petritz, Andreas; Lassnig, Roman; Winkler, Adolf; Stadlober, Barbara

2015-01-01

We report on the electrical in-situ characterisation of organic thin film transistors under high vacuum conditions. Model devices in a bottom-gate/bottom-contact (coplanar) configuration are electrically characterised in-situ, monolayer by monolayer (ML), while the organic semiconductor (OSC) is evaporated by organic molecular beam epitaxy (OMBE). Thermal SiO2 with an optional polymer interface stabilisation layer serves as the gate dielectric and pentacene is chosen as the organic semiconductor. The evolution of transistor parameters is studied on a bi-layer dielectric of a 150 nm of SiO2 and 20 nm of poly((±)endo,exo-bicyclo[2.2.1]hept-5-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) and compared to the behaviour on a pure SiO2 dielectric. The thin layer of PNDPE, which is an intrinsically photo-patternable organic dielectric, shows an excellent stabilisation performance, significantly reducing the calculated interface trap density at the OSC/dielectric interface up to two orders of magnitude, and thus remarkably improving the transistor performance. PMID:26457122

Design and implementation of power efficient 10-bit dual port SRAM on 28 nm technology

NASA Astrophysics Data System (ADS)

Gulati, Anmol; Gupta, Ashutosh; Murgai, Shruti; Bhaskar, Lala

2016-03-01

In this paper, 10 bit synchronous clock gated Dual port RAM has been designed. The negative latch based clock gating technique has been employed to optimize the power of the design. The design has been implemented on XV7K70T device, -3 speed grade, and kintex 7 FPGA family on Xilinx ISE Design Suite 14.7 using 28 nm technology. The design has been synthesized using Verilog HDL. We have been successful in achieving approximately 55 % reduction in total clock power, 81.55% reduction in BRAM power, 82.65%, 0.07%, 1.04% and 11.31% reduction in static power, 72.32%, 38.60%, 68.74% and 71.97%, reduction in dynamic power and 72.44%, 16.96%, 60.88% and 71.06% reduction in total supply power at 1 THz, 1GHz, 100 GHz and 1000 GHz frequency respectively. The power of the device has been calculated using XPower Analyzer tool of Xilinx ISE Design Suite 14.7.

Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Greene, Brian Joseph

Thin film silicon on insulator fabrication is an increasingly important technology requirement for improving performance in future generation devices and circuits. One process for SOI fabrication that has recently been generating renewed interest is Lateral Solid Phase Epitaxy (LSPE) of silicon over oxide. This process involves annealing amorphous silicon that has been deposited on oxide patterned Si wafers. The (001) Si substrate forms the crystalline seed for epitaxial growth, permitting the generation of Si films that are both single crystal, and oriented to the substrate. This method is particularly attractive to fabrication that requires low temperature processing, because the Si films are deposited in the amorphous phase at temperatures near 525°C, and crystallized at temperatures near 570°C. It is also attractive for applications requiring three dimensional stacking of active silicon device layers, due to the relatively low temperatures involved. For sub-50 nm gate length MOSFET fabrication, an SOI thickness on the order of 10 nm will be required. One limitation of the LSPE process has been the need for thick films (0.5--2 mum) and/or heavy P doping (10 19--1020 cm-3) to increase the maximum achievable lateral growth distance, and therefore minimize the area on the substrate occupied by seed holes. This dissertation discusses the characterization and optimization of process conditions for large area LSPE silicon film growth, as well as efforts to adapt the traditional LSPE process to achieve ultra-thin SOI layers (Tsilicon ≤ 25 nm) while avoiding the use of heavy active doping layers. MOSFETs fabricated in these films that exhibit electron mobility comparable to the Universal Si MOS Mobility are described.

Entangled spin chain

NASA Astrophysics Data System (ADS)

Salberger, Olof; Korepin, Vladimir

We introduce a new model of interacting spin 1/2. It describes interactions of three nearest neighbors. The Hamiltonian can be expressed in terms of Fredkin gates. The Fredkin gate (also known as the controlled swap gate) is a computational circuit suitable for reversible computing. Our construction generalizes the model presented by Peter Shor and Ramis Movassagh to half-integer spins. Our model can be solved by means of Catalan combinatorics in the form of random walks on the upper half plane of a square lattice (Dyck walks). Each Dyck path can be mapped on a wave function of spins. The ground state is an equally weighted superposition of Dyck walks (instead of Motzkin walks). We can also express it as a matrix product state. We further construct a model of interacting spins 3/2 and greater half-integer spins. The models with higher spins require coloring of Dyck walks. We construct a SU(k) symmetric model (where k is the number of colors). The leading term of the entanglement entropy is then proportional to the square root of the length of the lattice (like in the Shor-Movassagh model). The gap closes as a high power of the length of the lattice [5, 11].