Gate length scaling optimization of FinFETs

NASA Astrophysics Data System (ADS)

Chen, Shoumian; Shang, Enming; Hu, Shaojian

2018-06-01

This paper introduces a device performance optimization approach for the FinFET through optimization of the gate length. As a result of reducing the gate length, the leakage current (Ioff) increases, and consequently, the stress along the channel enhances which leads to an increase in the drive current (Isat) of the PMOS. In order to sustain Ioff, work function is adjusted to offset the effect of the increased stress. Changing the gate length of the transistor yields different drive currents when the leakage current is fixed by adjusting the work function. For a given device, an optimal gate length is found to provide the highest drive current. As an example, for a standard performance device with Ioff = 1 nA/um, the best performance Isat = 856 uA/um is at L = 34 nm for 14 nm FinFET and Isat = 1130 uA/um at L = 21 nm for 7 nm FinFET. A 7 nm FinFET will exhibit performance boost of 32% comparing with 14 nm FinFET. However, applying the same method to a 5 nm FinFET, the performance boosting is out of expectance comparing to the 7 nm FinFET, which is due to the severe short-channel-effect and the exhausted channel stress in the FinFET.

Nanofabrication of 10-nm T-shaped gates using a double patterning process with electron beam lithography and dry etch

NASA Astrophysics Data System (ADS)

Shao, Jinhai; Deng, Jianan; Lu, W.; Chen, Yifang

2017-07-01

A process to fabricate T-shaped gates with the footprint scaling down to 10 nm using a double patterning procedure is reported. One of the keys in this process is to separate the definition of the footprint from that for the gate-head so that the proximity effect originated from electron forward scattering in the resist is significantly minimized, enabling us to achieve as narrow as 10-nm foot width. Furthermore, in contrast to the reported technique for 10-nm T-shaped profile in resist, this process utilizes a metallic film with a nanoslit as an etch mask to form a well-defined 10-nm-wide foot in a SiNx layer by reactive ion etch. Such a double patterning process has demonstrated enhanced reliability. The detailed process is comprehensively described, and its advantages and limitations are discussed. Nanofabrication of InP-based high-electron-mobility transistors using the developed process for 10- to 20-nm T-shaped gates is currently under the way.

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Mizubayashi, Wataru; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Masahara, Meishoku

2014-01-01

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (Vt) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal-oxide-nitride-oxide-silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial Vt roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (Lg) is scaled down to 46 nm or less.

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

NASA Astrophysics Data System (ADS)

Okamoto, Shin-ichi; Maekawa, Kei-ichi; Kawashima, Yoshiyuki; Shiba, Kazutoshi; Sugiyama, Hideki; Inoue, Masao; Nishida, Akio

2015-04-01

High quality static random access memory (SRAM) for 40-nm embedded MONOS flash memory with split gate (SG-MONOS) was developed. Marginal failure, which results in threshold voltage/drain current tailing and outliers of SRAM transistors, occurs when using a conventional SRAM structure. These phenomena can be explained by not only gate depletion but also partial depletion and percolation path formation in the MOS channel. A stacked poly-Si gate structure can suppress these phenomena and achieve high quality SRAM without any defects in the 6σ level and with high affinity to the 40-nm SG-MONOS process was developed.

Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

NASA Astrophysics Data System (ADS)

Chinnappan, U.; Sanudin, R.

2017-08-01

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.

Kerr-gated picosecond Raman spectroscopy and Raman photon migration of equine bone tissue with 400-nm excitation

NASA Astrophysics Data System (ADS)

Morris, Michael D.; Goodship, Allen E.; Draper, Edward R. C.; Matousek, Pavel; Towrie, Michael; Parker, Anthony W.

2004-07-01

We show that Raman spectroscopy with visible lasers, even in the deep blue is possible with time-gated Raman spectroscopy. A 4 picosec time gate allows efficient fluorescence rejection, up to 1000X, and provides almost background-free Raman spectra with low incident laser power. The technology enables spectroscopy with better than 10X higher scattering efficiency than is possible with the NIR (785 nm and 830 nm) lasers that are conventionally used. Raman photon migration is shown to allow depth penetration. We show for the first time that Kerr-gated Raman spectra of bone tissue with blue laser excitation enables both fluorescence rejection and depth penetration.

Multi-Subband Ensemble Monte Carlo simulations of scaled GAA MOSFETs

NASA Astrophysics Data System (ADS)

Donetti, L.; Sampedro, C.; Ruiz, F. G.; Godoy, A.; Gamiz, F.

2018-05-01

We developed a Multi-Subband Ensemble Monte Carlo simulator for non-planar devices, taking into account two-dimensional quantum confinement. It couples self-consistently the solution of the 3D Poisson equation, the 2D Schrödinger equation, and the 1D Boltzmann transport equation with the Ensemble Monte Carlo method. This simulator was employed to study MOS devices based on ultra-scaled Gate-All-Around Si nanowires with diameters in the range from 4 nm to 8 nm with gate length from 8 nm to 14 nm. We studied the output and transfer characteristics, interpreting the behavior in the sub-threshold region and in the ON state in terms of the spatial charge distribution and the mobility computed with the same simulator. We analyzed the results, highlighting the contribution of different valleys and subbands and the effect of the gate bias on the energy and velocity profiles. Finally the scaling behavior was studied, showing that only the devices with D = 4nm maintain a good control of the short channel effects down to the gate length of 8nm .

Analysis of electrical characteristics and proposal of design guide for ultra-scaled nanoplate vertical FET and 6T-SRAM

NASA Astrophysics Data System (ADS)

Seo, Youngsoo; Kim, Shinkeun; Ko, Kyul; Woo, Changbeom; Kim, Minsoo; Lee, Jangkyu; Kang, Myounggon; Shin, Hyungcheol

2018-02-01

In this paper, electrical characteristics of gate-all-around (GAA) nanoplate (NP) vertical FET (VFET) were analyzed for single transistor and 6T-SRAM cell through 3D technology computer-aided design (TCAD) simulation. In VFET, gate and extension lengths are not limited by the area of device because theses lengths are vertically located. The height of NP is assumed in 40 nm considering device fabrication method (top-down approach). According to the sizes of devices, we analyzed the performances of device such as total resistance, capacitance, intrinsic gate delay, sub-threshold swing (S.S), drain-induced barrier lowering (DIBL) and static noise margin (SNM). As the gate length becomes larger, the resistance should be smaller because the total height of NP is fixed in 40 nm. Also, when the channel thickness becomes thicker, the total resistance becomes smaller since the sheet resistances of channel and extension become smaller and the contact resistance becomes smaller due to the increasing contact area. In addition, as the length of channel pitch increases, the parasitic capacitance comes to be larger due to the increasing area of gate-drain and gate-source. The performance of RC delay is best in the shortest gate length (12 nm), the thickest channel (6 nm) and the shortest channel pitch (17 nm) owing to the reduced resistance and parasitic capacitance. However, the other performances such as DIBL, S.S, on/off ratio and SNM are worst because the short channel effect is highest in this situation. Also, we investigated the performance of the multi-channel device. As the number of channels increases, the performance of device and the reliability of SRAM improve because of reduced contact resistance, increased gate dimension and multi-channel compensation effect.

Sub-THz Imaging Using Non-Resonant HEMT Detectors.

PubMed

Delgado-Notario, Juan A; Velazquez-Perez, Jesus E; Meziani, Yahya M; Fobelets, Kristel

2018-02-10

Plasma waves in gated 2-D systems can be used to efficiently detect THz electromagnetic radiation. Solid-state plasma wave-based sensors can be used as detectors in THz imaging systems. An experimental study of the sub-THz response of II-gate strained-Si Schottky-gated MODFETs (Modulation-doped Field-Effect Transistor) was performed. The response of the strained-Si MODFET has been characterized at two frequencies: 150 and 300 GHz: The DC drain-to-source voltage transducing the THz radiation (photovoltaic mode) of 250-nm gate length transistors exhibited a non-resonant response that agrees with theoretical models and physics-based simulations of the electrical response of the transistor. When imposing a weak source-to-drain current of 5 μA, a substantial increase of the photoresponse was found. This increase is translated into an enhancement of the responsivity by one order of magnitude as compared to the photovoltaic mode, while the NEP (Noise Equivalent Power) is reduced in the subthreshold region. Strained-Si MODFETs demonstrated an excellent performance as detectors in THz imaging.

Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET.

PubMed

Dutta, Sangya; Kumar, Vinay; Shukla, Aditya; Mohapatra, Nihar R; Ganguly, Udayan

2017-08-15

Neuro-biology inspired Spiking Neural Network (SNN) enables efficient learning and recognition tasks. To achieve a large scale network akin to biology, a power and area efficient electronic neuron is essential. Earlier, we had demonstrated an LIF neuron by a novel 4-terminal impact ionization based n+/p/n+ with an extended gate (gated-INPN) device by physics simulation. Excellent improvement in area and power compared to conventional analog circuit implementations was observed. In this paper, we propose and experimentally demonstrate a compact conventional 3-terminal partially depleted (PD) SOI- MOSFET (100 nm gate length) to replace the 4-terminal gated-INPN device. Impact ionization (II) induced floating body effect in SOI-MOSFET is used to capture LIF neuron behavior to demonstrate spiking frequency dependence on input. MHz operation enables attractive hardware acceleration compared to biology. Overall, conventional PD-SOI-CMOS technology enables very-large-scale-integration (VLSI) which is essential for biology scale (~10 11 neuron based) large neural networks.

Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

NASA Astrophysics Data System (ADS)

Guerfi, Youssouf; Larrieu, Guilhem

2016-04-01

Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.

Power efficient, clock gated multiplexer based full adder cell using 28 nm technology

NASA Astrophysics Data System (ADS)

Gupta, Ashutosh; Murgai, Shruti; Gulati, Anmol; Kumar, Pradeep

2016-03-01

Clock gating is a leading technique used for power saving. Full adders is one of the basic circuit that can be found in maximum VLSI circuits. In this paper clock gated multiplexer based full adder cell is implemented on 28 nm technology. We have designed a full adder cell using a multiplexer with a gated clock without degrading its performance of the cell. We have negative latch circuit for generating gated clock. This gated clock is used to control the multiplexer based full adder cell. The circuit has been synthesized on kintex FPGA through Xilinx ISE Design Suite 14.7 using 28 nm technology in Verilog HDL. The circuit has been simulated on Modelsim 10.3c. The design is verified using System Verilog on QuestaSim in UVM environment. The total power of the circuit has been reduced by 7.41% without degrading the performance of original circuit. The power has been calculated using XPower Analyzer tool of XILINX ISE DESIGN SUITE 14.3.

Polysilicon Gate Enhancement of the Random Dopant Induced Threshold Voltage Fluctuations in Sub-100 nm MOSFET's with Ultrathin Gate Oxide

NASA Technical Reports Server (NTRS)

Asenov, Asen; Saini, Subhash

2000-01-01

In this paper, we investigate various aspects of the polysilicon gate influence on the random dopant induced threshold voltage fluctuations in sub-100 nm MOSFET's with ultrathin gate oxides. The study is done by using an efficient statistical three-dimensional (3-D) "atomistic" simulation technique described else-where. MOSFET's with uniform channel doping and with low doped epitaxial channels have been investigated. The simulations reveal that even in devices with a single crystal gate the gate depletion and the random dopants in it are responsible for a substantial fraction of the threshold voltage fluctuations when the gate oxide is scaled-in the range of 1-2 nm. Simulation experiments have been used in order to separate the enhancement in the threshold voltage fluctuations due to an effective increase in the oxide thickness associated with the gate depletion from the direct influence of the random dopants in the gate depletion layer. The results of the experiments show that the both factors contribute to the enhancement of the threshold voltage fluctuations, but the effective increase in the oxide-thickness has a dominant effect in the investigated range of devices. Simulations illustrating the effect or the polysilicon grain boundaries on the threshold voltage variation are also presented.

2D Quantum Transport Modeling in Nanoscale MOSFETs

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, Bryan

2001-01-01

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density- gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions, oxide tunneling and phase-breaking scattering are treated on equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. Quantum simulations are focused on MIT 25, 50 and 90 nm "well- tempered" MOSFETs and compared to classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. These results are quantitatively consistent with I D Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and sub-threshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

Acousto-optic modulation and opto-acoustic gating in piezo-optomechanical circuits

PubMed Central

Balram, Krishna C.; Davanço, Marcelo I.; Ilic, B. Robert; Kyhm, Ji-Hoon; Song, Jin Dong; Srinivasan, Kartik

2017-01-01

Acoustic wave devices provide a promising chip-scale platform for efficiently coupling radio frequency (RF) and optical fields. Here, we use an integrated piezo-optomechanical circuit platform that exploits both the piezoelectric and photoelastic coupling mechanisms to link 2.4 GHz RF waves to 194 THz (1550 nm) optical waves, through coupling to propagating and localized 2.4 GHz acoustic waves. We demonstrate acousto-optic modulation, resonant in both the optical and mechanical domains, in which waveforms encoded on the RF carrier are mapped to the optical field. We also show opto-acoustic gating, in which the application of modulated optical pulses interferometrically gates the transmission of propagating acoustic pulses. The time-domain characteristics of this system under both pulsed RF and pulsed optical excitation are considered in the context of the different physical pathways involved in driving the acoustic waves, and modelled through the coupled mode equations of cavity optomechanics. PMID:28580373

High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2017-03-01

In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (˜17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (˜87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH-1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

NASA Astrophysics Data System (ADS)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

Resonant tunneling of 1-dimensional electrons across an array of 3-dimensionally confined potential wells

NASA Astrophysics Data System (ADS)

Allee, D. R.; Chou, S. Y.; Harris, J. S.; Pease, R. F. W.

A lateral resonant tunneling field effect transistor has been fabricated with a gate electrode in the form of a railway such that the two rails form a lateral double barrier potential at the GaAs/AlGaAs interface. The ties confine the electrons in the third dimension forming an array of potential boxes or three dimensionally confined potential wells. The width of the ties and rails is 50nm; the spacings between the ties and between the two rails are 230nm and 150nm respectively. The ties are 750nm long and extend beyond the the two rails forming one dimensional wires on either side. Conductance oscillations are observed in the drain current at 4.2K as the gate voltage is scanned. Comparison with devices with a solid gate, and with a monorail gate with ties fabricated on the same wafer suggest that these conductance oscillations are electron resonant tunneling from one dimensional wires through the quasi-bound states of the three dimensionally confined potential wells. Comparison with a device with a two rail gate without ties (previously published) indicates that additional confinement due to the ties enhances the strength of the conductance oscillations.

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

2D Quantum Mechanical Study of Nanoscale MOSFETs

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, B.; Kwak, Dochan (Technical Monitor)

2000-01-01

With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density-gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions and oxide tunneling are treated on an equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. We present the results of our simulations of MIT 25, 50 and 90 nm "well-tempered" MOSFETs and compare them to those of classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. Surprisingly, the self-consistent potential profile shows lower injection barrier in the channel in quantum case. These results are qualitatively consistent with ID Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and subthreshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.

On gate stack scalability of double-gate negative-capacitance FET with ferroelectric HfO2 for energy efficient sub-0.2 V operation

NASA Astrophysics Data System (ADS)

Jang, Kyungmin; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2018-02-01

We have investigated the gate stack scalability and energy efficiency of double-gate negative-capacitance FET (DGNCFET) with a CMOS-compatible ferroelectric HfO2 (FE:HfO2). Analytic model-based simulation is conducted to investigate the impacts of ferroelectric characteristic of FE:HfO2 and gate stack thickness on the I on/I off ratio of DGNCFET. DGNCFET has wider design window for the gate stack where higher I on/I off ratio can be achieved than DG classical MOSFET. Under a process-induced constraint with sub-10 nm gate length (L g), FE:HfO2-based DGNCFET still has a design point for high I on/I off ratio. With an optimized gate stack thickness for sub-10 nm L g, FE:HfO2-based DGNCFET has 2.5× higher energy efficiency than DG classical MOSFET even at ultralow operation voltage of sub-0.2 V.

Sub-THz Imaging Using Non-Resonant HEMT Detectors

PubMed Central

Delgado-Notario, Juan A.; Meziani, Yahya M.; Fobelets, Kristel

2018-01-01

Plasma waves in gated 2-D systems can be used to efficiently detect THz electromagnetic radiation. Solid-state plasma wave-based sensors can be used as detectors in THz imaging systems. An experimental study of the sub-THz response of II-gate strained-Si Schottky-gated MODFETs (Modulation-doped Field-Effect Transistor) was performed. The response of the strained-Si MODFET has been characterized at two frequencies: 150 and 300 GHz: The DC drain-to-source voltage transducing the THz radiation (photovoltaic mode) of 250-nm gate length transistors exhibited a non-resonant response that agrees with theoretical models and physics-based simulations of the electrical response of the transistor. When imposing a weak source-to-drain current of 5 μA, a substantial increase of the photoresponse was found. This increase is translated into an enhancement of the responsivity by one order of magnitude as compared to the photovoltaic mode, while the NEP (Noise Equivalent Power) is reduced in the subthreshold region. Strained-Si MODFETs demonstrated an excellent performance as detectors in THz imaging. PMID:29439437

Molecule counting with alkanethiol and DNA immobilized on gold microplates for extended gate FET.

PubMed

Cao, Zhong; Xiao, Zhong-Liang; Zhang, Ling; Luo, Dong-Mei; Kamahori, Masao; Shimoda, Maki

2013-04-01

Several molecule counting methods based on electrochemical characterization of alkanethiol and thiolated single-stranded oligonucleotide (HS-ssDNA) immobilized on gold microplates, which were used as extended gates of field effect transistors (FETs), have been investigated in this paper. The surface density of alkanethiol and DNA monolayers on gold microplates were quantitatively evaluated from the reductive desorption charge by using cyclic voltammetry (CV) and fast CV (FCV) methods in strong alkali solution. Typically, the surface density of 6-hydroxy-1-hexanethiol (6-HHT) was evaluated to be 4.639 molecules/nm(2), and the 28 base-pair dsDNA about 1.226-4.849 molecules/100 nm(2) on Au microplates after post-treatment with 6-HHT. The behaviors on surface potential and capacitance of different aminoalkanethiols on Au microplates were measured in 0.1 mol/L Na2SO4 and 10 mmol/L Tris-HCl (pH=7.4) solutions, indicating that the surface potential increases and the double-layer capacitance decreases with the length of carbon chain increased for the thiol monolayers, which obey a physics relationship for a capacitor. Comparably, a simple sensing method based on the electronic signals of biochemical reaction events on DNA immobilization and hybridization at the Au surface of the extended gate FET (EGFET) was developed, with which the surface density of the hybridized dsDNA on the gold surface of the EGFET was evaluated to be 1.36 molecules per 100 nm(2), showing that the EGFET is a promising sensing biochip for DNA molecule counting. Copyright © 2012 Elsevier B.V. All rights reserved.

MOCVD of HfO2 and ZrO2 high-k gate dielectrics for InAlN/AlN/GaN MOS-HEMTs

NASA Astrophysics Data System (ADS)

Abermann, S.; Pozzovivo, G.; Kuzmik, J.; Strasser, G.; Pogany, D.; Carlin, J.-F.; Grandjean, N.; Bertagnolli, E.

2007-12-01

We apply metal organic chemical vapour deposition (MOCVD) of HfO2 and of ZrO2 from β-diketonate precursors to grow high-k gate dielectrics for InAlN/AlN/GaN metal oxide semiconductor (MOS)-high electron mobility transistors (HEMTs). High-k oxides of about 12 nm-14 nm are deposited for the MOS-HEMTs incorporating Ni/Au gates, whereas as a reference, Ni-contact-based 'conventional' Schottky-barrier (SB)-HEMTs are processed. The processed dielectrics decrease the gate current leakage of the HEMTs by about four orders of magnitude if compared with the SB-gated HEMTs and show superior device characteristics in terms of IDS and breakdown.

Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology

NASA Astrophysics Data System (ADS)

Athanasiou, Sotirios; Legrand, Charles-Alexandre; Cristoloveanu, Sorin; Galy, Philippe

2017-02-01

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28 nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR) of 4.9 V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimum value of 3.5 V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

PubMed

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-15

Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2

NASA Astrophysics Data System (ADS)

Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

2018-06-01

Top-gated and bottom-gated transistors with multilayer MoS2 channel fully encapsulated by stacked Al2O3/HfO2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on–off current ratio of 108, high field-effect mobility of 102 cm2 V‑1 s‑1, and low subthreshold swing of 93 mV dec–1. Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10‑3–10‑2 V MV–1 cm–1 after 6 MV cm‑1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS2 channel fully encapsulated by stacked Al2O3/HfO2 is a promising way to fabricate high-performance ML MoS2 field-effect transistors for practical electron device applications.

New designs of a complete set of Photonic Crystals logic gates

NASA Astrophysics Data System (ADS)

Hussein, Hussein M. E.; Ali, Tamer A.; Rafat, Nadia H.

2018-03-01

In this paper, we introduce new designs of all-optical OR, AND, XOR, NOT, NOR, NAND and XNOR logic gates based on the interference effect. The designs are built using 2D square lattice Photonic Crystal (PhC) structure of dielectric rods embedded in air background. The lattice constant, a, and the rod radius, r, are designed to achieve maximum operating range of frequencies using the gap map. We use the Plane Wave Expansion (PWE) method to obtain the band structure and the gap map of the proposed designs. The operating wavelengths achieve a wide band range that varies between 1266.9 nm and 1996 nm with center wavelength at 1550 nm. The Finite-Difference Time-Domain (FDTD) method is used to study the field behavior inside the PhC gates. The gates satisfy their truth tables with reasonable power contrast ratio between logic '1' and logic '0'.

High Performance 50 nm InAlAs/In0.75GaAs Metamorphic High Electron Mobility Transistors with Si3N4 Passivation on Thin InGaAs Layer

NASA Astrophysics Data System (ADS)

Yeon, Seongjin; Seo, Kwangseok

2008-04-01

We fabricated 50 nm InAlAs/InGaAs metamorphic high electron mobility transistors (HEMTs) with a very thin barrier. Through the reduction of the gate-channel distance (dGC) in the epitaxial structure, a channel aspect ratio (ARC) of over three was achieved when Lg was 50 nm. We inserted a thin InGaAs layer as a protective layer, and tested various gate structures to reduce surface problems induced by barrier shrinkage and to optimize the device characteristics. Through the optimization of the gate structure with the thin InGaAs layer, the fabricated 50 nm metamorphic HEMT exhibited high DC and RF characteristics, Gm of 1.5 S/mm, and fT of 490 GHz.

Ultrashort Channel Length Black Phosphorus Field-Effect Transistors.

PubMed

Miao, Jinshui; Zhang, Suoming; Cai, Le; Scherr, Martin; Wang, Chuan

2015-09-22

This paper reports high-performance top-gated black phosphorus (BP) field-effect transistors with channel lengths down to 20 nm fabricated using a facile angle evaporation process. By controlling the evaporation angle, the channel length of the transistors can be reproducibly controlled to be anywhere between 20 and 70 nm. The as-fabricated 20 nm top-gated BP transistors exhibit respectable on-state current (174 μA/μm) and transconductance (70 μS/μm) at a VDS of 0.1 V. Due to the use of two-dimensional BP as the channel material, the transistors exhibit relatively small short channel effects, preserving a decent on-off current ratio of 10(2) even at an extremely small channel length of 20 nm. Additionally, unlike the unencapsulated BP devices, which are known to be chemically unstable in ambient conditions, the top-gated BP transistors passivated by the Al2O3 gate dielectric layer remain stable without noticeable degradation in device performance after being stored in ambient conditions for more than 1 week. This work demonstrates the great promise of atomically thin BP for applications in ultimately scaled transistors.

High transconductance zinc oxide thin-film transistors on flexible plastic substrates

NASA Astrophysics Data System (ADS)

Kimura, Yuta; Higaki, Tomohiro; Maemoto, Toshihiko; Sasa, Shigehiko; Inoue, Masataka

2012-02-01

We report the fabrication and characterization on high-performance ZnO based TFTs on unheated plastic substrate. ZnO films were grown by pulsed laser deposition (PLD) on polyethylene napthalate (PEN) substrates. Top-gate ZnO-TFTs were fabricated by photolithography and wet chemical etching. The source and drain contacts were formed by lift-off of e-beam deposited Ti(20 nm)/Au(200 nm). An HfO2 with thickness 100 nm was selected as the gate insulator, and top gate electrode Ti(20 nm)/Au(200 nm) was deposited by e-beam evaporation. We prepared a set of the structure with SiO2/TiO2 to investigate the characteristic changes that appear in the film characteristics in response to bending. From the ID-VDS and the transfer characteristics which are affected by bending and return for the ZnO-TFT with SiO2/TiO2 buffers, the TFTs were bent to a curvature radius of 8.5 mm. The transconductance, gm is obtained 1.7 mS/mm on flat, 1.4 mS/mm on bending and 1.3 mS/mm on returning the film, respectively. The ID-VDS characteristics were therefore not changed by bending. All of the devices exhibited a clear pinch-off behavior and a high on/off current ratio of ˜10^6. The threshold voltages, Vth were not changed drastically. Furthermore, TFT structures were changed from a conventional top-gate type to a bottom-gate type. A high transconductance of 95.8 mS/mm was achieved in the bottom-gate type TFT by using Al2O3 oxide buffer.

Gate length variation effect on performance of gate-first self-aligned In₀.₅₃Ga₀.₄₇As MOSFET.

PubMed

Mohd Razip Wee, Mohd F; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y

2013-01-01

A multi-gate n-type In₀.₅₃Ga₀.₄₇As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm(2)/Vs are achieved for the gate length and width of 0.2 µm and 30 µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10(-8) A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.

Gate Length Variation Effect on Performance of Gate-First Self-Aligned In0.53Ga0.47As MOSFET

PubMed Central

Mohd Razip Wee, Mohd F.; Dehzangi, Arash; Bollaert, Sylvain; Wichmann, Nicolas; Majlis, Burhanuddin Y.

2013-01-01

A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm2/Vs are achieved for the gate length and width of 0.2 µm and 30µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10−8 A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared. PMID:24367548

Design considerations and emerging challenges for nanotube-, nanowire-, and negative capacitor-field effect transistors

NASA Astrophysics Data System (ADS)

Wahab, Md. Abdul

As the era of classical planar metal-oxide-semiconductor field-effect transistors (MOSFETs) comes to an end, the semiconductor industry is beginning to adopt 3D device architectures, such as FinFETs, starting at the 22 nm technology node. Since physical limits such as short channel effect (SCE) and self-heating may dominate, it may be difficult to scale Si FinFET below 10 nm. In this regard, transistors with different materials, geometries, or operating principles may help. For example, gate has excellent electrostatic control over 2D thin film channel with planar geometry, and 1D nanowire (NW) channel with gate-all-around (GAA) geometry to reduce SCE. High carrier mobility of single wall carbon nanotube (SWNT) or III-V channels may reduce VDD to reduce power consumption. Therefore, as channel of transistor, 2D thin film of array SWNTs and 1D III-V multi NWs are promising for sub 10 nm technology nodes. In this thesis, we analyze the potential of these transistors from process, performance, and reliability perspectives. For SWNT FETs, we discuss a set of challenges (such as how to (i) characterize diameter distribution, (ii) remove metallic (m)-SWNTs, and (iii) avoid electrostatic cross-talk among the neighboring SWNTs), and demonstrate solution strategies both theoretically and experimentally. Regarding self-heating in these new class of devices (SWNT FET and GAA NW FET including state-of-the-art FinFET), higher thermal resistance from poor thermal conducting oxides results significant temperature rise, and reduces the IC life-time. For GAA NW FETs, we discuss accurate self-heating evaluation with good spatial, temporal, and thermal resolutions. The introduction of negative capacitor (NC), as gate dielectric stack of transistor, allows sub 60 mV/dec operation to reduce power consumption significantly. Taken together, our work provides a comprehensive perspective regarding the challenges and opportunities of sub 10 nm technology nodes.

Tuning the gate-opening pressure and particle size distribution of the switchable metal-organic framework DUT-8(Ni) by controlled nucleation in a micromixer.

PubMed

Miura, Hiroki; Bon, Volodymyr; Senkovska, Irena; Ehrling, Sebastian; Watanabe, Satoshi; Ohba, Masaaki; Kaskel, Stefan

2017-10-17

Controlled nucleation in a micromixer and further crystal growth were used to synthesize Ni 2 (2,6-ndc) 2 dabco (2,6-ndc - 2,6-naphthalenedicarboxylate, dabco - 1,4-diazabicyclo[2.2.2]octane), also termed DUT-8(Ni) (DUT = Dresden University of Technology), with narrow particle size distribution in a range of a few nm to several μm. The crystal size was found to significantly affect the switching characteristics, in particular the gate opening pressure in nitrogen adsorption isotherms at 77 K for this highly porous and flexible network. Below a critical size of about 500 nm, a type Ia isotherm typical of rigid MOFs is observed, while above approximately 1000 nm a pronounced gating behaviour is detected, starting at p/p 0 = 0.2. With increasing crystal size this transition gate becomes steeper indicating a more uniform distribution of activation energies within the crystal ensemble. At an intermediate size (500-1000 nm), the DUT-8(Ni) crystals close during activation but cannot be reopened by nitrogen at 77 K possibly indicating monodomain switching.

Radiation Failures in Intel 14nm Microprocessors

NASA Technical Reports Server (NTRS)

Bossev, Dobrin P.; Duncan, Adam R.; Gadlage, Matthew J.; Roach, Austin H.; Kay, Matthew J.; Szabo, Carl; Berger, Tammy J.; York, Darin A.; Williams, Aaron; LaBel, K.;

Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for AdvancedCMOS Devices

PubMed Central

Suzuki, Masamichi

2012-01-01

A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3) high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT) of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al) atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process. PMID:28817057

Atomic layer deposition of dielectrics on graphene using reversibly physisorbed ozone.

PubMed

Jandhyala, Srikar; Mordi, Greg; Lee, Bongki; Lee, Geunsik; Floresca, Carlo; Cha, Pil-Ryung; Ahn, Jinho; Wallace, Robert M; Chabal, Yves J; Kim, Moon J; Colombo, Luigi; Cho, Kyeongjae; Kim, Jiyoung

2012-03-27

Integration of graphene field-effect transistors (GFETs) requires the ability to grow or deposit high-quality, ultrathin dielectric insulators on graphene to modulate the channel potential. Here, we study a novel and facile approach based on atomic layer deposition through ozone functionalization to deposit high-κ dielectrics (such as Al(2)O(3)) without breaking vacuum. The underlying mechanisms of functionalization have been studied theoretically using ab initio calculations and experimentally using in situ monitoring of transport properties. It is found that ozone molecules are physisorbed on the surface of graphene, which act as nucleation sites for dielectric deposition. The physisorbed ozone molecules eventually react with the metal precursor, trimethylaluminum to form Al(2)O(3). Additionally, we successfully demonstrate the performance of dual-gated GFETs with Al(2)O(3) of sub-5 nm physical thickness as a gate dielectric. Back-gated GFETs with mobilities of ~19,000 cm(2)/(V·s) are also achieved after Al(2)O(3) deposition. These results indicate that ozone functionalization is a promising pathway to achieve scaled gate dielectrics on graphene without leaving a residual nucleation layer. © 2012 American Chemical Society

Nanocrystal floating gate memory with solution-processed indium-zinc-tin-oxide channel and colloidal silver nanocrystals

NASA Astrophysics Data System (ADS)

Hu, Quanli; Ha, Sang-Hyub; Lee, Hyun Ho; Yoon, Tae-Sik

2011-12-01

A nanocrystal (NC) floating gate memory with solution-processed indium-zinc-tin-oxide (IZTO) channel and silver (Ag) NCs embedded in thin gate dielectric layer (SiO2(30 nm)/Al2O3(3 nm)) was fabricated. Both the IZTO channel and colloidal Ag NC layers were prepared by spin-coating and subsequent annealing, and dip-coating process, respectively. A threshold voltage shift up to ~0.9 V, corresponding to the electron density of 6.5 × 1011 cm-2, at gate pulsing <=10 V was achieved by the charging of high density NCs. These results present the successful non-volatile memory characteristics of an oxide-semiconductor transistor fabricated through solution processes.

Junctionless tri-gate InGaAs MOSFETs

NASA Astrophysics Data System (ADS)

Zota, Cezar B.; Borg, Mattias; Wernersson, Lars-Erik; Lind, Erik

2017-12-01

We demonstrate and characterize junctionless tri-gate InGaAs MOSFETs, fabricated using a simplified process with gate lengths down to L g = 25 nm at a nanowire dimension of 7 × 16 nm2. These devices use a single 7-nm-thick In0.80Ga0.20As (N D = 1 × 1019 cm-3) layer as both channel and contacts. The devices show SSsat = 76 mV/dec, peak g m = 1.6 mS/µm and I ON = 160 µA/µm (at I OFF = 100 nA/µm and V DD = 0.5 V), the latter which is the highest reported value for a junctionless FET. We also show that device performance is mainly limited by high parasitic access resistance due to the narrow and thin contact layer.

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

NASA Astrophysics Data System (ADS)

Aleksandrova, P. V.; Gueorguiev, V. K.; Ivanov, Tz. E.; Kaschieva, S.

2006-08-01

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×1013 el/cm2, a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×1014 el/cm2 was observed.

Simulation study of reticle enhancement technology applications for 157-nm lithography

NASA Astrophysics Data System (ADS)

Schurz, Dan L.; Flack, Warren W.; Karklin, Linard

2002-03-01

The acceleration of the International Technology Roadmap for Semiconductors (ITRS) is placing significant pressure on the industry's infrastructure, particularly the lithography equipment. As recently as 1997, there was no optical solution offered past the 130 nm design node. The current roadmap has the 65 nm node (reduced from 70 nm) pulled in one year to 2007. Both 248 nm and 193 nm wavelength lithography tools will be pushed to their practical resolution limits in the near term. Very high numerical aperture (NA) 193 nm exposure tools in conjunction with resolution enhancement techniques (RET) will postpone the requirement for 157 nm lithography in manufacturing. However, ICs produced at 70 nm design rules with manufacturable k 1 values will require that 157 nm wavelength lithography tools incorporate the same RETs utilized in 248nm, and 193 nm tools. These enhancements will include Alternating Phase Shifting Masks (AltPSM) and Optical Proximity Correction (OPC) on F 2 doped quartz reticle substrates. This study investigates simulation results when AltPSM is applied to sub-100 nm test patterns in 157 nm lithography in order to maintain Critical Dimension (CD) control for both nested and isolated geometries. Aerial image simulations are performed for a range of numerical apertures, chrome regulators, gate pitches and gate widths. The relative performance for phase shifted versus binary structures is also compared. Results are demonstrated in terms of aerial image contrast and process window changes. The results clearly show that a combination of high NA and RET is necessary to achieve usable process windows for 70 nm line/space structures. In addition, it is important to consider two-dimensional proximity effects for sub-100 nm gate structures.

Low-Power and High-Speed Technique for logic Gates in 20nm Double-Gate FinFET Technology

NASA Astrophysics Data System (ADS)

Priydarshi, A.; Chattopadhyay, M. K.

2016-10-01

The FinFET is the leading example of multigate MOSFETS to substitute conventional single gate MOSFETs for ultimate scaling [1], The FinFET structure is a combination of a thin channel region and a double gate to suppress the short channel effects (SCEs) and Vthvariation [2], By using FinFET,figure of merits viz, ION, IOFF, output resistance, propagation delay, noise margin and leakage power, can be improved for ultra low power and high performance applications[3]. In this paper, a new high speed low power dynamic circuit design technique has been proposed using 20nm FinFETs. By applying the appropriate clock and sleep signal to the back gates of the FinFETs, the proposed circuit can efficiently control the dynamic power, During the pre-charging period, Vth of PMOS is controlled low so that a fast precharging can occur;

Addressing FinFET metrology challenges in 1X node using tilt-beam CD-SEM

NASA Astrophysics Data System (ADS)

Zhang, Xiaoxiao; Zhou, Hua; Ge, Zhenhua; Vaid, Alok; Konduparthi, Deepasree; Osorio, Carmen; Ventola, Stefano; Meir, Roi; Shoval, Ori; Kris, Roman; Adan, Ofer; Bar-Zvi, Maayan

2014-04-01

At 1X node, 3D FinFETS raise a number of new metrology challenges. Gate height and fin height are two of the most important parameters for process control. At present there is a metrology gap in inline in-die measurement of these parameters. In order to fill this metrology gap, in-column beam tilt has been developed and implemented on Applied Materials V4i+ top-down CD-SEM for height measurement. A low tilt (5°) beam and a high tilt (14°) beam have been calibrated to obtain two sets of images providing measurement of sidewall edge width to calculate height in the host. Evaluations are done with applications in both gate height and fin height. TEM correlation with R2 being 0.89 and precision of 0.81nm have been achieved on various in-die features in gate height application. Fin height measurement shows less accuracy (R2 being 0.77) and precision (1.49 nm) due to challenges brought by fin geometry, yet still promising as first attempt. Sensitivity to DOE offset, die-to-die and in-die variation is demonstrated in both gate height and fin height. Process defect is successfully captured from inline wafers with gate height measurement implemented in production. This is the first successful demonstration of inline in-die gate height measurement for 14nm FinFET process control.

Modeling of Nano-Scale Transistors and Memory Devices for Low Power Applications

NASA Astrophysics Data System (ADS)

Cao, Xi

As the featuring size of transistors scaled down to sub-20 nm, the continuous scaling of power has become one of the main challenges of the semiconductor industry. The power issue is raised by the barely scalable supply voltage and a limitation on the subthreshold swing (SS) of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, self-consistent quantum transport device simulators are developed to examine the nanoscale transistors based on black phosphorus (BP) materials. The scaling limit of double-gated BP MOSFETs is assessed. To reduce the SS below the thermionic limit for ultra-steep switching, tunnel FETs (TFETs) and vertical ballistic impact ionization FETs based on BP and its heterojunctions are investigated. Furthermore, the ferroelectric tunneling junction (FTJ) is modeled and examined for potential low power memory applications. For BP MOSFETs, the device physics at the ultimate scaling limit are examined. The performance of monolayer BP MOSFETs is projected to sub-10 nm and compared with the International Technology Roadmap for Semiconductors (ITRS) requirements. And the interplay of quantum mechanical effects and the highly anisotropic bandstructure of BP at this scale is investigated. By choice of layer number and crystalline direction, BP materials can offer a range of bandgap and effective mass values, which is attractive for TFET applications. Therefore, scaling behaviors of BP TFETs near and below the 10 nm scale are studied. The gate oxide thickness scaling and the effect of high-k dielectric are compared between the TFETs and the MOSFETs. For the TFETs with the gate lengths beyond 10 nm and at the sub-10 nm scale, the direct-source-to-drain tunneling issues are evaluated, and different strategies to achieve ultra-steep switching are specified. In a sub-10 nm graphene-BP-graphene heterojunction transistor, the sharp turnon behavior was observed, under a small source-drain bias of 0.1 V. The fast switch is attributed to a ballistic energy-dependent impact ionization mechanism. A device model is developed, which shows agreement with experiment results. The model is applied to explore the gate oxide scaling behavior and the effect of graphene doping, and to optimize the device for low power applications. Finally, to keep the integrity of the computing system, the FTJ is studied for its possible use as a low power memory device. A compact model for FTJ, dealing with both static and dynamic behaviors, is developed and compared with experimental data. The write energy consumed by the memory cell, comprising one transistor and one FTJ, is estimated by applying the compact model to circuit simulation. And a way to reduce the write energy is suggested.

Thickness engineering of atomic layer deposited Al2O3 films to suppress interfacial reaction and diffusion of Ni/Au gate metal in AlGaN/GaN HEMTs up to 600 °C in air

NASA Astrophysics Data System (ADS)

Suria, Ateeq J.; Yalamarthy, Ananth Saran; Heuser, Thomas A.; Bruefach, Alexandra; Chapin, Caitlin A.; So, Hongyun; Senesky, Debbie G.

2017-06-01

In this paper, we describe the use of 50 nm atomic layer deposited (ALD) Al2O3 to suppress the interfacial reaction and inter-diffusion between the gate metal and semiconductor interface, to extend the operation limit up to 600 °C in air. Suppression of diffusion is verified through Auger electron spectroscopy (AES) depth profiling and X-ray diffraction (XRD) and is further supported with electrical characterization. An ALD Al2O3 thin film (10 nm and 50 nm), which functions as a dielectric layer, was inserted between the gate metal (Ni/Au) and heterostructure-based semiconductor material (AlGaN/GaN) to form a metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). This extended the 50 nm ALD Al2O3 MIS-HEMT (50-MIS) current-voltage (Ids-Vds) and gate leakage (Ig,leakage) characteristics up to 600 °C. Both, the 10 nm ALD Al2O3 MIS-HEMT (10-MIS) and HEMT, failed above 350 °C, as evidenced by a sudden increase of approximately 50 times and 5.3 × 106 times in Ig,leakage, respectively. AES on the HEMT revealed the formation of a Ni-Au alloy and Ni present in the active region. Additionally, XRD showed existence of metal gallides in the HEMT. The 50-MIS enables the operation of AlGaN/GaN based electronics in oxidizing high-temperature environments, by suppressing interfacial reaction and inter-diffusion of the gate metal with the semiconductor.

Indium arsenide-on-SOI MOSFETs with extreme lattice mismatch

NASA Astrophysics Data System (ADS)

Wu, Bin

Both molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD) have been used to explore the growth of InAs on Si. Despite 11.6% lattice mismatch, planar InAs structures have been observed by scanning electron microscopy (SEM) when nucleating using MBE on patterned submicron Si-on-insulator (SOI) islands. Planar structures of size as large as 500 x 500 nm 2 and lines of width 200 nm and length a few microns have been observed. MOCVD growth of InAs also generates single grain structures on Si islands when the size is reduced to 100 x 100 nm2. By choosing SOI as the growth template, selective growth is enabled by MOCVD. Post-growth pattern-then-anneal process, in which MOCVD InAs is deposited onto unpatterned SOI followed with patterning and annealing of InAs-on-Si structure, is found to change the relative lattice parameters of encapsulated 17/5 nm InAs/Si island. Observed from transmission electron diffraction (TED) patterns, the lattice mismatch of 17/5 nm InAs/Si island reduces from 11.2 to 4.2% after being annealed at 800°C for 30 minutes. High-k Al2O3 dielectrics have been deposited by both electron-beam-enabled physical vapor deposition (PVD) and atomic layer deposition (ALD). Films from both techniques show leakage currents on the order of 10-9A/cm2, at ˜1 MV/cm electric field, breakdown field > ˜6 MV/cm, and dielectric constant > 6, comparable to those of reported ALD prior arts by Groner. The first MOSFETs with extreme lattice mismatch InAs-on-SOI channels using PVD Al2O3 as the gate dielectric are characterized. Channel recess was used to improve the gate control of the drain current.

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE PAGES

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.; ...

2014-10-15

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Ellipticity dependence of high harmonics generated using 400 nm driving lasers

NASA Astrophysics Data System (ADS)

Cheng, Yan; Khan, Sabih; Zhao, Kun; Zhao, Baozhen; Chini, Michael; Chang, Zenghu

2011-05-01

High order harmonics generated from 400 nm driving pulses hold promise of scaling photon flux of single attosecond pulses by one to two orders of magnitude. We report ellipticity dependence and phase matching of high order harmonics generated from such pulses in Neon gas target and compared them with similar measurements using 800 nm driving pulses. Based on measured ellipticity dependence, we predict that double optical gating (DOG) and generalized double optical gating (GDOG) can be employed to extract intense single attosecond pulses from pulse train, while polarization gating (PG) may not work for this purpose. This material is supported by the U.S. Army Research Office under grant number W911NF-07-1-0475, and by the Chemical Sciences, Geosciences and Biosciences Division, Office of Basic Energy Sciences, Office of Science, U.S. Department of Energy.

Atomic layer deposited Ta2O5 gate insulation for enhancing breakdown voltage of AlN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Deen, D. A.; Storm, D. F.; Bass, R.; Meyer, D. J.; Katzer, D. S.; Binari, S. C.; Lacis, J. W.; Gougousi, T.

2011-01-01

AlN/GaN heterostructures with a 3.5 nm AlN cap have been grown by molecular beam epitaxy followed by a 6 nm thick atomic layer deposited Ta2O5 film. Transistors fabricated with 150 nm length gates showed drain current density of 1.37 A/mm, transconductance of 315 mS/mm, and sustained drain-source biases up to 96 V while in the off-state before destructive breakdown as a result of the Ta2O5 gate insulator. Terman's method has been modified for the multijunction capacitor and allowed the measurement of interface state density (˜1013 cm-2 eV-1). Small-signal frequency performance of 75 and 115 GHz was obtained for ft and fmax, respectively.

Nanocharacterization Challenges in a Changing Microelectronics Landscape

NASA Astrophysics Data System (ADS)

Brilloüt, Michel

2011-11-01

As the microelectronics industry enters the "nano"-era new challenges emerge. Traditional scaling of the MOS transistor faces major obstacles in fulfilling "Moore's law". New features like strain and new materials (e.g. high k—metal gate stack) are introduced in order to sustain performance increases. For a better electrostatic control, devices will use the third dimension, e.g., in gate-all-around nanowire structures. Due to the escalating cost and complexity of sub-28 nm technologies fewer industrial players can afford the development and production of advanced CMOS processes and many companies acknowledge the fact that the value in products can also be obtained in using more diversified non-digital technologies (the so-called "More-than-Moore" domain). This evolving landscape brings new requirements—discussed in this paper—in terms of physical characterization of technologies and devices.

Study of fully-depleted Ge double-gate n-type Tunneling Field-Effect Transistors for improvement in on-state current and sub-threshold swing

NASA Astrophysics Data System (ADS)

Liu, Xiangyu; Hu, Huiyong; Wang, Meng; Zhang, Heming; Cui, Shimin; Shu, Bin; Wang, Bin

2018-01-01

In this paper, a fully-depleted (FD) Ge double-gate (DG) n-type Tunneling Field-Effect Transistors (TFET) structure is studied in detail by two-dimensional numerical simulation. The simulation results indicated that the on-state current Ion and on-off ratio of the FD Ge DG-TFET increases about 1 order of magnitude comparing with the Conventional Ge DG-TFET, and Ion=3.95×10-5 A/μm and the below 60 mV/decade subthreshold swing S=26.4 mV/decade are achieved with the length of gate LD=20 nm, the workfuntion of metal gate Φm=0.2 eV and the doping concentration of n+-type-channel ND=1×1018 cm-3. Moreover, the impacts of Φm, ND and LD are investigated. The simulation results indicated that the off-state current Ioff includes the tunneling current at the middle of channel IB the gated-induced drain leakage (GIDL) current IGIDL. With optimized Φm and ND, Ioff is reduced about 2 orders of magnitude to 2.5×10-13 A/μm with LD increasing from 40 nm to 100 nm, and on-off ratio is increased to 1.58×107.

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Lin, H. C.; Yang, T.; Sharifi, H.; Kim, S. K.; Xuan, Y.; Shen, T.; Mohammadi, S.; Ye, P. D.

2007-11-01

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with ex situ atomic-layer-deposited Al2O3 as gate dielectrics are studied. Maximum drain currents of 211 and 263mA/mm are obtained for 1μm gate-length Al2O3 MOS-HEMTs with 3 and 6nm thick gate oxide, respectively. C-V characteristic shows negligible hysteresis and frequency dispersion. The gate leakage current density of the MOS-HEMTs is 3-5 orders of magnitude lower than the conventional HEMTs under similar bias conditions. The drain current on-off ratio of MOS-HEMTs is ˜3×103 with a subthreshold swing of 90mV/decade. A maximum cutoff frequency (fT) of 27.3GHz and maximum oscillation frequency (fmax) of 39.9GHz and an effective channel mobility of 4250cm2/Vs are measured for the 1μm gate-length Al2O3 MOS-HEMT with 6nm gate oxide. Hooge's constant measured by low frequency noise spectral density characterization is 3.7×10-5 for the same device.

Practical implementation, characterization and applications of a multi-colour time-gated luminescence microscope.

PubMed

Zhang, Lixin; Zheng, Xianlin; Deng, Wei; Lu, Yiqing; Lechevallier, Severine; Ye, Zhiqiang; Goldys, Ewa M; Dawes, Judith M; Piper, James A; Yuan, Jingli; Verelst, Marc; Jin, Dayong

2014-10-13

Time-gated luminescence microscopy using long-lifetime molecular probes can effectively eliminate autofluorescence to enable high contrast imaging. Here we investigate a new strategy of time-gated imaging for simultaneous visualisation of multiple species of microorganisms stained with long-lived complexes under low-background conditions. This is realized by imaging two pathogenic organisms (Giardia lamblia stained with a red europium probe and Cryptosporidium parvum with a green terbium probe) at UV wavelengths (320-400 nm) through synchronization of a flash lamp with high repetition rate (1 kHz) to a robust time-gating detection unit. This approach provides four times enhancement in signal-to-background ratio over non-time-gated imaging, while the average signal intensity also increases six-fold compared with that under UV LED excitation. The high sensitivity is further confirmed by imaging the single europium-doped Y₂O₂S nanocrystals (150 nm). We report technical details regarding the time-gating detection unit and demonstrate its compatibility with commercial epi-fluorescence microscopes, providing a valuable and convenient addition to standard laboratory equipment.

Practical Implementation, Characterization and Applications of a Multi-Colour Time-Gated Luminescence Microscope

NASA Astrophysics Data System (ADS)

Zhang, Lixin; Zheng, Xianlin; Deng, Wei; Lu, Yiqing; Lechevallier, Severine; Ye, Zhiqiang; Goldys, Ewa M.; Dawes, Judith M.; Piper, James A.; Yuan, Jingli; Verelst, Marc; Jin, Dayong

2014-10-01

Time-gated luminescence microscopy using long-lifetime molecular probes can effectively eliminate autofluorescence to enable high contrast imaging. Here we investigate a new strategy of time-gated imaging for simultaneous visualisation of multiple species of microorganisms stained with long-lived complexes under low-background conditions. This is realized by imaging two pathogenic organisms (Giardia lamblia stained with a red europium probe and Cryptosporidium parvum with a green terbium probe) at UV wavelengths (320-400 nm) through synchronization of a flash lamp with high repetition rate (1 kHz) to a robust time-gating detection unit. This approach provides four times enhancement in signal-to-background ratio over non-time-gated imaging, while the average signal intensity also increases six-fold compared with that under UV LED excitation. The high sensitivity is further confirmed by imaging the single europium-doped Y2O2S nanocrystals (150 nm). We report technical details regarding the time-gating detection unit and demonstrate its compatibility with commercial epi-fluorescence microscopes, providing a valuable and convenient addition to standard laboratory equipment.

Analytical model of nanoscale junctionless transistors towards controlling of short channel effects through source/drain underlap and channel thickness engineering

NASA Astrophysics Data System (ADS)

Roy, Debapriya; Biswas, Abhijit

2018-01-01

We develop a 2D analytical subthreshold model for nanoscale double-gate junctionless transistors (DGJLTs) with gate-source/drain underlap. The model is validated using well-calibrated TCAD simulation deck obtained by comparing experimental data in the literature. To analyze and control short-channel effects, we calculate the threshold voltage, drain induced barrier lowering (DIBL) and subthreshold swing of DGJLTs using our model and compare them with corresponding simulation value at channel length of 20 nm with channel thickness tSi ranging 5-10 nm, gate-source/drain underlap (LSD) values 0-7 nm and source/drain doping concentrations (NSD) ranging 5-12 × 1018 cm-3. As tSi reduces from 10 to 5 nm DIBL drops down from 42.5 to 0.42 mV/V at NSD = 1019 cm-3 and LSD = 5 nm in contrast to decrement from 71 to 4.57 mV/V without underlap. For a lower tSiDIBL increases marginally with increasing NSD. The subthreshold swing reduces more rapidly with thinning of channel thickness rather than increasing LSD or decreasing NSD.

Naphthalenetetracarboxylic diimide layer-based transistors with nanometer oxide and side chain dielectrics operating below one volt.

PubMed

Jung, Byung Jun; Martinez Hardigree, Josue F; Dhar, Bal Mukund; Dawidczyk, Thomas J; Sun, Jia; See, Kevin Cua; Katz, Howard E

2011-04-26

We designed a new naphthalenetetracarboxylic diimide (NTCDI) semiconductor molecule with long fluoroalkylbenzyl side chains. The side chains, 1.2 nm long, not only aid in self-assembly and kinetically stabilize injected electrons but also act as part of the gate dielectric in field-effect transistors. On Si substrates coated only with the 2 nm thick native oxide, NTCDI semiconductor films were deposited with thicknesses from 17 to 120 nm. Top contact Au electrodes were deposited as sources and drains. The devices showed good transistor characteristics in air with 0.1-1 μA of drain current at 0.5 V of V(G) and V(DS) and W/L of 10-20, even though channel width (250 μm) is over 1000 times the distance (20 nm) between gate and drain electrodes. The extracted capacitance-times-mobility product, an expression of the sheet transconductance, can exceed 100 nS V(-1), 2 orders of magnitude higher than typical organic transistors. The vertical low-frequency capacitance with gate voltage applied in the accumulation regime reached as high as 650 nF/cm(2), matching the harmonic sum of capacitances of the native oxide and one side chain and indicating that some gate-induced carriers in such devices are distributed among all of the NTCDI core layers, although the preponderance of the carriers are still near the gate electrode. Besides demonstrating and analyzing thickness-dependent NTCDI-based transistor behavior, we also showed <1 V detection of dinitrotoluene vapor by such transistors.

Improved integration of ultra-thin high-k dielectrics in few-layer MoS2 FET by remote forming gas plasma pretreatment

NASA Astrophysics Data System (ADS)

Wang, Xiao; Zhang, Tian-Bao; Yang, Wen; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

2017-01-01

The effective and high-quality integration of high-k dielectrics on two-dimensional (2D) crystals is essential to the device structure engineering and performance improvement of field-effect transistor (FET) based on the 2D semiconductors. We report a 2D MoS2 transistor with ultra-thin Al2O3 top-gate dielectric (6.1 nm) and extremely low leakage current. Remote forming gas plasma pretreatment was carried out prior to the atomic layer deposition, providing nucleation sites with the physically adsorbed ions on the MoS2 surface. The top gate MoS2 FET exhibited excellent electrical performance, including high on/off current ratio over 109, subthreshold swing of 85 mV/decade and field-effect mobility of 45.03 cm2/V s. Top gate leakage current less than 0.08 pA/μm2 at 4 MV/cm has been obtained, which is the smallest compared with the reported top-gated MoS2 transistors. Such an optimized integration of high-k dielectric in 2D semiconductor FET with enhanced performance is very attractive, and it paves the way towards the realization of more advanced 2D nanoelectronic devices and integrated circuits.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Taehoon; Jung, Yong Chan; Seong, Sejong

The metal gate electrodes of Ni, W, and Pt have been investigated for their scavenging effect: a reduction of the GeO{sub x} interfacial layer (IL) between HfO{sub 2} dielectric and Ge substrate in metal/HfO{sub 2}/GeO{sub x}/Ge capacitors. All the capacitors were fabricated using the same process except for the material used in the metal electrodes. Capacitance-voltage measurements, scanning transmission electron microscopy, and electron energy loss spectroscopy were conducted to confirm the scavenging of GeO{sub x} IL. Interestingly, these metals are observed to remotely scavenge the interfacial layer, reducing its thickness in the order of Ni, W, and then Pt. Themore » capacitance equivalent thickness of these capacitors with Ni, W, and Pt electrodes are evaluated to be 2.7 nm, 3.0 nm, and 3.5 nm, and each final remnant physical thickness of GeO{sub x} IL layer is 1.1 nm 1.4 nm, and 1.9 nm, respectively. It is suggested that the scavenging effect induced by the metal electrodes is related to the concentration of oxygen vacancies generated by oxidation reaction at the metal/HfO{sub 2} interface.« less

Characterizations of and Radiation Effects in Several Emerging CMOS Technologies

NASA Astrophysics Data System (ADS)

Shufeng Ren

As the conventional scaling of Si based CMOS is approaching its limit at 7 nm technology node, many perceive that the adoption of novel materials and/or device structures are inevitable to keep Moore's law going. High mobility channel materials such as III-V compound semiconductors or Ge are considered promising to replace Si in order to achieve high performance as well as low power consumption. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, GaAs, InGaAs, GaSb, etc) to replace Si CMOS technology. Therefore novel high-k dielectrics, such as epitaxially grown crystalline oxides, have been explored to be incorporated onto the high mobility channel materials. Moreover, to enable continued scaling, extremely scaled devices structures such as nanowire gate-all-around structure are needed in the near future. Moreover, as the CMOS industry moves into the 7 nm node and beyond, novel lithography techniques such as EUV are believed to be adopted soon, which can bring radiation damage to CMOS devices and circuit during the fabrication process. Therefore radiation hardening technology in future generations of CMOS devices has again become an interesting research topic to deal with the possible process-induced damage as well as damage caused by operating in radiation harsh environment such as outer space, nuclear plant, etc. In this thesis, the electrical properties of a few selected emerging novel CMOS devices are investigated, which include InGaAs based extremely scaled ultra-thin body nanowire gate-all-around MOSFETs, GOI (Ge On Insulator) CMOS with recessed channel and source/drain, GaAs MOSFETs with crystalline La based gate stack, and crystalline SrTiO3, are investigated to extend our understanding of their electrical characteristics, underlying physical mechanisms, and material properties. Furthermore, the radiation responses of these aforementioned novel devices are thoroughly investigated, with a focus on the total ionizing dose (TID) effect, to understand the associated physical mechanisms, and to help to inspire ideas to improve radiation immunity of these novel devices. The experimental methods used in this thesis research include the measurements of C-V, I-V characteristics, where novel gate stack and interface characterization techniques are employed, such as AC Gm method, 1/f low frequency noise method, inelastic electron tunneling spectroscopy (IETS) for chemical bonding and defects detection, and carrier transport modeling. Sentaurus TCAD simulations are also carried out to obtain more physical insight in the complex, extremely scaled, device structures.

Reversibility and energy dissipation in adiabatic superconductor logic.

PubMed

Takeuchi, Naoki; Yamanashi, Yuki; Yoshikawa, Nobuyuki

2017-03-06

Reversible computing is considered to be a key technology to achieve an extremely high energy efficiency in future computers. In this study, we investigated the relationship between reversibility and energy dissipation in adiabatic superconductor logic. We analyzed the evolution of phase differences of Josephson junctions in the reversible quantum-flux-parametron (RQFP) gate and confirmed that the phase differences can change time reversibly, which indicates that the RQFP gate is physically, as well as logically, reversible. We calculated energy dissipation required for the RQFP gate to perform a logic operation and numerically demonstrated that the energy dissipation can fall below the thermal limit, or the Landauer bound, by lowering operation frequencies. We also investigated the 1-bit-erasure gate as a logically irreversible gate and the quasi-RQFP gate as a physically irreversible gate. We calculated the energy dissipation of these irreversible gates and showed that the energy dissipation of these gate is dominated by non-adiabatic state changes, which are induced by unwanted interactions between gates due to logical or physical irreversibility. Our results show that, in reversible computing using adiabatic superconductor logic, logical and physical reversibility are required to achieve energy dissipation smaller than the Landauer bound without non-adiabatic processes caused by gate interactions.

5. AVALON DAM GATE KEEPER'S COMPLEX: HOUSE (LEFT), WAREHOUSE ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

5. AVALON DAM - GATE KEEPER'S COMPLEX: HOUSE (LEFT), WAREHOUSE (RIGHT), AND CCC LANDSCAPING (FOREGROUND). VIEW TO SOUTHEAST - Carlsbad Irrigation District, Avalon Dam, On Pecos River, 4 miles North of Carlsbad, Carlsbad, Eddy County, NM

Organization of the 1991 Society of America Photonic Science Topical Meeting Held in Monterey, California on September 26 - 28, 1991. 1991 Technical Digest Series, Volume 16, Conference Edition

DTIC Science & Technology

1992-05-01

Yuxin Ni, Duoyuan Wang, Lingzhi Hu, Huizhu He, Jie Xie. 532 nm. (p. 122) Junyi Zhing, Academy of Sciences of China. Photon-gated persistent spectral hole...cal hole-burning, Duoyuan Wang, Lingzhi Hu, Huizhu He, Lizeng Zhao, Xin Mi, Yuxin Ni, Academy of Sciences, China. FES Marker mode structure in the...Dongxiang, Mi Xin, Nie Yuxin Institute of Physics, Academia Sinica Beijing 100080, China, Fax:(86-1)2562605 Wang Duoyuan, Hu Lingzhi , He Huizhu, Xie

Fabrication of resistively-coupled single-electron device using an array of gold nanoparticles

NASA Astrophysics Data System (ADS)

Huong, Tran Thi Thu; Matsumoto, Kazuhiko; Moriya, Masataka; Shimada, Hiroshi; Kimura, Yasuo; Hirano-Iwata, Ayumi; Mizugaki, Yoshinao

2017-08-01

We demonstrated one type of single-electron device that exhibited electrical characteristics similar to those of resistively-coupled SE transistor (R-SET) at 77 K and room temperature (287 K). Three Au electrodes on an oxidized Si chip served as drain, source, and gate electrodes were formed using electron-beam lithography and evaporation techniques. A narrow (70-nm-wide) gate electrode was patterned using thermal evaporation, whereas wide (800-nm-wide) drain and source electrodes were made using shadow evaporation. Subsequently, aqueous solution of citric acid and 15-nm-diameter gold nanoparticles (Au NPs) and toluene solution of 3-nm-diameter Au NPs chemisorbed via decanethiol were dropped on the chip to make the connections between the electrodes. Current-voltage characteristics between the drain and source electrodes exhibited Coulomb blockade (CB) at both 77 and 287 K. Dependence of the CB region on the gate voltage was similar to that of an R-SET. Simulation results of the model based on the scanning electron microscopy image of the device could reproduce the characteristics like the R-SET.

Sensing small neurotransmitter-enzyme interaction with nanoporous gated ion-sensitive field effect transistors.

PubMed

Kisner, Alexandre; Stockmann, Regina; Jansen, Michael; Yegin, Ugur; Offenhäusser, Andreas; Kubota, Lauro Tatsuo; Mourzina, Yulia

2012-01-15

Ion-sensitive field effect transistors with gates having a high density of nanopores were fabricated and employed to sense the neurotransmitter dopamine with high selectivity and detectability at micromolar range. The nanoporous structure of the gates was produced by applying a relatively simple anodizing process, which yielded a porous alumina layer with pores exhibiting a mean diameter ranging from 20 to 35 nm. Gate-source voltages of the transistors demonstrated a pH-dependence that was linear over a wide range and could be understood as changes in surface charges during protonation and deprotonation. The large surface area provided by the pores allowed the physical immobilization of tyrosinase, which is an enzyme that oxidizes dopamine, on the gates of the transistors, and thus, changes the acid-base behavior on their surfaces. Concentration-dependent dopamine interacting with immobilized tyrosinase showed a linear dependence into a physiological range of interest for dopamine concentration in the changes of gate-source voltages. In comparison with previous approaches, a response time relatively fast for detecting dopamine was obtained. Additionally, selectivity assays for other neurotransmitters that are abundantly found in the brain were examined. These results demonstrate that the nanoporous structure of ion-sensitive field effect transistors can easily be used to immobilize specific enzyme that can readily and selectively detect small neurotransmitter molecule based on its acid-base interaction with the receptor. Therefore, it could serve as a technology platform for molecular studies of neurotransmitter-enzyme binding and drugs screening. Copyright © 2011 Elsevier B.V. All rights reserved.

6. AVALON DAM GATE KEEPER'S COMPLEX: GARAGE AND WAREHOUSE ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

6. AVALON DAM - GATE KEEPER'S COMPLEX: GARAGE AND WAREHOUSE (LEFT), HOUSE (RIGHT), AND CCC LANDSCAPING (FOREGROUND). VIEW TO NORTH - Carlsbad Irrigation District, Avalon Dam, On Pecos River, 4 miles North of Carlsbad, Carlsbad, Eddy County, NM

7. McMILLAN DAM GATE KEEPER'S HOUSE WITH CCC LANDSCAPING ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

7. McMILLAN DAM - GATE KEEPER'S HOUSE WITH CCC LANDSCAPING IN THE FOREGROUND. VIEW TO SOUTHEAST - Carlsbad Irrigation District, McMillan Dam, On Pecos River, 13 miles North of Carlsbad, Carlsbad, Eddy County, NM

High-frequency graphene voltage amplifier.

PubMed

Han, Shu-Jen; Jenkins, Keith A; Valdes Garcia, Alberto; Franklin, Aaron D; Bol, Ageeth A; Haensch, Wilfried

2011-09-14

While graphene transistors have proven capable of delivering gigahertz-range cutoff frequencies, applying the devices to RF circuits has been largely hindered by the lack of current saturation in the zero band gap graphene. Herein, the first high-frequency voltage amplifier is demonstrated using large-area chemical vapor deposition grown graphene. The graphene field-effect transistor (GFET) has a 6-finger gate design with gate length of 500 nm. The graphene common-source amplifier exhibits ∼5 dB low frequency gain with the 3 dB bandwidth greater than 6 GHz. This first AC voltage gain demonstration of a GFET is attributed to the clear current saturation in the device, which is enabled by an ultrathin gate dielectric (4 nm HfO(2)) of the embedded gate structures. The device also shows extrinsic transconductance of 1.2 mS/μm at 1 V drain bias, the highest for graphene FETs using large-scale graphene reported to date.

Leakage and field emission in side-gate graphene field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Di Bartolomeo, A., E-mail: dibant@sa.infn.it; Iemmo, L.; Romeo, F.

We fabricate planar graphene field-effect transistors with self-aligned side-gate at 100 nm from the 500 nm wide graphene conductive channel, using a single lithographic step. We demonstrate side-gating below 1 V with conductance modulation of 35% and transconductance up to 0.5 mS/mm at 10 mV drain bias. We measure the planar leakage along the SiO{sub 2}/vacuum gate dielectric over a wide voltage range, reporting rapidly growing current above 15 V. We unveil the microscopic mechanisms driving the leakage, as Frenkel-Poole transport through SiO{sub 2} up to the activation of Fowler-Nordheim tunneling in vacuum, which becomes dominant at higher voltages. We report a field-emission current densitymore » as high as 1 μA/μm between graphene flakes. These findings are important for the miniaturization of atomically thin devices.« less

Direct current performance and current collapse in AlGaN/GaN insulated gate high-electron mobility transistors on Si (1 1 1) substrate with very thin SiO2 gate dielectric

NASA Astrophysics Data System (ADS)

Lachab, M.; Sultana, M.; Fatima, H.; Adivarahan, V.; Fareed, Q.; Khan, M. A.

2012-12-01

This work reports on the dc performance of AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) grown on Si (1 1 1) substrate and the study of current dispersion in these devices using various widely adopted methods. The MOSHEMTs were fabricated using a very thin (4.2 nm) SiO2 film as the gate insulator and were subsequently passivated with about 30 nm thick Si3N4 layer. For devices with 2.5 µm long gates and a 4 µm drain-to-source spacing, the maximum saturation drain current density was 822 mA mm-1 at + 4 V gate bias and the peak external transconductance was ˜100 mS mm-1. Furthermore, the oxide layer successfully suppressed the drain and gate leakage currents with the subthreshold current and the gate diode current levels exceeding by more than three orders of magnitude the levels found in their Schottky gate counterparts. Capacitance-voltage and dynamic current-voltage measurements were carried out to assess the oxide quality as well as the devices’ surface properties after passivation. The efficacy of each of these characterization techniques to probe the presence of interface traps and oxide charge in the nitride-based transistors is also discussed.

Improving subthreshold swing to thermionic emission limit in carbon nanotube network film-based field-effect

NASA Astrophysics Data System (ADS)

Zhao, Chenyi; Zhong, Donglai; Qiu, Chenguang; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2018-01-01

In this letter, we explore the vertical scaling-down behavior of carbon nanotube (CNT) network film field-effect transistors (FETs) and show that by using a high-efficiency gate insulator, we can substantially improve the subthreshold swing (SS) and its uniformity. By using an HfO2 layer with a thickness of 7.3 nm as the gate insulator, we fabricated CNT network film FETs with a long channel (>2 μm) that exhibit an SS of approximately 60 mV/dec. The preferred thickness of HfO2 as the gate insulator in a CNT network FET is between 7 nm and 10 nm, simultaneously yielding an excellent SS (<80 mV/decade) and low gate leakage. However, because of the statistical fluctuations of the network CNT channel, the lateral scaling of CNT network film-based FETs is more difficult than that of conventional FETs. Experiments suggest that excellent SS is difficult to achieve statistically in CNT network film FETs with a small channel length (smaller than the mean length of the CNTs), which eventually limits the further scaling down of this kind of CNT FET to the sub-micrometer regime.

Top-gated chemical vapor deposition grown graphene transistors with current saturation.

PubMed

Bai, Jingwei; Liao, Lei; Zhou, Hailong; Cheng, Rui; Liu, Lixin; Huang, Yu; Duan, Xiangfeng

2011-06-08

Graphene transistors are of considerable interest for radio frequency (rf) applications. In general, transistors with large transconductance and drain current saturation are desirable for rf performance, which is however nontrivial to achieve in graphene transistors. Here we report high-performance top-gated graphene transistors based on chemical vapor deposition (CVD) grown graphene with large transconductance and drain current saturation. The graphene transistors were fabricated with evaporated high dielectric constant material (HfO(2)) as the top-gate dielectrics. Length scaling studies of the transistors with channel length from 5.6 μm to 100 nm show that complete current saturation can be achieved in 5.6 μm devices and the saturation characteristics degrade as the channel length shrinks down to the 100-300 nm regime. The drain current saturation was primarily attributed to drain bias induced shift of the Dirac points. With the selective deposition of HfO(2) gate dielectrics, we have further demonstrated a simple scheme to realize a 300 nm channel length graphene transistors with self-aligned source-drain electrodes to achieve the highest transconductance of 250 μS/μm reported in CVD graphene to date.

Design and analysis of 30 nm T-gate InAlN/GaN HEMT with AlGaN back-barrier for high power microwave applications

NASA Astrophysics Data System (ADS)

Murugapandiyan, P.; Ravimaran, S.; William, J.; Meenakshi Sundaram, K.

2017-11-01

In this article, we present the DC and microwave characteristics of a novel 30 nm T-gate InAlN/AlN/GaN HEMT with AlGaN back-barrier. The device structure is simulated by using Synopsys Sentaurus TCAD Drift-Diffusion transport model at room temperature. The device features are heavily doped (n++ GaN) source/drain regions with Si3N4 passivated device surface for reducing the contact resistances and gate capacitances of the device, which uplift the microwave characteristics of the HEMTs. 30 nm gate length D-mode (E-mode) HEMT exhibited a peak drain current density Idmax of 2.3 (2.42) A/mm, transconductance gm of 1.24(1.65) S/mm, current gain cut-off frequency ft of 262 (246) GHz, power gain cut-off frequency fmax of 246(290) GHz and the three terminal off-state breakdown voltage VBR of 40(38) V. The preeminent microwave characteristics with the higher breakdown voltage of the proposed GaN-based HEMT are the expected to be the most optimistic applicant for future high power millimeter wave applications.

Dependence of Pentacene Crystal Growth on Dielectric Roughness for Fabrication of Flexible Field-Effect Transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, H.; Yang, C; Kim, S

2010-01-01

The dependence of pentacene nanostructures on gate dielectric surfaces were investigated for flexible organic field-effect transistor (OFET) applications. Two bilayer types of polymer/aluminum oxide (Al{sub 2}O{sub 3}) gate dielectrics were fabricated on commercial Al foils laminated onto a polymer back plate. Some Al foils were directly used as gate electrodes, and others were smoothly polished by an electrolytic etching. These Al surfaces were then anodized and coated with poly({alpha}-methyl styrene) (PAMS). For PAMS/Al{sub 2}O{sub 3} dielectrics onto etched Al foils, surface roughness up to 1 nm could be reached, although isolated dimples with a lateral diameter of several micrometers weremore » still present. On PAMS/Al{sub 2}O{sub 3} dielectrics (surface roughness >40 nm) containing mechanical grooves of Al foil, average hole mobility ({mu}FET) of 50 nm thick pentacene-FETs under the low operating voltages (|V| < 6 V) was {approx}0.15 cm{sup 2} V{sup -1} s{sup -1}. In contrast, pentacene-FETs employing the etched Al gates exhibited {mu}FET of 0.39 cm{sup 2} V{sup -1} s{sup -1}, which was comparable to that of reference samples with PAMS/Al{sub 2}O{sub 3} dielectrics onto flat sputtered Al gates. Conducting-probe atomic force microscopy and two-dimensional X-ray diffraction of pentacene films with various thicknesses revealed different out-of-plane and in-plane crystal orderings of pentacene, depending on the surface roughness of the gate dielectrics.« less

Investigation of aluminum gate CMP in a novel alkaline solution

NASA Astrophysics Data System (ADS)

Cuiyue, Feng; Yuling, Liu; Ming, Sun; Wenqian, Zhang; Jin, Zhang; Shuai, Wang

2016-01-01

Beyond 45 nm, due to the superior CMP performance requirements with the metal gate of aluminum in the advanced CMOS process, a novel alkaline slurry for an aluminum gate CMP with poly-amine alkali slurry is investigated. The aluminum gate CMP under alkaline conditions has two steps: stock polishing and fine polishing. A controllable removal rate, the uniformity of aluminum gate and low corrosion are the key challenges for the alkaline polishing slurry of the aluminum gate CMP. This work utilizes the complexation-soluble function of FA/O II and the preference adsorption mechanism of FA/O I nonionic surfactant to improve the uniformity of the surface chemistry function with the electrochemical corrosion research, such as OCP-TIME curves, Tafel curves and AC impedance. The result is that the stock polishing slurry (with SiO2 abrasive) contains 1 wt.% H2O2,0.5 wt.% FA/O II and 1.0 wt.% FA/O I nonionic surfactant. For a fine polishing process, 1.5 wt.% H2O2, 0.4 wt.% FA/O II and 2.0 wt.% FA/O I nonionic surfactant are added. The polishing experiments show that the removal rates are 3000 ± 50 Å/min and 1600 ± 60 Å/min, respectively. The surface roughnesses are 2.05 ± 0.128 nm and 1.59 ± 0.081 nm, respectively. A combination of the functions of FA/O II and FA/O I nonionic surfactant obtains a controllable removal rate and a better surface roughness in alkaline solution.

Effect of Environment on the Fidelity of Control and Measurements of Solid-State Quantum Devices

DTIC Science & Technology

2013-07-22

space vs. thickness of the film a for a DQD charge qubit in one dimension with dot geometry d = 30 nm and l = 60 nm at 0 K...constitute a conducting half- space , rather than the more sparse gate geometry used in [134]. It is also instructive to compare our results with the ...40 ms [134]. However, it must be kept in mind that we have so far considered the simpler top gate geometry of a conducting half-

9. BLACK RIVER CANAL CANAL (RIGHT), DISCHARGE GATE (BACKGROUND), ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

9. BLACK RIVER CANAL - CANAL (RIGHT), DISCHARGE GATE (BACKGROUND), FARMER'S TURNOUT (LEFT), AND LATERAL NO. 14 (FOREGROUND). VIEW TO SOUTHEAST - Carlsbad Irrigation District, Black River Canal, 15 miles Southeast of Carlsbad near Malaga, Carlsbad, Eddy County, NM

Development and characterization of ultrathin hafnium titanates as high permittivity gate insulators

NASA Astrophysics Data System (ADS)

Li, Min

High permittivity or high-kappa materials are being developed for use as gate insulators for future ultrascaled metal oxide semiconductor field effect transistors (MOSFETs). Hafnium containing compounds are the leading candidates. Due to its moderate permittivity, however, it is difficult to achieve HfO2 gate structures with an EOT well below 1.0 nm. One approach to increase HfO2 permittivity is combining it with a very high-kappa material, such as TiO2. In this thesis, we systematically studied the electrical and physical characteristics of high-kappa hafnium titanates films as gate insulators. A series of HfxTi1-xO2 films with well-controlled composition were deposited using an MOCVD system. The physical properties of the films were analyzed using a variety of characterization techniques. X-ray micro diffraction indicates that the Ti-rich thin film is more immune to crystallization. TEM analysis showed that the thick stoichiometric HfTiO 4 film has an orthorhombic structure and large anisotropic grains. The C-V curves from the devices with the hafnium titanates films displayed relatively low hysteresis. In a certain composition range, the interfacial layer (IL) EOT and permittivity of HfxTi1-x O2 increases linearly with increasing Ti. The charge is negative for HfxTi1-xO2/IL and positive for Si/IL interface, and the magnitude increases as Hf increases. For ultra-thin films (less than 2 nm EOT), the leakage current increases with increasing HE Moreover, the Hf-rich sample has weaker temperature dependence of the current. In the MOSFET devices with the hafnium titanates films, normal transistor characteristics were observed, also electron mobility degradation. Next, we investigated the effects that different pre-deposition surface treatments, including HF dipping, NH3 surface nitridation, and HfO2 deposition, have on the electrical properties of hafnium titanates. Surface nitridation shows stronger effect than the thin HfO2 layer. The nitrided samples displayed a negative flat band voltage shift and larger hysteresis relative to the HF-dipped samples. The IL EOT reduction by mtridation increases with increasing HE Surface nitridation also induces extra charge, more considerable at the Si/IL interface. The leakage current is reduced in the Hf-rich samples with a nitride layer. Electron mobility degradation by surface nitridation was also observed.

Gigahertz-gated InGaAs/InP single-photon detector with detection efficiency exceeding 55% at 1550 nm

DOE Office of Scientific and Technical Information (OSTI.GOV)

Comandar, L. C.; Engineering Department, Cambridge University, 9 J J Thomson Ave, Cambridge CB3 0FA; Fröhlich, B.

We report on a gated single-photon detector based on InGaAs/InP avalanche photodiodes (APDs) with a single-photon detection efficiency exceeding 55% at 1550 nm. Our detector is gated at 1 GHz and employs the self-differencing technique for gate transient suppression. It can operate nearly dead time free, except for the one clock cycle dead time intrinsic to self-differencing, and we demonstrate a count rate of 500 Mcps. We present a careful analysis of the optimal driving conditions of the APD measured with a dead time free detector characterization setup. It is found that a shortened gate width of 360 ps together with anmore » increased driving signal amplitude and operation at higher temperatures leads to improved performance of the detector. We achieve an afterpulse probability of 7% at 50% detection efficiency with dead time free measurement and a record efficiency for InGaAs/InP APDs of 55% at an afterpulse probability of only 10.2% with a moderate dead time of 10 ns.« less

Near-IR squaraine dye–loaded gated periodic mesoporous organosilica for photo-oxidation of phenol in a continuous-flow device

PubMed Central

Borah, Parijat; Sreejith, Sivaramapanicker; Anees, Palapuravan; Menon, Nishanth Venugopal; Kang, Yuejun; Ajayaghosh, Ayyappanpillai; Zhao, Yanli

2015-01-01

Periodic mesoporous organosilica (PMO) has been widely used for the fabrication of a variety of catalytically active materials. We report the preparation of novel photo-responsive PMO with azobenzene-gated pores. Upon activation, the azobenzene gate undergoes trans-cis isomerization, which allows an unsymmetrical near-infrared squaraine dye (Sq) to enter into the pores. The gate closure by cis-trans isomerization of the azobenzene unit leads to the safe loading of the monomeric dye inside the pores. The dye-loaded and azobenzene-gated PMO (Sq-azo@PMO) exhibits excellent generation of reactive oxygen species upon excitation at 664 nm, which can be effectively used for the oxidation of phenol into benzoquinone in aqueous solution. Furthermore, Sq-azo@PMO as the catalyst was placed inside a custom-built, continuous-flow device to carry out the photo-oxidation of phenol to benzoquinone in the presence of 664-nm light. By using the device, about 23% production of benzoquinone with 100% selectivity was achieved. The current research presents a prototype of transforming heterogeneous catalysts toward practical use. PMID:26601266

High-performance silicon nanowire field-effect transistor with silicided contacts

NASA Astrophysics Data System (ADS)

Rosaz, G.; Salem, B.; Pauc, N.; Gentile, P.; Potié, A.; Solanki, A.; Baron, T.

2011-08-01

Undoped silicon nanowire (Si NW) field-effect transistors (FETs) with a back-gate configuration have been fabricated and characterized. A thick (200 nm) Si3N4 layer was used as a gate insulator and a p++ silicon substrate as a back gate. Si NWs have been grown by the chemical vapour deposition method using the vapour-liquid-solid mechanism and gold as a catalyst. Metallic contacts have been deposited using Ni/Al (80 nm/120 nm) and characterized before and after an optimized annealing step at 400 °C, which resulted in a great decrease in the contact resistance due to the newly formed nickel silicide/Si interface at source and drain. These optimized devices show a good hole mobility of around 200 cm2 V-1 s-1, in the same range as the bulk material, with a good ON current density of about 28 kA cm-2. Finally, hysteretic behaviour of NW channel conductance is discussed to explain the importance of NW surface passivation.

Experimental determination of the impact of polysilicon LER on sub-100-nm transistor performance

NASA Astrophysics Data System (ADS)

Patterson, Kyle; Sturtevant, John L.; Alvis, John R.; Benavides, Nancy; Bonser, Douglas; Cave, Nigel; Nelson-Thomas, Carla; Taylor, William D.; Turnquest, Karen L.

2001-08-01

Photoresist line edge roughness (LER) has long been feared as a potential limitation to the application of various patterning technologies to actual devices. While this concern seems reasonable, experimental verification has proved elusive and thus LER specifications are typically without solid parametric rationale. We report here the transistor device performance impact of deliberate variations of polysilicon gate LER. LER magnitude was attenuated by more than a factor of 5 by altering the photoresist type and thickness, substrate reflectivity, masking approach, and etch process. The polysilicon gate LER for nominally 70 - 150 nm devices was quantified using digital image processing of SEM images, and compared to gate leakage and drive current for variable length and width transistors. With such comparisons, realistic LER specifications can be made for a given transistor. It was found that subtle cosmetic LER differences are often not discernable electrically, thus providing hope that LER will not limit transistor performance as the industry migrates to sub-100 nm patterning.

Gate-controlled quantum collimation in nanocolumn resonant tunneling transistors.

PubMed

Wensorra, J; Lepsa, M I; Trellenkamp, S; Moers, J; Indlekofer, K M; Lüth, H

2009-11-18

Nanoscaled resonant tunneling transistors (RTT) based on MBE-grown GaAs/AlAs double-barrier quantum well (DBQW) structures have been fabricated by a top-down approach using electron-beam lithographic definition of the vertical nanocolumns. In the preparation process, a reproducible mask alignment accuracy of below 10 nm has been achieved and the all-around metal gate at the level of the DBQW structure has been positioned at a distance of about 20 nm relative to the semiconductor nanocolumn. Due to the specific doping profile n++/i/n++ along the transistor nanocolumn, a particular confining potential is established for devices with diameters smaller than 70 nm, which causes a collimation effect of the propagating electrons. Under these conditions, room temperature optimum performance of the nano-RTTs is achieved with peak-to-valley current ratios above 2 and a peak current swing factor of about 6 for gate voltages between -6 and +6 V. These values indicate that our nano-RTTs can be successfully used in low power fast nanoelectronic circuits.

Organic field effect transistors - Study of performance parameters for different dielectric layer thickness

NASA Astrophysics Data System (ADS)

Assis, Anu; Shahul Hameed T., A.; Predeep, P.

2017-06-01

Mobility and current handling capabilities of Organic Field Effect Transistor (OFET) are vitally important parameters in the electrical performance where the material parameters and thickness of different layers play significant role. In this paper, we report the simulation of an OFET using multi physics tool, where the active layer is pentacene and Poly Methyl Methacrylate (PMMA) forms the dielectric. Electrical characterizations of the OFET on varying the thickness of the dielectric layer from 600nm to 400nm are simulated and drain current, transconductance and mobility are analyzed. In the study it is found that even though capacitance increases with reduction in dielectric layer thickness, the transconductance effect is reflected many more times in the mobility which in turn could be attributed to the variations in transverse electric field. The layer thickness below 300nm may result in gate leakage current points to the requirement of optimizing the thickness of different layers for better performance.

Meeting critical gate linewidth control needs at the 65 nm node

NASA Astrophysics Data System (ADS)

Mahorowala, Arpan; Halle, Scott; Gabor, Allen; Chu, William; Barberet, Alexandra; Samuels, Donald; Abdo, Amr; Tsou, Len; Yan, Wendy; Iseda, Seiji; Patel, Kaushal; Dirahoui, Bachir; Nomura, Asuka; Ahsan, Ishtiaq; Azam, Faisal; Berg, Gary; Brendler, Andrew; Zimmerman, Jeffrey; Faure, Tom

2006-03-01

With the nominal gate length at the 65 nm node being only 35 nm, controlling the critical dimension (CD) in polysilicon to within a few nanometers is essential to achieve a competitive power-to-performance ratio. Gate linewidths must be controlled, not only at the chip level so that the chip performs as the circuit designers and device engineers had intended, but also at the wafer level so that more chips with the optimum power-to-performance ratio are manufactured. Achieving tight across-chip linewidth variation (ACLV) and chip mean variation (CMV) is possible only if the mask-making, lithography, and etching processes are all controlled to very tight specifications. This paper identifies the various ACLV and CMV components, describes their root causes, and discusses a methodology to quantify them. For example, the site-to-site ACLV component is divided into systematic and random sub-components. The systematic component of the variation is attributed in part to pattern density variation across the field, and variation in exposure dose across the slit. The paper demonstrates our team's success in achieving the tight gate CD tolerances required for 65 nm technology. Certain key challenges faced, and methods employed to overcome them are described. For instance, the use of dose-compensation strategies to correct the small but systematic CD variations measured across the wafer, is described. Finally, the impact of immersion lithography on both ACLV and CMV is briefly discussed.

Effects of HfO2 encapsulation on electrical performances of few-layered MoS2 transistor with ALD HfO2 as back-gate dielectric.

PubMed

Xu, Jingping; Wen, Ming; Zhao, Xinyuan; Liu, Lu; Song, Xingjuan; Lai, Pui-To; Tang, Wing-Man

2018-08-24

The carrier mobility of MoS 2 transistors can be greatly improved by the screening role of high-k gate dielectric. In this work, atomic-layer deposited (ALD) HfO 2 annealed in NH 3 is used to replace SiO 2 as the gate dielectric to fabricate back-gated few-layered MoS 2 transistors, and good electrical properties are achieved with field-effect mobility (μ) of 19.1 cm 2 V -1 s -1 , subthreshold swing (SS) of 123.6 mV dec -1 and on/off ratio of 3.76 × 10 5 . Furthermore, enhanced device performance is obtained when the surface of the MoS 2 channel is coated by an ALD HfO 2 layer with different thicknesses (10, 15 and 20 nm), where the transistor with a 15 nm HfO 2 encapsulation layer exhibits the best overall electrical properties: μ = 42.1 cm 2 V -1 s -1 , SS = 87.9 mV dec -1 and on/off ratio of 2.72 × 10 6 . These improvements should be associated with the enhanced screening effect on charged-impurity scattering and protection from absorption of environmental gas molecules by the high-k encapsulation. The capacitance equivalent thickness of the back-gate dielectric (HfO 2 ) is only 6.58 nm, which is conducive to scaling of the MoS 2 transistors.

Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry

NASA Astrophysics Data System (ADS)

Vishvakarma, S. K.; Beohar, Ankur; Vijayvargiya, Vikas; Trivedi, Priyal

2017-07-01

In this paper, analysis of DC and analog/RF performance on cylindrical gate-all-around tunnel field-effect transistor (TFET) has been made using distinct device geometry. Firstly, performance parameters of GAA-TFET are analyzed in terms of drain current, gate capacitances, transconductance, source-drain conductance at different radii and channel length. Furthermore, we also produce the geometrical analysis towards the optimized investigation of radio frequency parameters like cut-off frequency, maximum oscillation frequency and gain bandwidth product using a 3D technology computer-aided design ATLAS. Due to band-to-band tunneling based current mechanism unlike MOSFET, gate-bias dependence values as primary parameters of TFET differ. We also analyze that the maximum current occurs when radii of Si is around 8 nm due to high gate controllability over channel with reduced fringing effects and also there is no change in the current of TFET on varying its length from 100 to 40 nm. However current starts to increase when channel length is further reduced for 40 to 30 nm. Both of these trades-offs affect the RF performance of the device. Project supported by the Council of Scientific and Industrial Research (CSIR) Funded Research Project, Grant No. 22/0651/14/EMR-II, Government of India.

Demonstration of a Sub-Millimeter Wave Integrated Circuit (S-MMIC) using InP HEMT with a 35-nm Gate

NASA Technical Reports Server (NTRS)

Deal, W. R.; Din, S.; Padilla, J.; Radisic, V.; Mei, G.; Yoshida, W.; Liu, P. S.; Uyeda, J.; Barsky, M.; Gaier, T.;

Design of a scanning gate microscope for mesoscopic electron systems in a cryogen-free dilution refrigerator.

PubMed

Pelliccione, M; Sciambi, A; Bartel, J; Keller, A J; Goldhaber-Gordon, D

2013-03-01

We report on our design of a scanning gate microscope housed in a cryogen-free dilution refrigerator with a base temperature of 15 mK. The recent increase in efficiency of pulse tube cryocoolers has made cryogen-free systems popular in recent years. However, this new style of cryostat presents challenges for performing scanning probe measurements, mainly as a result of the vibrations introduced by the cryocooler. We demonstrate scanning with root-mean-square vibrations of 0.8 nm at 3 K and 2.1 nm at 15 mK in a 1 kHz bandwidth with our design. Using Coulomb blockade thermometry on a GaAs/AlGaAs gate-defined quantum dot, we demonstrate an electron temperature of 45 mK.

Dual-Gated Active Metasurface at 1550 nm with Wide (>300°) Phase Tunability.

PubMed

Kafaie Shirmanesh, Ghazaleh; Sokhoyan, Ruzan; Pala, Ragip A; Atwater, Harry A

2018-05-09

Active metasurfaces composed of electrically reconfigurable nanoscale subwavelength antenna arrays can enable real-time control of scattered light amplitude and phase. Achievement of widely tunable phase and amplitude in chip-based active metasurfaces operating at or near 1550 nm wavelength has considerable potential for active beam steering, dynamic hologram rendition, and realization of flat optics with reconfigurable focal lengths. Previously, electrically tunable conducting oxide-based reflectarray metasurfaces have demonstrated dynamic phase control of reflected light with a maximum phase shift of 184° ( Nano Lett. 2016 , 16 , 5319 ). Here, we introduce a dual-gated reflectarray metasurface architecture that enables much wider (>300°) phase tunability. We explore light-matter interactions with dual-gated metasurface elements that incorporate two independent voltage-controlled MOS field effect channels connected in series to form a single metasurface element that enables wider phase tunability. Using indium tin oxide (ITO) as the active metasurface material and a composite hafnia/alumina gate dielectric, we demonstrate a prototype dual-gated metasurface with a continuous phase shift from 0 to 303° and a relative reflectance modulation of 89% under applied voltage bias of 6.5 V.

Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit

NASA Astrophysics Data System (ADS)

Al-Ameri, Talib; Georgiev, Vihar P.; Sadi, Toufik; Wang, Yijiao; Adamu-Lema, Fikru; Wang, Xingsheng; Amoroso, Salvatore M.; Towie, Ewan; Brown, Andrew; Asenov, Asen

2017-03-01

In this work we investigate the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future CMOS applications at the scaling limit. For the purpose of this paper, we created Si NWTs with two channel crystallographic orientations <1 1 0> and <1 0 0> and six different cross-section profiles. In the first part, we study the impact of quantum corrections on the gate capacitance and mobile charge in the channel. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic performance of the NWTs, is also investigated. The influence of the rotating of the NWTs cross-sectional geometry by 90° on charge distribution in the channel is also studied. We compare the correlation between the charge profile in the channel and cross-sectional dimension for circular transistor with four different cross-sections diameters: 5 nm, 6 nm, 7 nm and 8 nm. In the second part of this paper, we expand the computational study by including different gate lengths for some of the Si NWTs. As a result, we establish a correlation between the mobile charge distribution in the channel and the gate capacitance, drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All calculations are based on a quantum mechanical description of the mobile charge distribution in the channel. This description is based on the solution of the Schrödinger equation in NWT cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions.

Deep-submicron Graphene Field-Effect Transistors with State-of-Art fmax

PubMed Central

Lyu, Hongming; Lu, Qi; Liu, Jinbiao; Wu, Xiaoming; Zhang, Jinyu; Li, Junfeng; Niu, Jiebin; Yu, Zhiping; Wu, Huaqiang; Qian, He

2016-01-01

In order to conquer the short-channel effects that limit conventional ultra-scale semiconductor devices, two-dimensional materials, as an option of ultimate thin channels, receive wide attention. Graphene, in particular, bears great expectations because of its supreme carrier mobility and saturation velocity. However, its main disadvantage, the lack of bandgap, has not been satisfactorily solved. As a result, maximum oscillation frequency (fmax) which indicates transistors’ power amplification ability has been disappointing. Here, we present submicron field-effect transistors with specially designed low-resistance gate and excellent source/drain contact, and therefore significantly improved fmax. The fabrication was assisted by the advanced 8-inch CMOS back-end-of-line technology. A 200-nm-gate-length GFET achieves fT/fmax = 35.4/50 GHz. All GFET samples with gate lengths ranging from 200 nm to 400 nm possess fmax 31–41% higher than fT, closely resembling Si n-channel MOSFETs at comparable technology nodes. These results re-strengthen the promise of graphene field-effect transistors in next generation semiconductor electronics. PMID:27775009

Anomalous annealing of floating gate errors due to heavy ion irradiation

NASA Astrophysics Data System (ADS)

Yin, Yanan; Liu, Jie; Sun, Youmei; Hou, Mingdong; Liu, Tianqi; Ye, Bing; Ji, Qinggang; Luo, Jie; Zhao, Peixiong

2018-03-01

Using the heavy ions provided by the Heavy Ion Research Facility in Lanzhou (HIRFL), the annealing of heavy-ion induced floating gate (FG) errors in 34 nm and 25 nm NAND Flash memories has been studied. The single event upset (SEU) cross section of FG and the evolution of the errors after irradiation depending on the ion linear energy transfer (LET) values, data pattern and feature size of the device are presented. Different rates of annealing for different ion LET and different pattern are observed in 34 nm and 25 nm memories. The variation of the percentage of different error patterns in 34 nm and 25 nm memories with annealing time shows that the annealing of FG errors induced by heavy-ion in memories will mainly take place in the cells directly hit under low LET ion exposure and other cells affected by heavy ions when the ion LET is higher. The influence of Multiple Cell Upsets (MCUs) on the annealing of FG errors is analyzed. MCUs with high error multiplicity which account for the majority of the errors can induce a large percentage of annealed errors.

81. AVALON DAM Photographic copy of construction drawing c1908 ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

81. AVALON DAM - Photographic copy of construction drawing c1908 (from aperture card located at Bureau of Reclamation, Salt Lake City) UNTITLED DRAWING OF AUTOMATIC FLOOD GATES. GATE DETAILS - Carlsbad Irrigation District, Avalon Dam, On Pecos River, 4 miles North of Carlsbad, Carlsbad, Eddy County, NM

Ballistic Josephson junctions based on CVD graphene

NASA Astrophysics Data System (ADS)

Li, Tianyi; Gallop, John; Hao, Ling; Romans, Edward

2018-04-01

Josephson junctions with graphene as the weak link between superconductors have been intensely studied in recent years, with respect to both fundamental physics and potential applications. However, most of the previous work was based on mechanically exfoliated graphene, which is not compatible with wafer-scale production. To overcome this limitation, we have used graphene grown by chemical vapour deposition (CVD) as the weak link of Josephson junctions. We demonstrate that very short, wide CVD-graphene-based Josephson junctions with Nb electrodes can work without any undesirable hysteresis in their electrical characteristics from 1.5 K down to a base temperature of 320 mK, and their gate-tuneable critical current shows an ideal Fraunhofer-like interference pattern in a perpendicular magnetic field. Furthermore, for our shortest junctions (50 nm in length), we find that the normal state resistance oscillates with the gate voltage, consistent with the junctions being in the ballistic regime, a feature not previously observed in CVD-graphene-based Josephson junctions.

Polydiacetylene as an all-optical picosecond Switch

NASA Technical Reports Server (NTRS)

Abdeldayem, Hossin A.; Frazier, D. O.; Paley, M. S.; Whitaker, Ann F. (Technical Monitor)

2001-01-01

Polydiacetylene derivative of 2-methyl-4-nitroaniline (PDAMNA) shows a picosecond switching property, which illustrated a partial all-optical picosecond NAND logic gate. The switching phenomenon was demonstrated by waveguiding two collinear beams at 633 nm and 532 nm through a hollow fiber of 50 micrometers diameter, coated from inside with a thin film of PDAMNA. A Z-scan investigations of a PDAMNA thin film on quartz substrate revealed that the switching effect was attributed to an excited state absorption in the systems. The studies also showed that the polymer suffers a photo-oxidation beyond an intensity level of 2.9 x 10(exp 6) w/square cm. The photo-oxidized film has different physical properties that are different from the original film before oxidation. The life time of both excited states before and after oxidation as well as their absorption coefficients were estimated by fitting a three level system model to the experimental results.

Effects of dc bias on the kinetics and electrical properties of silicon dioxide grown in an electron cyclotron resonance plasma

NASA Astrophysics Data System (ADS)

Carl, D. A.; Hess, D. W.; Lieberman, M. A.; Nguyen, T. D.; Gronsky, R.

1991-09-01

Thin (3-300-nm) oxides were grown on single-crystal silicon substrates at temperatures from 523 to 673 K in a low-pressure electron cyclotron resonance (ECR) oxygen plasma. Oxides were grown under floating, anodic or cathodic bias conditions, although only the oxides grown under floating or anodic bias conditions are acceptable for use as gate dielectrics in metal-oxide-semiconductor technology. Oxide thickness uniformity as measured by ellipsometry decreased with increasing oxidation time for all bias conditions. Oxidation kinetics under anodic conditions can be explained by negatively charged atomic oxygen, O-, transport limited growth. Constant current anodizations yielded three regions of growth: (1) a concentration gradient dominated regime for oxides thinner than 10 nm, (2) a field dominated regime with ohmic charged oxidant transport for oxide thickness in the range of 10 nm to approximately 100 nm, and (3) a space-charge limited regime for films thicker than approximately 100 nm. The relationship between oxide thickness (xox), overall potential drop (Vox) and ion current (ji) in the space-charge limited transport region was of the form: ji ∝ V2ox/x3ox. Transmission electron microscopy analysis of 5-60-nm-thick anodized films indicated that the silicon-silicon dioxide interface was indistinguishable from that of thermal oxides grown at 1123 K. High-frequency capacitance-voltage (C-V) and ramped bias current-voltage (I-V) studies performed on 5.4-30-nm gate thickness capacitors indicated that the as-grown ECR films had high levels of fixed oxide charge (≳1011 cm-2) and interface traps (≳1012 cm-2 eV-1). The fixed charge level could be reduced to ≊4×1010 cm-2 by a 20 min polysilicon gate activation anneal at 1123 K in nitrogen; the interface trap density at mid-band gap decreased to ≊(1-2)×1011 cm-2 eV-1 after this process. The mean breakdown strength for anodic oxides grown under optimum conditions was 10.87±0.83 MV cm-1. Electrical properties of the 5.4-8-nm gates compared well with thicker films and control dry thermal oxides of similar thicknesses.

Field effect transistor with HfO2/Parylene-C bilayer hybrid gate insulator

NASA Astrophysics Data System (ADS)

Kumar, Neeraj; Kito, Ai; Inoue, Isao

2015-03-01

We have investigated the electric field control of the carrier density and the mobility at the surface of SrTiO3, a well known transition-metal oxide, in a field effect transistor (FET) geometry. We have used a Parylene-C (8 nm)/HfO2 (20 nm) double-layer gate insulator (GI), which can be a potential candidate for a solid state GI for the future Mott FETs. So far, only examples of the Mott FET used liquid electrolyte or ferroelectric oxides for the GI. However, possible electrochemical reaction at the interface causes damage to the surface of the Mott insulator. Thus, an alternative GI has been highly desired. We observed that even an ultra thin Parylene-C layer is effective for keeping the channel surface clean and free from oxygen vacancies. The 8 nm Parylene-C film has a relatively low resistance and consequentially its capacitance does not dominate the total capacitance of the Parylene-C/HfO2 GI. The breakdown gate voltage at 300 K is usually more than 10 V (~ 3.4 MV/cm). At gate voltage of 3 V the carrier density measured by the Hall effect is about 3 ×1013 cm-2, competent to cause the Mott transition. Moreover, the field effect mobility reaches in the range of 10 cm2/Vs indicating the Parylene-C passivated surface is actually very clean.

Scanning electron microscope measurement of width and shape of 10nm patterned lines using a JMONSEL-modeled library.

PubMed

Villarrubia, J S; Vladár, A E; Ming, B; Kline, R J; Sunday, D F; Chawla, J S; List, S

2015-07-01

The width and shape of 10nm to 12 nm wide lithographically patterned SiO2 lines were measured in the scanning electron microscope by fitting the measured intensity vs. position to a physics-based model in which the lines' widths and shapes are parameters. The approximately 32 nm pitch sample was patterned at Intel using a state-of-the-art pitch quartering process. Their narrow widths and asymmetrical shapes are representative of near-future generation transistor gates. These pose a challenge: the narrowness because electrons landing near one edge may scatter out of the other, so that the intensity profile at each edge becomes width-dependent, and the asymmetry because the shape requires more parameters to describe and measure. Modeling was performed by JMONSEL (Java Monte Carlo Simulation of Secondary Electrons), which produces a predicted yield vs. position for a given sample shape and composition. The simulator produces a library of predicted profiles for varying sample geometry. Shape parameter values are adjusted until interpolation of the library with those values best matches the measured image. Profiles thereby determined agreed with those determined by transmission electron microscopy and critical dimension small-angle x-ray scattering to better than 1 nm. Published by Elsevier B.V.

Direct visualization and in-depth physical study of metal filament formation in percolated high-κ dielectrics

NASA Astrophysics Data System (ADS)

Li, X.; Pey, K. L.; Bosman, M.; Liu, W. H.; Kauerauf, T.

2010-01-01

The migration of Ta atoms from a transistor gate electrode into the percolated high-κ (HK) gate dielectrics is directly shown using transmission electron microscopy analysis. A nanoscale metal filament that formed under high current injection is identified to be the physical defect responsible for the ultrafast transient breakdown (BD) of the metal-gate/high-κ (MG/HK) gate stacks. This highly conductive metal filament poses reliability concerns for MG/HK gate stacks as it significantly reduces the post-BD reliability margin of a transistor.

Planarized thick copper gate polycrystalline silicon thin film transistors for ultra-large AMOLED displays

NASA Astrophysics Data System (ADS)

Yun, Seung Jae; Lee, Yong Woo; Son, Se Wan; Byun, Chang Woo; Reddy, A. Mallikarjuna; Joo, Seung Ki

2012-08-01

A planarized thick copper (Cu) gate low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) is fabricated for ultra-large active-matrix organic light-emitting diode (AMOLED) displays. We introduce a damascene and chemical mechanical polishing process to embed a planarized Cu gate of 500 nm thickness into a trench and Si3N4/SiO2 multilayer gate insulator, to prevent the Cu gate from diffusing into the silicon (Si) layer at 550°C, and metal-induced lateral crystallization (MILC) technology to crystallize the amorphous Si layer. A poly-Si TFT with planarized thick Cu gate exhibits a field effect mobility of 5 cm2/Vs and a threshold voltage of -9 V, and a subthreshold swing (S) of 1.4 V/dec.

How small can MOSFETs get?

NASA Astrophysics Data System (ADS)

Risch, Lothar

2001-10-01

Scaling of CMOS technology made possible the key appliances of our information technology society, like the PC, mobile communication, and the internet. Reduction of feature sizes for semiconductor devices continued according to Moore's law for the last 25 years in order to achieve higher integration densities, higher speed, lower power consumption, and lower costs. But now, as we approach the sub 100 nm regime, several roadblocks have been predicted for the next generations down to 35 nm. The latest ITRS roadmap 99 describes in detail the challenges which have to be addressed for the future CMOS technology nodes, regarding lithography, metallization, power dissipation, and circuit design. Also for the MOSFET, performance degradation is a big issue. Because this is not a limitation from basic physical laws, novel architectures for MOSFETs will be needed to improve again the electrical characteristics and thus pave the way to much smaller transistors than expected in the past. 25 nm CMOS seems to be feasible using very thin silicon substrates on insulator. Further improvements down to 10 nm are very likely with two gates for the control of the charge carriers. So, it is very likely that CMOS will not end with today's roadmap at 35 nm or even before, but may continue with non bulk devices and fully depleted channels. Finally, tunnelling from source to drain will set an end to the reduction of channel length, which is estimated to be below 5 nm.

Smart Adsorbents with Photoregulated Molecular Gates for Both Selective Adsorption and Efficient Regeneration.

PubMed

Cheng, Lei; Jiang, Yao; Yan, Ni; Shan, Shu-Feng; Liu, Xiao-Qin; Sun, Lin-Bing

2016-09-07

Selective adsorption and efficient regeneration are two crucial issues for adsorption processes; unfortunately, only one of them instead of both is favored by traditional adsorbents with fixed pore orifices. Herein, we fabricated a new generation of smart adsorbents through grafting photoresponsive molecules, namely, 4-(3-triethoxysilylpropyl-ureido)azobenzene (AB-TPI), onto pore orifices of the support mesoporous silica. The azobenzene (AB) derivatives serve as the molecular gates of mesopores and are reversibly opened and closed upon light irradiation. Irradiation with visible light (450 nm) causes AB molecules to isomerize from cis to trans configuration, and the molecular gates are closed. It is easy for smaller adsorbates to enter while difficult for the larger ones, and the selective adsorption is consequently facilitated. Upon irradiation with UV light (365 nm), the AB molecules are transformed from trans to cis isomers, promoting the desorption of adsorbates due to the opened molecular gates. The present smart adsorbents can consequently benefit not only selective adsorption but also efficient desorption, which are exceedingly desirable for adsorptive separation but impossible for traditional adsorbents with fixed pore orifices.

Electrical characteristic fluctuation of 16-nm-gate high-κ/metal gate bulk FinFET devices in the presence of random interface traps

NASA Astrophysics Data System (ADS)

Hsu, Sheng-Chia; Li, Yiming

2014-11-01

In this work, we study the impact of random interface traps (RITs) at the interface of SiO x /Si on the electrical characteristic of 16-nm-gate high-κ/metal gate (HKMG) bulk fin-type field effect transistor (FinFET) devices. Under the same threshold voltage, the effects of RIT position and number on the degradation of electrical characteristics are clarified with respect to different levels of RIT density of state ( D it). The variability of the off-state current ( I off) and drain-induced barrier lowering (DIBL) will be severely affected by RITs with high D it varying from 5 × 1012 to 5 × 1013 eV-1 cm-2 owing to significant threshold voltage ( V th) fluctuation. The results of this study indicate that if the level of D it is lower than 1 × 1012 eV-1 cm-2, the normalized variability of the on-state current, I off, V th, DIBL, and subthreshold swing is within 5%.

Organization of the Optical Society of America Photonic Science Topical Meeting Series (1991). Volume 16. Conference Edition: Summaries of papers presented at the Persistent Spectral Hole-Burning: Science and Applications Topical Meeting Held in Monterey, California on 26-28 September 1991

DTIC Science & Technology

1992-05-22

Duoyuan Wang, Lingzhi Hu, Huizhu He, Jie Xie, 532 nm. (p. 122) Junyl Zhang, Academy of Sciences of China. Photon-gated persistent spectral hole...hole-burning, Duoyuan VWang, Lingzhi Hu, Huizhu He, Lizeng Zhao, Xin Mi, Yuxin Ni, Academy of Sciences, China. FE5 Marker mode structure in the primary...Xiulang, Zhang Dongxiang, Mi Xin, Nie Yuxin Institute of Physics, Academia Sinica Beijing 100080, China, Fax:(86-1)2562605 Wang Duoyuan, Hu Lingzhi , He

Physics of Gate Modulated Resonant Tunneling (RT)-FETs: Multi-barrier MOSFET for steep slope and high on-current

NASA Astrophysics Data System (ADS)

Afzalian, Aryan; Colinge, Jean-Pierre; Flandre, Denis

2011-05-01

A new concept of nanoscale MOSFET, the Gate Modulated Resonant Tunneling Transistor (RT-FET), is presented and modeled using 3D Non-Equilibrium Green's Function simulations enlightening the main physical mechanisms. Owing to the additional tunnel barriers and the related longitudinal confinement present in the device, the density of state is reduced in its off-state, while remaining comparable in its on-state, to that of a MOS transistor without barriers. The RT-FET thus features both a lower RT-limited off-current and a faster increase of the current with V G, i.e. an improved slope characteristic, and hence an improved Ion/ Ioff ratio. Such improvement of the slope can happen in subthreshold regime, and therefore lead to subthreshold slope below the kT/q limit. In addition, faster increase of current and improved slope occur above threshold and lead to high thermionic on-current and significant Ion/ Ioff ratio improvement, even with threshold voltage below 0.2 V and supply voltage V dd of a few hundreds of mV as critically needed for future technology nodes. Finally RT-FETs are intrinsically immune to source-drain tunneling and are therefore promising candidate for extending the roadmap below 10 nm.

Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

NASA Astrophysics Data System (ADS)

Kim, Young-Hee

Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is still necessary to understand what is intrinsic we can not change, or what is extrinsic one we can improve.

Improved Performance of h-BN Encapsulated Double Gate Graphene Nanomesh Field Effect Transistor for Short Channel Length

NASA Astrophysics Data System (ADS)

Tiwari, Durgesh Laxman; Sivasankaran, K.

This paper presents improved performance of Double Gate Graphene Nanomesh Field Effect Transistor (DG-GNMFET) with h-BN as substrate and gate oxide material. The DC characteristics of 0.95μm and 5nm channel length devices are studied for SiO2 and h-BN substrate and oxide material. For analyzing the ballistic behavior of electron for 5nm channel length, von Neumann boundary condition is considered near source and drain contact region. The simulated results show improved saturation current for h-BN encapsulated structure with two times higher on current value (0.375 for SiO2 and 0.621 for h-BN) as compared to SiO2 encapsulated structure. The obtained result shows h-BN to be a better substrate and oxide material for graphene electronics with improved device characteristics.

Characterization of gate recessed GaN/AlGaN/GaN high electron mobility transistors fabricated using a SiCl4/SF6 dry etch recipe

NASA Astrophysics Data System (ADS)

Green, R. T.; Luxmoore, I. J.; Lee, K. B.; Houston, P. A.; Ranalli, F.; Wang, T.; Parbrook, P. J.; Uren, M. J.; Wallis, D. J.; Martin, T.

2010-07-01

Incorporating GaN capping layers in conjunction with recessing has been identified as a means to maximize the high frequency performance of AlGaN/GaN high electron mobility transistors (HEMTs). Doping the cap heavily n-type is required in order to ensure minimal loss of carriers from the channel. Using a SiCl4/SF6 dry etch plasma recipe, 250 nm gate length HEMTs with recess lengths varying from 300 nm to 5 μm are fabricated. Heavily doped n+GaN caps enabled contact resistances of 0.3 Ω mm to be achieved. Recessing using a SiCl4/SF6 recipe does not introduce significant numbers of bulk traps. Gate recessing in conjunction with Si3N4 passivation reduces rf dispersion to negligible levels.

Highly efficient X-range AlGaN/GaN power amplifier

NASA Astrophysics Data System (ADS)

Tural'chuk, P. A.; Kirillov, V. V.; Osipov, P. E.; Vendik, I. B.; Vendik, O. G.; Parnes, M. D.

2017-09-01

The development of microwave power amplifiers (PAs) based on transistors with an AlGaN/GaN heterojunction are discussed in terms of the possible enhancement of their efficiency. The main focus is on the synthesis of the transforming circuits, which ensure the reactive load at the second- and third-harmonic frequencies and complex impedance at the fundamental frequency. This makes it possible to optimize the complex operation mode of a PA; i.e., to reduce the scattering power and enhance the efficiency. A microwave PA based on the Schottky-barrier-gate field-effect transistor with 80 electrodes based on the GaN pHEMT transistor with a gate length of 0.25 nm and a gate width of 125 nm is experimentally investigated. The amplifier has a pulse output power of 35 W and a power-added efficiency of at least 50% at a working frequency of 9 GHz.

Electro-optical logic gates based on graphene-silicon waveguides

NASA Astrophysics Data System (ADS)

Chen, Weiwei; Yang, Longzhi; Wang, Pengjun; Zhang, Yawei; Zhou, Liqiang; Yang, Tianjun; Wang, Yang; Yang, Jianyi

2016-08-01

In this paper, designs of electro-optical AND/NAND, OR/ NOR, XOR/XNOR logic gates based on cascaded silicon graphene switches and regular 2×1 multimode interference combiners are presented. Each switch consists of a Mach-Zehnder interferometer in which silicon slot waveguides embedded with graphene flakes are designed for phase shifters. High-speed switching function is achieved by applying an electrical signal to tune the Fermi levels of graphene flakes causing the variation of modal effective index. Calculation results show the crosstalk in the proposed optical switch is lower than -22.9 dB within a bandwidth from 1510 nm to 1600 nm. The designed six electro-optical logic gates with the operation speed of 10 Gbit/s have a minimum extinction ratio of 35.6 dB and a maximum insertion loss of 0.21 dB for transverse electric modes at 1.55 μm.

Self-Aligned van der Waals Heterojunction Diodes and Transistors.

PubMed

Sangwan, Vinod K; Beck, Megan E; Henning, Alex; Luo, Jiajia; Bergeron, Hadallia; Kang, Junmo; Balla, Itamar; Inbar, Hadass; Lauhon, Lincoln J; Hersam, Mark C

2018-02-14

A general self-aligned fabrication scheme is reported here for a diverse class of electronic devices based on van der Waals materials and heterojunctions. In particular, self-alignment enables the fabrication of source-gated transistors in monolayer MoS 2 with near-ideal current saturation characteristics and channel lengths down to 135 nm. Furthermore, self-alignment of van der Waals p-n heterojunction diodes achieves complete electrostatic control of both the p-type and n-type constituent semiconductors in a dual-gated geometry, resulting in gate-tunable mean and variance of antiambipolar Gaussian characteristics. Through finite-element device simulations, the operating principles of source-gated transistors and dual-gated antiambipolar devices are elucidated, thus providing design rules for additional devices that employ self-aligned geometries. For example, the versatility of this scheme is demonstrated via contact-doped MoS 2 homojunction diodes and mixed-dimensional heterojunctions based on organic semiconductors. The scalability of this approach is also shown by fabricating self-aligned short-channel transistors with subdiffraction channel lengths in the range of 150-800 nm using photolithography on large-area MoS 2 films grown by chemical vapor deposition. Overall, this self-aligned fabrication method represents an important step toward the scalable integration of van der Waals heterojunction devices into more sophisticated circuits and systems.

Large electron concentration modulation using capacitance enhancement in SrTiO{sub 3}/SmTiO{sub 3} Fin-field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Verma, Amit, E-mail: averma@cornell.edu; Nomoto, Kazuki; School of Electrical and Computer Engineering, Cornell University, Ithaca, New York 14853

2016-05-02

Solid-state modulation of 2-dimensional electron gases (2DEGs) with extreme (∼3.3 × 10{sup 14 }cm{sup −2}) densities corresponding to 1/2 electron per interface unit cell at complex oxide heterointerfaces (such as SrTiO{sub 3}/GdTiO{sub 3} or SrTiO{sub 3}/SmTiO{sub 3}) is challenging because it requires enormous gate capacitances. One way to achieve large gate capacitances is by geometrical capacitance enhancement in fin structures. In this work, we fabricate both Au-gated planar field effect transistors (FETs) and Fin-FETs with varying fin-widths on 60 nm SrTiO{sub 3}/5 nm SmTiO{sub 3} thin films grown by hybrid molecular beam epitaxy. We find that the FinFETs exhibit higher gate capacitance comparedmore » to planar FETs. By scaling down the SrTiO{sub 3}/SmTiO{sub 3} fin widths, we demonstrate further gate capacitance enhancement, almost twice compared to the planar FETs. In the FinFETs with narrowest fin-widths, we demonstrate a record 2DEG electron concentration modulation of ∼2.4 × 10{sup 14 }cm{sup −2}.« less

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

NASA Astrophysics Data System (ADS)

Jovanović, B.; Brum, R. M.; Torres, L.

2014-04-01

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

Design Optimization of Ge/GaAs-Based Heterojunction Gate-All-Around (GAA) Arch-Shaped Tunneling Field-Effect Transistor (A-TFET).

PubMed

Seo, Jae Hwa; Yoon, Young Jun; Kang, In Man

2018-09-01

The Ge/GaAs-based heterojunction gate-all-around (GAA) arch-shaped tunneling field-effect transistor (A-TFET) have been designed and optimized using technology computer-aided design (TCAD) simulations. In our previous work, the silicon-based A-TFET was designed and demonstrated. However, to progress the electrical characteristics of A-TFET, the III-V compound heterojunction structures which has enhanced electrical properties must be adopted. Thus, the germanium with gallium arsenide (Ge/GaAs) is considered as key materials of A-TFET. The proposed device has a Ge-based p-doped source, GaAs-based i-doped channel and GaAs-based n-doped drain. Due to the critical issues of device performances, the doping concentration of source and channel region (Dsource, Dchannel), height of source region (Hsource) and epitaxially grown thickness of channel (tepi) was selected as design optimization variables of Ge/GaAs-based GAA A-TFET. The DC characteristics such as on-state current (ion), off-state current (ioff), subthreshold-swing (S) were of extracted and analyzed. Finally, the proposed device has a gate length (LG) of 90 nm, Dsource 5 × 1019 cm-3, Dchannel of 1018 cm-3, tepi of 4 nm, Hsource of 90 nm, R of 10 nm and demonstrate an ion of 2 mA/μm, S of 12.9 mV/dec.

Observation of ambipolar switching in a silver nanoparticle single-electron transistor with multiple molecular floating gates

NASA Astrophysics Data System (ADS)

Yamamoto, Makoto; Shinohara, Shuhei; Tamada, Kaoru; Ishii, Hisao; Noguchi, Yutaka

2016-03-01

Ambipolar switching behavior was observed in a silver nanoparticle (AgNP)-based single-electron transistor (SET) with tetra-tert-butyl copper phthalocyanine (ttbCuPc) as a molecular floating gate. Depending on the wavelength of the incident light, the stability diagram shifted to the negative and positive directions along the gate voltage axis. These results were explained by the photoinduced charging of ttbCuPc molecules in the vicinity of AgNPs. Moreover, multiple device states were induced by the light irradiation at a wavelength of 600 nm, suggesting that multiple ttbCuPc molecules individually worked as a floating gate.

Photo-electronic current transport in back-gated graphene transistor

NASA Astrophysics Data System (ADS)

Srivastava, Ashok; Chen, Xinlu; Pradhan, Aswini K.

2017-04-01

In this work, we have studied photo-electronic current transport in a back-gated graphene field-effect transistor. Under the light illumination, band bending at the metal/graphene interface develops a built-in potential which generates photonic current at varying back-gate biases. A typical MOSFET type back-gated transistor structure uses a monolayer graphene as the channel layer formed over the silicon dioxide/silicon substrate. It is shown that the photo-electronic current consists of current contributions from photovoltaic, photo-thermoelectric and photo-bolometric effects. A maximum external responsivity close to 0.0009A/W is achieved at 30μW laser power source and 633nm wavelength.

Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

NASA Astrophysics Data System (ADS)

Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

2018-04-01

In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

Electro-optic modulator based gate transient suppression for sine-wave gated InGaAs/InP single photon avalanche photodiode

NASA Astrophysics Data System (ADS)

Zhang, Yixin; Zhang, Xuping; Shi, Yuanlei; Ying, Zhoufeng; Wang, Shun

2014-06-01

Capacitive gate transient noise has been problematic for the high-speed single photon avalanche photodiode (SPAD), especially when the operating frequency extends to the gigahertz level. We proposed an electro-optic modulator based gate transient noise suppression method for sine-wave gated InGaAs/InP SPAD. With the modulator, gate transient is up-converted to its higher-order harmonics that can be easily removed by low pass filtering. The proposed method enables online tuning of the operating rate without modification of the hardware setup. At 250 K, detection efficiency of 14.7% was obtained with 4.8×10-6 per gate dark count and 3.6% after-pulse probabilities for 1550-nm optical signal under 1-GHz gating frequency. Experimental results have shown that the performance of the detector can be maintained within a designated frequency range from 0.97 to 1.03 GHz, which is quite suitable for practical high-speed SPAD applications operated around the gigahertz level.

High fluence swift heavy ion structure modification of the SiO2/Si interface and gate insulator in 65 nm MOSFETs

NASA Astrophysics Data System (ADS)

Ma, Yao; Gao, Bo; Gong, Min; Willis, Maureen; Yang, Zhimei; Guan, Mingyue; Li, Yun

2017-04-01

In this work, a study of the structure modification, induced by high fluence swift heavy ion radiation, of the SiO2/Si structures and gate oxide interface in commercial 65 nm MOSFETs is performed. A key and novel point in this study is the specific use of the transmission electron microscopy (TEM) technique instead of the conventional atomic force microscope (AFM) or scanning electron microscope (SEM) techniques which are typically performed following the chemical etching of the sample to observe the changes in the structure. Using this method we show that after radiation, the appearance of a clearly visible thin layer between the SiO2 and Si is observed presenting as a variation in the TEM intensity at the interface of the two materials. Through measuring the EDX line scans we reveal that the Si:O ratio changed and that this change can be attributed to the migration of the Si towards interface after the Si-O bond is destroyed by the swift heavy ions. For the 65 nm MOSFET sample, the silicon substrate, the SiON insulator and the poly-silicon gate interfaces become blurred under the same irradiation conditions.

EduGATE - basic examples for educative purpose using the GATE simulation platform.

PubMed

Pietrzyk, Uwe; Zakhnini, Abdelhamid; Axer, Markus; Sauerzapf, Sophie; Benoit, Didier; Gaens, Michaela

2013-02-01

EduGATE is a collection of basic examples to introduce students to the fundamental physical aspects of medical imaging devices. It is based on the GATE platform, which has received a wide acceptance in the field of simulating medical imaging devices including SPECT, PET, CT and also applications in radiation therapy. GATE can be configured by commands, which are, for the sake of simplicity, listed in a collection of one or more macro files to set up phantoms, multiple types of sources, detection device, and acquisition parameters. The aim of the EduGATE is to use all these helpful features of GATE to provide insights into the physics of medical imaging by means of a collection of very basic and simple GATE macros in connection with analysis programs based on ROOT, a framework for data processing. A graphical user interface to define a configuration is also included. Copyright © 2012. Published by Elsevier GmbH.

Realization of quantum gates with multiple control qubits or multiple target qubits in a cavity

NASA Astrophysics Data System (ADS)

Waseem, Muhammad; Irfan, Muhammad; Qamar, Shahid

2015-06-01

We propose a scheme to realize a three-qubit controlled phase gate and a multi-qubit controlled NOT gate of one qubit simultaneously controlling n-target qubits with a four-level quantum system in a cavity. The implementation time for multi-qubit controlled NOT gate is independent of the number of qubit. Three-qubit phase gate is generalized to n-qubit phase gate with multiple control qubits. The number of steps reduces linearly as compared to conventional gate decomposition method. Our scheme can be applied to various types of physical systems such as superconducting qubits coupled to a resonator and trapped atoms in a cavity. Our scheme does not require adjustment of level spacing during the gate implementation. We also show the implementation of Deutsch-Joza algorithm. Finally, we discuss the imperfections due to cavity decay and the possibility of physical implementation of our scheme.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-01

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

PubMed

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-17

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Fabrication of Ta2O5/GeNx gate insulator stack for Ge metal-insulator-semiconductor structures by electron-cyclotron-resonance plasma nitridation and sputtering deposition techniques

NASA Astrophysics Data System (ADS)

Otani, Yohei; Itayama, Yasuhiro; Tanaka, Takuo; Fukuda, Yukio; Toyota, Hiroshi; Ono, Toshiro; Mitsui, Minoru; Nakagawa, Kiyokazu

2007-04-01

The authors have fabricated germanium (Ge) metal-insulator-semiconductor (MIS) structures with a 7-nm-thick tantalum pentaoxide (Ta2O5)/2-nm-thick germanium nitride (GeNx) gate insulator stack by electron-cyclotron-resonance plasma nitridation and sputtering deposition. They found that pure GeNx ultrathin layers can be formed by the direct plasma nitridation of the Ge surface without substrate heating. X-ray photoelectron spectroscopy revealed no oxidation of the GeNx layer after the Ta2O5 sputtering deposition. The fabricated MIS capacitor with a capacitance equivalent thickness of 4.3nm showed excellent leakage current characteristics. The interface trap density obtained by the modified conductance method was 4×1011cm-2eV-1 at the midgap.

88. AVALON DAM Photographic copy of construction drawing dated ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

88. AVALON DAM - Photographic copy of construction drawing dated February 9, 1912 (from Record Group 115, Box 17, Denver Branch of the National Archives, Denver) METHOD OF CLOSING UP OLD GATE OPENINGS IN SPILLWAY AND ARRANGEMENT OF TURBINES, OPERATING CYLINDER GATES - Carlsbad Irrigation District, Avalon Dam, On Pecos River, 4 miles North of Carlsbad, Carlsbad, Eddy County, NM

AlGaN/GaN-HEMTs with a breakdown voltage higher than 100 V and maximum oscillation frequency f{sub max} as high as 100 GHz

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mokerov, V. G., E-mail: vgmokerov@yandex.ru; Kuznetsov, A. L.; Fedorov, Yu. V.

2009-04-15

The N-Al{sub 0.27}Ga{sub 0.73}N/GaN High Electron Mobility Transistors (HEMTs) with different gate lengths L{sub g} (ranging from 170 nm to 0.5 {mu}m) and gate widths W{sub s} (ranging from 100 to 1200 {mu}m) have been studied. The S parameters have been measured; these parameters have been used to determine the current-gain cutoff frequency f{sub t}, the maximum oscillation frequency f{sub max}, and the power gain MSG/MAG and Mason's coefficients were investigated in the frequency range from 10 MHz to 67 GHz in relation to the gate length and gate width. It was found that the frequencies f{sub t} and f{submore » max} attain their maximum values of f{sub t} = 48 GHz and f{sub max} = 100 GHz at L{sub g} = 170 nm and W{sub g} = 100 {mu}m. The optimum values of W{sub g} and output power P out of the basic transistors have been determined for different frequencies of operation. It has also been demonstrated that the 170 nm Al{sub 0.27}Ga{sub 0.73}N/GaN HEMT technology provides both good frequency characteristics and high breakdown voltages and is very promising for high-frequency applications (up to 40 GHz)« less

Designing hybrid gate dielectric for fully printing high-performance carbon nanotube thin film transistors

NASA Astrophysics Data System (ADS)

Li, Qian; Li, Shilong; Yang, Dehua; Su, Wei; Wang, Yanchun; Zhou, Weiya; Liu, Huaping; Xie, Sishen

2017-10-01

The electrical characteristics of carbon nanotube (CNT) thin-film transistors (TFTs) strongly depend on the properties of the gate dielectric that is in direct contact with the semiconducting CNT channel materials. Here, we systematically investigated the dielectric effects on the electrical characteristics of fully printed semiconducting CNT-TFTs by introducing the organic dielectrics of poly(methyl methacrylate) (PMMA) and octadecyltrichlorosilane (OTS) to modify SiO2 dielectric. The results showed that the organic-modified SiO2 dielectric formed a favorable interface for the efficient charge transport in s-SWCNT-TFTs. Compared to single-layer SiO2 dielectric, the use of organic-inorganic hybrid bilayer dielectrics dramatically improved the performances of SWCNT-TFTs such as mobility, threshold voltage, hysteresis and on/off ratio due to the suppress of charge scattering, gate leakage current and charge trapping. The transport mechanism is related that the dielectric with few charge trapping provided efficient percolation pathways for charge carriers, while reduced the charge scattering. High density of charge traps which could directly act as physical transport barriers and significantly restrict the charge carrier transport and, thus, result in decreased mobile carriers and low device performance. Moreover, the gate leakage phenomenon is caused by conduction through charge traps. So, as a component of TFTs, the gate dielectric is of crucial importance to the manufacture of high quality TFTs from the aspects of affecting the gate leakage current and device operation voltage, as well as the charge carrier transport. Interestingly, the OTS-modified SiO2 allows to directly print horizontally aligned CNT film, and the corresponding devices exhibited a higher mobility than that of the devices with the hybrid PMMA/SiO2 dielectric although the thickness of OTS layer is only ˜2.5 nm. Our present result may provide key guidance for the further development of printed nanomaterial electronics.

On the physical operation and optimization of the p-GaN gate in normally-off GaN HEMT devices

NASA Astrophysics Data System (ADS)

Efthymiou, L.; Longobardi, G.; Camuso, G.; Chien, T.; Chen, M.; Udrea, F.

2017-03-01

In this study, an investigation is undertaken to determine the effect of gate design parameters on the on-state characteristics (threshold voltage and gate turn-on voltage) of pGaN/AlGaN/GaN high electron mobility transistors (HEMTs). Design parameters considered are pGaN doping and gate metal work function. The analysis considers the effects of variations on these parameters using a TCAD model matched with experimental results. A better understanding of the underlying physics governing the operation of these devices is achieved with a view to enable better optimization of such gate designs.

Towards a portable Raman spectrometer using a concave grating and a time-gated CMOS SPAD.

PubMed

Li, Zhiyun; Deen, M Jamal

2014-07-28

A low-cost, compact Raman spectrometer suitable for the on-line water monitoring applications is explored. A custom-designed concave grating for wavelength selection was fabricated and tested. The detection of the Raman signal is accomplished with a time-gated single photon avalanche diode (TG-SPAD). A fixed gate window of 3.5ns is designed and applied to the TG-SPAD. The temporal resolution of the SPAD was ~60ps when tested with a 7ps, 532nm solid-state laser. To test the efficiency of the gating in fluorescence signal suppression, different detection windows (3ns-0.25ns) within the 3.5ns gate window are used to measure the Raman spectra of Rhodamine B. Strong Raman peaks are resolved with this low-cost system.

Pulse oximeter using a gain-modulated avalanche photodiode operated in a pseudo lock-in light detection mode

NASA Astrophysics Data System (ADS)

Miyata, Tsuyoshi; Iwata, Tetsuo; Araki, Tsutomu

2006-01-01

We propose a reflection-type pulse oximeter, which employs two pairs of a light-emitting diode (LED) and a gated avalanche photodiode (APD). One LED is a red one with an emission wavelength λ = 635 nm and the other is a near-infrared one with that λ = 945 nm, which are both driven with a pulse mode at a frequency f (=10 kHz). Superposition of a transistor-transistor-logic (TTL) gate pulse on a direct-current (dc) bias, which is set so as not exceeding the breakdown voltage of each APD, makes the APD work in a gain-enhanced operation mode. Each APD is gated at a frequency 2f (=20 kHz) and its output signal is fed into a laboratory-made lock-in amplifier that works in synchronous with the pulse modulation signal of each LED at a frequency f (=10 kHz). A combination of the gated APD and the lock-in like signal detection scheme is useful for the reflection-type pulse oximeter thanks to the capability of detecting a weak signal against a large background (BG) light.

Photon-triggered nanowire transistors

NASA Astrophysics Data System (ADS)

Kim, Jungkil; Lee, Hoo-Cheol; Kim, Kyoung-Ho; Hwang, Min-Soo; Park, Jin-Sung; Lee, Jung Min; So, Jae-Pil; Choi, Jae-Hyuck; Kwon, Soon-Hong; Barrelet, Carl J.; Park, Hong-Gyu

2017-10-01

Photon-triggered electronic circuits have been a long-standing goal of photonics. Recent demonstrations include either all-optical transistors in which photons control other photons or phototransistors with the gate response tuned or enhanced by photons. However, only a few studies report on devices in which electronic currents are optically switched and amplified without an electrical gate. Here we show photon-triggered nanowire (NW) transistors, photon-triggered NW logic gates and a single NW photodetection system. NWs are synthesized with long crystalline silicon (CSi) segments connected by short porous silicon (PSi) segments. In a fabricated device, the electrical contacts on both ends of the NW are connected to a single PSi segment in the middle. Exposing the PSi segment to light triggers a current in the NW with a high on/off ratio of >8 × 106. A device that contains two PSi segments along the NW can be triggered using two independent optical input signals. Using localized pump lasers, we demonstrate photon-triggered logic gates including AND, OR and NAND gates. A photon-triggered NW transistor of diameter 25 nm with a single 100 nm PSi segment requires less than 300 pW of power. Furthermore, we take advantage of the high photosensitivity and fabricate a submicrometre-resolution photodetection system. Photon-triggered transistors offer a new venue towards multifunctional device applications such as programmable logic elements and ultrasensitive photodetectors.

Photon-triggered nanowire transistors.

PubMed

Kim, Jungkil; Lee, Hoo-Cheol; Kim, Kyoung-Ho; Hwang, Min-Soo; Park, Jin-Sung; Lee, Jung Min; So, Jae-Pil; Choi, Jae-Hyuck; Kwon, Soon-Hong; Barrelet, Carl J; Park, Hong-Gyu

2017-10-01

Photon-triggered electronic circuits have been a long-standing goal of photonics. Recent demonstrations include either all-optical transistors in which photons control other photons or phototransistors with the gate response tuned or enhanced by photons. However, only a few studies report on devices in which electronic currents are optically switched and amplified without an electrical gate. Here we show photon-triggered nanowire (NW) transistors, photon-triggered NW logic gates and a single NW photodetection system. NWs are synthesized with long crystalline silicon (CSi) segments connected by short porous silicon (PSi) segments. In a fabricated device, the electrical contacts on both ends of the NW are connected to a single PSi segment in the middle. Exposing the PSi segment to light triggers a current in the NW with a high on/off ratio of >8 × 10 6 . A device that contains two PSi segments along the NW can be triggered using two independent optical input signals. Using localized pump lasers, we demonstrate photon-triggered logic gates including AND, OR and NAND gates. A photon-triggered NW transistor of diameter 25 nm with a single 100 nm PSi segment requires less than 300 pW of power. Furthermore, we take advantage of the high photosensitivity and fabricate a submicrometre-resolution photodetection system. Photon-triggered transistors offer a new venue towards multifunctional device applications such as programmable logic elements and ultrasensitive photodetectors.

Overcoming the drawback of lower sense margin in tunnel FET based dynamic memory along with enhanced charge retention and scalability

NASA Astrophysics Data System (ADS)

Navlakha, Nupur; Kranti, Abhinav

2017-11-01

The work reports on the use of a planar tri-gate tunnel field effect transistor (TFET) to operate as dynamic memory at 85 °C with an enhanced sense margin (SM). Two symmetric gates (G1) aligned to the source at a partial region of intrinsic film result into better electrostatic control that regulates the read mechanism based on band-to-band tunneling, while the other gate (G2), positioned adjacent to the first front gate is responsible for charge storage and sustenance. The proposed architecture results in an enhanced SM of ˜1.2 μA μm-1 along with a longer retention time (RT) of ˜1.8 s at 85 °C, for a total length of 600 nm. The double gate architecture towards the source increases the tunneling current and also reduces short channel effects, enhancing SM and scalability, thereby overcoming the critical bottleneck faced by TFET based dynamic memories. The work also discusses the impact of overlap/underlap and interface charges on the performance of TFET based dynamic memory. Insights into device operation demonstrate that the choice of appropriate architecture and biases not only limit the trade-off between SM and RT, but also result in improved scalability with drain voltage and total length being scaled down to 0.8 V and 115 nm, respectively.

High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

PubMed

Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

2018-04-18

A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

3-D Observation of dopant distribution at NAND flash memory floating gate using Atom probe tomography

NASA Astrophysics Data System (ADS)

Lee, Ji-hyun; Chae, Byeong-Kyu; Kim, Joong-Jeong; Lee, Sun Young; Park, Chan Gyung

2015-01-01

Dopant control becomes more difficult and critical as silicon devices become smaller. We observed the dopant distribution in a thermally annealed polysilicon gate using Transmission Electron Microscopy (TEM) and Atom probe tomography (APT). Phosphorus was doped at the silicon-nitride-diffusion-barrier-layer-covered polycrystalline silicon gate. Carbon also incorporated at the gate for the enhancement of operation uniformity. The impurity distribution was observed using atom probe tomography. The carbon atoms had segregated at grain boundaries and suppressed silicon grain growth. Phosphorus atoms, on the other hand, tended to pile-up at the interface. A 1-nm-thick diffusion barrier effectively blocked P atom out-diffusion. [Figure not available: see fulltext.

Quasi-free-standing bilayer epitaxial graphene field-effect transistors on 4H-SiC (0001) substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yu, C.; Li, J.; Song, X. B.

2016-01-04

Quasi-free-standing epitaxial graphene grown on wide band gap semiconductor SiC demonstrates high carrier mobility and good material uniformity, which make it promising for graphene-based electronic devices. In this work, quasi-free-standing bilayer epitaxial graphene is prepared and its transistors with gate lengths of 100 nm and 200 nm are fabricated and characterized. The 100 nm gate length graphene transistor shows improved DC and RF performances including a maximum current density I{sub ds} of 4.2 A/mm, and a peak transconductance g{sub m} of 2880 mS/mm. Intrinsic current-gain cutoff frequency f{sub T} of 407 GHz is obtained. The exciting DC and RF performances obtained in the quasi-free-standingmore » bilayer epitaxial graphene transistor show the great application potential of this material system.« less

Photo-induced persistent inversion of germanium in a 200-nm-deep surface region.

PubMed

Prokscha, T; Chow, K H; Stilp, E; Suter, A; Luetkens, H; Morenzoni, E; Nieuwenhuys, G J; Salman, Z; Scheuermann, R

2013-01-01

The controlled manipulation of the charge carrier concentration in nanometer thin layers is the basis of current semiconductor technology and of fundamental importance for device applications. Here we show that it is possible to induce a persistent inversion from n- to p-type in a 200-nm-thick surface layer of a germanium wafer by illumination with white and blue light. We induce the inversion with a half-life of ~12 hours at a temperature of 220 K which disappears above 280 K. The photo-induced inversion is absent for a sample with a 20-nm-thick gold capping layer providing a Schottky barrier at the interface. This indicates that charge accumulation at the surface is essential to explain the observed inversion. The contactless change of carrier concentration is potentially interesting for device applications in opto-electronics where the gate electrode and gate oxide could be replaced by the semiconductor surface.

BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

NASA Astrophysics Data System (ADS)

Galy, Philippe; Athanasiou, S.; Cristoloveanu, S.

2016-01-01

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

Ion transport by gating voltage to nanopores produced via metal-assisted chemical etching method

NASA Astrophysics Data System (ADS)

Van Toan, Nguyen; Inomata, Naoki; Toda, Masaya; Ono, Takahito

2018-05-01

In this work, we report a simple and low-cost way to create nanopores that can be employed for various applications in nanofluidics. Nano sized Ag particles in the range from 1 to 20 nm are formed on a silicon substrate with a de-wetting method. Then the silicon nanopores with an approximate 15 nm average diameter and 200 μm height are successfully produced by the metal-assisted chemical etching method. In addition, electrically driven ion transport in the nanopores is demonstrated for nanofluidic applications. Ion transport through the nanopores is observed and could be controlled by an application of a gating voltage to the nanopores.

Two-color detection with charge sensitive infrared phototransistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Sunmi, E-mail: kimsunmi@iis.u-tokyo.ac.jp; Kajihara, Yusuke; Komiyama, Susumu

2015-11-02

Highly sensitive two-color detection is demonstrated at wavelengths of 9 μm and 14.5 μm by using a charge sensitive infrared phototransistor fabricated in a triple GaAs/AlGaAs quantum well (QW) crystal. Two differently thick QWs (7 nm- and 9 nm-thicknesses) serve as photosensitive floating gates for the respective wavelengths via intersubband excitation: The excitation in the QWs is sensed by a third QW, which works as a conducting source-drain channel in the photosensitive transistor. The two spectral bands of detection are shown to be controlled by front-gate biasing, providing a hint for implementing voltage tunable ultra-highly sensitive detectors.

Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high-κ oxide/tungsten nitride gate stacks

NASA Astrophysics Data System (ADS)

Kim, Kyoung H.; Gordon, Roy G.; Ritenour, Andrew; Antoniadis, Dimitri A.

2007-05-01

Atomic layer deposition (ALD) was used to deposit passivating interfacial nitride layers between Ge and high-κ oxides. High-κ oxides on Ge surfaces passivated by ultrathin (1-2nm) ALD Hf3N4 or AlN layers exhibited well-behaved C-V characteristics with an equivalent oxide thickness as low as 0.8nm, no significant flatband voltage shifts, and midgap density of interface states values of 2×1012cm-1eV-1. Functional n-channel and p-channel Ge field effect transistors with nitride interlayer/high-κ oxide/metal gate stacks are demonstrated.

Ultra-small, self-holding, optical gate switch using Ge2Sb2Te5 with a multi-mode Si waveguide.

PubMed

Tanaka, Daiki; Shoji, Yuya; Kuwahara, Masashi; Wang, Xiaomin; Kintaka, Kenji; Kawashima, Hitoshi; Toyosaki, Tatsuya; Ikuma, Yuichiro; Tsuda, Hiroyuki

2012-04-23

We report a multi-mode interference-based optical gate switch using a Ge(2)Sb(2)Te(5) thin film with a diameter of only 1 µm. The switching operation was demonstrated by laser pulse irradiation. This switch had a very wide operating wavelength range of 100 nm at around 1575 nm, with an average extinction ratio of 12.6 dB. Repetitive switching over 2,000 irradiation cycles was also successfully demonstrated. In addition, self-holding characteristics were confirmed by observing the dynamic responses, and the rise and fall times were 130 ns and 400 ns, respectively. © 2012 Optical Society of America

Ion transport by gating voltage to nanopores produced via metal-assisted chemical etching method.

PubMed

Van Toan, Nguyen; Inomata, Naoki; Toda, Masaya; Ono, Takahito

2018-05-11

In this work, we report a simple and low-cost way to create nanopores that can be employed for various applications in nanofluidics. Nano sized Ag particles in the range from 1 to 20 nm are formed on a silicon substrate with a de-wetting method. Then the silicon nanopores with an approximate 15 nm average diameter and 200 μm height are successfully produced by the metal-assisted chemical etching method. In addition, electrically driven ion transport in the nanopores is demonstrated for nanofluidic applications. Ion transport through the nanopores is observed and could be controlled by an application of a gating voltage to the nanopores.

Selective area deposited n-Al0.5Ga0.5N channel field effect transistors with high solar-blind ultraviolet photo-responsivity

NASA Astrophysics Data System (ADS)

Muhtadi, S.; Hwang, S.; Coleman, A.; Asif, F.; Lunev, A.; Chandrashekhar, M. V. S.; Khan, A.

2017-04-01

We report on AlGaN field effect transistors over AlN/sapphire templates with selective area grown n-Al0.5Ga0.5N channel layers for which a field-effect mobility of 55 cm2/V-sec was measured. Using a pulsed plasma enhanced chemical vapor deposition deposited 100 A thick SiO2 layer as the gate-insulator, the gate-leakage currents were reduced by three orders of magnitude. These devices with or without gate insulators are excellent solar-blind ultraviolet detectors, and they can be operated either in the photoconductive or the photo-voltaic modes. In the photo-conductive mode, gain arising from hole-trapping in the depletion region leads to steady-state photoresponsivity as high as 1.2 × 106A/W at 254 nm, which drops sharply below 290 nm. A hole-trapping limited detector response time of 34 ms, fast enough for real-time flame-detection and imaging applications, was estimated.

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

NASA Astrophysics Data System (ADS)

Ishii, Yuichiro; Tanaka, Miki; Yabuuchi, Makoto; Sawada, Yohei; Tanaka, Shinji; Nii, Koji; Lu, Tien Yu; Huang, Chun Hsien; Sian Chen, Shou; Tse Kuo, Yu; Lung, Ching Cheng; Cheng, Osbert

2018-04-01

We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (I read) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (V min) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

An Ultrathin Single Crystalline Relaxor Ferroelectric Integrated on a High Mobility Semiconductor.

PubMed

Moghadam, Reza M; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar; Grimley, Everett D; Bowden, Mark; Ong, Phuong-Vu; Chambers, Scott A; Lebeau, James M; Hong, Xia; Sushko, Peter V; Ngai, Joseph H

2017-10-11

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, the integration of gate materials that enable nonvolatile or hysteretic functionality in field-effect transistors could lead to device technologies that consume less power or allow for novel modalities in computing. Here we present electrical characterization of ultrathin single crystalline SrZr x Ti 1-x O 3 (x = 0.7) films epitaxially grown on a high mobility semiconductor, Ge. Epitaxial films of SrZr x Ti 1-x O 3 exhibit relaxor behavior, characterized by a hysteretic polarization that can modulate the surface potential of Ge. We find that gate layers as thin as 5 nm corresponding to an equivalent-oxide thickness of just 1.0 nm exhibit a ∼2 V hysteretic window in the capacitance-voltage characteristics. The development of hysteretic metal-oxide-semiconductor capacitors with nanoscale gate thicknesses opens new vistas for nanoelectronic devices.

Influence of 2D electrostatic effects on the high-frequency noise behavior of sub-100-nm scaled MOSFETs

NASA Astrophysics Data System (ADS)

Rengel, Raul; Pardo, Daniel; Martin, Maria J.

2004-05-01

In this work, we have performed an investigation of the consequences of dowscaling the bulk MOSFET beyond the 100 nm range by means of a particle-based Monte Carlo simulator. Taking a 250 nm gate-length ideal structure as the starting point, the constant field scaling rules (also known as "classical" scaling) are considered and the high-frequency dynamic and noise performance of transistors with 130 nm, 90 nm and 60 nm gate-lengths are studied in depth. The analysis of internal quantities such as electric fields, velocity and energy of carriers or conduction band profiles shows the increasing importance of electrostatic two-dimensional effects due to the proximity of source and drain regions even when the most ideal bias conditions are imposed. As a consequence, a loss of the transistor action for the smallest MOSFET and the degradation of the most important high-frequency figures of merit is observed. Whereas the comparative values of intrinsic noise sources (SID, SIG) are improved when reducing the dimensions and the bias voltages, the poor dynamic performance yields an overall worse noise behaviour than expected (especially for Rn and Gass), limiting at the same time the useful bias ranges and conditions for a proper low-noise configuration.

Hysteresis-Free Carbon Nanotube Field-Effect Transistors.

PubMed

Park, Rebecca S; Hills, Gage; Sohn, Joon; Mitra, Subhasish; Shulaker, Max M; Wong, H-S Philip

2017-05-23

While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As hysteresis is caused by traps surrounding the CNTs, previous works have shown that clean interfaces that are free of traps are important to minimize hysteresis. Our previous findings on the sources and physics of hysteresis in CNFETs enabled us to understand the influence of gate dielectric scaling on hysteresis. To begin with, we validate through simulations how scaling the gate dielectric thickness results in greater-than-expected benefits in reducing hysteresis. Leveraging this insight, we experimentally demonstrate reducing hysteresis to <0.5% of the gate-source voltage sweep range using a very large-scale integration compatible and solid-state technology, simply by fabricating CNFETs with a thin effective oxide thickness of 1.6 nm. However, even with negligible hysteresis, large subthreshold swing is still observed in the CNFETs with multiple CNTs per transistor. We show that the cause of large subthreshold swing is due to threshold voltage variation between individual CNTs. We also show that the source of this threshold voltage variation is not explained solely by variations in CNT diameters (as is often ascribed). Rather, other factors unrelated to the CNTs themselves (i.e., process variations, random fixed charges at interfaces) are a significant factor in CNT threshold voltage variations and thus need to be further improved.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seo, Jooyeok; Lee, Chulyeon; Han, Hyemi

We report a tactile touch sensor based on a planar liquid crystal-gated-organic field-effect transistor (LC-g-OFET) structure. The LC-g-OFET touch sensors were fabricated by forming the 10 μm thick LC layer (4-cyano-4{sup ′}-pentylbiphenyl - 5CB) on top of the 50 nm thick channel layer (poly(3-hexylthiophene) - P3HT) that is coated on the in-plane aligned drain/source/gate electrodes (indium-tin oxide - ITO). As an external physical stimulation to examine the tactile touch performance, a weak nitrogen flow (83.3 μl/s) was employed to stimulate the LC layer of the touch device. The LC-g-OFET device exhibited p-type transistor characteristics with a hole mobility of 1.5more » cm{sup 2}/Vs, but no sensing current by the nitrogen flow touch was measured at sufficiently high drain (V{sub D}) and gate (V{sub G}) voltages. However, a clear sensing current signal was detected at lower voltages, which was quite sensitive to the combination of V{sub D} and V{sub G}. The best voltage combination was V{sub D} = −0.2 V and V{sub G} = −1 V for the highest ratio of signal currents to base currents (i.e., signal-to-noise ratio). The change in the LC alignment upon the nitrogen flow touch was assigned as the mechanism for the present LC-g-OFET touch sensors.« less

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE PAGES

King, M. P.; Wu, X.; Eller, Manfred; ...

2016-12-07

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

The flash memory battle: How low can we go?

NASA Astrophysics Data System (ADS)

van Setten, Eelco; Wismans, Onno; Grim, Kees; Finders, Jo; Dusa, Mircea; Birkner, Robert; Richter, Rigo; Scherübl, Thomas

2008-03-01

With the introduction of the TWINSCAN XT:1900Gi the limit of the water based hyper-NA immersion lithography has been reached in terms of resolution. With a numerical aperture of 1.35 a single expose resolution of 36.5nm half pitch has been demonstrated. However the practical resolution limit in production will be closer to 40nm half pitch, without having to go to double patterning alike strategies. In the relentless Flash memory market the performance of the exposure tool is stretched to the limit for a competitive advantage and cost-effective product. In this paper we will present the results of an experimental study of the resolution limit of the NAND-Flash Memory Gate layer for a production-worthy process on the TWINSCAN XT:1900Gi. The entire gate layer will be qualified in terms of full wafer CD uniformity, aberration sensitivities for the different wordlines and feature-center placement errors for 38, 39, 40 and 43nm half pitch design rule. In this study we will also compare the performance of a binary intensity mask to a 6% attenuated phase shift mask and look at strategies to maximize Depth of Focus, and to desensitize the gate layer for lens aberrations and placement errors. The mask is one of the dominant contributors to the CD uniformity budget of the flash gate layer. Therefore the wafer measurements are compared to aerial image measurements of the mask using AIMSTM 45-193i to separate the mask contribution from the scanner contribution to the final imaging performance.

Analysis of TID process, geometry, and bias condition dependence in 14-nm FinFETs and implications for RF and SRAM performance

DOE Office of Scientific and Technical Information (OSTI.GOV)

King, M. P.; Wu, X.; Eller, Manfred

Here, total ionizing dose results are provided, showing the effects of different threshold adjust implant processes and irradiation bias conditions of 14-nm FinFETs. Minimal radiation-induced threshold voltage shift across a variety of transistor types is observed. Off-state leakage current of nMOSFET transistors exhibits a strong gate bias dependence, indicating electrostatic gate control of the sub-fin region and the corresponding parasitic conduction path are the largest concern for radiation hardness in FinFET technology. The high-Vth transistors exhibit the best irradiation performance across all bias conditions, showing a reasonably small change in off-state leakage current and Vth, while the low-Vth transistors exhibitmore » a larger change in off-state leakage current. The “worst-case” bias condition during irradiation for both pull-down and pass-gate nMOSFETs in static random access memory is determined to be the on-state (Vgs = Vdd). We find the nMOSFET pull-down and pass-gate transistors of the SRAM bit-cell show less radiation-induced degradation due to transistor geometry and channel doping differences than the low-Vth transistor. Near-threshold operation is presented as a methodology for reducing radiation-induced increases in off-state device leakage current. In a 14-nm FinFET technology, the modeling indicates devices with high channel stop doping show the most robust response to TID allowing stable operation of ring oscillators and the SRAM bit-cell with minimal shift in critical operating characteristics.« less

1030-nm diode-laser-based light source delivering pulses with nanojoule energies and picosecond duration adjustable by mode locking or pulse gating operation

NASA Astrophysics Data System (ADS)

Klehr, A.; Liero, A.; Wenzel, H.; Bugge, F.; Brox, O.; Fricke, J.; Ressel, P.; Knigge, A.; Heinrich, W.; Tränkle, G.

2017-02-01

A new compact 1030 nm picosecond light source which can be switched between pulse gating and mode locking operation is presented. It consists of a multi-section distributed Bragg reflector (DBR) laser, an ultrafast multisection optical gate and a flared power amplifier (PA), mounted together with high frequency electronics and optical elements on a 5×4 cm micro bench. The master oscillator (MO) is a 10 mm long ridge wave-guide (RW) laser consisting of 200 μm long saturable absorber, 1500 μm long gain, 8000 μm long cavity, 200 μm long DBR and 100 μm long monitor sections. The 2 mm long optical gate consisting of several RW sections is monolithically integrated with the 4 mm long gain-guided tapered amplifier on a single chip. The light source can be switched between pulse gating and passive mode locking operation. For pulse gating all sections of the MO (except of the DBR and monitor sections) are forward biased and driven by a constant current. By injecting electrical pulses into one section of the optical gate the CW beam emitted by the MO is converted into a train of optical pulses with adjustable widths between 250 ps and 1000 ps. Peak powers of 20 W and spectral linewidths in the MHz range are achieved. Shorter pulses with widths between 4 ps and 15 ps and peak powers up to 50 W but larger spectral widths of about 300 pm are generated by mode locking where the saturable absorber section of the MO is reversed biased. The repetition rate of 4.2 GHz of the pulse train emitted by the MO can be reduced to values between 1 kHz and 100 MHz by utilizing the optical gate as pulse picker. The pulse-to-pulse distance can be controlled by an external trigger source.

Assembly and stoichiometry of the core structure of the bacterial flagellar type III export gate complex.

PubMed

Fukumura, Takuma; Makino, Fumiaki; Dietsche, Tobias; Kinoshita, Miki; Kato, Takayuki; Wagner, Samuel; Namba, Keiichi; Imada, Katsumi; Minamino, Tohru

2017-08-01

The bacterial flagellar type III export apparatus, which is required for flagellar assembly beyond the cell membranes, consists of a transmembrane export gate complex and a cytoplasmic ATPase complex. FlhA, FlhB, FliP, FliQ, and FliR form the gate complex inside the basal body MS ring, although FliO is required for efficient export gate formation in Salmonella enterica. However, it remains unknown how they form the gate complex. Here we report that FliP forms a homohexameric ring with a diameter of 10 nm. Alanine substitutions of conserved Phe-137, Phe-150, and Glu-178 residues in the periplasmic domain of FliP (FliPP) inhibited FliP6 ring formation, suppressing flagellar protein export. FliO formed a 5-nm ring structure with 3 clamp-like structures that bind to the FliP6 ring. The crystal structure of FliPP derived from Thermotoga maritia, and structure-based photo-crosslinking experiments revealed that Phe-150 and Ser-156 of FliPP are involved in the FliP-FliP interactions and that Phe-150, Arg-152, Ser-156, and Pro-158 are responsible for the FliP-FliO interactions. Overexpression of FliP restored motility of a ∆fliO mutant to the wild-type level, suggesting that the FliP6 ring is a functional unit in the export gate complex and that FliO is not part of the final gate structure. Copurification assays revealed that FlhA, FlhB, FliQ, and FliR are associated with the FliO/FliP complex. We propose that the assembly of the export gate complex begins with FliP6 ring formation with the help of the FliO scaffold, followed by FliQ, FliR, and FlhB and finally FlhA during MS ring formation.

Assembly and stoichiometry of the core structure of the bacterial flagellar type III export gate complex

PubMed Central

Fukumura, Takuma; Makino, Fumiaki; Dietsche, Tobias; Kinoshita, Miki; Kato, Takayuki; Wagner, Samuel; Namba, Keiichi; Imada, Katsumi

2017-01-01

The bacterial flagellar type III export apparatus, which is required for flagellar assembly beyond the cell membranes, consists of a transmembrane export gate complex and a cytoplasmic ATPase complex. FlhA, FlhB, FliP, FliQ, and FliR form the gate complex inside the basal body MS ring, although FliO is required for efficient export gate formation in Salmonella enterica. However, it remains unknown how they form the gate complex. Here we report that FliP forms a homohexameric ring with a diameter of 10 nm. Alanine substitutions of conserved Phe-137, Phe-150, and Glu-178 residues in the periplasmic domain of FliP (FliPP) inhibited FliP6 ring formation, suppressing flagellar protein export. FliO formed a 5-nm ring structure with 3 clamp-like structures that bind to the FliP6 ring. The crystal structure of FliPP derived from Thermotoga maritia, and structure-based photo-crosslinking experiments revealed that Phe-150 and Ser-156 of FliPP are involved in the FliP–FliP interactions and that Phe-150, Arg-152, Ser-156, and Pro-158 are responsible for the FliP–FliO interactions. Overexpression of FliP restored motility of a ∆fliO mutant to the wild-type level, suggesting that the FliP6 ring is a functional unit in the export gate complex and that FliO is not part of the final gate structure. Copurification assays revealed that FlhA, FlhB, FliQ, and FliR are associated with the FliO/FliP complex. We propose that the assembly of the export gate complex begins with FliP6 ring formation with the help of the FliO scaffold, followed by FliQ, FliR, and FlhB and finally FlhA during MS ring formation. PMID:28771466

Structured back gates for high-mobility two-dimensional electron systems using oxygen ion implantation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berl, M., E-mail: mberl@phys.ethz.ch; Tiemann, L.; Dietsche, W.

2016-03-28

We present a reliable method to obtain patterned back gates compatible with high mobility molecular beam epitaxy via local oxygen ion implantation that suppresses the conductivity of an 80 nm thick silicon doped GaAs epilayer. Our technique was optimized to circumvent several constraints of other gating and implantation methods. The ion-implanted surface remains atomically flat which allows unperturbed epitaxial overgrowth. We demonstrate the practical application of this gating technique by using magneto-transport spectroscopy on a two-dimensional electron system (2DES) with a mobility exceeding 20 × 10{sup 6} cm{sup 2}/V s. The back gate was spatially separated from the Ohmic contacts of the 2DES,more » thus minimizing the probability for electrical shorts or leakage and permitting simple contacting schemes.« less

Static Noise Margin Enhancement by Flex-Pass-Gate SRAM

NASA Astrophysics Data System (ADS)

O'Uchi, Shin-Ichi; Masahara, Meishoku; Sakamoto, Kunihiro; Endo, Kazuhiko; Liu, Yungxun; Matsukawa, Takashi; Sekigawa, Toshihiro; Koike, Hanpei; Suzuki, Eiichi

A Flex-Pass-Gate SRAM, i.e. a fin-type-field-effect-transistor- (FinFET-) based SRAM, is proposed to enhance noise margin during both read and write operations. In its cell, the flip-flop is composed of usual three-terminal- (3T-) FinFETs while pass gates are composed of four-terminal- (4T-) FinFETs. The 4T-FinFETs enable to adopt a dynamic threshold-voltage control in the pass gates. During a write operation, the threshold voltage of the pass gates is lowered to enhance the writing speed and stability. During the read operation, on the other hand, the threshold voltage is raised to enhance the static noise margin. An asymmetric-oxide 4T-FinFET is helpful to manage the leakage current through the pass gate. In this paper, a design strategy of the pass gate with an asymmetric gate oxide is considered, and a TCAD-based Monte Carlo simulation reveals that the Flex-Pass-Gate SRAM based on that design strategy is expected to be effective in half-pitch 32-nm technology for low-standby-power (LSTP) applications, even taking into account the variability in the device performance.

Study of proton radiation effects among diamond and rectangular gate MOSFET layouts

NASA Astrophysics Data System (ADS)

Seixas, L. E., Jr.; Finco, S.; Silveira, M. A. G.; Medina, N. H.; Gimenez, S. P.

2017-01-01

This paper describes an experimental comparative study of proton ionizing radiation effects between the metal-oxide-semiconductor (MOS) Field Effect Transistors (MOSFETs) implemented with hexagonal gate shapes (diamond) and their respective counterparts designed with the classical rectangular ones, regarding the same gate areas, channel widths and geometrical ratios (W/L). The devices were manufactured by using the 350 nm bulk complementary MOS (CMOS) integrated circuits technology. The diamond MOSFET with α angles higher or equal to 90° tends to present a smaller vulnerability to the high doses ionizing radiation than those observed in the typical rectangular MOSFET counterparts.

Proton Irradiation-Induced Metal Voids in Gallium Nitride High Electron Mobility Transistors

DTIC Science & Technology

2015-09-01

13. ABSTRACT (maximum 200 words) Gallium nitride/aluminum gallium nitride high electron mobility transistors with nickel/ gold (Ni/Au) and...platinum/ gold (Pt/Au) gating are irradiated with 2 MeV protons. Destructive physical analysis revealed material voids underneath the gate finger of the...nickel/ gold (Ni/Au) and platinum/ gold (Pt/Au) gating are irradiated with 2 MeV protons. Destructive physical analysis revealed material voids underneath

Nanocrystals embedded in hafnium dioxide-based dielectrics as charge storage nodes of nano-floating gate memory

NASA Astrophysics Data System (ADS)

Lee, Pui Fai

2007-12-01

Nanocrystals (NC) embedded in dielectrics have attracted a great deal of attention recently because they can potentially be applied in nonvolatile, high-speed, high-density and low-power memory devices. This device benefits from a relatively low operating voltage, high endurance, fast write-erase speeds and better immunity to soft errors. The nanocrystal materials suitable for such an application can be either metals or semiconductors. Recent studies have shown that high-k dielectrics, instead of SiO2 , for the tunneling layer in nanocrystal floating gate memory can improve the trade-off between data retention and program efficiency due to the unique band alignment of high-k dielectrics in the programming and retention modes. In this project, HfAlO has been selected as the high- k dielectric for the nanocrystal floating gate memory structure. The trilayer structure (HfAlO/Ge-NC/HfAlO) on Si was fabricated by PLD. Results revealed that relatively low substrate temperature and growth rate are favourable for the formation of smaller-size Ge nanocrystals. Effects of size/density of the Ge nanocrystal, the tunneling and control oxide layer thicknesses and the oxygen partial pressure during their growth on the charge storage and charge retention characteristics have also been studied. The island structure of the Ge nanocrystal suggests that the growth is based on the Volmer-Webber mode. The self-organized Ge nanocrystals so formed were uniform in size (5--20 nm diameter) and distribution with a density approaching 1012--1013cm-2. Flat-band voltage shift (DeltaVFB) of about 3.6 V and good retention property have been achieved. By varying aggregation distance, sputtering gas pressure and ionization power of the nanocluster source, nanoclusters of Ge with different sizes can be formed. The memory effect of the trilayer structure so formed with 10 nm Ge nanoclusters are manifested by the counter-clockwise hysteresis loop in the C-V curves and a maximum flat-band voltage shift of 5.0 V has been achieved. For comparison purposes, metal nanocrystals have also been investigated by utilizing both of the physical deposition methods as mentioned above. Silver (Ag) nanocrystals with size of 10--40 nm have been embedded in HfAlO matrix in the trilayer capacitor structure and a flat-band voltage shift of 2.0 V has been achieved.

Role of Oxygen in Ionic Liquid Gating on Two-Dimensional Cr2Ge2Te6: A Non-oxide Material.

PubMed

Chen, Yangyang; Xing, Wenyu; Wang, Xirui; Shen, Bowen; Yuan, Wei; Su, Tang; Ma, Yang; Yao, Yunyan; Zhong, Jiangnan; Yun, Yu; Xie, X C; Jia, Shuang; Han, Wei

2018-01-10

Ionic liquid gating can markedly modulate a material's carrier density so as to induce metallization, superconductivity, and quantum phase transitions. One of the main issues is whether the mechanism of ionic liquid gating is an electrostatic field effect or an electrochemical effect, especially for oxide materials. Recent observation of the suppression of the ionic liquid gate-induced metallization in the presence of oxygen for oxide materials suggests the electrochemical effect. However, in more general scenarios, the role of oxygen in the ionic liquid gating effect is still unclear. Here, we perform ionic liquid gating experiments on a non-oxide material: two-dimensional ferromagnetic Cr 2 Ge 2 Te 6 . Our results demonstrate that despite the large increase of the gate leakage current in the presence of oxygen, the oxygen does not affect the ionic liquid gating effect on  the channel resistance of Cr 2 Ge 2 Te 6 devices (<5% difference), which suggests the electrostatic field effect as the mechanism on non-oxide materials. Moreover, our results show that ionic liquid gating is more effective on the modulation of the channel resistances compared to the back gating across the 300 nm thick SiO 2 .

Voltage-dependent gating of KCNH potassium channels lacking a covalent link between voltage-sensing and pore domains

PubMed Central

Lörinczi, Éva; Gómez-Posada, Juan Camilo; de la Peña, Pilar; Tomczak, Adam P.; Fernández-Trillo, Jorge; Leipscher, Ulrike; Stühmer, Walter; Barros, Francisco; Pardo, Luis A.

2015-01-01

Voltage-gated channels open paths for ion permeation upon changes in membrane potential, but how voltage changes are coupled to gating is not entirely understood. Two modules can be recognized in voltage-gated potassium channels, one responsible for voltage sensing (transmembrane segments S1 to S4), the other for permeation (S5 and S6). It is generally assumed that the conversion of a conformational change in the voltage sensor into channel gating occurs through the intracellular S4–S5 linker that provides physical continuity between the two regions. Using the pathophysiologically relevant KCNH family, we show that truncated proteins interrupted at, or lacking the S4–S5 linker produce voltage-gated channels in a heterologous model that recapitulate both the voltage-sensing and permeation properties of the complete protein. These observations indicate that voltage sensing by the S4 segment is transduced to the channel gate in the absence of physical continuity between the modules. PMID:25818916

Voltage-dependent gating of KCNH potassium channels lacking a covalent link between voltage-sensing and pore domains.

PubMed

Lörinczi, Éva; Gómez-Posada, Juan Camilo; de la Peña, Pilar; Tomczak, Adam P; Fernández-Trillo, Jorge; Leipscher, Ulrike; Stühmer, Walter; Barros, Francisco; Pardo, Luis A

2015-03-30

Voltage-gated channels open paths for ion permeation upon changes in membrane potential, but how voltage changes are coupled to gating is not entirely understood. Two modules can be recognized in voltage-gated potassium channels, one responsible for voltage sensing (transmembrane segments S1 to S4), the other for permeation (S5 and S6). It is generally assumed that the conversion of a conformational change in the voltage sensor into channel gating occurs through the intracellular S4-S5 linker that provides physical continuity between the two regions. Using the pathophysiologically relevant KCNH family, we show that truncated proteins interrupted at, or lacking the S4-S5 linker produce voltage-gated channels in a heterologous model that recapitulate both the voltage-sensing and permeation properties of the complete protein. These observations indicate that voltage sensing by the S4 segment is transduced to the channel gate in the absence of physical continuity between the modules.

Voltage-dependent gating of KCNH potassium channels lacking a covalent link between voltage-sensing and pore domains

NASA Astrophysics Data System (ADS)

Lörinczi, Éva; Gómez-Posada, Juan Camilo; de La Peña, Pilar; Tomczak, Adam P.; Fernández-Trillo, Jorge; Leipscher, Ulrike; Stühmer, Walter; Barros, Francisco; Pardo, Luis A.

2015-03-01

Voltage-gated channels open paths for ion permeation upon changes in membrane potential, but how voltage changes are coupled to gating is not entirely understood. Two modules can be recognized in voltage-gated potassium channels, one responsible for voltage sensing (transmembrane segments S1 to S4), the other for permeation (S5 and S6). It is generally assumed that the conversion of a conformational change in the voltage sensor into channel gating occurs through the intracellular S4-S5 linker that provides physical continuity between the two regions. Using the pathophysiologically relevant KCNH family, we show that truncated proteins interrupted at, or lacking the S4-S5 linker produce voltage-gated channels in a heterologous model that recapitulate both the voltage-sensing and permeation properties of the complete protein. These observations indicate that voltage sensing by the S4 segment is transduced to the channel gate in the absence of physical continuity between the modules.

Frequency-doubled passively Q-switched microchip laser producing 225  ps pulses at 671  nm.

PubMed

Nikkinen, Jari; Korpijärvi, Ville-Markus; Leino, Iiro; Härkönen, Antti; Guina, Mircea

2016-11-15

We report a 671 nm laser source emitting 225 ps pulses with an average power of 55 mW and a repetition rate of 444 kHz. The system consists of a 1342 nm SESAM Q-switched Nd:YVO₄ microchip master oscillator and a dual-stage Nd:YVO₄ power amplifier. The 1342 nm signal was frequency-doubled to 671 nm using a periodically poled lithium niobate crystal. This laser source provides a practical alternative for applications requiring high energy picosecond pulses, such as time-gated Raman spectroscopy.

Double-gated Si NW FET sensors: Low-frequency noise and photoelectric properties

NASA Astrophysics Data System (ADS)

Gasparyan, F.; Khondkaryan, H.; Arakelyan, A.; Zadorozhnyi, I.; Pud, S.; Vitusevich, S.

2016-08-01

The transport, noise, and photosensitivity properties of an array of silicon nanowire (NW) p+-p-p+ field-effect transistors (FETs) are investigated. The peculiarities of photosensitivity and detectivity are analyzed over a wide spectrum range. The absorbance of p-Si NW shifts to the short wavelength region compared with bulk Si. The photocurrent and photosensitivity reach increased values in the UV range of the spectrum at 300 K. It is shown that sensitivity values can be tuned by the drain-source voltage and may reach record values of up to 2-4 A/W at a wavelength of 300 nm at room temperature. Low-frequency noise studies allow calculating the photodetectivity values, which increase with decreasing wavelength down to 300 nm. We show that the drain current of Si NW biochemical sensors substantially depends on pH value and the signal-to-noise ratio reaches the high value of 105. Increasing pH sensitivity with gate voltage is revealed for certain source-drain currents of pH-sensors based on Si NW FETs. The noise characteristic index decreases from 1.1 to 0.7 with the growth of the liquid gate voltage. Noise behavior is successfully explained in the framework of the correlated number-mobility unified fluctuation model. pH sensitivity increases as a result of the increase in liquid gate voltage, thus giving the opportunity to measure very low proton concentrations in the electrolyte medium at certain values of the liquid gate voltage.

Field ion source development for neutron generators

NASA Astrophysics Data System (ADS)

Bargsten Johnson, B.; Schwoebel, P. R.; Holland, C. E.; Resnick, P. J.; Hertz, K. L.; Chichester, D. L.

2012-01-01

An ion source based on the principles of electrostatic field desorption is being developed to improve the performance of existing compact neutron generators. The ion source is an array of gated metal tips derived from field electron emitter array microfabrication technology. A comprehensive summary of development and experimental activities is presented. Many structural modifications to the arrays have been incorporated to achieve higher tip operating fields, while lowering fields at the gate electrode to prevent gate field electron emission which initiates electrical breakdown in the array. The latest focus of fabrication activities has been on rounding the gate electrode edge and surrounding the gate electrode with dielectric material. Array testing results have indicated a steady progression of increased array tip operating fields with each new design tested. The latest arrays have consistently achieved fields beyond those required for the onset of deuterium desorption (˜20 V/nm), and have demonstrated the desorption of deuterium at fields up to 36 V/nm. The number of ions desorbed from an array has been quantified, and field desorption of metal tip substrate material from array tips has been observed for the first time. Gas-phase field ionization studies with ˜10,000 tip arrays have achieved deuterium ion currents of ˜50 nA. Neutron production by field ionization has yielded ˜10 2 n/s from ˜1 mm 2 of array area using the deuterium-deuterium fusion reaction at 90 kV.

High-sensitivity pH sensor using separative extended-gate field-effect transistors with single-walled carbon-nanotube networks

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2018-04-01

We fabricate high-sensitivity pH sensors using single-walled carbon-nanotube (SWCNT) network thin-film transistors (TFTs). The sensing and transducer parts of the pH sensor are composed of separative extended-sensing gates (ESGs) with SnO2 ion-sensitive membranes and double-gate structure TFTs with thin SWCNT network channels of ∼1 nm and AlO x top-gate insulators formed by the solution-deposition method. To prevent thermal process-induced damages on the SWCNT channel layer due to the post-deposition annealing process and improve the electrical characteristics of the SWCNT-TFTs, microwave irradiation is applied at low temperatures. As a result, a pH sensitivity of 7.6 V/pH, far beyond the Nernst limit, is obtained owing to the capacitive coupling effect between the top- and bottom-gate insulators of the SWCNT-TFTs. Therefore, double-gate structure SWCNT-TFTs with separated ESGs are expected to be highly beneficial for high-sensitivity disposable biosensor applications.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach

NASA Astrophysics Data System (ADS)

Molaei Imen Abadi, Rouzbeh; Sedigh Ziabari, Seyed Ali

2016-11-01

In this paper, a first qualitative study on the performance characteristics of dual-work function gate junctionless TFET (DWG-JLTFET) on the basis of energy band profile modulation is investigated. A dual-work function gate technique is used in a JLTFET in order to create a downward band bending on the source side similar to PNPN structure. Compared with the single-work function gate junctionless TFET (SWG-JLTFET), the numerical simulation results demonstrated that the DWG-JLTFET simultaneously optimizes the ON-state current, the OFF-state leakage current, and the threshold voltage and also improves average subthreshold slope. It is illustrated that if appropriate work functions are selected for the gate materials on the source side and the drain side, the JLTFET exhibits a considerably improved performance. Furthermore, the optimization design of the tunnel gate length ( L Tun) for the proposed DWG-JLTFET is studied. All the simulations are done in Silvaco TCAD for a channel length of 20 nm using the nonlocal band-to-band tunneling (BTBT) model.

A novel low temperature soft reflow process for the fabrication of deep-submicron (<0.35 μm) T-gate pseudomorphic high electron mobility transistor structures

NASA Astrophysics Data System (ADS)

Ian, Ka Wa; Exarchos, Michael; Missous, Mohamed

2013-02-01

We report a new and simple low temperature soft reflow process using solvent vapour. The combination of this soft reflow and conventional i-line lithography enables low cost, highly efficient fabrication at the deep-submicron scale. Compared to the conventional thermal reflow process, the key benefits of the new soft reflow process are its low temperature operation (<50 °C), greater shrinkage of the structure size (up to 75%) and better controllability. Gate openings reflowed from 1 μm to 250 nm have been routinely and reproducibly achieved by utilizing the saturation characteristics of the process. The feasibility of this soft reflow process is demonstrated in the fabrication of a 350 nm T-gate pseudomorphic high electron mobility transistor. By shrinking the gate length by a factor of three (from a 1 μm initial opening), the output current is improved by 60% (500 mA mm-1 from 300 mA mm-1) and fT and fMAX are increased to 70 GHz (from 20 GHz) and 120 GHz (from 40 GHz) respectively. The proposed soft reflow could potentially be applied on other compatible substrates such as polymer based material for organic or thin film devices, potentially leading to many new possible applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Proctor, Timothy; Rudinger, Kenneth; Young, Kevin

Randomized benchmarking (RB) is widely used to measure an error rate of a set of quantum gates, by performing random circuits that would do nothing if the gates were perfect. In the limit of no finite-sampling error, the exponential decay rate of the observable survival probabilities, versus circuit length, yields a single error metric r. For Clifford gates with arbitrary small errors described by process matrices, r was believed to reliably correspond to the mean, over all Clifford gates, of the average gate infidelity between the imperfect gates and their ideal counterparts. We show that this quantity is not amore » well-defined property of a physical gate set. It depends on the representations used for the imperfect and ideal gates, and the variant typically computed in the literature can differ from r by orders of magnitude. We present new theories of the RB decay that are accurate for all small errors describable by process matrices, and show that the RB decay curve is a simple exponential for all such errors. Here, these theories allow explicit computation of the error rate that RB measures (r), but as far as we can tell it does not correspond to the infidelity of a physically allowed (completely positive) representation of the imperfect gates.« less

VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate

NASA Astrophysics Data System (ADS)

Ahmad, Nabihah; Hakimi Mokhtar, Ahmad; Othman, Nurmiza binti; Fhong Soon, Chin; Rahman, Ab Al Hadi Ab

2017-08-01

Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2×2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160μm x 420.3μm (67.25 mm2). This design achieved a low power consumption of 122.85μW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.

Disturb-Free Three-Dimensional Vertical Floating Gate NAND with Separated-Sidewall Control Gate

NASA Astrophysics Data System (ADS)

Seo, Moon-Sik; Endoh, Tetsuo

2012-02-01

Recently, the three-dimensional (3D) vertical floating gate (FG) type NAND cell arrays with the sidewall control gate (SCG) structure are receiving attention to overcome the reliability issues of charge trap (CT) type 3D NAND. In order to achieve the multilevel cell (MLC) operation for lower bit cost in 3D NAND, it is important to eliminate reliability issues, such as the Vth distribution with interference and disturbance problems and Vth shift with retention issues. In this paper, we intensively investigated the disturbance problems of the 3D vertical FG type NAND cell with separated-sidewall control gate (S-SCG) structure for the reliable MLC operation. Above all, we successfully demonstrate the fully suppressed disturbance problems, such as indirect programming of the unselected cells, hot electron injection of the edge cells and direct influence to the neighboring passing cells, by using the S-SCG with 30 nm pillar size.

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers

PubMed Central

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Abstract Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlOx), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers. PMID:28634499

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

PubMed

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

Study of drain-extended NMOS under electrostatic discharge stress in 28 nm and 40 nm CMOS process

NASA Astrophysics Data System (ADS)

Wang, Weihuai; Jin, Hao; Dong, Shurong; Zhong, Lei; Han, Yan

2016-02-01

Researches on the electrostatic discharge (ESD) performance of drain-extended NMOS (DeNMOS) under the state-of-the-art 28 nm and 40 nm bulk CMOS process are performed in this paper. Three distinguishing phases of avalanche breakdown stage, depletion region push-out stage and parasitic NPN turn on stage of the gate-grounded DeNMOS (GG-DeNMOS) fabricated under 28 nm CMOS process measured with transmission line pulsing (TLP) test are analyzed through TCAD simulations and tape-out silicon verification detailedly. Damage mechanisms and failure spots of GG-DeNMOS under both CMOS processes are thermal breakdown of drain junction. Improvements based on the basic structure adjustments can increase the GG-DeNMOS robustness from original 2.87 mA/μm to the highest 5.41 mA/μm. Under 40 nm process, parameter adjustments based on the basic structure have no significant benefits on the robustness improvements. By inserting P+ segments in the N+ implantation of drain or an entire P+ strip between the N+ implantation of drain and polysilicon gate to form the typical DeMOS-SCR (silicon-controlled rectifier) structure, the ESD robustness can be enhanced from 1.83 mA/μm to 8.79 mA/μm and 29.78 mA/μm, respectively.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Citterio, M.; Camplani, A.; Cannon, M.

SRAM based Field Programmable Gate Arrays (FPGAs) have been rarely used in High Energy Physics (HEP) due to their sensitivity to radiation. The last generation of commercial FPGAs based on 28 nm feature size and on Silicon On Insulator (SOI) technologies are more tolerant to radiation to the level that their use in front-end electronics is now feasible. FPGAs provide re-programmability, high-speed computation and fast data transmission through the embedded serial transceivers. They could replace custom application specific integrated circuits in front end electronics in locations with moderate radiation field. Finally, the use of a FPGA in HEP experiments ismore » only limited by our ability to mitigate single event effects induced by the high energy hadrons present in the radiation field.« less

A Cu2+-selective fluorescent chemosensor based on BODIPY with two pyridine ligands and logic gate

NASA Astrophysics Data System (ADS)

Huang, Liuqian; Zhang, Jing; Yu, Xiaoxiu; Ma, Yifan; Huang, Tianjiao; Shen, Xi; Qiu, Huayu; He, Xingxing; Yin, Shouchun

2015-06-01

A novel near-infrared fluorescent chemosensor based on BODIPY (Py-1) has been synthesized and characterized. Py-1 displays high selectivity and sensitivity for sensing Cu2+ over other metal ions in acetonitrile. Upon addition of Cu2+ ions, the maximum absorption band of Py-1 in CH3CN displays a red shift from 603 to 608 nm, which results in a visual color change from pink to blue. When Py-1 is excited at 600 nm in the presence of Cu2+, the fluorescent emission intensity of Py-1 at 617 nm is quenched over 86%. Notably, the complex of Py-1-Cu2+ can be restored with the introduction of EDTA or S2-. Consequently, an IMPLICATION logic gate at molecular level operating in fluorescence mode with Cu2+ and S2- as chemical inputs can be constructed. Finally, based on the reversible and reproducible system, a nanoscale sequential memory unit displaying "Writing-Reading-Erasing-Reading" functions can be integrated.

A chemosensor showing discriminating fluorescent response for highly selective and nanomolar detection of Cu²⁺ and Zn²⁺ and its application in molecular logic gate.

PubMed

Fegade, Umesh A; Sahoo, Suban K; Singh, Amanpreet; Singh, Narinder; Attarde, Sanjay B; Kuwar, Anil S

2015-05-04

A fluorescent based receptor (4Z)-4-(4-diethylamino)-2-hydroxybenzylidene amino)-1,2dihydro-1,5-dimethyl-2-phenylpyrazol-3-one (receptor 3) was developed for the highly selective and sensitive detection of Cu(2+) and Zn(2+) in semi-aqueous system. The fluorescence of receptor 3 was enhanced and quenched, respectively, with the addition of Zn(2+) and Cu(2+) ions over other surveyed cations. The receptor formed host-guest complexes in 1:1 stoichiometry with the detection limit of 5 nM and 15 nM for Cu(2+) and Zn(2+) ions, respectively. Further, we have effectively utilized the two metal ions (Cu(2+) and Zn(2+)) as chemical inputs for the manufacture of INHIBIT type logic gate at molecular level using the fluorescence responses of receptor 3 at 450 nm. Copyright © 2015 Elsevier B.V. All rights reserved.

Sub-10 nm Gate Length Graphene Transistors: Operating at Terahertz Frequencies with Current Saturation

PubMed Central

Zheng, Jiaxin; Wang, Lu; Quhe, Ruge; Liu, Qihang; Li, Hong; Yu, Dapeng; Mei, Wai-Ning; Shi, Junjie; Gao, Zhengxiang; Lu, Jing

2013-01-01

Radio-frequency application of graphene transistors is attracting much recent attention due to the high carrier mobility of graphene. The measured intrinsic cut-off frequency (fT) of graphene transistor generally increases with the reduced gate length (Lgate) till Lgate = 40 nm, and the maximum measured fT has reached 300 GHz. Using ab initio quantum transport simulation, we reveal for the first time that fT of a graphene transistor still increases with the reduced Lgate when Lgate scales down to a few nm and reaches astonishing a few tens of THz. We observe a clear drain current saturation when a band gap is opened in graphene, with the maximum intrinsic voltage gain increased by a factor of 20. Our simulation strongly suggests it is possible to design a graphene transistor with an extraordinary high fT and drain current saturation by continuously shortening Lgate and opening a band gap. PMID:23419782

A manufacturable process integration approach for graphene devices

NASA Astrophysics Data System (ADS)

Vaziri, Sam; Lupina, Grzegorz; Paussa, Alan; Smith, Anderson D.; Henkel, Christoph; Lippert, Gunther; Dabrowski, Jarek; Mehr, Wolfgang; Östling, Mikael; Lemme, Max C.

2013-06-01

In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

Thermally stable In0.7Ga0.3As/In0.52Al0.48As pHEMTs using thermally evaporated palladium gate metallization

NASA Astrophysics Data System (ADS)

Ian, Ka Wa; Zawawiand, Mohamad Adzhar Md; Missous, Mohamed

2014-03-01

This work described the fabrication and performances of strained channel In0.52Al0.47As/In0.7Ga0.3As/InP pHEMTs with thermally evaporated Pd/Ti/Au gate metallization. The electrical characteristics of these Pd-gate devices are studied to investigate the effects of changing the Pd metal thickness, annealing temperature and annealing time. Following annealing at 200 °C for 35 min, a 10 nm Pd-gate device displays a VTH of -0.25 V, which is significantly smaller compared to those with Ti/Au gate schemes showing VTH = -0.75 V. A 1 um gate length device exhibits an improved Gm of 580 mS mm-1 (from 500 mS mm-1), a high IDSmax of 400 mA mm-1 (from 330 mA mm-1) and good fT and fmax of 24.5 and 49 GHz commensurate with the 1 µm gate length. All these enhancements are attributed to the controllable gate sinking of Pd. The device shows no significant degradation even after annealing at 230 °C for more than 5 h, which implies that the reliability of these Pd-gate structures is excellent.

Synthesis and electron storage characteristics of isolated silver nanodots on/embedded in Al 2O 3 gate dielectric

NASA Astrophysics Data System (ADS)

Wang, Q.; Song, Z. T.; Liu, W. L.; Lin, C. L.; Wang, T. H.

2004-05-01

Monolayer-isolated silver (Ag) nanodots with the average diameter down to 7 nm are synthesized on Al 2O 3/Si substrate by vacuum electron-beam evaporation followed by annealing at 400 °C in N 2 ambient. Metal-insulator-silicon (MIS) structures with Ag nanodots embedded in Al 2O 3 gate dielectric are fabricated. Clear electron storage effect with the flatband voltage shift of 1.3 eV is observed through capacitance-conductance and conductance-voltage measurements. Our results demonstrate the feasibility of applying Ag nanodots for nanocrystal floating-gate memory devices.

Low voltage operation of IGZO thin film transistors enabled by ultrathin Al2O3 gate dielectric

NASA Astrophysics Data System (ADS)

Ma, Pengfei; Du, Lulu; Wang, Yiming; Jiang, Ran; Xin, Qian; Li, Yuxiang; Song, Aimin

2018-01-01

An ultrathin, 5 nm, Al2O3 film grown by atomic-layer deposition was used as a gate dielectric for amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). The Al2O3 layer showed a low surface roughness of 0.15 nm, a low leakage current, and a high breakdown voltage of 6 V. In particular, a very high gate capacitance of 720 nF/cm2 was achieved, making it possible for the a-IGZO TFTs to not only operate at a low voltage of 1 V but also exhibit desirable properties including a low threshold voltage of 0.3 V, a small subthreshold swing of 100 mV/decade, and a high on/off current ratio of 1.2 × 107. Furthermore, even under an ultralow operation voltage of 0.6 V, well-behaved transistor characteristics were still observed with an on/off ratio as high as 3 × 106. The electron transport through the Al2O3 layer has also been analyzed, indicating the Fowler-Nordheim tunneling mechanism.

Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2

NASA Astrophysics Data System (ADS)

Martin, Dominik; Yurchuk, Ekaterina; Müller, Stefan; Müller, Johannes; Paul, Jan; Sundquist, Jonas; Slesazeck, Stefan; Schlösser, Till; van Bentum, Ralf; Trentzsch, Martin; Schröder, Uwe; Mikolajick, Thomas

2013-10-01

Throughout the 22 nm technology node HfO2 is established as a reliable gate dielectric in contemporary complementary metal oxide semiconductor (CMOS) technology. The working principle of ferroelectric field effect transistors FeFET has also been demonstrated for some time for dielectric materials like Pb[ZrxTi1-x]O3 and SrBi2Ta2O9. However, integrating these into contemporary downscaled CMOS technology nodes is not trivial due to the necessity of an extremely thick gate stack. Recent developments have shown HfO2 to have ferroelectric properties, given the proper doping. Moreover, these doped HfO2 thin films only require layer thicknesses similar to the ones already in use in CMOS technology. This work will show how the incorporation of Si induces ferroelectricity in HfO2 based capacitor structures and finally demonstrate non-volatile storage in nFeFETs down to a gate length of 100 nm. A memory window of 0.41 V can be retained after 20,000 switching cycles. Retention can be extrapolated to 10 years.

30 nm T-gate enhancement-mode InAlN/AlN/GaN HEMT on SiC substrates for future high power RF applications

NASA Astrophysics Data System (ADS)

Murugapandiyan, P.; Ravimaran, S.; William, J.

2017-08-01

The DC and RF performance of 30 nm gate length enhancement mode (E-mode) InAlN/AlN/GaN high electron mobility transistor (HEMT) on SiC substrate with heavily doped source and drain region have been investigated using the Synopsys TCAD tool. The proposed device has the features of a recessed T-gate structure, InGaN back barrier and Al2O3 passivated device surface. The proposed HEMT exhibits a maximum drain current density of 2.1 A/mm, transconductance {g}{{m}} of 1050 mS/mm, current gain cut-off frequency {f}{{t}} of 350 GHz and power gain cut-off frequency {f}\\max of 340 GHz. At room temperature the measured carrier mobility (μ), sheet charge carrier density ({n}{{s}}) and breakdown voltage are 1580 cm2/(V \\cdot s), 1.9× {10}13 {{cm}}-2, and 10.7 V respectively. The superlatives of the proposed HEMTs are bewitching competitor or future sub-millimeter wave high power RF VLSI circuit applications.

Single-fabrication-step Ge nanosphere/SiO2/SiGe heterostructures: a key enabler for realizing Ge MOS devices

NASA Astrophysics Data System (ADS)

Liao, P. H.; Peng, K. P.; Lin, H. C.; George, T.; Li, P. W.

2018-05-01

We report channel and strain engineering of self-organized, gate-stacking heterostructures comprising Ge-nanosphere gate/SiO2/SiGe-channels. An exquisitely-controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials was effectively exploited to simultaneously create these heterostructures in a single oxidation step. Process-controlled tunability of the channel length (5–95 nm diameters for the Ge-nanospheres), gate oxide thickness (2.5–4.8 nm), as well as crystal orientation, chemical composition and strain engineering of the SiGe-channel was achieved. Single-crystalline (100) Si1‑x Ge x shells with Ge content as high as x = 0.85 and with a compressive strain of 3%, as well as (110) Si1‑x Ge x shells with Ge content of x = 0.35 and corresponding compressive strain of 1.5% were achieved. For each crystal orientation, our high Ge-content, highly-stressed SiGe shells feature a high degree of crystallinity and thus, provide a core ‘building block’ required for the fabrication of Ge-based MOS devices.

All-Aluminum Thin Film Transistor Fabrication at Room Temperature.

PubMed

Yao, Rihui; Zheng, Zeke; Zeng, Yong; Liu, Xianzhe; Ning, Honglong; Hu, Shiben; Tao, Ruiqiang; Chen, Jianqiu; Cai, Wei; Xu, Miao; Wang, Lei; Lan, Linfeng; Peng, Junbiao

2017-02-23

Bottom-gate all-aluminum thin film transistors with multi conductor/insulator nanometer heterojunction were investigated in this article. Alumina (Al₂O₃) insulating layer was deposited on the surface of aluminum doping zinc oxide (AZO) conductive layer, as one AZO/Al₂O₃ heterojunction unit. The measurements of transmittance electronic microscopy (TEM) and X-ray reflectivity (XRR) revealed the smooth interfaces between ~2.2-nm-thick Al₂O₃ layers and ~2.7-nm-thick AZO layers. The devices were entirely composited by aluminiferous materials, that is, their gate and source/drain electrodes were respectively fabricated by aluminum neodymium alloy (Al:Nd) and pure Al, with Al₂O₃/AZO multilayered channel and AlO x :Nd gate dielectric layer. As a result, the all-aluminum TFT with two Al₂O₃/AZO heterojunction units exhibited a mobility of 2.47 cm²/V·s and an I on / I off ratio of 10⁶. All processes were carried out at room temperature, which created new possibilities for green displays industry by allowing for the devices fabricated on plastic-like substrates or papers, mainly using no toxic/rare materials.

Strain and deformations engineered germanene bilayer double gate-field effect transistor by first principles

NASA Astrophysics Data System (ADS)

Meher Abhinav, E.; Chandrasekaran, Gopalakrishnan; Kasmir Raja, S. V.

2017-10-01

Germanene, silicene, stanene, phosphorene and graphene are some of single atomic materials with novel properties. In this paper, we explored bilayer germanene-based Double Gate-Field Effect Transistor (DG-FET) with various strains and deformations using Density Functional Theory (DFT) and Green's approach by first-principle calculations. The DG-FET of 1.6 nm width, 6 nm channel length (Lch) and HfO2 as gate dielectric has been modeled. For intrinsic deformation of germanene bilayer, we have enforced minute mechanical deformation of wrap and twist (5°) and ripple (0.5 Å) on germanene bilayer channel material. By using NEGF formalism, I-V Characteristics of various strains and deformation tailored DG-FET was calculated. Our results show that rough edge and single vacancy (5-9) in bilayer germanene diminishes the current around 47% and 58% respectively as compared with pristine bilayer germanene. In case of strain tailored bilayer DG-FET, multiple NDR regions were observed which can be utilized in building stable multiple logic states in digital circuits and high frequency oscillators using negative resistive techniques.

Single-fabrication-step Ge nanosphere/SiO2/SiGe heterostructures: a key enabler for realizing Ge MOS devices.

PubMed

Liao, P H; Peng, K P; Lin, H C; George, T; Li, P W

2018-05-18

We report channel and strain engineering of self-organized, gate-stacking heterostructures comprising Ge-nanosphere gate/SiO 2 /SiGe-channels. An exquisitely-controlled dynamic balance between the concentrations of oxygen, Si, and Ge interstitials was effectively exploited to simultaneously create these heterostructures in a single oxidation step. Process-controlled tunability of the channel length (5-95 nm diameters for the Ge-nanospheres), gate oxide thickness (2.5-4.8 nm), as well as crystal orientation, chemical composition and strain engineering of the SiGe-channel was achieved. Single-crystalline (100) Si 1-x Ge x shells with Ge content as high as x = 0.85 and with a compressive strain of 3%, as well as (110) Si 1-x Ge x shells with Ge content of x = 0.35 and corresponding compressive strain of 1.5% were achieved. For each crystal orientation, our high Ge-content, highly-stressed SiGe shells feature a high degree of crystallinity and thus, provide a core 'building block' required for the fabrication of Ge-based MOS devices.

Layer-by-layer charging in non-volatile memory devices using embedded sub-2 nm platinum nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ramalingam, Balavinayagam; Zheng, Haisheng; Gangopadhyay, Shubhra, E-mail: gangopadhyays@missouri.edu

In this work, we demonstrate multi-level operation of a non-volatile memory metal oxide semiconductor capacitor by controlled layer-by-layer charging of platinum nanoparticle (PtNP) floating gate devices with defined gate voltage bias ranges. The device consists of two layers of ultra-fine, sub-2 nm PtNPs integrated between Al{sub 2}O{sub 3} tunneling and separation layers. PtNP size and interparticle distance were varied to control the particle self-capacitance and associated Coulomb charging energy. Likewise, the tunneling layer thicknesses were also varied to control electron tunneling to the first and second PtNP layers. The final device configuration with optimal charging behavior and multi-level programming was attainedmore » with a 3 nm Al{sub 2}O{sub 3} initial tunneling layer, initial PtNP layer with particle size 0.54 ± 0.12 nm and interparticle distance 4.65 ± 2.09 nm, 3 nm Al{sub 2}O{sub 3} layer to separate the PtNP layers, and second particle layer with 1.11 ± 0.28 nm PtNP size and interparticle distance 2.75 ± 1.05 nm. In this device, the memory window of the first PtNP layer saturated over a programming bias range of 7 V to 14 V, after which the second PtNP layer starts charging, exhibiting a multi-step memory window with layer-by-layer charging.« less

Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

NASA Astrophysics Data System (ADS)

Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

2016-03-01

Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g. field-effect transistors (FETs), remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET) offers electronic-optical hybridization at the component level, which can continue Moore’s law to quantum region without requiring a FET’s fabrication complexity, e.g. physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g. on/off ratios up to ~1.0x106 with a source-drain voltage of ~1.43 V, gate-power of ~260 nW, and subthreshold swing of ~0.3 nW/decade (excluding losses). Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.

What Randomized Benchmarking Actually Measures

DOE PAGES

Proctor, Timothy; Rudinger, Kenneth; Young, Kevin; ...

2017-09-28

Randomized benchmarking (RB) is widely used to measure an error rate of a set of quantum gates, by performing random circuits that would do nothing if the gates were perfect. In the limit of no finite-sampling error, the exponential decay rate of the observable survival probabilities, versus circuit length, yields a single error metric r. For Clifford gates with arbitrary small errors described by process matrices, r was believed to reliably correspond to the mean, over all Clifford gates, of the average gate infidelity between the imperfect gates and their ideal counterparts. We show that this quantity is not amore » well-defined property of a physical gate set. It depends on the representations used for the imperfect and ideal gates, and the variant typically computed in the literature can differ from r by orders of magnitude. We present new theories of the RB decay that are accurate for all small errors describable by process matrices, and show that the RB decay curve is a simple exponential for all such errors. Here, these theories allow explicit computation of the error rate that RB measures (r), but as far as we can tell it does not correspond to the infidelity of a physically allowed (completely positive) representation of the imperfect gates.« less

Investigation of impact of post-metallization annealing on reliability of 65 nm NOR floating-gate flash memories

NASA Astrophysics Data System (ADS)

Chiu, Shengfen; Xu, Yue; Ji, Xiaoli; Yan, Feng

2016-12-01

This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65 nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.

Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation

NASA Astrophysics Data System (ADS)

Koike, Hiroki; Ohsawa, Takashi; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2015-04-01

A spintronic-based power-gated micro-processing unit (MPU) is proposed. It includes a power control circuit activated by the newly supported power-off instruction for the deep-sleep mode. These means enable the power-off procedure for the MPU to be executed appropriately. A test chip was designed and fabricated using 90 nm CMOS and an additional 100 nm MTJ process; it was successfully operated. The guideline of the energy reduction effects for this MPU was presented, using the estimation based on the measurement results of the test chip. The result shows that a large operation energy reduction of 1/28 can be achieved when the operation duty is 10%, under the condition of a sufficient number of idle clock cycles.

Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications.

PubMed

Jeon, Sanghun; Park, Sungho; Song, Ihun; Hur, Ji-Hyun; Park, Jaechul; Kim, Hojung; Kim, Sunil; Kim, Sangwook; Yin, Huaxiang; Chung, U-In; Lee, Eunha; Kim, Changjung

2011-01-01

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

MoS2 Negative-Capacitance Field-Effect Transistors with Subthreshold Swing below the Physics Limit.

PubMed

Liu, Xingqiang; Liang, Renrong; Gao, Guoyun; Pan, Caofeng; Jiang, Chunsheng; Xu, Qian; Luo, Jun; Zou, Xuming; Yang, Zhenyu; Liao, Lei; Wang, Zhong Lin

2018-05-21

The Boltzmann distribution of electrons induced fundamental barrier prevents subthreshold swing (SS) from less than 60 mV dec -1 at room temperature, leading to high energy consumption of MOSFETs. Herein, it is demonstrated that an aggressive introduction of the negative capacitance (NC) effect of ferroelectrics can decisively break the fundamental limit governed by the "Boltzmann tyranny". Such MoS 2 negative-capacitance field-effect transistors (NC-FETs) with self-aligned top-gated geometry demonstrated here pull down the SS value to 42.5 mV dec -1 , and simultaneously achieve superior performance of a transconductance of 45.5 μS μm and an on/off ratio of 4 × 10 6 with channel length less than 100 nm. Furthermore, the inserted HfO 2 layer not only realizes a stable NC gate stack structure, but also prevents the ferroelectric P(VDF-TrFE) from fatigue with robust stability. Notably, the fabricated MoS 2 NC-FETs are distinctly different from traditional MOSFETs. The on-state current increases as the temperature decreases even down to 20 K, and the SS values exhibit nonlinear dependence with temperature due to the implementation of the ferroelectric gate stack. The NC-FETs enable fundamental applications through overcoming the Boltzmann limit in nanoelectronics and open up an avenue to low-power transistors needed for many exciting long-endurance portable consumer products. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Simple all-microwave entangling gate for fixed-frequency superconducting qubits.

PubMed

Chow, Jerry M; Córcoles, A D; Gambetta, Jay M; Rigetti, Chad; Johnson, B R; Smolin, John A; Rozen, J R; Keefe, George A; Rothwell, Mary B; Ketchen, Mark B; Steffen, M

2011-08-19

We demonstrate an all-microwave two-qubit gate on superconducting qubits which are fixed in frequency at optimal bias points. The gate requires no additional subcircuitry and is tunable via the amplitude of microwave irradiation on one qubit at the transition frequency of the other. We use the gate to generate entangled states with a maximal extracted concurrence of 0.88, and quantum process tomography reveals a gate fidelity of 81%. © 2011 American Physical Society

Strain effects in low-dimensional silicon MOS and AlGaN/GaN HEMT devices

NASA Astrophysics Data System (ADS)

Baykan, Mehmet Onur

Strained silicon technology is a well established method to enhance sub-100nm MOSFET performance. With the scalability of process-induced strain, strained silicon channels have been used in every advanced CMOS technology since the 90nm node. At the 22nm node, due to the detrimental short channel effects, non-planar silicon CMOS has emerged as a viable solution to sustain transistor scaling without compromising the device performance. Therefore, it is necessary to conduct a physics based investigation of the effects of mechanical strain in silicon MOS device performance enhancement, as the transverse and longitudinal device dimensions scale down for future technology nodes. While silicon is widely used as the material basis for logic transistors, AlGaN/GaN HEMTs promise a superior device platform over silicon based power MOSFETs for high-frequency and high-power applications. In contrast to the mature Si crystal growth technology, the abundance of defects in the GaN material system creates obstacles for the realization of a reliable AlGaN/GaN HEMT device technology. Due to the high levels of internal mechanical strain present in AlGaN/GaN HEMTs, it is of utmost importance to understand the impact of mechanical stress on AlGaN/GaN trap generation. First, we have investigated the underlying physics of the comparable electron mobility observed in (100) and (110) sidewall silicon double-gate FinFETs, which is different from the observed planar (100) and (110) electron mobility. By conducting a systematic experimental study, it is shown that the undoped body, metal gate induced stress, and volume-inversion effects do not explain the comparable electron mobility. Using a self-consistent double-gate FinFET simulator, we have showed that for (110) FinFETs, an increased population of electrons is obtained for the Delta2 valley due to the heavy nonparabolic confinement mass, leading to a comparable average electron transport effective mass for both orientations. The width dependent strain response of tri-gate p-type FinFETs are experimentally extracted using a 4-point bending jig. It is found that the low-field piezoresistance coefficient of p-type FinFETs can be modeled by using a weighted conductance average of the top and sidewall bulk piezoresistance coefficients. Next, the strain enhancement of p-type ballistic silicon nanowire MOSFETs is studied using sp3d 5s* basis nearest-neighbor tight-binding simulations coupled with a semiclassical top-of-the-barrier transport model. Size and orientation dependent strain enhancement of ballistic hole transport is explained by the strain-induced modification of the 1D nanowire valence band density-of-states. Further insights are provided for future p-type high-performance silicon nanowire logic devices. A physics based investigation is conducted to understand the strain effects on surface roughness limited electron mobility in silicon inversion layers. Based on the evidence from electrical and material characterization, a strain-induced surface morphology change is hypothesized. To model the observed electrical characteristics, we have employed a self-consistent MOSFET mobility simulator coupled with an ad hoc strain-induced roughness modification. The strain induced surface morphology change is found to be consistent among electrical and materials characterization, as well as transport simulations. In order to bridge the gap between the drift-diffusion based models for long-channel devices and the quasi-ballistic models for nanoscale channels, a unified carrier transport model is developed using an updated one-flux theory. Including the high-field and carrier confinement effects, a surface-potential based analytical transmission expression is obtained for the entire MOSFET operation range. With the new channel transmission equation and average carrier drift velocity, a new expression for channel ballisticity is defined. Impact of mechanical strain on carrier transport for both nMOSFETs and pMOSFETs in both linear and saturation regimes is explained using the new channel transmission definitions. To understand the impact of mechanical strain on AlGaN/GaN HEMT trap generation, we have devised an experimental method to obtain the photon flux-normalized relative areal trap density distribution using photoionization spectroscopy technique. The details of the trap extraction method and the experimental setup are given. Using this setup, the trap characteristics are extracted for both ungated transmission line module (TLM) and gated HEMT devices from both Si and SiC substrates. The changes in the device trap characteristics are emphasized before and after electrical stressing. It is found through the step-voltage stressing of the AlGaN/GaN HEMT gate stack that the device degradation is due to the near bandgap trap generation, which are shown to be related to the structural defects in GaN.

Double-gated Si NW FET sensors: Low-frequency noise and photoelectric properties

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gasparyan, F.; Forschungszentrum Jülich, Peter Grünberg Institute; Khondkaryan, H.

2016-08-14

The transport, noise, and photosensitivity properties of an array of silicon nanowire (NW) p{sup +}-p-p{sup +} field-effect transistors (FETs) are investigated. The peculiarities of photosensitivity and detectivity are analyzed over a wide spectrum range. The absorbance of p-Si NW shifts to the short wavelength region compared with bulk Si. The photocurrent and photosensitivity reach increased values in the UV range of the spectrum at 300 K. It is shown that sensitivity values can be tuned by the drain-source voltage and may reach record values of up to 2–4 A/W at a wavelength of 300 nm at room temperature. Low-frequency noise studies allow calculatingmore » the photodetectivity values, which increase with decreasing wavelength down to 300 nm. We show that the drain current of Si NW biochemical sensors substantially depends on pH value and the signal-to-noise ratio reaches the high value of 10{sup 5}. Increasing pH sensitivity with gate voltage is revealed for certain source-drain currents of pH-sensors based on Si NW FETs. The noise characteristic index decreases from 1.1 to 0.7 with the growth of the liquid gate voltage. Noise behavior is successfully explained in the framework of the correlated number-mobility unified fluctuation model. pH sensitivity increases as a result of the increase in liquid gate voltage, thus giving the opportunity to measure very low proton concentrations in the electrolyte medium at certain values of the liquid gate voltage.« less

Selected area growth integrated wavelength converter based on PD-EAM optical logic gate

NASA Astrophysics Data System (ADS)

Bin, Niu; Jifang, Qiu; Daibing, Zhou; Can, Zhang; Song, Liang; Dan, Lu; Lingjuan, Zhao; Jian, Wu; Wei, Wang

2014-09-01

A selected area growth wavelength converter based on a PD-EAM optical logic gate for WDM application is presented, integrating an EML transmitter and a SOA-PD receiver. The design, fabrication, and DC characters were analyzed. A 2 Gb/s NRZ signal based on the C-band wavelength converted to 1555 nm with the highest extinction ratio of 7 dB was achieved and wavelength converted eye diagrams with eyes opened were presented.

Gating electrical transport through DNA molecules that bridge between silicon nanogaps.

PubMed

Takagi, Shogo; Takada, Tadao; Matsuo, Naoto; Yokoyama, Shin; Nakamura, Mitsunobu; Yamana, Kazushige

2012-03-21

DNA electronic devices were prepared on silicon-based three-terminal electrodes. Both ends of DNA molecules (400 bp long, mixed sequences) were bridged via chemical bonds between the source-drain nanogap (120 nm) electrodes. S-Shaped I-V curves were obtained and the electric current can be modulated by the gate voltage. The DNA molecules act as semiconducting p-type nanowires in the three-terminal device. This journal is © The Royal Society of Chemistry 2012

Partial hyperbolicity and attracting regions in 3-dimensional manifolds

NASA Astrophysics Data System (ADS)

Potrie, Rafael

The need for reliable, fiber-based sources of entangled and paired photons has intensified in recent years because of potential uses in optical quantum communication and computing. In particular, indistinguishable photon sources are an inherent part of several quantum communication protocols and are needed to establish the viability of quantum communication networks. This thesis is centered around the development of such sources at telecommunication-band wavelengths. In this thesis, we describe experiments on entangled photon generation and the creation of quantum logic gates in the C-band, and on photon indistinguishability in the O-band. These experiments utilize the four-wave mixing process in fiber which occurs as a result of the Kerr nonlinearity, to create paired photons. To begin, we report the development of a source of 1550-nm polarization entangled photons in fiber. We then interface this source with a quantum Controlled-NOT gate, which is a universal quantum logic gate. We set experimental bounds on the process fidelity of the Controlled-NOT gate. Next, we report a demonstration of quantum interference between 1310-nm photons produced in independent sources. We demonstrate high quantum interference visibility, a signature of quantum indistinguishability, while using distinguishable pump photons. Together, these efforts constitute preliminary steps toward establishing the viability of fiber-based quantum communication, which will allow us to utilize existing infrastructure for implementing quantum communication protocols.

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

Structural Characterization and Impedance Spectroscopy of Substituted, Fused-Ring Organic Semiconductors

NASA Astrophysics Data System (ADS)

Shaw, Charles Michael

Organic materials present a number of advantages over silicon that make them ideal candidates for modest performance devices like active matrix backplanes and RFID tags. The work detailed here describes both structural characterization of promising new materials, as well as the adaptation of impedance spectroscopy techniques to the study of organic transistors. Unit cells and solution casting behavior for dioctyl- and didodecyl-pentathienoacene are presented. Dioctyl pentathienoacene has an orthorhombic lattice with parameters a = 1.15 nm, b = 0.43 nm and c = 3.05 nm. Didodecyl pentathienoacene has an monoclinic lattice with parameters gamma = 92.2°, a = 1.10 urn, b = 0.42 nm and c = 3.89 nm. Additionally, thermotropic phase behavior is detailed. Both materials exhibit a "side chain melting" transition---characterized by a dramatic unit cell contraction of more than 20%---and smectic C liquid crystal phases. The side chain melting transition shows similarity to phase transitions elicited by exposing these materials to high energy electron flux. In both cases, disorder in the substitutions results in new phases for these materials. Dioctyl-pentathienoacene also exhibits a unique phase, which is intermediately ordered and shows a threefold increase in critical dose over the as-cast phase. Impedance spectroscopy of triisopropylsilyl pentacene transistors suggests these devices are well fit by a Voigt model equivalent circuit. The gate bias dependent resistor represents the channel conductance and the capacitor represents the drain-gate and source-gate capacitances. This in turn suggests that conduction occurs through delocalized states available in ordered regions, with disordered regions contributing localized, immobile states. Impedance spectroscopy of poly(2,5-bis(3-alkylthiophen-2-yl)thieno[3,2-b]thiophene) shows similar behavior. The use of variable temperature impedance spectroscopy is also demonstrated. This technique is used to measure the reduction in trap energy---from 200 meV to 140 meV---produced by annealing the material in its liquid crystal phase.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nielsen, Erik; Blume-Kohout, Robin; Rudinger, Kenneth

PyGSTi is an implementation of Gate Set Tomography in the python programming language. Gate Set Tomography (GST) is a theory and protocol for simultaneously estimating the state preparation, gate operations, and measurement effects of a physical system of one or many quantum bits (qubits). These estimates are based entirely on the statistics of experimental measurements, and their interpretation and analysis can provide a detailed understanding of the types of errors/imperfections in the physical system. In this way, GST provides not only a means of certifying the "goodness" of qubits but also a means of debugging (i.e. improving) them.

Epitaxial GeSn film formed by solid phase epitaxy and its application to Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor capacitors with sub-nm equivalent oxide thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Ching-Wei; Wu, Yung-Hsien; Hsieh, Ching-Heng

2014-11-17

Through the technique of solid phase epitaxy (SPE), an epitaxial Ge{sub 0.955}Sn{sub 0.045} film was formed on a Ge substrate by depositing an amorphous GeSn film followed by a rapid thermal annealing at 550 °C. A process that uses a SiO{sub 2} capping layer on the amorphous GeSn film during SPE was proposed and it prevents Sn precipitation from occurring while maintaining a smooth surface due to the reduced surface mobility of Sn atoms. The high-quality epitaxial GeSn film was observed to have single crystal structure, uniform thickness and composition, and tiny surface roughness with root mean square of 0.56 nm. Withmore » a SnO{sub x}-free surface, Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor (MOS) capacitors with equivalent oxide thickness (EOT) of 0.55 nm were developed. A small amount of traps inside the Yb{sub 2}O{sub 3} was verified by negligible hysteresis in capacitance measurement. Low leakage current of 0.4 A/cm{sup 2} at gate bias of flatband voltage (V{sub FB})-1 V suggests the high quality of the gate dielectric. In addition, the feasibility of using Yb{sub 2}O{sub 3} to well passivate GeSn surface was also evidenced by the small interface trap density (D{sub it}) of 4.02 × 10{sup 11} eV{sup −1} cm{sup −2}, which can be attributed to smooth GeSn surface and Yb{sub 2}O{sub 3} valency passivation. Both leakage current and D{sub it} performance outperform other passivation techniques at sub-nm EOT regime. The proposed epitaxial GeSn film along with Yb{sub 2}O{sub 3} dielectric paves an alternative way to enable high-performance GeSn MOS devices.« less

Intermodulation distortion and linearity performance assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC design

NASA Astrophysics Data System (ADS)

Chaujar, Rishu; Kaur, Ravneet; Saxena, Manoj; Gupta, Mridula; Gupta, R. S.

2008-08-01

The distortion and linearity behaviour of MOSFETs is imperative for low-noise applications and RFICs design. In this paper, an extensive study on the RF-distortion and linearity behaviour of Laterally Amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET is performed and the influence of technology variations such as gate length, negative junction depth (NJD), substrate bias, drain bias and gate material workfunction is explored using ATLAS device simulator. Simulation results reveal that L-DUMGAC MOSFET significantly enhances the linearity and intermodulation distortion performance in terms of figure of merit (FOM) metrics: V, V, IIP3, IMD3 and higher order transconductance coefficients: gm1, gm2, gm3, proving its efficacy for RFIC design. The work, thus, optimize the device's bias point for RFICs with higher efficiency and better linearity performance.

Visible to short wavelength infrared In2Se3-nanoflake photodetector gated by a ferroelectric polymer

NASA Astrophysics Data System (ADS)

Wu, Guangjian; Wang, Xudong; Wang, Peng; Huang, Hai; Chen, Yan; Sun, Shuo; Shen, Hong; Lin, Tie; Wang, Jianlu; Zhang, Shangtao; Bian, Lifeng; Sun, Jinglan; Meng, Xiangjian; Chu, Junhao

2016-09-01

Photodetectors based on two-dimensional (2D) transition-metal dichalcogenides have been studied extensively in recent years. However, the detective spectral ranges, dark current and response time are still unsatisfactory, even under high gate and source-drain bias. In this work, the photodetectors of In2Se3 have been fabricated on a ferroelectric field effect transistor structure. Based on this structure, high performance photodetectors have been achieved with a broad photoresponse spectrum (visible to 1550 nm) and quick response (200 μs). Most importantly, with the intrinsic huge electric field derived from the polarization of ferroelectric polymer (P(VDF-TrFE)) gating, a low dark current of the photodetector can be achieved without additional gate bias. These studies present a crucial step for further practical applications for 2D semiconductors.

SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

NASA Astrophysics Data System (ADS)

Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

Simulation of temperature dependent dielectric breakdown in n{sup +}-polySi/SiO{sub 2}/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias

DOE Office of Scientific and Technical Information (OSTI.GOV)

Samanta, Piyas, E-mail: piyas@vcfw.org; Mandal, Krishna C., E-mail: mandalk@cec.sc.edu

2016-08-14

We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7–25 nm) silicon dioxide (SiO{sub 2}) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n{sup +}-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV belowmore » the SiO{sub 2} conduction band. Holes were generated in the n{sup +}-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness t{sub ox} and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields E{sub ox} ranging from 5 to 10 MV/cm. Our simulated time-to-breakdown (t{sub BD}) results are in excellent agreement with those obtained from time consuming TDDB measurements. It is observed that irrespective of stress temperatures, the t{sub BD} values estimated in the field range between 5 and 9 MV/cm better fit to reciprocal field (1/E) model for the thickness range studied here. Furthermore, for a 10 year projected device lifetime, a good reliability margin of safe operating field from 8.5 to 7.5 MV/cm for 7 nm and 8.1 to 6.9 MV/cm for 25 nm thick SiO{sub 2} was observed between 27 and 225 °C.« less

Scanning photoelectron microscope for nanoscale three-dimensional spatial-resolved electron spectroscopy for chemical analysis.

PubMed

Horiba, K; Nakamura, Y; Nagamura, N; Toyoda, S; Kumigashira, H; Oshima, M; Amemiya, K; Senba, Y; Ohashi, H

2011-11-01

In order to achieve nondestructive observation of the three-dimensional spatially resolved electronic structure of solids, we have developed a scanning photoelectron microscope system with the capability of depth profiling in electron spectroscopy for chemical analysis (ESCA). We call this system 3D nano-ESCA. For focusing the x-ray, a Fresnel zone plate with a diameter of 200 μm and an outermost zone width of 35 nm is used. In order to obtain the angular dependence of the photoelectron spectra for the depth-profile analysis without rotating the sample, we adopted a modified VG Scienta R3000 analyzer with an acceptance angle of 60° as a high-resolution angle-resolved electron spectrometer. The system has been installed at the University-of-Tokyo Materials Science Outstation beamline, BL07LSU, at SPring-8. From the results of the line-scan profiles of the poly-Si/high-k gate patterns, we achieved a total spatial resolution better than 70 nm. The capability of our system for pinpoint depth-profile analysis and high-resolution chemical state analysis is demonstrated. © 2011 American Institute of Physics

3D super resolution range-gated imaging for canopy reconstruction and measurement

NASA Astrophysics Data System (ADS)

Huang, Hantao; Wang, Xinwei; Sun, Liang; Lei, Pingshun; Fan, Songtao; Zhou, Yan

2018-01-01

In this paper, we proposed a method of canopy reconstruction and measurement based on 3D super resolution range-gated imaging. In this method, high resolution 2D intensity images are grasped by active gate imaging, and 3D images of canopy are reconstructed by triangular-range-intensity correlation algorithm at the same time. A range-gated laser imaging system(RGLIS) is established based on 808 nm diode laser and gated intensified charge-coupled device (ICCD) camera with 1392´1040 pixels. The proof experiments have been performed for potted plants located 75m away and trees located 165m away. The experiments show it that can acquire more than 1 million points per frame, and 3D imaging has the spatial resolution about 0.3mm at the distance of 75m and the distance accuracy about 10 cm. This research is beneficial for high speed acquisition of canopy structure and non-destructive canopy measurement.

Rewritable ghost floating gates by tunnelling triboelectrification for two-dimensional electronics

PubMed Central

Kim, Seongsu; Kim, Tae Yun; Lee, Kang Hyuck; Kim, Tae-Ho; Cimini, Francesco Arturo; Kim, Sung Kyun; Hinchet, Ronan; Kim, Sang-Woo; Falconi, Christian

2017-01-01

Gates can electrostatically control charges inside two-dimensional materials. However, integrating independent gates typically requires depositing and patterning suitable insulators and conductors. Moreover, after manufacturing, gates are unchangeable. Here we introduce tunnelling triboelectrification for localizing electric charges in very close proximity of two-dimensional materials. As representative materials, we use chemical vapour deposition graphene deposited on a SiO2/Si substrate. The triboelectric charges, generated by friction with a Pt-coated atomic force microscope tip and injected through defects, are trapped at the air–SiO2 interface underneath graphene and act as ghost floating gates. Tunnelling triboelectrification uniquely permits to create, modify and destroy p and n regions at will with the spatial resolution of atomic force microscopes. As a proof of concept, we draw rewritable p/n+ and p/p+ junctions with resolutions as small as 200 nm. Our results open the way to time-variant two-dimensional electronics where conductors, p and n regions can be defined on demand. PMID:28649986

Rewritable ghost floating gates by tunnelling triboelectrification for two-dimensional electronics

NASA Astrophysics Data System (ADS)

Kim, Seongsu; Kim, Tae Yun; Lee, Kang Hyuck; Kim, Tae-Ho; Cimini, Francesco Arturo; Kim, Sung Kyun; Hinchet, Ronan; Kim, Sang-Woo; Falconi, Christian

2017-06-01

Gates can electrostatically control charges inside two-dimensional materials. However, integrating independent gates typically requires depositing and patterning suitable insulators and conductors. Moreover, after manufacturing, gates are unchangeable. Here we introduce tunnelling triboelectrification for localizing electric charges in very close proximity of two-dimensional materials. As representative materials, we use chemical vapour deposition graphene deposited on a SiO2/Si substrate. The triboelectric charges, generated by friction with a Pt-coated atomic force microscope tip and injected through defects, are trapped at the air-SiO2 interface underneath graphene and act as ghost floating gates. Tunnelling triboelectrification uniquely permits to create, modify and destroy p and n regions at will with the spatial resolution of atomic force microscopes. As a proof of concept, we draw rewritable p/n+ and p/p+ junctions with resolutions as small as 200 nm. Our results open the way to time-variant two-dimensional electronics where conductors, p and n regions can be defined on demand.

Novel technique of source and drain engineering for dual-material double-gate (DMDG) SOI MOSFETS

NASA Astrophysics Data System (ADS)

Yadav, Himanshu; Malviya, Abhishek Kumar; Chauhan, R. K.

2018-04-01

The dual-metal dual-gate (DMDG) SOI has been used with Dual Sided Source and Drain Engineered 50nm SOI MOSFET with various high-k gate oxide. It has been scrutinized in this work to enhance its electrical performance. The proposed structure is designed by creating Dual Sided Source and Drain Modification and its characteristics are evaluated on ATLAS device simulator. The consequence of this dual sided assorted doping on source and drain side of the DMDG transistor has better leakage current immunity and heightened ION current with higher ION to IOFF Ratio. Which thereby vesting the proposed device appropriate for low power digital applications.

Application of high-quality SiO2 grown by multipolar ECR source to Si/SiGe MISFET

NASA Technical Reports Server (NTRS)

Sung, K. T.; Li, W. Q.; Li, S. H.; Pang, S. W.; Bhattacharya, P. K.

1993-01-01

A 5 nm-thick SiO2 gate was grown on an Si(p+)/Si(0.8)Ge(0.2) modulation-doped heterostructure at 26 C with an oxygen plasma generated by a multipolar electron cyclotron resonance source. The ultrathin oxide has breakdown field above 12 MV/cm and fixed charge density about 3 x 10 exp 10/sq cm. Leakage current as low as 1/micro-A was obtained with the gate biased at 4 V. The MISFET with 0.25 x 25 sq m gate shows maximum drain current of 41.6 mA/mm and peak transconductance of 21 mS/mm.

Device and circuit analysis of a sub 20 nm double gate MOSFET with gate stack using a look-up-table-based approach

NASA Astrophysics Data System (ADS)

Chakraborty, S.; Dasgupta, A.; Das, R.; Kar, M.; Kundu, A.; Sarkar, C. K.

2017-12-01

In this paper, we explore the possibility of mapping devices designed in TCAD environment to its modeled version developed in cadence virtuoso environment using a look-up table (LUT) approach. Circuit simulation of newly designed devices in TCAD environment is a very slow and tedious process involving complex scripting. Hence, the LUT based modeling approach has been proposed as a faster and easier alternative in cadence environment. The LUTs are prepared by extracting data from the device characteristics obtained from device simulation in TCAD. A comparative study is shown between the TCAD simulation and the LUT-based alternative to showcase the accuracy of modeled devices. Finally the look-up table approach is used to evaluate the performance of circuits implemented using 14 nm nMOSFET.

A films based approach to intensity imbalance correction for 65nm node c:PSM

NASA Astrophysics Data System (ADS)

Cottle, Rand; Sixt, Pierre; Lassiter, Matt; Cangemi, Marc; Martin, Patrick; Progler, Chris

2005-11-01

Intensity imbalance between the 0 and π phase features of c:PSM cause gate CD control and edge placement problems. Strategies such as undercut, selective biasing, and combinations of undercut and bias are currently used in production to mitigate these problems. However, there are drawbacks to these strategies such as space CD delta through pitch, gate CD control through defocus, design rule restrictions, and reticle manufacturability. This paper investigates the application of an innovative films-based approach to intensity balancing known as the Transparent Etch Stop Layer (TESL). TESL, in addition to providing a host of reticle quality and manufacturability benefits, also can be tuned to significantly reduce imbalance. Rigorous 3D vector simulations and experimental data compare through pitch and defocus performance of TESL and conventional c:PSM for 65nm design rules.

A Pearson Effective Potential for Monte Carlo Simulation of Quantum Confinement Effects in nMOSFETs

NASA Astrophysics Data System (ADS)

Jaud, Marie-Anne; Barraud, Sylvain; Saint-Martin, Jérôme; Bournel, Arnaud; Dollfus, Philippe; Jaouen, Hervé

2008-12-01

A Pearson Effective Potential model for including quantization effects in the simulation of nanoscale nMOSFETs has been developed. This model, based on a realistic description of the function representing the non zero-size of the electron wave packet, has been used in a Monte-Carlo simulator for bulk, single gate SOI and double-gate SOI devices. In the case of SOI capacitors, the electron density has been computed for a large range of effective field (between 0.1 MV/cm and 1 MV/cm) and for various silicon film thicknesses (between 5 nm and 20 nm). A good agreement with the Schroedinger-Poisson results is obtained both on the total inversion charge and on the electron density profiles. The ability of an Effective Potential approach to accurately reproduce electrostatic quantum confinement effects is clearly demonstrated.

An Al₂O₃ Gating Substrate for the Greater Performance of Field Effect Transistors Based on Two-Dimensional Materials.

PubMed

Yang, Hang; Qin, Shiqiao; Zheng, Xiaoming; Wang, Guang; Tan, Yuan; Peng, Gang; Zhang, Xueao

2017-09-22

We fabricated 70 nm Al₂O₃ gated field effect transistors based on two-dimensional (2D) materials and characterized their optical and electrical properties. Studies show that the optical contrast of monolayer graphene on an Al₂O₃/Si substrate is superior to that on a traditional 300 nm SiO₂/Si substrate (2.4 times). Significantly, the transconductance of monolayer graphene transistors on the Al₂O₃/Si substrate shows an approximately 10-fold increase, due to a smaller dielectric thickness and a higher dielectric constant. Furthermore, this substrate is also suitable for other 2D materials, such as WS₂, and can enhance the transconductance remarkably by 61.3 times. These results demonstrate a new and ideal substrate for the fabrication of 2D materials-based electronic logic devices.

Radiation testing campaign results for understanding the suitability of FPGAs in detector electronics

DOE PAGES

Citterio, M.; Camplani, A.; Cannon, M.; ...

2015-11-19

SRAM based Field Programmable Gate Arrays (FPGAs) have been rarely used in High Energy Physics (HEP) due to their sensitivity to radiation. The last generation of commercial FPGAs based on 28 nm feature size and on Silicon On Insulator (SOI) technologies are more tolerant to radiation to the level that their use in front-end electronics is now feasible. FPGAs provide re-programmability, high-speed computation and fast data transmission through the embedded serial transceivers. They could replace custom application specific integrated circuits in front end electronics in locations with moderate radiation field. Finally, the use of a FPGA in HEP experiments ismore » only limited by our ability to mitigate single event effects induced by the high energy hadrons present in the radiation field.« less

Braiding by Majorana tracking and long-range CNOT gates with color codes

NASA Astrophysics Data System (ADS)

Litinski, Daniel; von Oppen, Felix

2017-11-01

Color-code quantum computation seamlessly combines Majorana-based hardware with topological error correction. Specifically, as Clifford gates are transversal in two-dimensional color codes, they enable the use of the Majoranas' non-Abelian statistics for gate operations at the code level. Here, we discuss the implementation of color codes in arrays of Majorana nanowires that avoid branched networks such as T junctions, thereby simplifying their realization. We show that, in such implementations, non-Abelian statistics can be exploited without ever performing physical braiding operations. Physical braiding operations are replaced by Majorana tracking, an entirely software-based protocol which appropriately updates the Majoranas involved in the color-code stabilizer measurements. This approach minimizes the required hardware operations for single-qubit Clifford gates. For Clifford completeness, we combine color codes with surface codes, and use color-to-surface-code lattice surgery for long-range multitarget CNOT gates which have a time overhead that grows only logarithmically with the physical distance separating control and target qubits. With the addition of magic state distillation, our architecture describes a fault-tolerant universal quantum computer in systems such as networks of tetrons, hexons, or Majorana box qubits, but can also be applied to nontopological qubit platforms.

Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory; Edmonds, Larry D.; Swift, Gary; Carmichael, Carl; Tseng, Chen Wei; Heldt, Kevin; Anderson, Scott Arlo; Coe, Michael

2010-01-01

We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilins Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.

Switches from pi- to sigma-bonding complexes controlled by gate voltages.

PubMed

Matsui, Eriko; Harnack, Oliver; Matsuzawa, Nobuyuki N; Yasuda, Akio

2005-10-01

A conjugated polymer/metal ion/liquid-crystal molecular system was set between source and drain electrodes with a 100 nm gap. When gate voltage (Vg) increases, the current between source and drain electrodes increases. Infrared spectra show this system to be composed of pi and sigma complexes. At Vg = 0, the pi complex dominates the sigma complex, whereas the sigma complex becomes dominant when Vg is switched on. Calculations found that the pi complex has lower conductivity than the sigma complex.

A smart temperature and magnetic-responsive gating carbon nanotube membrane for ion and protein transportation

PubMed Central

Cong, Hailin; Xu, Xiaodan; Yu, Bing; Yang, Zhaohui; Zhang, Xiaoyan

2016-01-01

Carbon nanotube (CNT) nanoporous membranes based on pre-aligned CNTs have superior nano-transportation properties in biological science. Herein, we report a smart temperature- and temperature-magnetic-responsive CNT nanoporous membrane (CNM) by grafting thermal-sensitive poly(N-isopropylacrylamide) (PNIPAM) and Fe3O4 nanoparticles (Fe3O4-NPs) on the open ends of pre-aligned CNTs with a diameter around 15 nm via surface-initiated atom transfer radical polymerization (SI-ATRP) method. The inner cavity of the modified CNTs in the membrane is designed to be the only path for ion and protein transportation, and its effective diameter with a variation from ~5.7 nm to ~12.4 nm can be reversible tuned by temperature and magnetic field. The PNIPAM modified CNM (PNIPAM-CNM) and PNIPAM magnetic nanoparticles modified CNM (PNIPAM-MAG-CNM) exhibit excellent temperature- or temperature-magnetic-responsive gating property to separate proteins of different sizes. The PNIPAM-CNMs and PNIPAM-MAG-CNMs have potential applications in making artificial cells, biosensors, bioseparation and purification filters. PMID:27535103

A Cu²⁺-selective fluorescent chemosensor based on BODIPY with two pyridine ligands and logic gate.

PubMed

Huang, Liuqian; Zhang, Jing; Yu, Xiaoxiu; Ma, Yifan; Huang, Tianjiao; Shen, Xi; Qiu, Huayu; He, Xingxing; Yin, Shouchun

2015-06-15

A novel near-infrared fluorescent chemosensor based on BODIPY (Py-1) has been synthesized and characterized. Py-1 displays high selectivity and sensitivity for sensing Cu(2+) over other metal ions in acetonitrile. Upon addition of Cu(2+) ions, the maximum absorption band of Py-1 in CH3CN displays a red shift from 603 to 608 nm, which results in a visual color change from pink to blue. When Py-1 is excited at 600 nm in the presence of Cu(2+), the fluorescent emission intensity of Py-1 at 617 nm is quenched over 86%. Notably, the complex of Py-1-Cu(2+) can be restored with the introduction of EDTA or S(2-). Consequently, an IMPLICATION logic gate at molecular level operating in fluorescence mode with Cu(2+) and S(2-) as chemical inputs can be constructed. Finally, based on the reversible and reproducible system, a nanoscale sequential memory unit displaying "Writing-Reading-Erasing-Reading" functions can be integrated. Copyright © 2015 Elsevier B.V. All rights reserved.

The active modulation of drug release by an ionic field effect transistor for an ultra-low power implantable nanofluidic system.

PubMed

Bruno, Giacomo; Canavese, Giancarlo; Liu, Xuewu; Filgueira, Carly S; Sacco, Adriano; Demarchi, Danilo; Ferrari, Mauro; Grattoni, Alessandro

2016-11-10

We report an electro-nanofluidic membrane for tunable, ultra-low power drug delivery employing an ionic field effect transistor. Therapeutic release from a drug reservoir was successfully modulated, with high energy efficiency, by actively adjusting the surface charge of slit-nanochannels 50, 110, and 160 nm in size, by the polarization of a buried gate electrode and the consequent variation of the electrical double layer in the nanochannel. We demonstrated control over the transport of ionic species, including two relevant hypertension drugs, atenolol and perindopril, that could benefit from such modulation. By leveraging concentration-driven diffusion, we achieve a 2 to 3 order of magnitude reduction in power consumption as compared to other electrokinetic phenomena. The application of a small gate potential (±5 V) in close proximity (150 nm) of 50 nm nanochannels generated a sufficiently strong electric field, which doubled or blocked the ionic flux depending on the polarity of the voltage applied. These compelling findings can lead to next generation, more reliable, smaller, and longer lasting drug delivery implants with ultra-low power consumption.

UV-light-induced one-color and two-color photorefractive effects in congruent and near-stoichiometric LiNbO 3:Mg crystals

NASA Astrophysics Data System (ADS)

Qiao, Haijun; Xu, Jingjun; Tomita, Yasuo; Zhu, Dengsong; Fu, Bo; Zhang, Guoquan; Zhang, Guangyin

2007-03-01

We describe the ultraviolet-light one-color photorefraction (UV-OPR) at 351 nm in LiNbO3 crystals with different Mg-doping concentrations and [Li]/[Nb] ratios. It is shown that as the Mg-doping concentration and/or the [Li]/[Nb] ratio increase, the refractive index change and the two-beam coupling gain increase but the response time decreases. It is also shown that the recording sensitivity as large as ∼27 cm/J is obtainable at a recording intensity of ∼1 W/cm2 in near-stoichiometric LiNbO3 doped with 2 mol% Mg. This sensitivity is approximately one order of magnitude higher than those for other LiNbO3 crystals. We also describe the ultraviolet-light-gating two-color photorefraction (UV-TPR) using 365 nm gating and 633 nm recording beams in LiNbO3 crystals with different Mg-doping concentrations and [Li]/[Nb] ratios. It is shown that UV-TPR is only observed in near-stoichiometric crystals and the grating-formation dynamics strongly depend on the Mg concentration.

Analysis of e-beam impact on the resist stack in e-beam lithography process

NASA Astrophysics Data System (ADS)

Indykeiwicz, K.; Paszkiewicz, B.

2013-07-01

Paper presents research on the sub-micron gate, AlGaN /GaN HEMT type transistors, fabrication by e-beam lithography and lift-off technique. The impact of the electron beam on the resists layer and the substrate was analyzed by MC method in Casino v3.2 software. The influence of technological process parameters on the metal structures resolution and quality for paths 100 nm, 300 nm and 500 nm wide and 20 μm long was studied. Qualitative simulation correspondences to the conducted experiments were obtained.

Single layer of Ge quantum dots in HfO2 for floating gate memory capacitors.

PubMed

Lepadatu, A M; Palade, C; Slav, A; Maraloiu, A V; Lazanu, S; Stoica, T; Logofatu, C; Teodorescu, V S; Ciurea, M L

2017-04-28

High performance trilayer memory capacitors with a floating gate of a single layer of Ge quantum dots (QDs) in HfO 2 were fabricated using magnetron sputtering followed by rapid thermal annealing (RTA). The layer sequence of the capacitors is gate HfO 2 /floating gate of single layer of Ge QDs in HfO 2 /tunnel HfO 2 /p-Si wafers. Both Ge and HfO 2 are nanostructured by RTA at moderate temperatures of 600-700 °C. By nanostructuring at 600 °C, the formation of a single layer of well separated Ge QDs with diameters of 2-3 nm at a density of 4-5 × 10 15 m -2 is achieved in the floating gate (intermediate layer). The Ge QDs inside the intermediate layer are arranged in a single layer and are separated from each other by HfO 2 nanocrystals (NCs) about 8 nm in diameter with a tetragonal/orthorhombic structure. The Ge QDs in the single layer are located at the crossing of the HfO 2 NCs boundaries. In the intermediate layer, besides Ge QDs, a part of the Ge atoms is segregated by RTA at the HfO 2 NCs boundaries, while another part of the Ge atoms is present inside the HfO 2 lattice stabilizing the tetragonal/orthorhombic structure. The fabricated capacitors show a memory window of 3.8 ± 0.5 V and a capacitance-time characteristic with 14% capacitance decay in the first 3000-4000 s followed by a very slow capacitance decrease extrapolated to 50% after 10 years. This high performance is mainly due to the floating gate of a single layer of well separated Ge QDs in HfO 2 , distanced from the Si substrate by the tunnel oxide layer with a precise thickness.

Fabrication of 80-nm T-gate high indium In0.7Ga0.3As/In0.6Ga0.4As composite channels mHEMT on GaAs substrate with simple technological process

NASA Astrophysics Data System (ADS)

Xian, Ji; Xiaodong, Zhang; Weihua, Kang; Zhili, Zhang; Jiahui, Zhou; Wenjun, Xu; Qi, Li; Gongli, Xiao; Zhijun, Yin; Yong, Cai; Baoshun, Zhang; Haiou, Li

2016-02-01

An 80-nm gate length metamorphic high electron mobility transistor (mHEMT) on a GaAs substrate with high indium composite compound-channels In0.7Ga0.3 As/In0.6Ga0.4 As and an optimized grade buffer scheme is presented. High 2-DEG Hall mobility values of 10200 cm2/(V·s) and a sheet density of 3.5 × 1012 cm-2 at 300 K have been achieved. The device's T-shaped gate was made by utilizing a simple three layers electron beam resist, instead of employing a passivation layer for the T-share gate, which is beneficial to decreasing parasitic capacitance and parasitic resistance of the gate and simplifying the device manufacturing process. The ohmic contact resistance Rc is 0.2 ω·mm when using the same metal system with the gate (Pt/Ti/Pt/Au), which reduces the manufacturing cycle of the device. The mHEMT device demonstrates excellent DC and RF characteristics. The peak extrinsic transconductance of 1.1 S/mm and the maximum drain current density of 0.86 A/mm are obtained. The unity current gain cut-off frequency (fT) and the maximum oscillation frequency (fmax) are 246 and 301 GHz, respectively. Project supported by the Key Laboratory of Nano-Devices and Applications, Nano-Fabrication Facility of SINANO, Chinese Academy of Sciences, the National Natural Science Foundation of China (Nos. 61274077, 61474031, 61464003), the Guangxi Natural Science Foundation (Nos. 2013GXNSFGA019003, 2013GXNSFAA019335), the National Basic Research Program of China (Nos. 2011CBA00605, 2010CB327501), the Project (No. 9140C140101140C14069), and the Innovation Project of GUET Graduate Education (Nos. GDYCSZ201448, GDYCSZ201449, YJCXS201529).

Twenty Years of Rad-Hard K14 SPAD in Space Projects

PubMed Central

Michálek, Vojtěch; Procházka, Ivan; Blažej, Josef

2015-01-01

During last two decades, several photon counting detectors have been developed in our laboratory. One of the most promising detector coming from our group silicon K14 Single Photon Avalanche Diode (SPAD) is presented with its valuable features and space applications. Based on the control electronics, it can be operated in both gated and non-gated mode. Although it was designed for photon counting detection, it can be employed for multiphoton detection as well. With respect to control electronics employed, the timing jitter can be as low as 20 ps RMS. Detection efficiency is about 40 % in range of 500 nm to 800 nm. The detector including gating and quenching circuitry has outstanding timing stability. Due to its radiation resistivity, the diode withstands 100 krad gamma ray dose without parameters degradation. Single photon detectors based on K14 SPAD were used for planetary altimeter and atmospheric lidar in MARS92/96 and Mars Surveyor ’98 space projects, respectively. Recent space applications of K14 SPAD comprises LIDAR and mainly time transfer between ground stations and artificial satellites. These include Laser Time Transfer, Time Transfer by Laser Link, and European Laser Timing projects. PMID:26213945

All-Aluminum Thin Film Transistor Fabrication at Room Temperature

PubMed Central

Yao, Rihui; Zheng, Zeke; Zeng, Yong; Liu, Xianzhe; Ning, Honglong; Hu, Shiben; Tao, Ruiqiang; Chen, Jianqiu; Cai, Wei; Xu, Miao; Wang, Lei; Lan, Linfeng; Peng, Junbiao

2017-01-01

Bottom-gate all-aluminum thin film transistors with multi conductor/insulator nanometer heterojunction were investigated in this article. Alumina (Al2O3) insulating layer was deposited on the surface of aluminum doping zinc oxide (AZO) conductive layer, as one AZO/Al2O3 heterojunction unit. The measurements of transmittance electronic microscopy (TEM) and X-ray reflectivity (XRR) revealed the smooth interfaces between ~2.2-nm-thick Al2O3 layers and ~2.7-nm-thick AZO layers. The devices were entirely composited by aluminiferous materials, that is, their gate and source/drain electrodes were respectively fabricated by aluminum neodymium alloy (Al:Nd) and pure Al, with Al2O3/AZO multilayered channel and AlOx:Nd gate dielectric layer. As a result, the all-aluminum TFT with two Al2O3/AZO heterojunction units exhibited a mobility of 2.47 cm2/V·s and an Ion/Ioff ratio of 106. All processes were carried out at room temperature, which created new possibilities for green displays industry by allowing for the devices fabricated on plastic-like substrates or papers, mainly using no toxic/rare materials. PMID:28772579

Dual-gate photo thin-film transistor: a “smart” pixel for high- resolution and low-dose X-ray imaging

NASA Astrophysics Data System (ADS)

Wang, Kai; Ou, Hai; Chen, Jun

2015-06-01

Since its emergence a decade ago, amorphous silicon flat panel X-ray detector has established itself as a ubiquitous platform for an array of digital radiography modalities. The fundamental building block of a flat panel detector is called a pixel. In all current pixel architectures, sensing, storage, and readout are unanimously kept separate, inevitably compromising resolution by increasing pixel size. To address this issue, we hereby propose a “smart” pixel architecture where the aforementioned three components are combined in a single dual-gate photo thin-film transistor (TFT). In other words, the dual-gate photo TFT itself functions as a sensor, a storage capacitor, and a switch concurrently. Additionally, by harnessing the amplification effect of such a thin-film transistor, we for the first time created a single-transistor active pixel sensor. The proof-of-concept device had a W/L ratio of 250μm/20μm and was fabricated using a simple five-mask photolithography process, where a 130nm transparent ITO was used as the top photo gate, and a 200nm amorphous silicon as the absorbing channel layer. The preliminary results demonstrated that the photocurrent had been increased by four orders of magnitude due to light-induced threshold voltage shift in the sub-threshold region. The device sensitivity could be simply tuned by photo gate bias to specifically target low-level light detection. The dependence of threshold voltage on light illumination indicated that a dynamic range of at least 80dB could be achieved. The "smart" pixel technology holds tremendous promise for developing high-resolution and low-dose X-ray imaging and may potentially lower the cancer risk imposed by radiation, especially among paediatric patients.

Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

NASA Astrophysics Data System (ADS)

Dentoni Litta, E.; Hellström, P.-E.; Östling, M.

2015-06-01

High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

Radiation sensors based on the generation of mobile protons in organic dielectrics.

PubMed

Kapetanakis, Eleftherios; Douvas, Antonios M; Argitis, Panagiotis; Normand, Pascal

2013-06-26

A sensing scheme based on mobile protons generated by radiation, including ionizing radiation (IonR), in organic gate dielectrics is investigated for the development of metal-insulator-semiconductor (MIS)-type dosimeters. Application of an electric field to the gate dielectric moves the protons and thereby alters the flat band voltage (VFB) of the MIS device. The shift in the VFB is proportional to the IonR-generated protons and, therefore, to the IonR total dose. Triphenylsulfonium nonaflate (TPSNF) photoacid generator (PAG)-containing poly(methyl methacrylate) (PMMA) polymeric films was selected as radiation-sensitive gate dielectrics. The effects of UV (249 nm) and gamma (Co-60) irradiations on the high-frequency capacitance versus the gate voltage (C-VG) curves of the MIS devices were investigated for different total dose values. Systematic improvements in sensitivity can be accomplished by increasing the concentration of the TPSNF molecules embedded in the polymeric matrix.

Formation of nanofilament field emission devices

DOEpatents

Morse, Jeffrey D.; Contolini, Robert J.; Musket, Ronald G.; Bernhardt, Anthony F.

2000-01-01

A process for fabricating a nanofilament field emission device. The process enables the formation of high aspect ratio, electroplated nanofilament structure devices for field emission displays wherein a via is formed in a dielectric layer and is self-aligned to a via in the gate metal structure on top of the dielectric layer. The desired diameter of the via in the dielectric layer is on the order of 50-200 nm, with an aspect ratio of 5-10. In one embodiment, after forming the via in the dielectric layer, the gate metal is passivated, after which a plating enhancement layer is deposited in the bottom of the via, where necessary. The nanofilament is then electroplated in the via, followed by removal of the gate passification layer, etch back of the dielectric, and sharpening of the nanofilament. A hard mask layer may be deposited on top of the gate metal and removed following electroplating of the nanofilament.

Electro-Optic Frequency Beam Splitters and Tritters for High-Fidelity Photonic Quantum Information Processing

DOE PAGES

Lu, Hsuan-Hao; Lukens, Joseph M.; Peters, Nicholas A.; ...

2018-01-18

In this paper, we report the experimental realization of high-fidelity photonic quantum gates for frequency-encoded qubits and qutrits based on electro-optic modulation and Fourier-transform pulse shaping. Our frequency version of the Hadamard gate offers near-unity fidelity (0.99998±0.00003), requires only a single microwave drive tone for near-ideal performance, functions across the entire C band (1530–1570 nm), and can operate concurrently on multiple qubits spaced as tightly as four frequency modes apart, with no observable degradation in the fidelity. For qutrits, we implement a 3×3 extension of the Hadamard gate: the balanced tritter. This tritter—the first ever demonstrated for frequency modes—attains fidelitymore » 0.9989±0.0004. Finally, these gates represent important building blocks toward scalable, high-fidelity quantum information processing based on frequency encoding.« less

Electro-Optic Frequency Beam Splitters and Tritters for High-Fidelity Photonic Quantum Information Processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Hsuan-Hao; Lukens, Joseph M.; Peters, Nicholas A.

In this paper, we report the experimental realization of high-fidelity photonic quantum gates for frequency-encoded qubits and qutrits based on electro-optic modulation and Fourier-transform pulse shaping. Our frequency version of the Hadamard gate offers near-unity fidelity (0.99998±0.00003), requires only a single microwave drive tone for near-ideal performance, functions across the entire C band (1530–1570 nm), and can operate concurrently on multiple qubits spaced as tightly as four frequency modes apart, with no observable degradation in the fidelity. For qutrits, we implement a 3×3 extension of the Hadamard gate: the balanced tritter. This tritter—the first ever demonstrated for frequency modes—attains fidelitymore » 0.9989±0.0004. Finally, these gates represent important building blocks toward scalable, high-fidelity quantum information processing based on frequency encoding.« less

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

NASA Astrophysics Data System (ADS)

Suarez, Ernesto; Chan, Pik-Yiu; Lingalugari, Murali; Ayers, John E.; Heller, Evan; Jain, Faquir

2013-11-01

This paper describes the use of II-VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II-VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

Use of laser drilling in the manufacture of organic inverter circuits.

PubMed

Iba, Shingo; Kato, Yusaku; Sekitani, Tsuyoshi; Kawaguchi, Hiroshi; Sakurai, Takayasu; Someya, Takao

2006-01-01

Inverter circuits have been made by connecting two high-quality pentacene field-effect transistors. A uniform and pinhole-free 900 nm thick polyimide gate-insulating layer was formed on a flexible polyimide film with gold gate electrodes and partially removed by using a CO2 laser drilling machine to make via holes and contact holes. Subsequent evaporation of the gold layer results in good electrical connection with a gold gate layer underneath the gate-insulating layer. By optimization of the settings of the CO2 laser drilling machine, contact resistance can be reduced to as low as 3 ohms for 180 microm square electrodes. No degradation of the transport properties of the organic transistors was observed after the laser-drilling process. This study demonstrates the feasibility of using the laser drilling process for implementation of organic transistors in integrated circuits on flexible polymer films.

Electron density and currents of AlN/GaN high electron mobility transistors with thin GaN/AlN buffer layer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bairamis, A.; Zervos, Ch.; Georgakilas, A., E-mail: alexandr@physics.uoc.gr

2014-09-15

AlN/GaN high electron mobility transistor (HEMT) structures with thin GaN/AlN buffer layer have been analyzed theoretically and experimentally, and the effects of the AlN barrier and GaN buffer layer thicknesses on two-dimensional electron gas (2DEG) density and transport properties have been evaluated. HEMT structures consisting of [300 nm GaN/ 200 nm AlN] buffer layer on sapphire were grown by plasma-assisted molecular beam epitaxy and exhibited a remarkable agreement with the theoretical calculations, suggesting a negligible influence of the crystalline defects that increase near the heteroepitaxial interface. The 2DEG density varied from 6.8 × 10{sup 12} to 2.1 × 10{sup 13} cm{sup −2} as themore » AlN barrier thickness increased from 2.2 to 4.5 nm, while a 4.5 nm AlN barrier would result to 3.1 × 10{sup 13} cm{sup −2} on a GaN buffer layer. The 3.0 nm AlN barrier structure exhibited the highest 2DEG mobility of 900 cm{sup 2}/Vs for a density of 1.3 × 10{sup 13} cm{sup −2}. The results were also confirmed by the performance of 1 μm gate-length transistors. The scaling of AlN barrier thickness from 1.5 nm to 4.5 nm could modify the drain-source saturation current, for zero gate-source voltage, from zero (normally off condition) to 0.63 A/mm. The maximum drain-source current was 1.1 A/mm for AlN barrier thickness of 3.0 nm and 3.7 nm, and the maximum extrinsic transconductance was 320 mS/mm for 3.0 nm AlN barrier.« less

Fast photomultiplier tube gating system for underwater laser detector

NASA Astrophysics Data System (ADS)

Lei, Xuanhua; Yang, Kecheng; Rao, Jionghui; Zhang, Xiaohui; Xia, Min; Zheng, Yi; Li, Wei

2007-01-01

Laser will attenuate during its propagation in water and also be backward scattered by water when it is used to detect bubbles in the ocean. Meanwhile backward scattering intensity of the bubbles is feeble, its dynamic range reaches to the order of 6, which saturates PMT and its post-treatment circuit. Timely gating system is used to solve the problem. The system contains pulsed laser and gating PMT receiver. The wavelength of the laser is 532nm, with pulse width of several nanometers. Its operational delay is matched with the time period between laser traveling forward and back after scattered by the target. By doing this, the light scattered by other object is eliminated, dynamic range of the signal reduces, and consequently SNR increases. In order to avoid Signal Induced Noise(SIN), we choose PMT R1333 having no HA coating. TTL logical level, which is used as gating signal, controls the first dynode voltage of PMT to implement gating. Gating speed is about 100ns, of which the width is tunable. By carefully designing the electronic system, SNR is eliminated to a level as low as possible, and the output signal of PMT is fast integrated in order to reduce the influences of signal induced by opening the gate.

Slowing DNA Translocation in a Nanofluidic Field-Effect Transistor.

PubMed

Liu, Yifan; Yobas, Levent

2016-04-26

Here, we present an experimental demonstration of slowing DNA translocation across a nanochannel by modulating the channel surface charge through an externally applied gate bias. The experiments were performed on a nanofluidic field-effect transistor, which is a monolithic integrated platform featuring a 50 nm-diameter in-plane alumina nanocapillary whose entire length is surrounded by a gate electrode. The field-effect transistor behavior was validated on the gating of ionic conductance and protein transport. The gating of DNA translocation was subsequently studied by measuring discrete current dips associated with single λ-DNA translocation events under a source-to-drain bias of 1 V. The translocation speeds under various gate bias conditions were extracted by fitting event histograms of the measured translocation time to the first passage time distributions obtained from a simple 1D biased diffusion model. A positive gate bias was observed to slow the translocation of single λ-DNA chains markedly; the translocation speed was reduced by an order of magnitude from 18.4 mm/s obtained under a floating gate down to 1.33 mm/s under a positive gate bias of 9 V. Therefore, a dynamic and flexible regulation of the DNA translocation speed, which is vital for single-molecule sequencing, can be achieved on this device by simply tuning the gate bias. The device is realized in a conventional semiconductor microfabrication process without the requirement of advanced lithography, and can be potentially further developed into a compact electronic single-molecule sequencer.

Air-gating and chemical-gating in transistors and sensing devices made from hollow TiO2 semiconductor nanotubes

NASA Astrophysics Data System (ADS)

Alivov, Yahya; Funke, Hans; Nagpal, Prashant

2015-07-01

Rapid miniaturization of electronic devices down to the nanoscale, according to Moore’s law, has led to some undesirable effects like high leakage current in transistors, which can offset additional benefits from scaling down. Development of three-dimensional transistors, by spatial extension in the third dimension, has allowed higher contact area with a gate electrode and better control over conductivity in the semiconductor channel. However, these devices do not utilize the large surface area and interfaces for new electronic functionality. Here, we demonstrate air gating and chemical gating in hollow semiconductor nanotube devices and highlight the potential for development of novel transistors that can be modulated using channel bias, gate voltage, chemical composition, and concentration. Using chemical gating, we reversibly altered the conductivity of nanoscaled semiconductor nanotubes (10-500 nm TiO2 nanotubes) by six orders of magnitude, with a tunable rectification factor (ON/OFF ratio) ranging from 1-106. While demonstrated air- and chemical-gating speeds were slow here (˜seconds) due to the mechanical-evacuation rate and size of our chamber, the small nanoscale volume of these hollow semiconductors can enable much higher switching speeds, limited by the rate of adsorption/desorption of molecules at semiconductor interfaces. These chemical-gating effects are completely reversible, additive between different chemical compositions, and can enable semiconductor nanoelectronic devices for ‘chemical transistors’, ‘chemical diodes’, and very high-efficiency sensing applications.

Scheme for Quantum Computing Immune to Decoherence

NASA Technical Reports Server (NTRS)

Williams, Colin; Vatan, Farrokh

2008-01-01

A constructive scheme has been devised to enable mapping of any quantum computation into a spintronic circuit in which the computation is encoded in a basis that is, in principle, immune to quantum decoherence. The scheme is implemented by an algorithm that utilizes multiple physical spins to encode each logical bit in such a way that collective errors affecting all the physical spins do not disturb the logical bit. The scheme is expected to be of use to experimenters working on spintronic implementations of quantum logic. Spintronic computing devices use quantum-mechanical spins (typically, electron spins) to encode logical bits. Bits thus encoded (denoted qubits) are potentially susceptible to errors caused by noise and decoherence. The traditional model of quantum computation is based partly on the assumption that each qubit is implemented by use of a single two-state quantum system, such as an electron or other spin-1.2 particle. It can be surprisingly difficult to achieve certain gate operations . most notably, those of arbitrary 1-qubit gates . in spintronic hardware according to this model. However, ironically, certain 2-qubit interactions (in particular, spin-spin exchange interactions) can be achieved relatively easily in spintronic hardware. Therefore, it would be fortunate if it were possible to implement any 1-qubit gate by use of a spin-spin exchange interaction. While such a direct representation is not possible, it is possible to achieve an arbitrary 1-qubit gate indirectly by means of a sequence of four spin-spin exchange interactions, which could be implemented by use of four exchange gates. Accordingly, the present scheme provides for mapping any 1-qubit gate in the logical basis into an equivalent sequence of at most four spin-spin exchange interactions in the physical (encoded) basis. The complexity of the mathematical derivation of the scheme from basic quantum principles precludes a description within this article; it must suffice to report that the derivation provides explicit constructions for finding the exchange couplings in the physical basis needed to implement any arbitrary 1-qubit gate. These constructions lead to spintronic encodings of quantum logic that are more efficient than those of a previously published scheme that utilizes a universal but fixed set of gates.

Optimization of fluorescent imaging in the operating room through pulsed acquisition and gating to ambient background cycling

PubMed Central

Sexton, Kristian J.; Zhao, Yan; Davis, Scott C.; Jiang, Shudong; Pogue, Brian W.

2017-01-01

The design of fluorescence imaging instruments for surgical guidance is rapidly evolving, and a key issue is to efficiently capture signals with high ambient room lighting. Here, we introduce a novel time-gated approach to fluorescence imaging synchronizing acquisition to the 120 Hz light of the room, with pulsed LED excitation and gated ICCD detection. It is shown that under bright ambient room light this technique allows for the detection of physiologically relevant nanomolar fluorophore concentrations, and in particular reduces the light fluctuations present from the room lights, making low concentration measurements more reliable. This is particularly relevant for the light bands near 700nm that are more dominated by ambient lights. PMID:28663895

Biomimetic glass nanopores employing aptamer gates responsive to a small molecule†

PubMed Central

Abelow, Alexis E.; Schepelina, Olga; White, Ryan J.; Vallée-Bélisle, Alexis

2011-01-01

We report the preparation of 20 and 65 nm radii glass nanopores whose surface is modified with DNA aptamers controlling the molecular transport through the nanopores in response to small molecule binding. PMID:20865192

Wavelength dependence and multiple-induced states in photoresponses of copper phthalocyanine-doped gold nanoparticle single-electron device

NASA Astrophysics Data System (ADS)

Yamamoto, Makoto; Ueda, Rieko; Terui, Toshifumi; Imazu, Keisuke; Tamada, Kaoru; Sakano, Takeshi; Matsuda, Kenji; Ishii, Hisao; Noguchi, Yutaka

2014-01-01

We have proposed a gold nanoparticle (GNP)-based single-electron transistor (SET) doped with a dye molecule, where the molecule works as a photoresponsive floating gate. Here, we examined the source-drain current (I_{\\text{SD}}) at a constant drain voltage under light irradiation with various wavelengths ranging from 400 to 700 nm. Current change was enhanced at the wavelengths of 600 and 700 nm, corresponding to the optical absorption band of the doped molecule (copper phthalocyanine: CuPc). Moreover, several peaks appear in the histograms of I_{\\text{SD}} during light irradiation, indicating that multiple discrete states were induced in the device. The results suggest that the current change was initiated by the light absorption of CuPc and multiple CuPc molecules near the GNP working as a floating gate. Molecular doping can activate advanced device functions in GNP-based SETs.

High-Performance InGaAs/InP Composite-Channel High Electron Mobility Transistors Grown by Metal-Organic Vapor-Phase Epitaxy

NASA Astrophysics Data System (ADS)

Sugiyama, Hiroki; Kosugi, Toshihiko; Yokoyama, Haruki; Murata, Koichi; Yamane, Yasuro; Tokumitsu, Masami; Enoki, Takatomo

2008-04-01

This paper reports InGaAs/InP composite-channel (CC) high electron mobility transistors (HEMTs) grown by metal-organic vapor-phase epitaxy (MOVPE) with excellent breakdown and high-speed characteristics. Atomic force microscopy (AFM) reveals high-quality heterointerfaces between In(Ga,Al)As and In(Al)P. Fabricated 80-nm-gate CC HEMTs exhibit on- and off-state breakdown (burnout) voltages estimated at higher than 3 and 8 V. An excellent current-gain cutoff frequency ( fT) of 186 GHz is also obtained in the CC HEMTs. The on-wafer uniformity of CC-HEMT characteristics is comparable to those of our mature 100-nm-gate InGaAs single-channel HEMTs. Bias-stress aging tests reveals that the lifetime of CC HEMTs is expected to be comparable to that of our conventional InGaAs single-channel HEMTs.

The fundamental downscaling limit of field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mamaluy, Denis, E-mail: mamaluy@sandia.gov; Gao, Xujiao

2015-05-11

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increasemore » in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.« less

The fundamental downscaling limit of field effect transistors

DOE PAGES

Mamaluy, Denis; Gao, Xujiao

2015-05-12

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increasemore » in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.« less

Reduced distribution of threshold voltage shift in double layer NiSi2 nanocrystals for nano-floating gate memory applications.

PubMed

Choi, Sungjin; Lee, Junhyuk; Kim, Donghyoun; Oh, Seulki; Song, Wangyu; Choi, Seonjun; Choi, Eunsuk; Lee, Seung-Beck

2011-12-01

We report on the fabrication and capacitance-voltage characteristics of double layer nickel-silicide nanocrystals with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO2 interlayer, the use of Si3N4 interlayer separation reduced the average size (4 nm) and distribution (+/- 2.5 nm) of NiSi2 nanocrystal (NC) charge traps by more than 50% and giving a two fold increase in NC density to 2.3 x 10(12) cm(-2). The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C-V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50% on average to less than 0.7 V demonstrating possible multi-level-cell operation.

Adhesion layer for etching of tracks in nuclear trackable materials

DOEpatents

Morse, Jeffrey D.; Contolini, Robert J.

2001-01-01

A method for forming nuclear tracks having a width on the order of 100-200 nm in nuclear trackable materials, such as polycarbonate (LEXAN) without causing delamination of the LEXAN. The method utilizes an adhesion film having a inert oxide which allows the track to be sufficiently widened to >200 nm without delamination of the nuclear trackable materials. The adhesion film may be composed of a metal such as Cr, Ni, Au, Pt, or Ti, or composed of a dielectric having a stable surface, such as silicon dioxide (SiO.sub.2), silicon nitride (SiN.sub.x), and aluminum oxide (AlO). The adhesion film can either be deposited on top of the gate metal layer, or if the properties of the adhesion film are adequate, it can be used as the gate layer. Deposition of the adhesion film is achieved by standard techniques, such as sputtering or evaporation.

An Al2O3 Gating Substrate for the Greater Performance of Field Effect Transistors Based on Two-Dimensional Materials

PubMed Central

Zheng, Xiaoming; Wang, Guang; Tan, Yuan; Zhang, Xueao

2017-01-01

We fabricated 70 nm Al2O3 gated field effect transistors based on two-dimensional (2D) materials and characterized their optical and electrical properties. Studies show that the optical contrast of monolayer graphene on an Al2O3/Si substrate is superior to that on a traditional 300 nm SiO2/Si substrate (2.4 times). Significantly, the transconductance of monolayer graphene transistors on the Al2O3/Si substrate shows an approximately 10-fold increase, due to a smaller dielectric thickness and a higher dielectric constant. Furthermore, this substrate is also suitable for other 2D materials, such as WS2, and can enhance the transconductance remarkably by 61.3 times. These results demonstrate a new and ideal substrate for the fabrication of 2D materials-based electronic logic devices. PMID:28937619

A modular design of molecular qubits to implement universal quantum gates

PubMed Central

Ferrando-Soria, Jesús; Moreno Pineda, Eufemio; Chiesa, Alessandro; Fernandez, Antonio; Magee, Samantha A.; Carretta, Stefano; Santini, Paolo; Vitorica-Yrezabal, Iñigo J.; Tuna, Floriana; Timco, Grigore A.; McInnes, Eric J.L.; Winpenny, Richard E.P.

2016-01-01

The physical implementation of quantum information processing relies on individual modules—qubits—and operations that modify such modules either individually or in groups—quantum gates. Two examples of gates that entangle pairs of qubits are the controlled NOT-gate (CNOT) gate, which flips the state of one qubit depending on the state of another, and the gate that brings a two-qubit product state into a superposition involving partially swapping the qubit states. Here we show that through supramolecular chemistry a single simple module, molecular {Cr7Ni} rings, which act as the qubits, can be assembled into structures suitable for either the CNOT or gate by choice of linker, and we characterize these structures by electron spin resonance spectroscopy. We introduce two schemes for implementing such gates with these supramolecular assemblies and perform detailed simulations, based on the measured parameters including decoherence, to demonstrate how the gates would operate. PMID:27109358

DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology. [Dual Injector Floating-gate MOS

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1977-01-01

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

A novel approach for the improvement of electrostatic behaviour of physically doped TFET using plasma formation and shortening of gate electrode with hetero-gate dielectric

NASA Astrophysics Data System (ADS)

Soni, Deepak; Sharma, Dheeraj; Aslam, Mohd.; Yadav, Shivendra

2018-04-01

This article presents a new device configuration to enhance current drivability and suppress negative conduction (ambipolar conduction) with improved RF characteristics of physically doped TFET. Here, we used a new approach to get excellent electrical characteristics of hetero-dielectric short gate source electrode TFET (HD-SG SE-TFET) by depositing a metal electrode of 5.93 eV work function over the heavily doped source (P+) region. Deposition of metal electrode induces the plasma (thin layer) of holes under the Si/HfO2 interface due to work function difference of metal and semiconductor. Plasma layer of holes is advantageous to increase abruptness as well as decrease the tunneling barrier at source/channel junction for attaining higher tunneling rate of charge carriers (i.e., electrons), which turns into 86.66 times higher ON-state current compared with the conventional physically doped TFET (C-TFET). Along with metal electrode deposition, gate electrode is under-lapped for inducing asymmetrical concentration of charge carriers in the channel region, which is helpful for widening the tunneling barrier width at the drain/channel interface. Consequently, HD-SG SE-TFET shows suppression of ambipolar behavior with reduction in gate-to-drain capacitance which is beneficial for improvement in RF performance. Furthermore, the effectiveness of hetero-gate dielectric concept has been used for improving the RF performance. Furthermore, reliability of C-TFET and proposed structures has been confirmed in term of linearity.

The Center for Nonlinear Phenomena and Magnetic Materials

DTIC Science & Technology

1992-09-30

ORGANIZATION Howard University REPORT NUMBER ComSERCIWashington DC 20059 AFOSR- ,, ? 9 v 5 4 9. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10... University . Visualization - Improved Marching Cubes. January 27, 1992: Dr. Gerald Chachere, Math Dept., Howard University . "An algorithm for box...James Gates, Physics Department, Howard University . "Introduction to Strings Part I". February 5, 1992: Dr. James Gates, Physics Department, Howard

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

NASA Astrophysics Data System (ADS)

Deen, David A.; Storm, David F.; Scott Katzer, D.; Bass, R.; Meyer, David J.

2016-08-01

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain current after bias stressed in subthreshold. These structures additionally achieved small signal metrics ft/fmax of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with ft/fmax of 48/60 GHz.

Submicron Structures and Various Technology

DTIC Science & Technology

1990-06-01

Replication in PMMA of a 30 nm-wide gold focused-ion-beam lithography alone. We are absorber line with (a) CK (A = 4.5 nm), ( b ) developing a new generation of...into soft x-ray spectroscopy and atom beam contact with the substrate b electrostatic interferometry, and to fabricate new classes means. A variety of...Professor Dimitri A. Antonaidis, Stuart B . Field, drain resistances and gate-source overlaps. Professor Marc A. Kastner, Udi Meirav, Samuel L. This will

Transcending binary logic by gating three coupled quantum dots.

PubMed

Klein, Michael; Rogge, S; Remacle, F; Levine, R D

2007-09-01

Physical considerations supported by numerical solution of the quantum dynamics including electron repulsion show that three weakly coupled quantum dots can robustly execute a complete set of logic gates for computing using three valued inputs and outputs. Input is coded as gating (up, unchanged, or down) of the terminal dots. A nanosecond time scale switching of the gate voltage requires careful numerical propagation of the dynamics. Readout is the charge (0, 1, or 2 electrons) on the central dot.

A Resonant Tunneling Nanowire Field Effect Transistor with Physical Contractions: A Negative Differential Resistance Device for Low Power Very Large Scale Integration Applications

NASA Astrophysics Data System (ADS)

Molaei Imen Abadi, Rouzbeh; Saremi, Mehdi

2018-02-01

In this paper, the influence of ultra-scaled physical symmetrical contraction on electrical characteristics of ultra-thin silicon-on-insulator nanowires with circular gate-all-around structure is investigated by using a 3D Atlas numerical quantum simulator based on non-equilibrium green's function formalism. It is demonstrated that local cross-section variation in a nanowire transistor results in the establishment of tunnel energy barriers at the source-channel and drain-channel junctions which change device physics and cause a transmission from a quantum wire (1-D) to a floating quantum dot nanowire (0-D) introducing a resonant tunneling nanowire FET (RT-NWFET) as an interesting concept of nanoscale MOSFETs. The barriers construct resonance energy levels in the channel region of nanowires because of the longitudinal confinement in three directions causing some fluctuation in I D- V GS characteristic. In addition, these barriers remarkably improve the subthreshold swing and minimize the ON/OFF-current ratio degradation at a low operation voltage of 0.5 V. As a result, RT-NWFETs are intrinsically preserved from drain-source tunneling and are an interesting candidate for developing the roadmap below 10 nm.

Enhanced transconductance in a double-gate graphene field-effect transistor

NASA Astrophysics Data System (ADS)

Hwang, Byeong-Woon; Yeom, Hye-In; Kim, Daewon; Kim, Choong-Ki; Lee, Dongil; Choi, Yang-Kyu

2018-03-01

Multi-gate transistors, such as double-gate, tri-gate and gate-all-around transistors are the most advanced Si transistor structure today. Here, a genuine double-gate transistor with a graphene channel is experimentally demonstrated. The top and bottom gates of the double-gate graphene field-effect transistor (DG GFET) are electrically connected so that the conductivity of the graphene channel can be modulated simultaneously by both the top and bottom gate. A single-gate graphene field-effect transistor (SG GFET) with only the top gate is also fabricated as a control device. For systematical analysis, the transfer characteristics of both GFETs were measured and compared. Whereas the maximum transconductance of the SG GFET was 17.1 μS/μm, that of the DG GFET was 25.7 μS/μm, which is approximately a 50% enhancement. The enhancement of the transconductance was reproduced and comprehensively explained by a physics-based compact model for GFETs. The investigation of the enhanced transfer characteristics of the DG GFET in this work shows the possibility of a multi-gate architecture for high-performance graphene transistor technology.

Semi-transparent a-IGZO thin-film transistors with polymeric gate dielectric.

PubMed

Hyung, Gun Woo; Wang, Jian-Xun; Li, Zhao-Hui; Koo, Ja-Ryong; Kwon, Sang Jik; Cho, Eou-Sik; Kim, Young Kwan

2013-06-01

We report the fabrication of semi-transparent a-IGZO-based thin-film transistors (TFTs) with crosslinked poly-4-vinylphenol (PVP) gate dielectric layers on PET substrate and thermally-evaporated Al/Ag/Al source and drain (S&D) electrodes, which showed a transmittance of 64% at a 500-nm wavelength and sheet resistance of 16.8 omega/square. The semi-transparent a-IGZO TFTs with a PVP layer exhibited decent saturation mobilities (maximum approximately 5.8 cm2Ns) and on/off current ratios of approximately 10(6).

FPGA chip performance improvement with gate shrink through alternating PSM 90nm process

NASA Astrophysics Data System (ADS)

Yu, Chun-Chi; Shieh, Ming-Feng; Liu, Erick; Lin, Benjamin; Ho, Jonathan; Wu, Xin; Panaite, Petrisor; Chacko, Manoj; Zhang, Yunqiang; Lei, Wen-Kang

2005-11-01

In the post-physical verification space called 'Mask Synthesis' a key component of design-for-manufacturing (DFM), double-exposure based, dark-field, alternating PSM (Alt-PSM) is being increasingly applied at the 90nm node in addition with other mature resolution enhancement techniques (RETs) such as optical proximity correction (OPC) and sub-resolution assist features (SRAF). Several high-performance IC manufacturers already use alt-PSM technology in 65nm production. At 90nm having strong control over the lithography process is a critical component in meeting targeted yield goals. However, implementing alt-PSM in production has been challenging due to several factors such as phase conflict errors, mask manufacturing, and the increased production cost due to the need for two masks in the process. Implementation of Alt-PSM generally requires phase compliance rules and proper phase topology in the layout and this has been successful for the technology node with these rules implemented. However, this may not be true for a mature, production process technology, in this case 90 nm. Especially, in the foundry-fabless business model where the foundry provides a standard set of design rules to its customers for a given process technology, and where not all the foundry customers require Alt-PSM in their tapeout flow. With minimum design changes, design houses usually are motivated by higher product performance for the existing designs. What follows is an in-depth review of the motivation to apply alt-PSM on a production FPGA, the DFM challenges to each partner faced, its effect on the tapeout flow, and how design, manufacturing, and EDA teams worked together to resolve phase conflicts, tapeout the chip, and finally verify the silicon results in production.

New positive Ca2+-activated K+ channel gating modulators with selectivity for KCa3.1.

PubMed

Coleman, Nichole; Brown, Brandon M; Oliván-Viguera, Aida; Singh, Vikrant; Olmstead, Marilyn M; Valero, Marta Sofia; Köhler, Ralf; Wulff, Heike

2014-09-01

Small-conductance (KCa2) and intermediate-conductance (KCa3.1) calcium-activated K(+) channels are voltage-independent and share a common calcium/calmodulin-mediated gating mechanism. Existing positive gating modulators like EBIO, NS309, or SKA-31 activate both KCa2 and KCa3.1 channels with similar potency or, as in the case of CyPPA and NS13001, selectively activate KCa2.2 and KCa2.3 channels. We performed a structure-activity relationship (SAR) study with the aim of optimizing the benzothiazole pharmacophore of SKA-31 toward KCa3.1 selectivity. We identified SKA-111 (5-methylnaphtho[1,2-d]thiazol-2-amine), which displays 123-fold selectivity for KCa3.1 (EC50 111 ± 27 nM) over KCa2.3 (EC50 13.7 ± 6.9 μM), and SKA-121 (5-methylnaphtho[2,1-d]oxazol-2-amine), which displays 41-fold selectivity for KCa3.1 (EC50 109 nM ± 14 nM) over KCa2.3 (EC50 4.4 ± 1.6 μM). Both compounds are 200- to 400-fold selective over representative KV (KV1.3, KV2.1, KV3.1, and KV11.1), NaV (NaV1.2, NaV1.4, NaV1.5, and NaV1.7), as well as CaV1.2 channels. SKA-121 is a typical positive-gating modulator and shifts the calcium-concentration response curve of KCa3.1 to the left. In blood pressure telemetry experiments, SKA-121 (100 mg/kg i.p.) significantly lowered mean arterial blood pressure in normotensive and hypertensive wild-type but not in KCa3.1(-/-) mice. SKA-111, which was found in pharmacokinetic experiments to have a much longer half-life and to be much more brain penetrant than SKA-121, not only lowered blood pressure but also drastically reduced heart rate, presumably through cardiac and neuronal KCa2 activation when dosed at 100 mg/kg. In conclusion, with SKA-121, we generated a KCa3.1-specific positive gating modulator suitable for further exploring the therapeutical potential of KCa3.1 activation. Copyright © 2014 by The American Society for Pharmacology and Experimental Therapeutics.

Gate oxide thickness dependence of the leakage current mechanism in Ru/Ta2O5/SiON/Si structures

NASA Astrophysics Data System (ADS)

Ťapajna, M.; Paskaleva, A.; Atanassova, E.; Dobročka, E.; Hušeková, K.; Fröhlich, K.

2010-07-01

Leakage conduction mechanisms in Ru/Ta2O5/SiON/Si structures with rf-sputtered Ta2O5 with thicknesses ranging from 13.5 to 1.8 nm were systematically studied. Notable reaction at the Ru/Ta2O5 interface was revealed by capacitance-voltage measurements. Temperature-dependent current-voltage characteristics suggest the bulk-limited conduction mechanism in all metal-oxide-semiconductor structures. Under gate injection, Poole-Frenkel emission was identified as a dominant mechanism for 13.5 nm thick Ta2O5. With an oxide thickness decreasing down to 3.5 nm, the conduction mechanism transforms to thermionic trap-assisted tunnelling through the triangular barrier. Under substrate injection, the dominant mechanism gradually changes with decreasing thickness from thermionic trap-assisted tunnelling to trap-assisted tunnelling through the triangular barrier; Poole-Frenkel emission was not observed at all. A 0.7 eV deep defect level distributed over Ta2O5 is assumed to be responsible for bulk-limited conduction mechanisms and is attributed to H-related defects or oxygen vacancies in Ta2O5.

Efficient Multi-Dimensional Simulation of Quantum Confinement Effects in Advanced MOS Devices

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Ancona, Mario G.; Rafferty, Conor S.; Yu, Zhiping

2000-01-01

We investigate the density-gradient (DG) transport model for efficient multi-dimensional simulation of quantum confinement effects in advanced MOS devices. The formulation of the DG model is described as a quantum correction ot the classical drift-diffusion model. Quantum confinement effects are shown to be significant in sub-100nm MOSFETs. In thin-oxide MOS capacitors, quantum effects may reduce gate capacitance by 25% or more. As a result, the inclusion of quantum effects may reduce gate capacitance by 25% or more. As a result, the inclusion of quantum effects in simulations dramatically improves the match between C-V simulations and measurements for oxide thickness down to 2 nm. Significant quantum corrections also occur in the I-V characteristics of short-channel (30 to 100 nm) n-MOSFETs, with current drive reduced by up to 70%. This effect is shown to result from reduced inversion charge due to quantum confinement of electrons in the channel. Also, subthreshold slope is degraded by 15 to 20 mV/decade with the inclusion of quantum effects via the density-gradient model, and short channel effects (in particular, drain-induced barrier lowering) are noticeably increased.

Genotyping of single nucleotide polymorphism by probe-gated silica nanoparticles.

PubMed

Ercan, Meltem; Ozalp, Veli C; Tuna, Bilge G

2017-11-15

The development of simple, reliable, and rapid approaches for molecular detection of common mutations is important for prevention and early diagnosis of genetic diseases, including Thalessemia. Oligonucleotide-gated mesoporous nanoparticles-based analysis is a new platform for mutation detection that has the advantages of sensitivity, rapidity, accuracy, and convenience. A specific mutation in β-thalassemia, one of the most prevalent inherited diseases in several countries, was used as model disease in this study. An assay for detection of IVS110 point mutation (A > G reversion) was developed by designing probe-gated mesoporous silica nanoparticles (MCM-41) loaded with reporter fluorescein molecules. The silica nanoparticles were characterized by AFM, TEM and BET analysis for having 180 nm diameter and 2.83 nm pore size regular hexagonal shape. Amine group functionalized nanoparticles were analysed with FTIR technique. Mutated and normal sequence probe oligonucleotides)about 12.7 nmol per mg nanoparticles) were used to entrap reporter fluorescein molecules inside the pores and hybridization with single stranded DNA targets amplified by PCR gave different fluorescent signals for mutated targets. Samples from IVS110 mutated and normal patients resulted in statistically significant differences when the assay procedure were applied. Copyright © 2017 Elsevier Inc. All rights reserved.

Characterization of Plasma-Induced Damage of Selectively Recessed GaN/InAlN/AlN/GaN Heterostructures Using SiCl4 and SF6

NASA Astrophysics Data System (ADS)

Ostermaier, Clemens; Pozzovivo, Gianmauro; Basnar, Bernhard; Schrenk, Werner; Carlin, Jean-François; Gonschorek, Marcus; Grandjean, Nicolas; Vincze, Andrej; Tóth, Lajos; Pécz, Bela; Strasser, Gottfried; Pogany, Dionyz; Kuzmik, Jan

2010-11-01

We have investigated an inductively coupled plasma etching recipe using SiCl4 and SF6 with a resulting selectivity >10 for GaN in respect to InAlN. The formation of an etch-resistant layer of AlF3 on InAlN required about 1 min and was noticed by a 4-times-higher initial etch rate on bare InAlN barrier high electron mobility transistors (HEMTs). Comparing devices with and without plasma-treatment below the gate showed no degradation in drain current and gate leakage current for plasma exposure durations shorter than 30 s, indicating no plasma-induced damage of the InAlN barrier. Devices etched longer than the required time for the formation of the etch-resistant barrier exhibited a slight decrease in drain current and an increase in gate leakage current which saturated for longer etching-time durations. Finally, we could prove the quality of the recipe by recessing the highly doped 6 nm GaN cap layer of a GaN/InAlN/AlN/GaN heterostructure down to the 2 nm thin InAlN/AlN barrier layer.

Reversible logic gates based on enzyme-biocatalyzed reactions and realized in flow cells: a modular approach.

PubMed

Fratto, Brian E; Katz, Evgeny

2015-05-18

Reversible logic gates, such as the double Feynman gate, Toffoli gate and Peres gate, with 3-input/3-output channels are realized using reactions biocatalyzed with enzymes and performed in flow systems. The flow devices are constructed using a modular approach, where each flow cell is modified with one enzyme that biocatalyzes one chemical reaction. The multi-step processes mimicking the reversible logic gates are organized by combining the biocatalytic cells in different networks. This work emphasizes logical but not physical reversibility of the constructed systems. Their advantages and disadvantages are discussed and potential use in biosensing systems, rather than in computing devices, is suggested. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Anomalous radiation effects in fully depleted SOI MOSFETs fabricated on SIMOX

NASA Astrophysics Data System (ADS)

Li, Ying; Niu, Guofu; Cressler, J. D.; Patel, J.; Marshall, C. J.; Marshall, P. W.; Kim, H. S.; Reed, R. A.; Palmer, M. J.

2001-12-01

We investigate the proton tolerance of fully depleted silicon-on-insulator (SOI) MOSFETs with H-gate and regular-gate structural configurations. For the front-gate characteristics, the H-gate does not show the edge leakage observed in the regular-gate transistor. An anomalous kink in the back-gate linear I/sub D/-V/sub GS/ characteristics of the fully depleted SOI nFETs has been observed at high radiation doses. This kink is attributed to charged traps generated in the bandgap at the buried oxide/silicon film interface during irradiation. Extensive two-dimensional simulations with MEDICI were used to understand the physical origin of this kink. We also report unusual self-annealing effects in the devices when they are cooled to liquid nitrogen temperature.

Super-resolution imaging of ciliary microdomains in isolated olfactory sensory neurons using a custom two-color stimulated emission depletion microscope

NASA Astrophysics Data System (ADS)

Meyer, Stephanie A.; Ozbay, Baris N.; Potcoava, Mariana; Salcedo, Ernesto; Restrepo, Diego; Gibson, Emily A.

2016-06-01

We performed stimulated emission depletion (STED) imaging of isolated olfactory sensory neurons (OSNs) using a custom-built microscope. The STED microscope uses a single pulsed laser to excite two separate fluorophores, Atto 590 and Atto 647N. A gated timing circuit combined with temporal interleaving of the different color excitation/STED laser pulses filters the two channel detection and greatly minimizes crosstalk. We quantified the instrument resolution to be ˜81 and ˜44 nm, for the Atto 590 and Atto 647N channels. The spatial separation between the two channels was measured to be under 10 nm, well below the resolution limit. The custom-STED microscope is incorporated onto a commercial research microscope allowing brightfield, differential interference contrast, and epifluorescence imaging on the same field of view. We performed immunolabeling of OSNs in mice to image localization of ciliary membrane proteins involved in olfactory transduction. We imaged Ca2+-permeable cyclic nucleotide gated (CNG) channel (Atto 594) and adenylyl cyclase type III (ACIII) (Atto 647N) in distinct cilia. STED imaging resolved well-separated subdiffraction limited clusters for each protein. We quantified the size of each cluster to have a mean value of 88±48 nm and 124±43 nm, for CNG and ACIII, respectively. STED imaging showed separated clusters that were not resolvable in confocal images.

High performance multi-finger MOSFET on SOI for RF amplifiers

NASA Astrophysics Data System (ADS)

Adhikari, M. Singh; Singh, Y.

2017-10-01

In this paper, we propose structural modifications in the conventional planar metal-oxide-semiconductor field-effect transistor (MOSFET) on silicon-on-insulator by utilizing trenches in the epitaxial layer. The proposed multi-finger MOSFET (MF-MOSFET) has dual vertical-gates placed in separate trenches to form multiple channels in the p-base which carry the drain current in parallel. The proposed device uses TaN as gate electrode and SiO2 as gate dielectric. Simultaneous conduction of multiple channels enhances the drain current (ID) and provides higher transconductance (gm) leading to significant improvement in cut-off frequency (ft). Two-dimensional simulations are performed to evaluate and compare the performance of the MF-MOSFET with the conventional MOSFET. At a gate length of 60 nm, the proposed device provides 4 times higher ID, 3 times improvement in gm and 1.25 times increase in ft with better control over the short channel effects as compared with the conventional device.

Photo-Patterned Ion Gel Electrolyte-Gated Thin Film Transistors

NASA Astrophysics Data System (ADS)

Choi, Jae-Hong; Gu, Yuanyan; Hong, Kihyun; Frisbie, C. Daniel; Lodge, Timothy P.

2014-03-01

We have developed a novel fabrication route to pattern electrolyte thin films in electrolyte-gated transistors (EGTs) using a chemically crosslinkable ABA-triblock copolymer ion gel. In the self-assembly of poly[(styrene-r-vinylbenzylazide)-b-ethylene oxide-b-(styrene-r-vinylbenzylazide)] (SOS-N3) triblock copolymer and the ionic liquid, 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide ([EMI][TFSI]), the azide groups of poly(styrene-r-vinylbenzylazide) (PS-N3) end-blocks in the cores can be chemically cross-linked via UV irradiation (λ = 254 nm). Impedance spectroscopy and small-angle X-ray scattering confirmed that ion transport and microstructure of the ion gel are not affected by UV cross-linking. Using this chemical cross-linking strategy, we demonstrate a photo-patterning of ion gels through a patterned mask and the fabricated electrolyte-gated thin film transistors with photo-patterned ion gels as high-capacitance gate insulators exhibited high device performance (low operation voltages and high on/off current ratios).

Impact of Lateral Straggle on the Analog/RF Performance of Asymmetric Gate Stack Double Gate MOSFET

NASA Astrophysics Data System (ADS)

Sivaram, Gollamudi Sai; Chakraborty, Shramana; Das, Rahul; Dasgupta, Arpan; Kundu, Atanu; Sarkar, Chandan K.

2016-09-01

This paper presents a systematic comparative study of Analog and RF performances of an underlapped double gate (U-DG) NMOSFET with Gate Stack (GS) for varying straggle lengths. Asymmetric underlap devices (A-U-DG) have been proposed as one of the remedies for reducing Short Channel Effects (SCE's) with the underlap being present towards the source for sub 20 nm devices. However, the Source to Drain (S/D) implant lateral diffusion leads to a variation in the effective underlap length. This paper investigates the impact of variation of straggle length on the Analog and RF parameters of the device. The RF performance is analyzed by considering the intrinsic capacitances (Cgd, Cgs), intrinsic resistances (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillations (fmax). The circuit performance of the devices are also studied. It is seen that the Analog and RF performances of the devices are improved by optimizing the S/D lateral straggle.

Comparative Study of HfTa-based gate-dielectric Ge metal-oxide-semiconductor capacitors with and without AlON interlayer

NASA Astrophysics Data System (ADS)

Xu, J. P.; Zhang, X. F.; Li, C. X.; Chan, C. L.; Lai, P. T.

2010-04-01

The electrical properties and high-field reliability of HfTa-based gate-dielectric metal-oxide-semiconductor (MOS) devices with and without AlON interlayer on Ge substrate are investigated. Experimental results show that the MOS capacitor with HfTaON/AlON stack gate dielectric exhibits low interface-state/oxide-charge densities, low gate leakage, small capacitance equivalent thickness (˜1.1 nm), and high dielectric constant (˜20). All of these should be attributed to the blocking role of the ultrathin AlON interlayer against interdiffusions of Ge, Hf, and Ta and penetration of O into the Ge substrate, with the latter effectively suppressing the unintentional formation of unstable poor-quality low- k GeO x and giving a superior AlON/Ge interface. Moreover, incorporation of N into both the interlayer and high- k dielectric further improves the device reliability under high-field stress through the formation of strong N-related bonds.

Artificial neuron synapse transistor based on silicon nanomembrane on plastic substrate

NASA Astrophysics Data System (ADS)

Liu, Minjie; Huang, Gaoshan; Feng, Ping; Guo, Qinglei; Shao, Feng; Tian, Ziao; Li, Gongjin; Wan, Qing; Mei, Yongfeng

2017-06-01

Silicon nanomembrane (SiNM) transistors gated by chitosan membrane were fabricated on plastic substrate to mimic synapse behaviors. The device has both a bottom proton gate (BG) and multiple side gates (SG). Electrical transfer properties of BG show hysteresis curves different from those of typical SiO2 gate dielectric. Synaptic behaviors and functions by linear accumulation and release of protons have been mimicked on this device: excitatory post-synaptic current (EPSC) and paired pulse facilitation behavior of biological synapses were mimicked and the paired-pulse facilitation index could be effectively tuned by the spike interval applied on the BG. Synaptic behaviors and functions, including short-term memory and long-term memory, were also experimentally demonstrated in BG mode. Meanwhile, spiking logic operation and logic modulation were realized in SG mode. Project supported by the National Natural Science Foundation of China (No. 51322201), the Specialized Research Fund for the Doctoral Program of Higher Education (No. 20120071110025), and Science and Technology Commission of Shanghai Municipality (No. 14JC1400200).

Dielectric collapse at the LaAlO 3/SrTiO 3 (001) heterointerface under applied electric field

DOE Office of Scientific and Technical Information (OSTI.GOV)

Minohara, M.; Hikita, Y.; Bell, C.

The fascinating interfacial transport properties at the LaAlO 3/SrTiO 3 heterointerface have led to intense investigations of this oxide system. Exploiting the large dielectric constant of SrTiO 3 at low temperatures, tunability in the interfacial conductivity over a wide range has been demonstrated using a back-gate device geometry. In order to understand the effect of back-gating, it is crucial to assess the interface band structure and its evolution with external bias. In this study, we report measurements of the gate-bias dependent interface band alignment, especially the confining potential profile, at the conducting LaAlO 3/SrTiO 3 (001) heterointerface using soft andmore » hard x-ray photoemission spectroscopy in conjunction with detailed model simulations. Depth-profiling analysis incorporating the electric field dependent dielectric constant in SrTiO 3 reveals that a significant potential drop on the SrTiO 3 side of the interface occurs within ~2 nm of the interface under negative gate-bias. These results demonstrate gate control of the collapse of the dielectric permittivity at the interface, and explain the dramatic loss of electron mobility with back-gate depletion.« less

Using Ultrathin Parylene Films as an Organic Gate Insulator in Nanowire Field-Effect Transistors.

PubMed

Gluschke, J G; Seidl, J; Lyttleton, R W; Carrad, D J; Cochrane, J W; Lehmann, S; Samuelson, L; Micolich, A P

2018-06-27

We report the development of nanowire field-effect transistors featuring an ultrathin parylene film as a polymer gate insulator. The room temperature, gas-phase deposition of parylene is an attractive alternative to oxide insulators prepared at high temperatures using atomic layer deposition. We discuss our custom-built parylene deposition system, which is designed for reliable and controlled deposition of <100 nm thick parylene films on III-V nanowires standing vertically on a growth substrate or horizontally on a device substrate. The former case gives conformally coated nanowires, which we used to produce functional Ω-gate and gate-all-around structures. These give subthreshold swings as low as 140 mV/dec and on/off ratios exceeding 10 3 at room temperature. For the gate-all-around structure, we developed a novel fabrication strategy that overcomes some of the limitations with previous lateral wrap-gate nanowire transistors. Finally, we show that parylene can be deposited over chemically treated nanowire surfaces, a feature generally not possible with oxides produced by atomic layer deposition due to the surface "self-cleaning" effect. Our results highlight the potential for parylene as an alternative ultrathin insulator in nanoscale electronic devices more broadly, with potential applications extending into nanobioelectronics due to parylene's well-established biocompatible properties.

Dielectric collapse at the LaAlO 3/SrTiO 3 (001) heterointerface under applied electric field

DOE PAGES

Minohara, M.; Hikita, Y.; Bell, C.; ...

2017-08-25

The fascinating interfacial transport properties at the LaAlO 3/SrTiO 3 heterointerface have led to intense investigations of this oxide system. Exploiting the large dielectric constant of SrTiO 3 at low temperatures, tunability in the interfacial conductivity over a wide range has been demonstrated using a back-gate device geometry. In order to understand the effect of back-gating, it is crucial to assess the interface band structure and its evolution with external bias. In this study, we report measurements of the gate-bias dependent interface band alignment, especially the confining potential profile, at the conducting LaAlO 3/SrTiO 3 (001) heterointerface using soft andmore » hard x-ray photoemission spectroscopy in conjunction with detailed model simulations. Depth-profiling analysis incorporating the electric field dependent dielectric constant in SrTiO 3 reveals that a significant potential drop on the SrTiO 3 side of the interface occurs within ~2 nm of the interface under negative gate-bias. These results demonstrate gate control of the collapse of the dielectric permittivity at the interface, and explain the dramatic loss of electron mobility with back-gate depletion.« less

Programmable Schottky Junctions Based on Ferroelectric Gated MoS2 Transistors

NASA Astrophysics Data System (ADS)

Xiao, Zhiyong; Song, Jingfeng; Drcharme, Stephen; Hong, Xia

We report a programmable Schottky junction based on MoS2 field effect transistors with a SiO2 back gate and a ferroelectric copolymer poly(vinylidene-fluoride-trifluorethylene) (PVDF) top gate. We fabricated mechanically exfoliated single layer MoS2 flakes into two point devices via e-beam lithography, and deposited on the top of the devices ~20 nm PVDF thin films. The polarization of the PVDF layer is controlled locally by conducting atomic force microscopy. The devices exhibit linear ID-VD characteristics when the ferroelectric gate is uniformly polarized in one direction. We then polarized the gate into two domains with opposite polarization directions, and observed that the ID-VD characteristics of the MoS2 channel can be modulated between linear and rectified behaviors depending on the back gate voltage. The nonlinear ID-VD relation emerges when half of the channel is in the semiconductor phase while the other half is in the metallic phase, and it can be well described by the thermionic emission model with a Schottky barrier of ~0.5 eV. The Schottky junction can be erased by re-write the entire channel in the uniform polarization state. Our study facilitates the development of programmable, multifunctional nanoelectronics based on layered 2D TMDs..

Analysis of power gating in different hierarchical levels of 2MB cache, considering variation

NASA Astrophysics Data System (ADS)

Jafari, Mohsen; Imani, Mohsen; Fathipour, Morteza

2015-09-01

This article reintroduces power gating technique in different hierarchical levels of static random-access memory (SRAM) design including cell, row, bank and entire cache memory in 16 nm Fin field effect transistor. Different structures of SRAM cells such as 6T, 8T, 9T and 10T are used in design of 2MB cache memory. The power reduction of the entire cache memory employing cell-level optimisation is 99.7% with the expense of area and other stability overheads. The power saving of the cell-level optimisation is 3× (1.2×) higher than power gating in cache (bank) level due to its superior selectivity. The access delay times are allowed to increase by 4% in the same energy delay product to achieve the best power reduction for each supply voltages and optimisation levels. The results show the row-level power gating is the best for optimising the power of the entire cache with lowest drawbacks. Comparisons of cells show that the cells whose bodies have higher power consumption are the best candidates for power gating technique in row-level optimisation. The technique has the lowest percentage of saving in minimum energy point (MEP) of the design. The power gating also improves the variation of power in all structures by at least 70%.

Two-Dimensional Arrays of Neutral Atom Quantum Gates

DTIC Science & Technology

2012-10-20

Box 12211 Research Triangle Park, NC 27709-2211 15. SUBJECT TERMS quantum computing , Rydberg atoms, entanglement Mark Saffman University of...Nature Physics, (01 2009): 0. doi: 10.1038/nphys1178 10/19/2012 9.00 K. Mølmer, M. Saffman. Scaling the neutral-atom Rydberg gate quantum computer by...Saffman, E. Brion, K. Mølmer. Error Correction in Ensemble Registers for Quantum Repeaters and Quantum Computers , Physical Review Letters, (3 2008): 0

Comparison of the physical, chemical and electrical properties of ALD Al 2 O 3 on c- and m- plane GaN: Comparison of the physical, chemical and electrical properties of ALD Al 2 O 3 on c- and m- plane GaN

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wei, D.; Hossain, T.; Nepal, N.

2014-02-01

Our study compares the physical, chemical and electrical properties of Al 2O 3 thin films deposited on gallium polar c- and nonpolar m -plane GaN substrates by atomic layer deposition (ALD). Correlations were sought between the film's structure, composition, and electrical properties. The thickness of the Al 2O 3 films was 19.2 nm as determined from a Si witness sample by spectroscopic ellipsometry. We measured the gate dielectric was slightly aluminum-rich (Al:O=1:1.3) from X-ray photoelectron spectroscopy (XPS) depth profile, and the oxide-semiconductor interface carbon concentration was lower on c -plane GaN. The oxide's surface morphology was similar on both substrates,more » but was smoothest on c -plane GaN as determined by atomic force microscopy (AFM). Circular capacitors (50-300 μm diameter) with Ni/Au (20/100 nm) metal contacts on top of the oxide were created by standard photolithography and e-beam evaporation methods to form metal-oxide-semiconductor capacitors (MOSCAPs). Moreover, the alumina deposited on c -plane GaN showed less hysteresis (0.15 V) than on m -plane GaN (0.24 V) in capacitance-voltage (CV) characteristics, consistent with its better quality of this dielectric as evidenced by negligible carbon contamination and smooth oxide surface. These results demonstrate the promising potential of ALD Al 2O 3 on c -plane GaN, but further optimization of ALD is required to realize the best properties of Al 2O 3 on m -plane GaN.« less

Submillimeter-Wave Amplifier Module with Integrated Waveguide Transitions

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Chattopadhyay, Goutam; Pukala, David; Gaier, Todd; Soria, Mary; ManFung, King; Deal, William; Mei, Gerry; Radisic, Vesna; Lai, Richard

2009-01-01

To increase the usefulness of monolithic millimeter-wave integrated circuit (MMIC) components at submillimeter-wave frequencies, a chip has been designed that incorporates two integrated, radial E-plane probes with an MMIC amplifier in between, thus creating a fully integrated waveguide module. The integrated amplifier chip has been fabricated in 35-nm gate length InP high-electron-mobility-transistor (HEMT) technology. The radial probes were mated to grounded coplanar waveguide input and output lines in the internal amplifier. The total length of the internal HEMT amplifier is 550 m, while the total integrated chip length is 1,085 m. The chip thickness is 50 m with the chip width being 320 m. The internal MMIC amplifier is biased through wire-bond connections to the gates and drains of the chip. The chip has 3 stages, employing 35-nm gate length transistors in each stage. Wire bonds from the DC drain and gate pads are connected to off-chip shunt 51-pF capacitors, and additional off-chip capacitors and resistors are added to the gate and drain bias lines for low-frequency stability of the amplifier. Additionally, bond wires to the grounded coplanar waveguide pads at the RF input and output of the internal amplifier are added to ensure good ground connections to the waveguide package. The S-parameters of the module, not corrected for input or output waveguide loss, are measured at the waveguide flange edges. The amplifier module has over 10 dB of gain from 290 to 330 GHz, with a peak gain of over 14 dB at 307 GHz. The WR2.2 waveguide cutoff is again observed at 268 GHz. The module is biased at a drain current of 27 mA, a drain voltage of 1.24 V, and a gate voltage of +0.21 V. Return loss of the module is very good between 5 to 25 dB. This result illustrates the usefulness of the integrated radial probe transition, and the wide (over 10-percent) bandwidth that one can expect for amplifier modules with integrated radial probes in the submillimeter-regime (>300 GHz).

Characterization and metrology implications of the 1997 NTRS

NASA Astrophysics Data System (ADS)

Class, W.; Wortman, J. J.

1998-11-01

In the Front-end (transistor forming) area of silicon CMOS device processing, several NTRS difficult challenges have been identified including; scaled and alternate gate dielectric materials, new DRAM dielectric materials, alternate gate materials, elevated contact structures, engineered channels, and large-area cost-effective silicon substrates. This paper deals with some of the characterization and metrology challenges facing the industry if it is to meet the projected needs identified in the NTRS. In the areas of gate and DRAM dielectric, scaling requires that existing material layers be thinned to maximize capacitance. For the current gate dielectric, SiO2 and its nitrided derivatives, direct tunneling will limit scaling to approximately 1.5nm for logic applications before power losses become unacceptable. Low power logic and memory applications may limit scaling to the 2.0-2.2nm range. Beyond these limits, dielectric materials having higher dielectric constant, will permit continued capacitance increases while allowing for the use of thicker dielectric layers, where tunneling may be minimized. In the near term silicon nitride is a promising SiO2 substitute material while in the longer term "high-k" materials such as tantalum pentoxide and barium strontium titanate (BST) will be required. For these latter materials, it is likely that a multilayer dielectric stack will be needed, consisting of an ultra-thin (1-2 atom layer) interfacial SiO2 layer and a high-k overlayer. Silicon wafer surface preparation control, as well as the control of composition, crystal structure, and thickness for such stacks pose significant characterization and metrology challenges. In addition to the need for new gate dielectric materials, new gate materials will be required to overcome the limitations of the current doped polysilicon gate materials. Such a change has broad ramifications on device electrical performance and manufacturing process robustness which again implies a broad range of new characterization and metrology requirements. Finally, the doped structure of the MOS transistor must scale to very small lateral and depth dimensions, and thermal budgets must be reduced to permit the retention of very abrupt highly doped drain and channel engineered structures. Eventually, the NTRS forecasts the need for an elevated contact structure. Here, there are significant challenges associated with three-dimensional dopant profiling, measurement of dopant activity in ultra-shallow device regions, as well as point defect metrology and characterization.

Bubbles, Gating, and Anesthetics in Ion Channels

PubMed Central

Roth, Roland; Gillespie, Dirk; Nonner, Wolfgang; Eisenberg, Robert E.

2008-01-01

We suggest that bubbles are the bistable hydrophobic gates responsible for the on-off transitions of single channel currents. In this view, many types of channels gate by the same physical mechanism—dewetting by capillary evaporation—but different types of channels use different sensors to modulate hydrophobic properties of the channel wall and thereby trigger and control bubbles and gating. Spontaneous emptying of channels has been seen in many simulations. Because of the physics involved, such phase transitions are inherently sensitive, unstable threshold phenomena that are difficult to simulate reproducibly and thus convincingly. We present a thermodynamic analysis of a bubble gate using morphometric density functional theory of classical (not quantum) mechanics. Thermodynamic analysis of phase transitions is generally more reproducible and less sensitive to details than simulations. Anesthetic actions of inert gases—and their interactions with hydrostatic pressure (e.g., nitrogen narcosis)—can be easily understood by actions on bubbles. A general theory of gas anesthesia may involve bubbles in channels. Only experiments can show whether, or when, or which channels actually use bubbles as hydrophobic gates: direct observation of bubbles in channels is needed. Existing experiments show thin gas layers on hydrophobic surfaces in water and suggest that bubbles nearly exist in bulk water. PMID:18234836

Surface characterization of carbon fiber reinforced polymers by picosecond laser induced breakdown spectroscopy

NASA Astrophysics Data System (ADS)

Ledesma, Rodolfo; Palmieri, Frank; Connell, John; Yost, William; Fitz-Gerald, James

2018-02-01

Adhesive bonding of composite materials requires reliable monitoring and detection of surface contaminants as part of a vigorous quality control process to assure robust and durable bonded structures. Surface treatment and effective monitoring prior to bonding are essential in order to obtain a surface which is free from contaminants that may lead to inferior bond quality. In this study, the focus is to advance the laser induced breakdown spectroscopy (LIBS) technique by using pulse energies below 100 μJ (μLIBS) for the detection of low levels of silicone contaminants in carbon fiber reinforced polymer (CFRP) composites. Various CFRP surface conditions were investigated by LIBS using ∼10 ps, 355 nm laser pulses with pulse energies below 30 μJ. Time-resolved analysis was conducted to optimize the gate delay and gate width for the detection of the C I emission line at 247.9 nm to monitor the epoxy resin matrix of CFRP composites and the Si I emission line at 288.2 nm for detection of silicone contaminants in CFRP. To study the surface sensitivity to silicone contamination, CFRP surfaces were coated with polydimethylsiloxane (PDMS), the active ingredient in many mold release agents. The presence of PDMS was studied by inspecting the Si I emission lines at 251.6 nm and 288.2 nm. The measured PDMS areal densities ranged from 0.15 to 2 μg/cm2. LIBS measurements were performed before and after laser surface ablation. The results demonstrate the successful detection of PDMS thin layers on CFRP using picosecond μLIBS.

Picosecond imaging of sprays

NASA Technical Reports Server (NTRS)

Breisacher, Kevin; Liou, Larry; Wang, L.; Liang, X.; Galland, P.; Ho, P. P.; Alfano, R. R.

1994-01-01

Preliminary results from applying a Kerr-Fourier imaging system to a water/air spray produced by a shear coaxial element are presented. The physics behind ultrafast time-gated optical techniques is discussed briefly. A typical setup of a Kerr-Fourier time gating system is presented.

Crystalline ZrTiO{sub 4} gated p-metal–oxide–semiconductor field effect transistors with sub-nm equivalent oxide thickness featuring good electrical characteristics and reliability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Chao-Yi; Hsieh, Ching-Heng; Lee, Ching-Wei

2015-02-02

ZrTiO{sub 4} crystallized in orthorhombic (o-) phase was stacked with an amorphous Yb{sub 2}O{sub 3} interfacial layer as the gate dielectric for Si-based p-MOSFETs. With thermal annealing after gate electrode, the gate stack with equivalent oxide thickness (EOT) of 0.82 nm achieves high dielectric quality by showing a low interface trap density (D{sub it}) of 2.75 × 10{sup 11 }cm{sup −2}eV{sup −1} near the midgap and low oxide traps. Crystallization of ZrTiO{sub 4} and post metal annealing are also proven to introduce very limited amount of metal induced gap states or interfacial dipole. The p-MOSFETs exhibit good sub-threshold swing of 75 mV/dec which is ascribedmore » to the low D{sub it} value and small EOT. Owing to the Y{sub 2}O{sub 3} interfacial layer and smooth interface with Si substrate that, respectively, suppress phonon and surface roughness scattering, the p-MOSFETs also display high hole mobility of 49 cm{sup 2}/V-s at 1 MV/cm. In addition, I{sub on}/I{sub off} ratio larger than 10{sup 6} is also observed. From the reliability evaluation by negative bias temperature instability test, after stressing with an electric field of −10 MV/cm at 85 °C for 1000 s, satisfactory threshold voltage shift of 12 mV and sub-threshold swing degradation of 3% were obtained. With these promising characteristics, the Yb{sub 2}O{sub 3}/o-ZrTiO{sub 4} gate stack holds the great potential for next-generation electronics.« less

Hybrid Toffoli gate on photons and quantum spins

PubMed Central

Luo, Ming-Xing; Ma, Song-Ya; Chen, Xiu-Bo; Wang, Xiaojun

2015-01-01

Quantum computation offers potential advantages in solving a number of interesting and difficult problems. Several controlled logic gates, the elemental building blocks of quantum computer, have been realized with various physical systems. A general technique was recently proposed that significantly reduces the realization complexity of multiple-control logic gates by harnessing multi-level information carriers. We present implementations of a key quantum circuit: the three-qubit Toffoli gate. By exploring the optical selection rules of one-sided optical microcavities, a Toffoli gate may be realized on all combinations of photon and quantum spins in the QD-cavity. The three general controlled-NOT gates are involved using an auxiliary photon with two degrees of freedom. Our results show that photons and quantum spins may be used alternatively in quantum information processing. PMID:26568078

Hybrid Toffoli gate on photons and quantum spins.

PubMed

Luo, Ming-Xing; Ma, Song-Ya; Chen, Xiu-Bo; Wang, Xiaojun

2015-11-16

Quantum computation offers potential advantages in solving a number of interesting and difficult problems. Several controlled logic gates, the elemental building blocks of quantum computer, have been realized with various physical systems. A general technique was recently proposed that significantly reduces the realization complexity of multiple-control logic gates by harnessing multi-level information carriers. We present implementations of a key quantum circuit: the three-qubit Toffoli gate. By exploring the optical selection rules of one-sided optical microcavities, a Toffoli gate may be realized on all combinations of photon and quantum spins in the QD-cavity. The three general controlled-NOT gates are involved using an auxiliary photon with two degrees of freedom. Our results show that photons and quantum spins may be used alternatively in quantum information processing.

Heralded Quantum Gate between Remote Quantum Memories

DTIC Science & Technology

2009-06-25

emission fre- quency. Second, the geometrical modes from the two fibers are matched to better than 98% as characterized with laser light. Third, the...remains in the trap for several weeks. Doppler-cooling by laser light slightly red detuned from the 2S1=2 $ 2P1=2 transition at 369.5 nm localizes the ions...state decays to the metastable 2D3=2 level. This level is depopulated with a laser near 935.2 nm to maintain efficient cooling and state detection. We

A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience

NASA Astrophysics Data System (ADS)

Li, Y.-Q.; Wang, H.-B.; Liu, R.; Chen, L.; Nofal, I.; Shi, S.-T.; He, A.-L.; Guo, G.; Baeg, S. H.; Wen, S.-J.; Wong, R.; Chen, M.; Wu, Q.

2017-06-01

A flip-flop circuit hardened against soft errors is presented in this paper. This design is an improved version of Quatro for further enhanced soft-error resilience by integrating the guard-gate technique. The proposed design, as well as reference Quatro and regular flip-flops, was implemented and manufactured in a 65-nm CMOS bulk technology. Experimental characterization results of their alpha and heavy ions soft-error rates verified the superior hardening performance of the proposed design over the other two circuits.

1/F Noise in Indium Phosphide Transistors

DTIC Science & Technology

1992-04-01

Zn/5 nm Au. The gate length and width were 1 Pm and 400 gm, respectively. The device was annealed at 375"C in argon for 1 minute to simultaneously...evaporation, defined by lift-off, and annealed at 375°C for 10 minutes. The gate region was recessed until a source-drain current of 35 mA was obtained...considerations for the signal Sn V,2/R, at the network input from the amplifier output show that vo2 4RoR,, s - 4 nR 2 = So •Mo. (6) 4Ro (Ro + R,) 2

Monte Carlo simulations of spin transport in a strained nanoscale InGaAs field effect transistor

NASA Astrophysics Data System (ADS)

Thorpe, B.; Kalna, K.; Langbein, F. C.; Schirmer, S.

2017-12-01

Spin-based logic devices could operate at a very high speed with a very low energy consumption and hold significant promise for quantum information processing and metrology. We develop a spintronic device simulator by combining an in-house developed, experimentally verified, ensemble self-consistent Monte Carlo device simulator with spin transport based on a Bloch equation model and a spin-orbit interaction Hamiltonian accounting for Dresselhaus and Rashba couplings. It is employed to simulate a spin field effect transistor operating under externally applied voltages on a gate and a drain. In particular, we simulate electron spin transport in a 25 nm gate length In0.7Ga0.3As metal-oxide-semiconductor field-effect transistor with a CMOS compatible architecture. We observe a non-uniform decay of the net magnetization between the source and the gate and a magnetization recovery effect due to spin refocusing induced by a high electric field between the gate and the drain. We demonstrate a coherent control of the polarization vector of the drain current via the source-drain and gate voltages, and show that the magnetization of the drain current can be increased twofold by the strain induced into the channel.

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

NASA Astrophysics Data System (ADS)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

Design and implementation of low power clock gated 64-bit ALU on ultra scale FPGA

NASA Astrophysics Data System (ADS)

Gupta, Ashutosh; Murgai, Shruti; Gulati, Anmol; Kumar, Pradeep

2016-03-01

64-bit energy efficient Arithmetic and Logic Unit using negative latch based clock gating technique is designed in this paper. The 64-bit ALU is designed using multiplexer based full adder cell. We have designed a 64-bit ALU with a gated clock. We have used negative latch based circuit for generating gated clock. This gated clock is used to control the multiplexer based 64-bit ALU. The circuit has been synthesized on kintex FPGA through Xilinx ISE Design Suite 14.7 using 28 nm technology in Verilog HDL. The circuit has been simulated on Modelsim 10.3c. The design is verified using System Verilog on QuestaSim in UVM environment. We have achieved 74.07%, 92. 93% and 95.53% reduction in total clock power, 89.73%, 91.35% and 92.85% reduction in I/Os power, 67.14%, 62.84% and 74.34% reduction in dynamic power and 25.47%, 29.05% and 46.13% reduction in total supply power at 20 MHz, 200 MHz and 2 GHz frequency respectively. The power has been calculated using XPower Analyzer tool of Xilinx ISE Design Suite 14.3.

Suppression of surface-originated gate lag by a dual-channel AlN/GaN high electron mobility transistor architecture

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deen, David A., E-mail: david.deen@alumni.nd.edu; Storm, David F.; Scott Katzer, D.

A dual-channel AlN/GaN high electron mobility transistor (HEMT) architecture is demonstrated that leverages ultra-thin epitaxial layers to suppress surface-related gate lag. Two high-density two-dimensional electron gas (2DEG) channels are utilized in an AlN/GaN/AlN/GaN heterostructure wherein the top 2DEG serves as a quasi-equipotential that screens potential fluctuations resulting from distributed surface and interface states. The bottom channel serves as the transistor's modulated channel. Dual-channel AlN/GaN heterostructures were grown by molecular beam epitaxy on free-standing hydride vapor phase epitaxy GaN substrates. HEMTs fabricated with 300 nm long recessed gates demonstrated a gate lag ratio (GLR) of 0.88 with no degradation in drain currentmore » after bias stressed in subthreshold. These structures additionally achieved small signal metrics f{sub t}/f{sub max} of 27/46 GHz. These performance results are contrasted with the non-recessed gate dual-channel HEMT with a GLR of 0.74 and 82 mA/mm current collapse with f{sub t}/f{sub max} of 48/60 GHz.« less

Photonic ququart logic assisted by the cavity-QED system.

PubMed

Luo, Ming-Xing; Deng, Yun; Li, Hui-Ran; Ma, Song-Ya

2015-08-14

Universal quantum logic gates are important elements for a quantum computer. In contrast to previous constructions of qubit systems, we investigate the possibility of ququart systems (four-dimensional states) dependent on two DOFs of photon systems. We propose some useful one-parameter four-dimensional quantum transformations for the construction of universal ququart logic gates. The interface between the spin of a photon and an electron spin confined in a quantum dot embedded in a microcavity is applied to build universal ququart logic gates on the photon system with two freedoms. Our elementary controlled-ququart gates cost no more than 8 CNOT gates in a qubit system, which is far less than the 104 CNOT gates required for a general four-qubit logic gate. The ququart logic is also used to generate useful hyperentanglements and hyperentanglement-assisted quantum error-correcting code, which may be available in modern physical technology.

Photonic ququart logic assisted by the cavity-QED system

PubMed Central

Luo, Ming-Xing; Deng, Yun; Li, Hui-Ran; Ma, Song-Ya

2015-01-01

Universal quantum logic gates are important elements for a quantum computer. In contrast to previous constructions of qubit systems, we investigate the possibility of ququart systems (four-dimensional states) dependent on two DOFs of photon systems. We propose some useful one-parameter four-dimensional quantum transformations for the construction of universal ququart logic gates. The interface between the spin of a photon and an electron spin confined in a quantum dot embedded in a microcavity is applied to build universal ququart logic gates on the photon system with two freedoms. Our elementary controlled-ququart gates cost no more than 8 CNOT gates in a qubit system, which is far less than the 104 CNOT gates required for a general four-qubit logic gate. The ququart logic is also used to generate useful hyperentanglements and hyperentanglement-assisted quantum error-correcting code, which may be available in modern physical technology. PMID:26272869

Efficient Nonlocal M-Control and N-Target Controlled Unitary Gate Using Non-symmetric GHZ States

NASA Astrophysics Data System (ADS)

Chen, Li-Bing; Lu, Hong

2018-03-01

Efficient local implementation of a nonlocal M-control and N-target controlled unitary gate is considered. We first show that with the assistance of two non-symmetric qubit(1)-qutrit(N) Greenberger-Horne-Zeilinger (GHZ) states, a nonlocal 2-control and N-target controlled unitary gate can be constructed from 2 local two-qubit CNOT gates, 2 N local two-qutrit conditional SWAP gates, N local qutrit-qubit controlled unitary gates, and 2 N single-qutrit gates. At each target node, the two third levels of the two GHZ target qutrits are used to expose one and only one initial computational state to the local qutrit-qubit controlled unitary gate, instead of being used to hide certain states from the conditional dynamics. This scheme can be generalized straightforwardly to implement a higher-order nonlocal M-control and N-target controlled unitary gate by using M non-symmetric qubit(1)-qutrit(N) GHZ states as quantum channels. Neither the number of the additional levels of each GHZ target particle nor that of single-qutrit gates needs to increase with M. For certain realistic physical systems, the total gate time may be reduced compared with that required in previous schemes.

Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

NASA Astrophysics Data System (ADS)

Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

2015-04-01

In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on-off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10-13-10-11 µm2/Hz for n-type and 10-12-10-10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11,000 cm(2)/V·s.

PubMed

Smith, Casey; Qaisi, Ramy; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

2013-07-23

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11,000 cm(2)/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low tox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance.

Looking for Speed!! Go Optical Ultra-Fast Photonic Logic Gates for the Future Optical Communication and Computing

NASA Technical Reports Server (NTRS)

Abdeldayem, Hossin; Frazier, Donald O.; Penn, Benjamin; Paley, Mark S.

2003-01-01

Recently, we developed two ultra-fast all-optical switches in the nanosecond and picosecond regimes. The picosecond switch is made of a polydiacetylene thin film coated on the interior wall of a hollow capillary of approximately 50 micron diameter by a photo-polymerization process. In the setup a picosecond Nd:YAG laser at 10 Hz and at 532 nm with a pulse duration of approximately 40 ps was sent collinearly along a cw He-Ne laser beam and both were waveguided through the hollow capillary. The setup functioned as an Exclusive OR gate. On the other hand, the material used in the nanosecond switch is a phthalocyanine thin film, deposited on a glass substrate by a vapor deposition technique. In the setup a nanosecond, 10 Hz, Nd:YAG laser of 8 ns pulse duration was sent collinearly along a cw He-Ne laser beam and both were wave-guided through the phthalocyanine thin film. The setup in this case functioned as an all-optical AND logic gate. The characteristic table of the ExOR gate in polydiacetylene film was attributed to an excited state absorption process, while that of the AND gate was attributed to a saturation process of the first excited state. Both mechanisms were thoroughly investigated theoretically and found to agree remarkably well with the experimental results. An all-optical inverter gate has been designed but has not yet been demonstrated. The combination of all these three gates form the foundation for building all the necessary gates needed to build a prototype of an all-optical system.

Scaling behavior of fully spin-coated TFT

NASA Astrophysics Data System (ADS)

Mondal, Sandip; Kumar, Arvind; Rao, K. S. R. Koteswara; Venkataraman, V.

2017-05-01

We studied channel scaling behavior of fully spin coated, low temperature solution processed thin film transistor (TFT) fabricated on p++ - Si (˜1021 cm-3) as bottom gate. The solution processed, spin coated 40 nm thick amorphous Indium Gallium Zinc Oxide (a-IGZO) and 50 nm thick amorphous zirconium di-oxide (a-ZrO2) has been used as channel and low leakage dielectric at 350°C respectively. The channel scaling effect of the TFT with different width/length ratio (W/L= 2.5, 5 and 15) for same channel length (L = 10 μm) has been demonstrated. The lowest threshold voltage (Vth) is 6.25 V for the W/L=50/10. The maximum field effect mobility (μFE) has been found to be 0.123 cm2/Vs from W/L of 50/10 with the drain to source voltage (VD) of 10V and 20V gate to source voltage (VG). We also demonstrated that there is no contact resistance effect on the mobility of the fully sol-gel spin coated TFT.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mamaluy, Denis; Gao, Xujiao; Tierney, Brian David

We created a highly efficient, universal 3D quant um transport simulator. We demonstrated that the simulator scales linearly - both with the problem size (N) and number of CPUs, which presents an important break-through in the field of computational nanoelectronics. It allowed us, for the first time, to accurately simulate and optim ize a large number of realistic nanodevices in a much shorter time, when compared to other methods/codes such as RGF[%7EN 2.333 ]/KNIT, KWANT, and QTBM[%7EN 3 ]/NEMO5. In order to determine the best-in-class for different beyond-CMOS paradigms, we performed rigorous device optimization for high-performance logic devices at 6-,more » 5- and 4-nm gate lengths. We have discovered that there exists a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs). We have found that, at room temperatures, all FETs, irre spective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths.« less

Suspended sub-50 nm vanadium dioxide membrane transistors: fabrication and ionic liquid gating studies

NASA Astrophysics Data System (ADS)

Sim, Jai S.; Zhou, You; Ramanathan, Shriram

2012-10-01

We demonstrate a robust lithographic patterning method to fabricate self-supported sub-50 nm VO2 membranes that undergo a phase transition. Utilizing such self-supported membranes, we directly observed a shift in the metal-insulator transition temperature arising from stress relaxation and consistent opening of the hysteresis. Electric double layer transistors were then fabricated with the membranes and compared to thin film devices. The ionic liquid allowed reversible modulation of channel resistance and distinguishing bulk processes from the surface effects. From the shift in the metal-insulator transition temperature, the carrier density doped through electrolyte gating is estimated to be 1 × 1020 cm-3. Hydrogen annealing studies showed little difference in resistivity between the film and the membrane indicating rapid diffusion of hydrogen in the vanadium oxide rutile lattice consistent with previous observations. The ability to fabricate electrically-wired, suspended VO2 ultra-thin membranes creates new opportunities to study mesoscopic size effects on phase transitions and may also be of interest in sensor devices.

Numerical analysis of the reverse blocking enhancement in High-K passivation AlGaN/GaN Schottky barrier diodes with gated edge termination

NASA Astrophysics Data System (ADS)

Bai, Zhiyuan; Du, Jiangfeng; Xin, Qi; Li, Ruonan; Yu, Qi

2018-02-01

We conducted a numerical analysis on high-K dielectric passivated AlGaN/GaN Schottky barrier diodes (HPG-SBDs) with a gated edge termination (GET). The reverse blocking characteristics were significantly enhanced without the stimulation of any parasitic effect by varying the dielectric thickness dge under the GET, thickness TP, and dielectric constant εr of the high-K passivation layer. The leakage current was reduced by increasing εr and decreasing dge. The breakdown voltage of the device was enhanced by increasing εr and TP. The highest breakdown voltage of 970 V and the lowest leakage current of 0.5 nA/mm were achieved under the conditions of εr = 80, TP = 800 nm, and dge = 10 nm. C-V simulation revealed that the HPG-SBDs induced no parasitic capacitance by comparing the integrated charges of the devices with different high-K dielectrics and different dge.

Electrical in-situ characterisation of interface stabilised organic thin-film transistors

PubMed Central

Striedinger, Bernd; Fian, Alexander; Petritz, Andreas; Lassnig, Roman; Winkler, Adolf; Stadlober, Barbara

2015-01-01

We report on the electrical in-situ characterisation of organic thin film transistors under high vacuum conditions. Model devices in a bottom-gate/bottom-contact (coplanar) configuration are electrically characterised in-situ, monolayer by monolayer (ML), while the organic semiconductor (OSC) is evaporated by organic molecular beam epitaxy (OMBE). Thermal SiO2 with an optional polymer interface stabilisation layer serves as the gate dielectric and pentacene is chosen as the organic semiconductor. The evolution of transistor parameters is studied on a bi-layer dielectric of a 150 nm of SiO2 and 20 nm of poly((±)endo,exo-bicyclo[2.2.1]hept-5-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) and compared to the behaviour on a pure SiO2 dielectric. The thin layer of PNDPE, which is an intrinsically photo-patternable organic dielectric, shows an excellent stabilisation performance, significantly reducing the calculated interface trap density at the OSC/dielectric interface up to two orders of magnitude, and thus remarkably improving the transistor performance. PMID:26457122

Design and implementation of power efficient 10-bit dual port SRAM on 28 nm technology

NASA Astrophysics Data System (ADS)

Gulati, Anmol; Gupta, Ashutosh; Murgai, Shruti; Bhaskar, Lala

2016-03-01

In this paper, 10 bit synchronous clock gated Dual port RAM has been designed. The negative latch based clock gating technique has been employed to optimize the power of the design. The design has been implemented on XV7K70T device, -3 speed grade, and kintex 7 FPGA family on Xilinx ISE Design Suite 14.7 using 28 nm technology. The design has been synthesized using Verilog HDL. We have been successful in achieving approximately 55 % reduction in total clock power, 81.55% reduction in BRAM power, 82.65%, 0.07%, 1.04% and 11.31% reduction in static power, 72.32%, 38.60%, 68.74% and 71.97%, reduction in dynamic power and 72.44%, 16.96%, 60.88% and 71.06% reduction in total supply power at 1 THz, 1GHz, 100 GHz and 1000 GHz frequency respectively. The power of the device has been calculated using XPower Analyzer tool of Xilinx ISE Design Suite 14.7.

T-gate geometric (solution for submicrometer gate length) HEMT: Physical analysis, modeling and implementation as parasitic elements and its usage as dual gate for variable gain amplifiers

NASA Astrophysics Data System (ADS)

Gupta, Ritesh; Rathi, Servin; Kaur, Ravneet; Gupta, Mridula; Gupta, R. S.

2009-03-01

In order to achieve superior RF performance, short gate length is required for the compound semiconductor field effect transistors, but the limitation in lithography for submicrometer gate lengths leads to the formation of various metal-insulator geometries like T-gate [Sandeep R. Bahl, Jesus A. del Alamo, Physics of breakdown in InAlAs/ n +-InGaAs heterostructure field-effect transistors, IEEE Trans. Electron Devices 41 (12) (1994) 2268-2275]. These geometries are the combination of various Metal-Semiconductor (MS)/Metal-Air-Semiconductor (MAS) contacts. Moreover, field plates [S. Karmalkar, M.S. Shur, G. Simin, M. Asif Khan, Field-plate engineering for HFETs, IEEE Trans. Electron Devices 52 (2005) 2534-2540] are also being fabricated these days, mainly at the drain end ( Γ-gate) having Metal-Insulator-Semiconductor (MIS) instead of MAS contact with the intention of increasing the breakdown voltage of the device. To realize the effect of upper gate electrode in the T-gate structure and field plates, an analytical model has been proposed in the present article by dividing the whole structure into MS/MIS contact regions, applying current continuity among them and solving iteratively. The model proposed for Metal-Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) [R. Gupta, S.K. Aggarwal, M. Gupta, R.S. Gupta, Analytical model for metal insulator semiconductor high electron mobility transistor (MISHEMT) for its high frequency and high power applications, J. Semicond. Technol. Sci. 6 (3) (2006) 189-198], is equally applicable to High Electron Mobility Transistors (HEMT) and has been used to formulate this model. In this paper, various structures and geometries have been compared to anticipate the need of T-gate modeling. The effect of MIS contacts has been implemented as parasitic resistance and capacitance and has also been studied to control the middle conventional gate as in dual gate technology by applying separate voltages across it. The results obtained using the proposed analytical scheme has been compared with simulated and experimental results, to prove the validity of our model.

Enhancing the noise performance of monolithic microwave integrated circuit-based low noise amplifiers through the use of a discrete preamplifying transistor

NASA Astrophysics Data System (ADS)

McCulloch, Mark A.; Melhuish, Simon J.; Piccirillo, Lucio

2015-01-01

An approach to enhancing the noise performance of an InP monolithic microwave integrated circuit (MMIC)-based low noise amplifiers (LNA) through the use of a discrete 100-nm gate length InP high electron mobility transistor is outlined. This LNA, known as a transistor in front of MMIC (T + MMIC) LNA, possesses a gain in excess of 40 dB and an average noise temperature of 9.4 K across the band 27 to 33 GHz at a physical temperature of 8 K. This compares favorably with 14.5 K for an LNA containing an equivalent MMIC. A simple advanced design system model offering further insights into the operation of the LNA is also presented and the LNA is compared with the current state-of-the-art Planck LFI LNAs.

Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

NASA Astrophysics Data System (ADS)

Huynh-Bao, Trong; Ryckaert, Julien; Sakhare, Sushil; Mercha, Abdelkarim; Verkest, Diederik; Thean, Aaron; Wambacq, Piet

2016-03-01

In this paper, we present a layout and performance analysis of logic and SRAM circuits for vertical and lateral GAA FETs using 5nm (iN5) design rules. Extreme ultra-violet lithography (EUVL) processes are exploited to print the critical features: 32 nm gate pitch and 24 nm metal pitch. Layout architectures and patterning compromises for enabling the 5nm node will be discussed in details. A distinct standard-cell template for vertical FETs is proposed and elaborated for the first time. To assess electrical performances, a BSIM-CMG model has been developed and calibrated with TCAD simulations, which accounts for the quasi-ballistic transport in the nanowire channel. The results show that the inbound power rail layout construct for vertical devices could achieve the highest density while the interleaving diffusion template can maximize the port accessibility. By using a representative critical path circuit of a generic low power SoCs, it is shown that the VFET-based circuit is 40% more energy efficient than LFET designs at iso-performance. Regarding SRAMs, benefits given by vertical channel orientation in VFETs has reduced the SRAM area by 20%~30% compared to lateral SRAMs. A double exposures with EUV canner is needed to reach a minimum tip-to-tip (T2T) of 16 nm for middle-of-line (MOL) layers. To enable HD SRAMs with two metal layers, a fully self-aligned gate contact for LFETs and 2D routing of the top electrode for VFETs are required. The standby leakage of vertical SRAMs is 4~6X lower than LFET-based SRAMs at iso-performance and iso-area. The minimum operating voltage (Vmin) of vertical SRAMs is 170 mV lower than lateral SRAMs. A high-density SRAM bitcell of 0.014 um2 can be obtained for the iN5 technology node, which fully follows the SRAM scaling trend for the 45nm nodes and beyond.

Deutsch, Toffoli, and cnot Gates via Rydberg Blockade of Neutral Atoms

NASA Astrophysics Data System (ADS)

Shi, Xiao-Feng

2018-05-01

Universal quantum gates and quantum error correction (QEC) lie at the heart of quantum-information science. Large-scale quantum computing depends on a universal set of quantum gates, in which some gates may be easily carried out, while others are restricted to certain physical systems. There is a unique three-qubit quantum gate called the Deutsch gate [D (θ )], from which a circuit can be constructed so that any feasible quantum computing is attainable. We design an easily realizable D (θ ) by using the Rydberg blockade of neutral atoms, where θ can be tuned to any value in [0 ,π ] by adjusting the strengths of external control fields. Using similar protocols, we further show that both the Toffoli and controlled-not gates can be achieved with only three laser pulses. The Toffoli gate, being universal for classical reversible computing, is also useful for QEC, which plays an important role in quantum communication and fault-tolerant quantum computation. The possibility and speed of realizing these gates shed light on the study of quantum information with neutral atoms.

High fidelity quantum gates with vibrational qubits.

PubMed

Berrios, Eduardo; Gruebele, Martin; Shyshlov, Dmytro; Wang, Lei; Babikov, Dmitri

2012-11-26

Physical implementation of quantum gates acting on qubits does not achieve a perfect fidelity of 1. The actual output qubit may not match the targeted output of the desired gate. According to theoretical estimates, intrinsic gate fidelities >99.99% are necessary so that error correction codes can be used to achieve perfect fidelity. Here we test what fidelity can be accomplished for a CNOT gate executed by a shaped ultrafast laser pulse interacting with vibrational states of the molecule SCCl(2). This molecule has been used as a test system for low-fidelity calculations before. To make our test more stringent, we include vibrational levels that do not encode the desired qubits but are close enough in energy to interfere with population transfer by the laser pulse. We use two complementary approaches: optimal control theory determines what the best possible pulse can do; a more constrained physical model calculates what an experiment likely can do. Optimal control theory finds pulses with fidelity >0.9999, in excess of the quantum error correction threshold with 8 × 10(4) iterations. On the other hand, the physical model achieves only 0.9992 after 8 × 10(4) iterations. Both calculations converge as an inverse power law toward unit fidelity after >10(2) iterations/generations. In principle, the fidelities necessary for quantum error correction are reachable with qubits encoded by molecular vibrations. In practice, it will be challenging with current laboratory instrumentation because of slow convergence past fidelities of 0.99.

Three-photon excitation source at 1250 nm generated in a dual zero dispersion wavelength nonlinear fiber

DOE PAGES

Domingue, Scott R.; Bartels, Randy A.

2014-12-04

Here, we demonstrate 1250 nm pulses generated in dual-zero dispersion photonic crystal fiber capable of three-photon excitation fluorescence microscopy. The total power conversion efficiency from the 28 fs seed pulse centered at 1075 nm to pulses at 1250 nm, including coupling losses from the nonlinear fiber, is 35%, with up to 67% power conversion efficiency of the fiber coupled light. Frequency-resolved optical gating measurements characterize 1250 nm pulses at 0.6 nJ and 2 nJ, illustrating the change in nonlinear spectral phase accumulation with pulse energy even for nonlinear fiber lengths < 50 mm. The 0.6 nJ pulse has a 26more » fs duration and is the shortest nonlinear fiber derived 1250 nm pulse yet reported (to the best of our knowledge). The short pulse durations and energies make these pulses a viable route to producing light at 1250 nm for multiphoton microscopy, which we we demonstrate here, via a three-photon excitation fluorescence microscope.« less

Relationship between effective mobility and border traps associated with charge trapping in In0.7Ga0.3As MOSFETs with various high-κ stacks

NASA Astrophysics Data System (ADS)

Kwon, Hyuk-Min; Kim, Dae-Hyun; Kim, Tae-Woo

2018-03-01

The effective mobility and reliability characteristics of In0.7Ga0.3As quantum-well (QW) MOSFETs with various high-κ gate stacks and HEMTs with a Schottky gate under bias temperature instability (BTI) stress were investigated. The effective mobilities (μeff) of HEMTs, single-layer Al2O3, bilayer Al2O3 (0.6 nm)/HfO2 (2.0 nm), and Al2O3 (0.6 nm)/HfO2 (3.0 nm) were ˜9000, ˜6158, ˜4789, and ˜4447 cm2 V-1 s-1 at N inv = 1.5 × 1012/cm2, respectively. The maximum effective mobility of In0.7Ga0.3As channel MOSFETs was compared with that of In0.7Ga0.3As/In0.48Al0.52As HEMTs, which are interface and border trap-free FETs. The results showed that the effective channel mobility was sensitive to traps in high-κ dielectrics related to interface trap density and border traps in the oxide. The ΔV T degradation of the bilayer Al2O3/HfO2 under BTI stress was greater than that of a single Al2O3 layer because the HfO2 layer had a high density of oxygen vacancies which were related to border traps.

Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

NASA Astrophysics Data System (ADS)

Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

2017-02-01

This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm-2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

Quantification of calcium using localized normalization on laser-induced breakdown spectroscopy data

NASA Astrophysics Data System (ADS)

Sabri, Nursalwanie Mohd; Haider, Zuhaib; Tufail, Kashif; Aziz, Safwan; Ali, Jalil; Wahab, Zaidan Abdul; Abbas, Zulkifly

2017-03-01

This paper focuses on localized normalization for improved calibration curves in laser-induced breakdown spectroscopy (LIBS) measurements. The calibration curves have been obtained using five samples consisting of different concentrations of calcium (Ca) in potassium bromide (KBr) matrix. The work has utilized Q-switched Nd:YAG laser installed in LIBS2500plus system with fundamental wavelength and laser energy of 650 mJ. Optimization of gate delay can be obtained from signal-to-background ratio (SBR) of Ca II 315.9 and 317.9 nm. The optimum conditions are determined in which having high spectral intensity and SBR. The highest spectral lines of ionic and emission lines of Ca at gate delay of 0.83 µs. From SBR, the optimized gate delay is at 5.42 µs for both Ca II spectral lines. Calibration curves consist of three parts; original intensity from LIBS experimentation, normalization and localized normalization of the spectral line intensity. The R2 values of the calibration curves plotted using locally normalized intensities of Ca I 610.3, 612.2 and 616.2 nm spectral lines are 0.96329, 0.97042, and 0.96131, respectively. The enhancement from calibration curves using the regression coefficient allows more accurate analysis in LIBS. At the request of all authors of the paper, and with the agreement of the Proceedings Editor, an updated version of this article was published on 24 May 2017.

Ultraclean single, double, and triple carbon nanotube quantum dots with recessed Re bottom gates

NASA Astrophysics Data System (ADS)

Jung, Minkyung; Schindele, Jens; Nau, Stefan; Weiss, Markus; Baumgartner, Andreas; Schoenenberger, Christian

2014-03-01

Ultraclean carbon nanotubes (CNTs) that are free from disorder provide a promising platform to manipulate single electron or hole spins for quantum information. Here, we demonstrate that ultraclean single, double, and triple quantum dots (QDs) can be formed reliably in a CNT by a straightforward fabrication technique. The QDs are electrostatically defined in the CNT by closely spaced metallic bottom gates deposited in trenches in Silicon dioxide by sputter deposition of Re. The carbon nanotubes are then grown by chemical vapor deposition (CVD) across the trenches and contacted using conventional electron beam lithography. The devices exhibit reproducibly the characteristics of ultraclean QDs behavior even after the subsequent electron beam lithography and chemical processing steps. We demonstrate the high quality using CNT devices with two narrow bottom gates and one global back gate. Tunable by the gate voltages, the device can be operated in four different regimes: i) fully p-type with ballistic transport between the outermost contacts (over a length of 700 nm), ii) clean n-type single QD behavior where a QD can be induced by either the left or the right bottom gate, iii) n-type double QD and iv) triple bipolar QD where the middle QD has opposite doping (p-type). Research at Basel is supported by the NCCR-Nano, NCCR-QIST, ERC project QUEST, and FP7 project SE2ND.

Graphene field effect transistor without an energy gap.

PubMed

Jang, Min Seok; Kim, Hyungjun; Son, Young-Woo; Atwater, Harry A; Goddard, William A

2013-05-28

Graphene is a room temperature ballistic electron conductor and also a very good thermal conductor. Thus, it has been regarded as an ideal material for postsilicon electronic applications. A major complication is that the relativistic massless electrons in pristine graphene exhibit unimpeded Klein tunneling penetration through gate potential barriers. Thus, previous efforts to realize a field effect transistor for logic applications have assumed that introduction of a band gap in graphene is a prerequisite. Unfortunately, extrinsic treatments designed to open a band gap seriously degrade device quality, yielding very low mobility and uncontrolled on/off current ratios. To solve this dilemma, we propose a gating mechanism that leads to a hundredfold enhancement in on/off transmittance ratio for normally incident electrons without any band gap engineering. Thus, our saw-shaped geometry gate potential (in place of the conventional bar-shaped geometry) leads to switching to an off state while retaining the ultrahigh electron mobility in the on state. In particular, we report that an on/off transmittance ratio of 130 is achievable for a sawtooth gate with a gate length of 80 nm. Our switching mechanism demonstrates that intrinsic graphene can be used in designing logic devices without serious alteration of the conventional field effect transistor architecture. This suggests a new variable for the optimization of the graphene-based device--geometry of the gate electrode.

Middle Electrode in a Vertical Transistor Structure Using an Sn Layer by Thermal Evaporation

NASA Astrophysics Data System (ADS)

Nogueira, Gabriel Leonardo; da Silva Ozório, Maiza; da Silva, Marcelo Marques; Morais, Rogério Miranda; Alves, Neri

2018-05-01

We report a process for performing the middle electrode for a vertical field effect transistor (VOFET) by the evaporation of a tin (Sn) layer. Bare aluminum oxide (Al2O3), obtained by anodization, and Al2O3 covered with a polymethylmethacrylate (PMMA) layer were used as the gate dielectric. We measured the electrical resistance of Sn while the evaporation was carried out to find the best condition to prepare the middle electrode, that is, good lateral conduction associated with openings that give permeability to the electric field in a vertical direction. This process showed that 55 nm Sn thick is suitable for use in a VOFET, being easier to achieve optimal thickness when the Sn is evaporated onto PMMA than onto bare Al2O3. The addition of a PMMA layer on the Al2O3 surface modifies the morphology of the Sn layer, resulting in a lowering of the threshold voltage. The values of threshold voltage and electric field, VTH = - 8 V and ETH = 354.5 MV/m respectively, were calculated using an Al2O3 film 20 nm thick covered with a 14 nm PMMA layer as gate dielectric, while for bare Al2O3 these values were VTH = - 10 V and ETH = 500 MV/m.

Method for reworkable packaging of high speed, low electrical parasitic power electronics modules through gate drive integration

DOEpatents

Passmore, Brandon; Cole, Zach; Whitaker, Bret; Barkley, Adam; McNutt, Ty; Lostetter, Alexander

2016-08-02

A multichip power module directly connecting the busboard to a printed-circuit board that is attached to the power substrate enabling extremely low loop inductance for extreme environments such as high temperature operation. Wire bond interconnections are taught from the power die directly to the busboard further enabling enable low parasitic interconnections. Integration of on-board high frequency bus capacitors provide extremely low loop inductance. An extreme environment gate driver board allows close physical proximity of gate driver and power stage to reduce overall volume and reduce impedance in the control circuit. Parallel spring-loaded pin gate driver PCB connections allows a reliable and reworkable power module to gate driver interconnections.

High-fidelity gates in quantum dot spin qubits

PubMed Central

Koh, Teck Seng; Coppersmith, S. N.; Friesen, Mark

2013-01-01

Several logical qubits and quantum gates have been proposed for semiconductor quantum dots controlled by voltages applied to top gates. The different schemes can be difficult to compare meaningfully. Here we develop a theoretical framework to evaluate disparate qubit-gating schemes on an equal footing. We apply the procedure to two types of double-dot qubits: the singlet–triplet and the semiconducting quantum dot hybrid qubit. We investigate three quantum gates that flip the qubit state: a DC pulsed gate, an AC gate based on logical qubit resonance, and a gate-like process known as stimulated Raman adiabatic passage. These gates are all mediated by an exchange interaction that is controlled experimentally using the interdot tunnel coupling g and the detuning ϵ, which sets the energy difference between the dots. Our procedure has two steps. First, we optimize the gate fidelity (f) for fixed g as a function of the other control parameters; this yields an that is universal for different types of gates. Next, we identify physical constraints on the control parameters; this yields an upper bound that is specific to the qubit-gate combination. We show that similar gate fidelities should be attainable for singlet-triplet qubits in isotopically purified Si, and for hybrid qubits in natural Si. Considerably lower fidelities are obtained for GaAs devices, due to the fluctuating magnetic fields ΔB produced by nuclear spins. PMID:24255105

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pratap, Surender; Sarkar, Niladri, E-mail: niladri@pilani.bits-pilani.ac.in

Self-Consistent Quantum Method using Schrodinger-Poisson equations have been used for determining the Channel electron density of Nano-Scale MOSFETs for 6nm and 9nm thick channels. The 6nm thick MOSFET show the peak of the electron density at the middle where as the 9nm thick MOSFET shows the accumulation of the electrons at the oxide/semiconductor interface. The electron density in the channel is obtained from the diagonal elements of the density matrix; [ρ]=[1/(1+exp(β(H − μ)))] A Tridiagonal Hamiltonian Matrix [H] is constructed for the oxide/channel/oxide 1D structure for the dual gate MOSFET. This structure is discretized and Finite-Difference method is used formore » constructing the matrix equation. The comparison of these results which are obtained by Quantum methods are done with Semi-Classical methods.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Lee, Choong Hyun; Nishimura, Tomonori

We investigated yttrium scandate (YScO{sub 3}) as an alternative high-permittivity (k) dielectric thin film for Ge gate stack formation. Significant enhancement of k-value is reported in YScO{sub 3} comparing to both of its binary compounds, Y{sub 2}O{sub 3} and Sc{sub 2}O{sub 3}, without any cost of interface properties. It suggests a feasible approach to a design of promising high-k dielectrics for Ge gate stack, namely, the formation of high-k ternary oxide out of two medium-k binary oxides. Aggressive scaling of equivalent oxide thickness (EOT) with promising interface properties is presented by using YScO{sub 3} as high-k dielectric and yttrium-doped GeO{submore » 2} (Y-GeO{sub 2}) as interfacial layer, for a demonstration of high-k gate stack on Ge. In addition, we demonstrate Ge n-MOSFET performance showing the peak electron mobility over 1000 cm{sup 2}/V s in sub-nm EOT region by YScO{sub 3}/Y-GeO{sub 2}/Ge gate stack.« less

Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance

NASA Astrophysics Data System (ADS)

Tayal, Shubham; Nandi, Ashutosh

2018-06-01

This paper for the first time investigates the effect of temperature variation on analog/RF performance of SiO2 as well as high-K gate dielectric based junctionless silicon nanotube FET (JL-SiNTFET). It is observed that the change in temperature does not variate the analog/RF performance of junctionless silicon nanotube FET by substantial amount. By increasing the temperature from 77 K to 400 K, the deterioration in intrinsic dc gain (AV) is marginal that is only ∼3 dB. Furthermore, the variation in cut-off frequency (fT), maximum oscillation frequency (fMAX), and gain-frequency product (GFP) with temperature is also minimal in JLSiNT-FET. More so, the same trend is observed even at scaled gate length (Lg = 15 nm). Furthermore, we have observed that the use of high-K gate dielectric deteriorates the analog/RF performance of JLSiNT-FET. However, the use of high-K gate dielectric negligibly changes the effect of temperature variation on analog/RF performance of JLSINT-FET device.

Examining kinesin processivity within a general gating framework

PubMed Central

Andreasson, Johan OL; Milic, Bojan; Chen, Geng-Yuan; Guydosh, Nicholas R; Hancock, William O; Block, Steven M

2015-01-01

Kinesin-1 is a dimeric motor that transports cargo along microtubules, taking 8.2-nm steps in a hand-over-hand fashion. The ATP hydrolysis cycles of its two heads are maintained out of phase by a series of gating mechanisms, which lead to processive runs averaging ∼1 μm. A key structural element for inter-head coordination is the neck linker (NL), which connects the heads to the stalk. To examine the role of the NL in regulating stepping, we investigated NL mutants of various lengths using single-molecule optical trapping and bulk fluorescence approaches in the context of a general framework for gating. Our results show that, although inter-head tension enhances motor velocity, it is crucial neither for inter-head coordination nor for rapid rear-head release. Furthermore, cysteine-light mutants do not produce wild-type motility under load. We conclude that kinesin-1 is primarily front-head gated, and that NL length is tuned to enhance unidirectional processivity and velocity. DOI: http://dx.doi.org/10.7554/eLife.07403.001 PMID:25902401

rf Quantum Capacitance of the Topological Insulator Bi2Se3 in the Bulk Depleted Regime for Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Inhofer, A.; Duffy, J.; Boukhicha, M.; Bocquillon, E.; Palomo, J.; Watanabe, K.; Taniguchi, T.; Estève, I.; Berroir, J. M.; Fève, G.; Plaçais, B.; Assaf, B. A.

2018-02-01

A metal-dielectric topological-insulator capacitor device based on hexagonal-boron-nitrate- (h -BN) encapsulated CVD-grown Bi2Se3 is realized and investigated in the radio-frequency regime. The rf quantum capacitance and device resistance are extracted for frequencies as high as 10 GHz and studied as a function of the applied gate voltage. The superior quality h -BN gate dielectric combined with the optimized transport characteristics of CVD-grown Bi2Se3 (n ˜1018 cm-3 in 8 nm) on h -BN allow us to attain a bulk depleted regime by dielectric gating. A quantum-capacitance minimum and a linear variation of the capacitance with the chemical potential are observed revealing a Dirac regime. The topological surface state in proximity to the gate is seen to reach charge neutrality, but the bottom surface state remains charged and capacitively coupled to the top via the insulating bulk. Our work paves the way toward implementation of topological materials in rf devices.

Effects of trap-assisted tunneling on gate-induced drain leakage in silicon-germanium channel p-type FET for scaled supply voltages

NASA Astrophysics Data System (ADS)

Tiwari, Vishal A.; Divakaruni, Rama; Hook, Terence B.; Nair, Deleep R.

2016-04-01

Silicon-germanium is considered as an alternative channel material to silicon p-type FET (pFET) for the development of energy efficient high performance transistors for 28 nm and beyond in a high-k metal gate technology because of its lower threshold voltage and higher mobility. However, gate-induced drain leakage (GIDL) is a concern for high threshold voltage device design because of tunneling at reduced bandgap. In this work, the trap-assisted tunneling and band-to-band tunneling (BTBT) effects on GIDL is analyzed and modeled for SiGe pFETs. Experimental results and Monte Carlo simulation results reveal that the pre-halo germanium pre-amorphization implant used to contain the short channel effects contribute to GIDL at the drain sidewall in addition to GIDL due to BTBT in SiGe devices. The results are validated by comparing the experimental observations with the numerical simulation and a set of calibrated models are used to describe the GIDL mechanisms for various drain and gate bias.

Carbon nanotube feedback-gate field-effect transistor: suppressing current leakage and increasing on/off ratio.

PubMed

Qiu, Chenguang; Zhang, Zhiyong; Zhong, Donglai; Si, Jia; Yang, Yingjun; Peng, Lian-Mao

2015-01-27

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

Gate-Tuned Thermoelectric Power in Black Phosphorus.

PubMed

Saito, Yu; Iizuka, Takahiko; Koretsune, Takashi; Arita, Ryotaro; Shimizu, Sunao; Iwasa, Yoshihiro

2016-08-10

The electric field effect is a useful means of elucidating intrinsic material properties as well as for designing functional devices. The electric-double-layer transistor (EDLT) enables the control of carrier density in a wide range, which is recently proved to be an effective tool for the investigation of thermoelectric properties. Here, we report the gate-tuning of thermoelectric power in a black phosphorus (BP) single crystal flake with the thickness of 40 nm. Using an EDLT configuration, we successfully control the thermoelectric power (S) and find that the S of ion-gated BP reached +510 μV/K at 210 K in the hole depleted state, which is much higher than the reported bulk single crystal value of +340 μV/K at 300 K. We compared this experimental data with the first-principles-based calculation and found that this enhancement is qualitatively explained by the effective thinning of the conduction channel of the BP flake and nonuniformity of the channel owing to the gate operation in a depletion mode. Our results provide new opportunities for further engineering BP as a thermoelectric material in nanoscale.

93-133 GHz Band InP High-Electron-Mobility Transistor Amplifier with Gain-Enhanced Topology

NASA Astrophysics Data System (ADS)

Sato, Masaru; Shiba, Shoichi; Matsumura, Hiroshi; Takahashi, Tsuyoshi; Nakasha, Yasuhiro; Suzuki, Toshihide; Hara, Naoki

2013-04-01

In this study, we developed a new type of high-frequency amplifier topology using 75-nm-gate-length InP-based high-electron-mobility transistors (InP HEMTs). To enhance the gain for a wide frequency range, a common-source common-gate hybrid amplifier topology was proposed. A transformer-based balun placed at the input of the amplifier generates differential signals, which are fed to the gate and source terminals of the transistor. The amplified signal is outputted at the drain node. The simulation results show that the hybrid topology exhibits a higher gain from 90 to 140 GHz than that of the conventional common-source or common-gate amplifier. The two-stage amplifier fabricated using the topology exhibits a small signal gain of 12 dB and a 3-dB bandwidth of 40 GHz (93-133 GHz), which is the largest bandwidth and the second highest gain reported among those of published 120-GHz-band amplifiers. In addition, the measured noise figure was 5 dB from 90 to 100 GHz.

Organic transistors making use of room temperature ionic liquids as gating medium

NASA Astrophysics Data System (ADS)

Hoyos, Jonathan Javier Sayago

The ability to couple ionic and electronic transport in organic transistors, based on pi conjugated organic materials for the transistor channel, can be particularly interesting to achieve low voltage transistor operation, i.e. below 1 V. The operation voltage in typical organic transistors based on conventional dielectrics (200 nm thick SiO2) is commonly higher than 10 V. Electrolyte-gated (EG) transistors, i.e. employing an electrolyte as the gating medium, permit current modulations of several orders of magnitude at relatively low gate voltages thanks to the exceptionally high capacitance at the electrolyte/transistor channel interface, in turn due to the low thickness (ca. 3 nm) of the electrical double layers forming at the electrolyte/semiconductor interface. Electrolytes based on room temperature ionic liquids (RTILs) are promising in EG transistor applications for their high electrochemical stability and good ionic conductivity. The main motivation behind this work is to achieve low voltage operation in organic transistors by making use of RTILs as gating medium. First we demonstrate the importance of the gate electrode material in the EG transistor performance. The use of high surface area carbon gate electrodes limits undesirable electrochemical processes and renders unnecessary the presence of a reference electrode to monitor the channel potential. This was demonstrated using activated carbon as gate electrode, the electronic conducting polymer MEH-PPV, poly[2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylene vinylene] channel material, and the ionic liquid [EMIM][TFSI] (1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide), as gating medium. Using high surface area gate electrodes resulted in sub-1 V operation and charge carrier mobilities of (1.0 +/- 0.5) x 10-2 cm2V -1s-1. A challenge in the field of EG transistors is to decrease their response time, a consequence of the slow ion redistribution in the transistor channel upon application of electric biases. We systematically investigated EG transistors employing RTILs belonging to the same family, i.e. based on a common anion and different cations. The transistor characteristics showed a limited cation influence in establishing the p-type doping of the conducting polymer. Interestingly, we observed that the transistor response time depends on at least two processes: the redistribution of ions from the electrolyte into the transistor channel, affecting the gate-source current (I gs); and the redistribution of charges in the transistor channel, affecting the drain-source current (Ids), as a function of time. The two processes have different rates, with the latter being the slowest. Incorporating propylene carbonate in the electrolyte proved to be an effective solution to increase the ionic conductivity, to lower the viscosity and, consequently, to reduce the transistor response time. Finally, we were able to demonstrate a multifunctional device integrating the transistor logic function with that of energy storage in a supercapacitor: the TransCap. The polymer/electrolyte/carbon vertical stacking of the EG transistor features the cell configuration of a hybrid supercapacitor. Supercapacitors are high specific power systems that, for their ability to store/deliver charge within short times may outperform batteries in applications having high power demand. When the TransCap is ON (open transistor channel), the polymer and the carbon gate electrodes store charge (Q) at a given Vgs, hence the stored energy equals Q˙V gs. When the TransCap is switched OFF, the channel and the gate are discharged and the energy can be delivered back to power other electronic components. EG transistors, making use of activated carbon as gate electrode and different RTILs as well as RTIL solvent mixtures as electrolyte gating medium, are interesting towards low voltage printable electronics. The high capacitance at the interface between the electrolyte and the transistor channel enables energy storage within the EG transistor architecture.

Simulating the performance of a distance-3 surface code in a linear ion trap

NASA Astrophysics Data System (ADS)

Trout, Colin J.; Li, Muyuan; Gutiérrez, Mauricio; Wu, Yukai; Wang, Sheng-Tao; Duan, Luming; Brown, Kenneth R.

2018-04-01

We explore the feasibility of implementing a small surface code with 9 data qubits and 8 ancilla qubits, commonly referred to as surface-17, using a linear chain of 171Yb+ ions. Two-qubit gates can be performed between any two ions in the chain with gate time increasing linearly with ion distance. Measurement of the ion state by fluorescence requires that the ancilla qubits be physically separated from the data qubits to avoid errors on the data due to scattered photons. We minimize the time required to measure one round of stabilizers by optimizing the mapping of the two-dimensional surface code to the linear chain of ions. We develop a physically motivated Pauli error model that allows for fast simulation and captures the key sources of noise in an ion trap quantum computer including gate imperfections and ion heating. Our simulations showed a consistent requirement of a two-qubit gate fidelity of ≥99.9% for the logical memory to have a better fidelity than physical two-qubit operations. Finally, we perform an analysis of the error subsets from the importance sampling method used to bound the logical error rates to gain insight into which error sources are particularly detrimental to error correction.

Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tari, Alireza, E-mail: atari@uwaterloo.ca; Lee, Czang-Ho; Wong, William S.

Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer intomore » the IGZO and resulted in higher resistivity films.« less

Undoped Si/SiGe Depletion-Mode Few-Electron Double Quantum Dots

NASA Astrophysics Data System (ADS)

Borselli, Matthew; Huang, Biqin; Ross, Richard; Croke, Edward; Holabird, Kevin; Hazard, Thomas; Watson, Christopher; Kiselev, Andrey; Deelman, Peter; Alvarado-Rodriguez, Ivan; Schmitz, Adele; Sokolich, Marko; Gyure, Mark; Hunter, Andrew

2011-03-01

We have successfully formed a double quantum dot in the sSi/SiGe material system without need for intentional dopants. In our design, a two-dimensional electron gas is formed in a strained silicon well by forward biasing a global gate. Lateral definition of quantum dots is established with reverse-biased gates with ~ 40 nm critical dimensions. Low-temperature capacitance and Hall measurements confirm electrons are confined in the Si-well with mobilities > 10 4 cm 2 / V - s . Further characterization identifies practical gate bias limits for this design and will be compared to simulation. Several double dot devices have been brought into the few-electron Coulomb blockade regime as measured by through-dot transport. Honeycomb diagrams and nonlinear through-dot transport measurements are used to quantify dot capacitances and addition energies of several meV. Sponsored by United States Department of Defense. Approved for Public Release, Distribution Unlimited.

Polarization entangled cluster state generation in a lithium niobate chip

NASA Astrophysics Data System (ADS)

Szep, Attila; Kim, Richard; Shin, Eunsung; Fanto, Michael L.; Osman, Joseph; Alsing, Paul M.

2016-10-01

We present a design of a quantum information processing C-phase (Controlled-phase) gate applicable for generating cluster states that has a form of integrated photonic circuits assembled with cascaded directional couplers on a Ti in-diffused Lithium Niobate (Ti-LN) platform where directional couplers as the integrated optical analogue of bulk beam splitters are used as fundamental building blocks. Based on experimentally optimized fabrication parameters of Ti-LN optical waveguides operating at an 810nm wavelength, an integrated Ti-LN quantum C-phase gate is designed and simulated. Our proposed C-phase gate consists of three tunable directional couplers cascaded together with having different weighted switching ratios for providing a tool of routing vertically- and horizontally-polarized photons independently. Its operation mechanism relies on selectively controlling the optical coupling of orthogonally polarized modes via the change in the index of refraction, and its operation is confirmed by the BPM simulation.

Raman imaging of carrier distribution in the channel of an ionic liquid-gated transistor fabricated with regioregular poly(3-hexylthiophene)

NASA Astrophysics Data System (ADS)

Wada, Y.; Enokida, I.; Yamamoto, J.; Furukawa, Y.

2018-05-01

Raman images of carriers (positive polarons) at the channel of an ionic liquid-gated transistor (ILGT) fabricated with regioregular poly(3-hexylthiophene) (P3HT) have been measured with excitation at 785 nm. The observed spectra indicate that carriers generated are positive polarons. The intensities of the 1415 cm-1 band attributed to polarons in the P3HT channel were plotted as Raman images; they showed the carrier density distribution. When the source-drain voltage VD is lower than the source-gate voltage VG (linear region), the carrier density was uniform. When VD is nearly equal to VG (saturation region), a negative carrier density gradient from the source electrode towards the drain electrode was observed. This carrier density distribution is associated with the observed current-voltage characteristics, which is not consistent with the "pinch-off" theory of inorganic semiconductor transistors.

Phagocytosis: studies by optical tweezers and time-resolved microspectrofluorometry

NASA Astrophysics Data System (ADS)

Schneckenburger, Herbert; Sailer, Reinhard; Hendinger, Anita; Gschwend, Michael H.; Bauer, Manfred; Strauss, Wolfgang S. L.

1999-01-01

Cellular uptake of transparent Latex particles by J774A.1 mouse macrophages has been studied: First, single beads were kept within an optical light trap and located in close vicinity to individual cells. Uptake of the beads was visualized, and intrinsic fluorescence was detected in the spectral range of 420 - 530 nm. Second, time-gated fluorescence spectra of single cells were recorded at pre- selected times during one hour after cellular uptake. A rapid increase of autofluorescence and a subsequent decrease to the level of control cells within about 10 min. was measured within a time gate of 0 - 5 ns after the exciting laser pulses, and attributed to the 'free' coenzyme NAD(P)H. In contrast, fluorescence increase of NAD(P)H bound to proteins (measured within time gates of 5 - 10 ns or 10 - 15 ns) was less pronounced, and the subsequent decrease occurred within a longer period (about one hour).

Nonvolatile MoS2 field effect transistors directly gated by single crystalline epitaxial ferroelectric

NASA Astrophysics Data System (ADS)

Lu, Zhongyuan; Serrao, Claudy; Khan, Asif Islam; You, Long; Wong, Justin C.; Ye, Yu; Zhu, Hanyu; Zhang, Xiang; Salahuddin, Sayeef

2017-07-01

We demonstrate non-volatile, n-type, back-gated, MoS2 transistors, placed directly on an epitaxial grown, single crystalline, PbZr0.2Ti0.8O3 (PZT) ferroelectric. The transistors show decent ON current (19 μA/μm), high on-off ratio (107), and a subthreshold swing of (SS ˜ 92 mV/dec) with a 100 nm thick PZT layer as the back gate oxide. Importantly, the ferroelectric polarization can directly control the channel charge, showing a clear anti-clockwise hysteresis. We have self-consistently confirmed the switching of the ferroelectric and corresponding change in channel current from a direct time-dependent measurement. Our results demonstrate that it is possible to obtain transistor operation directly on polar surfaces, and therefore, it should be possible to integrate 2D electronics with single crystalline functional oxides.

Electrolyte gated TFT biosensors based on the Donnan's capacitance of anchored biomolecules

NASA Astrophysics Data System (ADS)

Manoli, Kyriaki; Palazzo, Gerardo; Macchia, Eleonora; Tiwari, Amber; Di Franco, Cinzia; Scamarcio, Gaetano; Favia, Pietro; Mallardi, Antonia; Torsi, Luisa

2017-08-01

Biodetection using electrolyte gated field effect transistors has been mainly correlated to charge modulated transduction. Therefore, such platforms are designed and studied for limited applications involving relatively small charged species and much care is taken in the operating conditions particularly pH and salt concentration (ionic strength). However, there are several reports suggesting that the device conductance can also be very sensitive towards variations in the capacitance coupling. Understanding the sensing mechanism is important for further exploitation of these promising sensors in broader range of applications. In this paper, we present a thorough and in depth study of a multilayer protein system coupled to an electrolyte gated transistor. It is demonstrated that detection associated to a binding event taking place at a distance of 30 nm far from the organic semiconductor-electrolyte interface is possible and the device conductance is dominated by Donnan's capacitance of anchored biomolecules.

Vertical InAs nanowire wrap gate transistors with f(t) > 7 GHz and f(max) > 20 GHz.

PubMed

Egard, M; Johansson, S; Johansson, A-C; Persson, K-M; Dey, A W; Borg, B M; Thelander, C; Wernersson, L-E; Lind, E

2010-03-10

In this letter we report on high-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors). The nanowire transistors are fabricated from InAs nanowires that are epitaxially grown on a semi-insulating InP substrate. All three terminals of the MOSFETs are defined by wrap around contacts. This makes it possible to perform high-frequency measurements on the vertical InAs MOSFETs. We present S-parameter measurements performed on a matrix consisting of 70 InAs nanowire MOSFETs, which have a gate length of about 100 nm. The highest unity current gain cutoff frequency, f(t), extracted from these measurements is 7.4 GHz and the maximum frequency of oscillation, f(max), is higher than 20 GHz. This demonstrates that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires.

Automated cart with VIS/NIR hyperspectral reflectance and fluorescence imaging capabilities

USDA-ARS?s Scientific Manuscript database

A system to take high-resolution VIS/NIR hyperspectral reflectance and fluorescence images in outdoor fields using ambient lighting or a pulsed laser (355 nm), respectively, for illumination was designed, built, and tested. Components of the system include a semi-autonomous cart, a gated-intensified...

80. AVALON DAM Photographic copy of construction drawing c1908 ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

80. AVALON DAM - Photographic copy of construction drawing c1908 (from aperture card located at Bureau of Reclamation, Salt Lake City). UNTITLED DRAWING OF AUTOMATIC FLOOD GATES. PARTIAL PLAN AND ELEVATION - Carlsbad Irrigation District, Avalon Dam, On Pecos River, 4 miles North of Carlsbad, Carlsbad, Eddy County, NM

70. AVALON DAM Photographic copy of historic photo, August ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

70. AVALON DAM - Photographic copy of historic photo, August 5, 1911 (original print located at the Carlsbad Irrigation District offices, Carlsbad, New Mexico) photographer unknown AUTOMATIC GATES AT SPILLWAY NO. 1 - Carlsbad Irrigation District, Avalon Dam, On Pecos River, 4 miles North of Carlsbad, Carlsbad, Eddy County, NM

71. AVALON DAM Photographic copy of historic photo, 1911 ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

71. AVALON DAM - Photographic copy of historic photo, 1911 (original print located at the Carlsbad Irrigation District offices, Carlsbad, New Mexico) photographer unknown 'VIEW SHOWING CONSTRUCTION OF THE CYLINDER GATES' - Carlsbad Irrigation District, Avalon Dam, On Pecos River, 4 miles North of Carlsbad, Carlsbad, Eddy County, NM

34. MAIN CANAL Photographic copy of construction drawing c1907 ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

34. MAIN CANAL - Photographic copy of construction drawing c1907 (from Record Group 115, Box 17, Denver Branch of the National Archives, Denver) CHECK GATES ABOVE DARK CANYON SIPHON - Carlsbad Irrigation District, Main Canal, 4 miles North to 12 miles Southeast of Carlsbad, Carlsbad, Eddy County, NM

36. MAIN CANAL Photographic copy of construction drawing dated ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

36. MAIN CANAL - Photographic copy of construction drawing dated 1907 (from Record Group 115, Box 17, Denver Branch of the National Archives, Denver) WASTE GATES ABOVE DARK CANYON SIPHON - Carlsbad Irrigation District, Main Canal, 4 miles North to 12 miles Southeast of Carlsbad, Carlsbad, Eddy County, NM

Metallocarbohedrenes: Transmission Electron Microscopy of Mass Gated Deposits

NASA Astrophysics Data System (ADS)

Castleman, M. E. Lyn, Jr.

2002-03-01

Titanium and zirconium Met-Car cluster ions have been detected from the direct laser vaporization of metal-graphite mixtures using time-of-flight mass spectrometry. Optimization of the production conditions enabled sufficient intensities to mass select and deposit Met-Cars on surfaces. High-resolution transmission electron microscopy images of mass gated Met-Car species reveals deposited nanocrystals 2 nm in diameter. Diffraction patterns indicate the presence of multiple species and shows that the deposits have spatial orientation. Lattice parameters have been extracted. The implication of the findings will be discussed. Support for the work has been from the AFOSR F49620-01-1-0122.

Logic reversibility and thermodynamic irreversibility demonstrated by DNAzyme-based Toffoli and Fredkin logic gates.

PubMed

Orbach, Ron; Remacle, Françoise; Levine, R D; Willner, Itamar

2012-12-26

The Toffoli and Fredkin gates were suggested as a means to exhibit logic reversibility and thereby reduce energy dissipation associated with logic operations in dense computing circuits. We present a construction of the logically reversible Toffoli and Fredkin gates by implementing a library of predesigned Mg(2+)-dependent DNAzymes and their respective substrates. Although the logical reversibility, for which each set of inputs uniquely correlates to a set of outputs, is demonstrated, the systems manifest thermodynamic irreversibility originating from two quite distinct and nonrelated phenomena. (i) The physical readout of the gates is by fluorescence that depletes the population of the final state of the machine. This irreversible, heat-releasing process is needed for the generation of the output. (ii) The DNAzyme-powered logic gates are made to operate at a finite rate by invoking downhill energy-releasing processes. Even though the three bits of Toffoli's and Fredkin's logically reversible gates manifest thermodynamic irreversibility, we suggest that these gates could have important practical implication in future nanomedicine.

Signatures of Mechanosensitive Gating.

PubMed

Morris, Richard G

2017-01-10

The question of how mechanically gated membrane channels open and close is notoriously difficult to address, especially if the protein structure is not available. This perspective highlights the relevance of micropipette-aspirated single-particle tracking-used to obtain a channel's diffusion coefficient, D, as a function of applied membrane tension, σ-as an indirect assay for determining functional behavior in mechanosensitive channels. While ensuring that the protein remains integral to the membrane, such methods can be used to identify not only the gating mechanism of a protein, but also associated physical moduli, such as torsional and dilational rigidity, which correspond to the protein's effective shape change. As an example, three distinct D-versus-σ "signatures" are calculated, corresponding to gating by dilation, gating by tilt, and gating by a combination of both dilation and tilt. Both advantages and disadvantages of the approach are discussed. Copyright © 2017 Biophysical Society. Published by Elsevier Inc. All rights reserved.

Gate-Sensing the Potential Landscape of a GaAs Two-Dimensional Electron Gas

NASA Astrophysics Data System (ADS)

Croot, Xanthe; Mahoney, Alice; Pauka, Sebastian; Colless, James; Reilly, David; Watson, John; Fallahi, Saeed; Gardner, Geoff; Manfra, Michael; Lu, Hong; Gossard, Arthur

In situ dispersive gate sensors hold potential as a means of enabling the scalable readout of quantum dot arrays. Sensitive to quantum capacitance, dispersive sensors have been used to detect inter- and intra-dot transitions in GaAs double quantum dots, and can distinguish the spin states of singlet triplet qubits. In addition, the gate-sensing technique is likely of value in probing the physics of Majorana zero modes in nanowire devices. Beyond the readout signatures associated with charge and spin configurations of qubits, gate-sensing is sensitive to trapped charge in the potential landscape. Here, we report gate-sensing signals arising from tunnelling of electrons between puddles of trapped charge in a GaAs 2DEG. We examine these signals in a family of different devices with varying mobilities, and as a function of temperature and bias. Implications for qubit readout using the gate-sensing technique are discussed.

Picosecond imaging of signal propagation in integrated circuits

NASA Astrophysics Data System (ADS)

Frohmann, Sven; Dietz, Enrico; Dittrich, Helmar; Hübers, Heinz-Wilhelm

2017-04-01

Optical analysis of integrated circuits (IC) is a powerful tool for analyzing security functions that are implemented in an IC. We present a photon emission microscope for picosecond imaging of hot carrier luminescence in ICs in the near-infrared spectral range from 900 to 1700 nm. It allows for a semi-invasive signal tracking in fully operational ICs on the gate or transistor level with a timing precision of approximately 6 ps. The capabilities of the microscope are demonstrated by imaging the operation of two ICs made by 180 and 60 nm process technology.

Ultrahigh near infrared photoresponsive organic field-effect transistors with lead phthalocyanine/C60 heterojunction on poly(vinyl alcohol) gate dielectric.

PubMed

Sun, Lei; Zhang, Jianping; Zhao, Feiyu; Luo, Xiao; Lv, Wenli; li, Yao; Ren, Qiang; Wen, Zhanwei; Peng, Yingquan; Liu, Xingyuan

2015-05-08

Performances of photoresponsive organic field-effect transistors (photOFETs) operating in the near infrared (NIR) region utilizing SiO2 as the gate dielectric is generally low due to low carrier mobility of the channel. We report on NIR photOFETs based on lead phthalocyanine (PbPc)/C60 heterojunction with ultrahigh photoresponsivity by utilizing poly(vinyl alcohol) (PVA) as the gate dielectric. For 808 nm NIR illumination of 1.69 mW cm(-2), an ultrahigh photoresponsivity of 21 A W(-1), and an external quantum efficiency of 3230% were obtained at a gate voltage of 30 V and a drain voltage of 80 V, which are 124 times and 126 times as large as the reference device with SiO2 as the gate dielectric, respectively. The ultrahigh enhancement of photoresponsivity is resulted from the huge increase of electron mobility of C60 film grown on PVA dielectric. AFM investigations revealed that the C60 film grown on PVA is much smooth and uniform and the grain size is much larger than that grown on SiO2 dielectric, which together results in four orders of magnitude increase of the field-effect electron mobility of C60 film.

Using in-process measurements of open-gate structures to evaluate threshold voltage of normally-off GaN-based high electron mobility transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hou, Bin; Ma, Xiao-Hua, E-mail: xhma@xidian.edu.cn, E-mail: yhao@xidian.edu.cn; Chen, Wei-Wei

The parameters of open-gate structures treated with different etching time were monitored during the gate recess process, and their impacts on the threshold voltage (V{sub th}) of final fabricated AlGaN/GaN high electron mobility transistors (HEMTs) based on open-gate structures were discussed in this paper. It is found that V{sub th} can exceed 0 V when channel resistance in the recessed region (R{sub on-open}) increases over ∼275 Ω mm, maximum current (I{sub Dmax}) decreases below ∼29 mA/mm, or recessed barrier thickness (t{sub RB}) is below ∼7.5 nm. In addition, t{sub RB} obtained by atomic force microscopy measurements and C-V measurements are also compared. Finally,more » theoretical common criteria based on the experimental results of this work for t{sub RB} and R{sub on-open} were established to evaluate the V{sub th} of a regular normally-off AlGaN/GaN HEMTs. The results indicate that these parameters of open-gate structure can be utilized to achieve normally-off HEMTs with controllable V{sub th}.« less

Performance of a 512 x 512 Gated CMOS Imager with a 250 ps Exposure Time

DOE Office of Scientific and Technical Information (OSTI.GOV)

Teruya, A T; Moody, J D; Hsing, W W

2012-10-01

We describe the performance of a 512x512 gated CMOS read out integrated circuit (ROIC) with a 250 ps exposure time. A low-skew, H-tree trigger distribution system is used to locally generate individual pixel gates in each 8x8 neighborhood of the ROIC. The temporal width of the gate is voltage controlled and user selectable via a precision potentiometer. The gating implementation was first validated in optical tests of a 64x64 pixel prototype ROIC developed as a proof-of-concept during the early phases of the development program. The layout of the H-Tree addresses each quadrant of the ROIC independently and admits operation ofmore » the ROIC in two modes. If “common mode” triggering is used, the camera provides a single 512x512 image. If independent triggers are used, the camera can provide up to four 256x256 images with a frame separation set by the trigger intervals. The ROIC design includes small (sub-pixel) optical photodiode structures to allow test and characterization of the ROIC using optical sources prior to bump bonding. Reported test results were obtained using short pulse, second harmonic Ti:Sapphire laser systems operating at λ~ 400 nm at sub-ps pulse widths.« less

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

NASA Astrophysics Data System (ADS)

Sharma, Vijay Kumar; Pattanaik, Manisha

2015-11-01

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

Exploring the structure and function of Thermotoga maritima CorA reveals the mechanism of gating and ion selectivity in Co2+/Mg2+ transport

PubMed Central

Nordin, Nurhuda; Guskov, Albert; Phua, Terri; Sahaf, Newsha; Xia, Yu; Lu, Siyan; Eshaghi, Hojjat; Eshaghi, Said

2013-01-01

The CorA family of divalent cation transporters utilizes Mg2+ and Co2+ as primary substrates. The molecular mechanism of its function, including ion selectivity and gating, has not been fully characterized. Recently we reported a new structure of a CorA homologue from Methanocaldococcus jannaschii, which provided novel structural details that offered the conception of a unique gating mechanism involving conversion of an open hydrophilic gate into a closed hydrophobic one. In the present study we report functional evidence for this novel gating mechanism in the Thermotoga maritima CorA together with an improved crystal structure of this CorA to 2.7 Å (1 Å=0.1 nm) resolution. The latter reveals the organization of the selectivity filter to be similar to that of M. jannaschii CorA and also the previously unknown organization of the second signature motif of the CorA family. The proposed gating is achieved by a helical rotation upon the binding of a metal ion substrate to the regulatory binding sites. Additionally, our data suggest that the preference of this CorA for Co2+ over Mg2+ is controlled by the presence of threonine side chains in the channel. Finally, the roles of the intracellular metal-binding sites have been assigned to increased thermostability and regulation of the gating. These mechanisms most likely apply to the entire CorA family as they are regulated by the highly conserved amino acids. PMID:23425532

Coherent molecular transistor: control through variation of the gate wave function.

PubMed

Ernzerhof, Matthias

2014-03-21

In quantum interference transistors (QUITs), the current through the device is controlled by variation of the gate component of the wave function that interferes with the wave function component joining the source and the sink. Initially, mesoscopic QUITs have been studied and more recently, QUITs at the molecular scale have been proposed and implemented. Typically, in these devices the gate lead is subjected to externally adjustable physical parameters that permit interference control through modifications of the gate wave function. Here, we present an alternative model of a molecular QUIT in which the gate wave function is directly considered as a variable and the transistor operation is discussed in terms of this variable. This implies that we specify the gate current as well as the phase of the gate wave function component and calculate the resulting current through the source-sink channel. Thus, we extend on prior works that focus on the phase of the gate wave function component as a control parameter while having zero or certain discrete values of the current. We address a large class of systems, including finite graphene flakes, and obtain analytic solutions for how the gate wave function controls the transistor.

High-fidelity gates in quantum dot spin qubits.

PubMed

Koh, Teck Seng; Coppersmith, S N; Friesen, Mark

2013-12-03

Several logical qubits and quantum gates have been proposed for semiconductor quantum dots controlled by voltages applied to top gates. The different schemes can be difficult to compare meaningfully. Here we develop a theoretical framework to evaluate disparate qubit-gating schemes on an equal footing. We apply the procedure to two types of double-dot qubits: the singlet-triplet and the semiconducting quantum dot hybrid qubit. We investigate three quantum gates that flip the qubit state: a DC pulsed gate, an AC gate based on logical qubit resonance, and a gate-like process known as stimulated Raman adiabatic passage. These gates are all mediated by an exchange interaction that is controlled experimentally using the interdot tunnel coupling g and the detuning [Symbol: see text], which sets the energy difference between the dots. Our procedure has two steps. First, we optimize the gate fidelity (f) for fixed g as a function of the other control parameters; this yields an f(opt)(g) that is universal for different types of gates. Next, we identify physical constraints on the control parameters; this yields an upper bound f(max) that is specific to the qubit-gate combination. We show that similar gate fidelities (~99:5%) should be attainable for singlet-triplet qubits in isotopically purified Si, and for hybrid qubits in natural Si. Considerably lower fidelities are obtained for GaAs devices, due to the fluctuating magnetic fields ΔB produced by nuclear spins.

Beta-Estradiol Regulates Voltage-Gated Calcium Channels and Estrogen Receptors in Telocytes from Human Myometrium.

PubMed

Banciu, Adela; Banciu, Daniel Dumitru; Mustaciosu, Cosmin Catalin; Radu, Mihai; Cretoiu, Dragos; Xiao, Junjie; Cretoiu, Sanda Maria; Suciu, Nicolae; Radu, Beatrice Mihaela

2018-05-09

Voltage-gated calcium channels and estrogen receptors are essential players in uterine physiology, and their association with different calcium signaling pathways contributes to healthy and pathological conditions of the uterine myometrium. Among the properties of the various cell subtypes present in human uterine myometrium, there is increasing evidence that calcium oscillations in telocytes (TCs) contribute to contractile activity and pregnancy. Our study aimed to evaluate the effects of beta-estradiol on voltage-gated calcium channels and estrogen receptors in TCs from human uterine myometrium and to understand their role in pregnancy. For this purpose, we employed patch-clamp recordings, ratiometric Fura-2-based calcium imaging analysis, and qRT-PCR techniques for the analysis of cultured human myometrial TCs derived from pregnant and non-pregnant uterine samples. In human myometrial TCs from both non-pregnant and pregnant uterus, we evidenced by qRT-PCR the presence of genes encoding for voltage-gated calcium channels (Cav3.1, Ca3.2, Cav3.3, Cav2.1), estrogen receptors (ESR1, ESR2, GPR30), and nuclear receptor coactivator 3 (NCOA3). Pregnancy significantly upregulated Cav3.1 and downregulated Cav3.2, Cav3.3, ESR1, ESR2, and NCOA3, compared to the non-pregnant condition. Beta-estradiol treatment (24 h, 10, 100, 1000 nM) downregulated Cav3.2, Cav3.3, Cav1.2, ESR1, ESR2, GRP30, and NCOA3 in TCs from human pregnant uterine myometrium. We also confirmed the functional expression of voltage-gated calcium channels by patch-clamp recordings and calcium imaging analysis of TCs from pregnant human myometrium by perfusing with BAY K8644, which induced calcium influx through these channels. Additionally, we demonstrated that beta-estradiol (1000 nM) antagonized the effect of BAY K8644 (2.5 or 5 µM) in the same preparations. In conclusion, we evidenced the presence of voltage-gated calcium channels and estrogen receptors in TCs from non-pregnant and pregnant human uterine myometrium and their gene expression regulation by beta-estradiol in pregnant conditions. Further exploration of the calcium signaling in TCs and its modulation by estrogen hormones will contribute to the understanding of labor and pregnancy mechanisms and to the development of effective strategies to reduce the risk of premature birth.

Inhibition of Voltage-Gated Calcium Channels as Common Mode of Action for (Mixtures of) Distinct Classes of Insecticides

PubMed Central

Meijer, Marieke; Dingemans, Milou M.L.; van den Berg, Martin; Westerink, Remco H.S.

2014-01-01

Humans are exposed to distinct structural classes of insecticides with different neurotoxic modes of action. Because calcium homeostasis is essential for proper neuronal function and development, we investigated the effects of insecticides from different classes (pyrethroid: (α-)cypermethrin; organophosphate: chlorpyrifos; organochlorine: endosulfan; neonicotinoid: imidacloprid) and mixtures thereof on the intracellular calcium concentration ([Ca2+]i). Effects of acute (20 min) exposure to (mixtures of) insecticides on basal and depolarization-evoked [Ca2+]i were studied in vitro with Fura-2-loaded PC12 cells and high resolution single-cell fluorescence microscopy. The data demonstrate that cypermethrin, α-cypermethrin, endosulfan, and chlorpyrifos concentration-dependently decreased depolarization-evoked [Ca2+]i, with 50% (IC50) at 78nM, 239nM, 250nM, and 899nM, respectively. Additionally, acute exposure to chlorpyrifos or endosulfan (10μM) induced a modest increase in basal [Ca2+]i, amounting to 68 ± 8nM and 53 ± 8nM, respectively. Imidacloprid did not disturb basal or depolarization-evoked [Ca2+]i at 10μM. Following exposure to binary mixtures, effects on depolarization-evoked [Ca2+]i were within the expected effect additivity range, whereas the effect of the tertiary mixture was less than this expected additivity effect range. These results demonstrate that different types of insecticides inhibit depolarization-evoked [Ca2+]i in PC12 cells by inhibiting voltage-gated calcium channels (VGCCs) in vitro at concentrations comparable with human occupational exposure levels. Moreover, the effective concentrations in this study are below those for earlier described modes of action. Because inhibition of VGCCs appears to be a common and potentially additive mode of action of several classes of insecticides, this target should be considered in neurotoxicity risk assessment studies. PMID:24913802

Instantons in Self-Organizing Logic Gates

NASA Astrophysics Data System (ADS)

Bearden, Sean R. B.; Manukian, Haik; Traversa, Fabio L.; Di Ventra, Massimiliano

2018-03-01

Self-organizing logic is a recently suggested framework that allows the solution of Boolean truth tables "in reverse"; i.e., it is able to satisfy the logical proposition of gates regardless to which terminal(s) the truth value is assigned ("terminal-agnostic logic"). It can be realized if time nonlocality (memory) is present. A practical realization of self-organizing logic gates (SOLGs) can be done by combining circuit elements with and without memory. By employing one such realization, we show, numerically, that SOLGs exploit elementary instantons to reach equilibrium points. Instantons are classical trajectories of the nonlinear equations of motion describing SOLGs and connect topologically distinct critical points in the phase space. By linear analysis at those points, we show that these instantons connect the initial critical point of the dynamics, with at least one unstable direction, directly to the final fixed point. We also show that the memory content of these gates affects only the relaxation time to reach the logically consistent solution. Finally, we demonstrate, by solving the corresponding stochastic differential equations, that, since instantons connect critical points, noise and perturbations may change the instanton trajectory in the phase space but not the initial and final critical points. Therefore, even for extremely large noise levels, the gates self-organize to the correct solution. Our work provides a physical understanding of, and can serve as an inspiration for, models of bidirectional logic gates that are emerging as important tools in physics-inspired, unconventional computing.

REMOVAL OF TANK AND SEWER SEDIMENT BY GATE FLUSHING: COMPUTATIONAL FLUID DYNAMICS MODEL STUDIES

EPA Science Inventory

This presentation will discuss the application of a computational fluid dynamics 3D flow model to simulate gate flushing for removing tank/sewer sediments. The physical model of the flushing device was a tank fabricated and installed at the head-end of a hydraulic flume. The fl...

Fault-tolerant quantum computation with nondeterministic entangling gates

NASA Astrophysics Data System (ADS)

Auger, James M.; Anwar, Hussain; Gimeno-Segovia, Mercedes; Stace, Thomas M.; Browne, Dan E.

2018-03-01

Performing entangling gates between physical qubits is necessary for building a large-scale universal quantum computer, but in some physical implementations—for example, those that are based on linear optics or networks of ion traps—entangling gates can only be implemented probabilistically. In this work, we study the fault-tolerant performance of a topological cluster state scheme with local nondeterministic entanglement generation, where failed entangling gates (which correspond to bonds on the lattice representation of the cluster state) lead to a defective three-dimensional lattice with missing bonds. We present two approaches for dealing with missing bonds; the first is a nonadaptive scheme that requires no additional quantum processing, and the second is an adaptive scheme in which qubits can be measured in an alternative basis to effectively remove them from the lattice, hence eliminating their damaging effect and leading to better threshold performance. We find that a fault-tolerance threshold can still be observed with a bond-loss rate of 6.5% for the nonadaptive scheme, and a bond-loss rate as high as 14.5% for the adaptive scheme.

CNOT sequences for heterogeneous spin qubit architectures in a noisy environment

NASA Astrophysics Data System (ADS)

Ferraro, Elena; Fanciulli, Marco; de Michielis, Marco

Explicit CNOT gate sequences for two-qubits mixed architectures are presented in view of applications for large-scale quantum computation. Different kinds of coded spin qubits are combined allowing indeed the favorable physical properties of each to be employed. The building blocks for such composite systems are qubit architectures based on the electronic spin in electrostatically defined semiconductor quantum dots. They are the single quantum dot spin qubit, the double quantum dot singlet-triplet qubit and the double quantum dot hybrid qubit. The effective Hamiltonian models expressed by only exchange interactions between pair of electrons are exploited in different geometrical configurations. A numerical genetic algorithm that takes into account the realistic physical parameters involved is adopted. Gate operations are addressed by modulating the tunneling barriers and the energy offsets between different couple of quantum dots. Gate infidelities are calculated considering limitations due to unideal control of gate sequence pulses, hyperfine interaction and unwanted charge coupling. Second affiliation: Dipartimento di Scienza dei Materiali, University of Milano Bicocca, Via R. Cozzi, 55, 20126 Milano, Italy.

ZIF-67 derived porous Co3O4 hollow nanopolyhedron functionalized solution-gated graphene transistors for simultaneous detection of glucose and uric acid in tears.

PubMed

Xiong, Can; Zhang, Tengfei; Kong, Weiyu; Zhang, Zhixiang; Qu, Hao; Chen, Wei; Wang, Yanbo; Luo, Linbao; Zheng, Lei

2018-03-15

Biomarkers in tears have attracted much attention in daily healthcare sensing and monitoring. Here, highly sensitive sensors for simultaneous detection of glucose and uric acid are successfully constructed based on solution-gated graphene transistors (SGGTs) with two separate Au gate electrodes, modified with GOx-CHIT and BSA-CHIT respectively. The sensitivity of the SGGT is dramatically improved by co-modifying the Au gate with ZIF-67 derived porous Co 3 O 4 hollow nanopolyhedrons. The sensing mechanism for glucose sensor is attributed to the reaction of H 2 O 2 generated by the oxidation of glucose near the gate, while the sensing mechanism for uric acid is due to the direct electro-oxidation of uric acid molecules on the gate. The optimized glucose and uric acid sensors show the detection limits both down to 100nM, far beyond the sensitivity required for non-invasive detection of glucose and uric acid in tears. The glucose and uric acid in real tear samples was quantitatively detected at 323.2 ± 16.1μM and 98.5 ± 16.3μM by using the functionalized SGGT device. Due to the low-cost, high-biocompatibility and easy-fabrication features of the ZIF-67 derived porous Co 3 O 4 hollow nanopolyhedron, they provide excellent electrocatalytic nanomaterials for enhancing sensitivity of SGGTs for a broad range of disease-related biomarkers. Copyright © 2017 Elsevier B.V. All rights reserved.

Electron Spin Coherence Times in Si/SiGe Quantum Dots

NASA Astrophysics Data System (ADS)

Jock, R. M.; He, Jianhua; Tyryshkin, A. M.; Lyon, S. A.; Lee, C.-H.; Huang, S.-H.; Liu, C. W.

2014-03-01

Single electron spin states in silicon have shown a great deal of promise as qubits due to their long spin relaxation (T1) and coherence (T2) times. Recent results exhibit a T2 of 250 us for electrons confined in Si/SiGe quantum dots at 350 mK. These experiments used conventional X-band (10 GHz) pulsed Electron Spin Resonance on a large area (3.5 mm x 20 mm), dual-gated, undoped Si/SiGe heterostructure quantum dots. These dots are induced in a natural Si quantum well by e-beam defined gates having a lithographic radius of 150 nm and pitch of 700 nm. The relatively large size of these dots led to closely spaced energy levels and long T2's could only be measured at sub-Kelvin temperatures. At 2K confined electrons displayed a 3 us T2, which is comparable to that of 2D electrons at that temperature. Decreasing the quantum dot size increases the electron confinement and reduces the effects of valley-splitting and spin-orbit coupling on the electron spin coherence times. We will report results on dots with 80 nm lithographic radii and a 375 nm pitch. This device displays an extended electron coherence time of 30 us at 2K, suggesting tighter confinement of electrons. Further measurements at lower temperatures are in progress. This work was supported in part by NSF through the Materials World Network program (DMR-1107606) and the Princeton MRSEC (DMR-0819860), and in part by the U.S. Army Research Office (W911NF-13-1-0179).

45. McMILLAN DAM Photographic copy of historic photo, c1895 ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

45. McMILLAN DAM - Photographic copy of historic photo, c1895 (original print located at the Carlsbad Irrigation District offices, Carlsbad, New Mexico), photographer unknown. 'RAISING THE GATES AT LAKE McMILLAN' - Carlsbad Irrigation District, McMillan Dam, On Pecos River, 13 miles North of Carlsbad, Carlsbad, Eddy County, NM

65. AVALON DAM Photographic copy of historic photo, c1910 ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

65. AVALON DAM - Photographic copy of historic photo, c1910 (original print located at the Carlsbad Irrigation District offices, Carlsbad, New Mexico) photographer unknown VIEW OF U.S.R.S. ADMINISTRATIVE BUILDING (GATE KEEPER'S HOUSE) - Carlsbad Irrigation District, Avalon Dam, On Pecos River, 4 miles North of Carlsbad, Carlsbad, Eddy County, NM

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity

PubMed Central

Zhang, Fan; Niu, Hanben

2016-01-01

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 107 when illuminated by a 405-nm diode laser and 1/1.4 × 104 when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e− rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena. PMID:27367699

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity.

PubMed

Zhang, Fan; Niu, Hanben

2016-06-29

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 10⁷ when illuminated by a 405-nm diode laser and 1/1.4 × 10⁴ when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e(-) rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena.

Electrical Characteristics of WSi2 Nanocrystal Capacitors with Barrier-Engineered High-k Tunnel Layers

NASA Astrophysics Data System (ADS)

Lee, Hyo Jun; Lee, Dong Uk; Kim, Eun Kyu; You, Hee-Wook; Cho, Won-Ju

2011-06-01

Nanocrystal-floating gate capacitors with WSi2 nanocrystals and high-k tunnel layers were fabricated to improve the electrical properties such as retention, programming/erasing speed, and endurance. The WSi2 nanocrystals were distributed uniformly between the tunnel and control gate oxide layers. The electrical performance of the tunnel barrier with the SiO2/HfO2/Al2O3 (2/1/3 nm) (OHA) tunnel layer appeared to be better than that with the Al2O3/HfO2/Al2O3 (2/1/3 nm) (AHA) tunnel layer. When ΔVFB is about 1 V after applying voltage at ±8 V, the programming/erasing speeds of AHA and OHA tunnel layers are 300 ms and 500 µs, respectively. In particular, the device with WSi2 nanocrystals and the OHA tunnel barrier showed a large memory window of about 7.76 V when the voltage swept from 10 to -10 V, and it was maintained at about 2.77 V after 104 cycles.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE Office of Scientific and Technical Information (OSTI.GOV)

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

ALD Al2O3 passivation of Lg = 100 nm metamorphic InAlAs/InGaAs HEMTs with Si-doped Schottky layers on GaAs substrates

NASA Astrophysics Data System (ADS)

Sun, Bing; Chang, Hudong; Wang, Shengkai; Niu, Jiebin; Liu, Honggang

2017-12-01

In0.52Al0.48As/In0.7Ga0.3As metamorphic high-electron-mobility transistors (mHEMTs) on GaAs substrates have been demonstrated. The devices feature an epitaxial structure with Si-doped InP/In0.52Al0.48As Schottky layers, together with an atomic layer deposition (ALD) Al2O3 passivation process. In comparison to the GaAs mHEMTs with plasma enhanced chemical vapor deposition (PECVD) SiN passivation, the devices with ALD Al2O3 passivation exhibit more than one order of magnitude lower gate leakage current (Jg) and much lower contact resistance (RC) and specific contact resistivity (ρC). 100-nm gate length (Lg) In0.52Al0.48As/In0.7Ga0.3As mHEMTs with Si-doped InP/In0.52Al0.48As Schottky layers and ALD Al2O3 passivation exhibit excellent DC and RF characteristics, such as a maximum oscillation frequency (fmax) of 388.2 GHz.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

DOE PAGES

Llinas, Juan Pablo; Fairbrother, Andrew; Borin Barin, Gabriela; ...

2017-09-21

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (L ch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (I on > 1 μA at V d = -1 V) and highmore » I on /I off ~ 10 5 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.« less

Tuning Piezo ion channels to detect molecular-scale movements relevant for fine touch

PubMed Central

Poole, Kate; Herget, Regina; Lapatsina, Liudmila; Ngo, Ha-Duong; Lewin, Gary R.

2014-01-01

In sensory neurons, mechanotransduction is sensitive, fast and requires mechanosensitive ion channels. Here we develop a new method to directly monitor mechanotransduction at defined regions of the cell-substrate interface. We show that molecular-scale (~13 nm) displacements are sufficient to gate mechanosensitive currents in mouse touch receptors. Using neurons from knockout mice, we show that displacement thresholds increase by one order of magnitude in the absence of stomatin-like protein 3 (STOML3). Piezo1 is the founding member of a class of mammalian stretch-activated ion channels, and we show that STOML3, but not other stomatin-domain proteins, brings the activation threshold for Piezo1 and Piezo2 currents down to ~10 nm. Structure–function experiments localize the Piezo modulatory activity of STOML3 to the stomatin domain, and higher-order scaffolds are a prerequisite for function. STOML3 is the first potent modulator of Piezo channels that tunes the sensitivity of mechanically gated channels to detect molecular-scale stimuli relevant for fine touch. PMID:24662763

High quality HfO{sub 2}/p-GaSb(001) metal-oxide-semiconductor capacitors with 0.8 nm equivalent oxide thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barth, Michael; Datta, Suman, E-mail: sdatta@engr.psu.edu; Bruce Rayner, G.

2014-12-01

We investigate in-situ cleaning of GaSb surfaces and its effect on the electrical performance of p-type GaSb metal-oxide-semiconductor capacitor (MOSCAP) using a remote hydrogen plasma. Ultrathin HfO{sub 2} films grown by atomic layer deposition were used as a high permittivity gate dielectric. Compared to conventional ex-situ chemical cleaning methods, the in-situ GaSb surface treatment resulted in a drastic improvement in the impedance characteristics of the MOSCAPs, directly evidencing a much lower interface trap density and enhanced Fermi level movement efficiency. We demonstrate that by using a combination of ex-situ and in-situ surface cleaning steps, aggressively scaled HfO{sub 2}/p-GaSb MOSCAP structuresmore » with a low equivalent oxide thickness of 0.8 nm and efficient gate modulation of the surface potential are achieved, allowing to push the Fermi level far away from the valence band edge high up into the band gap of GaSb.« less

Bi-directional magnetic domain wall shift register

NASA Astrophysics Data System (ADS)

Read, D. E.; O'Brien, L.; Zeng, H. T.; Lewis, E. R.; Petit, D.; Cowburn, R. P.

2010-03-01

Data storage devices based on magnetic domain walls (DWs) propagating through ferromagnetic nanowires have attracted a great deal of attention in recent years [1,2]. Here we experimentally demonstrate a shift register based on an open-ended chain of ferromagnetic NOT gates. When used in combination with a globally applied magnetic field such devices can support bi-directional data flow [3]. We have demonstrated data writing, propagation, and readout in individually addressable NiFe nanowires 90 nm wide and 10 nm thick. Up to eight data bits are electrically input to the device, stored for extended periods without power supplied to the device, and then output using either a first in first out or a last in first out mode of operation. Compared to traditional electronic transistor-based circuits, the inherent bi-directionality afforded by these DW logic gates offers a range of devices that are reversible and not limited to only one mode of operation. [1] S. S. Parkin, US Patent 6,834,005 (2004) [2] D. A. Allwod, et al., Science 309 (5741), 1688 (2005) [3] L. O'Brien, et al. accepted for publication in APL (2009)

Analysis of current driving capability of pentacene TFTs for OLEDs

NASA Astrophysics Data System (ADS)

Ryu, Gi Seong; Byun, Hyun Sook; Xu, Yong Xian; Pyo, Kyung Soo; Choe, Ki Beom; Song, Chung Kun

2005-01-01

The flexible display and the application of Roll-To-Roll process is difficult because high temperature process of a-Si;H TFT and poly-Si TFT limited the use of plastic substrate. We proposed AMOLED using Pentacene TFT (OTFT) to fabricate flexible display. The first stage for OTFT application to OLED, we analyzed OTFT as driving device of OLED. The process performed on glass and plastic (PET) substrate that is coated ITO and PVP is used for gate insulator. The field effect mobility of the fabricated OTFT is 0.1~0.3cm2/V"sec and Ion/Ioff current ratio is 103~105. OLED is fabricated with two stories structure of TPD and Alq3, and we can observe the light at 5V by the naked eye. The wavelength of observed lights is 530nm ~550nm. We can confirm the driving of OLED due to OTFT using Test panel and observe OLED control by gate voltage of OTFT. Also, we verify designed structure and process, and make a demonstration fabricating 64 by 64 backplane based on Test panel.

Sensitivity, stability, and precision of quantitative Ns-LIBS-based fuel-air-ratio measurements for methane-air flames at 1-11 bar.

PubMed

Hsu, Paul S; Gragston, Mark; Wu, Yue; Zhang, Zhili; Patnaik, Anil K; Kiefer, Johannes; Roy, Sukesh; Gord, James R

2016-10-01

Nanosecond laser-induced breakdown spectroscopy (ns-LIBS) is employed for quantitative local fuel-air (F/A) ratio (i.e., ratio of actual fuel-to-oxidizer mass over ratio of fuel-to-oxidizer mass at stoichiometry, measurements in well-characterized methane-air flames at pressures of 1-11 bar). We selected nitrogen and hydrogen atomic-emission lines at 568 nm and 656 nm, respectively, to establish a correlation between the line intensities and the F/A ratio. We have investigated the effects of laser-pulse energy, camera gate delay, and pressure on the sensitivity, stability, and precision of the quantitative ns-LIBS F/A ratio measurements. We determined the optimal laser energy and camera gate delay for each pressure condition and found that measurement stability and precision are degraded with an increase in pressure. We have identified primary limitations of the F/A ratio measurement employing ns-LIBS at elevated pressures as instabilities caused by the higher density laser-induced plasma and the presence of the higher level of soot. Potential improvements are suggested.

Magnetoelectric domain wall dynamics and its implications for magnetoelectric memory

DOE PAGES

Belashchenko, K. D.; Tchernyshyov, O.; Kovalev, Alexey A.; ...

2016-03-30

Domain wall dynamics in a magnetoelectric antiferromagnet is analyzed, and its implications for magnetoelectric memory applications are discussed. Cr 2O 3 is used in the estimates of the materials parameters. It is found that the domain wall mobility has a maximum as a function of the electric field due to the gyrotropic coupling induced by it. In Cr 2O 3, the maximal mobility of 0.1 m/(s Oe) is reached at E≈0.06 V/nm. Fields of this order may be too weak to overcome the intrinsic depinning field, which is estimated for B-doped Cr 2O 3. These major drawbacks for device implementationmore » can be overcome by applying a small in-plane shear strain, which blocks the domain wall precession. Domain wall mobility of about 0.7 m/(s Oe) can then be achieved at E = 0.2 V/nm. Furthermore, a split-gate scheme is proposed for the domain-wall controlled bit element; its extension to multiple-gate linear arrays can offer advantages in memory density, programmability, and logic functionality.« less

High performance p-type organic thin film transistors with an intrinsically photopatternable, ultrathin polymer dielectric layer☆

PubMed Central

Petritz, Andreas; Wolfberger, Archim; Fian, Alexander; Krenn, Joachim R.; Griesser, Thomas; Stadlober, Barbara

2013-01-01

A high-performing bottom-gate top-contact pentacene-based oTFT technology with an ultrathin (25–48 nm) and electrically dense photopatternable polymeric gate dielectric layer is reported. The photosensitive polymer poly((±)endo,exo-bicyclo[2.2.1]hept-5-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) is patterned directly by UV-exposure (λ = 254 nm) at a dose typical for conventionally used negative photoresists without the need for any additional photoinitiator. The polymer itself undergoes a photo-Fries rearrangement reaction under UV illumination, which is accompanied by a selective cross-linking of the macromolecules, leading to a change in solubility in organic solvents. This crosslinking reaction and the negative photoresist behavior are investigated by means of sol–gel analysis. The resulting transistors show a field-effect mobility up to 0.8 cm2 V−1 s−1 at an operation voltage as low as −4.5 V. The ultra-low subthreshold swing in the order of 0.1 V dec−1 as well as the completely hysteresis-free transistor characteristics are indicating a very low interface trap density. It can be shown that the device performance is completely stable upon UV-irradiation and development according to a very robust chemical rearrangement. The excellent interface properties, the high stability and the small thickness make the PNDPE gate dielectric a promising candidate for fast organic electronic circuits. PMID:24748853

Conductance enhancement of InAs/InP heterostructure nanowires by surface functionalization with oligo(phenylene vinylene)s.

PubMed

Schukfeh, Muhammed Ihab; Storm, Kristian; Mahmoud, Ahmed; Søndergaard, Roar R; Szwajca, Anna; Hansen, Allan; Hinze, Peter; Weimann, Thomas; Svensson, Sofia Fahlvik; Bora, Achyut; Dick, Kimberly A; Thelander, Claes; Krebs, Frederik C; Lugli, Paolo; Samuelson, Lars; Tornow, Marc

2013-05-28

We have investigated the electronic transport through 3 μm long, 45 nm diameter InAs nanowires comprising a 5 nm long InP segment as electronic barrier. After assembly of 12 nm long oligo(phenylene vinylene) derivative molecules onto these InAs/InP nanowires, we observed a pronounced, nonlinear I-V characteristic with significantly increased currents of up to 1 μA at 1 V bias, for a back-gate voltage of 3 V. As supported by our model calculations based on a nonequilibrium Green Function approach, we attribute this effect to charge transport through those surface-bound molecules, which electrically bridge both InAs regions across the embedded InP barrier.

An analytic current-voltage model for quasi-ballistic III-nitride high electron mobility transistors

NASA Astrophysics Data System (ADS)

Li, Kexin; Rakheja, Shaloo

2018-05-01

We present an analytic model to describe the DC current-voltage (I-V) relationship in scaled III-nitride high electron mobility transistors (HEMTs) in which transport within the channel is quasi-ballistic in nature. Following Landauer's transport theory and charge calculation based on two-dimensional electrostatics that incorporates negative momenta states from the drain terminal, an analytic expression for current as a function of terminal voltages is developed. The model interprets the non-linearity of access regions in non-self-aligned HEMTs. Effects of Joule heating with temperature-dependent thermal conductivity are incorporated in the model in a self-consistent manner. With a total of 26 input parameters, the analytic model offers reduced empiricism compared to existing GaN HEMT models. To verify the model, experimental I-V data of InAlN/GaN with InGaN back-barrier HEMTs with channel lengths of 42 and 105 nm are considered. Additionally, the model is validated against numerical I-V data obtained from DC hydrodynamic simulations of an unintentionally doped AlGaN-on-GaN HEMT with 50-nm gate length. The model is also verified against pulsed I-V measurements of a 150-nm T-gate GaN HEMT. Excellent agreement between the model and experimental and numerical results for output current, transconductance, and output conductance is demonstrated over a broad range of bias and temperature conditions.

Fully industrialised single photon avalanche diodes

NASA Astrophysics Data System (ADS)

Pellegrini, S.; Rae, B.

2017-05-01

Single Photon Avalanche diodes (SPADs) were first realized more than five decades ago[1][1], and have now been industrialized for mass production in the 130 nm CMOS technology node by STMicroelectronics (STM). In this paper we present the latest STM SPAD with an excellent NIR photon detection probability (>5% at 850nm), a dark count rate median of 100 cps at room temperature and a low breakdown voltage of 14.2V. The dead time of the SPAD is approximately 25 ns, leading to a maximum count rate of 40 Mcps. Thanks to the 130 nm gate length of the CMOS technology used and the associated high digital gate density, complex digital signal processing can be implemented allowing fully integrated systems to be realized. The low bias required by the SPAD makes it possible for voltage generation to be achieved on-chip (e.g. charge pumped). We introduce our first generation time-of-flight system (VL6180) based on the STM SPAD technology, which is capable of ranging up to 60 cm in 60 ms. Ranging capabilities and accuracy are measured using a set of moving targets with reflectance of 5%, 17% and 88% in a fully automated test bed. To the best of our knowledge this was the first high volume SPAD-based device. To our knowledge this is the first time details of SPAD performance over production volumes and lifetime have been presented.

A two-qubit logic gate in silicon.

PubMed

Veldhorst, M; Yang, C H; Hwang, J C C; Huang, W; Dehollain, J P; Muhonen, J T; Simmons, S; Laucht, A; Hudson, F E; Itoh, K M; Morello, A; Dzurak, A S

2015-10-15

Quantum computation requires qubits that can be coupled in a scalable manner, together with universal and high-fidelity one- and two-qubit logic gates. Many physical realizations of qubits exist, including single photons, trapped ions, superconducting circuits, single defects or atoms in diamond and silicon, and semiconductor quantum dots, with single-qubit fidelities that exceed the stringent thresholds required for fault-tolerant quantum computing. Despite this, high-fidelity two-qubit gates in the solid state that can be manufactured using standard lithographic techniques have so far been limited to superconducting qubits, owing to the difficulties of coupling qubits and dephasing in semiconductor systems. Here we present a two-qubit logic gate, which uses single spins in isotopically enriched silicon and is realized by performing single- and two-qubit operations in a quantum dot system using the exchange interaction, as envisaged in the Loss-DiVincenzo proposal. We realize CNOT gates via controlled-phase operations combined with single-qubit operations. Direct gate-voltage control provides single-qubit addressability, together with a switchable exchange interaction that is used in the two-qubit controlled-phase gate. By independently reading out both qubits, we measure clear anticorrelations in the two-spin probabilities of the CNOT gate.

Adiabatic gate teleportation.

PubMed

Bacon, Dave; Flammia, Steven T

2009-09-18

The difficulty in producing precisely timed and controlled quantum gates is a significant source of error in many physical implementations of quantum computers. Here we introduce a simple universal primitive, adiabatic gate teleportation, which is robust to timing errors and many control errors and maintains a constant energy gap throughout the computation above a degenerate ground state space. This construction allows for geometric robustness based upon the control of two independent qubit interactions. Further, our piecewise adiabatic evolution easily relates to the quantum circuit model, enabling the use of standard methods from fault-tolerance theory for establishing thresholds.

Logic reversibility and thermodynamic irreversibility demonstrated by DNAzyme-based Toffoli and Fredkin logic gates

PubMed Central

Orbach, Ron; Remacle, Françoise; Levine, R. D.; Willner, Itamar

2012-01-01

The Toffoli and Fredkin gates were suggested as a means to exhibit logic reversibility and thereby reduce energy dissipation associated with logic operations in dense computing circuits. We present a construction of the logically reversible Toffoli and Fredkin gates by implementing a library of predesigned Mg2+-dependent DNAzymes and their respective substrates. Although the logical reversibility, for which each set of inputs uniquely correlates to a set of outputs, is demonstrated, the systems manifest thermodynamic irreversibility originating from two quite distinct and nonrelated phenomena. (i) The physical readout of the gates is by fluorescence that depletes the population of the final state of the machine. This irreversible, heat-releasing process is needed for the generation of the output. (ii) The DNAzyme-powered logic gates are made to operate at a finite rate by invoking downhill energy-releasing processes. Even though the three bits of Toffoli’s and Fredkin’s logically reversible gates manifest thermodynamic irreversibility, we suggest that these gates could have important practical implication in future nanomedicine. PMID:23236131

Development of Low Parasitic Light Sensitivity and Low Dark Current 2.8 μm Global Shutter Pixel †

PubMed Central

Yokoyama, Toshifumi; Tsutsui, Masafumi; Suzuki, Masakatsu; Nishi, Yoshiaki; Mizuno, Ikuo; Lahav, Assaf

2018-01-01

We developed a low parasitic light sensitivity (PLS) and low dark current 2.8 μm global shutter pixel. We propose a new inner lens design concept to realize both low PLS and high quantum efficiency (QE). 1/PLS is 7700 and QE is 62% at a wavelength of 530 nm. We also propose a new storage-gate based memory node for low dark current. P-type implants and negative gate biasing are introduced to suppress dark current at the surface of the memory node. This memory node structure shows the world smallest dark current of 9.5 e−/s at 60 °C. PMID:29370146

Development of Low Parasitic Light Sensitivity and Low Dark Current 2.8 μm Global Shutter Pixel.

PubMed

Yokoyama, Toshifumi; Tsutsui, Masafumi; Suzuki, Masakatsu; Nishi, Yoshiaki; Mizuno, Ikuo; Lahav, Assaf

2018-01-25

Abstract : We developed a low parasitic light sensitivity (PLS) and low dark current 2.8 μm global shutter pixel. We propose a new inner lens design concept to realize both low PLS and high quantum efficiency (QE). 1/PLS is 7700 and QE is 62% at a wavelength of 530 nm. We also propose a new storage-gate based memory node for low dark current. P-type implants and negative gate biasing are introduced to suppress dark current at the surface of the memory node. This memory node structure shows the world smallest dark current of 9.5 e - /s at 60 °C.

SCB Quantum Computers Using iSWAP and 1-Qubit Rotations

NASA Technical Reports Server (NTRS)

Williams, Colin; Echtemach, Pierre

2005-01-01

Units of superconducting circuitry that exploit the concept of the single- Cooper-pair box (SCB) have been built and are undergoing testing as prototypes of logic gates that could, in principle, constitute building blocks of clocked quantum computers. These units utilize quantized charge states as the quantum information-bearing degrees of freedom. An SCB is an artificial two-level quantum system that comprises a nanoscale superconducting electrode connected to a reservoir of Cooper-pair charges via a Josephson junction. The logical quantum states of the device, .0. and .1., are implemented physically as a pair of charge-number states that differ by 2e (where e is the charge of an electron). Typically, some 109 Cooper pairs are involved. Transitions between the logical states are accomplished by tunneling of Cooper pairs through the Josephson junction. Although the two-level system contains a macroscopic number of charges, in the superconducting regime, they behave collectively, as a Bose-Einstein condensate, making possible a coherent superposition of the two logical states. This possibility makes the SCB a candidate for the physical implementation of a qubit. A set of quantum logic operations and the gates that implement them is characterized as universal if, in principle, one can form combinations of the operations in the set to implement any desired quantum computation. To be able to design a practical quantum computer, one must first specify how to decompose any valid quantum computation into a sequence of elementary 1- and 2-qubit quantum gates that are universal and that can be realized in hardware that is feasible to fabricate. Traditionally, the set of universal gates has been taken to be the set of all 1-qubit quantum gates in conjunction with the controlled-NOT (CNOT) gate, which is a 2-qubit gate. Also, it has been known for some time that the SWAP gate, which implements square root of the simple 2-qubit exchange interaction, is as computationally universal as is the CNOT operation.

Dynamical decoupling of local transverse random telegraph noise in a two-qubit gate

NASA Astrophysics Data System (ADS)

D'Arrigo, A.; Falci, G.; Paladino, E.

2015-10-01

Achieving high-fidelity universal two-qubit gates is a central requisite of any implementation of quantum information processing. The presence of spurious fluctuators of various physical origin represents a limiting factor for superconducting nanodevices. Operating qubits at optimal points, where the qubit-fluctuator interaction is transverse with respect to the single qubit Hamiltonian, considerably improved single qubit gates. Further enhancement has been achieved by dynamical decoupling (DD). In this article we investigate DD of transverse random telegraph noise acting locally on each of the qubits forming an entangling gate. Our analysis is based on the exact numerical solution of the stochastic Schrödinger equation. We evaluate the gate error under local periodic, Carr-Purcell and Uhrig DD sequences. We find that a threshold value of the number, n, of pulses exists above which the gate error decreases with a sequence-specific power-law dependence on n. Below threshold, DD may even increase the error with respect to the unconditioned evolution, a behaviour reminiscent of the anti-Zeno effect.

Implementation of Basic and Universal Gates In a single Circuit Based On Quantum-dot Cellular Automata Using Multi-Layer Crossbar Wire

NASA Astrophysics Data System (ADS)

Bhowmik, Dhrubajyoti; Saha, Apu Kr; Dutta, Paramartha; Nandi, Supratim

2017-08-01

Quantum-dot Cellular Automata (QCA) is one of the most substitutes developing nanotechnologies for electronic circuits, as a result of lower force utilization, higher speed and smaller size in correlation with CMOS innovation. The essential devices, a Quantum-dot cell can be utilized to logic gates and wires. As it is the key building block on nanotechnology circuits. By applying simple gates, the hardware requirements for a QCA circuit can be decreased and circuits can be less complex as far as level, delay and cell check. This article exhibits an unobtrusive methodology for actualizing novel upgraded simple and universal gates, which can be connected to outline numerous variations of complex QCA circuits. Proposed gates are straightforward in structure and capable as far as implementing any digital circuits. The main aim is to build all basic and universal gates in a simple circuit with and without crossbar-wire. Simulation results and physical relations affirm its handiness in actualizing each advanced circuit.

Schools Adapting Curriculum to the Outdoors

ERIC Educational Resources Information Center

Manzo, Kathleen Kennedy

2008-01-01

Daily lessons at the Learning Gate Community School often tap the wonders of nature on the 27-acre campus, with its open fields and overgrown orange groves, and a treehouse overlooking an idyllic pond. Educators at Learning Gate say the outdoor classrooms and lessons are a balm for many of the ills that can hinder students' physical and mental…

Silicon-ion-implanted PMMA with nanostructured ultrathin layers for plastic electronics

NASA Astrophysics Data System (ADS)

Hadjichristov, G. B.; Ivanov, Tz E.; Marinov, Y. G.

2014-12-01

Being of interest for plastic electronics, ion-beam produced nanostructure, namely silicon ion (Si+) implanted polymethyl-methacrylate (PMMA) with ultrathin nanostructured dielectric (NSD) top layer and nanocomposite (NC) buried layer, is examined by electric measurements. In the proposed field-effect organic nanomaterial structure produced within the PMMA network by ion implantation with low energy (50 keV) Si+ at the fluence of 3.2 × 1016 cm-2 the gate NSD is ion-nanotracks-modified low-conductive surface layer, and the channel NC consists of carbon nanoclusters. In the studied ion-modified PMMA field-effect configuration, the gate NSD and the buried NC are formed as planar layers both with a thickness of about 80 nm. The NC channel of nano-clustered amorphous carbon (that is an organic semiconductor) provides a huge increase in the electrical conduction of the material in the subsurface region, but also modulates the electric field distribution in the drift region. The field effect via the gate NSD is analyzed. The most important performance parameters, such as the charge carrier field-effect mobility and amplification of this particular type of PMMA- based transconductance device with NC n-type channel and gate NSD top layer, are determined.

Control of short-channel effects in InAlN/GaN high-electron mobility transistors using graded AlGaN buffer

NASA Astrophysics Data System (ADS)

Han, Tiecheng; Zhao, Hongdong; Peng, Xiaocan; Li, Yuhai

2018-04-01

A graded AlGaN buffer is designed to realize the p-type buffer by inducing polarization-doping holes. Based on the two-dimensional device simulator, the effect of the graded AlGaN buffer on the direct-current (DC) and radio-frequency (RF) performance of short-gate InAlN/GaN high-electron mobility transistors (HEMTs) are investigated, theoretically. Compared to standard HEMT, an enhancement of electron confinement and a good control of short-channel effect (SCEs) are demonstrated in the graded AlGaN buffer HEMT. Accordingly, the pinched-off behavior and the ability of gate modulation are significantly improved. And, no serious SCEs are observed in the graded AlGaN buffer HEMT with an aspect ratio (LG/tch) of about 6.7, much lower than that of the standard HEMT (LG/tch = 13). In addition, for a 70-nm gate length, a peak current gain cutoff frequency (fT) of 171 GHz and power gain cutoff frequency (fmax) of 191 GHz are obtained in the grade buffer HEMT, which are higher than those of the standard one with the same gate length.

Surface modification of polyimide gate insulators for solution-processed 2,7-didecyl[1]benzothieno[3,2-b][1]benzothiophene (C10-BTBT) thin-film transistors.

PubMed

Jang, Kwang-Suk; Kim, Won Soo; Won, Jong-Myung; Kim, Yun-Ho; Myung, Sung; Ka, Jae-Won; Kim, Jinsoo; Ahn, Taek; Yi, Mi Hye

2013-01-21

The surface property of a polyimide gate insulator was successfully modified with an n-octadecyl side-chain. Alkyl chain-grafted poly(amic acid), the polyimide precursor, was synthesized using the diamine comonomer with an alkyl side-chain. By adding a base catalyst to the poly(amic acid) coating solution, the imidization temperature of the spin-coated film could be reduced to 200 °C. The 350 nm-thick polyimide film had a dielectric constant of 3.3 at 10 kHz and a leakage current density of less than 8.7 × 10(-10) A cm(-2), while biased from 0 to 100 V. To investigate the potential of the alkyl chain-grafted polyimide film as a gate insulator for solution-processed organic thin-film transistors (TFTs), we fabricated C(10)-BTBT TFTs. C(10)-BTBT was deposited on the alkyl chain-grafted polyimide gate insulator by spin-coating, forming a well-ordered crystal structure. The field-effect mobility and the on/off current ratio of the TFT device were measured to be 0.20-0.56 cm(2) V(-1) s(-1) and >10(5), respectively.

Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

NASA Astrophysics Data System (ADS)

Panda, D. K.; Lenka, T. R.

2017-06-01

An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted I d-V ds, I d-V gs, and C-V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays.

PubMed

Sánchez-Azqueta, Carlos; Goll, Bernhard; Celma, Santiago; Zimmermann, Horst

2016-05-25

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of -26.0 dBm and -25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10(-9) ) with an energy efficiency of 2 pJ/bit.

Demonstration of large field effect in topological insulator films via a high-κ back gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, C. Y.; Lin, H. Y.; Yang, S. R.

2016-05-16

The spintronics applications long anticipated for topological insulators (TIs) has been hampered due to the presence of high density intrinsic defects in the bulk states. In this work we demonstrate the back-gating effect on TIs by integrating Bi{sub 2}Se{sub 3} films 6–10 quintuple layer (QL) thick with amorphous high-κ oxides of Al{sub 2}O{sub 3} and Y{sub 2}O{sub 3}. Large gating effect of tuning the Fermi level E{sub F} to very close to the band gap was observed, with an applied bias of an order of magnitude smaller than those of the SiO{sub 2} back gate, and the modulation of filmmore » resistance can reach as high as 1200%. The dependence of the gating effect on the TI film thickness was investigated, and ΔN{sub 2D}/ΔV{sub g} varies with TI film thickness as ∼t{sup −0.75}. To enhance the gating effect, a Y{sub 2}O{sub 3} layer thickness 4 nm was inserted into Al{sub 2}O{sub 3} gate stack to increase the total κ value to 13.2. A 1.4 times stronger gating effect is observed, and the increment of induced carrier numbers is in good agreement with additional charges accumulated in the higher κ oxides. Moreover, we have reduced the intrinsic carrier concentration in the TI film by doping Te to Bi{sub 2}Se{sub 3} to form Bi{sub 2}Te{sub x}Se{sub 1−x}. The observation of a mixed state of ambipolar field that both electrons and holes are present indicates that we have tuned the E{sub F} very close to the Dirac Point. These results have demonstrated that our capability of gating TIs with high-κ back gate to pave the way to spin devices of tunable E{sub F} for dissipationless spintronics based on well-established semiconductor technology.« less

Ferroelectric FET for nonvolatile memory application with two-dimensional MoSe2 channels

NASA Astrophysics Data System (ADS)

Wang, Xudong; Liu, Chunsen; Chen, Yan; Wu, Guangjian; Yan, Xiao; Huang, Hai; Wang, Peng; Tian, Bobo; Hong, Zhenchen; Wang, Yutao; Sun, Shuo; Shen, Hong; Lin, Tie; Hu, Weida; Tang, Minghua; Zhou, Peng; Wang, Jianlu; Sun, Jinglan; Meng, Xiangjian; Chu, Junhao; Li, Zheng

2017-06-01

Graphene and other two-dimensional materials have received considerable attention regarding their potential applications in nano-electronics. Here, we report top-gate nonvolatile memory field-effect transistors (FETs) with different layers of MoSe2 nanosheets channel gated by ferroelectric film. The conventional gate dielectric of FETs was replaced by a ferroelectric thin film that provides a ferroelectric polarization electric field, and therefore defined as an Fe-FET where the poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) was used as the gate dielectric. Among the devices with MoSe2 channels of different thicknesses, the device with a single layer of MoSe2 exhibited a large hysteresis of electronic transport with an over 105 write/erase ratio, and displayed excellent retention and endurance performance. The possible mechanism of the device’s good properties was qualitatively analyzed using band theory. Additionally, a comprehensive study comparing the memory properties of MoSe2 channels of different thicknesses is presented. Increasing the numbers of MoSe2 layers was found to cause a reduced memory window. However, MoSe2 thickness of 5 nm yielded a write/erase ratio of more than 103. The results indicate that, based on a Fe-FET structure, the combination of two-dimensional semiconductors and organic ferroelectric gate dielectrics shows good promise for future applications in nonvolatile ferroelectric memory.

Mechanism of oxide thickness and temperature dependent current conduction in n+-polySi/SiO2/p-Si structures — a new analysis

NASA Astrophysics Data System (ADS)

Samanta, Piyas

2017-10-01

The conduction mechanism of gate leakage current through thermally grown silicon dioxide (SiO2) films on (100) p-type silicon has been investigated in detail under negative bias on the degenerately doped n-type polysilicon (n+-polySi) gate. The analysis utilizes the measured gate current density J G at high oxide fields E ox in 5.4 to 12 nm thick SiO2 films between 25 and 300 °C. The leakage current measured up to 300 °C was due to Fowler-Nordheim (FN) tunneling of electrons from the accumulated n +-polySi gate in conjunction with Poole Frenkel (PF) emission of trapped-electrons from the electron traps located at energy levels ranging from 0.6 to 1.12 eV (depending on the oxide thickness) below the SiO2 conduction band (CB). It was observed that PF emission current I PF dominates FN electron tunneling current I FN at oxide electric fields E ox between 6 and 10 MV/cm and throughout the temperature range studied here. Understanding of the mechanism of leakage current conduction through SiO2 films plays a crucial role in simulation of time-dependent dielectric breakdown (TDDB) of metaloxide-semiconductor (MOS) devices and to precisely predict the normal operating field or applied gate voltage for lifetime projection of the MOS integrated circuits.

A unified physical model of Seebeck coefficient in amorphous oxide semiconductor thin-film transistors

NASA Astrophysics Data System (ADS)

Lu, Nianduan; Li, Ling; Sun, Pengxiao; Banerjee, Writam; Liu, Ming

2014-09-01

A unified physical model for Seebeck coefficient was presented based on the multiple-trapping and release theory for amorphous oxide semiconductor thin-film transistors. According to the proposed model, the Seebeck coefficient is attributed to the Fermi-Dirac statistics combined with the energy dependent trap density of states and the gate-voltage dependence of the quasi-Fermi level. The simulation results show that the gate voltage, energy disorder, and temperature dependent Seebeck coefficient can be well described. The calculation also shows a good agreement with the experimental data in amorphous In-Ga-Zn-O thin-film transistor.

Quantum Computing Architectural Design

NASA Astrophysics Data System (ADS)

West, Jacob; Simms, Geoffrey; Gyure, Mark

2006-03-01

Large scale quantum computers will invariably require scalable architectures in addition to high fidelity gate operations. Quantum computing architectural design (QCAD) addresses the problems of actually implementing fault-tolerant algorithms given physical and architectural constraints beyond those of basic gate-level fidelity. Here we introduce a unified framework for QCAD that enables the scientist to study the impact of varying error correction schemes, architectural parameters including layout and scheduling, and physical operations native to a given architecture. Our software package, aptly named QCAD, provides compilation, manipulation/transformation, multi-paradigm simulation, and visualization tools. We demonstrate various features of the QCAD software package through several examples.

Facile fabrication of highly controllable gating systems based on the combination of inverse opal structure and dynamic covalent chemistry.

PubMed

Wang, Chen; Yang, Haowei; Tian, Li; Wang, Shiqiang; Gao, Ning; Zhang, Wanlin; Wang, Peng; Yin, Xianpeng; Li, Guangtao

2017-06-01

A three-dimensional (3D) inverse opal with periodic and porous structures has shown great potential for applications not only in optics and optoelectronics, but also in functional membranes. In this work, the benzaldehyde group was initially introduced into a 3D nanoporous inverse opal, serving as a platform for fabricating functional membranes. By employing the dynamic covalent approach, a highly controllable gating system was facilely fabricated to achieve modulable and reversible transport features. It was found that the physical/chemical properties and pore size of the gating system could easily be regulated through post-modification with amines. As a demonstration, the gated nanopores were modified with three kinds of amines to control the wettability, surface charge and nanopore size which in turn was exploited to achieve selective mass transport, including hydrophobic molecules, cations and anions, and the transport with respect to the physical steric hindrance. In particular, the gating system showed extraordinary reversibility and could recover to its pristine state by simply changing pH values. Due to the unlimited variety provided by the Schiff base reaction, the inverse opal described here exhibits a significant extendibility and could be easily post-modified with stimuli-responsive molecules for special purposes. Furthermore, this work can be extended to employ other dynamic covalent routes, for example Diels-Alder, ester exchange and disulfide exchange-based routes.

Combining Topological Hardware and Topological Software: Color-Code Quantum Computing with Topological Superconductor Networks

NASA Astrophysics Data System (ADS)

Litinski, Daniel; Kesselring, Markus S.; Eisert, Jens; von Oppen, Felix

2017-07-01

We present a scalable architecture for fault-tolerant topological quantum computation using networks of voltage-controlled Majorana Cooper pair boxes and topological color codes for error correction. Color codes have a set of transversal gates which coincides with the set of topologically protected gates in Majorana-based systems, namely, the Clifford gates. In this way, we establish color codes as providing a natural setting in which advantages offered by topological hardware can be combined with those arising from topological error-correcting software for full-fledged fault-tolerant quantum computing. We provide a complete description of our architecture, including the underlying physical ingredients. We start by showing that in topological superconductor networks, hexagonal cells can be employed to serve as physical qubits for universal quantum computation, and we present protocols for realizing topologically protected Clifford gates. These hexagonal-cell qubits allow for a direct implementation of open-boundary color codes with ancilla-free syndrome read-out and logical T gates via magic-state distillation. For concreteness, we describe how the necessary operations can be implemented using networks of Majorana Cooper pair boxes, and we give a feasibility estimate for error correction in this architecture. Our approach is motivated by nanowire-based networks of topological superconductors, but it could also be realized in alternative settings such as quantum-Hall-superconductor hybrids.

Dosimetry applications in GATE Monte Carlo toolkit.

PubMed

Papadimitroulas, Panagiotis

2017-09-01

Monte Carlo (MC) simulations are a well-established method for studying physical processes in medical physics. The purpose of this review is to present GATE dosimetry applications on diagnostic and therapeutic simulated protocols. There is a significant need for accurate quantification of the absorbed dose in several specific applications such as preclinical and pediatric studies. GATE is an open-source MC toolkit for simulating imaging, radiotherapy (RT) and dosimetry applications in a user-friendly environment, which is well validated and widely accepted by the scientific community. In RT applications, during treatment planning, it is essential to accurately assess the deposited energy and the absorbed dose per tissue/organ of interest, as well as the local statistical uncertainty. Several types of realistic dosimetric applications are described including: molecular imaging, radio-immunotherapy, radiotherapy and brachytherapy. GATE has been efficiently used in several applications, such as Dose Point Kernels, S-values, Brachytherapy parameters, and has been compared against various MC codes which are considered as standard tools for decades. Furthermore, the presented studies show reliable modeling of particle beams when comparing experimental with simulated data. Examples of different dosimetric protocols are reported for individualized dosimetry and simulations combining imaging and therapy dose monitoring, with the use of modern computational phantoms. Personalization of medical protocols can be achieved by combining GATE MC simulations with anthropomorphic computational models and clinical anatomical data. This is a review study, covering several dosimetric applications of GATE, and the different tools used for modeling realistic clinical acquisitions with accurate dose assessment. Copyright © 2017 Associazione Italiana di Fisica Medica. Published by Elsevier Ltd. All rights reserved.

Free energy dissipation of the spontaneous gating of a single voltage-gated potassium channel.

PubMed

Wang, Jia-Zeng; Wang, Rui-Zhen

2018-02-01

Potassium channels mainly contribute to the resting potential and re-polarizations, with the potassium electrochemical gradient being maintained by the pump Na + /K + -ATPase. In this paper, we construct a stochastic model mimicking the kinetics of a potassium channel, which integrates temporal evolving of the membrane voltage and the spontaneous gating of the channel. Its stationary probability density functions (PDFs) are found to be singular at the boundaries, which result from the fact that the evolving rates of voltage are greater than the gating rates of the channel. We apply PDFs to calculate the power dissipations of the potassium current, the leakage, and the gating currents. On a physical perspective, the essential role of the system is the K + -battery charging the leakage (L-)battery. A part of power will inevitably be dissipated among the process. So, the efficiency of energy transference is calculated.

Free energy dissipation of the spontaneous gating of a single voltage-gated potassium channel

NASA Astrophysics Data System (ADS)

Wang, Jia-Zeng; Wang, Rui-Zhen

2018-02-01

Potassium channels mainly contribute to the resting potential and re-polarizations, with the potassium electrochemical gradient being maintained by the pump Na+/K+-ATPase. In this paper, we construct a stochastic model mimicking the kinetics of a potassium channel, which integrates temporal evolving of the membrane voltage and the spontaneous gating of the channel. Its stationary probability density functions (PDFs) are found to be singular at the boundaries, which result from the fact that the evolving rates of voltage are greater than the gating rates of the channel. We apply PDFs to calculate the power dissipations of the potassium current, the leakage, and the gating currents. On a physical perspective, the essential role of the system is the K+-battery charging the leakage (L-)battery. A part of power will inevitably be dissipated among the process. So, the efficiency of energy transference is calculated.

Development of a 1000V, 200A, low-loss, fast-switching, gate-assisted turn-off thyristor

NASA Technical Reports Server (NTRS)

Schlegel, E. S.; Lowry, L. R.

1975-01-01

Feasibility was demonstrated for a thyristor that blocks 1000V forward and reverse, conducts 200A, and turns on in little more than 2 microsec with only 2A of gate drive. Its features include a turn-off time of 3 microsec achieved with 2A of gate assist current of a few microseconds duration and an energy dissipation of only 12 mJ per pulse for a 20 microsec half sine wave, 200A pulse. Extensive theoretical and experimental study of the electrical behavior of thyristors having a fast turn-off time have significantly improved the understanding of the physics of turning thyristor off. Thyristors of two new designs were fabricated and evaluated. The high speed and low power were achieved by a combination of gate amplification, cathode shunting, and gate-assisted turn-off. Two techniques for making this combination practical are described.

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications

NASA Astrophysics Data System (ADS)

Liu, Chunsen; Yan, Xiao; Song, Xiongfei; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-05-01

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moghadam, Reza M.; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to low-power field-effect devices that can be used for logic or memory. Essential to realizing such field-effect devices is the development of ferroelectric metal-oxide-semiconductor (MOS) capacitors, in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel. Here we demonstrate that ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x= 0.7) that has been epitaxially grown on Ge. We find that themore » ferroelectric properties of SrZrxTi1-xO3 are exceptionally robust, as gate layers as thin as 5 nm give rise to hysteretic capacitance-voltage characteristics that are 2 V in width. The development of ferroelectric MOS capacitors with gate thicknesses that are technologically relevant opens a pathway to realize scalable ferroelectric field-effect devices.« less

The Performance Improvement of N2 Plasma Treatment on ZrO2 Gate Dielectric Thin-Film Transistors with Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition IGZO Channel.

PubMed

Wu, Chien-Hung; Huang, Bo-Wen; Chang, Kow-Ming; Wang, Shui-Jinn; Lin, Jian-Hong; Hsu, Jui-Mei

2016-06-01

The aim of this paper is to illustrate the N2 plasma treatment for high-κ ZrO2 gate dielectric stack (30 nm) with indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs). Experimental results reveal that a suitable incorporation of nitrogen atoms could enhance the device performance by eliminating the oxygen vacancies and provide an amorphous surface with better surface roughness. With N2 plasma treated ZrO2 gate, IGZO channel is fabricated by atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique. The best performance of the AP-PECVD IGZO TFTs are obtained with 20 W-90 sec N2 plasma treatment with field-effect mobility (μ(FET)) of 22.5 cm2/V-s, subthreshold swing (SS) of 155 mV/dec, and on/off current ratio (I(on)/I(off)) of 1.49 x 10(7).

Improved interfacial and electrical properties of GaAs metal-oxide-semiconductor capacitors with HfTiON as gate dielectric and TaON as passivation interlayer

NASA Astrophysics Data System (ADS)

Wang, L. S.; Xu, J. P.; Zhu, S. Y.; Huang, Y.; Lai, P. T.

2013-08-01

The interfacial and electrical properties of sputtered HfTiON on sulfur-passivated GaAs with or without TaON as interfacial passivation layer (IPL) are investigated. Experimental results show that the GaAs metal-oxide-semiconductor capacitor with HfTiON/TaON stacked gate dielectric annealed at 600 °C exhibits low interface-state density (1.0 × 1012 cm-2 eV-1), small gate leakage current (7.3 × 10-5 A cm-2 at Vg = Vfb + 1 V), small capacitance equivalent thickness (1.65 nm), and large equivalent dielectric constant (26.2). The involved mechanisms lie in the fact that the TaON IPL can effectively block the diffusions of Hf, Ti, and O towards GaAs surface and suppress the formation of interfacial As-As bonds, Ga-/As-oxides, thus unpinning the Femi level at the TaON/GaAs interface and improving the interface quality and electrical properties of the device.

Nano-textured high sensitivity ion sensitive field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hajmirzaheydarali, M.; Sadeghipari, M.; Akbari, M.

2016-02-07

Nano-textured gate engineered ion sensitive field effect transistors (ISFETs), suitable for high sensitivity pH sensors, have been realized. Utilizing a mask-less deep reactive ion etching results in ultra-fine poly-Si features on the gate of ISFET devices where spacing of the order of 10 nm and less is achieved. Incorporation of these nano-sized features on the gate is responsible for high sensitivities up to 400 mV/pH in contrast to conventional planar structures. The fabrication process for this transistor is inexpensive, and it is fully compatible with standard complementary metal oxide semiconductor fabrication procedure. A theoretical modeling has also been presented to predict themore » extension of the diffuse layer into the electrolyte solution for highly featured structures and to correlate this extension with the high sensitivity of the device. The observed ultra-fine features by means of scanning electron microscopy and transmission electron microscopy tools corroborate the theoretical prediction.« less

CMOS image sensor with lateral electric field modulation pixels for fluorescence lifetime imaging with sub-nanosecond time response

NASA Astrophysics Data System (ADS)

Li, Zhuo; Seo, Min-Woong; Kagawa, Keiichiro; Yasutomi, Keita; Kawahito, Shoji

2016-04-01

This paper presents the design and implementation of a time-resolved CMOS image sensor with a high-speed lateral electric field modulation (LEFM) gating structure for time domain fluorescence lifetime measurement. Time-windowed signal charge can be transferred from a pinned photodiode (PPD) to a pinned storage diode (PSD) by turning on a pair of transfer gates, which are situated beside the channel. Unwanted signal charge can be drained from the PPD to the drain by turning on another pair of gates. The pixel array contains 512 (V) × 310 (H) pixels with 5.6 × 5.6 µm2 pixel size. The imager chip was fabricated using 0.11 µm CMOS image sensor process technology. The prototype sensor has a time response of 150 ps at 374 nm. The fill factor of the pixels is 5.6%. The usefulness of the prototype sensor is demonstrated for fluorescence lifetime imaging through simulation and measurement results.

Design and Performance Analysis of Depletion-Mode InSb Quantum-Well Field-Effect Transistor for Logic Applications

NASA Astrophysics Data System (ADS)

Islam, R.; Uddin, M. M.; Hossain, M. Mofazzal; Matin, M. A.

The design of a 1μm gate length depletion-mode InSb quantum-well field-effect transistor (QWFET) with a 10nm-thick Al2O3 gate dielectric has been optimized using a quantum corrected self-consistent Schrödinger-Poisson (QCSP) and two-dimensional drift-diffusion model. The model predicts a very high electron mobility of 4.42m2V-1s-1 at Vg=0V, a small pinch off gate voltage (Vp) of -0.25V, a maximum extrinsic transconductance (gm) of ˜4.85mS/μm and a drain current density of more than 3.34mA/μm. A short-circuit current-gain cut-off frequency (fT) of 374GHz and a maximum oscillation frequency (fmax) of 645GHz are predicted for the device. These characteristics make the device a potential candidate for low power, high-speed logic electronic device applications.

Energetic and spatial parameters for gating of the bacterial large conductance mechanosensitive channel, MscL

NASA Technical Reports Server (NTRS)

Sukharev, S. I.; Sigurdson, W. J.; Kung, C.; Sachs, F.

1999-01-01

MscL is multimeric protein that forms a large conductance mechanosensitive channel in the inner membrane of Escherichia coli. Since MscL is gated by tension transmitted through the lipid bilayer, we have been able to measure its gating parameters as a function of absolute tension. Using purified MscL reconstituted in liposomes, we recorded single channel currents and varied the pressure gradient (P) to vary the tension (T). The tension was calculated from P and the radius of curvature was obtained using video microscopy of the patch. The probability of being open (Po) has a steep sigmoidal dependence on T, with a midpoint (T1/2) of 11.8 dyn/cm. The maximal slope sensitivity of Po/Pc was 0.63 dyn/cm per e-fold. Assuming a Boltzmann distribution, the energy difference between the closed and fully open states in the unstressed membrane was DeltaE = 18.6 kBT. If the mechanosensitivity arises from tension acting on a change of in-plane area (DeltaA), the free energy, TDeltaA, would correspond to DeltaA = 6.5 nm2. MscL is not a binary channel, but has four conducting states and a closed state. Most transition rates are independent of tension, but the rate-limiting step to opening is the transition between the closed state and the lowest conductance substate. This transition thus involves the greatest DeltaA. When summed over all transitions, the in-plane area change from closed to fully open was 6 nm2, agreeing with the value obtained in the two-state analysis. Assuming a cylindrical channel, the dimensions of the (fully open) pore were comparable to DeltaA. Thus, the tension dependence of channel gating is primarily one of increasing the external channel area to accommodate the pore of the smallest conducting state. The higher conducting states appear to involve conformational changes internal to the channel that don't involve changes in area.

Dysregulated Zn2+ homeostasis impairs cardiac type-2 ryanodine receptor and mitsugumin 23 functions, leading to sarcoplasmic reticulum Ca2+ leakage.

PubMed

Reilly-O'Donnell, Benedict; Robertson, Gavin B; Karumbi, Angela; McIntyre, Connor; Bal, Wojciech; Nishi, Miyuki; Takeshima, Hiroshi; Stewart, Alan J; Pitt, Samantha J

2017-08-11

Aberrant Zn 2+ homeostasis is associated with dysregulated intracellular Ca 2+ release, resulting in chronic heart failure. In the failing heart a small population of cardiac ryanodine receptors (RyR2) displays sub-conductance-state gating leading to Ca 2+ leakage from sarcoplasmic reticulum (SR) stores, which impairs cardiac contractility. Previous evidence suggests contribution of RyR2-independent Ca 2+ leakage through an uncharacterized mechanism. We sought to examine the role of Zn 2+ in shaping intracellular Ca 2+ release in cardiac muscle. Cardiac SR vesicles prepared from sheep or mouse ventricular tissue were incorporated into phospholipid bilayers under voltage-clamp conditions, and the direct action of Zn 2+ on RyR2 channel function was examined. Under diastolic conditions, the addition of pathophysiological concentrations of Zn 2+ (≥2 nm) caused dysregulated RyR2-channel openings. Our data also revealed that RyR2 channels are not the only SR Ca 2+ -permeable channels regulated by Zn 2+ Elevating the cytosolic Zn 2+ concentration to 1 nm increased the activity of the transmembrane protein mitsugumin 23 (MG23). The current amplitude of the MG23 full-open state was consistent with that previously reported for RyR2 sub-conductance gating, suggesting that in heart failure in which Zn 2+ levels are elevated, RyR2 channels do not gate in a sub-conductance state, but rather MG23-gating becomes more apparent. We also show that in H9C2 cells exposed to ischemic conditions, intracellular Zn 2+ levels are elevated, coinciding with increased MG23 expression. In conclusion, these data suggest that dysregulated Zn 2+ homeostasis alters the function of both RyR2 and MG23 and that both ion channels play a key role in diastolic SR Ca 2+ leakage. © 2017 by The American Society for Biochemistry and Molecular Biology, Inc.

A new imaging method for understanding chemical dynamics: efficient slice imaging using an in-vacuum pixel detector.

PubMed

Jungmann, J H; Gijsbertsen, A; Visser, J; Visschers, J; Heeren, R M A; Vrakking, M J J

2010-10-01

The implementation of the Timepix complementary metal oxide semiconductor pixel detector in velocity map slice imaging is presented. This new detector approach eliminates the need for gating the imaging detector. In time-of-flight mode, the detector returns the impact position and the time-of-flight of charged particles with 12.5 ns resolution and a dynamic range of about 100 μs. The implementation of the Timepix detector in combination with a microchannel plate additionally allows for high spatial resolution information via center-of-mass centroiding. Here, the detector was applied to study the photodissociation of NO(2) at 452 nm. The energy resolution observed in the experiment was ΔE/E=0.05 and is limited by the experimental setup rather than by the detector assembly. All together, this new compact detector assembly is well-suited for slice imaging and is a promising tool for imaging studies in atomic and molecular physics research.

Investigation of thermal effects on FinFETs in the quasi-ballistic regime

NASA Astrophysics Data System (ADS)

Yin, Longxiang; Shen, Lei; Di, Shaoyan; Du, Gang; Liu, Xiaoyan

2018-04-01

In this work, the thermal effects of FinFETs in the quasi-ballistic regime are investigated using the Monte Carlo method. Bulk Si nFinFETs with the same fin structure and two different gate lengths L g = 20 and 80 nm are investigated and compared to evaluate the thermal effects on the performance of FinFETs in the quasi-ballistic regime. The on current of the 20 nm FinFET with V gs = 0.7 V does not decrease with increasing lattice temperature (T L) at a high V ds. The electrostatic properties in the 20 nm FinFET are more affected by T L than those in the 80 nm FinFET. However, the electron transport in the 20 nm FinFET is less affected by T L than that in the 80 nm FinFET. The electrostatic properties being more sensitive and the electron transport being less sensitive to thermal effects in the quasi-ballistic regime than in the diffusive regime should be considered for effective device modeling and design.

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities

PubMed Central

Jung, Han Sae; Tsai, Hsin-Zon; Wong, Dillon; Germany, Chad; Kahn, Salman; Kim, Youngkyou; Aikawa, Andrew S.; Desai, Dhruv K.; Rodgers, Griffin F.; Bradley, Aaron J.; Velasco, Jairo; Watanabe, Kenji; Taniguchi, Takashi; Wang, Feng; Zettl, Alex; Crommie, Michael F.

2015-01-01

Owing to its relativistic low-energy charge carriers, the interaction between graphene and various impurities leads to a wealth of new physics and degrees of freedom to control electronic devices. In particular, the behavior of graphene’s charge carriers in response to potentials from charged Coulomb impurities is predicted to differ significantly from that of most materials. Scanning tunneling microscopy (STM) and scanning tunneling spectroscopy (STS) can provide detailed information on both the spatial and energy dependence of graphene's electronic structure in the presence of a charged impurity. The design of a hybrid impurity-graphene device, fabricated using controlled deposition of impurities onto a back-gated graphene surface, has enabled several novel methods for controllably tuning graphene’s electronic properties.1-8 Electrostatic gating enables control of the charge carrier density in graphene and the ability to reversibly tune the charge2 and/or molecular5 states of an impurity. This paper outlines the process of fabricating a gate-tunable graphene device decorated with individual Coulomb impurities for combined STM/STS studies.2-5 These studies provide valuable insights into the underlying physics, as well as signposts for designing hybrid graphene devices. PMID:26273961

Rejection of fluorescence background in resonance and spontaneous Raman microspectroscopy.

PubMed

Smith, Zachary J; Knorr, Florian; Pagba, Cynthia V; Wachsmann-Hogiu, Sebastian

2011-05-18

Raman spectroscopy is often plagued by a strong fluorescent background, particularly for biological samples. If a sample is excited with a train of ultrafast pulses, a system that can temporally separate spectrally overlapping signals on a picosecond timescale can isolate promptly arriving Raman scattered light from late-arriving fluorescence light. Here we discuss the construction and operation of a complex nonlinear optical system that uses all-optical switching in the form of a low-power optical Kerr gate to isolate Raman and fluorescence signals. A single 808 nm laser with 2.4 W of average power and 80 MHz repetition rate is split, with approximately 200 mW of 808 nm light being converted to < 5 mW of 404 nm light sent to the sample to excite Raman scattering. The remaining unconverted 808 nm light is then sent to a nonlinear medium where it acts as the pump for the all-optical shutter. The shutter opens and closes in 800 fs with a peak efficiency of approximately 5%. Using this system we are able to successfully separate Raman and fluorescence signals at an 80 MHz repetition rate using pulse energies and average powers that remain biologically safe. Because the system has no spare capacity in terms of optical power, we detail several design and alignment considerations that aid in maximizing the throughput of the system. We also discuss our protocol for obtaining the spatial and temporal overlap of the signal and pump beams within the Kerr medium, as well as a detailed protocol for spectral acquisition. Finally, we report a few representative results of Raman spectra obtained in the presence of strong fluorescence using our time-gating system.

Determination of Cd, Cr and Pb in phosphate fertilizers by laser-induced breakdown spectroscopy

NASA Astrophysics Data System (ADS)

Nunes, Lidiane Cristina; de Carvalho, Gabriel Gustinelli Arantes; Santos, Dario; Krug, Francisco José

2014-07-01

A validated method for quantitative determination of Cd, Cr, and Pb in phosphate fertilizers by laser-induced breakdown spectroscopy (LIBS) is presented. Laboratory samples were comminuted and homogenized by cryogenic or planetary ball milling, pressed into pellets and analyzed by LIBS. The experimental setup was designed by using a Q-switched Nd:YAG at 1064 nm with 10 Hz repetition rate, and the intensity signals from Cd II 214.441 nm, Cr II 267.716 nm and Pb II 220.353 nm emission lines were measured by using a spectrometer furnished with an intensified charge-coupled device. LIBS parameters (laser fluence, lens-to-sample distance, delay time, integration time gate, number of sites and number of laser pulses per site) were chosen after univariate experiments with a pellet of NIST SRM 695 (Trace Elements in Multi-Nutrient Fertilizer). Calibration and validation were carried out with 30 fertilizer samples from single superphosphate, triple superphosphate, monoammonium phosphate, and NPK mixtures. Good results were obtained by using 30 pulses of 50 J cm- 2 (750 μm spot size), 2.0 μs delay time and 5.0 μs integration time gate. No significant differences between Cd, Cr, and Pb mass fractions determined by the proposed LIBS method and by ICP OES after microwave-assisted acid digestion (AOAC 2006.03 Official Method) were found at 95% confidence level. The limits of detection of 1 mg kg- 1 Cd, 2 mg kg- 1 Cr and 15 mg kg- 1 Pb and the precision (coefficients of variation of results ranging from 2% to 15%) indicate that the proposed LIBS method can be recommended for the determination of these analytes in phosphate fertilizers.

Silicon on insulator self-aligned transistors

DOEpatents

McCarthy, Anthony M.

2003-11-18

A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

The randomized benchmarking number is not what you think it is

NASA Astrophysics Data System (ADS)

Proctor, Timothy; Rudinger, Kenneth; Blume-Kohout, Robin; Sarovar, Mohan; Young, Kevin

Randomized benchmarking (RB) is a widely used technique for characterizing a gate set, whereby random sequences of gates are used to probe the average behavior of the gate set. The gates are chosen to ideally compose to the identity, and the rate of decay in the survival probability of an initial state with increasing length sequences is extracted from a set of experiments - this is the `RB number'. For reasonably well-behaved noise and particular gate sets, it has been claimed that the RB number is a reliable estimate of the average gate fidelity (AGF) of each noisy gate to the ideal target unitary, averaged over all gates in the set. Contrary to this widely held view, we show that this is not the case. We show that there are physically relevant situations, in which RB was thought to be provably reliable, where the RB number is many orders of magnitude away from the AGF. These results have important implications for interpreting the RB protocol, and immediate consequences for many advanced RB techniques. Sandia National Laboratories is a multi-mission laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.

The physics of bacterial decision making.

PubMed

Ben-Jacob, Eshel; Lu, Mingyang; Schultz, Daniel; Onuchic, Jose' N

2014-01-01

The choice that bacteria make between sporulation and competence when subjected to stress provides a prototypical example of collective cell fate determination that is stochastic on the individual cell level, yet predictable (deterministic) on the population level. This collective decision is performed by an elaborated gene network. Considerable effort has been devoted to simplify its complexity by taking physics approaches to untangle the basic functional modules that are integrated to form the complete network: (1) A stochastic switch whose transition probability is controlled by two order parameters-population density and internal/external stress. (2) An adaptable timer whose clock rate is normalized by the same two previous order parameters. (3) Sensing units which measure population density and external stress. (4) A communication module that exchanges information about the cells' internal stress levels. (5) An oscillating gate of the stochastic switch which is regulated by the timer. The unique circuit architecture of the gate allows special dynamics and noise management features. The gate opens a window of opportunity in time for competence transitions, during which the circuit generates oscillations that are translated into a chain of short intervals with high transition probability. In addition, the unique architecture of the gate allows filtering of external noise and robustness against variations in circuit parameters and internal noise. We illustrate that a physics approach can be very valuable in investigating the decision process and in identifying its general principles. We also show that both cell-cell variability and noise have important functional roles in the collectively controlled individual decisions.

The physics of bacterial decision making

PubMed Central

Ben-Jacob, Eshel; Lu, Mingyang; Schultz, Daniel; Onuchic, Jose' N.

2014-01-01

The choice that bacteria make between sporulation and competence when subjected to stress provides a prototypical example of collective cell fate determination that is stochastic on the individual cell level, yet predictable (deterministic) on the population level. This collective decision is performed by an elaborated gene network. Considerable effort has been devoted to simplify its complexity by taking physics approaches to untangle the basic functional modules that are integrated to form the complete network: (1) A stochastic switch whose transition probability is controlled by two order parameters—population density and internal/external stress. (2) An adaptable timer whose clock rate is normalized by the same two previous order parameters. (3) Sensing units which measure population density and external stress. (4) A communication module that exchanges information about the cells' internal stress levels. (5) An oscillating gate of the stochastic switch which is regulated by the timer. The unique circuit architecture of the gate allows special dynamics and noise management features. The gate opens a window of opportunity in time for competence transitions, during which the circuit generates oscillations that are translated into a chain of short intervals with high transition probability. In addition, the unique architecture of the gate allows filtering of external noise and robustness against variations in circuit parameters and internal noise. We illustrate that a physics approach can be very valuable in investigating the decision process and in identifying its general principles. We also show that both cell-cell variability and noise have important functional roles in the collectively controlled individual decisions. PMID:25401094

Field-Effect Transistor-Integration with TiO2 Nanoparticles for Sensing of Cardiac Troponin I Biomarker.

PubMed

Arshad, M K Md; Adzhri, R; Fathil, M F M; Gopinath, Subash C B; N M, Nuzaihan M

2018-08-01

The development of electrical biosensor towards device miniaturization in order to achieve better sensitivity with enhanced electrical signal has certain limitations especially complexity in fabrication process and costs. In this paper, an alternative technique with minor modification in the device structure is presented for signal amplification by implementing ambipolar conduction in the biosensor itself. We demonstrated the field-effect transistor (FET)-based biosensor coupled back-gate for attaining a higher sensitivity with the detection of lower target abundance. To utilize the coupled back-gate as a pre-amplifier, silicon-on-insulator wafer with thicknesses of top-silicon and buried oxide (BOX) layers of 70 nm and 145 nm, respectively were desired. Titanium dioxide (TiO2) nanomaterial was deposited using sol-gel method on the channel which acts as a transducer. Surface functionalization on TiO2 thin film allowed an effective immobilization of anti-cardiac troponin I antibody to interact cardiac troponin I (cTnI). Binding events at each step was validated by X-ray photoelectron spectroscopy (XPS) analysis. Further, electrical characterization (Id-Vd) confirms the potentiality of FET-based biosensor to detect cTnI (represents acute myocardial infarction disease) with the concentration ranges from 10 μg/ml down to 1 fg/ml. The sensitivity of 459.2 nA (g/ml)-1 and lower detection limit of 1 fg/ml were achieved at Vbg = -5 V and Vd = 5 V. The designed device demonstrates its ability to detect lower level of cTnI with pre-amplified electrical signal by back-gate biasing.

Resistance modulation in VO2 nanowires induced by an electric field via air-gap gates

NASA Astrophysics Data System (ADS)

Kanki, Teruo; Chikanari, Masashi; Wei, Tingting; Tanaka, Hidekazu; The Institute of Scientific; Industrial Research Team

Vanadium dioxide (VO2) shows huge resistance change with metal-insulator transition (MIT) at around room temperature. Controlling of the MIT by applying an electric field is a topical ongoing research toward the realization of Mott transistor. In this study, we have successfully switched channel resistance of VO2 nano-wire channels by a pure electrostatic field effect using a side-gate-type field-effect transistor (SG-FET) viaair gap and found that single crystalline VO2 nanowires and the channels with narrower width enhance transport modulation rate. The rate of change in resistance ((R0-R)/R, where R0 and R is the resistance of VO2 channel with off state and on state gate voltage (VG) , respectively) was 0.42 % at VG = 30 V in in-plane poly-crystalline VO2 channels on Al2O3(0001) substrates, while the rate in single crystalline channels on TiO2 (001) substrates was 3.84 %, which was 9 times higher than that using the poly-crystalline channels. With reducing wire width from 3000 nm to 400 nm of VO2 on TiO2 (001) substrate, furthermore, resistance modulation ratio enhanced from 0.67 % to 3.84 %. This change can not be explained by a simple free-electron model. In this presentation, we will compare the electronic properties between in-plane polycrystalline VO2 on Al2O3 (0001) and single crystalline VO2 on TiO2 (001) substrates, and show experimental data in detail..

155- and 213-GHz AlInAs/GaInAs/InP HEMT MMIC oscillators

NASA Technical Reports Server (NTRS)

Rosenbaum, Steven E.; Kormanyos, Brian K.; Jelloian, Linda M.; Matloubian, Mehran; Brown, April S.; Larson, Lawrence E.; Nguyen, Loi D.; Thompson, Mark A.; Katehi, Linda P. B.; Rebeiz, Gabriel M.

1995-01-01

We report on the design and measurement of monolithic 155- and 213-GHz quasi-optical oscillators using AlInAs/GaInAs/InP HEMTs (high-electron mobility transistors). These results are believed to be the highest frequency three-terminal oscillators reported to date. The indium concentration in the channel was 80% for high sheet charge and mobility. The HEMT gates were fabricated with self-aligned sub-tenth-micrometer electron-beam techniques to achieve gate lengths on the order of 50 nm and drain-source spacing of 0.25 micron. Planar antennas were integrated into the fabrication process resulting in a compact and efficient quasi-optical Monolithic Millimeter-wave Integrated Circuit (MMIC) oscillator.

Error-Transparent Quantum Gates for Small Logical Qubit Architectures

NASA Astrophysics Data System (ADS)

Kapit, Eliot

2018-02-01

One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016), 10.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.

Abstract probabilistic CNOT gate model based on double encoding: study of the errors and physical realizability

NASA Astrophysics Data System (ADS)

Gueddana, Amor; Attia, Moez; Chatta, Rihab

2015-03-01

In this work, we study the error sources standing behind the non-perfect linear optical quantum components composing a non-deterministic quantum CNOT gate model, which performs the CNOT function with a success probability of 4/27 and uses a double encoding technique to represent photonic qubits at the control and the target. We generalize this model to an abstract probabilistic CNOT version and determine the realizability limits depending on a realistic range of the errors. Finally, we discuss physical constraints allowing the implementation of the Asymmetric Partially Polarizing Beam Splitter (APPBS), which is at the heart of correctly realizing the CNOT function.

TDR method for determine IC's parameters

NASA Astrophysics Data System (ADS)

Timoshenkov, V.; Rodionov, D.; Khlybov, A.

2016-12-01

Frequency domain simulation is a widely used approach for determine integrated circuits parameters. This approach can be found in most of software tools used in IC industry. Time domain simulation approach shows intensive usage last years due to some advantages. In particular it applicable for analysis of nonlinear and nonstationary systems where frequency domain is inapplicable. Resolution of time domain systems allow see heterogeneities on distance 1mm, determine it parameters and properties. Authors used approach based on detecting reflected signals from heterogeneities - time domain reflectometry (TDR). Field effect transistor technology scaling up to 30-60nm gate length and 10nm gate dielectric, heterojunction bi-polar transistors with 10-30nm base width allows fabricate digital IC's with 20GHz clock frequency and RF-IC's with tens GHz bandwidth. Such devices and operation speed suppose transit signal by use microwave lines. There are local heterogeneities can be found inside of the signal path due to connections between different parts of signal lines (stripe line-RF-connector pin, stripe line - IC package pin). These heterogeneities distort signals that cause bandwidth decrease for RF-devices. Time domain research methods of transmission and reflected signals give the opportunities to determine heterogeneities, it properties, parameters and built up equivalent circuits. Experimental results are provided and show possibility for inductance and capacitance measurement up to 25GHz. Measurements contains result of signal path research on IC and printed circuit board (PCB) used for 12GHz RF chips. Also dielectric constant versus frequency was measured up to 35GHz.

Expanding the printable design space for lithography processes utilizing a cut mask

NASA Astrophysics Data System (ADS)

Wandell, Jerome; Salama, Mohamed; Wilkinson, William; Curtice, Mark; Feng, Jui-Hsuan; Gao, Shao Wen; Asthana, Abhishek

2016-03-01

The utilization of a cut-mask in semiconductor patterning processes has been in practice for logic devices since the inception of 32nm-node devices, notably with unidirectional gate level printing. However, the microprocessor applications where cut-mask patterning methods are used are expanding as Self-Aligned Double Patterning (SADP) processes become mainstream for 22/14nm fin diffusion, and sub-14nm metal levels. One common weakness for these types of lithography processes is that the initial pattern requiring the follow-up cut-mask typically uses an extreme off-axis imaging source such as dipole to enhance the resolution and line-width roughness (LWR) for critical dense patterns. This source condition suffers from poor process margin in the semi-dense (forbidden pitch) realm and wrong-way directional design spaces. Common pattern failures in these limited design regions include bridging and extra-printing defects that are difficult to resolve with traditional mask improvement means. This forces the device maker to limit the allowable geometries that a designer may use on a device layer. This paper will demonstrate methods to expand the usable design space on dipole-like processes such as unidirectional gate and SADP processes by utilizing the follow-up cut mask to improve the process window. Traditional mask enhancement means for improving the process window in this design realm will be compared to this new cut-mask approach. The unique advantages and disadvantages of the cut-mask solution will be discussed in contrast to those customary methods.

Nanoscience and Nanotechnology

DTIC Science & Technology

1992-05-05

Stanford has fabricated gate lengths down to 65 nm, and are entering into consortia to fabricate modulation doped field effect transistors (MODFETs...and from the substrate exposes the resist over a greater area than the beam xpot size. Correcting for these effects (where possible) is computationally...the lithographic pattern (proximity effects ). The push to smaller dimensions is concentrated on controlling and understanding these phenomena rather

SUB-ACUTE TREATMENT WITH METHYLMERCURY DURING DIFFERENTIATION OF PHEOCHROMOCYTOMA (PC12) CELLS DOES NOT ALTER BINDING OF ION CHANNEL LIGANDS OR CELL MORPHOLOGY.

EPA Science Inventory

We demonstrated recently that 6 days of exposure to nanomolar concentrations (3-10 nM) of methylmercury (MeHg) during nerve growth factor (NGF) induced PC12 cell differentiation reduced the amplitude and density of voltage-gated sodium and calcium currents. In the present study,...

30. MAIN CANAL Photographic copy of historic photo, January ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

30. MAIN CANAL - Photographic copy of historic photo, January 29, 1907 (original print filed in Record Group 115, National Archives, Washington, D.C.) W.J.Lubken, photographer 'CHECK GATES ON SOUTHERN CANAL, STA.118, JUST ABOVE THE ENTRANCE END OF DARK CANYON PRESSURE PIPE' - Carlsbad Irrigation District, Main Canal, 4 miles North to 12 miles Southeast of Carlsbad, Carlsbad, Eddy County, NM

Functionalized Fullerene Targeting Human Voltage-Gated Sodium Channel, hNav1.7.

PubMed

Hilder, Tamsyn A; Robinson, Anna; Chung, Shin-Ho

2017-08-16

Mutations of hNa v 1.7 that cause its activities to be enhanced contribute to severe neuropathic pain. Only a small number of hNa v 1.7 specific inhibitors have been identified, most of which interact with the voltage-sensing domain of the voltage-activated sodium ion channel. In our previous computational study, we demonstrated that a [Lys 6 ]-C 84 fullerene binds tightly (affinity of 46 nM) to Na v Ab, the voltage-gated sodium channel from the bacterium Arcobacter butzleri. Here, we extend this work and, using molecular dynamics simulations, demonstrate that the same [Lys 6 ]-C 84 fullerene binds strongly (2.7 nM) to the pore of a modeled human sodium ion channel hNa v 1.7. In contrast, the fullerene binds only weakly to a mutated model of hNa v 1.7 (I1399D) (14.5 mM) and a model of the skeletal muscle hNa v 1.4 (3.7 mM). Comparison of one representative sequence from each of the nine human sodium channel isoforms shows that only hNa v 1.7 possesses residues that are critical for binding the fullerene derivative and blocking the channel pore.

Fixed interface charges between AlGaN barrier and gate stack composed of in situ grown SiN and Al{sub 2}O{sub 3} in AlGaN/GaN high electron mobility transistors with normally off capability

DOE Office of Scientific and Technical Information (OSTI.GOV)

Capriotti, M., E-mail: mattia.capriotti@tuwien.ac.at; Alexewicz, A.; Fleury, C.

2014-03-17

Using a generalized extraction method, the fixed charge density N{sub int} at the interface between in situ deposited SiN and 5 nm thick AlGaN barrier is evaluated by measurements of threshold voltage V{sub th} of an AlGaN/GaN metal insulator semiconductor high electron mobility transistor as a function of SiN thickness. The thickness of the originally deposited 50 nm thick SiN layer is reduced by dry etching. The extracted N{sub int} is in the order of the AlGaN polarization charge density. The total removal of the in situ SiN cap leads to a complete depletion of the channel region resulting in V{sub th} = +1 V.more » Fabrication of a gate stack with Al{sub 2}O{sub 3} as a second cap layer, deposited on top of the in situ SiN, is not introducing additional fixed charges at the SiN/Al{sub 2}O{sub 3} interface.« less

Revealing the Molecular Structure and the Transport Mechanism at the Base of Primary Cilia Using Superresolution STED Microscopy

NASA Astrophysics Data System (ADS)

Yang, Tung-Lin

The primary cilium is an organelle that serves as a signaling center of the cell and is involved in the hedgehog signaling, cAMP pathway, Wnt pathways, etc. Ciliary function relies on the transportation of molecules between the primary cilium and the cell, which is facilitated by intraflagellar transport (IFT). IFT88, one of the important IFT proteins in complex B, is known to play a role in the formation and maintenance of cilia in various types of organisms. The ciliary transition zone (TZ), which is part of the gating apparatus at the ciliary base, is home to a large number of ciliopathy molecules. Recent studies have identified important regulating elements for TZ gating in cilia. However, the architecture of the TZ region and its arrangement relative to intraflagellar transport (IFT) proteins remain largely unknown, hindering the mechanistic understanding of the regulation processes. One of the major challenges comes from the tiny volume at the ciliary base packed with numerous proteins, with the diameter of the TZ close to the diffraction limit of conventional microscopes. Using a series of stimulated emission depletion (STED) superresolution images mapped to electron microscopy images, we analyzed the structural organization of the ciliary base. Subdiffraction imaging of TZ components defines novel geometric distributions of RPGRIP1L, MKS1, CEP290, TCTN2 and TMEM67, shedding light on their roles in TZ structure, assembly, and function. We found TCTN2 at the outmost periphery of the TZ close to the ciliary membrane, with a 227+/-18 nm diameter. TMEM67 was adjacent to TCTN2, with a 205+/-20 nm diameter. RPGRIP1L was localized toward the axoneme at the same axial level as TCTN2 and TMEM67, with a 165+/-8 nm diameter. MKS1 was situated between TMEM67 and RPGRIP1L, with an 186+/-21 nm diameter. Surprisingly, CEP290 was localized at the proximal side of the TZ close to the distal end of the centrin-labeled basal body. The lateral width was unexpectedly close to the width of the basal body, distant from the potential Y-links region of the TZ. Moreover, IFT88 was intriguingly distributed in two distinct patterns, forming three puncta or a Y shape at the ciliary base found in human retinal pigment epithelial cells (RPE), human fibroblasts (HFF), mouse inner medullary collecting duct (IMCD) cells and mouse embryonic fibroblasts (MEFs). We hypothesize that the two distribution states of IFT88 correspond to the open and closed gating states of the TZ, where IFT particles aggregate to form three puncta when the gate is closed, and move to form the branches of the Y-shape pattern when the gate is open. Two reservoirs of IFT particles, correlating with phases of ciliary growth, were localized relative to the internal structure of the TZ. These subdiffraction images reveal unprecedented architectural details of the TZ, providing a basic structural framework for future functional studies. To visualize the dynamic movement of IFT particles within primary cilia, we further conducted superresolution live-cell imaging of IFT88 fused to EYFP in IMCD cells. Our findings, in particular, show IFT88 particles pass through the TZ at a reduced speed by approximately 50%, implying the gating mechanism is involved at this region to slow down IFT trafficking. Finally, we report the distinct transport pathways of IFT88 and Smo (Smoothened), an essential player to hedgehog signaling, to support our hypothesis that two proteins are transported in different mechanisms at the ciliary base, based on dual-color superresolution imaging.

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays

PubMed Central

Sánchez-Azqueta, Carlos; Goll, Bernhard; Celma, Santiago; Zimmermann, Horst

2016-01-01

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of −26.0 dBm and −25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10−9 ) with an energy efficiency of 2 pJ/bit. PMID:27231915

Back-gated graphene anode for more efficient thermionic energy converters

DOE PAGES

Yuan, Hongyuan; Riley, Daniel C.; Shen, Zhi-Xun; ...

2016-12-15

Thermionic energy converters (TECs) are a direct heat-to-electricity conversion technology with great potential for high efficiency and scalability. However, space charge barrier in the inter-electrode gap and high anode work function are major obstacles toward realizing high efficiency. Here, we demonstrate for the first time a prototype TEC using a back-gated graphene anode, a barium dispenser cathode, and a controllable inter-electrode gap as small as 17 µm, which simultaneously addresses these two obstacles. This leads to an electronic conversion efficiency of 9.8% at cathode temperature of 1000 °C, the highest reported by far. We first demonstrate that electrostatic gating ofmore » graphene by a 20 nm HfO 2 dielectric layer changes the graphene anode work function by 0.63 eV, as observed from the current-voltage characteristics of the TEC. Next, we show that the efficiency increases by a factor of 30.6 by reducing the gap from 1 mm down to 17 µm, after a mono-layer of Ba is deposited on graphene by the dispenser cathode. Lastlu, we show that electrostatic gating of graphene further reduces the graphene work function from 1.85 to 1.69 eV, leading to an additional 67% enhancement in TEC efficiency. Note that the overall efficiency using the back-gated graphene anode is 6.7 times higher compared with that of a TEC with a tungsten anode and the same inter-electrode gap.« less

Back-gated graphene anode for more efficient thermionic energy converters

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yuan, Hongyuan; Riley, Daniel C.; Shen, Zhi-Xun

Thermionic energy converters (TECs) are a direct heat-to-electricity conversion technology with great potential for high efficiency and scalability. However, space charge barrier in the inter-electrode gap and high anode work function are major obstacles toward realizing high efficiency. Here, we demonstrate for the first time a prototype TEC using a back-gated graphene anode, a barium dispenser cathode, and a controllable inter-electrode gap as small as 17 µm, which simultaneously addresses these two obstacles. This leads to an electronic conversion efficiency of 9.8% at cathode temperature of 1000 °C, the highest reported by far. We first demonstrate that electrostatic gating ofmore » graphene by a 20 nm HfO 2 dielectric layer changes the graphene anode work function by 0.63 eV, as observed from the current-voltage characteristics of the TEC. Next, we show that the efficiency increases by a factor of 30.6 by reducing the gap from 1 mm down to 17 µm, after a mono-layer of Ba is deposited on graphene by the dispenser cathode. Lastlu, we show that electrostatic gating of graphene further reduces the graphene work function from 1.85 to 1.69 eV, leading to an additional 67% enhancement in TEC efficiency. Note that the overall efficiency using the back-gated graphene anode is 6.7 times higher compared with that of a TEC with a tungsten anode and the same inter-electrode gap.« less

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

PubMed

Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

2016-06-09

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

Electric-field assisted switching of magnetization in perpendicularly magnetized (Ga,Mn)As films at high temperatures

NASA Astrophysics Data System (ADS)

Wang, Hailong; Ma, Jialin; Yu, Xueze; Yu, Zhifeng; Zhao, Jianhua

2017-01-01

The electric-field effects on the magnetism in perpendicularly magnetized (Ga,Mn)As films at high temperatures have been investigated. An electric-field as high as 0.6 V nm-1 is applied by utilizing a solid-state dielectric Al2O3 film as a gate insulator. The coercive field, saturation magnetization and magnetic anisotropy have been clearly changed by the gate electric-field, which are detected via the anomalous Hall effect. In terms of the Curie temperature, a variation of about 3 K is observed as determined by the temperature derivative of the sheet resistance. In addition, electrical switching of the magnetization assisted by a fixed external magnetic field at 120 K is demonstrated, employing the gate-controlled coercive field. The above experimental results have been attributed to the gate voltage modulation of the hole density in (Ga,Mn)As films, since the ferromagnetism in (Ga,Mn)As is carrier-mediated. The limited modulation magnitude of magnetism is found to result from the strong charge screening effect introduced by the high hole concentration up to 1.10  ×  1021 cm-3, while the variation of the hole density is only about 1.16  ×  1020 cm-3.

Electrode influence on the number of oxygen vacancies at the gate/high-κ dielectric interface in nanoscale MIM capacitors

NASA Astrophysics Data System (ADS)

Stojanovska-Georgievska, Lihnida

2015-02-01

In this paper, a particular attention has been paid in determining the impact of the type of top electrode (the gate), on the overall characteristics of the examined metal-insulator-metal structures, that contain doped Ta2O5:Hf high-κ dielectric as an insulator. For that purpose MIM capacitors with different metal gates (conventional Al and also W, Au, Pt, Mo, TiN, Ta) were formed. The results obtained, consider both the influence of metal work function and oxygen affinity, as possible reasons for increasing of number of oxygen vacancies at the gate/dielectric interface. Here we use capacitance-voltage alteration (C-V measurements) under constant current stress (CCS) conditions as characterization technique. The measurements show grater creation of positive oxygen vacancies in the case of metal electrodes with high work function, like Au and Pt, for almost one order of magnitude. It is also indicative that these metals have also the lowest values of heat of oxygen formation, which also favors the creation of oxygen vacancies. All results are discussed taking into consideration the nanoscale thickness of the dielectric layer (of the order of 8 nm), implicating the stronger effect of interface properties on the overall behavior rather than the one originating from the bulk of material.

Fabrication and electrical properties of MoS2 nanodisc-based back-gated field effect transistors.

PubMed

Gu, Weixia; Shen, Jiaoyan; Ma, Xiying

2014-02-28

Two-dimensional (2D) molybdenum disulfide (MoS2) is an attractive alternative semiconductor material for next-generation low-power nanoelectronic applications, due to its special structure and large bandgap. Here, we report the fabrication of large-area MoS2 nanodiscs and their incorporation into back-gated field effect transistors (FETs) whose electrical properties we characterize. The MoS2 nanodiscs, fabricated via chemical vapor deposition (CVD), are homogeneous and continuous, and their thickness of around 5 nm is equal to a few layers of MoS2. In addition, we find that the MoS2 nanodisc-based back-gated field effect transistors with nickel electrodes achieve very high performance. The transistors exhibit an on/off current ratio of up to 1.9 × 105, and a maximum transconductance of up to 27 μS (5.4 μS/μm). Moreover, their mobility is as high as 368 cm2/Vs. Furthermore, the transistors have good output characteristics and can be easily modulated by the back gate. The electrical properties of the MoS2 nanodisc transistors are better than or comparable to those values extracted from single and multilayer MoS2 FETs.

A Novel Pan-Negative-Gating Modulator of KCa2/3 Channels, Fluoro-Di-Benzoate, RA-2, Inhibits Endothelium-Derived Hyperpolarization–Type Relaxation in Coronary Artery and Produces Bradycardia In Vivo

PubMed Central

Oliván-Viguera, Aida; Valero, Marta Sofía; Coleman, Nicole; Brown, Brandon M.; Laría, Celia; Divina Murillo, María; Gálvez, José A.; Díaz-de-Villegas, María D.; Wulff, Heike; Badorrey, Ramón

2015-01-01

Small/intermediate conductance KCa channels (KCa2/3) are Ca2+/calmodulin regulated K+ channels that produce membrane hyperpolarization and shape neurologic, epithelial, cardiovascular, and immunologic functions. Moreover, they emerged as therapeutic targets to treat cardiovascular disease, chronic inflammation, and some cancers. Here, we aimed to generate a new pharmacophore for negative-gating modulation of KCa2/3 channels. We synthesized a series of mono- and dibenzoates and identified three dibenzoates [1,3-phenylenebis(methylene) bis(3-fluoro-4-hydroxybenzoate) (RA-2), 1,2-phenylenebis(methylene) bis(3-fluoro-4-hydroxybenzoate), and 1,4-phenylenebis(methylene) bis(3-fluoro-4-hydroxybenzoate)] with inhibitory efficacy as determined by patch clamp. Among them, RA-2 was the most drug-like and inhibited human KCa3.1 with an IC50 of 17 nM and all three human KCa2 subtypes with similar potencies. RA-2 at 100 nM right-shifted the KCa3.1 concentration-response curve for Ca2+ activation. The positive-gating modulator naphtho[1,2-d]thiazol-2-ylamine (SKA-31) reversed channel inhibition at nanomolar RA-2 concentrations. RA-2 had no considerable blocking effects on distantly related large-conductance KCa1.1, Kv1.2/1.3, Kv7.4, hERG, or inwardly rectifying K+ channels. In isometric myography on porcine coronary arteries, RA-2 inhibited bradykinin-induced endothelium-derived hyperpolarization (EDH)–type relaxation in U46619-precontracted rings. Blood pressure telemetry in mice showed that intraperitoneal application of RA-2 (≤100 mg/kg) did not increase blood pressure or cause gross behavioral deficits. However, RA-2 decreased heart rate by ≈145 beats per minute, which was not seen in KCa3.1−/− mice. In conclusion, we identified the KCa2/3–negative-gating modulator, RA-2, as a new pharmacophore with nanomolar potency. RA-2 may be of use to generate structurally new types of negative-gating modulators that could help to define the physiologic and pathomechanistic roles of KCa2/3 in the vasculature, central nervous system, and during inflammation in vivo. PMID:25468883

Two-dimensional analytical model for dual-material control-gate tunnel FETs

NASA Astrophysics Data System (ADS)

Xu, Hui Fang; Dai, Yue Hua; Gui Guan, Bang; Zhang, Yong Feng

2016-09-01

An analytical model for a dual-material control-gate (DMCG) tunnel field effect transistor (TFET) is presented for the first time in this paper, and the influence of the mobile charges on the potential profile is taken into account. On the basis of the potential profile, the lateral electric field is derived and the expression for the drain current is obtained by integrating the band-to-band tunneling (BTBT) generation rate applicable to low-bandgap and high-bandgap materials over the tunneling region. The model also predicts the impacts of the control-gate work function on the potential and drain current. The advantage of this work is that it not only offers physical insight into device physics but also provides the basic designing guideline for DMCG TFETs, enabling the designer to optimize the device in terms of the on-state current, the on-off current ratio, and suppressed ambipolar behavior. Very good agreements for both the potential and drain current are observed between the model calculations and the simulated results.

Dynamic CT imaging of volumetric changes in pulmonary nodules correlates with physical measurements of stiffness.

PubMed

Lartey, Frederick M; Rafat, Marjan; Negahdar, Mohammadreza; Malkovskiy, Andrey V; Dong, Xinzhe; Sun, Xiaoli; Li, Mei; Doyle, Timothy; Rajadas, Jayakumar; Graves, Edward E; Loo, Billy W; Maxim, Peter G

2017-02-01

A major challenge in CT screening for lung cancer is limited specificity when distinguishing between malignant and non-malignant pulmonary nodules (PN). Malignant nodules have different mechanical properties and tissue characteristics ('stiffness') from non-malignant nodules. This study seeks to improve CT specificity by demonstrating in rats that measurements of volumetric ratios in PNs with varying composition can be determined by respiratory-gated dynamic CT imaging and that these ratios correlate with direct physical measurements of PN stiffness. Respiratory-gated MicroCT images acquired at extreme tidal volumes of 9 rats with PNs from talc, matrigel and A549 human lung carcinoma were analyzed and their volumetric ratios (δ) derived. PN stiffness was determined by measuring the Young's modulus using atomic force microscopy (AFM) for each nodule excised immediately after MicroCT imaging. There was significant correlation (p=0.0002) between PN volumetric ratios determined by respiratory-gated CT imaging and the physical stiffness of the PNs determined from AFM measurements. We demonstrated proof of concept that PN volume changes measured non-invasively correlate with direct physical measurements of stiffness. These results may translate clinically into a means of improving the specificity of CT screening for lung cancer and/or improving individual prognostic assessments based on lung tumor stiffness. Copyright © 2016 Elsevier Ireland Ltd. All rights reserved.

Hafnium oxide films for application as gate dielectrics

NASA Astrophysics Data System (ADS)

Hsu, Shuo-Lin

The deposition and characterization of HfO2 films for potential application as a high-kappa gate dielectric in MOS devices has been investigated. DC magnetron reactive sputtering was utilized to prepare the HfO2 films. Structural, chemical, and electrical analyses were performed to characterize the various physical, chemical and electrical properties of the sputtered HfO2 films. The sputtered HfO2 films were annealed to simulate the dopant activation process used in semiconductor processing, and to study the thermal stability of the high-kappa, films. The changes in the film properties due to the annealing are also discussed in this work. Glancing angle XRD was used to analyse the atomic scale structure of the films. The as deposited films exhibit an amorphous, regardless of the film thickness. During post-deposition annealing, the thicker films crystallized at lower temperature (< 600°C), and ultra-thin (5.8 nm) film crystallized at higher temperature (600--720°C). The crystalline phase which formed depended on the thickness of the films. The low temperature phase (monoclinic) formed in the 10--20 nm annealed films, and high temperature phase (tetragonal) formed in the ultra-thin annealed HfO2 film. TEM cross-section studies of as deposited samples show that an interfacial layer (< 1nm) exists between HfO2/Si for all film thicknesses. The interfacial layer grows thicker during heat treatment, and grows more rapidly when grain boundaries are present. XPS surface analysis shows the as deposited films are fully oxidized with an excess of oxygen. Interfacial chemistry analysis indicated that the interfacial layer is a silicon-rich silicate layer, which tends to transform to silica-like layer during heat treatment. I-V measurements show the leakage current density of the Al/as deposited-HfO 2/Si MOS diode is of the order of 10-3 A/cm 2, two orders of magnitude lower than that of a ZrO2 film with similar physical thickness. Carrier transport is dominated by Schottky emission at lower electric fields, and by Frenkel-Poole emission in the higher electric field region. After annealing, the leakage current density decreases significantly as the structure remains amorphous structure. It is suggested that this decrease is assorted with the densification and defect healing which accures when the porous as-deposited amorphous structure is annealed. The leakage current density increases of the HfO2 layer crystallizes on annealing, which is attributed to the presence of grain boundaries. C-V measurements of the as deposited film shows typical C-V characteristics, with negligible hystersis, a small flat band voltage shift, but great frequency dispersion. The relative permittivity of HfO2/interfacial layer stack obtained from the capacitance at accumulation is 15, which corresponds to an EOT (equivalent oxide thickness) = 1.66 nm. After annealing, the frequency dispersion is greatly enhanced, and the C-V curve is shifted toward the negative voltage. Reliability tests show that the HfO2 films which remain amorphous after annealing possess superior resistance to constant voltage stress and ambient aging. This study concluded that the sputtered HfO 2 films exhibit an amorphous as deposited. Postdeposition annealing alters the crystallinity, interfacial properties, and electrical characteristics. The HfO2 films which remain amorphous structure after annealing possess the best electrical properties.

The comprehensive analysis of DEG/ENaC subunits in Hydra reveals a large variety of peptide-gated channels, potentially involved in neuromuscular transmission.

PubMed

Assmann, Marc; Kuhn, Anne; Dürrnagel, Stefan; Holstein, Thomas W; Gründer, Stefan

2014-10-14

It is generally the case that fast transmission at neural synapses is mediated by small molecule neurotransmitters. The simple nervous system of the cnidarian Hydra, however, contains a large repertoire of neuropeptides and it has been suggested that neuropeptides are the principal transmitters of Hydra. An ion channel directly gated by Hydra-RFamide neuropeptides has indeed been identified in Hydra - the Hydra Na+ channel (HyNaC) 2/3/5, which is expressed at the oral side of the tentacle base. Hydra-RFamides are more widely expressed, however, being found in neurons of the head and peduncle region. Here, we explore whether further peptide-gated HyNaCs exist, where in the animal they are expressed, and whether they are all gated by Hydra-RFamides. We report molecular cloning of seven new HyNaC subunits - HyNaC6 to HyNaC12, all of which are members of the DEG/ENaC gene family. In Xenopus oocytes, these subunits assemble together with the four already known subunits into thirteen different ion channels that are directly gated by Hydra-RFamide neuropeptides with high affinity (up to 40 nM). In situ hybridization suggests that HyNaCs are expressed in epitheliomuscular cells at the oral and the aboral side of the tentacle base and at the peduncle. Moreover, diminazene, an inhibitor of HyNaCs, delayed tentacle movement in live Hydra. Our results show that Hydra has a large variety of peptide-gated ion channels that are activated by a restricted number of related neuropeptides. The existence and expression pattern of these channels, and behavioral effects induced by channel blockers, suggests that Hydra co-opted neuropeptides for fast neuromuscular transmission.

Physics Notes.

ERIC Educational Resources Information Center

School Science Review, 1978

1978-01-01

Discusses some high school physics demonstrations and experiments on a variety of topics: such as uses of the dipole, the vapour-liquid critical point, velocity of sound in metallic rods, the flux-density near a bar magnet, and a different style logic gate using basic units. (GA)

Ion-selective electrolyte-gated field-effect transistors: prerequisites for proper functioning

NASA Astrophysics Data System (ADS)

Kofler, Johannes; Schmoltner, Kerstin; List-Kratochvil, Emil J. W.

2014-10-01

Electrolyte-gated organic field-effect transistors (EGOFETs) used as transducers and amplifiers in potentiometric sensors have recently attracted a significant amount of scientific interest. For that reason, the fundamental prerequisites to achieve a proper potentiometric signal amplification and transduction are examined. First, polarizable as well as non-polarizable semiconductor- and gate-electrolyte- interface combinations are investigated by normal pulse voltammetry. The results of these measurements are correlated with the corresponding transistor characteristics, clarifying the functional principle of EGOFETs and the requirements for high signal amplification. In addition to a good electrical performance, the EGOFET-transducers should also be compatible with the targeted sensing application. Accordingly, the influence of different gate materials and electrolytes on the sensing abilities, are discussed. Even though all physical requirements are met, EGOFETs typically exhibit irreversible degradation, if the gate potential exceeds a certain level. For that reason, EGOFETs have to be operated using a constant source-drain operation mode which is presented by means of an H+ (pH) sensitive ion-sensor.

Tuning the metal-insulator crossover and magnetism in SrRuO 3 by ionic gating

DOE PAGES

Yi, Hee Taek; Gao, Bin; Xie, Wei; ...

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. We report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO 3. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90–250 K and 70–100 K,more » respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.« less

Tuning the metal-insulator crossover and magnetism in SrRuO₃ by ionic gating.

PubMed

Yi, Hee Taek; Gao, Bin; Xie, Wei; Cheong, Sang-Wook; Podzorov, Vitaly

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. Here we report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO₃. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90-250 K and 70-100 K, respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.

Computation of Flow Through Water-Control Structures Using Program DAMFLO.2

USGS Publications Warehouse

Sanders, Curtis L.; Feaster, Toby D.

2004-01-01

As part of its mission to collect, analyze, and store streamflow data, the U.S. Geological Survey computes flow through several dam structures throughout the country. Flows are computed using hydraulic equations that describe flow through sluice and Tainter gates, crest gates, lock gates, spillways, locks, pumps, and siphons, which are calibrated using flow measurements. The program DAMFLO.2 was written to compute, tabulate, and plot flow through dam structures using data that describe the physical properties of dams and various hydraulic parameters and ratings that use time-varying data, such as lake elevations or gate openings. The program uses electronic computer files of time-varying data, such as lake elevation or gate openings, retrieved from the U.S. Geological Survey Automated Data Processing System. Computed time-varying flow data from DAMFLO.2 are output in flat files, which can be entered into the Automated Data Processing System database. All computations are made in units of feet and seconds. DAMFLO.2 uses the procedures and language developed by the SAS Institute Inc.

Multi-element logic gates for trapped-ion qubits

NASA Astrophysics Data System (ADS)

Tan, T. R.; Gaebler, J. P.; Lin, Y.; Wan, Y.; Bowler, R.; Leibfried, D.; Wineland, D. J.

2015-12-01

Precision control over hybrid physical systems at the quantum level is important for the realization of many quantum-based technologies. In the field of quantum information processing (QIP) and quantum networking, various proposals discuss the possibility of hybrid architectures where specific tasks are delegated to the most suitable subsystem. For example, in quantum networks, it may be advantageous to transfer information from a subsystem that has good memory properties to another subsystem that is more efficient at transporting information between nodes in the network. For trapped ions, a hybrid system formed of different species introduces extra degrees of freedom that can be exploited to expand and refine the control of the system. Ions of different elements have previously been used in QIP experiments for sympathetic cooling, creation of entanglement through dissipation, and quantum non-demolition measurement of one species with another. Here we demonstrate an entangling quantum gate between ions of different elements which can serve as an important building block of QIP, quantum networking, precision spectroscopy, metrology, and quantum simulation. A geometric phase gate between a 9Be+ ion and a 25Mg+ ion is realized through an effective spin-spin interaction generated by state-dependent forces induced with laser beams. Combined with single-qubit gates and same-species entangling gates, this mixed-element entangling gate provides a complete set of gates over such a hybrid system for universal QIP. Using a sequence of such gates, we demonstrate a CNOT (controlled-NOT) gate and a SWAP gate. We further demonstrate the robustness of these gates against thermal excitation and show improved detection in quantum logic spectroscopy. We also observe a strong violation of a CHSH (Clauser-Horne-Shimony-Holt)-type Bell inequality on entangled states composed of different ion species.

Multi-element logic gates for trapped-ion qubits.

PubMed

Tan, T R; Gaebler, J P; Lin, Y; Wan, Y; Bowler, R; Leibfried, D; Wineland, D J

2015-12-17

Precision control over hybrid physical systems at the quantum level is important for the realization of many quantum-based technologies. In the field of quantum information processing (QIP) and quantum networking, various proposals discuss the possibility of hybrid architectures where specific tasks are delegated to the most suitable subsystem. For example, in quantum networks, it may be advantageous to transfer information from a subsystem that has good memory properties to another subsystem that is more efficient at transporting information between nodes in the network. For trapped ions, a hybrid system formed of different species introduces extra degrees of freedom that can be exploited to expand and refine the control of the system. Ions of different elements have previously been used in QIP experiments for sympathetic cooling, creation of entanglement through dissipation, and quantum non-demolition measurement of one species with another. Here we demonstrate an entangling quantum gate between ions of different elements which can serve as an important building block of QIP, quantum networking, precision spectroscopy, metrology, and quantum simulation. A geometric phase gate between a (9)Be(+) ion and a (25)Mg(+) ion is realized through an effective spin-spin interaction generated by state-dependent forces induced with laser beams. Combined with single-qubit gates and same-species entangling gates, this mixed-element entangling gate provides a complete set of gates over such a hybrid system for universal QIP. Using a sequence of such gates, we demonstrate a CNOT (controlled-NOT) gate and a SWAP gate. We further demonstrate the robustness of these gates against thermal excitation and show improved detection in quantum logic spectroscopy. We also observe a strong violation of a CHSH (Clauser-Horne-Shimony-Holt)-type Bell inequality on entangled states composed of different ion species.

Behaviour of a series of reservoirs separated by drowned gates

NASA Astrophysics Data System (ADS)

Kolechkina, Alla; van Nooijen, Ronald

2017-04-01

Modern control systems tend to be based on computers and therefore to operate by sending commands to structures at given intervals (discrete time control system). Moreover, for almost all water management control systems there are practical lower limits on the time interval between structure adjustments and even between measurements. The water resource systems that are being controlled are physical systems whose state changes continuously. If we combine a continuously changing system and a discrete time controller we get a hybrid system. We use material from recent control theory literature to examine the behaviour of a series of reservoirs separated by drowned gates where the gates are under computer control.

Magnetic tunnel junction based spintronic logic devices

NASA Astrophysics Data System (ADS)

Lyle, Andrew Paul

The International Technology Roadmap for Semiconductors (ITRS) predicts that complimentary metal oxide semiconductor (CMOS) based technologies will hit their last generation on or near the 16 nm node, which we expect to reach by the year 2025. Thus future advances in computational power will not be realized from ever-shrinking device sizes, but rather by 'outside the box' designs and new physics, including molecular or DNA based computation, organics, magnonics, or spintronic. This dissertation investigates magnetic logic devices for post-CMOS computation. Three different architectures were studied, each relying on a different magnetic mechanism to compute logic functions. Each design has it benefits and challenges that must be overcome. This dissertation focuses on pushing each design from the drawing board to a realistic logic technology. The first logic architecture is based on electrically connected magnetic tunnel junctions (MTJs) that allow direct communication between elements without intermediate sensing amplifiers. Two and three input logic gates, which consist of two and three MTJs connected in parallel, respectively were fabricated and are compared. The direct communication is realized by electrically connecting the output in series with the input and applying voltage across the series connections. The logic gates rely on the fact that a change in resistance at the input modulates the voltage that is needed to supply the critical current for spin transfer torque switching the output. The change in resistance at the input resulted in a voltage margin of 50--200 mV and 250--300 mV for the closest input states for the three and two input designs, respectively. The two input logic gate realizes the AND, NAND, NOR, and OR logic functions. The three input logic function realizes the Majority, AND, NAND, NOR, and OR logic operations. The second logic architecture utilizes magnetostatically coupled nanomagnets to compute logic functions, which is the basis of Magnetic Quantum Cellular Automata (MQCA). MQCA has the potential to be thousands of times more energy efficient than CMOS technology. While interesting, these systems are academic unless they can be interfaced into current technologies. This dissertation pushed past a major hurdle by experimentally demonstrating a spintronic input/output (I/O) interface for the magnetostatically coupled nanomagnets by incorporating MTJs. This spintronic interface allows individual nanomagnets to be programmed using spin transfer torque and read using magneto resistance structure. Additionally the spintronic interface allows statistical data on the reliability of the magnetic coupling utilized for data propagation to be easily measured. The integration of spintronics and MQCA for an electrical interface to achieve a magnetic logic device with low power creates a competitive post-CMOS logic device. The final logic architecture that was studied used MTJs to compute logic functions and magnetic domain walls to communicate between gates. Simulations were used to optimize the design of this architecture. Spin transfer torque was used to compute logic function at each MTJ gate and was used to drive the domain walls. The design demonstrated that multiple nanochannels could be connected to each MTJ to realize fan-out from the logic gates. As a result this logic scheme eliminates the need for intermediate reads and conversions to pass information from one logic gate to another.

1-GHz repetition rate femtosecond OPO with stabilized offset between signal and idler frequency combs.

PubMed

Gebs, R; Dekorsy, T; Diddams, S A; Bartels, A

2008-04-14

We report an optical parametric oscillator (OPO) based on periodically poled lithium niobate (PPLN) that is synchronously pumped by a femtosecond Ti:sapphire laser at 1 GHz repetition rate. The signal output has a center wavelength of 1558 nm and its spectral bandwidth amounts to 40 nm. The OPO operates in a regime where the signal- and idler frequency combs exhibit a partial overlap around 1600 nm. In this near-degeneracy region, a beat at the offset between the signal and idler frequency combs is detected. Phase-locking this beat to an external reference stabilizes the spectral envelopes of the signal- and idler output. At the same time, the underlying frequency combs are stabilized relative to each other with an instability of 1.5x10(-17) at 1 s gate time.

A digital boxcar integrator for IMS spectra

NASA Technical Reports Server (NTRS)

Cohen, Martin J.; Stimac, Robert M.; Wernlund, Roger F.; Parker, Donald C.

1995-01-01

When trying to detect or quantify a signal at or near the limit of detectability, it is invariably embeded in the noise. This statement is true for nearly all detectors of any physical phenomena and the limit of detectability, hopefully, occurs at very low signal-to-noise levels. This is particularly true of IMS (Ion Mobility Spectrometers) spectra due to the low vapor pressure of several chemical compounds of great interest and the small currents associated with the ionic detection process. Gated Integrators and Boxcar Integrators or Averagers are designed to recover fast, repetitive analog signals. In a typical application, a time 'Gate' or 'Window' is generated, characterized by a set delay from a trigger or gate pulse and a certain width. A Gated Integrator amplifies and integrates the signal that is present during the time the gate is open, ignoring noise and interference that may be present at other times. Boxcar Integration refers to the practice of averaging the output of the Gated Integrator over many sweeps of the detector. Since any signal present during the gate will add linearly, while noise will add in a 'random walk' fashion as the square root of the number of sweeps, averaging N sweeps will improve the 'Signal-to-Noise Ratio' by a factor of the square root of N.

Analysis and optimization of RC delay in vertical nanoplate FET

NASA Astrophysics Data System (ADS)

Woo, Changbeom; Ko, Kyul; Kim, Jongsu; Kim, Minsoo; Kang, Myounggon; Shin, Hyungcheol

2017-10-01

In this paper, we have analyzed short channel effects (SCEs) and RC delay with Vertical nanoplate FET (VNFET) using 3-D Technology computer-aided design (TCAD) simulation. The device is based on International Technology Road-map for Semiconductor (ITRS) 2013 recommendations, and it has initially gate length (LG) of 12.2 nm, channel thickness (Tch) of 4 nm, and spacer length (LSD) of 6 nm. To obtain improved performance by reducing RC delay, each dimension is adjusted (LG = 12.2 nm, Tch = 6 nm, LSD = 11.9 nm). It has each characteristic in this dimension (Ion/Ioff = 1.64 × 105, Subthreshold swing (S.S.) = 73 mV/dec, Drain-induced barrier lowering (DIBL) = 60 mV/V, and RC delay = 0.214 ps). Furthermore, with long shallow trench isolation (STI) length and thick insulator thickness (Ti), we can reduce RC delay from 0.214 ps to 0.163 ps. It is about a 23.8% reduction. Without decreasing drain current, there is a reduction of RC delay as reducing outer fringing capacitance (Cof). Finally, when source/drain spacer length is set to be different, we have verified RC delay to be optimum.

Lanthanide-based oxides and silicates for high-kappa gate dielectric applications

NASA Astrophysics Data System (ADS)

Jur, Jesse Stephen

The ability to improve performance of the high-end metal oxide semiconductor field effect transistor (MOSFET) is highly reliant on the dimensional scaling of such a device. In scaling, a decrease in dielectric thickness results in high current leakage between the electrode and the substrate by way of direct tunneling through the gate dielectric. Observation of a high leakage current when the standard gate dielectric, SiO2, is decreased below a thickness of 1.5 nm requires engineering of a replacement dielectric that is much more scalable. This high-kappa dielectric allows for a physically thicker oxide, reducing leakage current. Integration of select lanthanide-based oxides and silicates, in particular lanthanum oxide and silicate, into MOS gate stack devices is examined. The quality of the high-kappa dielectrics is monitored electrically to determine properties such as equivalent oxide thickness, leakage current density and defect densities. In addition, analytical characterization of the dielectric and the gate stack is provided to examine the materialistic significance to the change of the electrical properties of the devices. In this work, lanthanum oxide films have been deposited by thermal evaporation on to a pre-grown chemical oxide layer on silicon. It is observed that the SiO2 interfacial layer can be consumed by a low-temperature reaction with lanthanum oxide to produce a high-quality silicate. This is opposed to depositing lanthanum oxide directly on silicon, which can possibly favor silicide formation. The importance of oxygen regulation in the surrounding environment of the La2O3-SiO2 reaction-anneal is observed. By controlling the oxygen available during the reaction, SiO2 growth can be limited to achieve high stoichiometric ratios of La2O 3 to SiO2. As a result, MOS devices with an equivalent oxide thickness (EOT) of 5 A and a leakage current density of 5.0 A/cm 2 are attained. This data equals the best value achieved in this field and is a substantial improvement over SiO(N) dielectrics, allowing for increased device scaling. High-temperature processing, consistent with the source/drain activation anneal in MOSFET processing, is performed on lanthanum-silicate based MOS devices with Ta or TaN gate electrodes and a W metal capping layer. The thermal limit of Ta is observed to be less than 800°C, resulting in a phase transformation that can result in uncontrolled shifting of the MOS device flat-band voltage. TaN is observed to be more thermally stable (up to 1000°C) and results in an increase in the capacitance density suggesting that it impedes oxygen reaction with silicon to produce SiO2. It is later observed that a W metal capping layer can serve as a high-oxygen source, which results in an increased interfacial SiO2 formation. By limiting the oxygen content in the W capping layer and by utilizing a thermally stable TaN gate electrode, control over the electrical properties of the MOS device is acquired. To determine the stability of amorphous lanthanum-silicate in contact with investigated by means of back-side secondary ion mass spectroscopy profiling. The results are the first reported data showing that the lanthanum incorporated in the silica matrix doe not diffuse into the silicon substrate after high temperature processing. The decrease in the device effective work function (φM,eff ) observed in these samples is examined in detail. First, as a La 2O3 capping layer on HfSiO(N), the shift yields ideal-φ M,eff values for nMOSFET deices (4.0 eV) that were previously inaccessible. Other lanthanide oxides (Dy, Ho and Yb) used as capping layers show similar effects. It is also shown that tuning of φM,eff can be realized by controlling the extent of lanthanide-silicate formation. This research, conducted in conjunction with SEMATECH and the SRC, represents a significant technological advancement in realizing 45 and sub-45 nm MOSFET device nodes.

Physical realization of topological quantum walks on IBM-Q and beyond

NASA Astrophysics Data System (ADS)

Balu, Radhakrishnan; Castillo, Daniel; Siopsis, George

2018-07-01

We discuss an efficient physical realization of topological quantum walks on a one-dimensional finite lattice with periodic boundary conditions (circle). The N-point lattice is realized with {log}}2N qubits, and the quantum circuit utilizes a number of quantum gates that are polynomial in the number of qubits. In a certain scaling limit, we show that a large number of steps are implemented with a number of quantum gates which are independent of the number of steps. We ran the quantum algorithm on the IBM-Q five-qubit quantum computer, thus experimentally demonstrating topological features, such as boundary bound states, on a one-dimensional lattice with N = 4 points.

Engineering Ultra-Low Work Function of Graphene.

PubMed

Yuan, Hongyuan; Chang, Shuai; Bargatin, Igor; Wang, Ning C; Riley, Daniel C; Wang, Haotian; Schwede, Jared W; Provine, J; Pop, Eric; Shen, Zhi-Xun; Pianetta, Piero A; Melosh, Nicholas A; Howe, Roger T

2015-10-14

Low work function materials are critical for energy conversion and electron emission applications. Here, we demonstrate for the first time that an ultralow work function graphene is achieved by combining electrostatic gating with a Cs/O surface coating. A simple device is built from large-area monolayer graphene grown by chemical vapor deposition, transferred onto 20 nm HfO2 on Si, enabling high electric fields capacitive charge accumulation in the graphene. We first observed over 0.7 eV work function change due to electrostatic gating as measured by scanning Kelvin probe force microscopy and confirmed by conductivity measurements. The deposition of Cs/O further reduced the work function, as measured by photoemission in an ultrahigh vacuum environment, which reaches nearly 1 eV, the lowest reported to date for a conductive, nondiamond material.

Electronic Cortisol Detection Using an Antibody-Embedded Polymer Coupled to a Field-Effect Transistor.

PubMed

Jang, Hyun-June; Lee, Taein; Song, Jian; Russell, Luisa; Li, Hui; Dailey, Jennifer; Searson, Peter C; Katz, Howard E

2018-05-16

A field-effect transistor-based cortisol sensor was demonstrated in physiological conditions. An antibody-embedded polymer on the remote gate was proposed to overcome the Debye length issue (λ D ). The sensing membrane was made by linking poly(styrene- co-methacrylic acid) (PSMA) with anticortisol before coating the modified polymer on the remote gate. The embedded receptor in the polymer showed sensitivity from 10 fg/mL to 10 ng/mL for cortisol and a limit of detection (LOD) of 1 pg/mL in 1× PBS where λ D is 0.2 nm. A LOD of 1 ng/mL was shown in lightly buffered artificial sweat. Finally, a sandwich ELISA confirmed the antibody binding activity of antibody-embedded PSMA.

Positive and negative gain exceeding unity magnitude in silicon quantum well metal-oxide-semiconductor transistors

NASA Astrophysics Data System (ADS)

Hu, Gangyi; Wijesinghe, Udumbara; Naquin, Clint; Maggio, Ken; Edwards, H. L.; Lee, Mark

2017-10-01

Intrinsic gain (AV) measurements on Si quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors show that these devices can have |AV| > 1 in quantum transport negative transconductance (NTC) operation at room temperature. QW NMOS devices were fabricated using an industrial 45 nm technology node process incorporating ion implanted potential barriers to define a lateral QW in the conduction channel under the gate. While NTC at room temperature arising from transport through gate-controlled QW bound states has been previously established, it was unknown whether the quantum NTC mechanism could support gain magnitude exceeding unity. Bias conditions were found giving both positive and negative AV with |AV| > 1 at room temperature. This result means that QW NMOS devices could be useful in amplifier and oscillator applications.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

NASA Astrophysics Data System (ADS)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG in the form of PVD TaN was investigated along with high-k blocking dielectric. The material properties of TaN metal and high-k / low-k dielectric engineering were systematically studied. And the resulting memory structures exhibit excellent memory characteristics and scalability of the metal FG down to ˜1nm, which is promising in order to reduce the unwanted FG-FG interferences. In the later part of the study, the thermal stability of the combined stack was examined and various approaches to improve the stability and understand the cause of instability were explored. The performance of the high-k IPD metal FG memory structure was observed to degrade with higher annealing conditions and the deteriorated behavior was attributed to the leakage instability of the high-k /TaN capacitor. While the degradation is pronounced in both MIM and MIS capacitors, a higher leakage increment was seen in MIM, which was attributed to the higher degree of dielectric crystallization. In an attempt to improve the thermal stability, the trade-off in using amorphous interlayers to reduce the enhanced dielectric crystallization on metal was highlighted. Also, the effect of oxygen vacancies and grain growth on the dielectric leakage was studied through a multi-deposition-multi-anneal technique. Multi step deposition and annealing in a more electronegative ambient was observed to have a positive impact on the dielectric performance.