Micromachined Thin-Film Sensors for SOI-CMOS Co-Integration

NASA Astrophysics Data System (ADS)

Laconte, Jean; Flandre, D.; Raskin, Jean-Pierre

Co-integration of sensors with their associated electronics on a single silicon chip may provide many significant benefits regarding performance, reliability, miniaturization and process simplicity without significantly increasing the total cost. Micromachined Thin-Film Sensors for SOI-CMOS Co-integration covers the challenges and interests and demonstrates the successful co-integration of gas flow sensors on dielectric membrane, with their associated electronics, in CMOS-SOI technology. We firstly investigate the extraction of residual stress in thin layers and in their stacking and the release, in post-processing, of a 1 μm-thick robust and flat dielectric multilayered membrane using Tetramethyl Ammonium Hydroxide (TMAH) silicon micromachining solution.

Solid State Research.

DTIC Science & Technology

1984-08-15

for the Same Signal 30 3 -1 Schematic Diagrams of Two Configurations with SOI/ CMOS and Bipolar Devices Fabricated on the Same Si Wafer. The Bipolar...Waveform of 39-Stage SOI/ CMOS Ring Oscillator for 5-V Supply Voltage. The Propagation Delay per Stage is 藨 ps 33 3 -4 Common-Emitter I-V...multiple beam splitters and delay lines. 3 . MATERIALS RESEARCH Two merged CMOS ! bipolar technologies utilizing S01 films have been developed for

Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

NASA Technical Reports Server (NTRS)

DeGregorio, Kelly; Wilson, Dale G.

2009-01-01

Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand-alone ReBiLS chip will allow system designers to provide efficient bi-directional communication between components operating at different voltages. Embedding the ReBiLS cells into the proven Reed-Solomon encoder will demonstrate the ability to support new product development in a commercially viable, rad-hard, scalable 180-nm SOI CMOS process.

A silicon-on-insulator complementary-metal-oxide-semiconductor compatible flexible electronics technology

NASA Astrophysics Data System (ADS)

Tu, Hongen; Xu, Yong

2012-07-01

This paper reports a simple flexible electronics technology that is compatible with silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) processes. Compared with existing technologies such as direct fabrication on flexible substrates and transfer printing, the main advantage of this technology is its post-SOI-CMOS compatibility. Consequently, high-performance and high-density CMOS circuits can be first fabricated on SOI wafers using commercial foundry and then be integrated into flexible substrates. The yield is also improved by eliminating the transfer printing step. Furthermore, this technology allows the integration of various sensors and microfluidic devices. To prove the concept of this technology, flexible MOSFETs have been demonstrated.

Channel add-drop filter based on dual photonic crystal cavities in push-pull mode.

PubMed

Poulton, Christopher V; Zeng, Xiaoge; Wade, Mark T; Popović, Miloš A

2015-09-15

We demonstrate an add-drop filter based on a dual photonic crystal nanobeam cavity system that emulates the operation of a traveling wave resonator, and, thus, provides separation of the through and drop port transmission from the input port. The device is on a 3×3  mm chip fabricated in an advanced microelectronics silicon-on-insulator complementary metal-oxide semiconductor (SOI CMOS) process (IBM 45 nm SOI) without any foundry process modifications. The filter shows 1 dB of insertion loss in the drop port with a 3 dB bandwidth of 64 GHz, and 16 dB extinction in the through port. To the best of our knowledge, this is the first implementation of a port-separating, add-drop filter based on standing wave cavities coupled to conventional waveguides, and demonstrates a performance that suggests potential for photonic crystal devices within optical immersion lithography-based advanced CMOS electronics-photonics integration.

SOI-silicon as structural layer for NEMS applications

NASA Astrophysics Data System (ADS)

Villarroya, Maria; Figueras, Eduard; Perez-Murano, Francesc; Campabadal, Francesca; Esteve, Jaume; Barniol, Nuria

2003-04-01

The objective of this paper is to present the compatibilization between a standard CMOS on bulk silicon process and the fabrication of nanoelectromechanical systems using Silicon On Insulator (SOI) wafers as substrate. This compatibilization is required as first step to fabricate a very high sensitive mass sensor based on a resonant cantilever with nanometer dimensions using the crystal silicon COI layer as the structural layer. The cantilever is driven electrostatically to its resonance frequency by an electrode placed parallel to the cantilever. A capacitive readout is performed. To achieve very high resolution, very small dimensions of the cantilever (nanometer range) are needed. For this reason, the control and excitation circuitry has to be integrated on the same substrate than the cantilever. Prior to the development of this sensor, it is necessary to develop a substrate able to be used first to integrate a standard CMOS circuit and afterwards to fabricate the nano-resonator. Starting from a SOI wafer and using very simple processes, the SOI silicon layer is removed, except from the areas in which nano-structures will be fabricated; obtaining a silicon substrate with islands with a SOI structure. The CMOS circuitry will be integrated on the bulk silicon region, while the remainder SOI region will be used for the nanoresonator. The silicon oxide of this SOI region is used as insulator; and as sacrificial layer, etched to release the cantilever from the substrate. To assure the cover of the different CMOS layers over the step of the islands, it is essential to avoid very sharp steps.

25Gb/s 1V-driving CMOS ring modulator with integrated thermal tuning.

PubMed

Li, Guoliang; Zheng, Xuezhe; Yao, Jin; Thacker, Hiren; Shubin, Ivan; Luo, Ying; Raj, Kannan; Cunningham, John E; Krishnamoorthy, Ashok V

2011-10-10

We report a high-speed ring modulator that fits many of the ideal qualities for optical interconnect in future exascale supercomputers. The device was fabricated in a 130 nm SOI CMOS process, with 7.5 μm ring radius. Its high-speed section, employing PN junction that works at carrier-depletion mode, enables 25 Gb/s modulation and an extinction ratio >5 dB with only 1V peak-to-peak driving. Its thermal tuning section allows the device to work in broad wavelength range, with a tuning efficiency of 0.19 nm/mW. Based on microwave characterization and circuit modeling, the modulation energy is estimated ~7 fJ/bit. The whole device fits in a compact 400 μm2 footprint.

Design and implementation of a low-power SOI CMOS receiver

NASA Astrophysics Data System (ADS)

Zencir, Ertan

There is a strong demand for wireless communications in civilian and military applications, and space explorations. This work attempts to implement a low-power, high-performance fully-integrated receiver for deep space communications using Silicon on Insulator (SOI) CMOS technology. Design and implementation of a UHF low-IF receiver front-end in a 0.35-mum SOI CMOS technology are presented. Problems and challenges in implementing a highly integrated receiver at UHF are identified. Low-IF architecture, suitable for low-power design, has been adopted to mitigate the noise at the baseband. Design issues of the receiver building blocks including single-ended and differential LNA's, passive and active mixers, and variable gain/bandwidth complex filters are discussed. The receiver is designed to have a variable conversion gain of more than 100 dB with a 70 dB image rejection and a power dissipation of 45 mW from a 2.5-V supply. Design and measured performance of the LNA's, and the mixer are presented. Measurement results of RF front-end blocks including a single-ended LNA, a differential LNA, and a double-balanced mixer demonstrate the low power realizability of RF front-end circuits in SOI CMOS technology. We also report on the design and simulation of the image-rejecting complex IF filter and the full receiver circuit. Gain, noise, and linearity performance of the receiver components prove the viability of fully integrated low-power receivers in SOI CMOS technology.

Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

PubMed

Sun, Min-Chul; Kim, Garam; Kim, Sang Wan; Kim, Hyun Woo; Kim, Hyungjin; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook

2012-07-01

In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

Single halo SDODEL n-MOSFET: an alternative low-cost pseudo-SOI with better analog performance

NASA Astrophysics Data System (ADS)

Sarkar, Partha; Mallik, Abhijit; Sarkar, Chandan Kumar

2009-03-01

In this paper, with the help of extensive TCAD simulations, we investigate the analog performance of source/drain on depletion layer (SDODEL) MOSFETs with a single-halo (SH) implant near the source side of the channel. We use the SH implant in such a structure for the first time. The analog performance parameters in SH SDODEL MOSFETs are compared to those in SH MOSFETs as well as in SH SOI MOSFETs. In addition to reduced junction capacitance for the SH SDODEL structure as compared to that in bulk SH devices, it has been shown that such devices lead to improved performance and lower power dissipation for sub-100 nm CMOS technologies. Our results show that, in SH SDODEL MOSFETs, there is significant improvement in the intrinsic device performance for analog applications (such as device gain, gm/ID, etc) for the sub-100 nm technologies.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology.

PubMed

Malits, Maria; Nemirovsky, Yael

2017-07-29

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode's sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode's perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor's channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate "on-line" temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode's small area and perimeter causes a high 1/ f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing.

An accurate model for predicting high frequency noise of nanoscale NMOS SOI transistors

NASA Astrophysics Data System (ADS)

Shen, Yanfei; Cui, Jie; Mohammadi, Saeed

2017-05-01

A nonlinear and scalable model suitable for predicting high frequency noise of N-type Metal Oxide Semiconductor (NMOS) transistors is presented. The model is developed for a commercial 45 nm CMOS SOI technology and its accuracy is validated through comparison with measured performance of a microwave low noise amplifier. The model employs the virtual source nonlinear core and adds parasitic elements to accurately simulate the RF behavior of multi-finger NMOS transistors up to 40 GHz. For the first time, the traditional long-channel thermal noise model is supplemented with an injection noise model to accurately represent the noise behavior of these short-channel transistors up to 26 GHz. The developed model is simple and easy to extract, yet very accurate.

The operation of 0.35 μm partially depleted SOI CMOS technology in extreme environments

NASA Astrophysics Data System (ADS)

Li, Ying; Niu, Guofu; Cressler, John D.; Patel, Jagdish; Liu, S. T.; Reed, Robert A.; Mojarradi, Mohammad M.; Blalock, Benjamin J.

2003-06-01

We evaluate the usefulness of partially depleted SOI CMOS devices fabricated in a 0.35 μm technology on UNIBOND material for electronics applications requiring robust operation under extreme environment conditions consisting of low and/or high temperature, and under substantial radiation exposure. The threshold voltage, effective mobility, and the impact ionization parameters were determined across temperature for both the nFETs and the pFETs. The radiation response was characterized using threshold voltage shifts of both the front-gate and back-gate transistors. These results suggest that this 0.35 μm partially depleted SOI CMOS technology is suitable for operation across a wide range of extreme environment conditions consisting of: cryogenic temperatures down to 86 K, elevated temperatures up to 573 K, and under radiation exposure to 1.3 Mrad(Si) total dose.

Nanometric Integrated Temperature and Thermal Sensors in CMOS-SOI Technology

PubMed Central

Malits, Maria; Nemirovsky, Yael

2017-01-01

This paper reviews and compares the thermal and noise characterization of CMOS (complementary metal-oxide-semiconductor) SOI (Silicon on insulator) transistors and lateral diodes used as temperature and thermal sensors. DC analysis of the measured sensors and the experimental results in a broad (300 K up to 550 K) temperature range are presented. It is shown that both sensors require small chip area, have low power consumption, and exhibit linearity and high sensitivity over the entire temperature range. However, the diode’s sensitivity to temperature variations in CMOS-SOI technology is highly dependent on the diode’s perimeter; hence, a careful calibration for each fabrication process is needed. In contrast, the short thermal time constant of the electrons in the transistor’s channel enables measuring the instantaneous heating of the channel and to determine the local true temperature of the transistor. This allows accurate “on-line” temperature sensing while no additional calibration is needed. In addition, the noise measurements indicate that the diode’s small area and perimeter causes a high 1/f noise in all measured bias currents. This is a severe drawback for the sensor accuracy when using the sensor as a thermal sensor; hence, CMOS-SOI transistors are a better choice for temperature sensing. PMID:28758932

EDMOS in ultrathin FDSOI: Impact of the drift region properties

NASA Astrophysics Data System (ADS)

Litty, Antoine; Ortolland, Sylvie; Golanski, Dominique; Dutto, Christian; Cristoloveanu, Sorin

2016-11-01

The development of high-voltage MOSFET (HVMOS) is necessary for including power management or radiofrequency functionalities in CMOS technology. In this paper, we investigate the fabrication and optimization of an Extended Drain MOSFET (EDMOS) directly integrated in the ultra-thin SOI film (7 nm) of the 28 nm FDSOI CMOS technology node. Thanks to TCAD simulations, we analyse in detail the device behaviour as a function of the doping level and length of the drift region. The influence of the back-plane doping type and of the back-biasing schemes is discussed. DC measurements of fabricated EDMOS samples reveal promising performances in particular in terms of specific on-resistance versus breakdown voltage trade-off. The experimental results indicate that, even in an ultrathin film, the engineering of the drift region could be a lever to obtain integrated HVMOS (3.3-5 V).

Characterization of pixel sensor designed in 180 nm SOI CMOS technology

NASA Astrophysics Data System (ADS)

Benka, T.; Havranek, M.; Hejtmanek, M.; Jakovenko, J.; Janoska, Z.; Marcisovska, M.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

2018-01-01

A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET.

PubMed

Dutta, Sangya; Kumar, Vinay; Shukla, Aditya; Mohapatra, Nihar R; Ganguly, Udayan

2017-08-15

Neuro-biology inspired Spiking Neural Network (SNN) enables efficient learning and recognition tasks. To achieve a large scale network akin to biology, a power and area efficient electronic neuron is essential. Earlier, we had demonstrated an LIF neuron by a novel 4-terminal impact ionization based n+/p/n+ with an extended gate (gated-INPN) device by physics simulation. Excellent improvement in area and power compared to conventional analog circuit implementations was observed. In this paper, we propose and experimentally demonstrate a compact conventional 3-terminal partially depleted (PD) SOI- MOSFET (100 nm gate length) to replace the 4-terminal gated-INPN device. Impact ionization (II) induced floating body effect in SOI-MOSFET is used to capture LIF neuron behavior to demonstrate spiking frequency dependence on input. MHz operation enables attractive hardware acceleration compared to biology. Overall, conventional PD-SOI-CMOS technology enables very-large-scale-integration (VLSI) which is essential for biology scale (~10 11 neuron based) large neural networks.

High responsivity CMOS imager pixel implemented in SOI technology

NASA Technical Reports Server (NTRS)

Zheng, X.; Wrigley, C.; Yang, G.; Pain, B.

2000-01-01

Availability of mature sub-micron CMOS technology and the advent of the new low noise active pixel sensor (APS) concept have enabled the development of low power, miniature, single-chip, CMOS digital imagers in the decade of the 1990's.

Recent Design Development in Molecular Imaging for Breast Cancer Detection Using Nanometer CMOS Based Sensors.

PubMed

Nguyen, Dung C; Ma, Dongsheng Brian; Roveda, Janet M W

2012-01-01

As one of the key clinical imaging methods, the computed X-ray tomography can be further improved using new nanometer CMOS sensors. This will enhance the current technique's ability in terms of cancer detection size, position, and detection accuracy on the anatomical structures. The current paper reviewed designs of SOI-based CMOS sensors and their architectural design in mammography systems. Based on the existing experimental results, using the SOI technology can provide a low-noise (SNR around 87.8 db) and high-gain (30 v/v) CMOS imager. It is also expected that, together with the fast data acquisition designs, the new type of imagers may play important roles in the near-future high-dimensional images in additional to today's 2D imagers.

Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

NASA Astrophysics Data System (ADS)

Jain, Neeraj; Raj, Balwinder

2017-12-01

Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects (SCEs), leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs), because of its more effective gate-controlling capabilities. In this paper, our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope (SS), ON current (I on), OFF current (I off) and I on/I off ratio. The potential benefits of SOI FinFET at drain-to-source voltage, V DS = 0.05 V and V DS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (A V), output conductance (g d), trans-conductance (g m), gate capacitance (C gg), and cut-off frequency (f T = g m/2πC gg) with spacer region variations.

Novel Si-Ge-C Superlattices for More than Moore CMOS

DTIC Science & Technology

2016-03-31

diodes can be entirely formed by epitaxial growth, CMOS Active Pixel Sensors can be made with Fully-Depleted SOI CMOS . One important advantage of...a NMOS Transfer Gate (TG), which could be part of a 4T pixel APS. PPDs are preferred in CMOS image sensors for the ability of the pinning layer to...than Moore” with the creation of active photonic devices monolithically integrated with CMOS . Applications include Multispectral CMOS Image Sensors

Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

PubMed

Malits, Maria; Brouk, Igor; Nemirovsky, Yael

2018-05-19

This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.

1998-06-01

Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC.

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

NASA Astrophysics Data System (ADS)

Jovanović, B.; Brum, R. M.; Torres, L.

2014-04-01

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

PubMed

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

PubMed Central

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-01-01

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

SOI CMOS Imager with Suppression of Cross-Talk

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Zheng, Xingyu; Cunningham, Thomas J.; Seshadri, Suresh; Sun, Chao

2009-01-01

A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

CMOS Image Sensor Using SOI-MOS/Photodiode Composite Photodetector Device

NASA Astrophysics Data System (ADS)

Uryu, Yuko; Asano, Tanemasa

2002-04-01

A new photodetector device composed of a lateral junction photodiode and a metal-oxide-semiconductor field-effect-transistor (MOSFET), in which the output of the diode is fed through the body of the MOSFET, has been investigated. It is shown that the silicon-on-insulator (SOI)-MOSFET amplifies the junction photodiode current due to the lateral bipolar action. It is also shown that the presence of the electrically floating gate enhances the current amplification factor of the SOI-MOSFET. The output current of this composite device linearly responds by four orders of illumination intensity. As an application of the composite device, a complementary-metal-oxide-semiconductor (CMOS) line sensor incorporating the composite device is fabricated and its operation is demonstrated. The output signal of the line sensor using the composite device was two times larger than that using the lateral photodiode.

Ultra-low power high temperature and radiation hard complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) voltage reference.

PubMed

Boufouss, El Hafed; Francis, Laurent A; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

2013-12-13

This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of -40-200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V(REF) depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V(REF) and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

2006-01-01

SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.

Athermal and wavelength-trimmable photonic filters based on TiO₂-cladded amorphous-SOI.

PubMed

Lipka, Timo; Moldenhauer, Lennart; Müller, Jörg; Trieu, Hoc Khiem

2015-07-27

Large-scale integrated silicon photonic circuits suffer from two inevitable issues that boost the overall power consumption. First, fabrication imperfections even on sub-nm scale result in spectral device non-uniformity that require fine-tuning during device operation. Second, the photonic devices need to be actively corrected to compensate thermal drifts. As a result significant amount of power is wasted if no athermal and wavelength-trimmable solutions are utilized. Consequently, in order to minimize the total power requirement of photonic circuits in a passive way, trimming methods are required to correct the device inhomogeneities from manufacturing and athermal solutions are essential to oppose temperature fluctuations of the passive/active components during run-time. We present an approach to fabricate CMOS backend-compatible and athermal passive photonic filters that can be corrected for fabrication inhomogeneities by UV-trimming based on low-loss amorphous-SOI waveguides with TiO2 cladding. The trimming of highly confined 10 μm ring resonators is proven over a free spectral range retaining athermal operation. The athermal functionality of 2nd-order 5 μm add/drop microrings is demonstrated over 40°C covering a broad wavelength interval of 60 nm.

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

NASA Astrophysics Data System (ADS)

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Characterization of silicon-on-insulator wafers

NASA Astrophysics Data System (ADS)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Monolithic optical phased-array transceiver in a standard SOI CMOS process.

PubMed

Abediasl, Hooman; Hashemi, Hossein

2015-03-09

Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 × 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system.

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

2006-01-01

Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

Preface to the special issue of Solid State Electronics EUROSOI/ULIS 2017

NASA Astrophysics Data System (ADS)

Nassiopoulou, Androula G.

2018-05-01

This special issue is devoted to selected papers presented at the EuroSOI-ULIS2017 international conference, held in Athens on 3-5 April 2017. EuroSOI-ULIS2017 Conference was mainly devoted to Si devices, which constitute the basic building blocks of any microelectronic circuit. It included papers on advanced Si technologies, novel nanoscale devices, advanced electronic materials and device architectures, mechanisms involved, test structures, substrate materials and technologies, modeling/simulation and characterization. Both CMOS and beyond CMOS devices were presented, covering the More Moore domain, as well as new functionalities in silicon-compatible nanostructures and innovative devices, representing the More than Moore domain (on-chip sensors, biosensors, energy harvesting devices, RF passives, etc.).

The design of radiation-hardened ICs for space - A compendium of approaches

NASA Technical Reports Server (NTRS)

Kerns, Sherra E.; Shafer, B. D; Rockett, L. R., Jr.; Pridmore, J. S.; Berndt, D. F.

1988-01-01

Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ISs.

Silicon-on-insulator with hybrid orientations for heterogeneous integration of GaN on Si (100) substrate

NASA Astrophysics Data System (ADS)

Zhang, Runchun; Zhao, Beiji; Huang, Kai; You, Tiangui; Jia, Qi; Lin, Jiajie; Zhang, Shibin; Yan, Youquan; Yi, Ailun; Zhou, Min; Ou, Xin

2018-05-01

Heterogeneous integration of materials pave a new way for the development of the microsystem with miniaturization and complex functionalities. Two types of hybrid silicon on insulator (SOI) structures, i.e., Si (100)-on-Si (111) and Si (111)-on-Si (100), were prepared by the smart-cut technique, which is consist of ion-slicing and wafer bonding. The precise calculation of the lattice strain of the transferred films without the epitaxial matching relationship to the substrate was demonstrated based on X-ray diffraction (XRD) measurements. The XRD and Raman measurement results suggest that the transferred films possess single crystalline quality. With a chemical mechanical polishing (CMP) process, the surface roughness of the transferred thin films can be reduced from 5.57 nm to 0.30 nm. The 4-inch GaN thin film epitaxially grown on the as-prepared hybrid SOI of Si (111)-on-Si (100) by metalorganic chemical vapor deposition (MOCVD) is of improved quality with a full width at half maximum (FWHM) of 672.54 arcsec extracted from the XRD rocking curve and small surface roughness of 0.40 nm. The wafer-scale GaN on Si (111)-on-Si (100) can serve as a potential platform for the one chip integration of GaN-based high electron mobility transistors (HEMT) or photonics with the Si (100)-based complementary metal oxide semiconductor (CMOS).

SOI MESFETs on high-resistivity, trap-rich substrates

NASA Astrophysics Data System (ADS)

Mehr, Payam; Zhang, Xiong; Lepkowski, William; Li, Chaojiang; Thornton, Trevor J.

2018-04-01

The DC and RF characteristics of metal-semiconductor field-effect-transistors (MESFETs) on conventional CMOS silicon-on-insulator (SOI) substrates are compared to nominally identical devices on high-resistivity, trap-rich SOI substrates. While the DC transfer characteristics are statistically identical on either substrate, the maximum available gain at GHz frequencies is enhanced by ∼2 dB when using the trap-rich substrates, with maximum operating frequencies, fmax, that are approximately 5-10% higher. The increased fmax is explained by the reduced substrate conduction at GHz frequencies using a lumped-element, small-signal model.

Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

NASA Astrophysics Data System (ADS)

Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

2018-02-01

In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

High-speed Si/GeSi hetero-structure Electro Absorption Modulator.

PubMed

Mastronardi, L; Banakar, M; Khokhar, A Z; Hattasan, N; Rutirawut, T; Bucio, T Domínguez; Grabska, K M; Littlejohns, C; Bazin, A; Mashanovich, G; Gardes, F Y

2018-03-19

The ever-increasing demand for integrated, low power interconnect systems is pushing the bandwidth density of CMOS photonic devices. Taking advantage of the strong Franz-Keldysh effect in the C and L communication bands, electro-absorption modulators in Ge and GeSi are setting a new standard in terms of device footprint and power consumption for next generation photonics interconnect arrays. In this paper, we present a compact, low power electro-absorption modulator (EAM) Si/GeSi hetero-structure based on an 800 nm SOI overlayer with a modulation bandwidth of 56 GHz. The device design and fabrication tolerant process are presented, followed by the measurement analysis. Eye diagram measurements show a dynamic ER of 5.2 dB at a data rate of 56 Gb/s at 1566 nm, and calculated modulator power is 44 fJ/bit.

Nano-Multiplication-Region Avalanche Photodiodes and Arrays

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata; Cunningham, Thomas

2008-01-01

Nano-multiplication-region avalanche photodiodes (NAPDs), and imaging arrays of NAPDs integrated with complementary metal oxide/semiconductor (CMOS) active-pixel-sensor integrated circuitry, are being developed for applications in which there are requirements for high-sensitivity (including photoncounting) detection and imaging at wavelengths from about 250 to 950 nm. With respect to sensitivity and to such other characteristics as speed, geometric array format, radiation hardness, power demand of associated circuitry, size, weight, and robustness, NAPDs and arrays thereof are expected to be superior to prior photodetectors and arrays including CMOS active-pixel sensors (APSs), charge-coupled devices (CCDs), traditional APDs, and microchannelplate/ CCD combinations. Figure 1 depicts a conceptual NAPD array, integrated with APS circuitry, fabricated on a thick silicon-on-insulator wafer (SOI). Figure 2 presents selected aspects of the structure of a typical single pixel, which would include a metal oxide/semiconductor field-effect transistor (MOSFET) integrated with the NAPD. The NAPDs would reside in silicon islands formed on the buried oxide (BOX) layer of the SOI wafer. The silicon islands would be surrounded by oxide-filled insulation trenches, which, together with the BOX layer, would constitute an oxide embedding structure. There would be two kinds of silicon islands: NAPD islands for the NAPDs and MOSFET islands for in-pixel and global CMOS circuits. Typically, the silicon islands would be made between 5 and 10 m thick, but, if necessary, the thickness could be chosen outside this range. The side walls of the silicon islands would be heavily doped with electron-acceptor impurities (p+-doped) to form anodes for the photodiodes and guard layers for the MOSFETs. A nanoscale reach-through structure at the front (top in the figures) central position of each NAPD island would contain the APD multiplication region. Typically, the reach-through structure would be about 0.1 microns in diameter and between 0.3 and 0.4 nm high. The top layer in the reach-through structure would be heavily doped with electron-donor impurities (n+-doped) to make it act as a cathode. A layer beneath the cathode, between 0.1 and 0.2 nm thick, would be p-doped to a concentration .10(exp 17)cu cm. A thin n+-doped polysilicon pad would be formed on the top of the cathode to protect the cathode against erosion during a metal-silicon alloying step that would be part of the process of fabricating the array.

Buried Oxide Densification for Low Power, Low Voltage CMOS Applications

NASA Technical Reports Server (NTRS)

Allen, L. P.; Anc, M. J.; Dolan, B.; Jiao, J.; Guss, B.; Seraphin, S.; Liu, S. T.; Jenkins, W.

1998-01-01

Special technology and circuit architecture are of growing interest for implementation of circuits which operate at low supply voltages and consume low power levels without sacrificing performance[1]. Use of thin buried oxide SOI substrates is a primary approach to simultaneously achieve these goals. A significant aspect regarding SIMOX SOI for low voltage, low power applications is the reliability and performance of the thin buried oxide. In addition, when subjected to high total dose irradiation, the silicon islands within the BOX layer of SIMOX can store charges and significantly effect the back channel threshold voltages of devices. Thus, elimination of the islands within the buried oxide (BOX) layer is preferred in order to prevent leakage through these conductive islands and charge build-up within the buried oxide layer. A differential (2-step) ramp rate as applied to full and 100 nm BOX SIMOX was previously reported to play a significant role in the stoichiometry and island formation within the buried layer[2]. This paper focus is on the properties of a thin (120nm) buried oxide as a function of the anneal ramp rate and the temperature of anneal. In this research, we have found an improvement in the buried oxide stoichiometry with the use of a slower, singular ramp rate for specified thin buried oxides, with slower ramp rates and higher temperatures of anneal suggested for reducing the presence of Si islands within the BOX layer.

Fundamental performance differences between CMOS and CCD imagers: part III

NASA Astrophysics Data System (ADS)

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Cheng, John; Bishop, Jeanne

2009-08-01

This paper is a status report on recent scientific CMOS imager developments since when previous publications were written. Focus today is being given on CMOS design and process optimization because fundamental problems affecting performance are now reasonably well understood. Topics found in this paper include discussions on a low cost custom scientific CMOS fabrication approach, substrate bias for deep depletion imagers, near IR and x-ray point-spread performance, custom fabricated high resisitivity epitaxial and SOI silicon wafers for backside illuminated imagers, buried channel MOSFETs for ultra low noise performance, 1 e- charge transfer imagers, high speed transfer pixels, RTS/ flicker noise versus MOSFET geometry, pixel offset and gain non uniformity measurements, high S/N dCDS/aCDS signal processors, pixel thermal dark current sources, radiation damage topics, CCDs fabricated in CMOS and future large CMOS imagers planned at Sarnoff.

A novel high-performance high-frequency SOI MESFET by the damped electric field

NASA Astrophysics Data System (ADS)

Orouji, Ali A.; Khayatian, Ahmad; Keshavarzi, Parviz

2016-06-01

In this paper, we introduce a novel silicon-on-insulator (SOI) metal-semiconductor field-effect-transistor (MESFET) using the damped electric field (DEF). The proposed structure is geometrically symmetric and compatible with common SOI CMOS fabrication processes. It has two additional oxide regions under the side gates in order to improve DC and RF characteristics of the DEF structure due to changes in the electrical potential, the electrical field distributions, and rearrangement of the charge carriers. Improvement of device performance is investigated by two-dimensional and two-carrier simulation of fundamental parameters such as breakdown voltage (VBR), drain current (ID), output power density (Pmax), transconductance (gm), gate-drain and gate-source capacitances, cut-off frequency (fT), unilateral power gain (U), current gain (h21), maximum available gain (MAG), and minimum noise figure (Fmin). The results show that proposed structure operates with higher performances in comparison with the similar conventional SOI structure.

Strong room temperature electroluminescence from lateral p-SiGe/i-Ge/n-SiGe heterojunction diodes on silicon-on-insulator substrate

NASA Astrophysics Data System (ADS)

Lin, Guangyang; Yi, Xiaohui; Li, Cheng; Chen, Ningli; Zhang, Lu; Chen, Songyan; Huang, Wei; Wang, Jianyuan; Xiong, Xihuan; Sun, Jiaming

2016-10-01

A lateral p-Si0.05Ge0.95/i-Ge/n-Si0.05Ge0.95 heterojunction light emitting diode on a silicon-on-insulator (SOI) substrate was proposed, which is profitable to achieve higher luminous extraction compared to vertical junctions. Due to the high carrier injection ratio of heterostructures and optical reflection at the SiO2/Si interface of the SOI, strong room temperature electroluminescence (EL) at around 1600 nm from the direct bandgap of i-Ge with 0.30% tensile strain was observed. The EL peak intensity of the lateral heterojunction is enhanced by ˜4 folds with a larger peak energy than that of the vertical Ge p-i-n homojunction, suggesting that the light emitting efficiency of the lateral heterojunction is effectively improved. The EL peak intensity of the lateral heterojunction, which increases quadratically with injection current density, becomes stronger for diodes with a wider i-Ge region. The CMOS compatible fabrication process of the lateral heterojunctions paves the way for the integration of the light source with the Ge metal-oxide-semiconductor field-effect-transistor.

High Efficiency mm-Wave Transmitter Array

DTIC Science & Technology

2016-09-01

SECURITY CLASSIFICATION OF: High efficiency, high power transmitters integrated in silicon at 45, 94 and 138 GHz were developed. Our approach...employs CMOS-SOI and SiGe HBT unit amplifiers, power -combined in free-space using antenna arrays to attain high power levels. In the baseline approach...the-art were made. At 45GHz, a single CMOS chip produced an RF power of 630mW, which yielded an EIRP of 1. REPORT DATE (DD-MM-YYYY) 4. TITLE AND

InP on SOI devices for optical communication and optical network on chip

NASA Astrophysics Data System (ADS)

Fedeli, J.-M.; Ben Bakir, B.; Olivier, N.; Grosse, Ph.; Grenouillet, L.; Augendre, E.; Phillippe, P.; Gilbert, K.; Bordel, D.; Harduin, J.

2011-01-01

For about ten years, we have been developing InP on Si devices under different projects focusing first on μlasers then on semicompact lasers. For aiming the integration on a CMOS circuit and for thermal issue, we relied on SiO2 direct bonding of InP unpatterned materials. After the chemical removal of the InP substrate, the heterostructures lie on top of silicon waveguides of an SOI wafer with a separation of about 100nm. Different lasers or photodetectors have been achieved for off-chip optical communication and for intra-chip optical communication within an optical network. For high performance computing with high speed communication between cores, we developed InP microdisk lasers that are coupled to silicon waveguide and produced 100μW of optical power and that can be directly modulated up to 5G at different wavelengths. The optical network is based on wavelength selective circuits with ring resonators. InGaAs photodetectors are evanescently coupled to the silicon waveguide with an efficiency of 0.8A/W. The fabrication has been demonstrated at 200mm wafer scale in a microelectronics clean room for CMOS compatibility. For off-chip communication, silicon on InP evanescent laser have been realized with an innovative design where the cavity is defined in silicon and the gain localized in the QW of bonded InP hererostructure. The investigated devices operate at continuous wave regime with room temperature threshold current below 100 mA, the side mode suppression ratio is as high as 20dB, and the fibercoupled output power is {7mW. Direct modulation can be achieved with already 6G operation.

Tunnel FinFET CMOS inverter with very low short-circuit current for ultralow-power Internet of Things application

NASA Astrophysics Data System (ADS)

Morita, Yukinori; Fukuda, Koichi; Liu, Yongxun; Mori, Takahiro; Mizubayashi, Wataru; O'uchi, Shin-ichi; Fuketa, Hiroshi; Otsuka, Shintaro; Migita, Shinji; Masahara, Meishoku; Endo, Kazuhiko; Ota, Hiroyuki; Matsukawa, Takashi

2017-04-01

We have demonstrated the operation of a CMOS inverter consisting of Si tunnel FinFETs. Both p- and n-type tunnel FinFETs are successfully fabricated and operated on the same SOI wafer. The current mismatch between p- and n-type tunnel FETs is compensated by tuning the number of fin channels. Very low short-circuit current and clear voltage input-output characteristics are obtained. The thin epitaxial channel in the tunnel FinFETs effectively increases the drain current and accordingly reduces the drain capacitance, which could help high-performance tunnel FET CMOS inverter operation.

Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

NASA Technical Reports Server (NTRS)

Pellish, Jonathan A.; Marshall, Paul W.; Rodbell, Kenneth P.; Gordon, Michael S.; LaBel, Kenneth A.; Schwank, James R.; Dodds, Nathaniel A.; Castaneda, Carlos M.; Berg, Melanie D.; Kim, Hak S.;

Ultra-low loss fully-etched grating couplers for perfectly vertical coupling compatible with DUV lithography tools

NASA Astrophysics Data System (ADS)

Dabos, G.; Pleros, N.; Tsiokos, D.

2016-03-01

Hybrid integration of VCSELs onto silicon-on-insulator (SOI) substrates has emerged as an attractive approach for bridging the gap between cost-effective and energy-efficient directly modulated laser sources and silicon-based PICs by leveraging flip-chip (FC) bonding techniques and silicon grating couplers (GCs). In this context, silicon GCs, should comply with the process requirements imposed by the complimentary-metal-oxide-semiconductor manufacturing tools addressing in parallel the challenges originating from the perfectly vertical incidence. Firstly, fully etched GCs compatible with deep-ultraviolet lithography tools offering high coupling efficiencies are imperatively needed to maintain low fabrication cost. Secondly, GC's tolerance to VCSEL bonding misalignment errors is a prerequisite for practical deployment. Finally, a major challenge originating from the perfectly vertical coupling scheme is the minimization of the direct back-reflection to the VCSEL's outgoing facet which may destabilize its operation. Motivated from the above challenges, we used numerical simulation tools to design an ultra-low loss, bidirectional VCSEL-to-SOI optical coupling scheme for either TE or TM polarization, based on low-cost fully etched GCs with a Si-layer of 340 nm without employing bottom reflectors or optimizing the buried-oxide layer. Comprehensive 2D Finite-Difference-Time- Domain simulations have been performed. The reported GC layout remains fully compatible with the back-end-of-line (BEOL) stack associated with the 3D integration technology exploiting all the inter-metal-dielectric (IMD) layers of the CMOS fab. Simulation results predicted for the first time in fully etched structures a coupling efficiency of as low as -0.87 dB at 1548 nm and -1.47 dB at 1560 nm with a minimum direct back-reflection of -27.4 dB and -14.2 dB for TE and TM polarization, respectively.

Biodiesel sensing using silicon-on-insulator technologies

NASA Astrophysics Data System (ADS)

Casas Bedoya, Alvaro; Ling, Meng Y.; Brouckaert, Joost; Yebo, Nebiyu A.; Van Thourhout, Dries; Baets, Roel G.

2009-05-01

By measuring the transmission of Biodiesel/Diesel mixtures in the near- and far-infrared wavelength ranges, it is possible to predict the blend level with a high accuracy. Conventional photospectrometers are typically large and expensive and have a performance that often exceeds the requirements for most applications. For automotive applications for example, what counts is size, robustness and most important cost. As a result the miniaturization of the spectrometer can be seen as an attractive implementation of a Biodiesel sensor. Using Silicon-on-Insulator (SOI) this spectrometer miniaturization can be achieved. Due to the large refractive index contrast of the SOI material system, photonic devices can be made very compact. Moreover, they can be manufactured on high-quality SOI substrates using waferscale CMOS fabrication tools, making them cheap for the market. In this paper, we show that it is possible to determine Biodiesel blend levels using an SOI spectrometer-on-a-chip. We demonstrate absorption measurements using spiral shaped waveguides and we also present the spectrometer design for on-chip Biodiesel blend level measurements.

Fabrication of ultrathin and highly uniform silicon on insulator by numerically controlled plasma chemical vaporization machining.

PubMed

Sano, Yasuhisa; Yamamura, Kazuya; Mimura, Hidekazu; Yamauchi, Kazuto; Mori, Yuzo

2007-08-01

Metal-oxide semiconductor field-effect transistors fabricated on a silicon-on-insulator (SOI) wafer operate faster and at a lower power than those fabricated on a bulk silicon wafer. Scaling down, which improves their performances, demands thinner SOI wafers. In this article, improvement on the thinning of SOI wafers by numerically controlled plasma chemical vaporization machining (PCVM) is described. PCVM is a gas-phase chemical etching method in which reactive species generated in atmospheric-pressure plasma are used. Some factors affecting uniformity are investigated and methods for improvements are presented. As a result of thinning a commercial 8 in. SOI wafer, the initial SOI layer thickness of 97.5+/-4.7 nm was successfully thinned and made uniform at 7.5+/-1.5 nm.

Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory

NASA Astrophysics Data System (ADS)

Miyaji, Kousuke; Hung, Chinglin; Takeuchi, Ken

2012-04-01

The scaling trends and limitation in sub-20 nm a bulk and silicon-on-insulator (SOI) NAND flash memory is studied by the three-dimensional (3D) device simulation focusing on short channel effects (SCE), channel boost leakage and channel voltage boosting characteristics during the program-inhibit operation. Although increasing punch-through stopper doping concentration is effective for suppressing SCE in bulk NAND cells, the generation of junction leakage becomes serious. On the other hand, SCE can be suppressed by thinning the buried oxide (BOX) in SOI NAND cells. However, the boosted channel voltage decreases by the higher BOX capacitance. It is concluded that the scaling limitation is dominated by the junction leakage and channel boosting capability for bulk and SOI NAND flash cells, respectively, and the scaling limit is decreased to 9 nm using SOI NAND flash memory cells from 13 nm in bulk NAND flash memory cells.

Analysis and optimisation of lateral thin-film silicon-on-insulator (SOI) PMOS transistor with an NBL layer in the drift region

NASA Astrophysics Data System (ADS)

Cortés, I.; Toulon, G.; Morancho, F.; Flores, D.; Hugonnard-Bruyère, E.; Villard, B.

2012-04-01

This paper analyses the experimental results of voltage capability (VBR > 120 V) and output characteristics of a new lateral power P-channel MOS transistors manufactured on a 0.18 μm SOI CMOS technology by means of TCAD numerical simulations. The proposed LDPMOS structures have an N-type buried layer (NBL) inserted in the P-well drift region with the purpose of increasing the RESURF effectiveness and improving the static characteristics (Ron-sp/VBR trade-off) and the device switching performance. Some architecture modifications are also proposed in this paper to further improve the performance of fabricated transistors.

300 nm bandwidth adiabatic SOI polarization splitter-rotators exploiting continuous symmetry breaking.

PubMed

Socci, Luciano; Sorianello, Vito; Romagnoli, Marco

2015-07-27

Adiabatic polarization splitter-rotators are investigated exploiting continuous symmetry breaking thereby achieving significant device size and losses reduction in a single mask fabrication process for both SOI channel and ridge waveguides. A crosstalk lower than -25 dB is expected over 300nm bandwidth, making the device suitable for full grid CWDM and diplexer/triplexer FTTH applications at 1310, 1490 and 1550nm.

Effects of patterning induced stress relaxation in strained SOI/SiGe layers and substrate

NASA Astrophysics Data System (ADS)

Hermann, P.; Hecker, M.; Renn, F.; Rölke, M.; Kolanek, K.; Rinderknecht, J.; Eng, L. M.

2011-06-01

Local stress fields in strained silicon structures important for CMOS technology are essentially related to size effects and properties of involved materials. In the present investigation, Raman spectroscopy was utilized to analyze the stress distribution within strained silicon (sSi) and silicon-germanium (SiGe) island structures. As a result of the structuring of initially unpatterned strained films, a size-dependent relaxation of the intrinsic film stresses was obtained in agreement with model calculations. This changed stress state in the features also results in the appearance of opposing stresses in the substrate underneath the islands. Even for strained island structures on top of silicon-on-insulator (SOI) wafers, corresponding stresses in the silicon substrate underneath the oxide were detected. Within structures, the stress relaxation is more pronounced for islands on SOI substrates as compared to those on bulk silicon substrates.

Meniscus-force-mediated layer transfer technique using single-crystalline silicon films with midair cavity: Application to fabrication of CMOS transistors on plastic substrates

NASA Astrophysics Data System (ADS)

Sakaike, Kohei; Akazawa, Muneki; Nakagawa, Akitoshi; Higashi, Seiichiro

2015-04-01

A novel low-temperature technique for transferring a silicon-on-insulator (SOI) layer with a midair cavity (supported by narrow SiO2 columns) by meniscus force has been proposed, and a single-crystalline Si (c-Si) film with a midair cavity formed in dog-bone shape was successfully transferred to a poly(ethylene terephthalate) (PET) substrate at its heatproof temperature or lower. By applying this proposed transfer technique, high-performance c-Si-based complementary metal-oxide-semiconductor (CMOS) transistors were successfully fabricated on the PET substrate. The key processes are the thermal oxidation and subsequent hydrogen annealing of the SOI layer on the midair cavity. These processes ensure a good MOS interface, and the SiO2 layer works as a “blocking” layer that blocks contamination from PET. The fabricated n- and p-channel c-Si thin-film transistors (TFTs) on the PET substrate showed field-effect mobilities of 568 and 103 cm2 V-1 s-1, respectively.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

NASA Astrophysics Data System (ADS)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Noise performance of 0.35-(mu)m SOI CMOS devices and micropower preamplifier following 63-MeV, 1-Mrad (Si) proton irradiation

NASA Technical Reports Server (NTRS)

Binkley, D. M.; Hopper, C. E.; Cressler, J. D.; Mojarradi, M. M.; Blalock, B. J.

2004-01-01

This paper presents measured noise for 0.35(mu)m, silicon-on-insulator devices and a micropower preamplifier following 63-MeV, 1-Mrad (Si) proton irradiation. Flicker noise voltage, important for gyros having low frequency output, increases less than 32% after irradiation.

A proposal for digital electro-optic switches with free-carrier dispersion effect and Goos-Hanchen shift in silicon-on-insulator waveguide corner mirror

NASA Astrophysics Data System (ADS)

Sun, DeGui

2013-09-01

In a silicon-on-insulator (SOI) waveguide corner mirror (WCM) structure, with the quantum process of a frustrated total internal reflection (FTIR) phenomenon and the time delay principle in the two-dimensional potential barrier tunneling process of a mass of particles, we derive an accurate physical model for the Goos-Hanchen (GH) shift of optical guided-mode in the FTIR process, and in principle match the GH shift jumping states with the independent guided-modes. Then, we propose and demonstrate a new regime of 1 × N digital optical switches with a matching state between the free-carrier dispersion (FCD) based refractive index modulation (RIM) of silicon to create a GH shift jumping function of a photonic signal at the reflecting interface and the independent guided-modes in the FTIR process, where a MOS-capacitor type electro-optic modulation regime is proposed and discussed to realize an effective FCD-based RIM. At the critical matching state, i.e., the incident of an optical beam is at the vicinity of Brewster angle in the WCM, a mini-change of refractive index of waveguide material can cause a great jump of GH shift along the FTIR reflecting interface, and further a 1 × N digital optical switching process could be realized. For a 350-500 nm single-mode rib waveguide made on the 220 nm CMOS-compatible SOI substrate and with the FCD effect based RIM of silicon crystal, a concentration variation of 1018-1019 cm-3 has caused a 0.5-2.5 μm GH shift of reflected beam, which is at 2-5 times of a mode-size and hence radically convinces an optical switching function with a 1 × 3-1 × 10 scale.

Total Ionizing Dose Influence on the Single-Event Upset Sensitivity of 130-nm PD SOI SRAMs

NASA Astrophysics Data System (ADS)

Zheng, Qiwen; Cui, Jiangwei; Liu, Mengxin; Zhou, Hang; Liu, Mohan; Wei, Ying; Su, Dandan; Ma, Teng; Lu, Wu; Yu, Xuefeng; Guo, Qi; He, Chengfa

2017-07-01

Effect of total ionizing dose (TID) on single-event upset (SEU) hardness of 130 nm partially depleted (PD) silicon-on-insulator (SOI) static random access memories (SRAMs) is investigated in this paper. The measurable synergistic effect of TID on SEU sensitivity of 130-nm PD SOI SRAM was observed in our experiment, even though that is far less than micrometer and submicrometer devices. Moreover, SEU cross section after TID irradiation has no dependence on the data pattern that was applied during TID exposure: SEU cross sections are characterized by TID data pattern and its complement data pattern are decreased consistently rather than a preferred state and a nonpreferred state as micrometer and sub-micrometer SRAMs. The memory cell test structure allowing direct measurement of static noise margin (SNM) under standby operation was designed using identical memory cell layout of SRAM. Direct measurement of the memory cell SNM shows that both data sides' SNM is decreased by TID, indicating that SEU cross section of 130-nm PD SOI SRAM will be increased by TID. And, the decreased SNM is caused by threshold shift in memory cell transistors induced by “radiation-induced narrow channel effect”.

Photonic bandpass filter characteristics of multimode SOI waveguides integrated with submicron gratings.

PubMed

Sah, Parimal; Das, Bijoy Krishna

2018-03-20

It has been shown that a fundamental mode adiabatically launched into a multimode SOI waveguide with submicron grating offers well-defined flat-top bandpass filter characteristics in transmission. The transmitted spectral bandwidth is controlled by adjusting both waveguide and grating design parameters. The bandwidth is further narrowed down by cascading two gratings with detuned parameters. A semi-analytical model is used to analyze the filter characteristics (1500  nm≤λ≤1650  nm) of the device operating in transverse-electric polarization. The proposed devices were fabricated with an optimized set of design parameters in a SOI substrate with a device layer thickness of 250 nm. The pass bandwidth of waveguide devices integrated with single-stage gratings are measured to be ∼24  nm, whereas the device with two cascaded gratings with slightly detuned periods (ΔΛ=2  nm) exhibits a pass bandwidth down to ∼10  nm.

Ultra compact triplexing filters based on SOI nanowire AWGs

NASA Astrophysics Data System (ADS)

Jiashun, Zhang; Junming, An; Lei, Zhao; Shijiao, Song; Liangliang, Wang; Jianguang, Li; Hongjie, Wang; Yuanda, Wu; Xiongwei, Hu

2011-04-01

An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion.

Wide-Temperature-Range Integrated Operational Amplifier

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Levanas, Greg; Chen, Yuan; Kolawa, Elizabeth; Cozy, Raymond; Blalock, Benjamin; Greenwell, Robert; Terry, Stephen

2007-01-01

A document discusses a silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) integrated- circuit operational amplifier to be replicated and incorporated into sensor and actuator systems of Mars-explorer robots. This amplifier is designed to function at a supply potential less than or equal to 5.5 V, at any temperature from -180 to +120 C. The design is implemented on a commercial radiation-hard SOI CMOS process rated for a supply potential of less than or equal to 3.6 V and temperatures from -55 to +110 C. The design incorporates several innovations to achieve this, the main ones being the following: NMOS transistor channel lengths below 1 m are generally not used because research showed that this change could reduce the adverse effect of hot carrier injection on the lifetimes of transistors at low temperatures. To enable the amplifier to withstand the 5.5-V supply potential, a circuit topology including cascade devices, clamping devices, and dynamic voltage biasing was adopted so that no individual transistor would be exposed to more than 3.6 V. To minimize undesired variations in performance over the temperature range, the transistors in the amplifier are biased by circuitry that maintains a constant inversion coefficient over the temperature range.

Indium arsenide-on-SOI MOSFETs with extreme lattice mismatch

NASA Astrophysics Data System (ADS)

Wu, Bin

Both molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD) have been used to explore the growth of InAs on Si. Despite 11.6% lattice mismatch, planar InAs structures have been observed by scanning electron microscopy (SEM) when nucleating using MBE on patterned submicron Si-on-insulator (SOI) islands. Planar structures of size as large as 500 x 500 nm 2 and lines of width 200 nm and length a few microns have been observed. MOCVD growth of InAs also generates single grain structures on Si islands when the size is reduced to 100 x 100 nm2. By choosing SOI as the growth template, selective growth is enabled by MOCVD. Post-growth pattern-then-anneal process, in which MOCVD InAs is deposited onto unpatterned SOI followed with patterning and annealing of InAs-on-Si structure, is found to change the relative lattice parameters of encapsulated 17/5 nm InAs/Si island. Observed from transmission electron diffraction (TED) patterns, the lattice mismatch of 17/5 nm InAs/Si island reduces from 11.2 to 4.2% after being annealed at 800°C for 30 minutes. High-k Al2O3 dielectrics have been deposited by both electron-beam-enabled physical vapor deposition (PVD) and atomic layer deposition (ALD). Films from both techniques show leakage currents on the order of 10-9A/cm2, at ˜1 MV/cm electric field, breakdown field > ˜6 MV/cm, and dielectric constant > 6, comparable to those of reported ALD prior arts by Groner. The first MOSFETs with extreme lattice mismatch InAs-on-SOI channels using PVD Al2O3 as the gate dielectric are characterized. Channel recess was used to improve the gate control of the drain current.

Opportunities of CMOS-MEMS integration through LSI foundry and open facility

NASA Astrophysics Data System (ADS)

Mita, Yoshio; Lebrasseur, Eric; Okamoto, Yuki; Marty, Frédéfic; Setoguchi, Ryota; Yamada, Kentaro; Mori, Isao; Morishita, Satoshi; Imai, Yoshiaki; Hosaka, Kota; Hirakawa, Atsushi; Inoue, Shu; Kubota, Masanori; Denoual, Matthieu

2017-06-01

Since the 2000s, several countries have established micro- and nanofabrication platforms for the research and education community as national projects. By combining such platforms with VLSI multichip foundry services, various integrated devices, referred to as “CMOS-MEMS”, can be realized without constructing an entire cleanroom. In this paper, we summarize MEMS-last postprocess schemes for CMOS devices on a bulk silicon wafer as well as on a silicon-on-insulator (SOI) wafer using an open-access cleanroom of the Nanotechnology Platform of MEXT Japan. The integration devices presented in this article are free-standing structures and postprocess isolated LSI devices. Postprocess issues are identified with their solutions, such as the reactive ion etching (RIE) lag for dry release and the impact of the deep RIE (DRIE) postprocess on transistor characteristics. Integration with nonsilicon materials is proposed as one of the future directions.

Radiation-hardened transistor and integrated circuit

DOEpatents

Ma, Kwok K.

2007-11-20

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

Very thin, high Ge content Si 0.3Ge 0.7 relaxed buffer grown by MBE on SOI(0 0 1) substrate

NASA Astrophysics Data System (ADS)

Myronov, M.; Shiraki, Y.

2007-04-01

Growth procedure and excellent properties of very thin 240 nm thick, 95% relaxed, high Ge content Si 0.3Ge 0.7 buffer grown on SOI(0 0 1) substrate are demonstrated. All epilayers of the newly developed Si 0.3Ge 0.7/SOI(0 0 1) variable-temperature virtual substrate were grown in a single process by solid-source molecular beam epitaxy. Surface analysis of grown samples revealed smooth, cross-hatch free surface with low root mean square surface roughness of 0.9 nm and low threading dislocations density of 5×10 4 cm -2.

Solid-state semiconductor optical cryocooler based on CdS nanobelts.

PubMed

Li, Dehui; Zhang, Jun; Wang, Xinjiang; Huang, Baoling; Xiong, Qihua

2014-08-13

We demonstrate the laser cooling of silicon-on-insulator (SOI) substrate using CdS nanobelts. The local temperature change of the SOI substrate exactly beneath the CdS nanobelts is deduced from the ratio of the Stokes and anti-Stokes Raman intensities from the Si layer on the top of the SOI substrate. We have achieved a 30 and 20 K net cooling starting from 290 K under a 3.8 mW 514 nm and a 4.4 mW 532 nm pumping, respectively. In contrast, a laser heating effect has been observed pumped by 502 and 488 nm lasers. Theoretical analysis based on the general static heat conduction module in the Ansys program package is conducted, which agrees well with the experimental results. Our investigations demonstrate the laser cooling capability of an external thermal load, suggesting the applications of II-VI semiconductors in all-solid-state optical cryocoolers.

Single Event Transient Analysis of an SOI Operational Amplifier for Use in Low-Temperature Martian Exploration

NASA Technical Reports Server (NTRS)

Laird, Jamie S.; Scheik, Leif; Vizkelethy, Gyorgy; Mojarradi, Mohammad M; Chen, Yuan; Miyahira, Tetsuo; Blalock, Benjamin; Greenwell, Robert; Doyle, Barney

2006-01-01

The next generation of Martian rover#s to be launched by JPL are to examine polar regions where temperatures are extremely low and the absence of an earth-like atmosphere results in high levels of cosmic radiation at ground level. Cosmic rays lead to a plethora of radiation effects including Single Event Transients (SET) which can severely degrade microelectronic functionality. As such, a radiation-hardened, temperature compensated CMOS Single-On-Insulator (SOI) Operational Amplifier has been designed for JPL by the University of Tennessee and fabricated by Honeywell using the SOI V process. SOI technology has been shownto be far less sensitive to transient effects than both bulk and epilayer Si. Broad beam heavy-ion tests at the University of Texas A&M using Kr and Xebeams of energy 25MeV/amu were performed to ascertain the duration and severity of the SET for the op-amp configured for a low and high gain application. However, some ambiguity regarding the location of transient formation required the use of a focused MeV ion microbeam. A 36MeV O6(+) microbeam. the Sandia National Laboratory (SNL) was used to image and verify regions of particular concern. This is a viewgraph presentation

Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

NASA Astrophysics Data System (ADS)

Tu, Hongen

This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high-performance MEMS devices and electronics can be integrated into flexible substrates. The potential of our technology is enormous. Many wearable and implantable devices can be developed based on this technology.

Integrated Metamaterials and Nanophotonics in CMOS-Compatible Materials

NASA Astrophysics Data System (ADS)

Reshef, Orad

This thesis explores scalable nanophotonic devices in integrated, CMOS-compatible platforms. Our investigation focuses on two main projects: studying the material properties of integrated titanium dioxide (TiO2), and studying integrated metamaterials in silicon-on-insulator (SOI) technologies. We first describe the nanofabrication process for TiO2 photonic integrated circuits. We use this procedure to demonstrate polycrystalline anatase TiO2 ring resonators with high quality factors. We measure the thermo-optic coefficient of TiO2 and determine that it is negative, a unique property among CMOS-compatible dielectric photonic platforms. We also derive a transfer function for ring resonators in the presence of reflections and demonstrate using full-wave simulations that these reflections produce asymmetries in the resonances. For the second half of the dissertation, we design and demonstrate an SOI-based photonic-Dirac-cone metamaterial. Using a prism composed of this metamaterial, we measure its index of refraction and unambiguously determine that it is zero. Next, we take a single channel of this metamaterial to form a waveguide. Using interferometry, we independently confirm that the waveguide in this configuration preserves the dispersion profile of the aggregate medium, with a zero phase advance. We also characterize the waveguide, determining its propagation loss. Finally, we perform simulations to study nonlinear optical phenomena in zero-index media. We find that an isotropic refractive index near zero relaxes certain phase-matching constraints, allowing for more flexible configurations of nonlinear devices with dramatically reduced footprints. The outcomes of this work enable higher quality fabrication of scalable nanophotonic devices for use in nonlinear applications with passive temperature compensation. These devices are CMOS-compatible and can be integrated vertically for compact, device-dense industrial applications. It also provides access to a versatile, scalable and integrated medium with a refractive index that can be continuously engineered between n = -0.20 and n = +0.50. This opens the door to applications in high-precision interferometry, sensing, quantum information technologies and compact nonlinear applications.

A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

PubMed

Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

2014-02-10

We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

Novel spot size converter for coupling standard single mode fibers to SOI waveguides

NASA Astrophysics Data System (ADS)

Sisto, Marco Michele; Fisette, Bruno; Paultre, Jacques-Edmond; Paquet, Alex; Desroches, Yan

2016-03-01

We have designed and numerically simulated a novel spot size converter for coupling standard single mode fibers with 10.4μm mode field diameter to 500nm × 220nm SOI waveguides. Simulations based on the eigenmode expansion method show a coupling loss of 0.4dB at 1550nm for the TE mode at perfect alignment. The alignment tolerance on the plane normal to the fiber axis is evaluated at +/-2.2μm for <=1dB excess loss, which is comparable to the alignment tolerance between two butt-coupled standard single mode fibers. The converter is based on a cross-like arrangement of SiOxNy waveguides immersed in a 12μm-thick SiO2 cladding region deposited on top of the SOI chip. The waveguides are designed to collectively support a single degenerate mode for TE and TM polarizations. This guided mode features a large overlap to the LP01 mode of standard telecom fibers. Along the spot size converter length (450μm), the mode is first gradually confined in a single SiOxNy waveguide by tapering its width. Then, the mode is adiabatically coupled to a SOI waveguide underneath the structure through a SOI inverted taper. The shapes of SiOxNy and SOI tapers are optimized to minimize coupling loss and structure length, and to ensure adiabatic mode evolution along the structure, thus improving the design robustness to fabrication process errors. A tolerance analysis based on conservative microfabrication capabilities suggests that coupling loss penalty from fabrication errors can be maintained below 0.3dB. The proposed spot size converter is fully compliant to industry standard microfabrication processes available at INO.

Performance study of double SOI image sensors

NASA Astrophysics Data System (ADS)

Miyoshi, T.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Hara, K.; Ikegami, Y.; Kurachi, I.; Nishimura, R.; Ono, S.; Tauchi, K.; Tsuboyama, T.; Yamada, M.

2018-02-01

Double silicon-on-insulator (DSOI) sensors composed of two thin silicon layers and one thick silicon layer have been developed since 2011. The thick substrate consists of high resistivity silicon with p-n junctions while the thin layers are used as SOI-CMOS circuitry and as shielding to reduce the back-gate effect and crosstalk between the sensor and the circuitry. In 2014, a high-resolution integration-type pixel sensor, INTPIX8, was developed based on the DSOI concept. This device is fabricated using a Czochralski p-type (Cz-p) substrate in contrast to a single SOI (SSOI) device having a single thin silicon layer and a Float Zone p-type (FZ-p) substrate. In the present work, X-ray spectra of both DSOI and SSOI sensors were obtained using an Am-241 radiation source at four gain settings. The gain of the DSOI sensor was found to be approximately three times that of the SSOI device because the coupling capacitance is reduced by the DSOI structure. An X-ray imaging demonstration was also performed and high spatial resolution X-ray images were obtained.

Charge collection properties in an irradiated pixel sensor built in a thick-film HV-SOI process

NASA Astrophysics Data System (ADS)

Hiti, B.; Cindro, V.; Gorišek, A.; Hemperek, T.; Kishishita, T.; Kramberger, G.; Krüger, H.; Mandić, I.; Mikuž, M.; Wermes, N.; Zavrtanik, M.

2017-10-01

Investigation of HV-CMOS sensors for use as a tracking detector in the ATLAS experiment at the upgraded LHC (HL-LHC) has recently been an active field of research. A potential candidate for a pixel detector built in Silicon-On-Insulator (SOI) technology has already been characterized in terms of radiation hardness to TID (Total Ionizing Dose) and charge collection after a moderate neutron irradiation. In this article we present results of an extensive irradiation hardness study with neutrons up to a fluence of 1× 1016 neq/cm2. Charge collection in a passive pixelated structure was measured by Edge Transient Current Technique (E-TCT). The evolution of the effective space charge concentration was found to be compliant with the acceptor removal model, with the minimum of the space charge concentration being reached after 5× 1014 neq/cm2. An investigation of the in-pixel uniformity of the detector response revealed parasitic charge collection by the epitaxial silicon layer characteristic for the SOI design. The results were backed by a numerical simulation of charge collection in an equivalent detector layout.

Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

2010-10-01

Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

Enhanced spectroscopic gas sensors using in-situ grown carbon nanotubes

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Luca, A.; Cole, M. T.; Milne, W. I.

2015-05-11

In this letter, we present a fully complementary-metal-oxide-semiconductor (CMOS) compatible microelectromechanical system thermopile infrared (IR) detector employing vertically aligned multi-walled carbon nanotubes (CNT) as an advanced nano-engineered radiation absorbing material. The detector was fabricated using a commercial silicon-on-insulator (SOI) process with tungsten metallization, comprising a silicon thermopile and a tungsten resistive micro-heater, both embedded within a dielectric membrane formed by a deep-reactive ion etch following CMOS processing. In-situ CNT growth on the device was achieved by direct thermal chemical vapour deposition using the integrated micro-heater as a micro-reactor. The growth of the CNT absorption layer was verified through scanning electronmore » microscopy, transmission electron microscopy, and Raman spectroscopy. The functional effects of the nanostructured ad-layer were assessed by comparing CNT-coated thermopiles to uncoated thermopiles. Fourier transform IR spectroscopy showed that the radiation absorbing properties of the CNT adlayer significantly enhanced the absorptivity, compared with the uncoated thermopile, across the IR spectrum (3 μm–15.5 μm). This led to a four-fold amplification of the detected infrared signal (4.26 μm) in a CO{sub 2} non-dispersive-IR gas sensor system. The presence of the CNT layer was shown not to degrade the robustness of the uncoated devices, whilst the 50% modulation depth of the detector was only marginally reduced by 1.5 Hz. Moreover, we find that the 50% normalized absorption angular profile is subsequently more collimated by 8°. Our results demonstrate the viability of a CNT-based SOI CMOS IR sensor for low cost air quality monitoring.« less

Mask-less deposition of Au-SnO2 nanocomposites on CMOS MEMS platform for ethanol detection.

PubMed

Santra, S; Sinha, A K; De Luca, A; Ali, S Z; Udrea, F; Guha, P K; Ray, S K; Gardner, J W

2016-03-29

Here we report on the mask-less deposition of Au-SnO2 nanocomposites with a silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) micro electro mechanical system (MEMS) platform through the use of dip pen nanolithography (DPN) to create a low-cost ethanol sensor. MEMS technology is used in order to achieve low power consumption, by the employment of a membrane structure formed using deep reactive ion etching technique. The device consists of an embedded tungsten micro-heater with gold interdigitated electrodes on top of the SOI membrane. The tungsten micro-heater is used to raise the membrane temperature up to its operating temperature and the electrodes are used to measure the resistance of the nanocomposite sensing layer. The CMOS MEMS devices have high electro-thermal efficiency, with 8.2 °C temperature increase per mW power of consumption. The sensing material (Au-SnO2 nanocomposite) was synthesised starting from SnO nanoplates, then Au nanoparticles were attached chemically to the surface of SnO nanoplates, finally the mixture was heated at 700 °C in an oven in air for 4 h. This composite material was sonicated for 2 h in terpineol to make a viscous homogeneous slurry and then 'written' directly across the electrode area using the DPN technique without any mask. The devices were characterised by exposure to ethanol vapour in humid air in the concentration range of 100-1000 ppm. The sensitivity varied from 1.2 to 0.27 ppm(-1) for 100-1000 ppm of ethanol at 10% relative humid air. Selectivity measurements showed that the sensors were selective towards ethanol when they were exposed to acetone and toluene.

Mask-less deposition of Au-SnO2 nanocomposites on CMOS MEMS platform for ethanol detection

NASA Astrophysics Data System (ADS)

Santra, S.; Sinha, A. K.; De Luca, A.; Ali, S. Z.; Udrea, F.; Guha, P. K.; Ray, S. K.; Gardner, J. W.

2016-03-01

Here we report on the mask-less deposition of Au-SnO2 nanocomposites with a silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) micro electro mechanical system (MEMS) platform through the use of dip pen nanolithography (DPN) to create a low-cost ethanol sensor. MEMS technology is used in order to achieve low power consumption, by the employment of a membrane structure formed using deep reactive ion etching technique. The device consists of an embedded tungsten micro-heater with gold interdigitated electrodes on top of the SOI membrane. The tungsten micro-heater is used to raise the membrane temperature up to its operating temperature and the electrodes are used to measure the resistance of the nanocomposite sensing layer. The CMOS MEMS devices have high electro-thermal efficiency, with 8.2 °C temperature increase per mW power of consumption. The sensing material (Au-SnO2 nanocomposite) was synthesised starting from SnO nanoplates, then Au nanoparticles were attached chemically to the surface of SnO nanoplates, finally the mixture was heated at 700 °C in an oven in air for 4 h. This composite material was sonicated for 2 h in terpineol to make a viscous homogeneous slurry and then ‘written’ directly across the electrode area using the DPN technique without any mask. The devices were characterised by exposure to ethanol vapour in humid air in the concentration range of 100-1000 ppm. The sensitivity varied from 1.2 to 0.27 ppm-1 for 100-1000 ppm of ethanol at 10% relative humid air. Selectivity measurements showed that the sensors were selective towards ethanol when they were exposed to acetone and toluene.

16-channel arrayed waveguide grating (AWG) demultiplexer design on SOI wafer for application in CWDM-PON

NASA Astrophysics Data System (ADS)

Juhari, Nurjuliana; Menon, P. Susthitha; Ehsan, Abang Annuar; Shaari, Sahbudin

2015-01-01

Arrayed Waveguide Grating (AWG) functioning as a demultiplexer is designed on SOI platform with rib waveguide structure to be utilized in coarse wavelength division multiplexing-passive optical network (CWDM-PON) systems. Two design approaches; conventional and tapered configuration of AWG was developed with channel spacing of 20 nm that covers the standard transmission spectrum of CWDM ranging from 1311 nm to 1611 nm. The performance of insertion loss for tapered configuration offered the lowest insertion loss of 0.77 dB but the adjacent crosstalk gave non-significant relation for both designs. With average channel spacing of 20.4 nm, the nominal central wavelength of this design is close to the standard CWDM wavelength grid over 484 nm free spectrum range (FSR).

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2018-03-01

In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.

Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors

NASA Astrophysics Data System (ADS)

Simoen, Eddy; Gaillardin, Marc; Paillet, Philippe; Reed, Robert A.; Schrimpf, Ron D.; Alles, Michael L.; El-Mamouni, Farah; Fleetwood, Daniel M.; Griffoni, Alessio; Claeys, Cor

2013-06-01

The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.

Image sensor pixel with on-chip high extinction ratio polarizer based on 65-nm standard CMOS technology.

PubMed

Sasagawa, Kiyotaka; Shishido, Sanshiro; Ando, Keisuke; Matsuoka, Hitoshi; Noda, Toshihiko; Tokuda, Takashi; Kakiuchi, Kiyomi; Ohta, Jun

2013-05-06

In this study, we demonstrate a polarization sensitive pixel for a complementary metal-oxide-semiconductor (CMOS) image sensor based on 65-nm standard CMOS technology. Using such a deep-submicron CMOS technology, it is possible to design fine metal patterns smaller than the wavelengths of visible light by using a metal wire layer. We designed and fabricated a metal wire grid polarizer on a 20 × 20 μm(2) pixel for image sensor. An extinction ratio of 19.7 dB was observed at a wavelength 750 nm.

Growth and optical properties of CMOS-compatible silicon nanowires for photonic devices

NASA Astrophysics Data System (ADS)

Guichard, Alex Richard

Silicon (Si) is the dominant semiconductor material in both the microelectronic and photovoltaic industries. Despite its poor optical properties, Si is simply too abundant and useful to be completely abandoned in either industry. Since the initial discovery of efficient room temperature photoluminescence (PL) from porous Si and the following discoveries of PL and time-resolved optical gain from Si nanocrystals (Si-nc) in SiO2, many groups have studied the feasibility of making Si-based, CMOS-compatible electroluminescent devices and electrically pumped lasers. These studies have shown that for Si-ne sizes below about 10 nm, PL can be attributed to radiative recombination of confined excitons and quantum efficiencies can reach 90%. PL peak energies are blue-shifted from the bulk Si band edge of 1.1 eV due to the quantum confinement effect and PL decay lifetimes are on mus timescales. However, many unanswered questions still exist about both the ease of carrier injection and various non-radiative and loss mechanisms that are present. A potential alternative material system to porous Si and Si-nc is Si nanowires (SiNWs). In this thesis, I examine the optical properties of SiNWs with diameters in the range of 3-30 nm fabricated by a number of compound metal oxide semiconductor (CMOS) compatible fabrication techniques including Chemical Vapor Deposition on metal nanoparticle coated substrates, catalytic wet etching of bulk Si and top-down electron-beam lithographic patterning. Using thermal oxidation and etching, we can increase the degree of confinement in the SiNWs. I demonstrate PL peaked in the visible and near-infrared (NIR) wavelength ranges that is tunable by controlling the crystalline SiNW core diameter, which is measured with dark field and high-resolution transmission electron microscopy. PL decay lifetimes of the SiNWs are on the order of 50 mus after proper surface passivation, which suggest that the PL is indeed from confined carriers in the SiNW cores. Investigation of the non-radiative Auger recombination (AR) process suggests that for high carrier densities in excess of 1019 cm-3, the AR lifetime is about 80 ns and decreases with increasing carrier density. This SiNW AR lifetime is slower than the AR process in Si nanocrystals at similar carrier densities, but faster than the radiative process. I also study the light emission and absorption properties of single SiNWs patterned on Silicon-on-insulator (SOI) substrates and find that a large fraction of NWs is optically dead. Moreover, the active, light-emitting nanostructures exhibit PL blinking, a mechanism often seen for individual nanostructure light emitters. These results are essential to evaluating Si nanostructures as a feasible gain or lasing medium. A second potential application for SiNWs is as a building block for low-cost, Si-based photovoltaics (PV). The market for thin-film PV, particularly organic thin-film PV, exists because it offers potential lower cost solutions for solar power versus bulk Si-based PV. However, many thin film technologies, while possessing superior optical absorption properties compared to Si, suffer from poor electronic transport properties. Here, I present a new Si-based PV design that combines the desirable optical properties of highly absorptive organic molecules and the high-mobility electronic properties of crystalline Si. This synergy is achieved by exploiting efficient Forster energy transfer from the light absorbing organic to SiNWs that enable current extraction. The energy transfer radius of a particular dye and bulk Si is found to be roughly 4 nm. Spectroscopic photocurrent experiments were performed on unpatterned SOI wafers as well as SiNWs patterned in SOI substrates and a significant photocurrent increase was seen in samples coated with organics versus uncoated samples. The photocurrent increase is seen in the wavelength range of the dye's absorption band, suggesting absorption of the dye and subsequent energy transfer to the Si plays a role. These results could pave the way for new low-cost, Si-based solar cell designs that leverage the strengths of the Si PV and microelectronics industries.

Realization of back-side heterogeneous hybrid III-V/Si DBR lasers for silicon photonics

NASA Astrophysics Data System (ADS)

Durel, Jocelyn; Ferrotti, Thomas; Chantre, Alain; Cremer, Sébastien; Harduin, Julie; Bernabé, Stéphane; Kopp, Christophe; Boeuf, Frédéric; Ben Bakir, Badhise; Broquin, Jean-Emmanuel

2016-02-01

In this paper, the simulation, design and fabrication of a back-side coupling (BSC) concept for silicon photonics, which targets heterogeneous hybrid III-V/Si laser integration is presented. Though various demonstrations of a complete SOI integration of passive and active photonic devices have been made, they all feature multi-level planar metal interconnects, and a lack of integrated light sources. This is mainly due to the conflict between the need of planar surfaces for III-V/Si bonding and multiple levels of metallization. The proposed BSC solution to this topographical problem consists in fabricating lasers on the back-side of the Si waveguides using a new process sequence. The devices are based on a hybrid structure composed of an InGaAsP MQW active area and a Si-based DBR cavity. The emitted light wavelength is accordable within a range of 20 nm around 1.31μm thanks to thermal heaters and the laser output is fiber coupled through a Grating Coupler (GC). From a manufacturing point of view, the BSC approach provides not only the advantages of allowing the use of a thin-BOX SOI instead of a thick one; but it also shifts the laser processing steps and their materials unfriendly to CMOS process to the far back-end areas of fabrication lines. Moreover, aside from solving technological integration issues, the BSC concept offers several new design opportunities for active and passive devices (heat sink, Bragg gratings, grating couplers enhanced with integrated metallic mirrors, tapers…). These building boxes are explored here theoretically and experimentally.

PDSOI and Radiation Effects: An Overview

NASA Technical Reports Server (NTRS)

Forgione, Joshua B.

2005-01-01

Bulk silicon substrates are a common characteristic of nearly all commercial, Complementary Metal-Oxide-Semiconductor (CMOS), integrated circuits. These devices operate well on Earth, but are not so well received in the space environment. An alternative to bulk CMOS is the Silicon-On-Insulator (SOI), in which a &electric isolates the device layer from the substrate. SO1 behavior in the space environment has certain inherent advantages over bulk, a primary factor in its long-time appeal to space-flight IC designers. The discussion will investigate the behavior of the Partially-Depleted SO1 (PDSOI) device with respect to some of the more common space radiation effects: Total Ionized Dose (TID), Single-Event Upsets (SEUs), and Single-Event Latchup (SEL). Test and simulation results from the literature, bulk and epitaxial comparisons facilitate reinforcement of PDSOI radiation characteristics.

A Pearson Effective Potential for Monte Carlo Simulation of Quantum Confinement Effects in nMOSFETs

NASA Astrophysics Data System (ADS)

Jaud, Marie-Anne; Barraud, Sylvain; Saint-Martin, Jérôme; Bournel, Arnaud; Dollfus, Philippe; Jaouen, Hervé

2008-12-01

A Pearson Effective Potential model for including quantization effects in the simulation of nanoscale nMOSFETs has been developed. This model, based on a realistic description of the function representing the non zero-size of the electron wave packet, has been used in a Monte-Carlo simulator for bulk, single gate SOI and double-gate SOI devices. In the case of SOI capacitors, the electron density has been computed for a large range of effective field (between 0.1 MV/cm and 1 MV/cm) and for various silicon film thicknesses (between 5 nm and 20 nm). A good agreement with the Schroedinger-Poisson results is obtained both on the total inversion charge and on the electron density profiles. The ability of an Effective Potential approach to accurately reproduce electrostatic quantum confinement effects is clearly demonstrated.

Solid State Research

DTIC Science & Technology

1999-02-23

pumped at frequencies up to 5.5 kHz (with 10-W pumping). At high pulse repetition rates the radius of the beam waist decreases to ~60 jum, owing to...1998) A 1.3-GHz SOI CMOS Test Chip for R. Berger Low-Power High -Speed Pulse W. G. Lyons Processing A. M. Soares IEEE J. Solid-State Circuits...Goodhue D. E. Mull J. M. Rossler Y. Royter C.G.Fonstad* /. Vac. Sei. Technol. Modeling the Microwave Impedance of High -Tc Long Josephson

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Characterization of ultrathin SOI film and application to short channel MOSFETs.

PubMed

Tang, Xiaohui; Reckinger, Nicolas; Larrieu, Guilhem; Dubois, Emmanuel; Flandre, Denis; Raskin, Jean-Pierre; Nysten, Bernard; Jonas, Alain M; Bayot, Vincent

2008-04-23

In this study, a very dilute solution (NH(4)OH:H(2)O(2):H(2)O 1:8:64 mixture) was employed to reduce the thickness of commercially available SOI wafers down to 3 nm. The etch rate is precisely controlled at 0.11 Å s(-1) based on the self-limited etching speed of the solution. The thickness uniformity of the thin film, evaluated by spectroscopic ellipsometry and by high-resolution x-ray reflectivity, remains constant through the thinning process. Moreover, the film roughness, analyzed by atomic force microscopy, slightly improves during the thinning process. The residual stress in the thin film is much smaller than that obtained by sacrificial oxidation. Mobility, measured by means of a bridge-type Hall bar on 15 nm film, is not significantly reduced compared to the value of bulk silicon. Finally, the thinned SOI wafers were used to fabricate Schottky-barrier metal-oxide-semiconductor field-effect transistors with a gate length down to 30 nm, featuring state-of-the-art current drive performance.

SiNOI and AlGaAs-on-SOI nonlinear circuits for continuum generation in Si photonics

NASA Astrophysics Data System (ADS)

El Dirani, Houssein; Monat, Christelle; Brision, Stéphane; Olivier, Nicolas; Jany, Christophe; Letartre, Xavier; Pu, Minhao; Girouard, Peter D.; Hagedorn Frandsen, Lars; Semenova, Elizaveta; Katsuo Oxenløwe, Leif; Yvind, Kresten; Sciancalepore, Corrado

2018-02-01

In this communication, we report on the design, fabrication, and testing of Silicon Nitride on Insulator (SiNOI) and Aluminum-Gallium-Arsenide (AlGaAs) on silicon-on-insulator (SOI) nonlinear photonic circuits for continuum generation in Silicon (Si) photonics. As recently demonstrated, the generation of frequency continua and supercontinua can be used to overcome the intrinsic limitations of nowadays silicon photonics notably concerning the heterogeneous integration of III-V on SOI lasers for datacom and telecom applications. By using the Kerr nonlinearity of monolithic silicon nitride and heterointegrated GaAs-based alloys on SOI, the generation of tens or even hundreds of new optical frequencies can be obtained in dispersion tailored waveguides, thus providing an all-optical alternative to the heterointegration of hundreds of standalone III-V on Si lasers. In our work, we present paths to energy-efficient continua generation on silicon photonics circuits. Notably, we demonstrate spectral broadening covering the full C-band via Kerrbased self-phase modulation in SiNOI nanowires featuring full process compatibility with Si photonic devices. Moreover, AlGaAs waveguides are heterointegrated on SOI in order to dramatically reduce (x1/10) thresholds in optical parametric oscillation and in the power required for supercontinuum generation under pulsed pumping. The manufacturing techniques allowing the monolithic co-integration of nonlinear functionalities on existing CMOS-compatible Si photonics for both active and passive components will be shown. Experimental evidence based on self-phase modulation show SiNOI and AlGaAs nanowires capable of generating wide-spanning frequency continua in the C-Band. This will pave the way for low-threshold power-efficient Kerr-based comb- and continuum- sources featuring compatibility with Si photonic integrated circuits (Si-PICs).

Low-noise low-jitter 32-pixels CMOS single-photon avalanche diodes array for single-photon counting from 300 nm to 900 nm

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scarcella, Carmelo; Tosi, Alberto, E-mail: alberto.tosi@polimi.it; Villa, Federica

2013-12-15

We developed a single-photon counting multichannel detection system, based on a monolithic linear array of 32 CMOS SPADs (Complementary Metal-Oxide-Semiconductor Single-Photon Avalanche Diodes). All channels achieve a timing resolution of 100 ps (full-width at half maximum) and a photon detection efficiency of 50% at 400 nm. Dark count rate is very low even at room temperature, being about 125 counts/s for 50 μm active area diameter SPADs. Detection performance and microelectronic compactness of this CMOS SPAD array make it the best candidate for ultra-compact time-resolved spectrometers with single-photon sensitivity from 300 nm to 900 nm.

III-V/Ge MOS device technologies for low power integrated systems

NASA Astrophysics Data System (ADS)

Takagi, S.; Noguchi, M.; Kim, M.; Kim, S.-H.; Chang, C.-Y.; Yokoyama, M.; Nishi, K.; Zhang, R.; Ke, M.; Takenaka, M.

2016-11-01

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also demonstrate planar-type InGaAs and Ge/strained SOI TFETs. The defect-less p+-n source junction formation with steep impurity profiles is a key for high performance TFET operation.

Carrier mobility degradation due to high dose implantation in ultrathin unstrained and strained silicon-on-insulator films

NASA Astrophysics Data System (ADS)

Dupré, C.; Ernst, T.; Hartmann, J.-M.; Andrieu, F.; Barnes, J.-P.; Rivallin, P.; Faynot, O.; Deleonibus, S.; Fazzini, P. F.; Claverie, A.; Cristoloveanu, S.; Ghibaudo, G.; Cristiano, F.

2007-11-01

Based on electrical measurements and transmission electron microscopy (TEM) imaging, we propose an explanation for the electron and hole mobility degradation with gate length reduction in metal-oxide-semiconductor field effect transistors (MOSFETs). We demonstrate that ion implantation, normally used for source/drain doping, is responsible for transport degradation for short-channel devices. Implantation impact on electrons and holes mobility was investigated both on silicon-on-insulator (SOI) and tensile strained silicon-on-insulator (sSOI) substrates. Wafers with ultrathin Si films (from 8 to 35 nm) were Ge implanted at 3 keV and various concentrations (from 5×1014 to 2×1015 atoms cm-2), then annealed at 600 °C for 1 h. Secondary ion mass spectrometry enabled us to quantify the Ge-implanted atoms concentrations. The end-of-range defects impact on mobility was investigated with the pseudo-MOSFET technique. Measurements showed a mobility decrease as the implantation dose increased. We demonstrated that sSOI mobility is more sensitive to implantation than SOI mobility, without any implantation-induced strain relaxation in sSOI (checked using the ultraviolet Raman technique). A 36% (25%) holes (electrons) mobility degradation was measured for sSOI, while SOI presented a 21% mobility degradation for holes and 5% for electrons. Finally, the electrical results were compared with morphological studies. Plan-view TEM showed the presence of interstitial defects formed during ion implantation and annealing. The defect density was estimated to be two times higher in sSOI than in SOI, which is in full agreement with electrical results mentioned before. The results are relevant for the optimization of the source and drain regions of advanced nanoscale SOI and sSOI transistors.

Integrated Optics for Planar imaging and Optical Signal Processing

NASA Astrophysics Data System (ADS)

Song, Qi

Silicon photonics is a subject of growing interest with the potential of delivering planar electro-optical devices with chip scale integration. Silicon-on-insulator (SOI) technology has provided a marvelous platform for photonics industry because of its advantages in integration capability in CMOS circuit and countless nonlinearity applications in optical signal processing. This thesis is focused on the investigation of planar imaging techniques on SOI platform and potential applications in ultra-fast optical signal processing. In the first part, a general review and background introduction about integrated photonics circuit and planar imaging technique are provided. In chapter 2, planar imaging platform is realized by a silicon photodiode on SOI chip. Silicon photodiode on waveguide provides a high numerical aperture for an imaging transceiver pixel. An erbium doped Y2O3 particle is excited by 1550nm Laser and the fluorescent image is obtained with assistance of the scanning system. Fluorescence image is reconstructed by using image de-convolution technique. Under photovoltaic mode, we use an on-chip photodiode and an external PIN photodiode to realize similar resolution as 5μm. In chapter 3, a time stretching technique is developed to a spatial domain to realize a 2D imaging system as an ultrafast imaging tool. The system is evaluated based on theoretical calculation. The experimental results are shown for a verification of system capability to imaging a micron size particle or a finger print. Meanwhile, dynamic information for a moving object is also achieved by correlation algorithm. In chapter 4, the optical leaky wave antenna based on SOI waveguide has been utilized for imaging applications and extensive numerical studied has been conducted. and the theoretical explanation is supported by leaky wave theory. The highly directive radiation has been obtained from the broadside with 15.7 dB directivity and a 3dB beam width of ΔØ 3dB ≈ 1.65° in free space environment when β -1 = 2.409 × 105/m, α=4.576 ×103/m. At the end, electronics beam-steering principle has been studied and the comprehensive model has been built to explain carrier transformation behavior in a PIN junction as individual silicon perturbation. Results show that 1019/cm3 is possible obtained with electron injection mechanism. Although the radiation modulation based on carrier injection of 1019/cm3 gives 0.5dB variation, resonant structure, such as Fabry Perrot Cavity, can be integrated with LOWAs to enhance modulation effect.

Top-Down CMOS-NEMS Polysilicon Nanowire with Piezoresistive Transduction

PubMed Central

Marigó, Eloi; Sansa, Marc; Pérez-Murano, Francesc; Uranga, Arantxa; Barniol, Núria

2015-01-01

A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance assessing the capability to use it and enhance the CMOS-NEMS resonators towards more efficient oscillator. The displacement derived from the capacitive transduction allows to compute the gauge factor for the polysilicon material available in the CMOS technology. PMID:26184222

Top-Down CMOS-NEMS Polysilicon Nanowire with Piezoresistive Transduction.

PubMed

Marigó, Eloi; Sansa, Marc; Pérez-Murano, Francesc; Uranga, Arantxa; Barniol, Núria

2015-07-14

A top-down clamped-clamped beam integrated in a CMOS technology with a cross section of 500 nm × 280 nm has been electrostatic actuated and sensed using two different transduction methods: capacitive and piezoresistive. The resonator made from a single polysilicon layer has a fundamental in-plane resonance at 27 MHz. Piezoresistive transduction avoids the effect of the parasitic capacitance assessing the capability to use it and enhance the CMOS-NEMS resonators towards more efficient oscillator. The displacement derived from the capacitive transduction allows to compute the gauge factor for the polysilicon material available in the CMOS technology.

Tunable filters based on an SOI nano-wire waveguide micro ring resonator

NASA Astrophysics Data System (ADS)

Shuai, Li; Yuanda, Wu; Xiaojie, Yin; Junming, An; Jianguang, Li; Hongjie, Wang; Xiongwei, Hu

2011-08-01

Micro ring resonator (MRR) filters based on a silicon on insulator (SOI) nanowire waveguide are fabricated by electron beam photolithography (EBL) and inductive coupled plasma (ICP) etching technology. The cross-section size of the strip waveguides is 450 × 220 nm2, and the bending radius of the micro ring is around 5 μm. The test results from the tunable filter based on a single ring show that the free spectral range (FSR) is 16.8 nm and the extinction ratio (ER) around the wavelength 1550 nm is 18.1 dB. After thermal tuning, the filter's tuning bandwidth reaches 4.8 nm with a tuning efficiency of 0.12 nm/°C Meanwhile, we fabricated and studied multi-channel filters based on a single ring and a double ring. After measurement, we drew the following conclusions: during the signal transmission of multi-channel filters, crosstalk exists mainly among different transmission channels and are fairly distinct when there are signals input to add ports.

Radiation Performance of 1 Gbit DDR SDRAMs Fabricated in the 90 nm CMOS Technology Node

NASA Technical Reports Server (NTRS)

Ladbury, Raymond L.; Gorelick, Jerry L.; Berg, M. D.; Kim, H.; LaBel, K.; Friendlich, M.; Koga, R.; George, J.; Crain, S.; Yu, P.;

Synthesis of highly integrated optical network based on microdisk-resonator add-drop filters in silicon-on-insulator technology

NASA Astrophysics Data System (ADS)

Kaźmierczak, Andrzej; Dortu, Fabian; Giannone, Domenico; Bogaerts, Wim; Drouard, Emmanuel; Rojo-Romeo, Pedro; Gaffiot, Frederic

2009-10-01

We analyze a highly compact optical add-drop filter topology based on a pair of microdisk resonators and a bus waveguide intersection. The filter is further assessed on an integrated optical 4×4 network for optical on-chip communication. The proposed network structure, as compact as 50×50 μm, is fabricated in a CMOS-compatible process on a silicon-on-insulator (SOI) substrate. Finally, the experimental results demonstrate the proper operation of the fabricated devices.

Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

NASA Astrophysics Data System (ADS)

Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

2017-12-01

With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

NASA Astrophysics Data System (ADS)

Pradeep, Krishna; Poiroux, Thierry; Scheer, Patrick; Juge, André; Gouget, Gilles; Ghibaudo, Gérard

2018-07-01

This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

Novel technique of source and drain engineering for dual-material double-gate (DMDG) SOI MOSFETS

NASA Astrophysics Data System (ADS)

Yadav, Himanshu; Malviya, Abhishek Kumar; Chauhan, R. K.

2018-04-01

The dual-metal dual-gate (DMDG) SOI has been used with Dual Sided Source and Drain Engineered 50nm SOI MOSFET with various high-k gate oxide. It has been scrutinized in this work to enhance its electrical performance. The proposed structure is designed by creating Dual Sided Source and Drain Modification and its characteristics are evaluated on ATLAS device simulator. The consequence of this dual sided assorted doping on source and drain side of the DMDG transistor has better leakage current immunity and heightened ION current with higher ION to IOFF Ratio. Which thereby vesting the proposed device appropriate for low power digital applications.

Fully Integrated Optical Spectrometer in Visible and Near-IR in CMOS.

PubMed

Hong, Lingyu; Sengupta, Kaushik

2017-12-01

Optical spectrometry in the visible and near-infrared range has a wide range of applications in healthcare, sensing, imaging, and diagnostics. This paper presents the first fully integrated optical spectrometer in standard bulk CMOS process without custom fabrication, postprocessing, or any external optical passive structure such as lenses, gratings, collimators, or mirrors. The architecture exploits metal interconnect layers available in CMOS processes with subwavelength feature sizes to guide, manipulate, control, diffract light, integrated photodetector, and read-out circuitry to detect dispersed light, and then back-end signal processing for robust spectral estimation. The chip, realized in bulk 65-nm low power-CMOS process, measures 0.64 mm 0.56 mm in active area, and achieves 1.4 nm in peak detection accuracy for continuous wave excitations between 500 and 830 nm. This paper demonstrates the ability to use these metal-optic nanostructures to miniaturize complex optical instrumentation into a new class of optics-free CMOS-based systems-on-chip in the visible and near-IR for various sensing and imaging applications.

Sensitivity Enhancement in Si Nanophotonic Waveguides Used for Refractive Index Sensing

PubMed Central

Shi, Yaocheng; Ma, Ke; Dai, Daoxin

2016-01-01

A comparative study is given for the sensitivity of several typical Si nanophotonic waveguides, including SOI (silicon-on-insulator) nanowires, nanoslot waveguides, suspended Si nanowires, and nanofibers. The cases for gas sensing (ncl ~ 1.0) and liquid sensing (ncl ~ 1.33) are considered. When using SOI nanowires (with a SiO2 buffer layer), the sensitivity for liquid sensing (S ~ 0.55) is higher than that for gas sensing (S ~ 0.35) due to lower asymmetry in the vertical direction. By using SOI nanoslot waveguides, suspended Si nanowires, and Si nanofibers, one could achieve a higher sensitivity compared to sensing with a free-space beam (S = 1.0). The sensitivity for gas sensing is higher than that for liquid sensing due to the higher index-contrast. The waveguide sensitivity of an optimized suspended Si nanowire for gas sensing is as high as 1.5, which is much higher than that of a SOI nanoslot waveguide. Furthermore, the optimal design has very large tolerance to the core width variation due to the fabrication error (∆w ~ ±50 nm). In contrast, a Si nanofiber could also give a very high sensitivity (e.g., ~1.43) while the fabrication tolerance is very small (i.e., ∆w < ±5 nm). The comparative study shows that suspended Si nanowire is a good choice to achieve ultra-high waveguide sensitivity. PMID:26950132

Sensitivity Enhancement in Si Nanophotonic Waveguides Used for Refractive Index Sensing.

PubMed

Shi, Yaocheng; Ma, Ke; Dai, Daoxin

2016-03-03

A comparative study is given for the sensitivity of several typical Si nanophotonic waveguides, including SOI (silicon-on-insulator) nanowires, nanoslot waveguides, suspended Si nanowires, and nanofibers. The cases for gas sensing (ncl ~ 1.0) and liquid sensing (ncl ~ 1.33) are considered. When using SOI nanowires (with a SiO₂ buffer layer), the sensitivity for liquid sensing (S ~ 0.55) is higher than that for gas sensing (S ~ 0.35) due to lower asymmetry in the vertical direction. By using SOI nanoslot waveguides, suspended Si nanowires, and Si nanofibers, one could achieve a higher sensitivity compared to sensing with a free-space beam (S = 1.0). The sensitivity for gas sensing is higher than that for liquid sensing due to the higher index-contrast. The waveguide sensitivity of an optimized suspended Si nanowire for gas sensing is as high as 1.5, which is much higher than that of a SOI nanoslot waveguide. Furthermore, the optimal design has very large tolerance to the core width variation due to the fabrication error (∆w ~ ±50 nm). In contrast, a Si nanofiber could also give a very high sensitivity (e.g., ~1.43) while the fabrication tolerance is very small (i.e., ∆w < ±5 nm). The comparative study shows that suspended Si nanowire is a good choice to achieve ultra-high waveguide sensitivity.

Radiation Tolerance of 65nm CMOS Transistors

DOE PAGES

Krohn, M.; Bentele, B.; Christian, D. C.; ...

2015-12-11

We report on the effects of ionizing radiation on 65 nm CMOS transistors held at approximately -20°C during irradiation. The pattern of damage observed after a total dose of 1 Grad is similar to damage reported in room temperature exposures, but we observe less damage than was observed at room temperature.

Analysis of Soft Error Rates in 65- and 28-nm FD-SOI Processes Depending on BOX Region Thickness and Body Bias by Monte-Carlo Based Simulations

NASA Astrophysics Data System (ADS)

Zhang, Kuiyuan; Umehara, Shigehiro; Yamaguchi, Junki; Furuta, Jun; Kobayashi, Kazutoshi

2016-08-01

This paper analyzes how body bias and BOX region thickness affect soft error rates in 65-nm SOTB (Silicon on Thin BOX) and 28-nm UTBB (Ultra Thin Body and BOX) FD-SOI processes. Soft errors are induced by alpha-particle and neutron irradiation and the results are then analyzed by Monte Carlo based simulation using PHITS-TCAD. The alpha-particle-induced single event upset (SEU) cross-section and neutron-induced soft error rate (SER) obtained by simulation are consistent with measurement results. We clarify that SERs decreased in response to an increase in the BOX thickness for SOTB while SERs in UTBB are independent of BOX thickness. We also discover SOTB develops a higher tolerance to soft errors when reverse body bias is applied while UTBB become more susceptible.

A comprehensive model on field-effect pnpn devices (Z2-FET)

NASA Astrophysics Data System (ADS)

Taur, Yuan; Lacord, Joris; Parihar, Mukta Singh; Wan, Jing; Martinie, Sebastien; Lee, Kyunghwa; Bawedin, Maryline; Barbe, Jean-Charles; Cristoloveanu, Sorin

2017-08-01

A comprehensive model for field-effect pnpn devices (Z2-FET) is presented. It is based on three current continuity equations coupled to two MOS equations. The model reproduces the characteristic S-shaped I-V curve when the device is driven by a current source. The negative resistance region at intermediate currents occurs as the center junction undergoes a steep transition from reverse to forward bias. Also playing a vital role are the mix and match of the minority carrier diffusion current and the generation recombination current. Physical insights to the key mechanisms at work are gained by regional approximations of the model, from which analytical expressions for the maximum and minimum voltages at the switching points are derived. From 1981 to 2001, he was with the Silicon Technology Department of IBM Thomas J. Watson Research Center, Yorktown Heights, New York, where he was Manager of Exploratory Devices and Processes. Areas in which he has worked and published include latchup-free 1-um CMOS, self-aligned TiSi2, 0.5-um CMOS and BiCMOS, shallow trench isolation, 0.25-um CMOS with n+/p + poly gates, SOI, low-temperature CMOS, and 0.1-um CMOS. Since October 2001, he has been a professor in the Department of Electrical and Computer Engineering, University of California, San Diego. Dr. Yuan Taur was elected a Fellow of the IEEE in 1998. He has served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011. He authored or co-authored over 200 technical papers and holds 14 U.S. patents. He co-authored a book, ;Fundamentals of Modern VLSI Devices,; published by Cambridge University Press in 1998. The 2nd edition was published in 2009. Dr. Yuan Taur received IEEE Electron Devices Society's J. J. Ebers Award in 2012 ;for contributions to the advancement of several generations of CMOS process technologies.;

A 65 nm CMOS LNA for Bolometer Application

NASA Astrophysics Data System (ADS)

Huang, Tom Nan; Boon, Chirn Chye; Zhu, Forest Xi; Yi, Xiang; He, Xiaofeng; Feng, Guangyin; Lim, Wei Meng; Liu, Bei

2016-04-01

Modern bolometers generally consist of large-scale arrays of detectors. Implemented in conventional technologies, such bolometer arrays suffer from integrability and productivity issues. Recently, the development of CMOS technologies has presented an opportunity for the massive production of high-performance and highly integrated bolometers. This paper presents a 65-nm CMOS LNA designed for a millimeter-wave bolometer's pre-amplification stage. By properly applying some positive feedback, the noise figure of the proposed LNA is minimized at under 6 dB and the bandwidth is extended to 30 GHz.

Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

DOE Office of Scientific and Technical Information (OSTI.GOV)

Benoit, M.; de Mendizabal, J. Bilbao; Casse, G.

We investigated the active pixel sensors based on the High-Voltage CMOS technology as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. Our paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. These results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

Results of the 2015 testbeam of a 180 nm AMS High-Voltage CMOS sensor prototype

DOE PAGES

Benoit, M.; de Mendizabal, J. Bilbao; Casse, G.; ...

2016-07-21

We investigated the active pixel sensors based on the High-Voltage CMOS technology as a viable option for the future pixel tracker of the ATLAS experiment at the High-Luminosity LHC. Our paper reports on the testbeam measurements performed at the H8 beamline of the CERN Super Proton Synchrotron on a High-Voltage CMOS sensor prototype produced in 180 nm AMS technology. These results in terms of tracking efficiency and timing performance, for different threshold and bias conditions, are shown.

Dual Interlocked Logic for Single-Event Transient Mitigation

DTIC Science & Technology

2017-03-01

SPICE simulation and fault-injection analysis. Exemplar SPICE simulations have been performed in a 32nm partially- depleted silicon-on-insulator...in this work. The model has been validated at the 32nm SOI technology node with extensive heavy-ion data [7]. For the SPICE simulations, three

Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology

NASA Astrophysics Data System (ADS)

Athanasiou, Sotirios; Legrand, Charles-Alexandre; Cristoloveanu, Sorin; Galy, Philippe

2017-02-01

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28 nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR) of 4.9 V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimum value of 3.5 V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

High-sensitivity silicon nanowire phototransistors

NASA Astrophysics Data System (ADS)

Tan, Siew Li; Zhao, Xingyan; Dan, Yaping

2014-08-01

Silicon nanowires (SiNWs) have emerged as a promising material for high-sensitivity photodetection in the UV, visible and near-infrared spectral ranges. In this work, we demonstrate novel planar SiNW phototransistors on silicon-oninsulator (SOI) substrate using CMOS-compatible processes. The device consists of a bipolar transistor structure with an optically-injected base region. The electronic and optical properties of the SiNW phototransistors are investigated. Preliminary simulation and experimental results show that nanowire geometry, doping densities and surface states have considerable effects on the device performance, and that a device with optimized parameters can potentially outperform conventional Si photodetectors.

CMOS-Compatible SOI MESFETS for Radiation-Hardened DC-to-DC Converters

NASA Technical Reports Server (NTRS)

Thornton, Trevor; Lepkowski, William; Wilk, Seth

2013-01-01

A radiation-tolerant transistor switch has been developed that can operate between 196 and +150 C for DC-to-DC power conversion applications. A prototype buck regulator component was demonstrated to be performing well after a total ionizing dose of 300 krad(Si). The prototype buck converters showed good efficiencies at ultra-high switching speeds in the range of 1 to 10 MHz. Such high switching frequency will enable smaller, lighter buck converters to be developed as part of the next project. Switching regulators are widely used in commercial applications including portable consumer electronics.

Adaptive gain, equalization, and wavelength stabilization techniques for silicon photonic microring resonator-based optical receivers

NASA Astrophysics Data System (ADS)

Palermo, Samuel; Chiang, Patrick; Yu, Kunzhi; Bai, Rui; Li, Cheng; Chen, Chin-Hui; Fiorentino, Marco; Beausoleil, Ray; Li, Hao; Shafik, Ayman; Titriku, Alex

2016-03-01

Interconnect architectures based on high-Q silicon photonic microring resonator devices offer a promising solution to address the dramatic increase in datacenter I/O bandwidth demands due to their ability to realize wavelength-division multiplexing (WDM) in a compact and energy efficient manner. However, challenges exist in realizing efficient receivers for these systems due to varying per-channel link budgets, sensitivity requirements, and ring resonance wavelength shifts. This paper reports on adaptive optical receiver design techniques which address these issues and have been demonstrated in two hybrid-integrated prototypes based on microring drop filters and waveguide photodetectors implemented in a 130nm SOI process and high-speed optical front-ends designed in 65nm CMOS. A 10Gb/s powerscalable architecture employs supply voltage scaling of a three inverter-stage transimpedance amplifier (TIA) that is adapted with an eye-monitor control loop to yield the necessary sensitivity for a given channel. As reduction of TIA input-referred noise is more critical at higher data rates, a 25Gb/s design utilizes a large input-stage feedback resistor TIA cascaded with a continuous-time linear equalizer (CTLE) that compensates for the increased input pole. When tested with a waveguide Ge PD with 0.45A/W responsivity, this topology achieves 25Gb/s operation with -8.2dBm sensitivity at a BER=10-12. In order to address microring drop filters sensitivity to fabrication tolerances and thermal variations, efficient wavelength-stabilization control loops are necessary. A peak-power-based monitoring loop which locks the drop filter to the input wavelength, while achieving compatibility with the high-speed TIA offset-correction feedback loop is implemented with a 0.7nm tuning range at 43μW/GHz efficiency.

Adaptive Circuits for the 0.5-V Nanoscale CMOS Era

NASA Astrophysics Data System (ADS)

Itoh, Kiyoo; Yamaoka, Masanao; Oshima, Takashi

The minimum operating voltage, Vmin, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the lowest necessary threshold voltage, Vt0, of MOSFETs and to threshold-voltage variations, ΔVt, which become more significant with device scaling. There is thus a need for low-Vt0 circuits and ΔVt-immune MOSFETs to reduce Vmin. For memory-rich LSIs, the SRAM block is particularly problematic because it has the highest Vmin. Various techniques are thus proposed to reduce the Vmin: using RAM repair, shortening the data line, up-sizing, and using more relaxed MOSFET scaling. To effectively reduce Vmin of other circuit blocks, dual-Vt0 and dual-VDD circuits using gate-source reverse biasing, temporary activation, and series connection of another small low-Vt0 MOSFET are proposed. They are dynamic logic circuits enabling the power-delay product of the conventional static CMOS inverter to be reduced to 0.09 at a 0.2-V supply, and a DRAM dynamic sense amplifier and power switches operable at below 0.5V. In addition, a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) for Vt-immune MOSFETs are discussed in terms of their low-voltage potential and challenges. As a result, the height up-scalable FinFETs turns out to be quite effective to reduce Vmin to less than 0.5V, if combined with the low-Vt0 circuits. For mixed-signal LSIs, investigation of low-voltage potential of analog circuits, especially for comparators and operational amplifiers, reveals that simple inverter op-amps, in which the low gain and nonlinearity are compensated for by digitally assisted analog designs, are crucial to 0.5-V operations. Finally, it is emphasized that the development of relevant devices and fabrication processes is the key to the achievement of 0.5-V nanoscale LSIs.

How small can MOSFETs get?

NASA Astrophysics Data System (ADS)

Risch, Lothar

2001-10-01

Scaling of CMOS technology made possible the key appliances of our information technology society, like the PC, mobile communication, and the internet. Reduction of feature sizes for semiconductor devices continued according to Moore's law for the last 25 years in order to achieve higher integration densities, higher speed, lower power consumption, and lower costs. But now, as we approach the sub 100 nm regime, several roadblocks have been predicted for the next generations down to 35 nm. The latest ITRS roadmap 99 describes in detail the challenges which have to be addressed for the future CMOS technology nodes, regarding lithography, metallization, power dissipation, and circuit design. Also for the MOSFET, performance degradation is a big issue. Because this is not a limitation from basic physical laws, novel architectures for MOSFETs will be needed to improve again the electrical characteristics and thus pave the way to much smaller transistors than expected in the past. 25 nm CMOS seems to be feasible using very thin silicon substrates on insulator. Further improvements down to 10 nm are very likely with two gates for the control of the charge carriers. So, it is very likely that CMOS will not end with today's roadmap at 35 nm or even before, but may continue with non bulk devices and fully depleted channels. Finally, tunnelling from source to drain will set an end to the reduction of channel length, which is estimated to be below 5 nm.

Study of drain-extended NMOS under electrostatic discharge stress in 28 nm and 40 nm CMOS process

NASA Astrophysics Data System (ADS)

Wang, Weihuai; Jin, Hao; Dong, Shurong; Zhong, Lei; Han, Yan

2016-02-01

Researches on the electrostatic discharge (ESD) performance of drain-extended NMOS (DeNMOS) under the state-of-the-art 28 nm and 40 nm bulk CMOS process are performed in this paper. Three distinguishing phases of avalanche breakdown stage, depletion region push-out stage and parasitic NPN turn on stage of the gate-grounded DeNMOS (GG-DeNMOS) fabricated under 28 nm CMOS process measured with transmission line pulsing (TLP) test are analyzed through TCAD simulations and tape-out silicon verification detailedly. Damage mechanisms and failure spots of GG-DeNMOS under both CMOS processes are thermal breakdown of drain junction. Improvements based on the basic structure adjustments can increase the GG-DeNMOS robustness from original 2.87 mA/μm to the highest 5.41 mA/μm. Under 40 nm process, parameter adjustments based on the basic structure have no significant benefits on the robustness improvements. By inserting P+ segments in the N+ implantation of drain or an entire P+ strip between the N+ implantation of drain and polysilicon gate to form the typical DeMOS-SCR (silicon-controlled rectifier) structure, the ESD robustness can be enhanced from 1.83 mA/μm to 8.79 mA/μm and 29.78 mA/μm, respectively.

Multi-wavelength transceiver integration on SOI for high-performance computing system applications

NASA Astrophysics Data System (ADS)

Aalto, Timo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani; Cherchi, Matteo; Neumeyr, Christian; Ortsiefer, Markus; Malacarne, Antonio

2015-03-01

We present a vision for transceiver integration on a 3 μm SOI waveguide platform for systems scalable to Pb/s. We also present experimental results from the first building blocks developed in the EU-funded RAPIDO project. At 1.3 μm wavelength 80 Gb/s per wavelength is to be achieved using hybrid integration of III-V optoelectronics on SOI. Goals include athermal operation, low-loss I/O coupling, advanced modulation formats and packet switching. An example of the design results is an interposer chip that consists of 12 μm thick SOI waveguides locally tapered down to 3 μm to provide low-loss coupling between an optical single-mode fiber array and the 3 μm SOI chip. First example of experimental results is a 4x4 cyclic AWGs with 5 nm channel spacing, 0.4 dB/facet fiber coupling loss, 3.5 dB center-tocenter loss, and -23 dB adjacent channel crosstalk in 3.5x1.5 mm2 footprint. The second example result is a new VCSEL design that was demonstrated to have up to 40 Gb/s operation at 1.55 μm.

Introduction of performance boosters like Ge as channel material for the future of CMOS

DOE Office of Scientific and Technical Information (OSTI.GOV)

Samia, Slimani, E-mail: slimani.samia@gmail.com; Laboratoire de Modélisation et Méthodes de calcul LMMC,20002 Saida; Bouaza, Djellouli, E-mail: djelbou@hotmail.fr

High mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. Ge is one of new attractive channel materials that require CMOS scaling For future technology nodes and future high performance P-MOSFETS, we have studied a nanoscale SOI DG MOSFETs using quantum simulation approach on DG MOSFETs within the variation of Ge channel concentration and in the presence of source and drain doping by replacing Silicon in the channel by Ge using various dielectric constant. The use of high mobility channel (like Ge) to maximize the MOSFET IDsat and simultaneously circumventmore » the poor electrostatic control to suppress short-channel effects and enhance source injection velocity. The leakage current (I{sub off}) can be controlled by different gates oxide thickness more ever the required threshold voltage (V{sub TH}) can be achieved by keeping gate work function and altering the doping channel.« less

Amorphous silicon as high index photonic material

NASA Astrophysics Data System (ADS)

Lipka, T.; Harke, A.; Horn, O.; Amthor, J.; Müller, J.

2009-05-01

Silicon-on-Insulator (SOI) photonics has become an attractive research topic within the area of integrated optics. This paper aims to fabricate SOI-structures for optical communication applications with lower costs compared to standard fabrication processes as well as to provide a higher flexibility with respect to waveguide and substrate material choice. Amorphous silicon is deposited on thermal oxidized silicon wafers with plasma-enhanced chemical vapor deposition (PECVD). The material is optimized in terms of optical light transmission and refractive index. Different a-Si:H waveguides with low propagation losses are presented. The waveguides were processed with CMOS-compatible fabrication technologies and standard DUV-lithography enabling high volume production. To overcome the large mode-field diameter mismatch between incoupling fiber and sub-μm waveguides three dimensional, amorphous silicon tapers were fabricated with a KOH etched shadow mask for patterning. Using ellipsometric and Raman spectroscopic measurements the material properties as refractive index, layer thickness, crystallinity and material composition were analyzed. Rapid thermal annealing (RTA) experiments of amorphous thin films and rib waveguides were performed aiming to tune the refractive index of the deposited a-Si:H waveguide core layer after deposition.

Proposal for fabrication-tolerant SOI polarization splitter-rotator based on cascaded MMI couplers and an assisted bi-level taper

PubMed Central

Wang, Jing; Qi, Minghao; Xuan, Yi; Huang, Haiyang; Li, You; Li, Ming; Chen, Xin; Jia, Qi; Sheng, Zhen; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Gan, Fuwan

2014-01-01

A novel silicon-on-insulator (SOI) polarization splitter-rotator (PSR) with a large fabrication tolerance is proposed based on cascaded multimode interference (MMI) couplers and an assisted mode-evolution taper. The tapers are designed to adiabatically convert the input TM0 mode into the TE1 mode, which will output as the TE0 mode after processed by the subsequent MMI mode converter, 90-degree phase shifter (PS) and MMI 3 dB coupler. The numerical simulation results show that the proposed device has a < 0.5 dB insertion loss with < −17 dB crosstalk in C optical communication band. Fabrication tolerance analysis is also performed with respect to the deviations of MMI coupler width, PS width, slab height and upper-cladding refractive index, showing that this device could work well even when affected by considerable fabrication errors. With such a robust performance with a large bandwidth, this device offers potential applications for CMOS-compatible polarization diversity, especially in the booming 100 Gb/s coherent optical communications based on silicon photonics technology. PMID:25402029

Proposal for fabrication-tolerant SOI polarization splitter-rotator based on cascaded MMI couplers and an assisted bi-level taper.

PubMed

Wang, Jing; Qi, Minghao; Xuan, Yi; Huang, Haiyang; Li, You; Li, Ming; Chen, Xin; Jia, Qi; Sheng, Zhen; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Gan, Fuwan

2014-11-17

A novel silicon-on-insulator (SOI) polarization splitter-rotator (PSR) with a large fabrication tolerance is proposed based on cascaded multimode interference (MMI) couplers and an assisted mode-evolution taper. The tapers are designed to adiabatically convert the input TM(0) mode into the TE(1) mode, which will output as the TE(0) mode after processed by the subsequent MMI mode converter, 90-degree phase shifter (PS) and MMI 3 dB coupler. The numerical simulation results show that the proposed device has a < 0.5 dB insertion loss with < -17 dB crosstalk in C optical communication band. Fabrication tolerance analysis is also performed with respect to the deviations of MMI coupler width, PS width, slab height and upper-cladding refractive index, showing that this device could work well even when affected by considerable fabrication errors. With such a robust performance with a large bandwidth, this device offers potential applications for CMOS-compatible polarization diversity, especially in the booming 100 Gb/s coherent optical communications based on silicon photonics technology.

Adiabatic Nanofocusing in Hybrid Gap Plasmon Waveguides on the Silicon-on-Insulator Platform.

PubMed

Nielsen, Michael P; Lafone, Lucas; Rakovich, Aliaksandra; Sidiropoulos, Themistoklis P H; Rahmani, Mohsen; Maier, Stefan A; Oulton, Rupert F

2016-02-10

We present an experimental demonstration of a new class of hybrid gap plasmon waveguides on the silicon-on-insulator (SOI) platform. Created by the hybridization of the plasmonic mode of a gap in a thin metal sheet and the transverse-electric (TE) photonic mode of an SOI slab, this waveguide is designed for efficient adiabatic nanofocusing simply by varying the gap width. For gap widths greater than 100 nm, the mode is primarily photonic in character and propagation lengths can be many tens of micrometers. For gap widths below 100 nm, the mode becomes plasmonic in character with field confinement predominantly within the gap region and with propagation lengths of a few microns. We estimate the electric field intensity enhancement in hybrid gap plasmon waveguide tapers at 1550 nm by three-photon absorption of selectively deposited CdSe/ZnS quantum dots within the gap. Here, we show electric field intensity enhancements of up to 167 ± 26 for a 24 nm gap, proving the viability of low loss adiabatic nanofocusing on a commercially relevant photonics platform.

A low-noise wide-dynamic-range event-driven detector using SOI pixel technology for high-energy particle imaging

NASA Astrophysics Data System (ADS)

Shrestha, Sumeet; Kamehama, Hiroki; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Takeda, Ayaki; Tsuru, Takeshi Go; Arai, Yasuo

2015-08-01

This paper presents a low-noise wide-dynamic-range pixel design for a high-energy particle detector in astronomical applications. A silicon on insulator (SOI) based detector is used for the detection of wide energy range of high energy particles (mainly for X-ray). The sensor has a thin layer of SOI CMOS readout circuitry and a thick layer of high-resistivity detector vertically stacked in a single chip. Pixel circuits are divided into two parts; signal sensing circuit and event detection circuit. The event detection circuit consisting of a comparator and logic circuits which detect the incidence of high energy particle categorizes the incident photon it into two energy groups using an appropriate energy threshold and generate a two-bit code for an event and energy level. The code for energy level is then used for selection of the gain of the in-pixel amplifier for the detected signal, providing a function of high-dynamic-range signal measurement. The two-bit code for the event and energy level is scanned in the event scanning block and the signals from the hit pixels only are read out. The variable-gain in-pixel amplifier uses a continuous integrator and integration-time control for the variable gain. The proposed design allows the small signal detection and wide dynamic range due to the adaptive gain technique and capability of correlated double sampling (CDS) technique of kTC noise canceling of the charge detector.

Design and application of 8-channel SOI-based AWG demultiplexer for CWDM-system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Juhari, Nurjuliana; Menon, P. Susthitha; Ehsan, Abang Annuar

2015-04-24

Arrayed Waveguide Grating (AWG) serving as a demultiplexer (demux) has been designed on SOI platform and was utilized in a Coarse Wavelength Division Multiplexing (CWDM) system ranging from 1471 nm to 1611 nm. The investigation was carried out at device and system levels. At device level, 20 nm (∼ 2500 GHz) channel spacing was successfully simulated using beam propagation method (BPM) under TE mode polarization with a unique double S-shape pattern at arrays region. The performance of optical properties gave the low values of 0.96 dB dB for insertion loss and – 22.38 dB for optical crosstalk. AWG device wasmore » then successfully used as demultiplexer in CWDM system when 10 Gb/s data rate was applied in the system. Limitation of signal power due to attenuation and fiber dispersion detected by BER analyzer =10{sup −9} of the system was compared with theoretical value. Hence, the maximum distance of optical fiber can be achieved.« less

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Proceedings of the 1996 Space Surveillance Workshop Held in Lexington, Massachusetts on 2-4 April 1996. Volume 1,

DTIC Science & Technology

1996-04-04

of multi-spectral SOI data. These spectra are for blue (B), visible (V), red (R) and infrared (I). Broadband SOI can also be collected in the open...the etalon is of order 200nm with a finesse of order 20, three spectral channels in blue , red and near-IR can be created and separated using a low...References 1 Lincoln Labs. J. 5 (1992) Nol. 2 Laser Guide Star Adaptive Optics Workshop, Vols 1&2, R Q Fugate (Ed), SOR, Phillips Lab/LITE

Detection limit of a VCO based detection chain dedicated to particles recognition and tracking

NASA Astrophysics Data System (ADS)

Coulié, K.; Rahajandraibe, W.; Aziza, H.; Micolau, G.; Vauché, R.

2018-01-01

A particle detection chain based on CMOS-SOI VCO circuit is presented. The solution is used for the recognition and the tracking of a given particle at circuit level. TCAD simulation of the detector has been performed on a 3×3 matrix of diodes based detector for particles recognition and tracking. The current response of the detector has been used for a case study in order to determine the ability of the chain to recognize an alpha particle crossing a 3×3 detection cell. The detection limit of the proposed solution is investigated and discussed in this paper.

Radiation hard pixel sensors using high-resistive wafers in a 150 nm CMOS processing line

NASA Astrophysics Data System (ADS)

Pohl, D.-L.; Hemperek, T.; Caicedo, I.; Gonella, L.; Hügging, F.; Janssen, J.; Krüger, H.; Macchiolo, A.; Owtscharenko, N.; Vigani, L.; Wermes, N.

2017-06-01

Pixel sensors using 8'' CMOS processing technology have been designed and characterized offering the benefits of industrial sensor fabrication, including large wafers, high throughput and yield, as well as low cost. The pixel sensors are produced using a 150 nm CMOS technology offered by LFoundry in Avezzano. The technology provides multiple metal and polysilicon layers, as well as metal-insulator-metal capacitors that can be employed for AC-coupling and redistribution layers. Several prototypes were fabricated and are characterized with minimum ionizing particles before and after irradiation to fluences up to 1.1 × 1015 neq cm-2. The CMOS-fabricated sensors perform equally well as standard pixel sensors in terms of noise and hit detection efficiency. AC-coupled sensors even reach 100% hit efficiency in a 3.2 GeV electron beam before irradiation.

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

NASA Astrophysics Data System (ADS)

Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

2016-09-01

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

Assessment of a Low-Power 65 nm CMOS Technology for Analog Front-End Design

NASA Astrophysics Data System (ADS)

Manghisoni, Massimo; Gaioni, Luigi; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

2014-02-01

This work is concerned with the study of the analog properties of MOSFET devices belonging to a 65 nm CMOS technology with emphasis on intrinsic voltage gain and noise performance. This node appears to be a robust and promising solution to cope with the unprecedented requirements set by silicon vertex trackers in experiments upgrades and future colliders as well as by imaging detectors at light sources and free electron lasers. In this scaled-down technology, the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. An inversion level design methodology has been adopted to analyze data obtained from device measurements and provide a powerful tool to establish design criteria for detector front-ends in this nanoscale CMOS process. A comparison with data coming from less scaled technologies, such as 90 nm and 130 nm nodes, is also provided and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100 nm minimum feature size range.

Piezoelectric micromachined ultrasonic transducers for fingerprint sensing

NASA Astrophysics Data System (ADS)

Lu, Yipeng

Fingerprint identification is the most prevalent biometric technology due to its uniqueness, universality and convenience. Over the past two decades, a variety of physical mechanisms have been exploited to capture an electronic image of a human fingerprint. Among these, capacitive fingerprint sensors are the ones most widely used in consumer electronics because they are fabricated using conventional complementary metal oxide semiconductor (CMOS) integrated circuit technology. However, capacitive fingerprint sensors are extremely sensitive to finger contamination and moisture. This thesis will introduce an ultrasonic fingerprint sensor using a PMUT array, which offers a potential solution to this problem. In addition, it has the potential to increase security, as it allows images to be collected at various depths beneath the epidermis, providing images of the sub-surface dermis layer and blood vessels. Firstly, PMUT sensitivity is maximized by optimizing the layer stack and electrode design, and the coupling coefficient is doubled via series transduction. Moreover, a broadband PMUT with 97% fractional bandwidth is achieved by utilizing a thinner structure excited at two adjacent mechanical vibration modes with overlapping bandwidth. In addition, we proposed waveguide PMUTs, which function to direct acoustic waves, confine acoustic energy, and provide mechanical protection for the PMUT array. Furthermore, PMUT arrays were fabricated with different processes to form the membrane, including front-side etching with a patterned sacrificial layer, front-side etching with additional anchor, cavity SOI wafers and eutectic bonding. Additionally, eutectic bonding allows the PMUT to be integrated with CMOS circuits. PMUTs were characterized in the mechanical, electrical and acoustic domains. Using transmit beamforming, a narrow acoustic beam was achieved, and high-resolution (sub-100 microm) and short-range (~1 mm) pulse-echo ultrasonic imaging was demonstrated using a steel phantom. Finally, a novel ultrasonic fingerprint sensor was demonstrated using a 24x8 array of 22 MHz PMUTs with 100 microm pitch, fully integrated with 180 nm CMOS circuitry through eutectic wafer bonding. Each PMUT is directly bonded to a dedicated CMOS receive amplifier, minimizing electrical parasitics and eliminating the need for through-silicon vias. Pulse-echo imaging of a 1D steel grating is demonstrated using electronic scanning of a 20x8 sub-array, resulting in 300 mV maximum received amplitude and 5:1 contrast ratio. Because the small size of this array limits the maximum image size, mechanical scanning was used to image a 2D PDMS fingerprint phantom (10 mm by 8 mm) at a 1.2 mm distance from the array.

Investigating Degradation Mechanisms in 130 nm and 90 nm Commercial CMOS Technologies Under Extreme Radiation Conditions

NASA Astrophysics Data System (ADS)

Ratti, Lodovico; Gaioni, Luigi; Manghisoni, Massimo; Traversi, Gianluca; Pantano, Devis

2008-08-01

The purpose of this paper is to study the mechanisms underlying performance degradation in 130 nm and 90 nm commercial CMOS technologies exposed to high doses of ionizing radiation. The investigation has been mainly focused on their noise properties in view of applications to the design of low-noise, low-power analog circuits to be operated in harsh environment. Experimental data support the hypothesis that charge trapping in shallow trench isolation (STI), besides degrading the static characteristics of interdigitated NMOS transistors, also affects their noise performances in a substantial fashion. The model discussed in this paper, presented in a previous work focused on CMOS devices irradiated with a 10 Mrad(SiO2) gamma -ray dose, has been applied here also to transistors exposed to much higher (up to 100 Mrad(SiO2 )) doses of X-rays. Such a model is able to account for the extent of the observed noise degradation as a function of the device polarity, dimensions and operating point.

Fundamental Problems of Hybrid CMOS/Nanodevice Circuits

DTIC Science & Technology

2010-12-14

Development of an area-distributed CMOS/nanodevice interface We have carried out the first design of CMOS chips for the CMOS/nanodevice integration, and...got them fabricated in IBM’ 180-nm 7RF process (via MOSIS, Inc. silicon foundry). Each 44 mm2 chip assembly of the design consists of 4 component... chips , merged together for processing convenience. Each 22 mm2 component chip features two interface arrays, with 1010 vias each, with chip’s MOSFETs

SNR characteristics of 850-nm OEIC receiver with a silicon avalanche photodetector.

PubMed

Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

2014-01-13

We investigate signal-to-noise ratio (SNR) characteristics of an 850-nm optoelectronic integrated circuit (OEIC) receiver fabricated with standard 0.25-µm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. The OEIC receiver is composed of a Si avalanche photodetector (APD) and BiCMOS analog circuits including a transimpedance amplifier with DC-balanced buffer, a tunable equalizer, a limiting amplifier, and an output buffer with 50-Ω loads. We measure APD SNR characteristics dependence on the reverse bias voltage as well as BiCMOS circuit noise characteristics. From these, we determine the SNR characteristics of the entire OEIC receiver, and finally, the results are verified with bit-error rate measurement.

High-speed bipolar phototransistors in a 180 nm CMOS process.

PubMed

Kostov, P; Gaberl, W; Zimmermann, H

2013-03-01

Several high-speed pnp phototransistors built in a standard 180 nm CMOS process are presented. The phototransistors were implemented in sizes of 40×40 μm 2 and 100×100 μm 2 . Different base and emitter areas lead to different characteristics of the phototransistors. As starting material a p + wafer with a p - epitaxial layer on top was used. The phototransistors were optically characterized at wavelengths of 410, 675 and 850 nm. Bandwidths up to 92 MHz and dynamic responsivities up to 2.95 A/W were achieved. Evaluating the results, we can say that the presented phototransistors are well suited for high speed photosensitive optical applications where inherent amplification is needed. Further on, the standard silicon CMOS implementation opens the possibility for cheap integration of integrated optoelectronic circuits. Possible applications for the presented phototransistors are low cost high speed image sensors, opto-couplers, etc.

Compact Si-based asymmetric MZI waveguide on SOI as a thermo-optical switch

NASA Astrophysics Data System (ADS)

Rizal, C. S.; Niraula, B.

2018-03-01

A compact low power consuming asymmetric MZI based optical modulator with fast response time has been proposed on SOI platform. The geometrical and performance characteristics were analyzed in depth and optimized using coupled mode analysis and FDTD simulation tools, respectively. It was tested with and without implementation of thermo-optic (TO) effect. The device showed good frequency modulating characteristics when tested without the implementation of the TO effect. The fabricated device showed quality factor, Q ≈ 10,000, and this value is comparable to the Q of the device simulated with 25% transmission loss, showing FSR of 0.195 nm, FWHM ≈ 0.16 nm, and ER of 13 dB. With TO effect, it showed temperature sensitivity of 0.01 nm/°C and FSR of 0.19 nm. With the heater length of 4.18 mm, the device required 0.26 mW per π shift power with a switching voltage of 0.309 V, response time of 10 μ, and figure-of-merit of 2.6 mW μs. All of these characteristics make this device highly attractive for use in integrated Si photonics network as optical switch and wavelength modulator.

CMOS Ultralow Power Brain Signal Acquisition Front-Ends: Design and Human Testing.

PubMed

Karimi-Bidhendi, Alireza; Malekzadeh-Arasteh, Omid; Lee, Mao-Cheng; McCrimmon, Colin M; Wang, Po T; Mahajan, Akshay; Liu, Charles Yu; Nenadic, Zoran; Do, An H; Heydari, Payam

2017-08-01

Two brain signal acquisition (BSA) front-ends incorporating two CMOS ultralow power, low-noise amplifier arrays and serializers operating in mosfet weak inversion region are presented. To boost the amplifier's gain for a given current budget, cross-coupled-pair active load topology is used in the first stages of these two amplifiers. These two BSA front-ends are fabricated in 130 and 180 nm CMOS processes, occupying 5.45 mm 2 and 0.352 mm 2 of die areas, respectively (excluding pad rings). The CMOS 130-nm amplifier array is comprised of 64 elements, where each amplifier element consumes 0.216 μW from 0.4 V supply, has input-referred noise voltage (IRNoise) of 2.19 μV[Formula: see text] corresponding to a power efficiency factor (PEF) of 11.7, and occupies 0.044 mm 2 of die area. The CMOS 180 nm amplifier array employs 4 elements, where each element consumes 0.69 μW from 0.6 V supply with IRNoise of 2.3 μV[Formula: see text] (corresponding to a PEF of 31.3) and 0.051 mm 2 of die area. Noninvasive electroencephalographic and invasive electrocorticographic signals were recorded real time directly on able-bodied human subjects, showing feasibility of using these analog front-ends for future fully implantable BSA and brain- computer interface systems.

Fabrication and characterization of resonant SOI micromechanical silicon sensors based on DRIE micromachining, freestanding release process and silicon direct bonding

NASA Astrophysics Data System (ADS)

Gigan, Olivier; Chen, Hua; Robert, Olivier; Renard, Stephane; Marty, Frederic

2002-11-01

This paper is dedicated to the fabrication and technological aspect of a silicon microresonator sensor. The entire project includes the fabrication processes, the system modelling/simulation, and the electronic interface. The mechanical model of such resonator is presented including description of frequency stability and Hysterises behaviour of the electrostatically driven resonator. Numeric model and FEM simulations are used to simulate the system dynamic behaviour. The complete fabrication process is based on standard microelectronics technology with specific MEMS technological steps. The key steps are described: micromachining on SOI by Deep Reactive Ion Etching (DRIE), specific release processes to prevent sticking (resist and HF-vapour release process) and collective vacuum encapsulation by Silicon Direct Bonding (SDB). The complete process has been validated and prototypes have been fabricated. The ASIC was designed to interface the sensor and to control the vibration amplitude. This electronic was simulated and designed to work up to 200°C and implemented in a standard 0.6μ CMOS technology. Characterizations of sensor prototypes are done both mechanically and electrostatically. These measurements showed good agreements with theory and FEM simulations.

Heterojunction fully depleted SOI-TFET with oxide/source overlap

NASA Astrophysics Data System (ADS)

Chander, Sweta; Bhowmick, B.; Baishya, S.

2015-10-01

In this work, a hetero-junction fully depleted (FD) Silicon-on-Insulator (SOI) Tunnel Field Effect Transistor (TFET) nanostructure with oxide overlap on the Germanium-source region is proposed. Investigations using Synopsys Technology Computer Aided Design (TCAD) simulation tools reveal that the simple oxide overlap on the Germanium-source region increases the tunneling area as well as the tunneling current without degrading the band-to-band tunneling (BTBT) and improves the device performance. More importantly, the improvement is independent of gate overlap. Simulation study shows improvement in ON current, subthreshold swing (SS), OFF current, ION/IOFF ration, threshold voltage and transconductance. The proposed device with hafnium oxide (HfO2)/Aluminium Nitride (AlN) stack dielectric material offers an average subthreshold swing of 22 mV/decade and high ION/IOFF ratio (∼1010) at VDS = 0.4 V. Compared to conventional TFET, the Miller capacitance of the device shows the enhanced performance. The impact of the drain voltage variation on different parameters such as threshold voltage, subthreshold swing, transconductance, and ION/IOFF ration are also found to be satisfactory. From fabrication point of view also it is easy to utilize the existing CMOS process flows to fabricate the proposed device.

Toward athermal silicon-on-insulator (de)multiplexers in the O-band.

PubMed

Hassan, Karim; Sciancalepore, Corrado; Harduin, Julie; Ferrotti, Thomas; Menezo, Sylvie; Ben Bakir, Badhise

2015-06-01

We report on the design, fabrication, and characterization of a 1×4 silicon-on-insulator (SOI) demultiplexer exhibiting a significant reduction of its thermo-optical sensitivity in the O-band. The optical filtering is achieved by cascading several Mach-Zehnder interferometers (MZIs) fabricated on a 300-nm-thick SOI platform. Owing to an asymmetric design of the confinement for each MZIs, we found an athermal criterium that satisfies the spectral requirements. The thermal sensitivity of the structure is analyzed by a semi-analytical model in order to create an athermal multiplexer. Fiber-to-fiber thermo-optical testing reveals a thermal sensitivity of around 17  pm/°C reduced by 75% compared to the standard devices with promising performances for both the crosstalk (15 dB), the insertion losses (4 dB), and absolute lambda registration (<0.25  nm).

Area-Efficient 60 GHz +18.9 dBm Power Amplifier with On-Chip Four-Way Parallel Power Combiner in 65-nm CMOS

NASA Astrophysics Data System (ADS)

Farahabadi, Payam Masoumi; Basaligheh, Ali; Saffari, Parvaneh; Moez, Kambiz

2017-06-01

This paper presents a compact 60-GHz power amplifier utilizing a four-way on-chip parallel power combiner and splitter. The proposed topology provides the capability of combining the output power of four individual power amplifier cores in a compact die area. Each power amplifier core consists of a three-stage common-source amplifier with transformer-coupled impedance matching networks. Fabricated in 65-nm CMOS process, the measured gain of the 0.19-mm2 power amplifier at 60 GHz is 18.8 and 15 dB utilizing 1.4 and 1.0 V supply. Three-decibel band width of 4 GHz and P1dB of 16.9 dBm is measured while consuming 424 mW from a 1.4-V supply. A maximum saturated output power of 18.3 dBm is measured with the 15.9% peak power added efficiency at 60 GHz. The measured insertion loss is 1.9 dB at 60 GHz. The proposed power amplifier achieves the highest power density (power/area) compared to the reported 60-GHz CMOS power amplifiers in 65 nm or older CMOS technologies.

A low jitter all - digital phase - locked loop in 180 nm CMOS technology

NASA Astrophysics Data System (ADS)

Shumkin, O. V.; Butuzov, V. A.; Normanov, D. D.; Ivanov, P. Yu

2016-02-01

An all-digital phase locked loop (ADPLL) was implemented in 180 nm CMOS technology. The proposed ADPLL uses a digitally controlled oscillator to achieve 3 ps resolution. The pure digital phase locked loop is attractive because it is less sensitive to noise and operating conditions than its analog counterpart. The proposed ADPLL can be easily applied to different process as a soft IP block, making it very suitable for system-on-chip applications.

Engineered SOI slot waveguide ring resonator V-shape resonance combs for refraction index sensing up to 1300nm/RIU (Conference Presentation)

NASA Astrophysics Data System (ADS)

Zhang, Weiwei; Serna, Samuel; Le Roux, Xavier; Vivien, Laurent; Cassan, Eric

2016-05-01

Bio-detection based on CMOS technology boosts the miniaturization of detection systems and the success on highly efficient, robust, accurate, and low coast Lab-on-Chip detection schemes. Such on chip detection technologies have covered healthy related harmful gases, bio-chemical analytes, genetic micro RNA, etc. Their monitoring accuracy is mainly qualified in terms of sensitivity and limit of the detection (LOD) of the detection system. In this context, recently developed silicon on insulator (SOI) optical devices have displayed highly performant detection abilities that LOD could go beyond 10-8RIU and sensitivity could exceeds 103nm/RIU. The SOI integrated optical sensing devices include strip/slotted waveguide consisting in structures like Mach-Zehnder interferometers (MZI), ring resonators (RR), nano cavities, etc. Typically, hollow core RR and nano-cavities could exhibit higher sensitivity due to their optical mode confinement properties with a partial localization of the electric field in low index sensing regions than devices based on evanescent field tails outside of the optical cores. Furthermore, they also provide larger sensing areas for surface functionalization to reach higher sensitivities and lower LODs. The state of art of hollow core devices, either based on Bragg gratings formed from a slot waveguide cavity or photonic crystal slot cavities, show sensitivities (S) up to 400nm/RIU and Figure of Merit (FOM) around 3,000 in water environment, FOM being defined as the inverse of LOD and precisely as FOM=SQ/λ, with λ the resonance wavelength and Q the quality factor of the considered resonator. Such high achieved FOMs in nano cavities are mainly due to their large Q factors around 15,000. While for mostly used RR, which do not require particular design strategies, relatively low Q factors around 1800 in water are met and moderate sensitivities about 300nm/RIU are found. In this work, we present here a novel slot ring resonator design to make breakthrough of the performance of slot ring resonator sensing ability. Different from the normal sensing regime by monitoring one specific resonance (λres) peak shift, the proposed approach stems from the sensitivity of the RR critical coupling. The critical coupling peak is auto-selected out by matching the following condition: the ring resonator's round trip attenuation coefficient a(λ) being equal to the coupler self-coupling coefficient k(λ), thus resulting in the deepest extinction ratio (ER) among the spectrum RR comb. The obtained sensing comb, based on a V-shape spectrum envelop, is engineered by controlling a(λ) and k(λ) with opposite monotonicities. Both a(λ)and k(λ) are tuned to have a large dispersion along the wavelength, which means that |a(λ)-k(λ)| keeps rapidly increasing as λres is far away from λc, eliminating the resonance ER quickly down to 0. Experimentally, slot waveguide ring resonators with a radius of 50µm have been fabricated on a standard silicon platform with a Si thickness of 220nm, loaded by racetrack couplers with a straight coupling length of 20µm. Sensing experiments have been carried out by changing the top cladding material from a series of Cargille optical liquids with refraction index values ranging from 1.3 to 1.5. The Q factors of critical coupling resonances was monitored from 2,000 to 6,000, and measured wavelength shifts of this peak are from 1.41µm to 1.56µm. The maximum sensitivity of 1300nm/RIU is observed in the cladding index range 1.30-1.35. To conclude, a new sensing regime by tracking the critical coupling resonance λc of slot waveguide ring resonators is demonstrated. The reported sensitivity is up 1300nm/RIU around the water RI of 1.33, and the monitored sensing FOM is about 2300, which is very close to the FOM values achieved from nanobeam cavities. This work can thus contribute to future integrated optical sensing schemes based on slot RRs.

A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System.

PubMed

Current, K W; Yuk, K; McConaghy, C; Gascoyne, P R C; Schwartz, J A; Vykoukal, J V; Andrews, C

2007-06-01

A high-voltage (HV) integrated circuit has been demonstrated to transport fluidic droplet samples on programmable paths across the array of driving electrodes on its hydrophobically coated surface. This exciter chip is the engine for dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip systems, creating field excitations that inject and move fluidic droplets onto and about the manipulation surface. The architecture of this chip is expandable to arrays of N X N identical HV electrode driver circuits and electrodes. The exciter chip is programmable in several senses. The routes of multiple droplets may be set arbitrarily within the bounds of the electrode array. The electrode excitation waveform voltage amplitude, phase, and frequency may be adjusted based on the system configuration and the signal required to manipulate a particular fluid droplet composition. The voltage amplitude of the electrode excitation waveform can be set from the minimum logic level up to the maximum limit of the breakdown voltage of the fabrication technology. The frequency of the electrode excitation waveform can also be set independently of its voltage, up to a maximum depending upon the type of droplets that must be driven. The exciter chip can be coated and its oxide surface used as the droplet manipulation surface or it can be used with a top-mounted, enclosed fluidic chamber consisting of a variety of materials. The HV capability of the exciter chip allows the generated DEP forces to penetrate into the enclosed chamber region and an adjustable voltage amplitude can accommodate a variety of chamber floor thicknesses. This demonstration exciter chip has a 32 x 32 array of nominally 100 V electrode drivers that are individually programmable at each time point in the procedure to either of two phases: 0deg and 180deg with respect to the reference clock. For this demonstration chip, while operating the electrodes with a 100-V peak-to-peak periodic waveform, the maximum HV electrode waveform frequency is about 200 Hz; and standard 5-V CMOS logic data communication rate is variable up to 250 kHz. This HV demonstration chip is fabricated in a 130-V 1.0-mum SOI CMOS fabrication technology, dissipates a maximum of 1.87 W, and is about 10.4 mm x 8.2 mm.

Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

PubMed Central

Huang, Yue; Mason, Andrew J.

2013-01-01

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Lab-on-CMOS integration of microfluidics and electrochemical sensors.

PubMed

Huang, Yue; Mason, Andrew J

2013-10-07

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

Stopping electric field extension in a modified nanostructure based on SOI technology - A comprehensive numerical study

NASA Astrophysics Data System (ADS)

Anvarifard, Mohammad K.; Orouji, Ali A.

2017-11-01

This article has related a particular knowledge in order to reduce short channel effects (SCEs) in nano-devices based on silicon-on-insulator (SOI) MOSFETs. The device under study has been designed in 22 nm node technology with embedding Si3N4 extra oxide as a stopping layer of electric field and a useful heatsink for transferring generated heat. Two important subjects (DC characteristics and RF characteristics) have been investigated, simultaneously. Stopping electric field extension and enhancement of channel thermal conduction are introduced as an entrance gateway for this work so that improve the electrical characteristics, eventually. The inserted extra oxide made by the Si3N4 material has a vital impact on the modification of the electrical and thermal features in the proposed device. An immense comparison between the proposed SOI and conventional SOI showed that the proposed structure has higher electrical and thermal proficiency than the conventional structure in terms of main parameters such as short channel effects (SCEs), leakage current, floating body effect (FBE), self-heating effect (SHE), voltage gain, ratio of On-current to Off- current, transconductance, output conductance, minimum noise figure and power gain.

Analog 65/130 nm CMOS 5 GHz Sub-Arrays with ROACH-2 FPGA Beamformers for Hybrid Aperture-Array Receivers

DTIC Science & Technology

2017-03-20

sub-array, which is based on all-pass filters (APFs) is realized using 130 nm CMOS technology. Approximate- discrete Fourier transform (a-DFT...fixed beams are directed at known directions [9]. The proposed approximate- discrete Fourier transform (a-DFT) based multi-beamformer [9] yields L...to digital conversion daughter board. occurs in the discrete time domain (in ROACH-2 FPGA platform) following signal digitization (see Figs. 1(d) and

FDSOI 28nm performances study for RF energy scavenging

NASA Astrophysics Data System (ADS)

Rochefeuille, E.; Alicalapa, F.; Douyère, A.; Vuong, T. P.

2018-03-01

This paper presents a study on an integrated technology: Fully-Depleted-Silicon-On-Insulator (FDSOI) at a 28nm node. FDSOI results are compared to another technology: Complementary-Metal-Oxide-Semiconductor (CMOS) 350nm. The aim of this work was to demonstrate the advantages of using FDSOI technology in RF energy scavenging applications. Characteristics of transistors are pointed out and results showed an improved 22%-output voltage gain for a series rectifier and a 13%-output voltage gain for a Dickson charge pump in FDSOI technology compared to CMOS, for an input voltage and power of 0.5 V and 0 dBm respectively. Those results allowed to prove that FDSOI 28nm is a better technology choice for energy scavenging and low-power applications.

The DUV Stability of Superlattice-Doped CMOS Detector Arrays

NASA Technical Reports Server (NTRS)

Hoenk, M. E.; Carver, A. G.; Jones, T.; Dickie, M.; Cheng, P.; Greer, H. F.; Nikzad, S.; Sgro, J.; Tsur, S.

2013-01-01

JPL and Alacron have recently developed a high performance, DUV camera with a superlattice doped CMOS imaging detector. Supperlattice doped detectors achieve nearly 100% internal quantum efficiency in the deep and far ultraviolet, and a single layer, Al2O3 antireflection coating enables 64% external quantum efficiency at 263nm. In lifetime tests performed at Applied Materials using 263 nm pulsed, solid state and 193 nm pulsed excimer laser, the quantum efficiency and dark current of the JPL/Alacron camera remained stable to better than 1% precision during long-term exposure to several billion laser pulses, with no measurable degradation, no blooming and no image memory at 1000 fps.

Nano-patterned visible wavelength filter integrated with an image sensor exploiting a 90-nm CMOS process

NASA Astrophysics Data System (ADS)

Yoon, Yeo-Taek; Lee, Sang-Shin; Lee, Byoung-Su

2012-01-01

A highly efficient visible wavelength filter enabling a homogeneous integration with an image sensor was proposed and manufactured by employing a standard 90-nm CMOS process. A one dimensional subwavelength Al grating overlaid with an oxide film was built on top of an image sensor to serve as a low-pass wavelength filter; a microlens was then formed atop the filter to achieve beam focusing. The structural parameters for the filter were: a grating pitch of 300 nm, a grating height of 170 nm, and a 150-nm thick oxide overlay. The overall transmission was observed to reach up to 80% in the visible band with a decent roll-off near ∼700 nm. Finally, the discrepancy between the observed and calculated result was accounted for by appropriately modeling the implemented metallic grating structure, accompanying an undercut sidewall.

A 2.87 ppm/°C 65 nm CMOS bandgap reference with nonlinearity compensation

NASA Astrophysics Data System (ADS)

Xingyuan, Tong; Zhangming, Zhu; Yintang, Yang

2011-09-01

Based on the review and analysis of two recently reported low temperature coefficient (TC) bandgap voltage references (BGRs), a new temperature compensation technique is presented. With the double-end piecewise nonlinearity correction method, the logarithm cancellation technique and the mixed-mode output topology, a BGR with high-temperature stability is realised based on 65 nm CMOS low-leakage process. The post-simulation results using Spectre show that this BGR produces an output voltage of about 953 mV with 2.5 V supply voltage, and the output voltage varies by only 0.16 mV from -40°C to 125°C. This low TC BGR has been used in a 65 nm CMOS touch screen controller, and the measurement shows that the output voltage of this BGR is about 949 mV varying by 0.44 mV from -40°C to 125°C. The TC of this BGR is about 2.87 ppm/°C, meeting the requirement of high-precision SoC application.

Optical properties of new wide heterogeneous waveguides with thermo optical shifters.

PubMed

De Leonardis, Francesco; Tsarev, Andrei V; Passaro, Vittorio M

2008-12-22

We present analysis and simulation of novel silicon-on-insulator (SOI) heterogeneous waveguides with thermo-optic phase shifters. New structure design contains a p-n junction on both sides of SOI ridge waveguide with 220 nm x 35 microm silicon core. Strongly mode-dependent optical losses (by additional free charge absorption) provide quasi-singe-mode behavior of wide waveguide with mode size approximately 10 microm. Local heater produces an efficient phase shifting by small temperature increase (DeltaT approximately 2K), switching power (< 40 mW) and switching time (< 10 micros). Mode optical losses are significantly decreased at high heating (DeltaT approximately 120 K).

PAM4 silicon photonic microring resonator-based transceiver circuits

NASA Astrophysics Data System (ADS)

Palermo, Samuel; Yu, Kunzhi; Roshan-Zamir, Ashkan; Wang, Binhao; Li, Cheng; Seyedi, M. Ashkan; Fiorentino, Marco; Beausoleil, Raymond

2017-02-01

Increased data rates have motivated the investigation of advanced modulation schemes, such as four-level pulseamplitude modulation (PAM4), in optical interconnect systems in order to enable longer transmission distances and operation with reduced circuit bandwidth relative to non-return-to-zero (NRZ) modulation. Employing this modulation scheme in interconnect architectures based on high-Q silicon photonic microring resonator devices, which occupy small area and allow for inherent wavelength-division multiplexing (WDM), offers a promising solution to address the dramatic increase in datacenter and high-performance computing system I/O bandwidth demands. Two ring modulator device structures are proposed for PAM4 modulation, including a single phase shifter segment device driven with a multi-level PAM4 transmitter and a two-segment device driven by two simple NRZ (MSB/LSB) transmitters. Transmitter circuits which utilize segmented pulsed-cascode high swing output stages are presented for both device structures. Output stage segmentation is utilized in the single-segment device design for PAM4 voltage level control, while in the two-segment design it is used for both independent MSB/LSB voltage levels and impedance control for output eye skew compensation. The 65nm CMOS transmitters supply a 4.4Vppd output swing for 40Gb/s operation when driving depletion-mode microring modulators implemented in a 130nm SOI process, with the single- and two-segment designs achieving 3.04 and 4.38mW/Gb/s, respectively. A PAM4 optical receiver front-end is also described which employs a large input-stage feedback resistor transimpedance amplifier (TIA) cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE) for improved sensitivity. Receiver linearity, critical in PAM4 systems, is achieved with a peak-detector-based automatic gain control (AGC) loop.

Top-down nanofabrication of silicon nanoribbon field effect transistor (Si-NR FET) for carcinoembryonic antigen detection.

PubMed

Bao, Zengtao; Sun, Jialin; Zhao, Xiaoqian; Li, Zengyao; Cui, Songkui; Meng, Qingyang; Zhang, Ye; Wang, Tong; Jiang, Yanfeng

2017-01-01

Sensitive and quantitative detection of tumor markers is highly required in the clinic for cancer diagnosis and consequent treatment. A field-effect transistor-based (FET-based) nanobiosensor emerges with characteristics of being label-free, real-time, having high sensitivity, and providing direct electrical readout for detection of biomarkers. In this paper, a top-down approach is proposed and implemented to fulfill a novel silicon nano-ribbon FET, which acts as biomarker sensor for future clinical application. Compared with the bottom-up approach, a top-down fabrication approach can confine width and length of the silicon FET precisely to control its electrical properties. The silicon nanoribbon (Si-NR) transistor is fabricated on a Silicon-on-Insulator (SOI) substrate by a top-down approach with complementary metal oxide semiconductor (CMOS)-compatible technology. After the preparation, the surface of Si-NR is functionalized with 3-aminopropyltriethoxysilane (APTES). Glutaraldehyde is utilized to bind the amino terminals of APTES and antibody on the surface. Finally, a microfluidic channel is integrated on the top of the device, acting as a flowing channel for the carcinoembryonic antigen (CEA) solution. The Si-NR FET is 120 nm in width and 25 nm in height, with ambipolar electrical characteristics. A logarithmic relationship between the changing ratio of the current and the CEA concentration is measured in the range of 0.1-100 ng/mL. The sensitivity of detection is measured as 10 pg/mL. The top-down fabricated biochip shows feasibility in direct detecting of CEA with the benefits of real-time, low cost, and high sensitivity as a promising biosensor for tumor early diagnosis.

The design and hardware implementation of a low-power real-time seizure detection algorithm

NASA Astrophysics Data System (ADS)

Raghunathan, Shriram; Gupta, Sumeet K.; Ward, Matthew P.; Worth, Robert M.; Roy, Kaushik; Irazoqui, Pedro P.

2009-10-01

Epilepsy affects more than 1% of the world's population. Responsive neurostimulation is emerging as an alternative therapy for the 30% of the epileptic patient population that does not benefit from pharmacological treatment. Efficient seizure detection algorithms will enable closed-loop epilepsy prostheses by stimulating the epileptogenic focus within an early onset window. Critically, this is expected to reduce neuronal desensitization over time and lead to longer-term device efficacy. This work presents a novel event-based seizure detection algorithm along with a low-power digital circuit implementation. Hippocampal depth-electrode recordings from six kainate-treated rats are used to validate the algorithm and hardware performance in this preliminary study. The design process illustrates crucial trade-offs in translating mathematical models into hardware implementations and validates statistical optimizations made with empirical data analyses on results obtained using a real-time functioning hardware prototype. Using quantitatively predicted thresholds from the depth-electrode recordings, the auto-updating algorithm performs with an average sensitivity and selectivity of 95.3 ± 0.02% and 88.9 ± 0.01% (mean ± SEα = 0.05), respectively, on untrained data with a detection delay of 8.5 s [5.97, 11.04] from electrographic onset. The hardware implementation is shown feasible using CMOS circuits consuming under 350 nW of power from a 250 mV supply voltage from simulations on the MIT 180 nm SOI process.

Compact polarization beam splitter for silicon photonic integrated circuits with a 340-nm-thick silicon core layer.

PubMed

Li, Chenlei; Dai, Daoxin

2017-11-01

A polarization beam splitter (PBS) is proposed and realized for silicon photonic integrated circuits with a 340-nm-thick silicon core layer by introducing an asymmetric directional coupler (ADC), which consists of a silicon-on-insulator (SOI) nanowire and a subwavelength grating (SWG) waveguide. The SWG is introduced to provide an optical waveguide which has much higher birefringence than a regular 340-nm-thick SOI nanowire, so that it is possible to make the phase-matching condition satisfied for TE polarization only in the present design when the waveguide dimensions are optimized. Meanwhile, there is a significant phase mismatching for TM polarization automatically. In this way, the present ADC enables strong polarization selectivity to realize a PBS that separates TE and TM polarizations to the cross and through ports, respectively. The realized PBS has a length of ∼2  μm for the coupling region. For the fabricated PBS, the extinction ratio (ER) is 15-30 dB and the excess loss is 0.2-2.6 dB for TE polarization while the ER is 20-27 dB and the excess loss is 0.3-2.8 dB for TM polarization when operating in the wavelength range of 1520-1580 nm.

Formation of SIMOX-SOI structure by high-temperature oxygen implantation

NASA Astrophysics Data System (ADS)

Hoshino, Yasushi; Kamikawa, Tomohiro; Nakata, Jyoji

2015-12-01

We have performed oxygen ion implantation in silicon at very high substrate-temperatures (⩽1000 °C) for the purpose of forming silicon-on-insulator (SOI) structure. We have expected that the high-temperature implantation can effectively avoids ion-beam-induced damages in the SOI layer and simultaneously stabilizes the buried oxide (BOX) and SOI-Si layer. Such a high-temperature implantation makes it possible to reduce the post-implantation annealing temperature. In the present study, oxygen ions with 180 keV are incident on Si(0 0 1) substrates at various temperatures from room temperature (RT) up to 1000 °C. The ion-fluencies are in order of 1017-1018 ions/cm2. Samples have been analyzed by atomic force microscope, Rutherford backscattering, and micro-Raman spectroscopy. It is found in the AFM analysis that the surface roughness of the samples implanted at 500 °C or below are significantly small with mean roughness of less than 1 nm, and gradually increased for the 800 °C-implanted sample. On the other hand, a lot of dents are observed for the 1000 °C-implanted sample. RBS analysis has revealed that stoichiometric SOI-Si and BOX-SiO2 layers are formed by oxygen implantation at the substrate temperatures of RT, 500, and 800 °C. However, SiO2-BOX layer has been desorbed during the implantation. Raman spectra shows that the ion-beam-induced damages are fairly suppressed by such a high-temperatures implantation.

Application of CMOS Technology to Silicon Photomultiplier Sensors.

PubMed

D'Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

2017-09-25

We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments.

Broadband image sensor array based on graphene-CMOS integration

NASA Astrophysics Data System (ADS)

Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

2017-06-01

Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Greene, Brian Joseph

Thin film silicon on insulator fabrication is an increasingly important technology requirement for improving performance in future generation devices and circuits. One process for SOI fabrication that has recently been generating renewed interest is Lateral Solid Phase Epitaxy (LSPE) of silicon over oxide. This process involves annealing amorphous silicon that has been deposited on oxide patterned Si wafers. The (001) Si substrate forms the crystalline seed for epitaxial growth, permitting the generation of Si films that are both single crystal, and oriented to the substrate. This method is particularly attractive to fabrication that requires low temperature processing, because the Si films are deposited in the amorphous phase at temperatures near 525°C, and crystallized at temperatures near 570°C. It is also attractive for applications requiring three dimensional stacking of active silicon device layers, due to the relatively low temperatures involved. For sub-50 nm gate length MOSFET fabrication, an SOI thickness on the order of 10 nm will be required. One limitation of the LSPE process has been the need for thick films (0.5--2 mum) and/or heavy P doping (10 19--1020 cm-3) to increase the maximum achievable lateral growth distance, and therefore minimize the area on the substrate occupied by seed holes. This dissertation discusses the characterization and optimization of process conditions for large area LSPE silicon film growth, as well as efforts to adapt the traditional LSPE process to achieve ultra-thin SOI layers (Tsilicon ≤ 25 nm) while avoiding the use of heavy active doping layers. MOSFETs fabricated in these films that exhibit electron mobility comparable to the Universal Si MOS Mobility are described.

Defect Characterization in SiGe/SOI Epitaxial Semiconductors by Positron Annihilation

PubMed Central

2010-01-01

The potential of positron annihilation spectroscopy (PAS) for defect characterization at the atomic scale in semiconductors has been demonstrated in thin multilayer structures of SiGe (50 nm) grown on UTB (ultra-thin body) SOI (silicon-on-insulator). A slow positron beam was used to probe the defect profile. The SiO2/Si interface in the UTB-SOI was well characterized, and a good estimation of its depth has been obtained. The chemical analysis indicates that the interface does not contain defects, but only strongly localized charged centers. In order to promote the relaxation, the samples have been submitted to a post-growth annealing treatment in vacuum. After this treatment, it was possible to observe the modifications of the defect structure of the relaxed film. Chemical analysis of the SiGe layers suggests a prevalent trapping site surrounded by germanium atoms, presumably Si vacancies associated with misfit dislocations and threading dislocations in the SiGe films. PMID:21170391

A 205GHz Amplifier in 90nm CMOS Technology

DTIC Science & Technology

2017-03-01

San Jose State University San Jose, CA, USA       Abstract: This paper presents a 205GHz amplifier drawing 43.4mA from a 0.9V power supply with...10.5dB power gain, Psat of -1.6dBm, and P1dB ≈ -5.8dBm in a standard 90nm CMOS process. Moreover, the design employs internal (layout-based) /external...reported in [2]. In this paper, two neutralization techniques, internal and external approaches, have been implemented to achieve higher power

A 2x2 W-Band Reference Time-Shifted Phase-Locked Transmitter Array in 65nm CMOS Technology

NASA Technical Reports Server (NTRS)

Tang, Adrian; Virbila, Gabriel; Hsiao, Frank; Wu, Hao; Murphy, David; Mehdi, Imran; Siegel, P. H.; Chang, M-C. Frank

2013-01-01

This paper presents a complete 2x2 phased array transmitter system operating at W-band (90-95 GHz) which employs a PLL reference time-shifting approach instead of using traditional mm-wave phase shifters. PLL reference shifting enables a phased array to be distributed over multiple chips without the need for coherent mm-wave signal distribution between chips. The proposed phased array transmitter system consumes 248 mW per array element when implemented in a 65 nm CMOS technology.

Transparent, Flexible Silicon Nanostructured Wire Networks with Seamless Junctions for High-Performance Photodetector Applications.

PubMed

Hossain, Mozakkar; Kumar, Gundam Sandeep; Barimar Prabhava, S N; Sheerin, Emmet D; McCloskey, David; Acharya, Somobrata; Rao, K D M; Boland, John J

2018-05-22

Optically transparent photodetectors are crucial in next-generation optoelectronic applications including smart windows and transparent image sensors. Designing photodetectors with high transparency, photoresponsivity, and robust mechanical flexibility remains a significant challenge, as is managing the inevitable trade-off between high transparency and strong photoresponse. Here we report a scalable method to produce flexible crystalline Si nanostructured wire (NW) networks fabricated from silicon-on-insulator (SOI) with seamless junctions and highly responsive porous Si segments that combine to deliver exceptional performance. These networks show high transparency (∼92% at 550 nm), broadband photodetection (350 to 950 nm) with excellent responsivity (25 A/W), optical response time (0.58 ms), and mechanical flexibility (1000 cycles). Temperature-dependent photocurrent measurements indicate the presence of localized electronic states in the porous Si segments, which play a crucial role in light harvesting and photocarrier generation. The scalable low-cost approach based on SOI has the potential to deliver new classes of flexible optoelectronic devices, including next-generation photodetectors and solar cells.

Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schmid, H., E-mail: sih@zurich.ibm.com; Borg, M.; Moselund, K.

2015-06-08

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400 cm{sup 2}/V s, while the alongsidemore » fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at V{sub DS} = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneous material integration on Si.« less

Methods of producing strain in a semiconductor waveguide and related devices

DOEpatents

Cox, Johathan Albert; Rakich, Peter Thomas

2016-02-16

Quasi-phase matched (QPM), semiconductor photonic waveguides include periodically-poled alternating first and second sections. The first sections exhibit a high degree of optical coupling (abbreviated "X.sup.2"), while the second sections have a low X.sup.2. The alternating first and second sections may comprise high-strain and low-strain sections made of different material states (such as crystalline and amorphous material states) that exhibit high and low X.sup.2 properties when formed on a particular substrate, and/or strained corrugated sections of different widths. The QPM semiconductor waveguides may be implemented as silicon-on-insulator (SOI), or germanium-on-silicon structures compatible with standard CMOS processes, or as silicon-on-sapphire (SOS) structures.

Design of CMOS compatible and compact, thermally-compensated electro-optic modulator based on off-axis microring resonator for dense wavelength division multiplexing applications.

PubMed

Haldar, Raktim; Banik, Abhik D; Varshney, Shailendra K

2014-09-22

In this work, we propose and demonstrate the performance of silicon-on-insulator (SOI) off-axis microring resonator (MRR) as electro-optic modulator (EOM). Adding an extra off-axis inner-ring in conventional microring structure provides control to compensate thermal effects on EOM. It is shown that dynamically controlled bias-voltage applied to the outer ring has the potency to quell the thermal effects over a wide range of temperature. Thus, besides the appositely biased conventional microring, off-axis inner microring with pre-emphasized electrical input message signal enables our proposed structure suitable for high data-rate dense wavelength division multiplexing scheme of optical communication within a very compact device size.

Application of CMOS Technology to Silicon Photomultiplier Sensors

PubMed Central

D’Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

2017-01-01

We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments. PMID:28946675

Development of monolithic pixel detector with SOI technology for the ILC vertex detector

NASA Astrophysics Data System (ADS)

Yamada, M.; Ono, S.; Tsuboyama, T.; Arai, Y.; Haba, J.; Ikegami, Y.; Kurachi, I.; Togawa, M.; Mori, T.; Aoyagi, W.; Endo, S.; Hara, K.; Honda, S.; Sekigawa, D.

2018-01-01

We have been developing a monolithic pixel sensor for the International Linear Collider (ILC) vertex detector with the 0.2 μm FD-SOI CMOS process by LAPIS Semiconductor Co., Ltd. We aim to achieve a 3 μm single-point resolution required for the ILC with a 20×20 μm2 pixel. Beam bunch crossing at the ILC occurs every 554 ns in 1-msec-long bunch trains with an interval of 200 ms. Each pixel must record the charge and time stamp of a hit to identify a collision bunch for event reconstruction. Necessary functions include the amplifier, comparator, shift register, analog memory and time stamp implementation in each pixel, and column ADC and Zero-suppression logic on the chip. We tested the first prototype sensor, SOFIST ver.1, with a 120 GeV proton beam at the Fermilab Test Beam Facility in January 2017. SOFIST ver.1 has a charge sensitive amplifier and two analog memories in each pixel, and an 8-bit Wilkinson-type ADC is implemented for each column on the chip. We measured the residual of the hit position to the reconstructed track. The standard deviation of the residual distribution fitted by a Gaussian is better than 3 μm.

Design of novel SOI 1 × 4 optical power splitter using seven horizontally slotted waveguides

NASA Astrophysics Data System (ADS)

Katz, Oded; Malka, Dror

2017-07-01

In this paper, we demonstrate a compact silicon on insulator (SOI) 1 × 4 optical power splitter using seven horizontal slotted waveguides. Aluminum nitride (AIN) surrounded by silicon (Si) was used to confine the optical field in the slot region. All of the power analysis has been done in transverse magnetic (TM) polarization mode and a compact optical power splitter as short as 14.5 μm was demonstrated. The splitter was designed by using full vectorial beam propagation method (FV-BPM) simulations. Numerical investigations show that this device can work across the whole C-band (1530-1565 nm) with excess loss better than 0.23 dB.

CMOS chip planarization by chemical mechanical polishing for a vertically stacked metal MEMS integration

NASA Astrophysics Data System (ADS)

Lee, Hocheol; Miller, Michele H.; Bifano, Thomas G.

2004-01-01

In this paper we present the planarization process of a CMOS chip for the integration of a microelectromechanical systems (MEMS) metal mirror array. The CMOS chip, which comes from a commercial foundry, has a bumpy passivation layer due to an underlying aluminum interconnect pattern (1.8 µm high), which is used for addressing individual micromirror array elements. To overcome the tendency for tilt error in the CMOS chip planarization, the approach is to sputter a thick layer of silicon nitride at low temperature and to surround the CMOS chip with dummy silicon pieces that define a polishing plane. The dummy pieces are first lapped down to the height of the CMOS chip, and then all pieces are polished. This process produced a chip surface with a root-mean-square flatness error of less than 100 nm, including tilt and curvature errors.

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity

PubMed Central

Zhang, Fan; Niu, Hanben

2016-01-01

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 107 when illuminated by a 405-nm diode laser and 1/1.4 × 104 when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e− rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena. PMID:27367699

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity.

PubMed

Zhang, Fan; Niu, Hanben

2016-06-29

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 10⁷ when illuminated by a 405-nm diode laser and 1/1.4 × 10⁴ when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e(-) rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena.

System-level analysis and design for RGB-NIR CMOS camera

NASA Astrophysics Data System (ADS)

Geelen, Bert; Spooren, Nick; Tack, Klaas; Lambrechts, Andy; Jayapala, Murali

2017-02-01

This paper presents system-level analysis of a sensor capable of simultaneously acquiring both standard absorption based RGB color channels (400-700nm, 75nm FWHM), as well as an additional NIR channel (central wavelength: 808 nm, FWHM: 30nm collimated light). Parallel acquisition of RGB and NIR info on the same CMOS image sensor is enabled by monolithic pixel-level integration of both a NIR pass thin film filter and NIR blocking filters for the RGB channels. This overcomes the need for a standard camera-level NIR blocking filter to remove the NIR leakage present in standard RGB absorption filters from 700-1000nm. Such a camera-level NIR blocking filter would inhibit the acquisition of the NIR channel on the same sensor. Thin film filters do not operate in isolation. Rather, their performance is influenced by the system context in which they operate. The spectral distribution of light arriving at the photo diode is shaped a.o. by the illumination spectral profile, optical component transmission characteristics and sensor quantum efficiency. For example, knowledge of a low quantum efficiency (QE) of the CMOS image sensor above 800nm may reduce the filter's blocking requirements and simplify the filter structure. Similarly, knowledge of the incoming light angularity as set by the objective lens' F/# and exit pupil location may be taken into account during the thin film's optimization. This paper demonstrates how knowledge of the application context can facilitate filter design and relax design trade-offs and presents experimental results.

Design of a compact CMOS-compatible photonic antenna by topological optimization.

PubMed

Pita, Julián L; Aldaya, Ivan; Dainese, Paulo; Hernandez-Figueroa, Hugo E; Gabrielli, Lucas H

2018-02-05

Photonic antennas are critical in applications such as spectroscopy, photovoltaics, optical communications, holography, and sensors. In most of those applications, metallic antennas have been employed due to their reduced sizes. Nevertheless, compact metallic antennas suffer from high dissipative loss, wavelength-dependent radiation pattern, and they are difficult to integrate with CMOS technology. All-dielectric antennas have been proposed to overcome those disadvantages because, in contrast to metallic ones, they are CMOS-compatible, easier to integrate with typical silicon waveguides, and they generally present a broader wavelength range of operation. These advantages are achieved, however, at the expense of larger footprints that prevent dense integration and their use in massive phased arrays. In order to overcome this drawback, we employ topological optimization to design an all-dielectric compact antenna with vertical emission over a broad wavelength range. The fabricated device has a footprint of 1.78 µm × 1.78 µm and shows a shift in the direction of its main radiation lobe of only 4° over wavelengths ranging from 1470 nm to 1550 nm and a coupling efficiency bandwidth broader than 150 nm.

Mach-Zehnder Interferometer Biochemical Sensor Based on Silicon-on-Insulator Rib Waveguide with Large Cross Section

PubMed Central

Yuan, Dengpeng; Dong, Ying; Liu, Yujin; Li, Tianjian

2015-01-01

A high-sensitivity Mach-Zehnder interferometer (MZI) biochemical sensing platform based on Silicon-in-insulator (SOI) rib waveguide with large cross section is proposed in this paper. Based on the analyses of the evanescent field intensity, the mode polarization and cross section dimensions of the SOI rib waveguide are optimized through finite difference method (FDM) simulation. To realize high-resolution MZI read-out configuration based on the SOI rib waveguide, medium-filled trenches are employed and their performances are simulated through two-dimensional finite-difference-time domain (2D-FDTD) method. With the fundamental EH-polarized mode of the SOI rib waveguide with a total rib height of 10 μm, an outside rib height of 5 μm and a rib width of 2.5 μm at the operating wavelength of 1550 nm, when the length of the sensitive window in the MZI configuration is 10 mm, a homogeneous sensitivity of 7296.6%/refractive index unit (RIU) is obtained. Supposing the resolutions of the photoelectric detectors connected to the output ports are 0.2%, the MZI sensor can achieve a detection limit of 2.74 × 10−6 RIU. Due to high coupling efficiency of SOI rib waveguide with large cross section with standard single-mode glass optical fiber, the proposed MZI sensing platform can be conveniently integrated with optical fiber communication systems and (opto-) electronic systems, and therefore has the potential to realize remote sensing, in situ real-time detecting, and possible applications in the internet of things. PMID:26343678

Visible Wavelength Color Filters Using Dielectric Subwavelength Gratings for Backside-Illuminated CMOS Image Sensor Technologies.

PubMed

Horie, Yu; Han, Seunghoon; Lee, Jeong-Yub; Kim, Jaekwan; Kim, Yongsung; Arbabi, Amir; Shin, Changgyun; Shi, Lilong; Arbabi, Ehsan; Kamali, Seyedeh Mahsa; Lee, Hong-Seok; Hwang, Sungwoo; Faraon, Andrei

2017-05-10

We report transmissive color filters based on subwavelength dielectric gratings that can replace conventional dye-based color filters used in backside-illuminated CMOS image sensor (BSI CIS) technologies. The filters are patterned in an 80 nm-thick poly silicon film on a 115 nm-thick SiO 2 spacer layer. They are optimized for operating at the primary RGB colors, exhibit peak transmittance of 60-80%, and have an almost insensitive response over a ± 20° angular range. This technology enables shrinking of the pixel sizes down to near a micrometer.

Development of cryogenic CMOS Readout ASICs for the Point-Contact HPGe Detectors for Dark Matter Search and Neutrino Experiments

NASA Astrophysics Data System (ADS)

Deng, Zhi; He, Li; Liu, Feng; Liu, Yinong; Xue, Tao; Li, Yulan; Yue, Qian

2017-05-01

The paper presents the developments of two cryogenic readout ASICs for the point-contact HPGe detectors for dark matter search and neutrino experiments. Extremely low noise readout electronics were demanded and the capability of working at cryogenic temperatures may bring great advantages. The first ASIC was a monolithic CMOS charge sensitive preamplifier with its noise optimized for ∼1 pF input capacitance. The second ASIC was a waveform recorder based on switched capacitor array. These two ASICs were fabricated in CMOS 350 nm and 180 nm processes respectively. The prototype chips were tested and showed promising results. Both ASICs worked well at low temperature. The preamplifier had achieved ENC of 10.3 electrons with 0.7 pF input capacitance and the SCA chip could run at 9 bit effective resolution and 25 MSPS sampling rate.

Theoretical analysis and simulation study of low-power CMOS electrochemical impedance spectroscopy biosensor in 55 nm deeply depleted channel technology for cell-state monitoring

NASA Astrophysics Data System (ADS)

Itakura, Keisuke; Kayano, Keisuke; Nakazato, Kazuo; Niitsu, Kiichi

2018-01-01

We present an impedance-detection complementary metal oxide semiconductor (CMOS) biosensor circuit for cell-state observation. The proposed biosensor can measure the expected impedance values encountered by a cell-state observation measurement system within a 0.1-200 MHz frequency range. The proposed device is capable of monitoring the intracellular conditions necessary for real-time cell-state observation, and can be fabricated using a 55 nm deeply depleted channel CMOS process. Operation of the biosensor circuit with 0.9 and 1.7 V supply voltages is verified via a simulated program with integrated circuit emphasis (SPICE) simulation. The power consumption is 300 µW. Further, the standby power consumption is 290 µW, indicating that this biosensor is a low-power instrument suitable for use in Internet of Things (IoT) devices.

Wide modulation bandwidth terahertz detection in 130 nm CMOS technology

NASA Astrophysics Data System (ADS)

Nahar, Shamsun; Shafee, Marwah; Blin, Stéphane; Pénarier, Annick; Nouvel, Philippe; Coquillat, Dominique; Safwa, Amr M. E.; Knap, Wojciech; Hella, Mona M.

2016-11-01

Design, manufacturing and measurements results for silicon plasma wave transistors based wireless communication wideband receivers operating at 300 GHz carrier frequency are presented. We show the possibility of Si-CMOS based integrated circuits, in which by: (i) specific physics based plasma wave transistor design allowing impedance matching to the antenna and the amplifier, (ii) engineering the shape of the patch antenna through a stacked resonator approach and (iii) applying bandwidth enhancement strategies to the design of integrated broadband amplifier, we achieve an integrated circuit of the 300 GHz carrier frequency receiver for wireless wideband operation up to/over 10 GHz. This is, to the best of our knowledge, the first demonstration of low cost 130 nm Si-CMOS technology, plasma wave transistors based fast/wideband integrated receiver operating at 300 GHz atmospheric window. These results pave the way towards future large scale (cost effective) silicon technology based terahertz wireless communication receivers.

Monolithic integration of a plasmonic sensor with CMOS technology

NASA Astrophysics Data System (ADS)

Shakoor, Abdul; Cheah, Boon C.; Hao, Danni; Al-Rawhani, Mohammed; Nagy, Bence; Grant, James; Dale, Carl; Keegan, Neil; McNeil, Calum; Cumming, David R. S.

2017-02-01

Monolithic integration of nanophotonic sensors with CMOS detectors can transform the laboratory based nanophotonic sensors into practical devices with a range of applications in everyday life. In this work, by monolithically integrating an array of gold nanodiscs with the CMOS photodiode we have developed a compact and miniaturized nanophotonic sensor system having direct electrical read out. Doing so eliminates the need of expensive and bulky laboratory based optical spectrum analyzers used currently for measurements of nanophotonic sensor chips. The experimental optical sensitivity of the gold nanodiscs is measured to be 275 nm/RIU which translates to an electrical sensitivity of 5.4 V/RIU. This integration of nanophotonic sensors with the CMOS electronics has the potential to revolutionize personalized medical diagnostics similar to the way in which the CMOS technology has revolutionized the electronics industry.

A grating coupler with a trapezoidal hole array for perfectly vertical light coupling between optical fibers and waveguides

NASA Astrophysics Data System (ADS)

Mizutani, Akio; Eto, Yohei; Kikuta, Hisao

2017-12-01

A grating coupler with a trapezoidal hole array was designed and fabricated for perfectly vertical light coupling between a single-mode optical fiber and a silicon waveguide on a silicon-on-insulator (SOI) substrate. The grating coupler with an efficiency of 53% was computationally designed at a 1.1-µm-thick buried oxide (BOX) layer. The grating coupler and silicon waveguide were fabricated on the SOI substrate with a 3.0-µm-thick BOX layer by a single full-etch process. The measured coupling efficiency was 24% for TE-polarized light at 1528 nm wavelength, which was 0.69 times of the calculated coupling efficiency for the 3.0-µm-thick BOX layer.

10 Gb/s operation of photonic crystal silicon optical modulators.

PubMed

Nguyen, Hong C; Sakai, Yuya; Shinkawa, Mizuki; Ishikura, Norihiro; Baba, Toshihiko

2011-07-04

We report the first experimental demonstration of 10 Gb/s modulation in a photonic crystal silicon optical modulator. The device consists of a 200 μm-long SiO2-clad photonic crystal waveguide, with an embedded p-n junction, incorporated into an asymmetric Mach-Zehnder interferometer. The device is integrated on a SOI chip and fabricated by CMOS-compatible processes. With the bias voltage set at 0 V, we measure a V(π)L < 0.056 V∙cm. Optical modulation is demonstrated by electrically driving the device with a 2(31) - 1 bit non-return-to-zero pseudo-random bit sequence signal. An open eye pattern is observed at bitrates of 10 Gb/s and 2 Gb/s, with and without pre-emphasis of the drive signal, respectively.

Gyroscope and Micromirror Design Using Vertical-Axis CMOS-MEMS Actuation and Sensing

DTIC Science & Technology

2002-01-01

Interference pattern around the upper anchor (each fringe occurs at 310 nm vertical displacement...described above require extra lithography step(s) other than standard CMOS lithography steps and/or deposition of structural and sacrificial materials...Instruments’ dig- ital mirror device ( DMD ) [43]. The aluminum thin-film technology with vertical parallel- plate actuation has difficulty in achieving

Depleted fully monolithic CMOS pixel detectors using a column based readout architecture for the ATLAS Inner Tracker upgrade

NASA Astrophysics Data System (ADS)

Wang, T.; Barbero, M.; Berdalovic, I.; Bespin, C.; Bhat, S.; Breugnon, P.; Caicedo, I.; Cardella, R.; Chen, Z.; Degerli, Y.; Egidos, N.; Godiot, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Krüger, H.; Kugathasan, T.; Hügging, F.; Marin Tobon, C. A.; Moustakas, K.; Pangaud, P.; Schwemling, P.; Pernegger, H.; Pohl, D.-L.; Rozanov, A.; Rymaszewski, P.; Snoeys, W.; Wermes, N.

2018-03-01

Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. DMAPS integrating fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototype designs, named LF-Monopix and TJ-Monopix, are presented. LF-Monopix was fabricated in the LFoundry 150 nm CMOS technology, and TJ-Monopix has been designed in the TowerJazz 180 nm CMOS technology. Both chips employ the same readout architecture, i.e. the column drain architecture, whereas different sensor implementation concepts are pursued. The paper makes a joint description of the two prototypes, so that their technical differences and challenges can be addressed in direct comparison. First measurement results for LF-Monopix will also be shown, demonstrating for the first time a fully functional fast readout DMAPS prototype implemented in the LFoundry technology.

A scalable neural chip with synaptic electronics using CMOS integrated memristors.

PubMed

Cruz-Albrecht, Jose M; Derosier, Timothy; Srinivasa, Narayan

2013-09-27

The design and simulation of a scalable neural chip with synaptic electronics using nanoscale memristors fully integrated with complementary metal-oxide-semiconductor (CMOS) is presented. The circuit consists of integrate-and-fire neurons and synapses with spike-timing dependent plasticity (STDP). The synaptic conductance values can be stored in memristors with eight levels, and the topology of connections between neurons is reconfigurable. The circuit has been designed using a 90 nm CMOS process with via connections to on-chip post-processed memristor arrays. The design has about 16 million CMOS transistors and 73 728 integrated memristors. We provide circuit level simulations of the entire chip performing neuronal and synaptic computations that result in biologically realistic functional behavior.

Design of SOI wavelength filter based on multiple MMIs structures

NASA Astrophysics Data System (ADS)

Hu, Youfang; Gardes, Frédéric Y.; Jenkins, Richard M.; Finlayson, Ewan D.; Mashanovich, Goran Z.; Reed, Graham T.

2011-01-01

SOI based MMIs prove to be versatile photonic structures for optical power splitting/combining, directional coupling, wavelength multiplexing/demultiplexing, etc. Such a structure benefits from relative ease of fabrication, low sensitivity to fabrication error and low temperature dependence. Whilst the majority of previous designs and optimizations investigated single MMIs, there is significant potential to combine MMIs within a single device for the realization of improved device performance. We have designed and simulated a wavelength filter device consisting of a series of MMIs with different lengths. The bandwidth, free spectral range, and extinction ratio can be controlled by changing the MMI's width and length. We have optimized our design to achieve a -3dB bandwidth of 5nm, a free spectral range of 60nm, an extinction ratio of >30dB, and a side peak suppression ratio of >22dB. Such a device can be used for high performance coarse wavelength filtering. The whole structure can fit into a 70μm×300μm area. Temperature sensitivity of the designed structures was also investigated.

L-shaped fiber-chip grating couplers with high directionality and low reflectivity fabricated with deep-UV lithography.

PubMed

Benedikovic, Daniel; Alonso-Ramos, Carlos; Pérez-Galacho, Diego; Guerber, Sylvain; Vakarin, Vladyslav; Marcaud, Guillaume; Le Roux, Xavier; Cassan, Eric; Marris-Morini, Delphine; Cheben, Pavel; Boeuf, Frédéric; Baudot, Charles; Vivien, Laurent

2017-09-01

Grating couplers enable position-friendly interfacing of silicon chips by optical fibers. The conventional coupler designs call upon comparatively complex architectures to afford efficient light coupling to sub-micron silicon-on-insulator (SOI) waveguides. Conversely, the blazing effect in double-etched gratings provides high coupling efficiency with reduced fabrication intricacy. In this Letter, we demonstrate for the first time, to the best of our knowledge, the realization of an ultra-directional L-shaped grating coupler, seamlessly fabricated by using 193 nm deep-ultraviolet (deep-UV) lithography. We also include a subwavelength index engineered waveguide-to-grating transition that provides an eight-fold reduction of the grating reflectivity, down to 1% (-20  dB). A measured coupling efficiency of -2.7  dB (54%) is achieved, with a bandwidth of 62 nm. These results open promising prospects for the implementation of efficient, robust, and cost-effective coupling interfaces for sub-micrometric SOI waveguides, as desired for large-volume applications in silicon photonics.

Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gaioni, L.; Braga, D.; Christian, D.

This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

Silicon photonics: Design, fabrication, and characterization of on-chip optical interconnects

NASA Astrophysics Data System (ADS)

Hsieh, I.-Wei

In recent years, the research field of silicon photonics has been developing rapidly from a concept to a demonstrated technology, and has gathered much attention from both academia and industry communities. Its many potential applications in long-haul telecommunication, mid-range data-communication, on-chip optical interconnection networks, and nano-scale sensing as well as its compatibility with electronic integrated circuits have driven much effort in realizing silicon photonics both as a disruptive technology for existing markets and as an enabling technology for new ones. Despite the promising future of silicon photonics, many fundamental issues still remain to be understood---both in the linear- and nonlinear-optical regimes. There are also many engineering challenges to make silicon photonics the gold standard in photonic integrated circuits. In this thesis, we focus on the design, fabrication, and characterization of active and passive silicon-on-insulator (SOI) photonic devices. The SOI material system differs from most conventional optical material platforms because of its high-refractive-index-contrast, which enables engineers to design very compact integrated photonic networks with sub-micron transverse waveguide dimensions and sharp bends. On the other hand, because most analytical formulas for designing waveguide devices are valid only in low-index-contrast cases, SOI photonic devices need to be analyzed numerically for accurate results. The second chapter of this thesis describes some common numerical methods such as Beam Propagation Method (BPM) and Finite Element Method (FEM) for waveguide-design simulations, and presents two design studies based on these methods. The compatibility of silicon photonic integrated circuits with conventional CMOS fabrication technology is another important aspect that distinguishes silicon photonics from others such as III-V materials and lithium niobate. However, the requirements for fabricating silicon photonic devices are quite different from those of electronic devices. Minimizing propagation losses by reducing sidewall roughness to nanometer scale over a device length of several millimeters or even centimeters has prompted researchers in academia and industry to refine the fabrication process. Chapter 3 of this thesis summarizes our efforts in fabricating silicon photonic devices using standard CMOS technology. Chapter 4 describes the characterization of nonlinear effects, including self-phase modulation (SPM), cross-phase modulation (XPM), and supercontinuum generation in silicon-wire waveguides. Silicon-wire waveguides are strip waveguides with submicron transverse dimensions, which allow strong light confinement inside the silicon core. This strong optical confinement, in addition to the large third-order nonlinear optical susceptibility of crystalline silicon, leads to a net nonlinearity which is several orders of magnitude higher than the nonlinearity of silica fiber. Significant nonlinear effects can be observed and characterized over a device length of only several millimeters in silicon wires with very small input power. These effects provide opportunities for engineers to design active silicon photonic devices which are compact and energy-efficient. Chapter 5 presents a realization of an integrated SOI optical isolator, which is a critical yet often overlooked component in photonic integrated circuits. This study shows the feasibility to make a hybrid garnet/SOI active device with very promising results. Finally, Chapter 6 summarizes our demonstration of transmitting terabit-scale data streams in silicon-wire waveguides, which is an important first-step towards enabling intra-chip interconnection networks with ultra-high bandwidths. Although the scope of this thesis is limited to providing only fractional views of the whole silicon photonics area, it provides enough references for interested readers to conduct further literature research in other aspects of silicon photonics. It is the author's hope that the thesis would convey to its readers the significance and potential of this exciting emerging technology.

IR CMOS: near infrared enhanced digital imaging (Presentation Recording)

NASA Astrophysics Data System (ADS)

Pralle, Martin U.; Carey, James E.; Joy, Thomas; Vineis, Chris J.; Palsule, Chintamani

2015-08-01

SiOnyx has demonstrated imaging at light levels below 1 mLux (moonless starlight) at video frame rates with a 720P CMOS image sensor in a compact, low latency camera. Low light imaging is enabled by the combination of enhanced quantum efficiency in the near infrared together with state of the art low noise image sensor design. The quantum efficiency enhancements are achieved by applying Black Silicon, SiOnyx's proprietary ultrafast laser semiconductor processing technology. In the near infrared, silicon's native indirect bandgap results in low absorption coefficients and long absorption lengths. The Black Silicon nanostructured layer fundamentally disrupts this paradigm by enhancing the absorption of light within a thin pixel layer making 5 microns of silicon equivalent to over 300 microns of standard silicon. This results in a demonstrate 10 fold improvements in near infrared sensitivity over incumbent imaging technology while maintaining complete compatibility with standard CMOS image sensor process flows. Applications include surveillance, nightvision, and 1064nm laser see spot. Imaging performance metrics will be discussed. Demonstrated performance characteristics: Pixel size : 5.6 and 10 um Array size: 720P/1.3Mpix Frame rate: 60 Hz Read noise: 2 ele/pixel Spectral sensitivity: 400 to 1200 nm (with 10x QE at 1064nm) Daytime imaging: color (Bayer pattern) Nighttime imaging: moonless starlight conditions 1064nm laser imaging: daytime imaging out to 2Km

VCSEL-based optical transceiver module operating at 25 Gb/s and using a single CMOS IC

NASA Astrophysics Data System (ADS)

Afriat, Gil; Horwitz, Lior; Lazar, Dror; Issachar, Assaf; Pogrebinsky, Alexander; Ran, Adee; Shoor, Ehud; Bar, Roi; Saba, Rushdy

2012-01-01

We present here a low cost, small form factor, optical transceiver module composed of a CMOS IC transceiver, 850 nm emission wavelength VCSEL modulated at 25 Gb/s, and an InGaAs/InP PIN Photo Diode (PD). The transceiver IC is fabricated in a standard 28 nm CMOS process and integrates the analog circuits interfacing the VCSEL and PD, namely the VCSEL driver and Transimpedance Amplifier (TIA), as well as all other required transmitter and receiver circuits like Phase Locked Loop (PLL), Post Amplifier and Clock & Data Recovery (CDR). The transceiver module couples into a 62.5/125 um multi-mode (OM1) TX/RX fiber pair via a low cost plastic cover realizing the transmitter and receiver lens systems and demonstrates BER < 10-12 at the 25 Gb/s data rate over a distance of 3 meters. Using a 50/125 um laser optimized multi-mode fiber (OM3), the same performance was achieved over a distance of 30 meters.

Radiation hardness studies of AMS HV-CMOS 350 nm prototype chip HVStripV1

DOE PAGES

Kanisauskas, K.; Affolder, A.; Arndt, K.; ...

2017-02-15

CMOS active pixel sensors are being investigated for their potential use in the ATLAS inner tracker upgrade at the HL-LHC. The new inner tracker will have to handle a significant increase in luminosity while maintaining a sufficient signal-to-noise ratio and pulse shaping times. This paper focuses on the prototype chip "HVStripV1" (manufactured in the AMS HV-CMOS 350nm process) characterization before and after irradiation up to fluence levels expected for the strip region in the HL-LHC environment. The results indicate an increase of depletion region after irradiation for the same bias voltage by a factor of ≈2.4 and ≈2.8 for twomore » active pixels on the test chip. As a result, there was also a notable increase in noise levels from 85 e – to 386 e – and from 75 e – to 277 e – for the corresponding pixels.« less

Radiation hardness studies of AMS HV-CMOS 350 nm prototype chip HVStripV1

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kanisauskas, K.; Affolder, A.; Arndt, K.

CMOS active pixel sensors are being investigated for their potential use in the ATLAS inner tracker upgrade at the HL-LHC. The new inner tracker will have to handle a significant increase in luminosity while maintaining a sufficient signal-to-noise ratio and pulse shaping times. This paper focuses on the prototype chip "HVStripV1" (manufactured in the AMS HV-CMOS 350nm process) characterization before and after irradiation up to fluence levels expected for the strip region in the HL-LHC environment. The results indicate an increase of depletion region after irradiation for the same bias voltage by a factor of ≈2.4 and ≈2.8 for twomore » active pixels on the test chip. As a result, there was also a notable increase in noise levels from 85 e – to 386 e – and from 75 e – to 277 e – for the corresponding pixels.« less

Ge-cap quantum-well bulk FinFET for 5 nm node CMOS integration

NASA Astrophysics Data System (ADS)

Dwi Kurniawan, Erry; Peng, Kang-Hui; Yang, Shang-Yi; Yang, Yi-Yun; Thirunavukkarasu, Vasanthan; Lin, Yu-Hsien; Wu, Yung-Chun

2018-04-01

We propose the use of Ge-cap quantum-well (QW) bulk FinFET for 5 nm CMOS integration, which is a Si channel wrapped with Ge around three sides of the fin channel. The simulation results show that the Ge-cap FinFET structure demonstrates better performance than pure Si, pure Ge, and Si-cap FinFET structures. By optimizing Si fin width and Ge-cap thickness, the on-state current of nFET and pFET can also be symmetric without changing the total fin width (F Wp = F Wn). The electrons in Ge-cap nFinFET concentrate in the Si channel because of QWs formed in the lowest conduction band of the Ge and Si heterostructure, while the holes in Ge-cap pFinFET prefer to stay in Ge surfaces owing to QWs formed in the Ge valence band. The physics studies of this device have made the design rules relevant for the application of the CMOS inverter and static random access memory (SRAM) application technology.

Concentric Parallel Combining Balun for Millimeter-Wave Power Amplifier in Low-Power CMOS with High-Power Density

NASA Astrophysics Data System (ADS)

Han, Jiang-An; Kong, Zhi-Hui; Ma, Kaixue; Yeo, Kiat Seng; Lim, Wei Meng

2016-11-01

This paper presents a novel balun for a millimeter-wave power amplifier (PA) design to achieve high-power density in a 65-nm low-power (LP) CMOS process. By using a concentric winding technique, the proposed parallel combining balun with compact size accomplishes power combining and unbalance-balance conversion concurrently. For calculating its power combination efficiency in the condition of various amplitude and phase wave components, a method basing on S-parameters is derived. Based on the proposed parallel combining balun, a fabricated 60-GHz industrial, scientific, and medical (ISM) band PA with single-ended I/O achieves an 18.9-dB gain and an 8.8-dBm output power at 1-dB compression and 14.3-dBm saturated output power ( P sat) at 62 GHz. This PA occupying only a 0.10-mm2 core area has demonstrated a high-power density of 269.15 mW/mm2 in 65 nm LP CMOS.

Design of a 40-nm CMOS integrated on-chip oscilloscope for 5-50 GHz spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Csaba, György; Dietz, Andreas; Breitkreutz-von Gamm, Stephan; Russer, Johannes; Russer, Peter; Kreupl, Franz; Becherer, Markus

2018-05-01

Spin wave (SW) devices are receiving growing attention in research as a strong candidate for low power applications in the beyond-CMOS era. All SW applications would require an efficient, low power, on-chip read-out circuitry. Thus, we provide a concept for an on-chip oscilloscope (OCO) allowing parallel detection of the SWs at different frequencies. The readout system is designed in 40-nm CMOS technology and is capable of SW device characterization. First, the SWs are picked up by near field loop antennas, placed below yttrium iron garnet (YIG) film, and amplified by a low noise amplifier (LNA). Second, a mixer down-converts the radio frequency (RF) signal of 5 - 50 GHz to lower intermediate frequencies (IF) around 10 - 50 MHz. Finally, the IF signal can be digitized and analyzed regarding the frequency, amplitude and phase variation of the SWs. The power consumption and chip area of the whole OCO are estimated to 166.4 mW and 1.31 mm2, respectively.

Miniature Raman spectroscopy utilizing stabilized diode lasers and 2D CMOS detector arrays

NASA Astrophysics Data System (ADS)

Auz, Bryan; Bonvallet, Joseph; Rodriguez, John; Olmstead, Ty

2017-02-01

A miniature Raman spectrometer was designed in a rapid development cycle (< 4 months) to investigate the performance capabilities achievable with two dimensional (2D) CMOS detectors found in cell phone camera modules and commercial off the shelf optics (COTS). This paper examines the design considerations and tradeoffs made during the development cycle. The final system developed measures 40 mm in length, 40 mm in width, 15 mm tall and couples directly with the cell phone camera optics. Two variants were made: one with an excitation wavelength of 638 nm and the other with a 785 nm excitation wavelength. Raman spectra of the following samples were gathered at both excitations: Toluene, Cyclohexane, Bis(MSB), Aspirin, Urea, and Ammonium Nitrate. The system obtained a resolution of 40 cm-1. The spectra produced at 785 nm excitation required integration times of up to 10 times longer than the 1.5 seconds at 638 nm, however, contained reduced stray light and less fluorescence which led to an overall cleaner signal.

A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor

PubMed Central

Current, K. Wayne; Yuk, Kelvin; McConaghy, Charles; Gascoyne, Peter R. C.; Schwartz, Jon A.; Vykoukal, Jody V.; Andrews, Craig

2010-01-01

A high-voltage (HV) integrated circuit has been demonstrated to transport droplets on programmable paths across its coated surface. This chip is the engine for a dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip system. This chip creates DEP forces that move and help inject droplets. Electrode excitation voltage and frequency are variable. With the electrodes driven with a 100V peak-to-peak periodic waveform, the maximum high-voltage electrode waveform frequency is about 200Hz. Data communication rate is variable up to 250kHz. This demonstration chip has a 32×32 array of nominally 100V electrode drivers. It is fabricated in a 130V SOI CMOS fabrication technology, dissipates a maximum of 1.87W, and is about 10.4 mm × 8.2 mm. PMID:23989241

A comparison of heavy ion induced single event upset susceptibility in unhardened 6T/SRAM and hardened ADE/SRAM

NASA Astrophysics Data System (ADS)

Wang, Bin; Zeng, Chuanbin; Geng, Chao; Liu, Tianqi; Khan, Maaz; Yan, Weiwei; Hou, Mingdong; Ye, Bing; Sun, Youmei; Yin, Yanan; Luo, Jie; Ji, Qinggang; Zhao, Fazhan; Liu, Jie

2017-09-01

Single event upset (SEU) susceptibility of unhardened 6T/SRAM and hardened active delay element (ADE)/SRAM, fabricated with 0.35 μm silicon-on-insulator (SOI) CMOS technology, was investigated at heavy ion accelerator. The mechanisms were revealed by the laser irradiation and resistor-capacitor hardened techniques. Compared with conventional 6T/SRAM, the hardened ADE/SRAM exhibited higher tolerance to heavy ion irradiation, with an increase of about 80% in the LET threshold and a decrease of ∼64% in the limiting upset cross-section. Moreover, different probabilities between 0 → 1 and 1 → 0 transitions were observed, which were attributed to the specific architecture of ADE/SRAM memory cell. Consequently, the radiation-hardened technology can be an attractive alternative to the SEU tolerance of the device-level.

Embedded CMOS basecalling for nanopore DNA sequencing.

PubMed

Chengjie Wang; Junli Zheng; Magierowski, Sebastian; Ghafar-Zadeh, Ebrahim

2016-08-01

DNA sequencing based on nanopore sensors is now entering the marketplace. The ability to interface this technology to established CMOS microelectronics promises significant improvements in functionality and miniaturization. Among the key functions to benefit from this interface will be basecalling, the conversion of raw electronic molecular signatures to nucleotide sequence predictions. This paper presents the design and performance potential of custom CMOS base-callers embedded alongside nanopore sensors. A basecalliing architecture implemented in 32-nm technology is discussed with the ability to process the equivalent of 20 human genomes per day in real-time at a power density of 5 W/cm2 assuming a 3-mer nanopore sensor.

Novel Waveguide Architectures for Light Sources in Silicon Photonics

NASA Astrophysics Data System (ADS)

Tummidi, Ravi Sekhar

Of the many challenges which are threatening to derail the success trend set by Moore's Law, perhaps the most prominent one is the "Interconnect Bottleneck". The metallic interconnections which carry inter-chip and intra-chip signals are increasingly proving to be inadequate to carry the enormous amount of data due to band-width limitations, cross talk and increased latency. A silicon based optical interconnect is showing enormous promise to address this issue in a cost effective manner by leveraging the extremely matured CMOS fabrication infrastructure. An optical interconnect system consists of a low loss waveguide, modulator, photo detector and a light source. Of these the only component yet to be demonstrated in silicon is a CMOS compatible electrically pumped silicon based laser. The present work is our endeavor towards the goal of a practical light source in silicon. To this end we have focused our efforts on horizontal slot waveguide which consists of a nm thin low index silica layer sandwiched between two high index silicon layers. Such a structure provides an exceptionally high confinement for the TM-like mode in the thin silica slot. The shallow ridge profile of the waveguide allows in principle for lateral electrical access to the core of the waveguide for excitation of the slot embedded gain material like erbium or nano-crystal sensitized erbium using tunneling, polarization transfer or transport. Low losses in the proposed structure are paramount due to the low gain expectation (˜1dB/cm) from CMOS compatible gain media. This dissertation details the novel techniques conceived to mitigate the severe lateral radiation leakage loss of the TM-like mode in these waveguides and resonators using "Magic Widths" and "Magic Radii" designs. New fabrication techniques are discussed which were developed to achieve ultra-smooth waveguide surfaces to substantially reduce the scattering induced losses in the Silicon-on-Insulator (SOI) high index contrast system. This enabled us to achieve resonators with Qs of 1.6x106 for the TE-like mode in non-slot configurations and 3x105 for the TM-like mode in full slot configuration, the highest yet reported for this type of structure and close to our design requirements for a laser. Erbium was incorporated into the silica slot just 8.3 nm thick and photoluminescence was observed in full waveguide configuration. A simple phenomenological model based on spontaneous emission into a waveguide mode was developed, which predicted >10x Purcell enhancement of the luminescence decay in these slot waveguides even in the absence of a resonator, a result also yielded by a rigorous quantum electrodynamic analysis. These enhanced spontaneous emission rates were experimentally verified using time resolved photoluminescence decay and luminescence power measurements. The results so far indicate that these slot structures could be the enablers for very efficient LEDs due to the highly preferential characteristic of the spontaneous emission to go into the single guided mode. The future goal will be to harness this behavior for novel silicon photonic light sources.

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

NASA Astrophysics Data System (ADS)

Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

2018-04-01

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

Accurate Modeling Method for Cu Interconnect

NASA Astrophysics Data System (ADS)

Yamada, Kenta; Kitahara, Hiroshi; Asai, Yoshihiko; Sakamoto, Hideo; Okada, Norio; Yasuda, Makoto; Oda, Noriaki; Sakurai, Michio; Hiroi, Masayuki; Takewaki, Toshiyuki; Ohnishi, Sadayuki; Iguchi, Manabu; Minda, Hiroyasu; Suzuki, Mieko

This paper proposes an accurate modeling method of the copper interconnect cross-section in which the width and thickness dependence on layout patterns and density caused by processes (CMP, etching, sputtering, lithography, and so on) are fully, incorporated and universally expressed. In addition, we have developed specific test patterns for the model parameters extraction, and an efficient extraction flow. We have extracted the model parameters for 0.15μm CMOS using this method and confirmed that 10%τpd error normally observed with conventional LPE (Layout Parameters Extraction) was completely dissolved. Moreover, it is verified that the model can be applied to more advanced technologies (90nm, 65nm and 55nm CMOS). Since the interconnect delay variations due to the processes constitute a significant part of what have conventionally been treated as random variations, use of the proposed model could enable one to greatly narrow the guardbands required to guarantee a desired yield, thereby facilitating design closure.

A novel high-speed CMOS circuit based on a gang of capacitors

NASA Astrophysics Data System (ADS)

Sharroush, Sherif M.

2017-08-01

There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with VDD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.

A CMOS enhanced solid-state nanopore based single molecule detection platform.

PubMed

Chen, Chinhsuan; Yemenicioglu, Sukru; Uddin, Ashfaque; Corgliano, Ellie; Theogarajan, Luke

2013-01-01

Solid-state nanopores have emerged as a single molecule label-free electronic detection platform. Existing transimpedance stages used to measure ionic current nanopores suffer from dynamic range limitations resulting from steady-state baseline currents. We propose a digitally-assisted baseline cancellation CMOS platform that circumvents this issue. Since baseline cancellation is a form of auto-zeroing, the 1/f noise of the system is also reduced. Our proposed design can tolerate a steady state baseline current of 10µA and has a usable bandwidth of 750kHz. Quantitative DNA translocation experiments on 5kbp DNA was performed using a 5nm silicon nitride pore using both the CMOS platform and a commercial system. Comparison of event-count histograms show that the CMOS platform clearly outperforms the commercial system, allowing for unambiguous interpretation of the data.

Equalizing Si photodetectors fabricated in standard CMOS processes

NASA Astrophysics Data System (ADS)

Guerrero, E.; Aguirre, J.; Sánchez-Azqueta, C.; Royo, G.; Gimeno, C.; Celma, S.

2017-05-01

This work presents a new continuous-time equalization approach to overcome the limited bandwidth of integrated CMOS photodetectors. It is based on a split-path topology that features completely decoupled controls for boosting and gain; this capability allows a better tuning of the equalizer in comparison with other architectures based on the degenerated differential pair, which is particularly helpful to achieve a proper calibration of the system. The equalizer is intended to enhance the bandwidth of CMOS standard n-well/p-bulk differential photodiodes (DPDs), which falls below 10MHz representing a bottleneck in fully integrated optoelectronic interfaces to fulfill the low-cost requirements of modern smart sensors. The proposed equalizer has been simulated in a 65nm CMOS process and biased with a single supply voltage of 1V, where the bandwidth of the DPD has been increased up to 3 GHz.

High-efficiency fiber-to-chip grating couplers realized using an advanced CMOS-compatible silicon-on-insulator platform.

PubMed

Vermeulen, D; Selvaraja, S; Verheyen, P; Lepage, G; Bogaerts, W; Absil, P; Van Thourhout, D; Roelkens, G

2010-08-16

A new generation of Silicon-on-Insulator fiber-to-chip grating couplers which use a silicon overlay to enhance the directionality and thereby the coupling efficiency is presented. Devices are realized on a 200 mm wafer in a CMOS pilot line. The fabricated fiber couplers show a coupling efficiency of -1.6 dB and a 3 dB bandwidth of 80 nm.

Lateral Charge Transport in Silicon Nanomembranes

NASA Astrophysics Data System (ADS)

Hu, Weiwei

Silicon nanomembranes, also called SiNMs, Si thin sheets or films, are a great platform to study surface sciences, since the bulk is diminished and the surface-to-volume ratio is large. In a single crystalline material, atoms on the surface experience different forces, electric fields, thermodynamic surroundings, etc., than those within the bulk. Therefore, unique structural, mechanical, electronic, optical, and many other properties associated with surfaces overweigh bulk effects; novel phenomena emerge. In particular, electronic features of Si are of significance due to the extensive use of Si in integrated circuit devices and biochemical sensor technologies. As a result, especially with the size of transistors quickly decreasing nowadays, the exploration of electronic characteristics of Si surfaces become much more significant. This is also interesting as a topic within the area of fundamental surface science. Silicon-on-insulator (SOI) provides a new structure for studying charge transport in the SiNM, which is monocrystalline and sits on top of the SOI wafer. I use SOI based SiNMs with two surface orientations: Si (001) and Si (111). The former is pervasive in industrial applications while the latter has interesting metallic surface states when 7x7 reconstruction occurs on a clean surface. My goal is to measure/infer the sheet conductance in the true surface layer with different surface situations, and to further investigate the surface band structure and how carriers distribute and move accordingly. The biggest challenge is to eliminate interferences, e.g., bulk effects. The following are two solutions. 1) The thickness of the used SiNMs spans 40 nm to 500 nm, with a nominal doping level of 1015 cm -3 in our experiment. A straightforward calculation of areal dopant density indicates that charge carriers from the extrinsic doping are 1˜2 orders of magnitude fewer than the trap states at the interface between the buried oxide in SOI and the top SiNM, meaning that moderate doping is irrelevant and the SiNM acts like an intrinsic one. 2) The back gate that is applied to the measured sample is an innovative design among myriad analogous studies. It enables the tuning of the Fermi level (EF) throughout the SiNMs and makes it possible for a membrane to reach its most depleted status, thus efficiently removing the bulk conduction path. The four-probe van der Pauw measurements of film conductance are taken inside an ultrahigh vacuum chamber, where the surface condition remains stable and controllable. On Si (111) 7x7 surfaces, we find from the independence of conductance on membrane thickness that we are measuring the surface transport only. The sheet conductance is high, as it is on the microS/□scale, which supports the 7x7 surface having metallicity in lateral charge transport, a point which has been debated extensively. Nevertheless, weak semiconductor behavior is still present. For hydrogenated Si (001), which is obtained after hydrogen fluoric acid (HF) treatment, surface Fermi level is found around mid-bandgap based on temperature dependent measurements. No surface Fermi level pinning to closely below the conduction band minimum exists in my HF treated Si (001) NMs.

Enhancement of coupling ratios in SOI based asymmetrical optical directional couplers

NASA Astrophysics Data System (ADS)

Pendam, Nagaraju; Vardhani, Chunduru Parvatha

2017-11-01

A novel design of slab structured asymmetrical optical directional coupler with S-bend waveguides on silicon-on-insulator (SOI) platform has been designed by using R-Soft CAD tool. Beam propagation method (BPM) is used for light propagation analysis. The simulation results of asymmetrical optical directional couplers are reported. We find that the asymmetrical directional coupler has lower coupling ratios and higher extinction ratios with waveguide parameters such as width, wavelength, waveguide spacing, and coupling length. Simulation results designate that the coupling efficiency for transverse electric (TE) and transverse magnetic (TM) modes can reach about more than 95% and extinction ratio about 6 dB when the coupling length is 6 mm for both the polarization modes and insertion loss is 17 dB with same coupling length 6 mm at central wavelength 1550 nm.

Concentric circular focusing reflector realized using high index contrast gratings

NASA Astrophysics Data System (ADS)

Fang, Wenjing; Huang, Yongqing; Fei, Jiarui; Duan, Xiaofeng; Liu, Kai; Ren, Xiaomin

2017-11-01

A non-periodic concentric circular high index contrast grating (CC-HCG) focusing reflector on 500 nm silicon-on-insulator (SOI) platform is fabricated and experimentally demonstrated. The proposed mirror is realized with phase modulation of wave front in a high reflectivity region. The circular structure based HCG focusing reflector has a spot of high concentration at the 10.87 mm with normal incidence for radially polarization, along with the center wavelength set at 1550 nm. The FWHM spot size of the focusing beam decreases to 260 μm, and the intensity increases to 1.26 compared with the incident beam. The focusing efficiency of about 80% is observed at 1550 nm in the experimental measurement.

A Microfluidic Cytometer for Complete Blood Count With a 3.2-Megapixel, 1.1- μm-Pitch Super-Resolution Image Sensor in 65-nm BSI CMOS.

PubMed

Liu, Xu; Huang, Xiwei; Jiang, Yu; Xu, Hang; Guo, Jing; Hou, Han Wei; Yan, Mei; Yu, Hao

2017-08-01

Based on a 3.2-Megapixel 1.1- μm-pitch super-resolution (SR) CMOS image sensor in a 65-nm backside-illumination process, a lens-free microfluidic cytometer for complete blood count (CBC) is demonstrated in this paper. Backside-illumination improves resolution and contrast at the device level with elimination of surface treatment when integrated with microfluidic channels. A single-frame machine-learning-based SR processing is further realized at system level for resolution correction with minimum hardware resources. The demonstrated microfluidic cytometer can detect the platelet cells (< 2 μm) required in CBC, hence is promising for point-of-care diagnostics.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Demaria, N.

This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64×64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. Lastly, the collaborationmore » is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.« less

Design of fast signal processing readout front-end electronics implemented in CMOS 40 nm technology

NASA Astrophysics Data System (ADS)

Kleczek, Rafal

2016-12-01

The author presents considerations on the design of fast readout front-end electronics implemented in a CMOS 40 nm technology with an emphasis on the system dead time, noise performance and power dissipation. The designed processing channel consists of a charge sensitive amplifier with different feedback types (Krummenacher, resistive and constant current blocks), a threshold setting block, a discriminator and a counter with logic circuitry. The results of schematic and post-layout simulations with randomly generated input pulses in a time domain according to the Poisson distribution are presented and analyzed. Dead time below 20 ns is possible while keeping noise ENC ≈ 90 e- for a detector capacitance CDET = 160 fF.

SEE Sensitivity Analysis of 180 nm NAND CMOS Logic Cell for Space Applications

NASA Astrophysics Data System (ADS)

Sajid, Muhammad

2016-07-01

This paper focus on Single Event Effects caused by energetic particle strike on sensitive locations in CMOS NAND logic cell designed in 180nm technology node to be operated in space radiation environment. The generation of SE transients as well as upsets as function of LET of incident particle has been determined for logic devices onboard LEO and GEO satellites. The minimum magnitude pulse and pulse-width for threshold LET was determined to estimate the vulnerability /susceptibility of device for heavy ion strike. The impact of temperature, strike location and logic state of NAND circuit on total SEU/SET rate was estimated with physical mechanism simulations using Visual TCAD, Genius, runSEU program and Crad computer codes.

A 10 Gb/s laser driver in 130 nm CMOS technology for high energy physics applications

DOE PAGES

Zhang, T.; Tavernier, F.; Moreira, P.; ...

2015-02-19

The GigaBit Laser Driver (GBLD) is a key on-detector component of the GigaBit Transceiver (GBT) system at the transmitter side. We have developed a 10 Gb/s GBLD (GBLD10) in a 130 nm CMOS technology, as part of the design efforts towards the upgrade of the electrical components of the LHC experiments. The GBLD10 is based on the distributed-amplifier (DA) architecture and achieves data rates up to 10 Gb/s. It is capable of driving VCSELs with modulation currents up to 12 mA. Furthermore, a pre-emphasis function has been included in the proposed laser driver in order to compensate for the capacitivemore » load and channel losses.« less

Radiation Tolerant, Low Noise Phase Locked Loops in 65 nm CMOS Technology

NASA Astrophysics Data System (ADS)

Prinzie, Jeffrey; Christiansen, Jorgen; Moreira, Paulo; Steyaert, Michiel; Leroux, Paul

2018-04-01

This work presents an introduction to radiation hardened Phase Locked Loops (PLLs) for nuclear and high-energy physics application. An experimental circuit has been fabricated and irradiated with Xrays up to 600 Mrad. Heavy ions with an LET between 3.2 and 69.2 MeV.cm2/mg were used to verify the SEU cross section of the devices. A Two-photon Absorption (TPA) laser facility has been used to provide detailed results on the SEU sensitivity. The presented circuit employs TMR in the digital logic and an asynchronous phase-frequency detector (PFD) is presented. The PLL has a ringand LC-oscillator to be compared experimentally. The circuit has been fabricated in a 65 nm CMOS technology.

TriPleX: a versatile dielectric photonic platform

NASA Astrophysics Data System (ADS)

Wörhoff, Kerstin; Heideman, René G.; Leinse, Arne; Hoekman, Marcel

2015-04-01

Photonic applications based on planar waveguide technology impose stringent requirements on properties such as optical propagation losses, light coupling to optical fibers, integration density, as well as on reliability and reproducibility. The latter is correlated to a high level of control of the refractive index and waveguide geometry. In this paper, we review a versatile dielectric waveguide platform, called TriPleX, which is based on alternating silicon nitride and silicon dioxide films. Fabrication with CMOS-compatible equipment based on low-pressure chemical vapor deposition enables the realization of stable material compositions being a prerequisite to the control of waveguide properties and modal shape. The transparency window of both materials allows for the realization of low-loss waveguides over a wide wavelength range (400 nm-2.35 μm). Propagation losses as low as 5×10-4 dB/cm are reported. Three basic geometries (box shell, double stripe, and filled box) can be distinguished. A specific tapering technology is developed for on-chip, low-loss (<0.1 dB) spotsize convertors, allowing for combining efficient fiber to chip coupling with high-contrast waveguides required for increased functional complexity as well as for hybrid integration with other photonic platforms such as InP and SOI. The functionality of the TriPleX platform is captured by verified basic building blocks. The corresponding library and associated design kit is available for multi-project wafer (MPW) runs. Several applications of this platform technology in communications, biomedicine, sensing, as well as a few special fields of photonics are treated in more detail.

A 40 GHz fully integrated circuit with a vector network analyzer and a coplanar-line-based detection area for circulating tumor cell analysis using 65 nm CMOS technology

NASA Astrophysics Data System (ADS)

Nakanishi, Taiki; Matsunaga, Maya; Kobayashi, Atsuki; Nakazato, Kazuo; Niitsu, Kiichi

2018-03-01

A 40-GHz fully integrated CMOS-based circuit for circulating tumor cells (CTC) analysis, consisting of an on-chip vector network analyzer (VNA) and a highly sensitive coplanar-line-based detection area is presented in this paper. In this work, we introduce a fully integrated architecture that eliminates unwanted parasitic effects. The proposed analyzer was designed using 65 nm CMOS technology, and SPICE and MWS simulations were used to validate its operation. The simulation confirmed that the proposed circuit can measure S-parameter shifts resulting from the addition of various types of tumor cells to the detection area, the data of which are provided in a previous study: the |S 21| values for HepG2, A549, and HEC-1-A cells are -0.683, -0.580, and -0.623 dB, respectively. Additionally, the measurement demonstrated an S-parameters reduction of -25.7% when a silicone resin was put on the circuit. Hence, the proposed system is expected to contribute to cancer diagnosis.

Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2

NASA Astrophysics Data System (ADS)

Martin, Dominik; Yurchuk, Ekaterina; Müller, Stefan; Müller, Johannes; Paul, Jan; Sundquist, Jonas; Slesazeck, Stefan; Schlösser, Till; van Bentum, Ralf; Trentzsch, Martin; Schröder, Uwe; Mikolajick, Thomas

2013-10-01

Throughout the 22 nm technology node HfO2 is established as a reliable gate dielectric in contemporary complementary metal oxide semiconductor (CMOS) technology. The working principle of ferroelectric field effect transistors FeFET has also been demonstrated for some time for dielectric materials like Pb[ZrxTi1-x]O3 and SrBi2Ta2O9. However, integrating these into contemporary downscaled CMOS technology nodes is not trivial due to the necessity of an extremely thick gate stack. Recent developments have shown HfO2 to have ferroelectric properties, given the proper doping. Moreover, these doped HfO2 thin films only require layer thicknesses similar to the ones already in use in CMOS technology. This work will show how the incorporation of Si induces ferroelectricity in HfO2 based capacitor structures and finally demonstrate non-volatile storage in nFeFETs down to a gate length of 100 nm. A memory window of 0.41 V can be retained after 20,000 switching cycles. Retention can be extrapolated to 10 years.

Ion traps fabricated in a CMOS foundry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mehta, K. K.; Ram, R. J.; Eltony, A. M.

2014-07-28

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size.more » This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.« less

Ultra-low crosstalk, CMOS compatible waveguide crossings for densely integrated photonic interconnection networks.

PubMed

Jones, Adam M; DeRose, Christopher T; Lentine, Anthony L; Trotter, Douglas C; Starbuck, Andrew L; Norwood, Robert A

2013-05-20

We explore the design space for optimizing CMOS compatible waveguide crossings on a silicon photonics platform. This paper presents simulated and experimental excess loss and crosstalk suppression data for vertically integrated silicon nitride over silicon-on-insulator waveguide crossings. Experimental results show crosstalk suppression exceeding -49/-44 dB with simulation results as low as -65/-60 dB for the TE/TM mode in a waveguide crossing with a 410 nm vertical gap.

32 x 16 CMOS smart pixel array for optical interconnects

NASA Astrophysics Data System (ADS)

Kim, Jongwoo; Guilfoyle, Peter S.; Stone, Richard V.; Hessenbruch, John M.; Choquette, Kent D.; Kiamilev, Fouad E.

2000-05-01

Free space optical interconnects can increase throughput capacities and eliminate much of the energy consumption required for `all electronic' systems. High speed optical interconnects can be achieved by integrating optoelectronic devices with conventional electronics. Smart pixel arrays have been developed which use optical interconnects. An individual smart pixel cell is composed of a vertical cavity surface emitting laser (VCSEL), a photodetector, an optical receiver, a laser driver, and digital logic circuitry. Oxide-confined VCSELs are being developed to operate at 850 nm with a threshold current of approximately 1 mA. Multiple quantum well photodetectors are being fabricated from AlGaAs for use with the 850 nm VCSELs. The VCSELs and photodetectors are being integrated with complementary metal oxide semiconductor (CMOS) circuitry using flip-chip bonding. CMOS circuitry is being integrated with a 32 X 16 smart pixel array. The 512 smart pixels are serially linked. Thus, an entire data stream may be clocked through the chip and output electrically by the last pixel. Electrical testing is being performed on the CMOS smart pixel array. Using an on-chip pseudo random number generator, a digital data sequence was cycled through the chip verifying operation of the digital circuitry. Although, the prototype chip was fabricated in 1.2 micrometers technology, simulations have demonstrated that the array can operate at 1 Gb/s per pixel using 0.5 micrometers technology.

PNP PIN bipolar phototransistors for high-speed applications built in a 180 nm CMOS process.

PubMed

Kostov, P; Gaberl, W; Hofbauer, M; Zimmermann, H

2012-08-01

This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180 nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high -3 dB bandwidth at low collector-emitter voltages. For a further increase of the bandwidth the presented phototransistors were designed with small emitter areas resulting in a small base-emitter capacitance. The three presented phototransistors were implemented in sizes of 40 × 40 μm 2 and 100 × 100 μm 2 . Optical DC and AC measurements at 410 nm, 675 nm and 850 nm were done for phototransistor characterization. Due to the speed optimized design and the layer structure of the phototransistors, bandwidths up to 76.9 MHz and dynamic responsivities up to 2.89 A/W were achieved. Furthermore simulations of the electric field strength and space-charge regions were done.

Design of ultra-low power biopotential amplifiers for biosignal acquisition applications.

PubMed

Zhang, Fan; Holleman, Jeremy; Otis, Brian P

2012-08-01

Rapid development in miniature implantable electronics are expediting advances in neuroscience by allowing observation and control of neural activities. The first stage of an implantable biosignal recording system, a low-noise biopotential amplifier (BPA), is critical to the overall power and noise performance of the system. In order to integrate a large number of front-end amplifiers in multichannel implantable systems, the power consumption of each amplifier must be minimized. This paper introduces a closed-loop complementary-input amplifier, which has a bandwidth of 0.05 Hz to 10.5 kHz, an input-referred noise of 2.2 μ Vrms, and a power dissipation of 12 μW. As a point of comparison, a standard telescopic-cascode closed-loop amplifier with a 0.4 Hz to 8.5 kHz bandwidth, input-referred noise of 3.2 μ Vrms, and power dissipation of 12.5 μW is presented. Also for comparison, we show results from an open-loop complementary-input amplifier that exhibits an input-referred noise of 3.6 μ Vrms while consuming 800 nW of power. The two closed-loop amplifiers are fabricated in a 0.13 μ m CMOS process. The open-loop amplifier is fabricated in a 0.5 μm SOI-BiCMOS process. All three amplifiers operate with a 1 V supply.

IR sensitivity enhancement of CMOS Image Sensor with diffractive light trapping pixels.

PubMed

Yokogawa, Sozo; Oshiyama, Itaru; Ikeda, Harumi; Ebiko, Yoshiki; Hirano, Tomoyuki; Saito, Suguru; Oinoue, Takashi; Hagimoto, Yoshiya; Iwamoto, Hayato

2017-06-19

We report on the IR sensitivity enhancement of back-illuminated CMOS Image Sensor (BI-CIS) with 2-dimensional diffractive inverted pyramid array structure (IPA) on crystalline silicon (c-Si) and deep trench isolation (DTI). FDTD simulations of semi-infinite thick c-Si having 2D IPAs on its surface whose pitches over 400 nm shows more than 30% improvement of light absorption at λ = 850 nm and the maximum enhancement of 43% with the 540 nm pitch at the wavelength is confirmed. A prototype BI-CIS sample with pixel size of 1.2 μm square containing 400 nm pitch IPAs shows 80% sensitivity enhancement at λ = 850 nm compared to the reference sample with flat surface. This is due to diffraction with the IPA and total reflection at the pixel boundary. The NIR images taken by the demo camera equip with a C-mount lens show 75% sensitivity enhancement in the λ = 700-1200 nm wavelength range with negligible spatial resolution degradation. Light trapping CIS pixel technology promises to improve NIR sensitivity and appears to be applicable to many different image sensor applications including security camera, personal authentication, and range finding Time-of-Flight camera with IR illuminations.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm

NASA Astrophysics Data System (ADS)

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm.

PubMed

Asaithambi, Sasikumar; Rajappa, Muthaiah

2018-05-01

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Patterning and templating for nanoelectronics.

PubMed

Galatsis, Kosmas; Wang, Kang L; Ozkan, Mihri; Ozkan, Cengiz S; Huang, Yu; Chang, Jane P; Monbouquette, Harold G; Chen, Yong; Nealey, Paul; Botros, Youssry

2010-02-09

The semiconductor industry will soon be launching 32 nm complementary metal oxide semiconductor (CMOS) technology node using 193 nm lithography patterning technology to fabricate microprocessors with more than 2 billion transistors. To ensure the survival of Moore's law, alternative patterning techniques that offer advantages beyond conventional top-down patterning are aggressively being explored. It is evident that most alternative patterning techniques may not offer compelling advantages to succeed conventional top-down lithography for silicon integrated circuits, but alternative approaches may well indeed offer functional advantages in realising next-generation information processing nanoarchitectures such as those based on cellular, bioinsipired, magnetic dot logic, and crossbar schemes. This paper highlights and evaluates some patterning methods from the Center on Functional Engineered Nano Architectonics in Los Angeles and discusses key benchmarking criteria with respect to CMOS scaling.

High-voltage pixel sensors for ATLAS upgrade

NASA Astrophysics Data System (ADS)

Perić, I.; Kreidl, C.; Fischer, P.; Bompard, F.; Breugnon, P.; Clemens, J.-C.; Fougeron, D.; Liu, J.; Pangaud, P.; Rozanov, A.; Barbero, M.; Feigl, S.; Capeans, M.; Ferrere, D.; Pernegger, H.; Ristic, B.; Muenstermann, D.; Gonzalez Sevilla, S.; La Rosa, A.; Miucci, A.; Nessi, M.; Iacobucci, G.; Backhaus, M.; Hügging, Fabian; Krüger, H.; Hemperek, T.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Quadt, A.; Weingarten, J.; George, M.; Grosse-Knetter, J.; Rieger, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.

2014-11-01

The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180 nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.

Advancement of CMOS Doping Technology in an External Development Framework

NASA Astrophysics Data System (ADS)

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

Characterization of a smartphone camera's response to ultraviolet A radiation.

PubMed

Igoe, Damien; Parisi, Alfio; Carter, Brad

2013-01-01

As part of a wider study into the use of smartphones as solar ultraviolet radiation monitors, this article characterizes the ultraviolet A (UVA; 320-400 nm) response of a consumer complementary metal oxide semiconductor (CMOS)-based smartphone image sensor in a controlled laboratory environment. The CMOS image sensor in the camera possesses inherent sensitivity to UVA, and despite the attenuation due to the lens and neutral density and wavelength-specific bandpass filters, the measured relative UVA irradiances relative to the incident irradiances range from 0.0065% at 380 nm to 0.0051% at 340 nm. In addition, the sensor demonstrates a predictable response to low-intensity discrete UVA stimuli that can be modelled using the ratio of recorded digital values to the incident UVA irradiance for a given automatic exposure time, and resulting in measurement errors that are typically less than 5%. Our results support the idea that smartphones can be used for scientific monitoring of UVA radiation. © 2012 Wiley Periodicals, Inc. Photochemistry and Photobiology © 2012 The American Society of Photobiology.

CMOS compatible on-chip telecom-band to mid-infrared supercontinuum generation in dispersion-engineered reverse strip/slot hybrid Si3N4 waveguide

NASA Astrophysics Data System (ADS)

Hui, Zhanqiang; Zhang, Lingxuan; Zhang, Wenfu

2018-01-01

A silicon nitride (Si3N4)-based reverse strip/slot hybrid waveguide with single vertical silica slot is proposed to acquire extremely low and flat chromatic dispersion profile. This is achieved by design and optimization of the geometrical structural parameters of the reverse hybrid waveguide. The flat dispersion varying between ±10 ps/(nm.km) is obtained over 610 nm bandwidth. Both the effective area and nonlinear coefficient of the waveguide across the entire spectral range of interest are investigated. This led to design of an on-chip supercontinuum (SC) source with -30 dB bandwidth of 2996 nm covering from 1.209 to 4.205 μm. Furthermore, we discuss the output signal spectral and temporal characteristic as a function of the pump power. Our waveguide design offers a CMOS compatible, low-cost/high yield (no photolithography or lift-off processes are necessary) on-chip SC source for near- and mid-infrared nonlinear applications.

Athermal Silicon-on-insulator ring resonators by overlaying a polymer cladding on narrowed waveguides.

PubMed

Teng, Jie; Dumon, Pieter; Bogaerts, Wim; Zhang, Hongbo; Jian, Xigao; Han, Xiuyou; Zhao, Mingshan; Morthier, Geert; Baets, Roel

2009-08-17

Athermal silicon ring resonators are experimentally demonstrated by overlaying a polymer cladding on narrowed silicon wires. The ideal width to achieve athermal condition for the TE mode of 220 nm-height SOI waveguides is found to be around 350 nm. After overlaying a polymer layer, the wavelength temperature dependence of the silicon ring resonator is reduced to less than 5 pm/degrees C, almost eleven times less than that of normal silicon waveguides. The optical loss of a 350-nm bent waveguide (with a radius of 15 microm) is extracted from the ring transmission spectrum. The scattering loss is reduced to an acceptable level of about 50 dB/cm after overlaying a polymer cladding. (c) 2009 Optical Society of America

Push-broom imaging spectrometer based on planar lightwave circuit MZI array

NASA Astrophysics Data System (ADS)

Yang, Minyue; Li, Mingyu; He, Jian-Jun

2017-05-01

We propose a large aperture static imaging spectrometer (LASIS) based on planar lightwave circuit (PLC) MZI array. The imaging spectrometer works in the push-broom mode with the spectrum performed by interferometry. While the satellite/aircraft is orbiting, the same source, seen from the satellite/aircraft, moves across the aperture and enters different MZIs, while adjacent sources enter adjacent MZIs at the same time. The on-chip spectrometer consists of 256 input mode converters, followed by 256 MZIs with linearly increasing optical path delays and a detector array. Multiple chips are stick together to form the 2D image surface and receive light from the imaging lens. Two MZI arrays are proposed, one works in wavelength ranging from 500nm to 900nm with SiON(refractive index 1.6) waveguides and another ranging from 1100nm to 1700nm with SOI platform. To meet the requirements of imaging spectrometer applications, we choose large cross-section ridge waveguide to achieve polarization insensitive, maintain single mode propagation in broad spectrum and increase production tolerance. The SiON on-chip spectrometer has a spectral resolution of 80cm-1 with a footprint of 17×15mm2 and the SOI based on-chip spectrometer has a resolution of 38cm-1 with a size of 22×19mm2. The spectral and space resolution of the imaging spectrometer can be further improved by simply adding more MZIs. The on-chip waveguide MZI array based Fourier transform imaging spectrometer can provide a highly compact solution for remote sensing on unmanned aerial vehicles or satellites with advantages of small size, light weight, no moving parts and large input aperture.

George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

NASA Astrophysics Data System (ADS)

Chen, Tze-Chiang (T. C.)

The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

Integration of solid-state nanopores in a 0.5 μm cmos foundry process

PubMed Central

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Single Versus Multiple Solid Organ Injuries Following Blunt Abdominal Trauma.

PubMed

El-Menyar, Ayman; Abdelrahman, Husham; Al-Hassani, Ammar; Peralta, Ruben; AbdelAziz, Hiba; Latifi, Rifat; Al-Thani, Hassan

2017-11-01

We aimed to describe the pattern of solid organ injuries (SOIs) and analyze the characteristics, management and outcomes based on the multiplicity of SOIs. A retrospective study in a Level 1 trauma center was conducted and included patients admitted with blunt abdominal trauma between 2011 and 2014. Data were analyzed and compared for patients with single versus multiple SOIs. A total of 504 patients with SOIs were identified with a mean age of 28 ± 13 years. The most frequently injured organ was liver (45%) followed by spleen (30%) and kidney (18%). One-fifth of patients had multiple SOIs, of that 87% had two injured organs. Patients with multiple SOIs had higher frequency of head injury and injury severity scores (p < 0.05). The majority of SOIs were treated nonoperatively, whereas operative management was required in a quarter of patients, mostly in patients with multiple SOIs (p = 0.01). Blood transfusion, sepsis and hospital stay were greater in multiple than single SOIs (p < 0.05). The overall mortality was 11% which was comparable between the two groups. In patients with single SOIs, the mortality was significantly higher in those who had pancreatic (28.6%) or hepatic injuries (13%) than the other SOIs. SOIs represent one-tenth of trauma admissions in Qatar. Although liver was the most frequently injured organ, the rate of mortality was higher in pancreatic injury. Patients with multiple SOIs had higher morbidity which required frequent operative management. Further prospective studies are needed to develop management algorithm based on the multiplicity of SOIs.

Loss analysis and optimum design of a highly efficient and compact CMOS DC–DC converter with novel transistor layout using 60 nm multipillar-type vertical body channel MOSFET

NASA Astrophysics Data System (ADS)

Itoh, Kazuki; Endoh, Tetsuo

2018-04-01

In this paper, we present a novel transistor layout of multi pillar-type vertical body-channel (BC) MOSFET for cascode power switches for improving the efficiency and compactness of CMOS DC–DC converters. The proposed layout features a stacked and multifingered layout to suppress the loss due to parasitic components such as diffusion resistance and contact resistance. In addition, the loss of each MOSFET, which configures cascode power switches, is analyzed, and it is revealed that the total optimum gate width and loss with the high-side (HS) n-type MOSFET topology are 27 and 16% smaller than those with the HS p-type MOSFET topology, respectively. Moreover, a circuit simulation of 2.0 to 0.8 V, 100 MHz CMOS DC–DC converters with the proposed layout is carried out by using experimentally extracted models of BSIM4 60 nm vertical BC MOSFETs. The peak efficiency of the HS n-type MOSFET converter with the proposed layout is 90.1%, which is 6.0% higher than that with the conventional layout.

In vitro near-infrared imaging of occlusal dental caries using a germanium-enhanced CMOS camera

NASA Astrophysics Data System (ADS)

Lee, Chulsung; Darling, Cynthia L.; Fried, Daniel

2010-02-01

The high transparency of dental enamel in the near-infrared (NIR) at 1310-nm can be exploited for imaging dental caries without the use of ionizing radiation. The objective of this study was to determine whether the lesion contrast derived from NIR transillumination can be used to estimate lesion severity. Another aim was to compare the performance of a new Ge enhanced complementary metal-oxide-semiconductor (CMOS) based NIR imaging camera with the InGaAs focal plane array (FPA). Extracted human teeth (n=52) with natural occlusal caries were imaged with both cameras at 1310-nm and the image contrast between sound and carious regions was calculated. After NIR imaging, teeth were sectioned and examined using more established methods, namely polarized light microscopy (PLM) and transverse microradiography (TMR) to calculate lesion severity. Lesions were then classified into 4 categories according to the lesion severity. Lesion contrast increased significantly with lesion severity for both cameras (p<0.05). The Ge enhanced CMOS camera equipped with the larger array and smaller pixels yielded higher contrast values compared with the smaller InGaAs FPA (p<0.01). Results demonstrate that NIR lesion contrast can be used to estimate lesion severity.

In vitro near-infrared imaging of occlusal dental caries using germanium enhanced CMOS camera.

PubMed

Lee, Chulsung; Darling, Cynthia L; Fried, Daniel

2010-03-01

The high transparency of dental enamel in the near-infrared (NIR) at 1310-nm can be exploited for imaging dental caries without the use of ionizing radiation. The objective of this study was to determine whether the lesion contrast derived from NIR transillumination can be used to estimate lesion severity. Another aim was to compare the performance of a new Ge enhanced complementary metal-oxide-semiconductor (CMOS) based NIR imaging camera with the InGaAs focal plane array (FPA). Extracted human teeth (n=52) with natural occlusal caries were imaged with both cameras at 1310-nm and the image contrast between sound and carious regions was calculated. After NIR imaging, teeth were sectioned and examined using more established methods, namely polarized light microscopy (PLM) and transverse microradiography (TMR) to calculate lesion severity. Lesions were then classified into 4 categories according to the lesion severity. Lesion contrast increased significantly with lesion severity for both cameras (p<0.05). The Ge enhanced CMOS camera equipped with the larger array and smaller pixels yielded higher contrast values compared with the smaller InGaAs FPA (p<0.01). Results demonstrate that NIR lesion contrast can be used to estimate lesion severity.

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

PubMed

Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

2008-07-30

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC

DOE PAGES

Demaria, N.

2016-12-21

This paper is a review of recent progress of RD53 Collaboration. Results obtained on the study of the radiation effects on 65 nm CMOS have matured enough to define first strategies to adopt in the design of analog and digital circuits. Critical building blocks and analog very front end chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64×64 pixels with complex digital architectures have been produced, and point to address the main issues of dealing with extremely high pixel rates, while operating at very small in-time thresholds in the analog front end. Lastly, the collaborationmore » is now proceeding at full speed towards the design of a large scale prototype, called RD53A, in 65 nm CMOS technology.« less

A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maj, Piotr; Grybos, P.; Szczgiel, R.

2013-11-07

We present a prototype chip in 40 nm CMOS technology for readout of hybrid pixel detector. The prototype chip has a matrix of 18x24 pixels with a pixel pitch of 100 μm. It can operate both in single photon counting (SPC) mode and in C8P1 mode. In SPC the measured ENC is 84 e ₋rms (for the peaking time of 48 ns), while the effective offset spread is below 2 mV rms. In the C8P1 mode the chip reconstructs full charge deposited in the detector, even in the case of charge sharing, and it identifies a pixel with the largestmore » charge deposition. The chip architecture and preliminary measurements are reported.« less

Carrier-transport mechanism of Er-silicide Schottky contacts to strained-silicon-on-insulator and silicon-on-insulator.

PubMed

Jyothi, I; Janardhanam, V; Kang, Min-Sung; Yun, Hyung-Joong; Lee, Jouhahn; Choi, Chel-Jong

2014-11-01

The current-voltage characteristics and the carrier-transport mechanism of the Er-silicide (ErSi1.7) Schottky contacts to strained-silicon-on-insulator (sSOI) and silicon-on-insulator (SOI) were investigated. Barrier heights of 0.74 eV and 0.82 eV were obtained for the sSOI and SOI structures, respectively. The barrier height of the sSOI structure was observed to be lower than that of the SoI structure despite the formation of a Schottky contact using the same metal silicide. The sSOI structure exhibited better rectification and higher current level than the SOI structure, which could be associated with a reduction in the band gap of Si caused by strain. The generation-recombination mechanism was found to be dominant in the forward bias for both structures. Carrier generation along with the Poole-Frenkel mechanism dominated the reverse-biased current in the SOI structure. The saturation tendency of the reverse leakage current in the sSOI structure could be attributed to strain-induced defects at the interface in non-lattice-matched structures.

Analysis of Aluminum-Nitride SOI for High-Temperature Electronics

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Osman, Mohamed A.; Yu, Zhiping

2000-01-01

We use numerical simulation to investigate the high-temperature (up to 500K) operation of SOI MOSFETs with Aluminum-Nitride (AIN) buried insulators, rather than the conventional silicon-dioxide (SiO2). Because the thermal conductivity of AIN is about 100 times that of SiO2, AIN SOI should greatly reduce the often severe self-heating problem of conventional SOI, making SOI potentially suitable for high-temperature applications. A detailed electrothermal transport model is used in the simulations, and solved with a PDE solver called PROPHET In this work, we compare the performance of AIN-based SOI with that of SiO2-based SOI and conventional MOSFETs. We find that AIN SOI does indeed remove the self-heating penalty of SOL However, several device design trade-offs remain, which our simulations highlight.

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

NASA Technical Reports Server (NTRS)

Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

2014-01-01

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

Board-level optical clock signal distribution using Si CMOS-compatible polyimide-based 1- to 48-fanout H-tree

NASA Astrophysics Data System (ADS)

Wu, Linghui; Bihari, Bipin; Gan, Jianhua; Chen, Ray T.; Tang, Suning

1998-08-01

Si-CMOS compatible polymer-based waveguides for optoelectronic interconnects and packaging have been fabricated and characterized. A 1-to-48 fanout optoelectronic interconnection layer (OIL) structure based on Ultradel 9120/9020 for the high-speed massive clock signal distribution for a Cray T-90 supercomputer board has been constructed. The OIL employs multimode polymeric channel waveguides in conjunction with surface-normal waveguide output coupler and 1-to-2 splitter. A total insertion loss of 7.98 dB at 850 nm was measured experimentally.

Characterizations of and Radiation Effects in Several Emerging CMOS Technologies

NASA Astrophysics Data System (ADS)

Shufeng Ren

As the conventional scaling of Si based CMOS is approaching its limit at 7 nm technology node, many perceive that the adoption of novel materials and/or device structures are inevitable to keep Moore's law going. High mobility channel materials such as III-V compound semiconductors or Ge are considered promising to replace Si in order to achieve high performance as well as low power consumption. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, GaAs, InGaAs, GaSb, etc) to replace Si CMOS technology. Therefore novel high-k dielectrics, such as epitaxially grown crystalline oxides, have been explored to be incorporated onto the high mobility channel materials. Moreover, to enable continued scaling, extremely scaled devices structures such as nanowire gate-all-around structure are needed in the near future. Moreover, as the CMOS industry moves into the 7 nm node and beyond, novel lithography techniques such as EUV are believed to be adopted soon, which can bring radiation damage to CMOS devices and circuit during the fabrication process. Therefore radiation hardening technology in future generations of CMOS devices has again become an interesting research topic to deal with the possible process-induced damage as well as damage caused by operating in radiation harsh environment such as outer space, nuclear plant, etc. In this thesis, the electrical properties of a few selected emerging novel CMOS devices are investigated, which include InGaAs based extremely scaled ultra-thin body nanowire gate-all-around MOSFETs, GOI (Ge On Insulator) CMOS with recessed channel and source/drain, GaAs MOSFETs with crystalline La based gate stack, and crystalline SrTiO3, are investigated to extend our understanding of their electrical characteristics, underlying physical mechanisms, and material properties. Furthermore, the radiation responses of these aforementioned novel devices are thoroughly investigated, with a focus on the total ionizing dose (TID) effect, to understand the associated physical mechanisms, and to help to inspire ideas to improve radiation immunity of these novel devices. The experimental methods used in this thesis research include the measurements of C-V, I-V characteristics, where novel gate stack and interface characterization techniques are employed, such as AC Gm method, 1/f low frequency noise method, inelastic electron tunneling spectroscopy (IETS) for chemical bonding and defects detection, and carrier transport modeling. Sentaurus TCAD simulations are also carried out to obtain more physical insight in the complex, extremely scaled, device structures.

Silicon-on-insulator-based polarization-independent 1×3 broadband beam splitter with adiabatic coupling

NASA Astrophysics Data System (ADS)

Gong, Yuanhao; Liu, Lei; Chang, Limin; Li, Zhiyong; Tan, Manqing; Yu, Yude

2017-10-01

We propose and numerically simulate a polarization-independent 1×3 broadband beam splitter based on silicon-on-insulator (SOI) technology with adiabatic coupling. The designed structure is simulated by beam-propagation-method (BPM) and gets simulated transmission uniformity of three outputs better than 0.3dB for TE-polarization and 0.8dB for TM-polarization in a broadband of 180nm.

Non-periodic high-index contrast gratings reflector with large-angle beam forming ability

NASA Astrophysics Data System (ADS)

Fang, Wenjing; Huang, Yongqing; Duan, Xiaofeng; Fei, Jiarui; Ren, Xiaomin; Mao, Min

2016-05-01

A non-periodic high-index contrast gratings (HCGs) reflector on SOI wafer with large-angle beam forming ability has been proposed and fabricated. The proposed reflector was designed using rigorous coupled-wave analysis (RCWA) and finite-element-method (FEM). A deflection angle of 17.35° and high reflectivity of 92.31% are achieved under transverse magnetic (TM) polarized light in numerical simulation. Experimental results show that the reflected power peaked at 17.2° under a 1550 nm incident light, which is in good accordance with the simulation results. Moreover, the reflected power spectrum was also measured. Under different incident wavelengths around 1550 nm, reflected powers all peaked at 17.2°. The results show that the proposed non-periodic HCGs reflector has a good reflection and beam forming ability in a wavelength range as wide as 40 nm around 1550 nm.

Development Status of Optical and Electromagnetic Instruments onboard JEM-GLIMS

NASA Astrophysics Data System (ADS)

Sato, Mitsuteru; Ushio, Tomoo; Morimoto, Takeshi; Suzuki, Makoto; Yamazaki, Atsushi; Ishida, Ryohei; Takahashi, Yukihiro; Hobara, Yasuhide; Sakamoto, Yuji; Yoshita, Kengo

In order to study the generation mechanism of Transient Luminous Events (TLEs), global oc-currence rates and distributions of lightning and TLEs, and the relationship between lightning, TLEs and Terrestrial Gamma-ray Flashes (TGFs), we will carry out the lightning and TLE observation at Exposed Facility of Japanese Experiment Module (JEM-EF) of International Space Station (ISS). In this mission named JEM-GLIMS (Global Lightning and sprIte Mea-surementS on JEM-EF) two kinds of optical instruments and two sets of radio receivers will be integrated into the Multi mission Consolidated Equipment (MCE) which is the bus system and will be installed at JEM-EF. The optical instruments consist of two wide FOV CMOS cameras and six wide FOV photometers, and all these optical instruments are pointed to the nadir direction. CMOS cameras named LSI (Lightning and Sprite Imager) use the STAR-250 device as a detector, which has 512x512 pixels and 25x25 µm pixel size, and have 28.3x28.3 deg. FOV. One CMOS camera with a wide band filter (730-830 nm) mainly measures lightning emission, while another camera with a narrowband filter (766+/-6 nm) mainly measures TLE emission. Five of six photometers named as PH have 42.7 deg. FOV and use photomultiplier tube (PMT) as a photon detector. They equip band-pass filters (150-280 nm, 316+/-5 nm, 337+/-5 nm, 392+/-5 nm, and 762+/-5 nm) for the absolute intensity measurement of the TLE emission. One of six photometers equips a wide-band filter (600-900 nm) to detect light-ning occurring within 86.8 deg. FOV. These output signals will be recorded with the sampling frequency of 20 kHz with a 12-bit resolution. One of two electromagnetic instruments is a VLF receiver (VLFR), which measures electromagnetic waves in the frequency range of 1-40 kHz with 16-bit resolution. Another instrument is VHF interferometer (VITF), which measures VHF pulses generated lightning discharge in the frequency range of 70-100 MHz. JEM-GIMS will be launched in 2011. We have passed the critical design review (CDR) on January and February and have started the fabrication of the proto-flight model. We will present the devel-opment status of the JEM-GLISM optical instruments and discuss the scientific outputs derived from this mission more in detail.

NASA Tech Briefs, March 2009

NASA Technical Reports Server (NTRS)

2009-01-01

Topics covered include: Improved Instrument for Detecting Water and Ice in Soil; Real-Time Detection of Dust Devils from Pressure Readings; Determining Surface Roughness in Urban Areas Using Lidar Data; DSN Data Visualization Suite; Hamming and Accumulator Codes Concatenated with MPSK or QAM; Wide-Angle-Scanning Reflectarray Antennas Actuated by MEMS; Biasable Subharmonic Membrane Mixer for 520 to 600 GHz; Hardware Implementation of Serially Concatenated PPM Decoder; Symbolic Processing Combined with Model-Based Reasoning; Presentation Extensions of the SOAP; Spreadsheets for Analyzing and Optimizing Space Missions; Processing Ocean Images to Detect Large Drift Nets; Alternative Packaging for Back-Illuminated Imagers; Diamond Machining of an Off-Axis Biconic Aspherical Mirror; Laser Ablation Increases PEM/Catalyst Interfacial Area; Damage Detection and Self-Repair in Inflatable/Deployable Structures; Polyimide/Glass Composite High-Temperature Insulation; Nanocomposite Strain Gauges Having Small TCRs; Quick-Connect Windowed Non-Stick Penetrator Tips for Rapid Sampling; Modeling Unsteady Cavitation and Dynamic Loads in Turbopumps; Continuous-Flow System Produces Medical-Grade Water; Discrimination of Spore-Forming Bacilli Using spoIVA; nBn Infrared Detector Containing Graded Absorption Layer; Atomic References for Measuring Small Accelerations; Ultra-Broad-Band Optical Parametric Amplifier or Oscillator; Particle-Image Velocimeter Having Large Depth of Field; Enhancing SERS by Means of Supramolecular Charge Transfer; Improving 3D Wavelet-Based Compression of Hyperspectral Images; Improved Signal Chains for Readout of CMOS Imagers; SOI CMOS Imager with Suppression of Cross-Talk; Error-Rate Bounds for Coded PPM on a Poisson Channel; Biomorphic Multi-Agent Architecture for Persistent Computing; and Using Covariance Analysis to Assess Pointing Performance.

A new single-photon avalanche diode in 90nm standard CMOS technology.

PubMed

Karami, Mohammad Azim; Gersbach, Marek; Yoon, Hyung-June; Charbon, Edoardo

2010-10-11

We report on the first implementation of a single-photon avalanche diode (SPAD) in 90nm complementary metal oxide semiconductor (CMOS) technology. The detector features an octagonal multiplication region and a guard ring to prevent premature edge breakdown using a standard mask set exclusively. The proposed structure emerged from a systematic study aimed at miniaturization, while optimizing overall performance. The guard ring design is the result of an extensive modeling effort aimed at constraining the multiplication region within a well-defined area where the electric field exceeds the critical value for impact ionization. The device exhibits a dark count rate of 8.1 kHz, a maximum photon detection probability of 9% and the jitter of 398ps at a wavelength of 637nm, all of them measured at room temperature and 0.13V of excess bias voltage. An afterpulsing probability of 32% is achieved at the nominal dead time. Applications include time-of-flight 3D vision, fluorescence lifetime imaging microscopy, fluorescence correlation spectroscopy, and time-resolved gamma/X-ray imaging. Standard characterization of the SPAD was performed in different bias voltages and temperatures.

Gun muzzle flash detection using a CMOS single photon avalanche diode

NASA Astrophysics Data System (ADS)

Merhav, Tomer; Savuskan, Vitali; Nemirovsky, Yael

2013-10-01

Si based sensors, in particular CMOS Image sensors, have revolutionized low cost imaging systems but to date have hardly been considered as possible candidates for gun muzzle flash detection, due to performance limitations, and low SNR in the visible spectrum. In this study, a CMOS Single Photon Avalanche Diode (SPAD) module is used to record and sample muzzle flash events in the visible spectrum, from representative weapons, common on the modern battlefield. SPADs possess two crucial properties for muzzle flash imaging - Namely, very high photon detection sensitivity, coupled with a unique ability to convert the optical signal to a digital signal at the source pixel, thus practically eliminating readout noise. This enables high sampling frequencies in the kilohertz range without SNR degradation, in contrast to regular CMOS image sensors. To date, the SPAD has not been utilized for flash detection in an uncontrolled environment, such as gun muzzle flash detection. Gun propellant manufacturers use alkali salts to suppress secondary flashes ignited during the muzzle flash event. Common alkali salts are compounds based on Potassium or Sodium, with spectral emission lines around 769nm and 589nm, respectively. A narrow band filter around the Potassium emission doublet is used in this study to favor the muzzle flash signal over solar radiation. This research will demonstrate the SPAD's ability to accurately sample and reconstruct the temporal behavior of the muzzle flash in the visible wavelength under the specified imaging conditions. The reconstructed signal is clearly distinguishable from background clutter, through exploitation of flash temporal characteristics.

Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect

NASA Astrophysics Data System (ADS)

Belfiore, Guido; Szilagyi, Laszlo; Henker, Ronny; Ellinger, Frank

2015-09-01

This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm2. The driver can achieve an error-free (BER < 10 -12) electrical data-rate of 25 Gbit/s using a pseudo random bit sequence of 27 -1. When the driver is connected to the VCSEL module an open optical eye is reported at 15 Gbit/s. In the tested bias point the VCSEL module has a measured bandwidth of 10.7 GHz.

A 60 GOPS/W, -1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology

NASA Astrophysics Data System (ADS)

Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, Andrea; Flatresse, Philippe; Benini, Luca

2016-03-01

Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable Human-Computer Interfaces. A promising approach to achieve up to one order of magnitude of improvement in energy efficiency over current generation of integrated circuits is near-threshold computing. However, frequency degradation due to aggressive voltage scaling may not be acceptable across all performance-constrained applications. Thread-level parallelism over multiple cores can be used to overcome the performance degradation at low voltage. Moreover, enabling the processors to operate on-demand and over a wide supply voltage and body bias ranges allows to achieve the best possible energy efficiency while satisfying a large spectrum of computational demands. In this work we present the first ever implementation of a 4-core cluster fabricated using conventional-well 28 nm UTBB FD-SOI technology. The multi-core architecture we present in this work is able to operate on a wide range of supply voltages starting from 0.44 V to 1.2 V. In addition, the architecture allows a wide range of body bias to be applied from -1.8 V to 0.9 V. The peak energy efficiency 60 GOPS/W is achieved at 0.5 V supply voltage and 0.5 V forward body bias. Thanks to the extended body bias range of conventional-well FD-SOI technology, high energy efficiency can be guaranteed for a wide range of process and environmental conditions. We demonstrate the ability to compensate for up to 99.7% of chips for process variation with only ±0.2 V of body biasing, and compensate temperature variation in the range -40 °C to 120 °C exploiting -1.1 V to 0.8 V body biasing. When compared to leading-edge near-threshold RISC processors optimized for extremely low power applications, the multi-core architecture we propose has 144× more performance at comparable energy efficiency levels. Even when compared to other low-power processors with comparable performance, including those implemented in 28 nm technology, our platform provides 1.4× to 3.7× better energy efficiency.

30GHz Ge electro-absorption modulator integrated with 3 μm silicon-on-insulator waveguide.

PubMed

Feng, Ning-Ning; Feng, Dazeng; Liao, Shirong; Wang, Xin; Dong, Po; Liang, Hong; Kung, Cheng-Chih; Qian, Wei; Fong, Joan; Shafiiha, Roshanak; Luo, Ying; Cunningham, Jack; Krishnamoorthy, Ashok V; Asghari, Mehdi

2011-04-11

We demonstrate a compact waveguide-based high-speed Ge electro-absorption (EA) modulator integrated with a single mode 3 µm silicon-on-isolator (SOI) waveguide. The Ge EA modulator is based on a horizontally-oriented p-i-n structure butt-coupled with a deep-etched silicon waveguide, which transitions adiabatically to a shallow-etched single mode large core SOI waveguide. The demonstrated device has a compact active region of 1.0 × 45 µm(2), a total insertion loss of 2.5-5 dB and an extinction ratio of 4-7.5 dB over a wavelength range of 1610-1640 nm with -4V(pp) bias. The estimated Δα/α value is in the range of 2-3.3. The 3 dB bandwidth measurements show that the device is capable of operating at more than 30 GHz. Clear eye-diagram openings at 12.5 Gbps demonstrates large signal modulation at high transmission rate. © 2011 Optical Society of America

Electrical characterization of vertically stacked p-FET SOI nanowires

NASA Astrophysics Data System (ADS)

Cardoso Paz, Bruna; Cassé, Mikaël; Barraud, Sylvain; Reimbold, Gilles; Vinet, Maud; Faynot, Olivier; Antonio Pavanello, Marcelo

2018-03-01

This work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S&R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with [1 1 0]- and [1 0 0]-oriented channels, as a function of both fin width (WFIN) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15 nm gate length, for both orientations. Effective mobility is found around two times higher for [1 1 0]- in comparison to [1 0 0]-oriented NWs due to higher holes mobility contribution in (1 1 0) plan. Improvements obtained on ION/IOFF by reducing WFIN are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for [1 1 0]- and [1 0 0]-oriented NWs, respectively.

Lasing in silicon–organic hybrid waveguides

PubMed Central

Korn, Dietmar; Lauermann, Matthias; Koeber, Sebastian; Appel, Patrick; Alloatti, Luca; Palmer, Robert; Dumon, Pieter; Freude, Wolfgang; Leuthold, Juerg; Koos, Christian

2016-01-01

Silicon photonics enables large-scale photonic–electronic integration by leveraging highly developed fabrication processes from the microelectronics industry. However, while a rich portfolio of devices has already been demonstrated on the silicon platform, on-chip light sources still remain a key challenge since the indirect bandgap of the material inhibits efficient photon emission and thus impedes lasing. Here we demonstrate a class of infrared lasers that can be fabricated on the silicon-on-insulator (SOI) integration platform. The lasers are based on the silicon–organic hybrid (SOH) integration concept and combine nanophotonic SOI waveguides with dye-doped organic cladding materials that provide optical gain. We demonstrate pulsed room-temperature lasing with on-chip peak output powers of up to 1.1 W at a wavelength of 1,310 nm. The SOH approach enables efficient mass-production of silicon photonic light sources emitting in the near infrared and offers the possibility of tuning the emission wavelength over a wide range by proper choice of dye materials and resonator geometry. PMID:26949229

Post-Deployment Reintegration Experiences of AF Personnel: Implications for Scale Development

DTIC Science & Technology

2006-09-01

peuvent également présenter des avantages, notamment une amélioration aux points de vue suivants : confiance en soi , tolérance à l’égard de soi...notamment une amélioration aux points de vue suivants : confiance en soi , tolérance à l’égard de soi, compréhension politique et compétence militaire... confiance en soi , tolérance à l’égard de soi, compréhension politique et compétence militaire. À ce jour, les études sur l’expérience de réinsertion

Hybrid CMOS-Graphene Sensor Array for Subsecond Dopamine Detection.

PubMed

Nasri, Bayan; Wu, Ting; Alharbi, Abdullah; You, Kae-Dyi; Gupta, Mayank; Sebastian, Sunit P; Kiani, Roozbeh; Shahrjerdi, Davood

2017-12-01

We introduce a hybrid CMOS-graphene sensor array for subsecond measurement of dopamine via fast-scan cyclic voltammetry (FSCV). The prototype chip has four independent CMOS readout channels, fabricated in a 65-nm process. Using planar multilayer graphene as biologically compatible sensing material enables integration of miniaturized sensing electrodes directly above the readout channels. Taking advantage of the chemical specificity of FSCV, we introduce a region of interest technique, which subtracts a large portion of the background current using a programmable low-noise constant current at about the redox potentials. We demonstrate the utility of this feature for enhancing the sensitivity by measuring the sensor response to a known dopamine concentration in vitro at three different scan rates. This strategy further allows us to significantly reduce the dynamic range requirements of the analog-to-digital converter (ADC) without compromising the measurement accuracy. We show that an integrating dual-slope ADC is adequate for digitizing the background-subtracted current. The ADC operates at a sampling frequency of 5-10 kHz and has an effective resolution of about 60 pA, which corresponds to a theoretical dopamine detection limit of about 6 nM. Our hybrid sensing platform offers an effective solution for implementing next-generation FSCV devices that can enable precise recording of dopamine signaling in vivo on a large scale.

A CMOS Low-Power Optical Front-End for 5 Gbps Applications

NASA Astrophysics Data System (ADS)

Zohoori, Soorena; Dolatshahi, Mehdi

2018-01-01

In this paper, a new low-power optical receiver front-end is proposed in 90 nm CMOS technology for 5 Gb/s AApplications. However, to improve the gain-bandwidth trade-off, the proposed Trans-Impedance Amplifier (TIA) uses an active modified inverter-based topology followed by a common-source amplifier, which uses active inductive peaking technique to enhance the frequency bandwidth in an increased gain level for a reasonable power consumption value. The proposed TIA is analyzed and simulated in HSPICE using 90 nm CMOS technology parameters. Simulation results show a 53.5dBΩ trans-impedance gain, 3.5 GHz frequency bandwidth, 16.8pA/√Hz input referred noise, and 1.28 mW of power consumption at 1V supply voltage. The Optical receiver is completed using three stages of differential limiting amplifiers (LAs), which provide 27 dB voltage gain while consume 3.1 mW of power. Finally, the whole optical receiver front-end consumes only 5.6 mW of power at 1 V supply and amplifies the input signal by 80 dB, while providing 3.7 GHz of frequency bandwidth. Finally, the simulation results indicate that the proposed optical receiver is a proper candidate to be used in a low-power 5 Gbps optical communication system.

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of +/-500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.

Hybrid Quantum Cascade Lasers on Silicon-on-Sapphire

DTIC Science & Technology

2016-11-23

on-SOS devices mounted on a copper heat sink. The liquid crystal thermal absorber is attached to block mid-IR emission from any sections of the laser...directions. 2. Statement of the problem studied Short-wavelength infrared (SWIR, ~1-3 m) photonics systems based on silicon-on- insulator (SOI...Table 1. Layer type Layer thickness and doping Thickness (nm) Doping (cm-3) InP substrate 350000 Semi- insulating InP buffer layer 2000 2.00E

Modeling and experimental investigation of an integrated optical microheater in silicon-on-insulator.

PubMed

Kaushal, Saket; Das, Bijoy Krishna

2016-04-10

A linear piecewise model has been formulated to analyze the performance of a metallic microheater integrated with single-mode waveguides (λ∼1550  nm) in silicon-on-insulator (SOI). The model has been used to evaluate integrated optical microheaters fabricated in a SOI substrate with 2 µm device layer thickness. The Fabry-Perot modulation technique has been used to extract the effective thermo-optic phase shift and response time. The effective thermal power budget of P_eff,π∼500  µW (out of actually consumed power P_π=1.1  mW) for a π phase shift and a switching time of τ∼9  µs, have been recorded for a typical Ti heater stripe of length L_H=50  µm, width W_H=2  µm, and thickness t_H∼150  nm, integrated with a Fabry-Perot waveguide cavity of length ∼20  mm. It has been shown that the performance of a heater improves (in terms of power budget) as the length of a microheater decreases. However, smaller heater size requires higher joule heating to obtain a desired phase shift, which is again found to be dependent on polarization of the guided mode because of thermal stress.

An optofluidic metasurface for lateral flow-through detection of breast cancer biomarker.

PubMed

Wang, Yifei; Ali, Md Azahar; Chow, Edmond K C; Dong, Liang; Lu, Meng

2018-06-01

The rapid growth of point-of-care tests demands for biosensors with high sensitivity and small size. This paper demonstrates an optofluidic metasurface that combines silicon-on-insulator (SOI) nanophotonics and nanofluidics to realize a high-performance, lateral flow-through biosensor. The metasurface is made of a periodic array of silicon nanoposts on an SOI substrate, and functionalized with specific receptor molecules. Bonding of a polydimethylsiloxane slab directly onto the surface results in an ultracompact biosensor, where analyte solutions are restricted to flow only in the space between the nanoposts. No flow exists above the nanoposts. This sensor design overcomes the issue with diffusion-limited detection of many other biosensors. The lateral flow-through feature, in conjunction with high-Q resonance modes associated with optical bound states of the metasurface, offers an improved sensitivity to subtle molecule-bonding induced changes in refractive index. The device exhibits a resonance mode around 1550 nm wavelength and provides an index sensitivity of 720 nm/RIU. Biosensing is conducted to detect the epidermal growth factor receptor 2 (ErbB2), a protein biomarker for early-stage breast cancer screening, by monitoring resonance wavelength shifts in response to specific analyte-ligand binding events at the metasurface. The limit of detection of the device is 0.7 ng mL -1 for ErbB2. Copyright © 2018 Elsevier B.V. All rights reserved.

Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

PubMed

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

A Low-Power High-Speed Smart Sensor Design for Space Exploration Missions

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi

1997-01-01

A low-power high-speed smart sensor system based on a large format active pixel sensor (APS) integrated with a programmable neural processor for space exploration missions is presented. The concept of building an advanced smart sensing system is demonstrated by a system-level microchip design that is composed with an APS sensor, a programmable neural processor, and an embedded microprocessor in a SOI CMOS technology. This ultra-fast smart sensor system-on-a-chip design mimics what is inherent in biological vision systems. Moreover, it is programmable and capable of performing ultra-fast machine vision processing in all levels such as image acquisition, image fusion, image analysis, scene interpretation, and control functions. The system provides about one tera-operation-per-second computing power which is a two order-of-magnitude increase over that of state-of-the-art microcomputers. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and advanced VLSI system-on-a-chip implementation.

Radiation Status of Sub-65 nm Electronics

NASA Technical Reports Server (NTRS)

Pellish, Jonathan A.

2011-01-01

Ultra-scaled complementary metal oxide semiconductor (CMOS) includes commercial foundry capabilities at and below the 65 nm technology node Radiation evaluations take place using standard products and test characterization vehicles (memories, logic/latch chains, etc.) NEPP focus is two-fold: (1) Conduct early radiation evaluations to ascertain viability for future NASA missions (i.e. leverage commercial technology development). (2) Uncover gaps in current testing methodologies and mechanism comprehension -- early risk mitigation.

Second Harmonic Generation characterization of SOI wafers: Impact of layer thickness and interface electric field

NASA Astrophysics Data System (ADS)

Damianos, D.; Vitrant, G.; Lei, M.; Changala, J.; Kaminski-Cachopo, A.; Blanc-Pelissier, D.; Cristoloveanu, S.; Ionica, I.

2018-05-01

In this work, we investigate Second Harmonic Generation (SHG) as a non-destructive characterization method for Silicon-On-Insulator (SOI) materials. For thick SOI stacks, the SHG signal is related to the thickness variations of the different layers. However, in thin SOI films, the comparison between measurements and optical modeling suggests a supplementary SHG contribution attributed to the electric fields at the SiO2/Si interfaces. The impact of the electric field at each interface of the SOI on the SHG is assessed. The SHG technique can be used to evaluate interfacial electric fields and consequently interface charge density in SOI materials.

A 0.18 μm CMOS fluorescent detector system for bio-sensing application

NASA Astrophysics Data System (ADS)

Nan, Liu; Guoping, Chen; Zhiliang, Hong

2009-01-01

A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a 'contact imaging' detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm2 and consumes 37 mW.

Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Kremastiotis, I.

2017-12-01

The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128×128 square pixels with 25μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (~20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ~20 ns for a power consumption of 5μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (~20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using future assemblies with the readout chip.

High speed photodiodes in standard nanometer scale CMOS technology: a comparative study.

PubMed

Nakhkoob, Behrooz; Ray, Sagar; Hella, Mona M

2012-05-07

This paper compares various techniques for improving the frequency response of silicon photodiodes fabricated in mainstream CMOS technology for fully integrated optical receivers. The three presented photodiodes, Spatially Modulated Light detectors, Double, and Interrupted P-Finger photodiodes, aim at reducing the low speed diffusive component of the photo generated current. For the first photodiode, Spatially Modulated Light (SML) detectors, the low speed current component is canceled out by converting it to a common mode current driving a differential transimpedance amplifier. The Double Photodiode (DP) uses two depletion regions to increase the fast drift component, while the Interrupted-P Finger Photodiode (IPFPD) redirects the low speed component towards a different contact from the main fast terminal of the photodiode. Extensive device simulations using 130 nm CMOS technology-parameters are presented to compare their performance using the same technological platform. Finally a new type of photodiode that uses triple well CMOS technology is introduced that can achieve a bandwidth of roughly 10 GHz without any process modification or high reverse bias voltages that would jeopardize the photodetector and subsequent transimpedance amplifier reliability.

Detection of Short-Waved Spin Waves in Individual Microscopic Spin-Wave Waveguides Using the Inverse Spin Hall Effect.

PubMed

Brächer, T; Fabre, M; Meyer, T; Fischer, T; Auffret, S; Boulle, O; Ebels, U; Pirro, P; Gaudin, G

2017-12-13

The miniaturization of complementary metal-oxide-semiconductor (CMOS) devices becomes increasingly difficult due to fundamental limitations and the increase of leakage currents. Large research efforts are devoted to find alternative concepts that allow for a larger data-density and lower power consumption than conventional semiconductor approaches. Spin waves have been identified as a potential technology that can complement and outperform CMOS in complex logic applications, profiting from the fact that these waves enable wave computing on the nanoscale. The practical application of spin waves, however, requires the demonstration of scalable, CMOS compatible spin-wave detection schemes in material systems compatible with standard spintronics as well as semiconductor circuitry. Here, we report on the wave-vector independent detection of short-waved spin waves with wavelengths down to 150 nm by the inverse spin Hall effect in spin-wave waveguides made from ultrathin Ta/Co 8 Fe 72 B 20 /MgO. These findings open up the path for miniaturized scalable interconnects between spin waves and CMOS and the use of ultrathin films made from standard spintronic materials in magnonics.

Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

NASA Technical Reports Server (NTRS)

Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

2015-01-01

Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

Thermal Radiometer Signal Processing using Radiation Hard CMOS Application Specific Integrated Circuits for use in Harsh Planetary Environments

NASA Astrophysics Data System (ADS)

Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

2015-10-01

Thermal radiometers such as proposed for the Europa Clipper flyby mission [1] require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-cm2/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

A CMOS Front-End With Integrated Magnetoresistive Sensors for Biomolecular Recognition Detection Applications.

PubMed

Costa, Tiago; Cardoso, Filipe A; Germano, Jose; Freitas, Paulo P; Piedade, Moises S

2017-10-01

The development of giant magnetoresistive (GMR) sensors has demonstrated significant advantages in nanomedicine, particularly for ultrasensitive point-of-care diagnostics. To this end, the detection system is required to be compact, portable, and low power consuming at the same time that a maximum signal to noise ratio is maintained. This paper reports a CMOS front-end with integrated magnetoresistive sensors for biomolecular recognition detection applications. Based on the characterization of the GMR sensor's signal and noise, CMOS building blocks (i.e., current source, multiplexers, and preamplifier) were designed targeting a negligible noise when compared with the GMR sensor's noise and a low power consumption. The CMOS front-end was fabricated using AMS [Formula: see text] technology and the magnetoresistive sensors were post-fabricated on top of the CMOS chip with high yield ( [Formula: see text]). Due to its low circuit noise (16 [Formula: see text]) and overall equivalent magnetic noise ([Formula: see text]), the full system was able to detect 250 nm magnetic nanoparticles with a circuit imposed signal-to-noise ratio degradation of only -1.4 dB. Furthermore, the low power consumption (6.5 mW) and small dimensions ([Formula: see text] ) of the presented solution guarantees the portability of the detection system allowing its usage at the point-of-care.

Investigation of veritcal graded channel doping in nanoscale fully-depleted SOI-MOSFET

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2016-10-01

For achieving reliable transistor, we investigate an amended channel doping (ACD) engineering which improves the electrical and thermal performances of fully-depleted silicon-on-insulator (SOI) MOSFET. We have called the proposed structure with the amended channel doping engineering as ACD-SOI structure and compared it with a conventional fully-depleted SOI MOSFET (C-SOI) with uniform doping distribution using 2-D ATLAS simulator. The amended channel doping is a vertical graded doping that is distributed from the surface of structure with high doping density to the bottom of channel, near the buried oxide, with low doping density. Short channel effects (SCEs) and leakage current suppress due to high barrier height near the source region and electric field modification in the ACD-SOI in comparison with the C-SOI structure. Furthermore, by lower electric field and electron temperature near the drain region that is the place of hot carrier generation, we except the improvement of reliability and gate induced drain lowering (GIDL) in the proposed structure. Undesirable Self heating effect (SHE) that become a critical challenge for SOI MOSFETs is alleviated in the ACD-SOI structure because of utilizing low doping density near the buried oxide. Thus, refer to accessible results, the ACD-SOI structure with graded distribution in vertical direction is a reliable device especially in low power and high temperature applications.

Self-heating and scaling of thin body transistors

NASA Astrophysics Data System (ADS)

Pop, Eric

The most often cited technological roadblock of nanoscale electronics is the "power problem," i.e. power densities and device temperatures reaching levels that will prevent their reliable operation. Technology roadmap (ITRS) requirements are expected to lead to more heat dissipation problems, especially with the transition towards geometrically confined device geometries (SOI, FinFET, nanowires), and new materials with poor thermal properties. This work examines the physics of heat generation in silicon, and in the context of nanoscale CMOS transistors. A new Monte Carlo code (MONET) is introduced which uses analytic descriptions of both the electron bands and the phonon dispersion. Detailed heat generation statistics are computed in bulk and strained silicon, and within simple device geometries. It is shown that non-stationary transport affects heat generation near strongly peaked electric fields, and that self-heating occurs almost entirely in the drain end of short, quasi-ballistic devices. The dissipated power is spectrally distributed between the (slow) optical and (fast) acoustic phonon modes approximately by a ratio of two to one. In addition, this work explores the limits of device design and scaling from an electrical and thermal point of view. A self-consistent electro-thermal compact model for thin-body (SOI, GOI) devices is introduced for calculating operating temperature, saturation current and intrinsic gate delay. Self-heating is sensitive to several device parameters, such as raised source/drain height and material boundary thermal resistance. An experimental method is developed for extracting via/contact thermal resistance from electrical measurements. The analysis suggests it is possible to optimize device geometry in order to simultaneously minimize operating temperature and intrinsic gate delay. Electro-thermal contact and device design are expected to become more important with continued scaling.

An IO block array in a radiation-hardened SOI SRAM-based FPGA

NASA Astrophysics Data System (ADS)

Yan, Zhao; Lihua, Wu; Xiaowei, Han; Yan, Li; Qianli, Zhang; Liang, Chen; Guoquan, Zhang; Jianzhong, Li; Bo, Yang; Jiantou, Gao; Jian, Wang; Ming, Li; Guizhai, Liu; Feng, Zhang; Xufeng, Guo; Kai, Zhao; Chen, Stanley L.; Fang, Yu; Zhongli, Liu

2012-01-01

We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field-programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si), a dose survivability rate of 1.5 × 1011 rad(Si)/s, and a neutron fluence immunity of 1 × 1014 n/cm2.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Performance analysis of SOI MOSFET with rectangular recessed channel

NASA Astrophysics Data System (ADS)

Singh, M.; Mishra, S.; Mohanty, S. S.; Mishra, G. P.

2016-03-01

In this paper a two dimensional (2D) rectangular recessed channel-silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.

324GHz CMOS VCO Using Linear Superimposition Technique

NASA Technical Reports Server (NTRS)

Daquan, Huang; LaRocca, Tim R.; Samoska, Lorene A; Fung, Andy; Chang, Frank

2007-01-01

Terahertz (frequencies ranged from 300GHz to 3THz) imaging and spectroscopic systems have drawn increasing attention recently due to their unique capabilities in detecting and possibly analyzing concealed objects. The generation of terahertz signals is nonetheless nontrivial and traditionally accomplished by using either free-electron radiation, optical lasers, Gunn diodes or fundamental oscillation by using III-V based HBT/HEMT technology[1-3]... We have substantially extended the operation range of deep-scaled CMOS by using a linear superimposition method, in which we have realized a 324GHz VCO in 90nm digital CMOS with 4GHz tuning range under 1V supply voltage. This may also pave the way for ultra-high data rate wireless communications beyond that of IEEE 802.15.3c and reach data rates comparable to that of fiber optical communications, such as OC768 (40Gbps) and beyond.

Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

NASA Astrophysics Data System (ADS)

Kremastiotis, I.; Ballabriga, R.; Campbell, M.; Dannheim, D.; Fiergolski, A.; Hynds, D.; Kulis, S.; Peric, I.

2017-09-01

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128×128 square pixels with 25μm pitch. First prototypes have been produced with a standard resistivity of ~20 Ωcm for the substrate and tested in standalone mode. The results show a rise time of ~20 ns, charge gain of 190 mV/ke- and ~40 e- RMS noise for a power consumption of 4.8μW/pixel. The main design aspects, as well as standalone measurement results, are presented.

Investigation of radiation hardened SOI wafer fabricated by ion-cut technique

NASA Astrophysics Data System (ADS)

Chang, Yongwei; Wei, Xing; Zhu, Lei; Su, Xin; Gao, Nan; Dong, Yemin

2018-07-01

Total ionizing dose (TID) effect on Silicon-on-Insulator (SOI) wafers due to inherent buried oxide (BOX) is a significant concern as it leads to the degradation of electrical properties of SOI-based devices and circuits, even failures of the systems associated with them. This paper reports the radiation hardening implementation of SOI wafer fabricated by ion-cut technique integrated with low-energy Si+ implantation. The electrical properties and radiation response of pseudo-MOS transistors are analyzed. The results demonstrate that the hardening process can significantly improve the TID tolerance of SOI wafers by generating Si nanocrystals (Si-NCs) within the BOX. The presence of Si-NCs created through Si+ implantation is evidenced by high-resolution transmission electron microscopy (HR-TEM). Under the pass gate (PG) irradiation bias, the anti-radiation properties of H-gate SOI nMOSFETs suggest that the radiation hardened SOI wafers with optimized Si implantation dose can perform effectively in a radiation environment. The radiation hardening process provides an excellent way to reinforce the TID tolerance of SOI wafers.

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

NASA Astrophysics Data System (ADS)

Yuan, Shoucai; Liu, Yamei

2016-08-01

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

SOI layout decomposition for double patterning lithography on high-performance computer platforms

NASA Astrophysics Data System (ADS)

Verstov, Vladimir; Zinchenko, Lyudmila; Makarchuk, Vladimir

2014-12-01

In the paper silicon on insulator layout decomposition algorithms for the double patterning lithography on high performance computing platforms are discussed. Our approach is based on the use of a contradiction graph and a modified concurrent breadth-first search algorithm. We evaluate our technique on 45 nm Nangate Open Cell Library including non-Manhattan geometry. Experimental results show that our soft computing algorithms decompose layout successfully and a minimal distance between polygons in layout is increased.

Frequency Dependence of Single-Event Upset in Highly Advanced PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad; White, Mark; Kouba, Coy K.

2006-01-01

Single-event upset effects from heavy ions were measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes at three frequencies of 500, 1066 and 1600 MHz. Frequency dependence of single-event upsets is discussed. The results of our studies suggest the single-event upset in registers and D-Cache tend to increase with frequency. This might have important implications for the overall single-event upset trend as technology moves toward higher frequencies.

Experimental study of the spatially-modulated light detector

NASA Astrophysics Data System (ADS)

Coppée, Daniël; Pan, Wei; Stiens, Johan; Vounckx, Roger; Kuijk, Maarten

1999-03-01

Usually, integrated detectors in CMOS exhibit long recovery times, limiting the detector bandwidth to only a few MHz. This is due to the long absorption length and the slow diffusion speed of photo-generated carriers. Different approaches have been proposed to solve these problems hereby taxing the compatibility with standard CMOS fabrication processing. We present a novel detector for high-speed light detection in standard CMOS. To solve the problem of slow CMOS-detector recovery, the incident light is spatially modulated and the spatially modulated component of the photo-generated carrier distribution is measured. Though only a single light input signal is required, from the detector on, analog signal processing can be achieved fully differentially. Subsequently, expected good PSRR (Power supply rejection ratio) allows integration with digital circuits. Avoiding hybridization eliminates the conventional problems caused by bonding-pad capacitance, bonding-wire inductance. This reduces the associated signal degradation. In addition, the very low detector capacitance, due to the low effectively used detector area and the low area capacitance of the n-well junction, yields high voltage readout of the detector. This facilitates further amplification and conversion to digital signal levels. The detector will be applicable in arrays due to expected low cross talk. The expected fields of operation involve: serial and parallel optical communication receivers (e.g. for WDM), DVD-reading heads with integrated amplifier, etc. First measurements show 200 Mbit/s operation with a detector-responsivity of 0.05 A/W at λ=860 nm and 0.132 A/W at λ=635 nm. The detector has inherently a low capacitance, in this case only 50 fF (for an effective detector area of 70×70 μm 2).

A novel nanoscale SOI MOSFET by embedding undoped region for improving self-heating effect

NASA Astrophysics Data System (ADS)

Ghaffari, Majid; Orouji, Ali A.

2018-06-01

Because of the low thermal conductivity of the SiO2 (oxide), the Buried Oxide (BOX) layer in a Silicon-On-Insulator Metal-Oxide Semiconductor Field-Effect Transistor (SOI MOSFET) prevents heat dissipation in the silicon layer and causes increase in the device lattice temperature. In this paper, a new technique is proposed for reducing Self-Heating Effects (SHEs). The key idea in the proposed structure is using a Silicon undoped Region (SR) in the nanoscale SOI MOSFET under the drain and channel regions in order to decrease the SHE. The novel transistor is named Silicon undoped Region SOI-MOSFET (SR-SOI). Due to the embedded silicon undoped region in the suitable place, the proposed structure has decreased the device lattice temperature. The location and dimensions of the proposed region have been carefully optimized to achieve the best results. This work has explored enhancement such as decreased maximum lattice temperature, increased electron mobility, increased drain current, lower DC drain conductance and higher DC transconductance and also decreased bandgap energy variations. Also, for modeling of the structure in the SPICE tools, the main characterizations have been extracted such as thermal resistance (RTH), thermal capacitance (CTH), and SHE characteristic frequency (fTH). All parameters are extracted in relation with the AC operation indicate excellent performance of the SR-SOI device. The results show that proposed region is a suitable alternative to oxide as a part of the buried oxide layer in SOI structures and has better performance in high temperature. Using two-dimensional (2-D) and two-carrier device simulation is done comparison of the SR-SOI structure with a Conventional SOI (C-SOI). As a result, the SR-SOI device can be regarded as a useful substitution for the C-SOI device in nanoscale integrated circuits as a reliable device.

New integration concept of PIN photodiodes in 0.35μm CMOS technologies

NASA Astrophysics Data System (ADS)

Jonak-Auer, I.; Teva, J.; Park, J. M.; Jessenig, S.; Rohrbacher, M.; Wachmann, E.

2012-06-01

We report on a new and very cost effective way to integrate PIN photo detectors into a standard CMOS process. Starting with lowly p-doped (intrinsic) EPI we need just one additional mask and ion implantation in order to provide doping concentrations very similar to standard CMOS substrates to areas outside the photoactive regions. Thus full functionality of the standard CMOS logic can be guaranteed while the photo detectors highly benefit from the low doping concentrations of the intrinsic EPI. The major advantage of this integration concept is that complete modularity of the CMOS process remains untouched by the implementation of PIN photodiodes. Functionality of the implanted region as host of logic components was confirmed by electrical measurements of relevant standard transistor as well as ESD protection devices. We also succeeded in establishing an EPI deposition process in austriamicrosystems 200mm wafer fabrication which guarantees the formation of very lowly p-doped intrinsic layers, which major semiconductor vendors could not provide. With our EPI deposition process we acquire doping levels as low as 1•1012/cm3. In order to maintain those doping levels during CMOS processing we employed special surface protection techniques. After complete CMOS processing doping concentrations were about 4•1013/cm3 at the EPI surface while the bulk EPI kept its original low doping concentrations. Photodiode parameters could further be improved by bottom antireflective coatings and a special implant to reduce dark currents. For 100×100μm2 photodiodes in 20μm thick intrinsic EPI on highly p-doped substrates we achieved responsivities of 0.57A/W at λ=675nm, capacitances of 0.066pF and dark currents of 0.8pA at 2V reverse voltage.

Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor - System-on-a-Chip

NASA Technical Reports Server (NTRS)

Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

2015-01-01

Hardness assurance test results of Intel state-of-the-art 14nm Broadwell U-series processor System-on-a-Chip (SoC) for total dose are presented, along with first-look exploratory results from trials at a medical proton facility. Test method builds upon previous efforts by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

The Bridges SOI Model School Program at Palo Verde School, Palo Verde, Arizona.

ERIC Educational Resources Information Center

Stock, William A.; DiSalvo, Pamela M.

The Bridges SOI Model School Program is an educational service based upon the SOI (Structure of Intellect) Model School curriculum. For the middle seven months of the academic year, all students in the program complete brief daily exercises that develop specific cognitive skills delineated in the SOI model. Additionally, intensive individual…

Nondestructive assessment of the severity of occlusal caries lesions with near-infrared imaging at 1310 nm.

PubMed

Lee, Chulsung; Lee, Dustin; Darling, Cynthia L; Fried, Daniel

2010-01-01

The high transparency of dental enamel in the near-infrared (NIR) at 1310 nm can be exploited for imaging dental caries without the use of ionizing radiation. The objective of this study is to determine whether the lesion contrast derived from NIR imaging in both transmission and reflectance can be used to estimate lesion severity. Two NIR imaging detector technologies are investigated: a new Ge-enhanced complementary metal-oxide-semiconductor (CMOS)-based NIR imaging camera, and an InGaAs focal plane array (FPA). Natural occlusal caries lesions are imaged with both cameras at 1310 nm, and the image contrast between sound and carious regions is calculated. After NIR imaging, teeth are sectioned and examined using polarized light microscopy (PLM) and transverse microradiography (TMR) to determine lesion severity. Lesions are then classified into four categories according to lesion severity. Lesion contrast increases significantly with lesion severity for both cameras (p<0.05). The Ge-enhanced CMOS camera equipped with the larger array and smaller pixels yields higher contrast values compared with the smaller InGaAs FPA (p<0.01). Results demonstrate that NIR lesion contrast can be used to estimate lesion severity.

Nondestructive assessment of the severity of occlusal caries lesions with near-infrared imaging at 1310 nm

PubMed Central

Lee, Chulsung; Lee, Dustin; Darling, Cynthia L.; Fried, Daniel

2010-01-01

The high transparency of dental enamel in the near-infrared (NIR) at 1310 nm can be exploited for imaging dental caries without the use of ionizing radiation. The objective of this study is to determine whether the lesion contrast derived from NIR imaging in both transmission and reflectance can be used to estimate lesion severity. Two NIR imaging detector technologies are investigated: a new Ge-enhanced complementary metal-oxide-semiconductor (CMOS)-based NIR imaging camera, and an InGaAs focal plane array (FPA). Natural occlusal caries lesions are imaged with both cameras at 1310 nm, and the image contrast between sound and carious regions is calculated. After NIR imaging, teeth are sectioned and examined using polarized light microscopy (PLM) and transverse microradiography (TMR) to determine lesion severity. Lesions are then classified into four categories according to lesion severity. Lesion contrast increases significantly with lesion severity for both cameras (p<0.05). The Ge-enhanced CMOS camera equipped with the larger array and smaller pixels yields higher contrast values compared with the smaller InGaAs FPA (p<0.01). Results demonstrate that NIR lesion contrast can be used to estimate lesion severity. PMID:20799842

Nondestructive assessment of the severity of occlusal caries lesions with near-infrared imaging at 1310 nm

NASA Astrophysics Data System (ADS)

Lee, Chulsung; Lee, Dustin; Darling, Cynthia L.; Fried, Daniel

2010-07-01

The high transparency of dental enamel in the near-infrared (NIR) at 1310 nm can be exploited for imaging dental caries without the use of ionizing radiation. The objective of this study is to determine whether the lesion contrast derived from NIR imaging in both transmission and reflectance can be used to estimate lesion severity. Two NIR imaging detector technologies are investigated: a new Ge-enhanced complementary metal-oxide-semiconductor (CMOS)-based NIR imaging camera, and an InGaAs focal plane array (FPA). Natural occlusal caries lesions are imaged with both cameras at 1310 nm, and the image contrast between sound and carious regions is calculated. After NIR imaging, teeth are sectioned and examined using polarized light microscopy (PLM) and transverse microradiography (TMR) to determine lesion severity. Lesions are then classified into four categories according to lesion severity. Lesion contrast increases significantly with lesion severity for both cameras (p<0.05). The Ge-enhanced CMOS camera equipped with the larger array and smaller pixels yields higher contrast values compared with the smaller InGaAs FPA (p<0.01). Results demonstrate that NIR lesion contrast can be used to estimate lesion severity.

Integrating silicon photonic interconnects with CMOS: Fabrication to architecture

NASA Astrophysics Data System (ADS)

Sherwood, Nicholas Ramsey

While it was for many years the goal of microelectronics to speed up our daily tasks, the focus of today's technological developments is heavily centered on electronic media. Anyone can share their thoughts as text, sound, images or full videos, they can even make phone calls and download full movies on their computers, tablets and phones. The impact of this upsurge in bandwidth is directly on the infrastructure that carries this data. Long distance telecom lines were long ago replaced by optical fibers; now shorter and shorter distance connections have moved to optical transmission to keep up with the bandwidth requirements. Yet microprocessors that make up the switching nodes as well as the endpoints are not only stagnant in terms of processing speed, but also unlikely to continue Moore's transistor-doubling trend for much longer. Silicon photonics stands to make a technical leap in microprocessor technology by allowing monolithic communication speeds between arbitrarily spaced processing elements. The improvement in on-chip communication could reduce power and enable new improvements in this field. This work explores a few aspects involved in making such a leap practical in real life. The first part of the thesis develops process techniques and materials to make silicon photonics truly compatible with CMOS electronics, for two different stack layouts, including a glimpse into multilayerd photonics. Following this is an evaluation of the limitations of integrated devices and a post-fabrication/stabilizing solution using thermal index shifting. In the last parts we explore higher level device design and architecture on the SOI platform.

A third-order silicon racetrack add-drop filter with a moderate feature size

NASA Astrophysics Data System (ADS)

Wang, Ying; Zhou, Xin; Chen, Qian; Shao, Yue; Chen, Xiangning; Huang, Qingzhong; Jiang, Wei

2018-01-01

In this work, we design and fabricate a highly compact third-order racetrack add-drop filter consisting of silicon waveguides with modified widths on a silicon-on-insulator (SOI) wafer. Compared to the previous approach that requires an exceedingly narrow coupling gap less than 100nm, we propose a new approach that enlarges the minimum feature size of the whole device to be 300 nm to reduce the process requirement. The three-dimensional finite-difference time-domain (3D-FDTD) method is used for simulation. Experiment results show good agreement with simulation results in property. In the experiment, the filter shows a nearly box-like channel dropping response, which has a large flat 3-dB bandwidth ({3 nm), relatively large FSR ({13.3 nm) and out-of-band rejection larger than 14 dB at the drop port with a footprint of 0.0006 mm2 . The device is small and simple enough to have a wide range of applications in large scale on-chip photonic integration circuits.

Improved bandwidth and quantum efficiency in silicon photodiodes using photon-manipulating micro/nanostructures operating in the range of 700-1060 nm

NASA Astrophysics Data System (ADS)

Cansizoglu, Hilal; Gao, Yang; Ghandiparsi, Soroush; Kaya, Ahmet; Perez, Cesar Bartolo; Mayet, Ahmed; Ponizovskaya Devine, Ekaterina; Cansizoglu, Mehmet F.; Yamada, Toshishige; Elrefaie, Aly F.; Wang, Shih-Yuan; Islam, M. Saif

2017-08-01

Nanostructures allow broad spectrum and near-unity optical absorption and contributed to high performance low-cost Si photovoltaic devices. However, the efficiency is only a few percent higher than a conventional Si solar cell with thicker absorption layers. For high speed surface illuminated photodiodes, the thickness of the absorption layer is critical for short transit time and RC time. Recently a CMOS-compatible micro/nanohole silicon (Si) photodiode (PD) with more than 20 Gb/s data rate and with 52 % quantum efficiency (QE) at 850 nm was demonstrated. The achieved QE is over 400% higher than a similar Si PD with the same thickness but without absorption enhancement microstructure holes. The micro/nanoholes increases the QE by photon trapping, slow wave effects and generate a collective assemble of modes that radiate laterally, resulting in absorption enhancement and therefore increase in QE. Such Si PDs can be further designed to enhance the bandwidth (BW) of the PDs by reducing the device capacitance with etched holes in the pin junction. Here we present the BW and QE of Si PDs achievable with micro/nanoholes based on a combination of empirical evidence and device modeling. Higher than 50 Gb/s data rate with greater than 40% QE at 850 nm is conceivable in transceivers designed with such Si PDs that are integrated with photon trapping micro and nanostructures. By monolithic integration with CMOS/BiCMOS integrated circuits such as transimpedance amplifiers, equalizers, limiting amplifiers and other application specific integrated circuits (ASIC), the data rate can be increased to more than 50 Gb/s.

Stable and wavelength-tunable silicon-micro-ring-resonator based erbium-doped fiber laser.

PubMed

Yang, L G; Yeh, C H; Wong, C Y; Chow, C W; Tseng, F G; Tsang, H K

2013-02-11

In this work, we propose and demonstrate a stable and wavelength-tunable erbium-doped fiber (EDF) ring laser. Here, a silicon-on-insulator (SOI)-based silicon-micro-ring-resonator (SMRR) is used as the wavelength selective element inside the fiber ring cavity. A uniform period grating coupler (GC) is used to couple between the SMRR and single mode fiber (SMF) and serves also as a polarization dependent element in the cavity. The output lasing wavelength of the proposed fiber laser can be tuned at a tuning step of 2 nm (defined by the free spectral range (FSR) of the SMRR) in a bandwidth of 35.2 nm (1532.00 to 1567.20 nm), which is defined by the gain of the EDF. The optical-signal-to-noise-ratio (OSNR) of each lasing wavelength is larger than 42.0 dB. In addition, the output stabilities of power and wavelength are also discussed.

Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies

NASA Astrophysics Data System (ADS)

Vishnoi, U.; Noll, T. G.

2012-09-01

The COordinate Rotate DIgital Computer (CORDIC) algorithm is a well known versatile approach and is widely applied in today's SoCs for especially but not restricted to digital communications. Dedicated CORDIC blocks can be implemented in deep sub-micron CMOS technologies at very low area and energy costs and are attractive to be used as hardware accelerators for Application Specific Instruction Processors (ASIPs). Thereby, overcoming the well known energy vs. flexibility conflict. Optimizing Global Navigation Satellite System (GNSS) receivers to reduce the hardware complexity is an important research topic at present. In such receivers CORDIC accelerators can be used for digital baseband processing (fixed-point) and in Position-Velocity-Time estimation (floating-point). A micro architecture well suited to such applications is presented. This architecture is parameterized according to the wordlengths as well as the number of iterations and can be easily extended for floating point data format. Moreover, area can be traded for throughput by partially or even fully unrolling the iterations, whereby the degree of pipelining is organized with one CORDIC iteration per cycle. From the architectural description, the macro layout can be generated fully automatically using an in-house datapath generator tool. Since the adders and shifters play an important role in optimizing the CORDIC block, they must be carefully optimized for high area and energy efficiency in the underlying technology. So, for this purpose carry-select adders and logarithmic shifters have been chosen. Device dimensioning was automatically optimized with respect to dynamic and static power, area and performance using the in-house tool. The fully sequential CORDIC block for fixed-point digital baseband processing features a wordlength of 16 bits, requires 5232 transistors, which is implemented in a 40-nm CMOS technology and occupies a silicon area of 1560 μm2 only. Maximum clock frequency from circuit simulation of extracted netlist is 768 MHz under typical, and 463 MHz under worst case technology and application corner conditions, respectively. Simulated dynamic power dissipation is 0.24 uW MHz-1 at 0.9 V; static power is 38 uW in slow corner, 65 uW in typical corner and 518 uW in fast corner, respectively. The latter can be reduced by 43% in a 40-nm CMOS technology using 0.5 V reverse-backbias. These features are compared with the results from different design styles as well as with an implementation in 28-nm CMOS technology. It is interesting that in the latter case area scales as expected, but worst case performance and energy do not scale well anymore.

Design and Experimental Verification of a 0.19 V 53 μW 65 nm CMOS Integrated Supply-Sensing Sensor With a Supply-Insensitive Temperature Sensor and an Inductive-Coupling Transmitter for a Self-Powered Bio-sensing System Using a Biofuel Cell.

PubMed

Kobayashi, Atsuki; Ikeda, Kei; Ogawa, Yudai; Kai, Hiroyuki; Nishizawa, Matsuhiko; Nakazato, Kazuo; Niitsu, Kiichi

2017-12-01

In this paper, we present a self-powered bio-sensing system with the capability of proximity inductive-coupling communication for supply sensing and temperature monitoring. The proposed bio-sensing system includes a biofuel cell as a power source and a sensing frontend that is associated with the CMOS integrated supply-sensing sensor. The sensor consists of a digital-based gate leakage timer, a supply-insensitive time-domain temperature sensor, and a current-driven inductive-coupling transmitter and achieves low-voltage operation. The timer converts the output voltage from a biofuel cell to frequency. The temperature sensor provides a pulse width modulation (PWM) output that is not dependent on the supply voltage, and the associated inductive-coupling transmitter enables proximity communication. A test chip was fabricated in 65 nm CMOS technology and consumed 53 μW with a supply voltage of 190 mV. The low-voltage-friendly design satisfied the performance targets of each integrated sensor without any trimming. The chips allowed us to successfully demonstrate proximity communication with an asynchronous receiver, and the measurement results show the potential for self-powered operation using biofuel cells. The analysis and experimental verification of the system confirmed their robustness.

Integrated input protection against discharges for Micro Pattern Gas Detectors readout ASICs

NASA Astrophysics Data System (ADS)

Fiutowski, T.; Dąbrowski, W.; Koperny, S.; Wiącek, P.

2017-02-01

Immunity against possible random discharges inside active detector volume of MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC manufactured in a 350 nm CMOS process and test results using an electrical circuit to mimic discharges in the detectors.

A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel.

PubMed

Takahashi, Seiji; Huang, Yi-Min; Sze, Jhy-Jyi; Wu, Tung-Ting; Guo, Fu-Sheng; Hsu, Wei-Cheng; Tseng, Tung-Hsiung; Liao, King; Kuo, Chin-Chia; Chen, Tzu-Hsiang; Chiang, Wei-Chieh; Chuang, Chun-Hao; Chou, Keng-Yu; Chung, Chi-Hsien; Chou, Kuo-Yu; Tseng, Chien-Hsien; Wang, Chuan-Joung; Yaung, Dun-Nien

2017-12-05

A submicron pixel's light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e - /s at 60 °C, an ultra-low read noise of 0.90 e - ·rms, a high full well capacity (FWC) of 4100 e - , and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mamaluy, Denis; Gao, Xujiao; Tierney, Brian David

We created a highly efficient, universal 3D quant um transport simulator. We demonstrated that the simulator scales linearly - both with the problem size (N) and number of CPUs, which presents an important break-through in the field of computational nanoelectronics. It allowed us, for the first time, to accurately simulate and optim ize a large number of realistic nanodevices in a much shorter time, when compared to other methods/codes such as RGF[%7EN 2.333 ]/KNIT, KWANT, and QTBM[%7EN 3 ]/NEMO5. In order to determine the best-in-class for different beyond-CMOS paradigms, we performed rigorous device optimization for high-performance logic devices at 6-,more » 5- and 4-nm gate lengths. We have discovered that there exists a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs). We have found that, at room temperatures, all FETs, irre spective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths.« less

Collimation testing using slit Fresnel diffraction

NASA Astrophysics Data System (ADS)

Luo, Xiaohe; Hui, Mei; Wang, Shanshan; Hou, Yinlong; Zhou, Siyu; Zhu, Qiudong

2018-03-01

A simple collimation testing method based on slit Fresnel diffraction is proposed. The method needs only a CMOS and a slit with no requirement in dimensional accuracy. The light beam to be tested diffracts across the slit and forms a Fresnel diffraction pattern received by CMOS. After analysis, the defocusing amount and the distance between the primary peak point and secondary peak point of diffraction pattern fulfill an expression relationship and then the defocusing amount can be deduced from the expression. The method is applied to both the coherent beam and partially coherent beam, and these two beams are emitted from a laser and light-emitting diode (LED) with a spectrum width of about 50 nm in this paper. Simulations show that the wide spectrum of LED has the effect of smooth filtering to provide higher accuracy. Experiments show that the LED with a spectrum width of about 50 nm has a lower limitation error than the laser and can achieve up to 58.1601 μm with focal length 200 mm and slit width 15 mm.

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

NASA Astrophysics Data System (ADS)

Ishii, Yuichiro; Tanaka, Miki; Yabuuchi, Makoto; Sawada, Yohei; Tanaka, Shinji; Nii, Koji; Lu, Tien Yu; Huang, Chun Hsien; Sian Chen, Shou; Tse Kuo, Yu; Lung, Ching Cheng; Cheng, Osbert

2018-04-01

We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (I read) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (V min) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

Multiplexed Oversampling Digitizer in 65 nm CMOS for Column-Parallel CCD Readout

DOE Office of Scientific and Technical Information (OSTI.GOV)

Grace, Carl; Walder, Jean-Pierre; von der Lippe, Henrik

2012-04-10

A digitizer designed to read out column-parallel charge-coupled devices (CCDs) used for high-speed X-ray imaging is presented. The digitizer is included as part of the High-Speed Image Preprocessor with Oversampling (HIPPO) integrated circuit. The digitizer module comprises a multiplexed, oversampling, 12-bit, 80 MS/s pipelined Analog-to-Digital Converter (ADC) and a bank of four fast-settling sample-and-hold amplifiers to instrument four analog channels. The ADC multiplexes and oversamples to reduce its area to allow integration that is pitch-matched to the columns of the CCD. Novel design techniques are used to enable oversampling and multiplexing with a reduced power penalty. The ADC exhibits 188more » ?V-rms noise which is less than 1 LSB at a 12-bit level. The prototype is implemented in a commercially available 65 nm CMOS process. The digitizer will lead to a proof-of-principle 2D 10 Gigapixel/s X-ray detector.« less

Approaches of multilayer overlay process control for 28nm FD-SOI derivative applications

NASA Astrophysics Data System (ADS)

Duclaux, Benjamin; De Caunes, Jean; Perrier, Robin; Gatefait, Maxime; Le Gratiet, Bertrand; Chapon, Jean-Damien; Monget, Cédric

2018-03-01

Derivative technology like embedded Non-Volatile Memories (eNVM) is raising new types of challenges on the "more than Moore" path. By its construction: overlay is critical across multiple layers, by its running mode: usage of high voltage are stressing leakages and breakdown, and finally with its targeted market: Automotive, Industry automation, secure transactions… which are all requesting high device reliability (typically below 1ppm level). As a consequence, overlay specifications are tights, not only between one layer and its reference, but also among the critical layers sharing the same reference. This work describes a broad picture of the key points for multilayer overlay process control in the case of a 28nm FD-SOI technology and its derivative flows. First, the alignment trees of the different flow options have been optimized using a realistic process assumptions calculation for indirect overlay. Then, in the case of a complex alignment tree involving heterogeneous scanner toolset, criticality of tool matching between reference layer and critical layers of the flow has been highlighted. Improving the APC control loops of these multilayer dependencies has been studied with simulations of feed-forward as well as implementing new rework algorithm based on multi-measures. Finally, the management of these measurement steps raises some issues for inline support and using calculations or "virtual overlay" could help to gain some tool capability. A first step towards multilayer overlay process control has been taken.

Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor/System-on-a-Chip

NASA Technical Reports Server (NTRS)

Szabo, Carl M., Jr.; Duncan, Adam; LaBel, Kenneth A.; Kay, Matt; Bruner, Pat; Krzesniak, Mike; Dong, Lei

2015-01-01

Hardness assurance test results of Intel state-of-the-art 14nm “Broadwell” U-series processor / System-on-a-Chip (SoC) for total ionizing dose (TID) are presented, along with exploratory results from trials at a medical proton facility. Test method builds upon previous efforts [1] by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

Novel detectors for silicon based microdosimetry, their concepts and applications

NASA Astrophysics Data System (ADS)

Rosenfeld, Anatoly B.

2016-02-01

This paper presents an overview of the development of semiconductor microdosimetry and the most current (state-of-the-art) Silicon on Insulator (SOI) detectors for microdosimetry based mainly on research and development carried out at the Centre for Medical Radiation Physics (CMRP) at the University of Wollongong with collaborators over the last 18 years. In this paper every generation of CMRP SOI microdosimeters, including their fabrication, design, and electrical and charge collection characterisation are presented. A study of SOI microdosimeters in various radiation fields has demonstrated that under appropriate geometrical scaling, the response of SOI detectors with the well-known geometry of microscopically sensitive volumes will record the energy deposition spectra representative of tissue cells of an equivalent shape. This development of SOI detectors for microdosimetry with increased complexity has improved the definition of microscopic sensitive volume (SV), which is modelling the deposition of ionising energy in a biological cell, that are led from planar to 3D SOI detectors with an array of segmented microscopic 3D SVs. The monolithic ΔE-E silicon telescope, which is an alternative to the SOI silicon microdosimeter, is presented, and as an example, applications of SOI detectors and ΔE-E monolithic telescope for microdosimetery in proton therapy field and equivalent neutron dose measurements out of field are also presented. An SOI microdosimeter "bridge" with 3D SVs can derive the relative biological effectiveness (RBE) in 12C ion radiation therapy that matches the tissue equivalent proportional counter (TEPC) quite well, but with outstanding spatial resolution. The use of SOI technology in experimental microdosimetry offers simplicity (no gas system or HV supply), high spatial resolution, low cost, high count rates, and the possibility of integrating the system onto a single device with other types of detectors.

A device for multimodal imaging of skin

NASA Astrophysics Data System (ADS)

Spigulis, Janis; Garancis, Valerijs; Rubins, Uldis; Zaharans, Eriks; Zaharans, Janis; Elste, Liene

2013-03-01

A compact prototype device for diagnostic imaging of skin has been developed and tested. Polarized LED light at several spectral regions is used for illumination, and round skin spot of diameter 30mm is imaged by a CMOS sensor via crossoriented polarizing filter. Four consecutive imaging series are performed: (1) RGB image at white LED illumination for revealing subcutaneous structures; (2) four spectral images at narrowband LED illumination (450nm, 540nm, 660nm, 940nm) for mapping of the main skin chromophores; (3) video-imaging under green LED illumination for mapping of skin blood perfusion; (4) autofluorescence video-imaging under UV (365nm) LED irradiation for mapping of the skin fluorophores. Design details of the device as well as preliminary results of clinical tests are presented.

Investigation of AWG demultiplexer based SOI for CWDM application

NASA Astrophysics Data System (ADS)

Juhari, Nurjuliana; Susthitha Menon, P.; Shaari, Sahbudin; Annuar Ehsan, Abang

2017-11-01

9-channel Arrayed Waveguide Grating (AWG) demultiplexer for conventional and tapered structure were simulated using beam propagation method (BPM) with channel spacing of 20 nm. The AWG demultiplexer was design using high refractive index (n 3.47) material namely silicon-on-insulator (SOI) with rib waveguide structure. The characteristics of insertion loss, adjacent crosstalk and output spectrum response at central wavelength of 1.55 μm for both designs were compared and analyzed. The conventional AWG produced a minimum insertion loss of 6.64 dB whereas the tapered AWG design reduced the insertion loss by 2.66 dB. The lowest adjacent crosstalk value of -16.96 dB was obtained in the conventional AWG design and this was much smaller compared to the tapered AWG design where the lowest crosstalk value is -17.23 dB. Hence, a tapered AWG design significantly reduces the insertion loss but has a slightly higher adjacent crosstalk compared to the conventional AWG design. On the other hand, the output spectrum responses that are obtained from both designs were close to the Coarse Wavelength Division Multiplexing (CWDM) wavelength grid.

Fabrication of high aspect ratio structure and its releasing for silicon on insulator MEMS/MOEMS device application

NASA Astrophysics Data System (ADS)

Fan, Ji; Zhang, Wen Ting; Liu, Jin Quan; Wu, Wen Jie; Zhu, Tao; Tu, Liang Cheng

2015-04-01

We systematically investigate the fabrication and dry-release technology for a high aspect ratio (HAR) structure with vertical and smooth silicon etching sidewalls. One-hundred-micrometer silicon on insulator (SOI) wafers are used in this work. By optimizing the process parameters of inductively coupled plasma deep reactive-ion etching, a HAR (˜25∶1) structure with a microtrench width of 4 μm has been demonstrated. A perfect etching profile has been obtained in which the structures present an almost perfect verticality of 0.10 μm and no sidewall scallops. The root-mean square roughness of silicon sidewalls is 20 to 29 nm. An in situ dry-release method using notching effect is employed after etching. By analysis, we found that the final notch length is typically an aspect-ratio-dependent process. The structure designed in this work has been successfully released by this in situ dry-release method, and the released bottom roughness effectively prohibits the stiction mechanism. The results demonstrate potential applications for design and fabrication of HAR SOI MEMS/MOEMS.

X-ray characterization of Ge dots epitaxially grown on nanostructured Si islands on silicon-on-insulator substrates.

PubMed

Zaumseil, Peter; Kozlowski, Grzegorz; Yamamoto, Yuji; Schubert, Markus Andreas; Schroeder, Thomas

2013-08-01

On the way to integrate lattice mismatched semiconductors on Si(001), the Ge/Si heterosystem was used as a case study for the concept of compliant substrate effects that offer the vision to be able to integrate defect-free alternative semiconductor structures on Si. Ge nanoclusters were selectively grown by chemical vapour deposition on Si nano-islands on silicon-on-insulator (SOI) substrates. The strain states of Ge clusters and Si islands were measured by grazing-incidence diffraction using a laboratory-based X-ray diffraction technique. A tensile strain of up to 0.5% was detected in the Si islands after direct Ge deposition. Using a thin (∼10 nm) SiGe buffer layer between Si and Ge the tensile strain increases to 1.8%. Transmission electron microscopy studies confirm the absence of a regular grid of misfit dislocations in such structures. This clear experimental evidence for the compliance of Si nano-islands on SOI substrates opens a new integration concept that is not only limited to Ge but also extendable to semiconductors like III-V and II-VI materials.

Electron beam patterning for writing of positively charged gold colloidal nanoparticles

NASA Astrophysics Data System (ADS)

Zafri, Hadar; Azougi, Jonathan; Girshevitz, Olga; Zalevsky, Zeev; Zitoun, David

2018-02-01

Synthesis at the nanoscale has progressed at a very fast pace during the last decades. The main challenge today lies in precise localization to achieve efficient nanofabrication of devices. In the present work, we report on a novel method for the patterning of gold metallic nanoparticles into nanostructures on a silicon-on-insulator (SOI) wafer. The fabrication makes use of relatively accessible equipment, a scanning electron microscope (SEM), and wet chemical synthesis. The electron beam implants electrons into the insulating material, which further anchors the positively charged Au nanoparticles by electrostatic attraction. The novel fabrication method was applied to several substrates useful in microelectronics to add plasmonic particles. The resolution and surface density of the deposition were tuned, respectively, by the electron energy (acceleration voltage) and the dose of electronic irradiation. We easily achieved the smallest written feature of 68 ± 18 nm on SOI, and the technique can be extended to any positively charged nanoparticles, while the resolution is in principle limited by the particle size distribution and the scattering of the electrons in the substrate. [Figure not available: see fulltext.

I-line stepper based overlay evaluation method for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard front side resist in resist experiment. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated and exposed. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 µm SiGe:C BiCMOS technology. The developed technique also allows using significantly smaller alignment marks (i.e. standard FIA alignment marks). Furthermore, the presented method is used, in case of wafer bow related overlay tool problems, for the overlay evaluation of the last two metal layers from production wafers prepared in IHP's standard 0.25/0.13 µm SiGe:C BiCMOS technology. In conclusion, the exposure and measurement job can be done with the same tool, minimizing the back to front side/interface top layer misalignment which leads to a significant device performance improvement of backside/TSV integrated components and technologies.

Concurrent rib and pelvic fractures as an indicator of solid abdominal organ injury.

PubMed

Al-Hassani, Ammar; Afifi, Ibrahim; Abdelrahman, Husham; El-Menyar, Ayman; Almadani, Ammar; Recicar, Jan; Al-Thani, Hassan; Maull, Kimball; Latifi, Rifat

2013-01-01

To study the association of solid organ injuries (SOIs) in patients with concurrent rib and pelvic fractures. Retrospective analysis of prospectively collected data from November 2007 to May 2010. Patients' demographics, mechanism of injury, Injury severity scoring, pelvic fracture, and SOIs were analyzed. Patients with SOIs were compared in rib fractures with and without pelvic fracture. The study included 829 patients (460 with rib fractures ± pelvic fracture and 369 with pelvic fracture alone) with mean age of 35 ± 12.7 years. Motor vehicle crashes (45%) and falls from height (30%) were the most common mechanism of injury. The overall incidence of SOIs in this study was 22% (185/829). Further, 15% of patient with rib fractures had associated pelvic fracture. SOI was predominant in patients with concurrent rib fracture and pelvic fracture compared to ribs or pelvic fractures alone (42% vs. 26% vs. 15%, respectively, p = 0.02). Concurrent multiple rib fractures and pelvic fracture increases the risk of SOI compared to either group alone. Lower RFs and pelvic fracture had higher association for SOI and could be used as an early indicator of the presence of SOIs. Copyright © 2013 Surgical Associates Ltd. Published by Elsevier Ltd. All rights reserved.

Submicron mapping of strained silicon-on-insulator features induced

NASA Astrophysics Data System (ADS)

Murray, Conal E.; Sankarapandian, M.; Polvino, S. M.; Noyan, I. C.; Lai, B.; Cai, Z.

2007-04-01

Real-space maps of strain within silicon-on-insulator (SOI) features induced by adjacent, embedded shallow-trench-isolation (STI) SiO2 regions were obtained using x-ray microbeam diffraction. The quantitative strain mapping indicated that the SOI strain was largest at the SOI/STI interface and decreased as a function of distance from this interface. An out-of-plane residual strain of approximately -31μɛ was observed in the blanket regions of the SOI. A comparison of the depth-averaged strain distributions to the strain profiles calculated from an Eshelby inclusion model indicated an equivalent eigenstrain of -0.55% in the STI regions acting on the SOI features.

Method to improve commercial bonded SOI material

DOEpatents

Maris, Humphrey John; Sadana, Devendra Kumar

2000-07-11

A method of improving the bonding characteristics of a previously bonded silicon on insulator (SOI) structure is provided. The improvement in the bonding characteristics is achieved in the present invention by, optionally, forming an oxide cap layer on the silicon surface of the bonded SOI structure and then annealing either the uncapped or oxide capped structure in a slightly oxidizing ambient at temperatures greater than 1200.degree. C. Also provided herein is a method for detecting the bonding characteristics of previously bonded SOI structures. According to this aspect of the present invention, a pico-second laser pulse technique is employed to determine the bonding imperfections of previously bonded SOI structures.

Multimodal device for assessment of skin malformations

NASA Astrophysics Data System (ADS)

Bekina, A.; Garancis, V.; Rubins, U.; Spigulis, J.; Valeine, L.; Berzina, A.

2013-11-01

A variety of multi-spectral imaging devices is commercially available and used for skin diagnostics and monitoring; however, an alternative cost-efficient device can provide an advanced spectral analysis of skin. A compact multimodal device for diagnosis of pigmented skin lesions was developed and tested. A polarized LED light source illuminates the skin surface at four different wavelengths - blue (450 nm), green (545 nm), red (660 nm) and infrared (940 nm). Spectra of reflected light from the 25 mm wide skin spot are imaged by a CMOS sensor. Four spectral images are obtained for mapping of the main skin chromophores. The specific chromophore distribution differences between different skin malformations were analyzed and information of subcutaneous structures was consecutively extracted.

Ion/Ioff ratio enhancement and scalability of gate-all-around nanowire negative-capacitance FET with ferroelectric HfO2

NASA Astrophysics Data System (ADS)

Jang, Kyungmin; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2017-10-01

We have investigated the energy efficiency and scalability of ferroelectric HfO2 (FE:HfO2)-based negative-capacitance field-effect-transistor (NCFET) with gate-all-around (GAA) nanowire (NW) channel structure. Analytic simulation is conducted to characterize NW-NCFET by varying NW diameter and/or thickness of gate insulator as device structural parameters. Due to the negative-capacitance effect and GAA NW channel structure, NW-NCFET is found to have 5× higher Ion/Ioff ratio than classical NW-MOSFET and 2× higher than double-gate (DG) NCFET, which results in wider design window for high Ion/Ioff ratio. To analyze these obtained results from the viewpoint of the device scalability, we have considered constraints regarding very limited device structural spaces to fit by the gate insulator and NW channel for aggresively scaled gate length (Lg) and/or very tight NW pitch. NW-NCFET still has design point with very thinned gate insulator and/or narrowed NW. Therefore, FE:HfO2-based NW-NCFET is applicable to the aggressively scaled technology node of sub-10 nm Lg and to the very tight NW integration of sub-30 nm NW pitch for beyond 7 nm technology. From 2011 to 2014, he engaged in developing high-speed optical transceiver module as an alternative military service in Republic of Korea. His research interest includes the development of steep slope MOSFETs for high energy-efficient operation and ferroelectric HfO2-based semiconductor devices, and fabrication of nanostructured devices. He joined the IBM T.J. Watson Research Center, Yorktown Heights, NY, in 2010, where he worked on advanced CMOS technologies such as FinFET, nanowire FET, SiGe channel and III-V channel. He was also engaged in launching 14 nm SOI FinFET and RMG technology development. Since 2014, he has been an Associate Professor in Institute of Industrial Science, University of Tokyo, Tokyo, Japan, where he has been working on ultralow power transistor and memory technology. Dr. Kobayashi is a member of IEEE and the Japan Society of Applied Physics. Dr. Hiramoto is a fellow of Japan Society of Applied Physics and a member of IEEE and IEICE. He served as the General Chair of Silicon Nanoelectronics Workshop in 2003 and the Program Chair in 1997, 1999, and 2001. He was on Committee of IEDM from 2003 to 2009. He was the Program Chair of Symposium on VLSI Technology in 2013 and was the General Chair in 2015. He is the Program Chair of International Conference on Solid-State Devices and Materials (SSDM) in 2016.

Design, fabrication, and characteristics of microheaters with low consumption power using SDB SOI membrane and trench structures

NASA Astrophysics Data System (ADS)

Chung, Gwiy-Sang; Choi, Sung-Kyu; Nam, Hoy-Duck

2001-10-01

This paper presents the optimized design, fabrication and thermal characteristics of micro-heaters for thermal MEMS (micro electro mechanical system) applications using SDB and SOI membranes and trench structures. The micro-heater is based on a thermal measurement principle and contains for thermal isolation regions a 10 micrometers thick Si membrane with oxide-filled trenches in the SOI membrane rim. The micro- heater was fabricated with Pt-RTD on the same substrate by using MgO as medium layer. The thermal characteristics of the micro-heater with the SOI membrane is 280 degree(s)C at input power 0.9 W; for the SOI membrane with 10 trenches, it is 580 degree(s)C due to reduction of the external thermal loss. Consequently, the micro-heater with trenches in SOI membrane rim provides a powerful and versatile alternative technology for improving the performance of micro-thermal sensors and actuators.

Recent developments using TowerJazz SiGe BiCMOS platform for mmWave and THz applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Howard, David; Preisler, Edward J.; Racanelli, Marco

2013-05-01

In this paper, we report on the highest speed 240GHz/340GHz FT/FMAX NPN which is now available for product designs in the SBC18H4 process variant of TowerJazz's mature 0.18μm SBC18 silicon germanium (SiGe) BiCMOS technology platform. NFMIN of ~2dB at 50GHz has been obtained with these NPNs. We also describe the integration of earlier generation NPNs with FT/FMAX of 240GHz/280GHz into SBC13H3, a 0.13μm SiGe BiCMOS technology platform. Next, we detail the integration of the deep silicon via (DSV), through silicon via (TSV), high-resistivity substrate, sub-field stitching and hybrid-stitching capability into the 0.18μm SBC18 technology platform to enable higher performance and highly integrated product designs. The integration of SBC18H3 into a thick-film SOI substrate, with essentially unchanged FT and FMAX, is also described. We also report on recent circuit demonstrations using the SBC18H3 platform: (1) a 4-element phased-array 70-100GHz broadband transmit and receive chip with flat saturated power greater than 5dBm and conversion gain of 33dB; (2) a fully integrated W-band 9-element phase-controllable array with responsivity of 800MV/W and receiver NETD is 0.45K with 20ms integration time; (3) a 16-element 4x4 phased-array transmitter with scanning in both the E- and H-planes with maximum EIRP of 23-25 dBm at 100-110GHz; (4) a power efficient 200GHz VCO with -7.25dBm output power and tuning range of 3.5%; and (5) a 320GHz 16-element imaging receiver array with responsivity of 18KV/W at 315GHz, a 3dB bandwidth of 25GHz and a low NEP of 34pW/Hz1/2. Wafer-scale large-die implementation of the phased-arrays and mmWave imagers using stitching in TowerJazz SBC18 process are also discussed.

Full control of the spin-wave damping in a magnetic insulator using spin orbit torque

NASA Astrophysics Data System (ADS)

Klein, Olivier

2015-03-01

The spin-orbit interaction (SOI) has been an interesting and useful addition in the field of spintronics by opening it to non-metallic magnet. It capitalizes on adjoining a strong SOI normal metal next to a thin magnetic layer. The SOI converts a charge current, Jc, into a spin current, Js, with an efficiency parametrized by ΘSH, the spin Hall angle. An important benefit of the SOI is that Jc and Js are linked through a cross-product, allowing a charge current flowing in-plane to produce a spin current flowing out-of-plane. Hence it enables the transfer of spin angular momentum to non-metallic materials and in particular to insulating oxides, which offer improved performance compared to their metallic counterparts. Among all oxides, Yttrium Iron Garnet (YIG) holds a special place for having the lowest known spin-wave (SW) damping factor. Until recently the transmission of spin current through the YIG|Pt interface has been subject to debate. While numerous experiments have reported that Js produced by the excitation of ferromagnetic resonance (FMR) in YIG can cross efficiently the YIG|Pt interface and be converted into Jc in Pt through the inverse spin Hall effect (ISHE), most attempts to observe the reciprocal effect, where Js produced in Pt by the direct spin Hall effect (SHE) is transferred to YIG, resulting in damping compensation, have failed. This has been raising fundamental questions about the reciprocity of the spin transparency of the interface between a metal and a magnetic insulator. In this talk it will be demonstrated that the threshold current for damping compensation can be reached in a 5 μm diameter YIG(20nm)|Pt(7nm) disk. Reduction of both the thickness and lateral size of a YIG-structure were key to reach the microwave generation threshold current, Jc*. The experimental evidence rests upon the measurement of the ferromagnetic resonance linewidth as a function of Idc using a magnetic resonance force microscope (MRFM). It is shwon that the magnetic losses of spin-wave modes existing in the magnetic insulator can be reduced or enhanced by at least a factor of five depending on the polarity and intensity of the in-plane dc current, Idc. Complete compensation of the damping of the fundamental mode by spin-orbit torque is reached for a current density of ~ 3 .1011 A.m-2, in agreement with theoretical predictions. At this critical threshold the MRFM detects a small change of static magnetization, a behavior consistent with the onset of an auto-oscillation regime. This result opens up a new area of research on the electronic control of the damping of YIG-nanostructures.

A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience

NASA Astrophysics Data System (ADS)

Li, Y.-Q.; Wang, H.-B.; Liu, R.; Chen, L.; Nofal, I.; Shi, S.-T.; He, A.-L.; Guo, G.; Baeg, S. H.; Wen, S.-J.; Wong, R.; Chen, M.; Wu, Q.

2017-06-01

A flip-flop circuit hardened against soft errors is presented in this paper. This design is an improved version of Quatro for further enhanced soft-error resilience by integrating the guard-gate technique. The proposed design, as well as reference Quatro and regular flip-flops, was implemented and manufactured in a 65-nm CMOS bulk technology. Experimental characterization results of their alpha and heavy ions soft-error rates verified the superior hardening performance of the proposed design over the other two circuits.

Annual Progress Report.

DTIC Science & Technology

1981-10-20

Jamming strategies. D W 3 k 4 2 i t-iew or I oev Be is o ~5e TU SS ia Y LA P 16CUTV10’:F-,n-zv fam o& nm.o ANNUAL PROGRESS REPORT for Office of Naval...7:ectrtcal Enineering and :ne j drtinateo lc.aqce ’_aboratory :nlersit )t :llinol$ It rbana-ChampaLgn -roana, Illinois ild~l Abstract La the...11 treat the related problems of -ioLsa ncortaincy. robust Winner filtering and minimax icace estima- n eac,, case :nere la Assumed to is sois

Nano-optical single-photon response mapping of waveguide integrated molybdenum silicide (MoSi) superconducting nanowires.

PubMed

Li, Jian; Kirkwood, Robert A; Baker, Luke J; Bosworth, David; Erotokritou, Kleanthis; Banerjee, Archan; Heath, Robert M; Natarajan, Chandra M; Barber, Zoe H; Sorel, Marc; Hadfield, Robert H

2016-06-27

We present low temperature nano-optical characterization of a silicon-on-insulator (SOI) waveguide integrated SNSPD. The SNSPD is fabricated from an amorphous Mo₈₃Si₁₇ thin film chosen to give excellent substrate conformity. At 350 mK, the SNSPD exhibits a uniform photoresponse under perpendicular illumination, corresponding to a maximum system detection efficiency of approximately 5% at 1550 nm wavelength. Under these conditions 10 Hz dark count rate and 51 ps full width at half maximum (FWHM) timing jitter is observed.

Practicality of Evaluating Soft Errors in Commercial sub-90 nm CMOS for Space Applications

NASA Technical Reports Server (NTRS)

Pellish, Jonathan A.; LaBel, Kenneth A.

2010-01-01

The purpose of this presentation is to: Highlight space memory evaluation evolution, Review recent developments regarding low-energy proton direct ionization soft errors, Assess current space memory evaluation challenges, including increase of non-volatile technology choices, and Discuss related testing and evaluation complexities.

Design trade-off between spatial resolution and power consumption in CMOS biosensor circuit based on millimeter-wave LC oscillator array

NASA Astrophysics Data System (ADS)

Matsunaga, Maya; Kobayashi, Atsuki; Nakazato, Kazuo; Niitsu, Kiichi

2018-03-01

In this paper, we describe a trade-off between spatial resolution and power consumption in an LC oscillator-based CMOS biosensor, which can detect biomolecules by observing the resonance frequency shift due to changes in the complex permittivity of the biomolecules. The optimal operating frequency and improvement in the image resolution of the sensor output require a reduction in the size of the inductor. However, it is necessary to increase the transconductance of the cross-coupling transistor to achieve the oscillation condition, although the power consumption increases. We confirmed the trade-off between the spatial resolution and the power consumption of this sensor using SPICE simulation. A test chip was fabricated using a 65 nm CMOS process, and the transition in the peak frequency and the power consumption were measured. When the outer diameter of the inductor was 46 µm, the power consumption was 31.2 mW, which matched well with the simulation results.

A 0.1-1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS

NASA Astrophysics Data System (ADS)

Guo, Benqing; Chen, Jun; Chen, Hongpeng; Wang, Xuebing

2018-01-01

An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 μm CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8-3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13-18.9 and 24-40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.

CMOS image sensor with lateral electric field modulation pixels for fluorescence lifetime imaging with sub-nanosecond time response

NASA Astrophysics Data System (ADS)

Li, Zhuo; Seo, Min-Woong; Kagawa, Keiichiro; Yasutomi, Keita; Kawahito, Shoji

2016-04-01

This paper presents the design and implementation of a time-resolved CMOS image sensor with a high-speed lateral electric field modulation (LEFM) gating structure for time domain fluorescence lifetime measurement. Time-windowed signal charge can be transferred from a pinned photodiode (PPD) to a pinned storage diode (PSD) by turning on a pair of transfer gates, which are situated beside the channel. Unwanted signal charge can be drained from the PPD to the drain by turning on another pair of gates. The pixel array contains 512 (V) × 310 (H) pixels with 5.6 × 5.6 µm2 pixel size. The imager chip was fabricated using 0.11 µm CMOS image sensor process technology. The prototype sensor has a time response of 150 ps at 374 nm. The fill factor of the pixels is 5.6%. The usefulness of the prototype sensor is demonstrated for fluorescence lifetime imaging through simulation and measurement results.

A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

PubMed Central

Chen, Min-Cheng; Chen, Hao-Yu; Lin, Chia-Yi; Chien, Chao-Hsin; Hsieh, Tsung-Fan; Horng, Jim-Tong; Qiu, Jian-Tai; Huang, Chien-Chao; Ho, Chia-Hua; Yang, Fu-Liang

2012-01-01

This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording. PMID:22666012

A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

PubMed

Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

2014-10-01

This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

REVIEW ARTICLE: Medical implants based on microsystems

NASA Astrophysics Data System (ADS)

Mokwa, W.

2007-05-01

The fast development of CMOS technologies to smaller dimensions led to very high integration densities with complex circuitry on very small chip areas. In 2006 Intel fabricated the first products in a 65 nm technology. The cointegration of microsensors or actuators together with the very low power consumption of the CMOS circuitry is very well suited for use in implanted systems. Applications like intracranial or intraocular pressure measurements have become possible. This review presents an overview over actual applications and developments of sensor/actuator-based microsystems for medical implants. It concentrates on the technical part of these investigations. It will mainly review work on systems measuring pressure in blood vessels and on systems for ophthalmic applications.

Fast and compact internal scanning CMOS-based hyperspectral camera: the Snapscan

NASA Astrophysics Data System (ADS)

Pichette, Julien; Charle, Wouter; Lambrechts, Andy

2017-02-01

Imec has developed a process for the monolithic integration of optical filters on top of CMOS image sensors, leading to compact, cost-efficient and faster hyperspectral cameras. Linescan cameras are typically used in remote sensing or for conveyor belt applications. Translation of the target is not always possible for large objects or in many medical applications. Therefore, we introduce a novel camera, the Snapscan (patent pending), exploiting internal movement of a linescan sensor enabling fast and convenient acquisition of high-resolution hyperspectral cubes (up to 2048x3652x150 in spectral range 475-925 nm). The Snapscan combines the spectral and spatial resolutions of a linescan system with the convenience of a snapshot camera.

Emerging Applications for High K Materials in VLSI Technology

PubMed Central

Clark, Robert D.

2014-01-01

The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

Front end optimization for the monolithic active pixel sensor of the ALICE Inner Tracking System upgrade

NASA Astrophysics Data System (ADS)

Kim, D.; Aglieri Rinella, G.; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kofarago, M.; Kugathasan, T.; Kwon, Y.; Lattuca, A.; Mager, M.; Sielewicz, K. M.; Marin Tobon, C. A.; Marras, D.; Martinengo, P.; Mazza, G.; Mugnier, H.; Musa, L.; Pham, T. H.; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. W.; Yang, P.

2016-02-01

ALICE plans to replace its Inner Tracking System during the second long shut down of the LHC in 2019 with a new 10 m2 tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the development of the charge sensitive front end and in particular its optimization for uniformity of charge threshold and time response will be presented.

A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel †

PubMed Central

Takahashi, Seiji; Huang, Yi-Min; Sze, Jhy-Jyi; Wu, Tung-Ting; Guo, Fu-Sheng; Hsu, Wei-Cheng; Tseng, Tung-Hsiung; Liao, King; Kuo, Chin-Chia; Chen, Tzu-Hsiang; Chiang, Wei-Chieh; Chuang, Chun-Hao; Chou, Keng-Yu; Chung, Chi-Hsien; Chou, Kuo-Yu; Tseng, Chien-Hsien; Wang, Chuan-Joung; Yaung, Dun-Nien

2017-01-01

A submicron pixel’s light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e−/s at 60 °C, an ultra-low read noise of 0.90 e−·rms, a high full well capacity (FWC) of 4100 e−, and blooming of 0.5% in 0.9 μm pixels with a pixel supply voltage of 2.8 V. In addition, the simulation study result of 0.8 μm pixels is discussed. PMID:29206162

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS.

PubMed

Noack, Marko; Partzsch, Johannes; Mayr, Christian G; Hänzsche, Stefan; Scholze, Stefan; Höppner, Sebastian; Ellguth, Georg; Schüffny, Rene

2015-01-01

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm(2) and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling.

CMOS-compatible spot-size converter for optical fiber to sub-μm silicon waveguide coupling with low-loss low-wavelength dependence and high tolerance to misalignment

NASA Astrophysics Data System (ADS)

Picard, Marie-Josée.; Latrasse, Christine; Larouche, Carl; Painchaud, Yves; Poulin, Michel; Pelletier, François; Guy, Martin

2016-03-01

One of the biggest challenges of silicon photonics is the efficient coupling of light between the sub-micron SiP waveguides and a standard optical fiber (SMF-28). We recently proposed a novel approach based on a spot-size converter (SSC) that fulfills this need. The SSC integrates a tapered silicon waveguide and a superimposed structure made of a plurality of rods of high index material, disposed in an array-like configuration and embedded in a cladding of lower index material. This superimposed structure defines a waveguide designed to provide an efficient adiabatic transfer, through evanescent coupling, to a 220 nm thick Si waveguide tapered down to a narrow tip on one side, while providing a large mode overlap to the optical fiber on the other side. An initial demonstration was made using a SSC fabricated with post-processing steps. Great coupling to a SMF-28 fiber with a loss of 0.6 dB was obtained for TEpolarized light at 1550 nm with minimum wavelength dependence. In this paper, SSCs designed for operation at 1310 and 1550 nm for TE/TM polarizations and entirely fabricated in a CMOS fab are presented.

A Low-Power and In Situ Annealing Technique for the Recovery of Active Devices After Proton Irradiation

NASA Astrophysics Data System (ADS)

Francis, Laurent A.; Sedki, Amor; André, Nicolas; Kilchytska, Valéria; Gérard, Pierre; Ali, Zeeshan; Udrea, Florin; Flandre, Denis

2018-01-01

In this paper, we study the recovery of onmembrane semiconductor components, such as N-type Field-Effect Transistors (FETs) available in two different channel widths and a Complementary Metal-Oxide-Semiconductor (CMOS) inverter, after the exposure to high dose of proton radiation. Due to the ionizing effect, the electrical characteristics of the components established remarkable shifts, where the threshold voltages showed an average shift of -480 mV and -280 mV respectively for 6 μm and 24 μm N-channel transistors, likewise the inversion point of the inverter showed an important shift of -690 mV. The recovery concept is based mainly on a micro-hotplate, fabricated with backside MEMS micromachining structure and a Silicon-On-Insulator (SOI) technology, ensuring rapid, low power and in situ annealing technique, this method proved its reliability in recent works. Annealing the N-channel transistors and the inverter for 16 min with a temperature of the heater up to 385 °C, guaranteed a partial recovery of the semiconductor based components with a maximum power consumption of 66 mW.

Fabrication of silicon films from patterned protruded seeds

NASA Astrophysics Data System (ADS)

Zeng, Huang; Zhang, Wei; Li, Jizhou; Wang, Cong; Yang, Hui; Chen, Yigang; Chen, Xiaoyuan; Liu, Dongfang

2017-05-01

Thin, flexible silicon crystals are starting up applications such as light-weighted flexible solar cells, SOI, flexible IC chips, 3D ICs imagers and 3D CMOS imagers on the demand of high performance with low cost. Kerfless wafering technology by direct conversion of source gases into mono-crystalline wafers on reusable substrates is highly cost-effective and feedstock-effective route to cheap wafers with the thickness down to several microns. Here we show a prototype for direct conversion of silicon source gases to wafers by using the substrate with protruded seeds. A reliable and controllable method of wafer-scaled preparation of protruded seed patterns has been developed by filling liquid wax into a rod array as the mask for the selective removal of oxide layer on the rod head. Selectively epitaxial growth is performed on the protruded seeds, and the voidless film is formed by the merging of neighboring seeds through growing. And structured hollows are formed between the grown film and the substrate, which would offer the transferability of the grown film and the reusability of the protruded seeds.

Decadal variations in the strength of ENSO teleconnections with precipitation in the western United States

USGS Publications Warehouse

McCabe, G.J.; Dettinger, M.D.

1999-01-01

Changing patterns of correlations between the historical average June-November Southern Oscillation Index (SOI) and October-March precipitation totals for 84 climate divisions in the western US indicate a large amount of variability in SOI/precipitation relations on decadal time scales. Correlations of western US precipitation with SOI and other indices of tropical El Nino-Southern Oscillation (ENSO) processes were much weaker from 1920 to 1950 than during recent decades. This variability in teleconnections is associated with the character of tropical air-sea interactions as indexed by the number of out-of-phase SOI/tropical sea surface temperature (SST) episodes, and with decadal variability in the North Pacific Ocean as indexed by the Pacific Decadal Oscillation (PDO). ENSO teleconnections with precipitation in the western US are strong when SOI and NINO3 are out-of-phase and PDO is negative. ENSO teleconnections are weak when SOI and NINO3 are weakly correlated and PDO is positive. Decadal modes of tropical and North Pacific Ocean climate variability are important indicators of periods when ENSO indices, like SOI, can be used as reliable predictors of winter precipitation in the US.

Soft-light overhead illumination systems improve laparoscopic task performance.

PubMed

Takai, Akihiro; Takada, Yasutsugu; Motomura, Hideki; Teramukai, Satoshi

2014-02-01

The aim of this study was to evaluate the impact of attached shadow cues for laparoscopic task performance. We developed a soft-light overhead illumination system (SOIS) that produced attached shadows on objects. We compared results using the SOIS with those using a conventional illumination system with regard to laparoscopic experience and laparoscope-to-target distances (LTDs). Forty-two medical students and 23 surgeons participated in the study. A peg transfer task (LTD, 120 mm) for students and surgeons, and a suture removal task (LTD, 30 mm) for students were performed. Illumination systems were randomly assigned to each task. Endpoints were: total number of peg transfers; percentage of peg-dropping errors; and total execution time for suture removal. After the task, participants filled out a questionnaire on their preference for a particular illumination system. Total number of peg transfers was greater with the SOIS for both students and surgeons. Percentage of peg-dropping errors for surgeons was lower with the SOIS. Total execution time for suture removal was shorter with the SOIS. Forty-five participants (69% in total) evaluated the SOIS for easier task performance. The present results confirm that the SOIS improves laparoscopic task performance, regardless of previous laparoscopic experience or LTD.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yoshizumi, K.; Sasaki, A.; Kohda, M.

We demonstrate gate-controlled switching between persistent spin helix (PSH) state and inverse PSH state, which are detected by quantum interference effect on magneto-conductance. These special symmetric spin states showing weak localization effect give rise to a long spin coherence when the strength of Rashba spin-orbit interaction (SOI) is close to that of Dresselhaus SOI. Furthermore, in the middle of two persistent spin helix states, where the Rashba SOI can be negligible, the bulk Dresselhaus SOI parameter in a modulation doped InGaAs/InAlAs quantum well is determined.

Asymptomatic Hepadnaviral Persistence and Its Consequences in the Woodchuck Model of Occult Hepatitis B Virus Infection

PubMed Central

Mulrooney-Cousins, Patricia M.; Michalak, Tomasz I.

2015-01-01

Woodchuck hepatitis virus (WHV) is molecularly and pathogenically closely related to hepatitis B virus (HBV). Both viruses display tropism towards hepatocytes and cells of the immune system and cause similar liver pathology, where acute hepatitis can progress to chronic hepatitis and to hepatocellular carcinoma (HCC). Two forms of occult hepadnaviral persistence were identified in the woodchuck-WHV model: secondary occult infection (SOI) and primary occult infection (POI). SOI occurs after resolution of a serologically apparent infection with hepatitis or after subclinical serologically evident virus exposure. POI is caused by small amounts of virus and progresses without serological infection markers, but the virus genome and its replication are detectable in the immune system and with time in the liver. SOI can be accompanied by minimal hepatitis, while the hallmark of POI is normal liver morphology. Nonetheless, HCC develops in about 20% of animals with SOI or POI within 3 to 5 years. The virus persists throughout the lifespan in both SOI and POI at serum levels rarely greater than 100 copies/mL, causes hepatitis and HCC when concentrated and administered to virus-naïve woodchucks. SOI is accompanied by virus-specific T and B cell immune responses, while only virus-specific T cells are detected in POI. SOI coincides with protection against reinfection, while POI does not and hepatitis develops after challenge with liver pathogenic doses >1000 virions. Both SOI and POI are associated with virus DNA integration into the liver and the immune system genomes. Overall, SOI and POI are two distinct forms of silent hepadnaviral persistence that share common characteristics. Here, we review findings from the woodchuck model and discuss the relevant observations made in human occult HBV infection (OBI). PMID:26623268

Asymptomatic Hepadnaviral Persistence and Its Consequences in the Woodchuck Model of Occult Hepatitis B Virus Infection.

PubMed

Mulrooney-Cousins, Patricia M; Michalak, Tomasz I

2015-09-28

Woodchuck hepatitis virus (WHV) is molecularly and pathogenically closely related to hepatitis B virus (HBV). Both viruses display tropism towards hepatocytes and cells of the immune system and cause similar liver pathology, where acute hepatitis can progress to chronic hepatitis and to hepatocellular carcinoma (HCC). Two forms of occult hepadnaviral persistence were identified in the woodchuck-WHV model: secondary occult infection (SOI) and primary occult infection (POI). SOI occurs after resolution of a serologically apparent infection with hepatitis or after subclinical serologically evident virus exposure. POI is caused by small amounts of virus and progresses without serological infection markers, but the virus genome and its replication are detectable in the immune system and with time in the liver. SOI can be accompanied by minimal hepatitis, while the hallmark of POI is normal liver morphology. Nonetheless, HCC develops in about 20% of animals with SOI or POI within 3 to 5 years. The virus persists throughout the lifespan in both SOI and POI at serum levels rarely greater than 100 copies/mL, causes hepatitis and HCC when concentrated and administered to virus-naïve woodchucks. SOI is accompanied by virus-specific T and B cell immune responses, while only virus-specific T cells are detected in POI. SOI coincides with protection against reinfection, while POI does not and hepatitis develops after challenge with liver pathogenic doses >1000 virions. Both SOI and POI are associated with virus DNA integration into the liver and the immune system genomes. Overall, SOI and POI are two distinct forms of silent hepadnaviral persistence that share common characteristics. Here, we review findings from the woodchuck model and discuss the relevant observations made in human occult HBV infection (OBI).

Deuterated silicon nitride photonic devices for broadband optical frequency comb generation

NASA Astrophysics Data System (ADS)

Chiles, Jeff; Nader, Nima; Hickstein, Daniel D.; Yu, Su Peng; Briles, Travis Crain; Carlson, David; Jung, Hojoong; Shainline, Jeffrey M.; Diddams, Scott; Papp, Scott B.; Nam, Sae Woo; Mirin, Richard P.

2018-04-01

We report and characterize low-temperature, plasma-deposited deuterated silicon nitride thin films for nonlinear integrated photonics. With a peak processing temperature less than 300$^\\circ$C, it is back-end compatible with pre-processed CMOS substrates. We achieve microresonators with a quality factor of up to $1.6\\times 10^6 $ at 1552 nm, and $>1.2\\times 10^6$ throughout $\\lambda$ = 1510 -- 1600 nm, without annealing or stress management. We then demonstrate the immediate utility of this platform in nonlinear photonics by generating a 1 THz free spectral range, 900-nm-bandwidth modulation-instability microresonator Kerr comb and octave-spanning, supercontinuum-broadened spectra.

Ultra-short silicon MMI duplexer

NASA Astrophysics Data System (ADS)

Yi, Huaxiang; Huang, Yawen; Wang, Xingjun; Zhou, Zhiping

2012-11-01

The fiber-to-the-home (FTTH) systems are growing fast these days, where two different wavelengths are used for upstream and downstream traffic, typically 1310nm and 1490nm. The duplexers are the key elements to separate these wavelengths into different path in central offices (CO) and optical network unit (ONU) in passive optical network (PON). Multimode interference (MMI) has some benefits to be a duplexer including large fabrication tolerance, low-temperature dependence, and low-polarization dependence, but its size is too large to integrate in conventional case. Based on the silicon photonics platform, ultra-short silicon MMI duplexer was demonstrated to separate the 1310nm and 1490nm lights. By studying the theory of self-image phenomena in MMI, the first order images are adopted in order to keep the device short. A cascaded MMI structure was investigated to implement the wavelength splitting, where both the light of 1310nm and 1490nm was input from the same port, and the 1490nm light was coupling cross the first MMI and output at the cross-port in the device while the 1310nm light was coupling through the first and second MMI and output at the bar-port in the device. The experiment was carried on with the SOI wafer of 340nm top silicon. The cascaded MMI was investigated to fold the length of the duplexer as short as 117μm with the extinct ratio over 10dB.

Verification of E-Beam direct write integration into 28nm BEOL SRAM technology

NASA Astrophysics Data System (ADS)

Hohle, Christoph; Choi, Kang-Hoon; Gutsch, Manuela; Hanisch, Norbert; Seidel, Robert; Steidel, Katja; Thrun, Xaver; Werner, Thomas

2015-03-01

Electron beam direct write lithography (EBDW) potentially offers advantages for low-volume semiconductor manufacturing, rapid prototyping or design verification due to its high flexibility without the need of costly masks. However, the integration of this advanced patterning technology into complex CMOS manufacturing processes remains challenging. The low throughput of today's single e-Beam tools limits high volume manufacturing applications and maturity of parallel (multi) beam systems is still insufficient [1,2]. Additional concerns like transistor or material damage of underlying layers during exposure at high electron density or acceleration voltage have to be addressed for advanced technology nodes. In the past we successfully proved that potential degradation effects of high-k materials or ULK shrink can be neglected and were excluded by demonstrating integrated electrical results of 28nm node transistor and BEOL performance following 50kV electron beam dry exposure [3]. Here we will give an update on the integration of EBDW in the 300mm CMOS manufacturing processes of advanced integrated circuits at the 28nm SRAM node of GLOBALFOUNDRIES Dresden. The work is an update to what has been previously published [4]. E-beam patterning results of BEOL full chip metal and via layers with a dual damascene integration scheme using a 50kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMSCNT are demonstrated. For the patterning of the Metal layer a Mix & Match concept based on the sequence litho - etch -litho -etch (LELE) was developed and evaluated wherein several exposure fields were blanked out during the optical exposure. Etch results are shown and compared to the POR. Results are also shown on overlay performance and optimized e-Beam exposure time using most advanced data prep solutions and resist processes. The patterning results have been verified using fully integrated electrical measurement of metal lines and vias on wafer level. In summary we demonstrate the integration capability of EBDW into a productive CMOS process flow at the example of the 28nm SRAM technology node.

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s.

PubMed

Kim, Gyungock; Park, Jeong Woo; Kim, In Gyoo; Kim, Sanghoon; Kim, Sanggi; Lee, Jong Moo; Park, Gun Sik; Joo, Jiho; Jang, Ki-Seok; Oh, Jin Hyuk; Kim, Sun Ae; Kim, Jong Hoon; Lee, Jun Young; Park, Jong Moon; Kim, Do-Won; Jeong, Deog-Kyoon; Hwang, Moon-Sang; Kim, Jeong-Kyoum; Park, Kyu-Sang; Chi, Han-Kyu; Kim, Hyun-Chang; Kim, Dong-Wook; Cho, Mu Hee

2011-12-19

We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

Nanosecond-laser induced crosstalk of CMOS image sensor

NASA Astrophysics Data System (ADS)

Zhu, Rongzhen; Wang, Yanbin; Chen, Qianrong; Zhou, Xuanfeng; Ren, Guangsen; Cui, Longfei; Li, Hua; Hao, Daoliang

2018-02-01

The CMOS Image Sensor (CIS) is photoelectricity image device which focused the photosensitive array, amplifier, A/D transfer, storage, DSP, computer interface circuit on the same silicon substrate[1]. It has low power consumption, high integration,low cost etc. With large scale integrated circuit technology progress, the noise suppression level of CIS is enhanced unceasingly, and its image quality is getting better and better. It has been in the security monitoring, biometrice, detection and imaging and even military reconnaissance and other field is widely used. CIS is easily disturbed and damaged while it is irradiated by laser. It is of great significance to study the effect of laser irradiation on optoelectronic countermeasure and device for the laser strengthening resistance is of great significance. There are some researchers have studied the laser induced disturbed and damaged of CIS. They focused on the saturation, supersaturated effects, and they observed different effects as for unsaturation, saturation, supersaturated, allsaturated and pixel flip etc. This paper research 1064nm laser interference effect in a typical before type CMOS, and observring the saturated crosstalk and half the crosstalk line. This paper extracted from cmos devices working principle and signal detection methods such as the Angle of the formation mechanism of the crosstalk line phenomenon are analyzed.

Fluorescence-suppressed time-resolved Raman spectroscopy of pharmaceuticals using complementary metal-oxide semiconductor (CMOS) single-photon avalanche diode (SPAD) detector.

PubMed

Rojalin, Tatu; Kurki, Lauri; Laaksonen, Timo; Viitala, Tapani; Kostamovaara, Juha; Gordon, Keith C; Galvis, Leonardo; Wachsmann-Hogiu, Sebastian; Strachan, Clare J; Yliperttula, Marjo

2016-01-01

In this work, we utilize a short-wavelength, 532-nm picosecond pulsed laser coupled with a time-gated complementary metal-oxide semiconductor (CMOS) single-photon avalanche diode (SPAD) detector to acquire Raman spectra of several drugs of interest. With this approach, we are able to reveal previously unseen Raman features and suppress the fluorescence background of these drugs. Compared to traditional Raman setups, the present time-resolved technique has two major improvements. First, it is possible to overcome the strong fluorescence background that usually interferes with the much weaker Raman spectra. Second, using the high photon energy excitation light source, we are able to generate a stronger Raman signal compared to traditional instruments. In addition, observations in the time domain can be performed, thus enabling new capabilities in the field of Raman and fluorescence spectroscopy. With this system, we demonstrate for the first time the possibility of recording fluorescence-suppressed Raman spectra of solid, amorphous and crystalline, and non-photoluminescent and photoluminescent drugs such as caffeine, ranitidine hydrochloride, and indomethacin (amorphous and crystalline forms). The raw data acquired by utilizing only the picosecond pulsed laser and a CMOS SPAD detector could be used for identifying the compounds directly without any data processing. Moreover, to validate the accuracy of this time-resolved technique, we present density functional theory (DFT) calculations for a widely used gastric acid inhibitor, ranitidine hydrochloride. The obtained time-resolved Raman peaks were identified based on the calculations and existing literature. Raman spectra using non-time-resolved setups with continuous-wave 785- and 532-nm excitation lasers were used as reference data. Overall, this demonstration of time-resolved Raman and fluorescence measurements with a CMOS SPAD detector shows promise in diverse areas, including fundamental chemical research, the pharmaceutical setting, process analytical technology (PAT), and the life sciences.

Analysis of photonic spot profile converter and bridge structure on SOI platform for horizontal and vertical integration

NASA Astrophysics Data System (ADS)

Majumder, Saikat; Jha, Amit Kr.; Biswas, Aishik; Banerjee, Debasmita; Ganguly, Dipankar; Chakraborty, Rajib

2017-08-01

Horizontal spot size converter required for horizontal light coupling and vertical bridge structure required for vertical integration are designed on high index contrast SOI platform in order to form more compact integrated photonic circuits. Both the structures are based on the concept of multimode interference. The spot size converter can be realized by successive integration of multimode interference structures with reducing dimension on horizontal plane, whereas the optical bridge structure consists of a number of vertical multimode interference structure connected by single mode sections. The spot size converter can be modified to a spot profile converter when the final single mode waveguide is replaced by a slot waveguide. Analysis have shown that by using three multimode sections in a spot size converter, an Gaussian input having spot diameter of 2.51 μm can be converted to a spot diameter of 0.25 μm. If the output single mode section is replaced by a slot waveguide, this input profile can be converted to a flat top profile of width 50 nm. Similarly, vertical displacement of 8μm is possible by using a combination of two multimode sections and three single mode sections in the vertical bridge structure. The analyses of these two structures are carried out for both TE and TM modes at 1550 nm wavelength using the semi analytical matrix method which is simple and fast in computation time and memory. This work shows that the matrix method is equally applicable for analysis of horizontally as well as vertically integrated photonic circuit.

A Scanning scheimpflug lidar system developed for urban pollution monitoring

NASA Astrophysics Data System (ADS)

Yang, Yang; Guan, Peng; Mei, Liang

2018-04-01

A scanning Scheimpflug lidar system based on the Scheimpflug principle has been developed by employing a high power multimode 808 nm laser diode and a highly integrated CMOS sensor in Dalian University of Technology, Dalian, Northern China. Atmospheric scanning measurements in urban area were performed for the studies of particle emission sources.

Monolithic optical link in silicon-on-insulator CMOS technology.

PubMed

Dutta, Satadal; Agarwal, Vishal; Hueting, Raymond J E; Schmitz, Jurriaan; Annema, Anne-Johan

2017-03-06

This work presents a monolithic laterally-coupled wide-spectrum (350 nm < λ < 1270 nm) optical link in a silicon-on-insulator CMOS technology. The link consists of a silicon (Si) light-emitting diode (LED) as the optical source and a Si photodiode (PD) as the detector; both realized by vertical abrupt n⁺p junctions, separated by a shallow trench isolation composed of silicon dioxide. Medium trench isolation around the devices along with the buried oxide layer provides galvanic isolation. Optical coupling in both avalanche-mode and forward-mode operation of the LED are analyzed for various designs and bias conditions. From both DC and pulsed transient measurements, it is further shown that heating in the avalanche-mode LED leads to a slow thermal coupling to the PD with time constants in the ms range. An integrated heat sink in the same technology leads to a ∼ 6 times reduction in the change in PD junction temperature per unit electrical power dissipated in the avalanche-mode LED. The analysis paves way for wide-spectrum optical links integrated in smart power technologies.

A Compact Low-Power Driver Array for VCSELs in 65-nm CMOS Technology

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zeng, Zhiyao; Sun, Kexu; Wang, Guanhua

This article presents a compact low-power 4 x 10 Gb/s quad-driver module for Vertical-Cavity Surface-Emitting Laser (VCSEL) arrays in a 65 nm CMOS technology. The side-by-side drivers can be directly wire bonded to the VCSEL diode array, supporting up to 4 channels. To increase the bandwidth of the driver, an internal feed-forward path is added for pole-zero cancellation, without increasing the power consumption. An edge-configurable pre-emphasis technique is proposed to achieve high bandwidth and minimize the asymmetry of the fall and rise times of the driver output current. Measurement results demonstrate a RMS jitter of 0.68 ps for 10 Gb/smore » operation. Tests demonstrate negligible crosstalk between channels. Under irradiation, the modulation amplitude degrades less than 5% up to 300 Mrad ionizing dose. Finally, the area of the quaddriver array is 500 μm by 1000 μm and the total power consumption for the entire driver array chip is 130 mW for the typical current setting.« less

Design and performance of a custom ASIC digitizer for wire chamber readout in 65 nm CMOS technology

NASA Astrophysics Data System (ADS)

Lee, M. J.; Brown, D. N.; Chang, J. K.; Ding, D.; Gnani, D.; Grace, C. R.; Jones, J. A.; Kolomensky, Y. G.; von der Lippe, H.; Mcvittie, P. J.; Stettler, M. W.; Walder, J.-P.

2015-06-01

We present the design and performance of a prototype ASIC digitizer for integrated wire chamber readout, implemented in 65 nm commercial CMOS technology. Each channel of the 4-channel prototype is composed of two 16-bit Time-to-Digital Converters (TDCs), one 8-bit Analog-to-Digital Converter (ADC), a front-end preamplifier and shaper, plus digital and analog buffers that support a variety of digitization chains. The prototype has a multiplexed digital backend that executes a state machine, distributes control and timing signals, and buffers data for serial output. Laboratory bench tests measure the absolute TDC resolution between 74 ps and 480 ps, growing with the absolute delay, and a relative time resolution of 19 ps. Resolution outliers due to cross-talk between clock signals and supply or reference voltages are seen. After calibration, the ADC displays good linearity and noise performance, with an effective number of bits of 6.9. Under normal operating conditions the circuit consumes 32 mW per channel. Potential design improvements to address the resolution drift and tails are discussed.

An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.

PubMed

Fang, Wai-Chi; Huang, Kuan-Ju; Chou, Chia-Ching; Chang, Jui-Chung; Cauwenberghs, Gert; Jung, Tzyy-Ping

2014-01-01

This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.

A Compact Low-Power Driver Array for VCSELs in 65-nm CMOS Technology

DOE PAGES

Zeng, Zhiyao; Sun, Kexu; Wang, Guanhua; ...

2017-05-08

This article presents a compact low-power 4 x 10 Gb/s quad-driver module for Vertical-Cavity Surface-Emitting Laser (VCSEL) arrays in a 65 nm CMOS technology. The side-by-side drivers can be directly wire bonded to the VCSEL diode array, supporting up to 4 channels. To increase the bandwidth of the driver, an internal feed-forward path is added for pole-zero cancellation, without increasing the power consumption. An edge-configurable pre-emphasis technique is proposed to achieve high bandwidth and minimize the asymmetry of the fall and rise times of the driver output current. Measurement results demonstrate a RMS jitter of 0.68 ps for 10 Gb/smore » operation. Tests demonstrate negligible crosstalk between channels. Under irradiation, the modulation amplitude degrades less than 5% up to 300 Mrad ionizing dose. Finally, the area of the quaddriver array is 500 μm by 1000 μm and the total power consumption for the entire driver array chip is 130 mW for the typical current setting.« less

Feature Extraction and Classification of Magnetic and EMI Data, Camp Beale, CA

DTIC Science & Technology

2012-05-01

and non-specialists. However, as part of ESTCP 1004 we are presently working on transitioning our inversion algorithms to an API that will be...10 0 Time (ms) Cell 663 - Target 1965 - Model 1 (SOI) ISO IVS 0.001 0.005 10 0 Time (ms) Cell 1104 - Target 2532 - Model 1 (SOI) ISO IVS...0.0 1 0.005 10 0 Time (ms) Cell 663 - Target 1965 - Model 1 (SOI) ISO IVS 0.0 1 0.005 10 0 Time (ms) Cell 1104 - Target 2532 - Model 1 (SOI

Reduction of leakage current at the gate edge of SDB SOI NMOS transistor

NASA Astrophysics Data System (ADS)

Kang, Sung-Weon; Lyu, Jong-Son; Kang, Jin-Young; Kang, Sang-Won; Lee, Jin-Hyo

1995-06-01

Leakage current through the parasitic channel formed at the sidewall of the SOI active region has been investigated by measuring the subthreshold I-V characteristics. Partially depleted (PD, approximately 2500 Angstrom) and fully depleted (FD, approximately 800 Angstrom) SOI NMOS transistors of enhancement mode have been fabricated using the silicon direct bonding (SDB) technology. Isolation processes for the SOI devices were LOCOS, LOCOS with channel stop ion implantation or fully recessed trench (FRT). The electron concentration of the parasitic channel is calculated by the PISCES Ilb simulation. As a result, leakage current of the FD mode SOI device with FRT isolation at the front and back gate biases of 0 V was reduced to approximately pA and no hump was seen on the drain current curve.

Southern Ocean Climate and Sea Ice Anomalies Associated with the Southern Oscillation.

NASA Astrophysics Data System (ADS)

Kwok, R.; Comiso, J. C.

2002-03-01

The anomalies in the climate and sea ice cover of the Southern Ocean and their relationships with the Southern Oscillation (SO) are investigated using a 17-yr dataset from 1982 to 1998. The polar climate anomalies are correlated with the Southern Oscillation index (SOI) and the composites of these anomalies are examined under the positive (SOI > 0), neutral (0 > SOI > 1), and negative (SOI < 1) phases of SOI. The climate dataset consists of sea level pressure, wind, surface air temperature, and sea surface temperature fields, while the sea ice dataset describes its extent, concentration, motion, and surface temperature. The analysis depicts, for the first time, the spatial variability in the relationship of the above variables with the SOI. The strongest correlation between the SOI and the polar climate anomalies are found in the Bellingshausen, Amundsen, and Ross Seas. The composite fields reveal anomalies that are organized in distinct large-scale spatial patterns with opposing polarities at the two extremes of SOI, and suggest oscillations that are closely linked to the SO. Within these sectors, positive (negative) phases of the SOI are generally associated with lower (higher) sea level pressure, cooler (warmer) surface air temperature, and cooler (warmer) sea surface temperature in these sectors. Associations between these climate anomalies and the behavior of the Antarctic sea ice cover are evident. Recent anomalies in the sea ice cover that are clearly associated with the SOI include the following: the record decrease in the sea ice extent in the Bellingshausen Sea from mid-1988 to early 1991; the relationship between Ross Sea SST and the ENSO signal, and reduced sea ice concentration in the Ross Sea; and the shortening of the ice season in the eastern Ross Sea, Amundsen Sea, far western Weddell Sea and lengthening of the ice season in the western Ross Sea, Bellinghausen Sea, and central Weddell Sea gyre during the period 1988-94. Four ENSO episodes over the last 17 years contributed to a negative mean in the SOI (0.5). In each of these episodes, significant retreats in ice cover of the Bellingshausen and Amundsen Seas were observed showing a unique association of this region of the Antarctic with the Southern Oscillation.

PN-type carrier-induced filter with modulatable extinction ratio.

PubMed

Fang, Qing; Tu, Xiaoguang; Song, Junfeng; Jia, Lianxi; Luo, Xianshu; Yang, Yan; Yu, Mingbin; Lo, Guoqiang

2014-12-01

We demonstrate the first PN-type carrier-induced silicon waveguide Bragg grating filter on a SOI wafer. The optical extinction ratio of this kind of filter can be efficiently modulated under both reverse and forward biases. The carrier-induced Bragg grating based on a PN junction is fabricated on the silicon waveguide using litho compensation technology. The measured optical bandwidth and the extinction ratio of the filter are 0.45 nm and 19 dB, respectively. The optical extinction ratio modulation under the reverse bias is more than 11.5 dB and it is more than 10 dB under the forward bias. Only 1-dB optical transmission loss is realized in this Bragg grating under a reverse bias. The shifting rates of the central wavelength under forward and reverse biases are ~-1.25 nm/V and 0.01 nm/V, respectively. The 3-dB modulation bandwidth of this filter is 5.1 GHz at a bias of -10 V.

Broadband and fabrication-tolerant on-chip scalable mode-division multiplexing based on mode-evolution counter-tapered couplers.

PubMed

Wang, Jing; Xuan, Yi; Qi, Minghao; Huang, Haiyang; Li, You; Li, Ming; Chen, Xin; Sheng, Zhen; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Gan, Fuwan

2015-05-01

A broadband and fabrication-tolerant on-chip scalable mode-division multiplexing (MDM) scheme based on mode-evolution counter-tapered couplers is designed and experimentally demonstrated on a silicon-on-insulator (SOI) platform. Due to the broadband advantage offered by mode evolution, the two-mode MDM link exhibits a very large, -1  dB bandwidth of >180  nm, which is considerably larger than most of the previously reported MDM links whether they are based on mode-interference or evolution. In addition, the performance metrics remain stable for large-device width deviations from the designed valued by -60  nm to 40 nm, and for temperature variations from -25°C to 75°C. This MDM scheme can be readily extended to higher-order mode multiplexing and a three-mode MDM link is measured with less than -10  dB crosstalk from 1.46 to 1.64 μm wavelength range.

Multiple wavelength silicon photonic 200 mm R+D platform for 25Gb/s and above applications

NASA Astrophysics Data System (ADS)

Szelag, B.; Blampey, B.; Ferrotti, T.; Reboud, V.; Hassan, K.; Malhouitre, S.; Grand, G.; Fowler, D.; Brision, S.; Bria, T.; Rabillé, G.; Brianceau, P.; Hartmann, J. M.; Hugues, V.; Myko, A.; Elleboode, F.; Gays, F.; Fédéli, J. M.; Kopp, C.

2016-05-01

A silicon photonics platform that uses a CMOS foundry line is described. Fabrication process is following a modular integration scheme which leads to a flexible platform, allowing different device combinations. A complete device library is demonstrated for 1310 nm applications with state of the art performances. A PDK which includes specific photonic features and which is compatible with commercial EDA tools has been developed allowing an MPW shuttle service. Finally platform evolutions such as device offer extension to 1550 nm or new process modules introduction are presented.

Modeling and characterization of shielded low loss CPWs on 65 nm node silicon

NASA Astrophysics Data System (ADS)

Hongrui, Wang; Dongxu, Yang; Li, Zhang; Lei, Zhang; Zhiping, Yu

2011-06-01

Coplanar waveguides (CPWs) are promising candidates for high quality passive devices in millimeter-wave frequency bands. In this paper, CPW transmission lines with and without ground shields have been designed and fabricated on 65 nm CMOS technology. A physical-based model is proposed to describe the frequency-dependent per-unit-length L, C, R and G parameters. Starting with a basic CPW structure, the slow-wave effect and ground-shield influence have been analyzed and incorporated into the general model. The accuracy of the model is confirmed by experimental results.

Optimization of CMOS image sensor utilizing variable temporal multisampling partial transfer technique to achieve full-frame high dynamic range with superior low light and stop motion capability

NASA Astrophysics Data System (ADS)

Kabir, Salman; Smith, Craig; Armstrong, Frank; Barnard, Gerrit; Schneider, Alex; Guidash, Michael; Vogelsang, Thomas; Endsley, Jay

2018-03-01

Differential binary pixel technology is a threshold-based timing, readout, and image reconstruction method that utilizes the subframe partial charge transfer technique in a standard four-transistor (4T) pixel CMOS image sensor to achieve a high dynamic range video with stop motion. This technology improves low light signal-to-noise ratio (SNR) by up to 21 dB. The method is verified in silicon using a Taiwan Semiconductor Manufacturing Company's 65 nm 1.1 μm pixel technology 1 megapixel test chip array and is compared with a traditional 4 × oversampling technique using full charge transfer to show low light SNR superiority of the presented technology.

Design of a 0.13-μm CMOS cascade expandable ΣΔ modulator for multi-standard RF telecom systems

NASA Astrophysics Data System (ADS)

Morgado, Alonso; del Río, Rocío; de la Rosa, José M.

2007-05-01

This paper reports a 130-nm CMOS programmable cascade ΣΔ modulator for multi-standard wireless terminals, capable of operating on three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuit- level in order to adapt its performance to the different standards specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.

A photonic crystal waveguide with silicon on insulator in the near-infrared band

NASA Astrophysics Data System (ADS)

Tang, Hai-Xia; Zuo, Yu-Hua; Yu, Jin-Zhong; Wang, Qi-Ming

2007-07-01

A two-dimensional (2D) photonic crystal waveguide in the Γ-K direction with triangular lattice on a silicon-on-insulator (SOI) substrate in the near-infrared band is fabricated by the combination of electron beam lithography and inductively coupled plasma etching. Its transmission characteristics are analysed from the stimulated band diagram by the effective index and the 2D plane wave expansion (PWE) methods. In the experiment, the transmission band edge in a longer wavelength of the photonic crystal waveguide is about 1590 nm, which is in good qualitative agreement with the simulated value. However, there is a disagreement between the experimental and the simulated results when the wavelength ranges from 1607 to 1630 nm, which can be considered as due to the unpolarized source used in the transmission measurement.

Optomechanical and photothermal interactions in suspended photonic crystal membranes.

PubMed

Woolf, David; Hui, Pui-Chuen; Iwase, Eiji; Khan, Mughees; Rodriguez, Alejandro W; Deotare, Parag; Bulu, Irfan; Johnson, Steven G; Capasso, Federico; Loncar, Marko

2013-03-25

We present here an optomechanical system fabricated with novel stress management techniques that allow us to suspend an ultrathin defect-free silicon photonic-crystal membrane above a Silicon-on-Insulator (SOI) substrate with a gap that is tunable to below 200 nm. Our devices are able to generate strong attractive and repulsive optical forces over a large surface area with simple in- and out- coupling and feature the strongest repulsive optomechanical coupling in any geometry to date (gOM/2π ≈65 GHz/nm). The interplay between the optomechanical and photo-thermal-mechanical dynamics is explored, and the latter is used to achieve cooling and amplification of the mechanical mode, demonstrating that our platform is well-suited for potential applications in low-power mass, force, and refractive-index sensing as well as optomechanical accelerometry.

X-ray characterization of Ge dots epitaxially grown on nanostructured Si islands on silicon-on-insulator substrates

PubMed Central

Zaumseil, Peter; Kozlowski, Grzegorz; Yamamoto, Yuji; Schubert, Markus Andreas; Schroeder, Thomas

2013-01-01

On the way to integrate lattice mismatched semiconductors on Si(001), the Ge/Si heterosystem was used as a case study for the concept of compliant substrate effects that offer the vision to be able to integrate defect-free alternative semiconductor structures on Si. Ge nanoclusters were selectively grown by chemical vapour deposition on Si nano-islands on silicon-on-insulator (SOI) substrates. The strain states of Ge clusters and Si islands were measured by grazing-incidence diffraction using a laboratory-based X-ray diffraction technique. A tensile strain of up to 0.5% was detected in the Si islands after direct Ge deposition. Using a thin (∼10 nm) SiGe buffer layer between Si and Ge the tensile strain increases to 1.8%. Transmission electron microscopy studies confirm the absence of a regular grid of misfit dislocations in such structures. This clear experimental evidence for the compliance of Si nano-islands on SOI substrates opens a new integration concept that is not only limited to Ge but also extendable to semiconductors like III–V and II–VI materials. PMID:24046490

Silicide Nanowires for Low-Resistance CMOS Transistor Contacts.

NASA Astrophysics Data System (ADS)

Zollner, Stefan

2007-03-01

Transition metal (TM) silicide nanowires are used as contacts for modern CMOS transistors. (Our smallest wires are ˜20 nm thick and ˜50 nm wide.) While much research on thick TM silicides was conducted long ago, materials perform differently at the nanoscale. For example, the usual phase transformation sequences (e.g., Ni, Ni2Si, NiSi, NiSi2) for the reaction of thick metal films on Si no longer apply to nanostructures, because the surface and interface energies compete with the bulk energy of a given crystal structure. Therefore, a NiSi film will agglomerate into hemispherical droplets of NiSi by annealing before it reaches the lowest-energy (NiSi2) crystalline structure. These dynamics can be tuned by addition of impurities (such as Pt in Ni). The Si surface preparation is also a more important factor for nanowires than for silicidation of thick TM films. Ni nanowires formed on Si surfaces that were cleaned and amorphized by sputtering with Ar ions have a tendency to form NiSi2 pyramids (``spikes'') even at moderate temperatures (˜400^oC), while similar Ni films formed on atomically clean or hydrogen-terminated Si form uniform NiSi nanowires. Another issue affecting TM silicides is the barrier height between the silicide contact and the silicon transistor. For most TM silicides, the Fermi level of the silicide is aligned with the center of the Si band gap. Therefore, silicide contacts experience Schottky barrier heights of around 0.5 eV for both n-type and p-type Si. The resulting contact resistance becomes a significant term for the overall resistance of modern CMOS transistors. Lowering this contact resistance is an important goal in CMOS research. New materials are under investigation (for example PtSi, which has a barrier height of only 0.3 eV to p-type Si). This talk will describe recent results, with special emphasis on characterization techniques and electrical testing useful for the development of silicide nanowires for CMOS contacts. In collaboration with: P. Grudowski, D. Jawarani, R. Garcia, M.L. Kottke, R.B. Gregory, X.-D. Wang, D. Theodore, P. Fejes, W.J. Taylor, B.Y. Nguyen, C. Capasso, M. Raymond, D. Denning, K. Chang, R. Noble, M. Jahanbani, S. Bolton, P. Crabtree, D. Goedeke, M. Rossow, M. Chowdhury, H. Desjardins, A.Thean.

Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

NASA Astrophysics Data System (ADS)

Pavanello, Marcelo Antonio; de Souza, Michelly; Ribeiro, Thales Augusto; Martino, João Antonio; Flandre, Denis

2016-11-01

This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped transistors. Devices from two different technologies have been measured and show that the mobility increase rate with temperature for GC SOI transistors is similar to uniformly doped devices for temperatures down to 90 K. However, at liquid helium temperature the rate of mobility increase is larger in GC SOI than in standard devices because of the different mobility scattering mechanisms. The analog properties of GC SOI devices have been investigated down to 4.16 K and show that because of its better transconductance and output conductance, an intrinsic voltage gain improvement with temperature is also obtained for devices in the whole studied temperature range. GC devices are also capable of reducing the impact ionization due to the high electric field in the drain region, increasing the drain breakdown voltage of fully-depleted SOI MOSFETs at any studied temperature and the kink voltage at 4.16 K.

Waveguide-integrated vertical pin photodiodes of Ge fabricated on p+ and n+ Si-on-insulator layers

NASA Astrophysics Data System (ADS)

Ito, Kazuki; Hiraki, Tatsurou; Tsuchizawa, Tai; Ishikawa, Yasuhiko

2017-04-01

Vertical pin structures of Ge photodiodes (PDs) integrated with Si optical waveguides are fabricated by depositing Ge epitaxial layers on Si-on-insulator (SOI) layers, and the performances of n+-Ge/i-Ge/p+-SOI PDs are compared with those of p+-Ge/i-Ge/n+-SOI PDs. Both types of PDs show responsivities as high as 1.0 A/W at 1.55 µm, while the dark leakage current is different, which is consistent with previous reports on free-space PDs formed on bulk Si wafers. The dark current of the p+-Ge/i-Ge/n+-SOI PDs is higher by more than one order of magnitude. Taking into account the activation energies for dark current as well as the dependence on PD area, the dark current of the n+-Ge/i-Ge/p+-SOI PDs is dominated by the thermal generation of carriers via mid-gap defect levels in Ge, while for the p+-Ge/i-Ge/n+-SOI PDs, the dark current is ascribed to not only thermal generation but also other mechanisms such as locally formed conduction paths.

A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier

NASA Astrophysics Data System (ADS)

Wu, L.; San Segundo Bello, D.; Coppejans, P.; Craninckx, J.; Wambacq, P.; Borremans, J.

2017-02-01

This paper presents a 20 Mfps 32 × 84 pixels CMOS burst-mode imager featuring high frame depth with a passive in-pixel amplifier. Compared to the CCD alternatives, CMOS burst-mode imagers are attractive for their low power consumption and integration of circuitry such as ADCs. Due to storage capacitor size and its noise limitations, CMOS burst-mode imagers usually suffer from a lower frame depth than CCD implementations. In order to capture fast transitions over a longer time span, an in-pixel CDS technique has been adopted to reduce the required memory cells for each frame by half. Moreover, integrated with in-pixel CDS, an in-pixel NMOS-only passive amplifier alleviates the kTC noise requirements of the memory bank allowing the usage of smaller capacitors. Specifically, a dense 108-cell MOS memory bank (10fF/cell) has been implemented inside a 30μm pitch pixel, with an area of 25 × 30μm2 occupied by the memory bank. There is an improvement of about 4x in terms of frame depth per pixel area by applying in-pixel CDS and amplification. With the amplifier's gain of 3.3, an FD input-referred RMS noise of 1mV is achieved at 20 Mfps operation. While the amplification is done without burning DC current, including the pixel source follower biasing, the full pixel consumes 10μA at 3.3V supply voltage at full speed. The chip has been fabricated in imec's 130nm CMOS CIS technology.

Commercial silicon-on-insulator (SOI) wafers as a versatile substrate for laser desorption/ionization mass spectrometry.

PubMed

Kim, Shin Hye; Kim, Jeongkwon; Moon, Dae Won; Han, Sang Yun

2013-01-01

We report here that a commercial silicon-on-insulator (SOI) wafer offers an opportunity for laser desorption/ionization (LDI) of peptide molecules, which occurs directly from its flat surface without requiring special surface preparation. The LDI-on-SOI exhibits intact ionization of peptides with a good detection limit of lower than 20 fmol, of which the mass range is demonstrated up to insulin with citric acid additives. The LDI process most likely arises from laser-induced surface heating promoted by two-dimensional thermal confinement in the thin Si surface layer of the SOI wafer. As a consequence of the thermal process, the LDI-on-SOI method is also capable of creating post-source decay (PSD) of the resulting peptide LDI ions, which is suitable for peptide sequencing using conventional TOF/TOF mass spectrometry.

CCSDS SOIS Subnetwork Services: A First Reference Implementation

NASA Astrophysics Data System (ADS)

Gunes-Lasnet, S.; Notebaert, O.; Farges, P.-Y.; Fowell, S.

2008-08-01

The CCSDS SOIS working groups are developing a range of standards for spacecraft onboard interfaces with the intention of promoting reuse of hardware and software designs across a range of missions while enabling interoperability of onboard systems from diverse sources. The CCSDS SOIS working groups released in June 2007 their red books for both Subnetwork and application support layers. In order to allow the verification of these recommended standards and to pave the way for future implementation onboard spacecrafts, it is essential for these standards to be prototyped on a representative spacecraft platform, to provide valuable feed back to the SOIS working group. A first reference implementation of both Subnetwork and Application Support SOIS services over SpaceWire and Mil-Std-1553 bus is thus being realised by SciSys Ltd and Astrium under an ESA contract.

A novel self-aligned oxygen (SALOX) implanted SOI MOSFET device structure

NASA Astrophysics Data System (ADS)

Tzeng, J. C.; Baerg, W.; Ting, C.; Siu, B.

The morphology of the novel self-aligned oxygen implanted SOI (SALOX SOI) [1] MOSFET was studied. The channel silicon of SALOX SOI was confirmed to be undamaged single crystal silicon and was connected with the substrate. Buried oxide formed by oxygen implantation in this SALOX SOI structure was shown by a cross section transmission electron micrograph (X-TEM) to be amorphous. The source/drain silicon on top of the buried oxide was single crystal, as shown by the transmission electron diffraction (TED) pattern. The source/drain regions were elevated due to the buried oxide volume expansion. A sharp silicon—silicon dioxide interface between the source/drain silicon and buried oxide was observed by Auger electron spectroscopy (AES). Well behaved n-MOS transistor current voltage characteristics were obtained and showed no I-V kink.

High-contrast grating hollow-core waveguide splitter applied to optical phased array

NASA Astrophysics Data System (ADS)

Zhao, Che; Xue, Ping; Zhang, Hanxing; Chen, Te; Peng, Chao; Hu, Weiwei

2014-11-01

A novel hollow-core (HW) Y-branch waveguide splitter based on high-contrast grating (HCG) is presented. We calculated and designed the HCG-HW splitter using Rigorous Coupled Wave Analysis (RCWA). Finite-different timedomain (FDTD) simulation shows that the splitter has a broad bandwidth and the branching loss is as low as 0.23 dB. Fabrication is accomplished with standard Silicon-On-Insulator (SOI) process. The experimental measurement results indicate its good performance on beam splitting near the central wavelength λ = 1550 nm with a total insertion loss of 7.0 dB.

Low-loss slot waveguides with silicon (111) surfaces realized using anisotropic wet etching

NASA Astrophysics Data System (ADS)

Debnath, Kapil; Khokhar, Ali; Boden, Stuart; Arimoto, Hideo; Oo, Swe; Chong, Harold; Reed, Graham; Saito, Shinichi

2016-11-01

We demonstrate low-loss slot waveguides on silicon-on-insulator (SOI) platform. Waveguides oriented along the (11-2) direction on the Si (110) plane were first fabricated by a standard e-beam lithography and dry etching process. A TMAH based anisotropic wet etching technique was then used to remove any residual side wall roughness. Using this fabrication technique propagation loss as low as 3.7dB/cm was realized in silicon slot waveguide for wavelengths near 1550nm. We also realized low propagation loss of 1dB/cm for silicon strip waveguides.

A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters

NASA Astrophysics Data System (ADS)

Cristoloveanu, S.; Lee, K. H.; Parihar, M. S.; El Dirani, H.; Lacord, J.; Martinie, S.; Le Royer, C.; Barbe, J.-Ch.; Mescot, X.; Fonteneau, P.; Galy, Ph.; Gamiz, F.; Navarro, C.; Cheng, B.; Duan, M.; Adamu-Lema, F.; Asenov, A.; Taur, Y.; Xu, Y.; Kim, Y.-T.; Wan, J.; Bawedin, M.

2018-05-01

The band-modulation and sharp-switching mechanisms in Z2-FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments and simulations. This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10 nm thick SOI films. It offers low leakage current, high current margin, long retention, low operating voltage especially for programming, and high speed. The Z2-FET is suitable for embedded memory applications.

Single-event upset in highly scaled commercial silicon-on-insulator PowerPc microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad H.

2004-01-01

Single event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes, and core voltages. The results are compared with results for similar devices with build substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The scaling of the cross section with reduction of feature size and core voltage dependence for SOI microprocessors discussed.

Electronics for Extreme Environments

NASA Astrophysics Data System (ADS)

Patel, J. U.; Cressler, J.; Li, Y.; Niu, G.

2001-01-01

Most of the NASA missions involve extreme environments comprising radiation and low or high temperatures. Current practice of providing friendly ambient operating environment to electronics costs considerable power and mass (for shielding). Immediate missions such as the Europa orbiter and lander and Mars landers require the electronics to perform reliably in extreme conditions during the most critical part of the mission. Some other missions planned in the future also involve substantial surface activity in terms of measurements, sample collection, penetration through ice and crust and the analysis of samples. Thus it is extremely critical to develop electronics that could reliably operate under extreme space environments. Silicon On Insulator (SOI) technology is an extremely attractive candidate for NASA's future low power and high speed electronic systems because it offers increased transconductance, decreased sub-threshold slope, reduced short channel effects, elimination of kink effect, enhanced low field mobility, and immunity from radiation induced latch-up. A common belief that semiconductor devices function better at low temperatures is generally true for bulk devices but it does not hold true for deep sub-micron SOI CMOS devices with microscopic device features of 0.25 micrometers and smaller. Various temperature sensitive device parameters and device characteristics have recently been reported in the literature. Behavior of state of the art technology devices under such conditions needs to be evaluated in order to determine possible modifications in the device design for better performance and survivability under extreme environments. Here, we present a unique approach of developing electronics for extreme environments to benefit future NASA missions as described above. This will also benefit other long transit/life time missions such as the solar sail and planetary outposts in which electronics is out open in the unshielded space at the ambient space temperatures and always exposed to radiation. Additional information is contained in the original extended abstract.

The PixFEL project: Progress towards a fine pitch X-ray imaging camera for next generation FEL facilities

NASA Astrophysics Data System (ADS)

Rizzo, G.; Batignani, G.; Benkechkache, M. A.; Bettarini, S.; Casarosa, G.; Comotti, D.; Dalla Betta, G.-F.; Fabris, L.; Forti, F.; Grassi, M.; Lodola, L.; Malcovati, P.; Manghisoni, M.; Mendicino, R.; Morsani, F.; Paladino, A.; Pancheri, L.; Paoloni, E.; Ratti, L.; Re, V.; Traversi, G.; Vacchi, C.; Verzellesi, G.; Xu, H.

2016-07-01

The INFN PixFEL project is developing the fundamental building blocks for a large area X-ray imaging camera to be deployed at next generation free electron laser (FEL) facilities with unprecedented intensity. Improvement in performance beyond the state of art in imaging instrumentation will be explored adopting advanced technologies like active edge sensors, a 65 nm node CMOS process and vertical integration. These are the key ingredients of the PixFEL project to realize a seamless large area focal plane instrument composed by a matrix of multilayer four-side buttable tiles. In order to minimize the dead area and reduce ambiguities in image reconstruction, a fine pitch active edge thick sensor is being optimized to cope with very high intensity photon flux, up to 104 photons per pixel, in the range from 1 to 10 keV. A low noise analog front-end channel with this wide dynamic range and a novel dynamic compression feature, together with a low power 10 bit analog to digital conversion up to 5 MHz, has been realized in a 110 μm pitch with a 65 nm CMOS process. Vertical interconnection of two CMOS tiers will be also explored in the future to build a four-side buttable readout chip with high density memories. In the long run the objective of the PixFEL project is to build a flexible X-ray imaging camera for operation both in burst mode, like at the European X-FEL, or in continuous mode with the high frame rates anticipated for future FEL facilities.

Gun muzzle flash detection using a single photon avalanche diode array in 0.18µm CMOS technology

NASA Astrophysics Data System (ADS)

Savuskan, Vitali; Jakobson, Claudio; Merhav, Tomer; Shoham, Avi; Brouk, Igor; Nemirovsky, Yael

2015-05-01

In this study, a CMOS Single Photon Avalanche Diode (SPAD) 2D array is used to record and sample muzzle flash events in the visible spectrum, from representative weapons. SPADs detect the emission peaks of alkali salts, potassium or sodium, with spectral emission lines around 769nm and 589nm, respectively. The alkali salts are included in the gunpowder to suppress secondary flashes ignited during the muzzle flash event. The SPADs possess two crucial properties for muzzle flash imaging: (i) very high photon detection sensitivity, (ii) a unique ability to convert the optical signal to a digital signal at the source pixel, thus practically eliminating readout noise. The sole noise sources are the ones prior to the readout circuitry (optical signal distribution, avalanche initiation distribution and nonphotonic generation). This enables high sampling frequencies in the kilohertz range without significant SNR degradation, in contrast to regular CMOS image sensors. This research will demonstrate the SPAD's ability to accurately sample and reconstruct the temporal behavior of the muzzle flash in the visible wavelength, in the presence of sunlight. The reconstructed signal is clearly distinguishable from background clutter, through exploitation of flash temporal characteristics and signal processing, which will be reported. The frame rate of ~16 KHz was chosen as an optimum between SNR degradation and temporal profile recognition accuracy. In contrast to a single SPAD, the 2D array allows for multiple events to be processed simultaneously. Moreover, a significant field of view is covered, enabling comprehensive surveillance and imaging.

Monolithic pixel development in TowerJazz 180 nm CMOS for the outer pixel layers in the ATLAS experiment

NASA Astrophysics Data System (ADS)

Berdalovic, I.; Bates, R.; Buttar, C.; Cardella, R.; Egidos Plaja, N.; Hemperek, T.; Hiti, B.; van Hoorne, J. W.; Kugathasan, T.; Mandic, I.; Maneuski, D.; Marin Tobon, C. A.; Moustakas, K.; Musa, L.; Pernegger, H.; Riedler, P.; Riegel, C.; Schaefer, D.; Schioppa, E. J.; Sharma, A.; Snoeys, W.; Solans Sanchez, C.; Wang, T.; Wermes, N.

2018-01-01

The upgrade of the ATLAS tracking detector (ITk) for the High-Luminosity Large Hadron Collider at CERN requires the development of novel radiation hard silicon sensor technologies. Latest developments in CMOS sensor processing offer the possibility of combining high-resistivity substrates with on-chip high-voltage biasing to achieve a large depleted active sensor volume. We have characterised depleted monolithic active pixel sensors (DMAPS), which were produced in a novel modified imaging process implemented in the TowerJazz 180 nm CMOS process in the framework of the monolithic sensor development for the ALICE experiment. Sensors fabricated in this modified process feature full depletion of the sensitive layer, a sensor capacitance of only a few fF and radiation tolerance up to 1015 neq/cm2. This paper summarises the measurements of charge collection properties in beam tests and in the laboratory using radioactive sources and edge TCT. The results of these measurements show significantly improved radiation hardness obtained for sensors manufactured using the modified process. This has opened the way to the design of two large scale demonstrators for the ATLAS ITk. To achieve a design compatible with the requirements of the outer pixel layers of the tracker, a charge sensitive front-end taking 500 nA from a 1.8 V supply is combined with a fast digital readout architecture. The low-power front-end with a 25 ns time resolution exploits the low sensor capacitance to reduce noise and analogue power, while the implemented readout architectures minimise power by reducing the digital activity.

Sociosexuality from Argentina to Zimbabwe: a 48-nation study of sex, culture, and strategies of human mating.

PubMed

Schmitt, David P

2005-04-01

The Sociosexual Orientation Inventory (SOI; Simpson & Gangestad 1991) is a self-report measure of individual differences in human mating strategies. Low SOI scores signify that a person is sociosexually restricted, or follows a more monogamous mating strategy. High SOI scores indicate that an individual is unrestricted, or has a more promiscuous mating strategy. As part of the International Sexuality Description Project (ISDP), the SOI was translated from English into 25 additional languages and administered to a total sample of 14,059 people across 48 nations. Responses to the SOI were used to address four main issues. First, the psychometric properties of the SOI were examined in cross-cultural perspective. The SOI possessed adequate reliability and validity both within and across a diverse range of modem cultures. Second, theories concerning the systematic distribution of sociosexuality across cultures were evaluated. Both operational sex ratios and reproductively demanding environments related in evolutionary-predicted ways to national levels of sociosexuality. Third, sex differences in sociosexuality were generally large and demonstrated cross-cultural universality across the 48 nations of the ISDP, confirming several evolutionary theories of human mating. Fourth, sex differences in sociosexuality were significantly larger when reproductive environments were demanding but were reduced to more moderate levels in cultures with more political and economic gender equality. Implications for evolutionary and social role theories of human sexuality are discussed.

Pure gauge spin-orbit couplings

NASA Astrophysics Data System (ADS)

Shikakhwa, M. S.

2017-01-01

Planar systems with a general linear spin-orbit interaction (SOI) that can be cast in the form of a non-Abelian pure gauge field are investigated using the language of non-Abelian gauge field theory. A special class of these fields that, though a 2×2 matrix, are Abelian are seen to emerge and their general form is given. It is shown that the unitary transformation that gauges away these fields induces at the same time a rotation on the wave function about a fixed axis but with a space-dependent angle, both of which being characteristics of the SOI involved. The experimentally important case of equal-strength Rashba and Dresselhaus SOI (R+D SOI) is shown to fall within this special class of Abelian gauge fields, and the phenomenon of persistent spin helix (PSH) that emerges in the presence of this latter SOI in a plane is shown to fit naturally within the general formalism developed. The general formalism is also extended to the case of a particle confined to a ring. It is shown that the Hamiltonian on a ring in the presence of equal-strength R+D SOI is unitarily equivalent to that of a particle subject to only a spin-independent but θ-dependent potential with the unitary transformation relating the two being again the space-dependent rotation operator characteristic of R+D SOI.

Toward Three Dimensional Circuits Formed by Molten-Alloy Driven Self-Assembly

DTIC Science & Technology

2008-12-01

layers. Next, we deposited a lead-free, eutectic Bi-Sn alloy with a 138°C melting point shown in Fig. 2D). First, we evaporated 100nm of Au to...IEEE, 427-429. Chan, V. W. C., P. C. H. Chan, and M. Chan, 2001: Multiple layers of CMOS integrated circuits using recrystallized silicon film

Detailed study of NBTI characterization in 40-nm CMOS process using comprehensive models

NASA Astrophysics Data System (ADS)

Zeng, Yan; Li, Xiao-Jin; Qing, Jian; Sun, Ya-Bin; Shi, Yan-Ling; Guo, Ao; Hu, Shao-Jian

2017-09-01

Not Available Project supported by the National Natural Science Foundation of China (Grant Nos. 61574056 and 61204038), the Natural Science Funds of Shanghai, China (Grant No. 14ZR1412000), the Fund from the Science and Technology Commission of Shanghai Municipality (Grant No. 14DZ2260800), and Shanghai Sailing Program (Grant No. 17YF1404700).

Nanoelectronics and More-than-Moore at IMEC

NASA Astrophysics Data System (ADS)

Cartuyvels, Rudi; Biesemans, Serge; Vandervorst, Wilfried; De Boeck, Jo

2011-11-01

This paper presents an overview of imec's R&D addressing the challenges of CMOS scaling towards the 10 nm node and its outlook beyond. In addition to the relentless geometrical shrinks, opportunities to further increase nanoelectronic system functionality and performance by co-integration and chip stacking technologies combined with emerging MEMS and optoelectronic technologies will be presented.

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS

PubMed Central

Noack, Marko; Partzsch, Johannes; Mayr, Christian G.; Hänzsche, Stefan; Scholze, Stefan; Höppner, Sebastian; Ellguth, Georg; Schüffny, Rene

2015-01-01

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm2 and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling. PMID:25698914

Post place and route design-technology co-optimization for scaling at single-digit nodes with constant ground rules

NASA Astrophysics Data System (ADS)

Mattii, Luca; Milojevic, Dragomir; Debacker, Peter; Berekovic, Mladen; Sherazi, Syed Muhammad Yasser; Chava, Bharani; Bardon, Marie Garcia; Schuddinck, Pieter; Rodopoulos, Dimitrios; Baert, Rogier; Gerousis, Vassilios; Ryckaert, Julien; Raghavan, Praveen

2018-01-01

Standard-cell design, technology choices, and place and route (P&R) efficiency are deeply interrelated in CMOS technology nodes below 10 nm, where lower number of tracks cells and higher pin densities pose increasingly challenging problems to the router in terms of congestion and pin accessibility. To evaluate and downselect the best solutions, a holistic design-technology co-optimization approach leveraging state-of-the-art P&R tools is thus necessary. We adopt such an approach using the imec N7 technology platform, with contacted poly pitch of 42 nm and tightest metal pitch of 32 nm, by comparing post P&R area of an IP block for different standard cell configurations, technology options, and cell height. Keeping the technology node and the set of ground rules unchanged, we demonstrate that a careful combination of these solutions can enable area gains of up to 50%, comparable with the area benefits of migrating to another node. We further demonstrate that these area benefits can be achieved at isoperformance with >20% reduced power. As at the end of the CMOS roadmap, conventional scaling enacted through pitch reduction is made more and more challenging by constraints imposed by lithography limits, material resistivity, manufacturability, and ultimately wafer cost, the approach shown herein offers a valid, attractive, and low-cost alternative.

Fully industrialised single photon avalanche diodes

NASA Astrophysics Data System (ADS)

Pellegrini, S.; Rae, B.

2017-05-01

Single Photon Avalanche diodes (SPADs) were first realized more than five decades ago[1][1], and have now been industrialized for mass production in the 130 nm CMOS technology node by STMicroelectronics (STM). In this paper we present the latest STM SPAD with an excellent NIR photon detection probability (>5% at 850nm), a dark count rate median of 100 cps at room temperature and a low breakdown voltage of 14.2V. The dead time of the SPAD is approximately 25 ns, leading to a maximum count rate of 40 Mcps. Thanks to the 130 nm gate length of the CMOS technology used and the associated high digital gate density, complex digital signal processing can be implemented allowing fully integrated systems to be realized. The low bias required by the SPAD makes it possible for voltage generation to be achieved on-chip (e.g. charge pumped). We introduce our first generation time-of-flight system (VL6180) based on the STM SPAD technology, which is capable of ranging up to 60 cm in 60 ms. Ranging capabilities and accuracy are measured using a set of moving targets with reflectance of 5%, 17% and 88% in a fully automated test bed. To the best of our knowledge this was the first high volume SPAD-based device. To our knowledge this is the first time details of SPAD performance over production volumes and lifetime have been presented.

Detecting single-abasic residues within a DNA strand immobilized in a biological nanopore using an integrated CMOS sensor.

PubMed

Kim, Jungsuk; Maitra, Raj D; Pedrotti, Ken; Dunbar, William B

2013-02-01

In this paper, we demonstrate the application of a novel current-measuring sensor (CMS) customized for nanopore applications. The low-noise CMS is fabricated in a 0.35μm CMOS process and is implemented in experiments involving DNA captured in an α-hemolysin (α-HL) nanopore. Specifically, the CMS is used to build a current amplitude map as a function of varying positions of a single-abasic residue within a homopolymer cytosine single-stranded DNA (ssDNA) that is captured and held in the pore. Each ssDNA is immobilized using a biotin-streptavidin linkage. Five different DNA templates are measured and compared: one all-cytosine ssDNA, and four with a single-abasic residue substitution that resides in or near the ~1.5nm aperture of the α-HL channel when the strand is immobilized. The CMOS CMS is shown to resolves the ~5Å displacements of the abasic residue within the varying templates. The demonstration represents an advance in application-specific circuitry that is optimized for small-footprint nanopore applications, including genomic sequencing.

1024-Pixel CMOS Multimodality Joint Cellular Sensor/Stimulator Array for Real-Time Holistic Cellular Characterization and Cell-Based Drug Screening.

PubMed

Park, Jong Seok; Aziz, Moez Karim; Li, Sensen; Chi, Taiyun; Grijalva, Sandra Ivonne; Sung, Jung Hoon; Cho, Hee Cheol; Wang, Hua

2018-02-01

This paper presents a fully integrated CMOS multimodality joint sensor/stimulator array with 1024 pixels for real-time holistic cellular characterization and drug screening. The proposed system consists of four pixel groups and four parallel signal-conditioning blocks. Every pixel group contains 16 × 16 pixels, and each pixel includes one gold-plated electrode, four photodiodes, and in-pixel circuits, within a pixel footprint. Each pixel supports real-time extracellular potential recording, optical detection, charge-balanced biphasic current stimulation, and cellular impedance measurement for the same cellular sample. The proposed system is fabricated in a standard 130-nm CMOS process. Rat cardiomyocytes are successfully cultured on-chip. Measured high-resolution optical opacity images, extracellular potential recordings, biphasic current stimulations, and cellular impedance images demonstrate the unique advantages of the system for holistic cell characterization and drug screening. Furthermore, this paper demonstrates the use of optical detection on the on-chip cultured cardiomyocytes to real-time track their cyclic beating pattern and beating rate.

Pushing the limits of CMOS optical parametric amplifiers with USRN:Si7N3 above the two-photon absorption edge

PubMed Central

Ooi, K. J. A.; Ng, D. K. T.; Wang, T.; Chee, A. K. L.; Ng, S. K.; Wang, Q.; Ang, L. K.; Agarwal, A. M.; Kimerling, L. C.; Tan, D. T. H.

2017-01-01

CMOS platforms operating at the telecommunications wavelength either reside within the highly dissipative two-photon regime in silicon-based optical devices, or possess small nonlinearities. Bandgap engineering of non-stoichiometric silicon nitride using state-of-the-art fabrication techniques has led to our development of USRN (ultra-silicon-rich nitride) in the form of Si7N3, that possesses a high Kerr nonlinearity (2.8 × 10−13 cm2 W−1), an order of magnitude larger than that in stoichiometric silicon nitride. Here we experimentally demonstrate high-gain optical parametric amplification using USRN, which is compositionally tailored such that the 1,550 nm wavelength resides above the two-photon absorption edge, while still possessing large nonlinearities. Optical parametric gain of 42.5 dB, as well as cascaded four-wave mixing with gain down to the third idler is observed and attributed to the high photon efficiency achieved through operating above the two-photon absorption edge, representing one of the largest optical parametric gains to date on a CMOS platform. PMID:28051064

Characterization of a CMOS sensing core for ultra-miniature wireless implantable temperature sensors with application to cryomedicine.

PubMed

Khairi, Ahmad; Thaokar, Chandrajit; Fedder, Gary; Paramesh, Jeyanandh; Rabin, Yoed

2014-09-01

In effort to improve thermal control in minimally invasive cryosurgery, the concept of a miniature, wireless, implantable sensing unit has been developed recently. The sensing unit integrates a wireless power delivery mechanism, wireless communication means, and a sensing core-the subject matter of the current study. The current study presents a CMOS ultra-miniature PTAT temperature sensing core and focuses on design principles, fabrication of a proof-of-concept, and characterization in a cryogenic environment. For this purpose, a 100 μm × 400 μm sensing core prototype has been fabricated using a 130 nm CMOS process. The senor has shown to operate between -180°C and room temperature, to consume power of less than 1 μW, and to have an uncertainty range of 1.4°C and non-linearity of 1.1%. Results of this study suggest that the sensing core is ready to be integrated in the sensing unit, where system integration is the subject matter of a parallel effort. Copyright © 2014 IPEM. Published by Elsevier Ltd. All rights reserved.

Science Goal and Mission Status of JEM-GLIMS

NASA Astrophysics Data System (ADS)

Sato, M.; Ushio, T.; Morimoto, T.; Suzuki, M.; Yamazaki, A.; Masayuki, K.; Ishida, R.; Takahashi, Y.; Inan, U. S.; Hobara, Y.; Sakamoto, Y.; Yoshida, K.; Ishikawa, H.; Yoshita, K.

2009-12-01

In order to study the generation mechanism of TLEs, global occurrence rates and distributions of lightning and TLEs, and the relationship between lightning, TLEs and TGFs, we will carry out the lightning and TLE observation at Exposed Facility of Japanese Experiment Module (JEM-EF) of International Space Station (ISS). In this mission named JEM-GLIMS (Global Lightning and sprIte MeasurementS on JEM-EF) two kinds of optical instruments and two sets of radio receivers will be integrated into the Multi mission Consolidated Equipment (MCE) which is the bus system and will be installed at JEM-EF finally. The optical instruments consist of two wide FOV CMOS cameras and six wide FOV photometers, and all these optical instruments look the nadir direction. CMOS cameras named LSI (Lightning and Sprite Imager) use the STAR-250 device as a detector, which has 512x512 pixels and 25x25 um pixel size, and have 40 deg. FOV. One CMOS camera with a wide band filter (730-830 nm) mainly measures lightning emission, while another camera with a narrowband filter (766+/-6 nm) mainly measures TLE emission. Five of six photometers named as PH have 40 deg FOV and use photomultiplier tube (PMT) as a photon detector. They equip band-pass filters (150-280 nm, 316+/-5 nm, 337+/-5 nm, 392+/-5 nm, and 762+/-5 nm) for the absolute intensity measurement of the TLE emission. One of six photometers equips a wide-band filter (600-900 nm) to detect lightning occurring within 87 deg FOV. These output signals will be recorded with the sampling frequency of 20 kHz with a 12-bit resolution. One VLF receiver will observe electric field perturbations in the frequency range of 1-40 kHz. One monopole antenna with a 15 cm length will be installed along the nadir direction. Outputs signal from the VLF antenna will be digitally sampled at the VLF electronics by 16-bit resolution with a sampling frequency. There are two sets of VHF antenna, which will be installed at the bottom plate of MCE. VLF antenna will detect VHF pulses in the frequency range of 70-100 MHz and will be recorded by the VHF electronics with 8-bit resolution with 200 MHz sampling frequency. A science instrument handling unit named as SHU is also installed. The function of SHU is to control all the science instruments, to carry out the data acquisition with a trigger function, and to establish the command and telemetry interfaces. JEM-GIMS will be launched at the beginning of 2012. We have passed the preliminary design review (PDR) on July and have started the development of the pre-flight model. We will present the development status of the JEM-GLISM mission and discuss the scientific outputs derived from this mission more in detail.

Assessment of SOI Devices and Circuits at Extreme Temperatures

NASA Technical Reports Server (NTRS)

Elbuluk, Malik; Hammoud, Ahmad; Patterson, Richard L.

2007-01-01

Electronics designed for use in future NASA space exploration missions are expected to encounter extreme temperatures and wide thermal swings. Such missions include planetary surface exploration, bases, rovers, landers, orbiters, and satellites. Electronics designed for such applications must, therefore, be able to withstand exposure to extreme temperatures and to perform properly for the duration of mission. The Low Temperature Electronics Program at the NASA Glenn Research Center focuses on research and development of electrical devices, circuits, and systems suitable for applications in deep space exploration missions and aerospace environment. Silicon-On-Insulator (SOI) technology has been under active consideration in the electronics industry for many years due to the advantages that it can provide in integrated circuit (IC) chips and computer processors. Faster switching, less power, radiationtolerance, reduced leakage, and high temp-erature capability are some of the benefits that are offered by using SOI-based devices. A few SOI circuits are available commercially. However, there is a noticeable interest in SOI technology for different applications. Very little data, however, exist on the performance of such circuits under cryogenic temperatures. In this work, the performance of SOI integrated circuits, evaluated under low temperature and thermal cycling, are reported. In particular, three examples of SOI circuits that have been tested for operation at low at temperatures are given. These circuits are SOI operational amplifiers, timers and power MOSFET drivers. The investigations were carried out to establish a baseline on the functionality and to determine suitability of these circuits for use in space exploration missions at cryogenic temperatures. The findings are useful to mission planners and circuit designers so that proper selection of electronic parts can be made, and risk assessment can be established for such circuits for use in space missions.

Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

DOEpatents

Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

2001-01-01

A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

A CMOS Luminescence Intensity and Lifetime Dual Sensor Based on Multicycle Charge Modulation.

PubMed

Fu, Guoqing; Sonkusale, Sameer R

2018-06-01

Luminescence plays an important role in many scientific and industrial applications. This paper proposes a novel complementary metal-oxide-semiconductor (CMOS) sensor chip that can realize both luminescence intensity and lifetime sensing. To enable high sensitivity, we propose parasitic insensitive multicycle charge modulation scheme for low-light lifetime extraction benefiting from simplicity, accuracy, and compatibility with deeply scaled CMOS process. The designed in-pixel capacitive transimpedance amplifier (CTIA) based structure is able to capture the weak luminescence-induced voltage signal by accumulating photon-generated charges in 25 discrete gated 10-ms time windows and 10-μs pulsewidth. A pinned photodiode on chip with 1.04 pA dark current is utilized for luminescence detection. The proposed CTIA-based circuitry can achieve 2.1-mV/(nW/cm 2 ) responsivity and 4.38-nW/cm 2 resolution at 630 nm wavelength for intensity measurement and 45-ns resolution for lifetime measurement. The sensor chip is employed for measuring time constants and luminescence lifetimes of an InGaN-based white light-emitting diode at different wavelengths. In addition, we demonstrate accurate measurement of the lifetime of an oxygen sensitive chromophore with sensitivity to oxygen concentration of 7.5%/ppm and 6%/ppm in both intensity and lifetime domain. This CMOS-enabled oxygen sensor was then employed to test water quality from different sources (tap water, lakes, and rivers).

SOI technology for power management in automotive and industrial applications

NASA Astrophysics Data System (ADS)

Stork, Johannes M. C.; Hosey, George P.

2017-02-01

Semiconductor on Insulator (SOI) technology offers an assortment of opportunities for chip manufacturers in the Power Management market. Recent advances in the automotive and industrial markets, along with emerging features, the increasing use of sensors, and the ever-expanding "Internet of Things" (IoT) are providing for continued growth in these markets while also driving more complex solutions. The potential benefits of SOI include the ability to place both high-voltage and low-voltage devices on a single chip, saving space and cost, simplifying designs and models, and improving performance, thereby cutting development costs and improving time to market. SOI also offers novel new approaches to long-standing technologies.

Thick-SOI Echelle grating for any-to-any wavelength routing interconnection in multi-socket computing environments

NASA Astrophysics Data System (ADS)

Dabos, G.; Pitris, S.; Mitsolidou, C.; Alexoudi, T.; Fitsios, D.; Cherchi, M.; Harjanne, M.; Aalto, T.; Kanellos, G. T.; Pleros, N.

2017-02-01

As data centers constantly expand, electronic switches are facing the challenge of enhanced scalability and the request for increased pin-count and bandwidth. Photonic technology and wavelength division multiplexing have always been a strong alternative for efficient routing and their potential was already proven in the telecoms. CWDM transceivers have emerged in the board-to-board level interconnection, revealing the potential for wavelength-routing to be applied in the datacom and an AWGR-based approach has recently been proposed towards building an optical multi-socket interconnection to offer any-to-any connectivity with high aggregated throughput and reduced power consumption. Echelle gratings have long been recognized as the multiplexing block exhibiting smallest footprint and robustness in a wide number of applications compared to other alternatives such as the Arrayed Waveguide Grating. Such filtering devices can also perform in a similar way to cyclical AWGR and serve as mid-board routing platforms in multi-socket environments. In this communication, we present such a 3x3 Echelle grating integrated on thick SOI platform with aluminum-coated facets that is shown to perform successful wavelength-routing functionality at 10 Gb/s. The device exhibits a footprint of 60x270 μm2, while the static characterization showed a 3 dB on-chip loss for the best channel. The 3 dB-bandwidth of the channels was 4.5 nm and the free spectral range was 90 nm. The echelle was evaluated in a 2x2 wavelength routing topology, exhibiting a power penalty of below 0.4 dB at 10-9 BER for the C-band. Further experimental evaluations of the platform involve commercially available CWDM datacenter transceivers, towards emulating an optically-interconnected multi-socket environment traffic scenario.

A sub-nJ CMOS ECG classifier for wireless smart sensor.

PubMed

Chollet, Paul; Pallas, Remi; Lahuec, Cyril; Arzel, Matthieu; Seguin, Fabrice

2017-07-01

Body area sensor networks hold the promise of more efficient and cheaper medical care services through the constant monitoring of physiological markers such as heart beats. Continuously transmitting the electrocardiogram (ECG) signal requires most of the wireless ECG sensor energy budget. This paper presents the analog implantation of a classifier for ECG signals that can be embedded onto a sensor. The classifier is a sparse neural associative memory. It is implemented using the ST 65 nm CMOS technology and requires only 234 pJ per classification while achieving a 93.6% classification accuracy. The energy requirement is 6 orders of magnitude lower than a digital accelerator that performs a similar task. The lifespan of the resulting sensor is 191 times as large as that of a sensor sending all the data.

A goggle navigation system for cancer resection surgery

NASA Astrophysics Data System (ADS)

Xu, Junbin; Shao, Pengfei; Yue, Ting; Zhang, Shiwu; Ding, Houzhu; Wang, Jinkun; Xu, Ronald

2014-02-01

We describe a portable fluorescence goggle navigation system for cancer margin assessment during oncologic surgeries. The system consists of a computer, a head mount display (HMD) device, a near infrared (NIR) CCD camera, a miniature CMOS camera, and a 780 nm laser diode excitation light source. The fluorescence and the background images of the surgical scene are acquired by the CCD camera and the CMOS camera respectively, co-registered, and displayed on the HMD device in real-time. The spatial resolution and the co-registration deviation of the goggle navigation system are evaluated quantitatively. The technical feasibility of the proposed goggle system is tested in an ex vivo tumor model. Our experiments demonstrate the feasibility of using a goggle navigation system for intraoperative margin detection and surgical guidance.

Three-mode all-optical (de)multiplexing on a SOI chip

NASA Astrophysics Data System (ADS)

Le, Yan-Si; Wang, Zhi; Li, Zhi-Yong; Li, Ying; Li, Qiang; Cui, Can; Wu, Chong-Qing

2018-01-01

An on-chip three-mode division multiplexing circuit using a simple ADC-based TE0 & TE1 & TE2 (de)multiplexer is demonstrated to improve the link capacity of on-chip optical interconnects. The proposed (de)multiplexer does not contain any tapered waveguide which is different from the previous mode (de)multiplexer based on ADCs. Here, we choose multimode waveguide width first and then confirm corresponding width of the other two waveguides. Thus the bus waveguide without any tapers can not only reduce complexity of (de)multiplexer but also reduce difficulty of the fabrication. Our simulation results show that the hybrid multiplexer has relatively low loss and low crosstalk about -40 dB, -26.99 dB and -28.72 dB for each mode around 1550 nm with a width-variation w =± 25 nm. These properties make the proposed mode-(de)multiplexer suitable for application in high-capacity data transmission.

A webcam in Bayer-mode as a light beam profiler for the near infra-red

PubMed Central

Langer, Gregor; Hochreiner, Armin; Burgholzer, Peter; Berer, Thomas

2013-01-01

Beam profiles are commonly measured with complementary metal oxide semiconductors (CMOS) or charge coupled devices (CCD). The devices are fast and reliable but expensive. By making use of the fact that the Bayer-filter in commercial webcams is transparent in the near infra-red (>800 nm) and their CCD chips are sensitive up to about 1100 nm, we demonstrate a cheap and simple way to measure laser beam profiles with a resolution down to around ±1 μm, which is close to the resolution of the knife-edge technique. PMID:23645943

A webcam in Bayer-mode as a light beam profiler for the near infra-red.

PubMed

Langer, Gregor; Hochreiner, Armin; Burgholzer, Peter; Berer, Thomas

2013-05-01

Beam profiles are commonly measured with complementary metal oxide semiconductors (CMOS) or charge coupled devices (CCD). The devices are fast and reliable but expensive. By making use of the fact that the Bayer-filter in commercial webcams is transparent in the near infra-red (>800 nm) and their CCD chips are sensitive up to about 1100 nm, we demonstrate a cheap and simple way to measure laser beam profiles with a resolution down to around ±1 μm, which is close to the resolution of the knife-edge technique.

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays.

PubMed

Sánchez-Azqueta, Carlos; Goll, Bernhard; Celma, Santiago; Zimmermann, Horst

2016-05-25

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of -26.0 dBm and -25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10(-9) ) with an energy efficiency of 2 pJ/bit.

OPC for curved designs in application to photonics on silicon

NASA Astrophysics Data System (ADS)

Orlando, Bastien; Farys, Vincent; Schneider, Loïc.; Cremer, Sébastien; Postnikov, Sergei V.; Millequant, Matthieu; Dirrenberger, Mathieu; Tiphine, Charles; Bayle, Sébastian; Tranquillin, Céline; Schiavone, Patrick

2016-03-01

Today's design for photonics devices on silicon relies on non-Manhattan features such as curves and a wide variety of angles with minimum feature size below 100nm. Industrial manufacturing of such devices requires optimized process window with 193nm lithography. Therefore, Resolution Enhancement Techniques (RET) that are commonly used for CMOS manufacturing are required. However, most RET algorithms are based on Manhattan fragmentation (0°, 45° and 90°) which can generate large CD dispersion on masks for photonic designs. Industrial implementation of RET solutions to photonic designs is challenging as most currently available OPC tools are CMOS-oriented. Discrepancy from design to final results induced by RET techniques can lead to lower photonic device performance. We propose a novel sizing algorithm allowing adjustment of design edge fragments while preserving the topology of the original structures. The results of the algorithm implementation in the rule based sizing, SRAF placement and model based correction will be discussed in this paper. Corrections based on this novel algorithm were applied and characterized on real photonics devices. The obtained results demonstrate the validity of the proposed correction method integrated in Inscale software of Aselta Nanographics.

Simulation environment based on the Universal Verification Methodology

NASA Astrophysics Data System (ADS)

Fiergolski, A.

2017-01-01

Universal Verification Methodology (UVM) is a standardized approach of verifying integrated circuit designs, targeting a Coverage-Driven Verification (CDV). It combines automatic test generation, self-checking testbenches, and coverage metrics to indicate progress in the design verification. The flow of the CDV differs from the traditional directed-testing approach. With the CDV, a testbench developer, by setting the verification goals, starts with an structured plan. Those goals are targeted further by a developed testbench, which generates legal stimuli and sends them to a device under test (DUT). The progress is measured by coverage monitors added to the simulation environment. In this way, the non-exercised functionality can be identified. Moreover, the additional scoreboards indicate undesired DUT behaviour. Such verification environments were developed for three recent ASIC and FPGA projects which have successfully implemented the new work-flow: (1) the CLICpix2 65 nm CMOS hybrid pixel readout ASIC design; (2) the C3PD 180 nm HV-CMOS active sensor ASIC design; (3) the FPGA-based DAQ system of the CLICpix chip. This paper, based on the experience from the above projects, introduces briefly UVM and presents a set of tips and advices applicable at different stages of the verification process-cycle.

Thin-Film Quantum Dot Photodiode for Monolithic Infrared Image Sensors.

PubMed

Malinowski, Pawel E; Georgitzikis, Epimitheas; Maes, Jorick; Vamvaka, Ioanna; Frazzica, Fortunato; Van Olmen, Jan; De Moor, Piet; Heremans, Paul; Hens, Zeger; Cheyns, David

2017-12-10

Imaging in the infrared wavelength range has been fundamental in scientific, military and surveillance applications. Currently, it is a crucial enabler of new industries such as autonomous mobility (for obstacle detection), augmented reality (for eye tracking) and biometrics. Ubiquitous deployment of infrared cameras (on a scale similar to visible cameras) is however prevented by high manufacturing cost and low resolution related to the need of using image sensors based on flip-chip hybridization. One way to enable monolithic integration is by replacing expensive, small-scale III-V-based detector chips with narrow bandgap thin-films compatible with 8- and 12-inch full-wafer processing. This work describes a CMOS-compatible pixel stack based on lead sulfide quantum dots (PbS QD) with tunable absorption peak. Photodiode with a 150-nm thick absorber in an inverted architecture shows dark current of 10 -6 A/cm² at -2 V reverse bias and EQE above 20% at 1440 nm wavelength. Optical modeling for top illumination architecture can improve the contact transparency to 70%. Additional cooling (193 K) can improve the sensitivity to 60 dB. This stack can be integrated on a CMOS ROIC, enabling order-of-magnitude cost reduction for infrared sensors.

Co-integrating plasmonics with Si3N4 photonics towards a generic CMOS compatible PIC platform for high-sensitivity multi-channel biosensors: the H2020 PlasmoFab approach (Conference Presentation)

NASA Astrophysics Data System (ADS)

Tsiokos, Dimitris M.; Dabos, George; Ketzaki, Dimitra; Weeber, Jean-Claude; Markey, Laurent; Dereux, Alain; Giesecke, Anna Lena; Porschatis, Caroline; Chmielak, Bartos; Wahlbrink, Thorsten; Rochracher, Karl; Pleros, Nikos

2017-05-01

Silicon photonics meet most fabrication requirements of standard CMOS process lines encompassing the photonics-electronics consolidation vision. Despite this remarkable progress, further miniaturization of PICs for common integration with electronics and for increasing PIC functional density is bounded by the inherent diffraction limit of light imposed by optical waveguides. Instead, Surface Plasmon Polariton (SPP) waveguides can guide light at sub-wavelength scales at the metal surface providing unique light-matter interaction properties, exploiting at the same time their metallic nature to naturally integrate with electronics in high-performance ASPICs. In this article, we demonstrate the main goals of the recently introduced H2020 project PlasmoFab towards addressing the ever increasing needs for low energy, small size and high performance mass manufactured PICs by developing a revolutionary yet CMOS-compatible fabrication platform for seamless co-integration of plasmonics with photonic and supporting electronic. We demonstrate recent advances on the hosting SiN photonic hosting platform reporting on low-loss passive SiN waveguide and Grating Coupler circuits for both the TM and TE polarization states. We also present experimental results of plasmonic gold thin-film and hybrid slot waveguide configurations that can allow for high-sensitivity sensing, providing also the ongoing activities towards replacing gold with Cu, Al or TiN metal in order to yield the same functionality over a CMOS metallic structure. Finally, the first experimental results on the co-integrated SiN+plasmonic platform are demonstrated, concluding to an initial theoretical performance analysis of the CMOS plasmo-photonic biosensor that has the potential to allow for sensitivities beyond 150000nm/RIU.

ZnO/(Hf,Zr)O2/ZnO-trilayered nanowire capacitor structure fabricated solely by metalorganic chemical vapor deposition

NASA Astrophysics Data System (ADS)

Fujisawa, Hironori; Kuwamoto, Kei; Nakashima, Seiji; Shimizu, Masaru

2016-02-01

HfO2-based thin films are one of the key dielectric and ferroelectric materials in Si-CMOS LSIs as well as in oxide electronic nanodevices. In this study, we demonstrated the fabrication of a ZnO/(Hf,Zr)O2/ZnO-trilayered nanowire (NW) capacitor structure solely by metalorganic chemical vapor deposition (MOCVD). 15-nm-thick dielectric (Hf,Zr)O2 and 40-nm-thick top ZnO electrode layers were uniformly grown by MOCVD on a ZnO NW template with average diameter, length, and aspect ratio of 110 nm, 10 µm, and ˜90, respectively. The diameter and aspect ratio of the resultant trilayerd NWs are 200-300 nm and above 30, respectively. The crystalline phase of HfO2 and stacked the structure are also discussed.

Characterizing SOI Wafers By Use Of AOTF-PHI

NASA Technical Reports Server (NTRS)

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

Effects of spin-orbit coupling and many-body correlations in STM transport through copper phthalocyanine.

PubMed

Siegert, Benjamin; Donarini, Andrea; Grifoni, Milena

2015-01-01

The interplay of exchange correlations and spin-orbit interaction (SOI) on the many-body spectrum of a copper phtalocyanine (CuPc) molecule and their signatures in transport are investigated. We first derive a minimal model Hamiltonian in a basis of frontier orbitals that is able to reproduce experimentally observed singlet-triplet splittings. In a second step SOI effects are included perturbatively. Major consequences of the SOI are the splitting of former degenerate levels and a magnetic anisotropy, which can be captured by an effective low-energy spin Hamiltonian. We show that scanning tunneling microscopy-based magnetoconductance measurements can yield clear signatures of both these SOI-induced effects.

Development of the Stress of Immigration Survey (SOIS): a Field Test among Mexican Immigrant Women

PubMed Central

Sternberg, Rosa Maria; Nápoles, Anna Maria; Gregorich, Steven; Paul, Steven; Lee, Kathryn A.; Stewart, Anita L.

2016-01-01

The Stress of Immigration Survey (SOIS) is a screening tool used to assess immigration-related stress. The mixed methods approach included concept development, pretesting, field-testing, and psychometric evaluation in a sample of 131 low-income women of Mexican descent. The 21-item SOIS screens for stress related to language; immigrant status; work issues; yearning for family and home country; and cultural dissonance. Mean scores ranged from 3.6 to 4.4 (1-5 scale, higher is more stress). Cronbach's alphas >.80 for all sub-scales. The SOIS may be a useful screening tool for detecting high levels of immigration-related stress in low-income Mexican immigrant women. PMID:26605954

Optical-Interferometry-Based CMOS-MEMS Sensor Transduced by Stress-Induced Nanomechanical Deflection

PubMed Central

Maruyama, Satoshi; Hizawa, Takeshi; Takahashi, Kazuhiro; Sawada, Kazuaki

2018-01-01

We developed a Fabry–Perot interferometer sensor with a metal-oxide-semiconductor field-effect transistor (MOSFET) circuit for chemical sensing. The novel signal transducing technique was performed in three steps: mechanical deflection, transmittance change, and photocurrent change. A small readout photocurrent was processed by an integrated source follower circuit. The movable film of the sensor was a 350-nm-thick polychloro-para-xylylene membrane with a diameter of 100 µm and an air gap of 300 nm. The linearity of the integrated source follower circuit was obtained. We demonstrated a gas response using 80-ppm ethanol detected by small membrane deformation of 50 nm, which resulted in an output-voltage change with the proposed high-efficiency transduction. PMID:29304011

Optical-Interferometry-Based CMOS-MEMS Sensor Transduced by Stress-Induced Nanomechanical Deflection.

PubMed

Maruyama, Satoshi; Hizawa, Takeshi; Takahashi, Kazuhiro; Sawada, Kazuaki

2018-01-05

We developed a Fabry-Perot interferometer sensor with a metal-oxide-semiconductor field-effect transistor (MOSFET) circuit for chemical sensing. The novel signal transducing technique was performed in three steps: mechanical deflection, transmittance change, and photocurrent change. A small readout photocurrent was processed by an integrated source follower circuit. The movable film of the sensor was a 350-nm-thick polychloro-para-xylylene membrane with a diameter of 100 µm and an air gap of 300 nm. The linearity of the integrated source follower circuit was obtained. We demonstrated a gas response using 80-ppm ethanol detected by small membrane deformation of 50 nm, which resulted in an output-voltage change with the proposed high-efficiency transduction.

Twin-bit via resistive random access memory in 16 nm FinFET logic technologies

NASA Astrophysics Data System (ADS)

Shih, Yi-Hong; Hsu, Meng-Yin; King, Ya-Chin; Lin, Chrong Jung

2018-04-01

A via resistive random access memory (RRAM) cell fully compatible with the standard CMOS logic process has been successfully demonstrated for high-density logic nonvolatile memory (NVM) modules in advanced FinFET circuits. In this new cell, the transition metal layers are formed on both sides of a via, given two storage bits per via. In addition to its compact cell area (1T + 14 nm × 32 nm), the twin-bit via RRAM cell features a low operation voltage, a large read window, good data retention, and excellent cycling capability. As fine alignments between mask layers become possible, the twin-bit via RRAM cell is expected to be highly scalable in advanced FinFET technology.

Progress and opportunities in high-voltage microactuator powering technology towards one-chip MEMS

NASA Astrophysics Data System (ADS)

Mita, Yoshio; Hirakawa, Atsushi; Stefanelli, Bruno; Mori, Isao; Okamoto, Yuki; Morishita, Satoshi; Kubota, Masanori; Lebrasseur, Eric; Kaiser, Andreas

2018-04-01

In this paper, we address issues and solutions for micro-electro-mechanical-systems (MEMS) powering through semiconductor devices towards one-chip MEMS, especially those with microactuators that require high voltage (HV, which is more than 10 V, and is often over 100 V) for operation. We experimentally and theoretically demonstrated that the main reason why MEMS actuators need such HV is the tradeoff between resonant frequency and displacement amplitude. Indeed, the product of frequency and displacement is constant regardless of the MEMS design, but proportional to the input energy, which is the square of applied voltage in an electrostatic actuator. A comprehensive study on the principles of HV device technology and associated circuit technologies, especially voltage shifter circuits, was conducted. From the viewpoint of on-chip energy source, series-connected HV photovoltaic cells have been discussed. Isolation and electrical connection methods were identified to be key enabling technologies. Towards future rapid development of such autonomous devices, a technology to convert standard 5 V CMOS devices into HV circuits using SOI substrate and a MEMS postprocess is presented. HV breakdown experiments demonstrated this technology can hold over 700 to 1000 V, depending on the layout.

Thermal Flow Sensors for Harsh Environments.

PubMed

Balakrishnan, Vivekananthan; Phan, Hoang-Phuong; Dinh, Toan; Dao, Dzung Viet; Nguyen, Nam-Trung

2017-09-08

Flow sensing in hostile environments is of increasing interest for applications in the automotive, aerospace, and chemical and resource industries. There are thermal and non-thermal approaches for high-temperature flow measurement. Compared to their non-thermal counterparts, thermal flow sensors have recently attracted a great deal of interest due to the ease of fabrication, lack of moving parts and higher sensitivity. In recent years, various thermal flow sensors have been developed to operate at temperatures above 500 °C. Microelectronic technologies such as silicon-on-insulator (SOI), and complementary metal-oxide semiconductor (CMOS) have been used to make thermal flow sensors. Thermal sensors with various heating and sensing materials such as metals, semiconductors, polymers and ceramics can be selected according to the targeted working temperature. The performance of these thermal flow sensors is evaluated based on parameters such as thermal response time, flow sensitivity. The data from thermal flow sensors reviewed in this paper indicate that the sensing principle is suitable for the operation under harsh environments. Finally, the paper discusses the packaging of the sensor, which is the most important aspect of any high-temperature sensing application. Other than the conventional wire-bonding, various novel packaging techniques have been developed for high-temperature application.

2D materials integrated in Si3N4 photonics platform

NASA Astrophysics Data System (ADS)

Faneca, Joaquin; Hogan, Benjamin T.; Torres Alonso, E.; Craciun, Monica; Baldycheva, Anna

2018-02-01

In this paper, we discuss a back-end CMOS fabrication process for the large-scale integration of 2D materials on SOI (siliconon-insulator) platform and present a complete theoretical study of the change in the effective refractive index of 2D materialsenabled silicon nitride waveguide structures. The chemical vapour deposition (CVD) and liquid exfoliation fabrication methods are described for the fabrication of graphene, WS2 and MoS2 thin films. Finite-difference frequency-domain (FDFD) approach and the Transfer Matrix Method were used in order to mathematically describe these structures. The introduction of thin films of 2D material onto Si3N4 waveguide structures allows manipulation of the optical characteristics to a high degree of precision by varying the Fermi-level through the engineering of the number of atomically thin layers or by electrical tuning, for example. Based on the proposed tuning approach, designs of graphene, WS2 and MoS2 enabled Si3N4 micro-ring structures are presented for the visible and NIR range, which demonstrate versatility and desirable properties for a wide range of applications, such as bio-chemical sensing and optical communications.

Thermal Flow Sensors for Harsh Environments

PubMed Central

Dinh, Toan; Dao, Dzung Viet

2017-01-01

Flow sensing in hostile environments is of increasing interest for applications in the automotive, aerospace, and chemical and resource industries. There are thermal and non-thermal approaches for high-temperature flow measurement. Compared to their non-thermal counterparts, thermal flow sensors have recently attracted a great deal of interest due to the ease of fabrication, lack of moving parts and higher sensitivity. In recent years, various thermal flow sensors have been developed to operate at temperatures above 500 °C. Microelectronic technologies such as silicon-on-insulator (SOI), and complementary metal-oxide semiconductor (CMOS) have been used to make thermal flow sensors. Thermal sensors with various heating and sensing materials such as metals, semiconductors, polymers and ceramics can be selected according to the targeted working temperature. The performance of these thermal flow sensors is evaluated based on parameters such as thermal response time, flow sensitivity. The data from thermal flow sensors reviewed in this paper indicate that the sensing principle is suitable for the operation under harsh environments. Finally, the paper discusses the packaging of the sensor, which is the most important aspect of any high-temperature sensing application. Other than the conventional wire-bonding, various novel packaging techniques have been developed for high-temperature application. PMID:28885595

High performance tunnel field-effect transistor by gate and source engineering.

PubMed

Huang, Ru; Huang, Qianqian; Chen, Shaowen; Wu, Chunlei; Wang, Jiaxin; An, Xia; Wang, Yangyuan

2014-12-19

As one of the most promising candidates for future nanoelectronic devices, tunnel field-effect transistors (TFET) can overcome the subthreshold slope (SS) limitation of MOSFET, whereas high ON-current, low OFF-current and steep switching can hardly be obtained at the same time for experimental TFETs. In this paper, we developed a new nanodevice technology based on TFET concepts. By designing the gate configuration and introducing the optimized Schottky junction, a multi-finger-gate TFET with a dopant-segregated Schottky source (mFSB-TFET) is proposed and experimentally demonstrated. A steeper SS can be achieved in the fabricated mFSB-TFET on the bulk Si substrate benefiting from the coupled quantum band-to-band tunneling (BTBT) mechanism, as well as a high I(ON)/I(OFF) ratio (∼ 10(7)) at V(DS) = 0.2 V without an area penalty. By compatible SOI CMOS technology, the fabricated Si mFSB-TFET device was further optimized with a high ION/IOFF ratio of ∼ 10(8) and a steeper SS of over 5.5 decades of current. A minimum SS of below 60 mV dec(-1) was experimentally obtained, indicating its dominant quantum BTBT mechanism for switching.

Monolithically Integrated InGaAs Nanowires on 3D Structured Silicon-on-Insulator as a New Platform for Full Optical Links.

PubMed

Kim, Hyunseok; Farrell, Alan C; Senanayake, Pradeep; Lee, Wook-Jae; Huffaker, Diana L

2016-03-09

Monolithically integrated III-V semiconductors on a silicon-on-insulator (SOI) platform can be used as a building block for energy-efficient on-chip optical links. Epitaxial growth of III-V semiconductors on silicon, however, has been challenged by the large mismatches in lattice constants and thermal expansion coefficients between epitaxial layers and silicon substrates. Here, we demonstrate for the first time the monolithic integration of InGaAs nanowires on the SOI platform and its feasibility for photonics and optoelectronic applications. InGaAs nanowires are grown not only on a planar SOI layer but also on a 3D structured SOI layer by catalyst-free metal-organic chemical vapor deposition. The precise positioning of nanowires on 3D structures, including waveguides and gratings, reveals the versatility and practicality of the proposed platform. Photoluminescence measurements exhibit that the composition of ternary InGaAs nanowires grown on the SOI layer has wide tunability covering all telecommunication wavelengths from 1.2 to 1.8 μm. We also show that the emission from an optically pumped single nanowire is effectively coupled and transmitted through an SOI waveguide, explicitly showing that this work lays the foundation for a new platform toward energy-efficient optical links.

Effect of strain on the electron effective mobility in biaxially strained silicon inversion layers: An experimental and theoretical analysis via atomic force microscopy measurements and Kubo-Greenwood mobility calculations

NASA Astrophysics Data System (ADS)

Bonno, Olivier; Barraud, Sylvain; Mariolle, Denis; Andrieu, François

2008-03-01

Recently, in order to explain the long-channel electron effective mobility at a high sheet carrier density in strained silicon channel transistors, it has been suggested by [M. V. Fischetti, F. Gamiz, and W. Hansch, J. Appl. Phys. 92, 7230 (2002)] that biaxial tensile strain should smooth the Si/SiO2 interface. To address this topic, the roughness properties of biaxial strained silicon-on-insulator (s-SOI) films are investigated by means of atomic force microscopy. Through in-depth statistical analysis of the digitalized surface profiles, the roughness parameters are extracted for unstrained and strained SOI films, with 0.8% biaxial tensile strain. Especially, it is found that strain significantly reduces the roughness amplitude. Then, mobility calculations in SOI and s-SOI inversion layers are performed in the framework of the Kubo-Greenwood formalism. The model accounts for the main scattering mechanisms that are dominant in the high electron density range, namely phonon and surface roughness. Special attention has been paid to the modeling of the latter by accounting for all the contributions of the potential which arise from the deformed rough interface, and by using a multisubband wavelength-dependent screening model. This model is then applied to study the influence of the surface morphology on the mobility in s-SOI inversion layers. In this context, the mobility gain between s-SOI and unstrained SOI layers is found to agree significantly better with experimental data if the strain-induced decrease of the roughness amplitude is taken into account.

Characterisation results of the CMOS VISNIR spectral band detector for the METimage instrument

NASA Astrophysics Data System (ADS)

Pratlong, Jérôme; Schmuelling, Frank; Benitez, Victor; Breart De Boisanger, Michel; Skegg, Michael; Simpson, Robert; Bowring, Steve; Krzizok, Natalie

2017-09-01

The METimage instrument is part of the EPS-SG (EUMETSAT Polar System Second Generation) program. It will be situated on the MetOp-SG platform which in operation has an objective of collecting data for meteorology and climate monitoring as well as their forecasting. Teledyne e2v has developed and characterised the CMOS VISNIR detector flight module part of the METimage instrument. This paper will focus on the silicon results obtained from the CMOS VISNIR detector flight model. The detector is a large multi-linear device composed of 7 spectral bands covering a wavelength range from 428 nm to 923 nm (some bands are placed twice and added together to enhance the signal-to-noise performance). This detector uses a 4T pixel, with a size of 250μm square, presenting challenges to achieve good charge transfer efficiency with high conversion factor and good linearity for signal levels up to 2M electrons and with high line rates. Low noise has been achieved using correlated double sampling to suppress the read-out noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. The photodiode occupies a significant fraction of the large pixel area. This makes it possible to meet the detection efficiency when front illuminated. A thicker than standard epitaxial silicon is used to improve NIR response. However, the dielectric stack on top of the sensor produces Fabry-Perot étalon effects, which are problematic for narrow band illumination as this causes the detection efficiency to vary significantly over a small wavelength range. In order to reduce this effect and to meet the specification, the silicon manufacturing process has been modified. The flight model will have black coating deposited between each spectral channel, onto the active silicon regions.

Direct synthesis of ultrathin SOI structure by extremely low-energy oxygen implantation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hoshino, Yasushi, E-mail: yhoshino@kanagawa-u.ac.jp; Yachida, Gosuke; Inoue, Kodai

2016-06-15

We performed extremely low-energy {sup 16}O{sup +} implantation at 10 keV (R{sub p} ∼ 25 nm) followed by annealing aiming at directly synthesizing an ultrathin Si layer separated by a buried SiO{sub 2} layer in Si(001) substrates, and then investigated feasible condition of recrystallization and stabilization of the superficial Si and the buried oxide layer by significantly low temperature annealing. The elemental compositions were analyzed by Rutherford backscattering (RBS) and secondary ion mass spectroscopy (SIMS). The crystallinity of the superficial Si layer was quantitatively confirmed by ananlyzing RBS-channeling spectra. Cross-sectional morphologies and atomic configurations were observed by transmission electron microscopemore » (TEM). As a result, we succeeded in directly synthesizing an ultrathin single-crystalline silicon layer with ≤20 nm thick separated by a thin buried stoichiometric SiO{sub 2} layer with ≤20 nm thick formed by extremely low-energy {sup 16}O{sup +} implantation followed by surprisingly low temperature annealing at 1050{sup ∘} C.« less

Hardness assurance for proton direct ionization-induced SEEs using a high-energy proton beam

DOE PAGES

Dodds, Nathaniel Anson; Schwank, James R.; Shaneyfelt, Marty R.; ...

2014-11-06

The low-energy proton energy spectra of all shielded space environments have the same shape. This shape is easily reproduced in the laboratory by degrading a high-energy proton beam, producing a high-fidelity test environment. We use this test environment to dramatically simplify rate prediction for proton direct ionization effects, allowing the work to be done at high-energy proton facilities, on encapsulated parts, without knowledge of the IC design, and with little or no computer simulations required. Proton direct ionization (PDI) is predicted to significantly contribute to the total error rate under the conditions investigated. Scaling effects are discussed using data frommore » 65-nm, 45-nm, and 32-nm SOI SRAMs. These data also show that grazing-angle protons will dominate the PDI-induced error rate due to their higher effective LET, so PDI hardness assurance methods must account for angular effects to be conservative. As a result, we show that this angular dependence can be exploited to quickly assess whether an IC is susceptible to PDI.« less

On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS

PubMed Central

Liang, Yuan; Yu, Hao; Wen, Jincai; Apriyana, Anak Agung Alit; Li, Nan; Luo, Yu; Sun, Lingling

2016-01-01

An on-chip low-loss and high conversion efficiency plasmonic waveguide converter is demonstrated at sub-THz in CMOS. By introducing a subwavelength periodic corrugated structure onto the transmission line (T-line) implemented by a top-layer metal, surface plasmon polaritons (SPP) are established to propagate signals with strongly localized surface-wave. To match both impedance and momentum of other on-chip components with TEM-wave propagation, a mode converter structure featured by a smooth bridge between the Ground coplanar waveguide (GCPW) with 50 Ω impedance and SPP T-line is proposed. To further reduce area, the converter is ultimately simplified to a gradual increment of groove with smooth gradient. The proposed SPP T-lines with the converter is designed and fabricated in the standard 65 nm CMOS process. Both near-field simulation and measurement results show excellent conversion efficiency from quasi-TEM to SPP modes in a broadband frequency range. The converter achieves wideband impedance matching (<−9 dB) with excellent transmission efficiency (averagely −1.9 dB) from 110 GHz–325 GHz. The demonstrated compact and wideband SPP T-lines with mode converter have shown great potentials to replace existing waveguides as future on-chip THz interconnects. To the best of the author’s knowledge, this is the first time to demonstrate the (sub)-THz surface mode conversion on-chip in CMOS technology. PMID:27444782

A saw-less direct conversion long term evolution receiver with 25% duty-cycle LO in 130 nm CMOS technology

NASA Astrophysics Data System (ADS)

Siyuan, He; Changhong, Zhang; Liang, Tao; Weifeng, Zhang; Longyue, Zeng; Wei, Lü; Haijun, Wu

2013-03-01

A CMOS long-term evolution (LTE) direct convert receiver that eliminates the interstage SAW filter is presented. The receiver consists of a low noise variable gain transconductance amplifier (TCA), a quadrature passive current commutating mixer with a 25% duty-cycle LO, a trans-impedance amplifier (TIA), a 7th-order Chebyshev filter and programmable gain amplifiers (PGAs). A wide dynamic gain range is allocated in the RF and analog parts. A current commutating passive mixer with a 25% duty-cycle LO improves gain, noise, and linearity. An LPF based on a Tow-Thomas biquad suppresses out-of-band interference. Fabricated in a 0.13 μm CMOS process, the receiver chain achieves a 107 dB maximum voltage gain, 2.7 dB DSB NF (from PAD port), -11 dBm IIP3, and > +65 dBm IIP2 after calibration, 96 dB dynamic control range with 1 dB steps, less than 2% error vector magnitude (EVM) from 2.3 to 2.7 GHz. The total receiver (total I Q path) draws 89 mA from a 1.2-V LDO on chip supply.

Three-dimensional crossbar arrays of self-rectifying Si/SiO 2/Si memristors

DOE PAGES

Li, Can; Han, Lili; Jiang, Hao; ...

2017-06-05

Memristors are promising building blocks for the next generation memory, unconventional computing systems and beyond. Currently common materials used to build memristors are not necessarily compatible with the silicon dominant complementary metal-oxide-semiconductor (CMOS) technology. Furthermore, external selector devices or circuits are usually required in order for large memristor arrays to function properly, resulting in increased circuit complexity. Here we demonstrate fully CMOS-compatible, all-silicon based and self-rectifying memristors that negate the need for external selectors in large arrays. It consists of p- and n-type doped single crystalline silicon electrodes and a thin chemically produced silicon oxide switching layer. The device exhibitsmore » repeatable resistance switching behavior with high rectifying ratio (10 5), high ON/OFF conductance ratio (10 4) and attractive retention at 300 °C. We further build a 5-layer 3-dimensional (3D) crossbar array of 100 nm memristors by stacking fluid supported silicon membranes. The CMOS compatibility and self-rectifying behavior open up opportunities for mass production of memristor arrays and 3D hybrid circuits on full-wafer scale silicon and flexible substrates without increasing circuit complexity.« less

Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Meier, Christian; Csaba, György; Breitkreutz-von Gamm, Stephan

2017-05-01

Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF) receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz) signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA). Then, it is down-converted by a mixer to Intermediate Frequency (IF). Finally, an Operational Amplifier (OpAmp) brings the IF signal to higher voltages (50-300 mV). The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO) is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

Energy-efficient neuron, synapse and STDP integrated circuits.

PubMed

Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

2012-06-01

Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alloatti, L., E-mail: luca.alloatti@gmail.com; Cheian, D.; Ram, R. J.

A microring depletion modulator is demonstrated with T-shaped lateral p-n junctions used to realize efficient modulation while maximizing the RC limited bandwidth. The device having a 3 dB bandwidth of 13 GHz has been fabricated in a standard 45 nm microelectronics CMOS process. The cavity has a linewidth of 17 GHz and an average wavelength-shift of 9 pm/V in reverse-bias conditions.

High accuracy digital aging monitor based on PLL-VCO circuit

NASA Astrophysics Data System (ADS)

Yuejun, Zhang; Zhidi, Jiang; Pengjun, Wang; Xuelong, Zhang

2015-01-01

As the manufacturing process is scaled down to the nanoscale, the aging phenomenon significantly affects the reliability and lifetime of integrated circuits. Consequently, the precise measurement of digital CMOS aging is a key aspect of nanoscale aging tolerant circuit design. This paper proposes a high accuracy digital aging monitor using phase-locked loop and voltage-controlled oscillator (PLL-VCO) circuit. The proposed monitor eliminates the circuit self-aging effect for the characteristic of PLL, whose frequency has no relationship with circuit aging phenomenon. The PLL-VCO monitor is implemented in TSMC low power 65 nm CMOS technology, and its area occupies 303.28 × 298.94 μm2. After accelerating aging tests, the experimental results show that PLL-VCO monitor improves accuracy about high temperature by 2.4% and high voltage by 18.7%.

Fill-factor improvement of Si CMOS single-photon avalanche diode detector arrays by integration of diffractive microlens arrays.

PubMed

Intermite, Giuseppe; McCarthy, Aongus; Warburton, Ryan E; Ren, Ximing; Villa, Federica; Lussana, Rudi; Waddie, Andrew J; Taghizadeh, Mohammad R; Tosi, Alberto; Zappa, Franco; Buller, Gerald S

2015-12-28

Single-photon avalanche diode (SPAD) detector arrays generally suffer from having a low fill-factor, in which the photo-sensitive area of each pixel is small compared to the overall area of the pixel. This paper describes the integration of different configurations of high efficiency diffractive optical microlens arrays onto a 32 × 32 SPAD array, fabricated using a 0.35 µm CMOS technology process. The characterization of SPAD arrays with integrated microlens arrays is reported over the spectral range of 500-900 nm, and a range of f-numbers from f/2 to f/22. We report an average concentration factor of 15 measured for the entire SPAD array with integrated microlens array. The integrated SPAD and microlens array demonstrated a very high uniformity in overall efficiency.

Automated translating beam profiler for in situ laser beam spot-size and focal position measurements

NASA Astrophysics Data System (ADS)

Keaveney, James

2018-03-01

We present a simple and convenient, high-resolution solution for automated laser-beam profiling with axial translation. The device is based on a Raspberry Pi computer, Pi Noir CMOS camera, stepper motor, and commercial translation stage. We also provide software to run the device. The CMOS sensor is sensitive over a large wavelength range between 300 and 1100 nm and can be translated over 25 mm along the beam axis. The sensor head can be reversed without changing its axial position, allowing for a quantitative estimate of beam overlap with counter-propagating laser beams. Although not limited to this application, the intended use for this device is the automated measurement of the focal position and spot-size of a Gaussian laser beam. We present example data of one such measurement to illustrate device performance.

Automated translating beam profiler for in situ laser beam spot-size and focal position measurements.

PubMed

Keaveney, James

2018-03-01

We present a simple and convenient, high-resolution solution for automated laser-beam profiling with axial translation. The device is based on a Raspberry Pi computer, Pi Noir CMOS camera, stepper motor, and commercial translation stage. We also provide software to run the device. The CMOS sensor is sensitive over a large wavelength range between 300 and 1100 nm and can be translated over 25 mm along the beam axis. The sensor head can be reversed without changing its axial position, allowing for a quantitative estimate of beam overlap with counter-propagating laser beams. Although not limited to this application, the intended use for this device is the automated measurement of the focal position and spot-size of a Gaussian laser beam. We present example data of one such measurement to illustrate device performance.

Analysis of multiple cell upset sensitivity in bulk CMOS SRAM after neutron irradiation

NASA Astrophysics Data System (ADS)

Pan, Xiaoyu; Guo, Hongxia; Luo, Yinhong; Zhang, Fengqi; Ding, Lili

2018-03-01

In our previous studies, we have proved that neutron irradiation can decrease the single event latch-up (SEL) sensitivity of CMOS SRAM. And one of the key contributions to the multiple cell upset (MCU) is the parasitic bipolar amplification, it bring us to study the impact of neutron irradiation on the SRAM’s MCU sensitivity. After the neutron experiment, we test the devices’ function and electrical parameters. Then, we use the heavy ion fluence to examine the changes on the devices’ MCU sensitivity pre- and post-neutron-irradiation. Unfortunately, neutron irradiation makes the MCU phenomenon worse. Finally, we use the electric static discharge (ESD) testing technology to deduce the experimental results and find that the changes on the WPM region take the lead rather than the changes on the parasitic bipolar amplification for the 90 nm process.

Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits

NASA Astrophysics Data System (ADS)

Strangio, S.; Palestri, P.; Lanuzza, M.; Esseni, D.; Crupi, F.; Selmi, L.

2017-02-01

In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against a conventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits, which are commonly identified as representative of the digital logic environment. 28T and 24T topologies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated. Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solution. The extracted delays and energy characteristics are post-processed and translated into figures-of-merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (for the same device technology platform) and to the different technology platforms (for the same full-adder topology) are presented and discussed.

Optimal and Local Connectivity Between Neuron and Synapse Array in the Quantum Dot/Silicon Brain

NASA Technical Reports Server (NTRS)

Duong, Tuan A.; Assad, Christopher; Thakoor, Anikumar P.

2010-01-01

This innovation is used to connect between synapse and neuron arrays using nanowire in quantum dot and metal in CMOS (complementary metal oxide semiconductor) technology to enable the density of a brain-like connection in hardware. The hardware implementation combines three technologies: 1. Quantum dot and nanowire-based compact synaptic cell (50x50 sq nm) with inherently low parasitic capacitance (hence, low dynamic power approx.l0(exp -11) watts/synapse), 2. Neuron and learning circuits implemented in 50-nm CMOS technology, to be integrated with quantum dot and nanowire synapse, and 3. 3D stacking approach to achieve the overall numbers of high density O(10(exp 12)) synapses and O(10(exp 8)) neurons in the overall system. In a 1-sq cm of quantum dot layer sitting on a 50-nm CMOS layer, innovators were able to pack a 10(exp 6)-neuron and 10(exp 10)-synapse array; however, the constraint for the connection scheme is that each neuron will receive a non-identical 10(exp 4)-synapse set, including itself, via its efficacy of the connection. This is not a fully connected system where the 100x100 synapse array only has a 100-input data bus and 100-output data bus. Due to the data bus sharing, it poses a great challenge to have a complete connected system, and its constraint within the quantum dot and silicon wafer layer. For an effective connection scheme, there are three conditions to be met: 1. Local connection. 2. The nanowire should be connected locally, not globally from which it helps to maximize the data flow by sharing the same wire space location. 3. Each synapse can have an alternate summation line if needed (this option is doable based on the simple mask creation). The 10(exp 3)x10(exp 3)-neuron array was partitioned into a 10-block, 10(exp 2)x10(exp 3)-neuron array. This building block can be completely mapped within itself (10,000 synapses to a neuron).

Southern Ocean Climate and Sea Ice Anomalies Associated with the Southern Oscillation

NASA Technical Reports Server (NTRS)

Kwok, R.; Comiso, J. C.

2001-01-01

The anomalies in the climate and sea ice cover of the Southern Ocean and their relationships with the Southern Oscillation (SO) are investigated using a 17-year of data set from 1982 through 1998. We correlate the polar climate anomalies with the Southern Oscillation index (SOI) and examine the composites of these anomalies under the positive (SOI > 0), neutral (0 > SOI > -1), and negative (SOI < -1) phases of SOL The climate data set consists of sea-level pressure, wind, surface air temperature, and sea surface temperature fields, while the sea ice data set describes its extent, concentration, motion, and surface temperature. The analysis depicts, for the first time, the spatial variability in the relationship of the above variables and the SOL The strongest correlation between the SOI and the polar climate anomalies are found in the Bellingshausen, Amundsen and Ross sea sectors. The composite fields reveal anomalies that are organized in distinct large-scale spatial patterns with opposing polarities at the two extremes of SOI, and suggest oscillating climate anomalies that are closely linked to the SO. Within these sectors, positive (negative) phases of the SOI are generally associated with lower (higher) sea-level pressure, cooler (warmer) surface air temperature, and cooler (warmer) sea surface temperature in these sectors. Associations between these climate anomalies and the behavior of the Antarctic sea ice cover are clearly evident. Recent anomalies in the sea ice cover that are apparently associated with the SOI include: the record decrease in the sea ice extent in the Bellingshausen Sea from mid- 1988 through early 199 1; the relationship between Ross Sea SST and ENSO signal, and reduced sea ice concentration in the Ross Sea; and, the shortening of the ice season in the eastern Ross Sea, Amundsen Sea, far western Weddell Sea, and the lengthening of the ice season in the western Ross Sea, Bellingshausen Sea and central Weddell Sea gyre over the period 1988-1994. Four ENSO episodes over the last 17 years contributed to a negative mean in the SOI (-0.5). In each of these episodes, significant retreats in the Bellingshausen/Amundsen Sea were observed providing direct confirmation of the impact of SO on the Antarctic sea ice cover.

Acute care surgery: defining mortality in emergency general surgery in the state of Maryland.

PubMed

Narayan, Mayur; Tesoriero, Ronald; Bruns, Brandon R; Klyushnenkova, Elena N; Chen, Hegang; Diaz, Jose J

2015-04-01

Emergency general surgery (EGS) is a major component of acute care surgery, however, limited data exist on mortality with respect to trauma center (TC) designation. We hypothesized that mortality would be lower for EGS patients treated at a TC vs non-TC (NTC). A retrospective review of the Maryland Health Services Cost Review Commission database from 2009 to 2013 was performed. The American Association for the Surgery of Trauma EGS ICD-9 codes were used to identify EGS patients. Data collected included demographics, TC designation, emergency department admissions, and All Patients Refined Severity of Illness (APR_SOI). Trauma center designation was used as a marker of a formal acute care surgery program. Primary outcomes included in-hospital mortality. Multivariable logistic regression analysis was performed controlling for age. There were 817,942 EGS encounters. Mean ± SD age of patients was 60.1 ± 18.7 years, 46.5% were males; 71.1% of encounters were at NTCs; and 75.8% were emergency department admissions. Overall mortality was 4.05%. Mortality was calculated based on TC designation controlling for age across APR_SOI strata. Multivariable logistic regression analysis did not show statistically significant differences in mortality between hospital levels for minor APR_SOI. For moderate APR_SOI, mortality was significantly lower for TCs compared with NTCs (p < 0.001). Among TCs, the effect was strongest for Level I TC (odds ratio = 0.34). For extreme APR_SOI, mortality was higher at TCs vs NTCs (p < 0.001). Emergency general surgery patients treated at TCs had lower mortality for moderate APR_SOI, but increased mortality for extreme APR_SOI when compared with NTCs. Additional investigation is required to better evaluate this unexpected finding. Copyright © 2015 American College of Surgeons. Published by Elsevier Inc. All rights reserved.

Spontaneous magnetic order in complex materials: Role of longitudinal spin-orbit interactions

NASA Astrophysics Data System (ADS)

Chakraborty, Subrata; Vijay, Amrendra

2017-06-01

We show that the longitudinal spin-orbit interactions (SOI) critically determine the fate of spontaneous magnetic order (SMO) in complex materials. To study the magnetic response of interacting electrons constituting the material, we implement an extension of the Hubbard model that faithfully accounts for the SOI. Next, we use the double-time Green functions of quantum statistical mechanics to obtain the spontaneous magnetization, Msp , and thence ascertain the possibility of SMO. For materials with quenched SOI, in an arbitrary dimension, Msp vanishes at finite temperatures, implying the presence of the disordered (paramagnetic) phase. This is consistent with and goes beyond the Bogolyubov's inequality based analysis in one and two dimensions. In the presence of longitudinal SOI, Msp , for materials in an arbitrary dimension, remains non-zero at finite temperatures, which indicates the existence of the ordered (ferromagnetic) phase. As a plausible experimental evidence of the present SOI-based phenomenology, we discuss, inter alia, a recent experimental study on Y4Mn1-xGa12-yGey, an intermetallic compound, which exhibits a magnetic phase transition (paramagnetic to ferromagnetic) upon tuning the fraction of Ge atoms and thence the vacancies of the magnetic centers in this system. The availability of Ge atoms to form a direct chemical bond with octahedral Mn in this material appears to quench the SOI and, as a consequence, favours the formation of the disordered (paramagnetic) phase.

Spin transport and accumulation in n{sup +}-Si using Heusler compound Co{sub 2}FeSi/MgO tunnel contacts

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ishikawa, Mizue, E-mail: mizue.ishikawa@toshiba.co.jp; Sugiyama, Hideyuki; Inokuchi, Tomoaki

2015-08-31

We investigate spin transport and accumulation in n{sup +}-Si using Heusler compound Co{sub 2}FeSi/MgO/Si on insulator (SOI) devices. The magnitudes of the non-local four- and three-terminal Hanle effect signals when using Heusler compound Co{sub 2}FeSi/MgO/SOI devices are larger than when using CoFe/MgO/SOI devices, whereas the preparation methods of MgO layers on SOI are exactly same in both devices. Different bias voltage dependencies on the magnitude of spin accumulation signals are also observed between these devices. Especially, Co{sub 2}FeSi/MgO/SOI devices show large spin accumulation signals compared with CoFe/MgO/SOI devices in the low bias voltage region less than ∼1000 mV in which themore » increase of the spin polarization is expected from the estimation of the density of states in Heusler compound Co{sub 2}FeSi and CoFe under spin extraction conditions. These results indicate that the species of ferromagnetic material definitely affects the magnitude and behavior of the spin signals. The use of highly polarized ferromagnets such as Heusler compounds would be important for improving the spin polarization and the magnitude of spin signals through Si channels.« less

FinFET and UTBB for RF SOI communication systems

NASA Astrophysics Data System (ADS)

Raskin, Jean-Pierre

2016-11-01

Performance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Thanks to the introduction of the trap-rich high-resistivity Silicon-on-Insulator (SOI) substrate on the market, the ICs requirements in term of linearity are fulfilled. Today partially depleted SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. In this paper, their analog/RF behavior is described and compared. Both show similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances.

Classical emergence of intrinsic spin-orbit interaction of light at the nanoscale

NASA Astrophysics Data System (ADS)

Vázquez-Lozano, J. Enrique; Martínez, Alejandro

2018-03-01

Traditionally, in macroscopic geometrical optics intrinsic polarization and spatial degrees of freedom of light can be treated independently. However, at the subwavelength scale these properties appear to be coupled together, giving rise to the spin-orbit interaction (SOI) of light. In this work we address theoretically the classical emergence of the optical SOI at the nanoscale. By means of a full-vector analysis involving spherical vector waves we show that the spin-orbit factorizability condition, accounting for the mutual influence between the amplitude (spin) and phase (orbit), is fulfilled only in the far-field limit. On the other side, in the near-field region, an additional relative phase introduces an extra term that hinders the factorization and reveals an intricate dynamical behavior according to the SOI regime. As a result, we find a suitable theoretical framework able to capture analytically the main features of intrinsic SOI of light. Besides allowing for a better understanding into the mechanism leading to its classical emergence at the nanoscale, our approach may be useful to design experimental setups that enhance the response of SOI-based effects.

El Niño Southern Oscillation (ENSO) and dysentery in Shandong province, China.

PubMed

Zhang, Ying; Bi, Peng; Wang, Guoyong; Hiller, Janet E

2007-01-01

To investigate the impact of the El Niño Southern Oscillation (ENSO) on dysentery transmission, the relationship between monthly dysentery cases in Shandong Province of China and the monthly Southern Oscillation Index (SOI), a broad index of ENSO, was examined over the period 1991-2003. Spearman correlations and generalized linear models were calculated to detect the association between the SOI and dysentery cases. Data from 1991 to 2001 were used to estimate the parameters, while data from 2002 to 2003 were used to test the forecasting ability of the model. After controlling for seasonality, autocorrelation, and a time-lagged effect, the results indicate that there was a significant negative association between the number of dysentery cases and the SOI, with a lagged effect of 2 months. A one-standard-deviation decrease in the SOI might cause up to 207 more dysentery cases per month in Shandong Province. This is the first report of the impact of the Southern Oscillation on dysentery risk in China, indicating that the SOI may be a useful early indicator of potential dysentery risk in Shandong Province.

Characterization of wafer-level bonded hermetic packages using optical leak detection

NASA Astrophysics Data System (ADS)

Duan, Ani; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

2009-07-01

For MEMS devices required to be operated in a hermetic environment, one of the main reliability issues is related to the packaging methods applied. In this paper, an optical method for testing low volume hermetic cavities formed by anodic bonding between glass and SOI (silicon on insulator) wafer is presented. Several different cavity-geometry structures have been designed, fabricated and applied to monitor the hermeticity of wafer level anodic bonding. SOI wafer was used as the cap wafer on which the different-geometry structures were fabricated using standard MEMS technology. The test cavities were bonded using SOI wafers to glass wafers at 400C and 1000mbar pressure inside a vacuum bonding chamber. The bonding voltage varies from 200V to 600V. The bonding strength between glass and SOI wafer was mechanically tested using shear tester. The deformation amplitudes of the cavity cap surface were monitored by using an optical interferometer. The hermeticity of the glass-to-SOI wafer level bonding was characterized through observing the surface deformation in a 6 months period in atmospheric environment. We have observed a relatively stable micro vacuum-cavity.

Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2010-01-01

Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Synchronous OEIC Integrating Receiver for Optically Reconfigurable Gate Arrays

PubMed Central

Sánchez-Azqueta, Carlos; Goll, Bernhard; Celma, Santiago; Zimmermann, Horst

2016-01-01

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of −26.0 dBm and −25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10−9 ) with an energy efficiency of 2 pJ/bit. PMID:27231915

Intra-cavity upconversion to 631 nm of images illuminated by an eye-safe ASE source at 1550 nm.

PubMed

Torregrosa, A J; Maestre, H; Capmany, J

2015-11-15

We report an image wavelength upconversion system. The system mixes an incoming image at around 1550 nm (eye-safe region) illuminated by an amplified spontaneous emission (ASE) fiber source with a Gaussian beam at 1064 nm generated in a continuous-wave diode-pumped Nd(3+):GdVO(4) laser. Mixing takes place in a periodically poled lithium niobate (PPLN) crystal placed intra-cavity. The upconverted image obtained by sum-frequency mixing falls around the 631 nm red spectral region, well within the spectral response of standard silicon focal plane array bi-dimensional sensors, commonly used in charge-coupled device (CCD) or complementary metal-oxide-semiconductor (CMOS) video cameras, and of most image intensifiers. The use of ASE illumination benefits from a noticeable increase in the field of view (FOV) that can be upconverted with regard to using coherent laser illumination. The upconverted power allows us to capture real-time video in a standard nonintensified CCD camera.

Silicon-based optoelectronics: Monolithic integration for WDM

NASA Astrophysics Data System (ADS)

Pearson, Matthew Richard T.

2000-10-01

This thesis details the development of enabling technologies required for inexpensive, monolithic integration of Si-based wavelength division multiplexing (WDM) components and photodetectors. The work involves the design and fabrication of arrayed waveguide grating demultiplexers in silicon-on-insulator (SOI), the development of advanced SiGe photodetectors capable of photodetection at 1.55 mum wavelengths, and the development of a low cost fabrication technique that enables the high volume production of Si-based photonic components. Arrayed waveguide grating (AWG) demultiplexers were designed and fabricated in SOI. The fabrication of AWGs in SOI has been reported in the literature, however there are a number of design issues specific to the SOI material system that can have a large effect on device performance and design, and have not been theoretically examined in earlier work. The SOI AWGs presented in this thesis are the smallest devices of this type reported, and they exhibit performance acceptable for commercial applications. The SiGe photodetectors reported in the literature exhibit extremely low responsivities at wavelengths near 1.55 mum. We present the first use of three dimensional growth modes to enhance the photoresponse of SiGe at 1.55 mum wavelengths. Metal semiconductor-metal (MSM) photodetectors were fabricated using this undulating quantum well structure, and demonstrate the highest responsivities yet reported for a SiGe-based photodetector at 1.55 mum. These detectors were monolithically integrated with low-loss SOI waveguides, enabling integration with nearly any Si-based passive WDM component. The pursuit of inexpensive Si-based photonic components also requires the development of new manufacturing techniques that are more suitable for high volume production. This thesis presents the development of a low cost fabrication technique based on the local oxidation of silicon (LOCOS), a standard processing technique used for Si integrated circuits. This process is developed for both SiGe and SOI waveguides, but is shown to be commercially suitable only for SOI waveguide devices. The technique allows nearly any Si microelectronics fabrication facility to begin manufacturing optical components with minimal change in processing equipment or techniques. These enabling technologies provide the critical elements for inexpensive, monolithic integration in a Si-based system.

Structural makeup, biopolymer conformation, and biodegradation characteristics of a newly developed super genotype of oats (CDC SO-I versus conventional varieties): a novel approach.

PubMed

Damiran, Daalkhaijav; Yu, Peiqiang

2010-02-24

Recently, a new "super" genotype of oats (CDC SO-I or SO-I) has been developed. The objectives of this study were to determine structural makeup (features) of oat grain in endosperm and pericarp regions and to reveal and identify differences in protein amide I and II and carbohydrate structural makeup (conformation) between SO-I and two conventional oats (CDC Dancer and Derby) grown in western Canada in 2006, using advanced synchrotron radiation based Fourier transform infrared microspectroscopy (SRFTIRM). The SRFTIRM experiments were conducted at National Synchrotron Light Sources, Brookhaven National Laboratory (NSLS, BNL, U.S. Department of Energy). From the results, it was observed that comparison between the new genotype oats and conventional oats showed (1) differences in basic chemical and protein subfraction profiles and energy values with the new SO-I oats containing lower lignin (21 g/kg of DM) and higher soluble crude protein (530 g/kg CP), crude fat (59 g/kg of DM), and energy values (TDN, 820 g/kg of DM; NE(L3x), 7.8 MJ/kg of DM); (2) significant differences in rumen biodegradation kinetics of dry matter, starch, and protein with the new SO-I oats containing lower EDDM (638 g/kg of DM) and higher EDCP (103 g/kg of DM); (3) significant differences in nutrient supply with highest truly absorbed rumen undegraded protein (ARUP, 23 g/kg of DM) and total metabolizable protein supply (MP, 81 g/kg of DM) from the new SO-I oats; and (4) significant differences in structural makeup in terms of protein amide I in the endosperm region (with amide I peak height from 0.13 to 0.22 IR absorbance unit) and cellulosic compounds to carbohydrate ratio in the pericarp region (ratio from 0.02 to 0.06). The results suggest that with the SRFTIRM technique, the structural makeup differences between the new genotype oats (SO-I) and two conventional oats (Dancer and Derby) could be revealed.

Structural Make-up, Biopolymer Conformation, and Biodegradation Characteristics of Newly Developed Super Genotype of Oats (CDC SO-I vs. Conventional Varieties): Novel Approach

DOE Office of Scientific and Technical Information (OSTI.GOV)

Damiran, D.; Yu, P

Recently, a new 'super' genotype of oats (CDC SO-I or SO-I) has been developed. The objectives of this study were to determine structural makeup (features) of oat grain in endosperm and pericarp regions and to reveal and identify differences in protein amide I and II and carbohydrate structural makeup (conformation) between SO-I and two conventional oats (CDC Dancer and Derby) grown in western Canada in 2006, using advanced synchrotron radiation based Fourier transform infrared microspectroscopy (SRFTIRM). The SRFTIRM experiments were conducted at National Synchrotron Light Sources, Brookhaven National Laboratory (NSLS, BNL, U.S. Department of Energy). From the results, it wasmore » observed that comparison between the new genotype oats and conventional oats showed (1) differences in basic chemical and protein subfraction profiles and energy values with the new SO-I oats containing lower lignin (21 g/kg of DM) and higher soluble crude protein (530 g/kg CP), crude fat (59 g/kg of DM), and energy values (TDN, 820 g/kg of DM; NE{sub L3x}, 7.8 MJ/kg of DM); (2) significant differences in rumen biodegradation kinetics of dry matter, starch, and protein with the new SO-I oats containing lower EDDM (638 g/kg of DM) and higher EDCP (103 g/kg of DM); (3) significant differences in nutrient supply with highest truly absorbed rumen undegraded protein (ARUP, 23 g/kg of DM) and total metabolizable protein supply (MP, 81 g/kg of DM) from the new SO-I oats; and (4) significant differences in structural makeup in terms of protein amide I in the endosperm region (with amide I peak height from 0.13 to 0.22 IR absorbance unit) and cellulosic compounds to carbohydrate ratio in the pericarp region (ratio from 0.02 to 0.06). The results suggest that with the SRFTIRM technique, the structural makeup differences between the new genotype oats (SO-I) and two conventional oats (Dancer and Derby) could be revealed.« less

Atmospheric aerosol measurements by employing a polarization scheimpflug lidar system

NASA Astrophysics Data System (ADS)

Mei, Liang; Guan, Peng; Yang, Yang

2018-04-01

A polarization Scheimpflug lidar system based on the Scheimpflug principle has been developed by employing a compact 808-nm multimode highpower laser diode and two highly integrated CMOS sensors in Dalian University of Technology (DLUT), Dalian, China. The parallel and orthogonal polarized backscattering signal are recorded by two 45 degree tilted image sensors, respectively. Atmospheric particle measurements were carried out by employing the polarization Scheimpflug lidar system.

SEMICONDUCTOR INTEGRATED CIRCUITS: A high performance 90 nm CMOS SAR ADC with hybrid architecture

NASA Astrophysics Data System (ADS)

Xingyuan, Tong; Jianming, Chen; Zhangming, Zhu; Yintang, Yang

2010-01-01

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shifters are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlin-earity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238 × 214 μm2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.

Impact of time-dependent annealing on TiO2 films for CMOS application

NASA Astrophysics Data System (ADS)

Gyanan, Mondal, Sandip; Kumar, Arvind

2017-05-01

Post-deposition annealing (PDA) is the inherent part of sol-gel fabrication process to achieve the optimum device performance, especially in CMOS applications. The annealing removes the oxygen vacancies and improves the structural order of dielectric films. The process also reduces the interface related defects and improves the interfacial properties. In this work, we have integrated the sol-gel spin-coating deposited high-κ TiO2 films in MOS. The films are fired at 400°C for the duration of 20, 40, 60 and 80 min. The thicknesses of the films were found to be of ˜ 30 nm using ellipsometry. The (Al/TiO2/p-Si) devices were examined with current-voltage (I-V) and capacitance-voltage (C-V) at room temperature to understand the influence of firing time. The C-V and I-V characteristic showed a significant dependence on annealing time such as variation in dielectric constant and leakage current. The accumulation capacitance (Cox), dielectric constant (κ) and the equivalent oxide thickness (EOT) of the film fired for 60 min were found to be 458 pF, 33, and 4.25nm, respectively with a low leakage current density (1.09 × 10-6 A/cm2) fired for 80 min at +1 V.

Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology.

PubMed

Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

2015-07-22

This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode's current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm(2) of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA.

A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment

NASA Astrophysics Data System (ADS)

Stefan Devlin, Benjamin; Nakura, Toru; Ikeda, Makoto; Asada, Kunihiro

We detail a self synchronous field programmable gate array (SSFPGA) with dual-pipeline (DP) architecture to conceal pre-charge time for dynamic logic, and its throughput optimization by using pipeline alignment implemented on benchmark circuits. A self synchronous LUT (SSLUT) consists of a three input tree-type structure with 8bits of SRAM for programming. A self synchronous switch box (SSSB) consists of both pass transistors and buffers to route signals, with 12bits of SRAM. One common block with one SSLUT and one SSSB occupies 2.2Mλ2 area with 35bits of SRAM, and the prototype SSFPGA with 34 × 30 (1020) blocks is designed and fabricated using 65nm CMOS. Measured results show at 1.2V 430MHz and 647MHz operation for a 3bit ripple carry adder, without and with throughput optimization, respectively. We find that using the proposed pipeline alignment techniques we can perform at maximum throughput of 647MHz in various benchmarks on the SSFPGA. We demonstrate up to 56.1 times throughput improvement with our pipeline alignment techniques. The pipeline alignment is carried out within the number of logic elements in the array and pipeline buffers in the switching matrix.

A 65nm CMOS low-power MedRadio-band integer-N cascaded phase-locked loop for implantable medical systems.

PubMed

Wang, Yi-Xiao; Chen, Wei-Ming; Wu, Chung-Yu

2014-01-01

This paper presents a low-power MedRadio-band integer-N phase-locked Loop (PLL) system which is composed of two charge-pump PLLs cascade connected. The PLL provides the operation clock and local carrier signals for an implantable medical electronic system. In addition, to avoid the off-chip crystal oscillator, the 13.56 MHz Industrial, Scientific and Medical (ISM) band signal from the wireless power transmission system is adopted as the input reference signal for the PLL. Ring-based voltage controlled oscillators (VCOs) with current control units are adopted to reduce chip area and power dissipation. The proposed cascaded PLL system is designed and implemented in TSMC 65-nm CMOS technology. The measured jitter for 216.96 MHz signal is 12.23 ps and the phase noise is -65.9 dBc/Hz at 100 kHz frequency offset under 402.926 MHz carrier frequency. The measured power dissipations are 66 μW in the first PLL and 195 μW in the whole system under 1-V supply voltage. The chip area is 0.1088 mm(2) and no off-chip component is required which is suitable for the integration of the implantable medical electronic system.

An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

NASA Astrophysics Data System (ADS)

Yanbin, Luo; Chengyan, Ma; Yebing, Gan; Min, Qian; Tianchun, Ye

2015-10-01

An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2.

Thin-Film Quantum Dot Photodiode for Monolithic Infrared Image Sensors †

PubMed Central

Georgitzikis, Epimitheas; Vamvaka, Ioanna; Frazzica, Fortunato; Van Olmen, Jan; De Moor, Piet; Heremans, Paul; Hens, Zeger; Cheyns, David

2017-01-01

Imaging in the infrared wavelength range has been fundamental in scientific, military and surveillance applications. Currently, it is a crucial enabler of new industries such as autonomous mobility (for obstacle detection), augmented reality (for eye tracking) and biometrics. Ubiquitous deployment of infrared cameras (on a scale similar to visible cameras) is however prevented by high manufacturing cost and low resolution related to the need of using image sensors based on flip-chip hybridization. One way to enable monolithic integration is by replacing expensive, small-scale III–V-based detector chips with narrow bandgap thin-films compatible with 8- and 12-inch full-wafer processing. This work describes a CMOS-compatible pixel stack based on lead sulfide quantum dots (PbS QD) with tunable absorption peak. Photodiode with a 150-nm thick absorber in an inverted architecture shows dark current of 10−6 A/cm2 at −2 V reverse bias and EQE above 20% at 1440 nm wavelength. Optical modeling for top illumination architecture can improve the contact transparency to 70%. Additional cooling (193 K) can improve the sensitivity to 60 dB. This stack can be integrated on a CMOS ROIC, enabling order-of-magnitude cost reduction for infrared sensors. PMID:29232871

Fabrication of Total-Dose-Radiation-Hardened (TDRH) SOI wafer with embedded silicon nanoclusters

NASA Astrophysics Data System (ADS)

Wu, Aimin; Wang, Xi; Wei, Xing; Chen, Jing; Chen, Ming; Zhang, Zhengxuan

2009-05-01

Si ion-implantation and post annealing of silicon wafers prior to wafer bonding were used to radiation-harden the thermal oxide layer of Silicon on Insulator structures. After grinding and polishing, Total-Dose-Radiation-Hardened SOI (TDRH-SOI) wafers with several-micron-thick device layers were prepared. Electrical characterization before and after X-ray irradiation showed that the flatband voltage shift induced by irradiation was reduced by this preprocessing. Photoluminescence Spectroscopy (PL), Transmission Electron Microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) results indicated that the improvement of the total dose response of the TDRH-SOI wafer was associated with formation of Si nanoclusters in the implanted oxide layer, suggesting that these were the likely candidates for electron and proton trapping centers that reduce the positive charge buildup effect in the buried oxide.

Spacecraft Onboard Interface Services: Current Status and Roadmap

NASA Astrophysics Data System (ADS)

Prochazka, Marek; Lopez Trescastro, Jorge; Krueger, Sabine

2016-08-01

Spacecraft Onboard Interface Services (SOIS) is a set of CCSDS standards defining communication stack services to interact with hardware equipment onboard spacecraft. In 2014 ESA kicked off three parallel activities to critically review the SOIS standards, use legacy spacecraft flight software (FSW), make it compliant to a preselected subset of SOIS standards and make performance and architecture assessment. As a part of the three parallel activities, led by Airbus DS Toulouse, OHB Bremen and Thales Alenia Space Cannes respectively, it was to provide feedback back to ESA and CCSDS and also to propose a roadmap of transition towards an operational FSW system fully compliant to applicable SOIS standards. The objective of the paper is twofold: Firstly it is to summarise main results of the three parallel activities and secondly, based on the results, to propose a roadmap for the future.

A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

NASA Astrophysics Data System (ADS)

Priya, Anjali; Mishra, Ram Awadh

2016-04-01

In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.