On the origin of resistive switching volatility in Ni/TiO{sub 2}/Ni stacks

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cortese, Simone, E-mail: simone.cortese@soton.ac.uk; Trapatseli, Maria; Khiat, Ali

2016-08-14

Resistive switching and resistive random access memories have attracted huge interest for next generation nonvolatile memory applications, also thought to be able to overcome flash memories limitations when arranged in crossbar arrays. A cornerstone of their potential success is that the toggling between two distinct resistance states, usually a High Resistive State (HRS) and a Low Resistive State (LRS), is an intrinsic non-volatile phenomenon with the two states being thermodynamically stable. TiO{sub 2} is one of the most common materials known to support non-volatile RS. In this paper, we report a volatile resistive switching in a titanium dioxide thin filmmore » sandwiched by two nickel electrodes. The aim of this work is to understand the underlying physical mechanism that triggers the volatile effect, which is ascribed to the presence of a NiO layer at the bottom interface. The NiO layer alters the equilibrium between electric field driven filament formation and thermal enhanced ion diffusion, resulting in the volatile behaviour. Although the volatility is not ideal for non-volatile memory applications, it shows merit for access devices in crossbar arrays due to its high LRS/HRS ratio, which are also briefly discussed.« less

Investigation of Hafnium oxide/Copper resistive memory for advanced encryption applications

NASA Astrophysics Data System (ADS)

Briggs, Benjamin D.

The Advanced Encryption Standard (AES) is a widely used encryption algorithm to protect data and communications in today's digital age. Modern AES CMOS implementations require large amounts of dedicated logic and must be tuned for either performance or power consumption. A high throughput, low power, and low die area AES implementation is required in the growing mobile sector. An emerging non-volatile memory device known as resistive memory (ReRAM) is a simple metal-insulator-metal capacitor device structure with the ability to switch between two stable resistance states. Currently, ReRAM is targeted as a non-volatile memory replacement technology to eventually replace flash. Its advantages over flash include ease of fabrication, speed, and lower power consumption. In addition to memory, ReRAM can also be used in advanced logic implementations given its purely resistive behavior. The combination of a new non-volatile memory element ReRAM along with high performance, low power CMOS opens new avenues for logic implementations. This dissertation will cover the design and process implementation of a ReRAM-CMOS hybrid circuit, built using IBM's 10LPe process, for the improvement of hardware AES implementations. Further the device characteristics of ReRAM, specifically the HfO2/Cu memory system, and mechanisms for operation are not fully correlated. Of particular interest to this work is the role of material properties such as the stoichiometry, crystallinity, and doping of the HfO2 layer and their effect on the switching characteristics of resistive memory. Material properties were varied by a combination of atomic layer deposition and reactive sputtering of the HfO2 layer. Several studies will be discussed on how the above mentioned material properties influence switching parameters, and change the underlying physics of device operation.

Giant Electroresistance in Edge Metal-Insulator-Metal Tunnel Junctions Induced by Ferroelectric Fringe Fields

PubMed Central

Jung, Sungchul; Jeon, Youngeun; Jin, Hanbyul; Lee, Jung-Yong; Ko, Jae-Hyeon; Kim, Nam; Eom, Daejin; Park, Kibog

2016-01-01

An enormous amount of research activities has been devoted to developing new types of non-volatile memory devices as the potential replacements of current flash memory devices. Theoretical device modeling was performed to demonstrate that a huge change of tunnel resistance in an Edge Metal-Insulator-Metal (EMIM) junction of metal crossbar structure can be induced by the modulation of electric fringe field, associated with the polarization reversal of an underlying ferroelectric layer. It is demonstrated that single three-terminal EMIM/Ferroelectric structure could form an active memory cell without any additional selection devices. This new structure can open up a way of fabricating all-thin-film-based, high-density, high-speed, and low-power non-volatile memory devices that are stackable to realize 3D memory architecture. PMID:27476475

Two-dimensional molybdenum disulphide nanosheet-covered metal nanoparticle array as a floating gate in multi-functional flash memories

NASA Astrophysics Data System (ADS)

Han, Su-Ting; Zhou, Ye; Chen, Bo; Zhou, Li; Yan, Yan; Zhang, Hua; Roy, V. A. L.

2015-10-01

Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure.Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure. Electronic supplementary information (ESI) available: Energy-dispersive X-ray spectroscopy (EDS) spectra of the metal NPs, SEM image of MoS2 on Au NPs, erasing operations of the metal NPs-MoS2 memory device, transfer characteristics of the standard FET devices and Ag NP devices under programming operation, tapping-mode AFM height image of the fabricated MoS2 film for pristine MoS2 flash memory, gate signals used for programming the Au NPs-MoS2 and Pt NPs-MoS2 flash memories, and data levels recorded for 100 sequential cycles. See DOI: 10.1039/c5nr05054e

A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

NASA Astrophysics Data System (ADS)

Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

2016-06-01

The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

Review of radiation effects on ReRAM devices and technology

NASA Astrophysics Data System (ADS)

Gonzalez-Velo, Yago; Barnaby, Hugh J.; Kozicki, Michael N.

2017-08-01

A review of the ionizing radiation effects on resistive random access memory (ReRAM) technology and devices is presented in this article. The review focuses on vertical devices exhibiting bipolar resistance switching, devices that have already exhibited interesting properties and characteristics for memory applications and, in particular, for non-volatile memory applications. Non-volatile memories are important devices for any type of electronic and embedded system, as they are for space applications. In such applications, specific environmental issues related to the existence of cosmic rays and Van Allen radiation belts around the Earth contribute to specific failure mechanisms related to the energy deposition induced by such ionizing radiation. Such effects are important in non-volatile memory as the current leading technology, i.e. flash-based technology, is sensitive to the total ionizing dose (TID) and single-event effects. New technologies such as ReRAM, if competing with or complementing the existing non-volatile area of memories from the point of view of performance, also have to exhibit great reliability for use in radiation environments such as space. This has driven research on the radiation effects of such ReRAM technology, on both the conductive-bridge RAM as well as the valence-change memories, or OxRAM variants of the technology. Initial characterizations of ReRAM technology showed a high degree of resilience to TID, developing researchers’ interest in characterizing such resilience as well as investigating the cause of such behavior. The state of the art of such research is reviewed in this article.

Inadvertently programmed bits in Samsung 128 Mbit flash devices: a flaky investigation

NASA Technical Reports Server (NTRS)

Swift, G.

2002-01-01

JPL's X2000 avionics design pioneers new territory by specifying a non-volatile memory (NVM) board based on flash memories. The Samsung 128Mb device chosen was found to demonstrate bit errors (mostly program disturbs) and block-erase failures that increase with cycling. Low temperature, certain pseudo- random patterns, and, probably, higher bias increase the observable bit errors. An experiment was conducted to determine the wearout dependence of the bit errors to 100k cycles at cold temperature using flight-lot devices (some pre-irradiated). The results show an exponential growth rate, a wide part-to-part variation, and some annealing behavior.

GaAs metal-oxide-semiconductor based non-volatile flash memory devices with InAs quantum dots as charge storage nodes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Islam, Sk Masiul, E-mail: masiulelt@gmail.com; Chowdhury, Sisir; Sarkar, Krishnendu

2015-06-24

Ultra-thin InP passivated GaAs metal-oxide-semiconductor based non-volatile flash memory devices were fabricated using InAs quantum dots (QDs) as charge storing elements by metal organic chemical vapor deposition technique to study the efficacy of the QDs as charge storage elements. The grown QDs were embedded between two high-k dielectric such as HfO{sub 2} and ZrO{sub 2}, which were used for tunneling and control oxide layers, respectively. The size and density of the QDs were found to be 5 nm and 1.8×10{sup 11} cm{sup −2}, respectively. The device with a structure Metal/ZrO{sub 2}/InAs QDs/HfO{sub 2}/GaAs/Metal shows maximum memory window equivalent to 6.87 V. Themore » device also exhibits low leakage current density of the order of 10{sup −6} A/cm{sup 2} and reasonably good charge retention characteristics. The low value of leakage current in the fabricated memory device is attributed to the Coulomb blockade effect influenced by quantum confinement as well as reduction of interface trap states by ultra-thin InP passivation on GaAs prior to HfO{sub 2} deposition.« less

PIYAS-proceeding to intelligent service oriented memory allocation for flash based data centric sensor devices in wireless sensor networks.

PubMed

Rizvi, Sanam Shahla; Chung, Tae-Sun

2010-01-01

Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS). This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks.

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Cohn, Lewis M.

2008-01-01

At GOMAC 2007, we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art memory technologies. This included FLASH non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs). In this presentation, we extend this discussion in device packaging and complexity as well as single event upset (SEU) mechanisms using several technology areas as examples including: system-on-a-chip (SOC) devices and photonic or fiber optic systems. The underlying goal is intended to provoke thought for understanding the limitations and interpretation of radiation testing results.

Design and fabrication of memory devices based on nanoscale polyoxometalate clusters

NASA Astrophysics Data System (ADS)

Busche, Christoph; Vilà-Nadal, Laia; Yan, Jun; Miras, Haralampos N.; Long, De-Liang; Georgiev, Vihar P.; Asenov, Asen; Pedersen, Rasmus H.; Gadegaard, Nikolaj; Mirza, Muhammad M.; Paul, Douglas J.; Poblet, Josep M.; Cronin, Leroy

2014-11-01

Flash memory devices--that is, non-volatile computer storage media that can be electrically erased and reprogrammed--are vital for portable electronics, but the scaling down of metal-oxide-semiconductor (MOS) flash memory to sizes of below ten nanometres per data cell presents challenges. Molecules have been proposed to replace MOS flash memory, but they suffer from low electrical conductivity, high resistance, low device yield, and finite thermal stability, limiting their integration into current MOS technologies. Although great advances have been made in the pursuit of molecule-based flash memory, there are a number of significant barriers to the realization of devices using conventional MOS technologies. Here we show that core-shell polyoxometalate (POM) molecules can act as candidate storage nodes for MOS flash memory. Realistic, industry-standard device simulations validate our approach at the nanometre scale, where the device performance is determined mainly by the number of molecules in the storage media and not by their position. To exploit the nature of the core-shell POM clusters, we show, at both the molecular and device level, that embedding [(Se(IV)O3)2]4- as an oxidizable dopant in the cluster core allows the oxidation of the molecule to a [Se(V)2O6]2- moiety containing a {Se(V)-Se(V)} bond (where curly brackets indicate a moiety, not a molecule) and reveals a new 5+ oxidation state for selenium. This new oxidation state can be observed at the device level, resulting in a new type of memory, which we call `write-once-erase'. Taken together, these results show that POMs have the potential to be used as a realistic nanoscale flash memory. Also, the configuration of the doped POM core may lead to new types of electrical behaviour. This work suggests a route to the practical integration of configurable molecules in MOS technologies as the lithographic scales approach the molecular limit.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

NASA Astrophysics Data System (ADS)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG in the form of PVD TaN was investigated along with high-k blocking dielectric. The material properties of TaN metal and high-k / low-k dielectric engineering were systematically studied. And the resulting memory structures exhibit excellent memory characteristics and scalability of the metal FG down to ˜1nm, which is promising in order to reduce the unwanted FG-FG interferences. In the later part of the study, the thermal stability of the combined stack was examined and various approaches to improve the stability and understand the cause of instability were explored. The performance of the high-k IPD metal FG memory structure was observed to degrade with higher annealing conditions and the deteriorated behavior was attributed to the leakage instability of the high-k /TaN capacitor. While the degradation is pronounced in both MIM and MIS capacitors, a higher leakage increment was seen in MIM, which was attributed to the higher degree of dielectric crystallization. In an attempt to improve the thermal stability, the trade-off in using amorphous interlayers to reduce the enhanced dielectric crystallization on metal was highlighted. Also, the effect of oxygen vacancies and grain growth on the dielectric leakage was studied through a multi-deposition-multi-anneal technique. Multi step deposition and annealing in a more electronegative ambient was observed to have a positive impact on the dielectric performance.

Don’t make cache too complex: A simple probability-based cache management scheme for SSDs

PubMed Central

Cho, Sangyeun; Choi, Jongmoo

2017-01-01

Solid-state drives (SSDs) have recently become a common storage component in computer systems, and they are fueled by continued bit cost reductions achieved with smaller feature sizes and multiple-level cell technologies. However, as the flash memory stores more bits per cell, the performance and reliability of the flash memory degrade substantially. To solve this problem, a fast non-volatile memory (NVM-)based cache has been employed within SSDs to reduce the long latency required to write data. Absorbing small writes in a fast NVM cache can also reduce the number of flash memory erase operations. To maximize the benefits of an NVM cache, it is important to increase the NVM cache utilization. In this paper, we propose and study ProCache, a simple NVM cache management scheme, that makes cache-entrance decisions based on random probability testing. Our scheme is motivated by the observation that frequently written hot data will eventually enter the cache with a high probability, and that infrequently accessed cold data will not enter the cache easily. Owing to its simplicity, ProCache is easy to implement at a substantially smaller cost than similar previously studied techniques. We evaluate ProCache and conclude that it achieves comparable performance compared to a more complex reference counter-based cache-management scheme. PMID:28358897

Don't make cache too complex: A simple probability-based cache management scheme for SSDs.

PubMed

Baek, Seungjae; Cho, Sangyeun; Choi, Jongmoo

2017-01-01

Solid-state drives (SSDs) have recently become a common storage component in computer systems, and they are fueled by continued bit cost reductions achieved with smaller feature sizes and multiple-level cell technologies. However, as the flash memory stores more bits per cell, the performance and reliability of the flash memory degrade substantially. To solve this problem, a fast non-volatile memory (NVM-)based cache has been employed within SSDs to reduce the long latency required to write data. Absorbing small writes in a fast NVM cache can also reduce the number of flash memory erase operations. To maximize the benefits of an NVM cache, it is important to increase the NVM cache utilization. In this paper, we propose and study ProCache, a simple NVM cache management scheme, that makes cache-entrance decisions based on random probability testing. Our scheme is motivated by the observation that frequently written hot data will eventually enter the cache with a high probability, and that infrequently accessed cold data will not enter the cache easily. Owing to its simplicity, ProCache is easy to implement at a substantially smaller cost than similar previously studied techniques. We evaluate ProCache and conclude that it achieves comparable performance compared to a more complex reference counter-based cache-management scheme.

Foundry Technologies Focused on Environmental and Ecological Applications

NASA Astrophysics Data System (ADS)

Roizin, Ya.; Lisiansky, M.; Pikhay, E.

Solutions allowing fabrication of remote control systems with integrated sensors (motes) were introduced as a part of CMOS foundry production platform and verified on silicon. The integrated features include sensors employing principles previously verified in the development of ultra-low power consuming non-volatile memories (C-Flash, MRAM) and components allowing low-power energy harvesting (low voltage rectifiers, high -voltage solar cells). The developed systems are discussed with emphasis on their environmental and security applications.

Phase-change materials for non-volatile memory devices: from technological challenges to materials science issues

NASA Astrophysics Data System (ADS)

Noé, Pierre; Vallée, Christophe; Hippert, Françoise; Fillot, Frédéric; Raty, Jean-Yves

2018-01-01

Chalcogenide phase-change materials (PCMs), such as Ge-Sb-Te alloys, have shown outstanding properties, which has led to their successful use for a long time in optical memories (DVDs) and, recently, in non-volatile resistive memories. The latter, known as PCM memories or phase-change random access memories (PCRAMs), are the most promising candidates among emerging non-volatile memory (NVM) technologies to replace the current FLASH memories at CMOS technology nodes under 28 nm. Chalcogenide PCMs exhibit fast and reversible phase transformations between crystalline and amorphous states with very different transport and optical properties leading to a unique set of features for PCRAMs, such as fast programming, good cyclability, high scalability, multi-level storage capability, and good data retention. Nevertheless, PCM memory technology has to overcome several challenges to definitively invade the NVM market. In this review paper, we examine the main technological challenges that PCM memory technology must face and we illustrate how new memory architecture, innovative deposition methods, and PCM composition optimization can contribute to further improvements of this technology. In particular, we examine how to lower the programming currents and increase data retention. Scaling down PCM memories for large-scale integration means the incorporation of the PCM into more and more confined structures and raises materials science issues in order to understand interface and size effects on crystallization. Other materials science issues are related to the stability and ageing of the amorphous state of PCMs. The stability of the amorphous phase, which determines data retention in memory devices, can be increased by doping the PCM. Ageing of the amorphous phase leads to a large increase of the resistivity with time (resistance drift), which has up to now hindered the development of ultra-high multi-level storage devices. A review of the current understanding of all these issues is provided from a materials science point of view.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vanheusden, K.; Warren, W.L.; Devine, R.A.B.

It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protonsmore » are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).« less

Giant tunnelling electroresistance in metal/ferroelectric/semiconductor tunnel junctions by engineering the Schottky barrier

PubMed Central

Xi, Zhongnan; Ruan, Jieji; Li, Chen; Zheng, Chunyan; Wen, Zheng; Dai, Jiyan; Li, Aidong; Wu, Di

2017-01-01

Recently, ferroelectric tunnel junctions have attracted much attention due to their potential applications in non-destructive readout non-volatile memories. Using a semiconductor electrode has been proven effective to enhance the tunnelling electroresistance in ferroelectric tunnel junctions. Here we report a systematic investigation on electroresistance of Pt/BaTiO3/Nb:SrTiO3 metal/ferroelectric/semiconductor tunnel junctions by engineering the Schottky barrier on Nb:SrTiO3 surface via varying BaTiO3 thickness and Nb doping concentration. The optimum ON/OFF ratio as great as 6.0 × 106, comparable to that of commercial Flash memories, is achieved in a device with 0.1 wt% Nb concentration and a 4-unit-cell-thick BaTiO3 barrier. With this thinnest BaTiO3 barrier, which shows a negligible resistance to the tunnelling current but is still ferroelectric, the device is reduced to a polarization-modulated metal/semiconductor Schottky junction that exhibits a more efficient control on the tunnelling resistance to produce the giant electroresistance observed. These results may facilitate the design of high performance non-volatile resistive memories. PMID:28513590

Giant tunnelling electroresistance in metal/ferroelectric/semiconductor tunnel junctions by engineering the Schottky barrier

NASA Astrophysics Data System (ADS)

Xi, Zhongnan; Ruan, Jieji; Li, Chen; Zheng, Chunyan; Wen, Zheng; Dai, Jiyan; Li, Aidong; Wu, Di

2017-05-01

Recently, ferroelectric tunnel junctions have attracted much attention due to their potential applications in non-destructive readout non-volatile memories. Using a semiconductor electrode has been proven effective to enhance the tunnelling electroresistance in ferroelectric tunnel junctions. Here we report a systematic investigation on electroresistance of Pt/BaTiO3/Nb:SrTiO3 metal/ferroelectric/semiconductor tunnel junctions by engineering the Schottky barrier on Nb:SrTiO3 surface via varying BaTiO3 thickness and Nb doping concentration. The optimum ON/OFF ratio as great as 6.0 × 106, comparable to that of commercial Flash memories, is achieved in a device with 0.1 wt% Nb concentration and a 4-unit-cell-thick BaTiO3 barrier. With this thinnest BaTiO3 barrier, which shows a negligible resistance to the tunnelling current but is still ferroelectric, the device is reduced to a polarization-modulated metal/semiconductor Schottky junction that exhibits a more efficient control on the tunnelling resistance to produce the giant electroresistance observed. These results may facilitate the design of high performance non-volatile resistive memories.

A Radiation-Tolerant, Low-Power Non-Volatile Memory Based on Silicon Nanocrystal Quantum Dots

NASA Technical Reports Server (NTRS)

Bell, L. D.; Boer, E. A.; Ostraat, M. L.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; deBlauwe, J.; Green, M. L.

2001-01-01

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO2 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled in program/erase threshold voltage swing was seen during 100,000 program and erase cycles. Additional near-term goals for this project include extensive testing for radiation hardness and the development of artificial layered tunnel barrier heterostructures which have the potential for large speed enhancements for read/write of nanocrystal memory elements, compared with conventional flash devices. Additional information is contained in the original extended abstract.

Evaluating Non-In-Place Update Techniques for Flash-Based Transaction Processing Systems

NASA Astrophysics Data System (ADS)

Wang, Yongkun; Goda, Kazuo; Kitsuregawa, Masaru

Recently, flash memory is emerging as the storage device. With price sliding fast, the cost per capacity is approaching to that of SATA disk drives. So far flash memory has been widely deployed in consumer electronics even partly in mobile computing environments. For enterprise systems, the deployment has been studied by many researchers and developers. In terms of the access performance characteristics, flash memory is quite different from disk drives. Without the mechanical components, flash memory has very high random read performance, whereas it has a limited random write performance because of the erase-before-write design. The random write performance of flash memory is comparable with or even worse than that of disk drives. Due to such a performance asymmetry, naive deployment to enterprise systems may not exploit the potential performance of flash memory at full blast. This paper studies the effectiveness of using non-in-place-update (NIPU) techniques through the IO path of flash-based transaction processing systems. Our deliberate experiments using both open-source DBMS and commercial DBMS validated the potential benefits; x3.0 to x6.6 performance improvement was confirmed by incorporating non-in-place-update techniques into file system without any modification of applications or storage devices.

Towards Terabit Memories

NASA Astrophysics Data System (ADS)

Hoefflinger, Bernd

Memories have been the major yardstick for the continuing validity of Moore's law. In single-transistor-per-Bit dynamic random-access memories (DRAM), the number of bits per chip pretty much gives us the number of transistors. For decades, DRAM's have offered the largest storage capacity per chip. However, DRAM does not scale any longer, both in density and voltage, severely limiting its power efficiency to 10 fJ/b. A differential DRAM would gain four-times in density and eight-times in energy. Static CMOS RAM (SRAM) with its six transistors/cell is gaining in reputation because it scales well in cell size and operating voltage so that its fundamental advantage of speed, non-destructive read-out and low-power standby could lead to just 2.5 electrons/bit in standby and to a dynamic power efficiency of 2aJ/b. With a projected 2020 density of 16 Gb/cm², the SRAM would be as dense as normal DRAM and vastly better in power efficiency, which would mean a major change in the architecture and market scenario for DRAM versus SRAM. Non-volatile Flash memory have seen two quantum jumps in density well beyond the roadmap: Multi-Bit storage per transistor and high-density TSV (through-silicon via) technology. The number of electrons required per Bit on the storage gate has been reduced since their first realization in 1996 by more than an order of magnitude to 400 electrons/Bit in 2010 for a complexity of 32Gbit per chip at the 32 nm node. Chip stacking of eight chips with TSV has produced a 32GByte solid-state drive (SSD). A stack of 32 chips with 2 b/cell at the 16 nm node will reach a density of 2.5 Terabit/cm². Non-volatile memory with a density of 10 × 10 nm²/Bit is the target for widespread development. Phase-change memory (PCM) and resistive memory (RRAM) lead in cell density, and they will reach 20 Gb/cm² in 2D and higher with 3D chip stacking. This is still almost an order-of-magnitude less than Flash. However, their read-out speed is ~10-times faster, with as yet little data on their energy/b. As a read-out memory with unparalleled retention and lifetime, the ROM with electron-beam direct-write-lithography (Chap. 8) should be considered for its projected 2D density of 250 Gb/cm², a very small read energy of 0.1 μW/Gb/s. The lithography write-speed 10 ms/Terabit makes this ROM a serious contentender for the optimum in non-volatile, tamper-proof storage.

Data Movement Dominates: Final Report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jacob, Bruce L.

Over the past three years in this project, what we have observed is that the primary reason for data movement in large-scale systems is that the per-node capacity is not large enough—i.e., one of the solutions to the data-movement problem (certainly not the only solution that is required, but a significant one nonetheless) is to increase per-node capacity so that inter-node traffic is reduced. This unfortunately is not as simple as it sounds. Today’s main memory systems for datacenters, enterprise computing systems, and supercomputers, fail to provide high per-socket capacity [Dirik & Jacob 2009; Cooper-Balis et al. 2012], except atmore » extremely high price points (factors of 10–100x the cost/bit of consumer main-memory systems) [Stokes 2008]. The reason is that our choice of technology for today’s main memory systems—i.e., DRAM, which we have used as a main-memory technology since the 1970s [Jacob et al. 2007]—can no longer keep up with our needs for density and price per bit. Main memory systems have always been built from the cheapest, densest, lowest-power memory technology available, and DRAM is no longer the cheapest, the densest, nor the lowest-power storage technology out there. It is now time for DRAM to go the way that SRAM went: move out of the way for a cheaper, slower, denser storage technology, and become a cache instead. This inflection point has happened before, in the context of SRAM yielding to DRAM. There was once a time that SRAM was the storage technology of choice for all main memories [Tomasulo 1967; Thornton 1970; Kidder 1981]. However, once DRAM hit volume production in the 1970s and 80s, it supplanted SRAM as a main memory technology because it was cheaper, and it was denser. It also happened to be lower power, but that was not the primary consideration of the day. At the time, it was recognized that DRAM was much slower than SRAM, but it was only at the supercomputer level (For instance the Cray X-MP in the 1980s and its follow-on, the Cray Y-MP, in the 1990s) that could one afford to build ever- larger main memories out of SRAM—the reasoning for moving to DRAM was that an appropriately designed memory hierarchy, built of DRAM as main memory and SRAM as a cache, would approach the performance of SRAM, at the price-per-bit of DRAM [Mashey 1999]. Today it is quite clear that, were one to build an entire multi-gigabyte main memory out of SRAM instead of DRAM, one could improve the performance of almost any computer system by up to an order of magnitude—but this option is not even considered, because to build that system would be prohibitively expensive. It is now time to revisit the same design choice in the context of modern technologies and modern systems. For reasons both technical and economic, we can no longer afford to build ever-larger main memory systems out of DRAM. Flash memory, on the other hand, is significantly cheaper and denser than DRAM and therefore should take its place. While it is true that flash is significantly slower than DRAM, one can afford to build much larger main memories out of flash than out of DRAM, and we show that an appropriately designed memory hierarchy, built of flash as main memory and DRAM as a cache, will approach the performance of DRAM, at the price-per-bit of flash. In our studies as part of this project, we have investigated Non-Volatile Main Memory (NVMM), a new main-memory architecture for large-scale computing systems, one that is specifically designed to address the weaknesses described previously. In particular, it provides the following features: non-volatility: The bulk of the storage is comprised of NAND flash, and in this organization DRAM is used only as a cache, not as main memory. Furthermore, the flash is journaled, which means that operations such as checkpoint/restore are already built into the system. 1+ terabytes of storage per socket: SSDs and DRAM DIMMs have roughly the same form factor (several square inches of PCB surface area), and terabyte SSDs are now commonplace. performance approaching that of DRAM: DRAM is used as a cache to the flash system. price-per-bit approaching that of NAND: Flash is currently well under $0.50 per gigabyte; DDR3 SDRAM is currently just over $10 per gigabyte [Newegg 2014]. Even today, one can build an easily affordable main memory system with a terabyte or more of NAND storage per CPU socket (which would be extremely expensive were one to use DRAM), and our cycle- accurate, full-system experiments show that this can be done at a performance point that lies within a factor of two of DRAM.« less

Robust resistive memory devices using solution-processable metal-coordinated azo aromatics

NASA Astrophysics Data System (ADS)

Goswami, Sreetosh; Matula, Adam J.; Rath, Santi P.; Hedström, Svante; Saha, Surajit; Annamalai, Meenakshi; Sengupta, Debabrata; Patra, Abhijeet; Ghosh, Siddhartha; Jani, Hariom; Sarkar, Soumya; Motapothula, Mallikarjuna Rao; Nijhuis, Christian A.; Martin, Jens; Goswami, Sreebrata; Batista, Victor S.; Venkatesan, T.

2017-12-01

Non-volatile memories will play a decisive role in the next generation of digital technology. Flash memories are currently the key player in the field, yet they fail to meet the commercial demands of scalability and endurance. Resistive memory devices, and in particular memories based on low-cost, solution-processable and chemically tunable organic materials, are promising alternatives explored by the industry. However, to date, they have been lacking the performance and mechanistic understanding required for commercial translation. Here we report a resistive memory device based on a spin-coated active layer of a transition-metal complex, which shows high reproducibility (~350 devices), fast switching (<=30 ns), excellent endurance (~1012 cycles), stability (>106 s) and scalability (down to ~60 nm2). In situ Raman and ultraviolet-visible spectroscopy alongside spectroelectrochemistry and quantum chemical calculations demonstrate that the redox state of the ligands determines the switching states of the device whereas the counterions control the hysteresis. This insight may accelerate the technological deployment of organic resistive memories.

MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

NASA Astrophysics Data System (ADS)

Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

2014-10-01

Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

CoNNeCT Baseband Processor Module

NASA Technical Reports Server (NTRS)

Yamamoto, Clifford K; Jedrey, Thomas C.; Gutrich, Daniel G.; Goodpasture, Richard L.

2011-01-01

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

Exploration of perpendicular magnetic anisotropy material system for application in spin transfer torque - Random access memory

NASA Astrophysics Data System (ADS)

Natarajarathinam, Anusha

Perpendicular magnetic anisotropy (PMA) materials have unique advantages when used in magnetic tunnel junctions (MTJ) which are the most critical part of spin-torque transfer random access memory devices (STT-RAMs) that are being researched intensively as future non-volatile memory technology. They have high magnetoresistance which improves their sensitivity. The STT-RAM has several advantages over competing technologies, for instance, low power consumption, non-volatility, ultra-fast read and write speed and high endurance. In personal computers, it can replace SRAM for high-speed applications, Flash for non-volatility, and PSRAM and DRAM for high-speed program execution. The main aim of this research is to identify and optimize the best perpendicular magnetic anisotropy (PMA) material system for application to STT-RAM technology. Preliminary search for perpendicular magnetic anisotropy (PMA) materials for pinned layer for MTJs started with the exploration and optimization of crystalline alloys such as Co50Pd50 alloy, Mn50Al50 and amorphous alloys such as Tb21Fe72Co7 and are first presented in this work. Further optimization includes the study of Co/[Pd/Pt]x multilayers (ML), and the development of perpendicular synthetic antiferromagnets (SAF) utilizing these multilayers. Focused work on capping and seed layers to evaluate interfacial perpendicular anisotropy in free layers for pMTJs is then discussed. Optimization of the full perpendicular magnetic tunnel junction (pMTJ) includes the CoFeB/MgO/CoFeB trilayer coupled to a pinned/pinning layer with perpendicular Co/[Pd/Pt]x SAF and a thin Ta seeded CoFeB free layer. Magnetometry, simulations, annealing studies, transport measurements and TEM analysis on these samples will then be presented.

Securing non-volatile memory regions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Faraboschi, Paolo; Ranganathan, Parthasarathy; Muralimanohar, Naveen

Methods, apparatus and articles of manufacture to secure non-volatile memory regions are disclosed. An example method disclosed herein comprises associating a first key pair and a second key pair different than the first key pair with a process, using the first key pair to secure a first region of a non-volatile memory for the process, and using the second key pair to secure a second region of the non-volatile memory for the same process, the second region being different than the first region.

NASA's 3D Flight Computer for Space Applications

NASA Technical Reports Server (NTRS)

Alkalai, Leon

2000-01-01

The New Millennium Program (NMP) Integrated Product Development Team (IPDT) for Microelectronics Systems was planning to validate a newly developed 3D Flight Computer system on its first deep-space flight, DS1, launched in October 1998. This computer, developed in the 1995-97 time frame, contains many new computer technologies previously never used in deep-space systems. They include: advanced 3D packaging architecture for future low-mass and low-volume avionics systems; high-density 3D packaged chip-stacks for both volatile and non-volatile mass memory: 400 Mbytes of local DRAM memory, and 128 Mbytes of Flash memory; high-bandwidth Peripheral Component Interface (Per) local-bus with a bridge to VME; high-bandwidth (20 Mbps) fiber-optic serial bus; and other attributes, such as standard support for Design for Testability (DFT). Even though this computer system did not complete on time for delivery to the DS1 project, it was an important development along a technology roadmap towards highly integrated and highly miniaturized avionics systems for deep-space applications. This continued technology development is now being performed by NASA's Deep Space System Development Program (also known as X2000) and within JPL's Center for Integrated Space Microsystems (CISM).

Hysteresis in Lanthanide Aluminum Oxides Observed by Fast Pulse CV Measurement

PubMed Central

Zhao, Chun; Zhao, Ce Zhou; Lu, Qifeng; Yan, Xiaoyi; Taylor, Stephen; Chalker, Paul R.

2014-01-01

Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). A novel characterization (pulse capacitance-voltage) method was proposed in detail. The pulse capacitance-voltage technique was employed to characterize oxide traps of high-k dielectrics based on the Metal Oxide Semiconductor (MOS) capacitor structure. The variation of flat-band voltages of the MOS structure was observed and discussed accordingly. Some interesting trapping/detrapping results related to the lanthanide aluminum oxide traps were identified for possible application in Flash memory technology. After understanding the trapping/detrapping mechanism of the high-k oxides, a solid foundation was prepared for further exploration into charge-trapping non-volatile memory in the future. PMID:28788225

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications

NASA Astrophysics Data System (ADS)

Liu, Chunsen; Yan, Xiao; Song, Xiongfei; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-05-01

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

Method for refreshing a non-volatile memory

DOEpatents

Riekels, James E.; Schlesinger, Samuel

2008-11-04

A non-volatile memory and a method of refreshing a memory are described. The method includes allowing an external system to control refreshing operations within the memory. The memory may generate a refresh request signal and transmit the refresh request signal to the external system. When the external system finds an available time to process the refresh request, the external system acknowledges the refresh request and transmits a refresh acknowledge signal to the memory. The memory may also comprise a page register for reading and rewriting a data state back to the memory. The page register may comprise latches in lieu of supplemental non-volatile storage elements, thereby conserving real estate within the memory.

A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5-x/TaO2-x bilayer structures

NASA Astrophysics Data System (ADS)

Lee, Myoung-Jae; Lee, Chang Bum; Lee, Dongsoo; Lee, Seung Ryul; Chang, Man; Hur, Ji Hyun; Kim, Young-Bae; Kim, Chang-Jung; Seo, David H.; Seo, Sunae; Chung, U.-In; Yoo, In-Kyeong; Kim, Kinam

2011-08-01

Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaOx-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 1012. Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

Modular nonvolatile solid state recorder (MONSSTR) update

NASA Astrophysics Data System (ADS)

Klang, Mark R.; Small, Martin B.; Beams, Tom

2001-12-01

Solid state recorders have begun replacing traditional tape recorders in fulfilling the requirement to record images on airborne platforms. With the advances in electro-optical, IR, SAR, Multi and Hyper-spectral sensors and video recording requirements, solid state recorders have become the recorder of choice. Solid state recorders provide the additional storage, higher sustained bandwidth, less power, less weight and smaller footprint to meet the current and future recording requirements. CALCULEX, Inc., manufactures a non-volatile flash memory solid state recorder called the MONSSTR (Modular Non-volatile Solid State Recorder). MONSSTR is being used to record images from many different digital sensors on high performance aircraft such as the RF- 4, F-16 and the Royal Air Force Tornado. MONSSTR, with its internal multiplexer, is also used to record instrumentation data. This includes multiple streams of PCM and multiple channels of 1553 data. Instrumentation data is being recorded by MONSSTR systems in a range of platforms including F-22, F-15, F-16, Comanche Helicopter and US Navy torpedos. MONSSTR can also be used as a cockpit video recorder. This paper will provide an update of the MONSSTR.

NAFFS: network attached flash file system for cloud storage on portable consumer electronics

NASA Astrophysics Data System (ADS)

Han, Lin; Huang, Hao; Xie, Changsheng

Cloud storage technology has become a research hotspot in recent years, while the existing cloud storage services are mainly designed for data storage needs with stable high speed Internet connection. Mobile Internet connections are often unstable and the speed is relatively low. These native features of mobile Internet limit the use of cloud storage in portable consumer electronics. The Network Attached Flash File System (NAFFS) presented the idea of taking the portable device built-in NAND flash memory as the front-end cache of virtualized cloud storage device. Modern portable devices with Internet connection have built-in more than 1GB NAND Flash, which is quite enough for daily data storage. The data transfer rate of NAND flash device is much higher than mobile Internet connections[1], and its non-volatile feature makes it very suitable as the cache device of Internet cloud storage on portable device, which often have unstable power supply and intermittent Internet connection. In the present work, NAFFS is evaluated with several benchmarks, and its performance is compared with traditional network attached file systems, such as NFS. Our evaluation results indicate that the NAFFS achieves an average accessing speed of 3.38MB/s, which is about 3 times faster than directly accessing cloud storage by mobile Internet connection， and offers a more stable interface than that of directly using cloud storage API. Unstable Internet connection and sudden power off condition are tolerable, and no data in cache will be lost in such situation.

Carbon nanomaterials for non-volatile memories

NASA Astrophysics Data System (ADS)

Ahn, Ethan C.; Wong, H.-S. Philip; Pop, Eric

2018-03-01

Carbon can create various low-dimensional nanostructures with remarkable electronic, optical, mechanical and thermal properties. These features make carbon nanomaterials especially interesting for next-generation memory and storage devices, such as resistive random access memory, phase-change memory, spin-transfer-torque magnetic random access memory and ferroelectric random access memory. Non-volatile memories greatly benefit from the use of carbon nanomaterials in terms of bit density and energy efficiency. In this Review, we discuss sp2-hybridized carbon-based low-dimensional nanostructures, such as fullerene, carbon nanotubes and graphene, in the context of non-volatile memory devices and architectures. Applications of carbon nanomaterials as memory electrodes, interfacial engineering layers, resistive-switching media, and scalable, high-performance memory selectors are investigated. Finally, we compare the different memory technologies in terms of writing energy and time, and highlight major challenges in the manufacturing, integration and understanding of the physical mechanisms and material properties.

Different importance of the volatile and non-volatile fractions of an olfactory signature for individual social recognition in rats versus mice and short-term versus long-term memory.

PubMed

Noack, Julia; Richter, Karin; Laube, Gregor; Haghgoo, Hojjat Allah; Veh, Rüdiger W; Engelmann, Mario

2010-11-01

When tested in the olfactory cued social recognition/discrimination test, rats and mice differ in their retention of a recognition memory for a previously encountered conspecific juvenile: Rats are able to recognize a given juvenile for approximately 45 min only whereas mice show not only short-term, but also long-term recognition memory (≥ 24 h). Here we modified the social recognition/social discrimination procedure to investigate the neurobiological mechanism(s) underlying the species differences. We presented a conspecific juvenile repeatedly to the experimental subjects and monitored the investigation duration as a measure for recognition. Presentation of only the volatile fraction of the juvenile olfactory signature was sufficient for both short- and long-term recognition in mice but not rats. Applying additional volatile, mono-molecular odours to the "to be recognized" juveniles failed to affect short-term memory in both species, but interfered with long-term recognition in mice. Finally immunocytochemical analysis of c-Fos as a marker for cellular activation, revealed that juvenile exposure stimulated areas involved in the processing of olfactory signals in both the main and the accessory olfactory bulb in mice. In rats, we measured an increased c-Fos synthesis almost exclusively in cells of the accessory olfactory bulb. Our data suggest that the species difference in the retention of social recognition memory is based on differences in the processing of the volatile versus non-volatile fraction of the individuals' olfactory signature. The non-volatile fraction is sufficient for retaining a short-term social memory only. Long-term social memory - as observed in mice - requires a processing of both the volatile and non-volatile fractions of the olfactory signature. Copyright © 2010 Elsevier Inc. All rights reserved.

Flash memory management system and method utilizing multiple block list windows

NASA Technical Reports Server (NTRS)

Chow, James (Inventor); Gender, Thomas K. (Inventor)

2005-01-01

The present invention provides a flash memory management system and method with increased performance. The flash memory management system provides the ability to efficiently manage and allocate flash memory use in a way that improves reliability and longevity, while maintaining good performance levels. The flash memory management system includes a free block mechanism, a disk maintenance mechanism, and a bad block detection mechanism. The free block mechanism provides efficient sorting of free blocks to facilitate selecting low use blocks for writing. The disk maintenance mechanism provides for the ability to efficiently clean flash memory blocks during processor idle times. The bad block detection mechanism provides the ability to better detect when a block of flash memory is likely to go bad. The flash status mechanism stores information in fast access memory that describes the content and status of the data in the flash disk. The new bank detection mechanism provides the ability to automatically detect when new banks of flash memory are added to the system. Together, these mechanisms provide a flash memory management system that can improve the operational efficiency of systems that utilize flash memory.

Method for providing uranium with a protective copper coating

DOEpatents

Waldrop, Forrest B.; Jones, Edward

1981-01-01

The present invention is directed to a method for providing uranium metal with a protective coating of copper. Uranium metal is subjected to a conventional cleaning operation wherein oxides and other surface contaminants are removed, followed by etching and pickling operations. The copper coating is provided by first electrodepositing a thin and relatively porous flash layer of copper on the uranium in a copper cyanide bath. The resulting copper-layered article is then heated in an air or inert atmosphere to volatilize and drive off the volatile material underlying the copper flash layer. After the heating step an adherent and essentially non-porous layer of copper is electro-deposited on the flash layer of copper to provide an adherent, multi-layer copper coating which is essentially impervious to corrosion by most gases.

Computing with volatile memristors: an application of non-pinched hysteresis

NASA Astrophysics Data System (ADS)

Pershin, Y. V.; Shevchenko, S. N.

2017-02-01

The possibility of in-memory computing with volatile memristive devices, namely, memristors requiring a power source to sustain their memory, is demonstrated theoretically. We have adopted a hysteretic graphene-based field emission structure as a prototype of a volatile memristor, which is characterized by a non-pinched hysteresis loop. A memristive model of the structure is developed and used to simulate a polymorphic circuit implementing stateful logic gates, such as the material implication. Specific regions of parameter space realizing useful logic functions are identified. Our results are applicable to other realizations of volatile memory devices, such as certain NEMS switches.

Active non-volatile memory post-processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kannan, Sudarsun; Milojicic, Dejan S.; Talwar, Vanish

A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.

40 CFR 60.591 - Definitions.

Code of Federal Regulations, 2011 CFR

2011-07-01

... Bitumen) is a black or dark brown solid or semi-solid thermo-plastic material possessing waterproofing and... hydrogen ratio. It is essentially non-volatile at ambient temperatures with closed cup flash point of 445...

A review of emerging non-volatile memory (NVM) technologies and applications

NASA Astrophysics Data System (ADS)

Chen, An

2016-11-01

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

Hold-up power supply for flash memory

NASA Technical Reports Server (NTRS)

Ott, William E. (Inventor)

2004-01-01

A hold-up power supply for flash memory systems is provided. The hold-up power supply provides the flash memory with the power needed to temporarily operate when a power loss exists. This allows the flash memory system to complete any erasures and writes, and thus allows it to shut down gracefully. The hold-up power supply detects when a power loss on a power supply bus is occurring and supplies the power needed for the flash memory system to temporally operate. The hold-up power supply stores power in at least one capacitor. During normal operation, power from a high voltage supply bus is used to charge the storage capacitors. When a power supply loss is detected, the power supply bus is disconnected from the flash memory system. A hold-up controller controls the power flow from the storage capacitors to the flash memory system. The hold-up controller uses feedback to assure that the proper voltage is provided from the storage capacitors to the flash memory system. This power supplied by the storage capacitors allows the flash memory system to complete any erasures and writes, and thus allows the flash memory system to shut down gracefully.

Makalu: fast recoverable allocation of non-volatile memory

DOE PAGES

Bhandari, Kumud; Chakrabarti, Dhruva R.; Boehm, Hans-J.

2016-10-19

Byte addressable non-volatile memory (NVRAM) is likely to supplement, and perhaps eventually replace, DRAM. Applications can then persist data structures directly in memory instead of serializing them and storing them onto a durable block device. However, failures during execution can leave data structures in NVRAM unreachable or corrupt. In this paper, we present Makalu, a system that addresses non-volatile memory management. Makalu offers an integrated allocator and recovery-time garbage collector that maintains internal consistency, avoids NVRAM memory leaks, and is efficient, all in the face of failures. We show that a careful allocator design can support a less restrictive andmore » a much more familiar programming model than existing persistent memory allocators. Our allocator significantly reduces the per allocation persistence overhead by lazily persisting non-essential metadata and by employing a post-failure recovery-time garbage collector. Experimental results show that the resulting online speed and scalability of our allocator are comparable to well-known transient allocators, and significantly better than state-of-the-art persistent allocators.« less

Makalu: fast recoverable allocation of non-volatile memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bhandari, Kumud; Chakrabarti, Dhruva R.; Boehm, Hans-J.

Byte addressable non-volatile memory (NVRAM) is likely to supplement, and perhaps eventually replace, DRAM. Applications can then persist data structures directly in memory instead of serializing them and storing them onto a durable block device. However, failures during execution can leave data structures in NVRAM unreachable or corrupt. In this paper, we present Makalu, a system that addresses non-volatile memory management. Makalu offers an integrated allocator and recovery-time garbage collector that maintains internal consistency, avoids NVRAM memory leaks, and is efficient, all in the face of failures. We show that a careful allocator design can support a less restrictive andmore » a much more familiar programming model than existing persistent memory allocators. Our allocator significantly reduces the per allocation persistence overhead by lazily persisting non-essential metadata and by employing a post-failure recovery-time garbage collector. Experimental results show that the resulting online speed and scalability of our allocator are comparable to well-known transient allocators, and significantly better than state-of-the-art persistent allocators.« less

Non-Volatile Memory Technology Symposium 2000: Proceedings

NASA Technical Reports Server (NTRS)

Aranki, Nazeeh (Editor)

2000-01-01

This publication contains the proceedings for the Non-Volatile Memory Technology Symposium 2000 that was held on November 15-16, 2000 in Arlington, Virginia. The proceedings contains a wide range of papers that cover the presentations of myriad advances in the nonvolatile memory technology during the recent past including memory cell design, simulations, radiation environment, and emerging memory technologies. The papers presented in the proceedings address the design challenges and applications and deals with newer, emerging memory technologies as well as related issues of radiation environment and die packaging.

40 CFR 60.591a - Definitions.

Code of Federal Regulations, 2011 CFR

2011-07-01

... dark brown solid or semi-solid thermo-plastic material possessing waterproofing and adhesive properties... essentially non-volatile at ambient temperatures with closed cup flash point of 445 °F (230 °C) or greater...

Extraction of the gate capacitance coupling coefficient in floating gate non-volatile memories: Statistical study of the effect of mismatching between floating gate memory and reference transistor in dummy cell extraction methods

NASA Astrophysics Data System (ADS)

Rafhay, Quentin; Beug, M. Florian; Duane, Russell

2007-04-01

This paper presents an experimental comparison of dummy cell extraction methods of the gate capacitance coupling coefficient for floating gate non-volatile memory structures from different geometries and technologies. These results show the significant influence of mismatching floating gate devices and reference transistors on the extraction of the gate capacitance coupling coefficient. In addition, it demonstrates the accuracy of the new bulk bias dummy cell extraction method and the importance of the β function, introduced recently in [Duane R, Beug F, Mathewson A. Novel capacitance coupling coefficient measurement methodology for floating gate non-volatile memory devices. IEEE Electr Dev Lett 2005;26(7):507-9], to determine matching pairs of floating gate memory and reference transistor.

Overview of Non-Volatile Testing and Screening Methods

NASA Technical Reports Server (NTRS)

Irom, Farokh

2001-01-01

Testing methods for memories and non-volatile memories have become increasingly sophisticated as they become denser and more complex. High frequency and faster rewrite times as well as smaller feature sizes have led to many testing challenges. This paper outlines several testing issues posed by novel memories and approaches to testing for radiation and reliability effects. We discuss methods for measurements of Total Ionizing Dose (TID).

Nanoscale CuO solid-electrolyte-based conductive-bridging, random-access memory cell with a TiN liner

NASA Astrophysics Data System (ADS)

Lee, Jong-Sun; Kim, Dong-Won; Kim, Hea-Jee; Jin, Soo-Min; Song, Myung-Jin; Kwon, Ki-Hyun; Park, Jea-Gun; Jalalah, Mohammed; Al-Hajry, Ali

2018-01-01

The Conductive-bridge random-access memory (CBRAM) cell is a promising candidate for a terabit-level non-volatile memory due to its remarkable advantages. We present for the first time TiN as a diffusion barrier in CBRAM cells for enhancing their reliability. CuO solid-electrolyte-based CBRAM cells implemented with a 0.1-nm TiN liner demonstrated better non-volatile memory characteristics such as 106 AC write/erase endurance cycles with 100-μs AC pulse width and a long retention time of 7.4-years at 85 °C. In addition, the analysis of Ag diffusion in the CBRAM cell suggests that the morphology of the Ag filaments in the electrolyte can be effectively controlled by tuning the thickness of the TiN liner. These promising results pave the way for faster commercialization of terabit-level non-volatile memories.

Metal-organic molecular device for non-volatile memory storage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Radha, B., E-mail: radha.boya@manchester.ac.uk, E-mail: kulkarni@jncasr.ac.in; Sagade, Abhay A.; Kulkarni, G. U., E-mail: radha.boya@manchester.ac.uk, E-mail: kulkarni@jncasr.ac.in

Non-volatile memory devices have been of immense research interest for their use in active memory storage in powered off-state of electronic chips. In literature, various molecules and metal compounds have been investigated in this regard. Molecular memory devices are particularly attractive as they offer the ease of storing multiple memory states in a unique way and also represent ubiquitous choice for miniaturized devices. However, molecules are fragile and thus the device breakdown at nominal voltages during repeated cycles hinders their practical applicability. Here, in this report, a synergetic combination of an organic molecule and an inorganic metal, i.e., a metal-organicmore » complex, namely, palladium hexadecylthiolate is investigated for memory device characteristics. Palladium hexadecylthiolate following partial thermolysis is converted to a molecular nanocomposite of Pd(II), Pd(0), and long chain hydrocarbons, which is shown to exhibit non-volatile memory characteristics with exceptional stability and retention. The devices are all solution-processed and the memory action stems from filament formation across the pre-formed cracks in the nanocomposite film.« less

Integrated semiconductor-magnetic random access memory system

NASA Technical Reports Server (NTRS)

Katti, Romney R. (Inventor); Blaes, Brent R. (Inventor)

2001-01-01

The present disclosure describes a non-volatile magnetic random access memory (RAM) system having a semiconductor control circuit and a magnetic array element. The integrated magnetic RAM system uses CMOS control circuit to read and write data magnetoresistively. The system provides a fast access, non-volatile, radiation hard, high density RAM for high speed computing.

78 FR 48188 - Certain Flash Memory Chips and Products Containing the Same Notice of Receipt of Complaint...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-08-07

... INTERNATIONAL TRADE COMMISSION [Docket No. 2971] Certain Flash Memory Chips and Products.... International Trade Commission has received a complaint entitled Certain Flash Memory Chips and Products... sale within the United States after importation of certain flash memory chips and products containing...

78 FR 55095 - Certain Flash Memory Chips and Products Containing Same; Institution of Investigation

Federal Register 2010, 2011, 2012, 2013, 2014

2013-09-09

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-893] Certain Flash Memory Chips and... States after importation of certain flash memory chips and products containing the same by reason of... sale within the United States after importation of certain flash memory chips and products containing...

Enhancement of memory margins in the polymer composite of [6,6]-phenyl-C61-butyric acid methyl ester and polystyrene.

PubMed

Sun, Yanmei; Lu, Junguo; Ai, Chunpeng; Wen, Dianzhong; Bai, Xuduo

2016-11-09

Memory devices based on composites of polystyrene (PS) and [6,6]-phenyl-C 61 -butyric acid methyl ester (PCBM) were investigated with bistable resistive switching behavior. Current-voltage (I-V) curves for indium-tin-oxide (ITO)/PS + PCBM/Al devices with 33 wt% PCBM showed non-volatile, rewritable, flash memory properties with a maximum ON/OFF current ratio of 1 × 10 4 , which was 100 times larger than the ON/OFF ratio of the device with 5 wt% PCBM. For ITO/PS + PCBM/Al devices with 33 wt% PCBM, the write-read-erase-read test cycles demonstrated the bistable devices with ON and OFF states at the same voltage. The programmable ON and OFF states endured up to 10 4 read pulses and possessed a retention time of over 10 5 s, indicative of the memory stability of the device. In the OFF state, the I-V curve at lower voltages up to 0.45 V was attributed to the thermionic emission mechanism, and the I-V characteristics in the applied voltage above 0.5 V dominantly followed the space-charge-limited-current behaviors. In the ON state, the curve in the applied voltage range was related to an Ohmic mechanism.

CoNNeCT Baseband Processor Module Boot Code SoftWare (BCSW)

NASA Technical Reports Server (NTRS)

Yamamoto, Clifford K.; Orozco, David S.; Byrne, D. J.; Allen, Steven J.; Sahasrabudhe, Adit; Lang, Minh

2012-01-01

This software provides essential startup and initialization routines for the CoNNeCT baseband processor module (BPM) hardware upon power-up. A command and data handling (C&DH) interface is provided via 1553 and diagnostic serial interfaces to invoke operational, reconfiguration, and test commands within the code. The BCSW has features unique to the hardware it is responsible for managing. In this case, the CoNNeCT BPM is configured with an updated CPU (Atmel AT697 SPARC processor) and a unique set of memory and I/O peripherals that require customized software to operate. These features include configuration of new AT697 registers, interfacing to a new HouseKeeper with a flash controller interface, a new dual Xilinx configuration/scrub interface, and an updated 1553 remote terminal (RT) core. The BCSW is intended to provide a "safe" mode for the BPM when initially powered on or when an unexpected trap occurs, causing the processor to reset. The BCSW allows the 1553 bus controller in the spacecraft or payload controller to operate the BPM over 1553 to upload code; upload Xilinx bit files; perform rudimentary tests; read, write, and copy the non-volatile flash memory; and configure the Xilinx interface. Commands also exist over 1553 to cause the CPU to jump or call a specified address to begin execution of user-supplied code. This may be in the form of a real-time operating system, test routine, or specific application code to run on the BPM.

Multilevel non-volatile data storage utilizing common current hysteresis of networked single walled carbon nanotubes

NASA Astrophysics Data System (ADS)

Hwang, Ihn; Wang, Wei; Hwang, Sun Kak; Cho, Sung Hwan; Kim, Kang Lib; Jeong, Beomjin; Huh, June; Park, Cheolmin

2016-05-01

The characteristic source-drain current hysteresis frequently observed in field-effect transistors with networked single walled carbon-nanotube (NSWNT) channels is problematic for the reliable switching and sensing performance of devices. But the two distinct current states of the hysteresis curve at a zero gate voltage can be useful for memory applications. In this work, we demonstrate a novel non-volatile transistor memory with solution-processed NSWNTs which are suitable for multilevel data programming and reading. A polymer passivation layer with a small amount of water employed on the top of the NSWNT channel serves as an efficient gate voltage dependent charge trapping and de-trapping site. A systematic investigation evidences that the water mixed in a polymer passivation solution is critical for reliable non-volatile memory operation. The optimized device is air-stable and temperature-resistive up to 80 °C and exhibits excellent non-volatile memory performance with an on/off current ratio greater than 104, a switching time less than 100 ms, data retention longer than 4000 s, and write/read endurance over 100 cycles. Furthermore, the gate voltage dependent charge injection mediated by water in the passivation layer allowed for multilevel operation of our memory in which 4 distinct current states were programmed repetitively and preserved over a long time period.The characteristic source-drain current hysteresis frequently observed in field-effect transistors with networked single walled carbon-nanotube (NSWNT) channels is problematic for the reliable switching and sensing performance of devices. But the two distinct current states of the hysteresis curve at a zero gate voltage can be useful for memory applications. In this work, we demonstrate a novel non-volatile transistor memory with solution-processed NSWNTs which are suitable for multilevel data programming and reading. A polymer passivation layer with a small amount of water employed on the top of the NSWNT channel serves as an efficient gate voltage dependent charge trapping and de-trapping site. A systematic investigation evidences that the water mixed in a polymer passivation solution is critical for reliable non-volatile memory operation. The optimized device is air-stable and temperature-resistive up to 80 °C and exhibits excellent non-volatile memory performance with an on/off current ratio greater than 104, a switching time less than 100 ms, data retention longer than 4000 s, and write/read endurance over 100 cycles. Furthermore, the gate voltage dependent charge injection mediated by water in the passivation layer allowed for multilevel operation of our memory in which 4 distinct current states were programmed repetitively and preserved over a long time period. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr00505e

A room-temperature non-volatile CNT-based molecular memory cell

NASA Astrophysics Data System (ADS)

Ye, Senbin; Jing, Qingshen; Han, Ray P. S.

2013-04-01

Recent experiments with a carbon nanotube (CNT) system confirmed that the innertube can oscillate back-and-forth even under a room-temperature excitation. This demonstration of relative motion suggests that it is now feasible to build a CNT-based molecular memory cell (MC), and the key to bring the concept to reality is the precision control of the moving tube for sustained and reliable read/write (RW) operations. Here, we show that by using a 2-section outertube design, we are able to suitably recalibrate the system energetics and obtain the designed performance characteristics of a MC. Further, the resulting energy modification enables the MC to operate as a non-volatile memory element at room temperatures. Our paper explores a fundamental understanding of a MC and its response at the molecular level to roadmap a novel approach in memory technologies that can be harnessed to overcome the miniaturization limit and memory volatility in memory technologies.

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

PubMed

Ng, Tse Nga; Schwartz, David E; Lavery, Leah L; Whiting, Gregory L; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

75 FR 55604 - In the Matter of Certain Flash Memory Chips and Products Containing the Same; Notice of...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-09-13

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-735] In the Matter of Certain Flash Memory Chips... the sale within the United States after importation of certain flash memory chips and products... importation of certain flash memory chips and products containing the same that infringe one or more of claims...

Reconfigurable Electronics and Non-Volatile Memory Research

DTIC Science & Technology

2015-11-10

Kirtland AFB, NM 87117-5776 2 cys Official Record Copy AFRL /RVSE/Arthur Edwards 1 cy... AFRL -RV-PS- AFRL -RV-PS- TR-2015-0151 TR-2015-0151 RECONFIGURABLE ELECTRONICS AND NON- VOLATILE MEMORY RESEARCH Kristy A. Campbell Boise State... KIRTLAND AIR FORCE BASE, NM 87117-5776 NOTICE AND SIGNATURE PAGE Using Government drawings, specifications, or other data included in this document for

Non-volatile resistive switching in the Mott insulator (V1-xCrx)2O3

NASA Astrophysics Data System (ADS)

Querré, M.; Tranchant, J.; Corraze, B.; Cordier, S.; Bouquet, V.; Députier, S.; Guilloux-Viry, M.; Besland, M.-P.; Janod, E.; Cario, L.

2018-05-01

The discovery of non-volatile resistive switching in Mott insulators related to an electric-field-induced insulator to metal transition (IMT) has paved the way for their use in a new type of non-volatile memories, the Mott memories. While most of the previous studies were dedicated to uncover the resistive switching mechanism and explore the memory potential of chalcogenide Mott insulators, we present here a comprehensive study of resistive switching in the canonical oxide Mott insulator (V1-xCrx)2O3. Our work demonstrates that this compound undergoes a non-volatile resistive switching under electric field. This resistive switching is induced by a Mott transition at the local scale which creates metallic domains closely related to existing phases of the temperature-pressure phase diagram of (V1-xCrx)2O3. Our work demonstrates also reversible resistive switching in (V1-xCrx)2O3 crystals and thin film devices. Preliminary performances obtained on 880 nm thick layers with 500 nm electrodes show the strong potential of Mott memories based on the Mott insulator (V1-xCrx)2O3.

Evaluation of 1.5-T Cell Flash Memory Total Ionizing Dose Response

NASA Astrophysics Data System (ADS)

Clark, Lawrence T.; Holbert, Keith E.; Adams, James W.; Navale, Harshad; Anderson, Blake C.

2015-12-01

Flash memory is an essential part of systems used in harsh environments, experienced by both terrestrial and aerospace TID applications. This paper presents studies of COTS flash memory TID hardness. While there is substantial literature on flash memory TID response, this work focuses for the first time on 1.5 transistor per cell flash memory. The experimental results show hardness varying from about 100 krad(Si) to over 250 krad(Si) depending on the usage model. We explore the circuit and device aspects of the results, based on the extensive reliability literature for this flash memory type. Failure modes indicate both device damage and circuit marginalities. Sector erase failure limits, but read only operation allows TID exceeding 200 krad(Si). The failures are analyzed by type.

76 FR 55417 - In the Matter of Certain Dynamic Random Access Memory and Nand Flash Memory Devices and Products...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-09-07

... Access Memory and Nand Flash Memory Devices and Products Containing Same; Notice of Institution of... importation, and the sale within the United States after importation of certain dynamic random access memory and NAND flash memory devices and products containing same by reason of infringement of certain claims...

A Comprehensive Study on Energy Efficiency and Performance of Flash-based SSD

DOE Office of Scientific and Technical Information (OSTI.GOV)

Park, Seon-Yeon; Kim, Youngjae; Urgaonkar, Bhuvan

2011-01-01

Use of flash memory as a storage medium is becoming popular in diverse computing environments. However, because of differences in interface, flash memory requires a hard-disk-emulation layer, called FTL (flash translation layer). Although the FTL enables flash memory storages to replace conventional hard disks, it induces significant computational and space overhead. Despite the low power consumption of flash memory, this overhead leads to significant power consumption in an overall storage system. In this paper, we analyze the characteristics of flash-based storage devices from the viewpoint of power consumption and energy efficiency by using various methodologies. First, we utilize simulation tomore » investigate the interior operation of flash-based storage of flash-based storages. Subsequently, we measure the performance and energy efficiency of commodity flash-based SSDs by using microbenchmarks to identify the block-device level characteristics and macrobenchmarks to reveal their filesystem level characteristics.« less

A bi-stable nanoelectromechanical non-volatile memory based on van der Waals force

NASA Astrophysics Data System (ADS)

Soon, Bo Woon; Jiaqiang Ng, Eldwin; Qian, You; Singh, Navab; Julius Tsai, Minglin; Lee, Chengkuo

2013-07-01

By using complementary-metal-oxide-semiconductor processes, a silicon based bi-stable nanoelectromechanical non-volatile memory is fabricated and characterized. The main feature of this device is an 80 nm wide and 3 μm high silicon nanofin (SiNF) of a high aspect ratio (1:35). The switching mechanism is realized by electrostatic actuation between two lateral electrodes, i.e., terminals. Bi-stable hysteresis behavior is demonstrated when the SiNF maintains its contact to one of the two terminals by leveraging on van der Waals force even after voltage bias is turned off. The compelling results indicate that this design is promising for realization of high density non-volatile memory application due to its nano-scale footprint and zero on-hold power consumption.

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

PubMed Central

Ng, Tse Nga; Schwartz, David E.; Lavery, Leah L.; Whiting, Gregory L.; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic. PMID:22900143

Peroxide induced volatile and non-volatile switching behavior in ZnO-based electrochemical metallization memory cell

NASA Astrophysics Data System (ADS)

Mangasa Simanjuntak, Firman; Chandrasekaran, Sridhar; Pattanayak, Bhaskar; Lin, Chun-Chieh; Tseng, Tseung-Yuen

2017-09-01

We explore the use of cubic-zinc peroxide (ZnO2) as a switching material for electrochemical metallization memory (ECM) cell. The ZnO2 was synthesized with a simple peroxide surface treatment. Devices made without surface treatment exhibits a high leakage current due to the self-doped nature of the hexagonal-ZnO material. Thus, its switching behavior can only be observed when a very high current compliance is employed. The synthetic ZnO2 layer provides a sufficient resistivity to the Cu/ZnO2/ZnO/ITO devices. The high resistivity of ZnO2 encourages the formation of a conducting bridge to activate the switching behavior at a lower operation current. Volatile and non-volatile switching behaviors with sufficient endurance and an adequate memory window are observed in the surface-treated devices. The room temperature retention of more than 104 s confirms the non-volatility behavior of the devices. In addition, our proposed device structure is able to work at a lower operation current among other reported ZnO-based ECM cells.

Active Flash: Performance-Energy Tradeoffs for Out-of-Core Processing on Non-Volatile Memory Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Boboila, Simona; Kim, Youngjae; Vazhkudai, Sudharshan S

2012-01-01

In this abstract, we study the performance and energy tradeoffs involved in migrating data analysis into the flash device, a process we refer to as Active Flash. The Active Flash paradigm is similar to 'active disks', which has received considerable attention. Active Flash allows us to move processing closer to data, thereby minimizing data movement costs and reducing power consumption. It enables true out-of-core computation. The conventional definition of out-of-core solvers refers to an approach to process data that is too large to fit in the main memory and, consequently, requires access to disk. However, in Active Flash, processing outsidemore » the host CPU literally frees the core and achieves real 'out-of-core' analysis. Moving analysis to data has long been desirable, not just at this level, but at all levels of the system hierarchy. However, this requires a detailed study on the tradeoffs involved in achieving analysis turnaround under an acceptable energy envelope. To this end, we first need to evaluate if there is enough computing power on the flash device to warrant such an exploration. Flash processors require decent computing power to run the internal logic pertaining to the Flash Translation Layer (FTL), which is responsible for operations such as address translation, garbage collection (GC) and wear-leveling. Modern SSDs are composed of multiple packages and several flash chips within a package. The packages are connected using multiple I/O channels to offer high I/O bandwidth. SSD computing power is also expected to be high enough to exploit such inherent internal parallelism within the drive to increase the bandwidth and to handle fast I/O requests. More recently, SSD devices are being equipped with powerful processing units and are even embedded with multicore CPUs (e.g. ARM Cortex-A9 embedded processor is advertised to reach 2GHz frequency and deliver 5000 DMIPS; OCZ RevoDrive X2 SSD has 4 SandForce controllers, each with 780MHz max frequency Tensilica core). Efforts that take advantage of the available computing cycles on the processors on SSDs to run auxiliary tasks other than actual I/O requests are beginning to emerge. Kim et al. investigate database scan operations in the context of processing on the SSDs, and propose dedicated hardware logic to speed up scans. Also, cluster architectures have been explored, which consist of low-power embedded CPUs coupled with small local flash to achieve fast, parallel access to data. Processor utilization on SSD is highly dependent on workloads and, therefore, they can be idle during periods with no I/O accesses. We propose to use the available processing capability on the SSD to run tasks that can be offloaded from the host. This paper makes the following contributions: (1) We have investigated Active Flash and its potential to optimize the total energy cost, including power consumption on the host and the flash device; (2) We have developed analytical models to analyze the performance-energy tradeoffs for Active Flash, by treating the SSD as a blackbox, this is particularly valuable due to the proprietary nature of the SSD internal hardware; and (3) We have enhanced a well-known SSD simulator (from MSR) to implement 'on-the-fly' data compression using Active Flash. Our results provide a window into striking a balance between energy consumption and application performance.« less

EDITORIAL: Non-volatile memory based on nanostructures Non-volatile memory based on nanostructures

NASA Astrophysics Data System (ADS)

Kalinin, Sergei; Yang, J. Joshua; Demming, Anna

2011-06-01

Non-volatile memory refers to the crucial ability of computers to store information once the power source has been removed. Traditionally this has been achieved through flash, magnetic computer storage and optical discs, and in the case of very early computers paper tape and punched cards. While computers have advanced considerably from paper and punched card memory devices, there are still limits to current non-volatile memory devices that restrict them to use as secondary storage from which data must be loaded and carefully saved when power is shut off. Denser, faster, low-energy non-volatile memory is highly desired and nanostructures are the critical enabler. This special issue on non-volatile memory based on nanostructures describes some of the new physics and technology that may revolutionise future computers. Phase change random access memory, which exploits the reversible phase change between crystalline and amorphous states, also holds potential for future memory devices. The chalcogenide Ge2Sb2Te5 (GST) is a promising material in this field because it combines a high activation energy for crystallization and a relatively low crystallization temperature, as well as a low melting temperature and low conductivity, which accommodates localized heating. Doping is often used to lower the current required to activate the phase change or 'reset' GST but this often aggravates other problems. Now researchers in Korea report in-depth studies of SiO2-doped GST and identify ways of optimising the material's properties for phase-change random access memory [1]. Resistance switching is an area that has attracted a particularly high level of interest for non-volatile memory technology, and a great deal of research has focused on the potential of TiO2 as a model system in this respect. Researchers at HP labs in the US have made notable progress in this field, and among the work reported in this special issue they describe means to control the switch resistance and show that limiting the current during electroforming leads to the coexistence of two resistance switching modes in TiO2 memristive devices [2]. They also present spectromicroscopic observations and modelling results for the Joule heating during switching, providing insights into the ON/OFF switching process [3]. Researchers in Korea have examined in detail the mechanism of electronic bipolar resistance switching in the Pt/TiO2/Pt structure and show that degradation in switching performance of this system can be explained by the modified distribution of trap densities [4]. The issue also includes studies of TiO2 that demonstrate analog memory, synaptic plasticity, and spike-timing-dependent plasticity functions, work that contributes to the development of neuromorphic devices that have high efficiency and low power consumption [5]. In addition to enabling a wide range of data storage and logic applications, electroresistive non-volatile memories invite us to re-evaluate the long-held paradigms in the condensed matter physics of oxides. In the past three years, much attention has been attracted to polarization-mediated electronic transport [6, 7] and domain wall conduction [8] as the key to the next generation of electronic and spintronic devices based on ferroelectric tunnelling barriers. Typically local probe experiments are performed on an ambient scanning probe microscope platform under conditions of high voltage stresses, conditions highly conducive to electrochemical reactions. Recent experiments [9-13] suggest that ionic motion can heavily contribute to the measured responses and compete with purely physical mechanisms. Electrochemical effects can also be expected in non-ferroelectric materials such as manganites and cobaltites, as well as for thick ferroelectrics under high-field conditions, as in capacitors and tunnelling junctions where the ionic motion could be a major contributor to electric field-induced strain. Such strain, in turn, can affect the effective barrier width in tunnelling experiments, resulting in memristive ionic switching. These phenomena must be differentiated from intrinsic physical polarization switching effects. Similar analysis of solid-state electrochemistry versus physical mechanisms is also important for future research in all areas of oxide materials. In an age where miniaturised computer components can enable GPS tracking, internet access and even the remote operation of machinery from a mobile phone, there is an endearing quaintness associated with images of the large rooms rammed with wires and boxes that comprised early computers. Yet there was a time when these cumbersome devices were state of the art. When the electronic numerical integrator and computer (ENIAC) was developed it achieved speeds one thousand times faster than previous electromechanical machines, a leap in processing power that has not been achieved since. It is easy to imagine future generations looking back on the slow start up and shut down times and high energy consumption of today's computers with a similar wry smile. The articles in this special issue on non-volatile memory based on nanostructures present the very latest research into the next generation's device technology, which may eventually consign today's cutting edge electronics to the history books. References [1] Ryu S W et al 2011 Nanotechnology 22 254005 [2] Miao F, Yang J J, Borghetti J, Medeiros-Ribeiro G and Williams R S 2011 Nanotechnology 22 254007 [3] Strachan J P, Strukov D B, Borghetti J, Yang J J, Medeiros-Ribeiro G and Williams R S 2011 Nanotechnology 22 245015 [4] Kim K M, Choi B J, Lee M H, Kim G H, Song S J, Seok J Y, Yoon J H, Han S and Hwang C S 2011 Nanotechnology 22 254010 [5] Seo K et al 2011 Nanotechnology 22 254023 [6] Garcia V, Fusil S, Bouzehouane K, Enouz-Vedrenne S, Mathur N D, Barthelemy A and Bibes M 2009 Nature 460 81-4 [7] Maksymovych P, Jesse S, Yu P, Ramesh R, Baddorf A P and Kalinin S V 2009 Science 324 1421 [8] Seidel J et al 2009 Nature Mat. 8 229 [9] Tsuruoka T, Terabe K, Hasegawa T, and Aono M 2010 Nanotechnology 21 425205 [10] Waser R and Aono M 2007 Nature Mat. 6 833 [11] Sawa A 2008 Materials Today 11 28 [12] Strukov D B, Snider G S, Stewart D R and Williams R S 2008 Nature 453 80 Changes were made to this Editorial on 16 May 2011. An author was added to the Editorial.

40 CFR 60.591 - Definitions.

Code of Federal Regulations, 2010 CFR

2010-07-01

... hydrogen ratio. It is essentially non-volatile at ambient temperatures with closed cup flash point of 445... recordkeeping and reporting only, compressors are considered equipment. In hydrogen service means that a... sufficient storage facilities for the product. For the purpose of this subpart, process unit includes any...

The Forensic Potential of Flash Memory

DTIC Science & Technology

2009-09-01

limit range of 10 to 100 years before data is lost [12]. 5. Flash Memory Logical Structure The logical structure of flash memory from least to...area is not standardized and is manufacturer specific. This information will be used by the wear leveling algorithms and as such will be proprietary...memory cells, the manufacturers of the flash implement a wear leveling algorithm . In contrast, a magnetic disk in an overwrite operation will reuse the

An upconverted photonic nonvolatile memory.

PubMed

Zhou, Ye; Han, Su-Ting; Chen, Xian; Wang, Feng; Tang, Yong-Bing; Roy, V A L

2014-08-21

Conventional flash memory devices are voltage driven and found to be unsafe for confidential data storage. To ensure the security of the stored data, there is a strong demand for developing novel nonvolatile memory technology for data encryption. Here we show a photonic flash memory device, based on upconversion nanocrystals, which is light driven with a particular narrow width of wavelength in addition to voltage bias. With the help of near-infrared light, we successfully manipulate the multilevel data storage of the flash memory device. These upconverted photonic flash memory devices exhibit high ON/OFF ratio, long retention time and excellent rewritable characteristics.

Overview of emerging nonvolatile memory technologies

PubMed Central

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices. PMID:25278820

Overview of emerging nonvolatile memory technologies.

PubMed

Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices.

Materials and other needs for advanced phase change memory (Presentation Recording)

NASA Astrophysics Data System (ADS)

Sosa, Norma E.

2015-09-01

Phase change memory (PCM), with its long history, may now hold its brightest promise to date. This bright future is being fueled by the "push" from big data. PCM is a non-volatile memory technology used to create solid-state random access memory devices that operate based the resistance properties of materials. Employing the electrical resistance differences-as opposed to differences in charge stored-between the amorphous and crystalline phases of the material, PCM can store bits, namely one's and zero's. Indeed, owing to the method of storage, PCM can in fact be designed to hold multiple bits thus leading to a high-density technology twice the storage density and less than half the cost of DRAM, the main kind found in typical personal computers. It has been long known that PCM can fill a need gap that spans 3 decades in performance from DRAM to solid state drive (NAND Flash). Furthermore, PCM devices can lead to performance and reliability improvements essential to enabling significant steps forward to supporting big data centric computing. This talk will focus on the science and challenges of aggressive scaling to realize the density needed, how this scaling challenge is intertwined with materials needs for endurance into the giga-cycles, and the associated forefront research aiming to realizing multi-level functionality into these nanoscale programmable resistor devices.

Analog Nonvolatile Computer Memory Circuits

NASA Technical Reports Server (NTRS)

MacLeod, Todd

2007-01-01

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

The computation of dynamic fractional difference parameter for S&P500 index

NASA Astrophysics Data System (ADS)

Pei, Tan Pei; Cheong, Chin Wen; Galagedera, Don U. A.

2015-10-01

This study evaluates the time-varying long memory behaviors of the S&P500 volatility index using dynamic fractional difference parameters. Time-varying fractional difference parameter shows the dynamic of long memory in volatility series for the pre and post subprime mortgage crisis triggered by U.S. The results find an increasing trend in the S&P500 long memory volatility for the pre-crisis period. However, the onset of Lehman Brothers event reduces the predictability of volatility series following by a slight fluctuation of the factional differencing parameters. After that, the U.S. financial market becomes more informationally efficient and follows a non-stationary random process.

The consentaneous model of the financial markets exhibiting spurious nature of long-range memory

NASA Astrophysics Data System (ADS)

Gontis, V.; Kononovicius, A.

2018-09-01

It is widely accepted that there is strong persistence in the volatility of financial time series. The origin of the observed persistence, or long-range memory, is still an open problem as the observed phenomenon could be a spurious effect. Earlier we have proposed the consentaneous model of the financial markets based on the non-linear stochastic differential equations. The consentaneous model successfully reproduces empirical probability and power spectral densities of volatility. This approach is qualitatively different from models built using fractional Brownian motion. In this contribution we investigate burst and inter-burst duration statistics of volatility in the financial markets employing the consentaneous model. Our analysis provides an evidence that empirical statistical properties of burst and inter-burst duration can be explained by non-linear stochastic differential equations driving the volatility in the financial markets. This serves as an strong argument that long-range memory in finance can have spurious nature.

Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2010

NASA Technical Reports Server (NTRS)

Irom, Farokh; Nguyen, Duc N.

2010-01-01

High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) and multi-level cell (MLC) NAND flash memories manufactured by Micron Technology.

76 FR 41824 - In the Matter of Certain Flash Memory Chips And Products Containing Same; Notice of Commission...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-07-15

... Memory Chips And Products Containing Same; Notice of Commission Determination Not To Review an Initial... unopposed motion to terminate in its entirety Inv. No. 337-TA-735, Certain Flash Memory Chips and Products... flash memory chips and products containing same by reason of infringement of certain claims of U.S...

Spin torque switching of 20 nm magnetic tunnel junctions with perpendicular anisotropy

NASA Astrophysics Data System (ADS)

Gajek, M.; Nowak, J. J.; Sun, J. Z.; Trouilloud, P. L.; O'Sullivan, E. J.; Abraham, D. W.; Gaidis, M. C.; Hu, G.; Brown, S.; Zhu, Y.; Robertazzi, R. P.; Gallagher, W. J.; Worledge, D. C.

2012-03-01

Spin-transfer torque magnetic random access memory (STT-MRAM) is one of the most promising emerging non-volatile memory technologies. MRAM has so far been demonstrated with a unique combination of density, speed, and non-volatility in a single chip, however, without the capability to replace any single mainstream memory. In this paper, we demonstrate the basic physics of spin torque switching in 20 nm diameter magnetic tunnel junctions with perpendicular magnetic anisotropy materials. This deep scaling capability clearly indicates the STT MRAM device itself may be suitable for integration at much higher densities than previously proven.

Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2015-07-21

Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

Radiation Tests of Highly scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories--Update 2011

NASA Technical Reports Server (NTRS)

Irom, Farokh; Nguyen, Duc N.

2011-01-01

High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) 32Gb and multi-level cell (MLC) 64Gb NAND flash memories manufactured by Micron Technology.

Digital Device Architecture and the Safe Use of Flash Devices in Munitions

NASA Technical Reports Server (NTRS)

Katz, Richard B.; Flowers, David; Bergevin, Keith

2017-01-01

Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Digital devices of interest to designers include flash-based microcontrollers and field programmable gate arrays (FPGAs). Almost a decade ago, a study was undertaken to determine if flash-based microcontrollers could be safely used in fuzes and, if so, how should such devices be applied. The results were documented in the Technical Manual for the Use of Logic Devices in Safety Features. This paper will first review the Technical Manual and discuss the rationale behind the suggested architectures for microcontrollers and a brief review of the concern about data retention in flash cells. An architectural feature in the microcontroller under study will be discussed and its use will show how to screen for weak or failed cells during manufacture, storage, or immediately prior to use. As was done for microcontrollers a decade ago, architectures for a flash-based FPGA will be discussed, showing how it can be safely used in fuzes. Additionally, architectures for using non-volatile (including flash-based) storage will be discussed for SRAM-based FPGAs.

Development of Next Generation Memory Test Experiment for Deployment on a Small Satellite

NASA Technical Reports Server (NTRS)

MacLeod, Todd; Ho, Fat D.

2012-01-01

The original Memory Test Experiment successfully flew on the FASTSAT satellite launched in November 2010. It contained a single Ramtron 512K ferroelectric memory. The memory device went through many thousands of read/write cycles and recorded any errors that were encountered. The original mission length was schedule to last 6 months but was extended to 18 months. New opportunities exist to launch a similar satellite and considerations for a new memory test experiment should be examined. The original experiment had to be designed and integrated in less than two months, so the experiment was a simple design using readily available parts. The follow-on experiment needs to be more sophisticated and encompass more technologies. This paper lays out the considerations for the design and development of this follow-on flight memory experiment. It also details the results from the original Memory Test Experiment that flew on board FASTSAT. Some of the design considerations for the new experiment include the number and type of memory devices to be used, the kinds of tests that will be performed, other data needed to analyze the results, and best use of limited resources on a small satellite. The memory technologies that are considered are FRAM, FLASH, SONOS, Resistive Memory, Phase Change Memory, Nano-wire Memory, Magneto-resistive Memory, Standard DRAM, and Standard SRAM. The kinds of tests that could be performed are read/write operations, non-volatile memory retention, write cycle endurance, power measurements, and testing Error Detection and Correction schemes. Other data that may help analyze the results are GPS location of recorded errors, time stamp of all data recorded, radiation measurements, temperature, and other activities being perform by the satellite. The resources of power, volume, mass, temperature, processing power, and telemetry bandwidth are extremely limited on a small satellite. Design considerations must be made to allow the experiment to not interfere with the satellite s primary mission.

76 FR 4375 - In the Matter of Certain MLC Flash Memory Devices and Products Containing Same; Notice of...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-01-25

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-683] In the Matter of Certain MLC Flash Memory Devices and Products Containing Same; Notice of Commission Determination Not To Review an Initial... the United States after importation of certain MLC flash memory devices and products containing same...

78 FR 49287 - Certain Flash Memory Chips and Products Containing the Same Correction to Notice of Receipt of...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-08-13

... INTERNATIONAL TRADE COMMISSION [Docket No 2971] Certain Flash Memory Chips and Products Containing the Same Correction to Notice of Receipt of Complaint; Solicitation of Comments Relating to the Public..., Certain Flash Memory Chips and Products Containing the Same, DN 2971; the Commission solicited comments on...

A Fault-Tolerant Radiation-Robust Mass Storage Concept for Highly Scaled Flash Memory

NASA Astrophysics Data System (ADS)

Fuchs, Cristian M.; Trinitis, Carsten; Appel, Nicolas; Langer, Martin

2015-09-01

Future spacemissions will require vast amounts of data to be stored and processed aboard spacecraft. While satisfying operational mission requirements, storage systems must guarantee data integrity and recover damaged data throughout the mission. NAND-flash memories have become popular for space-borne high performance mass memory scenarios, though future storage concepts will rely upon highly scaled flash or other memory technologies. With modern flash memory, single bit erasure coding and RAID based concepts are insufficient. Thus, a fully run-time configurable, high performance, dependable storage concept, requiring a minimal set of logic or software. The solution is based on composite erasure coding and can be adjusted for altered mission duration or changing environmental conditions.

Environmental Effects on Data Retention in Flash Cells

NASA Technical Reports Server (NTRS)

Katz, Rich; Flowers, David; Bergevin, Keith

2017-01-01

Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Antifuse technology, prevalent in non-volatile field programmable gate arrays (FPGAs), will eventually be phased out as new devices have not been developed for approximately a decade. The reliance on flash technology presents a long-term reliability issue for both DoD and NASA safety- and mission-critical applications. A thorough understanding of the data retention failure modes and statistics associated with Flash data retention is of vital concern to the fuze safety community. A key retention parameter for a flash cell is the threshold voltage (VTH), which is an indirect indicator of the amount of charge stored on the cells floating gate. This paper will present the results of our on-going tests: long-term storage at 150 C for a small population of devices, neutron radiation exposure, electrostatic discharge (ESD) testing, and the trends of large populations (over 300 devices for each condition) exposed to three difference temperatures: 25 C, 125 C, and 150 C.

Novel conformal organic antireflective coatings for advanced I-line lithography

NASA Astrophysics Data System (ADS)

Deshpande, Shreeram V.; Nowak, Kelly A.; Fowler, Shelly; Williams, Paul; Arjona, Mikko

2001-08-01

Flash memory chips are playing a critical role in semiconductor devices due to increased popularity of hand held electronic communication devices such as cell phones and PDAs (personal Digital Assistants). Flash memory offers two primary advantages in semiconductor devices. First, it offers flexibility of in-circuit programming capability to reduce the loss from programming errors and to significantly reduce commercialization time to market for new devices. Second, flash memory has a double density memory capability through stacked gate structures which increases the memory capability and thus saves significantly on chip real estate. However, due to stacked gate structures the requirements for manufacturing of flash memory devices are significantly different from traditional memory devices. Stacked gate structures also offer unique challenges to lithographic patterning materials such as Bottom Anti-Reflective Coating (BARC) compositions used to achieve CD control and to minimize standing wave effect in photolithography. To be applicable in flash memory manufacturing a BARC should form a conformal coating on high topography of stacked gate features as well as provide the normal anti-reflection properties for CD control. In this paper we report on a new highly conformal advanced i-line BARC for use in design and manufacture of flash memory devices. Conformal BARCs being significantly thinner in trenches than the planarizing BARCs offer the advantage of reducing BARC overetch and thus minimizing resist thickness loss.

Phonological and Sensory Short-Term Memory Are Correlates and Both Affected in Developmental Dyslexia

ERIC Educational Resources Information Center

Laasonen, Marja; Virsu, Veijo; Oinonen, Suvi; Sandbacka, Mirja; Salakari, Anita; Service, Elisabet

2012-01-01

We investigated whether poor short-term memory (STM) in developmental dyslexia affects the processing of sensory stimulus sequences in addition to phonological material. STM for brief binary non-verbal stimuli (light flashes, tone bursts, finger touches, and their crossmodal combinations) was studied in 20 Finnish adults with dyslexia and 24…

Dynamic Forest: An Efficient Index Structure for NAND Flash Memory

NASA Astrophysics Data System (ADS)

Yang, Chul-Woong; Yong Lee, Ki; Ho Kim, Myoung; Lee, Yoon-Joon

In this paper, we present an efficient index structure for NAND flash memory, called the Dynamic Forest (D-Forest). Since write operations incur high overhead on NAND flash memory, D-Forest is designed to minimize write operations for index updates. The experimental results show that D-Forest significantly reduces write operations compared to the conventional B+-tree.

76 FR 40931 - In the Matter of Certain Flash Memory and Products Containing Same; Notice of Commission...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-07-12

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-685] In the Matter of Certain Flash Memory and... for importation, and the sale within the United States after importation of certain flash memory and... other agreements, written or oral, express or implied, between the parties concerning the subject matter...

75 FR 82071 - In the Matter of Certain Flash Memory Chips and Products Containing Same; Notice of Commission...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-12-29

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-664] In the Matter of Certain Flash Memory Chips and Products Containing Same; Notice of Commission Decision Not To Review the ALJ'S Final... States after importation of certain flash memory chips and products containing the same by reason of...

75 FR 82071 - In the Matter of Certain Flash Memory Chips and Products Containing Same; Notice of Commission...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-12-29

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-664] In the Matter of Certain Flash Memory Chips and Products Containing Same; Notice of Commission Decision Not To Review the ALJ's Final... flash memory chips and products containing the same by reason of infringement of various claims of...

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Mizubayashi, Wataru; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Masahara, Meishoku

2014-01-01

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (Vt) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal-oxide-nitride-oxide-silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial Vt roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (Lg) is scaled down to 46 nm or less.

Radiation-Hardened Solid-State Drive

NASA Technical Reports Server (NTRS)

Sheldon, Douglas J.

2010-01-01

A method is provided for a radiationhardened (rad-hard) solid-state drive for space mission memory applications by combining rad-hard and commercial off-the-shelf (COTS) non-volatile memories (NVMs) into a hybrid architecture. The architecture is controlled by a rad-hard ASIC (application specific integrated circuit) or a FPGA (field programmable gate array). Specific error handling and data management protocols are developed for use in a rad-hard environment. The rad-hard memories are smaller in overall memory density, but are used to control and manage radiation-induced errors in the main, and much larger density, non-rad-hard COTS memory devices. Small amounts of rad-hard memory are used as error buffers and temporary caches for radiation-induced errors in the large COTS memories. The rad-hard ASIC/FPGA implements a variety of error-handling protocols to manage these radiation-induced errors. The large COTS memory is triplicated for protection, and CRC-based counters are calculated for sub-areas in each COTS NVM array. These counters are stored in the rad-hard non-volatile memory. Through monitoring, rewriting, regeneration, triplication, and long-term storage, radiation-induced errors in the large NV memory are managed. The rad-hard ASIC/FPGA also interfaces with the external computer buses.

Optimal proximity correction: application for flash memory design

NASA Astrophysics Data System (ADS)

Chen, Y. O.; Huang, D. L.; Sung, K. T.; Chiang, J. J.; Yu, M.; Teng, F.; Chu, Lung; Rey, Juan C.; Bernard, Douglas A.; Li, Jiangwei; Li, Junling; Moroz, V.; Boksha, Victor V.

1998-06-01

Proximity Correction is the technology for which the most of IC manufacturers are committed already. The final intended result of correction is affected by many factors other than the optical characteristics of the mask-stepper system, such as photoresist exposure, post-exposure bake and development parameters, etch selectivity and anisotropy, and underlying topography. The most advanced industry and research groups already reported immediate need to consider wafer topography as one of the major components during a Proximity Correction procedure. In the present work we are discussing the corners rounding effect (which eventually cause electrical leakage) observed for the elements of Poly2 layer for a Flash Memory Design. It was found that the rounding originated by three- dimensional effects due to variation of photoresist thickness resulting from the non-planar substrate. Our major goal was to understand the reasons and correct corner rounding. As a result of this work highly effective layout correction methodology was demonstrated and manufacturable Depth Of Focus was achieved. Another purpose of the work was to demonstrate complete integration flow for a Flash Memory Design based on photolithography; deposition/etch; ion implantation/oxidation/diffusion; and device simulators.

Some Improvements in Utilization of Flash Memory Devices

NASA Technical Reports Server (NTRS)

Gender, Thomas K.; Chow, James; Ott, William E.

2009-01-01

Two developments improve the utilization of flash memory devices in the face of the following limitations: (1) a flash write element (page) differs in size from a flash erase element (block), (2) a block must be erased before its is rewritten, (3) lifetime of a flash memory is typically limited to about 1,000,000 erases, (4) as many as 2 percent of the blocks of a given device may fail before the expected end of its life, and (5) to ensure reliability of reading and writing, power must not be interrupted during minimum specified reading and writing times. The first development comprises interrelated software components that regulate reading, writing, and erasure operations to minimize migration of data and unevenness in wear; perform erasures during idle times; quickly make erased blocks available for writing; detect and report failed blocks; maintain the overall state of a flash memory to satisfy real-time performance requirements; and detect and initialize a new flash memory device. The second development is a combination of hardware and software that senses the failure of a main power supply and draws power from a capacitive storage circuit designed to hold enough energy to sustain operation until reading or writing is completed.

Resistive switching characteristics of polymer non-volatile memory devices in a scalable via-hole structure.

PubMed

Kim, Tae-Wook; Choi, Hyejung; Oh, Seung-Hwan; Jo, Minseok; Wang, Gunuk; Cho, Byungjin; Kim, Dong-Yu; Hwang, Hyunsang; Lee, Takhee

2009-01-14

The resistive switching characteristics of polyfluorene-derivative polymer material in a sub-micron scale via-hole device structure were investigated. The scalable via-hole sub-microstructure was fabricated using an e-beam lithographic technique. The polymer non-volatile memory devices varied in size from 40 x 40 microm(2) to 200 x 200 nm(2). From the scaling of junction size, the memory mechanism can be attributed to the space-charge-limited current with filamentary conduction. Sub-micron scale polymer memory devices showed excellent resistive switching behaviours such as a large ON/OFF ratio (I(ON)/I(OFF) approximately 10(4)), excellent device-to-device switching uniformity, good sweep endurance, and good retention times (more than 10,000 s). The successful operation of sub-micron scale memory devices of our polyfluorene-derivative polymer shows promise to fabricate high-density polymer memory devices.

Performance analysis of three-dimensional-triple-level cell and two-dimensional-multi-level cell NAND flash hybrid solid-state drives

NASA Astrophysics Data System (ADS)

Sakaki, Yukiya; Yamada, Tomoaki; Matsui, Chihiro; Yamaga, Yusuke; Takeuchi, Ken

2018-04-01

In order to improve performance of solid-state drives (SSDs), hybrid SSDs have been proposed. Hybrid SSDs consist of more than two types of NAND flash memories or NAND flash memories and storage-class memories (SCMs). However, the cost of hybrid SSDs adopting SCMs is more expensive than that of NAND flash only SSDs because of the high bit cost of SCMs. This paper proposes unique hybrid SSDs with two-dimensional (2D) horizontal multi-level cell (MLC)/three-dimensional (3D) vertical triple-level cell (TLC) NAND flash memories to achieve higher cost-performance. The 2D-MLC/3D-TLC hybrid SSD achieves up to 31% higher performance than the conventional 2D-MLC/2D-TLC hybrid SSD. The factors of different performance between the proposed hybrid SSD and the conventional hybrid SSD are analyzed by changing its block size, read/write/erase latencies, and write unit of 3D-TLC NAND flash memory, by means of a transaction-level modeling simulator.

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

NASA Astrophysics Data System (ADS)

Nedic, Stanko; Tea Chun, Young; Hong, Woong-Ki; Chu, Daping; Welland, Mark

2014-01-01

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ˜16.5 V, a high drain current on/off ratio of ˜105, a gate leakage current below ˜300 pA, and excellent retention characteristics for over 104 s.

Within-wafer CD variation induced by wafer shape

NASA Astrophysics Data System (ADS)

Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

2016-03-01

In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer PEB temperature non-uniformity attributed to wafer warpage is uncorrectable, and the photo-resist profile variation is believed to affect across-wafer etch bias uniformity to some degree.

Flash pyrolysis of coal, coal maceral, and coal-derived pyrite with on-line characterization of volatile sulfur compounds

USGS Publications Warehouse

Chou, I.-Ming; Lake, M.A.; Griffin, R.A.

1988-01-01

A Pyroprobe flash pyrolysis-gas chromatograph equipped with a flame photometric detector was used to study volatile sulfur compounds produced during the thermal decomposition of Illinois coal, coal macerals and coal-derived pyrite. Maximum evolution of volatile organic sulfur compounds from all coal samples occurred at a temperature of approximately 700??C. At this temperature, the evolution of thiophene, its alkyl isomers, and short-chain dialkyl sulfide compounds relative to the evolution of benzothiophene and dibenzothiophene compounds was greater from coal high in organic sulfur than from coal low in organic sulfur. The variation in the evolution of sulfur compounds observed for three separate coal macerals (exinite, vitrinite, and inertinite) was similar to that observed for whole coal samples. However, the variation trend for the macerals was much more pronounced. Decomposition of coal-derived pyrite with the evolution of elemental sulfur was detected at a temperature greater than 700??C. The results of this study indicated that the gas chromotographic profile of the volatile sulfur compounds produced during flash pyrolysis of coals and coal macerals varied as a function of the amount of organic sulfur that occurred in the samples. Characterization of these volatile sulfur compounds provides a better understanding of the behavior of sulfur in coal during the thermolysis process, which could be incorporated in the design for coal cleaning using flash pyrolysis techniques. ?? 1988.

Co-design of application software and NAND flash memory in solid-state drive for relational database storage system

NASA Astrophysics Data System (ADS)

Miyaji, Kousuke; Sun, Chao; Soga, Ayumi; Takeuchi, Ken

2014-01-01

A relational database management system (RDBMS) is designed based on NAND flash solid-state drive (SSD) for storage. By vertically integrating the storage engine (SE) and the flash translation layer (FTL), system performance is maximized and the internal SSD overhead is minimized. The proposed RDBMS SE utilizes physical information about the NAND flash memory which is supplied from the FTL. The query operation is also optimized for SSD. By these treatments, page-copy-less garbage collection is achieved and data fragmentation in the NAND flash memory is suppressed. As a result, RDBMS performance increases by 3.8 times, power consumption of SSD decreases by 46% and SSD life time is increased by 61%. The effectiveness of the proposed scheme increases with larger erase block sizes, which matches the future scaling trend of three-dimensional (3D-) NAND flash memories. The preferable row data size of the proposed scheme is below 500 byte for 16 kbyte page size.

Non-exponential resistive switching in Ag2S memristors: a key to nanometer-scale non-volatile memory devices.

PubMed

Gubicza, Agnes; Csontos, Miklós; Halbritter, András; Mihály, György

2015-03-14

The dynamics of resistive switchings in nanometer-scale metallic junctions formed between an inert metallic tip and an Ag film covered by a thin Ag2S layer are investigated. Our thorough experimental analysis and numerical simulations revealed that the resistance change upon a switching bias voltage pulse exhibits a strongly non-exponential behaviour yielding markedly different response times at different bias levels. Our results demonstrate the merits of Ag2S nanojunctions as nanometer-scale non-volatile memory cells with stable switching ratios, high endurance as well as fast response to write/erase, and an outstanding stability against read operations at technologically optimal bias and current levels.

Method for programming a flash memory

DOEpatents

Brosky, Alexander R.; Locke, William N.; Maher, Conrado M.

2016-08-23

A method of programming a flash memory is described. The method includes partitioning a flash memory into a first group having a first level of write-protection, a second group having a second level of write-protection, and a third group having a third level of write-protection. The write-protection of the second and third groups is disabled using an installation adapter. The third group is programmed using a Software Installation Device.

Multi-floor cascading ferroelectric nanostructures: multiple data writing-based multi-level non-volatile memory devices.

PubMed

Hyun, Seung; Kwon, Owoong; Lee, Bom-Yi; Seol, Daehee; Park, Beomjin; Lee, Jae Yong; Lee, Ju Hyun; Kim, Yunseok; Kim, Jin Kon

2016-01-21

Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process.

Quantitative Analysis of Charge Injection and Discharging of Si Nanocrystals and Arrays by Electrostatic Force Microscopy

NASA Technical Reports Server (NTRS)

Bell, L. D.; Boer, E.; Ostraat, M.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.

2000-01-01

NASA requirements for computing and memory for microspacecraft emphasize high density, low power, small size, and radiation hardness. The distributed nature of storage elements in nanocrystal floating-gate memories leads to intrinsic fault tolerance and radiation hardness. Conventional floating-gate non-volatile memories are more susceptible to radiation damage. Nanocrystal-based memories also offer the possibility of faster, lower power operation. In the pursuit of filling these requirements, the following tasks have been accomplished: (1) Si nanocrystal charging has been accomplished with conducting-tip AFM; (2) Both individual nanocrystals on an oxide surface and nanocrystals formed by implantation have been charged; (3) Discharging is consistent with tunneling through a field-lowered oxide barrier; (4) Modeling of the response of the AFM to trapped charge has allowed estimation of the quantity of trapped charge; and (5) Initial attempts to fabricate competitive nanocrystal non-volatile memories have been extremely successful.

Effect of Radiation Exposure on the Retention of Commercial NAND Flash Memory

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; Chen, D.; Friendlich, M.; Carts, M. A.; Seidleck, C. M.; LaBel, K. A.

2011-01-01

We have compared the data retention of irradiated commercial NAND flash memories with that of unirradiated controls. Under some circumstanc es, radiation exposure has a significant effect on the retention of f lash memories.

Ensuring the Trust of NAND Flash Memory: Going Beyond the Published Interface

DTIC Science & Technology

2016-03-17

Ensuring the Trust of NAND Flash Memory: Going Beyond the Published Interface Austin H. Roach, Matthew J. Gadlage, James D. Ingalls, Aaron...reliability and trust of memories is very important, but because of incomplete documentation provided by commercial vendors and a lack of low-level...shown here that useful information about the trust and reliability of COTS NAND Flash components can be obtained by going beyond the standard product

Messier: A Detailed NVM-Based DIMM Model for the SST Simulation Framework.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Awad, Amro; Voskuilen, Gwendolyn Renae; Rodrigues, Arun F.

2017-02-01

DRAM technology is the main building block of main memory, however, DRAM scaling is becoming very challenging. The main issues for DRAM scaling are the increasing error rates with each new generation, the geometric and physical constraints of scaling the capacitor part of the DRAM cells, and the high power consumption caused by the continuous need for refreshing cell values. At the same time, emerging Non- Volatile Memory (NVM) technologies, such as Phase-Change Memory (PCM), are emerging as promising replacements for DRAM. NVMs, when compared to current technologies e.g., NAND-based ash, have latencies comparable to DRAM. Additionally, NVMs are non-volatile,more » which eliminates the need for refresh power and enables persistent memory applications. Finally, NVMs have promising densities and the potential for multi-level cell (MLC) storage.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fernandes, Ana; Pereira, Rita C.; Sousa, Jorge

The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memoriesmore » for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)« less

A hybrid ferroelectric-flash memory cells

NASA Astrophysics Data System (ADS)

Park, Jae Hyo; Byun, Chang Woo; Seok, Ki Hwan; Kim, Hyung Yoon; Chae, Hee Jae; Lee, Sol Kyu; Son, Se Wan; Ahn, Donghwan; Joo, Seung Ki

2014-09-01

A ferroelectric-flash (F-flash) memory cells having a metal-ferroelectric-nitride-oxynitride-silicon structure are demonstrated, and the ferroelectric materials were perovskite-dominated Pb(Zr,Ti)O3 (PZT) crystallized by Pt gate electrode. The PZT thin-film as a blocking layer improves electrical and memorial performance where programming and erasing mechanism are different from the metal-ferroelectric-insulator-semiconductor device or the conventional silicon-oxide-nitride-oxide-silicon device. F-flash cells exhibit not only the excellent electrical transistor performance, having 442.7 cm2 V-1 s-1 of field-effect mobility, 190 mV dec-1 of substhreshold slope, and 8 × 105 on/off drain current ratio, but also a high reliable memory characteristics, having a large memory window (6.5 V), low-operating voltage (0 to -5 V), faster P/E switching speed (50/500 μs), long retention time (>10 years), and excellent fatigue P/E cycle (>105) due to the boosting effect, amplification effect, and energy band distortion of nitride from the large polarization. All these characteristics correspond to the best performances among conventional flash cells reported so far.

Large-area, flexible imaging arrays constructed by light-charge organic memories

PubMed Central

Zhang, Lei; Wu, Ti; Guo, Yunlong; Zhao, Yan; Sun, Xiangnan; Wen, Yugeng; Yu, Gui; Liu, Yunqi

2013-01-01

Existing organic imaging circuits, which offer attractive benefits of light weight, low cost and flexibility, are exclusively based on phototransistor or photodiode arrays. One shortcoming of these photo-sensors is that the light signal should keep invariant throughout the whole pixel-addressing and reading process. As a feasible solution, we synthesized a new charge storage molecule and embedded it into a device, which we call light-charge organic memory (LCOM). In LCOM, the functionalities of photo-sensor and non-volatile memory are integrated. Thanks to the deliberate engineering of electronic structure and self-organization process at the interface, 92% of the stored charges, which are linearly controlled by the quantity of light, retain after 20000 s. The stored charges can also be non-destructively read and erased by a simple voltage program. These results pave the way to large-area, flexible imaging circuits and demonstrate a bright future of small molecular materials in non-volatile memory. PMID:23326636

Scaling Trends and Tradeoffs between Short Channel Effect and Channel Boosting Characteristics in Sub-20 nm Bulk/Silicon-on-Insulator NAND Flash Memory

NASA Astrophysics Data System (ADS)

Miyaji, Kousuke; Hung, Chinglin; Takeuchi, Ken

2012-04-01

The scaling trends and limitation in sub-20 nm a bulk and silicon-on-insulator (SOI) NAND flash memory is studied by the three-dimensional (3D) device simulation focusing on short channel effects (SCE), channel boost leakage and channel voltage boosting characteristics during the program-inhibit operation. Although increasing punch-through stopper doping concentration is effective for suppressing SCE in bulk NAND cells, the generation of junction leakage becomes serious. On the other hand, SCE can be suppressed by thinning the buried oxide (BOX) in SOI NAND cells. However, the boosted channel voltage decreases by the higher BOX capacitance. It is concluded that the scaling limitation is dominated by the junction leakage and channel boosting capability for bulk and SOI NAND flash cells, respectively, and the scaling limit is decreased to 9 nm using SOI NAND flash memory cells from 13 nm in bulk NAND flash memory cells.

Analysis on applicable error-correcting code strength of storage class memory and NAND flash in hybrid storage

NASA Astrophysics Data System (ADS)

Matsui, Chihiro; Kinoshita, Reika; Takeuchi, Ken

2018-04-01

A hybrid of storage class memory (SCM) and NAND flash is a promising technology for high performance storage. Error correction is inevitable on SCM and NAND flash because their bit error rate (BER) increases with write/erase (W/E) cycles, data retention, and program/read disturb. In addition, scaling and multi-level cell technologies increase BER. However, error-correcting code (ECC) degrades storage performance because of extra memory reading and encoding/decoding time. Therefore, applicable ECC strength of SCM and NAND flash is evaluated independently by fixing ECC strength of one memory in the hybrid storage. As a result, weak BCH ECC with small correctable bit is recommended for the hybrid storage with large SCM capacity because SCM is accessed frequently. In contrast, strong and long-latency LDPC ECC can be applied to NAND flash in the hybrid storage with large SCM capacity because large-capacity SCM improves the storage performance.

Electrical and ferroelectric properties of RF sputtered PZT/SBN on silicon for non-volatile memory applications

NASA Astrophysics Data System (ADS)

Singh, Prashant; Jha, Rajesh Kumar; Singh, Rajat Kumar; Singh, B. R.

2018-02-01

We report the integration of multilayer ferroelectric film deposited by RF magnetron sputtering and explore the electrical characteristics for its application as the gate of ferroelectric field effect transistor for non-volatile memories. PZT (Pb[Zr0.35Ti0.65]O3) and SBN (SrBi2Nb2O9) ferroelectric materials were selected for the stack fabrication due to their large polarization and fatigue free properties respectively. Electrical characterization has been carried out to obtain memory window, leakage current density, PUND and endurance characteristics. Fabricated multilayer ferroelectric film capacitor structure shows large memory window of 17.73 V and leakage current density of the order 10-6 A cm-2 for the voltage sweep of -30 to +30 V. This multilayer gate stack of PZT/SBN shows promising endurance property with no degradation in the remnant polarization for the read/write iteration cycles upto 108.

Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

NASA Astrophysics Data System (ADS)

Riente, Fabrizio; Ziemys, Grazvydas; Mattersdorfer, Clemens; Boche, Silke; Turvani, Giovanna; Raberg, Wolfgang; Luber, Sebastian; Breitkreutz-v. Gamm, Stephan

2017-05-01

Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML) is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

Non-volatile magnetic random access memory

NASA Technical Reports Server (NTRS)

Katti, Romney R. (Inventor); Stadler, Henry L. (Inventor); Wu, Jiin-Chuan (Inventor)

1994-01-01

Improvements are made in a non-volatile magnetic random access memory. Such a memory is comprised of an array of unit cells, each having a Hall-effect sensor and a thin-film magnetic element made of material having an in-plane, uniaxial anisotropy and in-plane, bipolar remanent magnetization states. The Hall-effect sensor is made more sensitive by using a 1 m thick molecular beam epitaxy grown InAs layer on a silicon substrate by employing a GaAs/AlGaAs/InAlAs superlattice buffering layer. One improvement avoids current shunting problems of matrix architecture. Another improvement reduces the required magnetizing current for the micromagnets. Another improvement relates to the use of GaAs technology wherein high electron-mobility GaAs MESFETs provide faster switching times. Still another improvement relates to a method for configuring the invention as a three-dimensional random access memory.

Electrical reliability, multilevel data storage and mechanical stability of MoS2-PMMA nanocomposite-based non-volatile memory device

NASA Astrophysics Data System (ADS)

Bhattacharjee, Snigdha; Sarkar, Pranab Kumar; Prajapat, Manoj; Roy, Asim

2017-07-01

Molybdenum disulfide (MoS2) is of great interest for its applicability in various optoelectronic devices. Here we report the resistive switching properties of polymethylmethacrylate embedding MoS2 nano-crystals. The devices are developed on an ITO-coated PET substrate with copper as the top electrode. Systematic evaluation of resistive switching parameters, on the basis of MoS2 content, suggests non-volatile memory characteristics. A decent ON/OFF ratio, high retention time and long endurance of 3  ×  103, 105 s and 105 cycles are respectively recorded in a device with 1 weight percent (wt%) of MoS2. The bending cyclic measurements confirm the flexibility of the memory devices with good electrical reliability as well as mechanical stability. In addition, multilevel storage has been demonstrated by controlling the current compliance and span of voltage sweeping in the memory device.

Highly Stretchable Non-volatile Nylon Thread Memory

NASA Astrophysics Data System (ADS)

Kang, Ting-Kuo

2016-04-01

Integration of electronic elements into textiles, to afford e-textiles, can provide an ideal platform for the development of lightweight, thin, flexible, and stretchable e-textiles. This approach will enable us to meet the demands of the rapidly growing market of wearable-electronics on arbitrary non-conventional substrates. However the actual integration of the e-textiles that undergo mechanical deformations during both assembly and daily wear or satisfy the requirements of the low-end applications, remains a challenge. Resistive memory elements can also be fabricated onto a nylon thread (NT) for e-textile applications. In this study, a simple dip-and-dry process using graphene-PEDOT:PSS (poly(3,4-ethylenedioxythiophene) polystyrene sulfonate) ink is proposed for the fabrication of a highly stretchable non-volatile NT memory. The NT memory appears to have typical write-once-read-many-times characteristics. The results show that an ON/OFF ratio of approximately 103 is maintained for a retention time of 106 s. Furthermore, a highly stretchable strain and a long-term digital-storage capability of the ON-OFF-ON states are demonstrated in the NT memory. The actual integration of the knitted NT memories into textiles will enable new design possibilities for low-cost and large-area e-textile memory applications.

Static Behavior of Chalcogenide Based Programmable Metallization Cells

NASA Astrophysics Data System (ADS)

Rajabi, Saba

Nonvolatile memory (NVM) technologies have been an integral part of electronic systems for the past 30 years. The ideal non-volatile memory have minimal physical size, energy usage, and cost while having maximal speed, capacity, retention time, and radiation hardness. A promising candidate for next-generation memory is ion-conducting bridging RAM which is referred to as programmable metallization cell (PMC), conductive bridge RAM (CBRAM), or electrochemical metallization memory (ECM), which is likely to surpass flash memory in all the ideal memory characteristics. A comprehensive physics-based model is needed to completely understand PMC operation and assist in design optimization. To advance the PMC modeling effort, this thesis presents a precise physical model parameterizing materials associated with both ion-rich and ion-poor layers of the PMC's solid electrolyte, so that captures the static electrical behavior of the PMC in both its low-resistance on-state (LRS) and high resistance off-state (HRS). The experimental data is measured from a chalcogenide glass PMC designed and manufactured at ASU. The static on- and off-state resistance of a PMC device composed of a layered (Ag-rich/Ag-poor) Ge30Se70 ChG film is characterized and modeled using three dimensional simulation code written in Silvaco Atlas finite element analysis software. Calibrating the model to experimental data enables the extraction of device parameters such as material bandgaps, workfunctions, density of states, carrier mobilities, dielectric constants, and affinities. The sensitivity of our modeled PMC to the variation of its prominent achieved material parameters is examined on the HRS and LRS impedance behavior. The obtained accurate set of material parameters for both Ag-rich and Ag-poor ChG systems and process variation verification on electrical characteristics enables greater fidelity in PMC device simulation, which significantly enhances our ability to understand the underlying physics of ChG-based resistive switching memory.

Space Radiation Effects in Advanced Flash Memories

NASA Technical Reports Server (NTRS)

Johnston, A. H.

2001-01-01

Memory storage requirements in space systems have steadily increased, much like storage requirements in terrestrial systems. Large arrays of dynamic memories (DRAMs) have been used in solid-state recorders, relying on a combination of shielding and error-detection-and correction (EDAC) to overcome the extreme sensitivity of DRAMs to space radiation. For example, a 2-Gbit memory (with 4-Mb DRAMs) used on the Clementine mission functioned perfectly during its moon mapping mission, in spite of an average of 71 memory bit flips per day from heavy ions. Although EDAC worked well with older types of memory circuits, newer DRAMs use extremely complex internal architectures which has made it increasingly difficult to implement EDAC. Some newer DRAMs have also exhibited catastrophic latchup. Flash memories are an intriguing alternative to DRAMs because of their nonvolatile storage and extremely high storage density, particularly for applications where writing is done relatively infrequently. This paper discusses radiation effects in advanced flash memories, including general observations on scaling and architecture as well as the specific experience obtained at the Jet Propulsion Laboratory in evaluating high-density flash memories for use on the NASA mission to Europa, one of Jupiter's moons. This particular mission must pass through the Jovian radiation belts, which imposes a very demanding radiation requirement.

Long-term memory and volatility clustering in high-frequency price changes

NASA Astrophysics Data System (ADS)

oh, Gabjin; Kim, Seunghwan; Eom, Cheoljun

2008-02-01

We studied the long-term memory in diverse stock market indices and foreign exchange rates using Detrended Fluctuation Analysis (DFA). For all high-frequency market data studied, no significant long-term memory property was detected in the return series, while a strong long-term memory property was found in the volatility time series. The possible causes of the long-term memory property were investigated using the return data filtered by the AR(1) model, reflecting the short-term memory property, the GARCH(1,1) model, reflecting the volatility clustering property, and the FIGARCH model, reflecting the long-term memory property of the volatility time series. The memory effect in the AR(1) filtered return and volatility time series remained unchanged, while the long-term memory property diminished significantly in the volatility series of the GARCH(1,1) filtered data. Notably, there is no long-term memory property, when we eliminate the long-term memory property of volatility by the FIGARCH model. For all data used, although the Hurst exponents of the volatility time series changed considerably over time, those of the time series with the volatility clustering effect removed diminish significantly. Our results imply that the long-term memory property of the volatility time series can be attributed to the volatility clustering observed in the financial time series.

FPGA Flash Memory High Speed Data Acquisition

NASA Technical Reports Server (NTRS)

Gonzalez, April

2013-01-01

The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

Advanced error-prediction LDPC with temperature compensation for highly reliable SSDs

NASA Astrophysics Data System (ADS)

Tokutomi, Tsukasa; Tanakamaru, Shuhei; Iwasaki, Tomoko Ogura; Takeuchi, Ken

2015-09-01

To improve the reliability of NAND Flash memory based solid-state drives (SSDs), error-prediction LDPC (EP-LDPC) has been proposed for multi-level-cell (MLC) NAND Flash memory (Tanakamaru et al., 2012, 2013), which is effective for long retention times. However, EP-LDPC is not as effective for triple-level cell (TLC) NAND Flash memory, because TLC NAND Flash has higher error rates and is more sensitive to program-disturb error. Therefore, advanced error-prediction LDPC (AEP-LDPC) has been proposed for TLC NAND Flash memory (Tokutomi et al., 2014). AEP-LDPC can correct errors more accurately by precisely describing the error phenomena. In this paper, the effects of AEP-LDPC are investigated in a 2×nm TLC NAND Flash memory with temperature characterization. Compared with LDPC-with-BER-only, the SSD's data-retention time is increased by 3.4× and 9.5× at room-temperature (RT) and 85 °C, respectively. Similarly, the acceptable BER is increased by 1.8× and 2.3×, respectively. Moreover, AEP-LDPC can correct errors with pre-determined tables made at higher temperatures to shorten the measurement time before shipping. Furthermore, it is found that one table can cover behavior over a range of temperatures in AEP-LDPC. As a result, the total table size can be reduced to 777 kBytes, which makes this approach more practical.

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

NASA Astrophysics Data System (ADS)

Jovanović, B.; Brum, R. M.; Torres, L.

2014-04-01

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2012

NASA Technical Reports Server (NTRS)

Irom, Farokh; Allen, Gregory R.

2012-01-01

The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.

Fast neutron irradiation tests of flash memories used in space environment at the ISIS spallation neutron source

NASA Astrophysics Data System (ADS)

Andreani, C.; Senesi, R.; Paccagnella, A.; Bagatin, M.; Gerardin, S.; Cazzaniga, C.; Frost, C. D.; Picozza, P.; Gorini, G.; Mancini, R.; Sarno, M.

2018-02-01

This paper presents a neutron accelerated study of soft errors in advanced electronic devices used in space missions, i.e. Flash memories performed at the ChipIr and VESUVIO beam lines at the ISIS spallation neutron source. The two neutron beam lines are set up to mimic the space environment spectra and allow neutron irradiation tests on Flash memories in the neutron energy range above 10 MeV and up to 800 MeV. The ISIS neutron energy spectrum is similar to the one occurring in the atmospheric as well as in space and planetary environments, with intensity enhancements varying in the range 108- 10 9 and 106- 10 7 respectively. Such conditions are suitable for the characterization of the atmospheric, space and planetary neutron radiation environments, and are directly applicable for accelerated tests of electronic components as demonstrated here in benchmark measurements performed on flash memories.

Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

NASA Astrophysics Data System (ADS)

Ando, K.; Fujita, S.; Ito, J.; Yuasa, S.; Suzuki, Y.; Nakatani, Y.; Miyazaki, T.; Yoda, H.

2014-05-01

Most parts of present computer systems are made of volatile devices, and the power to supply them to avoid information loss causes huge energy losses. We can eliminate this meaningless energy loss by utilizing the non-volatile function of advanced spin-transfer torque magnetoresistive random-access memory (STT-MRAM) technology and create a new type of computer, i.e., normally off computers. Critical tasks to achieve normally off computers are implementations of STT-MRAM technologies in the main memory and low-level cache memories. STT-MRAM technology for applications to the main memory has been successfully developed by using perpendicular STT-MRAMs, and faster STT-MRAM technologies for applications to the cache memory are now being developed. The present status of STT-MRAMs and challenges that remain for normally off computers are discussed.

Multi-floor cascading ferroelectric nanostructures: multiple data writing-based multi-level non-volatile memory devices

NASA Astrophysics Data System (ADS)

Hyun, Seung; Kwon, Owoong; Lee, Bom-Yi; Seol, Daehee; Park, Beomjin; Lee, Jae Yong; Lee, Ju Hyun; Kim, Yunseok; Kim, Jin Kon

2016-01-01

Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process.Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr07377d

Flash Memory Reliability: Read, Program, and Erase Latency Versus Endurance Cycling

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2010-01-01

This report documents the efforts and results of the fiscal year (FY) 2010 NASA Electronic Parts and Packaging Program (NEPP) task for nonvolatile memory (NVM) reliability. This year's focus was to measure latency (read, program, and erase) of NAND Flash memories and determine how these parameters drift with erase/program/read endurance cycling.

Asymmetric programming: a highly reliable metadata allocation strategy for MLC NAND flash memory-based sensor systems.

PubMed

Huang, Min; Liu, Zhaoqing; Qiao, Liyan

2014-10-10

While the NAND flash memory is widely used as the storage medium in modern sensor systems, the aggressive shrinking of process geometry and an increase in the number of bits stored in each memory cell will inevitably degrade the reliability of NAND flash memory. In particular, it's critical to enhance metadata reliability, which occupies only a small portion of the storage space, but maintains the critical information of the file system and the address translations of the storage system. Metadata damage will cause the system to crash or a large amount of data to be lost. This paper presents Asymmetric Programming, a highly reliable metadata allocation strategy for MLC NAND flash memory storage systems. Our technique exploits for the first time the property of the multi-page architecture of MLC NAND flash memory to improve the reliability of metadata. The basic idea is to keep metadata in most significant bit (MSB) pages which are more reliable than least significant bit (LSB) pages. Thus, we can achieve relatively low bit error rates for metadata. Based on this idea, we propose two strategies to optimize address mapping and garbage collection. We have implemented Asymmetric Programming on a real hardware platform. The experimental results show that Asymmetric Programming can achieve a reduction in the number of page errors of up to 99.05% with the baseline error correction scheme.

Asymmetric Programming: A Highly Reliable Metadata Allocation Strategy for MLC NAND Flash Memory-Based Sensor Systems

PubMed Central

Huang, Min; Liu, Zhaoqing; Qiao, Liyan

2014-01-01

While the NAND flash memory is widely used as the storage medium in modern sensor systems, the aggressive shrinking of process geometry and an increase in the number of bits stored in each memory cell will inevitably degrade the reliability of NAND flash memory. In particular, it's critical to enhance metadata reliability, which occupies only a small portion of the storage space, but maintains the critical information of the file system and the address translations of the storage system. Metadata damage will cause the system to crash or a large amount of data to be lost. This paper presents Asymmetric Programming, a highly reliable metadata allocation strategy for MLC NAND flash memory storage systems. Our technique exploits for the first time the property of the multi-page architecture of MLC NAND flash memory to improve the reliability of metadata. The basic idea is to keep metadata in most significant bit (MSB) pages which are more reliable than least significant bit (LSB) pages. Thus, we can achieve relatively low bit error rates for metadata. Based on this idea, we propose two strategies to optimize address mapping and garbage collection. We have implemented Asymmetric Programming on a real hardware platform. The experimental results show that Asymmetric Programming can achieve a reduction in the number of page errors of up to 99.05% with the baseline error correction scheme. PMID:25310473

Error Characterization and Mitigation for 16Nm MLC NAND Flash Memory Under Total Ionizing Dose Effect

NASA Technical Reports Server (NTRS)

Li, Yue (Inventor); Bruck, Jehoshua (Inventor)

2018-01-01

A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count.

Design rules for phase-change materials in data storage applications.

PubMed

Lencer, Dominic; Salinga, Martin; Wuttig, Matthias

2011-05-10

Phase-change materials can rapidly and reversibly be switched between an amorphous and a crystalline phase. Since both phases are characterized by very different optical and electrical properties, these materials can be employed for rewritable optical and electrical data storage. Hence, there are considerable efforts to identify suitable materials, and to optimize them with respect to specific applications. Design rules that can explain why the materials identified so far enable phase-change based devices would hence be very beneficial. This article describes materials that have been successfully employed and dicusses common features regarding both typical structures and bonding mechanisms. It is shown that typical structural motifs and electronic properties can be found in the crystalline state that are indicative for resonant bonding, from which the employed contrast originates. The occurence of resonance is linked to the composition, thus providing a design rule for phase-change materials. This understanding helps to unravel characteristic properties such as electrical and thermal conductivity which are discussed in the subsequent section. Then, turning to the transition kinetics between the phases, the current understanding and modeling of the processes of amorphization and crystallization are discussed. Finally, present approaches for improved high-capacity optical discs and fast non-volatile electrical memories, that hold the potential to succeed present-day's Flash memory, are presented. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Investigation of Current Spike Phenomena During Heavy Ion Irradiation of NAND Flash Memories

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; Berg, Melanie; Friendlich, Mark; Wilcox, Ted; Seidleck, Christina; LaBel, Kenneth A.; Irom, Farokh; Buchner, Steven P.; McMorrow, Dale; Mavis, David G.;

Blackcomb: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schreiber, Robert

Summary of technical results of Blackcomb Memory Devices We explored various different memory technologies (STTRAM, PCRAM, FeRAM, and ReRAM). The progress can be classified into three categories, below. Modeling and Tool Releases Various modeling tools have been developed over the last decade to help in the design of SRAM or DRAM-based memory hierarchies. To explore new design opportunities that NVM technologies can bring to the designers, we have developed similar high-level models for NVM, including PCRAMsim [Dong 2009], NVSim [Dong 2012], and NVMain [Poremba 2012]. NVSim is a circuit-level model for NVM performance, energy, and area estimation, which supports variousmore » NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies. On the other side, NVMain is a cycle accurate main memory simulator designed to simulate emerging nonvolatile memories at the architectural level. We have released these models as open source tools and provided contiguous support to them. We also proposed PS3-RAM, which is a fast, portable and scalable statistical STT-RAM reliability analysis model [Wen 2012]. Design Space Exploration and Optimization With the support of these models, we explore different device/circuit optimization techniques. For example, in [Niu 2012a] we studied the power reduction technique for the application of ECC scheme in ReRAM designs and proposed to use ECC code to relax the BER (Bit Error Rate) requirement of a single memory to improve the write energy consumption and latency for both 1T1R and cross-point ReRAM designs. In [Xu 2011], we proposed a methodology to design STT-RAM for different optimization goals such as read performance, write performance and write energy by leveraging the trade-off between write current and write time of MTJ. We also studied the tradeoffs in building a reliable crosspoint ReRAM array [Niu 2012b]. We have conducted an in depth analysis of the circuit and system level design implications of multi-layer cross-point Resistive RAM (MLCReRAM) from performance, power and reliability perspectives [Xu 2013]. The objective of this study is to understand the design trade-offs of this technology with respect to the MLC Phase Change Memory (MLCPCM).Our MLC ReRAM design at the circuit and system levels indicates that different resistance allocation schemes, programming strategies, peripheral designs, and material selections profoundly affect the area, latency, power, and reliability of MLC ReRAM. Based on this analysis, we conduct two case studies: first we compare MLC ReRAM design against MLC phase-change memory (PCM) and multi-layer cross-point ReRAM design, and point out why multi-level ReRAM is appealing; second we further explore the design space for MLC ReRAM. Architecture and Application We explored hybrid checkpointing using phase-change memory for future exascale systems [Dong 2011] and showed that the use of nonvolatile memory for local checkpointing significantly increases the number of faults covered by local checkpoints and reduces the probability of a global failure in the middle of a global checkpoint to less than 1%. We also proposed a technique called i2WAP to mitigate the write variations in NVM-based last-level cache for the improvement of the NVM lifetime [Wang 2013]. Our wear leveling technique attempts to work around the limitations of write endurance by arranging data access so that write operations can be distributed evenly across all the storage cells. During our intensive research on fault-tolerant NVM design, we found that ECC cannot effectively tolerate hard errors from limited write endurance and process imperfection. Therefore, we devised a novel Point and Discard (PAD) architecture in in [ 2012] as a hard-error-tolerant architecture for ReRAM-based Last Level Caches. PAD improves the lifetime of ReRAM caches by 1.6X-440X under different process variations without performance overhead in the system's early life. We have investigated the applicability of NVM for persistent memory design [Zhao 2013]. New byte addressable NVM enables fast persistent memory that allows in-memory persistent data objects to be updated with much higher throughput. Despite the significant improvement, the performance of these designs is only 50% of the native system with no persistence support, due to the logging or copy-on-write mechanisms used to update the persistent memory. A challenge in this approach is therefore how to efficiently enable atomic, consistent, and durable updates to ensure data persistence that survives application and/or system failures. We have designed a persistent memory system, called Klin, that can provide performance as close as that of the native system. The Klin design adopts a non-volatile cache and a non-volatile main memory for constructing a multi-versioned durable memory system, enabling atomic updates without logging or copy-on-write. Our evaluation shows that the proposed Kiln mechanism can achieve up to 2X of performance improvement to NVRAM-based persistent memory employing write-ahead logging. In addition, our design has numerous practical advantages: a simple and intuitive abstract interface, microarchitecture-level optimizations, fast recovery from failures, and no redundant writes to slow non-volatile storage media. The work was published in MICRO 2013 and received Best Paper Honorable Mentioned Award.« less

An Analysis of MARSIS Radar Flash Memory Data from Lunae Planum, Mars: Searching for Subsurface Structures.

NASA Astrophysics Data System (ADS)

Caprarelli, G.; Orosei, R.; Mastrogiuseppe, M.; Cartacci, M.

2017-12-01

Lunae Planum is a Martian plain measuring approximately 1000 km in width and 2000 km in length, centered at coordinates 294°E-11°N. MOLA elevations range from +2500 m to +500 m in the south, gently sloping northward to -500 m. The plain is part of a belt of terrains located between the southern highlands and the northern lowlands, that are transitional in character (e.g., by elevation, age and morphology). These transitional terrains are poorly understood, in part because of their relative lack of major geomorphological features. They record however a very significant part of Mars's geologic history. The most evident features on Lunae Planum's Hesperian surface are regularly spaced, longitudinally striking, wrinkle ridges. These indicate the presence of blind thrust faults cutting through thick stacks of layers of volcanic or sedimentary rocks. The presence of fluidized ejecta craters scattered all over the region suggests also the presence of ice or volatiles in the subsurface. In a preliminary study of Lunae Planum's subsurface we used the Mars Express ground penetrating radar MARSIS dataset [1], in order to detect reflectors that could indicate the presence of fault planes or layering. Standard radargrams however, provided no evidence of changes in value of dielectric constant that could indicate possible geologic discontinuities or stratification of physically diverse materials. We thus started a new investigation based on processing of raw MARSIS data. Here we report on the preliminary results of this study. We searched the MARSIS archive for raw data stored in flash memory. When operating with flash storage, the radar collects 2 frequency bands along-track covering a distance = 100-250 km, depending on the orbiter altitude [2]. We found flash memory data from 24 orbits over the area. We processed the data focusing radar returns in off-nadir directions, to maximize the likelihood of detecting sloping subsurface structures, including those striking parallel to the Mars Express sub-polar orbits. We plan to follow this study by applying a new processor aimed at improving the resolution and signal to noise ratio of the data. [1] Caprarelli et al. (2017), LPSC 48, 1720. [2] Watters et al. (2017), LPSC 48, 1693.

Multi-Level Bitmap Indexes for Flash Memory Storage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Kesheng; Madduri, Kamesh; Canon, Shane

2010-07-23

Due to their low access latency, high read speed, and power-efficient operation, flash memory storage devices are rapidly emerging as an attractive alternative to traditional magnetic storage devices. However, tests show that the most efficient indexing methods are not able to take advantage of the flash memory storage devices. In this paper, we present a set of multi-level bitmap indexes that can effectively take advantage of flash storage devices. These indexing methods use coarsely binned indexes to answer queries approximately, and then use finely binned indexes to refine the answers. Our new methods read significantly lower volumes of data atmore » the expense of an increased disk access count, thus taking full advantage of the improved read speed and low access latency of flash devices. To demonstrate the advantage of these new indexes, we measure their performance on a number of storage systems using a standard data warehousing benchmark called the Set Query Benchmark. We observe that multi-level strategies on flash drives are up to 3 times faster than traditional indexing strategies on magnetic disk drives.« less

Titanium-tungsten nanocrystals embedded in a SiO(2)/Al(2)O(3) gate dielectric stack for low-voltage operation in non-volatile memory.

PubMed

Yang, Shiqian; Wang, Qin; Zhang, Manhong; Long, Shibing; Liu, Jing; Liu, Ming

2010-06-18

Titanium-tungsten nanocrystals (NCs) were fabricated by a self-assembly rapid thermal annealing (RTA) process. Well isolated Ti(0.46)W(0.54) NCs were embedded in the gate dielectric stack of SiO(2)/Al(2)O(3). A metal-oxide-semiconductor (MOS) capacitor was fabricated to investigate its application in a non-volatile memory (NVM) device. It demonstrated a large memory window of 6.2 V in terms of flat-band voltage (V(FB)) shift under a dual-directional sweeping gate voltage of - 10 to 10 V. A 1.1 V V(FB) shift under a low dual-directional sweeping gate voltage of - 4 to 4 V was also observed. The retention characteristic of this MOS capacitor was demonstrated by a 0.5 V memory window after 10(4) s of elapsed time at room temperature. The endurance characteristic was demonstrated by a program/erase cycling test.

Investing the effectiveness of retention performance in a non-volatile floating gate memory device with a core-shell structure of CdSe nanoparticles

NASA Astrophysics Data System (ADS)

Lee, Dong-Hoon; Kim, Jung-Min; Lim, Ki-Tae; Cho, Hyeong Jun; Bang, Jin Ho; Kim, Yong-Sang

2016-03-01

In this paper, we empirically investigate the retention performance of organic non-volatile floating gate memory devices with CdSe nanoparticles (NPs) as charge trapping elements. Core-structured CdSe NPs or core-shell-structured ZnS/CdSe NPs were mixed in PMMA and their performance in pentacene based device was compared. The NPs and self-organized thin tunneling PMMA inside the devices exhibited hysteresis by trapping hole during capacitance-voltage characterization. Despite of core-structured NPs showing a larger memory window, the retention time was too short to be adopted by an industry. By contrast core-shell structured NPs showed an improved retention time of >10000 seconds than core-structure NCs. Based on these results and the energy band structure, we propose the retention mechanism of each NPs. This investigation of retention performance provides a comparative and systematic study of the charging/discharging behaviors of NPs based memory devices. [Figure not available: see fulltext.

75 FR 11909 - In the Matter of: Certain Flash Memory Chips and Products Containing Same; Notice of Commission...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-03-12

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-664] In the Matter of: Certain Flash Memory Chips and Products Containing Same; Notice of Commission Determination Not To Review an Initial..., and the [[Page 11910

Effect of electrode material on characteristics of non-volatile resistive memory consisting of Ag{sub 2}S nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jang, Jaewon, E-mail: j1jang@knu.ac.kr

2016-07-15

In this study, Ag{sub 2}S nanoparticles are synthesized and used as the active material for two-terminal resistance switching memory devices. Sintered Ag{sub 2}S films are successfully crystallized on plastic substrates with synthesized Ag{sub 2}S nanoparticles, after a relatively low-temperature sintering process (200 °C). After the sintering process, the crystallite size is increased from 6.8 nm to 80.3 nm. The high ratio of surface atoms to inner atoms of nanoparticles reduces the melting point temperature, deciding the sintering process temperature. In order to investigate the resistance switching characteristics, metal/Ag{sub 2}S/metal structures are fabricated and tested. The effect of the electrode materialmore » on the non-volatile resistive memory characteristics is studied. The bottom electrochemically inert materials, such as Au and Pt, were critical for maintaining stable memory characteristics. By using Au and Pt inert bottom electrodes, we are able to significantly improve the memory endurance and retention to more than 10{sup 3} cycles and 10{sup 4} sec, respectively.« less

Indium-oxide nanoparticles for RRAM devices compatible with CMOS back-end-off-line

NASA Astrophysics Data System (ADS)

León Pérez, Edgar A. A.; Guenery, Pierre-Vincent; Abouzaid, Oumaïma; Ayadi, Khaled; Brottet, Solène; Moeyaert, Jérémy; Labau, Sébastien; Baron, Thierry; Blanchard, Nicholas; Baboux, Nicolas; Militaru, Liviu; Souifi, Abdelkader

2018-05-01

We report on the fabrication and characterization of Resistive Random Access Memory (RRAM) devices based on nanoparticles in MIM structures. Our approach is based on the use of indium oxide (In2O3) nanoparticles embedded in a dielectric matrix using CMOS-full-compatible fabrication processes in view of back-end-off-line integration for non-volatile memory (NVM) applications. A bipolar switching behavior has been observed using current-voltage measurements (I-V) for all devices. Very high ION/IOFF ratios have been obtained up to 108. Our results provide insights for further integration of In2O3 nanoparticles-based devices for NVM applications. He is currently a Postdoctoral Researcher in the Institute of Nanotechnologies of Lyon (INL), INSA de Lyon, France, in the Electronics Department. His current research include indium oxide nanoparticles for non-volatile memory applications, and the integrations of these devices in CMOS BEOL.

Eliminating Overerase Behavior by Designing Energy Band in High-Speed Charge-Trap Memory Based on WSe2.

PubMed

Liu, Chunsen; Yan, Xiao; Wang, Jianlu; Ding, Shijin; Zhou, Peng; Zhang, David Wei

2017-05-01

Atomic crystal charge trap memory, as a new concept of nonvolatile memory, possesses an atomic level flatness interface, which makes them promising candidates for replacing conventional FLASH memory in the future. Here, a 2D material WSe 2 and a 3D Al 2 O 3 /HfO 2 /Al 2 O 3 charge-trap stack are combined to form a charge-trap memory device with a separation of control gate and memory stack. In this device, the charges are erased/written by built-in electric field, which significantly enhances the write speed to 1 µs. More importantly, owing to the elaborate design of the energy band structure, the memory only captures electrons with a large electron memory window over 20 V and trap selectivity about 13, both of them are the state-of-the-art values ever reported in FLASH memory based on 2D materials. Therefore, it is demonstrated that high-performance charge trap memory based on WSe 2 without the fatal overerase issue in conventional FLASH memory can be realized to practical application. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Non-volatile main memory management methods based on a file system.

PubMed

Oikawa, Shuichi

2014-01-01

There are upcoming non-volatile (NV) memory technologies that provide byte addressability and high performance. PCM, MRAM, and STT-RAM are such examples. Such NV memory can be used as storage because of its data persistency without power supply while it can be used as main memory because of its high performance that matches up with DRAM. There are a number of researches that investigated its uses for main memory and storage. They were, however, conducted independently. This paper presents the methods that enables the integration of the main memory and file system management for NV memory. Such integration makes NV memory simultaneously utilized as both main memory and storage. The presented methods use a file system as their basis for the NV memory management. We implemented the proposed methods in the Linux kernel, and performed the evaluation on the QEMU system emulator. The evaluation results show that 1) the proposed methods can perform comparably to the existing DRAM memory allocator and significantly better than the page swapping, 2) their performance is affected by the internal data structures of a file system, and 3) the data structures appropriate for traditional hard disk drives do not always work effectively for byte addressable NV memory. We also performed the evaluation of the effects caused by the longer access latency of NV memory by cycle-accurate full-system simulation. The results show that the effect on page allocation cost is limited if the increase of latency is moderate.

Investigation of the environmental implications of the CNT switch through its life cycle

NASA Astrophysics Data System (ADS)

Dahlben, Lindsay Johanna

Carbon nanotubes (CNTs) are unique allotropes of carbon that have high tensile strength, a high Young's modulus, good thermal conductivity, and depending on the CNT chirality can be metallic or semiconducting. These mechanical, thermal, and electrical properties make CNTs an attractive element in electronic applications such as conductive films, photovoltaics, non-volatile memory devices, batteries, sensors, and displays. Although commercialization of CNT-enabled products is increasing, there remains a significant lack of information regarding the health effects and environmental impacts of CNTs. Some studies have even shown that the behavior, toxicity, and persistence of CNTs may differ from bulk heterogeneous carbon. Given these uncertainties, it is prudent to assess the environmental attributes of CNT products and processes now to discover and potentially prevent adverse effects. This study investigates the environmental implications of a non-volatile bi-stable electromechanical CNT switch through its life cycle. Life cycle assessment (LCA) methodology is used to track the environmental impacts of the CNT switch through its fabrication and expected use and end-of-life (EOL) stages. Process parameters, energy consumption, input materials, output emissions, and yield efficiencies are determined for the laboratory and full-scale manufacture environments. The Ecoinvent(TM) inventory database and Eco-indicator 1999(TM) method are utilized for the impact assessment. Results for the fabrication stage are reported for highest contributions to environmental impact such as airborne inorganics, land use, and fossil fuels due to Au refining processes and electricity consumption. Extension of the LCA scope is evaluated for the potential replacement of CNT switches to current field-effect transistors (FETs) in flash memory for a cellular phone application. First-order predictions are made for the functionality and performance of the CNT switch during the use stage through an environmental perspective. Existing cellular phone EOL management options including recycling and direct disposal to landfill and incineration are evaluated for potential limitations, concerns, and environmental releases that may occur from the assimilation of CNT switch-enabled phones into the waste stream. In this manner, potential environmental effects of the CNT switch throughout its life cycle stages can be addressed alongside its technological development to ensure safe, sustainable, and successful CNT products.

Practicality of Evaluating Soft Errors in Commercial sub-90 nm CMOS for Space Applications

NASA Technical Reports Server (NTRS)

Pellish, Jonathan A.; LaBel, Kenneth A.

2010-01-01

The purpose of this presentation is to: Highlight space memory evaluation evolution, Review recent developments regarding low-energy proton direct ionization soft errors, Assess current space memory evaluation challenges, including increase of non-volatile technology choices, and Discuss related testing and evaluation complexities.

Multiple switching modes and multiple level states in memristive devices

NASA Astrophysics Data System (ADS)

Miao, Feng; Yang, J. Joshua; Borghetti, Julien; Strachan, John Paul; Zhang, M.-X.; Goldfarb, Ilan; Medeiros-Ribeiro, Gilberto; Williams, R. Stanley

2011-03-01

As one of the most promising technologies for next generation non-volatile memory, metal oxide based memristive devices have demonstrated great advantages on scalability, operating speed and power consumption. Here we report the observation of multiple switching modes and multiple level states in different memristive systems. The multiple switching modes can be obtained by limiting the current during electroforming, and related transport behaviors, including ionic and electronic motions, are characterized. Such observation can be rationalized by a model of two effective switching layers adjacent to the bottom and top electrodes. Multiple level states, corresponding to different composition of the conducting channel, will also be discussed in the context of multiple-level storage for high density, non-volatile memory applications.

The floating-gate non-volatile semiconductor memory--from invention to the digital age.

PubMed

Sze, S M

2012-10-01

In the past 45 years (from 1967 to 2012), the non-volatile semiconductor memory (NVSM) has emerged from a floating-gate concept to the prime technology driver of the largest industry in the world-the electronics industry. In this paper, we briefly review the historical development of NVSM and project its future trends to the year 2020. In addition, we consider NVSM's wide-range of applications from the digital cellular phone to tablet computer to digital television. As the device dimension is scaled down to the deca-nanometer regime, we expect that many innovations will be made to meet the scaling challenges, and NVSM-inspired technology will continue to enrich and improve our lives for decades to come.

Reactive flash volatilization of fluid fuels

DOEpatents

Schmidt, Lanny D.; Dauenhauer, Paul J.; Dreyer, Bradon J.; Salge, James R.

2013-01-08

The invention provides methods for the production of synthesis gas. More particularly, various embodiments of the invention relate to systems and methods for volatilizing fluid fuel to produce synthesis gas by using a metal catalyst on a solid support matrix.

Distributed Micro-Processor Applications to Guidance and Control Systems.

DTIC Science & Technology

1982-07-01

nanoseconds compared with 22 milliseconds for the older type of NMOS non-volatile RAM. This non-volatile RAM is estimated to hold its memory for 100 years...illustrated in figure 1.4.3.3 and compared with the traditional permalog chevron bubble structure. The contiguous element bubble structure is being developed ...M for its 8086 based Digital Advanced Avionics System (DAAS) developed for NASA Ames, but rejected it as being unsuitable. Ada is the new DoD

Electric field controlled strain induced reversible switching of magnetization in Galfenol nanomagnets delineated on PMN-PT substrate

NASA Astrophysics Data System (ADS)

Ahmad, Hasnain; Atulasimha, Jayasimha; Bandyopadhyay, Supriyo

We report a non-volatile converse magneto-electric effect in elliptical Galfenol (FeGa) nanomagnets of ~300 nm lateral dimensions and ~10nm thickness delineated on a PMN-PT substrate. This effect can be harnessed for energy-efficient non-volatile memory. The nanomagnets are fabricated with e-beam lithography and sputtering. Their major axes are aligned parallel to the direction in which the substrate is poled and they are magnetized in this direction with a magnetic field. An electric field in the opposite direction generates compressive strain in the piezoelectric substrate which is partially transferred to the nanomagnets and rotates their magnetization away from the major axes to metastable orientations. There they remain after the field is removed, resulting in non-volatility. Reversing the electric field generates tensile strain which returns the magnetization to the original state. The two states can encode two binary bits which can be written using the correct voltage polarity, resulting in non-toggle behavior. Scaled memory fashioned on this effect can exhibit write energy dissipation of only ~2 aJ. Work is supported by NSF under ECCS-1124714 and CCF-1216614. Sputtering was carried out at NIST Gaithersburg.

System for loading executable code into volatile memory in a downhole tool

DOEpatents

Hall, David R.; Bartholomew, David B.; Johnson, Monte L.

2007-09-25

A system for loading an executable code into volatile memory in a downhole tool string component comprises a surface control unit comprising executable code. An integrated downhole network comprises data transmission elements in communication with the surface control unit and the volatile memory. The executable code, stored in the surface control unit, is not permanently stored in the downhole tool string component. In a preferred embodiment of the present invention, the downhole tool string component comprises boot memory. In another embodiment, the executable code is an operating system executable code. Preferably, the volatile memory comprises random access memory (RAM). A method for loading executable code to volatile memory in a downhole tool string component comprises sending the code from the surface control unit to a processor in the downhole tool string component over the network. A central processing unit writes the executable code in the volatile memory.

Overlay degradation induced by film stress

NASA Astrophysics Data System (ADS)

Huang, Chi-hao; Liu, Yu-Lin; Luo, Shing-Ann; Yang, Mars; Yang, Elvis; Hung, Yung-Tai; Luoh, Tuung; Yang, T. H.; Chen, K. C.

2017-03-01

The semiconductor industry has continually sought the approaches to produce memory devices with increased memory cells per memory die. One way to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories is 3D stacked flash cell array. In constructing 3D NAND flash memories, increasing the number of stacked layers to build more memory cell number per unit area necessitates many high-aspect-ratio etching processes accordingly the incorporation of thick and unique etching hard-mask scheme has been indispensable. However, the ever increasingly thick requirement on etching hard-mask has made the hard-mask film stress control extremely important for maintaining good process qualities. The residual film stress alters the wafer shape consequently several process impacts have been readily observed across wafer, such as wafer chucking error on scanner, film peeling, materials coating and baking defects, critical dimension (CD) non-uniformity and overlay degradation. This work investigates the overlay and residual order performance indicator (ROPI) degradation coupling with increasingly thick advanced patterning film (APF) etching hard-mask. Various APF films deposited by plasma enhanced chemical vapor deposition (PECVD) method under different deposition temperatures, chemicals combinations, radio frequency powers and chamber pressures were carried out. And -342MPa to +80MPa film stress with different film thicknesses were generated for the overlay performance study. The results revealed the overlay degradation doesn't directly correlate with convex or concave wafer shapes but the magnitude of residual APF film stress, while increasing the APF thickness will worsen the overlay performance and ROPI strongly. High-stress APF film was also observed to enhance the scanner chucking difference and lead to more serious wafer to wafer overlay variation. To reduce the overlay degradation from ever increasingly thick APF etching hard-mask, optimizing the film stress of APF is the most effective way and high order overlay compensation is also helpful.

Origami-based tunable truss structures for non-volatile mechanical memory operation.

PubMed

Yasuda, Hiromi; Tachi, Tomohiro; Lee, Mia; Yang, Jinkyu

2017-10-17

Origami has recently received significant interest from the scientific community as a method for designing building blocks to construct metamaterials. However, the primary focus has been placed on their kinematic applications by leveraging the compactness and auxeticity of planar origami platforms. Here, we present volumetric origami cells-specifically triangulated cylindrical origami (TCO)-with tunable stability and stiffness, and demonstrate their feasibility as non-volatile mechanical memory storage devices. We show that a pair of TCO cells can develop a double-well potential to store bit information. What makes this origami-based approach more appealing is the realization of two-bit mechanical memory, in which two pairs of TCO cells are interconnected and one pair acts as a control for the other pair. By assembling TCO-based truss structures, we experimentally verify the tunable nature of the TCO units and demonstrate the operation of purely mechanical one- and two-bit memory storage prototypes.Origami is a popular method to design building blocks for mechanical metamaterials. Here, the authors assemble a volumetric origami-based structure, predict its axial and rotational movements during folding, and demonstrate the operation of mechanical one- and two-bit memory storage.

Capacitance-voltage measurement in memory devices using ferroelectric polymer

NASA Astrophysics Data System (ADS)

Nguyen, Chien A.; Lee, Pooi See

2006-01-01

Application of thin polymer film as storing mean for non-volatile memory devices is investigated. Capacitance-voltage (C-V) measurement of metal-ferroelectric-metal device using ferroelectric copolymer P(VDF-TrFE) as dielectric layer shows stable 'butter-fly' curve. The two peaks in C-V measurement corresponding to the largest capacitance are coincidental at the coercive voltages that give rise to zero polarization in the polarization hysteresis measurement. By comparing data of C-V and P-E measurement, a correlation between two types of hysteresis is established in which it reveals simultaneous electrical processes occurring inside the device. These processes are caused by the response of irreversible and reversible polarization to the applied electric field that can be used to present a memory window. The memory effect of ferroelectric copolymer is further demonstrated for fabricating polymeric non-volatile memory devices using metal-ferroelectric-insulator-semiconductor structure (MFIS). By applying different sweeping voltages at the gate, bidirectional flat-band voltage shift is observed in the ferroelectric capacitor. The asymmetrical shift after negative sweeping is resulted from charge accumulation at the surface of Si substrate caused by the dipole direction in the polymer layer. The effect is reversed for positive voltage sweeping.

Minimizing the Disruptive Effects of Prospective Memory in Simulated Air Traffic Control

PubMed Central

Loft, Shayne; Smith, Rebekah E.; Remington, Roger

2015-01-01

Prospective memory refers to remembering to perform an intended action in the future. Failures of prospective memory can occur in air traffic control. In two experiments, we examined the utility of external aids for facilitating air traffic management in a simulated air traffic control task with prospective memory requirements. Participants accepted and handed-off aircraft and detected aircraft conflicts. The prospective memory task involved remembering to deviate from a routine operating procedure when accepting target aircraft. External aids that contained details of the prospective memory task appeared and flashed when target aircraft needed acceptance. In Experiment 1, external aids presented either adjacent or non-adjacent to each of the 20 target aircraft presented over the 40min test phase reduced prospective memory error by 11% compared to a condition without external aids. In Experiment 2, only a single target aircraft was presented a significant time (39min–42min) after presentation of the prospective memory instruction, and the external aids reduced prospective memory error by 34%. In both experiments, costs to the efficiency of non-prospective memory air traffic management (non-target aircraft acceptance response time, conflict detection response time) were reduced by non-adjacent aids compared to no aids or adjacent aids. In contrast, in both experiments, the efficiency of the prospective memory air traffic management (target aircraft acceptance response time) was facilitated by adjacent aids compared to non-adjacent aids. Together, these findings have potential implications for the design of automated alerting systems to maximize multi-task performance in work settings where operators monitor and control demanding perceptual displays. PMID:24059825

Optically controlled electroresistance and electrically controlled photovoltage in ferroelectric tunnel junctions

PubMed Central

Jin Hu, Wei; Wang, Zhihong; Yu, Weili; Wu, Tom

2016-01-01

Ferroelectric tunnel junctions (FTJs) have recently attracted considerable interest as a promising candidate for applications in the next-generation non-volatile memory technology. In this work, using an ultrathin (3 nm) ferroelectric Sm0.1Bi0.9FeO3 layer as the tunnelling barrier and a semiconducting Nb-doped SrTiO3 single crystal as the bottom electrode, we achieve a tunnelling electroresistance as large as 105. Furthermore, the FTJ memory states could be modulated by light illumination, which is accompanied by a hysteretic photovoltaic effect. These complimentary effects are attributed to the bias- and light-induced modulation of the tunnel barrier, both in height and width, at the semiconductor/ferroelectric interface. Overall, the highly tunable tunnelling electroresistance and the correlated photovoltaic functionalities provide a new route for producing and non-destructively sensing multiple non-volatile electronic states in such FTJs. PMID:26924259

82 FR 28354 - Certain Non-Volatile Memory Devices and Products Containing Same Commission Determination Not To...

Federal Register 2010, 2011, 2012, 2013, 2014

2017-06-21

...Notice is hereby given that the U.S. International Trade Commission has determined not to review an initial determination (``ID'') (Order No. 11) of the presiding administrative law judge (``ALJ'') granting an unopposed motion for leave to amend the complaint and notice of investigation to add Toshiba Memory Corporation of Tokyo, Japan (``Toshiba Memory'') as a respondent to the investigation.

The effect of the bottom electrode on ferroelectric tunnel junctions based on CMOS-compatible HfO2.

PubMed

Goh, Youngin; Jeon, Sanghun

2018-08-17

Ferroelectric tunnel junctions (FTJs) have attracted research interest as promising candidates for non-destructive readout non-volatile memories. Unlike conventional perovskite FTJs, hafnia FTJs offer many advantages in terms of scalability and CMOS compatibility. However, so far, hafnia FTJs have shown poor endurance and relatively low resistance ratios and these have remained issues for real device applications. In our study, we fabricated HfZrO(HZO)-based FTJs with various electrodes (TiN, Si, SiGe, Ge) and improved the memory performance of HZO-based FTJs by using the asymmetry of the charge screening lengths of the electrodes. For the HZO-based FTJ with a Ge substrate, the effective barrier afforded by this FTJ can be electrically modulated because of the space charge-limited region formed at the ferroelectric/semiconductor interface. The optimized HZO-based FTJ with a Ge bottom electrode presents excellent ferroelectricity with a high remnant polarization of 18 μC cm -2 , high tunneling electroresistance value of 30, good retention at 85 °C and high endurance of 10 7 . The results demonstrate the great potential of HfO 2 -based FTJs in non-destructive readout non-volatile memories.

The conjunction of non-consciously perceived object identity and spatial position can be retained during a visual short-term memory task.

PubMed

Bergström, Fredrik; Eriksson, Johan

2015-01-01

Although non-consciously perceived information has previously been assumed to be short-lived (< 500 ms), recent findings show that non-consciously perceived information can be maintained for at least 15 s. Such findings can be explained as working memory without a conscious experience of the information to be retained. However, whether or not working memory can operate on non-consciously perceived information remains controversial, and little is known about the nature of such non-conscious visual short-term memory (VSTM). Here we used continuous flash suppression to render stimuli non-conscious, to investigate the properties of non-consciously perceived representations in delayed match-to-sample (DMS) tasks. In Experiment I we used variable delays (5 or 15 s) and found that performance was significantly better than chance and was unaffected by delay duration, thereby replicating previous findings. In Experiment II the DMS task required participants to combine information of spatial position and object identity on a trial-by-trial basis to successfully solve the task. We found that the conjunction of spatial position and object identity was retained, thereby verifying that non-conscious, trial-specific information can be maintained for prospective use. We conclude that our results are consistent with a working memory interpretation, but that more research is needed to verify this interpretation.

Effect with high density nano dot type storage layer structure on 20 nm planar NAND flash memory characteristics

NASA Astrophysics Data System (ADS)

Sasaki, Takeshi; Muraguchi, Masakazu; Seo, Moon-Sik; Park, Sung-kye; Endoh, Tetsuo

2014-01-01

The merits, concerns and design principle for the future nano dot (ND) type NAND flash memory cell are clarified, by considering the effect of storage layer structure on NAND flash memory characteristics. The characteristics of the ND cell for a NAND flash memory in comparison with the floating gate type (FG) is comprehensively studied through the read, erase, program operation, and the cell to cell interference with device simulation. Although the degradation of the read throughput (0.7% reduction of the cell current) and slower program time (26% smaller programmed threshold voltage shift) with high density (10 × 1012 cm-2) ND NAND are still concerned, the suppress of the cell to cell interference with high density (10 × 1012 cm-2) plays the most important part for scaling and multi-level cell (MLC) operation in comparison with the FG NAND. From these results, the design knowledge is shown to require the control of the number of nano dots rather than the higher nano dot density, from the viewpoint of increasing its memory capacity by MLC operation and suppressing threshold voltage variability caused by the number of dots in the storage layer. Moreover, in order to increase its memory capacity, it is shown the tunnel oxide thickness with ND should be designed thicker (>3 nm) than conventional designed ND cell for programming/erasing with direct tunneling mechanism.

76 FR 13207 - In the Matter of Certain Flash Memory and Products Containing Same Notice of Request for...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-03-10

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-685] In the Matter of Certain Flash Memory and Products Containing Same Notice of Request for Statements on the Public Interest Section 337 of the Tariff Act of 1930 provides that if the Commission finds a violation it shall exclude the...

An automated Y-maze based on a reduced instruction set computer (RISC) microcontroller for the assessment of continuous spontaneous alternation in rats.

PubMed

Heredia-López, Francisco J; Álvarez-Cervera, Fernando J; Collí-Alfaro, José G; Bata-García, José L; Arankowsky-Sandoval, Gloria; Góngora-Alfaro, José L

2016-12-01

Continuous spontaneous alternation behavior (SAB) in a Y-maze is used for evaluating working memory in rodents. Here, the design of an automated Y-maze equipped with three infrared optocouplers per arm, and commanded by a reduced instruction set computer (RISC) microcontroller is described. The software was devised for recording only true entries and exits to the arms. Experimental settings are programmed via a keyboard with three buttons and a display. The sequence of arm entries and the time spent in each arm and the neutral zone (NZ) are saved as a text file in a non-volatile memory for later transfer to a USB flash memory. Data files are analyzed with a program developed under LabVIEW® environment, and the results are exported to an Excel® spreadsheet file. Variables measured are: latency to exit the starting arm, sequence and number of arm entries, number of alternations, alternation percentage, and cumulative times spent in each arm and NZ. The automated Y-maze accurately detected the SAB decrease produced in rats by the muscarinic antagonist trihexyphenidyl, and its reversal by caffeine, having 100 % concordance with the alternation percentages calculated by two trained observers who independently watched videos of the same experiments. Although the values of time spent in the arms and NZ measured by the automated system had small discrepancies with those calculated by the observers, Bland-Altman analysis showed 95 % concordance in three pairs of comparisons, while in one it was 90 %, indicating that this system is a reliable and inexpensive alternative for the study of continuous SAB in rodents.

Resistive switching mechanisms in random access memory devices incorporating transition metal oxides: TiO2, NiO and Pr0.7Ca0.3MnO3.

PubMed

Magyari-Köpe, Blanka; Tendulkar, Mihir; Park, Seong-Geon; Lee, Hyung Dong; Nishi, Yoshio

2011-06-24

Resistance change random access memory (RRAM) cells, typically built as MIM capacitor structures, consist of insulating layers I sandwiched between metal layers M, where the insulator performs the resistance switching operation. These devices can be electrically switched between two or more stable resistance states at a speed of nanoseconds, with long retention times, high switching endurance, low read voltage, and large switching windows. They are attractive candidates for next-generation non-volatile memory, particularly as a flash successor, as the material properties can be scaled to the nanometer regime. Several resistance switching models have been suggested so far for transition metal oxide based devices, such as charge trapping, conductive filament formation, Schottky barrier modulation, and electrochemical migration of point defects. The underlying fundamental principles of the switching mechanism still lack a detailed understanding, i.e. how to control and modulate the electrical characteristics of devices incorporating defects and impurities, such as oxygen vacancies, metal interstitials, hydrogen, and other metallic atoms acting as dopants. In this paper, state of the art ab initio theoretical methods are employed to understand the effects that filamentary types of stable oxygen vacancy configurations in TiO(2) and NiO have on the electronic conduction. It is shown that strong electronic interactions between metal ions adjacent to oxygen vacancy sites results in the formation of a conductive path and thus can explain the 'ON' site conduction in these materials. Implication of hydrogen doping on electroforming is discussed for Pr(0.7)Ca(0.3)MnO(3) devices based on electrical characterization and FTIR measurements.

Biologically active nanocomposite of DNA-PbS nanoparticles: A new material for non-volatile memory devices

NASA Astrophysics Data System (ADS)

Murgunde, B. K.; Rabinal, M. K.; Kalasad, M. N.

2018-01-01

Composite films of deoxyribonucleic acid (DNA) and lead sulfide (PbS) nanoparticles are prepared to fabricate biological memory devices. A simple solution based electrografting is developed to deposit large (few cm2) uniform films of DNA:PbS on conducting substrates. The films are studied by X-ray photoelectron spectroscopy, field emission SEM, FTIR and optical spectroscopy to understand their properties. Charge transport measurements are carried out on ITO-DNA:PbS-metal junctions by cyclic voltage scans, electrical bi-stability is observed with ON/OFF ratio more than ∼104 times with good stability and endurance, such performance being rarely reported. The observed results are interpreted in the light of strong electrostatic binding of nanoparticles and DNA stands, which leads doping of Pb atoms into DNA. As a result, these devices exhibit negative differential resistance (NDR) effect due to oxidation of doped metal atoms. These composites can be the potential materials in the development of new generation non-volatile memory devices.

Guidelines Manual: Post Accident Procedures for Chemicals and Propellants.

DTIC Science & Technology

1983-01-01

chemicals, in paint and nail polish removers, as a solvent. It is quite volatile and has a flash point of 0 dog . F. It is lighter than water and...is a colorless liquid. It has a flash point of 165 dog . F. It slowly dissociates to acetone, a flamable liquid, and hydrogen cyanide, a flammable...4907215 WI 1917 Ethyl acrylate is a clear colorless liquid with an acrid odor. It is used to make paints and plastics. It has a flash point of 60 dog . F

Radiation Tests on 2Gb NAND Flash Memories

NASA Technical Reports Server (NTRS)

Nguyen, Duc N.; Guertin, Steven M.; Patterson, J. D.

2006-01-01

We report on SEE and TID tests of highly scaled Samsung 2Gbits flash memories. Both in-situ and biased interval irradiations were used to characterize the response of the total accumulated dose failures. The radiation-induced failures can be categorized as followings: single event upset (SEU) read errors in biased and unbiased modes, write errors, and single-event-functional-interrupt (SEFI) failures.

Hydraulic Universal Display Processor System (HUDPS).

DTIC Science & Technology

1981-11-21

emphasis on smart alphanumeric devices in Task II. Volatile and non-volatile memory components were utilized along with the Intel 8748 microprocessor...system. 1.2 TASK 11 Fault display methods for ground support personnel were investigated during Phase II with emphasis on smart alphanumeric devices...CONSIDERATIONS Methods of display fault indication for ground support personnel have been investigated with emphasis on " smart " alphanumeric devices

On Using the Volatile Mem-Capacitive Effect of TiO2 Resistive Random Access Memory to Mimic the Synaptic Forgetting Process

NASA Astrophysics Data System (ADS)

Sarkar, Biplab; Mills, Steven; Lee, Bongmook; Pitts, W. Shepherd; Misra, Veena; Franzon, Paul D.

2018-02-01

In this work, we report on mimicking the synaptic forgetting process using the volatile mem-capacitive effect of a resistive random access memory (RRAM). TiO2 dielectric, which is known to show volatile memory operations due to migration of inherent oxygen vacancies, was used to achieve the volatile mem-capacitive effect. By placing the volatile RRAM candidate along with SiO2 at the gate of a MOS capacitor, a volatile capacitance change resembling the forgetting nature of a human brain is demonstrated. Furthermore, the memory operation in the MOS capacitor does not require a current flow through the gate dielectric indicating the feasibility of obtaining low power memory operations. Thus, the mem-capacitive effect of volatile RRAM candidates can be attractive to the future neuromorphic systems for implementing the forgetting process of a human brain.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory

NASA Astrophysics Data System (ADS)

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-01

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory.

PubMed

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-23

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

CXRO - The Center for X-ray Optics

Science.gov Websites

advanced experimental systems to address national needs, support research in material, life, and provides a stepping stone for realizing stable and highly scalable (10 nm and below) non-volatile memory

Ultra-fast three terminal perpendicular spin-orbit torque MRAM (Presentation Recording)

NASA Astrophysics Data System (ADS)

Boulle, Olivier; Cubukcu, Murat; Hamelin, Claire; Lamard, Nathalie; Buda-Prejbeanu, Liliana; Mikuszeit, Nikolai; Garello, Kevin; Gambardella, Pietro; Langer, Juergen; Ocker, Berthold; Miron, Mihai; Gaudin, Gilles

2015-09-01

The discovery that a current flowing in a heavy metal can exert a torque on a neighboring ferromagnet has opened a new way to manipulate the magnetization at the nanoscale. This "spin orbit torque" (SOT) has been demonstrated in ultrathin magnetic multilayers with structural inversion asymmetry (SIA) and high spin orbit coupling, such as Pt/Co/AlOx multilayers. We have shown that this torque can lead to the magnetization switching of a perpendicularly magnetized nanomagnet by an in-plane current injection. The manipulation of magnetization by SOT has led to a novel concept of magnetic RAM memory, the SOT-MRAM, which combines non volatility, high speed, reliability and large endurance. These features make the SOT-MRAM a good candidate to replace SRAM for non-volatile cache memory application. We will present the proof of concept of a perpendicular SOT-MRAM cell composed of a Ta/FeCoB/MgO/FeCoB magnetic tunnel junction and demonstrate ultra-fast (down to 300 ps) deterministic bipolar magnetization switching. Macrospin and micromagnetic simulations including SOT cannot reproduce the experimental results, which suggests that additional physical mechanisms are at stacks. Our results show that SOT-MRAM is fast, reliable and low power, which is promising for non-volatile cache memory application. We will also discuss recent experiments of magnetization reversal in ultrathin multilayers Pt/Co/AlOx by very short (<200 ps) current pulses. We will show that in this material, the Dzyaloshinskii-Moryia interaction plays a key role in the reversal process.

Thermal annealing and temperature dependences of memory effect in organic memory transistor

NASA Astrophysics Data System (ADS)

Ren, X. C.; Wang, S. M.; Leung, C. W.; Yan, F.; Chan, P. K. L.

2011-07-01

We investigate the annealing and thermal effects of organic non-volatile memory with floating silver nanoparticles by real-time transfer curve measurements. During annealing, the memory window shows shrinkage of 23% due to structural variation of the nanoparticles. However, by increasing the device operating temperature from 20 to 90 °C after annealing, the memory window demonstrates an enlargement up to 100%. The differences in the thermal responses are explained and confirmed by the co-existence of electron and hole traps. Our findings provide a better understanding of organic memory performances under various operating temperatures and validate their applications for temperature sensing or thermal memories.

Devolatilization Analysis in a Twin Screw Extruder by using the Flow Analysis Network (FAN) Method

NASA Astrophysics Data System (ADS)

Tomiyama, Hideki; Takamoto, Seiji; Shintani, Hiroaki; Inoue, Shigeki

We derived the theoretical formulas for three mechanisms of devolatilization in a twin screw extruder. These are flash, surface refreshment and forced expansion. The method for flash devolatilization is based on the equation of equilibrium concentration which shows that volatiles break off from polymer when they are relieved from high pressure condition. For surface refreshment devolatilization, we applied Latinen's model to allow estimation of polymer behavior in the unfilled screw conveying condition. Forced expansion devolatilization is based on the expansion theory in which foams are generated under reduced pressure and volatiles are diffused on the exposed surface layer after mixing with the injected devolatilization agent. Based on these models, we developed the simulation software of twin-screw extrusion by the FAN method and it allows us to quantitatively estimate volatile concentration and polymer temperature with a high accuracy in the actual multi-vent extrusion process for LDPE + n-hexane.

Evaluation of Ferroelectric Materials for Memory Applications

DTIC Science & Technology

1990-06-01

as automobile odometers, access counters, and flight time recorders. Detailed product information is provided in Appendix A. 3. Optical Read...volatility but by definition are not reprogrammable , which severely restricts flexibility and makes error correction difficult. Magnetic core is non...battery-backed SRAMs as well. The programs for embedded controllers, such as those increasingly used in automobiles , are kept in nonvolatile memory. The

Integration of lead-free ferroelectric on HfO2/Si (100) for high performance non-volatile memory applications

PubMed Central

Kundu, Souvik; Maurya, Deepam; Clavel, Michael; Zhou, Yuan; Halder, Nripendra N.; Hudait, Mantu K.; Banerji, Pallab; Priya, Shashank

2015-01-01

We introduce a novel lead-free ferroelectric thin film (1-x)BaTiO3-xBa(Cu1/3Nb2/3)O3 (x = 0.025) (BT-BCN) integrated on to HfO2 buffered Si for non-volatile memory (NVM) applications. Piezoelectric force microscopy (PFM), x-ray diffraction, and high resolution transmission electron microscopy were employed to establish the ferroelectricity in BT-BCN thin films. PFM study reveals that the domains reversal occurs with 180° phase change by applying external voltage, demonstrating its effectiveness for NVM device applications. X-ray photoelectron microscopy was used to investigate the band alignments between atomic layer deposited HfO2 and pulsed laser deposited BT-BCN films. Programming and erasing operations were explained on the basis of band-alignments. The structure offers large memory window, low leakage current, and high and low capacitance values that were easily distinguishable even after ~106 s, indicating strong charge storage potential. This study explains a new approach towards the realization of ferroelectric based memory devices integrated on Si platform and also opens up a new possibility to embed the system within current complementary metal-oxide-semiconductor processing technology. PMID:25683062

Investigation of impact of post-metallization annealing on reliability of 65 nm NOR floating-gate flash memories

NASA Astrophysics Data System (ADS)

Chiu, Shengfen; Xu, Yue; Ji, Xiaoli; Yan, Feng

2016-12-01

This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65 nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.

Nonvolatile memory chips: critical technology for high-performance recce systems

NASA Astrophysics Data System (ADS)

Kaufman, Bruce

2000-11-01

Airborne recce systems universally require nonvolatile storage of recorded data. Both present and next generation designs make use of flash memory chips. Flash memory devices are in high volume use for a variety of commercial products ranging form cellular phones to digital cameras. Fortunately, commercial applications call for increasing capacities and fast write times. These parameters are important to the designer of recce recorders. Of economic necessity COTS devices are used in recorders that must perform in military avionics environments. Concurrently, recording rates are moving to $GTR10Gb/S. Thus to capture imagery for even a few minutes of record time, tactically meaningful solid state recorders will require storage capacities in the 100s of Gbytes. Even with memory chip densities at present day 512Mb, such capacities require thousands of chips. The demands on packaging technology are daunting. This paper will consider the differing flash chip architectures, both available and projected and discuss the impact on recorder architecture and performance. Emerging nonvolatile memory technologies, FeRAM AND MIRAM will be reviewed with regard to their potential use in recce recorders.

76 FR 2681 - Amended Environmental Impact Statement Filing System Guidance for Implementing 40 CFR 1506.9 and...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-01-14

...., compact discs (CDs), USB flash drives, or memory cards. Please note that if a Federal agency prepares an... of the NOA in the Federal Register. If a calculated time period would end on a non- working day, the assigned time period will be the next working day (i.e., time periods will not end on weekends or Federal...

The properties of realized volatility and realized correlation: Evidence from the Indian stock market

NASA Astrophysics Data System (ADS)

Gkillas (Gillas), Konstantinos; Vortelinos, Dimitrios I.; Saha, Shrabani

2018-02-01

This paper investigates the properties of realized volatility and correlation series in the Indian stock market by employing daily data converting to monthly frequency of five different stock indices from January 2, 2006 to November 30, 2014. Using non-parametric estimation technique the properties examined include normality, long-memory, asymmetries, jumps, and heterogeneity. The realized volatility is a useful technique which provides a relatively accurate measure of volatility based on the actual variance which is beneficial for asset management in particular for non-speculative funds. The results show that realized volatility and correlation series are not normally distributed, with some evidence of persistence. Asymmetries are also evident in both volatilities and correlations. Both jumps and heterogeneity properties are significant; whereas, the former is more significant than the latter. The findings show that properties of volatilities and correlations in Indian stock market have similarities as that show in the stock markets in developed countries such as the stock market in the United States which is more prevalent for speculative business traders.

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

NASA Astrophysics Data System (ADS)

Okamoto, Shin-ichi; Maekawa, Kei-ichi; Kawashima, Yoshiyuki; Shiba, Kazutoshi; Sugiyama, Hideki; Inoue, Masao; Nishida, Akio

2015-04-01

High quality static random access memory (SRAM) for 40-nm embedded MONOS flash memory with split gate (SG-MONOS) was developed. Marginal failure, which results in threshold voltage/drain current tailing and outliers of SRAM transistors, occurs when using a conventional SRAM structure. These phenomena can be explained by not only gate depletion but also partial depletion and percolation path formation in the MOS channel. A stacked poly-Si gate structure can suppress these phenomena and achieve high quality SRAM without any defects in the 6σ level and with high affinity to the 40-nm SG-MONOS process was developed.

A hot hole-programmed and low-temperature-formed SONOS flash memory

PubMed Central

2013-01-01

In this study, a high-performance TixZrySizO flash memory is demonstrated using a sol–gel spin-coating method and formed under a low annealing temperature. The high-efficiency charge storage layer is formed by depositing a well-mixed solution of titanium tetrachloride, silicon tetrachloride, and zirconium tetrachloride, followed by 60 s of annealing at 600°C. The flash memory exhibits a noteworthy hot hole trapping characteristic and excellent electrical properties regarding memory window, program/erase speeds, and charge retention. At only 6-V operation, the program/erase speeds can be as fast as 120:5.2 μs with a 2-V shift, and the memory window can be up to 8 V. The retention times are extrapolated to 106 s with only 5% (at 85°C) and 10% (at 125°C) charge loss. The barrier height of the TixZrySizO film is demonstrated to be 1.15 eV for hole trapping, through the extraction of the Poole-Frenkel current. The excellent performance of the memory is attributed to high trapping sites of the low-temperature-annealed, high-κ sol–gel film. PMID:23899050

Effect of Atomic Layer Depositions (ALD)-Deposited Titanium Oxide (TiO2) Thickness on the Performance of Zr40Cu35Al15Ni10 (ZCAN)/TiO2/Indium (In)-Based Resistive Random Access Memory (RRAM) Structures

DTIC Science & Technology

2015-08-01

metal structures, memristors, resistive random access memory, RRAM, titanium dioxide, Zr40Cu35Al15Ni10, ZCAN, resistive memory, tunnel junction 16...TiO2 thickness ........................6 1 1. Introduction Resistive-switching memory elements based on metal-insulator-metal (MIM) diodes ...have attracted great interest due to their potential as components for simple, inexpensive, and high-density non-volatile storage devices. MIM diodes

TiO2-based memristors and ReRAM: materials, mechanisms and models (a review)

NASA Astrophysics Data System (ADS)

Gale, Ella

2014-10-01

The memristor is the fundamental nonlinear circuit element, with uses in computing and computer memory. Resistive Random Access Memory (ReRAM) is a resistive switching memory proposed as a non-volatile memory. In this review we shall summarize the state of the art for these closely-related fields, concentrating on titanium dioxide, the well-utilized and archetypal material for both. We shall cover material properties, switching mechanisms and models to demonstrate what ReRAM and memristor scientists can learn from each other and examine the outlook for these technologies.

77 FR 58473 - Minimum Technical Standards for Class II Gaming Systems and Equipment

Federal Register 2010, 2011, 2012, 2013, 2014

2012-09-21

... as printed advertising material that cannot be validated directly by a voucher system. Critical... on that component. EPROM. Erasable Programmable Read Only Memory--a non-volatile storage chip or...

Four-state non-volatile memory in a multiferroic spin filter tunnel junction

NASA Astrophysics Data System (ADS)

Ruan, Jieji; Li, Chen; Yuan, Zhoushen; Wang, Peng; Li, Aidong; Wu, Di

2016-12-01

We report a spin filter type multiferroic tunnel junction with a ferromagnetic/ferroelectric bilayer barrier. Memory functions of a spin filter magnetic tunnel junction and a ferroelectric tunnel junction are combined in this single device, producing four non-volatile resistive states that can be read out in a non-destructive manner. This concept is demonstrated in a LaNiO3/Pr0.8Ca0.2MnO3/BaTiO3/La0.7Sr0.3MnO3 all-oxide tunnel junction. The ferromagnetic insulator Pr0.8Ca0.2MnO3 serves as the spin filter and the ferromagnetic metal La0.7Sr0.3MnO3 is the spin analyzer. The ferroelectric polarization reversal in the BaTiO3 barrier switches the tunneling barrier height to produce a tunneling electroresistance. The ferroelectric switching also modulates the spin polarization and the spin filtering efficiency in Pr0.8Ca0.2MnO3.

Multilevel Resistance Programming in Conductive Bridge Resistive Memory

NASA Astrophysics Data System (ADS)

Mahalanabis, Debayan

This work focuses on the existence of multiple resistance states in a type of emerging non-volatile resistive memory device known commonly as Programmable Metallization Cell (PMC) or Conductive Bridge Random Access Memory (CBRAM), which can be important for applications such as multi-bit memory as well as non-volatile logic and neuromorphic computing. First, experimental data from small signal, quasi-static and pulsed mode electrical characterization of such devices are presented which clearly demonstrate the inherent multi-level resistance programmability property in CBRAM devices. A physics based analytical CBRAM compact model is then presented which simulates the ion-transport dynamics and filamentary growth mechanism that causes resistance change in such devices. Simulation results from the model are fitted to experimental dynamic resistance switching characteristics. The model designed using Verilog-a language is computation-efficient and can be integrated with industry standard circuit simulation tools for design and analysis of hybrid circuits involving both CMOS and CBRAM devices. Three main circuit applications for CBRAM devices are explored in this work. Firstly, the susceptibility of CBRAM memory arrays to single event induced upsets is analyzed via compact model simulation and experimental heavy ion testing data that show possibility of both high resistance to low resistance and low resistance to high resistance transitions due to ion strikes. Next, a non-volatile sense amplifier based flip-flop architecture is proposed which can help make leakage power consumption negligible by allowing complete shutdown of power supply while retaining its output data in CBRAM devices. Reliability and energy consumption of the flip-flop circuit for different CBRAM low resistance levels and supply voltage values are analyzed and compared to CMOS designs. Possible extension of this architecture for threshold logic function computation using the CBRAM devices as re-configurable resistive weights is also discussed. Lastly, Spike timing dependent plasticity (STDP) based gradual resistance change behavior in CBRAM device fabricated in back-end-of-line on a CMOS die containing integrate and fire CMOS neuron circuits is demonstrated for the first time which indicates the feasibility of using CBRAM devices as electronic synapses in spiking neural network hardware implementations for non-Boolean neuromorphic computing.

Assessing Server Fault Tolerance and Disaster Recovery Implementation in Thin Client Architectures

DTIC Science & Technology

2007-09-01

server • Windows 2003 server Processor AMD Geode GX Memory 512MB Flash/256MB DDR RAM I/O/Peripheral Support • VGA-type video output (DB-15...2000 Advanced Server Processor AMD Geode NX 1500 Memory • 256MB or 512MB or 1GB DDR SDRAM • 1GB or 512MB Flash I/O/Peripheral Support • SiS741 GX

TID and SEE Response of an Advanced Samsung 4G NAND Flash Memory

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; Friendlich, M.; Howard, J. W.; Berg, M. D.; Kim, H. S.; Irwin, T. L.; LaBel, K. A.

2007-01-01

Initial total ionizing dose (TID) and single event heavy ion test results are presented for an unhardened commercial flash memory, fabricated with 63 nm technology. Results are that the parts survive to a TID of nearly 200 krad (SiO2), with a tractable soft error rate of about 10(exp -l2) errors/bit-day, for the Adams Ten Percent Worst Case Environment.

Testing and operating a multiprocessor chip with processor redundancy

DOEpatents

Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

2014-10-21

A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

A CMOS Compatible, Forming Free TaO x ReRAM

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lohn, A. J.; Stevens, J. E.; Mickel, P. R.

2013-08-31

Resistive random access memory (ReRAM) has become a promising candidate for next-generation high-performance non-volatile memory that operates by electrically tuning resistance states via modulating vacancy concentrations. Here, we demonstrate a wafer-scale process for resistive switching in tantalum oxide that is completely CMOS compatible. The resulting devices are forming-free and with greater than 1x10 5 cycle endurance.

Piezostrain tuning non-volatile 90° magnetic easy axis rotation in Co2FeAl Heusler alloy film grown on Pb(Mg1/3Nb2/3)O3-PbTiO3 heterostructures

NASA Astrophysics Data System (ADS)

Zhou, Cai; Wang, Fenglong; Dunzhu, Gesang; Yao, Jinli; Jiang, Changjun

2016-11-01

Non-volatile electric field-based control of magnetic anisotropy in Co2FeAl/ Pb(Mg1/3Nb2/3)O3-PbTiO3 (CFA/PMN-PT) heterostructures is investigated at room temperature. The remnant magnetization response under different electric fields shows a asymmetric butterfly-like behavior; specifically, this behavior is consistent with the asymmetric butterfly-like piezostrain versus applied electric field curve. Thus electric field-induced non-volatile 90° magnetic easy axis rotation can be attributed to the piezostrain effect. Further, the result measured by rotating-angle ferromagnetic resonance demonstrates piezostrain-mediated non-volatile 90° magnetic easy axis rotation at the initial state and the two remnant polarization states after application of the poling fields of 10 and  -10 kV cm-1 turned off. The angular dependence of magnetic damping also indicates a 90° phase shift at the above mentioned three different states. Additionally, the piezostrain-mediated non-volatile stable magnetization reversal in the two directions of easy and hard magnetization axes are observed under positive and negative pulsed electric fields, which can be used to improve the performance of low-loss multiple-state memory devices.

Saccades to remembered targets: the effects of smooth pursuit and illusory stimulus motion

NASA Technical Reports Server (NTRS)

Zivotofsky, A. Z.; Rottach, K. G.; Averbuch-Heller, L.; Kori, A. A.; Thomas, C. W.; Dell'Osso, L. F.; Leigh, R. J.

1996-01-01

1. Measurements were made in four normal human subjects of the accuracy of saccades to remembered locations of targets that were flashed on a 20 x 30 deg random dot display that was either stationary or moving horizontally and sinusoidally at +/-9 deg at 0.3 Hz. During the interval between the target flash and the memory-guided saccade, the "memory period" (1.4 s), subjects either fixated a stationary spot or pursued a spot moving vertically sinusoidally at +/-9 deg at 0.3 Hz. 2. When saccades were made toward the location of targets previously flashed on a stationary background as subjects fixated the stationary spot, median saccadic error was 0.93 deg horizontally and 1.1 deg vertically. These errors were greater than for saccades to visible targets, which had median values of 0.59 deg horizontally and 0.60 deg vertically. 3. When targets were flashed as subjects smoothly pursued a spot that moved vertically across the stationary background, median saccadic error was 1.1 deg horizontally and 1.2 deg vertically, thus being of similar accuracy to when targets were flashed during fixation. In addition, the vertical component of the memory-guided saccade was much more closely correlated with the "spatial error" than with the "retinal error"; this indicated that, when programming the saccade, the brain had taken into account eye movements that occurred during the memory period. 4. When saccades were made to targets flashed during attempted fixation of a stationary spot on a horizontally moving background, a condition that produces a weak Duncker-type illusion of horizontal movement of the primary target, median saccadic error increased horizontally to 3.2 deg but was 1.1 deg vertically. 5. When targets were flashed as subjects smoothly pursued a spot that moved vertically on the horizontally moving background, a condition that induces a strong illusion of diagonal target motion, median saccadic error was 4.0 deg horizontally and 1.5 deg vertically; thus the horizontal error was greater than under any other experimental condition. 6. In most trials, the initial saccade to the remembered target was followed by additional saccades while the subject was still in darkness. These secondary saccades, which were executed in the absence of visual feedback, brought the eye closer to the target location. During paradigms involving horizontal background movement, these corrections were more prominent horizontally than vertically. 7. Further measurements were made in two subjects to determine whether inaccuracy of memory-guided saccades, in the horizontal plane, was due to mislocalization at the time that the target flashed, misrepresentation of the trajectory of the pursuit eye movement during the memory period, or both. 8. The magnitude of the saccadic error, both with and without corrections made in darkness, was mislocalized by approximately 30% of the displacement of the background at the time that the target flashed. The magnitude of the saccadic error also was influenced by net movement of the background during the memory period, corresponding to approximately 25% of net background movement for the initial saccade and approximately 13% for the final eye position achieved in darkness. 9. We formulated simple linear models to test specific hypotheses about which combinations of signals best describe the observed saccadic amplitudes. We tested the possibilities that the brain made an accurate memory of target location and a reliable representation of the eye movement during the memory period, or that one or both of these was corrupted by the illusory visual stimulus. Our data were best accounted for by a model in which both the working memory of target location and the internal representation of the horizontal eye movements were corrupted by the illusory visual stimulus. We conclude that extraretinal signals played only a minor role, in comparison with visual estimates of the direction of gaze, in planning eye movements to remembered targ.

Estimation of stochastic volatility with long memory for index prices of FTSE Bursa Malaysia KLCI

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Kho Chia; Kane, Ibrahim Lawal; Rahman, Haliza Abd

In recent years, modeling in long memory properties or fractionally integrated processes in stochastic volatility has been applied in the financial time series. A time series with structural breaks can generate a strong persistence in the autocorrelation function, which is an observed behaviour of a long memory process. This paper considers the structural break of data in order to determine true long memory time series data. Unlike usual short memory models for log volatility, the fractional Ornstein-Uhlenbeck process is neither a Markovian process nor can it be easily transformed into a Markovian process. This makes the likelihood evaluation and parametermore » estimation for the long memory stochastic volatility (LMSV) model challenging tasks. The drift and volatility parameters of the fractional Ornstein-Unlenbeck model are estimated separately using the least square estimator (lse) and quadratic generalized variations (qgv) method respectively. Finally, the empirical distribution of unobserved volatility is estimated using the particle filtering with sequential important sampling-resampling (SIR) method. The mean square error (MSE) between the estimated and empirical volatility indicates that the performance of the model towards the index prices of FTSE Bursa Malaysia KLCI is fairly well.« less

Estimation of stochastic volatility with long memory for index prices of FTSE Bursa Malaysia KLCI

NASA Astrophysics Data System (ADS)

Chen, Kho Chia; Bahar, Arifah; Kane, Ibrahim Lawal; Ting, Chee-Ming; Rahman, Haliza Abd

2015-02-01

In recent years, modeling in long memory properties or fractionally integrated processes in stochastic volatility has been applied in the financial time series. A time series with structural breaks can generate a strong persistence in the autocorrelation function, which is an observed behaviour of a long memory process. This paper considers the structural break of data in order to determine true long memory time series data. Unlike usual short memory models for log volatility, the fractional Ornstein-Uhlenbeck process is neither a Markovian process nor can it be easily transformed into a Markovian process. This makes the likelihood evaluation and parameter estimation for the long memory stochastic volatility (LMSV) model challenging tasks. The drift and volatility parameters of the fractional Ornstein-Unlenbeck model are estimated separately using the least square estimator (lse) and quadratic generalized variations (qgv) method respectively. Finally, the empirical distribution of unobserved volatility is estimated using the particle filtering with sequential important sampling-resampling (SIR) method. The mean square error (MSE) between the estimated and empirical volatility indicates that the performance of the model towards the index prices of FTSE Bursa Malaysia KLCI is fairly well.

Solution processed molecular floating gate for flexible flash memories

NASA Astrophysics Data System (ADS)

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-10-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices.

Solution processed molecular floating gate for flexible flash memories

PubMed Central

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-01-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices. PMID:24172758

Study of the photovoltaic effect in thin film barium titanate

NASA Technical Reports Server (NTRS)

Grannemann, W. W.; Dharmadhikari, V. S.

1983-01-01

The feasibility of making non-volatile digital memory devices of barium titanate, BaTiO3, that are integrated onto a silicon substrate with the required ferroelectric film produced by processing, compatible with silicon technology was examined.

Three-terminal resistive switching memory in a transparent vertical-configuration device

NASA Astrophysics Data System (ADS)

Ungureanu, Mariana; Llopis, Roger; Casanova, Fèlix; Hueso, Luis E.

2014-01-01

The resistive switching phenomenon has attracted much attention recently for memory applications. It describes the reversible change in the resistance of a dielectric between two non-volatile states by the application of electrical pulses. Typical resistive switching memories are two-terminal devices formed by an oxide layer placed between two metal electrodes. Here, we report on the fabrication and operation of a three-terminal resistive switching memory that works as a reconfigurable logic component and offers an increased logic density on chip. The three-terminal memory device we present is transparent and could be further incorporated in transparent computing electronic technologies.

Magnetic vortex racetrack memory

NASA Astrophysics Data System (ADS)

Geng, Liwei D.; Jin, Yongmei M.

2017-02-01

We report a new type of racetrack memory based on current-controlled movement of magnetic vortices in magnetic nanowires with rectangular cross-section and weak perpendicular anisotropy. Data are stored through the core polarity of vortices and each vortex carries a data bit. Besides high density, non-volatility, fast data access, and low power as offered by domain wall racetrack memory, magnetic vortex racetrack memory has additional advantages of no need for constrictions to define data bits, changeable information density, adjustable current magnitude for data propagation, and versatile means of ultrafast vortex core switching. By using micromagnetic simulations, current-controlled motion of magnetic vortices in cobalt nanowire is demonstrated for racetrack memory applications.

Organic memory device with self-assembly monolayered aptamer conjugated nanoparticles

NASA Astrophysics Data System (ADS)

Oh, Sewook; Kim, Minkeun; Kim, Yejin; Jung, Hunsang; Yoon, Tae-Sik; Choi, Young-Jin; Jung Kang, Chi; Moon, Myeong-Ju; Jeong, Yong-Yeon; Park, In-Kyu; Ho Lee, Hyun

2013-08-01

An organic memory structure using monolayered aptamer conjugated gold nanoparticles (Au NPs) as charge storage nodes was demonstrated. Metal-pentacene-insulator-semiconductor device was adopted for the non-volatile memory effect through self assembly monolayer of A10-aptamer conjugated Au NPs, which was formed on functionalized insulator surface with prostate-specific membrane antigen protein. The capacitance versus voltage (C-V) curves obtained for the monolayered Au NPs capacitor exhibited substantial flat-band voltage shift (ΔVFB) or memory window of 3.76 V under (+/-)7 V voltage sweep. The memory device format can be potentially expanded to a highly specific capacitive sensor for the aptamer-specific biomolecule detection.

Feasibility and limitations of anti-fuses based on bistable non-volatile switches for power electronic applications

NASA Astrophysics Data System (ADS)

Erlbacher, T.; Huerner, A.; Bauer, A. J.; Frey, L.

2012-09-01

Anti-fuse devices based on non-volatile memory cells and suitable for power electronic applications are demonstrated for the first time using silicon technology. These devices may be applied as stand alone devices or integrated using standard junction-isolation into application-specific and smart-power integrated circuits. The on-resistance of such devices can be permanently switched by nine orders of magnitude by triggering the anti-fuse with a positive voltage pulse. Extrapolation of measurement data and 2D TCAD process and device simulations indicate that 20 A anti-fuses with 10 mΩ can be reliably fabricated in 0.35 μm technology with a footprint of 2.5 mm2. Moreover, this concept offers distinguished added-values compared to existing mechanical relays, e.g. pre-test, temporary and permanent reset functions, gradual turn-on mode, non-volatility, and extendibility to high voltage capability.

Characterization of Au/PbTi0.5Fe0.5O3/Si structure for possible multiferroic based non-volatile memory applications

NASA Astrophysics Data System (ADS)

Nawaz, S.; Roy, S.; Tulapurkar, A. A.; Palkar, V. R.

2017-03-01

Magnetoelectric multiferroic PbTi0.5Fe0.5O3 films are deposited on a ⟨100⟩ conducting p-Si substrate without any buffer layer by using pulsed laser deposition and characterized for possible non-volatile memory applications. Their crystalline structure and surface morphology were characterized by using x-ray diffraction and AFM techniques. HRTEM was employed to determine the film-substrate interface. The electronic structure of the film was investigated by XPS, and no signature of metal was found for all the elements. The chemical shift of the Ti 2p XPS peak is attributed to the replacement of Ti with Fe in the PbTiO3 matrix. Piezoelectric force microscopy (PFM) results indicate the 180° phase shift of ferroelectric polarization. The upward self-polarization phenomenon is also observed in the PFM study. Magnetic and magneto-electric coupling measurements were carried out to confirm the magnetic nature and electro-magnetic coupling characteristics. C-V measurements exhibit clock-wise hysteresis loops with a maximum memory window of 1.2 V and a sweep voltage of ±7 V. This study could influence the fabrication of silicon compatible multiple memory device structures.

On-chip phase-change photonic memory and computing

NASA Astrophysics Data System (ADS)

Cheng, Zengguang; Ríos, Carlos; Youngblood, Nathan; Wright, C. David; Pernice, Wolfram H. P.; Bhaskaran, Harish

2017-08-01

The use of photonics in computing is a hot topic of interest, driven by the need for ever-increasing speed along with reduced power consumption. In existing computing architectures, photonic data storage would dramatically improve the performance by reducing latencies associated with electrical memories. At the same time, the rise of `big data' and `deep learning' is driving the quest for non-von Neumann and brain-inspired computing paradigms. To succeed in both aspects, we have demonstrated non-volatile multi-level photonic memory avoiding the von Neumann bottleneck in the existing computing paradigm and a photonic synapse resembling the biological synapses for brain-inspired computing using phase-change materials (Ge2Sb2Te5).

A Compute Capable SSD Architecture for Next-Generation Non-volatile Memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

De, Arup

2014-01-01

Existing storage technologies (e.g., disks and ash) are failing to cope with the processor and main memory speed and are limiting the overall perfor- mance of many large scale I/O or data-intensive applications. Emerging fast byte-addressable non-volatile memory (NVM) technologies, such as phase-change memory (PCM), spin-transfer torque memory (STTM) and memristor are very promising and are approaching DRAM-like performance with lower power con- sumption and higher density as process technology scales. These new memories are narrowing down the performance gap between the storage and the main mem- ory and are putting forward challenging problems on existing SSD architecture, I/O interfacemore » (e.g, SATA, PCIe) and software. This dissertation addresses those challenges and presents a novel SSD architecture called XSSD. XSSD o oads com- putation in storage to exploit fast NVMs and reduce the redundant data tra c across the I/O bus. XSSD o ers a exible RPC-based programming framework that developers can use for application development on SSD without dealing with the complication of the underlying architecture and communication management. We have built a prototype of XSSD on the BEE3 FPGA prototyping system. We implement various data-intensive applications and achieve speedup and energy ef- ciency of 1.5-8.9 and 1.7-10.27 respectively. This dissertation also compares XSSD with previous work on intelligent storage and intelligent memory. The existing ecosystem and these new enabling technologies make this system more viable than earlier ones.« less

A non-volatile flip-flop based on diode-selected PCM for ultra-low power systems

NASA Astrophysics Data System (ADS)

Ye, Yong; Du, Yuan; Gao, Dan; Kang, Yong; Song, Zhitang; Chen, Bomy

2016-10-01

As the process technology is continuously shrinking, low power consumption is a major issue in VLSI Systems-on-Chip (SoCs), especially for standby-power-critical applications. Recently, the emerging CMOS-compatible non-volatile memories (NVMs), such as Phase Change Memory (PCM), have been used as on-chip storage elements, which can obtain non-volatile processing, nearly-zero standby power and instant-on capability. PCM has been considered as the best candidate for the next generation of NVMs for its low cost, high density and high resistance transformation ratio. In this paper, for the first time, we present a diode-selected PCM based non-volatile flip-flop (NVFF) which is optimized for better power consumption and process variation tolerance. With dual trench isolation process, the diode-selected PCM realizes ultra small area, which is very suitable for multi-context configuration and large scale flip-flops matrix. Since the MOS-selected PCM is hard to shrink further due to large amount of PCM write current, the proposed NVFF achieves higher power efficiency without loss of current driving capability. Using the 40nm manufacturing process, the area of the cell (1D1R) is as small as 0.016 μm2. Simulation results show that the energy consumption during the recall operation is 62 fJ with 1.1 standard supply voltage, which is reduced by 54.9% compared to the previous 2T2R based NVFF. When the supply voltage reduces to 0.7 V, the recall energy is as low as 17 fJ. With the great advantages in cell size and energy, the proposed diode-selected NVFF is very applicable and cost-effective for ULP systems.

Radiation Effects on Advanced Flash Memories

NASA Technical Reports Server (NTRS)

Nguyen, D. N.; Guertin, S.; Swift, G. M.; Johnston, A. H.

1998-01-01

Flash memories have evolved very rapidly in recent ears. New design techniques such as multilevel storage have been proposed to increase storage density, and are now available commercially. Threshold voltage distributions for single- and three-level technologies are compared. In order to implement this technology special circuitry must be added to allow the amount of charge stored in the floating gate to be controlled within narrow limits during the writing and also to detect the different amounts of charge during reading.

BLACKCOMB2: Hardware-software co-design for non-volatile memory in exascale systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mudge, Trevor

This work was part of a larger project, Blackcomb2, centered at Oak Ridge National Labs (Jeff Vetter PI) to investigate the opportunities for replacing or supplementing DRAM main memory with nonvolatile memory (NVmemory) in Exascale memory systems. The goal was to reduce the energy consumed by in future supercomputer memory systems and to improve their resiliency. Building on the accomplishments of the original Blackcomb Project, funded in 2010, the goal for Blackcomb2 was to identify, evaluate, and optimize the most promising emerging memory technologies, architecture hardware and software technologies, which are essential to provide the necessary memory capacity, performance, resilience,more » and energy efficiency in Exascale systems. Capacity and energy are the key drivers.« less

Interactions of numerical and temporal stimulus characteristics on the control of response location by brief flashes of light.

PubMed

Fetterman, J Gregor; Killeen, P Richard

2011-09-01

Pigeons pecked on three keys, responses to one of which could be reinforced after 3 flashes of the houselight, to a second key after 6, and to a third key after 12. The flashes were arranged according to variable-interval schedules. Response allocation among the keys was a function of the number of flashes. When flashes were omitted, transitions occurred very late. Increasing flash duration produced a leftward shift in the transitions along a number axis. Increasing reinforcement probability produced a leftward shift, and decreasing reinforcement probability produced a rightward shift. Intermixing different flash rates within sessions separated allocations: Faster flash rates shifted the functions sooner in real time, but later in terms of flash count, and conversely for slower flash rates. A model of control by fading memories of number and time was proposed.

Non-volatile Clocked Spin Wave Interconnect for Beyond-CMOS Nanomagnet Pipelines

PubMed Central

Dutta, Sourav; Chang, Sou-Chi; Kani, Nickvash; Nikonov, Dmitri E.; Manipatruni, Sasikanth; Young, Ian A.; Naeemi, Azad

2015-01-01

The possibility of using spin waves for information transmission and processing has been an area of active research due to the unique ability to manipulate the amplitude and phase of the spin waves for building complex logic circuits with less physical resources and low power consumption. Previous proposals on spin wave logic circuits have suggested the idea of utilizing the magneto-electric effect for spin wave amplification and amplitude- or phase-dependent switching of magneto-electric cells. Here, we propose a comprehensive scheme for building a clocked non-volatile spin wave device by introducing a charge-to-spin converter that translates information from electrical domain to spin domain, magneto-electric spin wave repeaters that operate in three different regimes - spin wave transmitter, non-volatile memory and spin wave detector, and a novel clocking scheme that ensures sequential transmission of information and non-reciprocity. The proposed device satisfies the five essential requirements for logic application: nonlinearity, amplification, concatenability, feedback prevention, and complete set of Boolean operations. PMID:25955353

3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate

NASA Astrophysics Data System (ADS)

Oh, Jae-Sub; Yang, Seong-Dong; Lee, Sang-Youl; Kim, Young-Su; Kang, Min-Ho; Lim, Sung-Kyu; Lee, Hi-Deok; Lee, Ga-Won

2013-08-01

In this paper, a gate-all-around bandgap-engineered silicon-oxide-nitride-oxide-silicon device with a vertical silicon pillar structure and a Ti metal gate are demonstrated for a potential solution to overcome the scaling-down of flash memory device. The devices were fabricated using CMOS-compatible technology and exhibited well-behaved memory characteristics in terms of the program/erase window, retention, and endurance properties. Moreover, the integration of the Ti metal gate demonstrated a significant improvement in the erase characteristics due to the efficient suppression of the electron back tunneling through the blocking oxide.

Effects of botanicals and combined hormone therapy on cognition in postmenopausal women.

PubMed

Maki, Pauline M; Rubin, Leah H; Fornelli, Deanne; Drogos, Lauren; Banuvar, Suzanne; Shulman, Lee P; Geller, Stacie E

2009-01-01

The aim of this study was to characterize the effects of red clover, black cohosh, and combined hormone therapy on cognitive function in comparison to placebo in women with moderate to severe vasomotor symptoms. In a phase II randomized, double-blind, placebo-controlled study, 66 midlife women (of 89 from a parent study; mean age, 53 y) with 35 or more weekly hot flashes were randomized to receive red clover (120 mg), black cohosh (128 mg), 0.625 mg conjugated equine estrogens plus 2.5 mg medroxyprogesterone acetate (CEE/MPA), or placebo. Participants completed measures of verbal memory (primary outcome) and other cognitive measures (secondary outcomes) before and during the 12th treatment month. A subset of 19 women completed objective, physiological measures of hot flashes using ambulatory skin conductance monitors. Neither of the botanical treatments had an impact on any cognitive measure. Compared with placebo, CEE/MPA led to a greater decline in verbal learning (one of five verbal memory measures). This effect just missed statistical significance (P = 0.057) in unadjusted analyses but reached significance (P = 0.02) after adjusting for vasomotor symptoms. Neither of the botanical treatment groups showed a change in verbal memory that differed from the placebo group (Ps > 0.28), even after controlling for improvements in hot flashes. In secondary outcomes, CEE/MPA led to a decrease in immediate digit recall and an improvement in letter fluency. Only CEE/MPA significantly reduced objective hot flashes. Results indicate that a red clover (phytoestrogen) supplement or black cohosh has no effects on cognitive function. CEE/MPA reduces objective hot flashes but worsens some aspects of verbal memory.

Effects of Botanicals and Combined Hormone Therapy on Cognition in Postmenopausal Women

PubMed Central

Maki, Pauline M.; Rubin, Leah H.; Fornelli, Deanne; Drogos, Lauren; Banuvar, Suzanne; Shulman, Lee P.; Geller, Stacie E.

2009-01-01

Objective To characterize the effects of red clover, black cohosh, and combined hormone therapy on cognitive function in comparison to placebo in women with moderate to severe vasomotor symptoms. Design In a Phase II randomized, double-blind, placebo-controlled study, 66 midlife women (out of 89 from a parent study; mean age=53 y) with ≥ 35 weekly hot flashes were randomized to receive red clover (120 mg), black cohosh (128 mg), CEE/MPA (0.625 mg conjugated equine estrogens plus 2.5 mg medroxyprogesterone acetate), or placebo. Participants completed measures of verbal memory (primary outcome) and other cognitive measures (secondary outcomes) before and during the 12th treatment month. A subset of 19 women completed objective, physiological measures of hot flashes using ambulatory skin conductance monitors. Results There was no impact of either of the botanical treatments on any cognitive measure. Compared to placebo, CEE/MPA led to greater decline in verbal learning (one of five verbal memory measures). This effect just missed statistical significance (p=0.057) in unadjusted analyses, but reached significance (p=.02) after adjusting for vasomotor symptoms. Neither botanical treatment group showed a change in verbal memory that differed from the placebo group (ps>0.28), even after controlling for improvements in hot flashes. In secondary outcomes, CEE/MPA led to a decrease in immediate digit recall and an improvement in letter fluency. Only CEE/MPA significantly reduced objective hot flashes. Conclusions Results indicate no effects of a red clover (phytoestrogen) supplement or black cohosh on cognitive function. CEE/MPA reduces objective hot flashes but worsens some aspects of verbal memory. PMID:19590458

Hafnia-based resistive switching devices for non-volatile memory applications and effects of gamma irradiation on device performance

NASA Astrophysics Data System (ADS)

Arun, N.; Kumar, K. Vinod; Pathak, A. P.; Avasthi, D. K.; Nageswara Rao, S. V. S.

2018-04-01

Non-volatile memory (NVM) devices were fabricated as a Metal- Insulator-Metal (MIM) structures by sandwiching Hafnium dioxide (HfO2) thin film in between two metal electrodes. The top and bottom metal electrodes were deposited by using the thermal evaporation, and the oxide layer was deposited by using the RF magnetron sputtering technique. The Resistive Random Access Memory (RRAM) device structures such as Ag/HfO2/Au/Si were fabricated and I-V characteristics for the pristine and gamma-irradiated devices with a dose 24 kGy were measured. Further we have studied the thermal annealing effects, in the range of 100°-400°C in a tubular furnace for the HfO2/Au/Si samples. The X-ray diffraction (XRD), Rutherford Backscattering Spectrometry (RBS), field emission-scanning electron microscopy (FESEM) analysis measurements were performed to determine the thickness, crystallinity and stoichiometry of these films. The electrical characteristics such as resistive switching, endurance, retention time and switching speed were measured by a semiconductor device analyser. The effects of gamma irradiation on the switching properties of these RRAM devices have been studied.

Facile fabrication of highly ordered poly(vinylidene fluoride-trifluoroethylene) nanodot arrays for organic ferroelectric memory

NASA Astrophysics Data System (ADS)

Fang, Huajing; Yan, Qingfeng; Geng, Chong; Chan, Ngai Yui; Au, Kit; Yao, Jianjun; Ng, Sheung Mei; Leung, Chi Wah; Li, Qiang; Guo, Dong; Wa Chan, Helen Lai; Dai, Jiyan

2016-01-01

Nano-patterned ferroelectric materials have attracted significant attention as the presence of two or more thermodynamically equivalent switchable polarization states can be employed in many applications such as non-volatile memory. In this work, a simple and effective approach for fabrication of highly ordered poly(vinylidene fluoride-trifluoroethylene) P(VDF-TrFE) nanodot arrays is demonstrated. By using a soft polydimethylsiloxane mold, we successfully transferred the 2D array pattern from the initial monolayer of colloidal polystyrene nanospheres to the imprinted P(VDF-TrFE) films via nanoimprinting. The existence of a preferred orientation of the copolymer chain after nanoimprinting was confirmed by Fourier transform infrared spectra. Local polarization switching behavior was measured by piezoresponse force microscopy, and each nanodot showed well-formed hysteresis curve and butterfly loop with a coercive field of ˜62.5 MV/m. To illustrate the potential application of these ordered P(VDF-TrFE) nanodot arrays, the writing and reading process as non-volatile memory was demonstrated at a relatively low voltage. As such, our results offer a facile and promising route to produce arrays of ferroelectric polymer nanodots with improved piezoelectric functionality.

Sub-10 nm Ta Channel Responsible for Superior Performance of a HfO 2 Memristor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jiang, Hao; Han, Lili; Lin, Peng

Memristive devices are promising candidates for the next generation non-volatile memory and neuromorphic computing. It has been widely accepted that the motion of oxygen anions leads to the resistance changes for valence-change-memory (VCM) type of materials. Only very recently it was speculated that metal cations could also play an important role, but no direct physical characterizations have been reported yet. We report a Ta/HfO 2/Pt memristor with fast switching speed, record high endurance (120 billion cycles) and reliable retention. We also programmed the device to 24 discrete resistance levels, and also demonstrated over a million (220) epochs of potentiation andmore » depression, suggesting that our devices can be used for both multi-level non-volatile memory and neuromorphic computing applications. More importantly, we directly observed a sub-10 nm Ta-rich and O-deficient conduction channel within the HfO 2 layer that is responsible for the switching. Our work deepens our understanding of the resistance switching mechanism behind oxide-based memristive devices and paves the way for further device performance optimization for a broad spectrum of applications.« less

Redefining the Speed Limit of Phase Change Memory Revealed by Time-resolved Steep Threshold-Switching Dynamics of AgInSbTe Devices

NASA Astrophysics Data System (ADS)

Shukla, Krishna Dayal; Saxena, Nishant; Durai, Suresh; Manivannan, Anbarasu

2016-11-01

Although phase-change memory (PCM) offers promising features for a ‘universal memory’ owing to high-speed and non-volatility, achieving fast electrical switching remains a key challenge. In this work, a correlation between the rate of applied voltage and the dynamics of threshold-switching is investigated at picosecond-timescale. A distinct characteristic feature of enabling a rapid threshold-switching at a critical voltage known as the threshold voltage as validated by an instantaneous response of steep current rise from an amorphous off to on state is achieved within 250 picoseconds and this is followed by a slower current rise leading to crystallization. Also, we demonstrate that the extraordinary nature of threshold-switching dynamics in AgInSbTe cells is independent to the rate of applied voltage unlike other chalcogenide-based phase change materials exhibiting the voltage dependent transient switching characteristics. Furthermore, numerical solutions of time-dependent conduction process validate the experimental results, which reveal the electronic nature of threshold-switching. These findings of steep threshold-switching of ‘sub-50 ps delay time’, opens up a new way for achieving high-speed non-volatile memory for mainstream computing.

Sub-10 nm Ta Channel Responsible for Superior Performance of a HfO 2 Memristor

DOE PAGES

Jiang, Hao; Han, Lili; Lin, Peng; ...

2016-06-23

Memristive devices are promising candidates for the next generation non-volatile memory and neuromorphic computing. It has been widely accepted that the motion of oxygen anions leads to the resistance changes for valence-change-memory (VCM) type of materials. Only very recently it was speculated that metal cations could also play an important role, but no direct physical characterizations have been reported yet. We report a Ta/HfO 2/Pt memristor with fast switching speed, record high endurance (120 billion cycles) and reliable retention. We also programmed the device to 24 discrete resistance levels, and also demonstrated over a million (220) epochs of potentiation andmore » depression, suggesting that our devices can be used for both multi-level non-volatile memory and neuromorphic computing applications. More importantly, we directly observed a sub-10 nm Ta-rich and O-deficient conduction channel within the HfO 2 layer that is responsible for the switching. Our work deepens our understanding of the resistance switching mechanism behind oxide-based memristive devices and paves the way for further device performance optimization for a broad spectrum of applications.« less

Hydrocarbon emissions characterization in the Colorado Front Range: A pilot study

NASA Astrophysics Data System (ADS)

Pétron, Gabrielle; Frost, Gregory; Miller, Benjamin R.; Hirsch, Adam I.; Montzka, Stephen A.; Karion, Anna; Trainer, Michael; Sweeney, Colm; Andrews, Arlyn E.; Miller, Lloyd; Kofler, Jonathan; Bar-Ilan, Amnon; Dlugokencky, Ed J.; Patrick, Laura; Moore, Charles T., Jr.; Ryerson, Thomas B.; Siso, Carolina; Kolodzey, William; Lang, Patricia M.; Conway, Thomas; Novelli, Paul; Masarie, Kenneth; Hall, Bradley; Guenther, Douglas; Kitzis, Duane; Miller, John; Welsh, David; Wolfe, Dan; Neff, William; Tans, Pieter

2012-02-01

The multispecies analysis of daily air samples collected at the NOAA Boulder Atmospheric Observatory (BAO) in Weld County in northeastern Colorado since 2007 shows highly correlated alkane enhancements caused by a regionally distributed mix of sources in the Denver-Julesburg Basin. To further characterize the emissions of methane and non-methane hydrocarbons (propane, n-butane, i-pentane, n-pentane and benzene) around BAO, a pilot study involving automobile-based surveys was carried out during the summer of 2008. A mix of venting emissions (leaks) of raw natural gas and flashing emissions from condensate storage tanks can explain the alkane ratios we observe in air masses impacted by oil and gas operations in northeastern Colorado. Using the WRAP Phase III inventory of total volatile organic compound (VOC) emissions from oil and gas exploration, production and processing, together with flashing and venting emission speciation profiles provided by State agencies or the oil and gas industry, we derive a range of bottom-up speciated emissions for Weld County in 2008. We use the observed ambient molar ratios and flashing and venting emissions data to calculate top-down scenarios for the amount of natural gas leaked to the atmosphere and the associated methane and non-methane emissions. Our analysis suggests that the emissions of the species we measured are most likely underestimated in current inventories and that the uncertainties attached to these estimates can be as high as a factor of two.

Titanium oxide nonvolatile memory device and its application

NASA Astrophysics Data System (ADS)

Wang, Wei

In recent years, the semiconductor memory industry has seen an ever-increasing demand for nonvolatile memory (NVM), which is fueled by portable consumer electronic applications like the mobile phone and MP3 player. FLASH memory has been the most widely used nonvolatile memories in these systems, and has successfully kept up with CMOS scaling for many generations. However, as FLASH memory faces major scaling challenges beyond 22nm, non-charge-based nonvolatile memories are widely researched as candidates to replace FLASH. Titanium oxide (TiOx) nonvolatile memory device is considered to be a promising choice due to its controllable nonvolatile memory switching, good scalability, compatibility with CMOS processing and potential for 3D stacking. However, several major issues need to be overcome before TiOx NVM device can be adopted in manufacturing. First, there exists a highly undesirable high-voltage stress initiation process (FORMING) before the device can switch between high and low resistance states repeatedly. By analyzing the conductive behaviors of the memory device before and after FORMING, we propose that FORMING involves breaking down an interfacial layer between its Pt electrode and the TiOx thin film, and that FORMING is not needed if the Pt-TiOx interface can be kept clean during fabrication. An in-situ fabrication process is developed for cross-point TiOx NVM device, which enables in-situ deposition of the critical layers of the memory device and thus achieves clean interfaces between Pt electrodes and TiOx film. Testing results show that FORMING is indeed eliminated for memory devices made with the in-situ fabrication process. It verifies the significance of in-situ deposition without vacuum break in the fabrication of TiOx NVM devices. Switching parameters statistics of TiOx NVM devices are studied and compared for unipolar and bipolar switching modes. RESET mechanisms are found to be different for the two switching modes: unipolar switching can be explained by thermal dissolution model, and bipolar switching by local redox reaction model. Since it is generally agreed that the memory switching of TiOx NVM devices is based on conductive filaments, reusability of these conductive filaments becomes an intriguing issue to determine the memory device's endurance. A 1X3 cross-point test structure is built to investigate whether conductive filaments can be reused after RESET. It is found that the conductive filament is destroyed during unipolar switching, while can be reused during bipolar switching. The result is a good indication that bipolar switching should have better endurance than unipolar switching. Finally a novel application of the two-terminal resistive switching NVM devices is demonstrated. To reduce SRAM leakage power, we propose a nonvolatile SRAM cell with two back-up NVM devices. This novel cell offers nonvolatile storage, thus allowing selected blocks of SRAM to be powered down during operation. There is no area penalty in this approach. Only a slight performance penalty is expected.

Electric-field-controlled interface dipole modulation for Si-based memory devices.

PubMed

Miyata, Noriyuki

2018-05-31

Various nonvolatile memory devices have been investigated to replace Si-based flash memories or emulate synaptic plasticity for next-generation neuromorphic computing. A crucial criterion to achieve low-cost high-density memory chips is material compatibility with conventional Si technologies. In this paper, we propose and demonstrate a new memory concept, interface dipole modulation (IDM) memory. IDM can be integrated as a Si field-effect transistor (FET) based memory device. The first demonstration of this concept employed a HfO 2 /Si MOS capacitor where the interface monolayer (ML) TiO 2 functions as a dipole modulator. However, this configuration is unsuitable for Si-FET-based devices due to its large interface state density (D it ). Consequently, we propose, a multi-stacked amorphous HfO 2 /1-ML TiO 2 /SiO 2 IDM structure to realize a low D it and a wide memory window. Herein we describe the quasi-static and pulse response characteristics of multi-stacked IDM MOS capacitors and demonstrate flash-type and analog memory operations of an IDM FET device.

Solution-processed flexible NiO resistive random access memory device

NASA Astrophysics Data System (ADS)

Kim, Soo-Jung; Lee, Heon; Hong, Sung-Hoon

2018-04-01

Non-volatile memories (NVMs) using nanocrystals (NCs) as active materials can be applied to soft electronic devices requiring a low-temperature process because NCs do not require a heat treatment process for crystallization. In addition, memory devices can be implemented simply by using a patterning technique using a solution process. In this study, a flexible NiO ReRAM device was fabricated using a simple NC patterning method that controls the capillary force and dewetting of a NiO NC solution at low temperature. The switching behavior of a NiO NC based memory was clearly observed by conductive atomic force microscopy (c-AFM).

A new non-destructive readout by using photo-recovered surface potential contrast

NASA Astrophysics Data System (ADS)

Wang, Le; Jin, Kui-Juan; Gu, Jun-Xing; Ma, Chao; He, Xu; Zhang, Jiandi; Wang, Can; Feng, Yu; Wan, Qian; Shi, Jin-An; Gu, Lin; He, Meng; Lu, Hui-Bin; Yang, Guo-Zhen

2014-11-01

Ferroelectric random access memory is still challenging in the feature of combination of room temperature stability, non-destructive readout and high intensity storage. As a non-contact and non-destructive information readout method, surface potential has never been paid enough attention because of the unavoidable decay of the surface potential contrast between oppositely polarized domains. That is mainly due to the recombination of the surface movable charges around the domain walls. Here, by introducing a laser beam into the combination of piezoresponse force microscopy and Kelvin probe force microscopy, we demonstrate that the surface potential contrast of BiFeO3 films can be recovered under light illumination. The recovering mechanism is understood based on the redistribution of the photo-induced charges driven by the internal electric field. Furthermore, we have created a 12-cell memory pattern based on BiFeO3 films to show the feasibility of such photo-assisted non-volatile and non-destructive readout of the ferroelectric memory.

Channel doping concentration and cell program state dependence on random telegraph noise spatial and statistical distribution in 30 nm NAND flash memory

NASA Astrophysics Data System (ADS)

Tomita, Toshihiro; Miyaji, Kousuke

2015-04-01

The dependence of spatial and statistical distribution of random telegraph noise (RTN) in a 30 nm NAND flash memory on channel doping concentration NA and cell program state Vth is comprehensively investigated using three-dimensional Monte Carlo device simulation considering random dopant fluctuation (RDF). It is found that single trap RTN amplitude ΔVth is larger at the center of the channel region in the NAND flash memory, which is closer to the jellium (uniform) doping results since NA is relatively low to suppress junction leakage current. In addition, ΔVth peak at the center of the channel decreases in the higher Vth state due to the current concentration at the shallow trench isolation (STI) edges induced by the high vertical electrical field through the fringing capacitance between the channel and control gate. In such cases, ΔVth distribution slope λ cannot be determined by only considering RDF and single trap.

47 CFR 15.611 - General technical requirements.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 47 Telecommunication 1 2010-10-01 2010-10-01 false General technical requirements. 15.611 Section 15.611 Telecommunication FEDERAL COMMUNICATIONS COMMISSION GENERAL RADIO FREQUENCY DEVICES Access... shut-off procedure, by the use of a non-volatile memory, or some other method, to immediately restore...

Memory switches based on metal oxide thin films

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni (Inventor); Thakoor, Anilkumar P. (Inventor); Lambe, John J. (Inventor)

1990-01-01

MnO.sub.2-x thin films (12) exhibit irreversible memory switching (28) with an OFF/ON resistance ratio of at least about 10.sup.3 and the tailorability of ON state (20) resistance. Such films are potentially extremely useful as a connection element in a variety of microelectronic circuits and arrays (24). Such films provide a pre-tailored, finite, non-volatile resistive element at a desired place in an electric circuit, which can be electrically turned OFF (22) or disconnected as desired, by application of an electrical pulse. Microswitch structures (10) constitute the thin film element, contacted by a pair of separate electrodes (16a, 16b) and have a finite, pre-selected ON resistance which is ideally suited, for example, as a programmable binary synaptic connection for electronic implementation of neural network architectures. The MnO.sub.2-x microswitch is non-volatile, patternable, insensitive to ultraviolet light, and adherent to a variety of insulating substrates (14), such as glass and silicon dioxide-coated silicon substrates.

Rapid direct analysis to discriminate geographic origin of extra virgin olive oils by flash gas chromatography electronic nose and chemometrics.

PubMed

Melucci, Dora; Bendini, Alessandra; Tesini, Federica; Barbieri, Sara; Zappi, Alessandro; Vichi, Stefania; Conte, Lanfranco; Gallina Toschi, Tullia

2016-08-01

At present, the geographical origin of extra virgin olive oils can be ensured by documented traceability, although chemical analysis may add information that is useful for possible confirmation. This preliminary study investigated the effectiveness of flash gas chromatography electronic nose and multivariate data analysis to perform rapid screening of commercial extra virgin olive oils characterized by a different geographical origin declared in the label. A comparison with solid phase micro extraction coupled to gas chromatography mass spectrometry was also performed. The new method is suitable to verify the geographic origin of extra virgin olive oils based on principal components analysis and discriminant analysis applied to the volatile profile of the headspace as a fingerprint. The selected variables were suitable in discriminating between "100% Italian" and "non-100% Italian" oils. Partial least squares discriminant analysis also allowed prediction of the degree of membership of unknown samples to the classes examined. Copyright © 2016. Published by Elsevier Ltd.

Italian and Spanish commercial tomato sauces for pasta dressing: study of sensory and head-space profiles by Flash Profiling and solid-phase microextraction-gas chomatography-mass spectrometry.

PubMed

Bendini, Alessandra; Vallverdú-Queralt, Anna; Valli, Enrico; Palagano, Rosa; Lamuela-Raventos, Rosa Maria; Toschi, Tullia Gallina

2017-08-01

The sensory and head-space profiles of Italian and Spanish commercial tomato sauces were investigated. The Flash Profiling method was used to evaluate sensory characteristics. Samples within each set were ranked according to selected descriptors. One hundred volatile compounds were identified by solid-phase microextraction-gas chomatography-mass spectrometry. For Italian samples, the sensory notes of basil/aromatic herbs, acid and cooked tomato were among those perceived most by the assessors, whereas, in Spanish samples, the sensory attributes of garlic/onion and onion/sweet pepper and, in Italian samples, cooked tomato were among those found most frequently. Data were elaborated using multivariate statistical approaches and interesting correlations were observed among the different sensory attributes and related volatile compounds. Spanish samples were characterized by the highest content of volatiles linked to the thermal treatment of tomatoes and to raw and sautéed garlic and onion, whereas the Italian samples were characterized by terpenic compounds typical of basil and volatile molecules derived from fresh tomato. These results confirm the influence of both formulation and production processes on the aromatic profile (sensory attributes and volatile compounds) of tomato products, which is probably related to the different eating habits and culinary traditions in Italy and Spain. © 2016 Society of Chemical Industry. © 2016 Society of Chemical Industry.

The influence of cognitive load on spatial search performance.

PubMed

Longstaffe, Kate A; Hood, Bruce M; Gilchrist, Iain D

2014-01-01

During search, executive function enables individuals to direct attention to potential targets, remember locations visited, and inhibit distracting information. In the present study, we investigated these executive processes in large-scale search. In our tasks, participants searched a room containing an array of illuminated locations embedded in the floor. The participants' task was to press the switches at the illuminated locations on the floor so as to locate a target that changed color when pressed. The perceptual salience of the search locations was manipulated by having some locations flashing and some static. Participants were more likely to search at flashing locations, even when they were explicitly informed that the target was equally likely to be at any location. In large-scale search, attention was captured by the perceptual salience of the flashing lights, leading to a bias to explore these targets. Despite this failure of inhibition, participants were able to restrict returns to previously visited locations, a measure of spatial memory performance. Participants were more able to inhibit exploration to flashing locations when they were not required to remember which locations had previously been visited. A concurrent digit-span memory task further disrupted inhibition during search, as did a concurrent auditory attention task. These experiments extend a load theory of attention to large-scale search, which relies on egocentric representations of space. High cognitive load on working memory leads to increased distractor interference, providing evidence for distinct roles for the executive subprocesses of memory and inhibition during large-scale search.

Multibit Polycristalline Silicon-Oxide-Silicon Nitride-Oxide-Silicon Memory Cells with High Density Designed Utilizing a Separated Control Gate

NASA Astrophysics Data System (ADS)

Rok Kim, Kyeong; You, Joo Hyung; Dal Kwack, Kae; Kim, Tae Whan

2010-10-01

Unique multibit NAND polycrystalline silicon-oxide-silicon nitride-oxide-silicon (SONOS) memory cells utilizing a separated control gate (SCG) were designed to increase memory density. The proposed NAND SONOS memory device based on a SCG structure was operated as two bits, resulting in an increase in the storage density of the NVM devices in comparison with conventional single-bit memories. The electrical properties of the SONOS memory cells with a SCG were investigated to clarify the charging effects in the SONOS memory cells. When the program voltage was supplied to each gate of the NAND SONOS flash memory cells, the electrons were trapped in the nitride region of the oxide-nitride-oxide layer under the gate to supply the program voltage. The electrons were accumulated without affecting the other gate during the programming operation, indicating the absence of cross-talk between two trap charge regions. It is expected that the inference effect will be suppressed by the lower program voltage than the program voltage of the conventional NAND flash memory. The simulation results indicate that the proposed unique NAND SONOS memory cells with a SCG can be used to increase memory density.

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

NASA Astrophysics Data System (ADS)

Guo, Jiarong

2017-04-01

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper, capable of operating with minimum supply voltage at 1 V. A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current, which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier. A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted, which not only improves the sense window enhancing read precision but also saves power consumption. The sense amplifier was implemented in a flash realized in 90 nm flash technology. Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125 °C. Project supported by the National Natural Science Fundation of China (No. 61376028).

Signal and noise extraction from analog memory elements for neuromorphic computing.

PubMed

Gong, N; Idé, T; Kim, S; Boybat, I; Sebastian, A; Narayanan, V; Ando, T

2018-05-29

Dense crossbar arrays of non-volatile memory (NVM) can potentially enable massively parallel and highly energy-efficient neuromorphic computing systems. The key requirements for the NVM elements are continuous (analog-like) conductance tuning capability and switching symmetry with acceptable noise levels. However, most NVM devices show non-linear and asymmetric switching behaviors. Such non-linear behaviors render separation of signal and noise extremely difficult with conventional characterization techniques. In this study, we establish a practical methodology based on Gaussian process regression to address this issue. The methodology is agnostic to switching mechanisms and applicable to various NVM devices. We show tradeoff between switching symmetry and signal-to-noise ratio for HfO 2 -based resistive random access memory. Then, we characterize 1000 phase-change memory devices based on Ge 2 Sb 2 Te 5 and separate total variability into device-to-device variability and inherent randomness from individual devices. These results highlight the usefulness of our methodology to realize ideal NVM devices for neuromorphic computing.

Two-dimensional non-volatile programmable p-n junctions

NASA Astrophysics Data System (ADS)

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Non-Volatile Ferroelectric Switching of Ferromagnetic Resonance in NiFe/PLZT Multiferroic Thin Film Heterostructures.

PubMed

Hu, Zhongqiang; Wang, Xinjun; Nan, Tianxiang; Zhou, Ziyao; Ma, Beihai; Chen, Xiaoqin; Jones, John G; Howe, Brandon M; Brown, Gail J; Gao, Yuan; Lin, Hwaider; Wang, Zhiguang; Guo, Rongdi; Chen, Shuiyuan; Shi, Xiaoling; Shi, Wei; Sun, Hongzhi; Budil, David; Liu, Ming; Sun, Nian X

2016-09-01

Magnetoelectric effect, arising from the interfacial coupling between magnetic and electrical order parameters, has recently emerged as a robust means to electrically manipulate the magnetic properties in multiferroic heterostructures. Challenge remains as finding an energy efficient way to modify the distinct magnetic states in a reliable, reversible, and non-volatile manner. Here we report ferroelectric switching of ferromagnetic resonance in multiferroic bilayers consisting of ultrathin ferromagnetic NiFe and ferroelectric Pb0.92La0.08Zr0.52Ti0.48O3 (PLZT) films, where the magnetic anisotropy of NiFe can be electrically modified by low voltages. Ferromagnetic resonance measurements confirm that the interfacial charge-mediated magnetoelectric effect is dominant in NiFe/PLZT heterostructures. Non-volatile modification of ferromagnetic resonance field is demonstrated by applying voltage pulses. The ferroelectric switching of magnetic anisotropy exhibits extensive applications in energy-efficient electronic devices such as magnetoelectric random access memories, magnetic field sensors, and tunable radio frequency (RF)/microwave devices.

Non-Volatile Ferroelectric Switching of Ferromagnetic Resonance in NiFe/PLZT Multiferroic Thin Film Heterostructures

PubMed Central

Hu, Zhongqiang; Wang, Xinjun; Nan, Tianxiang; Zhou, Ziyao; Ma, Beihai; Chen, Xiaoqin; Jones, John G.; Howe, Brandon M.; Brown, Gail J.; Gao, Yuan; Lin, Hwaider; Wang, Zhiguang; Guo, Rongdi; Chen, Shuiyuan; Shi, Xiaoling; Shi, Wei; Sun, Hongzhi; Budil, David; Liu, Ming; Sun, Nian X.

2016-01-01

Magnetoelectric effect, arising from the interfacial coupling between magnetic and electrical order parameters, has recently emerged as a robust means to electrically manipulate the magnetic properties in multiferroic heterostructures. Challenge remains as finding an energy efficient way to modify the distinct magnetic states in a reliable, reversible, and non-volatile manner. Here we report ferroelectric switching of ferromagnetic resonance in multiferroic bilayers consisting of ultrathin ferromagnetic NiFe and ferroelectric Pb0.92La0.08Zr0.52Ti0.48O3 (PLZT) films, where the magnetic anisotropy of NiFe can be electrically modified by low voltages. Ferromagnetic resonance measurements confirm that the interfacial charge-mediated magnetoelectric effect is dominant in NiFe/PLZT heterostructures. Non-volatile modification of ferromagnetic resonance field is demonstrated by applying voltage pulses. The ferroelectric switching of magnetic anisotropy exhibits extensive applications in energy-efficient electronic devices such as magnetoelectric random access memories, magnetic field sensors, and tunable radio frequency (RF)/microwave devices. PMID:27581071

Non-Volatile Ferroelectric Switching of Ferromagnetic Resonance in NiFe/PLZT Multiferroic Thin Film Heterostructures

NASA Astrophysics Data System (ADS)

Hu, Zhongqiang; Wang, Xinjun; Nan, Tianxiang; Zhou, Ziyao; Ma, Beihai; Chen, Xiaoqin; Jones, John G.; Howe, Brandon M.; Brown, Gail J.; Gao, Yuan; Lin, Hwaider; Wang, Zhiguang; Guo, Rongdi; Chen, Shuiyuan; Shi, Xiaoling; Shi, Wei; Sun, Hongzhi; Budil, David; Liu, Ming; Sun, Nian X.

2016-09-01

Magnetoelectric effect, arising from the interfacial coupling between magnetic and electrical order parameters, has recently emerged as a robust means to electrically manipulate the magnetic properties in multiferroic heterostructures. Challenge remains as finding an energy efficient way to modify the distinct magnetic states in a reliable, reversible, and non-volatile manner. Here we report ferroelectric switching of ferromagnetic resonance in multiferroic bilayers consisting of ultrathin ferromagnetic NiFe and ferroelectric Pb0.92La0.08Zr0.52Ti0.48O3 (PLZT) films, where the magnetic anisotropy of NiFe can be electrically modified by low voltages. Ferromagnetic resonance measurements confirm that the interfacial charge-mediated magnetoelectric effect is dominant in NiFe/PLZT heterostructures. Non-volatile modification of ferromagnetic resonance field is demonstrated by applying voltage pulses. The ferroelectric switching of magnetic anisotropy exhibits extensive applications in energy-efficient electronic devices such as magnetoelectric random access memories, magnetic field sensors, and tunable radio frequency (RF)/microwave devices.

Two-dimensional non-volatile programmable p-n junctions.

PubMed

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe 2 /hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 10 4 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

A novel architecture of non-volatile magnetic arithmetic logic unit using magnetic tunnel junctions

NASA Astrophysics Data System (ADS)

Guo, Wei; Prenat, Guillaume; Dieny, Bernard

2014-04-01

Complementary metal-oxide-semiconductor (CMOS) technology is facing increasingly difficult obstacles such as power consumption and interconnection delay. Novel hybrid technologies and architectures are being investigated with the aim to circumvent some of these limits. In particular, hybrid CMOS/magnetic technology based on magnetic tunnel junctions (MTJs) is considered as a very promising approach thanks to the full compatibility of MTJs with CMOS technology. By tightly merging the conventional electronics with magnetism, both logic and memory functions can be implemented in the same device. As a result, non-volatility is directly brought into logic circuits, yielding significant improvement of device performances and new functionalities as well. We have conceived an innovative methodology to construct non-volatile magnetic arithmetic logic units (MALUs) combining spin-transfer torque MTJs with MOS transistors. The present 4-bit MALU utilizes 4 MTJ pairs to store its operation code (opcode). Its operations and performances have been confirmed and evaluated through electrical simulations.

SSD Market Overview

NASA Astrophysics Data System (ADS)

Wong, G.

The unparalleled cost and form factor advantages of NAND flash memory has driven 35 mm photographic film, floppy disks and one-inch hard drives to extinction. Due to its compelling price/performance characteristics, NAND Flash memory is now expanding its reach into the once-exclusive domain of hard disk drives and DRAM in the form of Solid State Drives (SSDs). Driven by the proliferation of thin and light mobile devices and the need for near-instantaneous accessing and sharing of content through the cloud, SSDs are expected to become a permanent fixture in the computing infrastructure.

Total Ionizing Dose Influence on the Single Event Effect Sensitivity in Samsung 8Gb NAND Flash Memories

NASA Astrophysics Data System (ADS)

Edmonds, Larry D.; Irom, Farokh; Allen, Gregory R.

2017-08-01

A recent model provides risk estimates for the deprogramming of initially programmed floating gates via prompt charge loss produced by an ionizing radiation environment. The environment can be a mixture of electrons, protons, and heavy ions. The model requires several input parameters. This paper extends the model to include TID effects in the control circuitry by including one additional parameter. Parameters intended to produce conservative risk estimates for the Samsung 8 Gb SLC NAND flash memory are given, subject to some qualifications.

Composition-dependent nanoelectronics of amido-phenazines: non-volatile RRAM and WORM memory devices.

PubMed

Maiti, Dilip K; Debnath, Sudipto; Nawaz, Sk Masum; Dey, Bapi; Dinda, Enakhi; Roy, Dipanwita; Ray, Sudipta; Mallik, Abhijit; Hussain, Syed A

2017-10-17

A metal-free three component cyclization reaction with amidation is devised for direct synthesis of DFT-designed amido-phenazine derivative bearing noncovalent gluing interactions to fabricate organic nanomaterials. Composition-dependent organic nanoelectronics for nonvolatile memory devices are discovered using mixed phenazine-stearic acid (SA) nanomaterials. We discovered simultaneous two different types of nonmagnetic and non-moisture sensitive switching resistance properties of fabricated devices utilizing mixed organic nanomaterials: (a) sample-1(8:SA = 1:3) is initially off, turning on at a threshold, but it does not turn off again with the application of any voltage, and (b) sample-2 (8:SA = 3:1) is initially off, turning on at a sharp threshold and off again by reversing the polarity. No negative differential resistance is observed in either type. These samples have different device implementations: sample-1 is attractive for write-once-read-many-times memory devices, such as novel non-editable database, archival memory, electronic voting, radio frequency identification, sample-2 is useful for resistive-switching random access memory application.

Long Memory in STOCK Market Volatility: the International Evidence

NASA Astrophysics Data System (ADS)

Yang, Chunxia; Hu, Sen; Xia, Bingying; Wang, Rui

2012-08-01

It is still a hot topic to catch the auto-dependence behavior of volatility. Here, based on the measurement of average volatility, under different observation window size, we investigated the dependence of successive volatility of several main stock indices and their simulated GARCH(1, 1) model, there were obvious linear auto-dependence in the logarithm of volatility under a small observation window size and nonlinear auto-dependence under a big observation. After calculating the correlation and mutual information of the logarithm of volatility for Dow Jones Industrial Average during different periods, we find that some influential events can change the correlation structure and the volatilities of different periods have distinct influence on that of the remote future. Besides, GARCH model could produce similar behavior of dependence as real data and long memory property. But our analyses show that the auto-dependence of volatility in GARCH is different from that in real data, and the long memory is undervalued by GARCH.

61 FR 41385 - Notice of Government-Owned Inventions; Availability for Licensing

Federal Register 2010, 2011, 2012, 2013, 2014

1996-08-08

... PRESSURE VESSEL; filed 24 February 1995; patented 21 November 1995.// Patent 5,468,356: LARGE SCALE...,477,482: ULTRA HIGH DENSITY, NON- VOLATILE FERROMAGNETIC RANDOM ACCESS MEMORY; filed 1 October 1993....// Patent 5,483,017: HIGH TEMPERATURE THERMOSETS AND CERAMICS DERIVED FROM LINEAR CARBORANE-(SILOXANE OR...

Design and realization of flash translation layer in tiny embedded system

NASA Astrophysics Data System (ADS)

Ren, Xiaoping; Sui, Chaoya; Luo, Zhenghua; Cao, Wenji

2018-05-01

We design a solution of tiny embedded device NAND Flash storage system on the basis of deeply studying the characteristics of widely used NAND Flash in the embedded devices in order to adapt to the development of intelligent interconnection trend and solve the storage problem of large data volume in tiny embedded system. The hierarchical structure and function purposes of the system are introduced. The design and realization of address mapping, error correction, bad block management, wear balance, garbage collection and other algorithms in flash memory transformation layer are described in details. NAND Flash drive and management are realized on STM32 micro-controller, thereby verifying design effectiveness and feasibility.

Electrically-controlled nonlinear switching and multi-level storage characteristics in WOx film-based memory cells

NASA Astrophysics Data System (ADS)

Duan, W. J.; Wang, J. B.; Zhong, X. L.

2018-05-01

Resistive switching random access memory (RRAM) is considered as a promising candidate for the next generation memory due to its scalability, high integration density and non-volatile storage characteristics. Here, the multiple electrical characteristics in Pt/WOx/Pt cells are investigated. Both of the nonlinear switching and multi-level storage can be achieved by setting different compliance current in the same cell. The correlations among the current, time and temperature are analyzed by using contours and 3D surfaces. The switching mechanism is explained in terms of the formation and rupture of conductive filament which is related to oxygen vacancies. The experimental results show that the non-stoichiometric WOx film-based device offers a feasible way for the applications of oxide-based RRAMs.

Preparation and characterization of Sb2Se3 devices for memory applications

NASA Astrophysics Data System (ADS)

Shylashree, N.; Uma B., V.; Dhanush, S.; Abachi, Sagar; Nisarga, A.; Aashith, K.; Sangeetha B., G.

2018-05-01

In this paper, A phase change material of Sb2Se3 was proposed for non volatile memory application. The thin film device preparation and characterization were carried out. The deposition method used was vapor evaporation technique and a thickness of 180nm was deposited. The switching between the SET and RESET state is shown by the I-V characterization. The change of phase was studied using R-V characterization. Different fundamental modes were also identified using Raman spectroscopy.

ASA-FTL: An adaptive separation aware flash translation layer for solid state drives

DOE PAGES

Xie, Wei; Chen, Yong; Roth, Philip C

2016-11-03

Here, the flash-memory based Solid State Drive (SSD) presents a promising storage solution for increasingly critical data-intensive applications due to its low latency (high throughput), high bandwidth, and low power consumption. Within an SSD, its Flash Translation Layer (FTL) is responsible for exposing the SSD’s flash memory storage to the computer system as a simple block device. The FTL design is one of the dominant factors determining an SSD’s lifespan and performance. To reduce the garbage collection overhead and deliver better performance, we propose a new, low-cost, adaptive separation-aware flash translation layer (ASA-FTL) that combines sampling, data clustering and selectivemore » caching of recency information to accurately identify and separate hot/cold data while incurring minimal overhead. We use sampling for light-weight identification of separation criteria, and our dedicated selective caching mechanism is designed to save the limited RAM resource in contemporary SSDs. Using simulations of ASA-FTL with both real-world and synthetic workloads, we have shown that our proposed approach reduces the garbage collection overhead by up to 28% and the overall response time by 15% compared to one of the most advanced existing FTLs. We find that the data clustering using a small sample size provides significant performance benefit while only incurring a very small computation and memory cost. In addition, our evaluation shows that ASA-FTL is able to adapt to the changes in the access pattern of workloads, which is a major advantage comparing to existing fixed data separation methods.« less

Ferroelectric-field-effect-enhanced electroresistance in metal/ferroelectric/semiconductor tunnel junctions

NASA Astrophysics Data System (ADS)

Wen, Zheng; Li, Chen; Wu, Di; Li, Aidong; Ming, Naiben

2013-07-01

Ferroelectric tunnel junctions (FTJs), composed of two metal electrodes separated by an ultrathin ferroelectric barrier, have attracted much attention as promising candidates for non-volatile resistive memories. Theoretical and experimental works have revealed that the tunnelling resistance switching in FTJs originates mainly from a ferroelectric modulation on the barrier height. However, in these devices, modulation on the barrier width is very limited, although the tunnelling transmittance depends on it exponentially as well. Here we propose a novel tunnelling heterostructure by replacing one of the metal electrodes in a normal FTJ with a heavily doped semiconductor. In these metal/ferroelectric/semiconductor FTJs, not only the height but also the width of the barrier can be electrically modulated as a result of a ferroelectric field effect, leading to a greatly enhanced tunnelling electroresistance. This idea is implemented in Pt/BaTiO3/Nb:SrTiO3 heterostructures, in which an ON/OFF conductance ratio above 104, about one to two orders greater than those reported in normal FTJs, can be achieved at room temperature. The giant tunnelling electroresistance, reliable switching reproducibility and long data retention observed in these metal/ferroelectric/semiconductor FTJs suggest their great potential in non-destructive readout non-volatile memories.

Impact of process parameters on the structural and electrical properties of metal/PZT/Al2O3/silicon gate stack for non-volatile memory applications

NASA Astrophysics Data System (ADS)

Singh, Prashant; Jha, Rajesh Kumar; Singh, Rajat Kumar; Singh, B. R.

2018-02-01

In this paper, we present the structural and electrical properties of the Al2O3 buffer layer on non-volatile memory behavior using Metal/PZT/Al2O3/Silicon structures. Metal/PZT/Silicon and Metal/Al2O3/Silicon structures were also fabricated and characterized to obtain capacitance and leakage current parameters. Lead zirconate titanate (PZT::35:65) and Al2O3 films were deposited by sputtering on the silicon substrate. Memory window, PUND, endurance, breakdown voltage, effective charges, flat-band voltage and leakage current density parameters were measured and the effects of process parameters on the structural and electrical characteristics were investigated. X-ray data show dominant (110) tetragonal phase of the PZT film, which crystallizes at 500 °C. The sputtered Al2O3 film annealed at different temperatures show dominant (312) orientation and amorphous nature at 425 °C. Multiple angle laser ellipsometric analysis reveals the temperature dependence of PZT film refractive index and extinction coefficient. Electrical characterization shows the maximum memory window of 3.9 V and breakdown voltage of 25 V for the Metal/Ferroelectric/Silicon (MFeS) structures annealed at 500 °C. With 10 nm Al2O3 layer in the Metal/Ferroelectric/Insulator/Silicon (MFeIS) structure, the memory window and breakdown voltage was improved to 7.21 and 35 V, respectively. Such structures show high endurance with no significant reduction polarization charge for upto 2.2 × 109 iteration cycles.

Recent Advances on Neuromorphic Systems Using Phase-Change Materials

NASA Astrophysics Data System (ADS)

Wang, Lei; Lu, Shu-Ren; Wen, Jing

2017-05-01

Realization of brain-like computer has always been human's ultimate dream. Today, the possibility of having this dream come true has been significantly boosted due to the advent of several emerging non-volatile memory devices. Within these innovative technologies, phase-change memory device has been commonly regarded as the most promising candidate to imitate the biological brain, owing to its excellent scalability, fast switching speed, and low energy consumption. In this context, a detailed review concerning the physical principles of the neuromorphic circuit using phase-change materials as well as a comprehensive introduction of the currently available phase-change neuromorphic prototypes becomes imperative for scientists to continuously progress the technology of artificial neural networks. In this paper, we first present the biological mechanism of human brain, followed by a brief discussion about physical properties of phase-change materials that recently receive a widespread application on non-volatile memory field. We then survey recent research on different types of neuromorphic circuits using phase-change materials in terms of their respective geometrical architecture and physical schemes to reproduce the biological events of human brain, in particular for spike-time-dependent plasticity. The relevant virtues and limitations of these devices are also evaluated. Finally, the future prospect of the neuromorphic circuit based on phase-change technologies is envisioned.

Giant Electroresistive Ferroelectric Diode on 2DEG

PubMed Central

Kim, Shin-Ik; Jin Gwon, Hyo; Kim, Dai-Hong; Keun Kim, Seong; Choi, Ji-Won; Yoon, Seok-Jin; Jung Chang, Hye; Kang, Chong-Yun; Kwon, Beomjin; Bark, Chung-Wung; Hong, Seong-Hyeon; Kim, Jin-Sang; Baek, Seung-Hyub

2015-01-01

Manipulation of electrons in a solid through transmitting, storing, and switching is the fundamental basis for the microelectronic devices. Recently, the electroresistance effect in the ferroelectric capacitors has provided a novel way to modulate the electron transport by polarization reversal. Here, we demonstrate a giant electroresistive ferroelectric diode integrating a ferroelectric capacitor into two-dimensional electron gas (2DEG) at oxide interface. As a model system, we fabricate an epitaxial Au/Pb(Zr0.2Ti0.8)O3/LaAlO3/SrTiO3 heterostructure, where 2DEG is formed at LaAlO3/SrTiO3 interface. This device functions as a two-terminal, non-volatile memory of 1 diode-1 resistor with a large I+/I− ratio (>108 at ±6 V) and Ion/Ioff ratio (>107). This is attributed to not only Schottky barrier modulation at metal/ferroelectric interface by polarization reversal but also the field-effect metal-insulator transition of 2DEG. Moreover, using this heterostructure, we can demonstrate a memristive behavior for an artificial synapse memory, where the resistance can be continuously tuned by partial polarization switching, and the electrons are only unidirectionally transmitted. Beyond non-volatile memory and logic devices, our results will provide new opportunities to emerging electronic devices such as multifunctional nanoelectronics and neuromorphic electronics. PMID:26014446

Recent Advances on Neuromorphic Systems Using Phase-Change Materials.

PubMed

Wang, Lei; Lu, Shu-Ren; Wen, Jing

2017-12-01

Realization of brain-like computer has always been human's ultimate dream. Today, the possibility of having this dream come true has been significantly boosted due to the advent of several emerging non-volatile memory devices. Within these innovative technologies, phase-change memory device has been commonly regarded as the most promising candidate to imitate the biological brain, owing to its excellent scalability, fast switching speed, and low energy consumption. In this context, a detailed review concerning the physical principles of the neuromorphic circuit using phase-change materials as well as a comprehensive introduction of the currently available phase-change neuromorphic prototypes becomes imperative for scientists to continuously progress the technology of artificial neural networks. In this paper, we first present the biological mechanism of human brain, followed by a brief discussion about physical properties of phase-change materials that recently receive a widespread application on non-volatile memory field. We then survey recent research on different types of neuromorphic circuits using phase-change materials in terms of their respective geometrical architecture and physical schemes to reproduce the biological events of human brain, in particular for spike-time-dependent plasticity. The relevant virtues and limitations of these devices are also evaluated. Finally, the future prospect of the neuromorphic circuit based on phase-change technologies is envisioned.

Feasibilty of a Multi-bit Cell Perpendicular Magnetic Tunnel Junction Device

NASA Astrophysics Data System (ADS)

Kim, Chang Soo

The ultimate objective of this research project was to explore the feasibility of making a multi-bit cell perpendicular magnetic tunnel junction (PMTJ) device to increase the storage density of spin-transfer-torque random access memory (STT-RAM). As a first step toward demonstrating a multi-bit cell device, this dissertation contributed a systematic and detailed study of developing a single cell PMTJ device using L10 FePt films. In the beginning of this research, 13 up-and-coming non-volatile memory (NVM) technologies were investigated and evaluated to see whether one of them might outperform NAND flash memories and even HDDs on a cost-per-TB basis in 2020. This evaluation showed that STT-RAM appears to potentially offer superior power efficiency, among other advantages. It is predicted that STTRAM's density could make it a promising candidate for replacing NAND flash memories and possibly HDDs if STTRAM could be improved to store multiple bits per cell. Ta/Mg0 under-layers were used first in order to develop (001) L1 0 ordering of FePt at a low temperature of below 400 °C. It was found that the tradeoff between surface roughness and (001) L10 ordering of FePt makes it difficult to achieve low surface roughness and good perpendicular magnetic properties simultaneously when Ta/Mg0 under-layers are used. It was, therefore, decided to investigate MgO/CrRu under-layers to simultaneously achieve smooth films with good ordering below 400°C. A well ordered 4 nm L10 FePt film with RMS surface roughness close to 0.4 nm, perpendicular coercivity of about 5 kOe, and perpendicular squareness near 1 was obtained at a deposition temperature of 390 °C on a thermally oxidized Si substrate when MgO/CrRu under-layers are used. A PMTJ device was developed by depositing a thin MgO tunnel barrier layer and a top L10 FePt film and then being postannealed at 450 °C for 30 minutes. It was found that the sputtering power needs to be minimized during the thin MgO tunnel barrier deposition because the high sputtering power can degrade perpendicular magnetic anisotropy of the bottom L1 0 FePt film and also increase RMS film surface roughness of the MgO tunnel barrier layer. From a lithographically unpatterned PMTJ sample, MR ratio and RA were measured at room temperature by the CIPT method and found to be 138% and 6.4 kOmicrom2, respectively. A completed PMTJ test pattern with a junction size of 80x40 microm2 was fabricated and showed a measured MR ratio and RA product of 108% and 4~6 kOmicrom 2, respectively. These values agree relatively well with the corresponding values of 138% and 6.4 kOmicrom2 obtained from the unpatterned PMTJ sample measured by a current-in-plane tunneling (CIPT) method.

CD uniformity control for thick resist process

NASA Astrophysics Data System (ADS)

Huang, Chi-hao; Liu, Yu-Lin; Wang, Weihung; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

2017-03-01

In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked flash cell array has been proposed. In constructing 3D NAND flash memories, the higher bit number per area is achieved by increasing the number of stacked layers. Thus the so-called "staircase" patterning to form electrical connection between memory cells and word lines has become one of the primarily critical processes in 3D memory manufacture. To provide controllable critical dimension (CD) with good uniformity involving thick photo-resist has also been of particular concern for staircase patterning. The CD uniformity control has been widely investigated with relatively thinner resist associated with resolution limit dimension but thick resist coupling with wider dimension. This study explores CD uniformity control associated with thick photo-resist processing. Several critical parameters including exposure focus, exposure dose, baking condition, pattern size and development recipe, were found to strongly correlate with the thick photo-resist profile accordingly affecting the CD uniformity control. To minimize the within-wafer CD variation, the slightly tapered resist profile is proposed through well tailoring the exposure focus and dose together with optimal development recipe. Great improvements on DCD (ADI CD) and ECD (AEI CD) uniformity as well as line edge roughness were achieved through the optimization of photo resist profile.

Patterning optimization for 55nm design rule DRAM/flash memory using production-ready customized illuminations

NASA Astrophysics Data System (ADS)

Chen, Ting; Van Den Broeke, Doug; Hsu, Stephen; Hsu, Michael; Park, Sangbong; Berger, Gabriel; Coskun, Tamer; de Vocht, Joep; Chen, Fung; Socha, Robert; Park, JungChul; Gronlund, Keith

2005-11-01

Illumination optimization, often combined with optical proximity corrections (OPC) to the mask, is becoming one of the critical components for a production-worthy lithography process for 55nm-node DRAM/Flash memory devices and beyond. At low-k1, e.g. k1<0.31, both resolution and imaging contrast can be severely limited by the current imaging tools while using the standard illumination sources. Illumination optimization is a process where the source shape is varied, in both profile and intensity distribution, to achieve enhancement in the final image contrast as compared to using the non-optimized sources. The optimization can be done efficiently for repetitive patterns such as DRAM/Flash memory cores. However, illumination optimization often produces source shapes that are "free-form" like and they can be too complex to be directly applicable for production and lack the necessary radial and annular symmetries desirable for the diffractive optical element (DOE) based illumination systems in today's leading lithography tools. As a result, post-optimization rendering and verification of the optimized source shape are often necessary to meet the production-ready or manufacturability requirements and ensure optimal performance gains. In this work, we describe our approach to the illumination optimization for k1<0.31 DRAM/Flash memory patterns, using an ASML XT:1400i at NA 0.93, where the all necessary manufacturability requirements are fully accounted for during the optimization. The imaging contrast in the resist is optimized in a reduced solution space constrained by the manufacturability requirements, which include minimum distance between poles, minimum opening pole angles, minimum ring width and minimum source filling factor in the sigma space. For additional performance gains, the intensity within the optimized source can vary in a gray-tone fashion (eight shades used in this work). Although this new optimization approach can sometimes produce closely spaced solutions as gauged by the NILS based metrics, we show that the optimal and production-ready source shape solution can be easily determined by comparing the best solutions to the "free-form" solution and more importantly, by their respective imaging fidelity and process latitude ranking. Imaging fidelity and process latitude simulations are performed to analyze the impact and sensitivity of the manufacturability requirements on pattern specific illumination optimizations using ASML XT:1400i and other latest imaging systems. Mask model based OPC (MOPC) is applied and optimized sequentially to ensure that the CD uniformity requirements are met.

Environmentally friendly and biobased lubricants

USDA-ARS?s Scientific Manuscript database

Biobased and environmentally friendly lubricants are finding applications in many areas ranging from hydraulic fluids to grease. They offer excellent biodegradability and very low ecotoxicity; high viscosity index; improved tribological properties; lower volatility and flash points relative to petro...

Printing Electronic Components from Copper-Infused Ink and Thermoplastic Mediums

NASA Astrophysics Data System (ADS)

Flowers, Patrick F.

The demand for printable electronics has sharply increased in recent years and is projected to continue to rise. Unfortunately, electronic materials which are suitable for desired applications while being compatible with available printing techniques are still often lacking. This thesis addresses two such challenging areas. In the realm of two-dimensional ink-based printing of electronics, a major barrier to the realization of printable computers that can run programs is the lack of a solution-coatable non-volatile memory with performance metrics comparable to silicon-based devices. To address this deficiency, I developed a nonvolatile memory based on Cu-SiO2 core-shell nanowires that can be printed from solution and exhibits on-off ratios of 106, switching speeds of 50 ns, a low operating voltage of 2 V, and operates for at least 104 cycles without failure. Each of these metrics is similar to or better than Flash memory (the write speed is 20 times faster than Flash). Memory architectures based on the individual memory cells demonstrated here could enable the printing of the more complex, embedded computing devices that are expected to make up an internet of things. Recently, the exploration of three-dimensional printing techniques to fabricate electronic materials began. A suitable general-purpose conductive thermoplastic filament was not available, however. In this work I examine the current state of conductive thermoplastic filaments, including a newly-released highly conductive filament that my lab has produced which we call Electrifi. I focus on the use of dual-material fused filament fabrication (FFF) to 3D print electronic components (conductive traces, resistors, capacitors, inductors) and circuits (a fully-printed high-pass filter). The resistivity of traces printed from conductive thermoplastic filaments made with carbon-black, graphene, and copper as conductive fillers was found to be 12, 0.78, and 0.014 ohm cm, respectively, enabling the creation of resistors with resistances spanning 3 orders of magnitude. The carbon black and graphene filaments were brittle and fractured easily, but the copper-based filament could be bent at least 500 times with little change in its resistance. Impedance measurements made on the thermoplastic filaments demonstrate that the copper-based filament had an impedance similar to a conductive PCB trace at 1 MHz. Dual material 3D printing was used to fabricate a variety of inductors and capacitors with properties that could be predictably tuned by modifying either the geometry of the components, or the materials used to fabricate the components. These resistors, capacitors, and inductors were combined to create a fully 3D printed high-pass filter with properties comparable to its conventional counterparts. The relatively low impedance of the copper-based filament enable its use to 3D print a receiver coil for wireless power transfer. We also demonstrate the ability to embed and connect surface mounted components in 3D printed objects with a low-cost ($1,000 in parts), open source dual-material 3D printer. This work thus demonstrates the potential for FFF 3D printing to create complex, three-dimensional circuits composed of either embedded or fully-printed electronic components.

Program scheme using common source lines in channel stacked NAND flash memory with layer selection by multilevel operation

NASA Astrophysics Data System (ADS)

Kim, Do-Bin; Kwon, Dae Woong; Kim, Seunghyun; Lee, Sang-Ho; Park, Byung-Gook

2018-02-01

To obtain high channel boosting potential and reduce a program disturbance in channel stacked NAND flash memory with layer selection by multilevel (LSM) operation, a new program scheme using boosted common source line (CSL) is proposed. The proposed scheme can be achieved by applying proper bias to each layer through its own CSL. Technology computer-aided design (TCAD) simulations are performed to verify the validity of the new method in LSM. Through TCAD simulation, it is revealed that the program disturbance characteristics is effectively improved by the proposed scheme.

The future of memory

NASA Astrophysics Data System (ADS)

Marinella, M.

In the not too distant future, the traditional memory and storage hierarchy of may be replaced by a single Storage Class Memory (SCM) device integrated on or near the logic processor. Traditional magnetic hard drives, NAND flash, DRAM, and higher level caches (L2 and up) will be replaced with a single high performance memory device. The Storage Class Memory paradigm will require high speed (< 100 ns read/write), excellent endurance (> 1012), nonvolatility (retention > 10 years), and low switching energies (< 10 pJ per switch). The International Technology Roadmap for Semiconductors (ITRS) has recently evaluated several potential candidates SCM technologies, including Resistive (or Redox) RAM, Spin Torque Transfer RAM (STT-MRAM), and phase change memory (PCM). All of these devices show potential well beyond that of current flash technologies and research efforts are underway to improve the endurance, write speeds, and scalabilities to be on-par with DRAM. This progress has interesting implications for space electronics: each of these emerging device technologies show excellent resistance to the types of radiation typically found in space applications. Commercially developed, high density storage class memory-based systems may include a memory that is physically radiation hard, and suitable for space applications without major shielding efforts. This paper reviews the Storage Class Memory concept, emerging memory devices, and possible applicability to radiation hardened electronics for space.

Defect reduction for semiconductor memory applications using jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Ye, Zhengmao; Luo, Kang; Irving, J. W.; Lu, Xiaoming; Zhang, Wei; Fletcher, Brian; Liu, Weijun; Xu, Frank; LaBrake, Dwayne; Resnick, Douglas; Sreenivasan, S. V.

2013-03-01

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography (J-FIL) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned resist on the substrate. Acceptance of imprint lithography for manufacturing will require demonstration that it can attain defect levels commensurate with the defect specifications of high end memory devices. Typical defectivity targets are on the order of 0.10/cm2. In previous studies, we have focused on defects such as random non-fill defects occurring during the resist filling process and repeater defects caused by interactions with particles on the substrate. In this work, we attempted to identify the critical imprint defect types using a mask with NAND Flash-like patterns at dimensions as small as 26nm. The two key defect types identified were line break defects induced by small particulates and airborne contaminants which result in local adhesion failure. After identification, the root cause of the defect was determined, and corrective measures were taken to either eliminate or reduce the defect source. As a result, we have been able to reduce defectivity levels by more than three orders of magnitude in only 12 months and are now achieving defectivity adders as small as 2 adders per lot of wafers.

Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

NASA Astrophysics Data System (ADS)

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Bhansali, Unnat. S.; Alshareef, H. N.

2012-06-01

High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin film transistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectric transistors, which is very promising for low-power non-volatile memory applications.

Integrated, nonvolatile, high-speed analog random access memory

NASA Technical Reports Server (NTRS)

Katti, Romney R. (Inventor); Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor)

1994-01-01

This invention provides an integrated, non-volatile, high-speed random access memory. A magnetically switchable ferromagnetic or ferrimagnetic layer is sandwiched between an electrical conductor which provides the ability to magnetize the magnetically switchable layer and a magneto resistive or Hall effect material which allows sensing the magnetic field which emanates from the magnetization of the magnetically switchable layer. By using this integrated three-layer form, the writing process, which is controlled by the conductor, is separated from the storage medium in the magnetic layer and from the readback process which is controlled by the magnetoresistive layer. A circuit for implementing the memory in CMOS or the like is disclosed.

Evaluation of Magnetoresistive RAM for Space Applications

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2014-01-01

Magnetoresistive random-access memory (MRAM) is a non-volatile memory that exploits electronic spin, rather than charge, to store data. Instead of moving charge on and off a floating gate to alter the threshold voltage of a CMOS transistor (creating different bit states), MRAM uses magnetic fields to flip the polarization of a ferromagnetic material thus switching its resistance and bit state. These polarized states are immune to radiation-induced upset, thus making MRAM very attractive for space application. These magnetic memory elements also have infinite data retention and erase/program endurance. Presented here are results of reliability testing of two space-qualified MRAM products from Aeroflex and Honeywell.

Ferroelectric tunneling element and memory applications which utilize the tunneling element

DOEpatents

Kalinin, Sergei V [Knoxville, TN; Christen, Hans M [Knoxville, TN; Baddorf, Arthur P [Knoxville, TN; Meunier, Vincent [Knoxville, TN; Lee, Ho Nyung [Oak Ridge, TN

2010-07-20

A tunneling element includes a thin film layer of ferroelectric material and a pair of dissimilar electrically-conductive layers disposed on opposite sides of the ferroelectric layer. Because of the dissimilarity in composition or construction between the electrically-conductive layers, the electron transport behavior of the electrically-conductive layers is polarization dependent when the tunneling element is below the Curie temperature of the layer of ferroelectric material. The element can be used as a basis of compact 1R type non-volatile random access memory (RAM). The advantages include extremely simple architecture, ultimate scalability and fast access times generic for all ferroelectric memories.

A Low Cost Microcomputer Laboratory for Investigating Computer Architecture.

ERIC Educational Resources Information Center

Mitchell, Eugene E., Ed.

1980-01-01

Described is a microcomputer laboratory at the United States Military Academy at West Point, New York, which provides easy access to non-volatile memory and a single input/output file system for 16 microcomputer laboratory positions. A microcomputer network that has a centralized data base is implemented using the concepts of computer network…

Architectural Techniques For Managing Non-volatile Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh

As chip power dissipation becomes a critical challenge in scaling processor performance, computer architects are forced to fundamentally rethink the design of modern processors and hence, the chip-design industry is now at a major inflection point in its hardware roadmap. The high leakage power and low density of SRAM poses serious obstacles in its use for designing large on-chip caches and for this reason, researchers are exploring non-volatile memory (NVM) devices, such as spin torque transfer RAM, phase change RAM and resistive RAM. However, since NVMs are not strictly superior to SRAM, effective architectural techniques are required for making themmore » a universal memory solution. This book discusses techniques for designing processor caches using NVM devices. It presents algorithms and architectures for improving their energy efficiency, performance and lifetime. It also provides both qualitative and quantitative evaluation to help the reader gain insights and motivate them to explore further. This book will be highly useful for beginners as well as veterans in computer architecture, chip designers, product managers and technical marketing professionals.« less

Brownmillerite thin films as fast ion conductors for ultimate-performance resistance switching memory.

PubMed

Acharya, Susant Kumar; Jo, Janghyun; Raveendra, Nallagatlla Venkata; Dash, Umasankar; Kim, Miyoung; Baik, Hionsuck; Lee, Sangik; Park, Bae Ho; Lee, Jae Sung; Chae, Seung Chul; Hwang, Cheol Seong; Jung, Chang Uk

2017-07-27

An oxide-based resistance memory is a leading candidate to replace Si-based flash memory as it meets the emerging specifications for future memory devices. The non-uniformity in the key switching parameters and low endurance in conventional resistance memory devices are preventing its practical application. Here, a novel strategy to overcome the aforementioned challenges has been unveiled by tuning the growth direction of epitaxial brownmillerite SrFeO 2.5 thin films along the SrTiO 3 [111] direction so that the oxygen vacancy channels can connect both the top and bottom electrodes rather directly. The controlled oxygen vacancy channels help reduce the randomness of the conducting filament (CF). The resulting device displayed high endurance over 10 6 cycles, and a short switching time of ∼10 ns. In addition, the device showed very high uniformity in the key switching parameters for device-to-device and within a device. This work demonstrates a feasible example for improving the nanoscale device performance by controlling the atomic structure of a functional oxide layer.

Low-temperature post-deposition annealing investigation for 3D charge trap flash memory by Kelvin probe force microscopy

NASA Astrophysics Data System (ADS)

Huo, Zongliang; Jin, Lei; Han, Yulong; Li, Xinkai; Ye, Tianchun; Liu, Ming

2015-01-01

The influence of post-deposition annealing (PDA) temperature condition on charge distribution behavior of HfO2 thin films was systematically investigated by various-temperature Kelvin probe force microscopy technology. Contact potential difference profiles demonstrated that charge storage capability shrinks with decreasing annealing temperature from 1,000 to 500 °C and lower. Compared to 1,000 °C PDA, it was found that 500 °C PDA causes deeper effective trap energy level, suppresses lateral charge spreading, and improves the retention characteristics. It is concluded that low-temperature PDA can be adopted in 3D HfO2-based charge trap flash memory to improve the thermal treatment compatibility of the bottom peripheral logic and upper memory arrays.

Numerical model of a single nanocrystal devoted to the study of disordered nanocrystal floating gates of new flash memories

NASA Astrophysics Data System (ADS)

Leroy, Yann; Armeanu, Dumitru; Cordan, Anne-Sophie

2011-05-01

The improvement of our model concerning a single nanocrystal that belongs to a nanocrystal floating gate of a flash memory is presented. In order to extend the gate voltage range applicability of the model, the 3D continuum of states of either metallic or semiconducting electrodes is discretized into 2D subbands. Such an approach gives precise information about the mechanisms behind the charging or release processes of the nanocrystal. Then, the self-energy and screening effects of an electron within the nanocrystal are evaluated and introduced in the model. This enables a better determination of the operating point of the nanocrystal memory. The impact of those improvements on the charging or release time of the nanocrystal is discussed.

Skewness, long-time memory, and non-stationarity: Application to leverage effect in financial time series

NASA Astrophysics Data System (ADS)

Roman, H. E.; Porto, M.; Dose, C.

2008-10-01

We analyze daily log-returns data for a set of 1200 stocks, taken from US stock markets, over a period of 2481 trading days (January 1996-November 2005). We estimate the degree of non-stationarity in daily market volatility employing a polynomial fit, used as a detrending function. We find that the autocorrelation function of absolute detrended log-returns departs strongly from the corresponding original data autocorrelation function, while the observed leverage effect depends only weakly on trends. Such effect is shown to occur when both skewness and long-time memory are simultaneously present. A fractional derivative random walk model is discussed yielding a quantitative agreement with the empirical results.

Coexistence of diode-like volatile and multilevel nonvolatile resistive switching in a ZrO2/TiO2 stack structure.

PubMed

Li, Yingtao; Yuan, Peng; Fu, Liping; Li, Rongrong; Gao, Xiaoping; Tao, Chunlan

2015-10-02

Diode-like volatile resistive switching as well as nonvolatile resistive switching behaviors in a Cu/ZrO₂/TiO₂/Ti stack are investigated. Depending on the current compliance during the electroforming process, either volatile resistive switching or nonvolatile resistive switching is observed. With a lower current compliance (<10 μA), the Cu/ZrO₂/TiO₂/Ti device exhibits diode-like volatile resistive switching with a rectifying ratio over 10(6). The permanent transition from volatile to nonvolatile resistive switching can be obtained by applying a higher current compliance of 100 μA. Furthermore, by using different reset voltages, the Cu/ZrO₂/TiO₂/Ti device exhibits multilevel memory characteristics with high uniformity. The coexistence of nonvolatile multilevel memory and diode-like volatile resistive switching behaviors in the same Cu/ZrO₂/TiO₂/Ti device opens areas of applications in high-density storage, logic circuits, neural networks, and passive crossbar memory selectors.

Portable Electromyograph

NASA Technical Reports Server (NTRS)

De Luca, Gianluca; De Luca, Carlo J.; Bergman, Per

2004-01-01

A portable electronic apparatus records electromyographic (EMG) signals in as many as 16 channels at a sampling rate of 1,024 Hz in each channel. The apparatus (see figure) includes 16 differential EMG electrodes (each electrode corresponding to one channel) with cables and attachment hardware, reference electrodes, an input/output-and-power-adapter unit, a 16-bit analog-to-digital converter, and a hand-held computer that contains a removable 256-MB flash memory card. When all 16 EMG electrodes are in use, full-bandwidth data can be recorded in each channel for as long as 8 hours. The apparatus is powered by a battery and is small enough that it can be carried in a waist pouch. The computer is equipped with a small screen that can be used to display the incoming signals on each channel. Amplitude and time adjustments of this display can be made easily by use of touch buttons on the screen. The user can also set up a data-acquisition schedule to conform to experimental protocols or to manage battery energy and memory efficiently. Once the EMG data have been recorded, the flash memory card is removed from the EMG apparatus and placed in a flash-memory- card-reading external drive unit connected to a personal computer (PC). The PC can then read the data recorded in the 16 channels. Preferably, before further analysis, the data should be stored in the hard drive of the PC. The data files are opened and viewed on the PC by use of special- purpose software. The software for operation of the apparatus resides in a random-access memory (RAM), with backup power supplied by a small internal lithium cell. A backup copy of this software resides on the flash memory card. In the event of loss of both main and backup battery power and consequent loss of this software, the backup copy can be used to restore the RAM copy after power has been restored. Accessories for this device are also available. These include goniometers, accelerometers, foot switches, and force gauges.

Checkpoint-Restart in User Space

DOE Office of Scientific and Technical Information (OSTI.GOV)

CRUISE implements a user-space file system that stores data in main memory and transparently spills over to other storage, like local flash memory or the parallel file system, as needed. CRUISE also exposes file contents fo remote direct memory access, allowing external tools to copy files to the parallel file system in the background with reduced CPU interruption.

Multiscaling and clustering of volatility

NASA Astrophysics Data System (ADS)

Pasquini, Michele; Serva, Maurizio

1999-07-01

The dynamics of prices in stock markets has been studied intensively both experimentally (data analysis) and theoretically (models). Nevertheless, while the distribution of returns of the most important indices is known to be a truncated Lévy, the behaviour of volatility correlations is still poorly understood. What is well known is that absolute returns have memory on a long time range, this phenomenon is known in financial literature as clustering of volatility. In this paper we show that volatility correlations are power laws with a non-unique scaling exponent. This kind of multiscale phenomenology is known to be relevant in fully developed turbulence and in disordered systems and it is pointed out here for the first time for a financial series. In our study we consider the New York Stock Exchange (NYSE) daily index, from January 1966 to June 1998, for a total of 8180 working days.

Compact Holographic Data Storage

NASA Technical Reports Server (NTRS)

Chao, T. H.; Reyes, G. F.; Zhou, H.

2001-01-01

NASA's future missions would require massive high-speed onboard data storage capability to Space Science missions. For Space Science, such as the Europa Lander mission, the onboard data storage requirements would be focused on maximizing the spacecraft's ability to survive fault conditions (i.e., no loss in stored science data when spacecraft enters the 'safe mode') and autonomously recover from them during NASA's long-life and deep space missions. This would require the development of non-volatile memory. In order to survive in the stringent environment during space exploration missions, onboard memory requirements would also include: (1) survive a high radiation environment (1 Mrad), (2) operate effectively and efficiently for a very long time (10 years), and (3) sustain at least a billion write cycles. Therefore, memory technologies requirements of NASA's Earth Science and Space Science missions are large capacity, non-volatility, high-transfer rate, high radiation resistance, high storage density, and high power efficiency. JPL, under current sponsorship from NASA Space Science and Earth Science Programs, is developing a high-density, nonvolatile and rad-hard Compact Holographic Data Storage (CHDS) system to enable large-capacity, high-speed, low power consumption, and read/write of data in a space environment. The entire read/write operation will be controlled with electrooptic mechanism without any moving parts. This CHDS will consist of laser diodes, photorefractive crystal, spatial light modulator, photodetector array, and I/O electronic interface. In operation, pages of information would be recorded and retrieved with random access and high-speed. The nonvolatile, rad-hard characteristics of the holographic memory will provide a revolutionary memory technology meeting the high radiation challenge facing the Europa Lander mission. Additional information is contained in the original extended abstract.

Evaluating automatic attentional capture by self-relevant information.

PubMed

Ocampo, Brenda; Kahan, Todd A

2016-01-01

Our everyday decisions and memories are inadvertently influenced by self-relevant information. For example, we are faster and more accurate at making perceptual judgments about stimuli associated with ourselves, such as our own face or name, as compared with familiar non-self-relevant stimuli. Humphreys and Sui propose a "self-attention network" to account for these effects, wherein self-relevant stimuli automatically capture our attention and subsequently enhance the perceptual processing of self-relevant information. We propose that the masked priming paradigm and continuous flash suppression represent two ways to experimentally examine these controversial claims.

Impact of gate work-function on memory characteristics in Al2O3/HfOx/Al2O3/graphene charge-trap memory devices

NASA Astrophysics Data System (ADS)

Lee, Sejoon; Song, Emil B.; Kim, Sungmin; Seo, David H.; Seo, Sunae; Won Kang, Tae; Wang, Kang L.

2012-01-01

Graphene-based non-volatile memory devices composed of a single-layer graphene channel and an Al2O3/HfOx/Al2O3 charge-storage layer exhibit memory functionality. The impact of the gate material's work-function (Φ) on the memory characteristics is investigated using different types of metals [Ti (ΦTi = 4.3 eV) and Ni (ΦNi = 5.2 eV)]. The ambipolar carrier conduction of graphene results in an enlargement of memory window (ΔVM), which is ˜4.5 V for the Ti-gate device and ˜9.1 V for the Ni-gate device. The increase in ΔVM is attributed to the change in the flat-band condition and the suppression of electron back-injection within the gate stack.

Air-stable memory array of bistable rectifying diodes based on ferroelectric-semiconductor polymer blends

NASA Astrophysics Data System (ADS)

Kumar, Manasvi; Sharifi Dehsari, Hamed; Anwar, Saleem; Asadi, Kamal

2018-03-01

Organic bistable diodes based on phase-separated blends of ferroelectric and semiconducting polymers have emerged as promising candidates for non-volatile information storage for low-cost solution processable electronics. One of the bottlenecks impeding upscaling is stability and reliable operation of the array in air. Here, we present a memory array fabricated with an air-stable amine-based semiconducting polymer. Memory diode fabrication and full electrical characterizations were carried out in atmospheric conditions (23 °C and 45% relative humidity). The memory diodes showed on/off ratios greater than 100 and further exhibited robust and stable performance upon continuous write-read-erase-read cycles. Moreover, we demonstrate a 4-bit memory array that is free from cross-talk with a shelf-life of several months. Demonstration of the stability and reliable air operation further strengthens the feasibility of the resistance switching in ferroelectric memory diodes for low-cost applications.

Heavy Ion Irradiation Fluence Dependence for Single-Event Upsets of NAND Flash Memory

NASA Technical Reports Server (NTRS)

Chen, Dakai; Wilcox, Edward; Ladbury, Raymond; Kim, Hak; Phan, Anthony; Seidleck, Christina; LaBel, Kenneth

2016-01-01

We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found the single-event upset (SEU) cross section varied inversely with fluence. The SEU cross section decreased with increasing fluence. We attribute the effect to the variable upset sensitivities of the memory cells. The current test standards and procedures assume that SEU follow a Poisson process and do not take into account the variability in the error rate with fluence. Therefore, heavy ion irradiation of devices with variable upset sensitivity distribution using typical fluence levels may underestimate the cross section and on-orbit event rate.

Endurance degradation and lifetime model of p-channel floating gate flash memory device with 2T structure

NASA Astrophysics Data System (ADS)

Wei, Jiaxing; Liu, Siyang; Liu, Xiaoqiang; Sun, Weifeng; Liu, Yuwei; Liu, Xiaohong; Hou, Bo

2017-08-01

The endurance degradation mechanisms of p-channel floating gate flash memory device with two-transistor (2T) structure are investigated in detail in this work. With the help of charge pumping (CP) measurements and Sentaurus TCAD simulations, the damages in the drain overlap region along the tunnel oxide interface caused by band-to-band (BTB) tunneling programming and the damages in the channel region resulted from Fowler-Nordheim (FN) tunneling erasure are verified respectively. Furthermore, the lifetime model of endurance characteristic is extracted, which can extrapolate the endurance degradation tendency and predict the lifetime of the device.

Tunable bandgap energy of fluorinated nanocrystals for flash memory applications produced by low-damage plasma treatment.

PubMed

Huang, Chi-Hsien; Lin, Chih-Ting; Wang, Jer-Chyi; Chou, Chien; Ye, Yu-Ren; Cheng, Bing-Ming; Lai, Chao-Sung

2012-11-30

A plasma system with a complementary filter to shield samples from damage during tetrafluoromethane (CF(4)) plasma treatment was proposed in order to incorporate fluorine atoms into gadolinium oxide nanocrystals (Gd(2)O(3)-NCs) for flash memory applications. X-ray photoelectron spectroscopy confirmed that fluorine atoms were successfully introduced into the Gd(2)O(3)-NCs despite the use of a filter in the plasma-enhanced chemical vapour deposition system to shield against several potentially damaging species. The number of incorporated fluorine atoms can be controlled by varying the treatment time. The optimized memory window of the resulting flash memory devices was twice that of devices treated by a filterless system because more fluorine atoms were incorporated into the Gd(2)O(3)-NCs film with very little damage. This enlarged the bandgap energy from 5.48 to 6.83 eV, as observed by ultraviolet absorption measurements. This bandgap expansion can provide a large built-in electric field that allows more charges to be stored in the Gd(2)O(3)-NCs. The maximum improvement in the retention characteristic was >60%. Because plasma damage during treatment is minimal, maximum fluorination can be achieved. The concept of simply adding a filter to a plasma system to prevent plasma damage exhibits great promise for functionalization or modification of nanomaterials for advanced nanoelectronics while introducing minimal defects.

Malware Memory Analysis of the IVYL Linux Rootkit: Investigating a Publicly Available Linux Rootkit Using the Volatility Memory Analysis Framework

DTIC Science & Technology

2015-04-01

report is to examine how a computer forensic investigator/incident handler, without specialised computer memory or software reverse engineering skills ...The skills amassed by incident handlers and investigators alike while using Volatility to examine Windows memory images will be of some help...bin/pulseaudio --start --log-target=syslog 1362 1000 1000 nautilus 1366 1000 1000 /usr/lib/pulseaudio/pulse/gconf- helper 1370 1000 1000 nm-applet

Pyrolysis with cyclone burner

DOEpatents

Green, Norman W.; Duraiswamy, Kandaswamy; Lumpkin, Robert E.

1978-07-25

In a continuous process for recovery of values contained in a solid carbonaceous material, the carbonaceous material is comminuted and then subjected to flash pyrolysis in the presence of a particulate heat source over an overflow weir to form a pyrolysis product stream containing a carbon containing solid residue and volatilized hydrocarbons. After the carbon containing solid residue is separated from the pyrolysis product stream, values are obtained by condensing volatilized hydrocarbons. The particulate source of heat is formed by oxidizing carbon in the solid residue and separating out the fines.

Pyrolysis with staged recovery

DOEpatents

Green, Norman W.; Duraiswamy, Kandaswamy; Lumpkin, Robert E.; Winter, Bruce L.

1979-03-20

In a continuous process for recovery of values contained in a solid carbonaceous material, the carbonaceous material is comminuted and then subjected to flash pyrolysis in the presence of a particulate heat source fed over an overflow weir to form a pyrolysis product stream containing a carbon containing solid residue and volatilized hydrocarbons. After the carbon containing solid residue is separated from the pyrolysis product stream, values are obtained by condensing volatilized hydrocarbons. The particulate source of heat is formed by oxidizing carbon in the solid residue.

An overview of Experimental Condensed Matter Physics in Argentina by 2014, and Oxides for Non Volatile Memory Devices: The MeMOSat Project

NASA Astrophysics Data System (ADS)

Levy, Pablo

2015-03-01

In the first part of my talk, I will describe the status of the experimental research in Condensed Matter Physics in Argentina, biased towards developments related to micro and nanotechnology. In the second part, I will describe the MeMOSat Project, a consortium aimed at producing non-volatile memory devices to work in aggressive environments, like those found in the aerospace and nuclear industries. Our devices rely on the Resistive Switching mechanism, which produces a permanent but reversible change in the electrical resistance across a metal-insulator-metal structure by means of a pulsed protocol of electrical stimuli. Our project is devoted to the study of Memory Mechanisms in Oxides (MeMO) in order to establish a technological platform that tests the Resistive RAM (ReRAM) technology for aerospace applications. A review of MeMOSat's activities is presented, covering the initial Proof of Concept in ceramic millimeter sized samples; the study of different oxide-metal couples including (LaPr)2/3Ca1/3MnO, La2/3Ca1/3MnO3, YBa2Cu3O7, TiO2, HfO2, MgO and CuO; and recent miniaturized arrays of micrometer sized devices controlled by in-house designed electronics, which were launched with the BugSat01 satellite in June2014 by the argentinian company Satellogic.

Nonvolatile floating gate organic memory device based on pentacene/CdSe quantum dot heterojuction

NASA Astrophysics Data System (ADS)

Shin, Ik-Soo; Kim, Jung-Min; Jeun, Jun-Ho; Yoo, Seok-Hyun; Ge, Ziyi; Hong, Jong-In; Ho Bang, Jin; Kim, Yong-Sang

2012-04-01

An organic floating-gate memory device using CdSe quantum dots (QDs) as a charge-trapping element was fabricated. CdSe QDs were localized beneath a pentacene without any tunneling insulator, and the QD layer played a role as hole-trapping sites. The band bending formed at the junction between pentacene and QD layers inhibited back-injection of holes trapped in CdSe into pentacene, which appeared as a hysteretic capacitance-voltage response during the operation of the device. Nearly, 60% of trapped charge was sustained even after 104 s in programmed state, and this long retention time can be potentially useful in practical applications of non-volatile memory.

Synaptic plasticity functions in an organic electrochemical transistor

NASA Astrophysics Data System (ADS)

Gkoupidenis, Paschalis; Schaefer, Nathan; Strakosas, Xenofon; Fairfield, Jessamyn A.; Malliaras, George G.

2015-12-01

Synaptic plasticity functions play a crucial role in the transmission of neural signals in the brain. Short-term plasticity is required for the transmission, encoding, and filtering of the neural signal, whereas long-term plasticity establishes more permanent changes in neural microcircuitry and thus underlies memory and learning. The realization of bioinspired circuits that can actually mimic signal processing in the brain demands the reproduction of both short- and long-term aspects of synaptic plasticity in a single device. Here, we demonstrate the implementation of neuromorphic functions similar to biological memory, such as short- to long-term memory transition, in non-volatile organic electrochemical transistors (OECTs). Depending on the training of the OECT, the device displays either short- or long-term plasticity, therefore, exhibiting non von Neumann characteristics with merged processing and storing functionalities. These results are a first step towards the implementation of organic-based neuromorphic circuits.

Microdose Induced Data Loss on Floating Gate Memories

NASA Technical Reports Server (NTRS)

Guertin, Steven M.; Nguyen, Duc M.; Patterson, Jeffrey D.

2006-01-01

Heavy ion irradiation of flash memories shows loss of stored data. The fluence dependence is indicative of microdose effects. Other qualitative factors identifying the effect as microdose are discussed. The data is presented, and compared to statistical results of a microdose target-based model.

Layer-by-layer charging in non-volatile memory devices using embedded sub-2 nm platinum nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ramalingam, Balavinayagam; Zheng, Haisheng; Gangopadhyay, Shubhra, E-mail: gangopadhyays@missouri.edu

In this work, we demonstrate multi-level operation of a non-volatile memory metal oxide semiconductor capacitor by controlled layer-by-layer charging of platinum nanoparticle (PtNP) floating gate devices with defined gate voltage bias ranges. The device consists of two layers of ultra-fine, sub-2 nm PtNPs integrated between Al{sub 2}O{sub 3} tunneling and separation layers. PtNP size and interparticle distance were varied to control the particle self-capacitance and associated Coulomb charging energy. Likewise, the tunneling layer thicknesses were also varied to control electron tunneling to the first and second PtNP layers. The final device configuration with optimal charging behavior and multi-level programming was attainedmore » with a 3 nm Al{sub 2}O{sub 3} initial tunneling layer, initial PtNP layer with particle size 0.54 ± 0.12 nm and interparticle distance 4.65 ± 2.09 nm, 3 nm Al{sub 2}O{sub 3} layer to separate the PtNP layers, and second particle layer with 1.11 ± 0.28 nm PtNP size and interparticle distance 2.75 ± 1.05 nm. In this device, the memory window of the first PtNP layer saturated over a programming bias range of 7 V to 14 V, after which the second PtNP layer starts charging, exhibiting a multi-step memory window with layer-by-layer charging.« less

High Performance Data Transfer for Distributed Data Intensive Sciences

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fang, Chin; Cottrell, R 'Les' A.; Hanushevsky, Andrew B.

We report on the development of ZX software providing high performance data transfer and encryption. The design scales in: computation power, network interfaces, and IOPS while carefully balancing the available resources. Two U.S. patent-pending algorithms help tackle data sets containing lots of small files and very large files, and provide insensitivity to network latency. It has a cluster-oriented architecture, using peer-to-peer technologies to ease deployment, operation, usage, and resource discovery. Its unique optimizations enable effective use of flash memory. Using a pair of existing data transfer nodes at SLAC and NERSC, we compared its performance to that of bbcp andmore » GridFTP and determined that they were comparable. With a proof of concept created using two four-node clusters with multiple distributed multi-core CPUs, network interfaces and flash memory, we achieved 155Gbps memory-to-memory over a 2x100Gbps link aggregated channel and 70Gbps file-to-file with encryption over a 5000 mile 100Gbps link.« less

Improved speed and data retention characteristics in flash memory using a stacked HfO2/Ta2O5 charge-trapping layer

NASA Astrophysics Data System (ADS)

Zheng, Zhiwei; Huo, Zongliang; Zhang, Manhong; Zhu, Chenxin; Liu, Jing; Liu, Ming

2011-10-01

This paper reports the simultaneous improvements in erase speed and data retention characteristics in flash memory using a stacked HfO2/Ta2O5 charge-trapping layer. In comparison to a memory capacitor with a single HfO2 trapping layer, the erase speed of a memory capacitor with a stacked HfO2/Ta2O5 charge-trapping layer is 100 times faster and its memory window is enlarged from 2.7 to 4.8 V for the same ±16 V sweeping voltage range. With the same initial window of ΔVFB = 4 V, the device with a stacked HfO2/Ta2O5 charge-trapping layer has a 3.5 V extrapolated 10-year retention window, while the control device with a single HfO2 trapping layer has only 2.5 V for the extrapolated 10-year window. The present results demonstrate that the device with the stacked HfO2/Ta2O5 charge-trapping layer has a strong potential for future high-performance nonvolatile memory application.

Modeling of SONOS Memory Cell Erase Cycle

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat H.

2011-01-01

Utilization of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) nonvolatile semiconductor memories as a flash memory has many advantages. These electrically erasable programmable read-only memories (EEPROMs) utilize low programming voltages, have a high erase/write cycle lifetime, are radiation hardened, and are compatible with high-density scaled CMOS for low power, portable electronics. In this paper, the SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. Comparisons were made between the model predictions and experimental data.

SONOS Nonvolatile Memory Cell Programming Characteristics

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2010-01-01

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory is gaining favor over conventional EEPROM FLASH memory technology. This paper characterizes the SONOS write operation using a nonquasi-static MOSFET model. This includes floating gate charge and voltage characteristics as well as tunneling current, voltage threshold and drain current characterization. The characterization of the SONOS memory cell predicted by the model closely agrees with experimental data obtained from actual SONOS memory cells. The tunnel current, drain current, threshold voltage and read drain current all closely agreed with empirical data.

Performance Evaluation and Improvement of Ferroelectric Field-Effect Transistor Memory

NASA Astrophysics Data System (ADS)

Yu, Hyung Suk

Flash memory is reaching scaling limitations rapidly due to reduction of charge in floating gates, charge leakage and capacitive coupling between cells which cause threshold voltage fluctuations, short retention times, and interference. Many new memory technologies are being considered as alternatives to flash memory in an effort to overcome these limitations. Ferroelectric Field-Effect Transistor (FeFET) is one of the main emerging candidates because of its structural similarity to conventional FETs and fast switching speed. Nevertheless, the performance of FeFETs have not been systematically compared and analyzed against other competing technologies. In this work, we first benchmark the intrinsic performance of FeFETs and other memories by simulations in order to identify the strengths and weaknesses of FeFETs. To simulate realistic memory applications, we compare memories on an array structure. For the comparisons, we construct an accurate delay model and verify it by benchmarking against exact HSPICE simulations. Second, we propose an accurate model for FeFET memory window since the existing model has limitations. The existing model assumes symmetric operation voltages but it is not valid for the practical asymmetric operation voltages. In this modeling, we consider practical operation voltages and device dimensions. Also, we investigate realistic changes of memory window over time and retention time of FeFETs. Last, to improve memory window and subthreshold swing, we suggest nonplanar junctionless structures for FeFETs. Using the suggested structures, we study the dimensional dependences of crucial parameters like memory window and subthreshold swing and also analyze key interference mechanisms.

Statistical regularities in the return intervals of volatility

NASA Astrophysics Data System (ADS)

Wang, F.; Weber, P.; Yamasaki, K.; Havlin, S.; Stanley, H. E.

2007-01-01

We discuss recent results concerning statistical regularities in the return intervals of volatility in financial markets. In particular, we show how the analysis of volatility return intervals, defined as the time between two volatilities larger than a given threshold, can help to get a better understanding of the behavior of financial time series. We find scaling in the distribution of return intervals for thresholds ranging over a factor of 25, from 0.6 to 15 standard deviations, and also for various time windows from one minute up to 390 min (an entire trading day). Moreover, these results are universal for different stocks, commodities, interest rates as well as currencies. We also analyze the memory in the return intervals which relates to the memory in the volatility and find two scaling regimes, ℓ<ℓ* with α1=0.64±0.02 and ℓ> ℓ* with α2=0.92±0.04; these exponent values are similar to results of Liu et al. for the volatility. As an application, we use the scaling and memory properties of the return intervals to suggest a possibly useful method for estimating risk.

Microwave-Assisted Size Control of Colloidal Nickel Nanocrystals for Colloidal Nanocrystals-Based Non-volatile Memory Devices

NASA Astrophysics Data System (ADS)

Yadav, Manoj; Velampati, Ravi Shankar R.; Mandal, D.; Sharma, Rohit

2018-03-01

Colloidal synthesis and size control of nickel (Ni) nanocrystals (NCs) below 10 nm are reported using a microwave synthesis method. The synthesised colloidal NCs have been characterized using x-ray diffraction, transmission electron microscopy (TEM) and dynamic light scattering (DLS). XRD analysis highlights the face centred cubic crystal structure of synthesised NCs. The size of NCs observed using TEM and DLS have a distribution between 2.6 nm and 10 nm. Furthermore, atomic force microscopy analysis of spin-coated NCs over a silicon dioxide surface has been carried out to identify an optimum spin condition that can be used for the fabrication of a metal oxide semiconductor (MOS) non-volatile memory (NVM) capacitor. Subsequently, the fabrication of a MOS NVM capacitor is reported to demonstrate the potential application of colloidal synthesized Ni NCs in NVM devices. We also report the capacitance-voltage (C-V) and capacitance-time (C-t) response of the fabricated MOS NVM capacitor. The C-V and C-t characteristics depict a large flat band voltage shift (V FB) and high retention time, respectively, which indicate that colloidal Ni NCs are excellent candidates for applications in next-generation NVM devices.

A graphene-based non-volatile memory

NASA Astrophysics Data System (ADS)

Loisel, Loïc.; Maurice, Ange; Lebental, Bérengère; Vezzoli, Stefano; Cojocaru, Costel-Sorin; Tay, Beng Kang

2015-09-01

We report on the development and characterization of a simple two-terminal non-volatile graphene switch. After an initial electroforming step during which Joule heating leads to the formation of a nano-gap impeding the current flow, the devices can be switched reversibly between two well-separated resistance states. To do so, either voltage sweeps or pulses can be used, with the condition that VSET < VRESET , where SET is the process decreasing the resistance and RESET the process increasing the resistance. We achieve reversible switching on more than 100 cycles with resistance ratio values of 104. This approach of graphene memory is competitive as compared to other graphene approaches such as redox of graphene oxide, or electro-mechanical switches with suspended graphene. We suggest a switching model based on a planar electro-mechanical switch, whereby electrostatic, elastic and friction forces are competing to switch devices ON and OFF, and the stability in the ON state is achieved by the formation of covalent bonds between the two stretched sides of the graphene, hence bridging the nano-gap. Developing a planar electro-mechanical switch enables to obtain the advantages of electro-mechanical switches while avoiding most of their drawbacks.

Pricing European option with transaction costs under the fractional long memory stochastic volatility model

NASA Astrophysics Data System (ADS)

Wang, Xiao-Tian; Wu, Min; Zhou, Ze-Min; Jing, Wei-Shu

2012-02-01

This paper deals with the problem of discrete time option pricing using the fractional long memory stochastic volatility model with transaction costs. Through the 'anchoring and adjustment' argument in a discrete time setting, a European call option pricing formula is obtained.

Sentinel 2 MMFU: The first European Mass Memory System Based on NAND-Flash Storage Technology

NASA Astrophysics Data System (ADS)

Staehle, M.; Cassel, M.; Lonsdorfer, U.; Gliem, F.; Walter, D.; Fichna, T.

2011-08-01

Sentinel-2 is the multispectral optical mission of the EU-ESA GMES (Global Monitoring for Environment and Security) program, currently under development by Astrium-GmbH in Friedrichshafen (Germany) for a launch in 2013. The mission features a 490 Mbit/s optical sensor operating at high duty cycles, requiring in turn a large 2.4 Tbit on-board storage capacity.The required storage capacity motivated the selection of the NAND-Flash technology which was already secured by a lengthy period (2004-2009) of detailed testing, analysis and qualification by Astrium GmbH, IDA and ESTEC. The mass memory system is currently being realized by Astrium GmbH.

A 300MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers

NASA Astrophysics Data System (ADS)

Kajiyama, Shinya; Fujito, Masamichi; Kasai, Hideo; Mizuno, Makoto; Yamaguchi, Takanori; Shinagawa, Yutaka

A novel 300MHz embedded flash memory for dual-core microcontrollers with a shared ROM architecture is proposed. One of its features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduces performance penalty due to conflict of shared ROM accesses. Another feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch as a result of a shortened sense time of 0.63ns. The combination of the pipeline architecture and proposed sense amplifiers significantly reduces access-conflict penalties with shared ROM and enhances performance of 32-bit RISC dual-core microcontrollers by 30%.

Heavy Ion Irradiation Fluence Dependence for Single-Event Upsets in a NAND Flash Memory

NASA Technical Reports Server (NTRS)

Chen, Dakai; Wilcox, Edward; Ladbury, Raymond L.; Kim, Hak; Phan, Anthony; Seidleck, Christina; Label, Kenneth

2016-01-01

We investigated the single-event effect (SEE) susceptibility of the Micron 16 nm NAND flash, and found that the single-event upset (SEU) cross section varied inversely with cumulative fluence. We attribute the effect to the variable upset sensitivities of the memory cells. Furthermore, the effect impacts only single cell upsets in general. The rate of multiple-bit upsets remained relatively constant with fluence. The current test standards and procedures assume that SEU follow a Poisson process and do not take into account the variability in the error rate with fluence. Therefore, traditional SEE testing techniques may underestimate the on-orbit event rate for a device with variable upset sensitivity.

Solution-processed Al-chelated gelatin for highly transparent non-volatile memory applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang, Yu-Chi; Wang, Yeong-Her, E-mail: yhw@ee.ncku.edu.tw

2015-03-23

Using the biomaterial of Al-chelated gelatin (ACG) prepared by sol-gel method in the ITO/ACG/ITO structure, a highly transparent resistive random access memory (RRAM) was obtained. The transmittance of the fabricated device is approximately 83% at 550 nm while that of Al/gelatin/ITO is opaque. As to the ITO/gelatin/ITO RRAM, no resistive switching behavior can be seen. The ITO/ACG/ITO RRAM shows high ON/OFF current ratio (>10{sup 5}), low operation voltage, good uniformity, and retention characteristics at room temperature and 85 °C. The mechanism of the ACG-based memory devices is presented. The enhancement of these electrical properties can be attributed to the chelate effect ofmore » Al ions with gelatin. Results show that transparent ACG-based memory devices possess the potential for next-generation resistive memories and bio-electronic applications.« less

Characterization of nitride hole lateral transport in a charge trap flash memory by using a random telegraph signal method

NASA Astrophysics Data System (ADS)

Liu, Yu-Heng; Jiang, Cheng-Min; Lin, Hsiao-Yi; Wang, Tahui; Tsai, Wen-Jer; Lu, Tao-Cheng; Chen, Kuang-Chao; Lu, Chih-Yuan

2017-07-01

We use a random telegraph signal method to investigate nitride trapped hole lateral transport in a charge trap flash memory. The concept of this method is to utilize an interface oxide trap and its associated random telegraph signal as an internal probe to detect a local channel potential change resulting from nitride charge lateral movement. We apply different voltages to the drain of a memory cell and vary a bake temperature in retention to study the electric field and temperature dependence of hole lateral movement in a nitride. Thermal energy absorption by trapped holes in lateral transport is characterized. Mechanisms of hole lateral transport in retention are investigated. From the measured and modeled results, we find that thermally assisted trap-to-band tunneling is a major trapped hole emission mechanism in nitride hole lateral transport.

Long memory and volatility clustering: Is the empirical evidence consistent across stock markets?

NASA Astrophysics Data System (ADS)

Bentes, Sónia R.; Menezes, Rui; Mendes, Diana A.

2008-06-01

Long memory and volatility clustering are two stylized facts frequently related to financial markets. Traditionally, these phenomena have been studied based on conditionally heteroscedastic models like ARCH, GARCH, IGARCH and FIGARCH, inter alia. One advantage of these models is their ability to capture nonlinear dynamics. Another interesting manner to study the volatility phenomenon is by using measures based on the concept of entropy. In this paper we investigate the long memory and volatility clustering for the SP 500, NASDAQ 100 and Stoxx 50 indexes in order to compare the US and European Markets. Additionally, we compare the results from conditionally heteroscedastic models with those from the entropy measures. In the latter, we examine Shannon entropy, Renyi entropy and Tsallis entropy. The results corroborate the previous evidence of nonlinear dynamics in the time series considered.

The flash memory battle: How low can we go?

NASA Astrophysics Data System (ADS)

van Setten, Eelco; Wismans, Onno; Grim, Kees; Finders, Jo; Dusa, Mircea; Birkner, Robert; Richter, Rigo; Scherübl, Thomas

2008-03-01

With the introduction of the TWINSCAN XT:1900Gi the limit of the water based hyper-NA immersion lithography has been reached in terms of resolution. With a numerical aperture of 1.35 a single expose resolution of 36.5nm half pitch has been demonstrated. However the practical resolution limit in production will be closer to 40nm half pitch, without having to go to double patterning alike strategies. In the relentless Flash memory market the performance of the exposure tool is stretched to the limit for a competitive advantage and cost-effective product. In this paper we will present the results of an experimental study of the resolution limit of the NAND-Flash Memory Gate layer for a production-worthy process on the TWINSCAN XT:1900Gi. The entire gate layer will be qualified in terms of full wafer CD uniformity, aberration sensitivities for the different wordlines and feature-center placement errors for 38, 39, 40 and 43nm half pitch design rule. In this study we will also compare the performance of a binary intensity mask to a 6% attenuated phase shift mask and look at strategies to maximize Depth of Focus, and to desensitize the gate layer for lens aberrations and placement errors. The mask is one of the dominant contributors to the CD uniformity budget of the flash gate layer. Therefore the wafer measurements are compared to aerial image measurements of the mask using AIMSTM 45-193i to separate the mask contribution from the scanner contribution to the final imaging performance.

A Semi-Preemptive Garbage Collector for Solid State Drives

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Junghee; Kim, Youngjae; Shipman, Galen M

2011-01-01

NAND flash memory is a preferred storage media for various platforms ranging from embedded systems to enterprise-scale systems. Flash devices do not have any mechanical moving parts and provide low-latency access. They also require less power compared to rotating media. Unlike hard disks, flash devices use out-of-update operations and they require a garbage collection (GC) process to reclaim invalid pages to create free blocks. This GC process is a major cause of performance degradation when running concurrently with other I/O operations as internal bandwidth is consumed to reclaim these invalid pages. The invocation of the GC process is generally governedmore » by a low watermark on free blocks and other internal device metrics that different workloads meet at different intervals. This results in I/O performance that is highly dependent on workload characteristics. In this paper, we examine the GC process and propose a semi-preemptive GC scheme that can preempt on-going GC processing and service pending I/O requests in the queue. Moreover, we further enhance flash performance by pipelining internal GC operations and merge them with pending I/O requests whenever possible. Our experimental evaluation of this semi-preemptive GC sheme with realistic workloads demonstrate both improved performance and reduced performance variability. Write-dominant workloads show up to a 66.56% improvement in average response time with a 83.30% reduced variance in response time compared to the non-preemptive GC scheme.« less

Highly conducting leakage-free electrolyte for SrCoOx-based non-volatile memory device

NASA Astrophysics Data System (ADS)

Katase, Takayoshi; Suzuki, Yuki; Ohta, Hiromichi

2017-10-01

The electrochemical switching of SrCoOx-based non-volatile memory with a thin-film-transistor structure was examined by using liquid-leakage-free electrolytes with different conductivities (σ) as the gate insulator. We first examined leakage-free water, which is incorporated in the amorphous (a-) 12CaO.7Al2O3 film with a nanoporous structure (Calcium Aluminate with Nanopore), but the electrochemical oxidation/reduction of the SrCoOx layer required the application of a high gate voltage (Vg) up to 20 V for a very long current-flowing-time (t) ˜40 min, primarily due to the low σ [2.0 × 10-8 S cm-1 at room temperature (RT)] of leakage-free water. We then controlled the σ of the leakage-free electrolyte, infiltrated in the a-NaxTaO3 film with a nanopillar array structure, from 8.0 × 10-8 S cm-1 to 2.5 × 10-6 S cm-1 at RT by changing the x = 0.01-1.0. As the result, the t, required for the metallization of the SrCoOx layer under small Vg = -3 V, becomes two orders of magnitude shorter with increase of the σ of the a-NaxTaO3 leakage-free electrolyte. These results indicate that the ion migration in the leakage-free electrolyte is the rate-determining step for the electrochemical switching, compared to the other electrochemical process, and the high σ of the leakage-free electrolyte is the key factor for the development of the non-volatile SrCoOx-based electro-magnetic phase switching device.

A light writable microfluidic "flash memory": optically addressed actuator array with latched operation for microfluidic applications.

PubMed

Hua, Zhishan; Pal, Rohit; Srivannavit, Onnop; Burns, Mark A; Gulari, Erdogan

2008-03-01

This paper presents a novel optically addressed microactuator array (microfluidic "flash memory") with latched operation. Analogous to the address-data bus mediated memory address protocol in electronics, the microactuator array consists of individual phase-change based actuators addressed by localized heating through focused light patterns (address bus), which can be provided by a modified projector or high power laser pointer. A common pressure manifold (data bus) for the entire array is used to generate large deflections of the phase change actuators in the molten phase. The use of phase change material as the working media enables latched operation of the actuator array. After the initial light "writing" during which the phase is temporarily changed to molten, the actuated status is self-maintained by the solid phase of the actuator without power and pressure inputs. The microfluidic flash memory can be re-configured by a new light illumination pattern and common pressure signal. The proposed approach can achieve actuation of arbitrary units in a large-scale array without the need for complex external equipment such as solenoid valves and electrical modules, which leads to significantly simplified system implementation and compact system size. The proposed work therefore provides a flexible, energy-efficient, and low cost multiplexing solution for microfluidic applications based on physical displacements. As an example, the use of the latched microactuator array as "normally closed" or "normally open" microvalves is demonstrated. The phase-change wax is fully encapsulated and thus immune from contamination issues in fluidic environments.

Informing hot flash treatment decisions for breast cancer survivors: a systematic review of randomized trials comparing active interventions.

PubMed

Johns, Claire; Seav, Susan M; Dominick, Sally A; Gorman, Jessica R; Li, Hongying; Natarajan, Loki; Mao, Jun James; Irene Su, H

2016-04-01

Patient-centered decision making about hot flash treatments often incorporates a balance of efficacy and side effects in addition to patient preference. This systematic review examines randomized controlled trials (RCTs) comparing at least two non-hormonal hot flash treatments in breast cancer survivors. In July 2015, PubMed, SCOPUS, CINAHL, Cochrane, and Web of Science databases were searched for RCTs comparing active, non-hormonal hot flash treatments in female breast cancer survivors. Thirteen trials were included after identifying 906 potential studies. Four trials were dose comparison studies of pharmacologic treatments citalopram, venlafaxine, gabapentin, and paroxetine. Hot flash reduction did not differ by tamoxifen or aromatase inhibitor use. Citalopram 10, 20, and 30 mg daily had comparable outcomes. Venlafaxine 75 mg daily improved hot flashes without additional side effects from higher dosing. Gabapentin 900 mg daily improved hot flashes more than 300 mg. Paroxetine 10 mg daily had fewer side effects than 20 mg. Among four trials comparing different pharmacologic treatments, venlafaxine alleviated hot flash symptoms faster than clonidine; participants preferred venlafaxine over gabapentin. Five trials compared pharmacologic to non-pharmacologic treatments. Acupuncture had similar efficacy to venlafaxine and gabapentin but may have longer durability after completing treatment and fewer side effects. We could not perform a pooled meta-analysis because outcomes were not reported in comparable formats. Clinical trial data on non-hormonal hot flash treatments provide comparisons of hot flash efficacy and other patient important outcomes to guide clinical management. Clinicians can use the information to help patients select hot flash interventions.

Nanocrystal floating gate memory with solution-processed indium-zinc-tin-oxide channel and colloidal silver nanocrystals

NASA Astrophysics Data System (ADS)

Hu, Quanli; Ha, Sang-Hyub; Lee, Hyun Ho; Yoon, Tae-Sik

2011-12-01

A nanocrystal (NC) floating gate memory with solution-processed indium-zinc-tin-oxide (IZTO) channel and silver (Ag) NCs embedded in thin gate dielectric layer (SiO2(30 nm)/Al2O3(3 nm)) was fabricated. Both the IZTO channel and colloidal Ag NC layers were prepared by spin-coating and subsequent annealing, and dip-coating process, respectively. A threshold voltage shift up to ~0.9 V, corresponding to the electron density of 6.5 × 1011 cm-2, at gate pulsing <=10 V was achieved by the charging of high density NCs. These results present the successful non-volatile memory characteristics of an oxide-semiconductor transistor fabricated through solution processes.

Pyrolysis of carbonaceous materials with solvent quench recovery

DOEpatents

Green, Norman W.; Duraiswamy, Kandaswamy; Lumpkin, Robert E.; Knell, Everett W.; Mirza, Zia I.; Winter, Bruce L.

1978-04-18

In a continuous process for recovery of values contained in a solid carbonaceous material, the carbonaceous material is comminuted and then subjected to flash pyrolysis in the presence of a particulate heat source to form a pyrolysis product stream containing a carbon containing solid residue and volatilized hydrocarbons. After the carbon containing solid residue is separated from the pyrolysis product stream, values are obtained by condensing volatilized hydrocarbons. The particulate source of heat is formed by oxidizing carbon in the solid residue. Apparatus useful for practicing this process are disclosed.

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

NASA Astrophysics Data System (ADS)

Sargentis, Ch.; Giannakopoulos, K.; Travlos, A.; Tsamakis, D.

2007-04-01

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO 2 layer and are then fully covered by a HfO 2 layer. The HfO 2 is a high- k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance-voltage and conductance-voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.

Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

PubMed

Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

2016-09-19

Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

Multi-terminal memtransistors from polycrystalline monolayer molybdenum disulfide

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Lee, Hong-Sub; Bergeron, Hadallia; Balla, Itamar; Beck, Megan E.; Chen, Kan-Sheng; Hersam, Mark C.

2018-02-01

Memristors are two-terminal passive circuit elements that have been developed for use in non-volatile resistive random-access memory and may also be useful in neuromorphic computing. Memristors have higher endurance and faster read/write times than flash memory and can provide multi-bit data storage. However, although two-terminal memristors have demonstrated capacity for basic neural functions, synapses in the human brain outnumber neurons by more than a thousandfold, which implies that multi-terminal memristors are needed to perform complex functions such as heterosynaptic plasticity. Previous attempts to move beyond two-terminal memristors, such as the three-terminal Widrow-Hoff memristor and field-effect transistors with nanoionic gates or floating gates, did not achieve memristive switching in the transistor. Here we report the experimental realization of a multi-terminal hybrid memristor and transistor (that is, a memtransistor) using polycrystalline monolayer molybdenum disulfide (MoS2) in a scalable fabrication process. The two-dimensional MoS2 memtransistors show gate tunability in individual resistance states by four orders of magnitude, as well as large switching ratios, high cycling endurance and long-term retention of states. In addition to conventional neural learning behaviour of long-term potentiation/depression, six-terminal MoS2 memtransistors have gate-tunable heterosynaptic functionality, which is not achievable using two-terminal memristors. For example, the conductance between a pair of floating electrodes (pre- and post-synaptic neurons) is varied by a factor of about ten by applying voltage pulses to modulatory terminals. In situ scanning probe microscopy, cryogenic charge transport measurements and device modelling reveal that the bias-induced motion of MoS2 defects drives resistive switching by dynamically varying Schottky barrier heights. Overall, the seamless integration of a memristor and transistor into one multi-terminal device could enable complex neuromorphic learning and the study of the physics of defect kinetics in two-dimensional materials.

Organic non-volatile resistive photo-switches for flexible image detector arrays.

PubMed

Nau, Sebastian; Wolf, Christoph; Sax, Stefan; List-Kratochvil, Emil J W

2015-02-01

A unique implementation of an organic image detector using resistive photo-switchable pixels is presented. This resistive photo-switch comprises the vertical integration of an organic photodiode and an organic resistive switching memory element. The photodiodes act as a photosensitive element while the resistive switching elements simultaneously store the detected light information. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A Layered Solution for Supercomputing Storage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Grider, Gary

To solve the supercomputing challenge of memory keeping up with processing speed, a team at Los Alamos National Laboratory developed two innovative memory management and storage technologies. Burst buffers peel off data onto flash memory to support the checkpoint/restart paradigm of large simulations. MarFS adds a thin software layer enabling a new tier for campaign storage—based on inexpensive, failure-prone disk drives—between disk drives and tape archives.

Flexible and twistable non-volatile memory cell array with all-organic one diode-one resistor architecture.

PubMed

Ji, Yongsung; Zeigler, David F; Lee, Dong Su; Choi, Hyejung; Jen, Alex K-Y; Ko, Heung Cho; Kim, Tae-Wook

2013-01-01

Flexible organic memory devices are one of the integral components for future flexible organic electronics. However, high-density all-organic memory cell arrays on malleable substrates without cross-talk have not been demonstrated because of difficulties in their fabrication and relatively poor performances to date. Here we demonstrate the first flexible all-organic 64-bit memory cell array possessing one diode-one resistor architectures. Our all-organic one diode-one resistor cell exhibits excellent rewritable switching characteristics, even during and after harsh physical stresses. The write-read-erase-read output sequence of the cells perfectly correspond to the external pulse signal regardless of substrate deformation. The one diode-one resistor cell array is clearly addressed at the specified cells and encoded letters based on the standard ASCII character code. Our study on integrated organic memory cell arrays suggests that the all-organic one diode-one resistor cell architecture is suitable for high-density flexible organic memory applications in the future.

Piezoelectric control of magnetoelectric coupling driven non-volatile memory switching and self cooling effects in FE/FSMA multiferroic heterostructures

NASA Astrophysics Data System (ADS)

Singh, Kirandeep; Kaur, Davinder

2017-02-01

The manipulation of magnetic states and materials' spin degree-of-freedom via a control of an electric (E-) field has been recently pursued to develop magnetoelectric (ME) coupling-driven electronic data storage devices with high read/write endurance, fast dynamic response, and low energy dissipation. One major hurdle for this approach is to develop reliable materials which should be compatible with prevailing silicon (Si)-based complementary metal-oxide-semiconductor (CMOS) technology, simultaneously allowing small voltage for the tuning of magnetization switching. In this regard, multiferroic heterostructures where ferromagnetic (FM) and ferroelectric (FE) layers are alternatively grown on conventional Si substrates are promising as the piezoelectric control of magnetization switching is anticipated to be possible by an E-field. In this work, we study the ferromagnetic shape memory alloys based PbZr0.52Ti0.48O3/Ni50Mn35In15 (PZT/Ni-Mn-In) multiferroic heterostructures, and investigate their potential for CMOS compatible non-volatile magnetic data storage applications. We demonstrate the voltage-impulse controlled nonvolatile, reversible, and bistable magnetization switching at room temperature in Si-integrated PZT/Ni-Mn-In thin film multiferroic heterostructures. We also thoroughly unveil the various intriguing features in these materials, such as E-field tuned ME coupling and magnetocaloric effect, shape memory induced ferroelectric modulation, improved fatigue endurance as well as Refrigeration Capacity (RC). This comprehensive study suggests that these novel materials have a great potential for the development of unconventional nanoscale memory and refrigeration devices with self-cooling effect and enhanced refrigeration efficiency, thus providing a new venue for their applications.

Memristive behavior in a junctionless flash memory cell

DOE Office of Scientific and Technical Information (OSTI.GOV)

Orak, Ikram; Department of Physics, Faculty of Science and Art, Bingöl University, 12000 Bingöl; Ürel, Mustafa

2015-06-08

We report charge storage based memristive operation of a junctionless thin film flash memory cell when it is operated as a two terminal device by grounding the gate. Unlike memristors based on nanoionics, the presented device mode, which we refer to as the flashristor mode, potentially allows greater control over the memristive properties, allowing rational design. The mode is demonstrated using a depletion type n-channel ZnO transistor grown by atomic layer deposition (ALD), with HfO{sub 2} as the tunnel dielectric, Al{sub 2}O{sub 3} as the control dielectric, and non-stoichiometric silicon nitride as the charge storage layer. The device exhibits themore » pinched hysteresis of a memristor and in the unoptimized device, R{sub off}/R{sub on} ratios of about 3 are presented with low operating voltages below 5 V. A simplified model predicts R{sub off}/R{sub on} ratios can be improved significantly by adjusting the native threshold voltage of the devices. The repeatability of the resistive switching is excellent and devices exhibit 10{sup 6 }s retention time, which can, in principle, be improved by engineering the gate stack and storage layer properties. The flashristor mode can find use in analog information processing applications, such as neuromorphic computing, where well-behaving and highly repeatable memristive properties are desirable.« less

A Layered Solution for Supercomputing Storage

ScienceCinema

Grider, Gary

2018-06-13

To solve the supercomputing challenge of memory keeping up with processing speed, a team at Los Alamos National Laboratory developed two innovative memory management and storage technologies. Burst buffers peel off data onto flash memory to support the checkpoint/restart paradigm of large simulations. MarFS adds a thin software layer enabling a new tier for campaign storage—based on inexpensive, failure-prone disk drives—between disk drives and tape archives.

Numerical simulation of internal and near-nozzle flow of a gasoline direct injection fuel injector

NASA Astrophysics Data System (ADS)

Saha, Kaushik; Som, Sibendu; Battistoni, Michele; Li, Yanheng; Quan, Shaoping; Senecal, Peter Kelly

2015-12-01

A numerical study of two-phase flow inside the nozzle holes and the issuing spray jets for a multi-hole direct injection gasoline injector has been presented in this work. The injector geometry is representative of the Spray G nozzle, an eight-hole counterbore injector, from, the Engine Combustion Network (ECN). Simulations have been carried out for the fixed needle lift. Effects of turbulence, compressibility and, non-condensable gases have been considered in this work. Standard k—ɛ turbulence model has been used to model the turbulence. Homogeneous Relaxation Model (HRM) coupled with Volume of Fluid (VOF) approach has been utilized to capture the phase change phenomena inside and outside the injector nozzle. Three different boundary conditions for the outlet domain have been imposed to examine non-flashing and evaporative, non-flashing and non-evaporative, and flashing conditions. Inside the nozzle holes mild cavitation-like and in the near-nozzle region flash boiling phenomena have been predicted in this study when liquid fuel is subjected to superheated ambiance. Noticeable hole to hole variation has been also observed in terms of mass flow rates for all the holes under both flashing and non-flashing conditions.

Resistive RAMs as analog trimming elements

NASA Astrophysics Data System (ADS)

Aziza, H.; Perez, A.; Portal, J. M.

2018-04-01

This work investigates the use of Resistive Random Access Memory (RRAM) as an analog trimming device. The analog storage feature of the RRAM cell is evaluated and the ability of the RRAM to hold several resistance states is exploited to propose analog trim elements. To modulate the memory cell resistance, a series of short programming pulses are applied across the RRAM cell allowing a fine calibration of the RRAM resistance. The RRAM non volatility feature makes the analog device powers up already calibrated for the system in which the analog trimmed structure is embedded. To validate the concept, a test structure consisting of a voltage reference is evaluated.

Systems and methods for rapid processing and storage of data

DOEpatents

Stalzer, Mark A.

2017-01-24

Systems and methods of building massively parallel computing systems using low power computing complexes in accordance with embodiments of the invention are disclosed. A massively parallel computing system in accordance with one embodiment of the invention includes at least one Solid State Blade configured to communicate via a high performance network fabric. In addition, each Solid State Blade includes a processor configured to communicate with a plurality of low power computing complexes interconnected by a router, and each low power computing complex includes at least one general processing core, an accelerator, an I/O interface, and cache memory and is configured to communicate with non-volatile solid state memory.

Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory

NASA Astrophysics Data System (ADS)

Choe, Byeong-In; Park, Byung-Gook; Lee, Jong-Ho

2013-06-01

The program disturbance characteristic in the three-dimensional (3D) stack NAND flash was analyzed for the first time in terms of string select line (SSL) threshold voltage (Vth) and p-type body doping profile. From the edge word line (W/L) program disturbance, we can observe the boosted channel potential loss as a function of SSL Vth and body doping profile for SSL device. According to simulation work, a high Vth of the SSL device is required to suppress channel leakage during programming. When the body doping of the SSL device is high in the channel, there is a large band bending near the gate edge of the SSL adjacent to the edge W/L cell of boosted cell strings, which generates significantly electron-hole pairs. The generated electrons decreases the boosted channel potential, resulting in increase of program disturbance of the inhibit strings. Through optimization of the body doping profile of the SSL device, both channel leakage and the program disturbance are successfully suppressed for a highly reliable 3D stack NAND flash memory cell operation.

Face classification using electronic synapses

NASA Astrophysics Data System (ADS)

Yao, Peng; Wu, Huaqiang; Gao, Bin; Eryilmaz, Sukru Burc; Huang, Xueyao; Zhang, Wenqiang; Zhang, Qingtian; Deng, Ning; Shi, Luping; Wong, H.-S. Philip; Qian, He

2017-05-01

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system.

A Trustworthy Key Generation Prototype Based on DDR3 PUF for Wireless Sensor Networks

PubMed Central

Liu, Wenchao; Zhang, Zhenhua; Li, Miaoxin; Liu, Zhenglin

2014-01-01

Secret key leakage in wireless sensor networks (WSNs) is a high security risk especially when sensor nodes are deployed in hostile environment and physically accessible to attackers. With nowadays semi/fully-invasive attack techniques attackers can directly derive the cryptographic key from non-volatile memory (NVM) storage. Physically Unclonable Function (PUF) is a promising technology to resist node capture attacks, and it also provides a low cost and tamper-resistant key provisioning solution. In this paper, we designed a PUF based on double-data-rate SDRAM Type 3 (DDR3) memory by exploring its memory decay characteristics. We also described a prototype of 128-bit key generation based on DDR3 PUF with integrated fuzzy extractor. Due to the wide adoption of DDR3 memory in WSN, our proposed DDR3 PUF technology with high security levels and no required hardware changes is suitable for a wide range of WSN applications. PMID:24984058

Device and methods for writing and erasing analog information in small memory units via voltage pulses

DOEpatents

El Gabaly Marquez, Farid; Talin, Albert Alec

2018-04-17

Devices and methods for non-volatile analog data storage are described herein. In an exemplary embodiment, an analog memory device comprises a potential-carrier source layer, a barrier layer deposited on the source layer, and at least two storage layers deposited on the barrier layer. The memory device can be prepared to write and read data via application of a biasing voltage between the source layer and the storage layers, wherein the biasing voltage causes potential-carriers to migrate into the storage layers. After initialization, data can be written to the memory device by application of a voltage pulse between two storage layers that causes potential-carriers to migrate from one storage layer to another. A difference in concentration of potential carriers caused by migration of potential-carriers between the storage layers results in a voltage that can be measured in order to read the written data.

Face classification using electronic synapses.

PubMed

Yao, Peng; Wu, Huaqiang; Gao, Bin; Eryilmaz, Sukru Burc; Huang, Xueyao; Zhang, Wenqiang; Zhang, Qingtian; Deng, Ning; Shi, Luping; Wong, H-S Philip; Qian, He

2017-05-12

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system.

Enabling universal memory by overcoming the contradictory speed and stability nature of phase-change materials.

PubMed

Wang, Weijie; Loke, Desmond; Shi, Luping; Zhao, Rong; Yang, Hongxin; Law, Leong-Tat; Ng, Lung-Tat; Lim, Kian-Guan; Yeo, Yee-Chia; Chong, Tow-Chong; Lacaita, Andrea L

2012-01-01

The quest for universal memory is driving the rapid development of memories with superior all-round capabilities in non-volatility, high speed, high endurance and low power. Phase-change materials are highly promising in this respect. However, their contradictory speed and stability properties present a key challenge towards this ambition. We reveal that as the device size decreases, the phase-change mechanism changes from the material inherent crystallization mechanism (either nucleation- or growth-dominated), to the hetero-crystallization mechanism, which resulted in a significant increase in PCRAM speeds. Reducing the grain size can further increase the speed of phase-change. Such grain size effect on speed becomes increasingly significant at smaller device sizes. Together with the nano-thermal and electrical effects, fast phase-change, good stability and high endurance can be achieved. These findings lead to a feasible solution to achieve a universal memory.

Enabling Universal Memory by Overcoming the Contradictory Speed and Stability Nature of Phase-Change Materials

PubMed Central

Wang, Weijie; Loke, Desmond; Shi, Luping; Zhao, Rong; Yang, Hongxin; Law, Leong-Tat; Ng, Lung-Tat; Lim, Kian-Guan; Yeo, Yee-Chia; Chong, Tow-Chong; Lacaita, Andrea L.

2012-01-01

The quest for universal memory is driving the rapid development of memories with superior all-round capabilities in non-volatility, high speed, high endurance and low power. Phase-change materials are highly promising in this respect. However, their contradictory speed and stability properties present a key challenge towards this ambition. We reveal that as the device size decreases, the phase-change mechanism changes from the material inherent crystallization mechanism (either nucleation- or growth-dominated), to the hetero-crystallization mechanism, which resulted in a significant increase in PCRAM speeds. Reducing the grain size can further increase the speed of phase-change. Such grain size effect on speed becomes increasingly significant at smaller device sizes. Together with the nano-thermal and electrical effects, fast phase-change, good stability and high endurance can be achieved. These findings lead to a feasible solution to achieve a universal memory. PMID:22496956

Quantification of Lightning-induced Nitrogen Oxides in CMAQ and the Assessment of its impact on Ground-level Air Quality

EPA Science Inventory

Lightning-induced nitrogen oxides (LNOX), in the presence of sunlight, volatile organic compounds and water, can be a relatively large but uncertain source for ozone (O3) and hydroxyl radical (OH) in the atmosphere. Using lightning flash data from the National Lightning Detection...

Investigation of the non-volatile resistance change in noncentrosymmetric compounds

PubMed Central

Herng, T. S.; Kumar, A.; Ong, C. S.; Feng, Y. P.; Lu, Y. H.; Zeng, K. Y.; Ding, J.

2012-01-01

Coexistence of polarization and resistance-switching characteristics in single compounds has been long inspired scientific and technological interests. Here, we report the non-volatile resistance change in noncentrosymmetric compounds investigated by using defect nanotechnology and contact engineering. Using a noncentrosymmetric material of ZnO as example, we first transformed ZnO into high resistance state. Then ZnO electrical polarization was probed and its domains polarized 180° along the [001]-axis with long-lasting memory effect (>25 hours). Based on our experimental observations, we have developed a vacancy-mediated pseudoferroelectricity model. Our first-principle calculations propose that vacancy defects initiate a spontaneous inverted domains nucleation at grain boundaries, and then they grow in the presence of an electrical field. The propagation of inverted domains follows the scanning tip motion under applied electrical field, leading to the growth of polarized domains over large areas. PMID:22905318

The non-random walk of stock prices: the long-term correlation between signs and sizes

NASA Astrophysics Data System (ADS)

La Spada, G.; Farmer, J. D.; Lillo, F.

2008-08-01

We investigate the random walk of prices by developing a simple model relating the properties of the signs and absolute values of individual price changes to the diffusion rate (volatility) of prices at longer time scales. We show that this benchmark model is unable to reproduce the diffusion properties of real prices. Specifically, we find that for one hour intervals this model consistently over-predicts the volatility of real price series by about 70%, and that this effect becomes stronger as the length of the intervals increases. By selectively shuffling some components of the data while preserving others we are able to show that this discrepancy is caused by a subtle but long-range non-contemporaneous correlation between the signs and sizes of individual returns. We conjecture that this is related to the long-memory of transaction signs and the need to enforce market efficiency.

Recent trends in hardware security exploiting hybrid CMOS-resistive memory circuits

NASA Astrophysics Data System (ADS)

Sahay, Shubham; Suri, Manan

2017-12-01

This paper provides a comprehensive review and insight of recent trends in the field of random number generator (RNG) and physically unclonable function (PUF) circuits implemented using different types of emerging resistive non-volatile (NVM) memory devices. We present a detailed review of hybrid RNG/PUF implementations based on the use of (i) Spin-Transfer Torque (STT-MRAM), and (ii) metal-oxide based (OxRAM), NVM devices. Various approaches on Hybrid CMOS-NVM RNG/PUF circuits are considered, followed by a discussion on different nanoscale device phenomena. Certain nanoscale device phenomena (variability/stochasticity etc), which are otherwise undesirable for reliable memory and storage applications, form the basis for low power and highly scalable RNG/PUF circuits. Detailed qualitative comparison and benchmarking of all implementations is performed.

A CCD Monolithic LMS Adaptive Analog Signal Processor Integrated Circuit.

DTIC Science & Technology

1980-03-01

adaptive filter with electrically- reprogrammable MOS analog conductance weights. I The analog and digital peripheral MOS on-chip circuits are provided with...electrically reprogrammable analog weights at tap positions along a CCD analog delay line in order to form a basic linear combiner for adaptive filtering...electrically reprogrammable analog conductance weights was introduced with the use of non-volatile MNOS memory 6-7 transistors biased in their triode

Ferroelectric behavior and reproducible Bi-stable resistance switching property in K-doped ZnO thin films as candidate for application in non-volatile memories

NASA Astrophysics Data System (ADS)

Lee, J. W.; Subramaniam, N. G.; Kang, T. W.; Shon, Yoon; Kim, E. K.

2015-05-01

Potassium-doped ZnO thin films electrodeposited on indium tin oxide (ITO) coated glass substrates exhibited ferroelectric behavior with a remnant polarization of 0.2 μC/cm2. Especially, wave forms showing the applied input voltage Vi and output voltage Vo were obtained for Al/ZnO:K/ITO structure. It exhibits a superposition of Vi (input) and Vo (output) signal from Al/ZnO:K/ITO structure with a clear phase shift between the two wave forms which again confirms that the observed ferroelectric hysteresis curve is not related to leaky dielectric materials. The current-voltage characteristics of Al/ZnO:K/ITO structures measured for several cycles revealed bi-stable switching characteristics. The reproducible bi-stable switching characteristics for the mentioned structures had good retention in one particular resistance state. Around one order of switching was realized between low and high resistance states. The switching property thought to be polarization induced originating out from the ferroelectric properties of the potassium doped ZnO thin film. The switching between ZnO:K/ITO interface is assumed to be critical for stability in switching for several cycles. Possible application of this structure in non-volatile memories is explored.

MSL-RAD Cruise Operations Concept

NASA Technical Reports Server (NTRS)

Brinza, David E.; Zeitlin, Cary; Hassler, Donald; Weigle, Gerald E.; Boettcher, Stephan; Martin, Cesar; Wimmer-Schweingrubber, Robert

2012-01-01

The Mars Science Laboratory (MSL) payload includes the Radiation Assessment Detector (RAD) instrument, intended to fully characterize the radiation environment for the MSL mission. The RAD instrument operations concept is intended to reduce impact to spacecraft resources and effort for the MSL operations team. By design, RAD autonomously performs regular science observations without the need for frequent commanding from the Rover Compute Element (RCE). RAD operates with pre-defined "sleep" and "observe" periods, with an adjustable duty cycle for meeting power and data volume constraints during the mission. At the start of a new science observation, RAD performs a pre-observation activity to assess count rates for selected RAD detector elements. Based on this assessment, RAD can enter "solar event" mode, in which instrument parameters (including observation duration) are selected to more effectively characterize the environment. At the end of each observation period, RAD stores a time-tagged, fixed length science data packet in its non-volatile mass memory storage. The operating cadence is defined by adjustable parameters, also stored in non-volatile memory within the instrument. Periodically, the RCE executes an on-board sequence to transfer RAD science data packets from the instrument mass storage to the MSL downlink buffer. Infrequently, the RAD instrument operating configuration is modified by updating internal parameter tables and configuration entries.

Non-volatile, high density, high speed, Micromagnet-Hall effect Random Access Memory (MHRAM)

NASA Technical Reports Server (NTRS)

Wu, Jiin C.; Katti, Romney R.; Stadler, Henry L.

1991-01-01

The micromagnetic Hall effect random access memory (MHRAM) has the potential of replacing ROMs, EPROMs, EEPROMs, and SRAMs because of its ability to achieve non-volatility, radiation hardness, high density, and fast access times, simultaneously. Information is stored magnetically in small magnetic elements (micromagnets), allowing unlimited data retention time, unlimited numbers of rewrite cycles, and inherent radiation hardness and SEU immunity, making the MHRAM suitable for ground based as well as spaceflight applications. The MHRAM device design is not affected by areal property fluctuations in the micromagnet, so high operating margins and high yield can be achieved in large scale integrated circuit (IC) fabrication. The MHRAM has short access times (less than 100 nsec). Write access time is short because on-chip transistors are used to gate current quickly, and magnetization reversal in the micromagnet can occur in a matter of a few nanoseconds. Read access time is short because the high electron mobility sensor (InAs or InSb) produces a large signal voltage in response to the fringing magnetic field from the micromagnet. High storage density is achieved since a unit cell consists only of two transistors and one micromagnet Hall effect element. By comparison, a DRAM unit cell has one transistor and one capacitor, and a SRAM unit cell has six transistors.

DOE Office of Scientific and Technical Information (OSTI.GOV)

An, Ho-Myoung; Kim, Hee-Dong; Kim, Tae Geun, E-mail: tgkim1@korea.ac.kr

Graphical abstract: The degradation tendency extracted by CP technique was almost the same in both the bulk-type and TFT-type cells. - Highlights: • D{sub it} is directly investigated from bulk-type and TFT-type CTF memory. • Charge pumping technique was employed to analyze the D{sub it} information. • To apply the CP technique to monitor the reliability of the 3D NAND flash. - Abstract: The energy distribution and density of interface traps (D{sub it}) are directly investigated from bulk-type and thin-film transistor (TFT)-type charge trap flash memory cells with tunnel oxide degradation, under program/erase (P/E) cycling using a charge pumping (CP)more » technique, in view of application in a 3-demension stackable NAND flash memory cell. After P/E cycling in bulk-type devices, the interface trap density gradually increased from 1.55 × 10{sup 12} cm{sup −2} eV{sup −1} to 3.66 × 10{sup 13} cm{sup −2} eV{sup −1} due to tunnel oxide damage, which was consistent with the subthreshold swing and transconductance degradation after P/E cycling. Its distribution moved toward shallow energy levels with increasing cycling numbers, which coincided with the decay rate degradation with short-term retention time. The tendency extracted with the CP technique for D{sub it} of the TFT-type cells was similar to those of bulk-type cells.« less

Dependence of Grain Size on the Performance of a Polysilicon Channel TFT for 3D NAND Flash Memory.

PubMed

Kim, Seung-Yoon; Park, Jong Kyung; Hwang, Wan Sik; Lee, Seung-Jun; Lee, Ki-Hong; Pyi, Seung Ho; Cho, Byung Jin

2016-05-01

We investigated the dependence of grain size on the performance of a polycrystalline silicon (poly-Si) channel TFT for application to 3D NAND Flash memory devices. It has been found that the device performance and memory characteristics are strongly affected by the grain size of the poly-Si channel. Higher on-state current, faster program speed, and poor endurance/reliability properties are observed when the poly-Si grain size is large. These are mainly attributed to the different local electric field induced by an oxide valley at the interface between the poly-Si channel and the gate oxide. In addition, the trap density at the gate oxide interface was successfully measured using a charge pumping method by the separation between the gate oxide interface traps and traps at the grain boundaries in the poly-Si channel. The poly-Si channel with larger grain size has lower interface trap density.

Memory Decline in Peri- and Post-menopausal Women: The Potential of Mind–Body Medicine to Improve Cognitive Performance

PubMed Central

Sliwinski, Jim R; Johnson, Aimee K; Elkins, Gary R

2014-01-01

Cognitive decline is a frequent complaint during the menopause transition and among post-menopausal women. Changes in memory correspond with diminished estrogen production. Further, many peri- and post-menopausal women report sleep concerns, depression, and hot flashes, and these factors may contribute to cognitive decline. Hormone therapy can increase estrogen but is contraindicated for many women. Mind–body medicine has been shown to have beneficial effects on sleep, mood, and hot flashes, among post-menopausal women. Further, mind–body medicine holds potential in addressing symptoms of cognitive decline post-menopause. This study proposes an initial framework for how mind–body interventions may improve cognitive performance and inform future research seeking to identify the common and specific factors associated with mind–body medicine for addressing memory decline in peri- and post-menopausal women. It is our hope that this article will eventually lead to a more holistic and integrative approach to the treatment of cognitive deficits in peri- and post-menopausal women. PMID:25125972

High performance SONOS flash memory with in-situ silicon nanocrystals embedded in silicon nitride charge trapping layer

NASA Astrophysics Data System (ADS)

Lim, Jae-Gab; Yang, Seung-Dong; Yun, Ho-Jin; Jung, Jun-Kyo; Park, Jung-Hyun; Lim, Chan; Cho, Gyu-seok; Park, Seong-gye; Huh, Chul; Lee, Hi-Deok; Lee, Ga-Won

2018-02-01

In this paper, SONOS-type flash memory device with highly improved charge-trapping efficiency is suggested by using silicon nanocrystals (Si-NCs) embedded in silicon nitride (SiNX) charge trapping layer. The Si-NCs were in-situ grown by PECVD without additional post annealing process. The fabricated device shows high program/erase speed and retention property which is suitable for multi-level cell (MLC) application. Excellent performance and reliability for MLC are demonstrated with large memory window of ∼8.5 V and superior retention characteristics of 7% charge loss for 10 years. High resolution transmission electron microscopy image confirms the Si-NC formation and the size is around 1-2 nm which can be verified again in X-ray photoelectron spectroscopy (XPS) where pure Si bonds increase. Besides, XPS analysis implies that more nitrogen atoms make stable bonds at the regular lattice point. Photoluminescence spectra results also illustrate that Si-NCs formation in SiNx is an effective method to form deep trap states.

Flexible non-volatile memory devices based on organic semiconductors

NASA Astrophysics Data System (ADS)

Cosseddu, Piero; Casula, Giulia; Lai, Stefano; Bonfiglio, Annalisa

2015-09-01

The possibility of developing fully organic electronic circuits is critically dependent on the ability to realize a full set of electronic functionalities based on organic devices. In order to complete the scene, a fundamental element is still missing, i.e. reliable data storage. Over the past few years, a considerable effort has been spent on the development and optimization of organic polymer based memory elements. Among several possible solutions, transistor-based memories and resistive switching-based memories are attracting a great interest in the scientific community. In this paper, a route for the fabrication of organic semiconductor-based memory devices with performances beyond the state of the art is reported. Both the families of organic memories will be considered. A flexible resistive memory based on a novel combination of materials is presented. In particular, high retention time in ambient conditions are reported. Complementary, a low voltage transistor-based memory is presented. Low voltage operation is allowed by an hybrid, nano-sized dielectric, which is also responsible for the memory effect in the device. Thanks to the possibility of reproducibly fabricating such device on ultra-thin substrates, high mechanical stability is reported.

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S; Li, Dong

Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large increase in the size of on-chip caches. Since SRAM has low density and consumes large amount of leakage power, its use in designing on-chip caches has become more challenging. To address this issue, researchers are exploring the use of several emerging memory technologies, such as embedded DRAM, spin transfer torque RAM, resistive RAM, phase change RAM and domain wall memory. In this paper, we survey the architectural approaches proposed for designing memory systems and, specifically, caches with these emerging memory technologies. To highlight theirmore » similarities and differences, we present a classification of these technologies and architectural approaches based on their key characteristics. We also briefly summarize the challenges in using these technologies for architecting caches. We believe that this survey will help the readers gain insights into the emerging memory device technologies, and their potential use in designing future computing systems.« less

Dynamics of bid-ask spread return and volatility of the Chinese stock market

NASA Astrophysics Data System (ADS)

Qiu, Tian; Chen, Guang; Zhong, Li-Xin; Wu, Xiao-Run

2012-04-01

The bid-ask spread is taken as an important measure of the financial market liquidity. In this article, we study the dynamics of the spread return and the spread volatility of four liquid stocks in the Chinese stock market, including the memory effect and the multifractal nature. By investigating the autocorrelation function and the Detrended Fluctuation Analysis (DFA), we find that the spread return is the lack of long-range memory, while the spread volatility is long-range time correlated. Besides, the spread volatilities of different stocks present long-range cross-correlations. Moreover, by applying the Multifractal Detrended Fluctuation Analysis (MF-DFA), the spread return is observed to possess a strong multifractality, which is similar to the dynamics of a variety of financial quantities. Different from the spread return, the spread volatility exhibits a weak multifractal nature.

A portable ECG monitoring device with Bluetooth and Holter capabilities for telemedicine applications.

PubMed

Lucani, Daniel; Cataldo, Giancarlos; Cruz, Julio; Villegas, Guillermo; Wong, Sara

2006-01-01

A prototype of a portable ECG-monitoring device has been developed for clinical and non-clinical environments as part of a telemedicine system to provide remote and continuous surveillance of patients. The device can acquire, store and/or transmit ECG signals to computer-based platforms or specially configured access points (AP) with Intranet/Internet capabilities in order to reach remote monitoring stations. Acquired data can be stored in a flash memory card in FAT16 format for later recovery, or transmitted via Bluetooth or USB to a local station or AP. This data acquisition module (DAM) operates in two modes: Holter and on-line transmission.

77 FR 74222 - Certain Dynamic Random Access Memory and NAND Flash Memory Devices and Products Containing Same...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-12-13

..., California; Kingston Technology Co., Inc. of Fountain Valley, California; Logitek International S.A. (``LISA...: Clint Gerdine, Esq., Office of the General Counsel, U.S. International Trade Commission, 500 E Street SW....m. to 5:15 p.m.) in the Office of the Secretary, U.S. International Trade Commission, 500 E Street...

The Load of Lightning-induced Nitrogen Oxides and Its Impact on the Ground-level Ozone during Summertime over the Mountain West States

EPA Science Inventory

Lightning-induced nitrogen oxides (LNOX), in the presence of sunlight, volatile organic compounds and water, can be a relatively large but uncertain source for ozone (O3) and hydroxyl radical (OH) in the atmosphere. Using lightning flash data from the National Lightning Detection...

Semiconductor-based, large-area, flexible, electronic devices

DOEpatents

Goyal, Amit [Knoxville, TN

2011-03-15

Novel articles and methods to fabricate the same resulting in flexible, large-area, triaxially textured, single-crystal or single-crystal-like, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Semiconductor-based, large-area, flexible, electronic devices on {110}<100> oriented substrates

DOEpatents

Goyal, Amit

2014-08-05

Novel articles and methods to fabricate the same resulting in flexible, oriented, semiconductor-based, electronic devices on {110}<100> textured substrates are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

[100] or [110] aligned, semiconductor-based, large-area, flexible, electronic devices

DOEpatents

Goyal, Amit

2015-03-24

Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Forced Ion Migration for Chalcogenide Phase Change Memory Device

NASA Technical Reports Server (NTRS)

Campbell, Kristy A (Inventor)

2013-01-01

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge2Se3/SnTe, and Ge2Se3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

Forced ion migration for chalcogenide phase change memory device

NASA Technical Reports Server (NTRS)

Campbell, Kristy A. (Inventor)

2011-01-01

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more that two data states.

Forced ion migration for chalcogenide phase change memory device

NASA Technical Reports Server (NTRS)

Campbell, Kristy A. (Inventor)

2012-01-01

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

Relation between volatility correlations in financial markets and Omori processes occurring on all scales

NASA Astrophysics Data System (ADS)

Weber, Philipp; Wang, Fengzhong; Vodenska-Chitkushev, Irena; Havlin, Shlomo; Stanley, H. Eugene

2007-07-01

We analyze the memory in volatility by studying volatility return intervals, defined as the time between two consecutive fluctuations larger than a given threshold, in time periods following stock market crashes. Such an aftercrash period is characterized by the Omori law, which describes the decay in the rate of aftershocks of a given size with time t by a power law with exponent close to 1. A shock followed by such a power law decay in the rate is here called Omori process. We find self-similar features in the volatility. Specifically, within the aftercrash period there are smaller shocks that themselves constitute Omori processes on smaller scales, similar to the Omori process after the large crash. We call these smaller shocks subcrashes, which are followed by their own aftershocks. We also show that the Omori law holds not only after significant market crashes as shown by Lillo and Mantegna [Phys. Rev. E 68, 016119 (2003)], but also after “intermediate shocks.” By appropriate detrending we remove the influence of the crashes and subcrashes from the data, and find that this procedure significantly reduces the memory in the records. Moreover, when studying long-term correlated fractional Brownian motion and autoregressive fractionally integrated moving average artificial models for volatilities, we find Omori-type behavior after high volatilities. Thus, our results support the hypothesis that the memory in the volatility is related to the Omori processes present on different time scales.

Programmable computing with a single magnetoresistive element

NASA Astrophysics Data System (ADS)

Ney, A.; Pampuch, C.; Koch, R.; Ploog, K. H.

2003-10-01

The development of transistor-based integrated circuits for modern computing is a story of great success. However, the proved concept for enhancing computational power by continuous miniaturization is approaching its fundamental limits. Alternative approaches consider logic elements that are reconfigurable at run-time to overcome the rigid architecture of the present hardware systems. Implementation of parallel algorithms on such `chameleon' processors has the potential to yield a dramatic increase of computational speed, competitive with that of supercomputers. Owing to their functional flexibility, `chameleon' processors can be readily optimized with respect to any computer application. In conventional microprocessors, information must be transferred to a memory to prevent it from getting lost, because electrically processed information is volatile. Therefore the computational performance can be improved if the logic gate is additionally capable of storing the output. Here we describe a simple hardware concept for a programmable logic element that is based on a single magnetic random access memory (MRAM) cell. It combines the inherent advantage of a non-volatile output with flexible functionality which can be selected at run-time to operate as an AND, OR, NAND or NOR gate.

Current alcohol use is associated with a reduced risk of hot flashes in midlife women.

PubMed

Schilling, Chrissy; Gallicchio, Lisa; Miller, Susan R; Babus, Janice K; Lewis, Lynn M; Zacur, Howard; Flaws, Jodi A

2005-01-01

To examine the relation between current alcohol use, estradiol, estrone, and testosterone levels, and hot flashes in midlife women using a case-control study design. Cases were midlife women (45-54 years) who reported ever experiencing hot flashes. Controls were midlife women (45-54 years) who reported never experiencing hot flashes. Each participant completed a questionnaire and provided a blood sample that was used to measure estradiol, estrone, and testosterone levels by enzyme-linked immunosorbent assay. The results indicate that current alcohol use (at least one day per month) was significantly associated with a reduced risk of hot flashes compared to non-use of alcohol, independent of age and smoking habits. The hot flashes experienced by current alcohol users were less severe and less frequent than those experienced by non-users of alcohol. Further, current alcohol users had similar levels of estradiol, estrone, and testosterone compared to non-users of alcohol. These data suggest that current alcohol use is associated with a reduced risk of any, severe, and frequent hot flashes in midlife women by a mechanism that may not include changes in sex steroid hormone levels.

Volatilities, Traded Volumes, and Price Increments in Derivative Securities

NASA Astrophysics Data System (ADS)

Kim, Kyungsik; Lim, Gyuchang; Kim, Soo Yong; Scalas, Enrico

2007-03-01

We apply the detrended fluctuation analysis (DFA) to the statistics of the Korean treasury bond (KTB) futures from which the logarithmic increments, volatilities, and traded volumes are estimated over a specific time lag. For our case, the logarithmic increment of futures prices has no long-memory property, while the volatility and the traded volume exhibit the existence of long-memory property. To analyze and calculate whether the volatility clustering is due to the inherent higher-order correlation not detected by applying directly the DFA to logarithmic increments of the KTB futures, it is of importance to shuffle the original tick data of futures prices and to generate the geometric Brownian random walk with the same mean and standard deviation. It is really shown from comparing the three tick data that the higher-order correlation inherent in logarithmic increments makes the volatility clustering. Particularly, the result of the DFA on volatilities and traded volumes may be supported the hypothesis of price changes.

Volatilities, traded volumes, and the hypothesis of price increments in derivative securities

NASA Astrophysics Data System (ADS)

Lim, Gyuchang; Kim, SooYong; Scalas, Enrico; Kim, Kyungsik

2007-08-01

A detrended fluctuation analysis (DFA) is applied to the statistics of Korean treasury bond (KTB) futures from which the logarithmic increments, volatilities, and traded volumes are estimated over a specific time lag. In this study, the logarithmic increment of futures prices has no long-memory property, while the volatility and the traded volume exhibit the existence of the long-memory property. To analyze and calculate whether the volatility clustering is due to a inherent higher-order correlation not detected by with the direct application of the DFA to logarithmic increments of KTB futures, it is of importance to shuffle the original tick data of future prices and to generate a geometric Brownian random walk with the same mean and standard deviation. It was found from a comparison of the three tick data that the higher-order correlation inherent in logarithmic increments leads to volatility clustering. Particularly, the result of the DFA on volatilities and traded volumes can be supported by the hypothesis of price changes.

RISK OF LONG TERM HOT FLASHES AFTER NATURAL MENOPAUSE: EVIDENCE FROM THE PENN OVARIAN AGING COHORT

PubMed Central

Freeman, Ellen W.; Sammel, Mary D.; Sanders, Richard J.

2015-01-01

Objectives To estimate the risk of hot flashes relative to natural menopause and evaluate associations of hormone levels, behavioral and demographic variables with the risk of hot flashes following menopause. Methods Annual assessments of 255 women who were premenopausal at baseline and reached natural menopause during 16 years of follow-up. Results The prevalence of moderate/severe hot flashes increased in each premenopausal year, reaching a peak of 46% in the first two years after the final menstrual period (FMP). Hot flashes decreased slowly following menopause and did not return to premenopausal levels until 9 years after FMP. The mean duration of moderate/severe hot flashes after FMP was 4.6 (SD2.9) years (4.9, SD3.1 years for any hot flashes). One-third of women at 10 or more years following menopause continued to experience moderate/severe hot flashes. African American women (obese and non-obese) and obese white women had significantly greater risk of hot flashes compared to non-obese white women (interaction P=0.01). In multivariable analysis, increasing FSH levels before FMP (P<0.001), decreasing estradiol (OR 0.87, 95% CI: 0.78–0.96, P=0.008), and increasing anxiety (OR 1.05, 95% CI: 1.03–1.06, P<0.001) were significant risk factors for hot flashes, while higher education levels were protective (OR 0.66, 95% CI: 0.47–0.91, P=0.011). Conclusions Moderate/severe hot flashes continued on average for nearly 5 years following menopause; more than one- third of women observed for 10 or more years following menopause had moderate/severe hot flashes. Continuation of hot flashes for more than 5 years following menopause underscores the importance of determining individual risk/benefit when selecting hormone or non-hormonal therapy for menopausal symptoms. PMID:24473530

Reconfigurable Fault Tolerance for FPGAs

NASA Technical Reports Server (NTRS)

Shuler, Robert, Jr.

2010-01-01

The invention allows a field-programmable gate array (FPGA) or similar device to be efficiently reconfigured in whole or in part to provide higher capacity, non-redundant operation. The redundant device consists of functional units such as adders or multipliers, configuration memory for the functional units, a programmable routing method, configuration memory for the routing method, and various other features such as block RAM, I/O (random access memory, input/output) capability, dedicated carry logic, etc. The redundant device has three identical sets of functional units and routing resources and majority voters that correct errors. The configuration memory may or may not be redundant, depending on need. For example, SRAM-based FPGAs will need some type of radiation-tolerant configuration memory, or they will need triple-redundant configuration memory. Flash or anti-fuse devices will generally not need redundant configuration memory. Some means of loading and verifying the configuration memory is also required. These are all components of the pre-existing redundant FPGA. This innovation modifies the voter to accept a MODE input, which specifies whether ordinary voting is to occur, or if redundancy is to be split. Generally, additional routing resources will also be required to pass data between sections of the device created by splitting the redundancy. In redundancy mode, the voters produce an output corresponding to the two inputs that agree, in the usual fashion. In the split mode, the voters select just one input and convey this to the output, ignoring the other inputs. In a dual-redundant system (as opposed to triple-redundant), instead of a voter, there is some means to latch or gate a state update only when both inputs agree. In this case, the invention would require modification of the latch or gate so that it would operate normally in redundant mode, and would separately latch or gate the inputs in non-redundant mode.

Investigating of Memory - Colours of Intellectually Disabled Children and Virtual Game Addict Students

NASA Astrophysics Data System (ADS)

Sik Lányi, Cecília

We describe an investigation of memory colours. For this investigation Flash test software was developed. 75 observers used this test software in 4 groups: average elementary school children (aged: 8-9 years), intellectually disabled children (age: 9-15), virtual game addict university students (average age: 20) and university students who play with VR games rarely or never (average age: 20). In this pilot test we investigated the difference of memory colours of these 4 groups.

Variability of lightning activity over India on ENSO time scales

NASA Astrophysics Data System (ADS)

Ahmad, Adnan; Ghosh, Mili

2017-12-01

ENSO, the reliable indicator of inter-annual climate variation of the ocean-atmosphere system in the tropical Pacific region, can affect the overall lightning activity which is another atmospheric phenomenon. In the present study, the impact of the ENSO on the total lightning activity over India has been studied for the period 2004-2014. During the El-Nino period (July 2004-April 2005 and July 2009-April 2010), total number of lightning flashes increased by 10% and 18% respectively and during La-Nina period (July 2010-April 2011 and August 2011 to March 2012), the total number of lightning flashes decreased approximately by 19% and 28% respectively as compared to the mean of corresponding period (2004-14) of the Non-ENSO. Seasonal variation of flash density is also examined for the El-Nino and La-Nina period. The result shows that in the El-Nino period of the pre-monsoon and monsoon seasons, there is an increment in the flash density approximately by 48% and 9% respectively than the Non-ENSO and the spatial variation also having high flash density along the foot of Himalayas region. In the post-monsoon season, there is a marginal change in the flash density between El-Nino and the Non-ENSO. In the winter season, there is an increment in flash density in the El-Nino period approximately by 45% than the Non-ENSO. In the La-Nina period of the pre-monsoon and monsoon seasons, there is the decrement in the flash density approximately by the 44% and 24% respectively than the Non-ENSO. In the Post-monsoon season and winter season of La-Nina, the flash density is increased by about 24% and 33% over India. These findings can be applied to do proper planning of lightning induced hazard mitigation as lightning is of one of the major natural disasters of India.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhu, H. X.; Zhang, T.; Wang, R. X.

A nano-floating gate memory structure based on Ni nanocrystals (NCs) embedded HfO{sub x} film is deposited by means of radio-frequency magnetron sputtering. Microstructure investigations reveal that self-organized Ni-NCs with diameters of 4-8 nm are well dispersed in amorphous HfO{sub x} matrix. Pt/Ni-NCs embedded HfO{sub x}/Si/Ag capacitor structures exhibit voltage-dependent capacitance-voltage hysteresis, and a maximum flat-band voltage shift of 1.5 V, corresponding to a charge storage density of 6.0 × 10{sup 12} electrons/cm{sup 2}, is achieved. These capacitor memory cells exhibit good endurance characteristic up to 4 × 10{sup 4} cycles and excellent retention performance of 10{sup 5} s, fulfilling themore » requirements of next generation non-volatile memory devices. Schottky tunneling is proven to be responsible for electrons tunneling in these capacitors.« less

Charge storage and tunneling mechanism of Ni nanocrystals embedded HfOx film

NASA Astrophysics Data System (ADS)

Zhu, H. X.; Zhang, T.; Wang, R. X.; Zhang, Y. Y.; Li, L. T.; Qiu, X. Y.

2016-05-01

A nano-floating gate memory structure based on Ni nanocrystals (NCs) embedded HfOx film is deposited by means of radio-frequency magnetron sputtering. Microstructure investigations reveal that self-organized Ni-NCs with diameters of 4-8 nm are well dispersed in amorphous HfOx matrix. Pt/Ni-NCs embedded HfOx/Si/Ag capacitor structures exhibit voltage-dependent capacitance-voltage hysteresis, and a maximum flat-band voltage shift of 1.5 V, corresponding to a charge storage density of 6.0 × 1012 electrons/cm2, is achieved. These capacitor memory cells exhibit good endurance characteristic up to 4 × 104 cycles and excellent retention performance of 105 s, fulfilling the requirements of next generation non-volatile memory devices. Schottky tunneling is proven to be responsible for electrons tunneling in these capacitors.

Emulating short-term synaptic dynamics with memristive devices

NASA Astrophysics Data System (ADS)

Berdan, Radu; Vasilaki, Eleni; Khiat, Ali; Indiveri, Giacomo; Serb, Alexandru; Prodromakis, Themistoklis

2016-01-01

Neuromorphic architectures offer great promise for achieving computation capacities beyond conventional Von Neumann machines. The essential elements for achieving this vision are highly scalable synaptic mimics that do not undermine biological fidelity. Here we demonstrate that single solid-state TiO2 memristors can exhibit non-associative plasticity phenomena observed in biological synapses, supported by their metastable memory state transition properties. We show that, contrary to conventional uses of solid-state memory, the existence of rate-limiting volatility is a key feature for capturing short-term synaptic dynamics. We also show how the temporal dynamics of our prototypes can be exploited to implement spatio-temporal computation, demonstrating the memristors full potential for building biophysically realistic neural processing systems.

Acoustically assisted spin-transfer-torque switching of nanomagnets: An energy-efficient hybrid writing scheme for non-volatile memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Biswas, Ayan K.; Bandyopadhyay, Supriyo; Atulasimha, Jayasimha

We show that the energy dissipated to write bits in spin-transfer-torque random access memory can be reduced by an order of magnitude if a surface acoustic wave (SAW) is launched underneath the magneto-tunneling junctions (MTJs) storing the bits. The SAW-generated strain rotates the magnetization of every MTJs' soft magnet from the easy towards the hard axis, whereupon passage of a small spin-polarized current through a target MTJ selectively switches it to the desired state with > 99.99% probability at room temperature, thereby writing the bit. The other MTJs return to their original states at the completion of the SAW cycle.

Scientific developments of liquid crystal-based optical memory: a review

NASA Astrophysics Data System (ADS)

Prakash, Jai; Chandran, Achu; Biradar, Ashok M.

2017-01-01

The memory behavior in liquid crystals (LCs), although rarely observed, has made very significant headway over the past three decades since their discovery in nematic type LCs. It has gone from a mere scientific curiosity to application in variety of commodities. The memory element formed by numerous LCs have been protected by patents, and some commercialized, and used as compensation to non-volatile memory devices, and as memory in personal computers and digital cameras. They also have the low cost, large area, high speed, and high density memory needed for advanced computers and digital electronics. Short and long duration memory behavior for industrial applications have been obtained from several LC materials, and an LC memory with interesting features and applications has been demonstrated using numerous LCs. However, considerable challenges still exist in searching for highly efficient, stable, and long-lifespan materials and methods so that the development of useful memory devices is possible. This review focuses on the scientific and technological approach of fascinating applications of LC-based memory. We address the introduction, development status, novel design and engineering principles, and parameters of LC memory. We also address how the amalgamation of LCs could bring significant change/improvement in memory effects in the emerging field of nanotechnology, and the application of LC memory as the active component for futuristic and interesting memory devices.

Scientific developments of liquid crystal-based optical memory: a review.

PubMed

Prakash, Jai; Chandran, Achu; Biradar, Ashok M

2017-01-01

The memory behavior in liquid crystals (LCs), although rarely observed, has made very significant headway over the past three decades since their discovery in nematic type LCs. It has gone from a mere scientific curiosity to application in variety of commodities. The memory element formed by numerous LCs have been protected by patents, and some commercialized, and used as compensation to non-volatile memory devices, and as memory in personal computers and digital cameras. They also have the low cost, large area, high speed, and high density memory needed for advanced computers and digital electronics. Short and long duration memory behavior for industrial applications have been obtained from several LC materials, and an LC memory with interesting features and applications has been demonstrated using numerous LCs. However, considerable challenges still exist in searching for highly efficient, stable, and long-lifespan materials and methods so that the development of useful memory devices is possible. This review focuses on the scientific and technological approach of fascinating applications of LC-based memory. We address the introduction, development status, novel design and engineering principles, and parameters of LC memory. We also address how the amalgamation of LCs could bring significant change/improvement in memory effects in the emerging field of nanotechnology, and the application of LC memory as the active component for futuristic and interesting memory devices.

Aging changes in the female reproductive system

MedlinePlus

... Other common changes include: Menopause symptoms such as hot flashes, moodiness, headaches, and trouble sleeping Problems with short-term memory Decrease in breast tissue Lower sex drive (libido) and sexual response Increased risk of ...

In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory.

PubMed

Hwang, Eun Suk; Kim, Jun Shik; Jeon, Seok Min; Lee, Seung Jun; Jang, Younjin; Cho, Deok-Yong; Hwang, Cheol Seong

2018-04-01

The programming characteristics of charge trap flash memory device adopting amorphous In 2 Ga 2 ZnO 7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO 2 (blocking oxide)/p ++ -Si (control gate) substrate, where 3 nm thick atomic layer deposited Al 2 O 3 (tunneling oxide) and 5 nm thick low-pressure CVD Si 3 N 4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (E F ) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher E F of MOCVD a-IGZO.

In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory

NASA Astrophysics Data System (ADS)

Hwang, Eun Suk; Kim, Jun Shik; Jeon, Seok Min; Lee, Seung Jun; Jang, Younjin; Cho, Deok-Yong; Hwang, Cheol Seong

2018-04-01

The programming characteristics of charge trap flash memory device adopting amorphous In2Ga2ZnO7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO2 (blocking oxide)/p++-Si (control gate) substrate, where 3 nm thick atomic layer deposited Al2O3 (tunneling oxide) and 5 nm thick low-pressure CVD Si3N4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (E F) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher E F of MOCVD a-IGZO.

Mask replication using jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Selinidis, Kosta S.; Jones, Chris; Doyle, Gary F.; Brown, Laura; Imhof, Joseph; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

2011-11-01

The Jet and Flash Imprint Lithography (J-FILTM) process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 104 - 105imprints. This suggests that tens of thousands of templates/masks will be required to satisfy the needs of a manufacturing environment. Electron-beam patterning is too slow to feasibly deliver these volumes, but instead can provide a high quality "master" mask which can be replicated many times with an imprint lithography tool. This strategy has the capability to produce the required supply of "working" templates/masks. In this paper, we review the development of the mask form factor, imprint replication tools and the semiconductor mask replication process. A PerfectaTM MR5000 mask replication tool has been developed specifically to pattern replica masks from an ebeam written master. Performance results, including image placement, critical dimension uniformity, and pattern transfer are covered in detail.

Pilot evaluation of hypnosis for the treatment of hot flashes in breast cancer survivors.

PubMed

Elkins, Gary; Marcus, Joel; Stearns, Vered; Hasan Rajab, M

2007-05-01

This single arm, pilot study investigated the use of hypnosis to reduce hot flashes in 16 breast cancer survivors. Each patient provided baseline data and received 4 weekly sessions of hypnosis that followed a standardized transcript. Patients were also instructed in self-hypnosis. Throughout the clinical care, patients completed daily diaries of the frequency and severity of their hot flashes. Patients also completed baseline and post-treatment ratings of the degree to which hot flashes interfered with daily activities and quality of life. Results indicated a 59% decrease in total daily hot flashes and a 70% decrease in weekly hot flash scores from their baselines. There was also a significant decrease in the degree to which hot flashes interfered with daily activities for all measures including work, social activities, leisure activities, sleep, mood, concentration, relations with others, sexuality, enjoyment of life, and overall quality of life. This pilot study suggests that clinical hypnosis may be an effective non-hormonal and non-pharmacological treatment for hot flashes. A randomized, controlled clinical trial is planned to more definitively elucidate the efficacy and applicability of hypnosis for reducing hot flashes.

MRAM Technology Status

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2013-01-01

Magnetoresistive Random Access Memory (MRAM) is much different from conventional types of memory like SRAM, DRAM, and Flash, where electric charge is used to store information. Instead of exploiting the charge of an electron, MRAM uses its spin to store data. This new type of electronics is known as "spintronics." The primary focus of this report is the current generation of MRAM technology, and its reliability, vendors, and space-readiness.

Ferroelectric translational antiphase boundaries in nonpolar materials

PubMed Central

Wei, Xian-Kui; Tagantsev, Alexander K.; Kvasov, Alexander; Roleder, Krystian; Jia, Chun-Lin; Setter, Nava

2014-01-01

Ferroelectric materials are heavily used in electro-mechanics and electronics. Inside the ferroelectric, domain walls separate regions in which the spontaneous polarization is differently oriented. Properties of ferroelectric domain walls can differ from those of the domains themselves, leading to new exploitable phenomena. Even more exciting is that a non-ferroelectric material may have domain boundaries that are ferroelectric. Many materials possess translational antiphase boundaries. Such boundaries could be interesting entities to carry information if they were ferroelectric. Here we show first that antiphase boundaries in antiferroelectrics may possess ferroelectricity. We then identify these boundaries in the classical antiferroelectric lead zirconate and evidence their polarity by electron microscopy using negative spherical-aberration imaging technique. Ab initio modelling confirms the polar bi-stable nature of the walls. Ferroelectric antiphase boundaries could make high-density non-volatile memory; in comparison with the magnetic domain wall memory, they do not require current for operation and are an order of magnitude thinner. PMID:24398704

Average cross-responses in correlated financial markets

NASA Astrophysics Data System (ADS)

Wang, Shanshan; Schäfer, Rudi; Guhr, Thomas

2016-09-01

There are non-vanishing price responses across different stocks in correlated financial markets, reflecting non-Markovian features. We further study this issue by performing different averages, which identify active and passive cross-responses. The two average cross-responses show different characteristic dependences on the time lag. The passive cross-response exhibits a shorter response period with sizeable volatilities, while the corresponding period for the active cross-response is longer. The average cross-responses for a given stock are evaluated either with respect to the whole market or to different sectors. Using the response strength, the influences of individual stocks are identified and discussed. Moreover, the various cross-responses as well as the average cross-responses are compared with the self-responses. In contrast to the short-memory trade sign cross-correlations for each pair of stocks, the sign cross-correlations averaged over different pairs of stocks show long memory.

Announcing Supercomputer Summit

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wells, Jack; Bland, Buddy; Nichols, Jeff

Summit is the next leap in leadership-class computing systems for open science. With Summit we will be able to address, with greater complexity and higher fidelity, questions concerning who we are, our place on earth, and in our universe. Summit will deliver more than five times the computational performance of Titan’s 18,688 nodes, using only approximately 3,400 nodes when it arrives in 2017. Like Titan, Summit will have a hybrid architecture, and each node will contain multiple IBM POWER9 CPUs and NVIDIA Volta GPUs all connected together with NVIDIA’s high-speed NVLink. Each node will have over half a terabyte ofmore » coherent memory (high bandwidth memory + DDR4) addressable by all CPUs and GPUs plus 800GB of non-volatile RAM that can be used as a burst buffer or as extended memory. To provide a high rate of I/O throughput, the nodes will be connected in a non-blocking fat-tree using a dual-rail Mellanox EDR InfiniBand interconnect. Upon completion, Summit will allow researchers in all fields of science unprecedented access to solving some of the world’s most pressing challenges.« less

{100}<100> or 45.degree.-rotated {100}<100>, semiconductor-based, large-area, flexible, electronic devices

DOEpatents

Goyal, Amit [Knoxville, TN

2012-05-15

Novel articles and methods to fabricate the same resulting in flexible, {100}<100> or 45.degree.-rotated {100}<100> oriented, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Lead-free epitaxial ferroelectric material integration on semiconducting (100) Nb-doped SrTiO3 for low-power non-volatile memory and efficient ultraviolet ray detection

PubMed Central

Kundu, Souvik; Clavel, Michael; Biswas, Pranab; Chen, Bo; Song, Hyun-Cheol; Kumar, Prashant; Halder, Nripendra N.; Hudait, Mantu K.; Banerji, Pallab; Sanghadasa, Mohan; Priya, Shashank

2015-01-01

We report lead-free ferroelectric based resistive switching non-volatile memory (NVM) devices with epitaxial (1-x)BaTiO3-xBiFeO3 (x = 0.725) (BT-BFO) film integrated on semiconducting (100) Nb (0.7%) doped SrTiO3 (Nb:STO) substrates. The piezoelectric force microscopy (PFM) measurement at room temperature demonstrated ferroelectricity in the BT-BFO thin film. PFM results also reveal the repeatable polarization inversion by poling, manifesting its potential for read-write operation in NVM devices. The electroforming-free and ferroelectric polarization coupled electrical behaviour demonstrated excellent resistive switching with high retention time, cyclic endurance, and low set/reset voltages. X-ray photoelectron spectroscopy was utilized to determine the band alignment at the BT-BFO and Nb:STO heterojunction, and it exhibited staggered band alignment. This heterojunction is found to behave as an efficient ultraviolet photo-detector with low rise and fall time. The architecture also demonstrates half-wave rectification under low and high input signal frequencies, where the output distortion is minimal. The results provide avenue for an electrical switch that can regulate the pixels in low or high frequency images. Combined this work paves the pathway towards designing future generation low-power ferroelectric based microelectronic devices by merging both electrical and photovoltaic properties of BT-BFO materials. PMID:26202946

Lead-free epitaxial ferroelectric material integration on semiconducting (100) Nb-doped SrTiO3 for low-power non-volatile memory and efficient ultraviolet ray detection.

PubMed

Kundu, Souvik; Clavel, Michael; Biswas, Pranab; Chen, Bo; Song, Hyun-Cheol; Kumar, Prashant; Halder, Nripendra N; Hudait, Mantu K; Banerji, Pallab; Sanghadasa, Mohan; Priya, Shashank

2015-07-23

We report lead-free ferroelectric based resistive switching non-volatile memory (NVM) devices with epitaxial (1-x)BaTiO3-xBiFeO3 (x = 0.725) (BT-BFO) film integrated on semiconducting (100) Nb (0.7%) doped SrTiO3 (Nb:STO) substrates. The piezoelectric force microscopy (PFM) measurement at room temperature demonstrated ferroelectricity in the BT-BFO thin film. PFM results also reveal the repeatable polarization inversion by poling, manifesting its potential for read-write operation in NVM devices. The electroforming-free and ferroelectric polarization coupled electrical behaviour demonstrated excellent resistive switching with high retention time, cyclic endurance, and low set/reset voltages. X-ray photoelectron spectroscopy was utilized to determine the band alignment at the BT-BFO and Nb:STO heterojunction, and it exhibited staggered band alignment. This heterojunction is found to behave as an efficient ultraviolet photo-detector with low rise and fall time. The architecture also demonstrates half-wave rectification under low and high input signal frequencies, where the output distortion is minimal. The results provide avenue for an electrical switch that can regulate the pixels in low or high frequency images. Combined this work paves the pathway towards designing future generation low-power ferroelectric based microelectronic devices by merging both electrical and photovoltaic properties of BT-BFO materials.

78 FR 18637 - Self-Regulatory Organizations; Miami International Securities Exchange LLC; Notice of Filing of a...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-03-27

... the affected series, just prior to the erroneous transaction, was at least two times the standard bid... Regulation NMS, as it may be amended from time to time (the ``Plan''). The text of the proposed rule change... the markets experienced excessive volatility in an abbreviated time period, i.e., the ``flash crash...

82 FR 35991 - Certain Flash Memory Devices and Components Thereof; Notice of Commission Determination Not To...

Federal Register 2010, 2011, 2012, 2013, 2014

2017-08-02

... following respondents: SanDisk LLC of Milpitas, California; Western Digital Corporation of Irvine, California; Western Digital Technologies, Inc. of Milpitas, California; SanDisk Limited of Yokohama, Japan...

Direct observation of conductive filament formation in Alq3 based organic resistive memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Busby, Y., E-mail: yan.busby@unamur.be; Pireaux, J.-J.; Nau, S.

2015-08-21

This work explores resistive switching mechanisms in non-volatile organic memory devices based on tris(8-hydroxyquinolie)aluminum (Alq{sub 3}). Advanced characterization tools are applied to investigate metal diffusion in ITO/Alq{sub 3}/Ag memory device stacks leading to conductive filament formation. The morphology of Alq{sub 3}/Ag layers as a function of the metal evaporation conditions is studied by X-ray reflectivity, while depth profile analysis with X-ray photoelectron spectroscopy and time-of-flight secondary ion mass spectrometry is applied to characterize operational memory elements displaying reliable bistable current-voltage characteristics. 3D images of the distribution of silver inside the organic layer clearly point towards the existence of conductive filamentsmore » and allow for the identification of the initial filament formation and inactivation mechanisms during switching of the device. Initial filament formation is suggested to be driven by field assisted diffusion of silver from abundant structures formed during the top electrode evaporation, whereas thermochemical effects lead to local filament inactivation.« less

Effect of oxide insertion layer on resistance switching properties of copper phthalocyanine

NASA Astrophysics Data System (ADS)

Joshi, Nikhil G.; Pandya, Nirav C.; Joshi, U. S.

2013-02-01

Organic memory device showing resistance switching properties is a next-generation of the electrical memory unit. We have investigated the bistable resistance switching in current-voltage (I-V) characteristics of organic diode based on copper phthalocyanine (CuPc) film sandwiched between aluminum (Al) electrodes. Pronounced hysteresis in the I-V curves revealed a resistance switching with on-off ratio of the order of 85%. In order to control the charge injection in the CuPc, nanoscale indium oxide buffer layer was inserted to form Al/CuPc/In2O3/Al device. Analysis of I-V measurements revealed space charge limited switching conduction at the Al/CuPc interface. The traps in the organic layer and charge blocking by oxide insertion layer have been used to explain the absence of resistance switching in the oxide buffer layered memory device cell. Present study offer potential applications for CuPc organic semiconductor in low power non volatile resistive switching memory and logic circuits.

A wavelet analysis of scaling laws and long-memory in stock market volatility

NASA Astrophysics Data System (ADS)

Vuorenmaa, Tommi A.

2005-05-01

This paper studies the time-varying behavior of scaling laws and long-memory. This is motivated by the earlier finding that in the FX markets a single scaling factor might not always be sufficient across all relevant timescales: a different region may exist for intradaily time-scales and for larger time-scales. In specific, this paper investigates (i) if different scaling regions appear in stock market as well, (ii) if the scaling factor systematically differs from the Brownian, (iii) if the scaling factor is constant in time, and (iv) if the behavior can be explained by the heterogenuity of the players in the market and/or by intraday volatility periodicity. Wavelet method is used because it delivers a multiresolution decomposition and has excellent local adaptiviness properties. As a consequence, a wavelet-based OLS method allows for consistent estimation of long-memory. Thus issues (i)-(iv) shed light on the magnitude and behavior of a long-memory parameter, as well. The data are the 5-minute volatility series of Nokia Oyj at the Helsinki Stock Exchange around the burst of the IT-bubble. Period one represents the era of "irrational exuberance" and another the time after it. The results show that different scaling regions (i.e. multiscaling) may appear in the stock markets and not only in the FX markets, the scaling factor and the long-memory parameter are systematically different from the Brownian and they do not have to be constant in time, and that the behavior can be explained for a significant part by an intraday volatility periodicity called the New York effect. This effect was magnified by the frenzy trading of short-term speculators in the bubble period. The found stronger long-memory is also attributable to irrational exuberance.

An assessment of memristor intrinsic fluctuations: a measurement of single atomic motion

NASA Astrophysics Data System (ADS)

Borghetti, Julien; Yang, J. Joshua; Medeiros-Ribeiro, Gilberto; Williams, R. Stanley

2010-03-01

Memristors provides electrically tunable resistance for upcoming non-volatile memory and future neuromorphic computing. One of the key benefits of such a device is its scalability, which can be demonstrated from an architectural perspective as well as from a fundamental physics limit. 4D addressing schemes utilizing cross bar structures that can be stacked several layers high above the chip embodies unlimited addressing space. On the other limit, the basic operating principles of memristive devices allow one to reach storage of information in a single atom. In this report of nanoscale (sub 50nm) devices, we detect single atom fluctuations, which would then represent the ultimate limit for noise sources thus delineating the boundary conditions for circuit design. We show that electrically induced individual atom migrations do not affect the overall device atomic configuration until a critical bias where a single local fluctuation triggers a general atomic reconfiguration. This instability illustrates the robustness of the device non-volatility upon small electrical stress.

EqualChance: Addressing Intra-set Write Variation to Increase Lifetime of Non-volatile Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S

To address the limitations of SRAM such as high-leakage and low-density, researchers have explored use of non-volatile memory (NVM) devices, such as ReRAM (resistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches. A crucial limitation of NVMs, however, is that their write endurance is low and the large intra-set write variation introduced by existing cache management policies may further exacerbate this problem, thereby reducing the cache lifetime significantly. We present EqualChance, a technique to increase cache lifetime by reducing intra-set write variation. EqualChance works by periodically changing the physical cache-block location of a write-intensive data item withinmore » a set to achieve wear-leveling. Simulations using workloads from SPEC CPU2006 suite and HPC (high-performance computing) field show that EqualChance improves the cache lifetime by 4.29X. Also, its implementation overhead is small, and it incurs very small performance and energy loss.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Juhee; Lee, Sungpyo; Lee, Moo Hyung

Quasi-unipolar non-volatile organic transistor memory (NOTM) can combine the best characteristics of conventional unipolar and ambipolar NOTMs and, as a result, exhibit improved device performance. Unipolar NOTMs typically exhibit a large signal ratio between the programmed and erased current signals but also require a large voltage to program and erase the memory cells. Meanwhile, an ambipolar NOTM can be programmed and erased at lower voltages, but the resulting signal ratio is small. By embedding a discontinuous n-type fullerene layer within a p-type pentacene film, quasi-unipolar NOTMs are fabricated, of which the signal storage utilizes both electrons and holes while themore » electrical signal relies on only hole conduction. These devices exhibit superior memory performance relative to both pristine unipolar pentacene devices and ambipolar fullerene/pentacene bilayer devices. The quasi-unipolar NOTM exhibited a larger signal ratio between the programmed and erased states while also reducing the voltage required to program and erase a memory cell. This simple approach should be readily applicable for various combinations of advanced organic semiconductors that have been recently developed and thereby should make a significant impact on organic memory research.« less

All oxide semiconductor-based bidirectional vertical p-n-p selectors for 3D stackable crossbar-array electronics

PubMed Central

Bae, Yoon Cheol; Lee, Ah Rahm; Baek, Gwang Ho; Chung, Je Bock; Kim, Tae Yoon; Park, Jea Gun; Hong, Jin Pyo

2015-01-01

Three-dimensional (3D) stackable memory devices including nano-scaled crossbar array are central for the realization of high-density non-volatile memory electronics. However, an essential sneak path issue affecting device performance in crossbar array remains a bottleneck and a grand challenge. Therefore, a suitable bidirectional selector as a two-way switch is required to facilitate a major breakthrough in the 3D crossbar array memory devices. Here, we show the excellent selectivity of all oxide p-/n-type semiconductor-based p-n-p open-based bipolar junction transistors as selectors in crossbar memory array. We report that bidirectional nonlinear characteristics of oxide p-n-p junctions can be highly enhanced by manipulating p-/n-type oxide semiconductor characteristics. We also propose an associated Zener tunneling mechanism that explains the unique features of our p-n-p selector. Our experimental findings are further extended to confirm the profound functionality of oxide p-n-p selectors integrated with several bipolar resistive switching memory elements working as storage nodes. PMID:26289565

Stochastic model of financial markets reproducing scaling and memory in volatility return intervals

NASA Astrophysics Data System (ADS)

Gontis, V.; Havlin, S.; Kononovicius, A.; Podobnik, B.; Stanley, H. E.

2016-11-01

We investigate the volatility return intervals in the NYSE and FOREX markets. We explain previous empirical findings using a model based on the interacting agent hypothesis instead of the widely-used efficient market hypothesis. We derive macroscopic equations based on the microscopic herding interactions of agents and find that they are able to reproduce various stylized facts of different markets and different assets with the same set of model parameters. We show that the power-law properties and the scaling of return intervals and other financial variables have a similar origin and could be a result of a general class of non-linear stochastic differential equations derived from a master equation of an agent system that is coupled by herding interactions. Specifically, we find that this approach enables us to recover the volatility return interval statistics as well as volatility probability and spectral densities for the NYSE and FOREX markets, for different assets, and for different time-scales. We find also that the historical S&P500 monthly series exhibits the same volatility return interval properties recovered by our proposed model. Our statistical results suggest that human herding is so strong that it persists even when other evolving fluctuations perturbate the financial system.

Organic bistable memory devices based on MoO3 nanoparticle embedded Alq3 structures.

PubMed

Abhijith, T; Kumar, T V Arun; Reddy, V S

2017-03-03

Organic bistable memory devices were fabricated by embedding a thin layer of molybdenum trioxide (MoO 3 ) between two tris-(8-hydroxyquinoline)aluminum (Alq 3 ) layers. The device exhibited excellent switching characteristics with an ON/OFF current ratio of 1.15 × 10 3 at a read voltage of 1 V. The device showed repeatable write-erase capability and good stability in both the conductance states. These conductance states are non-volatile in nature and can be obtained by applying appropriate voltage pulses. The effect of MoO 3 layer thickness and its location in the Alq 3 matrix on characteristics of the memory device was investigated. The field emission scanning electron microscopy (FE-SEM) images of the MoO 3 layer revealed the presence of isolated nanoparticles. Based on the experimental results, a mechanism has been proposed for explaining the conductance switching of fabricated devices.

Filamentary model in resistive switching materials

NASA Astrophysics Data System (ADS)

Jasmin, Alladin C.

2017-12-01

The need for next generation computer devices is increasing as the demand for efficient data processing increases. The amount of data generated every second also increases which requires large data storage devices. Oxide-based memory devices are being studied to explore new research frontiers thanks to modern advances in nanofabrication. Various oxide materials are studied as active layers for non-volatile memory. This technology has potential application in resistive random-access-memory (ReRAM) and can be easily integrated in CMOS technologies. The long term perspective of this research field is to develop devices which mimic how the brain processes information. To realize such application, a thorough understanding of the charge transport and switching mechanism is important. A new perspective in the multistate resistive switching based on current-induced filament dynamics will be discussed. A simple equivalent circuit of the device gives quantitative information about the nature of the conducting filament at different resistance states.

Adaptive microwave impedance memory effect in a ferromagnetic insulator.

PubMed

Lee, Hanju; Friedman, Barry; Lee, Kiejin

2016-12-14

Adaptive electronics, which are often referred to as memristive systems as they often rely on a memristor (memory resistor), are an emerging technology inspired by adaptive biological systems. Dissipative systems may provide a proper platform to implement an adaptive system due to its inherent adaptive property that parameters describing the system are optimized to maximize the entropy production for a given environment. Here, we report that a non-volatile and reversible adaptive microwave impedance memory device can be realized through the adaptive property of the dissipative structure of the driven ferromagnetic system. Like the memristive device, the microwave impedance of the device is modulated as a function of excitation microwave passing through the device. This kind of new device may not only helpful to implement adaptive information processing technologies, but also may be useful to investigate and understand the underlying mechanism of spontaneous formation of complex and ordered structures.

Organic bistable memory devices based on MoO3 nanoparticle embedded Alq3 structures

NASA Astrophysics Data System (ADS)

Abhijith, T.; Kumar, T. V. Arun; Reddy, V. S.

2017-03-01

Organic bistable memory devices were fabricated by embedding a thin layer of molybdenum trioxide (MoO3) between two tris-(8-hydroxyquinoline)aluminum (Alq3) layers. The device exhibited excellent switching characteristics with an ON/OFF current ratio of 1.15 × 103 at a read voltage of 1 V. The device showed repeatable write-erase capability and good stability in both the conductance states. These conductance states are non-volatile in nature and can be obtained by applying appropriate voltage pulses. The effect of MoO3 layer thickness and its location in the Alq3 matrix on characteristics of the memory device was investigated. The field emission scanning electron microscopy (FE-SEM) images of the MoO3 layer revealed the presence of isolated nanoparticles. Based on the experimental results, a mechanism has been proposed for explaining the conductance switching of fabricated devices.

Feasibility of self-structured current accessed bubble devices in spacecraft recording systems

NASA Technical Reports Server (NTRS)

Nelson, G. L.; Krahn, D. R.; Dean, R. H.; Paul, M. C.; Lo, D. S.; Amundsen, D. L.; Stein, G. A.

1985-01-01

The self-structured, current aperture approach to magnetic bubble memory is described. Key results include: (1) demonstration that self-structured bubbles (a lattice of strongly interacting bubbles) will slip by one another in a storage loop at spacings of 2.5 bubble diameters, (2) the ability of self-structured bubbles to move past international fabrication defects (missing apertures) in the propagation conductors (defeat tolerance), and (3) moving bubbles at mobility limited speeds. Milled barriers in the epitaxial garnet are discussed for containment of the bubble lattice. Experimental work on input/output tracks, storage loops, gates, generators, and magneto-resistive detectors for a prototype device are discussed. Potential final device architectures are described with modeling of power consumption, data rates, and access times. Appendices compare the self-structured bubble memory from the device and system perspectives with other non-volatile memory technologies.

Adaptive microwave impedance memory effect in a ferromagnetic insulator

PubMed Central

Lee, Hanju; Friedman, Barry; Lee, Kiejin

2016-01-01

Adaptive electronics, which are often referred to as memristive systems as they often rely on a memristor (memory resistor), are an emerging technology inspired by adaptive biological systems. Dissipative systems may provide a proper platform to implement an adaptive system due to its inherent adaptive property that parameters describing the system are optimized to maximize the entropy production for a given environment. Here, we report that a non-volatile and reversible adaptive microwave impedance memory device can be realized through the adaptive property of the dissipative structure of the driven ferromagnetic system. Like the memristive device, the microwave impedance of the device is modulated as a function of excitation microwave passing through the device. This kind of new device may not only helpful to implement adaptive information processing technologies, but also may be useful to investigate and understand the underlying mechanism of spontaneous formation of complex and ordered structures. PMID:27966536

External Verification of SCADA System Embedded Controller Firmware

DTIC Science & Technology

2012-03-01

microprocessor and read-only memory (ROM) or flash memory for storing firmware and control logic [5],[8]. A PLC typically has three software levels as shown in...implementing different firmware. Because PLCs are in effect a microprocessor device, an analysis of the current research on embedded devices is important...Electronics Engineers (IEEE) published a 15 best practices guide for firmware control on microprocessors [44]. IEEE suggests that microprocessors

Flash flood disasters analysis and evaluation: a case study of Yiyang County in China

NASA Astrophysics Data System (ADS)

Li, Haichen; Zhang, Xiaolei; Li, Qing; Qin, Tao; Lei, Xiaohui

2018-03-01

Global climate change leads to the more extreme precipitation and more flash flood disasters, which is a serious threat to the mountain inhabitants. To prevent flash flood disasters, China started flash flood disaster control planning and other projects from 2006. Among those measures, non-engineering measures are effective and economical. This paper introduced the framework of flash flood disaster analysis and evaluation in China, followed by a case study of Yiyang County.

77 FR 35718 - Certain Universal Serial Bus (“USB”) Portable Storage Devices, Including USB Flash Drives and...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-14

... on the Commission's electronic docket (EDIS) at http://edis.usitc.gov . Hearing-impaired persons are... Sunnyvale, California; Kingston Technology Company, Inc. of Fountain Valley, California; Patriot Memory, LLC...

Total ionizing dose effect in an input/output device for flash memory

NASA Astrophysics Data System (ADS)

Liu, Zhang-Li; Hu, Zhi-Yuan; Zhang, Zheng-Xuan; Shao, Hua; Chen, Ming; Bi, Da-Wei; Ning, Bing-Xu; Zou, Shi-Chang

2011-12-01

Input/output devices for flash memory are exposed to gamma ray irradiation. Total ionizing dose has been shown great influence on characteristic degradation of transistors with different sizes. In this paper, we observed a larger increase of off-state leakage in the short channel device than in long one. However, a larger threshold voltage shift is observed for the narrow width device than for the wide one, which is well known as the radiation induced narrow channel effect. The radiation induced charge in the shallow trench isolation oxide influences the electric field of the narrow channel device. Also, the drain bias dependence of the off-state leakage after irradiation is observed, which is called the radiation enhanced drain induced barrier lowing effect. Finally, we found that substrate bias voltage can suppress the off-state leakage, while leading to more obvious hump effect.

A microcomputer-based daily living activity recording system.

PubMed

Matsuoka, Shingo; Yonezawa, Yoshiharu; Maki, Hiromichi; Ogawa, Hidekuni; Hahn, Allen W; Thayer, Julian F; Caldwell, W Morton

2003-01-01

A new daily living activity recording system has been developed for monitoring health conditions and living patterns, such as respiration, posture, activity/rest ratios and general activity level. The system employs a piezoelectric sensor, a dual axis accelerometer, two low-power active filters, a low-power 8-bit single chip microcomputer and a 128 MB compact flash memory. The piezoelectric sensor, whose electrical polarization voltage is produced by mechanical strain, detects body movements. Its high-frequency output components reflect body movements produced by walking and running activities, while the low frequency components are mainly respiratory. The dual axis accelerometer detects, from body X and Y tilt angles, whether the patient is standing, sitting or lying down (prone, supine, left side or right side). The detected respiratory, behavior and posture signals are stored by the compact flash memory. After recording, these data are downloaded to a desktop computer and analyzed.

Analysis of the Evaluation of a New Glucose Meter with Integrated Self-Management Software and USB Connectivity

PubMed Central

Crowe, Daniel J

2011-01-01

Glucose meter technology has not kept up with the advances that have occurred in other sectors in mobile and health care technology. A new device that combines strip-based capillary blood glucose monitoring and USB flash drive technology is evaluated in an industry-funded study in a cohort of patients and health care professionals. The expanded memory capacity of flash drives allows the software program to be stored on the device for analyzing the blood glucose readings in memory. The study analyzes the device for precision and accuracy as well as for ease of adaptability and usage. This analysis focuses on shortcomings in the design of the study and methodology in addition to features of the hardware device itself. Although the device has distinct advantages over many devices on the market, a challenge is made to device manufacturers to encourage further innovation. PMID:22027309

Mistaking the recent past for the present: false seeing by older adults.

PubMed

Jacoby, Larry L; Rogers, Chad S; Bishara, Anthony J; Shimizu, Yujiro

2012-03-01

Results of three experiments revealed that older, as compared to young, adults are more reliant on context when "seeing" a briefly flashed word that was preceded by a prime. In a congruent condition, the prime was the same word as flashed (e.g., DIRT dirt) whereas in an incongruent condition, the prime differed in a single letter from the word that was flashed (DART dirt). Following their attempt to identify the flashed word, participants were asked to report whether they had "seen" the flashed word or, instead, had responded on some other basis (knowing or guessing). Older adults showed dramatically higher false seeing by reporting the prime on incongruent trials and claiming to have seen it flashed. This was true even though a titration procedure was used to equate the performance of young and older adults on baseline trials which did not provide a biasing context. Results of Experiment 3 related age differences in false seeing to willingness to respond when given the option to withhold responses. Convergence of results with those showing higher false memory and false hearing are interpreted as evidence that older adults are less able to avoid misleading effects of context. That lessened ability may be associated with decline in frontal lobe functioning.

Nonpolar resistive memory switching with all four possible resistive switching modes in amorphous LaHoO{sub 3} thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sharma, Yogesh; Pavunny, Shojan P.; Katiyar, Ram S., E-mail: rkatiyar@hpcf.upr.edu

2015-09-07

We studied the resistive memory switching in pulsed laser deposited amorphous LaHoO{sub 3} (a-LHO) thin films for non-volatile resistive random access memory applications. Nonpolar resistive switching (RS) was achieved in Pt/a-LHO/Pt memory cells with all four possible RS modes (i.e., positive unipolar, positive bipolar, negative unipolar, and negative bipolar) having high R{sub ON}/R{sub OFF} ratios (in the range of ∼10{sup 4}–10{sup 5}) and non-overlapping switching voltages (set voltage, V{sub ON} ∼ ±3.6–4.2 V and reset voltage, V{sub OFF} ∼ ±1.3–1.6 V) with a small variation of about ±5–8%. Temperature dependent current-voltage (I–V) characteristics indicated the metallic conduction in low resistance states (LRS). We believe that themore » formation (set) and rupture (reset) of mixed conducting filaments formed out of oxygen vacancies and metallic Ho atoms could be responsible for the change in the resistance states of the memory cell. Detailed analysis of I–V characteristics further corroborated the formation of conductive nanofilaments based on metal-like (Ohmic) conduction in LRS. Simmons-Schottky emission was found to be the dominant charge transport mechanism in the high resistance state.« less

Development and characterization of a ferroelectric non-volatile memory for flexible electronics

NASA Astrophysics Data System (ADS)

Mao, Duo

Flexible electronics have received significant attention recently because of the potential applications in displays, sensors, radio frequency identification (RFID) tags and other integrated circuits. Electrically addressable non-volatile memory is a key component for these applications. The major challenges are to fabricate the memory at a low temperature compatible with plastic substrates while maintaining good device reliability, by being compatible with process as needed to integrate with other electronic components for system-on-chip applications. In this work, ferroelectric capacitors fabricated at low temperature were developed. Based on that, a ferroelectric random access memory (FRAM) for flexible electronics was developed and characterized. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] copolymer was used as a ferroelectric material and a photolithographic process was developed to fabricate ferroelectric capacitors. Different characterization methods including atomic force microscopy, x-ray diffraction and Fourier-transform infrared reflection-absorption spectroscopy were used to study the material properties of the P(VDF-TrFE) film. The material properties were correlated with the electrical characteristics of the ferroelectric capacitors. To understand the polarization switching behavior of the P(VDF-TrFE) ferroelectric capacitors, a Nucleation-Limited-Switching (NLS) model was used to study the switching kinetics. The switching kinetics were characterized over the temperature range from -60 °C to 100 °C. Fatigue characteristics were studied at different electrical stress voltages and frequencies to evaluate the reliability of the ferroelectric capacitor. The degradation mechanism is attributed to the increase of the activation field and the suppression of the switchable polarization. To develop a FRAM circuit for flexible electronics, an n-channel thin film transistor (TFT) based on CdS as the semiconductor was integrated with a P(VDF-TrFE) ferroelectric capacitor for a one-transistor-one-capacitor (1T1C) memory cell. The 1T1C devices were fabricated at low temperature and demonstrated a memory window (DeltaVBL) of 2.3 V and 3.5 V, depending on the device dimensions. Next, FRAM arrays (4-bit, 16-bit and 64-bit) based on the two-transistor-two-capacitor (2T2C) memory cell architecture were designed and fabricated using a photolithographic process with 9 masks. The fabricated FRAM arrays were packaged in 28-pin ceramic packages. The read/write schemes were developed and the FRAM arrays show successful program and erase with a memory window of approximately 1 V at the output of the sense amplifier.

A complementary switching mechanism for organic memory devices to regulate the conductance of binary states

NASA Astrophysics Data System (ADS)

Vyas, Giriraj; Dagar, Parveen; Sahu, Satyajit

2016-06-01

We have fabricated an organic non-volatile memory device wherein the ON/OFF current ratio has been controlled by varying the concentration of a small organic molecule, 2,3-Dichloro-5,6-dicyano-p-benzoquinone (DDQ), in an insulating matrix of a polymer Poly(4-vinylphenol) (PVP). A maximum ON-OFF ratio of 106 is obtained when the concentration of DDQ is half or 10 wt. % of PVP. In this process, the switching direction for the devices has also been altered, indicating the disparity in conduction mechanism. Conduction due to metal filament formation through the active material and the voltage dependent conformational change of the organic molecule seem to be the motivation behind the gradual change in the switching direction.

Tamper indicating bolt

DOEpatents

Blagin, Sergei V.; Barkanov, Boris P.

2004-09-14

A tamper-indicating fastener has a cylindrical body with threads extending from one end along a portion of the body, and a tamper indicating having a transducer for converting physical properties of the body into electronic data; electronics for recording the electronic data; and means for communicating the recorded information to a remote location from said fastener. The electronics includes a capacitor that varies as a function of force applied by the fastener, and non-volatile memory for recording instances when the capacitance varies, providing an indication of unauthorized access.

A Study on Reactive Ion Etching of Barium Strontium Titanate Films Using Mixtures of Argon (Ar), Carbon Tetrafluoride (CF4), and Sulfur Hexafluoride (SF6)

DTIC Science & Technology

2014-07-01

BST) is a complex oxide material with ferroic properties which has been considered for applications ranging from non-volatile memory to microwave...utilizing self-aligned etching to create metal-insulator-metal (MIM) varactors . As part of this method we employed reactive ion etching (RIE) to remove BST...of BST removed vs. etch time for Ar:SF6. .........................................................4 Figure 3. SEM cross-section of varactor showing

Reconfigurable Electronics and Non-Volatile Memory Research

DTIC Science & Technology

2011-10-14

Sources of metal dopants were elemental metals and as well as, metal-Se compounds, and there was no evident difference in the measured Raman and Electron...similar in nature. Intensity of the most of the sample reduces with dopant concentration. This is due to the reduction in Ge-Ge and Ge-Se bonds as...the metal is incorporated into the glass. The metal dopant atoms will bond with the Se atoms [5] reducing the number of Se atoms that are available

Selected Thermophysical Properties of 2,2 Dimethylcyclopentyl Methylphosphonofluoridate (GP) and 2,2 Dimethylcyclopentanol (DMCP)

DTIC Science & Technology

2016-09-01

Thermophysical properties, including vapor pressure, density, viscosity, surface tension, and flash point, are reported for 2,2-dimethylcyclopentyl...methylphosphonofluoridate (GP; Chemical Abstracts Service [CAS] no. 453574-97-5). Density data above the melting point, and vapor pressure of the liquid and solid...experimental vapor pressure data and were used to calculate the temperature-dependent enthalpy of vaporization , volatility, and entropy of

A wavelet-based evaluation of time-varying long memory of equity markets: A paradigm in crisis

NASA Astrophysics Data System (ADS)

Tan, Pei P.; Chin, Cheong W.; Galagedera, Don U. A.

2014-09-01

This study, using wavelet-based method investigates the dynamics of long memory in the returns and volatility of equity markets. In the sample of five developed and five emerging markets we find that the daily return series from January 1988 to June 2013 may be considered as a mix of weak long memory and mean-reverting processes. In the case of volatility in the returns, there is evidence of long memory, which is stronger in emerging markets than in developed markets. We find that although the long memory parameter may vary during crisis periods (1997 Asian financial crisis, 2001 US recession and 2008 subprime crisis) the direction of change may not be consistent across all equity markets. The degree of return predictability is likely to diminish during crisis periods. Robustness of the results is checked with de-trended fluctuation analysis approach.

Cost aware cache replacement policy in shared last-level cache for hybrid memory based fog computing

NASA Astrophysics Data System (ADS)

Jia, Gangyong; Han, Guangjie; Wang, Hao; Wang, Feng

2018-04-01

Fog computing requires a large main memory capacity to decrease latency and increase the Quality of Service (QoS). However, dynamic random access memory (DRAM), the commonly used random access memory, cannot be included into a fog computing system due to its high consumption of power. In recent years, non-volatile memories (NVM) such as Phase-Change Memory (PCM) and Spin-transfer torque RAM (STT-RAM) with their low power consumption have emerged to replace DRAM. Moreover, the currently proposed hybrid main memory, consisting of both DRAM and NVM, have shown promising advantages in terms of scalability and power consumption. However, the drawbacks of NVM, such as long read/write latency give rise to potential problems leading to asymmetric cache misses in the hybrid main memory. Current last level cache (LLC) policies are based on the unified miss cost, and result in poor performance in LLC and add to the cost of using NVM. In order to minimize the cache miss cost in the hybrid main memory, we propose a cost aware cache replacement policy (CACRP) that reduces the number of cache misses from NVM and improves the cache performance for a hybrid memory system. Experimental results show that our CACRP behaves better in LLC performance, improving performance up to 43.6% (15.5% on average) compared to LRU.

Active Flash: Out-of-core Data Analytics on Flash Storage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Boboila, Simona; Kim, Youngjae; Vazhkudai, Sudharshan S

2012-01-01

Next generation science will increasingly come to rely on the ability to perform efficient, on-the-fly analytics of data generated by high-performance computing (HPC) simulations, modeling complex physical phenomena. Scientific computing workflows are stymied by the traditional chaining of simulation and data analysis, creating multiple rounds of redundant reads and writes to the storage system, which grows in cost with the ever-increasing gap between compute and storage speeds in HPC clusters. Recent HPC acquisitions have introduced compute node-local flash storage as a means to alleviate this I/O bottleneck. We propose a novel approach, Active Flash, to expedite data analysis pipelines bymore » migrating to the location of the data, the flash device itself. We argue that Active Flash has the potential to enable true out-of-core data analytics by freeing up both the compute core and the associated main memory. By performing analysis locally, dependence on limited bandwidth to a central storage system is reduced, while allowing this analysis to proceed in parallel with the main application. In addition, offloading work from the host to the more power-efficient controller reduces peak system power usage, which is already in the megawatt range and poses a major barrier to HPC system scalability. We propose an architecture for Active Flash, explore energy and performance trade-offs in moving computation from host to storage, demonstrate the ability of appropriate embedded controllers to perform data analysis and reduction tasks at speeds sufficient for this application, and present a simulation study of Active Flash scheduling policies. These results show the viability of the Active Flash model, and its capability to potentially have a transformative impact on scientific data analysis.« less

[Research on improving memory impairment of blue lavender volatile oil].

PubMed

Zhu, Li-Yun; Gao, Yong-Sheng; Song, Lin-Zhen; Li, Su-Fang; Qian, Jun-Qing

2017-12-01

In order to study the potential application value of lavender volatile oil (LVO), the chemical composition of the volatile oil of lavender was analyzed by GC-MS, and the mouse model of Alzheimer's disease (AD) was established. Additionally, the antioxidant enzymes activity of T-SOD, GSH-PX, CAT and MDA content were studied. Experimental results showed that 55 kinds of chemical constituents including terpene, terpene alcohol and ester compounds from LVO were identified, and the content of linalool and linalyl acetate was the highest, accounting for 49.71% of the total volatile oil. The ability of mouse platform memory was improved significantly. The levels of GSH-PX, CAT and T-SOD of mouse brain tissue in the treatment group were significantly higher than those in the model group (P<0.05). The level of MDA reached the maximum value in the model group, while there was no notable difference between the levels of MDA in the drug group and the normal group. The result indicated the significant oxidative activity of LVO, the possibility of induced oxidative stress reduction in neurons, and the reversal effect of memory acquired disorder. Copyright© by the Chinese Pharmaceutical Association.

Development of template and mask replication using jet and flash imprint lithography

NASA Astrophysics Data System (ADS)

Brooks, Cynthia; Selinidis, Kosta; Doyle, Gary; Brown, Laura; LaBrake, Dwayne; Resnick, Douglas J.; Sreenivasan, S. V.

2010-09-01

The Jet and Flash Imprint Lithography (J-FILTM)1-7 process uses drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for memory markets including Flash memory and patterned media for hard disk drives. It is anticipated that the lifetime of a single template (for patterned media) or mask (for semiconductor) will be on the order of 104 - 105 imprints. This suggests that tens of thousands of templates/masks will be required. It is not feasible to employ electronbeam patterning directly to deliver these volumes. Instead, a "master" template - created by directly patterning with an electron-beam tool - will be replicated many times with an imprint lithography tool to produce the required supply of "working" templates/masks. In this paper, we review the development of the pattern transfer process for both template and mask replicas. Pattern transfer of resolutions down to 25nm has been demonstrated for bit patterned media replication. In addition, final resolution on a semiconductor mask of 28nm has been confirmed. The early results on both etch depth and CD uniformity are promising, but more extensive work is required to characterize the pattern transfer process.

Long memory of abnormal investor attention and the cross-correlations between abnormal investor attention and trading volume, volatility respectively

NASA Astrophysics Data System (ADS)

Fan, Xiaoqian; Yuan, Ying; Zhuang, Xintian; Jin, Xiu

2017-03-01

Taking Baidu Index as a proxy for abnormal investor attention (AIA), the long memory property in the AIA of Shanghai Stock Exchange (SSE) 50 Index component stocks was empirically investigated using detrended fluctuation analysis (DFA) method. The results show that abnormal investor attention is power-law correlated with Hurst exponents between 0.64 and 0.98. Furthermore, the cross-correlations between abnormal investor attention and trading volume, volatility respectively are studied using detrended cross-correlation analysis (DCCA) and the DCCA cross-correlation coefficient (ρDCCA). The results suggest that there are positive correlations between AIA and trading volume, volatility respectively. In addition, the correlations for trading volume are in general higher than the ones for volatility. By carrying on rescaled range analysis (R/S) and rolling windows analysis, we find that the results mentioned above are effective and significant.

Low-voltage all-inorganic perovskite quantum dot transistor memory

NASA Astrophysics Data System (ADS)

Chen, Zhiliang; Zhang, Yating; Zhang, Heng; Yu, Yu; Song, Xiaoxian; Zhang, Haiting; Cao, Mingxuan; Che, Yongli; Jin, Lufan; Li, Yifan; Li, Qingyan; Dai, Haitao; Yang, Junbo; Yao, Jianquan

2018-05-01

An all-inorganic cesium lead halide quantum dot (QD) based Au nanoparticle (NP) floating-gate memory with a solution processed layer-by-layer method is demonstrated. Easy synthesis at room temperature and excellent stability make all-inorganic CsPbBr3 perovskite QDs suitable as a semiconductor layer in low voltage nonvolatile transistor memory. The bipolarity of QDs has both electrons and holes stored in the Au NP floating gate, resulting in bidirectional shifts of initial threshold voltage according to the applied programing and erasing pulses. Under low operation voltage (±5 V), the memory achieved a great memory window (˜2.4 V), long retention time (>105 s), and stable endurance properties after 200 cycles. So the proposed memory device based on CsPbBr3 perovskite QDs has a great potential in the flash memory market.

Adaptive P300 based control system

PubMed Central

Jin, Jing; Allison, Brendan Z.; Sellers, Eric W.; Brunner, Clemens; Horki, Petar; Wang, Xingyu; Neuper, Christa

2015-01-01

An adaptive P300 brain-computer interface (BCI) using a 12 × 7 matrix explored new paradigms to improve bit rate and accuracy. During online use, the system adaptively selects the number of flashes to average. Five different flash patterns were tested. The 19-flash paradigm represents the typical row/column presentation (i.e., 12 columns and 7 rows). The 9- and 14-flash A & B paradigms present all items of the 12 × 7 matrix three times using either nine or 14 flashes (instead of 19), decreasing the amount of time to present stimuli. Compared to 9-flash A, 9-flash B decreased the likelihood that neighboring items would flash when the target was not flashing, thereby reducing interference from items adjacent to targets. 14-flash A also reduced adjacent item interference and 14-flash B additionally eliminated successive (double) flashes of the same item. Results showed that accuracy and bit rate of the adaptive system were higher than the non-adaptive system. In addition, 9- and 14-flash B produced significantly higher performance than their respective A conditions. The results also show the trend that the 14-flash B paradigm was better than the 19-flash pattern for naïve users. PMID:21474877

Out of sight but not out of mind: the neurophysiology of iconic memory in the superior temporal sulcus.

PubMed

Keysers, C; Xiao, D-K; Foldiak, P; Perrett, D I

2005-05-01

Iconic memory, the short-lasting visual memory of a briefly flashed stimulus, is an important component of most models of visual perception. Here we investigate what physiological mechanisms underlie this capacity by showing rapid serial visual presentation (RSVP) sequences with and without interstimulus gaps to human observers and macaque monkeys. For gaps of up to 93 ms between consecutive images, human observers and neurones in the temporal cortex of macaque monkeys were found to continue processing a stimulus as if it was still present on the screen. The continued firing of neurones in temporal cortex may therefore underlie iconic memory. Based on these findings, a neurophysiological vision of iconic memory is presented.

Non-destructive reversible resistive switching in Cr doped Mott insulator Ca2RuO4: Interface vs bulk effects

NASA Astrophysics Data System (ADS)

Shen, Shida; Williamson, Morgan; Cao, Gang; Zhou, Jianshi; Goodenough, John; Tsoi, Maxim

2017-12-01

A non-destructive reversible resistive switching is demonstrated in single crystals of Cr-doped Mott insulator Ca2RuO4. An applied electrical bias was shown to reduce the DC resistance of the crystal by as much as 75%. The original resistance of the sample could be restored by applying an electrical bias of opposite polarity. We have studied this resistive switching as a function of the bias strength, applied magnetic field, and temperature. A combination of 2-, 3-, and 4-probe measurements provide a means to distinguish between bulk and interfacial contributions to the switching and suggests that the switching is mostly an interfacial effect. The switching was tentatively attributed to electric-field driven lattice distortions which accompany the impurity-induced Mott transition. This field effect was confirmed by temperature-dependent resistivity measurements which show that the activation energy of this material can be tuned by an applied DC electrical bias. The observed resistance switching can potentially be used for building non-volatile memory devices like resistive random access memory.

An Assessment of Land Surface and Lightning Characteristics Associated with Lightning-Initiated Wildfires

NASA Technical Reports Server (NTRS)

Coy, James; Schultz, Christopher J.; Case, Jonathan L.

2017-01-01

Can we use modeled information of the land surface and characteristics of lightning beyond flash occurrence to increase the identification and prediction of wildfires? Combine observed cloud-to-ground (CG) flashes with real-time land surface model output, and Compare data with areas where lightning did not start a wildfire to determine what land surface conditions and lightning characteristics were responsible for causing wildfires. Statistical differences between suspected fire-starters and non-fire-starters were peak-current dependent 0-10 cm Volumetric and Relative Soil Moisture comparisons were statistically dependent to at least the p = 0.05 independence level for both polarity flash types Suspected fire-starters typically occurred in areas of lower soil moisture than non-fire-starters. GVF value comparisons were only found to be statistically dependent for -CG flashes. However, random sampling of the -CG non-fire starter dataset revealed that this relationship may not always hold.

Non-invasive online wavelength measurements at FLASH2 and present benchmark

PubMed Central

Braune, Markus; Buck, Jens; Kuhlmann, Marion; Grunewald, Sören; Düsterer, Stefan; Viefhaus, Jens; Tiedtke, Kai

2018-01-01

At FLASH2, the free-electron laser radiation wavelength is routinely measured by an online spectrometer based on photoionization of gas targets. Photoelectrons are detected with time-of-flight spectrometers and the wavelength is determined by means of well known binding energies of the target species. The wavelength measurement is non-invasive and transparent with respect to running user experiments due to the low gas pressure applied. Sophisticated controls for setting the OPIS operation parameters have been created and integrated into the distributed object-oriented control system at FLASH2. Raw and processed data can be stored on request in the FLASH data acquisition system for later correlation with data from user experiments or re-analysis. In this paper, the commissioning of the instrument at FLASH2 and the challenges of space charge effects on wavelength determination are reported. Furthermore, strategies for fast data reduction and online data processing are presented. PMID:29271744

FLASH Interface; a GUI for managing runtime parameters in FLASH simulations

NASA Astrophysics Data System (ADS)

Walker, Christopher; Tzeferacos, Petros; Weide, Klaus; Lamb, Donald; Flocke, Norbert; Feister, Scott

2017-10-01

We present FLASH Interface, a novel graphical user interface (GUI) for managing runtime parameters in simulations performed with the FLASH code. FLASH Interface supports full text search of available parameters; provides descriptions of each parameter's role and function; allows for the filtering of parameters based on categories; performs input validation; and maintains all comments and non-parameter information already present in existing parameter files. The GUI can be used to edit existing parameter files or generate new ones. FLASH Interface is open source and was implemented with the Electron framework, making it available on Mac OSX, Windows, and Linux operating systems. The new interface lowers the entry barrier for new FLASH users and provides an easy-to-use tool for experienced FLASH simulators. U.S. Department of Energy (DOE), NNSA ASC/Alliances Center for Astrophysical Thermonuclear Flashes, U.S. DOE NNSA ASC through the Argonne Institute for Computing in Science, U.S. National Science Foundation.

Computer Game Play Reduces Intrusive Memories of Experimental Trauma via Reconsolidation-Update Mechanisms.

PubMed

James, Ella L; Bonsall, Michael B; Hoppitt, Laura; Tunbridge, Elizabeth M; Geddes, John R; Milton, Amy L; Holmes, Emily A

2015-08-01

Memory of a traumatic event becomes consolidated within hours. Intrusive memories can then flash back repeatedly into the mind's eye and cause distress. We investigated whether reconsolidation-the process during which memories become malleable when recalled-can be blocked using a cognitive task and whether such an approach can reduce these unbidden intrusions. We predicted that reconsolidation of a reactivated visual memory of experimental trauma could be disrupted by engaging in a visuospatial task that would compete for visual working memory resources. We showed that intrusive memories were virtually abolished by playing the computer game Tetris following a memory-reactivation task 24 hr after initial exposure to experimental trauma. Furthermore, both memory reactivation and playing Tetris were required to reduce subsequent intrusions (Experiment 2), consistent with reconsolidation-update mechanisms. A simple, noninvasive cognitive-task procedure administered after emotional memory has already consolidated (i.e., > 24 hours after exposure to experimental trauma) may prevent the recurrence of intrusive memories of those emotional events. © The Author(s) 2015.

Computer Game Play Reduces Intrusive Memories of Experimental Trauma via Reconsolidation-Update Mechanisms

PubMed Central

James, Ella L.; Bonsall, Michael B.; Hoppitt, Laura; Tunbridge, Elizabeth M.; Geddes, John R.; Milton, Amy L.

2015-01-01

Memory of a traumatic event becomes consolidated within hours. Intrusive memories can then flash back repeatedly into the mind’s eye and cause distress. We investigated whether reconsolidation—the process during which memories become malleable when recalled—can be blocked using a cognitive task and whether such an approach can reduce these unbidden intrusions. We predicted that reconsolidation of a reactivated visual memory of experimental trauma could be disrupted by engaging in a visuospatial task that would compete for visual working memory resources. We showed that intrusive memories were virtually abolished by playing the computer game Tetris following a memory-reactivation task 24 hr after initial exposure to experimental trauma. Furthermore, both memory reactivation and playing Tetris were required to reduce subsequent intrusions (Experiment 2), consistent with reconsolidation-update mechanisms. A simple, noninvasive cognitive-task procedure administered after emotional memory has already consolidated (i.e., > 24 hours after exposure to experimental trauma) may prevent the recurrence of intrusive memories of those emotional events. PMID:26133572

Onset conditions for flash sintering of UO 2

DOE PAGES

Raftery, Alicia M.; Pereira da Silva, João Gustavo; Byler, Darrin D.; ...

2017-06-22

In this paper, flash sintering was demonstrated on stoichiometric and non-stoichiometric uranium dioxide pellets at temperatures ranging from room temperature (26°C) up to 600°C. The onset conditions for flash sintering were determined for three stoichiometries (UO 2.00, UO 2.08, and UO 2.16) and analyzed against an established thermal runaway model. The presence of excess oxygen was found to enhance the flash sintering onset behavior of uranium dioxide, lowering the field required to flash and shortening the time required for a flash to occur. Finally, the results from this study highlight the effect of stoichiometry on the flash sintering behavior ofmore » uranium dioxide and will serve as the foundation for future studies on this material.« less

Onset conditions for flash sintering of UO2

NASA Astrophysics Data System (ADS)

Raftery, Alicia M.; Pereira da Silva, João Gustavo; Byler, Darrin D.; Andersson, David A.; Uberuaga, Blas P.; Stanek, Christopher R.; McClellan, Kenneth J.

2017-09-01

In this work, flash sintering was demonstrated on stoichiometric and non-stoichiometric uranium dioxide pellets at temperatures ranging from room temperature (26 °C) up to 600 °C . The onset conditions for flash sintering were determined for three stoichiometries (UO2.00, UO2.08, and UO2.16) and analyzed against an established thermal runaway model. The presence of excess oxygen was found to enhance the flash sintering onset behavior of uranium dioxide, lowering the field required to flash and shortening the time required for a flash to occur. The results from this study highlight the effect of stoichiometry on the flash sintering behavior of uranium dioxide and will serve as the foundation for future studies on this material.

Vegetable Oils as Alternative Solvents for Green Oleo-Extraction, Purification and Formulation of Food and Natural Products.

PubMed

Yara-Varón, Edinson; Li, Ying; Balcells, Mercè; Canela-Garayoa, Ramon; Fabiano-Tixier, Anne-Sylvie; Chemat, Farid

2017-09-05

Since solvents of petroleum origin are now strictly regulated worldwide, there is a growing demand for using greener, bio-based and renewable solvents for extraction, purification and formulation of natural and food products. The ideal alternative solvents are non-volatile organic compounds (VOCs) that have high dissolving power and flash point, together with low toxicity and less environmental impact. They should be obtained from renewable resources at a reasonable price and be easy to recycle. Based on the principles of Green Chemistry and Green Engineering, vegetable oils could become an ideal alternative solvent to extract compounds for purification, enrichment, or even pollution remediation. This review presents an overview of vegetable oils as solvents enriched with various bioactive compounds from natural resources, as well as the relationship between dissolving power of non-polar and polar bioactive components with the function of fatty acids and/or lipid classes in vegetable oils, and other minor components. A focus on simulation of solvent-solute interactions and a discussion of polar paradox theory propose a mechanism explaining the phenomena of dissolving polar and non-polar bioactive components in vegetable oils as green solvents with variable polarity.

Mechanical memory

DOEpatents

Gilkey, Jeffrey C [Albuquerque, NM; Duesterhaus, Michelle A [Albuquerque, NM; Peter, Frank J [Albuquerque, NM; Renn, Rosemarie A [Alburquerque, NM; Baker, Michael S [Albuquerque, NM

2006-08-15

A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of memory cells, with each memory cell having a beam which can be bowed in either of two directions of curvature to indicate two different logic states for that memory cell. The memory cells can be arranged around a wheel which operates as a clocking actuator to serially shift data from one memory cell to the next. The mechanical memory can be formed using conventional surface micromachining, and can be formed as either a nonvolatile memory or as a volatile memory.

Mechanical memory

DOEpatents

Gilkey, Jeffrey C [Albuquerque, NM; Duesterhaus, Michelle A [Albuquerque, NM; Peter, Frank J [Albuquerque, NM; Renn, Rosemarie A [Albuquerque, NM; Baker, Michael S [Albuquerque, NM

2006-05-16

A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of memory cells, with each memory cell having a beam which can be bowed in either of two directions of curvature to indicate two different logic states for that memory cell. The memory cells can be arranged around a wheel which operates as a clocking actuator to serially shift data from one memory cell to the next. The mechanical memory can be formed using conventional surface micromachining, and can be formed as either a nonvolatile memory or as a volatile memory.

Announcing Supercomputer Summit

ScienceCinema

Wells, Jack; Bland, Buddy; Nichols, Jeff; Hack, Jim; Foertter, Fernanda; Hagen, Gaute; Maier, Thomas; Ashfaq, Moetasim; Messer, Bronson; Parete-Koon, Suzanne

2018-01-16

Summit is the next leap in leadership-class computing systems for open science. With Summit we will be able to address, with greater complexity and higher fidelity, questions concerning who we are, our place on earth, and in our universe. Summit will deliver more than five times the computational performance of Titan’s 18,688 nodes, using only approximately 3,400 nodes when it arrives in 2017. Like Titan, Summit will have a hybrid architecture, and each node will contain multiple IBM POWER9 CPUs and NVIDIA Volta GPUs all connected together with NVIDIA’s high-speed NVLink. Each node will have over half a terabyte of coherent memory (high bandwidth memory + DDR4) addressable by all CPUs and GPUs plus 800GB of non-volatile RAM that can be used as a burst buffer or as extended memory. To provide a high rate of I/O throughput, the nodes will be connected in a non-blocking fat-tree using a dual-rail Mellanox EDR InfiniBand interconnect. Upon completion, Summit will allow researchers in all fields of science unprecedented access to solving some of the world’s most pressing challenges.

Does long-term object priming depend on the explicit detection of object identity at encoding?

PubMed Central

Gomes, Carlos A.; Mayes, Andrew

2015-01-01

It is currently unclear whether objects have to be explicitly identified at encoding for reliable behavioral long-term object priming to occur. We conducted two experiments that investigated long-term object and non-object priming using a selective-attention encoding manipulation that reduces explicit object identification. In Experiment 1, participants either counted dots flashed within an object picture (shallow encoding) or engaged in an animacy task (deep encoding) at study, whereas, at test, they performed an object-decision task. Priming, as measured by reaction times (RTs), was observed for both types of encoding, and was of equivalent magnitude. In Experiment 2, non-object priming (faster RTs for studied relative to unstudied non-objects) was also obtained under the same selective-attention encoding manipulation as in Experiment 1, and the magnitude of the priming effect was equivalent between experiments. In contrast, we observed a linear decrement in recognition memory accuracy across conditions (deep encoding of Experiment 1 > shallow encoding Experiment 1 > shallow encoding of Experiment 2), suggesting that priming was not contaminated by explicit memory strategies. We argue that our results are more consistent with the identification/production framework than the perceptual/conceptual distinction, and we conclude that priming of pictures largely ignored at encoding can be subserved by the automatic retrieval of two types of instances: one at the motor level and another at an object-decision level. PMID:25852594

Copper atomic-scale transistors.

PubMed

Xie, Fangqing; Kavalenka, Maryna N; Röger, Moritz; Albrecht, Daniel; Hölscher, Hendrik; Leuthold, Jürgen; Schimmel, Thomas

2017-01-01

We investigated copper as a working material for metallic atomic-scale transistors and confirmed that copper atomic-scale transistors can be fabricated and operated electrochemically in a copper electrolyte (CuSO 4 + H 2 SO 4 ) in bi-distilled water under ambient conditions with three microelectrodes (source, drain and gate). The electrochemical switching-on potential of the atomic-scale transistor is below 350 mV, and the switching-off potential is between 0 and -170 mV. The switching-on current is above 1 μA, which is compatible with semiconductor transistor devices. Both sign and amplitude of the voltage applied across the source and drain electrodes ( U bias ) influence the switching rate of the transistor and the copper deposition on the electrodes, and correspondingly shift the electrochemical operation potential. The copper atomic-scale transistors can be switched using a function generator without a computer-controlled feedback switching mechanism. The copper atomic-scale transistors, with only one or two atoms at the narrowest constriction, were realized to switch between 0 and 1 G 0 ( G 0 = 2e 2 /h; with e being the electron charge, and h being Planck's constant) or 2 G 0 by the function generator. The switching rate can reach up to 10 Hz. The copper atomic-scale transistor demonstrates volatile/non-volatile dual functionalities. Such an optimal merging of the logic with memory may open a perspective for processor-in-memory and logic-in-memory architectures, using copper as an alternative working material besides silver for fully metallic atomic-scale transistors.

Development of non-volatile semiconductor memory

NASA Technical Reports Server (NTRS)

Heikkila, W. W.

1979-01-01

A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

83 FR 22712 - Certain Non-Volatile Memory Devices and Products Containing the Same; Notice of Request for...

Federal Register 2010, 2011, 2012, 2013, 2014

2018-05-16

...Notice is hereby given that the presiding administrative law judge has issued a Final Initial Determination and Recommended Determination on Remedy and Bonding in the above-captioned investigation. The Commission is soliciting comments on public interest issues raised by the recommended relief, specifically a limited exclusion order directed to respondents Toshiba Corporation of Tokyo, Japan; Toshiba Memory Corporation of Tokyo, Japan; Toshiba America, Inc. of New York, New York; Toshiba America Electronic Components, Inc. of Irvine, California; Toshiba America Information Systems, Inc. of Irvine, California; and Toshiba Information Equipment (Philippines), Inc. of Binan, Philippines, and cease and desist orders directed to the domestic respondents. This notice is soliciting public interest comments from the public only. Parties are to file public interest submissions pursuant to Commission rules.

Software/hardware distributed processing network supporting the Ada environment

NASA Astrophysics Data System (ADS)

Wood, Richard J.; Pryk, Zen

1993-09-01

A high-performance, fault-tolerant, distributed network has been developed, tested, and demonstrated. The network is based on the MIPS Computer Systems, Inc. R3000 Risc for processing, VHSIC ASICs for high speed, reliable, inter-node communications and compatible commercial memory and I/O boards. The network is an evolution of the Advanced Onboard Signal Processor (AOSP) architecture. It supports Ada application software with an Ada- implemented operating system. A six-node implementation (capable of expansion up to 256 nodes) of the RISC multiprocessor architecture provides 120 MIPS of scalar throughput, 96 Mbytes of RAM and 24 Mbytes of non-volatile memory. The network provides for all ground processing applications, has merit for space-qualified RISC-based network, and interfaces to advanced Computer Aided Software Engineering (CASE) tools for application software development.

Realization of Minimum and Maximum Gate Function in Ta2O5-based Memristive Devices

NASA Astrophysics Data System (ADS)

Breuer, Thomas; Nielen, Lutz; Roesgen, Bernd; Waser, Rainer; Rana, Vikas; Linn, Eike

2016-04-01

Redox-based resistive switching devices (ReRAM) are considered key enablers for future non-volatile memory and logic applications. Functionally enhanced ReRAM devices could enable new hardware concepts, e.g. logic-in-memory or neuromorphic applications. In this work, we demonstrate the implementation of ReRAM-based fuzzy logic gates using Ta2O5 devices to enable analogous Minimum and Maximum operations. The realized gates consist of two anti-serially connected ReRAM cells offering two inputs and one output. The cells offer an endurance up to 106 cycles. By means of exemplary input signals, each gate functionality is verified and signal constraints are highlighted. This realization could improve the efficiency of analogous processing tasks such as sorting networks in the future.

Voltage switching of a VO{sub 2} memory metasurface using ionic gel

DOE Office of Scientific and Technical Information (OSTI.GOV)

Goldflam, M. D.; Liu, M. K.; Chapler, B. C.

2014-07-28

We demonstrate an electrolyte-based voltage tunable vanadium dioxide (VO{sub 2}) memory metasurface. Large spatial scale, low voltage, non-volatile switching of terahertz (THz) metasurface resonances is achieved through voltage application using an ionic gel to drive the insulator-to-metal transition in an underlying VO{sub 2} layer. Positive and negative voltage application can selectively tune the metasurface resonance into the “off” or “on” state by pushing the VO{sub 2} into a more conductive or insulating regime respectively. Compared to graphene based control devices, the relatively long saturation time of resonance modification in VO{sub 2} based devices suggests that this voltage-induced switching originates primarilymore » from electrochemical effects related to oxygen migration across the electrolyte–VO{sub 2} interface.« less

Targeting an efficient target-to-target interval for P300 speller brain–computer interfaces

PubMed Central

Sellers, Eric W.; Wang, Xingyu

2013-01-01

Longer target-to-target intervals (TTI) produce greater P300 event-related potential amplitude, which can increase brain–computer interface (BCI) classification accuracy and decrease the number of flashes needed for accurate character classification. However, longer TTIs requires more time for each trial, which will decrease the information transfer rate of BCI. In this paper, a P300 BCI using a 7 × 12 matrix explored new flash patterns (16-, 18- and 21-flash pattern) with different TTIs to assess the effects of TTI on P300 BCI performance. The new flash patterns were designed to minimize TTI, decrease repetition blindness, and examine the temporal relationship between each flash of a given stimulus by placing a minimum of one (16-flash pattern), two (18-flash pattern), or three (21-flash pattern) non-target flashes between each target flashes. Online results showed that the 16-flash pattern yielded the lowest classification accuracy among the three patterns. The results also showed that the 18-flash pattern provides a significantly higher information transfer rate (ITR) than the 21-flash pattern; both patterns provide high ITR and high accuracy for all subjects. PMID:22350331

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Seyong; Vetter, Jeffrey S

Computer architecture experts expect that non-volatile memory (NVM) hierarchies will play a more significant role in future systems including mobile, enterprise, and HPC architectures. With this expectation in mind, we present NVL-C: a novel programming system that facilitates the efficient and correct programming of NVM main memory systems. The NVL-C programming abstraction extends C with a small set of intuitive language features that target NVM main memory, and can be combined directly with traditional C memory model features for DRAM. We have designed these new features to enable compiler analyses and run-time checks that can improve performance and guard againstmore » a number of subtle programming errors, which, when left uncorrected, can corrupt NVM-stored data. Moreover, to enable recovery of data across application or system failures, these NVL-C features include a flexible directive for specifying NVM transactions. So that our implementation might be extended to other compiler front ends and languages, the majority of our compiler analyses are implemented in an extended version of LLVM's intermediate representation (LLVM IR). We evaluate NVL-C on a number of applications to show its flexibility, performance, and correctness.« less

Resistive switching effect in the planar structure of all-printed, flexible and rewritable memory device based on advanced 2D nanocomposite of graphene quantum dots and white graphene flakes

NASA Astrophysics Data System (ADS)

Muqeet Rehman, Muhammad; Uddin Siddiqui, Ghayas; Kim, Sowon; Choi, Kyung Hyun

2017-08-01

Pursuit of the most appropriate materials and fabrication methods is essential for developing a reliable, rewritable and flexible memory device. In this study, we have proposed an advanced 2D nanocomposite of white graphene (hBN) flakes embedded with graphene quantum dots (GQDs) as the functional layer of a flexible memory device owing to their unique electrical, chemical and mechanical properties. Unlike the typical sandwich type structure of a memory device, we developed a cost effective planar structure, to simplify device fabrication and prevent sneak current. The entire device fabrication was carried out using printing technology followed by encapsulation in an atomically thin layer of aluminum oxide (Al2O3) for protection against environmental humidity. The proposed memory device exhibited attractive bipolar switching characteristics of high switching ratio, large electrical endurance and enhanced lifetime, without any crosstalk between adjacent memory cells. The as-fabricated device showed excellent durability for several bending cycles at various bending diameters without any degradation in bistable resistive states. The memory mechanism was deduced to be conductive filamentary; this was validated by illustrating the temperature dependence of bistable resistive states. Our obtained results pave the way for the execution of promising 2D material based next generation flexible and non-volatile memory (NVM) applications.

Fully transparent, non-volatile bipolar resistive memory based on flexible copolyimide films

NASA Astrophysics Data System (ADS)

Yu, Hwan-Chul; Kim, Moon Young; Hong, Minki; Nam, Kiyong; Choi, Ju-Young; Lee, Kwang-Hun; Baeck, Kyoung Koo; Kim, Kyoung-Kook; Cho, Soohaeng; Chung, Chan-Moon

2017-01-01

Partially aliphatic homopolyimides and copolyimides were prepared from rel-(1'R,3S,5'S)-spiro[furan-3(2H),6'-[3]oxabicyclo[3.2.1]octane]-2,2',4',5(4H)-tetrone (DAn), 2,6-diaminoanthracene (AnDA), and 4,4'-oxydianiline (ODA) by varying the molar ratio of AnDA and ODA. We utilized these polyimide films as the resistive switching layer in transparent memory devices. While WORM memory behavior was obtained with the PI-A100-O0-based device (molar feed ratio of DAn : AnDA : ODA = 1 : 1 : 0), the PI-A70-O30-based device (molar feed ratio of DAn : AnDA : ODA = 1 : 0.7 : 0.3) exhibited bipolar resistive switching behavior with stable retention for 104 s. This result implies that the memory properties can be controlled by changing the polyimide composition. The two devices prepared from PI-A100-O0 and PI-A70-O30 showed over 90% transmittance in the visible wavelength range from 400 to 800 nm. The behavior of the memory devices is considered to be governed by trap-controlled, space-charge limited conduction (SCLC) and local filament formation. [Figure not available: see fulltext.

Threshold-voltage modulated phase change heterojunction for application of high density memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yan, Baihan; Tong, Hao, E-mail: tonghao@hust.edu.cn; Qian, Hang

2015-09-28

Phase change random access memory is one of the most important candidates for the next generation non-volatile memory technology. However, the ability to reduce its memory size is compromised by the fundamental limitations inherent in the CMOS technology. While 0T1R configuration without any additional access transistor shows great advantages in improving the storage density, the leakage current and small operation window limit its application in large-scale arrays. In this work, phase change heterojunction based on GeTe and n-Si is fabricated to address those problems. The relationship between threshold voltage and doping concentration is investigated, and energy band diagrams and X-raymore » photoelectron spectroscopy measurements are provided to explain the results. The threshold voltage is modulated to provide a large operational window based on this relationship. The switching performance of the heterojunction is also tested, showing a good reverse characteristic, which could effectively decrease the leakage current. Furthermore, a reliable read-write-erase function is achieved during the tests. Phase change heterojunction is proposed for high-density memory, showing some notable advantages, such as modulated threshold voltage, large operational window, and low leakage current.« less

Tin in a chondritic interplanetary dust particle

NASA Technical Reports Server (NTRS)

Rietmeijer, Frans J. M.

1989-01-01

Submicron platey Sn-rich grains are present in chondritic porous interplanetary dust particle (IDP) W7029 A and it is the second occurrence of a tin mineral in a stratospheric micrometeorite. Selected Area Electron Diffraction data for the Sn-rich grains match with Sn2O3 and Sn3O4. The oxide(s) may have formed in the solar nebula when tin metal catalytically supported reduction of CO or during flash heating on atmospheric entry of the IDP. The presence of tin is consistent with enrichments for other volatile trace elements in chondritic IDPs and may signal an emerging trend toward nonchondritic volatile element abundances in chondritic IDPs. The observation confirms small-scale mineralogical heterogeneity in fine-grained chondritic porous interplanetary dust.

Fabrication de memoire monoelectronique non volatile par une approche de nanogrille flottante

NASA Astrophysics Data System (ADS)

Guilmain, Marc

Les transistors monoelectroniques (SET) sont des dispositifs de tailles nanometriques qui permettent la commande d'un electron a la fois et donc, qui consomment peu d'energie. Une des applications complementaires des SET qui attire l'attention est son utilisation dans des circuits de memoire. Une memoire monoelectronique (SEM) non volatile a le potentiel d'operer a des frequences de l'ordre des gigahertz ce qui lui permettrait de remplacer en meme temps les memoires mortes de type FLASH et les memoires vives de type DRAM. Une puce SEM permettrait donc ultimement la reunification des deux grands types de memoire au sein des ordinateurs. Cette these porte sur la fabrication de memoires monoelectroniques non volatiles. Le procede de fabrication propose repose sur le procede nanodamascene developpe par C. Dubuc et al. a 1'Universite de Sherbrooke. L'un des avantages de ce procede est sa compatibilite avec le back-end-of-line (BEOL) des circuits CMOS. Ce procede a le potentiel de fabriquer plusieurs couches de circuits memoirestres denses au-dessus de tranches CMOS. Ce document presente, entre autres, la realisation d'un simulateur de memoires monoelectroniques ainsi que les resultats de simulations de differentes structures. L'optimisation du procede de fabrication de dispositifs monoelectroniques et la realisation de differentes architectures de SEM simples sont traitees. Les optimisations ont ete faites a plusieurs niveaux : l'electrolithographie, la gravure de l'oxyde, le soulevement du titane, la metallisation et la planarisation CMP. La caracterisation electrique a permis d'etudier en profondeur les dispositifs formes de jonction de Ti/TiO2 et elle a demontre que ces materiaux ne sont pas appropries. Par contre, un SET forme de jonction de TiN/Al2O3 a ete fabrique et caracterise avec succes a basse temperature. Cette demonstration demontre le potentiel du procede de fabrication et de la deposition de couche atomique (ALD) pour la fabrication de memoires monoelectroniques. Mots-cles: Transistor monoelectronique (SET), memoire monoelectronique (SEM), jonction tunnel, temps de retention, nanofabrication, electrolithographie, planarisation chimicomecanique.

Demonstration of Novel Sampling Techniques for Measurement of Turbine Engine Volatile and Non-Volatile Particulate Matter (PM) Emissions

DTIC Science & Technology

2017-03-06

WP-201317) Demonstration of Novel Sampling Techniques for Measurement of Turbine Engine Volatile and Non -volatile Particulate Matter (PM...Engine Volatile and Non -Volatile Particulate Matter (PM) Emissions 6. AUTHOR(S) E. Corporan, M. DeWitt, C. Klingshirn, M.D. Cheng, R. Miake-Lye, J. Peck...the performance and viability of two devices to condition aircraft turbine engine exhaust to allow the accurate measurement of total (volatile and non

Radiation-hardened MRAM-based LUT for non-volatile FPGA soft error mitigation with multi-node upset tolerance

NASA Astrophysics Data System (ADS)

Zand, Ramtin; DeMara, Ronald F.

2017-12-01

In this paper, we have developed a radiation-hardened non-volatile lookup table (LUT) circuit utilizing spin Hall effect (SHE)-magnetic random access memory (MRAM) devices. The design is motivated by modeling the effect of radiation particles striking hybrid complementary metal oxide semiconductor/spin based circuits, and the resistive behavior of SHE-MRAM devices via established and precise physics equations. The models developed are leveraged in the SPICE circuit simulator to verify the functionality of the proposed design. The proposed hardening technique is based on using feedback transistors, as well as increasing the radiation capacity of the sensitive nodes. Simulation results show that our proposed LUT circuit can achieve multiple node upset (MNU) tolerance with more than 38% and 60% power-delay product improvement as well as 26% and 50% reduction in device count compared to the previous energy-efficient radiation-hardened LUT designs. Finally, we have performed a process variation analysis showing that the MNU immunity of our proposed circuit is realized at the cost of increased susceptibility to transistor and MRAM variations compared to an unprotected LUT design.

Effect of AlN layer on the bipolar resistive switching behavior in TiN thin film based ReRAM device for non-volatile memory application

NASA Astrophysics Data System (ADS)

Prakash, Ravi; Kaur, Davinder

2018-05-01

The effect of an additional AlN layer in the Cu/TiN/AlN/Pt stack configuration deposited using sputtering has been investigated. The Cu/TiN/AlN/Pt device shows a tristate resistive switching. Multilevel switching is facilitated by ionic and metallic filament formation, and the nature of the filaments formed is confirmed by performing a resistance vs. temperature measurement. Ohmic behaviour and trap controlled space charge limited current (SCLC) conduction mechanisms are confirmed as dominant conduction mechanism at low resistance state (LRS) and high resistance state (HRS). High resistance ratio (102) corresponding to HRS and LRS, good write/erase endurance (105) and non-volatile long retention (105s) are also observed. Higher thermal conductivity of the AlN layer is the main reasons for the enhancement of resistive switching performance in Cu/TiN/AlN/Pt cell. The above result suggests the feasibility of Cu/TiN/AlN/Pt devices for multilevel nonvolatile ReRAM application.

Addressing Inter-set Write-Variation for Improving Lifetime of Non-Volatile Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S

We propose a technique which minimizes inter-set write variation in NVM caches for improving its lifetime. Our technique uses cache coloring scheme to add a software-controlled mapping layer between groups of physical pages (called memory regions) and cache sets. Periodically, the number of writes to different colors of the cache is computed and based on this result, the mapping of a few colors is changed to channel the write traffic to least utilized cache colors. This change helps to achieve wear-leveling.

Requirements and Usage of NVM in Advanced Onboard Data Processing Systems

NASA Technical Reports Server (NTRS)

Some, R.

2001-01-01

This viewgraph presentation gives an overview of the requirements and uses of non-volatile memory (NVM) in advanced onboard data processing systems. Supercomputing in space presents the only viable approach to the bandwidth problem (can't get data down to Earth), controlling constellations of cooperating satellites, reducing mission operating costs, and real-time intelligent decision making and science data gathering. Details are given on the REE vision and impact on NASA and Department of Defense missions, objectives of REE, baseline architecture, and issues. NVM uses and requirements are listed.

Short-Term Plasticity and Long-Term Potentiation in Magnetic Tunnel Junctions: Towards Volatile Synapses

NASA Astrophysics Data System (ADS)

Sengupta, Abhronil; Roy, Kaushik

2016-02-01

Synaptic memory is considered to be the main element responsible for learning and cognition in humans. Although traditionally nonvolatile long-term plasticity changes are implemented in nanoelectronic synapses for neuromorphic applications, recent studies in neuroscience reveal that biological synapses undergo metastable volatile strengthening followed by a long-term strengthening provided that the frequency of the input stimulus is sufficiently high. Such "memory strengthening" and "memory decay" functionalities can potentially lead to adaptive neuromorphic architectures. In this paper, we demonstrate the close resemblance of the magnetization dynamics of a magnetic tunnel junction (MTJ) to short-term plasticity and long-term potentiation observed in biological synapses. We illustrate that, in addition to the magnitude and duration of the input stimulus, the frequency of the stimulus plays a critical role in determining long-term potentiation of the MTJ. Such MTJ synaptic memory arrays can be utilized to create compact, ultrafast, and low-power intelligent neural systems.

Hypnosis for hot flashes among postmenopausal women study: A study protocol of an ongoing randomized clinical trial

PubMed Central

2011-01-01

Background Hot flashes are a highly prevalent problem associated with menopause and breast cancer treatments. The recent findings from the Women's Health Initiative have important implications for the significance of a non-hormonal, mind-body intervention for hot flashes in breast cancer survivors. Women who take hormone therapy long-term may have a 1.2 to 2.0 fold increased risk of developing breast cancer. In addition, it is now known that hormone therapy with estrogen and progestin is associated with increased risk of cardiovascular disease and stroke. Currently there are limited options to hormone replacement therapy as non-hormonal pharmacological agents are associated with only modest activity and many adverse side effects. Because of this there is a need for more alternative, non-hormonal therapies. Hypnosis is a mind-body intervention that has been shown to reduce self-reported hot flashes by up to 68% among breast cancer survivors, however, the use of hypnosis for hot flashes among post-menopausal women has not been adequately explored and the efficacy of hypnosis in reducing physiologically measured hot flashes has not yet been determined. Methods/design A sample of 180 post-menopausal women will be randomly assigned to either a 5-session Hypnosis Intervention or 5-session structured-attention control with 12 week follow-up. The present study will compare hypnosis to a structured-attention control in reducing hot flashes (perceived and physiologically monitored) in post-menopausal women in a randomized clinical trial. Outcomes will be hot flashes (self-report daily diaries; physiological monitoring; Hot Flash Related Daily Interference Scale), anxiety (State-Trait Anxiety Inventory; Hospital Anxiety and Depression Scale (HADS); anxiety visual analog scale (VAS rating); depression (Center for Epidemiologic Studies Depression Scale), sexual functioning (Sexual Activity Questionnaire), sleep quality (Pittsburgh Sleep Quality Index) and cortisol. Discussion This study will be the first full scale test of hypnosis for hot flashes; one of the first studies to examine both perceived impact and physiologically measured impact of a mind-body intervention for hot flashes using state-of-the-art 24 hour ambulatory physiological monitoring; the first study to examine the effect of hypnosis for hot flashes on cortisol; and the first investigation of the role of cognitive expectancies in treatment of hot flashes in comparison to a Structured-Attention Control. Trial Registration This clinical trial has been registered with ClinicalTrials.gov, a service of the U.S. National Institutes of Health, ClinicalTrials.gov Identifier: NCT01293695. PMID:21989181

Transparent resistive switching memory using aluminum oxide on a flexible substrate

NASA Astrophysics Data System (ADS)

Yeom, Seung-Won; Shin, Sang-Chul; Kim, Tan-Young; Ha, Hyeon Jun; Lee, Yun-Hi; Shim, Jae Won; Ju, Byeong-Kwon

2016-02-01

Resistive switching memory (ReRAM) has attracted much attention in recent times owing to its fast switching, simple structure, and non-volatility. Flexible and transparent electronic devices have also attracted considerable attention. We therefore fabricated an Al2O3-based ReRAM with transparent indium-zinc-oxide (IZO) electrodes on a flexible substrate. The device transmittance was found to be higher than 80% in the visible region (400-800 nm). Bended states (radius = 10 mm) of the device also did not affect the memory performance because of the flexibility of the two transparent IZO electrodes and the thin Al2O3 layer. The conduction mechanism of the resistive switching of our device was explained by ohmic conduction and a Poole-Frenkel emission model. The conduction mechanism was proved by oxygen vacancies in the Al2O3 layer, as analyzed by x-ray photoelectron spectroscopy analysis. These results encourage the application of ReRAM in flexible and transparent electronic devices.

FPGA-based prototype storage system with phase change memory

NASA Astrophysics Data System (ADS)

Li, Gezi; Chen, Xiaogang; Chen, Bomy; Li, Shunfen; Zhou, Mi; Han, Wenbing; Song, Zhitang

2016-10-01

With the ever-increasing amount of data being stored via social media, mobile telephony base stations, and network devices etc. the database systems face severe bandwidth bottlenecks when moving vast amounts of data from storage to the processing nodes. At the same time, Storage Class Memory (SCM) technologies such as Phase Change Memory (PCM) with unique features like fast read access, high density, non-volatility, byte-addressability, positive response to increasing temperature, superior scalability, and zero standby leakage have changed the landscape of modern computing and storage systems. In such a scenario, we present a storage system called FLEET which can off-load partial or whole SQL queries to the storage engine from CPU. FLEET uses an FPGA rather than conventional CPUs to implement the off-load engine due to its highly parallel nature. We have implemented an initial prototype of FLEET with PCM-based storage. The results demonstrate that significant performance and CPU utilization gains can be achieved by pushing selected query processing components inside in PCM-based storage.

Rewritable ferroelectric vortex pairs in BiFeO3

NASA Astrophysics Data System (ADS)

Li, Yang; Jin, Yaming; Lu, Xiaomei; Yang, Jan-Chi; Chu, Ying-Hao; Huang, Fengzhen; Zhu, Jinsong; Cheong, Sang-Wook

2017-08-01

Ferroelectric vortex in multiferroic materials has been considered as a promising alternative to current memory cells for the merit of high storage density. However, the formation of regular natural ferroelectric vortex is difficult, restricting the achievement of vortex memory device. Here, we demonstrated the creation of ferroelectric vortex-antivortex pairs in BiFeO3 thin films by using local electric field. The evolution of the polar vortex structure is studied by piezoresponse force microscopy at nanoscale. The results reveal that the patterns and stability of vortex structures are sensitive to the poling position. Consecutive writing and erasing processes cause no influence on the original domain configuration. The Z4 proper coloring vortex-antivortex network is then analyzed by graph theory, which verifies the rationality of artificial vortex-antivortex pairs. This study paves a foundation for artificial regulation of vortex, which provides a possible pathway for the design and realization of non-volatile vortex memory devices and logical devices.

A New Concept for Non-Volatile Memory: The Electric-Pulse Induced Resistive Change Effect in Colossal Magnetoresistive Thin Films

NASA Technical Reports Server (NTRS)

Liu, S. Q.; Wu, N. J.; Ignatiev, A.

2001-01-01

A novel electric pulse-induced resistive change (EPIR) effect has been found in thin film colossal magnetoresistive (CMR) materials, and has shown promise for the development of resistive, nonvolatile memory. The EPIR effect is induced by the application of low voltage (< 4 V) and short duration (< 20 ns) electrical pulses across a thin film sample of a CMR material at room temperature and under no applied magnetic field. The pulse can directly either increase or decrease the resistance of the thin film sample depending on pulse polarity. The sample resistance change has been shown to be over two orders of magnitude, and is nonvolatile after pulsing. The sample resistance can also be changed through multiple levels - as many as 50 have been shown. Such a device can provide a way for the development of a new kind of nonvolatile multiple-valued memory with high density, fast write/read speed, low power-consumption, and potential high radiation-hardness.

An amorphous titanium dioxide metal insulator metal selector device for resistive random access memory crossbar arrays with tunable voltage margin

NASA Astrophysics Data System (ADS)

Cortese, Simone; Khiat, Ali; Carta, Daniela; Light, Mark E.; Prodromakis, Themistoklis

2016-01-01

Resistive random access memory (ReRAM) crossbar arrays have become one of the most promising candidates for next-generation non volatile memories. To become a mature technology, the sneak path current issue must be solved without compromising all the advantages that crossbars offer in terms of electrical performances and fabrication complexity. Here, we present a highly integrable access device based on nickel and sub-stoichiometric amorphous titanium dioxide (TiO2-x), in a metal insulator metal crossbar structure. The high voltage margin of 3 V, amongst the highest reported for monolayer selector devices, and the good current density of 104 A/cm2 make it suitable to sustain ReRAM read and write operations, effectively tackling sneak currents in crossbars without compromising fabrication complexity in a 1 Selector 1 Resistor (1S1R) architecture. Furthermore, the voltage margin is found to be tunable by an annealing step without affecting the device's characteristics.

Forming free and ultralow-power erase operation in atomically crystal TiO2 resistive switching

NASA Astrophysics Data System (ADS)

Dai, Yawei; Bao, Wenzhong; Hu, Linfeng; Liu, Chunsen; Yan, Xiao; Chen, Lin; Sun, Qingqing; Ding, Shijin; Zhou, Peng; Zhang, David Wei

2017-06-01

Two-dimensional layered materials (2DLMs) have attracted broad interest from fundamental sciences to industrial applications. Their applications in memory devices have been demonstrated, yet much still remains to explore optimal materials and device structure for practical application. In this work, a forming-free, bipolar resistive switching behavior are demonstrated in 2D TiO2-based resistive random access memory (RRAM). Physical adsorption method is adopted to achieve high quality, continuous 2D TiO2 network efficiently. The 2D TiO2 RRAM devices exhibit superior properties such as fast switching capability (20 ns of erase operation) and extremely low erase energy consumption (0.16 fJ). Furthermore, the resistive switching mechanism is attributed to the formation and rupture of oxygen vacancies-based percolation path in 2D TiO2 crystals. Our results pave the way for the implementation of high performance 2DLMs-based RRAM in the next generation non-volatile memory (NVM) application.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

PubMed Central

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-01-01

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced. PMID:27834352

Logic and memory concepts for all-magnetic computing based on transverse domain walls

NASA Astrophysics Data System (ADS)

Vandermeulen, J.; Van de Wiele, B.; Dupré, L.; Van Waeyenberge, B.

2015-06-01

We introduce a non-volatile digital logic and memory concept in which the binary data is stored in the transverse magnetic domain walls present in in-plane magnetized nanowires with sufficiently small cross sectional dimensions. We assign the digital bit to the two possible orientations of the transverse domain wall. Numerical proofs-of-concept are presented for a NOT-, AND- and OR-gate, a FAN-out as well as a reading and writing device. Contrary to the chirality based vortex domain wall logic gates introduced in Omari and Hayward (2014 Phys. Rev. Appl. 2 044001), the presented concepts remain applicable when miniaturized and are driven by electrical currents, making the technology compatible with the in-plane racetrack memory concept. The individual devices can be easily combined to logic networks working with clock speeds that scale linearly with decreasing design dimensions. This opens opportunities to an all-magnetic computing technology where the digital data is stored and processed under the same magnetic representation.

A Common DPU Platform for ESA JUICE Mission Instruments

NASA Astrophysics Data System (ADS)

Aberg, Martin; Hellstrom, Daniel; Samuelsson, Arne; Torelli, Felice

2016-08-01

This paper describes the resulting hardware and software platform based on GR712RC [1] LEON3-FT that Cobham Gaisler developed in accordance with the common system requirements of the ten scientific instruments on-board the ESA JUICE spacecraft destined the Jupiter system [8].The radiation hardened DPU platform features EDAC protected boot, application memory and working memory of configurable sizes and SpaceWire, FPGA I/O-32/16/8, GPIO, UART and SPI I/O interfaces. The design has undergone PSA, Risk, WCA, Radiation analyses etc. to justify component and design choices resulting in a robust design that can be used in spacecrafts requiring a total dose up to 100krad(Si). The prototype board manufactured uses engineering models of the flight components to ensure that development is representative.Validated boot, standby and driver software accommodates the various DPU platform configurations. The boot performs low-level DPU initialization, standby handles OBC SpaceWire communication and finally the loading and executing of application images typically stored in the non-volatile application memory.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic.

PubMed

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-11-11

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

From MEMRISTOR to MEMImpedance device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wakrim, T.; Univ. Grenoble Alpes, G2Elab, F-38000 Grenoble; Vallée, C., E-mail: christophe.vallee@cea.fr

2016-02-01

The behavior of the capacitance switching of HfO{sub 2} Resistive non-volatile Memories is investigated in view of realizing a MEMImpedance (MEM-Z) device. In such a Metal Insulator Metal structure, the impedance value can be tuned by the adjustment of both resistance and capacitance values. We observe a strong variation of capacitance from positive to negative values in a single layer Metal Insulator Metal device made of HfO{sub 2} deposited by Atomic Layer Deposition, but unfortunately no memory effect is observed. However, in the case of a two layer structure, a device has been obtained with a memory effect where bothmore » resistance and capacitance values can be tuned simultaneously, with a variation of capacitance down to negative values to get an inductive behavior. Negative capacitance values are observed for voltage values near SET voltage. A schematic model based on shaped oxygen vacancy density is proposed to account for this capacitance variation. The oxygen vacancies can be either isolated or connected in the bulk of the oxide.« less

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

NASA Astrophysics Data System (ADS)

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-11-01

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

Method of manufacturing metallic products such as sheet by cold working and flash anealing

DOEpatents

Hajaligol, Mohammad R.; Sikka, Vinod K.

2001-01-01

A metallic alloy composition is manufactured into products such as press formed or stamped products or rolled products such as sheet, strip, rod, wire or band by one or more cold working steps with intermediate or final flash annealing. The method can include cold rolling an iron, nickel or titanium aluminide alloy and annealing the cold worked product in a furnace by infrared heating. The flash annealing is preferably carried out by rapidly heating the cold worked product to an elevated temperature for less than one minute. The flash annealing is effective to reduce surface hardness of the cold worked product sufficiently to allow further cold working. The product to be cold worked can be prepared by casting the alloy or by a powder metallurgical technique such as tape casting a mixture of metal powder and a binder, roll compacting a mixture of the powder and a binder or plasma spraying the powder onto a substrate. In the case of tape casting or roll compaction, the initial powder product can be heated to a temperature sufficient to remove volatile components. The method can be used to form a cold rolled sheet which is formed into an electrical resistance heating element capable of heating to 900.degree. C. in less than 1 second when a voltage up to 10 volts and up to 6 amps is passed through the heating element.

Method of manufacturing metallic products such as sheet by cold working and flash annealing

DOEpatents

Hajaligol, Mohammad R.; Sikka, Vinod K.

2000-01-01

A metallic alloy composition is manufactured into products such as press formed or stamped products or rolled products such as sheet, strip, rod, wire or band by one or more cold working steps with intermediate or final flash annealing. The method can include cold rolling an iron, nickel or titanium aluminide alloy and annealing the cold worked product in a furnace by infrared heating. The flash annealing is preferably carried out by rapidly heating the cold worked product to an elevated temperature for less than one minute. The flash annealing is effective to reduce surface hardness of the cold worked product sufficiently to allow further cold working. The product to be cold worked can be prepared by casting the alloy or by a powder metallurgical technique such as tape casting a mixture of metal powder and a binder, roll compacting a mixture of the powder and a binder or plasma spraying the powder onto a substrate. In the case of tape casting or roll compaction, the initial powder product can be heated to a temperature sufficient to remove volatile components. The method can be used to form a cold rolled sheet which is formed into an electrical resistance heating element capable of heating to 900.degree. C. in less than 1 second when a voltage up to 10 volts and up to 6 amps is passed through the heating element.

Electrically erasable non-volatile memory via electrochemical deposition of multifractal aggregates

NASA Astrophysics Data System (ADS)

West, William Clark

An electrically erasable non-volatile memory system based on the electrochemical deposition of Ag or Cu from a solid electrolyte is presented. This memory system, referred to as Metal Dendrite Memory, is characterized by its simplicity of design and operation, low power consumption, and potentially high cell density. By applying a small DC voltage (2.5-5V) across a Cu or Ag doped As-S amorphous chalcogenide film sandwiched between two metal electrodes, a metal filament can be electrodeposited, shorting the large impedance solid electrolyte ("on" state). Application of smaller amplitude voltage pulses (1-1.5V) across the metal filament ruptures the short, returning the cell to the high impedance state ("off" state). The state of the cell is read by applying very small amplitude voltage pulses (0.25V). These "read" voltage pulses do not disturb the state of the cell even after 10sp7 pulses. Due to difficulties in characterizing this solid electrolyte system via conventional techniques, the MDM cells have been examined using low excitation characterization methods such as Impedance Spectroscopy (IS) and polarization measurements. These studies have yielded a self-consistent equivalent circuit model as well as parameters such as ionic diffusivity and conductivity, double layer and geometric capacitances. In addition to materials characterization, the speed at which the MDM cells operate has been systematically studied using a series of statistically designed experiments, demonstrating the importance of photodoping time and applied voltage on device speed. These results were further examined using IS and Rutherford Backscattering Spectrometry (RBS). The morphology of the growing electrodeposit was studied in several different electrode arrangements and excitation conditions. Under migrationally limited conditions, the electrodeposit grew in multifractal patterns, as measured using lacunarity analysis. If a conducting film was deposited parallel to the growth direction, the electrodeposition could be driven from Diffusion Limited Aggregation (DLA) to Densely Branched Morphology (DBM) modes by changing the voltage applied to the cell. In summary, this study has laid the groundwork for future research and development of MDM memory systems by identifying many important characteristics of the MDM cell. These findings include quantitative measurement of ionic transport values, identification of the electrochemical mechanisms involved in MDM data storage, determination of parameters that are statistically significant in affecting data storage speed, and determination of the effect of cell geometry and bias on electrodeposit morphology.

Homogeneous-oxide stack in IGZO thin-film transistors for multi-level-cell NAND memory application

NASA Astrophysics Data System (ADS)

Ji, Hao; Wei, Yehui; Zhang, Xinlei; Jiang, Ran

2017-11-01

A nonvolatile charge-trap-flash memory that is based on amorphous indium-gallium-zinc-oxide thin film transistors was fabricated with a homogeneous-oxide structure for a multi-level-cell application. All oxide layers, i.e., tunneling layer, charge trapping layer, and blocking layer, were fabricated with Al2O3 films. The fabrication condition (including temperature and deposition method) of the charge trapping layer was different from those of the other oxide layers. This device demonstrated a considerable large memory window of 4 V between the states fully erased and programmed with the operation voltage less than 14 V. This kind of device shows a good prospect for multi-level-cell memory applications.

Memory Analysis of the KBeast Linux Rootkit: Investigating Publicly Available Linux Rootkit Using the Volatility Memory Analysis Framework

DTIC Science & Technology

2015-06-01

examine how a computer forensic investigator/incident handler, without specialised computer memory or software reverse engineering skills , can successfully...memory images and malware, this new series of reports will be directed at those who must analyse Linux malware-infected memory images. The skills ...disable 1287 1000 1000 /usr/lib/policykit-1-gnome/polkit-gnome-authentication- agent-1 1310 1000 1000 /usr/lib/pulseaudio/pulse/gconf- helper 1350

Remotely Powered Reconfigurable Receiver for Extreme Environment Sensing Platforms

NASA Technical Reports Server (NTRS)

Sheldon, Douglas J.

2012-01-01

Wireless sensors connected in a local network offer revolutionary exploration capabilities, but the current solutions do not work in extreme environments of low temperatures (200K) and low to moderate radiation levels (<50 krad). These sensors (temperature, radiation, infrared, etc.) would need to operate outside the spacecraft/ lander and be totally independent of power from the spacecraft/lander. Flash memory field-programmable gate arrays (FPGAs) are being used as the main signal processing and protocol generation platform in a new receiver. Flash-based FPGAs have been shown to have at least 100 reduced standby power and 10 reduction operating power when compared to normal SRAM-based FPGA technology.

Portable flash lamp reflectance analyzer system and method

NASA Technical Reports Server (NTRS)

Kalshoven, James Edward (Inventor)

1999-01-01

The system and method allow spectroscopic analysis of vegetation or the like without effects from changing sun and cloud conditions, undesired portions of the area of interest or atmospheric disturbances. The system (1) includes a light source (5) such as a xenon flash lamp, a telescope (7), a spectrometer (9), an analog/digital converter (11), a memory (13), a display (15), and an on-board microprocessor (17) or a port (19) for attachment to a laptop computer. The system is taken to an area of interest in the woods (step 41), the vegetation is illuminated from below (step 43) and data are taken (step 45).

A non-destructive crossbar architecture of multi-level memory-based resistor

NASA Astrophysics Data System (ADS)

Sahebkarkhorasani, Seyedmorteza

Nowadays, researchers are trying to shrink the memory cell in order to increase the capacity of the memory system and reduce the hardware costs. In recent years, there has been a revolution in electronics by using fundamentals of physics to build a new memory for computer application in order to increase the capacity and decrease the power consumption. Increasing the capacity of the memory causes a growth in the chip area. From 1971 to 2012 semiconductor manufacturing process improved from 6mum to 22 mum. In May 2008, S.Williams stated that "it is time to stop shrinking". In his paper, he declared that the process of shrinking memory element has recently become very slow and it is time to use another alternative in order to create memory elements [9]. In this project, we present a new design of a memory array using the new element named Memristor [3]. Memristor is a two-terminal passive electrical element that relates the charge and magnetic flux to each other. The device remained unknown since 1971 when it was discovered by Chua and introduced as the fourth fundamental passive element like capacitor, inductor and resistor [3]. Memristor has a dynamic resistance and it can retain its previous value even after disconnecting the power supply. Due to this interesting behavior of the Memristor, it can be a good replacement for all of the Non-Volatile Memories (NVMs) in the near future. Combination of this newly introduced element with the nanowire crossbar architecture would be a great structure which is called Crossbar Memristor. Some frameworks have recently been introduced in literature that utilized Memristor crossbar array, but there are many challenges to implement the Memristor crossbar array due to fabrication and device limitations. In this work, we proposed a simple design of Memristor crossbar array architecture which uses input feedback in order to preserve its data after each read operation.