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Sample records for nonvolatile memory devices

  1. Nonvolatile memory devices based on self-assembled nanocrystals

    NASA Astrophysics Data System (ADS)

    Lee, Jang-Sik

    2013-06-01

    Nonvolatile memory devices are one of the most important components in modern electronic devices. Many efforts have been made to fabricate high-density, low-cost, nonvolatile solid-state memory devices for use in portable/mobile electronic devices such as laptop computers, tablet devices, smart phones, etc. Among the many available nonvolatile memory devices, flash memory devices are of great interest to the electronics industry owing to their simple device structure, enabling high-density memory applications. Flash memory devices in which nanoparticles or nanocrystals are used as the charge-trapping elements have advantages over conventional flash memory devices because the charge-trapping layer and memory performance of the former can be readily optimized. Active research has recently been conducted to fabricate and characterize self-assembled-nanocrystal-based nonvolatile memory devices. We reviewed various strategies for fabricating nanocrystal-based nonvolatile memory devices and discussed the programmable memory properties and the device reliability characteristics of nanocrystal-based memory devices to possibly apply nanocrystal-based memory devices to those used in portable/mobile electronic devices. Finally, novel device applications such as printed/flexible/transparent electronic devices were explored based on nanocrystal-based memory devices.

  2. Titanium oxide nonvolatile memory device and its application

    NASA Astrophysics Data System (ADS)

    Wang, Wei

    In recent years, the semiconductor memory industry has seen an ever-increasing demand for nonvolatile memory (NVM), which is fueled by portable consumer electronic applications like the mobile phone and MP3 player. FLASH memory has been the most widely used nonvolatile memories in these systems, and has successfully kept up with CMOS scaling for many generations. However, as FLASH memory faces major scaling challenges beyond 22nm, non-charge-based nonvolatile memories are widely researched as candidates to replace FLASH. Titanium oxide (TiOx) nonvolatile memory device is considered to be a promising choice due to its controllable nonvolatile memory switching, good scalability, compatibility with CMOS processing and potential for 3D stacking. However, several major issues need to be overcome before TiOx NVM device can be adopted in manufacturing. First, there exists a highly undesirable high-voltage stress initiation process (FORMING) before the device can switch between high and low resistance states repeatedly. By analyzing the conductive behaviors of the memory device before and after FORMING, we propose that FORMING involves breaking down an interfacial layer between its Pt electrode and the TiOx thin film, and that FORMING is not needed if the Pt-TiOx interface can be kept clean during fabrication. An in-situ fabrication process is developed for cross-point TiOx NVM device, which enables in-situ deposition of the critical layers of the memory device and thus achieves clean interfaces between Pt electrodes and TiOx film. Testing results show that FORMING is indeed eliminated for memory devices made with the in-situ fabrication process. It verifies the significance of in-situ deposition without vacuum break in the fabrication of TiOx NVM devices. Switching parameters statistics of TiOx NVM devices are studied and compared for unipolar and bipolar switching modes. RESET mechanisms are found to be different for the two switching modes: unipolar switching can be

  3. Bioorganic nanodots for non-volatile memory devices

    SciTech Connect

    Amdursky, Nadav; Shalev, Gil; Handelman, Amir; Natan, Amir; Rosenwaks, Yossi; Litsyn, Simon; Szwarcman, Daniel; Rosenman, Gil; Roizin, Yakov

    2013-12-01

    In recent years we are witnessing an intensive integration of bio-organic nanomaterials in electronic devices. Here we show that the diphenylalanine bio-molecule can self-assemble into tiny peptide nanodots (PNDs) of ∼2 nm size, and can be embedded into metal-oxide-semiconductor devices as charge storage nanounits in non-volatile memory. For that purpose, we first directly observe the crystallinity of a single PND by electron microscopy. We use these nanocrystalline PNDs units for the formation of a dense monolayer on SiO{sub 2} surface, and study the electron/hole trapping mechanisms and charge retention ability of the monolayer, followed by fabrication of PND-based memory cell device.

  4. Evaluation of switchable organic devices for nonvolatile memory applications

    NASA Astrophysics Data System (ADS)

    Campbell Scott, J.

    2007-03-01

    Many organic electronic devices exhibit switching behavior and have therefore been proposed as the basis for a nonvolatile memory technology. In particular, bistable resistive elements, in which a high or low current state is selected by application of a specific voltage, may be used as the elements of a crosspoint memory array. This architecture places very stringent requirements on the electrical response of the individual devices, in terms of on-state current density, switching and retention times, cycling endurance, rectification and size-scaling. In this talk, I will describe the progress that we and others have made towards satisfying these requirements. In many cases, the mechanisms responsible for conduction and switching are not fully understood. In some devices, it has been shown that current flows in a few highly localized regions. These so-called ``filaments'' are not necessarily metallic bridges between the electrodes, but may be associated with chains of nanoparticles introduced into the organic matrix either deliberately or accidentally. Coulomb blockade effects can then explain the switching behavior observed in some devices. This work was done in collaboration with L. D. Bozano, M. Beinhoff, K. R. Carter, V. R. Deline, B. W. Kean, G. M. McClelland, D. C. Miller, P. M. Rice, J. R. Salem, and S. A. Swanson.

  5. Nickel nanocrystal formation on HfO2 dielectric for nonvolatile memory device applications

    NASA Astrophysics Data System (ADS)

    Lee, Jong Jin; Harada, Yoshinao; Pyun, Jung Woo; Kwong, Dim-Lee

    2005-03-01

    This letter presents the formation of nickel nanocrystal on HfO2 high-k dielectric and its application to the nonvolatile memory devices. The effects of the initial nickel layer thickness and annealing temperature on nickel nanocrystal formation are investigated. The n-metal-oxide-semiconductor field-effect transistor with nickel nanocrystals and HfO2 tunneling dielectrics is fabricated and its programming, data retention, and endurance properties are characterized to demonstrate its advantages for nonvolatile memory device applications.

  6. Flexible non-volatile memory devices based on organic semiconductors

    NASA Astrophysics Data System (ADS)

    Cosseddu, Piero; Casula, Giulia; Lai, Stefano; Bonfiglio, Annalisa

    2015-09-01

    The possibility of developing fully organic electronic circuits is critically dependent on the ability to realize a full set of electronic functionalities based on organic devices. In order to complete the scene, a fundamental element is still missing, i.e. reliable data storage. Over the past few years, a considerable effort has been spent on the development and optimization of organic polymer based memory elements. Among several possible solutions, transistor-based memories and resistive switching-based memories are attracting a great interest in the scientific community. In this paper, a route for the fabrication of organic semiconductor-based memory devices with performances beyond the state of the art is reported. Both the families of organic memories will be considered. A flexible resistive memory based on a novel combination of materials is presented. In particular, high retention time in ambient conditions are reported. Complementary, a low voltage transistor-based memory is presented. Low voltage operation is allowed by an hybrid, nano-sized dielectric, which is also responsible for the memory effect in the device. Thanks to the possibility of reproducibly fabricating such device on ultra-thin substrates, high mechanical stability is reported.

  7. Hydrogen annealing of silicon gate-nitride-oxide-silicon nonvolatile memory devices

    NASA Astrophysics Data System (ADS)

    Topich, James A.; Turi, Raymond A.

    1982-10-01

    A hydrogen annealing study of silicon gate-nitride-oxide-silicon (SNOS) nonvolatile memory devices showed that the important parameter in determining the optimum hydrogen annealing temperature for maximum charge retention is the previous thermal history of the memory devices. If a memory device's charge retention is not degraded by high-temperature processing, then the hydrogen anneal should be at the silicon nitride deposition temperature. If a device is degraded by high-temperature processing, then the hydrogen anneal should be at the degradation temperature.

  8. Integration of Flexible and Microscale Organic Nonvolatile Resistive Memory Devices Using Orthogonal Photolithography.

    PubMed

    Song, Younggul; Jang, Jingon; Yoo, Daekyoung; Jung, Seok-Heon; Jeong, Hyunhak; Hong, Seunghun; Lee, Jin-Kyun; Lee, Takhee

    2016-06-01

    We present the integration of flexible and microscale organic nonvolatile resistive memory devices fabricated in a cross-bar array structure on plastic substrates. This microscale integration was made via orthogonal photolithography method using fluorinated photoresist and solvents and was achieved without causing damage to the underlying organic memory materials. Our flexible microscale organic devices exhibited high ON/OFF ratio (I(ON/I(OFF) > 10(4)) under bending conditions. In addition, the ON and OFF states of our flexible and microscale memory devices were maintained for 10,000 seconds without any serious degradation.

  9. Metal-organic molecular device for non-volatile memory storage

    NASA Astrophysics Data System (ADS)

    Radha, B.; Sagade, Abhay A.; Kulkarni, G. U.

    2014-08-01

    Non-volatile memory devices have been of immense research interest for their use in active memory storage in powered off-state of electronic chips. In literature, various molecules and metal compounds have been investigated in this regard. Molecular memory devices are particularly attractive as they offer the ease of storing multiple memory states in a unique way and also represent ubiquitous choice for miniaturized devices. However, molecules are fragile and thus the device breakdown at nominal voltages during repeated cycles hinders their practical applicability. Here, in this report, a synergetic combination of an organic molecule and an inorganic metal, i.e., a metal-organic complex, namely, palladium hexadecylthiolate is investigated for memory device characteristics. Palladium hexadecylthiolate following partial thermolysis is converted to a molecular nanocomposite of Pd(II), Pd(0), and long chain hydrocarbons, which is shown to exhibit non-volatile memory characteristics with exceptional stability and retention. The devices are all solution-processed and the memory action stems from filament formation across the pre-formed cracks in the nanocomposite film.

  10. Metal-organic molecular device for non-volatile memory storage

    SciTech Connect

    Radha, B. E-mail: kulkarni@jncasr.ac.in; Sagade, Abhay A.; Kulkarni, G. U. E-mail: kulkarni@jncasr.ac.in

    2014-08-25

    Non-volatile memory devices have been of immense research interest for their use in active memory storage in powered off-state of electronic chips. In literature, various molecules and metal compounds have been investigated in this regard. Molecular memory devices are particularly attractive as they offer the ease of storing multiple memory states in a unique way and also represent ubiquitous choice for miniaturized devices. However, molecules are fragile and thus the device breakdown at nominal voltages during repeated cycles hinders their practical applicability. Here, in this report, a synergetic combination of an organic molecule and an inorganic metal, i.e., a metal-organic complex, namely, palladium hexadecylthiolate is investigated for memory device characteristics. Palladium hexadecylthiolate following partial thermolysis is converted to a molecular nanocomposite of Pd(II), Pd(0), and long chain hydrocarbons, which is shown to exhibit non-volatile memory characteristics with exceptional stability and retention. The devices are all solution-processed and the memory action stems from filament formation across the pre-formed cracks in the nanocomposite film.

  11. Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

    NASA Astrophysics Data System (ADS)

    Yu, Jie; Chen, Kun-ji; Ma, Zhong-yuan; Zhang, Xin-xin; Jiang, Xiao-fan; Wu, Yang-qing; Huang, Xin-fan; Oda, Shunri

    2016-09-01

    Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration. Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

  12. A fast and low-power microelectromechanical system-based non-volatile memory device

    PubMed Central

    Lee, Sang Wook; Park, Seung Joo; Campbell, Eleanor E. B.; Park, Yung Woo

    2011-01-01

    Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices. PMID:21364559

  13. High performance nonvolatile memory devices based on Cu2-xSe nanowires

    NASA Astrophysics Data System (ADS)

    Wu, Chun-Yan; Wu, Yi-Liang; Wang, Wen-Jian; Mao, Dun; Yu, Yong-Qiang; Wang, Li; Xu, Jun; Hu, Ji-Gang; Luo, Lin-Bao

    2013-11-01

    We report on the rational synthesis of one-dimensional Cu2-xSe nanowires (NWs) via a solution method. Electrical analysis of Cu2-xSe NWs based memory device exhibits a stable and reproducible bipolar resistive switching behavior with a low set voltage (0.3-0.6 V), which can enable the device to write and erase data efficiently. Remarkably, the memory device has a record conductance switching ratio of 108, much higher than other devices ever reported. At last, a conducting filaments model is introduced to account for the resistive switching behavior. The totality of this study suggests that the Cu2-xSe NWs are promising building blocks for fabricating high-performance and low-consumption nonvolatile memory devices.

  14. A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires

    PubMed Central

    2012-01-01

    In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n+-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and alleviating the requirement of precise control of the doping profile. Owing to the higher carrier concentration in the channel, the developed JL NW device exhibits significantly enhanced programming speed and larger memory window than its counterpart with conventional undoped-NW-channel. Moreover, it also displays acceptable erase and data retention properties. Hence, the desirable memory characteristics along with the much simplified fabrication process make the JL NW memory structure a promising candidate for future system-on-panel and three-dimensional ultrahigh density memory applications. PMID:22373446

  15. A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires.

    PubMed

    Su, Chun-Jung; Su, Tuan-Kai; Tsai, Tzu-I; Lin, Horng-Chih; Huang, Tiao-Yuan

    2012-02-29

    In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n+-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and alleviating the requirement of precise control of the doping profile. Owing to the higher carrier concentration in the channel, the developed JL NW device exhibits significantly enhanced programming speed and larger memory window than its counterpart with conventional undoped-NW-channel. Moreover, it also displays acceptable erase and data retention properties. Hence, the desirable memory characteristics along with the much simplified fabrication process make the JL NW memory structure a promising candidate for future system-on-panel and three-dimensional ultrahigh density memory applications.

  16. Flexible All-Inorganic Perovskite CsPbBr3 Nonvolatile Memory Device.

    PubMed

    Liu, Dongjue; Lin, Qiqi; Zang, Zhigang; Wang, Ming; Wangyang, Peihua; Tang, Xiaosheng; Zhou, Miao; Hu, Wei

    2017-02-22

    All-inorganic perovskite CsPbX3 (X = Cl, Br, or I) is widely used in a variety of photoelectric devices such as solar cells, light-emitting diodes, lasers, and photodetectors. However, studies to understand the flexible CsPbX3 electrical application are relatively scarce, mainly due to the limitations of the low-temperature fabricating process. In this study, all-inorganic perovskite CsPbBr3 films were successfully fabricated at 75 °C through a two-step method. The highly crystallized films were first employed as a resistive switching layer in the Al/CsPbBr3/PEDOT:PSS/ITO/PET structure for flexible nonvolatile memory application. The resistive switching operations and endurance performance demonstrated the as-prepared flexible resistive random access memory devices possess reproducible and reliable memory characteristics. Electrical reliability and mechanical stability of the nonvolatile device were further tested by the robust current-voltage curves under different bending angles and consecutive flexing cycles. Moreover, a model of the formation and rupture of filaments through the CsPbBr3 layer was proposed to explain the resistive switching effect. It is believed that this study will offer a new setting to understand and design all-inorganic perovskite materials for future stable flexible electronic devices.

  17. Non-volatile memory devices with redox-active diruthenium molecular compound

    NASA Astrophysics Data System (ADS)

    Pookpanratana, S.; Zhu, H.; Bittle, E. G.; Natoli, S. N.; Ren, T.; Richter, C. A.; Li, Q.; Hacker, C. A.

    2016-03-01

    Reduction-oxidation (redox) active molecules hold potential for memory devices due to their many unique properties. We report the use of a novel diruthenium-based redox molecule incorporated into a non-volatile Flash-based memory device architecture. The memory capacitor device structure consists of a Pd/Al2O3/molecule/SiO2/Si structure. The bulky ruthenium redox molecule is attached to the surface by using a ‘click’ reaction and the monolayer structure is characterized by x-ray photoelectron spectroscopy to verify the Ru attachment and molecular density. The ‘click’ reaction is particularly advantageous for memory applications because of (1) ease of chemical design and synthesis, and (2) provides an additional spatial barrier between the oxide/silicon to the diruthenium molecule. Ultraviolet photoelectron spectroscopy data identified the energy of the electronic levels of the surface before and after surface modification. The molecular memory devices display an unsaturated charge storage window attributed to the intrinsic properties of the redox-active molecule. Our findings demonstrate the strengths and challenges with integrating molecular layers within solid-state devices, which will influence the future design of molecular memory devices.

  18. Non-volatile Memory Devices with Redox-active Diruthenium Molecular Compound

    PubMed Central

    Pookpanratana, S.; Zhu, H.; Bittle, E. G.; Natoli, S. N.; Ren, T.; Richter, C. A; Li, Q.; Hacker, C. A.

    2016-01-01

    Reduction-oxidation (redox) active molecules hold potential for memory devices due to their many unique properties. We report the use of a novel diruthenium-based redox molecule incorporated into a non-volatile Flash-based memory device architecture. The memory capacitor device structure consists of a Pd/Al2O3/molecule/SiO2/Si structure. The bulky ruthenium redox molecule is attached to the surface by using a “click” reaction and the monolayer structure is characterized by X-ray photoelectron spectroscopy to verify the Ru attachment and molecular density. The “click” reaction is particularly advantageous for memory applications because of (1) ease of chemical design and synthesis, and (2) provides an additional spatial barrier between the oxide/silicon to the diruthenium molecule. Ultraviolet photoelectron spectroscopy data identified the energy of the electronic levels of the surface before and after surface modification. The molecular memory devices display an unsaturated charge storage window attributed to the intrinsic properties of the redox-active molecule. Our findings demonstrate the strengths and challenges with integrating molecular layers within solid-state devices, which will influence the future design of molecular memory devices. PMID:26871549

  19. Nonvolatile Memory Effect in Indium Gallium Arsenide-Based Metal-Oxide-Semiconductor Devices Using II-VI Tunnel Insulators

    NASA Astrophysics Data System (ADS)

    Chan, P.-Y.; Gogna, M.; Suarez, E.; Karmakar, S.; Al-Amoody, F.; Miller, B. I.; Jain, F. C.

    2011-08-01

    This paper reports the successful use of ZnSe/ZnS/ZnMgS/ZnS/ZnSe as a gate insulator stack for an InGaAs-based metal-oxide-semiconductor (MOS) device, and demonstrates the threshold voltage shift required in nonvolatile memory devices using a floating gate quantum dot layer. An InGaAs-based nonvolatile memory MOS device was fabricated using a high- κ II-VI tunnel insulator stack and self-assembled GeO x -cladded Ge quantum dots as the charge storage units. A Si3N4 layer was used as the control gate insulator. Capacitance-voltage data showed that, after applying a positive voltage to the gate of a MOS device, charges were being stored in the quantum dots. This was shown by the shift in the flat-band/threshold voltage, simulating the write process of a nonvolatile memory device.

  20. Memory effects of nonvolatile memory devices with a floating gate fabricated utilizing Ag nanoparticles embedded into a polymethylmethacrylate layer.

    PubMed

    Kim, Won Tae; Yun, Dong Yeol; Jung, Jae Hun; Kim, Tae Whan

    2011-01-01

    Nonvolatile memory devices based on a polymethylmethacrylate (PMMA) layer containing Ag nanoparticles were formed by using a spin coating method. High-resolution transmission electron microscopy images showed that Ag nanoparticles were randomly distributed in the PMMA layer. Capacitance-voltage (C-V) curves for the Al/Ag nanoparticles embedded in a PMMA layer/p-Si(100) device at 300 K showed a hysteresis with a large flat-band voltage shift, indicative of the Ag nanoparticles acting as the charge storage in the memory device. The magnitude of the flat-band voltage shift for the memory devices increased with increasing Ag nanoparticle concentration. The operating mechanisms for the writing and the erasing processes for the Al/Ag nanoparticles embedded in a PMMA layer/p-Si(100) device are described on the basis of the C-V results and electronic structures.

  1. Design of hybrid spintronic devices at scaled technologies for non-volatile memory applications

    NASA Astrophysics Data System (ADS)

    Mojumder, Niladri Narayan

    The ever-increasing demand for embedding more on- and off-chip memories to increase the bandwidth of high performance systems has led to a significant amount of research directed towards several potential high density memory technologies. With aggressive technology scaling, the researchers are incessantly confronted with various overwhelming challenges associated with the design of low power, ultra-high density and robust memory blocks. An alternative to all currently available memory technologies, spin-transfer torque (STT) Magnetic Random Access Memories (MRAM) offer many desirable memory-attributes. Data non-volatility, unlimited endurance, low power, high performance and high integration capabilities have stimulated an overwhelming interest for STT-MRAM among memory researchers. In an attempt to address the issues associated with parametric process variations and high switching energy consumptions, different genres of magnetic tunnel junction (MTJ) structures, memory bit-cells, and architecture are proposed. Unlike state-of-the-art tri-layer MTJ devices, the multi-port/multi-pillar structures provide the option to eliminate the self-conflicting design requirements for memory read, write and hold. Techniques to reduce thermal fluctuation induced delay spreads is discussed for reliable and deterministic magnetic switching characteristics in both in-plane and perpendicular anisotropy devices. The effect of thermal spin-transfer torque on high speed magnetic switching is discussed in the context of designing low power, robust, and reliable MRAM devices. Based on thermally initiated magnonic spin-transfer torque, we propose three new genres of multi-port MRAMs for low energy, high speed, and reliable magnetic switching. The proposition of several new genres of magnetic tunnel junctions (MTJ) based on both electric and thermal spin-transfer torque, the corresponding bit-cells, and memory architectures make STT-MRAM a promising choice as future universal memories.

  2. A robust molecular platform for non-volatile memory devices with optical and magnetic responses.

    PubMed

    Simão, Cláudia; Mas-Torrent, Marta; Crivillers, Núria; Lloveras, Vega; Artés, Juan Manuel; Gorostiza, Pau; Veciana, Jaume; Rovira, Concepció

    2011-05-01

    Bistable molecules that behave as switches in solution have long been known. Systems that can be reversibly converted between two stable states that differ in their physical properties are particularly attractive in the development of memory devices when immobilized in substrates. Here, we report a highly robust surface-confined switch based on an electroactive, persistent organic radical immobilized on indium tin oxide substrates that can be electrochemically and reversibly converted to the anion form. This molecular bistable system behaves as an extremely robust redox switch in which an electrical input is transduced into optical as well as magnetic outputs under ambient conditions. The fact that this molecular surface switch, operating at very low voltages, can be patterned and addressed locally, and also has exceptionally high long-term stability and excellent reversibility and reproducibility, makes it a very promising platform for non-volatile memory devices.

  3. Observation of nonvolatile resistive memory switching characteristics in Ag/graphene-oxide/Ag devices.

    PubMed

    Venugopal, Gunasekaran; Kim, Sang-Jae

    2012-11-01

    In this paper, we report highly stable and bipolar resistive switching effects of Ag/Graphene oxide thinfilm/Ag devices. The graphene-oxide (GO) thinfilms were prepared on Ag/SiO2/Si substrates by spin-coating technique. The Ag/GO/Ag devices showed a steady and bipolar resistive switching characteristic. The resistance switching from low resistance state (LRS) and high resistance state (HRS) with the resistance ratio of HRS to LRS of about 10 which was attained at a voltage bias of 0.1 V. Based on the filamentary conduction model, the dominant conduction mechanism of switching effect was well explained. Our results show GO can be a promising candidate for future development of nonvolatile memory devices.

  4. Vertically Stackable Novel One-Time Programmable Nonvolatile Memory Devices Based on Dielectric Breakdown Mechanism

    NASA Astrophysics Data System (ADS)

    Cho, Seongjae; Lee, Jung Hoon; Ryoo, Kyung-Chang; Jung, Sunghun; Lee, Jong-Ho; Park, Byung-Gook

    2011-12-01

    In this paper, a novel one-time programmable (OTP) nonvolatile memory (NVM) device and its array structures based on silicon technology are proposed. There have been many features of OTP NVM devices utilizing various combinations of channel, breakdown region, barrier, and contact materials. However, this invention can be realized by simple materials and fabrication methods: it is silicon-based materials and fully compatible with the conventional CMOS process. An individual memory cell is a silicon diode vertically integrated. Historically, OTP memories were widely used for read-only-memory (ROM) in the central processing unit (CPU) of the computer systems. By implanting the nanoscale fabrication technology into the concept of OTP memory, innovative high-density NVM appliances for massive storage media becomes very promising. The program operation is performed by breaking down the thin oxide layer between pn doped structure and wordline (WL) and its state can be sensed by the leakage current through the broken oxide. Since this invention is based on neither transistor structure nor charge-based mechanism, it is highly reliable and functional for the ultra-large scale integration. The feasibility of its stacked array will be also checked.

  5. A multilevel nonvolatile magnetoelectric memory

    NASA Astrophysics Data System (ADS)

    Shen, Jianxin; Cong, Junzhuang; Shang, Dashan; Chai, Yisheng; Shen, Shipeng; Zhai, Kun; Sun, Young

    2016-09-01

    The coexistence and coupling between magnetization and electric polarization in multiferroic materials provide extra degrees of freedom for creating next-generation memory devices. A variety of concepts of multiferroic or magnetoelectric memories have been proposed and explored in the past decade. Here we propose a new principle to realize a multilevel nonvolatile memory based on the multiple states of the magnetoelectric coefficient (α) of multiferroics. Because the states of α depends on the relative orientation between magnetization and polarization, one can reach different levels of α by controlling the ratio of up and down ferroelectric domains with external electric fields. Our experiments in a device made of the PMN-PT/Terfenol-D multiferroic heterostructure confirm that the states of α can be well controlled between positive and negative by applying selective electric fields. Consequently, two-level, four-level, and eight-level nonvolatile memory devices are demonstrated at room temperature. This kind of multilevel magnetoelectric memory retains all the advantages of ferroelectric random access memory but overcomes the drawback of destructive reading of polarization. In contrast, the reading of α is nondestructive and highly efficient in a parallel way, with an independent reading coil shared by all the memory cells.

  6. A multilevel nonvolatile magnetoelectric memory

    PubMed Central

    Shen, Jianxin; Cong, Junzhuang; Shang, Dashan; Chai, Yisheng; Shen, Shipeng; Zhai, Kun; Sun, Young

    2016-01-01

    The coexistence and coupling between magnetization and electric polarization in multiferroic materials provide extra degrees of freedom for creating next-generation memory devices. A variety of concepts of multiferroic or magnetoelectric memories have been proposed and explored in the past decade. Here we propose a new principle to realize a multilevel nonvolatile memory based on the multiple states of the magnetoelectric coefficient (α) of multiferroics. Because the states of α depends on the relative orientation between magnetization and polarization, one can reach different levels of α by controlling the ratio of up and down ferroelectric domains with external electric fields. Our experiments in a device made of the PMN-PT/Terfenol-D multiferroic heterostructure confirm that the states of α can be well controlled between positive and negative by applying selective electric fields. Consequently, two-level, four-level, and eight-level nonvolatile memory devices are demonstrated at room temperature. This kind of multilevel magnetoelectric memory retains all the advantages of ferroelectric random access memory but overcomes the drawback of destructive reading of polarization. In contrast, the reading of α is nondestructive and highly efficient in a parallel way, with an independent reading coil shared by all the memory cells. PMID:27681812

  7. An overview of advanced nonvolatile memory technologies

    SciTech Connect

    Dressendorfer, P.V.

    1991-01-01

    This report is an overview of advanced nonvolatile memory technologies. The memory technologies discussed are: floating gate nonvolatile memory technologies; SNOS nonvolatile technology; ferroelectric technology; and thin film magnetic memories.

  8. MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar memory arrays

    NASA Astrophysics Data System (ADS)

    Shenoy, Rohit S.; Burr, Geoffrey W.; Virwani, Kumar; Jackson, Bryan; Padilla, Alvaro; Narayanan, Pritish; Rettner, Charles T.; Shelby, Robert M.; Bethune, Donald S.; Raman, Karthik V.; BrightSky, Matthew; Joseph, Eric; Rice, Philip M.; Topuria, Teya; Kellock, Andrew J.; Kurdi, Bülent; Gopalakrishnan, Kailash

    2014-10-01

    Several attractive applications call for the organization of memristive devices (or other resistive non-volatile memory (NVM)) into large, densely-packed crossbar arrays. While resistive-NVM devices frequently possess some degree of inherent nonlinearity (typically 3-30× contrast), the operation of large (\\gt 1000×1000 device) arrays at low power tends to require quite large (\\gt 1e7) ON-to-OFF ratios (between the currents passed at high and at low voltages). One path to such large nonlinearities is the inclusion of a distinct access device (AD) together with each of the state-bearing resistive-NVM elements. While such an AD need not store data, its list of requirements is almost as challenging as the specifications demanded of the memory device. Several candidate ADs have been proposed, but obtaining high performance without requiring single-crystal silicon and/or the high processing temperatures of the front-end-of-the-line—which would eliminate any opportunity for 3D stacking—has been difficult. We review our work at IBM Research—Almaden on high-performance ADs based on Cu-containing mixed-ionic-electronic conduction (MIEC) materials [1-7]. These devices require only the low processing temperatures of the back-end-of-the-line, making them highly suitable for implementing multi-layer cross-bar arrays. MIEC-based ADs offer large ON/OFF ratios (\\gt 1e7), a significant voltage margin {{V}m} (over which current \\lt 10 nA), and ultra-low leakage (\\lt 10 pA), while also offering the high current densities needed for phase-change memory and the fully bipolar operation needed for high-performance RRAM. Scalability to critical lateral dimensions \\lt 30 nm and thicknesses \\lt 15 nm, tight distributions and 100% yield in large (512 kBit) arrays, long-term stability of the ultra-low leakage states, and sub-50 ns turn-ON times have all been demonstrated. Numerical modeling of these MIEC-based ADs shows that their operation depends on C{{u}+} mediated hole

  9. A Nonvolatile MOSFET Memory Device Based on Mobile Protons in SiO(2) Thin Films

    SciTech Connect

    Vanheusden, K.; Warren, W.L.; Devine, R.A.B.; Fleetwood, D.M.; Draper, B.L.; Schwank, J.R.

    1999-03-02

    It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protons are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).

  10. Nonvolatile Analog Memory

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C. (Inventor)

    2007-01-01

    A nonvolatile analog memory uses pairs of ferroelectric field effect transistors (FFETs). Each pair is defined by a first FFET and a second FFET. When an analog value is to be stored in one of the pairs, the first FFET has a saturation voltage applied thereto, and the second FFET has a storage voltage applied thereto that is indicative of the analog value. The saturation and storage voltages decay over time in accordance with a known decay function that is used to recover the original analog value when the pair of FFETs is read.

  11. High-performance nonvolatile write-once-read-many-times memory devices with ZnO nanoparticles embedded in polymethylmethacrylate

    NASA Astrophysics Data System (ADS)

    Thanh Dao, Toan; Viet Tran, Thu; Higashimine, Koichi; Okada, Hiromasa; Mott, Derrick; Maenosono, Shinya; Murata, Hideyuki

    2011-12-01

    A mixture of ZnO nanoparticles and polymethylmethacrylate was used as an active layer in a nonvolatile resistive memory device. Current-voltage characteristics of the device showed nonvolatile write-once-read-many-times memory behavior with a switching time on the order of μs. The device exhibited an on/off ratio of 104, retention time of >105 s, and number of readout of >4 × 104 times under a read voltage of 0.5 V. The emission, cross-sectional high-resolution transmission electron microscopy (TEM), scanning TEM-high angle annular dark field imaging, and energy dispersive x-ray spectroscopy elemental mapping measurements suggest that the electrical switching originates from the formation of conduction paths.

  12. Analog Nonvolatile Computer Memory Circuits

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd

    2007-01-01

    In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value

  13. Electric field mediated non-volatile tuning magnetism in CoPt/PMN-PT heterostructure for magnetoelectric memory devices

    NASA Astrophysics Data System (ADS)

    Yang, Y. T.; Li, J.; Peng, X. L.; Wang, X. Q.; Wang, D. H.; Cao, Q. Q.; Du, Y. W.

    2016-02-01

    We report a power efficient non-volatile magnetoelectric memory in the CoPt/(011)PMN-PT heterostructure. Two reversible and stable electric field induced coercivity states (i.e., high-HC or low-HC) are obtained due to the strain mediated converse magnetoelectric effect. The reading process of the different coercive field information written by electric fields is demonstrated by using a magnetoresistance read head. This result shows good prospects in the application of novel multiferroic devices.

  14. Resistive Switching in Al/Al2O3/TiO2/Al/PES Flexible Device for Nonvolatile Memory Application.

    PubMed

    Lin, Chun-Chieh; Lee, Wang-Ying; Lee, Han-Tang

    2016-05-01

    Resistive switching memory devices with superior properties are possibly used in next-generation nonvolatile memory to replace the flash memory. In addition, flexible electronics has also attracted much attention because of its light-weight and flexibility. Therefore, an Al/Al2O3/TiO2/Al/PES flexible resistive switching memory is employed in this study. The resistive switching characteristics and stability of the flexible device are improved by inserting the Al2O3 film. The resistive switching of the flexible device can be repeated over hundreds of times after the bending test. A possible resistive switching model of the flexible device is also proposed. In addition, the non-volatility of the flexible device is demonstrated. Based on our research results, the proposed Al2O3/TiO2-based resistive switching memory is possibly used in next-generation flexible electronics and nonvolatile memory applications.

  15. Controllable switching ratio in quantum dot/metal-metal oxide nanostructure based non-volatile memory device

    NASA Astrophysics Data System (ADS)

    Kannan, V.; Rhee, J. K.

    2012-07-01

    In this paper, we report a facile quantum dot/In-InOx(nanostructure)/quantum dot/In based non-volatile resistive memory device. The solution processed tri-layer structure exhibited bipolar resistive switching with a ratio of 100 between the high-resistance state and low-resistance state. The memory device was stable and functional even after 100,000 cycles of operation and it exhibited good retention characteristics. The ON/OFF switching ratio could be controlled by choosing appropriate metal in the structure. Memory operating mechanism is discussed based on charge trapping in quantum dots with InOx acting as barrier. A comparative study of memory devices consisting of aluminum and titanium in place of indium is presented. The possible reason for the variation in ON/OFF ratio is discussed on the size of the nano-sized grains of the middle metal layer.

  16. A nonvolatile memory device made of a ferroelectric polymer gate nanodot and a single-walled carbon nanotube.

    PubMed

    Son, Jong Yeog; Ryu, Sangwoo; Park, Yoon-Cheol; Lim, Yun-Tak; Shin, Yun-Sok; Shin, Young-Han; Jang, Hyun Myung

    2010-12-28

    We demonstrate a field-effect nonvolatile memory device made of a ferroelectric copolymer gate nanodot and a single-walled carbon nanotube (SW-CNT). A position-controlled dip-pen nanolithography was performed to deposit a poly(vinylidene fluoride-ran-trifluoroethylene) (PVDF-TrFE) nanodot onto the SW-CNT channel with both a source and drain for field-effect transistor (FET) function. PVDF-TrFE was chosen as a gate dielectric nanodot in order to efficiently exploit its bipolar chemical nature. A piezoelectric force microscopy study confirmed the canonical ferroelectric responses of the PVDF-TrFE nanodot fabricated at the center of the SW-CNT channel. The two distinct ferroelectric polarization states with the stable current retention and fatigue-resistant characteristics make the present PVDF-TrFE-based FET suitable for nonvolatile memory applications.

  17. Multi-floor cascading ferroelectric nanostructures: multiple data writing-based multi-level non-volatile memory devices.

    PubMed

    Hyun, Seung; Kwon, Owoong; Lee, Bom-Yi; Seol, Daehee; Park, Beomjin; Lee, Jae Yong; Lee, Ju Hyun; Kim, Yunseok; Kim, Jin Kon

    2016-01-21

    Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process.

  18. Nonvolatile and Cryogenic-Compatible Quantum Memory Devices (QuMEM)

    DTIC Science & Technology

    2016-06-01

    project is to design and implement novel concepts, designs for solid-state, cryogenic-compatible quantum memory device chips where writing , reading, and...4.3 MEMORY WRITE AND STORAGE TIMES ............................................................ 19 4.4 MODULATION OF THE AUNTUM COHERENCE LENGTH...16 13. SBIBS device concept where the write , read, and erase memory functions are achieved through low-voltage pulses resulting

  19. Nonvolatile and Cryogenic-compatible Quantum Memory Devices (QuMEM)

    DTIC Science & Technology

    2016-06-01

    project is to design and implement novel concepts, designs for solid-state, cryogenic-compatible quantum memory device chips where writing , reading, and...4.3 MEMORY WRITE AND STORAGE TIMES ............................................................ 19 4.4 MODULATION OF THE AUNTUM COHERENCE LENGTH...16 13. SBIBS device concept where the write , read, and erase memory functions are achieved through low-voltage pulses resulting

  20. Non-volatile memory for checkpoint storage

    SciTech Connect

    Blumrich, Matthias A.; Chen, Dong; Cipolla, Thomas M.; Coteus, Paul W.; Gara, Alan; Heidelberger, Philip; Jeanson, Mark J.; Kopcsay, Gerard V.; Ohmacht, Martin; Takken, Todd E.

    2014-07-22

    A system, method and computer program product for supporting system initiated checkpoints in high performance parallel computing systems and storing of checkpoint data to a non-volatile memory storage device. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity. In one embodiment, the non-volatile memory is a pluggable flash memory card.

  1. Nonvolatile Memory Technology for Space Applications

    NASA Technical Reports Server (NTRS)

    Oldham, Timothy R.; Irom, Farokh; Friendlich, Mark; Nguyen, Duc; Kim, Hak; Berg, Melanie; LaBel, Kenneth A.

    2010-01-01

    This slide presentation reviews several forms of nonvolatile memory for use in space applications. The intent is to: (1) Determine inherent radiation tolerance and sensitivities, (2) Identify challenges for future radiation hardening efforts, (3) Investigate new failure modes and effects, and technology modeling programs. Testing includes total dose, single event (proton, laser, heavy ion), and proton damage (where appropriate). Test vehicles are expected to be a variety of non-volatile memory devices as available including Flash (NAND and NOR), Charge Trap, Nanocrystal Flash, Magnetic Memory (MRAM), Phase Change--Chalcogenide, (CRAM), Ferroelectric (FRAM), CNT, and Resistive RAM.

  2. Nonvolatile random access memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor); Katti, Romney R. (Inventor)

    1994-01-01

    A nonvolatile magnetic random access memory can be achieved by an array of magnet-Hall effect (M-H) elements. The storage function is realized with a rectangular thin-film ferromagnetic material having an in-plane, uniaxial anisotropy and inplane bipolar remanent magnetization states. The thin-film magnetic element is magnetized by a local applied field, whose direction is used to form either a 0 or 1 state. The element remains in the 0 or 1 state until a switching field is applied to change its state. The stored information is detcted by a Hall-effect sensor which senses the fringing field from the magnetic storage element. The circuit design for addressing each cell includes transistor switches for providing a current of selected polarity to store a binary digit through a separate conductor overlying the magnetic element of the cell. To read out a stored binary digit, transistor switches are employed to provide a current through a row of Hall-effect sensors connected in series and enabling a differential voltage amplifier connected to all Hall-effect sensors of a column in series. To avoid read-out voltage errors due to shunt currents through resistive loads of the Hall-effect sensors of other cells in the same column, at least one transistor switch is provided between every pair of adjacent cells in every row which are not turned on except in the row of the selected cell.

  3. Characteristics of AgInSbTe-SiO2 nanocomposite thin film applied to nonvolatile floating gate memory devices.

    PubMed

    Chiang, Kuo-Chang; Hsieh, Tsung-Eong

    2010-10-22

    Nanocomposite thin films containing AgInSbTe (AIST) particles embedded in an SiO(2) matrix was prepared by sputtering deposition and its feasibility for nonvolatile floating gate memory (NFGM) was investigated. The sample subjected to a 400 °C annealing exhibited a distinct hysteresis memory window (ΔV(FB)) shift = 6.6 V and charge density = 5.2 × 10(12) cm(-2) after ± 8 V gate voltage sweep. Electrical measurement revealed the current transport is via the Schottky emission in low applied field and the space-charge-limited conduction mechanism in high applied field in the samples, regardless of their thermal history. Transmission electron microscopy and x-ray photoelectron spectroscopy indicated that the metallic Sb(2)Te nanocrystals (NCs) with diameters about 5-7 nm dispersed in a nanocomposite layer may serve as the discrete charge-storage traps for nonvolatile memory. Analytical results illustrate the utilization of an AIST-SiO(2) nanocomposite layer as the core structure of NFGM devices is able to simplify the device structure and fabrication process.

  4. Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

    NASA Astrophysics Data System (ADS)

    Hong, Augustin Jinwoo

    Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

  5. Lithography-Free Miniaturization of Resistive Nonvolatile Memory Devices to the 100 nm Scale by Glancing Angle Deposition.

    PubMed

    Ligorio, Giovanni; Nardi, Marco Vittorio; Koch, Norbert

    2017-02-08

    The scaling of nonvolatile memory (NVM) devices based on resistive filament switching to below a 100 nm(2) footprint area without employing cumbersome lithography is demonstrated. Nanocolumns of the organic semiconductor 4,4-bis[N-(1-naphthyl)-N-phenyl-amino]diphenyl (α-NPD) were grown by glancing angle deposition on a silver electrode. Individual NVM devices were electrically characterized by conductive atomic force microscopy with the tip of a conductive cantilever serving as second electrode. The resistive switching mechanism is unambiguously attributed to Ag filament formation between the electrodes. This sets the upper limit for the filament diameter to well below 100 nm. Full functionality of these NVM nanodevices is evidenced, revealing a potential memory density of >1 GB/cm(2) in appropriate architectures.

  6. Scalable processes for fabricating non-volatile memory devices using self-assembled 2D arrays of gold nanoparticles as charge storage nodes.

    PubMed

    Muralidharan, Girish; Bhat, Navakanta; Santhanam, Venugopal

    2011-11-01

    We propose robust and scalable processes for the fabrication of floating gate devices using ordered arrays of 7 nm size gold nanoparticles as charge storage nodes. The proposed strategy can be readily adapted for fabricating next generation (sub-20 nm node) non-volatile memory devices.

  7. Flexible nonvolatile memory devices based on Au/PMMA nanocomposites deposited on PEDOT:PSS/Ag nanowire hybrid electrodes

    NASA Astrophysics Data System (ADS)

    Sung, Sihyun; Kim, Tae Whan

    2017-07-01

    Flexible nonvolatile memory (NVM) devices fabricated utilizing Au nanoparticles (AuNPs) embedded in a poly(methylmethacrylate) (PMMA) layer were fabricated on a silver nanowire (AgNW) or a poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS)/AgNW coated on poly(ethylene terephthalate) (PET) substrates. The transmittance and the sheet resistance of the PEDOT:PSS/AgNW hybrid layer were approximately 89% and 50 Ω/sq, respectively, which were comparable to the values for commercial indium-tin-oxide (ITO) electrodes. Current-voltage curves for the Al/PMMA:AuNP/PEDOT:PSS/AgNW/PET devices at 300 K showed clockwise current hysteresis behaviors due to the existence of the AuNPs. The endurance number of ON/OFF switching for the NVM devices was above 30 cycles. An ON/OFF ratio of 1 × 103 was maintained for retention times longer than 1 × 104 s. The maximum memory margins of the NVM devices before and after bending were approximately 3.4 × 103 and 1.4 × 103, respectively. The retention times of the devices before and after bending remained same 1 × 104 s. The memory margin and the stability of flexible NVMs fabricated on AgNW electrodes were enhanced due to the embedded PEDOT:PSS buffer layer.

  8. Polymer-ultrathin graphite sheet-polymer composite structured flexible nonvolatile bistable organic memory devices

    NASA Astrophysics Data System (ADS)

    Ick Son, Dong; Shim, Jae Ho; Park, Dong Hee; Jung, Jae Hun; Lee, Jung Min; Park, Won Il; Kim, Tae Whan; Choi, Won Kook

    2011-07-01

    We present data, which were obtained before bending and after bending, for the electrical bistabilities, memory stabilities, and memory mechanisms of three-layer structured flexible bistable organic memory (BOM) devices, which were fabricated utilizing the ultrathin graphite sheets (UGS) sandwiched between insulating poly(methylmethacrylate) (PMMA) polymer layers. The UGS were formed by transferring UGS (about 30 layers) and using a simple spin-coating technique. Transmission electron microscopy (TEM) measurements were performed to investigate the microstructural properties of the PMMA/UGS/PMMA films. Current-voltage (I-V) measurements were carried out to investigate the electrical properties of the BOM devices containing the UGS embedded in the PMMA polymer. Current-time (I-t) and current-cycle measurements under flat and bent conditions were performed to investigate the memory stabilities of the BOM devices. The memory characteristics of the BOM maintained similar device efficiencies after bending and were stable during repeated bendings of the BOM devices. The mechanisms for these characteristics of the fabricated BOM are described on the basis of the I-V results.

  9. Bipolar resistive switching in Cu/AlN/Pt nonvolatile memory device

    NASA Astrophysics Data System (ADS)

    Chen, C.; Yang, Y. C.; Zeng, F.; Pan, F.

    2010-08-01

    Highly stable and reproducible bipolar resistive switching effects are reported on Cu/AlN/Pt devices. Memory characteristics including large memory window of 103, long retention time of >106 s and good endurance of >103 were demonstrated. It is concluded that the reset current decreases as compliance current decreases, which provides an approach to suppress power consumption. The dominant conduction mechanisms of low resistance state and high resistance state were verified by Ohmic behavior and trap-controlled space charge limited current, respectively. The memory effect is explained by the model concerning redox reaction mediated formation and rupture of the conducting filament in AlN films.

  10. Nonvolatile multilevel data storage memory device from controlled ambipolar charge trapping mechanism

    PubMed Central

    Zhou, Ye; Han, Su-Ting; Sonar, Prashant; Roy, V. A. L.

    2013-01-01

    The capability of storing multi-bit information is one of the most important challenges in memory technologies. An ambipolar polymer which intrinsically has the ability to transport electrons and holes as a semiconducting layer provides an opportunity for the charge trapping layer to trap both electrons and holes efficiently. Here, we achieved large memory window and distinct multilevel data storage by utilizing the phenomena of ambipolar charge trapping mechanism. As fabricated flexible memory devices display five well-defined data levels with good endurance and retention properties showing potential application in printed electronics. PMID:23900459

  11. Nonvolatile multilevel data storage memory device from controlled ambipolar charge trapping mechanism.

    PubMed

    Zhou, Ye; Han, Su-Ting; Sonar, Prashant; Roy, V A L

    2013-01-01

    The capability of storing multi-bit information is one of the most important challenges in memory technologies. An ambipolar polymer which intrinsically has the ability to transport electrons and holes as a semiconducting layer provides an opportunity for the charge trapping layer to trap both electrons and holes efficiently. Here, we achieved large memory window and distinct multilevel data storage by utilizing the phenomena of ambipolar charge trapping mechanism. As fabricated flexible memory devices display five well-defined data levels with good endurance and retention properties showing potential application in printed electronics.

  12. Overview of emerging nonvolatile memory technologies.

    PubMed

    Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  13. Overview of emerging nonvolatile memory technologies

    PubMed Central

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  14. Nonvolatile Memory Based on Nonlinear Magnetoelectric Effects

    NASA Astrophysics Data System (ADS)

    Shen, Jianxin; Cong, Junzhuang; Chai, Yisheng; Shang, Dashan; Shen, Shipeng; Zhai, Kun; Tian, Ying; Sun, Young

    2016-08-01

    The magnetoelectric effects in multiferroics have a great potential in creating next-generation memory devices. We use an alternative concept of nonvolatile memory based, on a type of nonlinear magnetoelectric effects showing a butterfly-shaped hysteresis loop. The principle is to utilize the states of the magnetoelectric coefficient, instead of magnetization, electric polarization, or resistance, to store binary information. Our experiments in a device made of the PMN-PT/Terfenol-D multiferroic heterostructure clearly demonstrate that the sign of the magnetoelectric coefficient can be repeatedly switched between positive and negative by applying electric fields, confirming the feasibility of this principle. This kind of nonvolatile memory has outstanding practical virtues such as simple structure, easy operation in writing and reading, low power, fast speed, and diverse materials available.

  15. Enhancing charge-storage capacity of non-volatile memory devices using template-directed assembly of gold nanoparticles.

    PubMed

    Gupta, Raju Kumar; Krishnamoorthy, Sivashankar; Kusuma, Damar Yoga; Lee, Pooi See; Srinivasan, M P

    2012-04-07

    We demonstrate the controlled fabrication of aggregates of gold nanoparticles as a means of enhancing the charge-storage capacity of metal-insulator-semiconductor (MIS) devices by up to 300% at a low biasing voltage of ±4 V. Aggregates of citrate stabilized gold nanoparticles were obtained by directed electrostatic self-assembly onto an underlying nanopattern of positively charged centers. The underlying nanopatterns consist of amine functionalized gold nanoparticle arrays formed using amphiphilic diblock copolymer reverse micelles as templates. The hierarchical self-organization leads to a twelve-fold increase in the number density of the gold nanoparticles and therefore significantly increases the charge storage centers for the MIS device. The MIS structure showed counterclockwise C-V hysteresis curves indicating a good memory effect. A memory window of 1 V was obtained at a low biasing voltage of ±4 V. Furthermore, C-t measurements conducted after applying a charging bias of 4 V showed that the charge was retained beyond 20,000 s. The proposed strategy can be readily adapted for fabricating next generation solution processible non-volatile memory devices.

  16. Non-volatile transistor memory devices using charge storage cross-linked core-shell nanoparticles.

    PubMed

    Lo, Chen-Tsyr; Watanabe, Yu; Oya, Hiroshi; Nakabayashi, Kazuhiro; Mori, Hideharu; Chen, Wen-Chang

    2016-06-07

    Solution processable cross-linked core-shell poly[poly(ethylene glycol)methylether methacrylate]-block-poly(2,5-dibromo-3-vinylthiophene) (poly(PEGMA)m-b-poly(DB3VT)n) nanoparticles are firstly explored as charge storage materials for transistor-type memory devices owing to their efficient and controllable ability in electric charge transfer and trapping.

  17. Flexible graphene-PZT ferroelectric nonvolatile memory

    NASA Astrophysics Data System (ADS)

    Lee, Wonho; Kahya, Orhan; Tat Toh, Chee; Özyilmaz, Barbaros; Ahn, Jong-Hyun

    2013-11-01

    We report the fabrication of a flexible graphene-based nonvolatile memory device using Pb(Zr0.35,Ti0.65)O3 (PZT) as the ferroelectric material. The graphene and PZT ferroelectric layers were deposited using chemical vapor deposition and sol-gel methods, respectively. Such PZT films show a high remnant polarization (Pr) of 30 μC cm-2 and a coercive voltage (Vc) of 3.5 V under a voltage loop over ±11 V. The graphene-PZT ferroelectric nonvolatile memory on a plastic substrate displayed an on/off current ratio of 6.7, a memory window of 6 V and reliable operation. In addition, the device showed one order of magnitude lower operation voltage range than organic-based ferroelectric nonvolatile memory after removing the anti-ferroelectric behavior incorporating an electrolyte solution. The devices showed robust operation in bent states of bending radii up to 9 mm and in cycling tests of 200 times. The devices exhibited remarkable mechanical properties and were readily integrated with plastic substrates for the production of flexible circuits.

  18. Towards the development of flexible non-volatile memories.

    PubMed

    Han, Su-Ting; Zhou, Ye; Roy, V A L

    2013-10-11

    Flexible non-volatile memories have attracted tremendous attentions for data storage for future electronics application. From device perspective, the advantages of flexible memory devices include thin, lightweight, printable, foldable and stretchable. The flash memories, resistive random access memories (RRAM) and ferroelectric random access memory/ferroelectric field-effect transistor memories (FeRAM/FeFET) are considered as promising candidates for next generation non-volatile memory device. Here, we review the general background knowledge on device structure, working principle, materials, challenges and recent progress with the emphasis on the flexibility of above three categories of non-volatile memories. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  19. Characteristics of resistive switching in ZnO/SiO x multi-layers for transparent nonvolatile memory devices

    NASA Astrophysics Data System (ADS)

    Kim, Kyongmin; Kim, Eunkyeom; Kim, Youngill; Sok, Jung Hyun; Park, Kyoungwan

    2016-12-01

    Bipolar resistive switching in ZnO/SiO x bi-layer and ZnO/SiO x /ZnO tri-layer structures was investigated for nonvolatile memory applications. ZnO thin films were grown using the radiofrequency magnetron sputtering technique at room temperature. SiO x films were grown using plasma-enhanced chemical-vapor deposition at 200 °C. Multiple high-resistance states were observed during the set process. The high/low resistance state ratio was 10 during 100 on/off cycles. The tri-layer memory device exhibited better endurance properties than the bi-layer device. Because an asymmetric conducting filament has a weak point for charge conduction at the oxide interfaces, we attributed the good endurance property to the reproducible formation/rupture of "micro"-conducting filaments. Moreover, the dynamics of the oxygen ions in the SiO x layer plays an important role in resistive switching.

  20. The impact of tunnel oxide nitridation to reliability performance of charge storage non-volatile memory devices.

    PubMed

    Lee, Meng Chuan; Wong, Hin Yong

    2014-02-01

    This paper is written to review the development of critical research on the overall impact of tunnel oxide nitridation (TON) with the aim to mitigate reliability issues due to incessant technology scaling of charge storage NVM devices. For more than 30 years, charge storage non-volatile memory (NVM) has been critical in the evolution of intelligent electronic devices and continuous development of integrated technologies. Technology scaling is the primary strategy implemented throughout the semiconductor industry to increase NVM density and drive down average cost per bit. In this paper, critical reliability challenges and key innovative technical mitigation methods are reviewed. TON is one of the major candidates to replace conventional oxide layer for its superior quality and reliability performance. Major advantages and caveats of key TON process techniques are discussed. The impact of TON on quality and reliability performance of charge storage NVM devices is carefully reviewed with emphasis on major advantages and drawbacks of top and bottom nitridation. Physical mechanisms attributed to charge retention and V(t) instability phenomenon are also reviewed in this paper.

  1. Cellulose Nanofiber Paper as an Ultra Flexible Nonvolatile Memory

    PubMed Central

    Nagashima, Kazuki; Koga, Hirotaka; Celano, Umberto; Zhuge, Fuwei; Kanai, Masaki; Rahong, Sakon; Meng, Gang; He, Yong; De Boeck, Jo; Jurczak, Malgorzata; Vandervorst, Wilfried; Kitaoka, Takuya; Nogi, Masaya; Yanagida, Takeshi

    2014-01-01

    On the development of flexible electronics, a highly flexible nonvolatile memory, which is an important circuit component for the portability, is necessary. However, the flexibility of existing nonvolatile memory has been limited, e.g. the smallest radius into which can be bent has been millimeters range, due to the difficulty in maintaining memory properties while bending. Here we propose the ultra flexible resistive nonvolatile memory using Ag-decorated cellulose nanofiber paper (CNP). The Ag-decorated CNP devices showed the stable nonvolatile memory effects with 6 orders of ON/OFF resistance ratio and the small standard deviation of switching voltage distribution. The memory performance of CNP devices can be maintained without any degradation when being bent down to the radius of 350 μm, which is the smallest value compared to those of existing any flexible nonvolatile memories. Thus the present device using abundant and mechanically flexible CNP offers a highly flexible nonvolatile memory for portable flexible electronics. PMID:24985164

  2. Multilevel characteristics and memory mechanisms for nonvolatile memory devices based on CuInS{sub 2} quantum dot-polymethylmethacrylate nanocomposites

    SciTech Connect

    Zhou, Yang; Yun, Dong Yeol; Kim, Tae Whan; Kim, Sang Wook

    2014-12-08

    Nonvolatile memory devices based on CuInS{sub 2} (CIS) quantum dots (QDs) embedded in a polymethylmethacrylate (PMMA) layer were fabricated using spin-coating method. The memory window widths of the capacitance-voltage (C-V) curves for the Al/CIS QDs embedded in PMMA layer/p-Si devices were 0.3, 0.6, and 1.0 V for sweep voltages of ±3, ±5, and ±7 V, respectively. Capacitance-cycle data demonstrated that the charge-trapping capability of the devices with an ON/OFF ratio value of 2.81 × 10{sup −10} was maintained for 8 × 10{sup 3} cycles without significant degradation and that the extrapolation of the ON/OFF ratio value to 1 × 10{sup 6} cycles converged to 2.40 × 10{sup −10}, indicative of the good stability of the devices. The memory mechanisms for the devices are described on the basis of the C-V curves and the energy-band diagrams.

  3. Electrical reliability, multilevel data storage and mechanical stability of MoS2-PMMA nanocomposite-based non-volatile memory device

    NASA Astrophysics Data System (ADS)

    Bhattacharjee, Snigdha; Sarkar, Pranab Kumar; Prajapat, Manoj; Roy, Asim

    2017-07-01

    Molybdenum disulfide (MoS2) is of great interest for its applicability in various optoelectronic devices. Here we report the resistive switching properties of polymethylmethacrylate embedding MoS2 nano-crystals. The devices are developed on an ITO-coated PET substrate with copper as the top electrode. Systematic evaluation of resistive switching parameters, on the basis of MoS2 content, suggests non-volatile memory characteristics. A decent ON/OFF ratio, high retention time and long endurance of 3  ×  103, 105 s and 105 cycles are respectively recorded in a device with 1 weight percent (wt%) of MoS2. The bending cyclic measurements confirm the flexibility of the memory devices with good electrical reliability as well as mechanical stability. In addition, multilevel storage has been demonstrated by controlling the current compliance and span of voltage sweeping in the memory device.

  4. Black phosphorus nonvolatile transistor memory

    NASA Astrophysics Data System (ADS)

    Lee, Dain; Choi, Yongsuk; Hwang, Euyheon; Kang, Moon Sung; Lee, Seungwoo; Cho, Jeong Ho

    2016-04-01

    We demonstrated nanofloating gate transistor memory devices (NFGTMs) using mechanically-exfoliated few-layered black phosphorus (BP) channels and gold nanoparticle (AuNPs) charge trapping layers. The resulting BP-NFGTMs exhibited excellent memory performances, including the five-level data storage, large memory window (58.2 V), stable retention (104 s), and cyclic endurance (1000 cycles).We demonstrated nanofloating gate transistor memory devices (NFGTMs) using mechanically-exfoliated few-layered black phosphorus (BP) channels and gold nanoparticle (AuNPs) charge trapping layers. The resulting BP-NFGTMs exhibited excellent memory performances, including the five-level data storage, large memory window (58.2 V), stable retention (104 s), and cyclic endurance (1000 cycles). Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr02078j

  5. Securing non-volatile memory regions

    DOEpatents

    Faraboschi, Paolo; Ranganathan, Parthasarathy; Muralimanohar, Naveen

    2013-08-20

    Methods, apparatus and articles of manufacture to secure non-volatile memory regions are disclosed. An example method disclosed herein comprises associating a first key pair and a second key pair different than the first key pair with a process, using the first key pair to secure a first region of a non-volatile memory for the process, and using the second key pair to secure a second region of the non-volatile memory for the same process, the second region being different than the first region.

  6. Nonvolatile memory technology at Sandia National Laboratories

    SciTech Connect

    Sokel, R.J.; Dodson, W.H.; Knoll, M.G.

    1981-01-01

    The nonvolatile memory program at Sandia National Laboratories is discussed with special emphasis on the relationship between technology and design. Three different MNOS technologies which have been developed for EAROM, RAM, and EEPROM applications are considered.

  7. Flexible non-volatile optical memory thin-film transistor device with over 256 distinct levels based on an organic bicomponent blend

    NASA Astrophysics Data System (ADS)

    Leydecker, Tim; Herder, Martin; Pavlica, Egon; Bratina, Gvido; Hecht, Stefan; Orgiu, Emanuele; Samorì, Paolo

    2016-09-01

    Organic nanomaterials are attracting a great deal of interest for use in flexible electronic applications such as logic circuits, displays and solar cells. These technologies have already demonstrated good performances, but flexible organic memories are yet to deliver on all their promise in terms of volatility, operational voltage, write/erase speed, as well as the number of distinct attainable levels. Here, we report a multilevel non-volatile flexible optical memory thin-film transistor based on a blend of a reference polymer semiconductor, namely poly(3-hexylthiophene), and a photochromic diarylethene, switched with ultraviolet and green light irradiation. A three-terminal device featuring over 256 (8 bit storage) distinct current levels was fabricated, the memory states of which could be switched with 3 ns laser pulses. We also report robustness over 70 write-erase cycles and non-volatility exceeding 500 days. The device was implemented on a flexible polyethylene terephthalate substrate, validating the concept for integration into wearable electronics and smart nanodevices.

  8. Flexible non-volatile optical memory thin-film transistor device with over 256 distinct levels based on an organic bicomponent blend.

    PubMed

    Leydecker, Tim; Herder, Martin; Pavlica, Egon; Bratina, Gvido; Hecht, Stefan; Orgiu, Emanuele; Samorì, Paolo

    2016-09-01

    Organic nanomaterials are attracting a great deal of interest for use in flexible electronic applications such as logic circuits, displays and solar cells. These technologies have already demonstrated good performances, but flexible organic memories are yet to deliver on all their promise in terms of volatility, operational voltage, write/erase speed, as well as the number of distinct attainable levels. Here, we report a multilevel non-volatile flexible optical memory thin-film transistor based on a blend of a reference polymer semiconductor, namely poly(3-hexylthiophene), and a photochromic diarylethene, switched with ultraviolet and green light irradiation. A three-terminal device featuring over 256 (8 bit storage) distinct current levels was fabricated, the memory states of which could be switched with 3 ns laser pulses. We also report robustness over 70 write-erase cycles and non-volatility exceeding 500 days. The device was implemented on a flexible polyethylene terephthalate substrate, validating the concept for integration into wearable electronics and smart nanodevices.

  9. Investigation of charge trapping mechanism for nanocrystal-based organic nonvolatile floating gate memory devices by band structure analysis

    NASA Astrophysics Data System (ADS)

    Lee, Dong-Hoon; Lim, Ki-Tae; Park, Eung-Kyu; Shin, Ha-Chul; Kim, Chung Soo; Park, Kee-Chan; Ahn, Joung-Real; Bang, Jin Ho; Kim, Yong-Sang

    2016-05-01

    This paper investigates the charge trapping mechanism and electrical performance of CdSe nanocrystals, such as nanoparticles and nanowires in organic floating gate memory devices. Despite of same chemical component, each nanocrystals show different electrical performances with distinct trapping mechanism. CdSe nanoparticles trap holes in the memory device; on the contrary, nanowires trap electrons. This phenomenon is mainly due to the difference of energy band structures between nanoparticles and nanowires, measured by the ultraviolet photoelectron spectroscopy. Also, we investigated the memory performance with C- V characteristics, charging and discharging phenomena, and retention time. The nanoparticle based hole trapping memory device has large memory window while the nanowire based electron trapping memory shows a narrow memory window. In spite of narrow memory window, the nanowire based memory device shows better retention performance of about 55% of the charge even after 104 sec of charging. The contrasting performance of nanoparticle and nanowire is attributed to the difference in their energy band and the morphology of thin layer in the device. [Figure not available: see fulltext.

  10. 2K nonvolatile shadow RAM and 265K EEPROM SONOS nonvolatile memory development

    SciTech Connect

    Nasby, R.D.; Murray, J.R.; Habermehl, S.D.; Bennett, R.S.; Tafoya-Porras, B.C.; Mahl, P.R.; Rodriguez, J.L.; Jones, R.V.; Knoll, M.G.

    1998-07-01

    This paper describes Silicon Oxide Nitride Oxide Semiconductor (SONOS) nonvolatile memory development at Sandia National Laboratories. A 256K EEPROM nonvolatile memory and a 2K nonvolatile shadow RAM are under development using an n-channel SONOS memory technology. The technology has 1.2 {micro}m minimum features in a twin well design using shallow trench isolation.

  11. Non-volatile resistive memory device fabricated from CdSe quantum dot embedded in thermally grown In2O3 nanostructure by oblique angle deposition

    NASA Astrophysics Data System (ADS)

    Kannan, V.; Kim, Hyun-Seok; Park, Hyun-Chang

    2016-11-01

    In this paper we report In2O3/CdSe quantum dot based non-volatile resistive memory device with ON/OFF ratio ∼1000. Indium nanostructures were grown by oblique angle deposition technique in a thermal evaporator. Indium oxide nanostructures had size ranging from 20 nm to 100 nm as observed from TEM and AFM methods. The facile device fabricated with a layer of CdSe quantum dot on indium oxide film exhibited excellent endurance characteristics over 100,000 switching cycles. Retention tests showed good stability for over 4000 s. Memory operating mechanism is proposed based on charge trapping/de-trapping in quantum dots with indium oxide acting as barrier leading to Coulomb blockade. The mechanism is supported by negative differential resistance (NDR) observed exclusively in the ON state.

  12. High-resolution transmission electron microscopy study of 1.5 nm ultrathin tunnel oxides of metal-nitride-oxide-silicon nonvolatile memory devices

    NASA Astrophysics Data System (ADS)

    Kamigaki, Yoshiaki; Minami, Shin-ichi; Shimotsu, Teruho

    1988-12-01

    Metal-nitride-oxide-silicon (MNOS) nonvolatile memory devices have an ultrathin tunnel oxide SiO2 layer and a signal-charge-stored nitride Si3N4 layer. Using high-resolution transmission electron microscopy (TEM), the cross-sectional structure of MNOS devices has been observed for the first time, including direct observation of tunnel SiO2. The following is revealed: (1) Tunnel SiO2 of 1.5 nm thickness is fabricated very uniformly on the surface of a Si substrate. (2) No mixing of tunnel SiO2 and Si3N4 is observed even though tunnel SiO2 is extremely thin. As a result, we can suggest that tunnel SiO2 in a MNOS device exhibits very stable morphology and stoichiometry characteristics.

  13. Non-volatile memory based on the ferroelectric photovoltaic effect

    PubMed Central

    Guo, Rui; You, Lu; Zhou, Yang; Shiuh Lim, Zhi; Zou, Xi; Chen, Lang; Ramesh, R.; Wang, Junling

    2013-01-01

    The quest for a solid state universal memory with high-storage density, high read/write speed, random access and non-volatility has triggered intense research into new materials and novel device architectures. Though the non-volatile memory market is dominated by flash memory now, it has very low operation speed with ~10 μs programming and ~10 ms erasing time. Furthermore, it can only withstand ~105 rewriting cycles, which prevents it from becoming the universal memory. Here we demonstrate that the significant photovoltaic effect of a ferroelectric material, such as BiFeO3 with a band gap in the visible range, can be used to sense the polarization direction non-destructively in a ferroelectric memory. A prototype 16-cell memory based on the cross-bar architecture has been prepared and tested, demonstrating the feasibility of this technique. PMID:23756366

  14. Investing the effectiveness of retention performance in a non-volatile floating gate memory device with a core-shell structure of CdSe nanoparticles

    NASA Astrophysics Data System (ADS)

    Lee, Dong-Hoon; Kim, Jung-Min; Lim, Ki-Tae; Cho, Hyeong Jun; Bang, Jin Ho; Kim, Yong-Sang

    2016-03-01

    In this paper, we empirically investigate the retention performance of organic non-volatile floating gate memory devices with CdSe nanoparticles (NPs) as charge trapping elements. Core-structured CdSe NPs or core-shell-structured ZnS/CdSe NPs were mixed in PMMA and their performance in pentacene based device was compared. The NPs and self-organized thin tunneling PMMA inside the devices exhibited hysteresis by trapping hole during capacitance-voltage characterization. Despite of core-structured NPs showing a larger memory window, the retention time was too short to be adopted by an industry. By contrast core-shell structured NPs showed an improved retention time of >10000 seconds than core-structure NCs. Based on these results and the energy band structure, we propose the retention mechanism of each NPs. This investigation of retention performance provides a comparative and systematic study of the charging/discharging behaviors of NPs based memory devices. [Figure not available: see fulltext.

  15. GaAs metal-oxide-semiconductor based non-volatile flash memory devices with InAs quantum dots as charge storage nodes

    SciTech Connect

    Islam, Sk Masiul Chowdhury, Sisir; Sarkar, Krishnendu; Nagabhushan, B.; Banerji, P.; Chakraborty, S.

    2015-06-24

    Ultra-thin InP passivated GaAs metal-oxide-semiconductor based non-volatile flash memory devices were fabricated using InAs quantum dots (QDs) as charge storing elements by metal organic chemical vapor deposition technique to study the efficacy of the QDs as charge storage elements. The grown QDs were embedded between two high-k dielectric such as HfO{sub 2} and ZrO{sub 2}, which were used for tunneling and control oxide layers, respectively. The size and density of the QDs were found to be 5 nm and 1.8×10{sup 11} cm{sup −2}, respectively. The device with a structure Metal/ZrO{sub 2}/InAs QDs/HfO{sub 2}/GaAs/Metal shows maximum memory window equivalent to 6.87 V. The device also exhibits low leakage current density of the order of 10{sup −6} A/cm{sup 2} and reasonably good charge retention characteristics. The low value of leakage current in the fabricated memory device is attributed to the Coulomb blockade effect influenced by quantum confinement as well as reduction of interface trap states by ultra-thin InP passivation on GaAs prior to HfO{sub 2} deposition.

  16. A simple device unit consisting of all NiO storage and switch elements for multilevel terabit nonvolatile random access memory.

    PubMed

    Lee, Myoung-Jae; Ahn, Seung-Eon; Lee, Chang Bum; Kim, Chang-Jung; Jeon, Sanghun; Chung, U-In; Yoo, In-Kyeong; Park, Gyeong-Su; Han, Seungwu; Hwang, In Rok; Park, Bae-Ho

    2011-11-01

    Present charge-based silicon memories are unlikely to reach terabit densities because of scaling limits. As the feature size of memory shrinks to just tens of nanometers, there is insufficient volume available to store charge. Also, process temperatures higher than 800 °C make silicon incompatible with three-dimensional (3D) stacking structures. Here we present a device unit consisting of all NiO storage and switch elements for multilevel terabit nonvolatile random access memory using resistance switching. It is demonstrated that NiO films are scalable to around 30 nm and compatible with multilevel cell technology. The device unit can be a building block for 3D stacking structure because of its simple structure and constituent, high performance, and process temperature lower than 300 °C. Memory resistance switching of NiO storage element is accompanied by an increase in density of grain boundary while threshold resistance switching of NiO switch element is controlled by current flowing through NiO film.

  17. Serial nonvolatile 1024 bit MNOS memory

    SciTech Connect

    Dodson, W. H.; Sokel, R. J.

    1980-01-01

    The characteristics and operation of a nonvolatile MNOS sequential memory designed and built by Sandia National Laboratories for DOD are described. First, a general description and block diagram are presented, followed by the power, voltage, clock and address requirements, and then operating descriptions for the control and data signals. 1 figure, 1 table.

  18. A new model for the discharge behaviour of metal-nitride-oxide-silicon (MNOS) non-volatile memory devices

    NASA Astrophysics Data System (ADS)

    Heyns, Guido L.; Maes, Herman E.

    1987-10-01

    A new model is presented for the discharge mechanism of MNOS memory devices. For moderate and large charge contents the discharging effect can actually be ascribed to the compensation of the stored charge by the injection from the silicon into the nitride of carriers of the opposite type.

  19. Concept of nonvolatile memory based on multiwall carbon nanotubes.

    PubMed

    Maslov, Leonid

    2006-05-28

    In this study, a novel concept is proposed for molecular electronics that uses vertically aligned multiwall carbon nanotubes as nonvolatile memory elements. Nanotubes grown on a patterned substrate may be opened by partially deleting the outer molecular layer or layers, so that the inner core is able to move along the vertical tube axis. Mounting another dielectric plate above the nanotube forest at a specific distance from the tube caps can provide two stable van der Waals states of the inner core, providing for nonvolatile data storage. A device built using this architecture can function as a two-dimensional memory array. At each cross point in the array, a multiwall carbon nanotube exists in either the separated off-state or in the contact on-state, and can be switched between these states by applying voltage pulses at the corresponding electrodes. A theoretical memory density as high as 10(13) memory elements per square centimetre is possible, with an operation frequency exceeding 100 GHz. Significant physical characteristics of such a device are bi-stability and reversibility. Such a device can function both as nonvolatile random access memory and as terabit solid-state storage.

  20. Concept of nonvolatile memory based on multiwall carbon nanotubes

    NASA Astrophysics Data System (ADS)

    Maslov, Leonid

    2006-05-01

    In this study, a novel concept is proposed for molecular electronics that uses vertically aligned multiwall carbon nanotubes as nonvolatile memory elements. Nanotubes grown on a patterned substrate may be opened by partially deleting the outer molecular layer or layers, so that the inner core is able to move along the vertical tube axis. Mounting another dielectric plate above the nanotube forest at a specific distance from the tube caps can provide two stable van der Waals states of the inner core, providing for nonvolatile data storage. A device built using this architecture can function as a two-dimensional memory array. At each cross point in the array, a multiwall carbon nanotube exists in either the separated off-state or in the contact on-state, and can be switched between these states by applying voltage pulses at the corresponding electrodes. A theoretical memory density as high as 1013 memory elements per square centimetre is possible, with an operation frequency exceeding 100 GHz. Significant physical characteristics of such a device are bi-stability and reversibility. Such a device can function both as nonvolatile random access memory and as terabit solid-state storage.

  1. SONOS Nonvolatile Memory Cell Programming Characteristics

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

    2010-01-01

    Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory is gaining favor over conventional EEPROM FLASH memory technology. This paper characterizes the SONOS write operation using a nonquasi-static MOSFET model. This includes floating gate charge and voltage characteristics as well as tunneling current, voltage threshold and drain current characterization. The characterization of the SONOS memory cell predicted by the model closely agrees with experimental data obtained from actual SONOS memory cells. The tunnel current, drain current, threshold voltage and read drain current all closely agreed with empirical data.

  2. Characterization of an Autonomous Non-Volatile Ferroelectric Memory Latch

    NASA Technical Reports Server (NTRS)

    John, Caroline S.; MacLeod, Todd C.; Evans, Joe; Ho, Fat D.

    2011-01-01

    We present the electrical characterization of an autonomous non-volatile ferroelectric memory latch using the principle that when an electric field is applied to a ferroelectriccapacitor,the positive and negative remnant polarization charge states of the capacitor are denoted as either data 0 or data 1. The properties of the ferroelectric material to store an electric polarization in the absence of an electric field make the device non-volatile. Further the memory latch is autonomous as it operates with the ground, power and output node connections, without any externally clocked control line. The unique quality of this latch circuit is that it can be written when powered off. The advantages of this latch over flash memories are: a) It offers unlimited reads/writes b) works on symmetrical read/write cycles. c) The latch is asynchronous. The circuit was initially developed by Radiant Technologies Inc., Albuquerque, New Mexico.

  3. EDITORIAL: Non-volatile memory based on nanostructures Non-volatile memory based on nanostructures

    NASA Astrophysics Data System (ADS)

    Kalinin, Sergei; Yang, J. Joshua; Demming, Anna

    2011-06-01

    Non-volatile memory refers to the crucial ability of computers to store information once the power source has been removed. Traditionally this has been achieved through flash, magnetic computer storage and optical discs, and in the case of very early computers paper tape and punched cards. While computers have advanced considerably from paper and punched card memory devices, there are still limits to current non-volatile memory devices that restrict them to use as secondary storage from which data must be loaded and carefully saved when power is shut off. Denser, faster, low-energy non-volatile memory is highly desired and nanostructures are the critical enabler. This special issue on non-volatile memory based on nanostructures describes some of the new physics and technology that may revolutionise future computers. Phase change random access memory, which exploits the reversible phase change between crystalline and amorphous states, also holds potential for future memory devices. The chalcogenide Ge2Sb2Te5 (GST) is a promising material in this field because it combines a high activation energy for crystallization and a relatively low crystallization temperature, as well as a low melting temperature and low conductivity, which accommodates localized heating. Doping is often used to lower the current required to activate the phase change or 'reset' GST but this often aggravates other problems. Now researchers in Korea report in-depth studies of SiO2-doped GST and identify ways of optimising the material's properties for phase-change random access memory [1]. Resistance switching is an area that has attracted a particularly high level of interest for non-volatile memory technology, and a great deal of research has focused on the potential of TiO2 as a model system in this respect. Researchers at HP labs in the US have made notable progress in this field, and among the work reported in this special issue they describe means to control the switch resistance and show

  4. Reconfigurable Electronics and Non-Volatile Memory Research

    DTIC Science & Technology

    2011-10-14

    of 20 fF to 500 pF, tunable by application of a short (ns) low amplitude (ə V) pulse. The capacitance is selected by the pulse amplitude. US patent...reconfigurable electronics applications and/or non-volatile memory. The grant enabled the development of microfabrication processes for exotic materials... capacitance . Additionally, devices displaying memristive behavior were discovered. This work resulted in two additional AFRL collaborations, an AFRL

  5. Graphene nonvolatile memory prototype based on charge-transfer mechanism

    NASA Astrophysics Data System (ADS)

    Lv, Hongming; Wu, Huaqiang; Huang, Can; Wang, Yuda; Qian, He

    2014-04-01

    A graphene nonvolatile memory (GNVM) prototype based on charge transfer between the graphene layer and the NH2(CH2)3Si(OEt)3 (APTES) self-assembled monolayer (SAM) is demonstrated. Graphene was transferred to an APTES-SAM-engineered SiO2 substrate and patterned into bottom-gate transistors. Owing to the charge trapping/detrapping property of the nitrogen atoms in APTES, a significant and reproducible transfer curve hysteresis is observed. Memory performance metrics, including retention and endurance, are reported. Comparisons between vacuum and ambient environment test results indicate air absorbates’ detrimental effect. Loss of nonvolatile storage is explained on the basis of a two-layer tunneling junction model, which sheds light on further device improvement through aminosilane molecule structure optimization.

  6. Nonvolatile semiconductor memory having three dimension charge confinement

    DOEpatents

    Dawson, L. Ralph; Osbourn, Gordon C.; Peercy, Paul S.; Weaver, Harry T.; Zipperian, Thomas E.

    1991-01-01

    A layered semiconductor device with a nonvolatile three dimensional memory comprises a storage channel which stores charge carriers. Charge carriers flow laterally through the storage channel from a source to a drain. Isolation material, either a Schottky barrier or a heterojunction, located in a trench of an upper layer controllably retains the charge within the a storage portion determined by the confining means. The charge is retained for a time determined by the isolation materials' nonvolatile characteristics or until a change of voltage on the isolation material and the source and drain permit a read operation. Flow of charge through an underlying sense channel is affected by the presence of charge within the storage channel, thus the presences of charge in the memory can be easily detected.

  7. Parallel programmable nonvolatile memory using ordinary static random access memory cells

    NASA Astrophysics Data System (ADS)

    Mizutani, Tomoko; Takeuchi, Kiyoshi; Saraya, Takuya; Shinohara, Hirofumi; Kobayashi, Masaharu; Hiramoto, Toshiro

    2017-04-01

    A technique of using an ordinary static random access memory (SRAM) array for a programmable nonvolatile (NV) memory is proposed. The parallel NV writing of the entire array is achieved by simply applying high-voltage stress to the power supply terminal, after storing inverted desired data in the static random access memory (SRAM) array. Successful 2 kbit NV writing is demonstrated using a device-matrix-array (DMA) test element group (TEG) fabricated by 0.18 µm technology.

  8. Non-volatile magnetic random access memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Stadler, Henry L. (Inventor); Wu, Jiin-Chuan (Inventor)

    1994-01-01

    Improvements are made in a non-volatile magnetic random access memory. Such a memory is comprised of an array of unit cells, each having a Hall-effect sensor and a thin-film magnetic element made of material having an in-plane, uniaxial anisotropy and in-plane, bipolar remanent magnetization states. The Hall-effect sensor is made more sensitive by using a 1 m thick molecular beam epitaxy grown InAs layer on a silicon substrate by employing a GaAs/AlGaAs/InAlAs superlattice buffering layer. One improvement avoids current shunting problems of matrix architecture. Another improvement reduces the required magnetizing current for the micromagnets. Another improvement relates to the use of GaAs technology wherein high electron-mobility GaAs MESFETs provide faster switching times. Still another improvement relates to a method for configuring the invention as a three-dimensional random access memory.

  9. Ultra-flexible nonvolatile memory based on donor-acceptor diketopyrrolopyrrole polymer blends

    PubMed Central

    Zhou, Ye; Han, Su-Ting; Yan, Yan; Zhou, Li; Huang, Long-Biao; Zhuang, Jiaqing; Sonar, Prashant; Roy, V. A. L.

    2015-01-01

    Flexible memory cell array based on high mobility donor-acceptor diketopyrrolopyrrole polymer has been demonstrated. The memory cell exhibits low read voltage, high cell-to-cell uniformity and good mechanical flexibility, and has reliable retention and endurance memory performance. The electrical properties of the memory devices are systematically investigated and modeled. Our results suggest that the polymer blends provide an important step towards high-density flexible nonvolatile memory devices. PMID:26029856

  10. Combination of volatile and non-volatile functions in a single memory cell and its scalability

    NASA Astrophysics Data System (ADS)

    Kim, Hyungjin; Hwang, Sungmin; Lee, Jong-Ho; Park, Byung-Gook

    2017-04-01

    A single memory cell which combines volatile memory and non-volatile memory functions has been demonstrated with an independent asymmetric dual-gate structure. Owing to the second gate whose dielectric is composed of oxide/nitride/oxide layers, floating body effect was observed even on a fully depleted silicon-on-insulator device and the non-volatile memory function was measured. In addition, read retention characteristics of the volatile memory function depending on the non-volatile memory state were evaluated and analyzed. Further scalability in body thickness was also verified through simulation studies. These results indicate that the proposed device is a promising candidate for high-density embedded memory applications.

  11. Active Flash: Performance-Energy Tradeoffs for Out-of-Core Processing on Non-Volatile Memory Devices

    SciTech Connect

    Boboila, Simona; Kim, Youngjae; Vazhkudai, Sudharshan S; Desnoyers, Peter; Shipman, Galen M

    2012-01-01

    In this abstract, we study the performance and energy tradeoffs involved in migrating data analysis into the flash device, a process we refer to as Active Flash. The Active Flash paradigm is similar to 'active disks', which has received considerable attention. Active Flash allows us to move processing closer to data, thereby minimizing data movement costs and reducing power consumption. It enables true out-of-core computation. The conventional definition of out-of-core solvers refers to an approach to process data that is too large to fit in the main memory and, consequently, requires access to disk. However, in Active Flash, processing outside the host CPU literally frees the core and achieves real 'out-of-core' analysis. Moving analysis to data has long been desirable, not just at this level, but at all levels of the system hierarchy. However, this requires a detailed study on the tradeoffs involved in achieving analysis turnaround under an acceptable energy envelope. To this end, we first need to evaluate if there is enough computing power on the flash device to warrant such an exploration. Flash processors require decent computing power to run the internal logic pertaining to the Flash Translation Layer (FTL), which is responsible for operations such as address translation, garbage collection (GC) and wear-leveling. Modern SSDs are composed of multiple packages and several flash chips within a package. The packages are connected using multiple I/O channels to offer high I/O bandwidth. SSD computing power is also expected to be high enough to exploit such inherent internal parallelism within the drive to increase the bandwidth and to handle fast I/O requests. More recently, SSD devices are being equipped with powerful processing units and are even embedded with multicore CPUs (e.g. ARM Cortex-A9 embedded processor is advertised to reach 2GHz frequency and deliver 5000 DMIPS; OCZ RevoDrive X2 SSD has 4 SandForce controllers, each with 780MHz max frequency

  12. Nonvolatile ``AND,'' ``OR,'' and ``NOT'' Boolean logic gates based on phase-change memory

    NASA Astrophysics Data System (ADS)

    Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.

    2013-12-01

    Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

  13. Enhancement of the memory effects for nonvolatile memory devices fabricated utilizing ZnO nanoparticles embedded in a Si3N4 layer.

    PubMed

    Oh, Do-Hyun; Cho, Woon-Jo; Son, Dong Ick; Kim, Tae Whan

    2010-05-01

    ZnO nanoparticles embedded in a Si3N4 layer by using spin-coating and thermal treatment were fabricated to investigate the feasible applications in charge trapping regions of the metal/oxide/nitride/oxide/p-Si memory devices. The magnitude of the flatband voltage shift of the capacitance-voltage (C-V) curve for the Al/SiO2/ZnO nanoparticles embedded in Si3N4 layer/SiO2/p-Si memory device was larger than that of Al/ZnO nanoparticles embedded in SiO2 layer/p-Si and Al/SiO2/Si3N4/SiO2/p-Si devices. The increase in the flatband voltage shift of the C-V curve for the Al/SiO2/ZnO nanoparticles embedded in Si3N4 layer/SiO2/p-Si memory device in comparison with other devices was attributed to the existence of the ZnO nanoparticles or the interface trap states between the ZnO nanoparticles and the Si3N4 layer resulting from existence of ZnO nanoparticles embedded in the Si3N4 layer.

  14. An FPGA-Based Test-Bed for Reliability and Endurance Characterization of Non-Volatile Memory

    NASA Technical Reports Server (NTRS)

    Rao, Vikram; Patel, Jagdish; Patel, Janak; Namkung, Jeffrey

    2001-01-01

    Memory technologies are divided into two categories. The first category, nonvolatile memories, are traditionally used in read-only or read-mostly applications because of limited write endurance and slow write speed. These memories are derivatives of read only memory (ROM) technology, which includes erasable programmable ROM (EPROM), electrically-erasable programmable ROM (EEPROM), Flash, and more recent ferroelectric non-volatile memory technology. Nonvolatile memories are able to retain data in the absence of power. The second category, volatile memories, are random access memory (RAM) devices including SRAM and DRAM. Writing to these memories is fast and write endurance is unlimited, so they are most often used to store data that change frequently, but they cannot store data in the absence of power. Nonvolatile memory technologies with better future potential are FRAM, Chalcogenide, GMRAM, Tunneling MRAM, and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) EEPROM.

  15. Influence of polarity of set voltage on the properties of conductive filaments in NiO based nonvolatile memory device

    NASA Astrophysics Data System (ADS)

    Yan, Hui-Yu; Li, Zhi-Qing

    2017-03-01

    In this paper, we realize the coexistence of bipolar and unipolar resistive switching (RS) in one Pt-Ir/NiO/TiB1+δ cell. The types of RS are controlled by polarity of set voltage and are free from the current compliance. Based on this coexistence, the set voltage and characters of filaments formed in RS are studied. The results show that the types of filaments also show polarity dependence on the set voltage. The positive set voltage can induce metallic filaments while the negative set voltage can result in semiconductor filaments. It reveals that the distribution of magnitude of set voltage shows abnormal polarity dependence in our devices. The combination the theory of interaction between oxygen vacancy defects and one-carrier impact ionization theory of breakdown account for these results. The influence of filament properties on RS types is also discussed.

  16. The retention characteristics of nonvolatile SNOS memory transistors in a radiation environment: Experiment and model

    SciTech Connect

    McWhorter, P.J.; Miller, S.L.; Dellin, T.A.; Axness, C.L.

    1987-01-01

    Experimental data and a model to accurately and quantitatively predict the data are presented for retention of SNOS memory devices over a wide range of dose rates. A wide range of SNOS stack geometries are examined. The model is designed to aid in screening nonvolatile memories for use in a radiation environment.

  17. Radiation and Reliability Concerns for Modern Nonvolatile Memory Technology

    NASA Technical Reports Server (NTRS)

    Oldham, Timothy R.; Friendlich, Mark R.; Kim, Hak S.; Berg, Melanie D.; LaBel, Kenneth A.; Buchner, S. P.; McMorrow, D.; Mavis, D. G.; Eaton, P. H.; Castillo, J.

    2011-01-01

    Commercial nonvolatile memory technology is attractive for space applications, but radiation issues are serious concerns. In addition, we discuss combined radiation/reliability concerns which are only beginning to be addressed.

  18. Non-Volatile Memory Technology Symposium 2000: Proceedings

    NASA Technical Reports Server (NTRS)

    Aranki, Nazeeh (Editor)

    2000-01-01

    This publication contains the proceedings for the Non-Volatile Memory Technology Symposium 2000 that was held on November 15-16, 2000 in Arlington, Virginia. The proceedings contains a wide range of papers that cover the presentations of myriad advances in the nonvolatile memory technology during the recent past including memory cell design, simulations, radiation environment, and emerging memory technologies. The papers presented in the proceedings address the design challenges and applications and deals with newer, emerging memory technologies as well as related issues of radiation environment and die packaging.

  19. Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

    SciTech Connect

    Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong

    2014-10-20

    High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

  20. Non-volatile memory based on transition metal perovskite oxide resistance switching

    NASA Astrophysics Data System (ADS)

    Nian, Yibo

    Driven by the non-volatile memory market looking for new advanced materials, this dissertation focuses on the study of non-volatile resistive random access memory (RRAM) based on transition metal perovskite oxides. Pr0.7Ca0.3MnO3 (PCMO), one of the representative materials in this family, has demonstrated a large range of resistance change when short electrical pulses with different polarity are applied. Such electrical-pulse-induced resistance (EPIR), with attractive features such as fast response, low power, high-density and non-volatility, makes PCMO and related materials promising candidates for non-volatile RRAM application. The objective of this work is to investigate, optimize and understand the properties of this universal EPIR behavior in transition metal perovskite oxide, represented by PCMO thin film devices. The research work includes fabrication of PCMO thin film devices, characterization of these EPIR devices as non-volatile memories, and investigation of their resistive switching mechanisms. The functionality of this perovskite oxide RRAM, including pulse magnitude/width dependence, power consumption, retention, endurance and radiation-hardness has been investigated. By studying the "shuttle tail" in hysteresis switching loops of oxygen deficient devices, a diffusion model with oxygen ions/vacancies as active agents at the metal/oxide interface is proposed for the non-volatile resistance switching effect in transition metal perovskite oxide thin films. The change of EPIR switching behavior after oxygen/argon ion implantation also shows experiment support for the proposed model. Furthermore, the universality, scalability and comparison with other non-volatile memories are discussed for future application.

  1. Nonvolatile memory behavior of nanocrystalline cellulose/graphene oxide composite films

    NASA Astrophysics Data System (ADS)

    Valentini, L.; Cardinali, M.; Fortunati, E.; Kenny, J. M.

    2014-10-01

    With the continuous advance of modern electronics, the demand for nonvolatile memory cells rapidly grows. In order to develop post-silicon electronic devices, it is necessary to find innovative solutions to the eco-sustainability problem of materials for nonvolatile memory cells. In this work, we realized a resistive memory device based on graphene oxide (GO) and GO/cellulose nanocrystals (CNC) thin films. Aqueous solutions of GO and GO with CNC have been prepared and drop cast between two metal electrodes. Such thin-film based devices showed a transition between low and high conductivity states upon the forward and backward sweeping of an external electric field. This reversible current density transition behavior demonstrates a typical memory characteristic. The obtained results open an easy route for electronic information storage based on the integration of nanocrystalline cellulose onto graphene based devices.

  2. Nonvolatile memory behavior of nanocrystalline cellulose/graphene oxide composite films

    SciTech Connect

    Valentini, L. Cardinali, M.; Fortunati, E.; Kenny, J. M.

    2014-10-13

    With the continuous advance of modern electronics, the demand for nonvolatile memory cells rapidly grows. In order to develop post-silicon electronic devices, it is necessary to find innovative solutions to the eco-sustainability problem of materials for nonvolatile memory cells. In this work, we realized a resistive memory device based on graphene oxide (GO) and GO/cellulose nanocrystals (CNC) thin films. Aqueous solutions of GO and GO with CNC have been prepared and drop cast between two metal electrodes. Such thin-film based devices showed a transition between low and high conductivity states upon the forward and backward sweeping of an external electric field. This reversible current density transition behavior demonstrates a typical memory characteristic. The obtained results open an easy route for electronic information storage based on the integration of nanocrystalline cellulose onto graphene based devices.

  3. Method for refreshing a non-volatile memory

    DOEpatents

    Riekels, James E.; Schlesinger, Samuel

    2008-11-04

    A non-volatile memory and a method of refreshing a memory are described. The method includes allowing an external system to control refreshing operations within the memory. The memory may generate a refresh request signal and transmit the refresh request signal to the external system. When the external system finds an available time to process the refresh request, the external system acknowledges the refresh request and transmits a refresh acknowledge signal to the memory. The memory may also comprise a page register for reading and rewriting a data state back to the memory. The page register may comprise latches in lieu of supplemental non-volatile storage elements, thereby conserving real estate within the memory.

  4. Molecular floating-gate organic nonvolatile memory with a fully solution processed core architecture

    NASA Astrophysics Data System (ADS)

    Wu, Chao; Wang, Wei; Song, Junfeng

    2016-11-01

    In this paper, we demonstrated a floating-gate organic thin film transistor based nonvolatile memory, in which the core architecture was processed by a sequential three-step solution spin-coating method. The molecular semiconductor 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-Pen) distributing in the matrix of polymer poly(styrene) (PS), acting as the floating-gate and tunneling layer, respectively, was processed by one-step spin-coating from their blending solution. The effect of the proportion of TIPS-Pen in the matrix of PS on the memory performances of devices was researched. As a result, a good nonvolatile memory was achieved, with a memory window larger than 25 V, stable memory endurance property over 500 cycles and retention time longer than 5000 s with a high memory ratio larger than 102, at an optimal proportion of TIPS-Pen in the matrix of PS.

  5. Non-volatile memory with self-assembled ferrocene charge trapping layer

    NASA Astrophysics Data System (ADS)

    Zhu, Hao; Hacker, Christina A.; Pookpanratana, Sujitra J.; Richter, Curt A.; Yuan, Hui; Li, Haitao; Kirillov, Oleg; Ioannou, Dimitris E.; Li, Qiliang

    2013-07-01

    A metal/oxide/molecule/oxide/Si capacitor structure containing redox-active ferrocene molecules has been fabricated for non-volatile memory application. Cyclic voltammetry and X-ray photoelectron spectroscopy were used to measure the molecules in the structure, showing that the molecules attach on SiO2/Si and the molecules are functional after device fabrication. These solid-state molecular memory devices have fast charge-storage speed and can endure more than 109 program/erase cycles. This excellent performance is derived from the intrinsic properties of the redox-active molecules and the hybrid Si-molecular device structure. These molecular devices are very attractive for future high-level non-volatile memory applications.

  6. SiCOH-based resistive random access memory for backend of line compatible nonvolatile memory application

    NASA Astrophysics Data System (ADS)

    Zheng, Liang; Dai, Ya-Wei; Yu, Lin-Jie; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

    2017-04-01

    We investigated the resistive switching characteristics of a SiCOH low-k-material-based resistive random access memory (RRAM) in this study. This SiCOH-based RRAM is fully compatible with backend CMOS technology, which is extremely important for its applicability. The device demonstrated here had higher performance characteristics than a conventional SiO2-based RRAM, such as a higher ON/OFF ratio (around 102), and a higher cycling endurance in an ambient environment. Taken together, these characteristics make the device a promising candidate for next-generation nonvolatile applications.

  7. Single-Hole Charging and Discharging Phenomena in Carbon Nanotube Field-Effect-Transistor-Based Nonvolatile Memory

    NASA Astrophysics Data System (ADS)

    Ohori, Takahiro; Nagaso, Satoshi; Ohno, Yasuhide; Maehashi, Kenzo; Inoue, Koichi; Matsumoto, Kazuhiko

    2010-06-01

    We have fabricated nonvolatile memory based on top-gated carbon nanotube field-effect transistors (CNTFETs). Two kinds of insulating films, SiNx and SiO2, were deposited to control the hysteresis characteristics after the removal of water molecules around the single-walled CNT channels. The interface between the SiNx and SiO2 films is expected to act as a charge storage node of nonvolatile memory. The fabricated CNTFET-based memory devices clearly exhibited not only a memory effect but also good retention characteristics for charge storage. Furthermore, single-hole charging and discharging phenomena were clearly observed in the CNTFET-based memory devices by reducing the number of carriers trapped in the interface between the SiNx and SiO2 films. These results indicate that the CNTFET-based nonvolatile memory can be potentially used to realize single-electron memory.

  8. Development of non-volatile semiconductor memory

    NASA Technical Reports Server (NTRS)

    Heikkila, W. W.

    1979-01-01

    A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

  9. All-inorganic spin-cast quantum dot based bipolar nonvolatile resistive memory

    NASA Astrophysics Data System (ADS)

    Kannan, V.; Chae, Y. S.; Ramana, CH. V. V.; Ko, Dong-Sik; Rhee, J. K.

    2011-04-01

    We introduce an all-inorganic solution processed bipolar nonvolatile resistive memory device with quantum dot/metal-metal oxide/quantum dot structure. The two terminal device exhibits excellent switching characteristics with ON/OFF ratio >103. The device maintained its state even after removal of the bias voltage. The switching time is faster than 50 ns. Device did not show degradation after 1-h retention test at 150 °C. The memory functionality was consistent even after multiple cycles of operation and the device is reproducible. The switching mechanism is discussed on the basis of charge trapping in quantum dots with metal oxide serving as the barrier.

  10. Active non-volatile memory post-processing

    DOEpatents

    Kannan, Sudarsun; Milojicic, Dejan S.; Talwar, Vanish

    2017-04-11

    A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.

  11. Transparent and flexible nonvolatile memory using poly(methylsilsesquioxane) dielectric embedded with cadmium selenide quantum dots

    NASA Astrophysics Data System (ADS)

    Ooi, Poh Choon; Li, Fushan; Perumal Veeramalai, Chandrasekar; Guo, Tailiang

    2014-12-01

    In this work, a transparent and flexible nonvolatile memory was fabricated using a solution process. The conduction mechanisms of the metal/insulator/metal structure consisting of cadmium selenide quantum dots embedded in poly(methylsilsesquioxane) dielectric layers were investigated in terms of current-voltage characteristics. The memory device is reprogrammable and stable up to 1 × 104 s with little deterioration and a distinct ON/OFF ratio of 104. Endurance cycle and retention tests of the as-fabricated memory device were also carried out. The results indicate that the device has good operating stability.

  12. Fabrication and characterization of non-volatile transistor memory based on polypeptide as gate dielectric

    NASA Astrophysics Data System (ADS)

    Liang, Lijuan; Li, LianFang; Wei, Xianfu; Huang, Beiqing; Wei, Yen

    2017-01-01

    The organic thin film transistor (OTFT) fabricated with the polypeptide as a dielectric layer shows memory function. In order to investigate the effect of polypeptide structure on the performance of non-volatile transistor memory, the Fourier-transform IR (FT- IR) and Circular Dichiroism (CD) spectral of PMLG film has been applied, respectively. In conclusion, the memory transistor device fabricated with polypeptide as the ferroelectric exhibit promising behavior such as a large memory window, and the dipole moment of the amide group was considered as the main source of the memory function.

  13. Nanopatterned ferroelectrics for ultrahigh density rad-hard nonvolatile memories.

    SciTech Connect

    Brennecka, Geoffrey L.; Stevens, Jeffrey; Scrymgeour, David; Gin, Aaron V.; Tuttle, Bruce Andrew

    2010-09-01

    Radiation hard nonvolatile random access memory (NVRAM) is a crucial component for DOE and DOD surveillance and defense applications. NVRAMs based upon ferroelectric materials (also known as FERAMs) are proven to work in radiation-rich environments and inherently require less power than many other NVRAM technologies. However, fabrication and integration challenges have led to state-of-the-art FERAMs still being fabricated using a 130nm process while competing phase-change memory (PRAM) has been demonstrated with a 20nm process. Use of block copolymer lithography is a promising approach to patterning at the sub-32nm scale, but is currently limited to self-assembly directly on Si or SiO{sub 2} layers. Successful integration of ferroelectrics with discrete and addressable features of {approx}15-20nm would represent a 100-fold improvement in areal memory density and would enable more highly integrated electronic devices required for systems advances. Towards this end, we have developed a technique that allows us to carry out block copolymer self-assembly directly on a huge variety of different materials and have investigated the fabrication, integration, and characterization of electroceramic materials - primarily focused on solution-derived ferroelectrics - with discrete features of {approx}20nm and below. Significant challenges remain before such techniques will be capable of fabricating fully integrated NVRAM devices, but the tools developed for this effort are already finding broader use. This report introduces the nanopatterned NVRAM device concept as a mechanism for motivating the subsequent studies, but the bulk of the document will focus on the platform and technology development.

  14. Physical principles and current status of emerging non-volatile solid state memories

    NASA Astrophysics Data System (ADS)

    Wang, L.; Yang, C.-H.; Wen, J.

    2015-07-01

    Today the influence of non-volatile solid-state memories on persons' lives has become more prominent because of their non-volatility, low data latency, and high robustness. As a pioneering technology that is representative of non-volatile solidstate memories, flash memory has recently seen widespread application in many areas ranging from electronic appliances, such as cell phones and digital cameras, to external storage devices such as universal serial bus (USB) memory. Moreover, owing to its large storage capacity, it is expected that in the near future, flash memory will replace hard-disk drives as a dominant technology in the mass storage market, especially because of recently emerging solid-state drives. However, the rapid growth of the global digital data has led to the need for flash memories to have larger storage capacity, thus requiring a further downscaling of the cell size. Such a miniaturization is expected to be extremely difficult because of the well-known scaling limit of flash memories. It is therefore necessary to either explore innovative technologies that can extend the areal density of flash memories beyond the scaling limits, or to vigorously develop alternative non-volatile solid-state memories including ferroelectric random-access memory, magnetoresistive random-access memory, phase-change random-access memory, and resistive random-access memory. In this paper, we review the physical principles of flash memories and their technical challenges that affect our ability to enhance the storage capacity. We then present a detailed discussion of novel technologies that can extend the storage density of flash memories beyond the commonly accepted limits. In each case, we subsequently discuss the physical principles of these new types of non-volatile solid-state memories as well as their respective merits and weakness when utilized for data storage applications. Finally, we predict the future prospects for the aforementioned solid-state memories for

  15. Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

    PubMed

    Ng, Tse Nga; Schwartz, David E; Lavery, Leah L; Whiting, Gregory L; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

    2012-01-01

    Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

  16. Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

    NASA Astrophysics Data System (ADS)

    Ng, Tse Nga; Schwartz, David E.; Lavery, Leah L.; Whiting, Gregory L.; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

    2012-08-01

    Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

  17. Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

    PubMed Central

    Ng, Tse Nga; Schwartz, David E.; Lavery, Leah L.; Whiting, Gregory L.; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

    2012-01-01

    Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic. PMID:22900143

  18. Electrostatically transparent graphene quantum-dot trap layers for efficient nonvolatile memory

    SciTech Connect

    Kim, Young Rae; Jo, Yong Eun; Sung, Yeo Hyun; Won, Ui Yeon; Shin, Yong Seon; Kang, Won Tae; Yu, Woo Jong E-mail: micco21@skku.edu; Lee, Young Hee E-mail: micco21@skku.edu

    2015-03-09

    In this study, we have demonstrated nonvolatile memory devices using graphene quantum-dots (GQDs) trap layers with indium zinc oxide (IZO) semiconductor channel. The Fermi-level of GQD was effectively modulated by tunneling electrons near the Dirac point because of limited density of states and weak electrostatic screening in monolayer graphene. As a result, large gate modulation was driven in IZO channel to achieve a subthreshold swing of 5.21 V/dec (300 nm SiO{sub 2} gate insulator), while Au quantum-dots memory shows 15.52 V/dec because of strong electrostatic screening in metal quantum-dots. Together, discrete charge traps of GQDs enable stable performance in the endurance test beyond 800 cycles of programming and erasing. Our study suggests the exciting potential of GQD trap layers to be used for a highly promising material in non-volatile memory devices.

  19. Electrostatically transparent graphene quantum-dot trap layers for efficient nonvolatile memory

    NASA Astrophysics Data System (ADS)

    Kim, Young Rae; Jo, Yong Eun; Shin, Yong Seon; Kang, Won Tae; Sung, Yeo Hyun; Won, Ui Yeon; Lee, Young Hee; Yu, Woo Jong

    2015-03-01

    In this study, we have demonstrated nonvolatile memory devices using graphene quantum-dots (GQDs) trap layers with indium zinc oxide (IZO) semiconductor channel. The Fermi-level of GQD was effectively modulated by tunneling electrons near the Dirac point because of limited density of states and weak electrostatic screening in monolayer graphene. As a result, large gate modulation was driven in IZO channel to achieve a subthreshold swing of 5.21 V/dec (300 nm SiO2 gate insulator), while Au quantum-dots memory shows 15.52 V/dec because of strong electrostatic screening in metal quantum-dots. Together, discrete charge traps of GQDs enable stable performance in the endurance test beyond 800 cycles of programming and erasing. Our study suggests the exciting potential of GQD trap layers to be used for a highly promising material in non-volatile memory devices.

  20. Retention characteristics of SNOS nonvolatile devices in a radiation environment

    SciTech Connect

    McWhorter, P.J.; Miller, S.L.; Dellin, T.A.; Axness, C.A.

    1987-12-01

    A quantitative model is developed that can accurately predict the threshold voltage shift, and hence data loss, in SNOS nonvolatile memory transistors over a wide range of dose rates. The model accounts for both the time dependent and radiation induced mechanisms leading to data loss. Experimental measurements are made to verify the validity and accuracy of the model under a variety of irradiation conditions.

  1. Non-Volatile Memory Technology Symposium 2001: Proceedings

    NASA Technical Reports Server (NTRS)

    Aranki, Nazeeh; Daud, Taher; Strauss, Karl

    2001-01-01

    This publication contains the proceedings for the Non-Volatile Memory Technology Symposium 2001 that was held on November 7-8, 2001 in San Diego, CA. The proceedings contains a a wide range of papers that cover current and new memory technologies including Flash memories, Magnetic Random Access Memories (MRAM and GMRAM), Ferro-electric RAM (FeRAM), and Chalcogenide RAM (CRAM). The papers presented in the proceedings address the use of these technologies for space applications as well as radiation effects and packaging issues.

  2. Low-power non-volatile spintronic memory: STT-RAM and beyond

    NASA Astrophysics Data System (ADS)

    Wang, K. L.; Alzate, J. G.; Khalili Amiri, P.

    2013-02-01

    The quest for novel low-dissipation devices is one of the most critical for the future of semiconductor technology and nano-systems. The development of a low-power, universal memory will enable a new paradigm of non-volatile computation. Here we consider STT-RAM as one of the emerging candidates for low-power non-volatile memory. We show different configurations for STT memory and demonstrate strategies to optimize key performance parameters such as switching current and energy. The energy and scaling limits of STT-RAM are discussed, leading us to argue that alternative writing mechanisms may be required to achieve ultralow power dissipation, a necessary condition for direct integration with CMOS at the gate level for non-volatile logic purposes. As an example, we discuss the use of the giant spin Hall effect as a possible alternative to induce magnetization reversal in magnetic tunnel junctions using pure spin currents. Further, we concentrate on magnetoelectric effects, where electric fields are used instead of spin-polarized currents to manipulate the nanomagnets, as another candidate solution to address the challenges of energy efficiency and density. The possibility of an electric-field-controlled magnetoelectric RAM as a promising candidate for ultralow-power non-volatile memory is discussed in the light of experimental data demonstrating voltage-induced switching of the magnetization and reorientation of the magnetic easy axis by electric fields in nanomagnets.

  3. A review of emerging non-volatile memory (NVM) technologies and applications

    NASA Astrophysics Data System (ADS)

    Chen, An

    2016-11-01

    This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

  4. Nonvolatile memory functionality of ZnO nanowire transistors controlled by mobile protons.

    PubMed

    Yoon, Jongwon; Hong, Woong-Ki; Jo, Minseok; Jo, Gunho; Choe, Minhyeok; Park, Woojin; Sohn, Jung Inn; Nedic, Stanko; Hwang, Hyungsang; Welland, Mark E; Lee, Takhee

    2011-01-25

    We demonstrated the nonvolatile memory functionality of ZnO nanowire field effect transistors (FETs) using mobile protons that are generated by high-pressure hydrogen annealing (HPHA) at relatively low temperature (400 °C). These ZnO nanowire devices exhibited reproducible hysteresis, reversible switching, and nonvolatile memory behaviors in comparison with those of the conventional FET devices. We show that the memory characteristics are attributed to the movement of protons between the Si/SiO(2) interface and the SiO(2)/ZnO nanowire interface by the applied gate electric field. The memory mechanism is explained in terms of the tuning of interface properties, such as effective electric field, surface charge density, and surface barrier potential due to the movement of protons in the SiO(2) layer, consistent with the UV photoresponse characteristics of nanowire memory devices. Our study will further provide a useful route of creating memory functionality and incorporating proton-based storage elements onto a modified CMOS platform for FET memory devices using nanomaterials.

  5. Integrated photonics with programmable non-volatile memory

    NASA Astrophysics Data System (ADS)

    Song, Jun-Feng; Luo, Xian-Shu; Lim, Andy Eu-Jin; Li, Chao; Fang, Qing; Liow, Tsung-Yang; Jia, Lian-Xi; Tu, Xiao-Guang; Huang, Ying; Zhou, Hai-Feng; Lo, Guo-Qiang

    2016-03-01

    Silicon photonics integrated circuits (Si-PIC) with well-established active and passive building elements are progressing towards large-scale commercialization in optical communications and high speed optical interconnects applications. However, current Si-PICs do not have memory capabilities, in particular, the non-volatile memory functionality for energy efficient data storage. Here, we propose an electrically programmable, multi-level non-volatile photonics memory cell (PMC) fabricated by standard complementary-metal-oxide-semiconductor (CMOS) compatible processes. A micro-ring resonator (MRR) was built using the PMC to optically read the memory states. Switching energy smaller than 20 pJ was achieved. Additionally, a MRR memory array was employed to demonstrate a four-bit memory read capacity. Theoretically, this can be increased up to ~400 times using a 100 nm free spectral range broadband light source. The fundamental concept of this design provides a route to eliminate the von Neumann bottleneck. The energy-efficient optical storage can complement on-chip optical interconnects for neutral networking, memory input/output interfaces and other computational intensive applications.

  6. Integrated photonics with programmable non-volatile memory.

    PubMed

    Song, Jun-Feng; Luo, Xian-Shu; Lim, Andy Eu-Jin; Li, Chao; Fang, Qing; Liow, Tsung-Yang; Jia, Lian-Xi; Tu, Xiao-Guang; Huang, Ying; Zhou, Hai-Feng; Lo, Guo-Qiang

    2016-03-04

    Silicon photonics integrated circuits (Si-PIC) with well-established active and passive building elements are progressing towards large-scale commercialization in optical communications and high speed optical interconnects applications. However, current Si-PICs do not have memory capabilities, in particular, the non-volatile memory functionality for energy efficient data storage. Here, we propose an electrically programmable, multi-level non-volatile photonics memory cell (PMC) fabricated by standard complementary-metal-oxide-semiconductor (CMOS) compatible processes. A micro-ring resonator (MRR) was built using the PMC to optically read the memory states. Switching energy smaller than 20 pJ was achieved. Additionally, a MRR memory array was employed to demonstrate a four-bit memory read capacity. Theoretically, this can be increased up to ~400 times using a 100 nm free spectral range broadband light source. The fundamental concept of this design provides a route to eliminate the von Neumann bottleneck. The energy-efficient optical storage can complement on-chip optical interconnects for neutral networking, memory input/output interfaces and other computational intensive applications.

  7. Integrated photonics with programmable non-volatile memory

    PubMed Central

    Song, Jun-Feng; Luo, Xian-Shu; Lim, Andy Eu-Jin; Li, Chao; Fang, Qing; Liow, Tsung-Yang; Jia, Lian-Xi; Tu, Xiao-Guang; Huang, Ying; Zhou, Hai-Feng; Lo, Guo-Qiang

    2016-01-01

    Silicon photonics integrated circuits (Si-PIC) with well-established active and passive building elements are progressing towards large-scale commercialization in optical communications and high speed optical interconnects applications. However, current Si-PICs do not have memory capabilities, in particular, the non-volatile memory functionality for energy efficient data storage. Here, we propose an electrically programmable, multi-level non-volatile photonics memory cell (PMC) fabricated by standard complementary-metal-oxide-semiconductor (CMOS) compatible processes. A micro-ring resonator (MRR) was built using the PMC to optically read the memory states. Switching energy smaller than 20 pJ was achieved. Additionally, a MRR memory array was employed to demonstrate a four-bit memory read capacity. Theoretically, this can be increased up to ~400 times using a 100 nm free spectral range broadband light source. The fundamental concept of this design provides a route to eliminate the von Neumann bottleneck. The energy-efficient optical storage can complement on-chip optical interconnects for neutral networking, memory input/output interfaces and other computational intensive applications. PMID:26941113

  8. Cubic-phase zirconia nano-islands growth using atomic layer deposition and application in low-power charge-trapping nonvolatile-memory devices.

    PubMed

    El Atab, Nazek; Ulusoy Ghobadi, Gamze; Ghobadi, Amir; Suh, Junkyo; Islam, Raisul; Okyay, Ali Kemal; Saraswat, Krishna C; Nayfeh, Ammar

    2017-08-23

    The manipulation of matter at the nanoscale enables the generation of properties in a material that would otherwise be challenging or impossible to realize in the bulk state. Here, we demonstrate growth of zirconia nano-islands using Atomic Layer Deposition (ALD) on different substrate terminations. Transmission Electron Microscopy and Raman measurements indicate that the nano-islands consist of nano-crystallites of the cubic-crystalline phase, which results in a higher dielectric constant (κ~35) than the amorphous phase case (κ~20). X-ray photoelectron spectroscopy measurements show that a deep quantum well is formed in the Al2O3/ZrO2/Al2O3 system which is substantially different than in the bulk state of zirconia and is more favorable for memory application. Finally, a memory device with ZrO2 nano-islands charge trapping layer is fabricated, a wide memory window of 4.5 V is obtained at a low programming voltage of 5 V due to the large dielectric constant of the islands in addition to excellent endurance and retention characteristics. © 2017 IOP Publishing Ltd.

  9. Flexible Nonvolatile Polymer Memory Array on Plastic Substrate via Initiated Chemical Vapor Deposition.

    PubMed

    Jang, Byung Chul; Seong, Hyejeong; Kim, Sung Kyu; Kim, Jong Yun; Koo, Beom Jun; Choi, Junhwan; Yang, Sang Yoon; Im, Sung Gap; Choi, Sung-Yool

    2016-05-25

    Resistive random access memory based on polymer thin films has been developed as a promising flexible nonvolatile memory for flexible electronic systems. Memory plays an important role in all modern electronic systems for data storage, processing, and communication; thus, the development of flexible memory is essential for the realization of flexible electronics. However, the existing solution-processed, polymer-based RRAMs have exhibited serious drawbacks in terms of the uniformity, electrical stability, and long-term stability of the polymer thin films. Here, we present poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3)-based RRAM arrays fabricated via the solvent-free technique called initiated chemical vapor deposition (iCVD) process for flexible memory application. Because of the outstanding chemical stability of pV3D3 films, the pV3D3-RRAM arrays can be fabricated by a conventional photolithography process. The pV3D3-RRAM on flexible substrates showed unipolar resistive switching memory with an on/off ratio of over 10(7), stable retention time for 10(5) s, excellent cycling endurance over 10(5) cycles, and robust immunity to mechanical stress. In addition, pV3D3-RRAMs showed good uniformity in terms of device-to-device distribution. The pV3D3-RRAM will pave the way for development of next-generation flexible nonvolatile memory devices.

  10. A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement.

    PubMed

    Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

    2016-01-01

    Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates.

  11. A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement

    PubMed Central

    Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

    2016-01-01

    Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates. PMID:26763827

  12. Nonvolatile GaAs Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R.; Stadler, Henry L.; Wu, Jiin-Chuan

    1994-01-01

    Proposed random-access integrated-circuit electronic memory offers nonvolatile magnetic storage. Bits stored magnetically and read out with Hall-effect sensors. Advantages include short reading and writing times and high degree of immunity to both single-event upsets and permanent damage by ionizing radiation. Use of same basic material for both transistors and sensors simplifies fabrication process, with consequent benefits in increased yield and reduced cost.

  13. Integrated, nonvolatile, high-speed analog random access memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor)

    1994-01-01

    This invention provides an integrated, non-volatile, high-speed random access memory. A magnetically switchable ferromagnetic or ferrimagnetic layer is sandwiched between an electrical conductor which provides the ability to magnetize the magnetically switchable layer and a magneto resistive or Hall effect material which allows sensing the magnetic field which emanates from the magnetization of the magnetically switchable layer. By using this integrated three-layer form, the writing process, which is controlled by the conductor, is separated from the storage medium in the magnetic layer and from the readback process which is controlled by the magnetoresistive layer. A circuit for implementing the memory in CMOS or the like is disclosed.

  14. Reactive ion etching of Si(x)Sb2Te in CF4/Ar plasma for nonvolatile phase-change memory device.

    PubMed

    Gu, Yifeng; Song, Sannian; Song, Zhitang; Cheng, Yan; Liu, Xuyan; Du, Xiaofeng; Liu, Bo; Feng, Songlin

    2013-02-01

    Si(x)Sb2Te material system is novel for phase-change random access memory applications. Its properties are more outstanding than the widely used material Ge2Sb2Te5. Etching process is one of the critical steps in the device fabrication. The etching characteristics of phase-change material Si(x)Sb2Te were studied with CF4/Ar gas mixture by a reactive ion etching system. The changes of etching rate, etching profile and surface root-mean-square roughness resulted from variation of the gas-mixing ratio were investigated under constant pressure (50 mTorr) and applying power (200 W). Si0.34Sb2Te is with the highest phase-change speed and the lowest power consumption in the PCRAM memory among these compositions, which means it is the most promising candidate for the PCRAM applications. So the most optimized CF4/Ar gas ratio for Si0.34Sb2Te was studied, the value is 25/25. The etching rate is 155 nm/min, and the selectivity of Si0.34Sb2Te to SiO2 is as high as 3.4 times. Furthermore, the smooth surface was achieved with this optimized gas ratio.

  15. Microprocessor Controller With Nonvolatile Memory Implementation.

    DTIC Science & Technology

    1985-12-01

    minor crystalline and circuit board break- 0 age . The causes of this damage were not positively identi- fied and were attributed to factors ranging...large. In assembly language programs, the code tends to be more optimized, further reducing memory us- age . It was against this backdrop that the Z-80 and...FRTAo1 ;’WRITE, READ IUBBLF Mir DATA C"’D 2USYEr: rCX ;DIC lIME OUT LOOP COUNTER- XRA A CPA ETEST B REG= eOE ORA C ;TEST C REG= e0H ." ", JZ TINSIB

  16. A bi-stable nanoelectromechanical non-volatile memory based on van der Waals force

    NASA Astrophysics Data System (ADS)

    Soon, Bo Woon; Jiaqiang Ng, Eldwin; Qian, You; Singh, Navab; Julius Tsai, Minglin; Lee, Chengkuo

    2013-07-01

    By using complementary-metal-oxide-semiconductor processes, a silicon based bi-stable nanoelectromechanical non-volatile memory is fabricated and characterized. The main feature of this device is an 80 nm wide and 3 μm high silicon nanofin (SiNF) of a high aspect ratio (1:35). The switching mechanism is realized by electrostatic actuation between two lateral electrodes, i.e., terminals. Bi-stable hysteresis behavior is demonstrated when the SiNF maintains its contact to one of the two terminals by leveraging on van der Waals force even after voltage bias is turned off. The compelling results indicate that this design is promising for realization of high density non-volatile memory application due to its nano-scale footprint and zero on-hold power consumption.

  17. Nonvolatile multilevel conductance and memory effects in organic thin films

    NASA Astrophysics Data System (ADS)

    Lauters, M.; McCarthy, B.; Sarid, D.; Jabbour, G. E.

    2005-12-01

    Organic thin-film structures, including organic light-emitting diodes, are demonstrated to contain multiple nonvolatile conductance states at low-read voltages. Retention time of states is more than several weeks, and more than 20 000 write-read-rewrite-read cycles have been performed with minimal degradation. The electrical characteristics of these devices are consistent with metal diffusion or filament phenomena found in metal-insulator-metal structures, suggesting a possible mechanism by which the states are stored.

  18. Nonvolatile transtance change random access memory based on magnetoelectric P(VDF-TrFE)/Metglas heterostructures

    NASA Astrophysics Data System (ADS)

    Lu, Peipei; Shang, Dashan; Shen, Jianxin; Chai, Yisheng; Yang, Chuansen; Zhai, Kun; Cong, Junzhuang; Shen, Shipeng; Sun, Young

    2016-12-01

    Transtance change random access memory (TCRAM) is a type of nonvolatile memory based on the nonlinear magnetoelectric coupling effects of multiferroics. In this work, ferroelectric P(VDF-TrFE) thin films were prepared on Metglas foil substrates by the sol-gel technique to form multiferroic heterostructures. The magnetoelectric voltage coefficient of the heterostructure can be switched reproducibly to different levels between positive and negative values by applying selective electric-field pulses. Compared with bulk multiferroic heterostructures, the polarization switching voltage was reduced to 7 V. Our facile technological approach enables this organic magnetoelectric heterostructure as a promising candidate for the applications in multilevel TCRAM devices.

  19. Nonvolatile organic bistable devices fabricated utilizing Cu2O nanocrystals embedded in a polyimide layer

    NASA Astrophysics Data System (ADS)

    Jung, Jae Hun; Kim, Jae-Ho; Kim, Tae Whan; Song, Mun Seop; Kim, Young-Ho; Jin, Sungho

    2006-09-01

    The bistable effects of cuprous oxide (Cu2O) nanoparticles embedded in a polyimide (PI) matrix were investigated. Transmission electron microscopy images and selected area electron diffraction patterns showed that Cu2O nanocrystals were formed inside the PI layer. Current-voltage (I-V) measurements on Al/PI/nanocrystalline Cu2O/PI/Al structures at 300K showed a nonvolatile electrical bistability behavior. A bistable behavior for the fabricated organic bistable device (OBD) structures is described on the basis of the I-V results. These results indicate that OBDs fabricated utilizing self-assembled inorganic Cu2O nanocrystals embedded in an organic PI layer hold promise for potential applications in nonvolatile flash memory devices.

  20. Lateral electric-field-driven non-volatile four-state memory in multiferroic heterostructures

    NASA Astrophysics Data System (ADS)

    Zhou, Cai; Zhang, Chao; Yao, Jinli; Jiang, Changjun

    2016-09-01

    A non-volatile four-state memory is formed using an in-plane side-polarization configuration in a Co/(011) Pb(Mg1/3Nb2/3)O3-PbTiO3 (Co/PMN-PT) heterostructure. The resistivity vs. electric field behavior shows a change from volatile butterfly to looplike to non-volatile butterfly characteristics when the temperature decreases from 290 K to 83 K under an electric field of 10 kV/cm and then increases back to 290 K; this behavior is attributed to the strain-mediated magnetoelectric effect. In addition, the in-plane resistivity of Co film, which was measured using the four-probe technique, can be controlled both electrically and magnetically. Specifically, a non-volatile resistivity is gained by the application of electric field pulses. Additionally, a four-state memory is obtained by co-mediation of the magnetic field and electric field pulses, compared with the two different states achieved under the application of the electric field only, which indicates that our results are highly important for multi-state memory and spintronic devices applications.

  1. Ordered arrays of a defect-modified ferroelectric polymer for non-volatile memory with minimized energy consumption

    NASA Astrophysics Data System (ADS)

    Chen, Xiang-Zhong; Chen, Xin; Guo, Xu; Cui, Yu-Shuang; Shen, Qun-Dong; Ge, Hai-Xiong

    2014-10-01

    Ferroelectric polymers are among the most promising materials for flexible electronic devices. Highly ordered arrays of the defect-modified ferroelectric polymer P(VDF-TrFE-CFE) (poly(vinylidene fluoride-trifluoroethylene-chlorofluoroethylene)) are fabricated by nanoimprint lithography for nonvolatile memory application. The defective CFE units reduce the coercive field to one-fifth of that of the un-modified P(VDF-TrFE), which can help minimize the energy consumption and extend the lifespan of the device. The nanoimprint process leads to preferable orientation of polymer chains and delicately controlled distribution of the defects, and thus a bi-stable polarization that makes the memory nonvolatile, as revealed by the pulsed polarization experiment.Ferroelectric polymers are among the most promising materials for flexible electronic devices. Highly ordered arrays of the defect-modified ferroelectric polymer P(VDF-TrFE-CFE) (poly(vinylidene fluoride-trifluoroethylene-chlorofluoroethylene)) are fabricated by nanoimprint lithography for nonvolatile memory application. The defective CFE units reduce the coercive field to one-fifth of that of the un-modified P(VDF-TrFE), which can help minimize the energy consumption and extend the lifespan of the device. The nanoimprint process leads to preferable orientation of polymer chains and delicately controlled distribution of the defects, and thus a bi-stable polarization that makes the memory nonvolatile, as revealed by the pulsed polarization experiment. Electronic supplementary information (ESI) available. See DOI: 10.1039/c4nr03866e

  2. Hybrid Flexible Resistive Random Access Memory-Gated Transistor for Novel Nonvolatile Data Storage.

    PubMed

    Han, Su-Ting; Zhou, Ye; Chen, Bo; Wang, Chundong; Zhou, Li; Yan, Yan; Zhuang, Jiaqing; Sun, Qijun; Zhang, Hua; Roy, V A L

    2016-01-20

    Here, a single-device demonstration of novel hybrid architecture is reported to achieve programmable transistor nodes which have analogies to flash memory by incorporating a resistive switching random access memory (RRAM) device as a resistive switch gate for field effect transistor (FET) on a flexible substrate. A high performance flexible RRAM with a three-layered structure is fabricated by utilizing solution-processed MoS2 nanosheets sandwiched between poly(methyl methacrylate) polymer layers. Gate coupling with the pentacene-based transistor can be controlled by the RRAM memory state to produce a nonprogrammed state (inactive) and a programmed state (active) with a well-defined memory window. Compared to the reference flash memory device based on the MoS2 floating gate, the hybrid device presents robust access speed and retention ability. Furthermore, the hybrid RRAM-gated FET is used to build an integrated logic circuit and a wide logic window in inverter logic is achieved. The controllable, well-defined memory window, long retention time, and fast access speed of this novel hybrid device may open up new possibilities of realizing fully functional nonvolatile memory for high-performance flexible electronics.

  3. Non-volatile flash memory with discrete bionanodot floating gate assembled by protein template.

    PubMed

    Miura, Atsushi; Tsukamoto, Rikako; Yoshii, Shigeo; Yamashita, Ichiro; Uraoka, Yukiharu; Fuyuki, Takashi

    2008-06-25

    We demonstrated non-volatile flash memory fabrication by utilizing uniformly sized cobalt oxide (Co(3)O(4)) bionanodot (Co-BND) architecture assembled by a cage-shaped supramolecular protein template. A fabricated high-density Co-BND array was buried in a metal-oxide-semiconductor field-effect-transistor (MOSFET) structure to use as the charge storage node of a floating nanodot gate memory. We observed a clockwise hysteresis in the drain current-gate voltage characteristics of fabricated BND-embedded MOSFETs. Observed hysteresis obviously indicates a memory operation of Co-BND-embedded MOSFETs due to the charge confinement in the embedded BND and successful functioning of embedded BNDs as the charge storage nodes of the non-volatile flash memory. Fabricated Co-BND-embedded MOSFETs showed good memory properties such as wide memory windows, long charge retention and high tolerance to repeated write/erase operations. A new pathway for device fabrication by utilizing the versatile functionality of biomolecules is presented.

  4. Nonvolatile multibit Schottky memory based on single n-type Ga doped CdSe nanowires.

    PubMed

    Wu, Di; Jiang, Yang; Yu, Yongqiang; Zhang, Yugang; Li, Guohua; Zhu, Zhifeng; Wu, Chunyan; Wang, Li; Luo, Linbao; Jie, Jiansheng

    2012-12-07

    Nonvolatile resistive switching has been observed for the first time in CdSe nanowire (NW)/Au Schottky barrier diodes, where a Schottky contact electrode and an Ohmic contact electrode were formed at the Au/CdSe NW and CdSe NW/In interfaces, respectively. The CdSe NWs Schottky devices were found to possess multibit storage ability in an individual nanowire, and exhibited excellent memory characteristics, with a resistance on/off ratio exceeding four orders of magnitude, a long retention time of over 10(4) s and a lower operating voltage of 2 V. By replacing the SiO(2)/Si substrate with a poly ethylene terephthalate substrate, flexible and transparent memory devices with superior stability under strain were realized. The resistive switching of CdSe NW/Au Schottky devices is understood by electron trapping and detrapping in the interfacial oxide layer. Our findings provide a viable way to create new functional high-density nonvolatile multibit memory devices compatible with simple processing techniques for normal one-dimensional nanomaterials.

  5. Nonvolatile multibit Schottky memory based on single n-type Ga doped CdSe nanowires

    NASA Astrophysics Data System (ADS)

    Wu, Di; Jiang, Yang; Yu, Yongqiang; Zhang, Yugang; Li, Guohua; Zhu, Zhifeng; Wu, Chunyan; Wang, Li; Luo, Linbao; Jie, Jiansheng

    2012-12-01

    Nonvolatile resistive switching has been observed for the first time in CdSe nanowire (NW)/Au Schottky barrier diodes, where a Schottky contact electrode and an Ohmic contact electrode were formed at the Au/CdSe NW and CdSe NW/In interfaces, respectively. The CdSe NWs Schottky devices were found to possess multibit storage ability in an individual nanowire, and exhibited excellent memory characteristics, with a resistance on/off ratio exceeding four orders of magnitude, a long retention time of over 104 s and a lower operating voltage of 2 V. By replacing the SiO2/Si substrate with a poly ethylene terephthalate substrate, flexible and transparent memory devices with superior stability under strain were realized. The resistive switching of CdSe NW/Au Schottky devices is understood by electron trapping and detrapping in the interfacial oxide layer. Our findings provide a viable way to create new functional high-density nonvolatile multibit memory devices compatible with simple processing techniques for normal one-dimensional nanomaterials.

  6. Highly Stretchable Non-volatile Nylon Thread Memory

    PubMed Central

    Kang, Ting-Kuo

    2016-01-01

    Integration of electronic elements into textiles, to afford e-textiles, can provide an ideal platform for the development of lightweight, thin, flexible, and stretchable e-textiles. This approach will enable us to meet the demands of the rapidly growing market of wearable-electronics on arbitrary non-conventional substrates. However the actual integration of the e-textiles that undergo mechanical deformations during both assembly and daily wear or satisfy the requirements of the low-end applications, remains a challenge. Resistive memory elements can also be fabricated onto a nylon thread (NT) for e-textile applications. In this study, a simple dip-and-dry process using graphene-PEDOT:PSS (poly(3,4-ethylenedioxythiophene) polystyrene sulfonate) ink is proposed for the fabrication of a highly stretchable non-volatile NT memory. The NT memory appears to have typical write-once-read-many-times characteristics. The results show that an ON/OFF ratio of approximately 103 is maintained for a retention time of 106 s. Furthermore, a highly stretchable strain and a long-term digital-storage capability of the ON-OFF-ON states are demonstrated in the NT memory. The actual integration of the knitted NT memories into textiles will enable new design possibilities for low-cost and large-area e-textile memory applications. PMID:27072786

  7. Highly Stretchable Non-volatile Nylon Thread Memory.

    PubMed

    Kang, Ting-Kuo

    2016-04-13

    Integration of electronic elements into textiles, to afford e-textiles, can provide an ideal platform for the development of lightweight, thin, flexible, and stretchable e-textiles. This approach will enable us to meet the demands of the rapidly growing market of wearable-electronics on arbitrary non-conventional substrates. However the actual integration of the e-textiles that undergo mechanical deformations during both assembly and daily wear or satisfy the requirements of the low-end applications, remains a challenge. Resistive memory elements can also be fabricated onto a nylon thread (NT) for e-textile applications. In this study, a simple dip-and-dry process using graphene- PSS (poly(3,4-ethylenedioxythiophene) polystyrene sulfonate) ink is proposed for the fabrication of a highly stretchable non-volatile NT memory. The NT memory appears to have typical write-once-read-many-times characteristics. The results show that an ON/OFF ratio of approximately 10(3) is maintained for a retention time of 10(6)s. Furthermore, a highly stretchable strain and a long-term digital-storage capability of the ON-OFF-ON states are demonstrated in the NT memory. The actual integration of the knitted NT memories into textiles will enable new design possibilities for low-cost and large-area e-textile memory applications.

  8. Highly Stretchable Non-volatile Nylon Thread Memory

    NASA Astrophysics Data System (ADS)

    Kang, Ting-Kuo

    2016-04-01

    Integration of electronic elements into textiles, to afford e-textiles, can provide an ideal platform for the development of lightweight, thin, flexible, and stretchable e-textiles. This approach will enable us to meet the demands of the rapidly growing market of wearable-electronics on arbitrary non-conventional substrates. However the actual integration of the e-textiles that undergo mechanical deformations during both assembly and daily wear or satisfy the requirements of the low-end applications, remains a challenge. Resistive memory elements can also be fabricated onto a nylon thread (NT) for e-textile applications. In this study, a simple dip-and-dry process using graphene-PEDOT:PSS (poly(3,4-ethylenedioxythiophene) polystyrene sulfonate) ink is proposed for the fabrication of a highly stretchable non-volatile NT memory. The NT memory appears to have typical write-once-read-many-times characteristics. The results show that an ON/OFF ratio of approximately 103 is maintained for a retention time of 106 s. Furthermore, a highly stretchable strain and a long-term digital-storage capability of the ON-OFF-ON states are demonstrated in the NT memory. The actual integration of the knitted NT memories into textiles will enable new design possibilities for low-cost and large-area e-textile memory applications.

  9. Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

    NASA Astrophysics Data System (ADS)

    Riente, Fabrizio; Ziemys, Grazvydas; Mattersdorfer, Clemens; Boche, Silke; Turvani, Giovanna; Raberg, Wolfgang; Luber, Sebastian; Breitkreutz-v. Gamm, Stephan

    2017-05-01

    Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML) is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

  10. Ferroelectric FET for nonvolatile memory application with two-dimensional MoSe2 channels

    NASA Astrophysics Data System (ADS)

    Wang, Xudong; Liu, Chunsen; Chen, Yan; Wu, Guangjian; Yan, Xiao; Huang, Hai; Wang, Peng; Tian, Bobo; Hong, Zhenchen; Wang, Yutao; Sun, Shuo; Shen, Hong; Lin, Tie; Hu, Weida; Tang, Minghua; Zhou, Peng; Wang, Jianlu; Sun, Jinglan; Meng, Xiangjian; Chu, Junhao; Li, Zheng

    2017-06-01

    Graphene and other two-dimensional materials have received considerable attention regarding their potential applications in nano-electronics. Here, we report top-gate nonvolatile memory field-effect transistors (FETs) with different layers of MoSe2 nanosheets channel gated by ferroelectric film. The conventional gate dielectric of FETs was replaced by a ferroelectric thin film that provides a ferroelectric polarization electric field, and therefore defined as an Fe-FET where the poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) was used as the gate dielectric. Among the devices with MoSe2 channels of different thicknesses, the device with a single layer of MoSe2 exhibited a large hysteresis of electronic transport with an over 105 write/erase ratio, and displayed excellent retention and endurance performance. The possible mechanism of the device’s good properties was qualitatively analyzed using band theory. Additionally, a comprehensive study comparing the memory properties of MoSe2 channels of different thicknesses is presented. Increasing the numbers of MoSe2 layers was found to cause a reduced memory window. However, MoSe2 thickness of 5 nm yielded a write/erase ratio of more than 103. The results indicate that, based on a Fe-FET structure, the combination of two-dimensional semiconductors and organic ferroelectric gate dielectrics shows good promise for future applications in nonvolatile ferroelectric memory.

  11. Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

    SciTech Connect

    Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.

    2013-12-21

    Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

  12. Progress on a New Non-Volatile Memory for Space Based on Chalcogenide Glass

    SciTech Connect

    Maimon, J.; Hunt, K.; Rodgers, J.; Burcin, L.; Knowles, K.

    2004-02-04

    We report on the progress of a recent addition to non-volatile solid state memory technologies suited for space and other ionizing radiation environments. We summarize the material and processing science behind the current generation of chalcogenide phase-change memories fabricated on CMOS structures. The chalcogenide material used for phase-change applications in rewritable optical storage (Ge2Sb2Te5) has been integrated with a radiation hardened CMOS process to produce 64kbit memory arrays. On selected arrays electrical testing demonstrated up to 100% memory cell yield, 100ns programming and read speeds, and write currents as low as 1mA/bit. Devices functioned normally from - 55 deg. C to 125 deg. C. Write/read endurance has been demonstrated to 1 x 108 before first bit failure. Radiation results show no degradation to the hardened CMOS or effects that can be attributed to the phase-change material. Future applications of the technology are discussed.

  13. PREFACE: Emerging non-volatile memories: magnetic and resistive technologies Emerging non-volatile memories: magnetic and resistive technologies

    NASA Astrophysics Data System (ADS)

    Dieny, B.; Jagadish, Chennupati

    2013-02-01

    In 2010, the International Technology Roadmap for Semiconductors (ITRS) published an assessment of the potential and maturity of selected emerging research on memory technologies. Eight different technologies of non-volatile memories were compared (ferroelectric gate field-effect transistor, nano-electro-mechanical switch, spin-transfer torque random access memories (STTRAM), various types of resistive RAM, in particular redox RAM, nanothermal phase change RAM, electronic effects RAM, macromolecular memories and molecular RAM). In this report, spin-transfer torque MRAM and redox RRAM were identified as two emerging memory technologies recommended for accelerated research and development leading to scaling and commercialization of non-volatile RAM to and beyond the 16nm generation. Nowadays, there is an intense research and development effort in microelectronics on these two technologies, one based on spintronic phenomena (tunnel magnetoresistance and spin-transfer torque), the other based on migration of vacancies or ions in an insulating matrix driven by oxydo-reduction potentials. Both technologies could be used for standalone or embedded applications. In this context, it appeared timely to publish a cluster of review articles related to these two technologies. In this cluster, the first two articles introduce the general principles of spin-transfer torque RAM and of thermally assisted RAM. The third presents a broader range of applications for this integrated CMOS/magnetic tunnel junction technology for low-power electronics. The fourth paper presents more advanced research on voltage control of magnetization switching with the aim of dramatically reducing the write energy in MRAM. The last two papers deal with two categories of resistive RAM, one based on the migration of cations, the other one based on nanowires. We thank all the authors and reviewers for their contribution to this cluster issue. Our special thanks are due to Dr Olivia Roche, Publisher, and Dr

  14. Graphene-quantum-dot nonvolatile charge-trap flash memories.

    PubMed

    Sin Joo, Soong; Kim, Jungkil; Kang, Soo Seok; Kim, Sung; Choi, Suk-Ho; Hwang, Sung Won

    2014-06-27

    Nonvolatile flash-memory capacitors containing graphene quantum dots (GQDs) of 6, 12, and 27 nm average sizes (d) between SiO2 layers for use as charge traps have been prepared by sequential processes: ion-beam sputtering deposition (IBSD) of 10 nm SiO2 on a p-type wafer, spin-coating of GQDs on the SiO2 layer, and IBSD of 20 nm SiO2 on the GQD layer. The presence of almost a single array of GQDs at a distance of ∼13 nm from the SiO2/Si wafer interface is confirmed by transmission electron microscopy and photoluminescence. The memory window estimated by capacitance-voltage curves is proportional to d for sweep voltages wider than  ± 3 V, and for d = 27 nm the GQD memories show a maximum memory window of 8 V at a sweep voltage of  ± 10 V. The program and erase speeds are largest at d = 12 and 27 nm, respectively, and the endurance and data-retention properties are the best at d = 27 nm. These memory behaviors can be attributed to combined effects of edge state and quantum confinement.

  15. High-Performance Nonvolatile Organic Field-Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers.

    PubMed

    Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Yi, Mingdong; Wang, Laiyuan; Wu, Dequn; Xie, Linghai; Huang, Wei

    2017-08-01

    Nonvolatile organic field-effect transistor (OFET) memory devices based on pentacene/N,N'-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n-type P13 embedded in p-type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well-like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge-trapping property of the poly(4-vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high-performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory.

  16. Organic CuTCNQ integrated in complementary metal oxide semiconductor copper back end-of-line for nonvolatile memories

    NASA Astrophysics Data System (ADS)

    Müller, R.; De Jonge, S.; Myny, K.; Wouters, D. J.; Genoe, J.; Heremans, P.

    2006-11-01

    Nanowires of the organometallic semiconductor CuTCNQ were grown from TCNQ vapor in 250nm diameter vias of a Cu back end-of-line process. Corresponding prototypes of cross-point Cu /CuTCNQ nanowire/Al memories exhibited nonvolatile bistable conductive switching for several ten write-erase cycles with switching currents below 10μA and current densities 1000 times higher than for large-area devices. Scaling of memory elements was also investigated.

  17. Design considerations for a radiation hardened nonvolatile memory

    SciTech Connect

    Murray, J.R.

    1993-02-01

    The SA3823 64K EEPROM was developed for both weapon and space applications. The circuit was designed for fabrication in a CMOS/SNOS (Complementary Metal Oxide Semiconductor/Silicon Nitride Oxide Semiconductor) process since this process offers maximum radiation hardness for nonvolatile circuits. [1--6] Specific aspects of the circuit design were influenced by each of the radiation environments of concern. Total dose radiation effects were a factor in the memory cell and sense amplifier designs. Power distribution to the various latches was designed to tolerate the photocurrents generated during a transient radiation pulse. Single event upset (SEU) concerns were accounted for in the design of the latches and the control logic. The SA3823 is a 8K x 8 bit EEPROM which is partitioned into 128 pages with 64 bytes in each page. Data is programmed into the memory one page at a time. Writing data into the memory is a two step process: loading 64 bytes into the data-in latches and then programming the latched data into a page of the memory.

  18. Design considerations for a radiation hardened nonvolatile memory

    SciTech Connect

    Murray, J.R.

    1993-01-01

    The SA3823 64K EEPROM was developed for both weapon and space applications. The circuit was designed for fabrication in a CMOS/SNOS (Complementary Metal Oxide Semiconductor/Silicon Nitride Oxide Semiconductor) process since this process offers maximum radiation hardness for nonvolatile circuits. [1--6] Specific aspects of the circuit design were influenced by each of the radiation environments of concern. Total dose radiation effects were a factor in the memory cell and sense amplifier designs. Power distribution to the various latches was designed to tolerate the photocurrents generated during a transient radiation pulse. Single event upset (SEU) concerns were accounted for in the design of the latches and the control logic. The SA3823 is a 8K x 8 bit EEPROM which is partitioned into 128 pages with 64 bytes in each page. Data is programmed into the memory one page at a time. Writing data into the memory is a two step process: loading 64 bytes into the data-in latches and then programming the latched data into a page of the memory.

  19. Reduced graphene oxide based flexible organic charge trap memory devices

    NASA Astrophysics Data System (ADS)

    Rani, Adila; Song, Ji-Min; Jung Lee, Mi; Lee, Jang-Sik

    2012-12-01

    A nonvolatile organic transistor memory device was developed using layer-by-layer assembly of 3-aminopropyltriethoxysilane (APTES) and solution-processed, reduced graphene oxide (rGO) as the charge trapping layer on flexible substrates. Reduction of graphene oxide and successful adsorption of the rGO on APTES-covered substrates were confirmed. The organic memory devices based on rGO exhibited reliable programmable memory operations, confirmed by program/erase operations, data retention, and endurance properties. These methods can potentially play a significant role in the fabrication of next-generation flexible nonvolatile memory devices based on graphene materials.

  20. P(VDF-TrFE-CFE) terpolymer thin-film for high performance nonvolatile memory

    NASA Astrophysics Data System (ADS)

    Chen, Xin; Liu, Lu; Liu, Shi-Zheng; Cui, Yu-Shuang; Chen, Xiang-Zhong; Ge, Hai-Xiong; Shen, Qun-Dong

    2013-02-01

    Vinylidene fluoride-trifluoroethylene-chlorofluoroethylene terpolymer, P(VDF-TrFE-CFE), with small amount of CFE is utilized for thin-film nonvolatile memory. Polarization switching voltage for a 50 nm-thick film can be as low as 1 V, and is well suited for integrated driving electronics. The writing-erasing procedure is completely reversible. High signal-to-noise and high capability for data storage are observed in this memory system. Polarization state of the terpolymer is rather stable, making it applicable for memory devices. Polarization switching behavior in the terpolymer can be ascribed to reduced polar domain size with respect to the P(VDF-TrFE) copolymer, and energy cost of domain wall motion during electrically polarization switching decreases.

  1. Opportunities for nonvolatile memory systems in extreme-scale high-performance computing

    DOE PAGES

    Vetter, Jeffrey S.; Mittal, Sparsh

    2015-01-12

    For extreme-scale high-performance computing systems, system-wide power consumption has been identified as one of the key constraints moving forward, where DRAM main memory systems account for about 30 to 50 percent of a node's overall power consumption. As the benefits of device scaling for DRAM memory slow, it will become increasingly difficult to keep memory capacities balanced with increasing computational rates offered by next-generation processors. However, several emerging memory technologies related to nonvolatile memory (NVM) devices are being investigated as an alternative for DRAM. Moving forward, NVM devices could offer solutions for HPC architectures. Researchers are investigating how to integratemore » these emerging technologies into future extreme-scale HPC systems and how to expose these capabilities in the software stack and applications. In addition, current results show several of these strategies could offer high-bandwidth I/O, larger main memory capacities, persistent data structures, and new approaches for application resilience and output postprocessing, such as transaction-based incremental checkpointing and in situ visualization, respectively.« less

  2. Opportunities for nonvolatile memory systems in extreme-scale high-performance computing

    SciTech Connect

    Vetter, Jeffrey S.; Mittal, Sparsh

    2015-01-12

    For extreme-scale high-performance computing systems, system-wide power consumption has been identified as one of the key constraints moving forward, where DRAM main memory systems account for about 30 to 50 percent of a node's overall power consumption. As the benefits of device scaling for DRAM memory slow, it will become increasingly difficult to keep memory capacities balanced with increasing computational rates offered by next-generation processors. However, several emerging memory technologies related to nonvolatile memory (NVM) devices are being investigated as an alternative for DRAM. Moving forward, NVM devices could offer solutions for HPC architectures. Researchers are investigating how to integrate these emerging technologies into future extreme-scale HPC systems and how to expose these capabilities in the software stack and applications. In addition, current results show several of these strategies could offer high-bandwidth I/O, larger main memory capacities, persistent data structures, and new approaches for application resilience and output postprocessing, such as transaction-based incremental checkpointing and in situ visualization, respectively.

  3. Quasi-unipolar pentacene films embedded with fullerene for non-volatile organic transistor memories

    SciTech Connect

    Lee, Juhee; Lee, Sungpyo; Lee, Moo Hyung; Kang, Moon Sung

    2015-02-09

    Quasi-unipolar non-volatile organic transistor memory (NOTM) can combine the best characteristics of conventional unipolar and ambipolar NOTMs and, as a result, exhibit improved device performance. Unipolar NOTMs typically exhibit a large signal ratio between the programmed and erased current signals but also require a large voltage to program and erase the memory cells. Meanwhile, an ambipolar NOTM can be programmed and erased at lower voltages, but the resulting signal ratio is small. By embedding a discontinuous n-type fullerene layer within a p-type pentacene film, quasi-unipolar NOTMs are fabricated, of which the signal storage utilizes both electrons and holes while the electrical signal relies on only hole conduction. These devices exhibit superior memory performance relative to both pristine unipolar pentacene devices and ambipolar fullerene/pentacene bilayer devices. The quasi-unipolar NOTM exhibited a larger signal ratio between the programmed and erased states while also reducing the voltage required to program and erase a memory cell. This simple approach should be readily applicable for various combinations of advanced organic semiconductors that have been recently developed and thereby should make a significant impact on organic memory research.

  4. A facile synthesis of CH3NH3PbBr3 perovskite quantum dots and their application in flexible nonvolatile memory

    NASA Astrophysics Data System (ADS)

    Yang, Kaiyu; Li, Fushan; Veeramalai, Chandrasekar Perumal; Guo, Tailiang

    2017-02-01

    In this work, we present a simple and facile one step synthesis strategy to prepare CH3NH3PbBr3 perovskite quantum dots and apply them into the nonvolatile memory. Resistive switching phenomenon was observed in this perovskite quantum dots and polymer composite based memory device with the ON/OFF current ratio larger than 103 as well as good reproducibility and reliability. Flexible memory was also demonstrated, and a possible resistance switching mechanism was discussed. Our work paves a way for the application of organolead halide perovskite quantum dots in flexible and transparent nonvolatile memories.

  5. Quantum Dot Channel (QDC) Field Effect Transistors (FETs) and Floating Gate Nonvolatile Memory Cells

    NASA Astrophysics Data System (ADS)

    Kondo, J.; Lingalugari, M.; Chan, P.-Y.; Heller, E.; Jain, F.

    2015-09-01

    This paper presents silicon quantum dot channel (QDC) field effect transistors (FETs) and floating gate nonvolatile memory structures. The QDC-FET operation is explained by carrier transport in narrow mini-energy bands which are manifested in an array of SiO x -cladded silicon quantum dot layers. For nonvolatile memory structures, simulations of electron charge densities in the floating quantum dot layers are presented. Experimental threshold voltage shift in I D- V G characteristics is presented after the `Write' cycle. The QDC-FETs and nonvolatile memory due to improved threshold voltage variations by incorporating the lattice-matched II-VI layer as the gate insulator.

  6. Electrically Variable Resistive Memory Devices

    NASA Technical Reports Server (NTRS)

    Liu, Shangqing; Wu, Nai-Juan; Ignatiev, Alex; Charlson, E. J.

    2010-01-01

    Nonvolatile electronic memory devices that store data in the form of electrical- resistance values, and memory circuits based on such devices, have been invented. These devices and circuits exploit an electrically-variable-resistance phenomenon that occurs in thin films of certain oxides that exhibit the colossal magnetoresistive (CMR) effect. It is worth emphasizing that, as stated in the immediately preceding article, these devices function at room temperature and do not depend on externally applied magnetic fields. A device of this type is basically a thin film resistor: it consists of a thin film of a CMR material located between, and in contact with, two electrical conductors. The application of a short-duration, low-voltage current pulse via the terminals changes the electrical resistance of the film. The amount of the change in resistance depends on the size of the pulse. The direction of change (increase or decrease of resistance) depends on the polarity of the pulse. Hence, a datum can be written (or a prior datum overwritten) in the memory device by applying a pulse of size and polarity tailored to set the resistance at a value that represents a specific numerical value. To read the datum, one applies a smaller pulse - one that is large enough to enable accurate measurement of resistance, but small enough so as not to change the resistance. In writing, the resistance can be set to any value within the dynamic range of the CMR film. Typically, the value would be one of several discrete resistance values that represent logic levels or digits. Because the number of levels can exceed 2, a memory device of this type is not limited to binary data. Like other memory devices, devices of this type can be incorporated into a memory integrated circuit by laying them out on a substrate in rows and columns, along with row and column conductors for electrically addressing them individually or collectively.

  7. Analysis of charge loss in nonvolatile memory with multi-layered SiC nanocrystals

    NASA Astrophysics Data System (ADS)

    Lee, Dong Uk; Lee, Tae Hee; Kim, Eun Kyu; Shin, Jin-Wook; Cho, Won-Ju

    2009-08-01

    A nonvolatile memory device with multilayered SiC nanocrystals for long-term data storage was fabricated, and its electrical properties were analyzed. The average size and density of the SiC nanocrystals, which were formed between the tunnel and control oxide layers, were approximately 5 nm and 2×1012 cm-2, respectively. The memory window of nonvolatile memory with the multilayer of SiC nanocrystals was about 2.5 V after program and erase voltages of ±12 V were applied for 500 ms, and then it was maintained at about 1.1 V for 105 s at 75 °C. The activation energy estimated from charge losses of 25% to 50% increased from 0.03 to 0.30 eV, respectively. The charge loss could be caused by a Pool-Frenkel current of holes and electrons between the SiC quantum dots and the carrier charge traps around the SiC nanocrystals embedded in SiO2 or the degradation effect of the tunnel oxide by stress induced leakage current.

  8. Attachable and flexible aluminum oxide resistive non-volatile memory arrays fabricated on tape as the substrate.

    PubMed

    Lee, Woocheol; Jang, Jingon; Song, Younggul; Cho, Kyungjune; Yoo, Daekyoung; Kim, Youngrok; Chung, Seungjun; Lee, Takhee

    2017-03-01

    We fabricated 8 × 8 arrays of non-volatile resistive memory devices on commercially available Scotch(®) Magic(™) tape as a flexible substrate. The memory devices consist of double active layers of Al2O3 with a structure of Au/Al2O3/Au/Al2O3/Al (50 nm/20 nm/20 nm/20 nm/50 nm) on attachable tape substrates. Because the memory devices were fabricated using only dry and low temperature processes, the tape substrate did not suffer from any physical or chemical damage during the fabrication. The fabricated memory devices were turned to the low resistance state at ∼3.5 V and turned to the high resistance state at ∼10 V with a negative differential resistance region after ∼5 V, showing typical unipolar non-volatile resistive memory behavior. The memory devices on the tape substrates exhibited reasonable electrical performances including a high ON/OFF ratio of 10(4), endurance over 200 cycles of reading/writing processes, and retention times of over 10(4) s in both the flat and bent configurations.

  9. Attachable and flexible aluminum oxide resistive non-volatile memory arrays fabricated on tape as the substrate

    NASA Astrophysics Data System (ADS)

    Lee, Woocheol; Jang, Jingon; Song, Younggul; Cho, Kyungjune; Yoo, Daekyoung; Kim, Youngrok; Chung, Seungjun; Lee, Takhee

    2017-03-01

    We fabricated 8 × 8 arrays of non-volatile resistive memory devices on commercially available Scotch® Magic™ tape as a flexible substrate. The memory devices consist of double active layers of Al2O3 with a structure of Au/Al2O3/Au/Al2O3/Al (50 nm/20 nm/20 nm/20 nm/50 nm) on attachable tape substrates. Because the memory devices were fabricated using only dry and low temperature processes, the tape substrate did not suffer from any physical or chemical damage during the fabrication. The fabricated memory devices were turned to the low resistance state at ∼3.5 V and turned to the high resistance state at ∼10 V with a negative differential resistance region after ∼5 V, showing typical unipolar non-volatile resistive memory behavior. The memory devices on the tape substrates exhibited reasonable electrical performances including a high ON/OFF ratio of 104, endurance over 200 cycles of reading/writing processes, and retention times of over 104 s in both the flat and bent configurations.

  10. Six-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions

    NASA Astrophysics Data System (ADS)

    Suzuki, D.; Natsui, M.; Endoh, T.; Ohno, H.; Hanyu, T.

    2012-04-01

    A compact 6-input lookup table (LUT) circuit using nonvolatile logic-in-memory (LIM) architecture with series/parallel-connected magnetic tunnel junction (MTJ) devices is proposed for a standby-power-free field-programmable gate array. Series/parallel connections of MTJ devices make it possible not only to reduce the effect of resistance variation, but also to enhance the programmability of resistance values, which achieves a sufficient sensing margin even when process variation is serious in the recent nanometer-scaled VLSI. Moreover, the additional MTJ devices do not increase the effective chip area because the configuration circuit using MTJ devices is simplified and these devices are stacked over the CMOS plane. As a result, the transistor counts of the proposed circuit are reduced by 62% in comparison with those of a conventional nonvolatile LUT circuit where CMOS-only-based volatile static random access memory cell circuits are replaced by MTJ-based nonvolatile ones.

  11. Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

    SciTech Connect

    Wang, Shun; Gao, Xu E-mail: gaoxu@suda.edu.cn; Zhong, Ya-Nan; Zhang, Zhong-Da; Xu, Jian-Long; Wang, Sui-Dong E-mail: gaoxu@suda.edu.cn

    2016-07-11

    High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio and good memory retention.

  12. Hot Carrier Trapping Induced Negative Photoconductance in InAs Nanowires toward Novel Nonvolatile Memory.

    PubMed

    Yang, Yiming; Peng, Xingyue; Kim, Hong-Seok; Kim, Taeho; Jeon, Sanghun; Kang, Hang Kyu; Choi, Wonjun; Song, Jindong; Doh, Yong-Joo; Yu, Dong

    2015-09-09

    We report a novel negative photoconductivity (NPC) mechanism in n-type indium arsenide nanowires (NWs). Photoexcitation significantly suppresses the conductivity with a gain up to 10(5). The origin of NPC is attributed to the depletion of conduction channels by light assisted hot electron trapping, supported by gate voltage threshold shift and wavelength-dependent photoconductance measurements. Scanning photocurrent microscopy excludes the possibility that NPC originates from the NW/metal contacts and reveals a competing positive photoconductivity. The conductivity recovery after illumination substantially slows down at low temperature, indicating a thermally activated detrapping mechanism. At 78 K, the spontaneous recovery of the conductance is completely quenched, resulting in a reversible memory device, which can be switched by light and gate voltage pulses. The novel NPC based optoelectronics may find exciting applications in photodetection and nonvolatile memory with low power consumption.

  13. Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

    NASA Astrophysics Data System (ADS)

    Wang, Shun; Gao, Xu; Zhong, Ya-Nan; Zhang, Zhong-Da; Xu, Jian-Long; Wang, Sui-Dong

    2016-07-01

    High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio and good memory retention.

  14. Reconfigurable magnetic logic combined with non-volatile memory in silicon

    NASA Astrophysics Data System (ADS)

    Luo, Zhaochu; Zhang, Xiaozhong

    Silicon-based complementary metal-oxide-semiconductor (CMOS) transistors have achieved great success and become the mainstream of integrated logic circuits. However, the traditional pathway to enhance computational performance and decrease cost by continuous miniaturization is approaching its fundamental limits. The recent emergence of magnetic logic devices, especially magnetic-field-based semiconductor logic devices, shows promise for surpassing the development limits of CMOS logic and arouses profound attentions. Based on our Si based magnetoresistance (MR) device, we proposed a Si based reconfigurable magnetic logic device by coupling nonlinear transport effect and Hall effect in Si, which could do all four basic Boolean logic operations including AND, OR, NOR and NAND combined with non-volatile memory. Further, we developed a Si based current-mode magnetic logic device, which allowed direct communication between different logic devices by current-induced magnetization switch effect without external intermediate magnetic-electric converters. This may result in a memory-logic integrated system leading to a non von Neumann computer.

  15. Nonvolatile Memory Solution for Near-Term NASA Missions

    NASA Technical Reports Server (NTRS)

    Patel, J. U.; Blaes, B. R.; Mojarradi, M. M.

    2001-01-01

    Nonvolatile memory (NVM) system that could reliably function in extreme environments is one of the most critical components for many spacecrafts being developed for NASA missions to be launched in next four to seven years. NVM supports the computer system in saving and updating critical state data required for a warm restart after power cycling or in case of a power bus failure. It also provides a power independent mass storage capacity for the scientific data gathered by the instruments. In some cases the window for gathering such data is very small and occurs only once in a given mission. Commercially popular and fully developed Flash NVM technology is inappropriate for many reasons such as the limited read write cycles with slower access speeds, radiation intolerance, higher Single Event Upsets (SEU) rates, etc. It is desirable to have an NVM system based upon a robust cell technology making it immune to the SEUs and with sufficient radiation hardness. Availability of such NVM system seems to be still 5 to 10 years in the future. Meanwhile, it is possible to provide an interim hybrid solution by combining the existing rad-hard technologies. Additional information is contained in the original extended abstract.

  16. Nonvolatile Memory Solution for Near-Term NASA Missions

    NASA Technical Reports Server (NTRS)

    Patel, J. U.; Blaes, B. R.; Mojarradi, M. M.

    2001-01-01

    Nonvolatile memory (NVM) system that could reliably function in extreme environments is one of the most critical components for many spacecrafts being developed for NASA missions to be launched in next four to seven years. NVM supports the computer system in saving and updating critical state data required for a warm restart after power cycling or in case of a power bus failure. It also provides a power independent mass storage capacity for the scientific data gathered by the instruments. In some cases the window for gathering such data is very small and occurs only once in a given mission. Commercially popular and fully developed Flash NVM technology is inappropriate for many reasons such as the limited read write cycles with slower access speeds, radiation intolerance, higher Single Event Upsets (SEU) rates, etc. It is desirable to have an NVM system based upon a robust cell technology making it immune to the SEUs and with sufficient radiation hardness. Availability of such NVM system seems to be still 5 to 10 years in the future. Meanwhile, it is possible to provide an interim hybrid solution by combining the existing rad-hard technologies. Additional information is contained in the original extended abstract.

  17. Electrostatic Switching in Vertically Oriented Nanotubes for Nonvolatile Memory Applications

    NASA Technical Reports Server (NTRS)

    Kaul, Anupama B.; Khan, Paul; Jennings, Andrew T.; Greer, Julia R.; Megerian, Krikor G.; Allmen, Paul von

    2009-01-01

    We have demonstrated electrostatic switching in vertically oriented nanotubes or nanofibers, where a nanoprobe was used as the actuating electrode inside an SEM. When the nanoprobe was manipulated to be in close proximity to a single tube, switching voltages between 10 V - 40 V were observed, depending on the geometrical parameters. The turn-on transitions appeared to be much sharper than the turn-off transitions which were limited by the tube-to-probe contact resistances. In many cases, stiction forces at these dimensions were dominant, since the tube appeared stuck to the probe even after the voltage returned to 0 V, suggesting that such structures are promising for nonvolatile memory applications. The stiction effects, to some extent, can be adjusted by engineering the switch geometry appropriately. Nanoscale mechanical measurements were also conducted on the tubes using a custom-built anoindentor inside an SEM, from which preliminary material parameters, such as the elastic modulus, were extracted. The mechanical measurements also revealed that the tubes appear to be well adhered to the substrate. The material parameters gathered from the mechanical measurements were then used in developing an electrostatic model of the switch using a commercially available finite-element simulator. The calculated pull-in voltages appeared to be in agreement to the experimentally obtained switching voltages to first order.

  18. Electrostatic Switching in Vertically Oriented Nanotubes for Nonvolatile Memory Applications

    NASA Technical Reports Server (NTRS)

    Kaul, Anupama B.; Khan, Paul; Jennings, Andrew T.; Greer, Julia R.; Megerian, Krikor G.; Allmen, Paul von

    2009-01-01

    We have demonstrated electrostatic switching in vertically oriented nanotubes or nanofibers, where a nanoprobe was used as the actuating electrode inside an SEM. When the nanoprobe was manipulated to be in close proximity to a single tube, switching voltages between 10 V - 40 V were observed, depending on the geometrical parameters. The turn-on transitions appeared to be much sharper than the turn-off transitions which were limited by the tube-to-probe contact resistances. In many cases, stiction forces at these dimensions were dominant, since the tube appeared stuck to the probe even after the voltage returned to 0 V, suggesting that such structures are promising for nonvolatile memory applications. The stiction effects, to some extent, can be adjusted by engineering the switch geometry appropriately. Nanoscale mechanical measurements were also conducted on the tubes using a custom-built anoindentor inside an SEM, from which preliminary material parameters, such as the elastic modulus, were extracted. The mechanical measurements also revealed that the tubes appear to be well adhered to the substrate. The material parameters gathered from the mechanical measurements were then used in developing an electrostatic model of the switch using a commercially available finite-element simulator. The calculated pull-in voltages appeared to be in agreement to the experimentally obtained switching voltages to first order.

  19. Effects of Heavy Ion Exposure on Nanocrystal Nonvolatile Memory

    NASA Technical Reports Server (NTRS)

    Oldham, Timothy R.; Suhail, Mohammed; Kuhn, Peter; Prinz, Erwin; Kim, Hak; LaBel, Kenneth A.

    2004-01-01

    We have irradiated engineering samples of Freescale 4M nonvolatile memories with heavy ions. They use Silicon nanocrystals as the storage element, rather than the more common floating gate. The irradiations were performed using the Texas A&M University cyclotron Single Event Effects Test Facility. The chips were tested in the static mode, and in the dynamic read mode, dynamic write (program) mode, and dynamic erase mode. All the errors observed appeared to be due to single, isolated bits, even in the program and erase modes. These errors appeared to be related to the micro-dose mechanism. All the errors corresponded to the loss of electrons from a programmed cell. The underlying physical mechanisms will be discussed in more detail later. There were no errors, which could be attributed to malfunctions of the control circuits. At the highest LET used in the test (85 MeV/mg/sq cm), however, there appeared to be a failure due to gate rupture. Failure analysis is being conducted to confirm this conclusion. There was no unambiguous evidence of latchup under any test conditions. Generally, the results on the nanocrystal technology compare favorably with results on currently available commercial floating gate technology, indicating that the technology is promising for future space applications, both civilian and military.

  20. Nonvolatile memory with graphene oxide as a charge storage node in nanowire field-effect transistors

    NASA Astrophysics Data System (ADS)

    Baek, David J.; Seol, Myeong-Lok; Choi, Sung-Jin; Moon, Dong-Il; Choi, Yang-Kyu

    2012-02-01

    Through the structural modification of a three-dimensional silicon nanowire field-effect transistor, i.e., a double-gate FinFET, a structural platform was developed which allowed for us to utilize graphene oxide (GO) as a charge trapping layer in a nonvolatile memory device. By creating a nanogap between the gate and the channel, GO was embedded after the complete device fabrication. By applying a proper gate voltage, charge trapping, and de-trapping within the GO was enabled and resulted in large threshold voltage shifts. The employment of GO with FinFET in our work suggests that graphitic materials can potentially play a significant role for future nanoelectronic applications.

  1. A Vertical Organic Transistor Architecture for Fast Nonvolatile Memory.

    PubMed

    She, Xiao-Jian; Gustafsson, David; Sirringhaus, Henning

    2017-02-01

    A new device architecture for fast organic transistor memory is developed, based on a vertical organic transistor configuration incorporating high-performance ambipolar conjugated polymers and unipolar small molecules as the transport layers, to achieve reliable and fast programming and erasing of the threshold voltage shift in less than 200 ns.

  2. High performance organic nonvolatile memory transistors based on HfO2 and poly(α-methylstyrene) electret hybrid charge-trapping layers

    NASA Astrophysics Data System (ADS)

    Xu, W. C.; He, H. X.; Jing, X. S.; Wu, S. J.; Zhang, Z.; Gao, J. W.; Gao, X. S.; Zhou, G. F.; Lu, X. B.; Liu, J.-M.

    2017-08-01

    In this work, we fabricated a high performance flash-type organic nonvolatile memory transistor, which adopted polymer-electret poly(α-methylstyrene) (PαMS) and HfO2 films as hybrid charge trapping layer (CTL). Compared with a single HfO2 or PαMS CTL structure, the hybrid HfO2/PαMS CTL structure can provide enhanced charge trapping efficiency to increase the device operation speed and reduce the leakage current to boost the device reliability. The fabricated nonvolatile organic memory transistors with the hybrid CTL shows excellent electrical properties, including low operation voltage (8 V), high speed (<10 ms), excellent data retention (on-off current ratio of 2.6 × 104 after 104 s), and good endurance (more than 2000 program/erase cycles). The present work provides useful idea for the design of future low-power consumption and highly reliable organic nonvolatile memories.

  3. Biomolecule nanoparticle-induced nanocomposites with resistive switching nonvolatile memory properties

    NASA Astrophysics Data System (ADS)

    Ko, Yongmin; Ryu, Sook Won; Cho, Jinhan

    2016-04-01

    Resistive switching behavior-based memory devices are considered promising candidates for next-generation data storage because of their simple structure configuration, low power consumption, and rapid operating speed. Here, the resistive switching nonvolatile memory properties of Fe2O3 nanocomposite (NC) films prepared from the thermal calcination of layer-by-layer (LbL) assembled ferritin multilayers were successfully investigated. For this study, negatively charged ferritin nanoparticles were alternately deposited onto the Pt-coated Si substrate with positively charged poly(allylamine hydrochloride) (PAH) by solution-based electrostatic LbL assembly, and the formed multilayers were thermally calcinated to obtain a homogeneous transition metal oxide NC film through the elimination of organic components, including the protein shell of ferritin. The formed memory device exhibits a stable ON/OFF current ratio of approximately 103, with nanosecond switching times under an applied external bias. In addition, these reversible switching properties were kept stable during the repeated cycling tests of above 200 cycles and a test period of approximately 105 s under atmosphere. These solution-based approaches can provide a basis for large-area inorganic nanoparticle-based electric devices through the design of bio-nanomaterials at the molecular level.

  4. Blackcomb: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems

    SciTech Connect

    Schreiber, Robert

    2014-11-26

    Summary of technical results of Blackcomb Memory Devices We explored various different memory technologies (STTRAM, PCRAM, FeRAM, and ReRAM). The progress can be classified into three categories, below. Modeling and Tool Releases Various modeling tools have been developed over the last decade to help in the design of SRAM or DRAM-based memory hierarchies. To explore new design opportunities that NVM technologies can bring to the designers, we have developed similar high-level models for NVM, including PCRAMsim [Dong 2009], NVSim [Dong 2012], and NVMain [Poremba 2012]. NVSim is a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies. On the other side, NVMain is a cycle accurate main memory simulator designed to simulate emerging nonvolatile memories at the architectural level. We have released these models as open source tools and provided contiguous support to them. We also proposed PS3-RAM, which is a fast, portable and scalable statistical STT-RAM reliability analysis model [Wen 2012]. Design Space Exploration and Optimization With the support of these models, we explore different device/circuit optimization techniques. For example, in [Niu 2012a] we studied the power reduction technique for the application of ECC scheme in ReRAM designs and proposed to use ECC code to relax the BER (Bit Error Rate) requirement of a single memory to improve the write energy consumption and latency for both 1T1R and cross-point ReRAM designs. In [Xu 2011], we proposed a methodology to design STT-RAM for different optimization goals such as read performance, write performance and write energy by leveraging the trade-off between write current and write time of MTJ. We also studied the tradeoffs in building a reliable crosspoint Re

  5. The floating-gate non-volatile semiconductor memory--from invention to the digital age.

    PubMed

    Sze, S M

    2012-10-01

    In the past 45 years (from 1967 to 2012), the non-volatile semiconductor memory (NVSM) has emerged from a floating-gate concept to the prime technology driver of the largest industry in the world-the electronics industry. In this paper, we briefly review the historical development of NVSM and project its future trends to the year 2020. In addition, we consider NVSM's wide-range of applications from the digital cellular phone to tablet computer to digital television. As the device dimension is scaled down to the deca-nanometer regime, we expect that many innovations will be made to meet the scaling challenges, and NVSM-inspired technology will continue to enrich and improve our lives for decades to come.

  6. Influence of silicon nanocrystal size and density on the performance of non-volatile memory arrays

    NASA Astrophysics Data System (ADS)

    Rao, R. A.; Gasquet, H. P.; Steimle, R. F.; Rinkenberger, G.; Straub, S.; Muralidhar, R.; Anderson, S. G. H.; Yater, J. A.; Ledezma, J. C.; Hamilton, J.; Acred, B.; Swift, C. T.; Hradsky, B.; Peschke, J.; Sadd, M.; Prinz, E. J.; Chang, K. M.; White, B. E.

    2005-11-01

    Silicon nanocrystal memories offer opportunities for voltage scaling and process simplification for embedded non-volatile memories. While electrically isolated nanocrystals mitigate charge loss through oxide defects, the impact of nanocrystal size and density characteristics as well as statistical fluctuations on memory arrays is not well understood. This paper shows that the memory window and high temperature data retention are roughly insensitive over a broad range of nanocrystal characteristics. Further, data from mega-bit arrays shows that nanocrystal coalescence effects are small.

  7. Properties of Dopants in HfOx for Improving the Performance of Nonvolatile Memory

    NASA Astrophysics Data System (ADS)

    Duncan, Dan; Magyari-Köpe, Blanka; Nishi, Yoshio

    2017-03-01

    Doping is an increasingly popular technique for improving the characteristics of cutting-edge HfOx nonvolatile memory devices, but relatively few dopant species have been investigated. In this work, the properties of 50 different cation and anion dopants in HfOx are explored using density-functional theory and are corroborated with experimental data. Depending on the atomic species, dopants are found to preferentially form on either substitutional or interstitial lattice sites and to reduce the formation energy of oxygen vacancies in the surrounding oxide. The behavior of cation dopants in HfOx is also found to be well predicted by six properties: dopant valence, atomic radius, native-oxide enthalpy of formation, coordination number, magnetization, and charge transfer with the HfOx lattice. These results can be used to optimize dopant selection for tuning of the switching characteristics of HfOx -based resistance-change random-access-memory and conductive-bridge random-access-memory devices.

  8. Radiation Tests of Highly scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories--Update 2011

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Nguyen, Duc N.

    2011-01-01

    High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) 32Gb and multi-level cell (MLC) 64Gb NAND flash memories manufactured by Micron Technology.

  9. Radiation Tests of Highly scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories--Update 2011

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Nguyen, Duc N.

    2011-01-01

    High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) 32Gb and multi-level cell (MLC) 64Gb NAND flash memories manufactured by Micron Technology.

  10. Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2010

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Nguyen, Duc N.

    2010-01-01

    High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) and multi-level cell (MLC) NAND flash memories manufactured by Micron Technology.

  11. Epitaxial Growth of Thin Ferroelectric Polymer Films on Graphene Layer for Fully Transparent and Flexible Nonvolatile Memory.

    PubMed

    Kim, Kang Lib; Lee, Wonho; Hwang, Sun Kak; Joo, Se Hun; Cho, Suk Man; Song, Giyoung; Cho, Sung Hwan; Jeong, Beomjin; Hwang, Ihn; Ahn, Jong-Hyun; Yu, Young-Jun; Shin, Tae Joo; Kwak, Sang Kyu; Kang, Seok Ju; Park, Cheolmin

    2016-01-13

    Enhancing the device performance of organic memory devices while providing high optical transparency and mechanical flexibility requires an optimized combination of functional materials and smart device architecture design. However, it remains a great challenge to realize fully functional transparent and mechanically durable nonvolatile memory because of the limitations of conventional rigid, opaque metal electrodes. Here, we demonstrate ferroelectric nonvolatile memory devices that use graphene electrodes as the epitaxial growth substrate for crystalline poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) polymer. The strong crystallographic interaction between PVDF-TrFE and graphene results in the orientation of the crystals with distinct symmetry, which is favorable for polarization switching upon the electric field. The epitaxial growth of PVDF-TrFE on a graphene layer thus provides excellent ferroelectric performance with high remnant polarization in metal/ferroelectric polymer/metal devices. Furthermore, a fully transparent and flexible array of ferroelectric field effect transistors was successfully realized by adopting transparent poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] semiconducting polymer.

  12. Nonvolatile nuclear spin memory enables sensor-unlimited nanoscale spectroscopy of small spin clusters.

    PubMed

    Pfender, Matthias; Aslam, Nabeel; Sumiya, Hitoshi; Onoda, Shinobu; Neumann, Philipp; Isoya, Junichi; Meriles, Carlos A; Wrachtrup, Jörg

    2017-10-10

    In nanoscale metrology, dissipation of the sensor limits its performance. Strong dissipation has a negative impact on sensitivity, and sensor-target interaction even causes relaxation or dephasing of the latter. The weak dissipation of nitrogen-vacancy (NV) sensors in room temperature diamond enables detection of individual target nuclear spins, yet limits the spectral resolution of nuclear magnetic resonance (NMR) spectroscopy to several hundred Hertz, which typically prevents molecular recognition. Here, we use the NV intrinsic nuclear spin as a nonvolatile classical memory to store NMR information, while suppressing sensor back-action on the target using controlled decoupling of sensor, memory, and target. We demonstrate memory lifetimes up to 4 min and apply measurement and decoupling protocols, which exploit such memories efficiently. Our universal NV-based sensor device records single-spin NMR spectra with 13 Hz resolution at room temperature.Dissipation of the sensor is a limiting factor in metrology. Here, Pfender et al. suppress this effect employing the nuclear spin of an NV centre for robust intermediate storage of classical NMR information, allowing then to record single-spin NMR spectra with 13 Hz resolution at room temperature.

  13. Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

    NASA Astrophysics Data System (ADS)

    Jayanti, Srikant

    Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG

  14. Inkjet-printing of non-volatile organic resistive devices and crossbar array structures

    NASA Astrophysics Data System (ADS)

    Sax, Stefan; Nau, Sebastian; Popovic, Karl; Bluemel, Alexander; Klug, Andreas; List-Kratochvil, Emil J. W.

    2015-09-01

    Due to the increasing demand for storage capacity in various electronic gadgets like mobile phones or tablets, new types of non-volatile memory devices have gained a lot of attention over the last few years. Especially multilevel conductance switching elements based on organic semiconductors are of great interest due to their relatively simple device architecture and their small feature size. Since organic semiconductors combine the electronic properties of inorganic materials with the mechanical characteristics of polymers, this class of materials is suitable for solution based large area device preparation techniques. Consequently, inkjet based deposition techniques are highly capable of facing preparation related challenges. By gradually replacing the evaporated electrodes with inkjet printed silver, the preparation related influence onto device performance parameters such as the ON/OFF ratio was investigated with IV measurements and high resolution transmission electron microscopy. Due to the electrode surface roughness the solvent load during the printing of the top electrode as well as organic layer inhomogeneity's the utilization in array applications is hampered. As a prototypical example a 1diode-1resistor element and a 2×2 subarray from 5×5 array matrix were fully characterized demonstrating the versatility of inkjet printing for device preparation.

  15. A Novel Non-Destructive Silicon-on-Insulator Nonvolatile Memory - LDRD 99-0750 Final Report

    SciTech Connect

    DRAPER,BRUCE L.; FLEETWOOD,D. M.; MEISENHEIMER,TIMOTHY L.; MURRAY,JAMES R.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; SMITH,PAUL M.; VANHEUSDEN,KAREL J.; WARREN,WILLIAM L.

    1999-11-01

    Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.

  16. Multilevel resistive switching nonvolatile memory based on MoS2 nanosheet-embedded graphene oxide

    NASA Astrophysics Data System (ADS)

    Shin, Gwang Hyuk; Kim, Choong-Ki; Bang, Gyeong Sook; Kim, Jong Yun; Jang, Byung Chul; Koo, Beom Jun; Woo, Myung Hun; Choi, Yang-Kyu; Choi, Sung-Yool

    2016-09-01

    An increasing demand for nonvolatile memory has driven extensive research on resistive switching memory because it uses simple structures with high density, fast switching speed, and low power consumption. To improve the storage density, the application of multilevel cells is among the most promising solutions, including three-dimensional cross-point array architectures. Two-dimensional nanomaterials have several advantages as resistive switching media, including flexibility, low cost, and simple fabrication processes. However, few reports exist on multilevel nonvolatile memory and its switching mechanism. We herein present a multilevel resistive switching memory based on graphene oxide (GO) and MoS2 fabricated by a simple spin-coating process. Metallic 1T-MoS2 nanosheets, chemically exfoliated by Li intercalation, were successfully embedded between two GO layers as charge-trapping sites. The resulting stacks of GO/MoS2/GO exhibited excellent nonvolatile memory performance with at least four resistance states, >102 endurance cycles, and >104 s retention time. Furthermore, the charge transport mechanism was systematically investigated through the analysis of low-frequency 1/f noise in various resistance states, which could be modulated by the input voltage bias in the negative differential resistance region. Accordingly, we propose a strategy to achieve multilevel nonvolatile memory in which the stacked layers of two-dimensional nanosheets are utilized as resistive and charge-storage materials.

  17. Nonvolatile Transistor Memory with Self-Assembled Semiconducting Polymer Nanodomain Floating Gates.

    PubMed

    Wang, Wei; Kim, Kang Lib; Cho, Suk Man; Lee, Ju Han; Park, Cheolmin

    2016-12-14

    Organic field effect transistor based nonvolatile memory (OFET-NVM) with semiconducting nanofloating gates offers additional benefits over OFET-NVMs with conventional metallic floating gates due to the facile controllability of charge storage based on the energetic structure of the floating gate. In particular, an all-in-one tunneling and floating-gate layer in which the semiconducting polymer nanodomains are self-assembled in the dielectric tunneling layer is promising. In this study, we utilize crystals of a p-type semiconducting polymer in which the crystalline lamellae of the polymer are spontaneously developed and embedded in the tunneling matrix as the nanofloating gate. The widths and lengths of the polymer nanodomains are approximately 20 nm and a few hundred nanometers, respectively. An OFET-NVM containing the crystalline nanofloating gates exhibits memory performance with a large memory window of 10 V, programming/erasing switching endurance for over 500 cycles, and a long retention time of 5000 s. Moreover, the device performance is improved by comixing with an n-type semiconductor; thus, the solution-processed p- and n-type double floating gates capable of storing both holes and electrons allow for the multilevel operation of our OFET-NVM. Four highly reliable levels (two bits per cell) of charge trapping and detrapping are achieved using this OFET-NVM by accurately choosing the programming/erasing voltages.

  18. The role of non-volatile memory from an application perspective

    SciTech Connect

    Kettering, Brett M; Nunez, James A

    2010-09-16

    Current, emerging, and future NVM (non-volatile memory) technologies give us hope that we will be able to architect HPC (high performance computing) systems that initially use them in a memory and storage hierarchy, and eventually use them as the memory and storage for the system, complete with ownership and protections as a HDD-based (hard-disk-drive-based) file system provides today.

  19. Peroxide induced volatile and non-volatile switching behavior in ZnO-based electrochemical metallization memory cell

    NASA Astrophysics Data System (ADS)

    Mangasa Simanjuntak, Firman; Chandrasekaran, Sridhar; Pattanayak, Bhaskar; Lin, Chun-Chieh; Tseng, Tseung-Yuen

    2017-09-01

    We explore the use of cubic-zinc peroxide (ZnO2) as a switching material for electrochemical metallization memory (ECM) cell. The ZnO2 was synthesized with a simple peroxide surface treatment. Devices made without surface treatment exhibits a high leakage current due to the self-doped nature of the hexagonal-ZnO material. Thus, its switching behavior can only be observed when a very high current compliance is employed. The synthetic ZnO2 layer provides a sufficient resistivity to the Cu/ZnO2/ZnO/ITO devices. The high resistivity of ZnO2 encourages the formation of a conducting bridge to activate the switching behavior at a lower operation current. Volatile and non-volatile switching behaviors with sufficient endurance and an adequate memory window are observed in the surface-treated devices. The room temperature retention of more than 104 s confirms the non-volatility behavior of the devices. In addition, our proposed device structure is able to work at a lower operation current among other reported ZnO-based ECM cells.

  20. A power-efficient and non-volatile programmable logic array based on phase change memory

    NASA Astrophysics Data System (ADS)

    Du, Yuan; Ye, Yong; Kang, Yong; Xia, Yangyang; Song, Zhitang; Chen, Bomy

    2016-10-01

    Recently, numerous efforts have been made on NVM-based Field Programmable Gate Arrays (FPGAs) because the emerging non-volatile memory (NVM) technologies have the advantages of lower leakage power and higher density than Static Random Access Memory (SRAM) technology. However, the cost and the scale of FPGAs are so high and large that they can't be applied in the consumer electronics field and Internet of Things (IoT). Due to the small scale and low cost, Programmable Logic Array (PLA) is an ideal option for these fields. However, up to now there are few researches on non-volatile PLA based on emerging NVMs. In this paper, a power-efficient non-volatile PLA based on Phase Change Memory (PCM) is proposed. The proposed non-volatile PLA architecture has been evaluated using the 40 nm Complementary Metal Oxide Semiconductor (CMOS) technology, and the simulation results show the correct functionality of the PLA. After the PLA reads the configuration bits from the non-volatile programmable elements (PEs), the power of the programmable elements can be OFF. Therefore, the standby power of the programmable elements is much smaller than that of the commonly SRAM-based PLAs. The simulation results also show that the total power of nvPLA is reduced by about 53.6% when the supply power of Programmable Element is OFF.

  1. A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

    NASA Astrophysics Data System (ADS)

    Jovanović, B.; Brum, R. M.; Torres, L.

    2014-04-01

    After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

  2. A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

    SciTech Connect

    Jovanović, B. E-mail: lionel.torres@lirmm.fr; Brum, R. M.; Torres, L.

    2014-04-07

    After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

  3. High-performance black phosphorus top-gate ferroelectric transistor for nonvolatile memory applications

    NASA Astrophysics Data System (ADS)

    Lee, Young Tack; Hwang, Do Kyung; Choi, Won Kook

    2016-10-01

    Two-dimensional (2D) van der Waals (vdW) atomic crystals have been extensively studied and significant progress has been made. The newest 2D vdW material, called black phosphorus (BP), has attracted considerable attention due to its unique physical properties, such as its being a singlecomponent material like graphene, and its having a high mobility and direct band gap. Here, we report on a high-performance BP nanosheet based ferroelectric field effect transistor (FeFET) with a poly(vinylidenefluoride-trifluoroethylene) top-gate insulator for a nonvolatile memory application. The BP FeFETs show the highest linear hole mobility of 563 cm2/Vs and a clear memory window of more than 15 V. For more advanced nonvolatile memory circuit applications, two different types of resistive-load and complementary ferroelectric memory inverters were implemented, which showed distinct memory on/off switching characteristics.

  4. Highly stable, extremely high-temperature, nonvolatile memory based on resistance switching in polycrystalline Pt nanogaps

    PubMed Central

    Suga, Hiroshi; Suzuki, Hiroya; Shinomura, Yuma; Kashiwabara, Shota; Tsukagoshi, Kazuhito; Shimizu, Tetsuo; Naitoh, Yasuhisa

    2016-01-01

    Highly stable, nonvolatile, high-temperature memory based on resistance switching was realized using a polycrystalline platinum (Pt) nanogap. The operating temperature of the memory can be drastically increased by the presence of a sharp-edged Pt crystal facet in the nanogap. A short distance between the facet edges maintains the nanogap shape at high temperature, and the sharp shape of the nanogap densifies the electric field to maintain a stable current flow due to field migration. Even at 873 K, which is a significantly higher temperature than feasible for conventional semiconductor memory, the nonvolatility of the proposed memory allows stable ON and OFF currents, with fluctuations of less than or equal to 10%, to be maintained for longer than eight hours. An advantage of this nanogap scheme for high-temperature memory is its secure operation achieved through the assembly and disassembly of a Pt needle in a high electric field. PMID:27725705

  5. Highly stable, extremely high-temperature, nonvolatile memory based on resistance switching in polycrystalline Pt nanogaps

    NASA Astrophysics Data System (ADS)

    Suga, Hiroshi; Suzuki, Hiroya; Shinomura, Yuma; Kashiwabara, Shota; Tsukagoshi, Kazuhito; Shimizu, Tetsuo; Naitoh, Yasuhisa

    2016-10-01

    Highly stable, nonvolatile, high-temperature memory based on resistance switching was realized using a polycrystalline platinum (Pt) nanogap. The operating temperature of the memory can be drastically increased by the presence of a sharp-edged Pt crystal facet in the nanogap. A short distance between the facet edges maintains the nanogap shape at high temperature, and the sharp shape of the nanogap densifies the electric field to maintain a stable current flow due to field migration. Even at 873 K, which is a significantly higher temperature than feasible for conventional semiconductor memory, the nonvolatility of the proposed memory allows stable ON and OFF currents, with fluctuations of less than or equal to 10%, to be maintained for longer than eight hours. An advantage of this nanogap scheme for high-temperature memory is its secure operation achieved through the assembly and disassembly of a Pt needle in a high electric field.

  6. A New Concept for Non-Volatile Memory: The Electric-Pulse Induced Resistive Change Effect in Colossal Magnetoresistive Thin Films

    NASA Technical Reports Server (NTRS)

    Liu, S. Q.; Wu, N. J.; Ignatiev, A.

    2001-01-01

    A novel electric pulse-induced resistive change (EPIR) effect has been found in thin film colossal magnetoresistive (CMR) materials, and has shown promise for the development of resistive, nonvolatile memory. The EPIR effect is induced by the application of low voltage (< 4 V) and short duration (< 20 ns) electrical pulses across a thin film sample of a CMR material at room temperature and under no applied magnetic field. The pulse can directly either increase or decrease the resistance of the thin film sample depending on pulse polarity. The sample resistance change has been shown to be over two orders of magnitude, and is nonvolatile after pulsing. The sample resistance can also be changed through multiple levels - as many as 50 have been shown. Such a device can provide a way for the development of a new kind of nonvolatile multiple-valued memory with high density, fast write/read speed, low power-consumption, and potential high radiation-hardness.

  7. A New Concept for Non-Volatile Memory: The Electric-Pulse Induced Resistive Change Effect in Colossal Magnetoresistive Thin Films

    NASA Technical Reports Server (NTRS)

    Liu, S. Q.; Wu, N. J.; Ignatiev, A.

    2001-01-01

    A novel electric pulse-induced resistive change (EPIR) effect has been found in thin film colossal magnetoresistive (CMR) materials, and has shown promise for the development of resistive, nonvolatile memory. The EPIR effect is induced by the application of low voltage (< 4 V) and short duration (< 20 ns) electrical pulses across a thin film sample of a CMR material at room temperature and under no applied magnetic field. The pulse can directly either increase or decrease the resistance of the thin film sample depending on pulse polarity. The sample resistance change has been shown to be over two orders of magnitude, and is nonvolatile after pulsing. The sample resistance can also be changed through multiple levels - as many as 50 have been shown. Such a device can provide a way for the development of a new kind of nonvolatile multiple-valued memory with high density, fast write/read speed, low power-consumption, and potential high radiation-hardness.

  8. Development and characterization of a ferroelectric non-volatile memory for flexible electronics

    NASA Astrophysics Data System (ADS)

    Mao, Duo

    Flexible electronics have received significant attention recently because of the potential applications in displays, sensors, radio frequency identification (RFID) tags and other integrated circuits. Electrically addressable non-volatile memory is a key component for these applications. The major challenges are to fabricate the memory at a low temperature compatible with plastic substrates while maintaining good device reliability, by being compatible with process as needed to integrate with other electronic components for system-on-chip applications. In this work, ferroelectric capacitors fabricated at low temperature were developed. Based on that, a ferroelectric random access memory (FRAM) for flexible electronics was developed and characterized. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] copolymer was used as a ferroelectric material and a photolithographic process was developed to fabricate ferroelectric capacitors. Different characterization methods including atomic force microscopy, x-ray diffraction and Fourier-transform infrared reflection-absorption spectroscopy were used to study the material properties of the P(VDF-TrFE) film. The material properties were correlated with the electrical characteristics of the ferroelectric capacitors. To understand the polarization switching behavior of the P(VDF-TrFE) ferroelectric capacitors, a Nucleation-Limited-Switching (NLS) model was used to study the switching kinetics. The switching kinetics were characterized over the temperature range from -60 °C to 100 °C. Fatigue characteristics were studied at different electrical stress voltages and frequencies to evaluate the reliability of the ferroelectric capacitor. The degradation mechanism is attributed to the increase of the activation field and the suppression of the switchable polarization. To develop a FRAM circuit for flexible electronics, an n-channel thin film transistor (TFT) based on CdS as the semiconductor was integrated with a P

  9. Voltage-tolerant circuit design for fully CMOS-compatible differential multiple-time programmable nonvolatile memories

    NASA Astrophysics Data System (ADS)

    Wu, Chia-You; Lin, Hongchin; Chiu, Hou-Jen

    2017-04-01

    In this paper, a fully CMOS-compatible differential multiple-time programmable (DFMTP) nonvolatile memory (NVM) circuit, fabricated by the standard TSMC 0.18 µm CMOS process without violating the design and electrical rules, is proposed. Novel voltage-tolerant circuits were designed using the standard 3.3 and 1.8 V devices for the bit line (BL) and control gate (CG) drivers for ‑3 and 6 V program/erase operations, as well as the negative voltage isolation circuits for sense amplifiers. The DFMTP array with these voltage-tolerant control circuits was used and measured to confirm the correct program/erase/read operations.

  10. Review of Emerging New Solid-State Non-Volatile Memories

    NASA Astrophysics Data System (ADS)

    Fujisaki, Yoshihisa

    2013-04-01

    The integration limit of flash memories is approaching, and many new types of memory to replace conventional flash memories have been proposed. Unlike flash memories, new nonvolatile memories do not require storage of electric charges. The possibility of phase-change random-access memories (PCRAMs) or resistive-change RAMs (ReRAMs) replacing ultrahigh-density NAND flash memories has been investigated; however, many issues remain to be overcome, making the replacement difficult. Nonetheless, ferroelectric RAMs (FeRAMs) and magnetoresistive RAMs (MRAMs) are gradually penetrating into fields where the shortcomings of flash memories, such as high operating voltage, slow rewriting speed, and limited number of rewrites, make their use inconvenient. For instance, FeRAMs are widely used in ICs that require low power consumption such as smart cards and wireless tags. MRAMs are used in many kinds of controllers in industrial equipment that require high speed and unlimited rewrite operations. For successful application of new non-volatile semiconductor memories, such memories must be practically utilized in new fields in which flash memories are not applicable, and their technologies must be further developed.

  11. Memory device using movement of protons

    DOEpatents

    Warren, W.L.; Vanheusden, K.J.R.; Fleetwood, D.M.; Devine, R.A.B.

    1998-11-03

    An electrically written memory element is disclosed utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element. 19 figs.

  12. Memory device using movement of protons

    DOEpatents

    Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.

    2000-01-01

    An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.

  13. Memory device using movement of protons

    DOEpatents

    Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.

    1998-01-01

    An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.

  14. Observation of AlO x material in electrical resistive switching for nonvolatile random access memory application

    NASA Astrophysics Data System (ADS)

    Jung, Kyun-Ho; Song, Seung-Gon; Park, Kyoung-Wan; Sok, Jung-Hyun; Kim, Kyong-Min; Park, Yun-Sun

    2017-03-01

    We fabricated an Al / AlO x / Al device by using a RF magnetron sputter system. The device showed a unipolar resistive switching process. In this study, the switching mechanism of the device followed the conductive filament model. The conduction mechanisms for the conductive filament model were explained by using Ohmic conduction for the low resistance state (LRS) and Schottky emission for the high resistance state (HRS). The average value of the resistance ratio between the HRS and the LRS was about 3.48 × 107 when the reading voltage (0.1 V) was achieved. The electrical property of the endurance was achieved under 50 switching cycles. A low switching voltage could be obtained for a low power consuming device. These results proved that the AlO x material has various possibilities for use in nonvolatile random access memory applications.

  15. Nonvolatile read/write memory element - A concept

    NASA Technical Reports Server (NTRS)

    Cricchi, J. R.; Lytle, W. J.

    1971-01-01

    Memory, with limited number of programming cycles, is achieved by using verticle, fusible links in series with oxide breakthrough elements. Memory elements are fabricated with integrated circuit technology and are ideal for low power digital computer application.

  16. Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

    PubMed

    Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

    2017-10-02

    The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

  17. Low-field Switching Four-state Nonvolatile Memory Based on Multiferroic Tunnel Junctions

    NASA Astrophysics Data System (ADS)

    Yau, H. M.; Yan, Z. B.; Chan, N. Y.; Au, K.; Wong, C. M.; Leung, C. W.; Zhang, F. Y.; Gao, X. S.; Dai, J. Y.

    2015-08-01

    Multiferroic tunneling junction based four-state non-volatile memories are very promising for future memory industry since this kind of memories hold the advantages of not only the higher density by scaling down memory cell but also the function of magnetically written and electrically reading. In this work, we demonstrate a success of this four-state memory in a material system of NiFe/BaTiO3/La0.7Sr0.3MnO3 with improved memory characteristics such as lower switching field and larger tunneling magnetoresistance (TMR). Ferroelectric switching induced resistive change memory with OFF/ON ratio of 16 and 0.3% TMR effect have been achieved in this multiferroic tunneling structure.

  18. Remarkable charge-trapping performance based in Zr0.5Hf0.5O2 with nanocrystal Ba0.6Sr0.4TiO3 blocking layer for nonvolatile memory device

    NASA Astrophysics Data System (ADS)

    Yan, X. B.; Jia, X. L.; Yang, T.; Zhao, J. H.; Li, Y. C.; Zhou, Z. Y.; Zhang, Y. Y.

    2016-10-01

    Two kinds of charge trapping memory device with Au/Zr0.5Hf0.5O2(ZHO)/SiO2/p-Si and Au/Ba0.6Sr0.4TiO3(BST)/Zr0.5Hf0.5O2/SiO2/p-Si structure were fabricated and investigated. The double BST/ZHO films exhibit a larger memory window of 7.36 V under ±14 V sweeping voltages in its C-V curve and the device has good charge retention properties with only small charge loss of ∼ 5% after more than 104 s. The good characteristics are attributed to the inter-diffusion between BST and ZHO where more deep defect sites were created after RTA treatment, which provides high potential barriers for the trapped charges to tunnel back to the silicon substrate. Furthermore, the nanocrystal in the BST layer increases the tunneling barrier of tunneling current into the gate and effectively restrains the leakage of storage charge from blocking layer, which improves the charge retention characteristic.

  19. Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

    SciTech Connect

    Han, Jinhua; Wang, Wei Ying, Jun; Xie, Wenfa

    2014-01-06

    An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

  20. Non-volatile, high density, high speed, Micromagnet-Hall effect Random Access Memory (MHRAM)

    NASA Technical Reports Server (NTRS)

    Wu, Jiin C.; Katti, Romney R.; Stadler, Henry L.

    1991-01-01

    The micromagnetic Hall effect random access memory (MHRAM) has the potential of replacing ROMs, EPROMs, EEPROMs, and SRAMs because of its ability to achieve non-volatility, radiation hardness, high density, and fast access times, simultaneously. Information is stored magnetically in small magnetic elements (micromagnets), allowing unlimited data retention time, unlimited numbers of rewrite cycles, and inherent radiation hardness and SEU immunity, making the MHRAM suitable for ground based as well as spaceflight applications. The MHRAM device design is not affected by areal property fluctuations in the micromagnet, so high operating margins and high yield can be achieved in large scale integrated circuit (IC) fabrication. The MHRAM has short access times (less than 100 nsec). Write access time is short because on-chip transistors are used to gate current quickly, and magnetization reversal in the micromagnet can occur in a matter of a few nanoseconds. Read access time is short because the high electron mobility sensor (InAs or InSb) produces a large signal voltage in response to the fringing magnetic field from the micromagnet. High storage density is achieved since a unit cell consists only of two transistors and one micromagnet Hall effect element. By comparison, a DRAM unit cell has one transistor and one capacitor, and a SRAM unit cell has six transistors.

  1. Four-state non-volatile memory in a multiferroic spin filter tunnel junction

    NASA Astrophysics Data System (ADS)

    Ruan, Jieji; Li, Chen; Yuan, Zhoushen; Wang, Peng; Li, Aidong; Wu, Di

    2016-12-01

    We report a spin filter type multiferroic tunnel junction with a ferromagnetic/ferroelectric bilayer barrier. Memory functions of a spin filter magnetic tunnel junction and a ferroelectric tunnel junction are combined in this single device, producing four non-volatile resistive states that can be read out in a non-destructive manner. This concept is demonstrated in a LaNiO3/Pr0.8Ca0.2MnO3/BaTiO3/La0.7Sr0.3MnO3 all-oxide tunnel junction. The ferromagnetic insulator Pr0.8Ca0.2MnO3 serves as the spin filter and the ferromagnetic metal La0.7Sr0.3MnO3 is the spin analyzer. The ferroelectric polarization reversal in the BaTiO3 barrier switches the tunneling barrier height to produce a tunneling electroresistance. The ferroelectric switching also modulates the spin polarization and the spin filtering efficiency in Pr0.8Ca0.2MnO3.

  2. Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

    NASA Astrophysics Data System (ADS)

    Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui

    2016-07-01

    Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

  3. Non-volatile memory elements based on the intercalation of organic molecules inside carbon nanotubes

    SciTech Connect

    Meunier, Vincent; Kalinin, Sergei V; Sumpter, Bobby G

    2007-01-01

    We propose a novel class of non-volatile memory elements based on the modification of the transport properties of a conducting carbon nanotube by the presence of a guest molecule having multiple stable orientational states relative to the nanotube that correspond to conducting and non-conducting states. The mechanism, governed by a local gating effect of the molecule on the electronic properties of the nanotube host, is studied using density functional theory. The mechanisms of reversible reading and writing of information are illustrated with a F4 TCNQ molecule encap-sulated inside a metallic carbon nanotube. Our results suggest that this new type of non-volatile memory element is robust, fatigue-free, and can operate at room temperature.

  4. High-G testing of MEMS mechanical non-volatile memory and silicon re-entry switch.

    SciTech Connect

    Baker, Michael Sean; Pohl, Kenneth Roy

    2005-10-01

    Two different Sandia MEMS devices have been tested in a high-g environment to determine their performance and survivability. The first test was performed using a drop-table to produce a peak acceleration load of 1792 g's over a period of 1.5 ms. For the second test the MEMS devices were assembled in a gun-fired penetrator and shot into a cement target at the Army Waterways Experiment Station in Vicksburg Mississippi. This test resulted in a peak acceleration of 7191 g's for a duration of 5.5 ms. The MEMS devices were instrumented using the MEMS Diagnostic Extraction System (MDES), which is capable of driving the devices and recording the device output data during the high-g event, providing in-flight data to assess the device performance. A total of six devices were monitored during the experiments, four mechanical non-volatile memory devices (MNVM) and two Silicon Reentry Switches (SiRES). All six devices functioned properly before, during, and after each high-g test without a single failure. This is the first known test under flight conditions of an active, powered MEMS device at Sandia.

  5. A Radiation-Tolerant, Low-Power Non-Volatile Memory Based on Silicon Nanocrystal Quantum Dots

    NASA Technical Reports Server (NTRS)

    Bell, L. D.; Boer, E. A.; Ostraat, M. L.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; deBlauwe, J.; Green, M. L.

    2001-01-01

    Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO2 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled in program/erase threshold voltage swing was seen during 100,000 program and erase cycles. Additional near-term goals for this project include extensive testing for radiation hardness and the development of artificial layered tunnel barrier heterostructures which have the potential for large speed enhancements for read/write of nanocrystal memory elements, compared with conventional flash devices. Additional information is contained in the original extended abstract.

  6. A Radiation-Tolerant, Low-Power Non-Volatile Memory Based on Silicon Nanocrystal Quantum Dots

    NASA Technical Reports Server (NTRS)

    Bell, L. D.; Boer, E. A.; Ostraat, M. L.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; deBlauwe, J.; Green, M. L.

    2001-01-01

    Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO2 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled in program/erase threshold voltage swing was seen during 100,000 program and erase cycles. Additional near-term goals for this project include extensive testing for radiation hardness and the development of artificial layered tunnel barrier heterostructures which have the potential for large speed enhancements for read/write of nanocrystal memory elements, compared with conventional flash devices. Additional information is contained in the original extended abstract.

  7. Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

    SciTech Connect

    Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin E-mail: chilf@suda.edu.cn Chi, Li-Feng E-mail: chilf@suda.edu.cn Wang, Sui-Dong E-mail: chilf@suda.edu.cn

    2015-03-23

    Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

  8. Reconfigurable Electronics and Non-Volatile Memory Research

    DTIC Science & Technology

    2015-11-10

    102. Micron inline testing data for the pillar cell structure devices .................................. 77  Figure 103. Wafer maps showing resistance...for each wafer of pillar structure devices .............. 78 viii Approved for public release; distribution is unlimited. LIST OF TABLES Table Page...the 300 mm wafer pillar cell structure data ................................ 78 ix Approved for public release; distribution is unlimited

  9. Non-volatile main memory management methods based on a file system.

    PubMed

    Oikawa, Shuichi

    2014-01-01

    There are upcoming non-volatile (NV) memory technologies that provide byte addressability and high performance. PCM, MRAM, and STT-RAM are such examples. Such NV memory can be used as storage because of its data persistency without power supply while it can be used as main memory because of its high performance that matches up with DRAM. There are a number of researches that investigated its uses for main memory and storage. They were, however, conducted independently. This paper presents the methods that enables the integration of the main memory and file system management for NV memory. Such integration makes NV memory simultaneously utilized as both main memory and storage. The presented methods use a file system as their basis for the NV memory management. We implemented the proposed methods in the Linux kernel, and performed the evaluation on the QEMU system emulator. The evaluation results show that 1) the proposed methods can perform comparably to the existing DRAM memory allocator and significantly better than the page swapping, 2) their performance is affected by the internal data structures of a file system, and 3) the data structures appropriate for traditional hard disk drives do not always work effectively for byte addressable NV memory. We also performed the evaluation of the effects caused by the longer access latency of NV memory by cycle-accurate full-system simulation. The results show that the effect on page allocation cost is limited if the increase of latency is moderate.

  10. Memory device using movement of protons

    DOEpatents

    Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.; Archer, Leo B.; Brown, George A.; Wallace, Robert M.

    2000-01-01

    An enhancement of an electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure during an anneal in an atmosphere containing hydrogen gas. Device operation is enhanced by concluding this anneal step with a sudden cooling. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronics elements on the same silicon substrate.

  11. Extraction of the gate capacitance coupling coefficient in floating gate non-volatile memories: Statistical study of the effect of mismatching between floating gate memory and reference transistor in dummy cell extraction methods

    NASA Astrophysics Data System (ADS)

    Rafhay, Quentin; Beug, M. Florian; Duane, Russell

    2007-04-01

    This paper presents an experimental comparison of dummy cell extraction methods of the gate capacitance coupling coefficient for floating gate non-volatile memory structures from different geometries and technologies. These results show the significant influence of mismatching floating gate devices and reference transistors on the extraction of the gate capacitance coupling coefficient. In addition, it demonstrates the accuracy of the new bulk bias dummy cell extraction method and the importance of the β function, introduced recently in [Duane R, Beug F, Mathewson A. Novel capacitance coupling coefficient measurement methodology for floating gate non-volatile memory devices. IEEE Electr Dev Lett 2005;26(7):507-9], to determine matching pairs of floating gate memory and reference transistor.

  12. Multifunctional organic phototransistor-based nonvolatile memory achieved by UV/ozone treatment of the Ta₂O₅ gate dielectric.

    PubMed

    Liu, Xiaohui; Zhao, Haoyan; Dong, Guifang; Duan, Lian; Li, Dong; Wang, Liduo; Qiu, Yong

    2014-06-11

    An organic phototransistor (OPT) shows nonvolatile memory effect due to its novel optical writing and electrical erasing processes. In this work, we utilize an organic light-emitting diode (OLED) as the light source to investigate OPT-based memory (OPTM) performance. It is found that the OPTM can be used as either flash memory or write-once read-many-times memory by adjusting the properties of the Ta2O5 gate dielectric layer. UV/ozone treatment is applied to effectively change dielectric properties of the Ta2O5 film. The mechanisms for this are examined by X-ray photoelectron spectroscopy and capacitance-voltage measurement. It turns out that the densities of oxygen vacancies and defects in the first 1.8 nm Ta2O5 films near the Ta2O5/semiconductor interface are reduced. Furthermore, for the first time, we use this multifunctional OPTM, which unites the photosensitive and memory properties in one single device, as an optical feedback system to tune the brightness of the OLED. Our study suggests that these OPTMs have potential applications in tuning the brightness uniformity, improving the display quality and prolonging the lifetime of flat panel displays.

  13. Magnetically induced nonvolatile magnetoresistance and resistance memory effect in phase-separated manganite thin films

    NASA Astrophysics Data System (ADS)

    Li, Qian; Cao, Qingqi; Wang, Dunhui; Du, Youwei

    2017-03-01

    We report the observation of magnetically induced resistance memory effect in a typical electronic phase-separated manganite La5/8‑x Pr x Ca3/8MnO3 (x  =  0.3) thin film. In the hysteresis region of metal-to-insulator transition, the resistance exhibits a sharp drop with the application of magnetic field and maintains the low resistance state after the removal of field, showing a nonvolatile magnetoresistance effect. The high resistance state can be recovered until the temperature is warmed. More explicit measurements at the hysteresis region exhibit the non-volatility and irreversibility of magnetoresistance, which can be ascribed to the percolative feature in the electronic phase-separated manganite. The origin and potential applications of these interesting effects are discussed.

  14. Investigation of p-channel and n-channel junctionless gate-all-around polycrystalline silicon nanowires with silicon nanocrystals nonvolatile memory

    NASA Astrophysics Data System (ADS)

    Yeh, Mu-Shih; Wu, Yung-Chun; Chung, Ming-Hsien; Jhan, Yi-Ruei; Chang-Liao, Kuei-Shu; Liu, Kuan-Cheng; Wu, Min-Hsin; Hung, Min-Feng

    2014-07-01

    This work presents p-channel and n-channel junctionless (JL) polycrystalline silicon (poly-Si) nanowires gate-all-around (GAA) nonvolatile memory (NVM) devices with silicon nanocrystals charge trapping layer. Experimental results indicate that the n-channel device has better programming efficiency and p-channel device has better erasing efficiency. For p-channel device, an extrapolation of the memory window to 10 yr demonstrates that 95% of the stored charge can be retained at high temperature of 85 °C. Such the p-channel and n-channel JL-GAA NVMs are feasible for use in system-on-panel (SOP) and 3-D stacked flash memory applications.

  15. Enhanced Giant Piezoresistance Performance of Sandwiched ZnS/Si/SiO2 Radial Heterostructure Nanotubes for Nonvolatile Stress Memory with Repeatable Writing and Erasing.

    PubMed

    Cheng, Baochang; Xiong, Li; Cai, Qiangsheng; Shi, Haiping; Zhao, Jie; Su, Xiaohui; Xiao, Yanhe; Lei, Shuijin

    2016-12-21

    It is a challenge to realize nonvolatile stress-writing memory. Herein, we propose a strategy to construct rewritable stress information storage devices, consisting of deliberately designing individual sandwiched ZnS/Si/SiO2 radial heterostructure nanotubes synthesized by one-step thermal evaporation method. A bulk trap-related Poole-Frenkel hopping mechanism is proposed. Carriers are localized in a narrow bandgap Si intermediate layer; moreover, incorporated impurities and heterointerface defects can serve as charge trap centers or storage mediators. Compressive strain can induce trap barrier height to decrease at relatively low operation bias voltage, whereas tensile strain can induce it to increase, resulting in a giant piezoresistance effect. After both loading compressive and tensile strains at low bias voltage, additionally, the emptying of trap states results in a high resistance state. However, the emptied trap states can be filled by applying a relatively high bias voltage without strains and, correspondingly, the memories return to low resistance state. The emptying and filling of trap states, respectively applied by strains and high electric field, result in a repeatable writing/erasing nonvolatile memory effect. The results indicate that the creation and modification of trap states in multiscale nanostructures can give an avenue to the development of novel nanodevices for rewritable nonvolatile stress sensor and memory.

  16. Effect of electrode material on characteristics of non-volatile resistive memory consisting of Ag2S nanoparticles

    NASA Astrophysics Data System (ADS)

    Jang, Jaewon

    2016-07-01

    In this study, Ag2S nanoparticles are synthesized and used as the active material for two-terminal resistance switching memory devices. Sintered Ag2S films are successfully crystallized on plastic substrates with synthesized Ag2S nanoparticles, after a relatively low-temperature sintering process (200 °C). After the sintering process, the crystallite size is increased from 6.8 nm to 80.3 nm. The high ratio of surface atoms to inner atoms of nanoparticles reduces the melting point temperature, deciding the sintering process temperature. In order to investigate the resistance switching characteristics, metal/Ag2S/metal structures are fabricated and tested. The effect of the electrode material on the non-volatile resistive memory characteristics is studied. The bottom electrochemically inert materials, such as Au and Pt, were critical for maintaining stable memory characteristics. By using Au and Pt inert bottom electrodes, we are able to significantly improve the memory endurance and retention to more than 103 cycles and 104 sec, respectively.

  17. Effect of electrode material on characteristics of non-volatile resistive memory consisting of Ag{sub 2}S nanoparticles

    SciTech Connect

    Jang, Jaewon

    2016-07-15

    In this study, Ag{sub 2}S nanoparticles are synthesized and used as the active material for two-terminal resistance switching memory devices. Sintered Ag{sub 2}S films are successfully crystallized on plastic substrates with synthesized Ag{sub 2}S nanoparticles, after a relatively low-temperature sintering process (200 °C). After the sintering process, the crystallite size is increased from 6.8 nm to 80.3 nm. The high ratio of surface atoms to inner atoms of nanoparticles reduces the melting point temperature, deciding the sintering process temperature. In order to investigate the resistance switching characteristics, metal/Ag{sub 2}S/metal structures are fabricated and tested. The effect of the electrode material on the non-volatile resistive memory characteristics is studied. The bottom electrochemically inert materials, such as Au and Pt, were critical for maintaining stable memory characteristics. By using Au and Pt inert bottom electrodes, we are able to significantly improve the memory endurance and retention to more than 10{sup 3} cycles and 10{sup 4} sec, respectively.

  18. Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2012

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Allen, Gregory R.

    2012-01-01

    The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.

  19. Nonvolatile floating-gate memories using Zr and ZrO2 nanodots.

    PubMed

    Hong, Seung Hui; Kim, Min Choul; Oh, Hyoung Taek; Choi, Suk-Ho; Kim, Kyung Joong

    2011-01-01

    Triple-layer structures of SiO2/Zr nanodots (NDs)/SiO2 for nonvolatile memories have been firstly fabricated at room temperature by using ion beam sputtering deposition (IBSD). High-resolution transmission electron microscopy and X-ray photoelectron spectroscopy demonstrate that Zr NDs self-assembled between the SiO2 layers by IBSD are changed into ZrO2 NDs by annealing. The memory window that is estimated by capacitance-voltage curves increases up to a maximum value of 5.8 V with increasing Zr amount up to 6 monolayers for the annealed samples. The memory window and the charge-loss rate at the programmed state are smaller before annealing, which is explained with reference to double oxide barriers of SiO2 and ZrO2.

  20. Epitaxial integration of tetragonal BiFeO3 with silicon for nonvolatile memory applications

    NASA Astrophysics Data System (ADS)

    Zhu, Jingbin; Yin, Zhigang; Fu, Zhen; Zhao, Yajuan; Zhang, Xingwang; Liu, Xin; You, Jingbi; Li, Xingxing; Meng, Junhua; Liu, Heng; Wu, Jinliang

    2017-02-01

    Ferroelectric field-effect transistor has long been considered as a promising nonvolatile memory technology, but its application is limited by the poor scalability. Here we show that this problem can be solved by epitaxially integrating tetragonal BiFeO3, a stress-induced metastable phase which exhibits remarkably low dielectric permittivity and high coercive field, on the silicon platform. Tetragonal BiFeO3 was stabilized on (001)-oriented silicon by using Bi2SiO5, which is chemically and structurally compatible with both silicon and tetragonal BiFeO3, as the buffer layer. Unlike the commonly observed MC structure, the obtained BiFeO3 layer exhibits a true tetragonal symmetry. An unprecedented high memory window of 6.5 V was observed for the Au/BiFeO3/Bi2SiO5/Si capacitor with BiFeO3 thickness of 135 nm. The epitaxial integration of tetragonal BiFeO3 with silicon may pave a possible avenue for nanosized, power-efficient ferroelectric nonvolatile memories.

  1. TOPICAL REVIEW Nanoscale memory devices

    NASA Astrophysics Data System (ADS)

    Chung, Andy; Deen, Jamal; Lee, Jeong-Soo; Meyyappan, M.

    2010-10-01

    This article reviews the current status and future prospects for the use of nanomaterials and devices in memory technology. First, the status and continuing scaling trends of the flash memory are discussed. Then, a detailed discussion on technologies trying to replace flash in the near-term is provided. This includes phase change random access memory, Fe random access memory and magnetic random access memory. The long-term nanotechnology prospects for memory devices include carbon-nanotube-based memory, molecular electronics and memristors based on resistive materials such as TiO2.

  2. Characteristics of a Nonvolatile SRAM Memory Cell Utilizing a Ferroelectric Transistor

    NASA Technical Reports Server (NTRS)

    Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

    2011-01-01

    The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.

  3. Electronic Structure and Charge-Trapping Characteristics of the Al2O3-TiAlO-SiO2 Gate Stack for Nonvolatile Memory Applications

    NASA Astrophysics Data System (ADS)

    Xu, Wenchao; Zhang, Yang; Tang, Zhenjie; Shao, Zhengjie; Zhou, Guofu; Qin, Minghui; Zeng, Min; Wu, Sujuan; Zhang, Zhang; Gao, Jinwei; Lu, Xubing; Liu, Junming

    2017-04-01

    In this work, high- k composite TiAlO film has been investigated as charge-trapping material for nonvolatile memory applications. The annealing formed Al2O3-TiAlO-SiO2 dielectric stack demonstrates significant memory effects and excellent reliability properties. The memory device exhibits a large memory window of 2.6 V under ±8 V sweeping voltage, and it shows only 14% charge loss after more than 10 years' retention, indicating excellent charge retention properties. The electronic structures of the Al2O3-TiAlO-SiO2 have been studied by X-ray photoelectron spectroscopy measurements, and it reveals that the quantum well and the defect traps in TiAlO film can provide a >1.8 eV deep barrier for charge confinement in the TiAlO layer. The mixing between Al2O3 and TiO2 can increase the defects related to the under-coordinated Ti3+ atoms, thereby enhancing the charge-trapping efficiency of the device. Our work implies that high- k TiAlO composite film is promising for applications in future nonvolatile charge-trapping memories.

  4. Electrical Bistabilities and Conduction Mechanisms of Nonvolatile Memories Based on a Polymethylsilsesquioxane Insulating Layer Containing CdSe/ZnS Quantum Dots

    NASA Astrophysics Data System (ADS)

    Ma, Zehao; Ooi, Poh Choon; Li, Fushan; Yun, Dong Yeol; Kim, Tae Whan

    2015-10-01

    Nonvolatile memory (NVM) devices based on a metal-insulator-metal structure consisting of CdSe/ZnS quantum dots embedded in polymethylsilsesquioxane dielectric layers were fabricated. The current-voltage ( I- V) curves showed a bistable current behavior and the presence of hysteresis. The current-time ( I- t) curves showed that the fabricated NVM memory devices were stable up to 1 × 104 s with a distinct ON/OFF ratio of 104 and were reprogrammable when the endurance test was performed. The extrapolation of the I- t curve to 105 s with corresponding current ON/OFF ratio 1 × 105 indicated a long performance stability of the NVM devices. Schottky emission, Poole-Frenkel emission, trapped-charge limited-current and Child-Langmuir law were proposed as the dominant conduction mechanisms for the fabricated NVM devices based on the obtained I- V characteristics.

  5. Programming a nonvolatile memory-like sensor for KRAS gene sensing and signal enhancement.

    PubMed

    Lin, Yi-Ting; Purwidyantri, Agnes; Luo, Ji-Dung; Chiou, Chiuan-Chian; Yang, Chia-Ming; Lo, Chih-Hong; Hwang, Tsann-Long; Yen, Tzung-Hai; Lai, Chao-Sung

    2016-05-15

    A programmable field effect-based electrolyte-insulator-semiconductor (EIS) sensor constructed with a nonvolatile memory-like structure is proposed for KRAS gene DNA hybridization detection. This programmable EIS structure was fabricated with silicon oxide (SiO2)/silicon nitride (Si3N4)/silicon oxide on a p-type silicon wafer, namely electrolyte-oxide-nitride-oxide-Si (EONOS). In this research, voltage stress programming from 4 to 20V was applied to trigger holes confinement in the nitride-trapping layer that, consequently, enhances the DNA attachment onto the sensing surface due to additional electrostatic interaction. Not solely resulting from the higher DNA load, the programming may affect the orientation of the DNA that finally contributes to the change in capacitance. Findings have shown that a higher voltage program is able to increase the total capacitance and results in ~3.5- and ~5.5-times higher sensitivities for a series of concentrations for complementary DNA and wild type versus mutant DNA hybridization detection, respectively. Overall, it has been proven that the voltage program on the nonvolatile memory-like structure of EONOS is a notable candidate for genosensor development, scoping the diagnosis of a single nucleotide polymorphism (SNP)-related disease.

  6. Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

    SciTech Connect

    Wang, Wei Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa

    2014-09-22

    Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm{sup 2}/V s. The unidirectional shift of turn-on voltage (V{sub on}) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V{sub P}/V{sub E}) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm{sup 2}/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V{sub P}/V{sub E} of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V{sub on} shift. As a result, an enlarged memory window of 28.6 V at the V{sub P}/V{sub E} of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

  7. Unipolar resistive switching characteristics and scaling behaviors in La2Mo2O9 thin films for nonvolatile memory applications

    NASA Astrophysics Data System (ADS)

    Hu, L.; Lin, G. T.; Luo, X.; Wei, R. H.; Zhu, X. B.; Song, W. H.; Dai, J. M.; Sun, Y. P.

    2016-12-01

    La2Mo2O9 (LMO) thin films have been deposited on Pt/Ti/SiO2/Si substrates by pulsed laser deposition and the resistive switching (RS) characteristics of the Au/LMO/Pt devices has been investigated. The Au/LMO/Pt devices show excellent unipolar RS characteristics with high resistance ratio between high resistance state and low resistance state (LRS), good endurance, and retention performances. The results of temperature dependence of resistance and x-ray photoelectron spectroscopy suggest that the observed RS characteristics can be explained by the formation and rupture of conducting filaments composed of oxygen vacancies. Furthermore, the plot of the reset current (IR) as a function of the third harmonic coefficient (B0) caused by Joule heating during the reset process shows scaling behavior with a power law of I R ∝ B0 - δ . The IR and reset power (PR) can also be scaled to the resistance in LRS (R0), i.e., I R ( P R ) ∝ R0 - α ( β ) . The observed scaling behaviors indicate the importance of the Joule heating for the RS characteristics of Au/LMO/Pt devices. These results demonstrate the potential application of LMO thin film in a nonvolatile memory device.

  8. Reversible insulator-metal transition of LaAlO3/SrTiO3 interface for nonvolatile memory

    PubMed Central

    Lu, Hong-Liang; Liao, Zhi-Min; Zhang, Liang; Yuan, Wen-Tao; Wang, Yong; Ma, Xiu-Mei; Yu, Da-Peng

    2013-01-01

    We report a new type of memory device based on insulating LaAlO3/SrTiO3 (LAO/STO) hetero-interface. The microstructures of the LAO/STO interface are characterized by Cs-corrected scanning transmission electron microscopy, which reveals the element intermixing at the interface. The inhomogeneous element distribution may result in carrier localization, which is responsible for the insulating state. The insulating state of such interface can be converted to metallic state by light illumination and the metallic state maintains after light off due to giant persistent photoconductivity (PPC) effect. The on/off ratio between the PPC and the initial dark conductance is as large as 105. The metallic state also can be converted back to insulating state by applying gate voltage. Reversible and reproducible resistive switching makes LAO/STO interface promising as a nonvolatile memory. Our results deepen the understanding of PPC phenomenon in LAO/STO, and pave the way for the development of all-oxide electronics integrating information storage devices. PMID:24100438

  9. High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

    SciTech Connect

    Nedic, Stanko; Welland, Mark E-mail: mew10@cam.ac.uk; Tea Chun, Young; Chu, Daping E-mail: mew10@cam.ac.uk; Hong, Woong-Ki

    2014-01-20

    A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ∼16.5 V, a high drain current on/off ratio of ∼10{sup 5}, a gate leakage current below ∼300 pA, and excellent retention characteristics for over 10{sup 4} s.

  10. Iii-V Compound Semiconductor Integrated Charge Storage Structures for Dynamic and Non-Volatile Memory Elements

    NASA Astrophysics Data System (ADS)

    Hetherington, Dale Laird

    This thesis presents an investigation into a novel group of GaAs charge storage devices. These devices, which are an integration of bipolar and junction field effect transistor structures were conceived, designed, fabricated, and tested within this study. The purpose was to analyse new types of charge storage devices, which are suitable for fabrication and lead to the development of dynamic and nonvolatile memories in III-V compound semiconductors. Currently, III-V semiconductor storage devices consist only of capacitors, where data is destroyed during reading and electrical erasure is difficult. In this work, four devices types were demonstrated that exhibit nondestructive reading, and three of the prototypes can be electrically erased. All types use the junction field effect transistor (JFET) for charge sensing, with each having different bipolar or epitaxial layer structure controlling the junction gate. The bottom epitaxial layer in each case served as the JFET channel. Two of the device types have three alternately doped layers, while the remaining two have four alternately doped layers. In all cases, removal of majority carriers from the middle layers constitutes stored charge. The missing carriers deplete the current carrying a region of the JFET channel. Drain current of the JFET becomes an indicator of stored charge. The basic function of each JFET memory element type is independent of interchanging n- and p- type doping within the structure type. Some performance advantage can be realized, however, by sensing with an n-type channel as compared to p- type due to increased carrier mobility. All device types exhibit storage time characteristics of order ten seconds. Devices are constructed in epitaxial layers grown by molecular beam epitaxy (MBE) reactors. The design of the epitaxial layers is an intrinsic part, together with the electrical design, of the storage device concept. These concepts are implemented first with photolithography masks which are used

  11. Graphene–ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

    PubMed Central

    Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

    2016-01-01

    Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer. PMID:26813710

  12. Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations.

    PubMed

    Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

    2016-01-27

    Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

  13. Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

    NASA Astrophysics Data System (ADS)

    Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

    2016-01-01

    Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

  14. Nonvolatile Multilevel Memory and Boolean Logic Gates Based on a Single Ni /[Pb (Mg1 /3Nb2 /3)O3]0.7[PbTiO3]0.3/Ni Heterostructure

    NASA Astrophysics Data System (ADS)

    Shen, Jianxin; Shang, Dashan; Chai, Yisheng; Wang, Yue; Cong, Junzhuang; Shen, Shipeng; Yan, Liqin; Wang, Wenhong; Sun, Young

    2016-12-01

    Memtranstor that correlates charge and magnetic flux via nonlinear magnetoelectric effects has a great potential in developing next-generation nonvolatile devices. In addition to multilevel nonvolatile memory, we demonstrate here that nonvolatile logic gates such as nor and nand can be implemented in a single memtranstor made of the Ni /PMN -PT /Ni heterostructure. After applying two sequent voltage pulses (X1 , X2 ) as the logic inputs on the memtranstor, the output magnetoelectric voltage can be positive high (logic 1), positive low (logic 0), or negative (logic 0), depending on the levels of X1 and X2 . The underlying physical mechanism is related to the complete or partial reversal of ferroelectric polarization controlled by inputting selective voltage pulses, which determines the magnitude and sign of the magnetoelectric voltage coefficient. The combined functions of both memory and logic could enable the memtranstor as a promising candidate for future computing systems beyond von Neumann architecture.

  15. Capacitance-voltage measurement in memory devices using ferroelectric polymer

    NASA Astrophysics Data System (ADS)

    Nguyen, Chien A.; Lee, Pooi See

    2006-01-01

    Application of thin polymer film as storing mean for non-volatile memory devices is investigated. Capacitance-voltage (C-V) measurement of metal-ferroelectric-metal device using ferroelectric copolymer P(VDF-TrFE) as dielectric layer shows stable 'butter-fly' curve. The two peaks in C-V measurement corresponding to the largest capacitance are coincidental at the coercive voltages that give rise to zero polarization in the polarization hysteresis measurement. By comparing data of C-V and P-E measurement, a correlation between two types of hysteresis is established in which it reveals simultaneous electrical processes occurring inside the device. These processes are caused by the response of irreversible and reversible polarization to the applied electric field that can be used to present a memory window. The memory effect of ferroelectric copolymer is further demonstrated for fabricating polymeric non-volatile memory devices using metal-ferroelectric-insulator-semiconductor structure (MFIS). By applying different sweeping voltages at the gate, bidirectional flat-band voltage shift is observed in the ferroelectric capacitor. The asymmetrical shift after negative sweeping is resulted from charge accumulation at the surface of Si substrate caused by the dipole direction in the polymer layer. The effect is reversed for positive voltage sweeping.

  16. Ferroelectricity in Covalently functionalized Two-dimensional Materials: Integration of High-mobility Semiconductors and Nonvolatile Memory.

    PubMed

    Wu, Menghao; Dong, Shuai; Yao, Kailun; Liu, Junming; Zeng, Xiao Cheng

    2016-11-09

    Realization of ferroelectric semiconductors by conjoining ferroelectricity with semiconductors remains a challenging task because most present-day ferroelectric materials are unsuitable for such a combination due to their wide bandgaps. Herein, we show first-principles evidence toward the realization of a new class of two-dimensional (2D) ferroelectric semiconductors through covalent functionalization of many prevailing 2D materials. Members in this new class of 2D ferroelectric semiconductors include covalently functionalized germanene, and stanene (Nat. Commun. 2014, 5, 3389), as well as MoS2 monolayer (Nat. Chem. 2015, 7, 45), covalent functionalization of the surface of bulk semiconductors such as silicon (111) (J. Phys. Chem. B 2006, 110 , 23898), and the substrates of oxides such as silica with self-assembly monolayers (Nano Lett. 2014, 14, 1354). The newly predicted 2D ferroelectric semiconductors possess high mobility, modest bandgaps, and distinct ferroelectricity that can be exploited for developing various heterostructural devices with desired functionalities. For example, we propose applications of the 2D materials as 2D ferroelectric field-effect transistors with ultrahigh on/off ratio, topological transistors with Dirac Fermions switchable between holes and electrons, ferroelectric junctions with ultrahigh electro-resistance, and multiferroic junctions for controlling spin by electric fields. All these heterostructural devices take advantage of the combination of high-mobility semiconductors with fast writing and nondestructive reading capability of nonvolatile memory, thereby holding great potential for the development of future multifunctional devices.

  17. Controlled fabrication of Si nanocrystal delta-layers in thin SiO{sub 2} layers by plasma immersion ion implantation for nonvolatile memories

    SciTech Connect

    Bonafos, C.; Ben-Assayag, G.; Groenen, J.; Carrada, M.; Spiegel, Y.; Torregrosa, F.; Normand, P.; Dimitrakis, P.; Kapetanakis, E.; Sahu, B. S.; Slaoui, A.

    2013-12-16

    Plasma Immersion Ion Implantation (PIII) is a promising alternative to beam line implantation to produce a single layer of nanocrystals (NCs) in the gate insulator of metal-oxide semiconductor devices. We report herein the fabrication of two-dimensional Si-NCs arrays in thin SiO{sub 2} films using PIII and rapid thermal annealing. The effect of plasma and implantation conditions on the structural properties of the NC layers is examined by transmission electron microscopy. A fine tuning of the NCs characteristics is possible by optimizing the oxide thickness, implantation energy, and dose. Electrical characterization revealed that the PIII-produced-Si NC structures are appealing for nonvolatile memories.

  18. Forced Ion Migration for Chalcogenide Phase Change Memory Device

    NASA Technical Reports Server (NTRS)

    Campbell, Kristy A (Inventor)

    2013-01-01

    Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge2Se3/SnTe, and Ge2Se3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

  19. Forced ion migration for chalcogenide phase change memory device

    NASA Technical Reports Server (NTRS)

    Campbell, Kristy A. (Inventor)

    2011-01-01

    Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more that two data states.

  20. Forced ion migration for chalcogenide phase change memory device

    NASA Technical Reports Server (NTRS)

    Campbell, Kristy A. (Inventor)

    2012-01-01

    Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

  1. Surface-type nonvolatile electric memory elements based on organic-on-organic CuPc-H2Pc heterojunction

    NASA Astrophysics Data System (ADS)

    Khasan, S. Karimov; Zubair, Ahmad; Farid, Touati; Mahroof-Tahir, M.; M. Muqeet, Rehman; S. Zameer, Abbas

    2015-11-01

    A novel surface-type nonvolatile electric memory elements based on organic semiconductors CuPc and H2Pc are fabricated by vacuum deposition of the CuPc and H2Pc films on preliminary deposited metallic (Ag and Cu) electrodes. The gap between Ag and Cu electrodes is 30-40 μm. For the current-voltage (I-V) characteristics the memory effect, switching effect, and negative differential resistance regions are observed. The switching mechanism is attributed to the electric-field-induced charge transfer. As a result the device switches from a low to a high-conductivity state and then back to a low conductivity state if the opposite polarity voltage is applied. The ratio of resistance at the high resistance state to that at the low resistance state is equal to 120-150. Under the switching condition, the electric current increases ˜ 80-100 times. A comparison between the forward and reverse I-V characteristics shows the presence of rectifying behavior. Project supported by the GIK Institute of Engineering Science and Technology, Pakistan and Physical Technical Institute of Academy of Sciences of Tajikistan.

  2. Study on the strontium bismuth tantalate (SBT) based ferroelectric gate FET for non-volatile non-destructive- read-out memory application

    NASA Astrophysics Data System (ADS)

    Lim, Myoungho

    1997-08-01

    A ferroelectric non-volatile memory has much more superior characteristics than the other non-volatile memories such as a EEPROM, a flash-EEPROM and so forth in terms of data transfer rate, fatigue characteristics, operating voltage etc. A ferroelectric non-volatile memory decreases the programming electric field by 2-3 order of magnitude, and consequently decreases the operation voltages, enhances the reliability of the memory elements, and foremost, increases the switching cycles and speed. The charge injection from silicon to ferroelectric is to be solved to create the Metal/Ferroelectric/Si(MFS) structure. Oxide based ferroelectric film has two physical problems: interdiffusion from ferroelectric into silicon and creation of natural oxide or complex oxide layer in-between ferroelectric and silicon substrate. The electric field in natural oxide grown during annealing ferroelectric film can affect the electrical characteristics of this structure. A ferroelectric gate MOS structure with buffer layers have been proposed and investigated for non-volatile Non- Destructive-Read-Out memory application. SBT was deposited by spun-on Metal Organic Deposition with and without ZrO2 and Y2O3 layer. The control parameters for MFIS structure are optimized. MFIS structures are examined with X-ray diffraction, and TEM. The X-ray diffraction results show good crystal structure of SBT on insulator. TEM pictures show that the ZrO2 and Y2O3 act as a inter-diffusion barrier without additional interface layer between SBT and insulator. C-V characteristics showed that the memory window was 1.8V at the applied voltage of /pm 8~10V in a bias sweep rate of 1sec/V. C-V measurement with the bias sweep rate of 100 sec/0.1V showed no threshold shift. It implies the retention time of this device is more than one day. Current voltage characteristic shows low leakage current density in the level of 10 nA/ cm2 in the operating voltage and below 1nA/ cm2 in the holding state. Finally, the Metal

  3. High performance non-volatile memory with the control of charge trapping states in an amorphous InSnZnO active channel

    NASA Astrophysics Data System (ADS)

    Phu Thi Nguyen, Cam; Thuy Trinh, Thanh; Raja, Jayapal; Le, Anh Huy Tuan; Jang, Kyungsoo; Lee, Youn-Jung; Yi, Junsin

    2015-07-01

    In this study, the influence of interface states between an indium tin zinc oxide (ITZO) active layer and a gate insulator on memory characteristics was examined as a function of annealing temperature. The annealing nonvolatile memory (NVM) devices have shown the best electrical characteristics such as high field effect mobility (27.22 cm2 V-1 s-1), low threshold voltage (0.15 V), low subthreshold slope (0.17 V dec-1), and high on/off current ratio (7.57 × 107) in comparison with as-deposited devices. By annealing at 250 °C, the number of ITZO/insulator interface trap densities was reduced. The effect of the remaining trap states on the retention characteristic of memory devices is negligible. The performance of NVM devices using different annealing temperatures of ITZO and a multi-stack gate insulator SiO2/SiOx/SiOxNy with Si-rich SiOx for the charge storage layer was also reported. The 250 °C annealed ITZO-based NVM device showed a retention exceeding ˜94% of the threshold voltage shift after 104 s and greater than ˜90% after 10 years with a low operating voltage of +11 V at only 1 μs programming duration time. Therefore, the NVM devices, which were fabricated by the low ITZO/insulator interface trap densities, were highly suitable for potential application in memory systems.

  4. Studies for the device structures and mechanisms of organic memories

    NASA Astrophysics Data System (ADS)

    Yang, Guanwen

    Non-volatile memories, which could retain the stored information without power, have undergone an impressive development due to the growth of the electronic portable equipments. Since the flash memory was commercialized in the early 1990s, it has become one of the most important techniques in non-volatile memories market. Due to the fact of technical and physical constraints to be further scaled down, new memory structures and technologies need to be invented to accommodate the future requirements of electronic equipments. In this dissertation, I focused on varied switching mechanisms in different device structures. To typical metal-insulator-metal structure, I proved that more than one conduction mechanism could be involved and different mechanisms could be switched from each other. An organic bistable light emitting devices based on the structure of OBDs, which provided both optical and electrical bistable state output, was proved in Chapter 3. Also, a new structure of nanoscale memory cell based on local milling of cavities is proposed in Chapter 4. The filament formation is considered to cause the switching.

  5. Electron Spin Resonance and Photoluminescence Study of Charge Trap Centers in Silicon Nitride Films and Fabrication of Proposed Oxide-Nitride-Oxide Sidewall 2-bit/Cell Nonvolatile Memories

    NASA Astrophysics Data System (ADS)

    Toki, Atsushi; Shinohara, Noriaki; Kamigaki, Yoshiaki; Nakano, Masayuki; Shibata, Akihide; Okumine, Tetsuya; Shiomi, Takeshi; Sugimoto, Kazuo; Negishi, Tetsu; Yoshioka, Fumiyoshi; Kotaki, Hiroshi

    2008-04-01

    We have proposed a novel oxide-nitride-oxide (ONO)-sidewall 2-bit/cell nonvolatile memory and fabricated 70-nm-node nonvolatile memory devices. For low-pressure chemical-vapor-deposition (LPCVD)-SiN films, with increasing SiH4/NH3 mixture gas ratio, we have found from ESR and PL evaluation that the paramagnetic defect density increases and some PL emission energy levels become deeper. We consider that the energy-level shift is due to the effects of trap potential overlapping, where the trap centers are generated at the excess silicon atoms in the SiN films. In this study, a SiH4/NH3 mixture gas ratio of less than 1:100 was used to suppress the potential overlapping. As a result, we have also shown that the proposed memory device has high performance and excellent scalability.

  6. Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

    PubMed

    Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

    2015-03-04

    Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

  7. A Compute Capable SSD Architecture for Next-Generation Non-volatile Memories

    SciTech Connect

    De, Arup

    2014-01-01

    Existing storage technologies (e.g., disks and ash) are failing to cope with the processor and main memory speed and are limiting the overall perfor- mance of many large scale I/O or data-intensive applications. Emerging fast byte-addressable non-volatile memory (NVM) technologies, such as phase-change memory (PCM), spin-transfer torque memory (STTM) and memristor are very promising and are approaching DRAM-like performance with lower power con- sumption and higher density as process technology scales. These new memories are narrowing down the performance gap between the storage and the main mem- ory and are putting forward challenging problems on existing SSD architecture, I/O interface (e.g, SATA, PCIe) and software. This dissertation addresses those challenges and presents a novel SSD architecture called XSSD. XSSD o oads com- putation in storage to exploit fast NVMs and reduce the redundant data tra c across the I/O bus. XSSD o ers a exible RPC-based programming framework that developers can use for application development on SSD without dealing with the complication of the underlying architecture and communication management. We have built a prototype of XSSD on the BEE3 FPGA prototyping system. We implement various data-intensive applications and achieve speedup and energy ef- ciency of 1.5-8.9 and 1.7-10.27 respectively. This dissertation also compares XSSD with previous work on intelligent storage and intelligent memory. The existing ecosystem and these new enabling technologies make this system more viable than earlier ones.

  8. Memory bistable mechanisms of organic memory devices

    NASA Astrophysics Data System (ADS)

    Lee, Ching-Ting; Yu, Li-Zhen; Chen, Hung-Chun

    2010-07-01

    To investigate the memory bistable mechanisms of organic memory devices, the structure of [top Au anode/9,10-di(2-naphthyl)anthracene (ADN) active layer/bottom Au cathode] was deposited using a thermal deposition system. The Au atoms migrated into the ADN active layer was observed from the secondary ion mass spectrometry. The density of 9.6×1016 cm-3 and energy level of 0.553 eV of the induced trapping centers caused by the migrated Au atoms in the ADN active layer were calculated. The induced trapping centers did not influence the carrier injection barrier height between Au and ADN active layer. Therefore, the memory bistable behaviors of the organic memory devices were attributed to the induced trapping centers. The energy diagram was established to verify the mechanisms.

  9. Large scale integration of flexible non-volatile, re-addressable memories using P(VDF-TrFE) and amorphous oxide transistors

    NASA Astrophysics Data System (ADS)

    Gelinck, Gerwin H.; Cobb, Brian; van Breemen, Albert J. J. M.; Myny, Kris

    2015-07-01

    Ferroelectric polymers and amorphous metal oxide semiconductors have emerged as important materials for re-programmable non-volatile memories and high-performance, flexible thin-film transistors, respectively. However, realizing sophisticated transistor memory arrays has proven to be a challenge, and demonstrating reliable writing to and reading from such a large scale memory has thus far not been demonstrated. Here, we report an integration of ferroelectric, P(VDF-TrFE), transistor memory arrays with thin-film circuitry that can address each individual memory element in that array. n-type indium gallium zinc oxide is used as the active channel material in both the memory and logic thin-film transistors. The maximum process temperature is 200 °C, allowing plastic films to be used as substrate material. The technology was scaled up to 150 mm wafer size, and offers good reproducibility, high device yield and low device variation. This forms the basis for successful demonstration of memory arrays, read and write circuitry, and the integration of these.

  10. Ultrathin flexible memory devices based on organic ferroelectric transistors

    NASA Astrophysics Data System (ADS)

    Sugano, Ryo; Hirai, Yoshinori; Tashiro, Tomoya; Sekine, Tomohito; Fukuda, Kenjiro; Kumaki, Daisuke; Domingues dos Santos, Fabrice; Miyabo, Atsushi; Tokito, Shizuo

    2016-10-01

    Here, we demonstrate ultrathin, flexible nonvolatile memory devices with excellent durability under compressive strain. Ferroelectric-gate field-effect transistors (FeFETs) employing organic semiconductor and polymer ferroelectric layers are fabricated on a 1-µm-thick plastic film substrate. The FeFETs are characterized by measuring their transfer characteristics, programming time, and data retention time. The data retention time is almost unchanged even when a 50% compressive strain is applied to the devices. To clarify the origin of the excellent durability of the devices against compressive strain, an intermediate plane is calculated. From the calculation result, the intermediate plane is placed close to the channel region of the FeFETs. The high flexibility of the ferroelectric polymer and ultrathin device structure contributes to achieving a bending radius of 0.8 µm without the degradation of memory characteristics.

  11. Operating mechanism of electrically bistable memory device based on Ag doped CdSe/PVA nanocomposite

    NASA Astrophysics Data System (ADS)

    Kaur, Ramneek; Tripathi, S. K.

    2015-06-01

    This paper reports the fabrication and characterization of electrically bistable memory device with device structure Al/Ag doped CdSe/PVA nanocomposite/Ag. Current-Voltage (I-V) measurements show two conductivity states at the same applied voltage indicating the bistability behavior. The possible operating mechanism for the memory effects has been described. During transition from the low resistance state to high resistance state, the current follows the change from the injection emission to the space charge limited conduction mechanism. The achieved results demonstrate that the device based on Ag doped CdSe/PVA nanocomposite has a potential for future non-volatile memory devices.

  12. SiNx Charge Trap Nonvolatile Memory Based on ZnO Thin Film Transistor Prepared by Atomic Layer Deposition

    NASA Astrophysics Data System (ADS)

    Kim, E.; Lee, K.; Kim, D.; Parsons, G. N.; Park, K.

    2011-12-01

    We fabricated a nonvolatile thin film transistor (TFT) memory with SiNx charge traps using a ZnO thin film as an active channel layer. The thin film of ZnO was deposited by using atomic layer deposition process at TALD = 125 °C. The ZnO films were investigated by X-ray diffraction and X-ray photoemission measurements. The electrical measurements of the nonvolatile TFT memory showed a field-effect mobility of 2.95 cm2 V-1 s-1, a threshold voltage of -7.24 V, a subthreshold swing of 1.7 V/dec, and an on/off ratio of 3.4×105. From the C-V measurement, the memory window of 2 V was obtained.

  13. Nonvolatile Ferroelectric Memory Circuit Using Black Phosphorus Nanosheet-Based Field-Effect Transistors with P(VDF-TrFE) Polymer.

    PubMed

    Lee, Young Tack; Kwon, Hyeokjae; Kim, Jin Sung; Kim, Hong-Hee; Lee, Yun Jae; Lim, Jung Ah; Song, Yong-Won; Yi, Yeonjin; Choi, Won-Kook; Hwang, Do Kyung; Im, Seongil

    2015-10-27

    Two-dimensional van der Waals (2D vdWs) materials are a class of new materials that can provide important resources for future electronics and materials sciences due to their unique physical properties. Among 2D vdWs materials, black phosphorus (BP) has exhibited significant potential for use in electronic and optoelectronic applications because of its allotropic properties, high mobility, and direct and narrow band gap. Here, we demonstrate a few-layered BP-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. Experiments showed that our BP-based ferroelectric transistors operate satisfactorily at room temperature in ambient air and exhibit a clear memory window. Unlike conventional ambipolar BP transistors, our ferroelectric transistors showed only p-type characteristics due to the carbon-fluorine (C-F) dipole effect of the P(VDF-TrFE) layer, as well as the highest linear mobility value of 1159 cm(2) V(-1) s(-1) with a 10(3) on/off current ratio. For more advanced memory applications beyond unit memory devices, we implemented two memory inverter circuits, a resistive-load inverter circuit and a complementary inverter circuit, combined with an n-type molybdenum disulfide (MoS2) nanosheet. Our memory inverter circuits displayed a clear memory window of 15 V and memory output voltage efficiency of 95%.

  14. Solution-processed Al-chelated gelatin for highly transparent non-volatile memory applications

    SciTech Connect

    Chang, Yu-Chi; Wang, Yeong-Her

    2015-03-23

    Using the biomaterial of Al-chelated gelatin (ACG) prepared by sol-gel method in the ITO/ACG/ITO structure, a highly transparent resistive random access memory (RRAM) was obtained. The transmittance of the fabricated device is approximately 83% at 550 nm while that of Al/gelatin/ITO is opaque. As to the ITO/gelatin/ITO RRAM, no resistive switching behavior can be seen. The ITO/ACG/ITO RRAM shows high ON/OFF current ratio (>10{sup 5}), low operation voltage, good uniformity, and retention characteristics at room temperature and 85 °C. The mechanism of the ACG-based memory devices is presented. The enhancement of these electrical properties can be attributed to the chelate effect of Al ions with gelatin. Results show that transparent ACG-based memory devices possess the potential for next-generation resistive memories and bio-electronic applications.

  15. Non-volatile nano-floating gate memory with Pt-Fe2O3 composite nanoparticles and indium gallium zinc oxide channel

    NASA Astrophysics Data System (ADS)

    Hu, Quanli; Lee, Seung Chang; Baek, Yoon-Jae; Lee, Hyun Ho; Kang, Chi Jung; Kim, Hyun-Mi; Kim, Ki-Bum; Yoon, Tae-Sik

    2013-02-01

    Non-volatile nano-floating gate memory characteristics with colloidal Pt-Fe2O3 composite nanoparticles with a mostly core-shell structure and indium gallium zinc oxide channel layer were investigated. The Pt-Fe2O3 nanoparticles were chemically synthesized through the preferential oxidation of Fe and subsequent pileup of Pt into the core in the colloidal solution. The uniformly assembled nanoparticles' layer could be formed with a density of 3 × 1011 cm-2 by a solution-based dip-coating process. The Pt core ( 3 nm in diameter) and Fe2O3-shell ( 6 nm in thickness) played the roles of the charge storage node and tunneling barrier, respectively. The device exhibited the hysteresis in current-voltage measurement with a threshold voltage shift of 4.76 V by gate voltage sweeping to +30 V. It also showed the threshold shift of 0.66 V after pulse programming at +20 V for 1 s with retention > 65 % after 104 s. These results demonstrate the feasibility of using colloidal nanoparticles with core-shell structure as gate stacks of the charge storage node and tunneling dielectric for low-temperature and solution-based processed non-volatile memory devices.

  16. Trade-Off Relationship of Size and Density of Platinum Nanocrystal in Nonvolatile Memory Characteristics

    NASA Astrophysics Data System (ADS)

    Seo, Jungmok; Lee, Taeyoon

    2010-10-01

    The replacement of metal nanocrystal (NC)-based nonvolatile memories (NVMs) with polycrystalline silicon floating-gate memories is very attractive, since they demonstrate superior capability of charge localization and a reduction in cell-to-cell interference. Varying the size (ranging from 15.1 to 55.2 nm) and density (from 5.6×1011 to 3.2×1010 cm-2) of the metal NC affects the entire memory properties such as the charging/discharging process, retention characteristic, and charge storage capability. Here, we investigated the effects of the size and density of platinum (Pt) NCs on the aforementioned memory characteristics by fabricating Pt-NC-embedded metal oxide semiconductor (MOS) capacitors using a direct self-assemble method. The flatband voltage shift, a measure of charge storage capability for NC-based NVMs, increased from 5.75 to 13.05 V as the mean size of the NCs was varied from 15.1 to 55.2 nm, which was relatively higher than that of other NC-based NVMs. Our studies revealed that the flatband voltage shift depends on not only the size and density of the NCs, but also the tunneling probability of the electrons, which is closely related to the applied electric field at a tunneling oxide. The relationships among the flatband voltage shift, the size and density of the NCs, and the applied electric field, which are revealed in this study, can be generally applicable to other NVMs based on various metal and semiconducting NCs.

  17. Synthesis of cobalt-based nanocrystal layer in silicon dioxide for nonvolatile memory applications.

    PubMed

    Yoon, Jong-Hwan

    2011-02-01

    Cobalt silicide (CoSi) nanocrystal (NC) layer distributed within narrow spatial region is synthesized by thermal annealing of a sandwich structure comprised of a thin cobalt (Co) film sandwiched between two silicon-rich oxide (SiO(x)) layers. It is shown that the size of the CoSi NCs can be controlled by varying the Co film thickness, an increase in the size with increasing thickness. Capacitance-voltage (C-V) measurements on a test metal/oxide/semiconductor (MOS) structure with floating gate based on CoSi NCs of 3.8 nm in diameter and 1.4 x 10(12) cm2 in density are shown to have C-V characteristics suitable for nonvolatile memory applications, including a C-V memory window of about 9.5 V for sweep voltages between -15 V and +8, a retention time >10(8) s, and an endurance > 10(6) program/erase cycles.

  18. Development of a Tritium Cleanup System for a Large Helical Device Using Nonvolatile Getter Materials

    SciTech Connect

    Kawano, Takao; Sakuma, Yoichi; Kabutomori, Toshiki; Shibuya, Mamoru

    2000-01-15

    A tritium cleanup system has been conceptually developed for the large helical device (LHD) at the National Institute for Fusion Science. The system is a processing device employed to remove tritium from exhaust gas. In the exhaust gas discharged from the LHD in normal operation, the major part of tritium constituents should be in a form of hydrogen molecules because the fuel used in plasma experiments with the LHD is hydrogen molecules. From this viewpoint, we have designed a tritium cleanup system, which is characterized by tritium being removed and stored in a form of hydrogen molecules with less impurities, like oxygen and carbon, and its decomposition and the separation processes are introduced to convert various tritiated compounds into a form of hydrogen molecules of high purity. Besides these, there is another aspect in that getter materials are applied in both decomposition of tritiated compounds and storage of hydrogen molecules containing tritium.The system design is composed of three essential component parts: a hydrogen separator, a hydrogen absorbing vessel, and a decomposition process vessel. The hydrogen separator and the decomposition process vessel make a process loop repeat to remove hydrogen into a form of hydrogen molecules with less impurities. It is important that 'less impurities' means having a less bad influence on hydrogen-absorbing materials used in the storage vessel.We think that the hydrogen separator will be manufactured by employing a palladium hydrogen purifier system, which is available in the marketplace, and the hydrogen storage vessel will also be manufactured by using hydrogen-absorbing alloys like titanium. Thus, the serious problem imposed on us is how to realize the decomposition process vessel. To develop the decomposition process vessel, we thought nonvolatile getter materials were promising and carried out performance tests of methane decomposition by the nonvolatile getter materials, where methane was used because it is

  19. Three-terminal resistive switching memory in a transparent vertical-configuration device

    SciTech Connect

    Ungureanu, Mariana; Llopis, Roger; Casanova, Fèlix; Hueso, Luis E.

    2014-01-06

    The resistive switching phenomenon has attracted much attention recently for memory applications. It describes the reversible change in the resistance of a dielectric between two non-volatile states by the application of electrical pulses. Typical resistive switching memories are two-terminal devices formed by an oxide layer placed between two metal electrodes. Here, we report on the fabrication and operation of a three-terminal resistive switching memory that works as a reconfigurable logic component and offers an increased logic density on chip. The three-terminal memory device we present is transparent and could be further incorporated in transparent computing electronic technologies.

  20. Nonvolatile memories of Ge nanodots self-assembled by depositing ultrasmall amount Ge on SiO{sub 2} at room temperature

    SciTech Connect

    Hong, Seung Hui; Kim, Min Choul; Jeong, Pil Seong; Choi, Suk-Ho; Kim, Yong-Sung; Kim, Kyung Joong

    2008-03-03

    Ge nanodots (NDs) for nonvolatile memories (NVMs) have been self-assembled at room temperature (RT) by ion beam sputtering deposition of ultrasmall amount Ge (<72 ML) on SiO{sub 2} without postannealing. High-resolution transmission electron microscopy demonstrates the existence of well-defined Ge ND layers with respect to the SiO{sub 2}/Si interface. As Ge amount increases, the size of NDs increases, while their density decreases. A possible mechanism is proposed to explain the formation of Ge NDs at RT based on simple model calculations. The memory window that is estimated by capacitance-voltage hysteresis increases up to 18.7 V with increasing Ge amount up to 54 ML. The program speed is enhanced by increasing Ge amount and the charge-loss speed in the programed state is slower for larger Ge amount. These NVM properties are very promising in view of device application.

  1. Unipolar resistive switching in metal oxide/organic semiconductor non-volatile memories as a critical phenomenon

    NASA Astrophysics Data System (ADS)

    Bory, Benjamin F.; Rocha, Paulo R. F.; Gomes, Henrique L.; de Leeuw, Dago M.; Meskers, Stefan C. J.

    2015-11-01

    Diodes incorporating a bilayer of an organic semiconductor and a wide bandgap metal oxide can show unipolar, non-volatile memory behavior after electroforming. The prolonged bias voltage stress induces defects in the metal oxide with an areal density exceeding 1017 m-2. We explain the electrical bistability by the coexistence of two thermodynamically stable phases at the interface between an organic semiconductor and metal oxide. One phase contains mainly ionized defects and has a low work function, while the other phase has mainly neutral defects and a high work function. In the diodes, domains of the phase with a low work function constitute current filaments. The phase composition and critical temperature are derived from a 2D Ising model as a function of chemical potential. The model predicts filamentary conduction exhibiting a negative differential resistance and nonvolatile memory behavior. The model is expected to be generally applicable to any bilayer system that shows unipolar resistive switching.

  2. Unipolar resistive switching in metal oxide/organic semiconductor non-volatile memories as a critical phenomenon

    SciTech Connect

    Bory, Benjamin F.; Meskers, Stefan C. J.; Rocha, Paulo R. F.; Gomes, Henrique L.; Leeuw, Dago M. de

    2015-11-28

    Diodes incorporating a bilayer of an organic semiconductor and a wide bandgap metal oxide can show unipolar, non-volatile memory behavior after electroforming. The prolonged bias voltage stress induces defects in the metal oxide with an areal density exceeding 10{sup 17 }m{sup −2}. We explain the electrical bistability by the coexistence of two thermodynamically stable phases at the interface between an organic semiconductor and metal oxide. One phase contains mainly ionized defects and has a low work function, while the other phase has mainly neutral defects and a high work function. In the diodes, domains of the phase with a low work function constitute current filaments. The phase composition and critical temperature are derived from a 2D Ising model as a function of chemical potential. The model predicts filamentary conduction exhibiting a negative differential resistance and nonvolatile memory behavior. The model is expected to be generally applicable to any bilayer system that shows unipolar resistive switching.

  3. Metal-oxide-semiconductor diodes containing C60 fullerenes for non-volatile memory applications

    NASA Astrophysics Data System (ADS)

    Beckmeier, Daniel; Baumgärtner, Hermann

    2013-01-01

    For non-volatile memories, silicon-oxide-nitride-oxide-silicon or floating gate structures are used to store information by charging and discharging electronic states reversibly. In this article, we propose to replace the floating gate by C60 molecules. This would allow more defined programming voltages because of the discrete molecular energy levels and a higher resistance to tunneling oxide defects because of the weak electrical connection between the single molecules. Such C60 MOS diode structures are produced and their electrical properties are analyzed regarding current transport and charging mechanism of the molecules. To create the MOS structures, C60 molecules (5% of a monolayer) are evaporated onto a part of a clean silicon wafer and covered by amorphous silicon in situ in an ultra high vacuum system. Then the wafer is oxidized in wet atmosphere at just 710 °C through the C60 layer. The goal is to produce a clean oxide above and under the molecules without destroying them. Aluminum gate contacts are defined on top of these layers to perform complementary capacitance voltage (CV) and current voltage (IV) measurements. First, the gate voltage is swept to analyze the injection current, then CV measurements are performed after each sweep to analyze the charge state of the C60 layer and the oxide quality. Reference diodes without C60 on the same wafer show an identical Fowler-Nordheim (FN) tunneling behavior for currents injected from silicon or from aluminum, respectively. In the CV curves, no pronounced flatband voltage shift is observable. In diodes with C60, for negative gate voltages, a classical FN tunneling is observed and compared to theory. The electron injection from silicon shows a different tunneling current behavior. It starts at a lower electric field and has a smaller slope then a FN current would have. It is identified as a trap-assisted tunneling (TAT) current caused by oxidation-induced traps under the C60 layer. It is modeled by an

  4. A novel polysilicon field-enhanced nanowire thin-film transistor with the TiN-hafnia-nitride-vacuum-silicon (THNVAS) structure for nonvolatile memory applications.

    PubMed

    Wu, Chun-Yu; Liao, Ta-Chuan; Liu, Yen-Ting; Yu, Ming H; Cheng, Huang-Chung

    2012-07-01

    A novel poly-Si field-enhanced nanowire (FEN) TFT memory with the TiN-hafnia-nitride-vacuum-silicon (THNVAS) structure fabricated simply via a sidewall spacer formation has been presented. The THNVAS devices with superior memory performance were demonstrated by introducing the hafnia as blocking oxide and the vacuum, the lowest-k in nature, as tunneling layer. According to the simulation results, the memory device with oxide/nitride/vacuum gate dielectric exhibited a higher local electric-field of 4.72 x 10(7) V/cm as compared to 2.55 x 10(7) V/cm for the conventional oxide/nitride/oxide counterpart. In addition, the electric-field of tunneling layer could be further increased to 7.06 x 10(7) V/cm while the blocking oxide was substituted for hafnia. The experimental data showed that THNVAS possessed a greater threshold voltage shift of 3.75 V in 10 ms at V(GS) = 12 V, whereas the shift only 2.5 V for THNOS ones. These considerable improvements for THNVAS devices could be attributed to the evident field enhancement across the vacuum tunneling layer. Furthermore, owing to the empty feature of vacuum tunneling layer, the THNVAS demonstrated much-improved endurance performance and preferable data retention property. Hence, such excellent characteristics of THNVAS will be an attractive nonvolatile memory for future system-on-panel and 3-D Flash applications.

  5. Bipolar tri-state resistive switching characteristics in Ti/CeOx/Pt memory device

    NASA Astrophysics Data System (ADS)

    Ismail, M.; W. Abbas, M.; M. Rana, A.; Talib, I.; E., Ahmed; Y. Nadeem, M.; L. Tsai, T.; U., Chand; A. Shah, N.; Hussain, M.; Aziz, A.; T. Bhatti, M.

    2014-12-01

    Highly repeatable multilevel bipolar resistive switching in Ti/CeOx/Pt nonvolatile memory device has been demonstrated. X-ray diffraction studies of CeO2 films reveal the formation of weak polycrystalline structure. The observed good memory performance, including stable cycling endurance and long data retention times (> 104 s) with an acceptable resistance ratio (~102), enables the device for its applications in future non-volatile resistive random access memories (RRAMs). Based on the unique distribution characteristics of oxygen vacancies in CeOx films, the possible mechanism of multilevel resistive switching in CeOx RRAM devices has been discussed. The conduction mechanism in low resistance state is found to be Ohmic due to conductive filamentary paths, while that in the high resistance state was identified as Ohmic for low applied voltages and a space-charge-limited conduction dominated by Schottky emission at high applied voltages.

  6. High Performance Nonvolatile Transistor Memories Utilizing Functional Polyimide-Based Supramolecular Electrets.

    PubMed

    Tung, Wei-Yao; Li, Meng-Hsien; Wu, Hung-Chin; Liu, Hsin-Yu; Hsieh, Yun-Ting; Chen, Wen-Chang

    2016-05-20

    We report pentacene-based organic field-effect transistor memory devices utilizing supramolecular electrets, consisting of a polyimide, PI(6FOH-ODPA), containing hydroxyl groups for hydrogen bonding with amine functionalized aromatic rings (AM) of 1-aniline (AM1), 2-naphthylamine (AM2), 2-aminoanthracene (AM3), and 1-aminopyrene (AM4). The effect of the phenyl ring size and composition of AM1-AM4 on the hole-trapping capability of the fabricated devices was investigated systematically. Under an operating voltage under ±40 V, the prepared devices using the electrets of 100 % AM1-AM4/PI ratios exhibited a memory window of 0, 8.59, 25.97, and 29.95 V, respectively, suggesting that the hole-trapping capability increased with enhancing phenyl ring size. The memory window was enhanced as the amount of AM in PI increased. Furthermore, the devices showed a long charge-retention time of 10(4)  s with an ON/OFF current ratio of around 10(3) -10(4) and multiple switching stability over 100 cycles. This study demonstrated that the electrical characteristics of the OFET memory devices could be manipulated through the chemical compositions of the supramolecular electrets. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  7. Fully transparent, non-volatile bipolar resistive memory based on flexible copolyimide films

    NASA Astrophysics Data System (ADS)

    Yu, Hwan-Chul; Kim, Moon Young; Hong, Minki; Nam, Kiyong; Choi, Ju-Young; Lee, Kwang-Hun; Baeck, Kyoung Koo; Kim, Kyoung-Kook; Cho, Soohaeng; Chung, Chan-Moon

    2017-01-01

    Partially aliphatic homopolyimides and copolyimides were prepared from rel-(1'R,3S,5'S)-spiro[furan-3(2H),6'-[3]oxabicyclo[3.2.1]octane]-2,2',4',5(4H)-tetrone (DAn), 2,6-diaminoanthracene (AnDA), and 4,4'-oxydianiline (ODA) by varying the molar ratio of AnDA and ODA. We utilized these polyimide films as the resistive switching layer in transparent memory devices. While WORM memory behavior was obtained with the PI-A100-O0-based device (molar feed ratio of DAn : AnDA : ODA = 1 : 1 : 0), the PI-A70-O30-based device (molar feed ratio of DAn : AnDA : ODA = 1 : 0.7 : 0.3) exhibited bipolar resistive switching behavior with stable retention for 104 s. This result implies that the memory properties can be controlled by changing the polyimide composition. The two devices prepared from PI-A100-O0 and PI-A70-O30 showed over 90% transmittance in the visible wavelength range from 400 to 800 nm. The behavior of the memory devices is considered to be governed by trap-controlled, space-charge limited conduction (SCLC) and local filament formation. [Figure not available: see fulltext.

  8. One-Transistor-One-Transistor (1T1T) Optoelectronic Nonvolatile MoS2 Memory Cell with Nondestructive Read-Out.

    PubMed

    Lee, Dain; Kim, Seongchan; Kim, Yeontae; Cho, Jeong Ho

    2017-08-09

    Taking advantage of the superlative optoelectronic properties of single-layer MoS2, we developed a one-transistor-one-transistor (1T1T)-type MoS2 optoelectronic nonvolatile memory cell. The 1T1T memory cell consisted of a control transistor (CT) and a memory transistor (MT), in which the drain electrode of the MT was connected electrically to the gate electrode of the CT, whereas the source electrode of the CT was connected electrically to the gate electrode of the MT. Single-layer MoS2 films were utilized as the channel materials in both transistors, and gold nanoparticles acted as the floating gates in the MT. This 1T1T device architecture allowed for a nondestructive read-out operation in the memory because the writing (programming or erasing) and read-out processes were operated separately. The switching of the CT could be controlled by light illumination as well as the applied gate voltage due to the strong light absorption induced by the direct band gap of single-layer MoS2 (∼1.8 eV). The resulting MoS2 1T1T memory cell exhibited excellent memory performance, including a large programming/erasing current ratio (over 10(6)), multilevel data storage (over 6 levels), cyclic endurance (200 cycles), and stable retention (10(3) s).

  9. Dielectric hysteresis, relaxation dynamics, and nonvolatile memory effect in carbon nanotube dispersed liquid crystal

    NASA Astrophysics Data System (ADS)

    Basu, Rajratan; Iannacchione, Germano S.

    2009-12-01

    Self-organizing nematic liquid crystals (LCs) impart their orientational order onto dispersed carbon nanotubes (CNTs) and obtain CNT-self-assembly on a macroscopic dimension. The nanotube-long axis, being coupled to the nematic director, enables orientational manipulation via the LC nematic reorientation. Electric-field-induced director rotation of a nematic LC+CNT system is of potential interest due to its possible application as a nanoelectromechanical system. Electric field and temperature dependence of dielectric properties of a LC+CNT composite system have been investigated to understand the principles governing CNT assembly mediated by the LC. In the LC+CNT nematic phase, the dielectric relaxation on removing the applied field follows a single-exponential decay, exhibiting a faster decay response than the pure LC above a threshold field. The observed dielectric behaviors on field cycling in the nematic phase for the composite indicates an electromechanical hysteresis effect of the director field due to the LC-CNT anchoring mechanism. Observations in the isotropic phase coherently combine to confirm the presence of anisotropic pseudonematic domains stabilized by the LC-CNT anchoring energy. These polarized domains maintain local directors and respond to external fields, but do not relax back to the original state on switching the field off, showing nonvolatile memory effect.

  10. Flexible and stackable non-volatile resistive memory for high integration

    NASA Astrophysics Data System (ADS)

    Ali, Shawkat; Bae, Jinho; Lee, Chong Hyun

    2015-08-01

    We propose a novel flexible and stackable resistive random access memory (ReRAM) array with multi-layered crossbar structures fabricated on a PET flexible substrate through EHD system. The basic memory block of the proposed device is based on one resistor and multi-layered column memristors (1R-MCM) structure, which can be easily extended to 3 dimensional columns for a high integration. To fabricate the device, the materials Ag for top and bottom electrodes, PVP for memristor, and (MEH:PPV and PMMA in acetonitrile) for pull-up resistors are used. Memory single cell is consisted of a high OFF/ON ratio (~4663) memristor and a pull-up resistor (20 MΩ) that operate on the principles of voltage divider circuit. Memory logic data is retrieve in the form of voltage levels instead of sensing current the of crossbar array. Two memory crossbar arrays are stacked vertically and they are sharing column bars, each column's memristors are with a single pull-up resistor. A 3x3 stacked memory with two layers that can store 18 bits of data is demonstrated to realize on a small area for a high integration.

  11. Control over variability in nonvolatile hafnium-oxide resistive-switching memory based on modeling of the switching processes

    NASA Astrophysics Data System (ADS)

    Butcher, Brian Jerad

    Resistive random access memory (ReRAM) technology presents an attractive option for embedded non-volatile (NV) memory systems if its variability (cycle-to-cycle and device-to-device) can be controlled. This dissertation has focused on investigations to identify key mechanisms and parameters which dominate ReRAM variability, and the development of subsequent experimental and simulation-based tools to address this variability. The first component of these efforts entailed identification of the modern-day non-volatile memory technological gaps that have driven the operational requirements and challenges for resistive memory as an emerging NV memory. Initial research confirmed the critical requirement of a sub-stoichiometric (HfO2-x) dielectric regarding the enablement of stable switching and suggested a defect-driven mechanism, which is discussed in detail. Preliminary experimental work was focused on the fabrication of a durable current-limiting (1T1R) testing structure; which was utilized to enable ReRAM device characterization, reduce unwanted parasitic capacitances, and overshoot-current. Initial electrical and physical characterization confirmed a filamentary based (defect-driven) mechanism based on ReRAM scalability-trends (in device sizes ranging from 50x50nm2 to 7x7microm2). Physical analysis (AFM, TEM and EELS) verified a `dominant-filament mechanism' in transmission-metal-oxide (specifically HfO2-x) based ReRAM. A novel characterization and analysis protocol for key electrical parameters affecting filament formation for HfO2-x-based ReRAMs was developed, focusing on the roles of current, voltage, and temperature. This protocol included characterization of the high-resistive-state (HRS) dependence on the maximum FORMING current (seen during 1st RESET Imax) and the characterization of low-power endurance. This characterization protocol was employed to investigate and develop an approach for ReRAM filament formation at elevated temperatures (hot FORMING) to

  12. Efficient Nonvolatile Rewritable Memories Based on Three-Dimensionally Confined Au Quantum Dots Embedded in Ultrathin Polyimide Layers

    NASA Astrophysics Data System (ADS)

    Wu, Chaoxing; Li, Fushan; Guo, Tailiang; Qu, Bo; Chen, Zhijian; Gong, Qihuang

    2011-03-01

    The electrical properties of a nonvolatile organic bistable device (OBD) utilizing Au quantum dots (QDs) sandwiched between two thin insulating polyimide layers were investigated. Current-voltage (I-V) measurements on the device at room temperature showed a current bistability due to the existence of the Au QDs. The maximum ON/OFF ratio of the current bistability in the OBD was 1 ×108, the largest value ever reported for a stable OBD. The device has excellent endurance and retention ability in ambient conditions. The electrical properties and operating mechanisms for the device are analyzed on the basis of the I-V results.

  13. Fast, Capacious Disk Memory Device

    NASA Technical Reports Server (NTRS)

    Muller, Ronald M.

    1990-01-01

    Device for recording digital data on, and playing back data from, memory disks has high recording or playback rate and utilizes available recording area more fully. Two disks, each with own reading/writing head, used to record data at same time. Head on disk A operates on one of tracks numbered from outside in; head on disk B operates on track of same number in sequence from inside out. Underlying concept of device applicable to magnetic or optical disks.

  14. Impact of time and space evolution of ion tracks in nonvolatile memory cells approaching nanoscale

    NASA Astrophysics Data System (ADS)

    Cellere, G.; Paccagnella, A.; Murat, M.; Barak, J.; Akkerman, A.; Harboe-Sorensen, R.; Virtanen, A.; Visconti, A.; Bonanomi, M.

    2010-12-01

    Swift heavy ions impacting on matter lose energy through the creation of dense tracks of charges. The study of the space and time evolution of energy exchange allows understanding the single event effects behavior in advanced microelectronic devices. In particular, the shrinking of minimum feature size of most advanced memory devices makes them very interesting test vehicles to study these effects since the device and the track dimensions are comparable; hence, measured effects are directly correlated with the time and space evolution of the energy release. In this work we are studying the time and space evolution of ion tracks by using advanced non volatile memories and Monte Carlo simulations. Experimental results are very well explained by the theoretical calculations.

  15. Impact of time and space evolution of ion tracks in nonvolatile memory cells approaching nanoscale

    SciTech Connect

    Cellere, G.; Paccagnella, A.; Harboe-Sorensen, R.; Visconti, A.; Bonanomi, M.

    2010-12-15

    Swift heavy ions impacting on matter lose energy through the creation of dense tracks of charges. The study of the space and time evolution of energy exchange allows understanding the single event effects behavior in advanced microelectronic devices. In particular, the shrinking of minimum feature size of most advanced memory devices makes them very interesting test vehicles to study these effects since the device and the track dimensions are comparable; hence, measured effects are directly correlated with the time and space evolution of the energy release. In this work we are studying the time and space evolution of ion tracks by using advanced non volatile memories and Monte Carlo simulations. Experimental results are very well explained by the theoretical calculations.

  16. Piezoelectric control of magnetoelectric coupling driven non-volatile memory switching and self cooling effects in FE/FSMA multiferroic heterostructures

    NASA Astrophysics Data System (ADS)

    Singh, Kirandeep; Kaur, Davinder

    2017-02-01

    The manipulation of magnetic states and materials' spin degree-of-freedom via a control of an electric (E-) field has been recently pursued to develop magnetoelectric (ME) coupling-driven electronic data storage devices with high read/write endurance, fast dynamic response, and low energy dissipation. One major hurdle for this approach is to develop reliable materials which should be compatible with prevailing silicon (Si)-based complementary metal-oxide-semiconductor (CMOS) technology, simultaneously allowing small voltage for the tuning of magnetization switching. In this regard, multiferroic heterostructures where ferromagnetic (FM) and ferroelectric (FE) layers are alternatively grown on conventional Si substrates are promising as the piezoelectric control of magnetization switching is anticipated to be possible by an E-field. In this work, we study the ferromagnetic shape memory alloys based PbZr0.52Ti0.48O3/Ni50Mn35In15 (PZT/Ni-Mn-In) multiferroic heterostructures, and investigate their potential for CMOS compatible non-volatile magnetic data storage applications. We demonstrate the voltage-impulse controlled nonvolatile, reversible, and bistable magnetization switching at room temperature in Si-integrated PZT/Ni-Mn-In thin film multiferroic heterostructures. We also thoroughly unveil the various intriguing features in these materials, such as E-field tuned ME coupling and magnetocaloric effect, shape memory induced ferroelectric modulation, improved fatigue endurance as well as Refrigeration Capacity (RC). This comprehensive study suggests that these novel materials have a great potential for the development of unconventional nanoscale memory and refrigeration devices with self-cooling effect and enhanced refrigeration efficiency, thus providing a new venue for their applications.

  17. Nonvolatile flexible organic bistable devices fabricated utilizing CdSe/ZnS nanoparticles embedded in a conducting poly N-vinylcarbazole polymer layer

    NASA Astrophysics Data System (ADS)

    Son, Dong-Ick; Kim, Ji-Hwan; Park, Dong-Hee; Choi, Won Kook; Li, Fushan; Ham, Jung Hun; Kim, Tae Whan

    2008-02-01

    The bistable effects of CdSe/ZnS nanoparticles embedded in a conducting poly N-vinylcarbazole (PVK) polymer layer by using flexible poly-vinylidene difluoride (PVDF) and polyethylene terephthalate (PET) substrates were investigated. Transmission electron microscopy (TEM) images revealed that CdSe/ZnS nanoparticles were formed inside the PVK polymer layer. Current-voltage (I-V) measurement on the Al/[CdSe/ZnS nanoparticles+ PVK]/ITO/PVDF and Al/[CdSe/ZnS nanoparticles+ PVK ]/ITO/PET structures at 300 K showed a nonvolatile electrical bistability behavior with a flat-band voltage shift due to the existence of the CdSe/ZnS nanoparticles, indicative of trapping, storing and emission of charges in the electronic states of the CdSe nanoparticles. A bistable behavior for the fabricated organic bistable device (OBD) structures is described on the basis of the I-V results. These results indicate that OBDs fabricated by embedding inorganic CdSe/ZnS nanoparticles in a conducting polymer matrix on flexible substrates are prospects for potential applications in flexible nonvolatile flash memory devices.

  18. Switching mechanism transition induced by annealing treatment in nonvolatile Cu/ZnO/Cu/ZnO/Pt resistive memory: From carrier trapping/detrapping to electrochemical metallization

    NASA Astrophysics Data System (ADS)

    Yang, Y. C.; Pan, F.; Zeng, F.; Liu, M.

    2009-12-01

    ZnO/Cu/ZnO trilayer films sandwiched between Cu and Pt electrodes were prepared for nonvolatile resistive memory applications. These structures show resistance switching under electrical bias both before and after a rapid thermal annealing (RTA) treatment, while it is found that the resistive switching effects in the two cases exhibit distinct characteristics. Compared with the as-fabricated device, the memory cell after RTA demonstrates remarkable device parameter improvements including lower threshold voltages, lower write current, and higher Roff/Ron ratio. A high-voltage forming process is avoided in the annealed device as well. Furthermore, the RTA treatment has triggered a switching mechanism transition from a carrier trapping/detrapping type to an electrochemical-redox-reaction-controlled conductive filament formation/rupture process, as indicated by different features in current-voltage characteristics. Both scanning electron microscopy observations and Auger electron spectroscopy depth profiles reveal that the Cu charge trapping layer in ZnO/Cu/ZnO disperses uniformly into the storage medium after RTA, while x-ray diffraction and x-ray photoelectron spectroscopy analyses demonstrate that the Cu atoms have lost electrons to become Cu2+ ions after dispersion. The above experimental facts indicate that the altered status of Cu in the ZnO/Cu/ZnO trilayer films during RTA treatment should be responsible for the switching mechanism transition. This study is envisioned to open the door for understanding the interrelation between different mechanisms that currently exist in the field of resistive memories.

  19. A triple quantum dot based nano-electromechanical memory device

    SciTech Connect

    Pozner, R.; Lifshitz, E.; Peskin, U.

    2015-09-14

    Colloidal quantum dots (CQDs) are free-standing nano-structures with chemically tunable electronic properties. This tunability offers intriguing possibilities for nano-electromechanical devices. In this work, we consider a nano-electromechanical nonvolatile memory (NVM) device incorporating a triple quantum dot (TQD) cluster. The device operation is based on a bias induced motion of a floating quantum dot (FQD) located between two bound quantum dots (BQDs). The mechanical motion is used for switching between two stable states, “ON” and “OFF” states, where ligand-mediated effective interdot forces between the BQDs and the FQD serve to hold the FQD in each stable position under zero bias. Considering realistic microscopic parameters, our quantum-classical theoretical treatment of the TQD reveals the characteristics of the NVM.

  20. Modeling floating body memory devices

    NASA Astrophysics Data System (ADS)

    Hindupur, Ramya

    TCAD simulations have been performed using SILVACO ATLAS 2D device simulator for a Zero-Capacitor Random Access Memory (ZRAM), a new generation memory cell which is being researched as an alternative for DRAM memory cells in order to get rid of the bulky storage capacitor. In our study we have taken into consideration a Dual Gate-ZRAM (DGZRAM) as it helps reduce drain-induced barrier lowering and hence leakage, while having better control of the charge in the substrate. The states are written into the device using impact ionization to generate a large number of holes in the substrate, which alter the threshold voltage of the device. The effect of the gate oxide thickness and substrate body thickness are being taken into consideration to increase the change in the threshold voltage and thereby the noise margin. A DGZRAM structure with a Quantum well introduced into the substrate via a SiGe layer was also simulated. The quantum well introduces a hole storage pocket in the substrate. Comparisons in terms of noise margin have been made for both the devices, which show that the structure with the quantum well in the substrate performs better than the bulk structure. Simulations have been performed taking into consideration gate electrodes with different work functions and it has been observed that while n-polysilicon has a detrimental impact in conventional MOSFETs due to high off-state leakage current, it can be used to obtain low power memory cells. Parameters such as the quantum well doping density, composition of Ge in the quantum well, channel length of the device, SiGe layer thickness and its position with respect to the top gate have been varied to obtain the optimum noise margin for the device.

  1. Improved Retention Characteristic in Polycrystalline Silicon-Oxide-Hafnium Oxide-Oxide-Silicon-Type Nonvolatile Memory with Robust Tunnel Oxynitride

    NASA Astrophysics Data System (ADS)

    Hsieh, Chih Ren; Lai, Chiung Hui; Lin, Bo Chun; Zheng, Yuan Kai; Chung Lou, Jen; Lin, Gray

    2011-03-01

    In this paper, we present a simple novel process for forming a robust and reliable oxynitride dielectric with a high nitrogen content. It is highly suitable for n-channel metal-oxide-semiconductor field-effect transistor (nMOSFETs) and polycrystalline silicon-oxide-hafnium oxide-oxide-silicon (SOHOS)-type memory applications. The proposed approach is realized by using chemical oxide with ammonia (NH3) nitridation followed by reoxidation with oxygen (O2). The novel oxynitride process is not only compatible with the standard complementary metal-oxide-semiconductor (CMOS) process, but also can ensure the improvement of flash memory with low-cost manufacturing. The characteristics of nMOSFETs and SOHOS-type nonvolatile memories (NVMs) with a robust oxynitride as a gate oxide or tunnel oxide are studied to demonstrate their advantages such as the retardation of the stress-induced trap generation during constant-voltage stress (CVS), the program/erase behaviors, cycling endurance, and data retention. The results indicate that the proposed robust oxynitride is suitable for future nonvolatile flash memory technology application.

  2. Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

    PubMed

    Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

    2016-09-19

    Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

  3. Oxygen plasma immersion ion implantation treatment to enhance data retention of tungsten nanocrystal nonvolatile memory

    SciTech Connect

    Wang, Jer-Chyi Chang, Wei-Cheng; Lai, Chao-Sung; Chang, Li-Chun; Ai, Chi-Fong; Tsai, Wen-Fa

    2014-03-15

    Data retention characteristics of tungsten nanocrystal (W-NC) memory devices using an oxygen plasma immersion ion implantation (PIII) treatment are investigated. With an increase of oxygen PIII bias voltage and treatment time, the capacitance–voltage hysteresis memory window is increased but the data retention characteristics become degraded. High-resolution transmission electron microscopy images show that this poor data retention is a result of plasma damage on the tunneling oxide layer, which can be prevented by lowering the bias voltage to 7 kV. In addition, by using the elevated temperature retention measurement technique, the effective charge trapping level of the WO{sub 3} film surrounding the W-NCs can be extracted. This measurement reveals that a higher oxygen PIII bias voltage and treatment time induces more shallow traps within the WO{sub 3} film, degrading the retention behavior of the W-NC memory.

  4. Multilevel Ultrafast Flexible Nanoscale Nonvolatile Hybrid Graphene Oxide-Titanium Oxide Memories.

    PubMed

    Nagareddy, V Karthik; Barnes, Matthew D; Zipoli, Federico; Lai, Khue T; Alexeev, Arseny M; Craciun, Monica Felicia; Wright, C David

    2017-02-27

    Graphene oxide (GO) resistive memories offer the promise of low-cost environmentally sustainable fabrication, high mechanical flexibility and high optical transparency, making them ideally suited to future flexible and transparent electronics applications. However, the dimensional and temporal scalability of GO memories, i.e., how small they can be made and how fast they can be switched, is an area that has received scant attention. Moreover, a plethora of GO resistive switching characteristics and mechanisms has been reported in the literature, sometimes leading to a confusing and conflicting picture. Consequently, the potential for graphene oxide to deliver high-performance memories operating on nanometer length and nanosecond time scales is currently unknown. Here we address such shortcomings, presenting not only the smallest (50 nm), fastest (sub-5 ns), thinnest (8 nm) GO-based memory devices produced to date, but also demonstrate that our approach provides easily accessible multilevel (4-level, 2-bit per cell) storage capabilities along with excellent endurance and retention performance-all on both rigid and flexible substrates. Via comprehensive experimental characterizations backed-up by detailed atomistic simulations, we also show that the resistive switching mechanism in our Pt/GO/Ti/Pt devices is driven by redox reactions in the interfacial region between the top (Ti) electrode and the GO layer.

  5. Evaluation of Radiation Effects in Flash Memories

    NASA Technical Reports Server (NTRS)

    Miyahira, T.; Swift, G.

    1998-01-01

    Features of flash memories: Flash memories are non-volatile; that is they do not require power to retain the information in its memory. They can be erased and written to while the device is still in the circuit.

  6. Analogue spin-orbit torque device for artificial-neural-network-based associative memory operation

    NASA Astrophysics Data System (ADS)

    Borders, William A.; Akima, Hisanao; Fukami, Shunsuke; Moriya, Satoshi; Kurihara, Shouta; Horio, Yoshihiko; Sato, Shigeo; Ohno, Hideo

    2017-01-01

    We demonstrate associative memory operations reminiscent of the brain using nonvolatile spintronics devices. Antiferromagnet-ferromagnet bilayer-based Hall devices, which show analogue-like spin-orbit torque switching under zero magnetic fields and behave as artificial synapses, are used. An artificial neural network is used to associate memorized patterns from their noisy versions. We develop a network consisting of a field-programmable gate array and 36 spin-orbit torque devices. An effect of learning on associative memory operations is successfully confirmed for several 3 × 3-block patterns. A discussion on the present approach for realizing spintronics-based artificial intelligence is given.

  7. Colossal Electroresistive Properties Of CSD Grown Pr{sub 0.7}Ca{sub 0.3}MnO{sub 3} Films For Nonvolatile Memory Applications

    SciTech Connect

    Bhavsar, K. H.; Joshi, U. S.

    2010-12-01

    Colossal electroresistance effects upon application of electric field in perovskite oxide Pr{sub 0.7}Ca{sub 0.3}MnO{sub 3}(PCMO) thin films, which is a promising candidate for resistance random access memory (RRAM) device have been investigated. Nanocrystalline PCMO films were grown on SiO{sub 2} substrates by chemical solution deposition and crystallized at 700 deg. C under different gas atmospheres. Four terminal current voltage characteristics of Ag/PCMO/Ag planar geometry exhibited a sharp transition from a low resistance state (LRS) to a high resistance state (HRS) with a resistance switching ratio of as high as 1100% at room temperature. Nonvolatility and high retention was confirmed by electric pulse induced resistive switching measurements. The resistance switching ratios were found to depend on the annealing conditions, suggesting an interaction between the nonlattice oxygen and oxygen vacancies and/or the cationic vacancy.

  8. Design of a Multi-Level/Analog Ferroelectric Memory Device

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

    2006-01-01

    Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

  9. Design of a Multi-Level/Analog Ferroelectric Memory Device

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

    2006-01-01

    Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

  10. A study on degradation mechanisms and low voltage operations in MNOS-type memory devices

    NASA Astrophysics Data System (ADS)

    Suzuki, E.

    1984-05-01

    Metal-nitride-oxide semiconductor (MNOS) type nonvolatile semiconductor memory devices that use electronic traps in the gate insulator as memory sites are studied. A method for measuring the separation of electrons and holes by utilizing the structure of insulated-gate field effect transistors is examined, and mechanisms of carrier conduction in MNOS structures are clarified. Degradation mechanisms of MNOS structure are investigated to improve the devices and to develop new memory devices. It is shown that positive holes, especially those injected from the gate into the nitride, play an important role in degrading the devices. A new electrically erasable programmable read-only memory with metal oxide nitride oxide semiconductor structures is proposed, and its superior memory properties are demonstrated.

  11. Integration of lead-free ferroelectric on HfO2/Si (100) for high performance non-volatile memory applications

    PubMed Central

    Kundu, Souvik; Maurya, Deepam; Clavel, Michael; Zhou, Yuan; Halder, Nripendra N.; Hudait, Mantu K.; Banerji, Pallab; Priya, Shashank

    2015-01-01

    We introduce a novel lead-free ferroelectric thin film (1-x)BaTiO3-xBa(Cu1/3Nb2/3)O3 (x = 0.025) (BT-BCN) integrated on to HfO2 buffered Si for non-volatile memory (NVM) applications. Piezoelectric force microscopy (PFM), x-ray diffraction, and high resolution transmission electron microscopy were employed to establish the ferroelectricity in BT-BCN thin films. PFM study reveals that the domains reversal occurs with 180° phase change by applying external voltage, demonstrating its effectiveness for NVM device applications. X-ray photoelectron microscopy was used to investigate the band alignments between atomic layer deposited HfO2 and pulsed laser deposited BT-BCN films. Programming and erasing operations were explained on the basis of band-alignments. The structure offers large memory window, low leakage current, and high and low capacitance values that were easily distinguishable even after ~106 s, indicating strong charge storage potential. This study explains a new approach towards the realization of ferroelectric based memory devices integrated on Si platform and also opens up a new possibility to embed the system within current complementary metal-oxide-semiconductor processing technology. PMID:25683062

  12. Integration of lead-free ferroelectric on HfO2/Si (100) for high performance non-volatile memory applications

    NASA Astrophysics Data System (ADS)

    Kundu, Souvik; Maurya, Deepam; Clavel, Michael; Zhou, Yuan; Halder, Nripendra N.; Hudait, Mantu K.; Banerji, Pallab; Priya, Shashank

    2015-02-01

    We introduce a novel lead-free ferroelectric thin film (1-x)BaTiO3-xBa(Cu1/3Nb2/3)O3 (x = 0.025) (BT-BCN) integrated on to HfO2 buffered Si for non-volatile memory (NVM) applications. Piezoelectric force microscopy (PFM), x-ray diffraction, and high resolution transmission electron microscopy were employed to establish the ferroelectricity in BT-BCN thin films. PFM study reveals that the domains reversal occurs with 180° phase change by applying external voltage, demonstrating its effectiveness for NVM device applications. X-ray photoelectron microscopy was used to investigate the band alignments between atomic layer deposited HfO2 and pulsed laser deposited BT-BCN films. Programming and erasing operations were explained on the basis of band-alignments. The structure offers large memory window, low leakage current, and high and low capacitance values that were easily distinguishable even after ~106 s, indicating strong charge storage potential. This study explains a new approach towards the realization of ferroelectric based memory devices integrated on Si platform and also opens up a new possibility to embed the system within current complementary metal-oxide-semiconductor processing technology.

  13. Integration of lead-free ferroelectric on HfO2/Si (100) for high performance non-volatile memory applications.

    PubMed

    Kundu, Souvik; Maurya, Deepam; Clavel, Michael; Zhou, Yuan; Halder, Nripendra N; Hudait, Mantu K; Banerji, Pallab; Priya, Shashank

    2015-02-16

    We introduce a novel lead-free ferroelectric thin film (1-x)BaTiO3-xBa(Cu1/3Nb2/3)O3 (x = 0.025) (BT-BCN) integrated on to HfO2 buffered Si for non-volatile memory (NVM) applications. Piezoelectric force microscopy (PFM), x-ray diffraction, and high resolution transmission electron microscopy were employed to establish the ferroelectricity in BT-BCN thin films. PFM study reveals that the domains reversal occurs with 180° phase change by applying external voltage, demonstrating its effectiveness for NVM device applications. X-ray photoelectron microscopy was used to investigate the band alignments between atomic layer deposited HfO2 and pulsed laser deposited BT-BCN films. Programming and erasing operations were explained on the basis of band-alignments. The structure offers large memory window, low leakage current, and high and low capacitance values that were easily distinguishable even after ~10(6) s, indicating strong charge storage potential. This study explains a new approach towards the realization of ferroelectric based memory devices integrated on Si platform and also opens up a new possibility to embed the system within current complementary metal-oxide-semiconductor processing technology.

  14. Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array

    PubMed Central

    Eryilmaz, Sukru B.; Kuzum, Duygu; Jeyasingh, Rakesh; Kim, SangBum; BrightSky, Matthew; Lam, Chung; Wong, H.-S. Philip

    2014-01-01

    Recent advances in neuroscience together with nanoscale electronic device technology have resulted in huge interests in realizing brain-like computing hardwares using emerging nanoscale memory devices as synaptic elements. Although there has been experimental work that demonstrated the operation of nanoscale synaptic element at the single device level, network level studies have been limited to simulations. In this work, we demonstrate, using experiments, array level associative learning using phase change synaptic devices connected in a grid like configuration similar to the organization of the biological brain. Implementing Hebbian learning with phase change memory cells, the synaptic grid was able to store presented patterns and recall missing patterns in an associative brain-like fashion. We found that the system is robust to device variations, and large variations in cell resistance states can be accommodated by increasing the number of training epochs. We illustrated the tradeoff between variation tolerance of the network and the overall energy consumption, and found that energy consumption is decreased significantly for lower variation tolerance. PMID:25100936

  15. Resistive Switching Memory Devices Based on Proteins.

    PubMed

    Wang, Hong; Meng, Fanben; Zhu, Bowen; Leow, Wan Ru; Liu, Yaqing; Chen, Xiaodong

    2015-12-09

    Resistive switching memory constitutes a prospective candidate for next-generation data storage devices. Meanwhile, naturally occurring biomaterials are promising building blocks for a new generation of environmentally friendly, biocompatible, and biodegradable electronic devices. Recent progress in using proteins to construct resistive switching memory devices is highlighted. The protein materials selection, device engineering, and mechanism of such protein-based resistive switching memory are discussed in detail. Finally, the critical challenges associated with protein-based resistive switching memory devices are presented, as well as insights into the future development of resistive switching memory based on natural biomaterials.

  16. Ferroelectric polymer thin films for solid-state non-volatile random access memory applications

    NASA Astrophysics Data System (ADS)

    Kaza, Swaroop

    Electronic polymers offer significant advantages towards ubiquitous computing due to their low-cost, flexibility and benign fabrication conditions. In this research, ferroelectric polymers were investigated for usage in non-volatile memory applications. The work is focused on the fabrication and ferroelectricity of Polyvinylidene-trifluoroethylene and Polyamide-11 (Nylon-11) thin films. Polyvinylidene fluoride (PVDF) and its copolymers were the first class of ferroelectric polymers discovered. Although the processes and properties of PVDF and copolymers have been extensively studied, most of the reports have been on polymers in the bulk form. This work focuses on thin films of PVDF-TrFE (75:25) copolymer fabricated by solution spin-casting. Remnant polarization, Pr, of the thin films was measured to be 6 muC/cm 2 with a coercive field, Ec, of 60 MV/m. The thin film properties are highly dependent on the temperature of crystallization and is attributed to the amount of all-trans beta-phase and crystallinity. Fatigue, defined as polarization loss with repeated switching, was studied and a model based on space charge formation was proposed as the fatigue mechanism. Space charge formation was proposed to be caused by electrochemical reaction of ions (F-) at electrodes and accumulations of detrapped ions at grain boundaries. Incorporating a F- scavenger and forming small crystallites was both observed to decrease fatigue. Nylon-11 and other odd-nylons are the only other class of polymers that have been reported to exhibit ferroelectric D-E hysteresis. The published work has almost exclusively been reported on melt-quenched and cold-drawn bulk polymers and consequently there is no literature on ferroelectricity in thin film odd-nylons. The present work developed a process for the fabrication of ferroelectric thin films of nylon-11 by spin-casting. Among the solvents tested, only a solution with m-cresol was observed to result in ferroelectricity in spun films and could

  17. Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

    NASA Astrophysics Data System (ADS)

    Sargentis, Ch.; Giannakopoulos, K.; Travlos, A.; Tsamakis, D.

    2007-04-01

    Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO 2 layer and are then fully covered by a HfO 2 layer. The HfO 2 is a high- k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance-voltage and conductance-voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.

  18. A radiation hardened nonvolatile MNOS RAM

    NASA Astrophysics Data System (ADS)

    Wrobel, T. F.; Dodson, W. H.; Hash, G. L.; Jones, R. V.; Nasby, R. D.; Olson, R. J.

    1983-12-01

    A radiation hardened nonvolatile MNOS RAM (SA2998) is being developed at Sandia National Laboratories. The memory organization is 128 x 8 bits and utilizes two p-channel MNOS transistors per memory cell. The peripheral circuitry is constructed with CMOS metal gate and is processed with standard Sandia rad-hard processing techniques. The device requires +10 V and +25 V for operation. The devices have memory retention after a dose-rate exposure of 1E12 rad(Si)/s, are functional after total dose exposure of 1E6 rad(Si), and are dose-rate upset resistant to levels of 7E8 rad(Si)/s.

  19. Investigating the bistability characteristics of GaN/AlN resonant tunneling diodes for ultrafast nonvolatile memory

    NASA Astrophysics Data System (ADS)

    Nagase, Masanori; Takahashi, Tokio; Shimizu, Mitsuaki

    2015-03-01

    The bistability characteristics of GaN/AlN resonant tunneling diodes (RTDs) grown on a sapphire substrate by metalorganic vapor phase epitaxy (MOVPE) were investigated to better understand their physical origin and explore their use in nonvolatile memories. The bistability current-voltage (I-V) characteristics of GaN/AlN RTDs, which were due to intersubband transitions and electron accumulation in the quantum well, were clearly observed over a wide temperature range between 50 and 300 K. However, the I-V characteristics sometimes degraded at temperatures above 250 K. Complex staircase structures were observed in the voltage region showing a negative differential resistance in the I-V curve, and the forward current increased or decreased rapidly as the forward-bias voltage increased. Repeated measurements of the I-V characteristics over the wide temperature range between 50 and 300 K revealed that the bistability characteristics of GaN/AlN RTDs degraded owing to the leakage of electrons accumulating in the quantum well through a deep level in the AlN barrier associated with crystal defects such as dislocations and impurities. Therefore, reduction in crystal defect and impurity densities in the AlN barrier, and a careful design that considers deep levels are important for realizing realize ultrafast nonvolatile memories based on the bistability characteristics of GaN/AlN RTDs.

  20. Characterization of Au/PbTi0.5Fe0.5O3/Si structure for possible multiferroic based non-volatile memory applications

    NASA Astrophysics Data System (ADS)

    Nawaz, S.; Roy, S.; Tulapurkar, A. A.; Palkar, V. R.

    2017-03-01

    Magnetoelectric multiferroic PbTi0.5Fe0.5O3 films are deposited on a ⟨100⟩ conducting p-Si substrate without any buffer layer by using pulsed laser deposition and characterized for possible non-volatile memory applications. Their crystalline structure and surface morphology were characterized by using x-ray diffraction and AFM techniques. HRTEM was employed to determine the film-substrate interface. The electronic structure of the film was investigated by XPS, and no signature of metal was found for all the elements. The chemical shift of the Ti 2p XPS peak is attributed to the replacement of Ti with Fe in the PbTiO3 matrix. Piezoelectric force microscopy (PFM) results indicate the 180° phase shift of ferroelectric polarization. The upward self-polarization phenomenon is also observed in the PFM study. Magnetic and magneto-electric coupling measurements were carried out to confirm the magnetic nature and electro-magnetic coupling characteristics. C-V measurements exhibit clock-wise hysteresis loops with a maximum memory window of 1.2 V and a sweep voltage of ±7 V. This study could influence the fabrication of silicon compatible multiple memory device structures.

  1. Enhancement of programming speed on gate-all-around poly-silicon nanowire nonvolatile memory using self-aligned NiSi Schottky barrier source/drain

    NASA Astrophysics Data System (ADS)

    Ho, Ching-Yuan; Chang, Yaw-Jen; Chiou, Y. L.

    2013-08-01

    The programming characteristics of gate-all-around silicon-oxide-nitride-oxide silicon (SONOS) nonvolatile memories are presented using NiSi/poly-Si nanowires (SiNW) Schottky barrier (SB) heterojunctions. The non-uniform thermal stress distribution on SiNW channels due to joule heating affected the carrier transport behavior. Under a high drain voltage, impact ionization was found as a large lateral field enhances carrier velocity. As gate voltage (Vg) increased, the difference in the drain current within a range of various temperature conditions can be mitigated because a high gate field lowers the SB height of a NiSi source/SiNW/NiSi drain junction to ensure efficient hot-carrier generation. By applying the Fowler-Nordheim programming voltage to the SONOS nanowire memory, the SB height (Φn = 0.34 eV) could be reduced by image force; thus, hot electrons could be injected from SB source/drain electrodes into the SiN storage node. To compare both SiNW and Si nanocrystal SONOS devices, the SB SiNW SONOS device was characterized experimentally to propose a wider threshold-voltage window, exhibiting efficient programming characteristics.

  2. DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology. [Dual Injector Floating-gate MOS

    NASA Technical Reports Server (NTRS)

    Gosney, W. M.

    1977-01-01

    Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

  3. Charge-trap non-volatile memories fabricated by laser-enabled low-thermal budget processes

    NASA Astrophysics Data System (ADS)

    Huang, Wen-Hsien; Shieh, Jia-Min; Pan, Fu-Ming; Yang, Chih-Chao; Shen, Chang-Hong; Wang, Hsing-Hsiang; Hsieh, Tung-Ying; Wu, Ssu-Yu; Wu, Meng-Chyi

    2015-11-01

    We fabricated charge-trap non-volatile memories (NVMs) using low thermal budget processes, including laser-crystallization of poly-Si thin film, chemical vapor deposition deposition of a stacked memory layer, and far-infrared-laser dopant activation. The thin poly-Si channel has a low defect-density at the interface with the bulk, resulting in a steep subthreshold swing for the NVM transistors. The introduction of the stacked SiO2/AlOxNy tunnel layer and the SiNx charge-trap layer with a gradient bandgap leads to reliable retention and endurance at low voltage for the NVMs. The low thermal budget processes are desirable for the integration of the nano-scaled NVMs into system on panels.

  4. Germanium sulfide-based solid electrolytes for non-volatile memory

    NASA Astrophysics Data System (ADS)

    Balakrishnan, Muralikrishnan

    Programmable Metallization Cell (PMC) technology involves the storage of data as reduced metal ions in a solid electrolyte. Earlier work on Selenide-based (Ag-Ge-Se) PMC devices requires relatively low back-end-of-line processing (BEOL) since the electrolyte may undergo undesirable changes at process temperatures in excess of 200°C. This dissertation is focused on Sulfide-based (Ag/Cu-Ge-S) solid electrolytes which have better temperature stability and the PMC technology based on these materials is compatible with most BEOL process in CMOS Integrated Circuits. The devices fabricated using Ag-Ge-S and Cu-Ge-S solid electrolytes were tested after annealing at 300°C and 430°C. Extensive material analysis was performed on both the systems in an effort to understand the behavior of the devices at elevated temperatures. Electrical characterization testing involved standard memory characterization techniques such as quasi-static measurements tests, retention tests, speed tests, elevated temperature operation tests and endurance tests. The Ag-Ge-S PMC devices were made with different compositions to find out the optimum composition which would ensure reliable operation even after the high temperature anneal. The Sulfide-based PMC devices were also tested for reconfigurable logic applications with special test structures that would demonstrate the low resistance connections that can be achieved by programming the PMC elements using higher currents. Optimum composition of the starting glass was found from the material and data analysis, to ensure reliable operation of the Sulfide-based PMC devices with no degradation in the electrical characteristics even after the typical BEOL anneal.

  5. NVL-C: Static Analysis Techniques for Efficient, Correct Programming of Non-Volatile Main Memory Systems

    SciTech Connect

    Lee, Seyong; Vetter, Jeffrey S

    2016-01-01

    Computer architecture experts expect that non-volatile memory (NVM) hierarchies will play a more significant role in future systems including mobile, enterprise, and HPC architectures. With this expectation in mind, we present NVL-C: a novel programming system that facilitates the efficient and correct programming of NVM main memory systems. The NVL-C programming abstraction extends C with a small set of intuitive language features that target NVM main memory, and can be combined directly with traditional C memory model features for DRAM. We have designed these new features to enable compiler analyses and run-time checks that can improve performance and guard against a number of subtle programming errors, which, when left uncorrected, can corrupt NVM-stored data. Moreover, to enable recovery of data across application or system failures, these NVL-C features include a flexible directive for specifying NVM transactions. So that our implementation might be extended to other compiler front ends and languages, the majority of our compiler analyses are implemented in an extended version of LLVM's intermediate representation (LLVM IR). We evaluate NVL-C on a number of applications to show its flexibility, performance, and correctness.

  6. Tuning the Electrical Memory Behavior from Nonvolatile to Volatile in Functional Copolyimides Bearing Varied Fluorene and Pyrene Moieties

    NASA Astrophysics Data System (ADS)

    Jia, Nanfang; Qi, Shengli; Tian, Guofeng; Wang, Xiaodong; Wu, Dezhen

    2017-04-01

    For producing polymer based electronics with good memory behavior, a series of functional copolyimides were designed and synthesized in this work by copolymerizing 3,3',4,4'-diphenylsulfonetetracarboxylic dianhydride (DSDA) with (9,9'-bis(4-aminophenyl)fluorene) (BAPF) and N, N-bis(4-aminophenyl) aminopyrene (DAPAP) diamines. The synthesized copolyimides DSDA/(DAPAP/BAPF) were denoted as coPI-DAPAP x ( x = 100, 50, 20, 10, 5, 1, 0), where x% represents the molar fraction of the DAPAP unit in the diamines. Characterization results indicate that the coPI-DAPAP x exhibits tunable electrical switching behaviors from write once read many times (WORM, nonvolatile, coPI-DAPAP100, coPI-DAPAP50, coPI-DAPAP20, coPI-DAPAP10) to the static random access memory (SRAM, volatile, coPI-DAPAP5, coPI-DAPAP1) with the variation of the DAPAP content. Optical and electrochemical characterization show gradually decreasing highest occupied molecular orbital levels and enlarged energy gap with the decrease of the DAPAP moiety, suggesting decreasing charge-transfer effect in the copolyimides, which can account for the observed WORM-SRAM memory conversion. Meanwhile, the charge transfer process was elucidated by quantum chemical calculation at B3LYP/6-31G(d) theory level. This work shows the effect of electron donor content on the memory behavior of polymer electronic materials.

  7. Tuning the Electrical Memory Behavior from Nonvolatile to Volatile in Functional Copolyimides Bearing Varied Fluorene and Pyrene Moieties

    NASA Astrophysics Data System (ADS)

    Jia, Nanfang; Qi, Shengli; Tian, Guofeng; Wang, Xiaodong; Wu, Dezhen

    2016-12-01

    For producing polymer based electronics with good memory behavior, a series of functional copolyimides were designed and synthesized in this work by copolymerizing 3,3',4,4'-diphenylsulfonetetracarboxylic dianhydride (DSDA) with (9,9'-bis(4-aminophenyl)fluorene) (BAPF) and N,N-bis(4-aminophenyl) aminopyrene (DAPAP) diamines. The synthesized copolyimides DSDA/(DAPAP/BAPF) were denoted as coPI-DAPAPx (x = 100, 50, 20, 10, 5, 1, 0), where x% represents the molar fraction of the DAPAP unit in the diamines. Characterization results indicate that the coPI-DAPAPx exhibits tunable electrical switching behaviors from write once read many times (WORM, nonvolatile, coPI-DAPAP100, coPI-DAPAP50, coPI-DAPAP20, coPI-DAPAP10) to the static random access memory (SRAM, volatile, coPI-DAPAP5, coPI-DAPAP1) with the variation of the DAPAP content. Optical and electrochemical characterization show gradually decreasing highest occupied molecular orbital levels and enlarged energy gap with the decrease of the DAPAP moiety, suggesting decreasing charge-transfer effect in the copolyimides, which can account for the observed WORM-SRAM memory conversion. Meanwhile, the charge transfer process was elucidated by quantum chemical calculation at B3LYP/6-31G(d) theory level. This work shows the effect of electron donor content on the memory behavior of polymer electronic materials.

  8. Radiation-hardened nonvolatile MNOS RAM

    SciTech Connect

    Wrobel, T.F.; Dodson, W.H.; Hash, G.L.; Jones, R.V.; Nasby, R.D.; Olson, R.J.

    1983-01-01

    A radiation hardened nonvolatile MNOS RAM is being developed at Sandia National Laboratories. The memory organization is 128 x 8 bits and utilizes two p-channel MNOS transistors per memory cell. The peripheral circuitry is constructed with CMOS metal gate and is processed with standard Sandia rad-hard processing techniques. The devices have memory retention after a dose-rate exposure of 1E12 rad(Si)/s, are functional after total dose exposure of 1E6 rad(Si), and are dose-rate upset resistant to levels of 7E8 rad(Si)/s.

  9. Polymer ferroelectric field-effect memory device with SnO channel layer exhibits record hole mobility

    NASA Astrophysics Data System (ADS)

    Caraveo-Frescas, J. A.; Khan, M. A.; Alshareef, H. N.

    2014-06-01

    Here we report for the first time a hybrid p-channel polymer ferroelectric field-effect transistor memory device with record mobility. The memory device, fabricated at 200°C on both plastic polyimide and glass substrates, uses ferroelectric polymer P(VDF-TrFE) as the gate dielectric and transparent p-type oxide (SnO) as the active channel layer. A record mobility of 3.3 cm2V-1s-1, large memory window (~16 V), low read voltages (~-1 V), and excellent retention characteristics up to 5000 sec have been achieved. The mobility achieved in our devices is over 10 times higher than previously reported polymer ferroelectric field-effect transistor memory with p-type channel. This demonstration opens the door for the development of non-volatile memory devices based on dual channel for emerging transparent and flexible electronic devices.

  10. Photo-electron double regulated resistive switching memory behaviors of Ag/CuWO4/FTO device

    NASA Astrophysics Data System (ADS)

    Sun, B.; Jia, X. J.; Wu, J. H.; Chen, P.

    2015-12-01

    In this work, the CuWO4 film based resistive switching memory capacitors were fabricated with hydrothermal and spin-coating approaches. The device exhibits excellent photo-electron double controlled resistive switching memory characteristics with OFF/ON resistance ratio of ~103. It is believed that the interface of CuWO4 and FTO is responsible for such a switching behavior and it can be described by the Schottky-like barriers model. This study is useful for exploring the multifunctional materials and their applications in photo-electron double controlled nonvolatile memory devices.

  11. Resistive Switching of Individual Dislocations in Insulating Perovskites -- A Potential Route Towards Nanoscale Non-Volatile Memories.

    NASA Astrophysics Data System (ADS)

    Szot, Krzystof; Speier, Wolfgang; Bihlmayer, Gustav; Waser, Rainer

    2006-03-01

    dislocations. Switching in our case corresponds then to an electrochemical ``closing'' or ``opening'' of the single dislocation in the uppermost portion of the network. Our results show that the switching behaviour in single-crystalline SrTiO3 is an inherent property of the material and can be easily activated by external stimuli. Due to the availability of dislocation densities up to 10^12 cm-2 in single crystals and thin film, one can even envisage to approach the Tbit regime, as long as the dislocations can be successfully arranged into registered superstructures. In summary, evidence is given that the electrical conductance of individual dislocations in a prototype perovskite, SrTiO3, can be switched between a low and a high conducting state by the application of an electrical field. We demonstrate on the basis of ab initio calculations and measurements with a scanning probe microscope SPM that the modulation of the electrical properties is related to the induced change in oxygen stoichiometry and the self-doping capability with a local insulator- metal transition along the core of the dislocations. A model is presented based on a three-dimensional network of such a filamentary structure to analyze the bi-stable resistive switching in the macroscopic metal-insulator-metal (MIM) structure. Our results show that electrically addressing individual dislocations in single crystals as well as epitaxial thin films provides a dynamic range for switching between low and high conducting states which covers several orders of magnitude in resistance and can be of technological interest for the application in Tbit non-volatile memory devices..

  12. Organic bistable memory devices based on MoO3 nanoparticle embedded Alq3 structures

    NASA Astrophysics Data System (ADS)

    Abhijith, T.; Kumar, T. V. Arun; Reddy, V. S.

    2017-03-01

    Organic bistable memory devices were fabricated by embedding a thin layer of molybdenum trioxide (MoO3) between two tris-(8-hydroxyquinoline)aluminum (Alq3) layers. The device exhibited excellent switching characteristics with an ON/OFF current ratio of 1.15 × 103 at a read voltage of 1 V. The device showed repeatable write–erase capability and good stability in both the conductance states. These conductance states are non-volatile in nature and can be obtained by applying appropriate voltage pulses. The effect of MoO3 layer thickness and its location in the Alq3 matrix on characteristics of the memory device was investigated. The field emission scanning electron microscopy (FE-SEM) images of the MoO3 layer revealed the presence of isolated nanoparticles. Based on the experimental results, a mechanism has been proposed for explaining the conductance switching of fabricated devices.

  13. Organic bistable memory devices based on MoO3 nanoparticle embedded Alq3 structures.

    PubMed

    Abhijith, T; Kumar, T V Arun; Reddy, V S

    2017-03-03

    Organic bistable memory devices were fabricated by embedding a thin layer of molybdenum trioxide (MoO3) between two tris-(8-hydroxyquinoline)aluminum (Alq3) layers. The device exhibited excellent switching characteristics with an ON/OFF current ratio of 1.15 × 10(3) at a read voltage of 1 V. The device showed repeatable write-erase capability and good stability in both the conductance states. These conductance states are non-volatile in nature and can be obtained by applying appropriate voltage pulses. The effect of MoO3 layer thickness and its location in the Alq3 matrix on characteristics of the memory device was investigated. The field emission scanning electron microscopy (FE-SEM) images of the MoO3 layer revealed the presence of isolated nanoparticles. Based on the experimental results, a mechanism has been proposed for explaining the conductance switching of fabricated devices.

  14. Mechanism of resistive switching in Cu/AlOx/W nonvolatile memory structures

    NASA Astrophysics Data System (ADS)

    Sleiman, A.; Sayers, P. W.; Mabrook, M. F.

    2013-04-01

    The mechanism for resistive switching in aluminum oxide (AlOx) based electrochemical metallization memory cells is presented. Copper/AlOx/tungsten (Cu/AlOx/W) cells show reproducible resistive switching with an ON/OFF ratio of about 5 × 102 at a reading voltage of 0.1 V and reliable retention characteristics. Resistive switching occurs due to the formation and rupture of a Cu filament between the active electrode (Cu) and the counter electrode (W). The conduction of the devices was explained through back-to-back Schottky contacts in the OFF state, while it exhibits ohmic behavior in the ON state. Thermionic emission model was used to calculate the barrier heights of the Schottky contacts. The rupture of the Cu filament proved to occur at the weakest point of the filament inside the AlOx. Using Ohms Law, the slope of the linear I-V characteristics in the ON state was used to extract the Cu filament resistance and its diameter was estimated to be between 6 and 23 nm.

  15. Shape memory polymer medical device

    DOEpatents

    Maitland, Duncan; Benett, William J.; Bearinger, Jane P.; Wilson, Thomas S.; Small, IV, Ward; Schumann, Daniel L.; Jensen, Wayne A.; Ortega, Jason M.; Marion, III, John E.; Loge, Jeffrey M.

    2010-06-29

    A system for removing matter from a conduit. The system includes the steps of passing a transport vehicle and a shape memory polymer material through the conduit, transmitting energy to the shape memory polymer material for moving the shape memory polymer material from a first shape to a second and different shape, and withdrawing the transport vehicle and the shape memory polymer material through the conduit carrying the matter.

  16. Metal ion formed conductive filaments by redox process induced nonvolatile resistive switching memories in MoS2 film

    NASA Astrophysics Data System (ADS)

    Xia, Yudong; Sun, Bai; Wang, Hongyan; Zhou, Guangdong; Kan, Xiang; Zhang, Yong; Zhao, Yong

    2017-12-01

    In this work, the resistive switching mechanism of metal/MoS2/Ti/Si devices with different metal acts top electrode materials have been investigated. The device represents an outstanding memory behavior with larger storage window when using Ag acts top electrode. This work reveals that Ag filaments can be easily formed by redox process in MoS2 film.

  17. Size-dependent metal-insulator transition in platinum-dispersed silicon dioxide thin film: A candidate for future non-volatile memory

    NASA Astrophysics Data System (ADS)

    Chen, Albert B. K.

    Non-volatile random access memories (NVRAM) are promising data storage and processing devices. Various NVRAM, such as FeRAM and MRAM, have been studied in the past. But resistance switching random access memory (RRAM) has demonstrated the most potential for replacing flash memory in use today. In this dissertation, a novel RRAM material design that relies upon an electronic transition, rather than a phase change (as in chalcogenide Ovonic RRAM) or a structural change (such in oxide and halide filamentary RRAM), is investigated. Since the design is not limited to a single material but applicable to general combinations of metals and insulators, the goal of this study is to use a model material to delineate the intrinsic features of the electronic metal/insulator transition in random systems and to demonstrate their relevance to reliable memory storage and retrieval. We fabricated amorphous SiO2 thin films embedded with randomly dispersed Pt atoms. Macroscopically, this random material exhibits a percolation transition in electric conductivity similar to the one found in various insulator/metal granular materials. However, at Pt concentrations well below the bulk percolation limit, a distinct insulator to metal transition occurs in the thickness direction as the film thickness falls below electron's "diffusion" distance, which is the tunneling distance at 0K. The thickness-triggered metal- to-insulator transition (MIT) can be similarly triggered by other conditions: (a) a changing Pt concentration (a concentration-triggered MIT), (b) a changing voltage/polarity (voltage-triggered MIT), and (c) an UV irradiation (photon-triggered MIT). The resistance switching characteristics of this random material were further investigated in several device configurations under various test conditions. These include: materials for the top and bottom electrodes, fast pulsing, impedance spectroscopy, static stressing, retention, fatigue and temperature from 10K to 448K. The SiO2-Pt

  18. Projected phase-change memory devices

    NASA Astrophysics Data System (ADS)

    Koelmans, Wabe W.; Sebastian, Abu; Jonnalagadda, Vara Prasad; Krebs, Daniel; Dellmann, Laurent; Eleftheriou, Evangelos

    2015-09-01

    Nanoscale memory devices, whose resistance depends on the history of the electric signals applied, could become critical building blocks in new computing paradigms, such as brain-inspired computing and memcomputing. However, there are key challenges to overcome, such as the high programming power required, noise and resistance drift. Here, to address these, we present the concept of a projected memory device, whose distinguishing feature is that the physical mechanism of resistance storage is decoupled from the information-retrieval process. We designed and fabricated projected memory devices based on the phase-change storage mechanism and convincingly demonstrate the concept through detailed experimentation, supported by extensive modelling and finite-element simulations. The projected memory devices exhibit remarkably low drift and excellent noise performance. We also demonstrate active control and customization of the programming characteristics of the device that reliably realize a multitude of resistance states.

  19. Projected phase-change memory devices

    PubMed Central

    Koelmans, Wabe W.; Sebastian, Abu; Jonnalagadda, Vara Prasad; Krebs, Daniel; Dellmann, Laurent; Eleftheriou, Evangelos

    2015-01-01

    Nanoscale memory devices, whose resistance depends on the history of the electric signals applied, could become critical building blocks in new computing paradigms, such as brain-inspired computing and memcomputing. However, there are key challenges to overcome, such as the high programming power required, noise and resistance drift. Here, to address these, we present the concept of a projected memory device, whose distinguishing feature is that the physical mechanism of resistance storage is decoupled from the information-retrieval process. We designed and fabricated projected memory devices based on the phase-change storage mechanism and convincingly demonstrate the concept through detailed experimentation, supported by extensive modelling and finite-element simulations. The projected memory devices exhibit remarkably low drift and excellent noise performance. We also demonstrate active control and customization of the programming characteristics of the device that reliably realize a multitude of resistance states. PMID:26333363

  20. Projected phase-change memory devices.

    PubMed

    Koelmans, Wabe W; Sebastian, Abu; Jonnalagadda, Vara Prasad; Krebs, Daniel; Dellmann, Laurent; Eleftheriou, Evangelos

    2015-09-03

    Nanoscale memory devices, whose resistance depends on the history of the electric signals applied, could become critical building blocks in new computing paradigms, such as brain-inspired computing and memcomputing. However, there are key challenges to overcome, such as the high programming power required, noise and resistance drift. Here, to address these, we present the concept of a projected memory device, whose distinguishing feature is that the physical mechanism of resistance storage is decoupled from the information-retrieval process. We designed and fabricated projected memory devices based on the phase-change storage mechanism and convincingly demonstrate the concept through detailed experimentation, supported by extensive modelling and finite-element simulations. The projected memory devices exhibit remarkably low drift and excellent noise performance. We also demonstrate active control and customization of the programming characteristics of the device that reliably realize a multitude of resistance states.

  1. Nonvolatile modulation of electronic structure and correlative magnetism of L10-FePt films using significant strain induced by shape memory substrates.

    PubMed

    Feng, Chun; Zhao, Jiancheng; Yang, Feng; Gong, Kui; Hao, Shijie; Cao, Yi; Hu, Chen; Zhang, Jingyan; Wang, Zhongqiang; Chen, Lei; Li, Sirui; Sun, Li; Cui, Lishan; Yu, Guanghua

    2016-02-01

    Tuning the lattice strain (εL) is a novel approach to manipulate the magnetic, electronic, and transport properties of spintronic materials. Achievable εL in thin film samples induced by traditional ferroelectric or flexible substrates is usually volatile and well below 1%. Such limits in the tuning capability cannot meet the requirements for nonvolatile applications of spintronic materials. This study answers to the challenge of introducing significant amount of elastic strain in deposited thin films so that noticeable tuning of the spintronic characteristics can be realized. Based on subtle elastic strain engineering of depositing L10-FePt films on pre-stretched NiTi(Nb) shape memory alloy substrates, steerable and nonvolatile lattice strain up to 2.18% has been achieved in the L10-FePt films by thermally controlling the shape memory effect of the substrates. Introduced strains at this level significantly modify the electronic density of state, orbital overlap, and spin-orbit coupling (SOC) strength in the FePt film, leading to nonvolatile modulation of magnetic anisotropy and magnetization reversal characteristics. This finding not only opens an efficient avenue for the nonvolatile tuning of SOC based magnetism and spintronic effects, but also helps to clarify the physical nature of pure strain effect.

  2. Nonvolatile modulation of electronic structure and correlative magnetism of L10-FePt films using significant strain induced by shape memory substrates

    NASA Astrophysics Data System (ADS)

    Feng, Chun; Zhao, Jiancheng; Yang, Feng; Gong, Kui; Hao, Shijie; Cao, Yi; Hu, Chen; Zhang, Jingyan; Wang, Zhongqiang; Chen, Lei; Li, Sirui; Sun, Li; Cui, Lishan; Yu, Guanghua

    2016-02-01

    Tuning the lattice strain (εL) is a novel approach to manipulate the magnetic, electronic, and transport properties of spintronic materials. Achievable εL in thin film samples induced by traditional ferroelectric or flexible substrates is usually volatile and well below 1%. Such limits in the tuning capability cannot meet the requirements for nonvolatile applications of spintronic materials. This study answers to the challenge of introducing significant amount of elastic strain in deposited thin films so that noticeable tuning of the spintronic characteristics can be realized. Based on subtle elastic strain engineering of depositing L10-FePt films on pre-stretched NiTi(Nb) shape memory alloy substrates, steerable and nonvolatile lattice strain up to 2.18% has been achieved in the L10-FePt films by thermally controlling the shape memory effect of the substrates. Introduced strains at this level significantly modify the electronic density of state, orbital overlap, and spin-orbit coupling (SOC) strength in the FePt film, leading to nonvolatile modulation of magnetic anisotropy and magnetization reversal characteristics. This finding not only opens an efficient avenue for the nonvolatile tuning of SOC based magnetism and spintronic effects, but also helps to clarify the physical nature of pure strain effect.

  3. Nonvolatile modulation of electronic structure and correlative magnetism of L10-FePt films using significant strain induced by shape memory substrates

    PubMed Central

    Feng, Chun; Zhao, Jiancheng; Yang, Feng; Gong, Kui; Hao, Shijie; Cao, Yi; Hu, Chen; Zhang, Jingyan; Wang, Zhongqiang; Chen, Lei; Li, Sirui; Sun, Li; Cui, Lishan; Yu, Guanghua

    2016-01-01

    Tuning the lattice strain (εL) is a novel approach to manipulate the magnetic, electronic, and transport properties of spintronic materials. Achievable εL in thin film samples induced by traditional ferroelectric or flexible substrates is usually volatile and well below 1%. Such limits in the tuning capability cannot meet the requirements for nonvolatile applications of spintronic materials. This study answers to the challenge of introducing significant amount of elastic strain in deposited thin films so that noticeable tuning of the spintronic characteristics can be realized. Based on subtle elastic strain engineering of depositing L10-FePt films on pre-stretched NiTi(Nb) shape memory alloy substrates, steerable and nonvolatile lattice strain up to 2.18% has been achieved in the L10-FePt films by thermally controlling the shape memory effect of the substrates. Introduced strains at this level significantly modify the electronic density of state, orbital overlap, and spin-orbit coupling (SOC) strength in the FePt film, leading to nonvolatile modulation of magnetic anisotropy and magnetization reversal characteristics. This finding not only opens an efficient avenue for the nonvolatile tuning of SOC based magnetism and spintronic effects, but also helps to clarify the physical nature of pure strain effect. PMID:26830325

  4. Electronic device aspects of neural network memories

    NASA Technical Reports Server (NTRS)

    Lambe, J.; Moopenn, A.; Thakoor, A. P.

    1985-01-01

    The basic issues related to the electronic implementation of the neural network model (NNM) for content addressable memories are examined. A brief introduction to the principles of the NNM is followed by an analysis of the information storage of the neural network in the form of a binary connection matrix and the recall capability of such matrix memories based on a hardware simulation study. In addition, materials and device architecture issues involved in the future realization of such networks in VLSI-compatible ultrahigh-density memories are considered. A possible space application of such devices would be in the area of large-scale information storage without mechanical devices.

  5. Electronic device aspects of neural network memories

    NASA Technical Reports Server (NTRS)

    Lambe, J.; Moopenn, A.; Thakoor, A. P.

    1985-01-01

    The basic issues related to the electronic implementation of the neural network model (NNM) for content addressable memories are examined. A brief introduction to the principles of the NNM is followed by an analysis of the information storage of the neural network in the form of a binary connection matrix and the recall capability of such matrix memories based on a hardware simulation study. In addition, materials and device architecture issues involved in the future realization of such networks in VLSI-compatible ultrahigh-density memories are considered. A possible space application of such devices would be in the area of large-scale information storage without mechanical devices.

  6. Bipolar resistive switching characteristics in tantalum nitride-based resistive random access memory devices

    SciTech Connect

    Kim, Myung Ju; Jeon, Dong Su; Park, Ju Hyun; Kim, Tae Geun

    2015-05-18

    This paper reports the bipolar resistive switching characteristics of TaN{sub x}-based resistive random access memory (ReRAM). The conduction mechanism is explained by formation and rupture of conductive filaments caused by migration of nitrogen ions and vacancies; this mechanism is in good agreement with either Ohmic conduction or the Poole-Frenkel emission model. The devices exhibit that the reset voltage varies from −0.82 V to −0.62 V, whereas the set voltage ranges from 1.01 V to 1.30 V for 120 DC sweep cycles. In terms of reliability, the devices exhibit good retention (>10{sup 5 }s) and pulse-switching endurance (>10{sup 6} cycles) properties. These results indicate that TaN{sub x}-based ReRAM devices have a potential for future nonvolatile memory devices.

  7. Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

    NASA Astrophysics Data System (ADS)

    Che, Yongli; Zhang, Yating; Cao, Xiaolong; Song, Xiaoxian; Cao, Mingxuan; Dai, Haitao; Yang, Junbo; Zhang, Guizhong; Yao, Jianquan

    2016-07-01

    Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔVth ˜ 15 V) and a long retention time (>105 s). The magnitude of ΔVth depended on both P/E voltages and the bias voltage (VDS): ΔVth was a cubic function to VP/E and linearly depended on VDS. Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.

  8. Membraneless Gas-Separation Microfluidic Paper-Based Analytical Devices for Direct Quantitation of Volatile and Nonvolatile Compounds.

    PubMed

    Phansi, Piyawan; Sumantakul, Saichon; Wongpakdee, Thinnapong; Fukana, Nutnaree; Ratanawimarnwong, Nuanlaor; Sitanurak, Jirayu; Nacapricha, Duangjai

    2016-09-06

    This work presents new chemical sensing devices called "membraneless gas-separation microfluidic paper-based analytical devices" (MBL-GS μPADs). MBL-GS μPADs were designed to make fabrication of the devices simple and user-friendly. MBL-GS μPADs offer direct quantitative analysis of volatile and nonvolatile compounds. Porous hydrophobic membrane is not needed for gas-separation, which makes fabrication of the device simple, rapid and low-cost. A MBL-GS μPAD consists of three layers: "donor layer", "spacer layer", and "acceptor layer". The donor and acceptor layers are made of filter paper with a printed pattern. The donor and acceptor layers are mounted together with a spacer layer in between. This spacer is a two-sided mounting tape, 0.8 mm thick, with a small disc cut out for the gas from the donor zone to diffuse to the acceptor zone. Photographic image of the color that is formed by the reagent in the acceptor layer is analyzed using the ImageJ program for quantitation. Proof of concept of the MBL-GS μPADs was demonstrated by analyzing standard solutions of ethanol, sulfide, and ammonium. Optimization of the MBL-GS μPADs was carried out for direct determination of ammonium in wastewaters and fertilizers to demonstrate the applicability of the system to real samples.

  9. Status and Prospects of ZnO-Based Resistive Switching Memory Devices.

    PubMed

    Simanjuntak, Firman Mangasa; Panda, Debashis; Wei, Kung-Hwa; Tseng, Tseung-Yuen

    2016-12-01

    In the advancement of the semiconductor device technology, ZnO could be a prospective alternative than the other metal oxides for its versatility and huge applications in different aspects. In this review, a thorough overview on ZnO for the application of resistive switching memory (RRAM) devices has been conducted. Various efforts that have been made to investigate and modulate the switching characteristics of ZnO-based switching memory devices are discussed. The use of ZnO layer in different structure, the different types of filament formation, and the different types of switching including complementary switching are reported. By considering the huge interest of transparent devices, this review gives the concrete overview of the present status and prospects of transparent RRAM devices based on ZnO. ZnO-based RRAM can be used for flexible memory devices, which is also covered here. Another challenge in ZnO-based RRAM is that the realization of ultra-thin and low power devices. Nevertheless, ZnO not only offers decent memory properties but also has a unique potential to be used as multifunctional nonvolatile memory devices. The impact of electrode materials, metal doping, stack structures, transparency, and flexibility on resistive switching properties and switching parameters of ZnO-based resistive switching memory devices are briefly compared. This review also covers the different nanostructured-based emerging resistive switching memory devices for low power scalable devices. It may give a valuable insight on developing ZnO-based RRAM and also should encourage researchers to overcome the challenges.

  10. Status and Prospects of ZnO-Based Resistive Switching Memory Devices

    NASA Astrophysics Data System (ADS)

    Simanjuntak, Firman Mangasa; Panda, Debashis; Wei, Kung-Hwa; Tseng, Tseung-Yuen

    2016-08-01

    In the advancement of the semiconductor device technology, ZnO could be a prospective alternative than the other metal oxides for its versatility and huge applications in different aspects. In this review, a thorough overview on ZnO for the application of resistive switching memory (RRAM) devices has been conducted. Various efforts that have been made to investigate and modulate the switching characteristics of ZnO-based switching memory devices are discussed. The use of ZnO layer in different structure, the different types of filament formation, and the different types of switching including complementary switching are reported. By considering the huge interest of transparent devices, this review gives the concrete overview of the present status and prospects of transparent RRAM devices based on ZnO. ZnO-based RRAM can be used for flexible memory devices, which is also covered here. Another challenge in ZnO-based RRAM is that the realization of ultra-thin and low power devices. Nevertheless, ZnO not only offers decent memory properties but also has a unique potential to be used as multifunctional nonvolatile memory devices. The impact of electrode materials, metal doping, stack structures, transparency, and flexibility on resistive switching properties and switching parameters of ZnO-based resistive switching memory devices are briefly compared. This review also covers the different nanostructured-based emerging resistive switching memory devices for low power scalable devices. It may give a valuable insight on developing ZnO-based RRAM and also should encourage researchers to overcome the challenges.

  11. System for simultaneously loading program to master computer memory devices and corresponding slave computer memory devices

    NASA Technical Reports Server (NTRS)

    Hall, William A. (Inventor)

    1993-01-01

    A bus programmable slave module card for use in a computer control system is disclosed which comprises a master computer and one or more slave computer modules interfacing by means of a bus. Each slave module includes its own microprocessor, memory, and control program for acting as a single loop controller. The slave card includes a plurality of memory means (S1, S2...) corresponding to a like plurality of memory devices (C1, C2...) in the master computer, for each slave memory means its own communication lines connectable through the bus with memory communication lines of an associated memory device in the master computer, and a one-way electronic door which is switchable to either a closed condition or a one-way open condition. With the door closed, communication lines between master computer memory (C1, C2...) and slave memory (S1, S2...) are blocked. In the one-way open condition invention, the memory communication lines or each slave memory means (S1, S2...) connect with the memory communication lines of its associated memory device (C1, C2...) in the master computer, and the memory devices (C1, C2...) of the master computer and slave card are electrically parallel such that information seen by the master's memory is also seen by the slave's memory. The slave card is also connectable to a switch for electronically removing the slave microprocessor from the system. With the master computer and the slave card in programming mode relationship, and the slave microprocessor electronically removed from the system, loading a program in the memory devices (C1, C2...) of the master accomplishes a parallel loading into the memory devices (S1, S2...) of the slave.

  12. Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

    SciTech Connect

    Che, Yongli; Zhang, Yating Song, Xiaoxian; Cao, Mingxuan; Zhang, Guizhong; Yao, Jianquan; Cao, Xiaolong; Dai, Haitao; Yang, Junbo

    2016-07-04

    Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV{sub th} ∼ 15 V) and a long retention time (>10{sup 5 }s). The magnitude of ΔV{sub th} depended on both P/E voltages and the bias voltage (V{sub DS}): ΔV{sub th} was a cubic function to V{sub P/E} and linearly depended on V{sub DS}. Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.

  13. Electrical Study of Trapped Charges in Copper-Doped Zinc Oxide Films by Scanning Probe Microscopy for Nonvolatile Memory Applications

    PubMed Central

    Su, Ting; Zhang, Haifeng

    2017-01-01

    Charge trapping properties of electrons and holes in copper-doped zinc oxide (ZnO:Cu) films have been studied by scanning probe microscopy. We investigated the surface potential dependence on the voltage and duration applied to the copper-doped ZnO films by Kelvin probe force microscopy. It is found that the Fermi Level of the 8 at.% Cu-doped ZnO films shifted by 0.53 eV comparing to undoped ZnO films. This shift indicates significant change in the electronic structure and energy balance in Cu-doped ZnO films. The Fermi Level (work function) of zinc oxide films can be tuned by Cu doping, which are important for developing this functional material. In addition, Kelvin probe force microscopy measurements demonstrate that the nature of contact at Pt-coated tip/ZnO:Cu interface is changed from Schottky contact to Ohmic contact by increasing sufficient amount of Cu ions. The charge trapping property of the ZnO films enhance greatly by Cu doping (~10 at.%). The improved stable bipolar charge trapping properties indicate that copper-doped ZnO films are promising for nonvolatile memory applications. PMID:28135335

  14. Cycling Endurance of SONOS Non-Volatile Memory Stacks Prepared with Nitrided SiO(2)/Si(100) Intefaces

    SciTech Connect

    Habermehl, S.; Nasby, R.D.; Rightley, M.J.

    1999-01-11

    The effects of nitrided SiO{sub 2}/Si(100) interfaces upon cycling endurance in silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory transistors are investigated. Analysis of MOSFET sub-threshold characteristics indicate cycling degradation to be a manifestation of interface state (D{sub it}) generation at the tunnel oxide/silicon interface. After 10{sup 6} write/erase cycles, SONOS film stacks prepared with nitrided tunnel oxides exhibit enhanced cycling endurance with {Delta}D{sub it}=3x10{sup 12} V{sup -1}cm{sup -2}, compared to {Delta}D{sub it}=2x10{sup 13} V{sup -l}cm{sup -2} for non-nitrided tunnel oxides. Additionally, if the capping oxide is formed by steam oxidation, rather than by deposition, SONOS stacks prepared with non-nitrided tunnel oxides exhibit endurance characteristics similar to stacks with nitrided tunnel oxides. From this observation it is concluded that latent nitridation of the tunnel oxidehilicon interface occurs during steam oxide cap formation.

  15. Dynamic manipulation of nanomechanical resonators in the high-amplitude regime and non-volatile mechanical memory operation.

    PubMed

    Bagheri, Mahmood; Poot, Menno; Li, Mo; Pernice, Wolfram P H; Tang, Hong X

    2011-10-23

    The ability to control mechanical motion with optical forces has made it possible to cool mechanical resonators to their quantum ground states. The same techniques can also be used to amplify rather than reduce the mechanical motion of such systems. Here, we study nanomechanical resonators that are slightly buckled and therefore have two stable configurations, denoted 'buckled up' and 'buckled down', when they are at rest. The motion of these resonators can be described by a double-well potential with a large central energy barrier between the two stable configurations. We demonstrate the high-amplitude operation of a buckled resonator coupled to an optical cavity by using a highly efficient process to generate enough phonons in the resonator to overcome the energy barrier in the double-well potential. This allows us to observe the first evidence for nanomechanical slow-down and a zero-frequency singularity predicted by theorists. We also demonstrate a non-volatile mechanical memory element in which bits are written and reset by using optomechanical backaction to direct the relaxation of a resonator in the high-amplitude regime to a specific stable configuration.

  16. Synthesis, characterization, and nonvolatile ternary memory behavior of a larger heteroacene with nine linearly fused rings and two different heteroatoms.

    PubMed

    Gu, Pei-Yang; Zhou, Feng; Gao, Junkuo; Li, Gang; Wang, Chengyuan; Xu, Qing-Feng; Zhang, Qichun; Lu, Jian-Mei

    2013-09-25

    To achieve ultrahigh density memory devices with the capacity of 3(n) or larger, organic materials with multilevel stable states are highly desirable. Here, we reported a novel larger stable heteroacene, 2,3,13,14-tetradecyloxy-5,11,16,22-tetraaza-6,10,17,21-tetrachloro-7,9,18,20-tetraoxa-8,19-dicyanoenneacene (CDPzN), which has two different types of heteroatoms (O and N) and nine linearly fused rings. The sandwich-structure memory devices based on CDPzN exhibited excellent ternary memory behaviors with high ON2/ON1/OFF current ratios of 10(6.3)/10(4.3)/1 and good stability for these three states.

  17. Ultraviolet to near infrared response of optically sensitive nonvolatile memories based on platinum nano-particles and high-k dielectrics on a silicon on insulator substrate

    NASA Astrophysics Data System (ADS)

    Mikhelashvili, V.; Meyler, B.; Shneider, Y.; Yofis, S.; Salzman, J.; Atiya, G.; Cohen-Hyams, T.; Ankonina, G.; Kaplan, W. D.; Lisiansky, M.; Roizin, Y.; Eisenstein, G.

    2013-02-01

    An optically triggered nonvolatile memory based on platinum nano-particles embedded within a SiO2 and HfO2 dielectric stack on a silicon on insulator (SOI) substrate is presented. The memory cell exhibits a very wide spectral response, from 220 nm to 950 nm; much wider than common photo-detectors fabricated on SOI. It offers several functionalities including a low programming voltage and wide hysteresis of the capacitance-voltage characteristics, an illumination and voltage sweep amplitude dependent hysteresis of the current-voltage characteristics, and plasmonic enhanced, efficient broad-band photo detection.

  18. A high performance triboelectric nanogenerator for self-powered non-volatile ferroelectric transistor memory

    NASA Astrophysics Data System (ADS)

    Fang, Huajing; Li, Qiang; He, Wenhui; Li, Jing; Xue, Qingtang; Xu, Chao; Zhang, Lijing; Ren, Tianling; Dong, Guifang; Chan, H. L. W.; Dai, Jiyan; Yan, Qingfeng

    2015-10-01

    We demonstrate an integrated module of self-powered ferroelectric transistor memory based on the combination of a ferroelectric FET and a triboelectric nanogenerator (TENG). The novel TENG was made of a self-assembled polystyrene nanosphere array and a poly(vinylidene fluoride) porous film. Owing to this unique structure, it exhibits an outstanding performance with an output voltage as high as 220 V per cycle. Meanwhile, the arch-shaped TENG is shown to be able to pole a bulk ferroelectric 0.65Pb(Mg1/3Nb2/3)O3-0.35PbTiO3 (PMN-PT) single crystal directly. Based on this effect, a bottom gate ferroelectric FET was fabricated using pentacene as the channel material and a PMN-PT single crystal as the gate insulator. Systematic tests illustrate that the ON/OFF current ratio of this transistor memory element is approximately 103. More importantly, we demonstrate the feasibility to switch the polarization state of this FET gate insulator, namely the stored information, by finger tapping the TENG with a designed circuit. These results may open up a novel application of TENGs in the field of self-powered memory systems.We demonstrate an integrated module of self-powered ferroelectric transistor memory based on the combination of a ferroelectric FET and a triboelectric nanogenerator (TENG). The novel TENG was made of a self-assembled polystyrene nanosphere array and a poly(vinylidene fluoride) porous film. Owing to this unique structure, it exhibits an outstanding performance with an output voltage as high as 220 V per cycle. Meanwhile, the arch-shaped TENG is shown to be able to pole a bulk ferroelectric 0.65Pb(Mg1/3Nb2/3)O3-0.35PbTiO3 (PMN-PT) single crystal directly. Based on this effect, a bottom gate ferroelectric FET was fabricated using pentacene as the channel material and a PMN-PT single crystal as the gate insulator. Systematic tests illustrate that the ON/OFF current ratio of this transistor memory element is approximately 103. More importantly, we demonstrate the

  19. Performance Measurement of a Multi-Level/Analog Ferroelectric Memory Device Design

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

    2007-01-01

    Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determinethe amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

  20. A non-volatile organic electrochemical device as a low-voltage artificial synapse for neuromorphic computing

    NASA Astrophysics Data System (ADS)

    van de Burgt, Yoeri; Lubberman, Ewout; Fuller, Elliot J.; Keene, Scott T.; Faria, Grégorio C.; Agarwal, Sapan; Marinella, Matthew J.; Alec Talin, A.; Salleo, Alberto

    2017-04-01

    The brain is capable of massively parallel information processing while consuming only ~1-100 fJ per synaptic event. Inspired by the efficiency of the brain, CMOS-based neural architectures and memristors are being developed for pattern recognition and machine learning. However, the volatility, design complexity and high supply voltages for CMOS architectures, and the stochastic and energy-costly switching of memristors complicate the path to achieve the interconnectivity, information density, and energy efficiency of the brain using either approach. Here we describe an electrochemical neuromorphic organic device (ENODe) operating with a fundamentally different mechanism from existing memristors. ENODe switches at low voltage and energy (<10 pJ for 103 μm2 devices), displays >500 distinct, non-volatile conductance states within a ~1 V range, and achieves high classification accuracy when implemented in neural network simulations. Plastic ENODes are also fabricated on flexible substrates enabling the integration of neuromorphic functionality in stretchable electronic systems. Mechanical flexibility makes ENODes compatible with three-dimensional architectures, opening a path towards extreme interconnectivity comparable to the human brain.

  1. A non-volatile organic electrochemical device as a low-voltage artificial synapse for neuromorphic computing

    DOE PAGES

    van de Burgt, Yoeri; Lubberman, Ewout; Fuller, Elliot J.; ...

    2017-02-20

    The brain is capable of massively parallel information processing while consuming only ~1- 100 fJ per synaptic event. Inspired by the efficiency of the brain, CMOS-based neural architectures and memristors are being developed for pattern recognition and machine learning. However, the volatility, design complexity and high supply voltages for CMOS architectures, and the stochastic and energy-costly switching of memristors complicate the path to achieve the interconnectivity, information density, and energy efficiency of the brain using either approach. Here we describe an electrochemical neuromorphic organic device (ENODe) operating with a fundamentally different mechanism from existing memristors. ENODe switches at low energymore » (<10 pJ for 103 μm2 devices) and voltage, displays >500 distinct, non-volatile conductance states within a ~1 V range, and achieves high classification accuracy when implemented in neural network simulations. Plastic ENODEs are also fabricated on flexible substrates enabling the integration of neuromorphic functionality in stretchable electronic systems. Mechanical flexibility makes ENODes compatible with 3D architectures, opening a path towards extreme interconnectivity comparable to the human brain.« less

  2. A non-volatile organic electrochemical device as a low-voltage artificial synapse for neuromorphic computing.

    PubMed

    van de Burgt, Yoeri; Lubberman, Ewout; Fuller, Elliot J; Keene, Scott T; Faria, Grégorio C; Agarwal, Sapan; Marinella, Matthew J; Alec Talin, A; Salleo, Alberto

    2017-04-01

    The brain is capable of massively parallel information processing while consuming only ∼1-100 fJ per synaptic event. Inspired by the efficiency of the brain, CMOS-based neural architectures and memristors are being developed for pattern recognition and machine learning. However, the volatility, design complexity and high supply voltages for CMOS architectures, and the stochastic and energy-costly switching of memristors complicate the path to achieve the interconnectivity, information density, and energy efficiency of the brain using either approach. Here we describe an electrochemical neuromorphic organic device (ENODe) operating with a fundamentally different mechanism from existing memristors. ENODe switches at low voltage and energy (<10 pJ for 10(3) μm(2) devices), displays >500 distinct, non-volatile conductance states within a ∼1 V range, and achieves high classification accuracy when implemented in neural network simulations. Plastic ENODes are also fabricated on flexible substrates enabling the integration of neuromorphic functionality in stretchable electronic systems. Mechanical flexibility makes ENODes compatible with three-dimensional architectures, opening a path towards extreme interconnectivity comparable to the human brain.

  3. Nonvolatile optical memory via recoil-induced resonance in a pure two-level system

    NASA Astrophysics Data System (ADS)

    de Almeida, A. J. F.; Maynard, M.-A.; Banerjee, C.; Felinto, D.; Goldfarb, F.; Tabosa, J. W. R.

    2016-12-01

    We report on the storage of light via the phenomenon of recoil-induced resonance in a pure two-level system of cold cesium atoms. We use a strong coupling beam and a weak probe beam to couple different external momentum states of the cesium atom via two-photon Raman interaction which leads to the storage of the optical information of the probe beam. We have also measured the probe transmission spectrum, as well as the light storage spectrum which reveals very narrow subnatural resonance features showing absorption and gain. We have demonstrated that this memory presents the unique property of being insensitive to the reading process, which does not destroy the stored information leading to a memory lifetime limited only by the atomic thermal motion.

  4. Three-terminal organic memory devices

    NASA Astrophysics Data System (ADS)

    He, Jun; Ma, Liping; Wu, Jianhua; Yang, Yang

    2005-03-01

    An organic electrical bistable device (OBD) has been reported previously, which has an organic/metal-nanocluster/organic structure sandwiched between a top and bottom electrode [L. P. Ma, J. Liu, and Y. Yang, Appl. Phys. Lett. 80, 2997 (2002)]. This device can be switched between a low- (OFF) and a high- (ON) conductivity state by external bias. In this article, we report a three-terminal organic memory device, which is realized by wiring out the metal-nanocluster layer of the OBD as the middle electrode. The ON and OFF states of the device can be read out by measuring the potential of the middle electrode. By controlling the interface formation of the device, a three-terminal OBD with a potential change on the middle electrode of more than three orders in magnitude between the OFF state and ON state (from 0.2mVto0.77V) is achieved. By wiring out the middle electrode, the three-terminal OBD can also be considered as two 2-terminal devices stacked together. By proper interface engineering (to be discussed in detail in the text), we found that both the top and bottom devices show electrical bistability and memory effect. This can double the data storage density of the memory device. Details of the device mechanism are provided.

  5. A high performance triboelectric nanogenerator for self-powered non-volatile ferroelectric transistor memory.

    PubMed

    Fang, Huajing; Li, Qiang; He, Wenhui; Li, Jing; Xue, Qingtang; Xu, Chao; Zhang, Lijing; Ren, Tianling; Dong, Guifang; Chan, H L W; Dai, Jiyan; Yan, Qingfeng

    2015-11-07

    We demonstrate an integrated module of self-powered ferroelectric transistor memory based on the combination of a ferroelectric FET and a triboelectric nanogenerator (TENG). The novel TENG was made of a self-assembled polystyrene nanosphere array and a poly(vinylidene fluoride) porous film. Owing to this unique structure, it exhibits an outstanding performance with an output voltage as high as 220 V per cycle. Meanwhile, the arch-shaped TENG is shown to be able to pole a bulk ferroelectric 0.65Pb(Mg1/3Nb2/3)O3-0.35PbTiO3 (PMN-PT) single crystal directly. Based on this effect, a bottom gate ferroelectric FET was fabricated using pentacene as the channel material and a PMN-PT single crystal as the gate insulator. Systematic tests illustrate that the ON/OFF current ratio of this transistor memory element is approximately 10(3). More importantly, we demonstrate the feasibility to switch the polarization state of this FET gate insulator, namely the stored information, by finger tapping the TENG with a designed circuit. These results may open up a novel application of TENGs in the field of self-powered memory systems.

  6. Flash drive memory apparatus and method

    NASA Technical Reports Server (NTRS)

    Hinchey, Michael G. (Inventor)

    2010-01-01

    A memory apparatus includes a non-volatile computer memory, a USB mass storage controller connected to the non-volatile computer memory, the USB mass storage controller including a daisy chain component, a male USB interface connected to the USB mass storage controller, and at least one other interface for a memory device, other than a USB interface, the at least one other interface being connected to the USB mass storage controller.

  7. Multistability, ionic doping, and charge dynamics in electrosynthesized polypyrrole, polymer-nanoparticle blend nonvolatile memory, and fixed p-i-n junction polymer light-emitting electrochemical cells

    NASA Astrophysics Data System (ADS)

    Simon, Daniel Theodore

    A variety of factors make semiconducting polymers a fascinating alternative for both device development and new areas of fundamental research. Among these are solution processability, low cost, flexibility, and the strong dependence of conduction on the presence of charge compensating ions. With the lack of a complete fundamental understanding of the materials, and the growing demand for novel solutions to semiconductor device design, research in the field can take many, often multifaceted, routes. Due to ion-mediated conduction and versatility of fabrication, conducting polymers can provide a route to the study of neural signaling. In the first of three research topics presented, junctions of polypyrrole electropolymenzed on microelectrode arrays are demonstrated. Indi vidual junctions, when synthesized in a three-electrode configuration, exhibit current switching behavior analogous to neural weighting. Junctions copolymerized with thiophene exhibit current rectification and the nonlinear current-voltage behavior requisite for complex neural systems. Applications to larger networks, and eventual use in analysis of signaling, are discussed. In the second research topic, nonvolatile resistive memory consisting of gold nanoparticles embedded in a polymer film is examined using admittance spectroscopy. The frequency dependence of the devices indicates space-charge-limited transport in the high-conductivity "on" state, and similar transport in the lower-conductivity "off' state. Furthermore, a larger do capacitance of the on state indicates that a greater amount of filling of midgap trap levels introduced by the nanoparticles increases conductivity, leading to the memory effect. Implications on the question as to whether or not the on state is the result of percolation pathways is discussed. The third and final research topic is a presentation of enhanced efficiency of polymer light-emitting electrochemical cells (LECs) by means of forming a doping self

  8. Skin-Inspired Haptic Memory Arrays with an Electrically Reconfigurable Architecture.

    PubMed

    Zhu, Bowen; Wang, Hong; Liu, Yaqing; Qi, Dianpeng; Liu, Zhiyuan; Wang, Hua; Yu, Jiancan; Sherburne, Matthew; Wang, Zhaohui; Chen, Xiaodong

    2016-02-24

    Skin-inspired haptic-memory devices, which can retain pressure information after the removel of external pressure by virtue of the nonvolatile nature of the memory devices, are achieved. The rise of haptic-memory devices will allow for mimicry of human sensory memory, opening new avenues for the design of next-generation high-performance sensing devices and systems.

  9. Novel synaptic memory device for neuromorphic computing

    PubMed Central

    Mandal, Saptarshi; El-Amin, Ammaarah; Alexander, Kaitlyn; Rajendran, Bipin; Jha, Rashmi

    2014-01-01

    This report discusses the electrical characteristics of two-terminal synaptic memory devices capable of demonstrating an analog change in conductance in response to the varying amplitude and pulse-width of the applied signal. The devices are based on Mn doped HfO2 material. The mechanism behind reconfiguration was studied and a unified model is presented to explain the underlying device physics. The model was then utilized to show the application of these devices in speech recognition. A comparison between a 20 nm × 20 nm sized synaptic memory device with that of a state-of-the-art VLSI SRAM synapse showed ~10× reduction in area and >106 times reduction in the power consumption per learning cycle. PMID:24939247

  10. Charging behavior of silicon nitride based non-volatile memory structures with embedded semiconductor nanocrystals

    NASA Astrophysics Data System (ADS)

    Horváth, Zs. J.; Basa, P.; Jászi, T.; Molnár, K. Z.; Pap, A. E.; Molnár, Gy.

    2013-03-01

    The charging behavior of MNS (metal-nitride-silicon) and MNOS (metal-nitride-oxide-silicon) structures containing Si or Ge nanocrystals were studied by capacitance-voltage (C-V) and memory window measurements and by simulation. Both the width of hysteresis of C-V characteristics and the injected charge exhibited exponential dependence on the charging voltage at moderate voltage values, while at high voltages the width of hysteresis of C-V characteristics and the injected charge exhibited saturation. The memory window for reference MNS structure without nanocrystals was wider than that for reference MNOS structures. The presence of nanocrystals enhanced the charging behavior of MNOS structures, but in MNS structures nanocrystals exhibited the opposite effect. The main conclusion is that the presence of nanocrystals or other deep levels close to the Si surface enhances the charge injection properties due to the increased tunneling probability, but nanocrystals or other deep levels located far from the Si surface in the nitride layer do not enhance, but even can degrade the charging behavior by the capture of charge carriers.

  11. Resistively heated shape memory polymer device

    DOEpatents

    Marion, III, John E.; Bearinger, Jane P.; Wilson, Thomas S.; Maitland, Duncan J.

    2016-10-25

    A resistively heated shape memory polymer device is made by providing a rod, sheet or substrate that includes a resistive medium. The rod, sheet or substrate is coated with a first shape memory polymer providing a coated intermediate unit. The coated intermediate unit is in turn coated with a conductive material providing a second intermediate unit. The second coated intermediate unit is in turn coated with an outer shape memory polymer. The rod, sheet or substrate is exposed and an electrical lead is attached to the rod, sheet or substrate. The conductive material is exposed and an electrical lead is attached to the conductive material.

  12. Transparent and flexible write-once-read-many (WORM) memory device based on egg albumen

    NASA Astrophysics Data System (ADS)

    Qu, Bo; Lin, Qianru; Wan, Tao; Du, Haiwei; Chen, Nan; Lin, Xi; Chu, Dewei

    2017-08-01

    Egg albumen, as an important protein resource in nature, is an interesting dielectric material exhibiting many fascinating properties for the development of environmentally friendly electronic devices. Taking advantage of their extraordinary transparency and flexibility, this paper presents an innovative preparation approach for albumen thin film based write-once-read-many-times (WORM) memory devices in a simple, cost-effective manner. The fabricated device shows superior data retention properties including non-volatile character (over 105 s) and promising great read durability (106 times). Furthermore, our results suggested that the electric-field-induced trap-controlled space charge limited current (SCLC) conduction is responsible for the observed resistance switching effect. The present study may likely reveal another pathway towards complete see-through electrical devices.

  13. Unipolar resistive switching behavior of amorphous YCrO{sub 3} films for nonvolatile memory applications

    SciTech Connect

    Sharma, Yogesh E-mail: rkatiyar@uprrp.edu; Misra, Pankaj; Katiyar, Ram S. E-mail: rkatiyar@uprrp.edu

    2014-08-28

    Amorphous YCrO{sub 3} (YCO) films were prepared on Pt/TiO{sub 2}/SiO{sub 2}/Si substrate by pulsed laser deposition in order to investigate resistive switching (RS) phenomenon. The Pt/YCO/Pt device showed stable unipolar RS with resistance ratio of ∼10{sup 5} between low and high resistance states, excellent endurance and retention characteristics, as well as, non-overlapping switching voltages with narrow dispersions. Based on the x-ray photoelectron spectroscopy and temperature dependent switching characteristics, observed RS was mainly ascribed to the oxygen vacancies. Moreover, current-voltage characteristics of the device in low and high resistance states were described by Ohmic and trap controlled space–charge limited conduction mechanisms, respectively.

  14. Design and fabrication of memory devices based on nanoscale polyoxometalate clusters

    NASA Astrophysics Data System (ADS)

    Busche, Christoph; Vilà-Nadal, Laia; Yan, Jun; Miras, Haralampos N.; Long, De-Liang; Georgiev, Vihar P.; Asenov, Asen; Pedersen, Rasmus H.; Gadegaard, Nikolaj; Mirza, Muhammad M.; Paul, Douglas J.; Poblet, Josep M.; Cronin, Leroy

    2014-11-01

    Flash memory devices--that is, non-volatile computer storage media that can be electrically erased and reprogrammed--are vital for portable electronics, but the scaling down of metal-oxide-semiconductor (MOS) flash memory to sizes of below ten nanometres per data cell presents challenges. Molecules have been proposed to replace MOS flash memory, but they suffer from low electrical conductivity, high resistance, low device yield, and finite thermal stability, limiting their integration into current MOS technologies. Although great advances have been made in the pursuit of molecule-based flash memory, there are a number of significant barriers to the realization of devices using conventional MOS technologies. Here we show that core-shell polyoxometalate (POM) molecules can act as candidate storage nodes for MOS flash memory. Realistic, industry-standard device simulations validate our approach at the nanometre scale, where the device performance is determined mainly by the number of molecules in the storage media and not by their position. To exploit the nature of the core-shell POM clusters, we show, at both the molecular and device level, that embedding [(Se(IV)O3)2]4- as an oxidizable dopant in the cluster core allows the oxidation of the molecule to a [Se(V)2O6]2- moiety containing a {Se(V)-Se(V)} bond (where curly brackets indicate a moiety, not a molecule) and reveals a new 5+ oxidation state for selenium. This new oxidation state can be observed at the device level, resulting in a new type of memory, which we call `write-once-erase'. Taken together, these results show that POMs have the potential to be used as a realistic nanoscale flash memory. Also, the configuration of the doped POM core may lead to new types of electrical behaviour. This work suggests a route to the practical integration of configurable molecules in MOS technologies as the lithographic scales approach the molecular limit.

  15. Design and fabrication of memory devices based on nanoscale polyoxometalate clusters.

    PubMed

    Busche, Christoph; Vilà-Nadal, Laia; Yan, Jun; Miras, Haralampos N; Long, De-Liang; Georgiev, Vihar P; Asenov, Asen; Pedersen, Rasmus H; Gadegaard, Nikolaj; Mirza, Muhammad M; Paul, Douglas J; Poblet, Josep M; Cronin, Leroy

    2014-11-27

    Flash memory devices--that is, non-volatile computer storage media that can be electrically erased and reprogrammed--are vital for portable electronics, but the scaling down of metal-oxide-semiconductor (MOS) flash memory to sizes of below ten nanometres per data cell presents challenges. Molecules have been proposed to replace MOS flash memory, but they suffer from low electrical conductivity, high resistance, low device yield, and finite thermal stability, limiting their integration into current MOS technologies. Although great advances have been made in the pursuit of molecule-based flash memory, there are a number of significant barriers to the realization of devices using conventional MOS technologies. Here we show that core-shell polyoxometalate (POM) molecules can act as candidate storage nodes for MOS flash memory. Realistic, industry-standard device simulations validate our approach at the nanometre scale, where the device performance is determined mainly by the number of molecules in the storage media and not by their position. To exploit the nature of the core-shell POM clusters, we show, at both the molecular and device level, that embedding [(Se(IV)O3)2](4-) as an oxidizable dopant in the cluster core allows the oxidation of the molecule to a [Se(v)2O6](2-) moiety containing a {Se(V)-Se(V)} bond (where curly brackets indicate a moiety, not a molecule) and reveals a new 5+ oxidation state for selenium. This new oxidation state can be observed at the device level, resulting in a new type of memory, which we call 'write-once-erase'. Taken together, these results show that POMs have the potential to be used as a realistic nanoscale flash memory. Also, the configuration of the doped POM core may lead to new types of electrical behaviour. This work suggests a route to the practical integration of configurable molecules in MOS technologies as the lithographic scales approach the molecular limit.

  16. High reliable and stable organic field-effect transistor nonvolatile memory with a poly(4-vinyl phenol) charge trapping layer based on a pn-heterojunction active layer

    SciTech Connect

    Xiang, Lanyi; Ying, Jun; Han, Jinhua; Zhang, Letian E-mail: wwei99@jlu.edu.cn; Wang, Wei E-mail: wwei99@jlu.edu.cn

    2016-04-25

    In this letter, we demonstrate a high reliable and stable organic field-effect transistor (OFET) based nonvolatile memory (NVM) with a polymer poly(4-vinyl phenol) (PVP) as the charge trapping layer. In the unipolar OFETs, the inreversible shifts of the turn-on voltage (V{sub on}) and severe degradation of the memory window (ΔV{sub on}) at programming (P) and erasing (E) voltages, respectively, block their application in NVMs. The obstacle is overcome by using a pn-heterojunction as the active layer in the OFET memory, which supplied a holes and electrons accumulating channel at the supplied P and E voltages, respectively. Both holes and electrons transferring from the channels to PVP layer and overwriting the trapped charges with an opposite polarity result in the reliable bidirectional shifts of V{sub on} at P and E voltages, respectively. The heterojunction OFET exhibits excellent nonvolatile memory characteristics, with a large ΔV{sub on} of 8.5 V, desired reading (R) voltage at 0 V, reliable P/R/E/R dynamic endurance over 100 cycles and a long retention time over 10 years.

  17. Non-volatile Al2O3 Memory using Nanoscale Al-rich Al2O3 Thin Film as a Charge Storage Layer

    NASA Astrophysics Data System (ADS)

    Nakata, Shunji; Saito, Kunio; Shimada, Masaru

    2006-04-01

    This article describes the fabrication process and capacitance-voltage (C-V) characteristics of a new non-volatile Al2O3 memory with nanoscale thin film deposited by electron-cyclotron-resonance sputtering. Al-rich Al2O3 shows characteristics somewhere between Al and Al2O3 in the refractive index and wet etching rate. C-V characteristics of Al-rich Al2O3 memory show a large hysteresis window due to the Al-rich structure, while there is no hysteresis window in the case of stoichiometric Al2O3. This memory is expected to stay non-volatile for several years or more because the capacitance value after writing and erasing operation remained almost unchanged after 4 h at T=85 °C. Also, another new memory structure comprising SiO2/Al2O3 and the Al-rich Al2O3 structure is proposed, which features increased mobility due to the reduction of electron scattering at the Si/Al2O3 interface.

  18. Electrically Modifiable Nonvolatile SONOS Synapses for Electronic Neural Networks.

    DTIC Science & Technology

    1992-09-30

    for the electrically reprogrammable analog conductance in an artificial neural network. We have demonstrated the attractive featuies of this synaptic ...Electrically Modifiable Synaptic Element for VLSI Neural Network Implementation", Proceedings of the 1991 IEEE Nonvolatile Semiconductor Memory Workshop...Nonvolatile Eletrically Modifiable Synaptic Element for VLSI Neural Network Implementation", 11th IEEE Nonvolatile Semiconductor Memory Workshop, 1991. 19. A

  19. Structural Phase Transition Effect on Resistive Switching Behavior of MoS2 -Polyvinylpyrrolidone Nanocomposites Films for Flexible Memory Devices.

    PubMed

    Zhang, Peng; Gao, Cunxu; Xu, Benhua; Qi, Lin; Jiang, Changjun; Gao, Meizhen; Xue, Desheng

    2016-04-01

    The 2H phase and 1T phase coexisting in the same molybdenum disulfide (MoS2 ) nanosheets can influence the electronic properties of the materials. The 1T phase of MoS2 is introduced into the 2H-MoS2 nanosheets by two-step hydrothermal synthetic methods. Two types of nonvolatile memory effects, namely write-once read-many times memory and rewritable memory effect, are observed in the flexible memory devices with the configuration of Al/1T@2H-MoS2 -polyvinylpyrrolidone (PVP)/indium tin oxide (ITO)/polyethylene terephthalate (PET) and Al/2H-MoS2 -PVP/ITO/PET, respectively. It is observed that structural phase transition in MoS2 nanosheets plays an important role on the resistive switching behaviors of the MoS2 -based device. It is hoped that our results can offer a general route for the preparation of various promising nanocomposites based on 2D nanosheets of layered transition metal dichalcogenides for fabricating the high performance and flexible nonvolatile memory devices through regulating the phase structure in the 2D nanosheets.

  20. High temperature polyimide containing anthracene moiety and its structure, interface, and nonvolatile memory behavior.

    PubMed

    Park, Samdae; Kim, Kyungtae; Kim, Dong Min; Kwon, Wonsang; Choi, Junman; Ree, Moonhor

    2011-03-01

    A high temperature polyimide bearing anthracene moieties, poly(3,3'-di(9-anthracenemethoxy)-4,4'-biphenylene hexafluoroisopropylidenediphthalimide) (6F-HAB-AM PI) was synthesized. The polymer exhibits excellent thermal stability up to around 410 °C. This polymer is amorphous but orients preferentially in the plane of nanoscale thin films. In device fabrications of its nanoscale thin films with metal top and bottom electrodes, no diffusion of the metal atoms or ions between the polymer and electrodes was found; however, the aluminum bottom electrode had somewhat undergone oxide layer (about 1.2 nm thick) formation at the surface during the post polymer layer formation process, which was confirmed to have no significant influence on the device performance. The polymer thin film exhibited excellent unipolar and bipolar switching behaviors over a very small voltage range, less than ±2 V. Further, the PI films show repeatable writing, reading, and erasing ability with long reliability and high ON/OFF current ratio (up to 10(7)) in air ambient conditions as well as even at temperatures up to 200 °C.

  1. CD uniformity correction on 45-nm technology non-volatile memory

    NASA Astrophysics Data System (ADS)

    Buttgereit, Ute; Birkner, Robert; Joyner, Mark; Graitzer, Erez; Cohen, Avi; Miyashita, Hiroyuki; Triulzi, Benedetta; Fasciszewski Zeballos, Alejandro; Romeo, Carmelo

    2010-03-01

    One of the key parameters necessary to assure a good and reliable functionality of any integrated circuit is the Critical Dimension Uniformity (CDU). There are different contributors which impact the total CDU: mask CD uniformity, scanner and lens fingerprint, resist process, wafer topography, mask error enhancement factor (MEEF) etc. In this work we focus on improvement of intra-field CDU at wafer level by improving the mask CD signature using a CDC200TM tool from Carl Zeiss SMS. The mask layout used is a line and space dark level of a 45nm node Non Volatile Memory (NVM). A prerequisite to improve intra-field CDU at wafer level is to characterize the mask CD signature precisely. For CD measurement on mask the newly developed wafer level CD metrology tool WLCD32 of Carl Zeiss SMS was used. The WLCD32 measures CD based on aerial imaging technology. The WLCD32 measurement data show an excellent correlation to wafer CD data. For CDU correction the CDC200TM tool is used. By utilizing an ultrafast femto-second laser the CDC200TM writes intra-volume shading elements (Shade-In ElementsTM) inside the bulk of the mask. By adjusting the density of the shading elements, the light transmission through the mask is locally changed in a manner that improves wafer CDU when the corrected mask is printed. In the present work we will demonstrate a closed loop process of WLCD32 and CDC200TM to improve mask CD signature as one of the main contributors to intra-field wafer CDU.

  2. Reversible strain-induced magnetization switching in FeGa nanomagnets: Pathway to a rewritable, non-volatile, non-toggle, extremely low energy straintronic memory

    NASA Astrophysics Data System (ADS)

    Ahmad, Hasnain; Atulasimha, Jayasimha; Bandyopadhyay, Supriyo

    2015-12-01

    We report reversible strain-induced magnetization switching between two stable/metastable states in ~300 nm sized FeGa nanomagnets delineated on a piezoelectric PMN-PT substrate. Voltage of one polarity applied across the substrate generates compressive strain in a nanomagnet and switches its magnetization to one state, while voltage of the opposite polarity generates tensile strain and switches the magnetization back to the original state. The two states can encode the two binary bits, and, using the right voltage polarity, one can write either bit deterministically. This portends an ultra-energy-efficient non-volatile “non-toggle” memory.

  3. Reversible strain-induced magnetization switching in FeGa nanomagnets: Pathway to a rewritable, non-volatile, non-toggle, extremely low energy straintronic memory

    PubMed Central

    Ahmad, Hasnain; Atulasimha, Jayasimha; Bandyopadhyay, Supriyo

    2015-01-01

    We report reversible strain-induced magnetization switching between two stable/metastable states in ~300 nm sized FeGa nanomagnets delineated on a piezoelectric PMN-PT substrate. Voltage of one polarity applied across the substrate generates compressive strain in a nanomagnet and switches its magnetization to one state, while voltage of the opposite polarity generates tensile strain and switches the magnetization back to the original state. The two states can encode the two binary bits, and, using the right voltage polarity, one can write either bit deterministically. This portends an ultra-energy-efficient non-volatile “non-toggle” memory. PMID:26657829

  4. High Performance Transparent Transistor Memory Devices Using Nano-Floating Gate of Polymer/ZnO Nanocomposites

    PubMed Central

    Shih, Chien-Chung; Lee, Wen-Ya; Chiu, Yu-Cheng; Hsu, Han-Wen; Chang, Hsuan-Chun; Liu, Cheng-Liang; Chen, Wen-Chang

    2016-01-01

    Nano-floating gate memory devices (NFGM) using metal nanoparticles (NPs) covered with an insulating polymer have been considered as a promising electronic device for the next-generation nonvolatile organic memory applications NPs. However, the transparency of the device with metal NPs is restricted to 60~70% due to the light absorption in the visible region caused by the surface plasmon resonance effects of metal NPs. To address this issue, we demonstrate a novel NFGM using the blends of hole-trapping poly (9-(4-vinylphenyl) carbazole) (PVPK) and electron-trapping ZnO NPs as the charge storage element. The memory devices exhibited a remarkably programmable memory window up to 60 V during the program/erase operations, which was attributed to the trapping/detrapping of charge carriers in ZnO NPs/PVPK composite. Furthermore, the devices showed the long-term retention time (>105 s) and WRER test (>200 cycles), indicating excellent electrical reliability and stability. Additionally, the fabricated transistor memory devices exhibited a relatively high transparency of 90% at the wavelength of 500 nm based on the spray-coated PEDOT:PSS as electrode, suggesting high potential for transparent organic electronic memory devices. PMID:26831222

  5. Memory Device and Nanofabrication Techniques Using Electrically Configurable Materials

    NASA Astrophysics Data System (ADS)

    Ascenso Simões, Bruno

    Development of novel nanofabrication techniques and single-walled carbon nanotubes field configurable transistor (SWCNT-FCT) memory devices using electrically configurable materials is presented. A novel lithographic technique, electric lithography (EL), that uses electric field for pattern generation has been demonstrated. It can be used for patterning of biomolecules on a polymer surface and patterning of resist as well. Using electrical resist composed of a polymer having Boc protected amine group and iodonium salt, Boc group on the surface of polymer was modified to free amine by applying an electric field. On the modified surface of the polymer, Streptavidin pattern was fabricated with a sub-micron scale. Also patterning of polymer resin composed of epoxy monomers and diaryl iodonium salt by EL has been demonstrated. Reaction mechanism for electric resist configuration is believed to be induced by an acid generation via electrochemical reduction in the resist. We show a novel field configurable transistor (FCT) based on single-walled carbon nanotube network field-effect transistors in which poly (ethylene glycol) crosslinked by electron-beam is incorporated into the gate. The device conductance can be configured to arbitrary states reversibly and repeatedly by applying external gate voltages. Raman spectroscopy revealed that evolution of the ratio of D- to G-band intensity in the SWCNTs of the FCT progressively increases as the device is configured to lower conductance states. Electron transport studies at low temperatures showed a strong temperature dependence of the resistance. Band gap widening of CNTs up to ˜ 4 eV has been observed by examining the differential conductance-gate voltage-bias voltage relationship. The switching mechanism of the FCT is attributed a structural transformation of CNTs via reversible hydrogenation and dehydrogenations induced by gate voltages, which tunes the CNT bandgap continuously and reversibly to non-volatile analog values

  6. Solid-state non-volatile electronically programmable reversible variable resistance device

    NASA Technical Reports Server (NTRS)

    Ramesham, Rajeshuni (Inventor); Thakoor, Sarita (Inventor); Daud, Taher (Inventor); Thakoor, Aniklumar P. (Inventor)

    1989-01-01

    A solid-state variable resistance device (10) whose resistance can be repeatedly altered by a control signal over a wide range, and which will remain stable after the signal is removed, is formed on an insulated layer (14), supported on a substrate (12) and comprises a set of electrodes (16a, 16b) connected by a layer (18) of material, which changes from an insulator to a conductor upon the injection of ions, covered by a layer (22) of material with insulating properties which permit the passage of ions, overlaid by an ion donor material (20). The ion donor material is overlaid by an insulating layer (24) upon which is deposited a control gate (26) located above the contacts. In a preferred embodiment, the variable resistance material comprises WO.sub.3, the ion donor layer comprises Cr.sub.2 O.sub.3, and the layers sandwiching the ion donor layer comprise silicon monoxide. When a voltage is applied to the gate, the resistance between the electrode contacts changes, decreasing with positive voltage and increasing with negative voltage.

  7. Effect of ZrOx/HfOx bilayer structure on switching uniformity and reliability in nonvolatile memory applications

    NASA Astrophysics Data System (ADS)

    Lee, Joonmyoung; Bourim, El Mostafa; Lee, Wootae; Park, Jubong; Jo, Minseok; Jung, Seungjae; Shin, Jungho; Hwang, Hyunsang

    2010-10-01

    We have investigated the bilayer structure of binary oxides such as HfOx and ZrOx for applications to resistance memory. The ZrOx/HfOx bilayer structure shows a lower reset current and operating voltage than an HfOx monolayer under dc sweep voltage. Furthermore, the bilayer structure exhibits a tight distribution of switching parameters, good switching endurance up to 105 cycles, and good data retention at 85 °C. The resistive switching mechanism of memory devices incorporating the ZrOx/HfOx bilayer structure can be attributed to the control of multiple conducting filaments through the occurrence of redox reactions at the tip of the localized filament.

  8. Shape memory polymer therapeutic devices for stroke

    NASA Astrophysics Data System (ADS)

    Wilson, Thomas S.; Small, Ward, IV; Benett, William J.; Bearinger, Jane P.; Maitland, Duncan J.

    2005-11-01

    Shape memory polymers (SMPs) are attracting a great deal of interest in the scientific community for their use in applications ranging from light weight structures in space to micro-actuators in MEMS devices. These relatively new materials can be formed into a primary shape, reformed into a stable secondary shape, and then controllably actuated to recover their primary shape. The first part of this presentation will be a brief review of the types of polymeric structures which give rise to shape memory behavior in the context of new shape memory polymers with highly regular network structures recently developed at LLNL for biomedical devices. These new urethane SMPs have improved optical and physical properties relative to commercial SMPs, including improved clarity, high actuation force, and sharper actuation transition. In the second part of the presentation we discuss the development of SMP based devices for mechanically removing neurovascular occlusions which result in ischemic stroke. These devices are delivered to the site of the occlusion in compressed form, are pushed through the occlusion, actuated (usually optically) to take on an expanded conformation, and then used to dislodge and grip the thrombus while it is withdrawn through the catheter.

  9. Shape Memory Polymer Therapeutic Devices for Stroke

    SciTech Connect

    Wilson, T S; Small IV, W; Benett, W J; Bearinger, J P; Maitland, D J

    2005-10-11

    Shape memory polymers (SMPs) are attracting a great deal of interest in the scientific community for their use in applications ranging from light weight structures in space to micro-actuators in MEMS devices. These relatively new materials can be formed into a primary shape, reformed into a stable secondary shape, and then controllably actuated to recover their primary shape. The first part of this presentation will be a brief review of the types of polymeric structures which give rise to shape memory behavior in the context of new shape memory polymers with highly regular network structures recently developed at LLNL for biomedical devices. These new urethane SMPs have improved optical and physical properties relative to commercial SMPs, including improved clarity, high actuation force, and sharper actuation transition. In the second part of the presentation we discuss the development of SMP based devices for mechanically removing neurovascular occlusions which result in ischemic stroke. These devices are delivered to the site of the occlusion in compressed form, are pushed through the occlusion, actuated (usually optically) to take on an expanded conformation, and then used to dislodge and grip the thrombus while it is withdrawn through the catheter.

  10. Novel spintronics devices for memory and logic: prospects and challenges for room temperature all spin computing

    NASA Astrophysics Data System (ADS)

    Wang, Jian-Ping

    An energy efficient memory and logic device for the post-CMOS era has been the goal of a variety of research fields. The limits of scaling, which we expect to reach by the year 2025, demand that future advances in computational power will not be realized from ever-shrinking device sizes, but rather by innovative designs and new materials and physics. Magnetoresistive based devices have been a promising candidate for future integrated magnetic computation because of its unique non-volatility and functionalities. The application of perpendicular magnetic anisotropy for potential STT-RAM application was demonstrated and later has been intensively investigated by both academia and industry groups, but there is no clear path way how scaling will eventually work for both memory and logic applications. One of main reasons is that there is no demonstrated material stack candidate that could lead to a scaling scheme down to sub 10 nm. Another challenge for the usage of magnetoresistive based devices for logic application is its available switching speed and writing energy. Although a good progress has been made to demonstrate the fast switching of a thermally stable magnetic tunnel junction (MTJ) down to 165 ps, it is still several times slower than its CMOS counterpart. In this talk, I will review the recent progress by my research group and my C-SPIN colleagues, then discuss the opportunities, challenges and some potential path ways for magnetoresitive based devices for memory and logic applications and their integration for room temperature all spin computing system.

  11. Nanodot-based organic memory devices

    NASA Astrophysics Data System (ADS)

    Liu, Zhengchun

    2006-04-01

    In this study, resistor-type, diode-type, and transistor-type organic memory devices were investigated, aiming at the low-cost plastic integrated circuit applications. A series of solution-processing techniques including spin-coating, inkjet printing, and self-assembly were employed to fabricate these devices. The organic resistive memory device is based on a novel molecular complex film composed of tetracyanoquinodimethane (TCNQ) and a soluble methanofullerene derivative [6,6]-phenyl C61-butyric acid methyl ester (PCBM). It has an Al/molecules/Al sandwich structure. The molecular layer was formed by spin-coating technique instead of expensive vacuum deposition method. The current-voltage characteristics show that the device switches from the initial 'low' conduction state to 'high' conduction state upon application of external electric field at room temperature and return to 'low' conduction state when a high current pulse is applied. The on/off ratio is over 106. Each state has been found to remain stable for more than five months, even after the external electric field is removed. The PCBM nanodots wrapped by TCNQ molecules can form potential wells for charge trapping, and are believed to be responsible for the memory effects. A rewritable diode memory device was achieved in an improved configuration, i.e., ITO-PEDOT:PSS-PCBM/TCNQ-Al, where a semiconductor polymer PEDOT:PSS is used to form p+-N heterojunction with PCBM/TCNQ. It exhibits a diode characteristic (low conductive) before switching to a high-conductive Poole-Frenkel regime upon applying a positive external bias to ITO. The on/off ratio at +1.0 V is up to 105. Simulation results from Taurus-Medici are in qualitative agreement with the experimental results and the proposed charge storage model. The transistor-type memory device is fabricated on a heavily doped n-type silicon (n+-Si) substrate with a 100 nm thick thermally-grown oxide layer. The n+-Si serves as the gate electrode, while the oxide layer

  12. Bipolar transparent resistive switching based in a-IGZO/STO/a-IGZO structure for nonvolatile memory application

    NASA Astrophysics Data System (ADS)

    Yan, Xiaobing; Zhou, Zhenyu; Zhao, Jianhui; Li, Yucheng; Hao, Hua; Li, Yan; Chen, Yingfang; Zheng, Shukai; Bai, Gang

    2017-04-01

    In this study, we have fabricated the bipolar transparent resistive random access memory (TRRAM) based in complex oxide amorphous STO films as dielectric layer grown by pulsed laser deposition (PLD) technique, and semiconducting In-Ga-Zn-O films were employed as electrode. The experimental results show that the average transmittance of the device is above 82.7% in the visible region (400-800nm). The device can be repeated more than 260 times, and the high and low resistance state can be held without obvious degradation within 5×104s. The conduction mechanisms at HRS and LRS were both attributed to the space charge limited current. And the RS mechanism is related to trapping and releasing of electrons which impact the current level though the cell for changing the resistance state.

  13. Migration of interfacial oxygen ions modulated resistive switching in oxide-based memory devices

    NASA Astrophysics Data System (ADS)

    Chen, C.; Gao, S.; Zeng, F.; Tang, G. S.; Li, S. Z.; Song, C.; Fu, H. D.; Pan, F.

    2013-07-01

    Oxides-based resistive switching memory induced by oxygen ions migration is attractive for future nonvolatile memories. Numerous works had focused their attentions on the sandwiched oxide materials for depressing the characteristic variations, but the comprehensive studies of the dependence of electrodes on the migration behavior of oxygen ions are overshadowed. Here, we investigated the interaction of various metals (Ni, Co, Al, Ti, Zr, and Hf) with oxygen atoms at the metal/Ta2O5 interface under electric stress and explored the effect of top electrode on the characteristic variations of Ta2O5-based memory device. It is demonstrated that chemically inert electrodes (Ni and Co) lead to the scattering switching characteristics and destructive gas bubbles, while the highly chemically active metals (Hf and Zr) formed a thick and dense interfacial intermediate oxide layer at the metal/Ta2O5 interface, which also degraded the resistive switching behavior. The relatively chemically active metals (Al and Ti) can absorb oxygen ions from the Ta2O5 film and avoid forming the problematic interfacial layer, which is benefit to the formation of oxygen vacancies composed conduction filaments in Ta2O5 film thus exhibit the minimum variations of switching characteristics. The clarification of oxygen ions migration behavior at the interface can lead further optimization of resistive switching performance in Ta2O5-based memory device and guide the rule of electrode selection for other oxide-based resistive switching memories.

  14. Silicon Nanocrystal Nonvolatile Memories

    NASA Astrophysics Data System (ADS)

    Muralidhar, R.; Sadd, M. A.; White, B. E.

    In 1959, physicist Richard Feynman delivered his "There's Plenty of Room Left at the Bottom" lecture [1] to the American Physical Society that spawned the field of nanotechnology. In that lecture, Feynman discussed two themes that are critical to the work presented here. The first was the recognition of the tremendous opportunities associated with the ability to miniaturize computers. At the time of his lecture, the most powerful computers consumed entire rooms, and Feynman realized the tremendous gains that could be realized in performance if the technology could be reduced to the size of one's thumbnail. The second important area Feynman touched on was the unique opportunities that surround the manipulation of matter at the atomic level to create materials with unique and, hopefully, useful properties. Both of these ideas have now been realized as evidenced by the exponential growth of the semiconductor industry over the last 40 years and the tremendous explosion in nanotechnology research, development, and product introduction over the last decade

  15. A complementary switching mechanism for organic memory devices to regulate the conductance of binary states

    NASA Astrophysics Data System (ADS)

    Vyas, Giriraj; Dagar, Parveen; Sahu, Satyajit

    2016-06-01

    We have fabricated an organic non-volatile memory device wherein the ON/OFF current ratio has been controlled by varying the concentration of a small organic molecule, 2,3-Dichloro-5,6-dicyano-p-benzoquinone (DDQ), in an insulating matrix of a polymer Poly(4-vinylphenol) (PVP). A maximum ON-OFF ratio of 106 is obtained when the concentration of DDQ is half or 10 wt. % of PVP. In this process, the switching direction for the devices has also been altered, indicating the disparity in conduction mechanism. Conduction due to metal filament formation through the active material and the voltage dependent conformational change of the organic molecule seem to be the motivation behind the gradual change in the switching direction.

  16. Flexible organic memory devices with multilayer graphene electrodes.

    PubMed

    Ji, Yongsung; Lee, Sangchul; Cho, Byungjin; Song, Sunghoon; Lee, Takhee

    2011-07-26

    We fabricated 8 × 8 cross-bar array-type flexible organic resistive memory devices with transparent multilayer graphene (MLG) electrodes on a poly(ethylene terephthalate) substrate. The active layer of the memory devices is a composite of polyimide and 6-phenyl-C61 butyric acid methyl ester. The sheet resistance of the MLG film on memory device was found to be ∼270 Ω/◻, and the transmittance of separated MLG film from memory device was ∼92%. The memory devices showed typical write-once-read-many (WORM) characteristics and an ON/OFF ratio of over ∼10(6). The memory devices also exhibited outstanding cell-to-cell uniformity with flexibility. There was no substantial variation observed in the current levels of the WORM memory devices upon bending and bending cycling up to 10 000 times. A retention time of over 10(4) s was observed without fluctuation under bending.

  17. Thermomechanical analysis of shape memory devices.

    PubMed

    Trochu, F; Brailovski, V; Meunier, M A; Terriault, P; Qian, Y Y

    1996-01-01

    Shape memory alloys (SMA) are being increasingly used in various industrial applications as actuators, connectors, or damping materials. In the medical field, superelastic devices such as eyeglass frames, stents or guide catheters have come to market in the recent years. The design of SMA devices has usually been based on trial and error, since until recently no general simulation model was available to assist application engineers. The purpose of this article is to describe the computational methodology developed, validated and used for several industrial projects at Ecole Polytechnique of Montréal to simulate the thermomechanical behavior of shape memory materials. This new approach includes three main stages: experimental characterization, construction of a nonlinear material law based on dual kriging interpolation and finally, calculation of the thermomechanical response of SMA devices. For complex geometry, finite element analysis is used, but for simple devices such as springs or electrically activated SMA wires, simplified calculation methods are satisfactory. Validation results recently obtained will also be presented, and examples of industrial applications briefly reviewed.

  18. Achieving high mobility, low-voltage operating organic field-effect transistor nonvolatile memory by an ultraviolet-ozone treating ferroelectric terpolymer

    PubMed Central

    Xiang, Lanyi; Wang, Wei; Xie, Wenfa

    2016-01-01

    Poly(vinylidene fluoride–trifluoroethylene) has been widely used as a dielectric of the ferroelectric organic field-effect transistor (FE-OFET) nonvolatile memory (NVM). Some critical issues, including low mobility and high operation voltage, existed in these FE-OFET NVMs, should be resolved before considering to their commercial application. In this paper, we demonstrated low-voltage operating FE-OFET NVMs based on a ferroelectric terpolymer poly(vinylidene-fluoride-trifluoroethylene-chlorotrifluoroethylene) [P(VDF-TrFE-CTFE)] owed to its low coercive field. By applying an ultraviolet-ozone (UVO) treatment to modify the surface of P(VDF-TrFE-CTFE) films, the growth model of the pentacene film was changed, which improved the pentacene grain size and the interface morphology of the pentacene/P(VDF-TrFE-CTFE). Thus, the mobility of the FE-OFET was significantly improved. As a result, a high performance FE-OFET NVM, with a high mobility of 0.8 cm2 V−1 s−1, large memory window of 15.4~19.2, good memory on/off ratio of 103, the reliable memory endurance over 100 cycles and stable memory retention ability, was achieved at a low operation voltage of ±15 V. PMID:27824101

  19. Achieving high mobility, low-voltage operating organic field-effect transistor nonvolatile memory by an ultraviolet-ozone treating ferroelectric terpolymer

    NASA Astrophysics Data System (ADS)

    Xiang, Lanyi; Wang, Wei; Xie, Wenfa

    2016-11-01

    Poly(vinylidene fluoride-trifluoroethylene) has been widely used as a dielectric of the ferroelectric organic field-effect transistor (FE-OFET) nonvolatile memory (NVM). Some critical issues, including low mobility and high operation voltage, existed in these FE-OFET NVMs, should be resolved before considering to their commercial application. In this paper, we demonstrated low-voltage operating FE-OFET NVMs based on a ferroelectric terpolymer poly(vinylidene-fluoride-trifluoroethylene-chlorotrifluoroethylene) [P(VDF-TrFE-CTFE)] owed to its low coercive field. By applying an ultraviolet-ozone (UVO) treatment to modify the surface of P(VDF-TrFE-CTFE) films, the growth model of the pentacene film was changed, which improved the pentacene grain size and the interface morphology of the pentacene/P(VDF-TrFE-CTFE). Thus, the mobility of the FE-OFET was significantly improved. As a result, a high performance FE-OFET NVM, with a high mobility of 0.8 cm2 V-1 s-1, large memory window of 15.4~19.2, good memory on/off ratio of 103, the reliable memory endurance over 100 cycles and stable memory retention ability, was achieved at a low operation voltage of ±15 V.

  20. Application of nanomaterials in two-terminal resistive-switching memory devices

    PubMed Central

    Ouyang, Jianyong

    2010-01-01

    Nanometer materials have been attracting strong attention due to their interesting structure and properties. Many important practical applications have been demonstrated for nanometer materials based on their unique properties. This article provides a review on the fabrication, electrical characterization, and memory application of two-terminal resistive-switching devices using nanomaterials as the active components, including metal and semiconductor nanoparticles (NPs), nanotubes, nanowires, and graphenes. There are mainly two types of device architectures for the two-terminal devices with NPs. One has a triple-layer structure with a metal film sandwiched between two organic semiconductor layers, and the other has a single polymer film blended with NPs. These devices can be electrically switched between two states with significant different resistances, i.e. the ‘ON’ and ‘OFF’ states. These render the devices important application as two-terminal non-volatile memory devices. The electrical behavior of these devices can be affected by the materials in the active layer and the electrodes. Though the mechanism for the electrical switches has been in argument, it is generally believed that the resistive switches are related to charge storage on the NPs. Resistive switches were also observed on crossbars formed by nanotubes, nanowires, and graphene ribbons. The resistive switches are due to nanoelectromechanical behavior of the materials. The Coulombic interaction of transient charges on the nanomaterials affects the configurable gap of the crossbars, which results into significant change in current through the crossbars. These nanoelectromechanical devices can be used as fast-response and high-density memory devices as well. PMID:22110862

  1. Reconfigurable Nonvolatile Logic Operations in Resistance Switching Crossbar Array for Large-Scale Circuits.

    PubMed

    Huang, Peng; Kang, Jinfeng; Zhao, Yudi; Chen, Sijie; Han, Runze; Zhou, Zheng; Chen, Zhe; Ma, Wenjia; Li, Mu; Liu, Lifeng; Liu, Xiaoyan

    2016-11-01

    Resistance switching (RS) devices have potential to offer computing and memory function. A new computer unit is built of RS array, where processing and storing of information occur on same devices. Resistance states stored in devices located in arbitrary positions of RS array can be performed various nonvolatile logic operations. Logic functions can be reconfigured by altering trigger signals. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  2. Lead-free epitaxial ferroelectric material integration on semiconducting (100) Nb-doped SrTiO3 for low-power non-volatile memory and efficient ultraviolet ray detection

    NASA Astrophysics Data System (ADS)

    Kundu, Souvik; Clavel, Michael; Biswas, Pranab; Chen, Bo; Song, Hyun-Cheol; Kumar, Prashant; Halder, Nripendra N.; Hudait, Mantu K.; Banerji, Pallab; Sanghadasa, Mohan; Priya, Shashank

    2015-07-01

    We report lead-free ferroelectric based resistive switching non-volatile memory (NVM) devices with epitaxial (1-x)BaTiO3-xBiFeO3 (x = 0.725) (BT-BFO) film integrated on semiconducting (100) Nb (0.7%) doped SrTiO3 (Nb:STO) substrates. The piezoelectric force microscopy (PFM) measurement at room temperature demonstrated ferroelectricity in the BT-BFO thin film. PFM results also reveal the repeatable polarization inversion by poling, manifesting its potential for read-write operation in NVM devices. The electroforming-free and ferroelectric polarization coupled electrical behaviour demonstrated excellent resistive switching with high retention time, cyclic endurance, and low set/reset voltages. X-ray photoelectron spectroscopy was utilized to determine the band alignment at the BT-BFO and Nb:STO heterojunction, and it exhibited staggered band alignment. This heterojunction is found to behave as an efficient ultraviolet photo-detector with low rise and fall time. The architecture also demonstrates half-wave rectification under low and high input signal frequencies, where the output distortion is minimal. The results provide avenue for an electrical switch that can regulate the pixels in low or high frequency images. Combined this work paves the pathway towards designing future generation low-power ferroelectric based microelectronic devices by merging both electrical and photovoltaic properties of BT-BFO materials.

  3. Lead-free epitaxial ferroelectric material integration on semiconducting (100) Nb-doped SrTiO3 for low-power non-volatile memory and efficient ultraviolet ray detection.

    PubMed

    Kundu, Souvik; Clavel, Michael; Biswas, Pranab; Chen, Bo; Song, Hyun-Cheol; Kumar, Prashant; Halder, Nripendra N; Hudait, Mantu K; Banerji, Pallab; Sanghadasa, Mohan; Priya, Shashank

    2015-07-23

    We report lead-free ferroelectric based resistive switching non-volatile memory (NVM) devices with epitaxial (1-x)BaTiO3-xBiFeO3 (x = 0.725) (BT-BFO) film integrated on semiconducting (100) Nb (0.7%) doped SrTiO3 (Nb:STO) substrates. The piezoelectric force microscopy (PFM) measurement at room temperature demonstrated ferroelectricity in the BT-BFO thin film. PFM results also reveal the repeatable polarization inversion by poling, manifesting its potential for read-write operation in NVM devices. The electroforming-free and ferroelectric polarization coupled electrical behaviour demonstrated excellent resistive switching with high retention time, cyclic endurance, and low set/reset voltages. X-ray photoelectron spectroscopy was utilized to determine the band alignment at the BT-BFO and Nb:STO heterojunction, and it exhibited staggered band alignment. This heterojunction is found to behave as an efficient ultraviolet photo-detector with low rise and fall time. The architecture also demonstrates half-wave rectification under low and high input signal frequencies, where the output distortion is minimal. The results provide avenue for an electrical switch that can regulate the pixels in low or high frequency images. Combined this work paves the pathway towards designing future generation low-power ferroelectric based microelectronic devices by merging both electrical and photovoltaic properties of BT-BFO materials.

  4. Lead-free epitaxial ferroelectric material integration on semiconducting (100) Nb-doped SrTiO3 for low-power non-volatile memory and efficient ultraviolet ray detection

    PubMed Central

    Kundu, Souvik; Clavel, Michael; Biswas, Pranab; Chen, Bo; Song, Hyun-Cheol; Kumar, Prashant; Halder, Nripendra N.; Hudait, Mantu K.; Banerji, Pallab; Sanghadasa, Mohan; Priya, Shashank

    2015-01-01

    We report lead-free ferroelectric based resistive switching non-volatile memory (NVM) devices with epitaxial (1-x)BaTiO3-xBiFeO3 (x = 0.725) (BT-BFO) film integrated on semiconducting (100) Nb (0.7%) doped SrTiO3 (Nb:STO) substrates. The piezoelectric force microscopy (PFM) measurement at room temperature demonstrated ferroelectricity in the BT-BFO thin film. PFM results also reveal the repeatable polarization inversion by poling, manifesting its potential for read-write operation in NVM devices. The electroforming-free and ferroelectric polarization coupled electrical behaviour demonstrated excellent resistive switching with high retention time, cyclic endurance, and low set/reset voltages. X-ray photoelectron spectroscopy was utilized to determine the band alignment at the BT-BFO and Nb:STO heterojunction, and it exhibited staggered band alignment. This heterojunction is found to behave as an efficient ultraviolet photo-detector with low rise and fall time. The architecture also demonstrates half-wave rectification under low and high input signal frequencies, where the output distortion is minimal. The results provide avenue for an electrical switch that can regulate the pixels in low or high frequency images. Combined this work paves the pathway towards designing future generation low-power ferroelectric based microelectronic devices by merging both electrical and photovoltaic properties of BT-BFO materials. PMID:26202946

  5. Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

    NASA Astrophysics Data System (ADS)

    Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Bhansali, Unnat. S.; Alshareef, H. N.

    2012-06-01

    High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin film transistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectric transistors, which is very promising for low-power non-volatile memory applications.

  6. Partial-Thickness Grooves In A VBL Memory Device

    NASA Technical Reports Server (NTRS)

    Katti, Romney R.; Wu, Jiin-Chuan; Stadler, Henry L.

    1994-01-01

    Bias magnetic fields tailored to match those needed elsewhere in device. Grooves through part of thickness of magnetic garnet storage layer of vertical-Bloch-line (VBL) memory device used to confine magnetic bubble and stripe domains in desired storage areas. VBL-memory concept described in "Vertical-Bloch-Line Memory" (NPO-18467).

  7. Charge-trapping characteristics of fluorinated thin ZrO{sub 2} film for nonvolatile memory applications

    SciTech Connect

    Huang, X. D. E-mail: laip@eee.hku.hk; Shi, R. P.; Lai, P. T. E-mail: laip@eee.hku.hk

    2014-04-21

    The effects of fluorine treatment on the charge-trapping characteristics of thin ZrO{sub 2} film are investigated by physical and electrical characterization techniques. The formation of silicate interlayer at the ZrO{sub 2}/SiO{sub 2} interface is effectively suppressed by fluorine passivation. However, excessive fluorine diffusion into the Si substrate deteriorates the quality of the SiO{sub 2}/Si interface. Compared with the ZrO{sub 2}-based memory devices with no or excessive fluorine treatment, the one with suitable fluorine-treatment time shows higher operating speed and better retention due to less resistance of built-in electric field (formed by trapped electrons) against electron injection from the substrate and smaller trap-assisted tunneling leakage, resulting from improved ZrO{sub 2}/SiO{sub 2} and SiO{sub 2}/Si interfaces.

  8. Random Access Memory Technologies.

    DTIC Science & Technology

    1985-02-01

    extreme temperatures. True nonvolatility is offered by the NVRAM or shadow RAM. In the NVRAM , a volatile NMOS static RAM memory cell is merged with the...or reapplied, and no longer require special power sources. The size of the nine-device memory cell required for the NVRAM has limited its capacity to...4K. While 8K NVRAMs are expected in 1985, the 30 . . .’o .-. . high cost of these devices will hamper further development for larger capacity memories

  9. Recent Progress of Ferroelectric-Gate Field-Effect Transistors and Applications to Nonvolatile Logic and FeNAND Flash Memory

    PubMed Central

    Sakai, Shigeki; Takahashi, Mitsue

    2010-01-01

    We have investigated ferroelectric-gate field-effect transistors (FeFETs) with Pt/SrBi2Ta2O9/(HfO2)x(Al2O3)1−x (Hf-Al-O) and Pt/SrBi2Ta2O9/HfO2 gate stacks. The fabricated FeFETs have excellent data retention characteristics: The drain current ratio between the on- and off-states of a FeFET was more than 2 × 106 after 12 days, and the decreasing rate of this ratio was so small that the extrapolated drain current ratio after 10 years is larger than 1 × 105. A fabricated self-aligned gate Pt/SrBi2Ta2O9/Hf-Al-O/Si FET revealed a sufficiently large drain current ratio of 2.4 × 105 after 33.5 day, which is 6.5 × 104 after 10 years by extrapolation. The developed FeFETs also revealed stable retention characteristics at an elevated temperature up to 120 °C and had small transistor threshold voltage (Vth) distribution. The Vth can be adjusted by controlling channel impurity densities for both n-channel and p-channel FeFETs. These performances are now suitable to integrated circuit application with nonvolatile functions. Fundamental properties for the applications to ferroelectric-CMOS nonvolatile logic-circuits and to ferroelectric-NAND flash memories are demonstrated.

  10. CF{sub 4} plasma treatment on nanostructure band engineered Gd{sub 2}O{sub 3}-nanocrystal nonvolatile memory

    SciTech Connect

    Wang, Jer-Chyi; Lin, Chih-Ting

    2011-03-15

    The effects of CF{sub 4} plasma treatment on Gd{sub 2}O{sub 3} nanocrystal (NC) memory were investigated. For material analysis, secondary ion mass spectrometry and x-ray photoelectron spectroscopy analyses were performed to characterize the fluorine depth profile of the Gd{sub 2}O{sub 3}-NC film. In addition, an UV-visible spectrophotometer was used to obtain the Gd{sub 2}O{sub 3} bandgap and analyzed to suggest the modified structure of the energy band. Moreover, the electrical properties, including the memory window, program/erase speed, charge retention, and endurance characteristics were significantly improved depending on the CF{sub 4} plasma treatment conditions. This can be explained by the physical model based on the built-in electric field in the Gd{sub 2}O{sub 3} nanostructure. However, it was observed that too much CF{sub 4} plasma caused large surface roughness induced by the plasma damage, leading to characteristics degradation. It was concluded that with suitable CF{sub 4} plasma treatment, this Gd{sub 2}O{sub 3}-NC memory can be applied to future nonvolatile memory applications.

  11. Exploring Spin-transfer-torque devices and memristors for logic and memory applications

    NASA Astrophysics Data System (ADS)

    Pajouhi, Zoha

    As scaling CMOS devices is approaching its physical limits, researchers have begun exploring newer devices and architectures to replace CMOS. Due to their non-volatility and high density, Spin Transfer Torque (STT) devices are among the most prominent candidates for logic and memory applications. In this research, we first considered a new logic style called All Spin Logic (ASL). Despite its advantages, ASL consumes a large amount of static power; thus, several optimizations can be performed to address this issue. We developed a systematic methodology to perform the optimizations to ensure stable operation of ASL. Second, we investigated reliable design of STT-MRAM bit-cells and addressed the conflicting read and write requirements, which results in overdesign of the bit-cells. Further, a Device/Circuit/Architecture co-design framework was developed to optimize the STT-MRAM devices by exploring the design space through jointly considering yield enhancement techniques at different levels of abstraction. Recent advancements in the development of memristive devices have opened new opportunities for hardware implementation of non-Boolean computing. To this end, the suitability of memristive devices for swarm intelligence algorithms has enabled researchers to solve a maze in hardware. In this research, we utilized swarm intelligence of memristive networks to perform image edge detection. First, we proposed a hardware-friendly algorithm for image edge detection based on ant colony. Next, we designed the image edge detection algorithm using memristive networks.

  12. Four-state memory based on a giant and non-volatile converse magnetoelectric effect in FeAl/PIN-PMN-PT structure

    NASA Astrophysics Data System (ADS)

    Wei, Yanping; Gao, Cunxu; Chen, Zhendong; Xi, Shibo; Shao, Weixia; Zhang, Peng; Chen, Guilin; Li, Jiangong

    2016-07-01

    We report a stable, tunable and non-volatile converse magnetoelectric effect (ME) in a new type of FeAl/PIN-PMN-PT heterostructure at room temperature, with a giant electrical modulation of magnetization for which the maximum relative magnetization change (ΔM/M) is up to 66%. The 109° ferroelastic domain switching in the PIN-PMN-PT and coupling with the ferromagnetic (FM) film via uniaxial anisotropy originating from the PIN-PMN-PT (011) surface are the key roles in converse ME effect. We also propose here a new, four-state memory through which it is possible to modify the remanent magnetism state by adjusting the electric field. This work represents a helpful approach to securing electric-writing magnetic-reading with low energy consumption for future high-density information storage applications.

  13. Four-state memory based on a giant and non-volatile converse magnetoelectric effect in FeAl/PIN-PMN-PT structure

    PubMed Central

    Wei, Yanping; Gao, Cunxu; Chen, Zhendong; Xi, Shibo; Shao, Weixia; Zhang, Peng; Chen, Guilin; Li, Jiangong

    2016-01-01

    We report a stable, tunable and non-volatile converse magnetoelectric effect (ME) in a new type of FeAl/PIN-PMN-PT heterostructure at room temperature, with a giant electrical modulation of magnetization for which the maximum relative magnetization change (ΔM/M) is up to 66%. The 109° ferroelastic domain switching in the PIN-PMN-PT and coupling with the ferromagnetic (FM) film via uniaxial anisotropy originating from the PIN-PMN-PT (011) surface are the key roles in converse ME effect. We also propose here a new, four-state memory through which it is possible to modify the remanent magnetism state by adjusting the electric field. This work represents a helpful approach to securing electric-writing magnetic-reading with low energy consumption for future high-density information storage applications. PMID:27417902

  14. Sub-band transport mechanism and switching properties for resistive switching nonvolatile memories with structure of silver/aluminum oxide/p-type silicon

    SciTech Connect

    Liu, Yanhong; Li, La; Wang, Song; Gao, Ping; Pan, Lujun; Zhang, Jialiang; Zhou, Peng; Li, Jinhua; Weng, Zhankun

    2015-02-09

    In this paper, we discuss a model of sub-band in resistive switching nonvolatile memories with a structure of silver/aluminum oxide/p-type silicon (Ag/Al{sub x}O{sub y}/p-Si), in which the sub-band is formed by overlapping of wave functions of electron-occupied oxygen vacancies in Al{sub x}O{sub y} layer deposited by atomic layer deposition technology. The switching processes exhibit the characteristics of the bipolarity, discreteness, and no need of forming process, all of which are discussed deeply based on the model of sub-band. The relationships between the SET voltages and distribution of trap levels are analyzed qualitatively. The semiconductor-like behaviors of ON-state resistance affirm the sub-band transport mechanism instead of the metal filament mechanism.

  15. Four-state memory based on a giant and non-volatile converse magnetoelectric effect in FeAl/PIN-PMN-PT structure.

    PubMed

    Wei, Yanping; Gao, Cunxu; Chen, Zhendong; Xi, Shibo; Shao, Weixia; Zhang, Peng; Chen, Guilin; Li, Jiangong

    2016-07-15

    We report a stable, tunable and non-volatile converse magnetoelectric effect (ME) in a new type of FeAl/PIN-PMN-PT heterostructure at room temperature, with a giant electrical modulation of magnetization for which the maximum relative magnetization change (ΔM/M) is up to 66%. The 109° ferroelastic domain switching in the PIN-PMN-PT and coupling with the ferromagnetic (FM) film via uniaxial anisotropy originating from the PIN-PMN-PT (011) surface are the key roles in converse ME effect. We also propose here a new, four-state memory through which it is possible to modify the remanent magnetism state by adjusting the electric field. This work represents a helpful approach to securing electric-writing magnetic-reading with low energy consumption for future high-density information storage applications.

  16. Chemical solution deposition of SrBi{sub 2}Ta{sub 2}O{sub 9} (SBT) films for non-volatile memory applications

    SciTech Connect

    Lakeman, C.D.E.; Boyle, T.J.; Ruffner, J.A.; Rodriguez, M.A.

    1998-03-01

    SrBi{sub 2}Ta{sub 2}O{sub 9} (SBT) films have received considerable attention for use as non-volatile memory elements. The authors have developed a process to prepare SBT films with good ferroelectric properties at low temperatures. In this paper, they will present strategies used to optimize the properties of the films including film composition, the nature of the substrate (or bottom electrode) used, and the thermal processing cycle. Under appropriate conditions, {approximately} 1,700 {angstrom} films can be prepared which have a large switchable polarization (2P{sub r} > 10{micro}C/cm{sup 2}), and an operating voltage {le} 2.0 V.

  17. Analysis of a Memory Device Failure

    NASA Technical Reports Server (NTRS)

    Nicolas, David P.; Devaney, John; Gores, Mark; Dicken, Howard

    1998-01-01

    The recent failure of a vintage memory device presented a unique challenge to failure analysts. Normally device layouts, fabrication parameters and other technical information were available to assist the analyst in the analysis. However, this device was out of production for many years and the manufacturer was no longer in business, so the information was not available. To further complicate this analysis, the package leads were all but removed making additional electrical testing difficult. Under these conditions, new and innovative methods were used to analyze the failure. The external visual exam, radiography, PIND, and leak testing were performed with nominal results. Since electrical testing was precluded by the short lead lengths, the device was delidded to expose the internal structures for microscopic examination. No failure mechanism was identified. The available electrical data suggested an ESD or low level EOS type mechanism which left no visible surface damage. Due to parallel electrical paths, electrical probing on the chip failed to locate the failure site. Two non-destructive Scanning Electron Microscopy techniques, CIVA (Charge Induced Voltage Alteration) and EBIC (Electron Beam Induced Current), and a liquid crystal decoration technique which detects localized heating were employed to aid in the analysis. CIVA and EBIC isolated two faults in the input circuitry, and the liquid crystal technique further localized two hot spots in regions on two input gates. Removal of the glassivation and metallization revealed multiple failure sites located in the gate oxide of two input transistors suggesting machine (testing) induced damage.

  18. Memory and Spin Injection Devices Involving Half Metals

    DOE PAGES

    Shaughnessy, M.; Snow, Ryan; Damewood, L.; ...

    2011-01-01

    We suggest memory and spin injection devices fabricated with half-metallic materials and based on the anomalous Hall effect. Schematic diagrams of the memory chips, in thin film and bulk crystal form, are presented. Spin injection devices made in thin film form are also suggested. These devices do not need any external magnetic field but make use of their own magnetization. Only a gate voltage is needed. The carriers are 100% spin polarized. Memory devices may potentially be smaller, faster, and less volatile than existing ones, and the injection devices may be much smaller and more efficient than existing spin injectionmore » devices.« less

  19. Multistate nonvolatile straintronics controlled by a lateral electric field.

    PubMed

    Iurchuk, V; Doudin, B; Kundys, B

    2014-07-23

    We present a multifunctional and multistate permanent memory device based on lateral electric field control of a strained surface. Sub-coercive electrical writing of a remnant strain of a PZT substrate imprints stable and rewritable resistance changes on a CoFe overlayer. A proof-of-principle device, with the simplest resistance strain gage design, is shown as a memory cell exhibiting 17-memory states of high reproducibility and reliability for nonvolatile operations. Magnetoresistance of the film also depends on the cell state, and indicates a rewritable change of magnetic properties persisting in the remnant strain of the substrate. This makes it possible to combine strain, magnetic and resistive functionalities in a single memory element, and suggests that sub-coercive stress studies are of interest for straintronics applications.

  20. Quantized conductance in Ta2O5 based resistive random access memory devices

    NASA Astrophysics Data System (ADS)

    Sahu, V. K.; Misra, P.; Das, A. K.; Ajimsha, R. S.; Singh, B.

    2017-05-01

    We report quantised conductance in Au/Ta2O5/Pt structures grown by pulsed laser deposition. Quantum conduction phenomenon was observed during reset switching event of resistive switching in tantalum oxide (Ta2O5) thin films. Nonvolatile and repeatable electric field controlled unipolar resistive switching was clearly seen in Au/Ta2O5/Pt structures with good endurance. The quantum conduction phenomenon has been attributed to formation of nanometer scale conducting filaments which constraints the motion of electron in transverse direction resulting in quantisation of device conductance in half integer multiple of fundamental unit of conductance G0 (2e2/h). These quantised conductance results in well separated resistance states, suitable for realising futuristic multi-bit resistance switching memory.

  1. All-magnetic magnetoresistive random access memory based on four terminal mCell device

    NASA Astrophysics Data System (ADS)

    Bromberg, D. M.; Sumbul, H. E.; Zhu, J.-G.; Pileggi, L.

    2015-05-01

    Magnetoresistive random access memory (MRAM) is a promising candidate to enable fast, non-volatile storage on chip. In this paper, we present an MRAM design where each bitcell is comprised entirely of four-terminal magnetic devices ("mCells") with no CMOS access transistors. We show that this design can achieve significant energy and area savings compared to the standard one transistor-one magnetic tunnel junction (1T1MTJ) bitcell based design. We estimate a write energy of ≈5 fJ/bit based on bitline and wordline voltages that operate at less than 100 mV with projected area smaller than that possible with aggressively scaled 10 nm node FinFETs in the 1T1MTJ design.

  2. Semiconductor-based, large-area, flexible, electronic devices

    DOEpatents

    Goyal, Amit

    2011-03-15

    Novel articles and methods to fabricate the same resulting in flexible, large-area, triaxially textured, single-crystal or single-crystal-like, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

  3. LaTiON/LaON as band-engineered charge-trapping layer for nonvolatile memory applications

    NASA Astrophysics Data System (ADS)

    Huang, X. D.; Lai, P. T.; Sin, Johnny K. O.

    2012-07-01

    Charge-trapping characteristics of stacked LaTiON/LaON film were investigated based on Al/Al2O3/LaTiON-LaON/SiO2/Si (band-engineered MONOS) capacitors. The physical properties of the high- k films were analyzed by X-ray diffraction, transmission electron microscopy and X-ray photoelectron spectroscopy. The band profile of this band-engineered MONOS device was characterized by investigating the current-conduction mechanism. By adopting stacked LaTiON/LaON film instead of LaON film as charge-trapping layer, improved electrical properties can be achieved in terms of larger memory window (5.4 V at ±10-V sweeping voltage), higher program speed with lower operating gate voltage (2.1 V at 100-μs +6 V), and smaller charge loss rate at 125 °C, mainly due to the variable tunneling path of charge carriers under program/erase and retention modes (realized by the band-engineered charge-trapping layer), high trap density of LaTiON, and large barrier height at LaTiON/SiO2 (2.3 eV).

  4. PIYAS-Proceeding to Intelligent Service Oriented Memory Allocation for Flash Based Data Centric Sensor Devices in Wireless Sensor Networks

    PubMed Central

    Rizvi, Sanam Shahla; Chung, Tae-Sun

    2010-01-01

    Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS). This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks. PMID:22315541

  5. PIYAS-proceeding to intelligent service oriented memory allocation for flash based data centric sensor devices in wireless sensor networks.

    PubMed

    Rizvi, Sanam Shahla; Chung, Tae-Sun

    2010-01-01

    Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS). This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks.

  6. Laser Fabrication of Polymer Ferroelectric Nanostructures for Nonvolatile Organic Memory Devices.

    PubMed

    Martínez-Tong, Daniel E; Rodríguez-Rodríguez, Álvaro; Nogales, Aurora; García-Gutiérrez, Mari-Cruz; Pérez-Murano, Francesc; Llobet, Jordi; Ezquerra, Tiberio A; Rebollar, Esther

    2015-09-09

    Polymer ferroelectric laser-induced periodic surface structures (LIPSS) have been prepared on ferroelectric thin films of a poly(vinylidene fluoride-trifluoroethylene) copolymer. Although this copolymer does not absorb light at the laser wavelength, LIPSS on the copolymer can be obtained by forming a bilayer with other light-absorbing polymers. The ferroelectric nature of the structured bilayer was proven by piezoresponse force microscopy measurements. Ferroelectric hysteresis was found on both the bilayer and the laser-structured bilayer. We show that it is possible to write ferroelectric information at the nanoscale. The laser-structured ferroelectric bilayer showed an increase in the information storage density of an order of magnitude, in comparison to the original bilayer.

  7. Memory device for two-dimensional radiant energy array computers

    NASA Technical Reports Server (NTRS)

    Schaefer, D. H.; Strong, J. P., III (Inventor)

    1977-01-01

    A memory device for two dimensional radiant energy array computers was developed, in which the memory device stores digital information in an input array of radiant energy digital signals that are characterized by ordered rows and columns. The memory device contains a radiant energy logic storing device having a pair of input surface locations for receiving a pair of separate radiant energy digital signal arrays and an output surface location adapted to transmit a radiant energy digital signal array. A regenerative feedback device that couples one of the input surface locations to the output surface location in a manner for causing regenerative feedback is also included

  8. Microwave impedance imaging on semiconductor memory devices

    NASA Astrophysics Data System (ADS)

    Kundhikanjana, Worasom; Lai, Keji; Yang, Yongliang; Kelly, Michael; Shen, Zhi-Xun

    2011-03-01

    Microwave impedance microscopy (MIM) maps out the real and imaginary components of the tip-sample impedance, from which the local conductivity and dielectric constant distribution can be derived. The stray field contribution is minimized in our shielded cantilever design, enabling quantitative analysis of nano-materials and device structures. We demonstrate here that the MIM can spatially resolve the conductivity variation in a dynamic random access memory (DRAM) sample. With DC or low-frequency AC bias applied to the tip, contrast between n-doped and p-doped regions in the dC/dV images is observed, and p-n junctions are highlighted in the dR/dV images. The results can be directly compared with data taken by scanning capacitance microscope (SCM), which uses unshielded cantilevers and resonant electronics, and the MIM reveals more information of the local dopant concentration than SCM.

  9. Fabrication of poly(methyl methacrylate)-MoS{sub 2}/graphene heterostructure for memory device application

    SciTech Connect

    Shinde, Sachin M.; Tanemura, Masaki; Kalita, Golap

    2014-12-07

    Combination of two dimensional graphene and semi-conducting molybdenum disulfide (MoS{sub 2}) is of great interest for various electronic device applications. Here, we demonstrate fabrication of a hybridized structure with the chemical vapor deposited graphene and MoS{sub 2} crystals to configure a memory device. Elongated hexagonal and rhombus shaped MoS{sub 2} crystals are synthesized by sulfurization of thermally evaporated molybdenum oxide (MoO{sub 3}) thin film. Scanning transmission electron microscope studies reveal atomic level structure of the synthesized high quality MoS{sub 2} crystals. In the prospect of a memory device fabrication, poly(methyl methacrylate) (PMMA) is used as an insulating dielectric material as well as a supporting layer to transfer the MoS{sub 2} crystals. In the fabricated device, PMMA-MoS{sub 2} and graphene layers act as the functional and electrode materials, respectively. Distinctive bistable electrical switching and nonvolatile rewritable memory effect is observed in the fabricated PMMA-MoS{sub 2}/graphene heterostructure. The developed material system and demonstrated memory device fabrication can be significant for next generation data storage applications.

  10. Guide wire extension for shape memory polymer occlusion removal devices

    DOEpatents

    Maitland, Duncan J.; Small, IV, Ward; Hartman, Jonathan

    2009-11-03

    A flexible extension for a shape memory polymer occlusion removal device. A shape memory polymer instrument is transported through a vessel via a catheter. A flexible elongated unit is operatively connected to the distal end of the shape memory polymer instrument to enhance maneuverability through tortuous paths en route to the occlusion.

  11. Role of the nano amorphous interface in the crystallization of Sb2Te3 towards non-volatile phase change memory: insights from first principles.

    PubMed

    Wang, Xue-Peng; Chen, Nian-Ke; Li, Xian-Bin; Cheng, Yan; Liu, X Q; Xia, Meng-Jiao; Song, Z T; Han, X D; Zhang, S B; Sun, Hong-Bo

    2014-06-14

    The nano amorphous interface is important as it controls the phase transition for data storage. Yet, atomic scale insights into such kinds of systems are still rare. By first-principles calculations, we obtain the atomic interface between amorphous Si and amorphous Sb2Te3, which prevails in the series of Si-Sb-Te phase change materials. This interface model reproduces the experiment-consistent phenomena, i.e. the amorphous stability of Sb2Te3, which defines the data retention in phase change memory, and is greatly enhanced by the nano interface. More importantly, this method offers a direct platform to explore the intrinsic mechanism to understand the material function: (1) by steric effects through the atomic "channel" of the amorphous interface, the arrangement of the Te network is significantly distorted and is separated from the p-orbital bond angle in the conventional phase-change material; and (2) through the electronic "channel" of the amorphous interface, high localized electrons in the form of a lone pair are "projected" to Sb2Te3 from amorphous Si by a proximity effect. These factors set an effective barrier for crystallization and improve the amorphous stability, and thus data retention. The present research and scheme sheds new light on the engineering and manipulation of other key amorphous interfaces, such as Si3N4/Ge2Sb2Te5 and C/Sb2Te3, through first-principles calculations towards non-volatile phase change memory.

  12. Fabrication of all thin film magneto-electric coupled memory devices

    NASA Astrophysics Data System (ADS)

    Luykx, Arun

    -electric memory element that is non-volatile, low power consuming, and all-thin-film. By being non-volatile it shall retain its memory state, even after an external electric field has been removed. A low power and all thin film configuration allow this device to be potentially implemented on an integrated circuit scale.

  13. Probing Cu doped Ge0.3Se0.7 based resistance switching memory devices with random telegraph noise

    NASA Astrophysics Data System (ADS)

    Soni, R.; Meuffels, P.; Petraru, A.; Weides, M.; Kügeler, C.; Waser, R.; Kohlstedt, H.

    2010-01-01

    The ultimate sensitivity of any solid state device is limited by fluctuations. Fluctuations are manifestations of the thermal motion of matter and the discreteness of its structure which are also inherent ingredients during the resistive switching process of resistance random access memory (RRAM) devices. In quest for the role of fluctuations in different memory states and to develop resistive switching based nonvolatile memory devices, here we present our study on random telegraph noise (RTN) resistance fluctuations in Cu doped Ge0.3Se0.7 based RRAM cells. The influence of temperature and electric field on the RTN fluctuations is studied on different resistance states of the memory cells to reveal the dynamics of the underlying fluctuators. Our analysis indicates that the observed fluctuations could arise from thermally activated transpositions of Cu ions inside ionic or redox "double-site traps" triggering fluctuations in the current transport through a filamentary conducting path. Giant RTN fluctuations characterized by relative resistance variations of up to 50% in almost macroscopic samples clearly point to the existence of weak links with small effective cross-sectional areas along the conducting paths. Such large resistance fluctuations can be an important issue for the industrial applications of RRAM devices because they might lead to huge bit-error rates during reading cycles.

  14. Enhanced organic memory devices (OMEM) with a photochromic perhydro DTE as a transduction layer (Conference Presentation)

    NASA Astrophysics Data System (ADS)

    Cordes, Sandra; Kranz, Darius; Maibach, Eduard; Kempf, Maxim; Meerholz, Klaus

    2016-09-01

    In modern electronic systems memory elements are of fundamental importance for data storage. Especially solution-processable nonvolatile organic memories, which are inexpensive and can be manufactured on flexible substrates, are a promising alternative to brittle inorganic devices. Organic photochromic switchable compounds, mostly dithienylethenes (DTEs), are thermally stable, fatigue resistant and can undergo an electrically- or/and photo-induced ring-opening and -closing reaction which results in a change of energy levels. Due to the energetic difference in the highest occupied molecular orbital (HOMO) between the open and closed isomer, the DTE layer can be exploited as a switchable hole injection barrier that controls the electrical current in the diode. We demonstrated that a light-emitting organic memory (LE-OMEM) device with a perfluoro DTE transduction layer can be switched electrically via high current densities pulses and optically by irradiated light, with impressive current ON/OFF Ratios (OOR) of 10Λ2, 10Λ4 respectively. Currently we aim to minimize the barrier of the ON state and maximize the barrier of the OFF state by designing DTE molecules with larger differences in the HOMO energies of the two isomers yielding improved OOR values. By synthesizing perhydro derivates of DTE we achieved molecules with high HOMO levels and large ΔHOMO energies providing OMEM devices with excellent physical properties (OOR 1.4 x higher than perfluoro DTE). Due to the high HOMO level of the perhydro DTE utilization of hole transport layers (HTLs) is not necessary and thus manufacturing of OMEM devices is simplified.

  15. Low power NiN-based resistive switching memory device using Ti doping

    NASA Astrophysics Data System (ADS)

    Jeon, Dong Su; Park, Ju Hyun; Kim, Myung Ju; Kim, Tae Geun

    2016-10-01

    In this study, we investigated the properties of Ti-doped NiN-based resistive switching random access memories (ReRAMs) in comparison with both Al-doped and conventional NiN-based samples. The Ti dopants form metallic TiN particles in the nitride film, which induce local electric fields during the forming process causing filaments to form close to the TiN clusters. The TiN components in the filaments reduce the current level for the high resistive switching state (HRS) and low resistive switching state (LRS). In our testing, the Ti-doped sample had a current of 10 nA in the HRS and 23 μA in the LRS with a high on/off ratio (>103). This implies that the Ti doping effect enabled the sample to operate at low power. Furthermore, the Ti-doped samples also exhibited highly uniform operating parameters. In terms of reliability, the retention was measured to be >106 s at 85 °C, and the endurance was found to be at least 107 cycles. These results indicate that Ti-doped NiN-based ReRAM devices have significant advantages over other approaches for future nonvolatile memory devices.

  16. Investigation of the Hydrogen Silsesquioxane (HSQ) Electron Resist as Insulating Material in Phase Change Memory Devices

    NASA Astrophysics Data System (ADS)

    Zhou, Jiao; Ji, Hongkai; Lan, Tian; Yan, Junbing; Zhou, Wenli; Miao, Xiangshui

    2015-01-01

    Phase change random access memory (PCRAM) affords many advantages over conventional solid-state memories due to its nonvolatility, high speed, and scalability. However, high programming current to amorphize the crystalline phase through the melt-quench process of PCRAM, known as the RESET current, poses a critical challenge and has become the most significant obstacle for its widespread commercialization. In this work, an excellent negative tone resist for high resolution electron beam lithography, hydrogen silsesquioxane (HSQ), has been investigated as the insulating material which locally blocks the contact between the bottom electrode and the phase change material in PCRAM devices. Fabrications of the highly scaled HSQ nanopore arrays (as small as 16 nm) are presented. The insulating properties of the HSQ material are studied, especially under e-beam exposure plus thermal curing. Some other critical issues about the thickness adjustment of HSQ films and the influence of the PCRAM electrode on electron scattering in e-beam lithography are discussed. In addition, the HSQ material was successfully integrated into the PCRAM devices, achieving ultra-low RESET current (sub-100 μA), outstanding on/off ratios (~50), and improved endurance at tens of nanometers.

  17. Investigation of the Hydrogen Silsesquioxane (HSQ) Electron Resist as Insulating Material in Phase Change Memory Devices

    NASA Astrophysics Data System (ADS)

    Zhou, Jiao; Ji, Hongkai; Lan, Tian; Yan, Junbing; Zhou, Wenli; Miao, Xiangshui

    2014-09-01

    Phase change random access memory (PCRAM) affords many advantages over conventional solid-state memories due to its nonvolatility, high speed, and scalability. However, high programming current to amorphize the crystalline phase through the melt-quench process of PCRAM, known as the RESET current, poses a critical challenge and has become the most significant obstacle for its widespread commercialization. In this work, an excellent negative tone resist for high resolution electron beam lithography, hydrogen silsesquioxane (HSQ), has been investigated as the insulating material which locally blocks the contact between the bottom electrode and the phase change material in PCRAM devices. Fabrications of the highly scaled HSQ nanopore arrays (as small as 16 nm) are presented. The insulating properties of the HSQ material are studied, especially under e-beam exposure plus thermal curing. Some other critical issues about the thickness adjustment of HSQ films and the influence of the PCRAM electrode on electron scattering in e-beam lithography are discussed. In addition, the HSQ material was successfully integrated into the PCRAM devices, achieving ultra-low RESET current (sub-100 μA), outstanding on/off ratios (~50), and improved endurance at tens of nanometers.

  18. Magnetic Random Access Memory based non-volatile asynchronous Muller cell for ultra-low power autonomous applications

    SciTech Connect

    Di Pendina, G. E-mail: eldar.zianbetov@cea.fr Zianbetov, E. E-mail: eldar.zianbetov@cea.fr; Beigne, E. E-mail: eldar.zianbetov@cea.fr

    2015-05-07

    Micro and nano electronic integrated circuit domain is today mainly driven by the advent of the Internet of Things for which the constraints are strong, especially in terms of power consumption and autonomy, not only during the computing phases but also during the standby or idle phases. In such ultra-low power applications, the circuit has to meet new constraints mainly linked to its changing energetic environment: long idle phases, automatic wake up, data back-up when the circuit is sporadically turned off, and ultra-low voltage power supply operation. Such circuits have to be completely autonomous regarding their unstable environment, while remaining in an optimum energetic configuration. Therefore, we propose in this paper the first MRAM-based non-volatile asynchronous Muller cell. This cell has been simulated and characterized in a very advanced 28 nm CMOS fully depleted silicon-on-insulator technology, presenting good power performance results due to an extremely efficient body biasing control together with ultra-wide supply voltage range from 160 mV up to 920 mV. The leakage current can be reduced to 154 pA thanks to reverse body biasing. We also propose an efficient standard CMOS bulk version of this cell in order to be compatible with different fabrication processes.

  19. Magnetic Random Access Memory based non-volatile asynchronous Muller cell for ultra-low power autonomous applications

    NASA Astrophysics Data System (ADS)

    Di Pendina, G.; Zianbetov, E.; Beigne, E.

    2015-05-01

    Micro and nano electronic integrated circuit domain is today mainly driven by the advent of the Internet of Things for which the constraints are strong, especially in terms of power consumption and autonomy, not only during the computing phases but also during the standby or idle phases. In such ultra-low power applications, the circuit has to meet new constraints mainly linked to its changing energetic environment: long idle phases, automatic wake up, data back-up when the circuit is sporadically turned off, and ultra-low voltage power supply operation. Such circuits have to be completely autonomous regarding their unstable environment, while remaining in an optimum energetic configuration. Therefore, we propose in this paper the first MRAM-based non-volatile asynchronous Muller cell. This cell has been simulated and characterized in a very advanced 28 nm CMOS fully depleted silicon-on-insulator technology, presenting good power performance results due to an extremely efficient body biasing control together with ultra-wide supply voltage range from 160 mV up to 920 mV. The leakage current can be reduced to 154 pA thanks to reverse body biasing. We also propose an efficient standard CMOS bulk version of this cell in order to be compatible with different fabrication processes.

  20. Transistor and memory devices based on novel organic and biomaterials

    NASA Astrophysics Data System (ADS)

    Tseng, Jia-Hung

    Organic semiconductor devices have aroused considerable interest because of the enormous potential in many technological applications. Organic electroluminescent devices have been extensively applied in display technology. Rapid progress has also been made in transistor and memory devices. This thesis considers aspects of the transistor based on novel organic single crystals and memory devices using hybrid nanocomposites comprising polymeric/inorganic nanoparticles, and biomolecule/quantum dots. Organic single crystals represent highly ordered structures with much less imperfections compared to amorphous thin films for probing the intrinsic charge transport in transistor devices. We demonstrate that free-standing, thin organic single crystals with natural flexing ability can be fabricated as flexible transistors. We study the surface properties of the organic crystals to determine a nearly perfect surface leading to high performance transistors. The flexible transistors can maintain high performance under reversible bending conditions. Because of the high quality crystal technique, we further develop applications on organic complementary circuits and organic single crystal photovoltaics. In the second part, two aspects of memory devices are studied. We examine the charge transfer process between conjugated polymers and metal nanoparticles. This charge transfer process is essential for the conductance switching in nanoseconds to induce the memory effect. Under the reduction condition, the charge transfer process is eliminated as well as the memory effect, raising the importance of coupling between conjugated systems and nanoparticle accepters. The other aspect of memory devices focuses on the interaction of virus biomolecules with quantum dots or metal nanoparticles in the devices. We investigate the impact of memory function on the hybrid bio-inorganic system. We perform an experimental analysis of the charge storage activation energy in tobacco mosaic virus with

  1. Ferroelectric memory based on nanostructures

    PubMed Central

    2012-01-01

    In the past decades, ferroelectric materials have attracted wide attention due to their applications in nonvolatile memory devices (NVMDs) rendered by the electrically switchable spontaneous polarizations. Furthermore, the combination of ferroelectric and nanomaterials opens a new route to fabricating a nanoscale memory device with ultrahigh memory integration, which greatly eases the ever increasing scaling and economic challenges encountered in the traditional semiconductor industry. In this review, we summarize the recent development of the nonvolatile ferroelectric field effect transistor (FeFET) memory devices based on nanostructures. The operating principles of FeFET are introduced first, followed by the discussion of the real FeFET memory nanodevices based on oxide nanowires, nanoparticles, semiconductor nanotetrapods, carbon nanotubes, and graphene. Finally, we present the opportunities and challenges in nanomemory devices and our views on the future prospects of NVMDs. PMID:22655750

  2. Multilevel non-volatile data storage utilizing common current hysteresis of networked single walled carbon nanotubes.

    PubMed

    Hwang, Ihn; Wang, Wei; Hwang, Sun Kak; Cho, Sung Hwan; Kim, Kang Lib; Jeong, Beomjin; Huh, June; Park, Cheolmin

    2016-05-21

    The characteristic source-drain current hysteresis frequently observed in field-effect transistors with networked single walled carbon-nanotube (NSWNT) channels is problematic for the reliable switching and sensing performance of devices. But the two distinct current states of the hysteresis curve at a zero gate voltage can be useful for memory applications. In this work, we demonstrate a novel non-volatile transistor memory with solution-processed NSWNTs which are suitable for multilevel data programming and reading. A polymer passivation layer with a small amount of water employed on the top of the NSWNT channel serves as an efficient gate voltage dependent charge trapping and de-trapping site. A systematic investigation evidences that the water mixed in a polymer passivation solution is critical for reliable non-volatile memory operation. The optimized device is air-stable and temperature-resistive up to 80 °C and exhibits excellent non-volatile memory performance with an on/off current ratio greater than 10(4), a switching time less than 100 ms, data retention longer than 4000 s, and write/read endurance over 100 cycles. Furthermore, the gate voltage dependent charge injection mediated by water in the passivation layer allowed for multilevel operation of our memory in which 4 distinct current states were programmed repetitively and preserved over a long time period.

  3. Semiconductor-based, large-area, flexible, electronic devices on {110}<100> oriented substrates

    SciTech Connect

    Goyal, Amit

    2014-08-05

    Novel articles and methods to fabricate the same resulting in flexible, oriented, semiconductor-based, electronic devices on {110}<100> textured substrates are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

  4. [100] or [110] aligned, semiconductor-based, large-area, flexible, electronic devices

    SciTech Connect

    Goyal, Amit

    2015-03-24

    Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

  5. Polymer-based resistive memory materials and devices.

    PubMed

    Lin, Wen-Peng; Liu, Shu-Juan; Gong, Tao; Zhao, Qiang; Huang, Wei

    2014-01-01

    Due to the advantages of good scalability, flexibility, low cost, ease of processing, 3D-stacking capability, and large capacity for data storage, polymer-based resistive memories have been a promising alternative or supplementary devices to conventional inorganic semiconductor-based memory technology, and attracted significant scientific interest as a new and promising research field. In this review, we first introduced the general characteristics of the device structures and fabrication, memory effects, switching mechanisms, and effects of electrodes on memory properties associated with polymer-based resistive memory devices. Subsequently, the research progress concerning the use of single polymers or polymer composites as active materials for resistive memory devices has been summarized and discussed. In particular, we consider a rational approach to their design and discuss how to realize the excellent memory devices and understand the memory mechanisms. Finally, the current challenges and several possible future research directions in this field have also been discussed. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  6. Multilevel nonvolatile flexible organic field-effect transistor memories employing polyimide electrets with different charge-transfer effects.

    PubMed

    Yu, An-Dih; Tung, Wei-Yao; Chiu, Yu-Cheng; Chueh, Chu-Chen; Liou, Guey-Sheng; Chen, Wen-Chang

    2014-06-01

    The electrical memory characteristics of the n-channel organic field-effect transistors (OFETs) employing diverse polyimide (PI) electrets are reported. The synthesized PIs comprise identical electron donor and three different building blocks with gradually increasing electron-accepting ability. The distinct charge-transfer capabilities of these PIs result in varied type of memory behaviors from the write-one-read-many (WORM) to flash type. Finally, a prominent flexible WORM-type transistor memory is demonstrated and shows not only promising write-many-read-many (WMRM) multilevel data storage but also excellent mechanical and retention stability. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  7. Enhanced non-volatile memory characteristics with quattro-layer graphene nanoplatelets vs. 2.85-nm Si nanoparticles with asymmetric Al2O 3/HfO 2 tunnel oxide.

    PubMed

    El-Atab, Nazek; Turgut, Berk Berkan; Okyay, Ali K; Nayfeh, Munir; Nayfeh, Ammar

    2015-12-01

    In this work, we demonstrate a non-volatile metal-oxide semiconductor (MOS) memory with Quattro-layer graphene nanoplatelets as charge storage layer with asymmetric Al2O3/HfO2 tunnel oxide and we compare it to the same memory structure with 2.85-nm Si nanoparticles charge trapping layer. The results show that graphene nanoplatelets with Al2O3/HfO2 tunnel oxide allow for larger memory windows at the same operating voltages, enhanced retention, and endurance characteristics. The measurements are further confirmed by plotting the energy band diagram of the structures, calculating the quantum tunneling probabilities, and analyzing the charge transport mechanism. Also, the required program time of the memory with ultra-thin asymmetric Al2O3/HfO2 tunnel oxide with graphene nanoplatelets storage layer is calculated under Fowler-Nordheim tunneling regime and found to be 4.1 ns making it the fastest fully programmed MOS memory due to the observed pure electrons storage in the graphene nanoplatelets. With Si nanoparticles, however, the program time is larger due to the mixed charge storage. The results confirm that band-engineering of both tunnel oxide and charge trapping layer is required to enhance the current non-volatile memory characteristics.

  8. Light-bias coupling erase process for non-volatile zinc tin oxide TFT memory with a nickel nanocrystals charge trap layer

    NASA Astrophysics Data System (ADS)

    Li, Jeng-Ting; Liu, Li-Chih; Ke, Po-Hsien; Chen, Jen-Sue; Jeng, Jiann-Shing

    2016-03-01

    A nonvolatile charge trapping memory is demonstrated on a thin film transistor (TFT) using a solution processed ultra-thin (~7 nm) zinc tin oxide (ZTO) semiconductor layer with an Al2O3/Ni-nanocrystals (NCs)/SiO2 dielectric stack. A positive threshold voltage (V TH) shift of 7 V is achieved at gate programming voltage of 40 V for 1 s but the state will not be erased by applying negative gate voltage. However, the programmed V TH shift can be expediently erased by applying a gate voltage of  -10 V in conjunction with visible light illumination for 1 s. It is found that the sub-threshold swing (SS) deteriorates slightly under light illumination, indicating that photo-ionized oxygen vacancies (V\\text{o}+ and/or V\\text{o}++ ) are trapped at the interface between Al2O3 and ZTO, which assists the capture of electrons discharged from the Ni NCs charge trapping layer. The light-bias coupling action and the role of ultra-thin ZTO thickness are discussed to elucidate the efficient erasing mechanism.

  9. Different importance of the volatile and non-volatile fractions of an olfactory signature for individual social recognition in rats versus mice and short-term versus long-term memory.

    PubMed

    Noack, Julia; Richter, Karin; Laube, Gregor; Haghgoo, Hojjat Allah; Veh, Rüdiger W; Engelmann, Mario

    2010-11-01

    When tested in the olfactory cued social recognition/discrimination test, rats and mice differ in their retention of a recognition memory for a previously encountered conspecific juvenile: Rats are able to recognize a given juvenile for approximately 45 min only whereas mice show not only short-term, but also long-term recognition memory (≥ 24 h). Here we modified the social recognition/social discrimination procedure to investigate the neurobiological mechanism(s) underlying the species differences. We presented a conspecific juvenile repeatedly to the experimental subjects and monitored the investigation duration as a measure for recognition. Presentation of only the volatile fraction of the juvenile olfactory signature was sufficient for both short- and long-term recognition in mice but not rats. Applying additional volatile, mono-molecular odours to the "to be recognized" juveniles failed to affect short-term memory in both species, but interfered with long-term recognition in mice. Finally immunocytochemical analysis of c-Fos as a marker for cellular activation, revealed that juvenile exposure stimulated areas involved in the processing of olfactory signals in both the main and the accessory olfactory bulb in mice. In rats, we measured an increased c-Fos synthesis almost exclusively in cells of the accessory olfactory bulb. Our data suggest that the species difference in the retention of social recognition memory is based on differences in the processing of the volatile versus non-volatile fraction of the individuals' olfactory signature. The non-volatile fraction is sufficient for retaining a short-term social memory only. Long-term social memory - as observed in mice - requires a processing of both the volatile and non-volatile fractions of the olfactory signature. Copyright © 2010 Elsevier Inc. All rights reserved.

  10. Electrically Variable or Programmable Nonvolatile Capacitors

    NASA Technical Reports Server (NTRS)

    Shangqing, Liu; NaiJuan, Wu; Ignatieu, Alex; Jianren, Li

    2009-01-01

    Electrically variable or programmable capacitors based on the unique properties of thin perovskite films are undergoing development. These capacitors show promise of overcoming two important deficiencies of prior electrically programmable capacitors: Unlike in the case of varactors, it is not necessary to supply power continuously to make these capacitors retain their capacitance values. Hence, these capacitors may prove useful as components of nonvolatile analog and digital electronic memories. Unlike in the case of ferroelectric capacitors, it is possible to measure the capacitance values of these capacitors without changing the values. In other words, whereas readout of ferroelectric capacitors is destructive, readout of these capacitors can be nondestructive. A capacitor of this type is a simple two terminal device. It includes a thin film of a suitable perovskite as the dielectric layer, sandwiched between two metal or metal oxide electrodes (for example, see Figure 1). The utility of this device as a variable capacitor is based on a phenomenon, known as electrical-pulse-induced capacitance (EPIC), that is observed in thin perovskite films and especially in those thin perovskite films that exhibit the colossal magnetoresistive (CMR) effect. In EPIC, the application of one or more electrical pulses that exceed a threshold magnitude (typically somewhat less than 1 V) gives rise to a nonvolatile change in capacitance. The change in capacitance depends on the magnitude duration, polarity, and number of pulses. It is not necessary to apply a magnetic field or to cool the device below (or heat it above) room temperature to obtain EPIC. Examples of suitable CMR perovskites include Pr(1-x)Ca(x)MnO3, La(1-x)S-r(x)MnO3,and Nb(1-x)Ca(x)MnO3. Figure 2 is a block diagram showing an EPIC capacitor connected to a circuit that can vary the capacitance, measure the capacitance, and/or measure the resistance of the capacitor.

  11. {100}<100> or 45.degree.-rotated {100}<100>, semiconductor-based, large-area, flexible, electronic devices

    DOEpatents

    Goyal, Amit [Knoxville, TN

    2012-05-15

    Novel articles and methods to fabricate the same resulting in flexible, {100}<100> or 45.degree.-rotated {100}<100> oriented, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

  12. Metal induced crystallized poly-Si-based conductive bridge resistive switching memory device with one transistor and one resistor architecture

    NASA Astrophysics Data System (ADS)

    Chand, Umesh; Huang, Chun-Yang; Kumar, Dayanand; Tseng, Tseung-Yuen

    2015-11-01

    In this letter, the metal induced crystallization (MIC) process is used in the Si-based conductive bridging resistive random access memory (CBRAM) application. The amorphous Si (a-Si) is transformed to crystallized poly-silicon (poly-Si) at a low temperature by using Ni metal for inducing poly-Si to provide the resistive switching. The MIC process can produce a highly preferred orientation poly-Si film, which can create the exact paths or grain boundaries through the top and down electrodes in the present CBRAM device. The grain boundary in MIC poly-Si layer can confine the conductive filament of metal bridging growth in it, which can improve the switching fluctuation behavior in the nonvolatile memory application. Compared with the a-Si based device, a significant improvement in terms of resistive switching parameters such as stability and resistance distribution is demonstrated in the MIC poly-Si CBRAM device. Moreover, the well-behaved memory performance, such as high ON/OFF resistance ratio (4 order), a large AC endurance (106), and good retention characteristics (104 s at 125 °C) are achieved in the Cu/poly-Si/n+-Si CMOS compatible cross bar structure.

  13. Effect of Mechanical Loads on Stability of Nanodomains in Ferroelectric Ultrathin Films: Towards Flexible Erasing of the Non-Volatile Memories

    PubMed Central

    Chen, W. J.; Zheng, Yue; Xiong, W. M.; Feng, Xue; Wang, Biao; Wang, Ying

    2014-01-01

    Intensive investigations have been drawn on nanoscale ferroelectrics for their prospective applications such as developing memory devices. In contrast with the commonly used electrical means to process (i.e., read, write or erase) the information carried by ferroelectric domains, at present, mechanisms of non-electrical processing ferroelectric domains are relatively lacking. Here we make a systematical investigation on the stability of 180° cylindrical domains in ferroelectric nanofilms subjected to macroscopic mechanical loads, and explore the possibility of mechanical erasing. Effects of domain size, film thickness, temperature and different mechanical loads, including uniform strain, cylindrical bending and wavy bending, have been revealed. It is found that the stability of a cylindrical domain depends on its radius, temperature and film thickness. More importantly, mechanical loads have great controllability on the stability of cylindrical domains, with the critical radius nonlinearly sensitive to both strain and strain gradient. This indicates that erasing cylindrical domain can be achieved by changing the strain state of nanofilm. Based on the calculated phase diagrams, we successfully simulate several mechanical erasing processes on 4 × 4 bits memory devices. Our study sheds light on prospective device applications of ferroelectrics involving mechanical loads, such as flexible memory devices and other micro-electromechanical systems. PMID:24938187

  14. Effect of mechanical loads on stability of nanodomains in ferroelectric ultrathin films: towards flexible erasing of the non-volatile memories.

    PubMed

    Chen, W J; Zheng, Yue; Xiong, W M; Feng, Xue; Wang, Biao; Wang, Ying

    2014-06-18

    Intensive investigations have been drawn on nanoscale ferroelectrics for their prospective applications such as developing memory devices. In contrast with the commonly used electrical means to process (i.e., read, write or erase) the information carried by ferroelectric domains, at present, mechanisms of non-electrical processing ferroelectric domains are relatively lacking. Here we make a systematical investigation on the stability of 180° cylindrical domains in ferroelectric nanofilms subjected to macroscopic mechanical loads, and explore the possibility of mechanical erasing. Effects of domain size, film thickness, temperature and different mechanical loads, including uniform strain, cylindrical bending and wavy bending, have been revealed. It is found that the stability of a cylindrical domain depends on its radius, temperature and film thickness. More importantly, mechanical loads have great controllability on the stability of cylindrical domains, with the critical radius nonlinearly sensitive to both strain and strain gradient. This indicates that erasing cylindrical domain can be achieved by changing the strain state of nanofilm. Based on the calculated phase diagrams, we successfully simulate several mechanical erasing processes on 4 × 4 bits memory devices. Our study sheds light on prospective device applications of ferroelectrics involving mechanical loads, such as flexible memory devices and other micro-electromechanical systems.

  15. Switching characteristics in TiO2/ZnO double layer resistive switching memory device

    NASA Astrophysics Data System (ADS)

    Jain, Praveen K.; Salim, Mohammad; Chand, Umesh; Periasamy, C.

    2017-06-01

    The uniform and reliable resistive switching characteristics of a ZnO based resistive random access memory device with a thin TiO2 layer are successfully investigated. In this study, the effect of thickness of the TiO2 layer on switching characteristics has been investigated. Compared with different thicknesses of the thin TiO2 layer, the remarkably improved resistive switching parameters such as lower forming voltage and the narrower variation of endurance are achieved for a TiO2 layer of thickness 2 nm. The forming voltages are dependent on the TiO2 thickness which supports the idea that forming process is governed by a dielectric breakdown-like phenomenon. The Ti/TiO2/ZnO/Pt device with the 2 nm TiO2 layer exhibits good DC endurance up to 103 cycles. The non-volatility of data storage is further confirmed by retention test measured at room temperature. It has been observed that both low resistance state and high resistance state do not exhibit any degradation for more than 104 s.

  16. Organic memory device with polyaniline nanoparticles embedded as charging elements

    NASA Astrophysics Data System (ADS)

    Kim, Yo-Han; Kim, Minkeun; Oh, Sewook; Jung, Hunsang; Kim, Yejin; Yoon, Tae-Sik; Kim, Yong-Sang; Ho Lee, Hyun

    2012-04-01

    Polyaniline nanoparticles (PANI NPs) were synthesized and fabricated as charging elements for organic memory devices. The PANI NPs charging layer was self-assembled by epoxy-amine bonds between 3-glycidylpropyl trimethoxysilane functionalized dielectrics and PANI NPs. A memory window of 5.8 V (ΔVFB) represented by capacitance-voltage hysteresis was obtained for metal-pentacene-insulator-silicon capacitor. In addition, program/erase operations controlled by gate bias (-/+90 V) were demonstrated in the PANI NPs embedded pentacene thin film transistor device with polyvinylalcohol dielectric on flexible polyimide substrate. These results can be extended to development of fully organic-based electronic device.

  17. High Density Memory Based on Quantum Device Technology

    NASA Technical Reports Server (NTRS)

    vanderWagt, Paul; Frazier, Gary; Tang, Hao

    1995-01-01

    We explore the feasibility of ultra-high density memory based on quantum devices. Starting from overall constraints on chip area, power consumption, access speed, and noise margin, we deduce boundaries on single cell parameters such as required operating voltage and standby current. Next, the possible role of quantum devices is examined. Since the most mature quantum device, the resonant tunneling diode (RTD) can easily be integrated vertically, it naturally leads to the issue of 3D integrated memory. We propose a novel method of addressing vertically integrated bistable two-terminal devices, such as resonant tunneling diodes (RTD) and Esaki diodes, that avoids individual physical contacts. The new concept has been demonstrated experimentally in memory cells of field effect transistors (FET's) and stacked RTD's.

  18. 76 FR 55417 - In the Matter of Certain Dynamic Random Access Memory and Nand Flash Memory Devices and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-09-07

    ... COMMISSION In the Matter of Certain Dynamic Random Access Memory and Nand Flash Memory Devices and Products... States after importation of certain dynamic random access memory and NAND flash memory devices and... patent''). The amended complaint further alleges that an industry in the United States exists as required...

  19. Stretchable Motion Memory Devices Based on Mechanical Hybrid Materials.

    PubMed

    Liu, Yaqing; Liu, Zhiyuan; Zhu, Bowen; Yu, Jiancan; He, Ke; Leow, Wan Ru; Wang, Ming; Chandran, Bevita K; Qi, Dianpeng; Wang, Hong; Chen, Geng; Xu, Cai; Chen, Xiaodong

    2017-09-01

    Animals possess various functional systems such as sensory, nervous, and motor systems, which show effective cooperation in order to realize complicated and intelligent behaviors. This inspires rational designs for the integration of individual electronic devices to exhibit a series of functions, such as sensing, memory, and feedback. Inspired by the fact that humans can monitor and memorize various body motions, a motion memory device is developed to mimic this biological process. In this work, mechanical hybrid substrates are introduced, in which rigid memory devices and stretchable strain sensors are integrated into a single module, which enables them to work cooperatively in the wearable state. When attached to the joints of limbs, the motion memory device can detect the deformations caused by limb motions and simultaneously store the corresponding information in the memory device. This work would be valuable in materials design and electronics technology toward the realization of wearable and multifunctional electronic modules. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  20. Memory and coupling in nanocrystal optoelectronic devices

    NASA Astrophysics Data System (ADS)

    Fairfield, Jessamyn A.

    Optoelectronic devices incorporating semiconducting nanocrystals are promising for many potential applications. Nanocrystals whose size is below the exciton Bohr radius have optical absorption and emission that is tunable with size, due to the quantum confinement of the charge carriers. However, the same confinement that yields these optical properties also makes electrical conduction in a film of nanocrystals occur via tunneling, due to the high energy barrier between nanocrystals. Hence, the extraction of photo-generated charge carriers presents a significant challenge. Several approaches to optimizing the reliability and efficiency of optoelectronic devices using semiconducting nanocrystals are explored herein. Force microscopy is used to investigate charge behavior in nanocrystal films. Plasmonic structures are lithographically defined to enhance electric field and thus charge collection efficiency in two-electrode nanocrystal devices illuminated at plasmonically resonant wavelengths. Graphene substrates are shown to couple electronically with nanocrystal films, improving device conduction while maintaining carrier quantum confinement within the nanocrystal. And finally, the occupancy of charge carrier traps is shown to both directly impact the temperature-dependent photocurrent behavior, and be tunable using a combination of illumination and electric field treatments. Trap population manipulation is robustly demonstrated and verified using a variety of wavelength, intensity, and time-dependent measurements of photocurrent in nanogap nanocrystal devices, emphasizing the importance of measurement history and the possibility of advanced device behavior tuning based on desired operating conditions. Each of these experiments reveals a path toward understanding and optimizing semiconducting nanocrystal optoelectronic devices.

  1. Comparative study of CNT, silicon nanowire and fullerene embedded multilayer high-k gate dielectric MOS memory devices

    NASA Astrophysics Data System (ADS)

    Sengupta, Amretashis; Sarkar, Chandan Kumar; Requejo, Felix G.

    2011-10-01

    Here, we present a comparative theoretical study on stacked (multilayer) gate dielectric MOS memory devices, having a metallic/semiconducting carbon nanotube (CNT), silicon nanowire (Si NW) and fullerene (C60) embedded nitride layer acting as a floating gate. Two types of devices, one with HfO2-SiO2 stack (stack-1) and the other with La2O3-SiO2 stack (stack-2) as the tunnel oxide were compared. We evaluated the effective barrier height, the dielectric constant and the effective electron mobility in the composite gate dielectric with the Maxwell-Garnett effective medium theory. Thereafter applying the WKB approximation, we simulated the Fowler-Nordheim (F-N) tunnelling/writing current and the direct tunnelling/leakage current in these devices. We evaluated the I-V characteristics, the charge decay and also the impact of CNT/Si NW aspect ratio and the volume fraction on the effective barrier height and the write voltage, respectively. We also simulated the write time, retention time and the erase time of these MOS devices. Based on the simulation results, it was concluded that the metallic CNT embedded stack-1 device offered the best performance in terms of higher F-N tunnelling current, lower direct tunnelling current and lesser write voltage and write time compared with the other devices. In case of direct tunnelling leakage and retention time it was found that the met CNT embedded stack-2 device showed better characteristics. For erasing, however, the C60 embedded stack-1 device showed the smallest erase time. When compared with earlier reports, it was seen that CNT, C60 and Si NW embedded devices all performed better than nanocrystalline Si embedded MOS non-volatile memories.

  2. Non-volatile polymer electrolyte based on poly(propylene carbonate), ionic liquid, and lithium perchlorate for electrochromic devices.

    PubMed

    Zhou, Dan; Zhou, Rui; Chen, Chuanxiang; Yee, Wu-Aik; Kong, Junhua; Ding, Guoqiang; Lu, Xuehong

    2013-06-27

    A series of solvent-free ionic liquid (IL)-based polymer electrolytes composed of amorphous and biodegradable poly(propylene carbonate) (PPC) host, LiClO4, and 1-butyl-3-methylimidazolium tetrafluoroborate (BMIM(+)BF4(-)) were prepared and characterized for the first time. FTIR studies reveal that the interaction between PPC chains and imidazolium cations weakens the complexation between PPC chains and Li(+) ions. Thermal analysis (DSC and TGA) results show that the incorporation of BMIM(+)BF4(-) into PPC/LiClO4 remarkably decreases the glass transition temperature and improves the thermal stability of the electrolytes. AC impedance results show that the ionic conductivities of the electrolytes are significantly increased with the increase of BMIM(+)BF4(-) amount, the ambient ionic conductivity of the electrolyte at a PPC/LiClO4/BMIM(+)BF4(-) weight ratio of 1/0.2/3 is 1.5 mS/cm, and the ionic transport behavior follows the Arrhenius equation. Both PPC/LiClO4/BMIM(+)BF4(-) and PPC/BMIM(+)BF4(-) electrolytes were applied in electrochromic devices with polyaniline as the electrochromic layer. The PPC/LiClO4/BMIM(+)BF4(-)-based device exhibits much better electrochromic performance in terms of optical contrast and switching time due to the presence of much smaller cations.

  3. Nonvolatile optically-erased colloidal memristors

    NASA Astrophysics Data System (ADS)

    Huebner, Christopher F.; Tsyalkovsky, Volodymyr; Bandera, Yuriy; Burdette, Mary K.; Shetzline, Jamie A.; Tonkin, Charles; Creager, Stephen E.; Foulger, Stephen H.

    2015-01-01

    A nonconjugated methacrylate terpolymer containing carbazole moieties (electron donors), 1,3,4-oxadiazole moieties (electron acceptors), and Coumarin-6 in the pendant groups was synthesized via free radical copolymerization of methacrylate monomers containing the respective functional groups. The terpolymer was formed into 57 nm particles through a mini-emulsion route. For a thin 100 nm film of the fused particles sandwiched between an indium-tin oxide (ITO) electrode and an Al electrode, the structure behaved as a nonvolatile flash (rewritable) memory with accessible electronic states that could be written, read, and optically erased. The device exhibited a turn-on voltage of ca. -4.5 VDC and a 106 current ratio. A device in the ON high conductance state could be reverted to the OFF state with a short exposure to a 360 nm light source. The development of semiconducting colloidal inks that can be converted into electroactive devices through a continuous processing method is a critical step in the widespread adoption of these 2D manufacturing technologies for printed electronics.

  4. Pattern recognition with magnonic holographic memory device

    SciTech Connect

    Kozhevnikov, A.; Dudko, G.; Filimonov, Y.; Gertz, F.; Khitun, A.

    2015-04-06

    In this work, we present experimental data demonstrating the possibility of using magnonic holographic devices for pattern recognition. The prototype eight-terminal device consists of a magnetic matrix with micro-antennas placed on the periphery of the matrix to excite and detect spin waves. The principle of operation is based on the effect of spin wave interference, which is similar to the operation of optical holographic devices. Input information is encoded in the phases of the spin waves generated on the edges of the magnonic matrix, while the output corresponds to the amplitude of the inductive voltage produced by the interfering spin waves on the other side of the matrix. The level of the output voltage depends on the combination of the input phases as well as on the internal structure of the magnonic matrix. Experimental data collected for several magnonic matrixes show the unique output signatures in which maxima and minima correspond to specific input phase patterns. Potentially, magnonic holographic devices may provide a higher storage density compare to optical counterparts due to a shorter wavelength and compatibility with conventional electronic devices. The challenges and shortcoming of the magnonic holographic devices are also discussed.

  5. Pattern recognition with magnonic holographic memory device

    NASA Astrophysics Data System (ADS)

    Kozhevnikov, A.; Gertz, F.; Dudko, G.; Filimonov, Y.; Khitun, A.

    2015-04-01

    In this work, we present experimental data demonstrating the possibility of using magnonic holographic devices for pattern recognition. The prototype eight-terminal device consists of a magnetic matrix with micro-antennas placed on the periphery of the matrix to excite and detect spin waves. The principle of operation is based on the effect of spin wave interference, which is similar to the operation of optical holographic devices. Input information is encoded in the phases of the spin waves generated on the edges of the magnonic matrix, while the output corresponds to the amplitude of the inductive voltage produced by the interfering spin waves on the other side of the matrix. The level of the output voltage depends on the combination of the input phases as well as on the internal structure of the magnonic matrix. Experimental data collected for several magnonic matrixes show the unique output signatures in which maxima and minima correspond to specific input phase patterns. Potentially, magnonic holographic devices may provide a higher storage density compare to optical counterparts due to a shorter wavelength and compatibility with conventional electronic devices. The challenges and shortcoming of the magnonic holographic devices are also discussed.

  6. Programmable Analog Memory Resistors For Electronic Neural Networks

    NASA Technical Reports Server (NTRS)

    Ramesham, Rajeshuni; Thakoor, Sarita; Daud, Taher; Thakoor, Anilkumar P.

    1990-01-01

    Electrical resistance of new solid-state device altered repeatedly by suitable control signals, yet remains at steady value when control signal removed. Resistance set at low value ("on" state), high value ("off" state), or at any convenient intermediate value and left there until new value desired. Circuits of this type particularly useful in nonvolatile, associative electronic memories based on models of neural networks. Such programmable analog memory resistors ideally suited as synaptic interconnects in "self-learning" neural nets. Operation of device depends on electrochromic property of WO3, which when pure is insulator. Potential uses include nonvolatile, erasable, electronically programmable read-only memories.

  7. Fabrication of a magnetic-tunnel-junction-based nonvolatile logic-in-memory LSI with content-aware write error masking scheme achieving 92% storage capacity and 79% power reduction

    NASA Astrophysics Data System (ADS)

    Natsui, Masanori; Tamakoshi, Akira; Endoh, Tetsuo; Ohno, Hideo; Hanyu, Takahiro

    2017-04-01

    A magnetic-tunnel-junction (MTJ)-based video coding hardware with an MTJ-write-error-rate relaxation scheme as well as a nonvolatile storage capacity reduction technique is designed and fabricated in a 90 nm MOS and 75 nm perpendicular MTJ process. The proposed MTJ-oriented dynamic error masking scheme suppresses the effect of write operation errors on the operation result of LSI, which results in the increase in an acceptable MTJ write error rate up to 7.8 times with less than 6% area overhead, while achieving 79% power reduction compared with that of the static-random-access-memory-based one.

  8. Memory characteristics of Co nanocrystal memory device with HfO2 as blocking oxide

    NASA Astrophysics Data System (ADS)

    Yang, F. M.; Chang, T. C.; Liu, P. T.; Yeh, P. H.; Yu, Y. C.; Lin, J. Y.; Sze, S. M.; Lou, J. C.

    2007-03-01

    In this letter, the Co nanocrystals using SiO2 and HfO2 as the tunneling and the control dielectric with memory effect has been fabricated. A significant memory effect was observed through the electrical measurements. Under the low voltage operation of 5V, the memory window was estimated to ˜1V. The retention characteristics were tested to be robust. Also, the endurance of the memory device was not degraded up to 106 write/erase cycles. The processing of the structure is compatible with the current manufacturing technology of semiconductor industry.

  9. Resistive switching effect in the planar structure of all-printed, flexible and rewritable memory device based on advanced 2D nanocomposite of graphene quantum dots and white graphene flakes

    NASA Astrophysics Data System (ADS)

    Muqeet Rehman, Muhammad; Uddin Siddiqui, Ghayas; Kim, Sowon; Choi, Kyung Hyun

    2017-08-01

    Pursuit of the most appropriate materials and fabrication methods is essential for developing a reliable, rewritable and flexible memory device. In this study, we have proposed an advanced 2D nanocomposite of white graphene (hBN) flakes embedded with graphene quantum dots (GQDs) as the functional layer of a flexible memory device owing to their unique electrical, chemical and mechanical properties. Unlike the typical sandwich type structure of a memory device, we developed a cost effective planar structure, to simplify device fabrication and prevent sneak current. The entire device fabrication was carried out using printing technology followed by encapsulation in an atomically thin layer of aluminum oxide (Al2O3) for protection against environmental humidity. The proposed memory device exhibited attractive bipolar switching characteristics of high switching ratio, large electrical endurance and enhanced lifetime, without any crosstalk between adjacent memory cells. The as-fabricated device showed excellent durability for several bending cycles at various bending diameters without any degradation in bistable resistive states. The memory mechanism was deduced to be conductive filamentary; this was validated by illustrating the temperature dependence of bistable resistive states. Our obtained results pave the way for the execution of promising 2D material based next generation flexible and non-volatile memory (NVM) applications.

  10. Nanoscale design of multifunctional organic layers for low-power high-density memory devices.

    PubMed

    Nougaret, Laurianne; Kassa, Hailu G; Cai, Ronggang; Patois, Tilia; Nysten, Bernard; van Breemen, Albert J J M; Gelinck, Gerwin H; de Leeuw, Dago M; Marrani, Alessio; Hu, Zhijun; Jonas, Alain M

    2014-04-22

    We demonstrate the design of a multifunctional organic layer by the rational combination of nanosized regions of two functional polymers. Instead of relying on a spontaneous and random phase separation process or on the tedious synthesis of block copolymers, the method involves the nanomolding of a first component, followed by the filling of the resulting open spaces by a second component. We apply this methodology to fabricate organic nonvolatile memory diodes of high density. These are built by first creating a regular array of ferroelectric nanodots by nanoimprint lithography, followed by the filling of the trenches separating the ferroelectric nanodots with a semiconducting polymer. The modulation of the current in the semiconductor by the polarization state of the ferroelectric material is demonstrated both at the scale of a single semiconductor channel and in a microscopic device measuring about 80,000 channels in parallel, for voltages below ca. 2 V. The fabrication process, which combines synergetically orthogonal functional properties with a fine control over their spatial distribution, is thus demonstrated to be efficient over large areas.

  11. Inverse heat conduction problem in a phase change memory device

    NASA Astrophysics Data System (ADS)

    Battaglia, Jean-Luc; De, Indrayush; Sousa, Véronique

    2017-01-01

    An invers heat conduction problem is solved considering the thermal investigation of a phase change memory device using the scanning thermal microscopy. The heat transfer model rests on system identification for the probe thermal impedance and on a finite element method for the device thermal impedance. Unknown parameters in the model are then identified using a nonlinear least square algorithm that minimizes the quadratic gap between the measured probe temperature and the simulated one.

  12. The analysis of polarization characteristics on 40nm memory devices

    NASA Astrophysics Data System (ADS)

    Yoo, Minae; Park, Chanha; You, Taejun; Yang, Hyunjo; Min, Young-Hong; Park, Ki-Yeop; Yim, Donggyu; Park, Sungki

    2009-03-01

    Hyper NA system has been introduced to develop sub-60nm node memory devices. Especially memory industries including DRAM and NAND Flash business have driven much finer technology to improve productivity. Polarization at hyper NA has been well known as important optical technology to enhance imaging performance and also achieve very low k1 process. The source polarization on dense structure has been used as one of the major RET techniques. The process capabilities of various layers under specific illumination and polarization have been explored. In this study, polarization characteristic on 40nm memory device will be analyzed. Especially, TE (Transverse Electric) polarization and linear X-Y polarization on hyper NA ArF system will be compared and investigated. First, IPS (Intensity in Preferred State) value will be measured with PMM (Polarization Metrology Module) to confirm polarization characteristic of each machine before simulation. Next simulation will be done to estimate the CD variation impact of each polarization to different illumination. Third, various line and space pattern of DRAM and Flash device will be analyzed under different polarized condition to see the effect of polarization on CD of actual wafer. Finally, conclusion will be made for this experiment and future work will be discussed. In this paper, the behavior of 40nm node memory devices with two types of polarization is presented and the guidelines for polarization control is discussed based on the patterning performances.

  13. Camera memory study for large space telescope. [charge coupled devices

    NASA Technical Reports Server (NTRS)

    Hoffman, C. P.; Brewer, J. E.; Brager, E. A.; Farnsworth, D. L.

    1975-01-01

    Specifications were developed for a memory system to be used as the storage media for camera detectors on the large space telescope (LST) satellite. Detectors with limited internal storage time such as intensities charge coupled devices and silicon intensified targets are implied. The general characteristics are reported of different approaches to the memory system with comparisons made within the guidelines set forth for the LST application. Priority ordering of comparisons is on the basis of cost, reliability, power, and physical characteristics. Specific rationales are provided for the rejection of unsuitable memory technologies. A recommended technology was selected and used to establish specifications for a breadboard memory. Procurement scheduling is provided for delivery of system breadboards in 1976, prototypes in 1978, and space qualified units in 1980.

  14. Automatic memory management policies for low power, memory limited, and delay intolerant devices

    NASA Astrophysics Data System (ADS)

    Jahid, Md. Abu

    Mobile devices such as smartphones and tablets are energy and memory limited, and implement graphical user interfaces that are intolerant of computational delays. Mobile device platforms supporting apps implemented in languages that require automatic memory management, such as the Dalvik (Java) virtual machine within Google's Android, have become dominant. It is essential that automatic memory management avoid causing unacceptable interface delays while responsibly managing energy and memory resource usage. Dalvik's automatic memory management policies for heap growth and garbage collection scheduling utilize heuristics tuned to minimize memory footprint. These policies result in only marginally acceptable response times and garbage collection signicantly contributes to apps' CPU time and therefore energy consumption. The primary contributions of this research include a characterization of Dalvik's "baseline" automatic memory management policy, the development of a new "adaptive" policy, and an investigation of the performance of this policy. The investigation indicates that this adaptive policy consumes less CPU time and improves interactive performance at the cost of increasing memory footprint size by an acceptable amount.

  15. Micro devices using shape memory polymer patches for mated connections

    DOEpatents

    Lee, Abraham P.; Fitch, Joseph P.

    2000-01-01

    A method and micro device for repositioning or retrieving miniature devices located in inaccessible areas, such as medical devices (e.g., stents, embolic coils, etc.) located in a blood vessel. The micro repositioning or retrieving device and method uses shape memory polymer (SMP) patches formed into mating geometries (e.g., a hoop and a hook) for re-attachment of the deposited medical device to a catheter or guidewire. For example, SMP or other material hoops are formed on the medical device to be deposited in a blood vessel, and SMP hooks are formed on the micro device attached to a guidewire, whereby the hooks on the micro device attach to the hoops on the medical device, or vice versa, enabling deposition, movement, re-deposit, or retrieval of the medical device. By changing the temperature of the SMP hooks, the hooks can be attached to or released from the hoops located on the medical device. An exemplary method for forming the hooks and hoops involves depositing a sacrificial thin film on a substrate, patterning and processing the thin film to form openings therethrough, depositing or bonding SMP materials in the openings so as to be attached to the substrate, and removing the sacrificial thin film.

  16. Computational design of digital and memory biological devices

    PubMed Central

    Rodrigo, Guillermo

    2008-01-01

    The use of combinatorial optimization techniques with computational design allows the development of automated methods to design biological systems. Automatic design integrates design principles in an unsupervised algorithm to sample a larger region of the biological network space, at the topology and parameter levels. The design of novel synthetic transcriptional networks with targeted behaviors will be key to understand the design principles underlying biological networks. In this work, we evolve transcriptional networks towards a targeted dynamics, by using a library of promoters and coding sequences, to design a complex biological memory device. The designed sequential transcription network implements a JK-Latch, which is fully predictable and richer than other memory devices. Furthermore, we present designs of transcriptional devices behaving as logic gates, and we show how to create digital behavior from analog promoters. Our procedure allows us to propose a scenario for the evolution of multi-functional genetic networks. In addition, we discuss the decomposability of regulatory networks in terms of genetic modules to develop a given cellular function. Summary. We show how to use an automated procedure to design logic and sequential transcription circuits. This methodology will allow advancing the rational design of biological devices to more complex systems, and we propose the first design of a biological JK-latch memory device. Electronic supplementary material The online version of this article (doi:10.1007/s11693-008-9017-0) contains supplementary material, which is available to authorized users. PMID:19003443

  17. A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

    NASA Astrophysics Data System (ADS)

    Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

    2016-04-01

    A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70 nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20 MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 µs using 128-dimension bag-of-feature patterns, and the measured average operation power of the entire processor core is only 600 µW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.

  18. Multilevel conductance switching of memory device through photoelectric effect.

    PubMed

    Ye, Changqing; Peng, Qian; Li, Mingzhu; Luo, Jia; Tang, Zhengming; Pei, Jian; Chen, Jianming; Shuai, Zhigang; Jiang, Lei; Song, Yanlin

    2012-12-12

    A photoelectronic switch of a multilevel memory device has been achieved using a meta-conjugated donor-bridge-acceptor (DBA) molecule. Such a DBA optoelectronic molecule responds to both the optical and electrical stimuli. The device exhibits good electrical bistable switching behaviors under dark, with a large ON/OFF ratio more than 10(6). In cooperation with the UV light, photoelectronic ternary states are addressable in a bistable switching system. On the basis of the CV measurement, charge carriers transport modeling, quantum chemical calculation, and absorption spectra analysis, the mechanism of the DBA memory is suggested to be attributed to the substep charge transfer transition process. The capability of tailoring photoelectrical properties is a very promising strategy to explore the multilevel storage, and it will give a new opportunity for designing multifunctional devices.

  19. Photoresponsive memory device based on Graphene/Boron Nitride heterostructure

    NASA Astrophysics Data System (ADS)

    Kahn, Salman; Velasco, Jairo, Jr.; Ju, Long; Wong, Dillon; Lee, Juwon; Tsai, Hsin Zon; Taniguchi, Takashi; Watanabe, Kenji; Zettl, Alex; Wang, Feng; Crommie, Michael

    2015-03-01

    Recent technological advancements have allowed the stacking of two dimensional layered material in order to create van der Waals heterostructures (VDH), enabling the design of novel properties by exploiting the proximal interaction between layers with different electronic properties. We report the creation of an optoelectronic memory device using a Graphene/Boron Nitride (hBN) heterostructure. Using the photo-induced doping phenomenon, we are able to spatially ``write'' a doping profile on graphene and ``read'' the profile through electrical transport and local probe techniques. We then utilize defect engineering to enhance the optoelectronic response of graphene and explore the effect of defects in hBN. Our work introduces a simple device architecture to create an optoelectronic memory device and contributes towards understanding the proximal effects of hBN on Graphene.

  20. Coexistence of diode-like volatile and multilevel nonvolatile resistive switching in a ZrO2/TiO2 stack structure.

    PubMed

    Li, Yingtao; Yuan, Peng; Fu, Liping; Li, Rongrong; Gao, Xiaoping; Tao, Chunlan

    2015-10-02

    Diode-like volatile resistive switching as well as nonvolatile resistive switching behaviors in a Cu/ZrO₂/TiO₂/Ti stack are investigated. Depending on the current compliance during the electroforming process, either volatile resistive switching or nonvolatile resistive switching is observed. With a lower current compliance (<10 μA), the Cu/ZrO₂/TiO₂/Ti device exhibits diode-like volatile resistive switching with a rectifying ratio over 10(6). The permanent transition from volatile to nonvolatile resistive switching can be obtained by applying a higher current compliance of 100 μA. Furthermore, by using different reset voltages, the Cu/ZrO₂/TiO₂/Ti device exhibits multilevel memory characteristics with high uniformity. The coexistence of nonvolatile multilevel memory and diode-like volatile resistive switching behaviors in the same Cu/ZrO₂/TiO₂/Ti device opens areas of applications in high-density storage, logic circuits, neural networks, and passive crossbar memory selectors.

  1. Some Improvements in Utilization of Flash Memory Devices

    NASA Technical Reports Server (NTRS)

    Gender, Thomas K.; Chow, James; Ott, William E.

    2009-01-01

    Two developments improve the utilization of flash memory devices in the face of the following limitations: (1) a flash write element (page) differs in size from a flash erase element (block), (2) a block must be erased before its is rewritten, (3) lifetime of a flash memory is typically limited to about 1,000,000 erases, (4) as many as 2 percent of the blocks of a given device may fail before the expected end of its life, and (5) to ensure reliability of reading and writing, power must not be interrupted during minimum specified reading and writing times. The first development comprises interrelated software components that regulate reading, writing, and erasure operations to minimize migration of data and unevenness in wear; perform erasures during idle times; quickly make erased blocks available for writing; detect and report failed blocks; maintain the overall state of a flash memory to satisfy real-time performance requirements; and detect and initialize a new flash memory device. The second development is a combination of hardware and software that senses the failure of a main power supply and draws power from a capacitive storage circuit designed to hold enough energy to sustain operation until reading or writing is completed.

  2. Floating-gated memory based on carbon nanotube field-effect transistors with Si floating dots

    NASA Astrophysics Data System (ADS)

    Seike, Kohei; Fujii, Yusuke; Ohno, Yasuhide; Maehashi, Kenzo; Inoue, Koichi; Matsumoto, Kazuhiko

    2014-01-01

    We have fabricated a carbon nanotube field-effect transistor (CNTFET)-based nonvolatile memory device with Si floating dots. The electrical characteristics of this memory device were compared with those of devices with a HfO2 charge storage layer or Au floating dots. For a sweep width of 6 V, the memory window of the devices with the Si floating dots increased twofold as compared with that of the devices with the HfO2 layer. Moreover, the retention characteristics revealed that, for the device with the Au floating dots, the off-state had almost the same current as the on-state at the 400th s. However, the devices with the Si floating dots had longer-retention characteristics. The results indicate that CNTFET-based devices with Si floating dots are promising candidates for low-power consumption nonvolatile memory devices.

  3. Direct observation of mobile protons in SiO{sub 2} thin films: Potential application in a novel memory device

    SciTech Connect

    Vanheusden, K.; Warren, W.L.; Fleetwood, D.M.

    1996-12-31

    In this work we show that annealing of silicon/silicon-dioxide/silicon structures in forming gas (N{sub 2}:H{sub 2}; 95:5) above 500{degrees}C leads to spontaneous incorporation of mobile H{sup +} ions in the buried SiO{sub 2} layer. We demonstrate that, unlike the alkali ions feared as killer contaminants in the early days, the space charge distribution of these mobile protons within the buried oxide layer can be very well controlled and easily rearranged with relatively high speed at room temperature. The hysteresis in the flat band voltage shift provides a unique vehicle to study proton kinetics in silicon dioxide thin films. It is further shown how this effect can be used as the basis for a reliable nonvolatile FET memory device that has potential to be competitive with state-of-the-art Si-based memory technologies. The power of this novel device is its simplicity; it requires few processing steps, all of which are standard in Si integrated-circuit fabrication.

  4. Fabrication of Nano-Crossbar Resistive Switching Memory Based on the Copper-Tantalum Pentoxide-Platinum Device Structure

    NASA Astrophysics Data System (ADS)

    Olga Gneri, Paula; Jardim, Marcos

    Resistive switching memory has been of interest lately not only for its simple metal-insulator-metal (MIM) structure but also for its promising ease of scalability an integration into current CMOS technologies like the Field Programmable Gate Arrays and other non-volatile memory applications. There are several resistive switching MIM combinations but under this scope of research, attention will be paid to the bipolar resistive switching characteristics and fabrication of Tantalum Pentaoxide sandwiched between platinum and copper. By changing the polarity of the voltage bias, this metal-insulator-metal (MIM) device can be switched between a high resistive state (OFF) and low resistive state (ON). The change in states is induced by an electrochemical metallization process, which causes a formation or dissolution of Cu metal filamentary paths in the Tantalum Pentaoxide insulator. There is very little thorough experimental information about the Cu-Ta 2O5-Pt switching characteristics when scaled to nanometer dimensions. In this light, the MIM structure was fabricated in a two-dimensional crossbar format. Also, with the limited available resources, a multi-spacer technique was formulated to localize the active device area in this MIM configuration to less than 20nm. This step is important in understanding the switching characteristics and reliability of this structure when scaled to nanometer dimensions.

  5. Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

    NASA Astrophysics Data System (ADS)

    Yamamoto, Shuu'ichirou; Shuto, Yusuke; Sugahara, Satoshi

    2013-07-01

    We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

  6. 76 FR 73676 - Certain Dynamic Random Access Memory Devices, and Products Containing Same; Receipt of Complaint...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-11-29

    ... COMMISSION Certain Dynamic Random Access Memory Devices, and Products Containing Same; Receipt of Complaint... complaint entitled In Re Certain Dynamic Random Access Memory Devices, and Products Containing Same, DN 2859... within the United States after importation of certain dynamic random access memory devices, and...

  7. Multilevel non-volatile data storage utilizing common current hysteresis of networked single walled carbon nanotubes

    NASA Astrophysics Data System (ADS)

    Hwang, Ihn; Wang, Wei; Hwang, Sun Kak; Cho, Sung Hwan; Kim, Kang Lib; Jeong, Beomjin; Huh, June; Park, Cheolmin

    2016-05-01

    The characteristic source-drain current hysteresis frequently observed in field-effect transistors with networked single walled carbon-nanotube (NSWNT) channels is problematic for the reliable switching and sensing performance of devices. But the two distinct current states of the hysteresis curve at a zero gate voltage can be useful for memory applications. In this work, we demonstrate a novel non-volatile transistor memory with solution-processed NSWNTs which are suitable for multilevel data programming and reading. A polymer passivation layer with a small amount of water employed on the top of the NSWNT channel serves as an efficient gate voltage dependent charge trapping and de-trapping site. A systematic investigation evidences that the water mixed in a polymer passivation solution is critical for reliable non-volatile memory operation. The optimized device is air-stable and temperature-resistive up to 80 °C and exhibits excellent non-volatile memory performance with an on/off current ratio greater than 104, a switching time less than 100 ms, data retention longer than 4000 s, and write/read endurance over 100 cycles. Furthermore, the gate voltage dependent charge injection mediated by water in the passivation layer allowed for multilevel operation of our memory in which 4 distinct current states were programmed repetitively and preserved over a long time period.The characteristic source-drain current hysteresis frequently observed in field-effect transistors with networked single walled carbon-nanotube (NSWNT) channels is problematic for the reliable switching and sensing performance of devices. But the two distinct current states of the hysteresis curve at a zero gate voltage can be useful for memory applications. In this work, we demonstrate a novel non-volatile transistor memory with solution-processed NSWNTs which are suitable for multilevel data programming and reading. A polymer passivation layer with a small amount of water employed on the top of the

  8. Laser-activated shape memory polymer intravascular thrombectomy device

    NASA Astrophysics Data System (ADS)

    Small, Ward, IV; Wilson, Thomas S.; Benett, William J.; Loge, Jeffrey M.; Maitland, Duncan J.

    2005-10-01

    A blood clot (thrombus) that becomes lodged in the arterial network supplying the brain can cause an ischemic stroke, depriving the brain of oxygen and often resulting in permanent disability. As an alternative to conventional clot-dissolving drug treatment, we are developing an intravascular laser-activated therapeutic device using shape memory polymer (SMP) to mechanically retrieve the thrombus and restore blood flow to the brain. Thermal imaging and computer simulation were used to characterize the optical and photothermal behavior of the SMP microactuator. Deployment of the SMP device in an in vitro thrombotic vascular occlusion model demonstrated the clinical treatment concept.

  9. RFID and Memory Devices Fabricated Integrally on Substrates

    NASA Technical Reports Server (NTRS)

    Schramm, Harry F.

    2004-01-01

    Electronic identification devices containing radio-frequency identification (RFID) circuits and antennas would be fabricated integrally with the objects to be identified, according to a proposal. That is to say, the objects to be identified would serve as substrates for the deposition and patterning of the materials of the devices used to identify them, and each identification device would be bonded to the identified object at the molecular level. Vacuum arc vapor deposition (VAVD) is the NASA derived process for depositing layers of material on the substrate. This proposal stands in contrast to the current practice of fabricating RFID and/or memory devices as wafer-based, self-contained integrated-circuit chips that are subsequently embedded in or attached to plastic cards to make smart account-information cards and identification badges. If one relies on such a chip to store data on the history of an object to be tracked and the chip falls off or out of the object, then one loses both the historical data and the means to track the object and verify its identity electronically. Also, in contrast is the manufacturing philosophy in use today to make many memory devices. Today s methods involve many subtractive processes such as etching. This proposal only uses additive methods, building RFID and memory devices from the substrate up in thin layers. VAVD is capable of spraying silicon, copper, and other materials commonly used in electronic devices. The VAVD process sprays most metals and some ceramics. The material being sprayed has a very strong bond with the substrate, whether that substrate is metal, ceramic, or even wood, rock, glass, PVC, or paper. An object to be tagged with an identification device according to the proposal must be compatible with a vacuum deposition process. Temperature is seldom an issue as the substrate rarely reaches 150 F (66 C) during the deposition process. A portion of the surface of the object would be designated as a substrate for

  10. Self-assembly of Al2O3 nanodots on SiO2 using two-step controlled annealing technique for long retention nonvolatile memories

    NASA Astrophysics Data System (ADS)

    Chen, Jing Hao; Yoo, Won Jong; Chan, Daniel S. H.; Tang, Lei-Jun

    2005-02-01

    A self-assembly of high-density Al2O3 nanodots (NDs) on SiO2 has been demonstrated by employing a two-step controlled annealing method. Results show that the conglomeration of Al is impeded by oxygen and the size and density of Al2O3 NDs can be controlled by the initial Al film thickness and annealing temperature. Memory devices with Al2O3 NDs fabricated using this technique show improved retention properties compared to those with Al2O3 continuous films. A comparison of temperature dependency shows that the good retention property originates from the suppression of lateral migration of electrons via Frenkel-Poole tunneling.

  11. Recent patents in semiconductor nanocluster floating gate flash memory.

    PubMed

    Dai, Jiyan Y; Lee, Pui-Fai

    2007-01-01

    Nanoclusters (NC) as charge storage nodes have been applied in nonvolatile, high-speed, high-density and low-power memory devices. Compared with conventional floating gate memory, where a layer of poly-Si is used for charge storage, a memory device composed of nanoclusters isolated by dielectrics benefits from a relatively low operating voltage, high endurance, fast write-erase speeds and better immunity to soft errors due to the quantum confinement and Coulomb blockade effects. Recent patents in this field have proposed several innovated structures and fabrication methods for nanocluster based floating gate flash memory and single-electron memory devices.

  12. Effect of annealing treatment on the electrical characteristics of Pt/Cr-embedded ZnO/Pt resistance random access memory devices

    SciTech Connect

    Chang, Li-Chun; Kao, Hsuan-Ling; Liu, Keng-Hao

    2014-03-15

    ZnO/Cr/ZnO trilayer films sandwiched with Pt electrodes were prepared for nonvolatile resistive memory applications. The threshold voltage of a ZnO device embedded with a 3-nm Cr interlayer was approximately 50% lower than that of a ZnO monolayer device. This study investigated threshold voltage as a function of Cr thickness. Both the ZnO monolayer device and the Cr-embedded ZnO device structures exhibited resistance switching under electrical bias both before and after rapid thermal annealing (RTA) treatment, but resistive switching effects in the two cases exhibited distinct characteristics. Compared with the as-fabricated device, the memory cell after RTA demonstrated remarkable device parameter improvements, including a lower threshold voltage, a lower write current, and a higher R{sub off}/R{sub on} ratio. Both transmission electron microscope observations and Auger electron spectroscopy revealed that the Cr charge trapping layer in Cr-embedded ZnO dispersed uniformly into the storage medium after RTA, and x-ray diffraction and x-ray photoelectron spectroscopy analyses demonstrated that the Cr atoms lost electrons to become Cr{sup 3+} ions after dispersion. These results indicated that the altered status of Cr in ZnO/Cr/ZnO trilayer films during RTA treatment was responsible for the switching mechanism transition.

  13. A flexible organic resistance memory device for wearable biomedical applications

    NASA Astrophysics Data System (ADS)

    Cai, Yimao; Tan, Jing; YeFan, Liu; Lin, Min; Huang, Ru

    2016-07-01

    Parylene is a Food and Drug Administration (FDA)-approved material which can be safely used within the human body and it is also offers chemically inert and flexible merits. Here, we present a flexible parylene-based organic resistive random access memory (RRAM) device suitable for wearable biomedical application. The proposed device is fabricated through standard lithography and pattern processes at room temperature, exhibiting the feasibility of integration with CMOS circuits. This organic RRAM device offers a high storage window (>104), superior retention ability and immunity to disturbing. In addition, brilliant mechanical and electrical stabilities of this device are demonstrated when under harsh bending (bending cycle >500, bending radius <10 mm). Finally, the underlying mechanism for resistance switching of this kind of device is discussed, and metallic conducting filament formation and annihilation related to oxidization/redox of Al and Al anions migrating in the parylene layer can be attributed to resistance switching in this device. These advantages reveal the significant potential of parylene-based flexible RRAM devices for wearable biomedical applications.

  14. A flexible organic resistance memory device for wearable biomedical applications.

    PubMed

    Cai, Yimao; Tan, Jing; YeFan, Liu; Lin, Min; Huang, Ru

    2016-07-08

    Parylene is a Food and Drug Administration (FDA)-approved material which can be safely used within the human body and it is also offers chemically inert and flexible merits. Here, we present a flexible parylene-based organic resistive random access memory (RRAM) device suitable for wearable biomedical application. The proposed device is fabricated through standard lithography and pattern processes at room temperature, exhibiting the feasibility of integration with CMOS circuits. This organic RRAM device offers a high storage window (>10(4)), superior retention ability and immunity to disturbing. In addition, brilliant mechanical and electrical stabilities of this device are demonstrated when under harsh bending (bending cycle >500, bending radius <10 mm). Finally, the underlying mechanism for resistance switching of this kind of device is discussed, and metallic conducting filament formation and annihilation related to oxidization/redox of Al and Al anions migrating in the parylene layer can be attributed to resistance switching in this device. These advantages reveal the significant potential of parylene-based flexible RRAM devices for wearable biomedical applications.

  15. Resistive switching characteristics and mechanisms in silicon oxide memory devices

    NASA Astrophysics Data System (ADS)

    Chang, Yao-Feng; Fowler, Burt; Chen, Ying-Chen; Zhou, Fei; Wu, Xiaohan; Chen, Yen-Ting; Wang, Yanzhen; Xue, Fei; Lee, Jack C.

    2016-05-01

    Intrinsic unipolar SiOx-based resistance random access memories (ReRAM) characterization, switching mechanisms, and applications have been investigated. Device structures, material compositions, and electrical characteristics are identified that enable ReRAM cells with high ON/OFF ratio, low static power consumption, low switching power, and high readout-margin using complementary metal-oxide semiconductor transistor (CMOS)-compatible SiOx-based materials. These ideas are combined with the use of horizontal and vertical device structure designs, composition optimization, electrical control, and external factors to help understand resistive switching (RS) mechanisms. Measured temperature effects, pulse response, and carrier transport behaviors lead to compact models of RS mechanisms and energy band diagrams in order to aid the development of computer-aided design for ultralarge-v scale integration. This chapter presents a comprehensive investigation of SiOx-based RS characteristics and mechanisms for the post-CMOS device era.

  16. Self-assembled nanostructured resistive switching memory devices fabricated by templated bottom-up growth

    PubMed Central

    Song, Ji-Min; Lee, Jang-Sik

    2016-01-01

    Metal-oxide-based resistive switching memory device has been studied intensively due to its potential to satisfy the requirements of next-generation memory devices. Active research has been done on the materials and device structures of resistive switching memory devices that meet the requirements of high density, fast switching speed, and reliable data storage. In this study, resistive switching memory devices were fabricated with nano-template-assisted bottom up growth. The electrochemical deposition was adopted to achieve the bottom-up growth of nickel nanodot electrodes. Nickel oxide layer was formed by oxygen plasma treatment of nickel nanodots at low temperature. The structures of fabricated nanoscale memory devices were analyzed with scanning electron microscope and atomic force microscope (AFM). The electrical characteristics of the devices were directly measured using conductive AFM. This work demonstrates the fabrication of resistive switching memory devices using self-assembled nanoscale masks and nanomateirals growth from bottom-up electrochemical deposition. PMID:26739122

  17. Self-assembled nanostructured resistive switching memory devices fabricated by templated bottom-up growth.

    PubMed

    Song, Ji-Min; Lee, Jang-Sik

    2016-01-07

    Metal-oxide-based resistive switching memory device has been studied intensively due to its potential to satisfy the requirements of next-generation memory devices. Active research has been done on the materials and device structures of resistive switching memory devices that meet the requirements of high density, fast switching speed, and reliable data storage. In this study, resistive switching memory devices were fabricated with nano-template-assisted bottom up growth. The electrochemical deposition was adopted to achieve the bottom-up growth of nickel nanodot electrodes. Nickel oxide layer was formed by oxygen plasma treatment of nickel nanodots at low temperature. The structures of fabricated nanoscale memory devices were analyzed with scanning electron microscope and atomic force microscope (AFM). The electrical characteristics of the devices were directly measured using conductive AFM. This work demonstrates the fabrication of resistive switching memory devices using self-assembled nanoscale masks and nanomateirals growth from bottom-up electrochemical deposition.

  18. Evaluation of reinitialization-free nonvolatile computer systems for energy-harvesting Internet of things applications

    NASA Astrophysics Data System (ADS)

    Onizawa, Naoya; Tamakoshi, Akira; Hanyu, Takahiro

    2017-08-01

    In this paper, reinitialization-free nonvolatile computer systems are designed and evaluated for energy-harvesting Internet of things (IoT) applications. In energy-harvesting applications, as power supplies generated from renewable power sources cause frequent power failures, data processed need to be backed up when power failures occur. Unless data are safely backed up before power supplies diminish, reinitialization processes are required when power supplies are recovered, which results in low energy efficiencies and slow operations. Using nonvolatile devices in processors and memories can realize a faster backup than a conventional volatile computer system, leading to a higher energy efficiency. To evaluate the energy efficiency upon frequent power failures, typical computer systems including processors and memories are designed using 90 nm CMOS or CMOS/magnetic tunnel junction (MTJ) technologies. Nonvolatile ARM Cortex-M0 processors with 4 kB MRAMs are evaluated using a typical computing benchmark program, Dhrystone, which shows a few order-of-magnitude reductions in energy in comparison with a volatile processor with SRAM.

  19. Organic electrical bistable devices and rewritable memory cells

    NASA Astrophysics Data System (ADS)

    Ma, L. P.; Liu, J.; Yang, Y.

    2002-04-01

    Electrical bistability is a phenomenon in which a device exhibits two states of different conductivities, at the same applied voltage. We report an organic electrical bistable device (OBD) comprising of a thin metal layer embedded within the organic material, as the active medium [L. P. Ma, J. Liu, and Y. Yang, US Patent Pending, (2001)]. The performance of this device makes it attractive for memory-cell type of applications. The two states of the OBD differ in their conductivity by several orders in magnitude and show remarkable stability, i.e., once the device reaches either state, it tends to remain in that state for a prolonged period of time. More importantly, the high and low conductivity states of an OBD can be precisely controlled by the application of a positive voltage pulse (to write) or a negative voltage pulse (to erase), respectively. One million writing-erasing cycles for the OBD have been tested in ambient conditions without significant device degradation. These discoveries pave the way for newer applications, such as low-cost, large-area, flexible, high-density, electrically addressable data storage devices.

  20. Nonvolatile Array Of Synapses For Neural Network

    NASA Technical Reports Server (NTRS)

    Tawel, Raoul

    1993-01-01

    Elements of array programmed with help of ultraviolet light. A 32 x 32 very-large-scale integrated-circuit array of electronic synapses serves as building-block chip for analog neural-network computer. Synaptic weights stored in nonvolatile manner. Makes information content of array invulnerable to loss of power, and, by eliminating need for circuitry to refresh volatile synaptic memory, makes architecture simpler and more compact.