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Sample records for nonvolatile memory devices

  1. Nonvolatile Ionic Two-Terminal Memory Device

    NASA Technical Reports Server (NTRS)

    Williams, Roger M.

    1990-01-01

    Conceptual solid-state memory device nonvolatile and erasable and has only two terminals. Proposed device based on two effects: thermal phase transition and reversible intercalation of ions. Transfer of sodium ions between source of ions and electrical switching element increases or decreases electrical conductance of element, turning switch "on" or "off". Used in digital computers and neural-network computers. In neural networks, many small, densely packed switches function as erasable, nonvolatile synaptic elements.

  2. Nonvolatile organic transistor memory devices based on nanostructured polymeric materials

    NASA Astrophysics Data System (ADS)

    Lu, Mau-Shen; Lu, Chien; Li, Meng-Hsien; Liu, Cheng-Liang; Chen, Wen-Chang

    2014-10-01

    We report the characteristics of ferroelectric field effect transistor (FeFET) nonvolatile flash memory devices using aligned P(VDF-TrFE) electrospun nanofibers as the dielectric layer. These FeFET devices showed reliable memory behaviors and memory window proportional to the quantity of aligned nanofibers containing the ferroelectric β-phase crystalline domain. Moreover, the FeFET devices using nanofibers exhibited the long-term stability in the data retention larger than 104 s with the ON/OFF ratio of ~103, and the multiple switching operation stability up to 100 cycles.

  3. Titanium oxide nonvolatile memory device and its application

    NASA Astrophysics Data System (ADS)

    Wang, Wei

    In recent years, the semiconductor memory industry has seen an ever-increasing demand for nonvolatile memory (NVM), which is fueled by portable consumer electronic applications like the mobile phone and MP3 player. FLASH memory has been the most widely used nonvolatile memories in these systems, and has successfully kept up with CMOS scaling for many generations. However, as FLASH memory faces major scaling challenges beyond 22nm, non-charge-based nonvolatile memories are widely researched as candidates to replace FLASH. Titanium oxide (TiOx) nonvolatile memory device is considered to be a promising choice due to its controllable nonvolatile memory switching, good scalability, compatibility with CMOS processing and potential for 3D stacking. However, several major issues need to be overcome before TiOx NVM device can be adopted in manufacturing. First, there exists a highly undesirable high-voltage stress initiation process (FORMING) before the device can switch between high and low resistance states repeatedly. By analyzing the conductive behaviors of the memory device before and after FORMING, we propose that FORMING involves breaking down an interfacial layer between its Pt electrode and the TiOx thin film, and that FORMING is not needed if the Pt-TiOx interface can be kept clean during fabrication. An in-situ fabrication process is developed for cross-point TiOx NVM device, which enables in-situ deposition of the critical layers of the memory device and thus achieves clean interfaces between Pt electrodes and TiOx film. Testing results show that FORMING is indeed eliminated for memory devices made with the in-situ fabrication process. It verifies the significance of in-situ deposition without vacuum break in the fabrication of TiOx NVM devices. Switching parameters statistics of TiOx NVM devices are studied and compared for unipolar and bipolar switching modes. RESET mechanisms are found to be different for the two switching modes: unipolar switching can be

  4. Bioorganic nanodots for non-volatile memory devices

    SciTech Connect

    Amdursky, Nadav; Shalev, Gil; Handelman, Amir; Natan, Amir; Rosenwaks, Yossi; Litsyn, Simon; Szwarcman, Daniel; Rosenman, Gil; Roizin, Yakov

    2013-12-01

    In recent years we are witnessing an intensive integration of bio-organic nanomaterials in electronic devices. Here we show that the diphenylalanine bio-molecule can self-assemble into tiny peptide nanodots (PNDs) of ∼2 nm size, and can be embedded into metal-oxide-semiconductor devices as charge storage nanounits in non-volatile memory. For that purpose, we first directly observe the crystallinity of a single PND by electron microscopy. We use these nanocrystalline PNDs units for the formation of a dense monolayer on SiO{sub 2} surface, and study the electron/hole trapping mechanisms and charge retention ability of the monolayer, followed by fabrication of PND-based memory cell device.

  5. Improving Memory Characteristics of Hydrogenated Nanocrystalline Silicon Germanium Nonvolatile Memory Devices by Controlling Germanium Contents.

    PubMed

    Kim, Jiwoong; Jang, Kyungsoo; Phu, Nguyen Thi Cam; Trinh, Thanh Thuy; Raja, Jayapal; Kim, Taeyong; Cho, Jaehyun; Kim, Sangho; Park, Jinjoo; Jung, Junhee; Lee, Youn-Jung; Yi, Junsin

    2016-05-01

    Nonvolatile memory (NVM) with silicon dioxide/silicon nitride/silicon oxynitride (ONO(n)) charge trap structure is a promising flash memory technology duo that will fulfill process compatibility for system-on-panel displays, down-scaling cell size and low operation voltage. In this research, charge trap flash devices were fabricated with ONO(n) stack gate insulators and an active layer using hydrogenated nanocrystalline silicon germanium (nc-SiGe:H) films at a low temperature. In this study, the effect of the interface trap density on the performance of devices, including memory window and retention, was investigated. The electrical characteristics of NVM devices were studied controlling Ge content from 0% to 28% in the nc-SiGe:H channel layer. The optimal Ge content in the channel layer was found to be around 16%. For nc-SiGe:H NVM with 16% Ge content, the memory window was 3.13 V and the retention data exceeded 77% after 10 years under the programming condition of 15 V for 1 msec. This showed that the memory window increased by 42% and the retention increased by 12% compared to the nc-Si:H NVM that does not contain Ge. However, when the Ge content was more than 16%, the memory window and retention property decreased. Finally, this research showed that the Ge content has an effect on the interface trap density and this enabled us to determine the optimal Ge content. PMID:27483856

  6. Integration of Flexible and Microscale Organic Nonvolatile Resistive Memory Devices Using Orthogonal Photolithography.

    PubMed

    Song, Younggul; Jang, Jingon; Yoo, Daekyoung; Jung, Seok-Heon; Jeong, Hyunhak; Hong, Seunghun; Lee, Jin-Kyun; Lee, Takhee

    2016-06-01

    We present the integration of flexible and microscale organic nonvolatile resistive memory devices fabricated in a cross-bar array structure on plastic substrates. This microscale integration was made via orthogonal photolithography method using fluorinated photoresist and solvents and was achieved without causing damage to the underlying organic memory materials. Our flexible microscale organic devices exhibited high ON/OFF ratio (I(ON/I(OFF) > 10(4)) under bending conditions. In addition, the ON and OFF states of our flexible and microscale memory devices were maintained for 10,000 seconds without any serious degradation.

  7. Metal-organic molecular device for non-volatile memory storage

    SciTech Connect

    Radha, B. E-mail: kulkarni@jncasr.ac.in; Sagade, Abhay A.; Kulkarni, G. U. E-mail: kulkarni@jncasr.ac.in

    2014-08-25

    Non-volatile memory devices have been of immense research interest for their use in active memory storage in powered off-state of electronic chips. In literature, various molecules and metal compounds have been investigated in this regard. Molecular memory devices are particularly attractive as they offer the ease of storing multiple memory states in a unique way and also represent ubiquitous choice for miniaturized devices. However, molecules are fragile and thus the device breakdown at nominal voltages during repeated cycles hinders their practical applicability. Here, in this report, a synergetic combination of an organic molecule and an inorganic metal, i.e., a metal-organic complex, namely, palladium hexadecylthiolate is investigated for memory device characteristics. Palladium hexadecylthiolate following partial thermolysis is converted to a molecular nanocomposite of Pd(II), Pd(0), and long chain hydrocarbons, which is shown to exhibit non-volatile memory characteristics with exceptional stability and retention. The devices are all solution-processed and the memory action stems from filament formation across the pre-formed cracks in the nanocomposite film.

  8. Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

    NASA Astrophysics Data System (ADS)

    Yu, Jie; Chen, Kun-ji; Ma, Zhong-yuan; Zhang, Xin-xin; Jiang, Xiao-fan; Wu, Yang-qing; Huang, Xin-fan; Oda, Shunri

    2016-09-01

    Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration. Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

  9. A fast and low-power microelectromechanical system-based non-volatile memory device

    PubMed Central

    Lee, Sang Wook; Park, Seung Joo; Campbell, Eleanor E. B.; Park, Yung Woo

    2011-01-01

    Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices. PMID:21364559

  10. A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires

    PubMed Central

    2012-01-01

    In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n+-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and alleviating the requirement of precise control of the doping profile. Owing to the higher carrier concentration in the channel, the developed JL NW device exhibits significantly enhanced programming speed and larger memory window than its counterpart with conventional undoped-NW-channel. Moreover, it also displays acceptable erase and data retention properties. Hence, the desirable memory characteristics along with the much simplified fabrication process make the JL NW memory structure a promising candidate for future system-on-panel and three-dimensional ultrahigh density memory applications. PMID:22373446

  11. High-performance nonvolatile organic transistor memory devices using the electrets of semiconducting blends.

    PubMed

    Chiu, Yu-Cheng; Chen, Tzu-Ying; Chen, Yougen; Satoh, Toshifumi; Kakuchi, Toyoji; Chen, Wen-Chang

    2014-08-13

    Organic nonvolatile transistor memory devices of the n-type semiconductor N,N'-bis(2-phenylethyl)-perylene-3,4:9,10-tetracarboxylic diimide (BPE-PTCDI) were prepared using various electrets (i.e., three-armed star-shaped poly[4-(diphenylamino)benzyl methacrylate] (N(PTPMA)3) and its blends with 6,6-phenyl-C61-butyric acid methyl ester (PCBM), 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-pen) or ferrocene). In the device using the PCBM:N(PTPMA)3 blend electret, it changed its memory feature from a write-once-read-many (WORM) type to a flash type as the PCBM content increased and could be operated repeatedly based on a tunneling process. The large shifts on the reversible transfer curves and the hysteresis after implementing a gate bias indicated the considerable charge storage in the electret layer. On the other hand, the memory characteristics showed a flash type and a WORM characteristic, respectively, using the donor/donor electrets TIPS-pen:N(PTPMA)3 and ferrocene:N(PTPMA)3. The variation on the memory characteristics was attributed to the difference of energy barrier at the interface when different types of electret materials were employed. All the studied memory devices exhibited a long retention over 10(4) s with a highly stable read-out current. In addition, the afore-discussed memory devices by inserting another electret layer of poly(methacrylic acid) (PMAA) between the BPE-PTCDI layer and the semiconducting blend layer enhanced the write-read-erase-read (WRER) operation cycle as high as 200 times. This study suggested that the energy level and charge transfer in the blend electret had a significant effect on tuning the characteristics of nonvolatile transistor memory devices.

  12. Non-volatile memory devices with redox-active diruthenium molecular compound.

    PubMed

    Pookpanratana, S; Zhu, H; Bittle, E G; Natoli, S N; Ren, T; Richter, C A; Li, Q; Hacker, C A

    2016-03-01

    Reduction-oxidation (redox) active molecules hold potential for memory devices due to their many unique properties. We report the use of a novel diruthenium-based redox molecule incorporated into a non-volatile Flash-based memory device architecture. The memory capacitor device structure consists of a Pd/Al2O3/molecule/SiO2/Si structure. The bulky ruthenium redox molecule is attached to the surface by using a 'click' reaction and the monolayer structure is characterized by x-ray photoelectron spectroscopy to verify the Ru attachment and molecular density. The 'click' reaction is particularly advantageous for memory applications because of (1) ease of chemical design and synthesis, and (2) provides an additional spatial barrier between the oxide/silicon to the diruthenium molecule. Ultraviolet photoelectron spectroscopy data identified the energy of the electronic levels of the surface before and after surface modification. The molecular memory devices display an unsaturated charge storage window attributed to the intrinsic properties of the redox-active molecule. Our findings demonstrate the strengths and challenges with integrating molecular layers within solid-state devices, which will influence the future design of molecular memory devices.

  13. Non-volatile memory devices with redox-active diruthenium molecular compound

    NASA Astrophysics Data System (ADS)

    Pookpanratana, S.; Zhu, H.; Bittle, E. G.; Natoli, S. N.; Ren, T.; Richter, C. A.; Li, Q.; Hacker, C. A.

    2016-03-01

    Reduction-oxidation (redox) active molecules hold potential for memory devices due to their many unique properties. We report the use of a novel diruthenium-based redox molecule incorporated into a non-volatile Flash-based memory device architecture. The memory capacitor device structure consists of a Pd/Al2O3/molecule/SiO2/Si structure. The bulky ruthenium redox molecule is attached to the surface by using a ‘click’ reaction and the monolayer structure is characterized by x-ray photoelectron spectroscopy to verify the Ru attachment and molecular density. The ‘click’ reaction is particularly advantageous for memory applications because of (1) ease of chemical design and synthesis, and (2) provides an additional spatial barrier between the oxide/silicon to the diruthenium molecule. Ultraviolet photoelectron spectroscopy data identified the energy of the electronic levels of the surface before and after surface modification. The molecular memory devices display an unsaturated charge storage window attributed to the intrinsic properties of the redox-active molecule. Our findings demonstrate the strengths and challenges with integrating molecular layers within solid-state devices, which will influence the future design of molecular memory devices.

  14. Zinc Cadmium Selenide Cladded Quantum Dot Based Electroluminescent and Nonvolatile Memory Devices

    NASA Astrophysics Data System (ADS)

    Al-Amody, Fuad H.

    This dissertation presents electroluminescent (EL) and nonvolatile memory devices fabricated using pseudomorphic ZnCdSe-based cladded quantum dots (QDs). These dots were grown using our own in-school built novel reactor. The EL device was fabricated on a substrate of ITO (indium tin oxide) coated glass with the quantum dots sandwiched between anode and cathode contacts with a small barrier layer on top of the QDs. The importance of these cladded dots is to increase the quantum yield of device. This device is unique as they utilize quantum dots that are pseudomorphic (nearly lattice-matched core and the shell of the dot). In the case of floating quantum dot gate nonvolatile memory, cladded ZnCdSe quantum dots are deposited on single crystalline gate insulator (ZnMgS/ZnMgSe), which is grown using metal-organic chemical vapor deposition (MOCVD). The control gate dielectric layer of the nonvolatile memory is Si3N4 or SiO2 and is grown using plasma enhanced chemical vapor deposition (PECVD). The cladded dots are grown using an improved methodology of photo-assisted microwave plasma metal-organic chemical vapor deposition (PMP-MOCVD) enhanced reactor. The cladding composition of the core and shell of the dots was engineered by the help of ultraviolet light which changed the incorporation of zinc (and hence composition of ZnCdSe). This makes ZnxCd1--xSe-ZnyCd1--y Se QDs to have a low composition of zinc in the core than the cladding (x

  15. Resistive switching behavior of reduced graphene oxide memory cells for low power nonvolatile device application

    PubMed Central

    Pradhan, Sangram K.; Xiao, Bo; Mishra, Saswat; Killam, Alex; Pradhan, Aswini K.

    2016-01-01

    Graphene Oxide (GO) based low cost flexible electronics and memory cell have recently attracted more attention for the fabrication of emerging electronic devices. As a suitable candidate for resistive random access memory technology, reduced graphene oxide (RGO) can be widely used for non-volatile switching memory applications because of its large surface area, excellent scalability, retention, and endurance properties. We demonstrated that the fabricated metal/RGO/metal memory device exhibited excellent switching characteristics, with on/off ratio of two orders of magnitude and operated threshold switching voltage of less than 1 V. The studies on different cell diameter, thickness, scan voltages and period of time corroborate the reliability of the device as resistive random access memory. The microscopic origin of switching operation is governed by the establishment of conducting filaments due to the interface amorphous layer rupturing and the movement of oxygen in the GO layer. This interesting experimental finding indicates that device made up of thermally reduced GO shows more reliability for its use in next generation electronics devices. PMID:27240537

  16. Resistive switching behavior of reduced graphene oxide memory cells for low power nonvolatile device application

    NASA Astrophysics Data System (ADS)

    Pradhan, Sangram K.; Xiao, Bo; Mishra, Saswat; Killam, Alex; Pradhan, Aswini K.

    2016-05-01

    Graphene Oxide (GO) based low cost flexible electronics and memory cell have recently attracted more attention for the fabrication of emerging electronic devices. As a suitable candidate for resistive random access memory technology, reduced graphene oxide (RGO) can be widely used for non-volatile switching memory applications because of its large surface area, excellent scalability, retention, and endurance properties. We demonstrated that the fabricated metal/RGO/metal memory device exhibited excellent switching characteristics, with on/off ratio of two orders of magnitude and operated threshold switching voltage of less than 1 V. The studies on different cell diameter, thickness, scan voltages and period of time corroborate the reliability of the device as resistive random access memory. The microscopic origin of switching operation is governed by the establishment of conducting filaments due to the interface amorphous layer rupturing and the movement of oxygen in the GO layer. This interesting experimental finding indicates that device made up of thermally reduced GO shows more reliability for its use in next generation electronics devices.

  17. Resistive switching behavior of reduced graphene oxide memory cells for low power nonvolatile device application.

    PubMed

    Pradhan, Sangram K; Xiao, Bo; Mishra, Saswat; Killam, Alex; Pradhan, Aswini K

    2016-01-01

    Graphene Oxide (GO) based low cost flexible electronics and memory cell have recently attracted more attention for the fabrication of emerging electronic devices. As a suitable candidate for resistive random access memory technology, reduced graphene oxide (RGO) can be widely used for non-volatile switching memory applications because of its large surface area, excellent scalability, retention, and endurance properties. We demonstrated that the fabricated metal/RGO/metal memory device exhibited excellent switching characteristics, with on/off ratio of two orders of magnitude and operated threshold switching voltage of less than 1 V. The studies on different cell diameter, thickness, scan voltages and period of time corroborate the reliability of the device as resistive random access memory. The microscopic origin of switching operation is governed by the establishment of conducting filaments due to the interface amorphous layer rupturing and the movement of oxygen in the GO layer. This interesting experimental finding indicates that device made up of thermally reduced GO shows more reliability for its use in next generation electronics devices. PMID:27240537

  18. Design of hybrid spintronic devices at scaled technologies for non-volatile memory applications

    NASA Astrophysics Data System (ADS)

    Mojumder, Niladri Narayan

    The ever-increasing demand for embedding more on- and off-chip memories to increase the bandwidth of high performance systems has led to a significant amount of research directed towards several potential high density memory technologies. With aggressive technology scaling, the researchers are incessantly confronted with various overwhelming challenges associated with the design of low power, ultra-high density and robust memory blocks. An alternative to all currently available memory technologies, spin-transfer torque (STT) Magnetic Random Access Memories (MRAM) offer many desirable memory-attributes. Data non-volatility, unlimited endurance, low power, high performance and high integration capabilities have stimulated an overwhelming interest for STT-MRAM among memory researchers. In an attempt to address the issues associated with parametric process variations and high switching energy consumptions, different genres of magnetic tunnel junction (MTJ) structures, memory bit-cells, and architecture are proposed. Unlike state-of-the-art tri-layer MTJ devices, the multi-port/multi-pillar structures provide the option to eliminate the self-conflicting design requirements for memory read, write and hold. Techniques to reduce thermal fluctuation induced delay spreads is discussed for reliable and deterministic magnetic switching characteristics in both in-plane and perpendicular anisotropy devices. The effect of thermal spin-transfer torque on high speed magnetic switching is discussed in the context of designing low power, robust, and reliable MRAM devices. Based on thermally initiated magnonic spin-transfer torque, we propose three new genres of multi-port MRAMs for low energy, high speed, and reliable magnetic switching. The proposition of several new genres of magnetic tunnel junctions (MTJ) based on both electric and thermal spin-transfer torque, the corresponding bit-cells, and memory architectures make STT-MRAM a promising choice as future universal memories.

  19. Vertically Stackable Novel One-Time Programmable Nonvolatile Memory Devices Based on Dielectric Breakdown Mechanism

    NASA Astrophysics Data System (ADS)

    Cho, Seongjae; Lee, Jung Hoon; Ryoo, Kyung-Chang; Jung, Sunghun; Lee, Jong-Ho; Park, Byung-Gook

    2011-12-01

    In this paper, a novel one-time programmable (OTP) nonvolatile memory (NVM) device and its array structures based on silicon technology are proposed. There have been many features of OTP NVM devices utilizing various combinations of channel, breakdown region, barrier, and contact materials. However, this invention can be realized by simple materials and fabrication methods: it is silicon-based materials and fully compatible with the conventional CMOS process. An individual memory cell is a silicon diode vertically integrated. Historically, OTP memories were widely used for read-only-memory (ROM) in the central processing unit (CPU) of the computer systems. By implanting the nanoscale fabrication technology into the concept of OTP memory, innovative high-density NVM appliances for massive storage media becomes very promising. The program operation is performed by breaking down the thin oxide layer between pn doped structure and wordline (WL) and its state can be sensed by the leakage current through the broken oxide. Since this invention is based on neither transistor structure nor charge-based mechanism, it is highly reliable and functional for the ultra-large scale integration. The feasibility of its stacked array will be also checked.

  20. A multilevel nonvolatile magnetoelectric memory

    PubMed Central

    Shen, Jianxin; Cong, Junzhuang; Shang, Dashan; Chai, Yisheng; Shen, Shipeng; Zhai, Kun; Sun, Young

    2016-01-01

    The coexistence and coupling between magnetization and electric polarization in multiferroic materials provide extra degrees of freedom for creating next-generation memory devices. A variety of concepts of multiferroic or magnetoelectric memories have been proposed and explored in the past decade. Here we propose a new principle to realize a multilevel nonvolatile memory based on the multiple states of the magnetoelectric coefficient (α) of multiferroics. Because the states of α depends on the relative orientation between magnetization and polarization, one can reach different levels of α by controlling the ratio of up and down ferroelectric domains with external electric fields. Our experiments in a device made of the PMN-PT/Terfenol-D multiferroic heterostructure confirm that the states of α can be well controlled between positive and negative by applying selective electric fields. Consequently, two-level, four-level, and eight-level nonvolatile memory devices are demonstrated at room temperature. This kind of multilevel magnetoelectric memory retains all the advantages of ferroelectric random access memory but overcomes the drawback of destructive reading of polarization. In contrast, the reading of α is nondestructive and highly efficient in a parallel way, with an independent reading coil shared by all the memory cells. PMID:27681812

  1. All-solution-processed nonvolatile flexible nano-floating gate memory devices

    NASA Astrophysics Data System (ADS)

    Kim, Chaewon; Song, Ji-Min; Lee, Jang-Sik; Lee, Mi Jung

    2014-01-01

    Organic semiconductors have great potential for future electronic applications owing to their inherent flexibility, low cost, light weight and ability to easily cover large areas. However, all of these advantageous material properties can only be harnessed if simple, cheap and low-temperature fabrication processes, which exclude the need for vacuum deposition and are compatible with flexible plastic substrates, are employed. There are a few solution-based techniques such as spin-coating and inkjet printing that meet the above criteria. In this paper, we describe a novel all-solution-processed nonvolatile memory device fabricated on a flexible plastic substrate. The source, drain and gate electrodes were printed using an inkjet printer with a conducting organic solution, while the semiconducting layer was spin-coated with an n-type polymer. The charge-trapping layer was composed of spin-coated reduced graphene oxide (rGO), which was prepared in the form of a solution using Hummer’s method. The fabricated device was characterized in order to confirm the memory characteristics. Device parameters such as threshold voltage shift, retention/endurance characteristics, mechanical robustness and reliability upon bending were also analyzed.

  2. MIEC (mixed-ionic-electronic-conduction)-based access devices for non-volatile crossbar memory arrays

    NASA Astrophysics Data System (ADS)

    Shenoy, Rohit S.; Burr, Geoffrey W.; Virwani, Kumar; Jackson, Bryan; Padilla, Alvaro; Narayanan, Pritish; Rettner, Charles T.; Shelby, Robert M.; Bethune, Donald S.; Raman, Karthik V.; BrightSky, Matthew; Joseph, Eric; Rice, Philip M.; Topuria, Teya; Kellock, Andrew J.; Kurdi, Bülent; Gopalakrishnan, Kailash

    2014-10-01

    Several attractive applications call for the organization of memristive devices (or other resistive non-volatile memory (NVM)) into large, densely-packed crossbar arrays. While resistive-NVM devices frequently possess some degree of inherent nonlinearity (typically 3-30× contrast), the operation of large (\\gt 1000×1000 device) arrays at low power tends to require quite large (\\gt 1e7) ON-to-OFF ratios (between the currents passed at high and at low voltages). One path to such large nonlinearities is the inclusion of a distinct access device (AD) together with each of the state-bearing resistive-NVM elements. While such an AD need not store data, its list of requirements is almost as challenging as the specifications demanded of the memory device. Several candidate ADs have been proposed, but obtaining high performance without requiring single-crystal silicon and/or the high processing temperatures of the front-end-of-the-line—which would eliminate any opportunity for 3D stacking—has been difficult. We review our work at IBM Research—Almaden on high-performance ADs based on Cu-containing mixed-ionic-electronic conduction (MIEC) materials [1-7]. These devices require only the low processing temperatures of the back-end-of-the-line, making them highly suitable for implementing multi-layer cross-bar arrays. MIEC-based ADs offer large ON/OFF ratios (\\gt 1e7), a significant voltage margin {{V}m} (over which current \\lt 10 nA), and ultra-low leakage (\\lt 10 pA), while also offering the high current densities needed for phase-change memory and the fully bipolar operation needed for high-performance RRAM. Scalability to critical lateral dimensions \\lt 30 nm and thicknesses \\lt 15 nm, tight distributions and 100% yield in large (512 kBit) arrays, long-term stability of the ultra-low leakage states, and sub-50 ns turn-ON times have all been demonstrated. Numerical modeling of these MIEC-based ADs shows that their operation depends on C{{u}+} mediated hole

  3. A Nonvolatile MOSFET Memory Device Based on Mobile Protons in SiO(2) Thin Films

    SciTech Connect

    Vanheusden, K.; Warren, W.L.; Devine, R.A.B.; Fleetwood, D.M.; Draper, B.L.; Schwank, J.R.

    1999-03-02

    It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protons are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).

  4. Nonvolatile Analog Memory

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C. (Inventor)

    2007-01-01

    A nonvolatile analog memory uses pairs of ferroelectric field effect transistors (FFETs). Each pair is defined by a first FFET and a second FFET. When an analog value is to be stored in one of the pairs, the first FFET has a saturation voltage applied thereto, and the second FFET has a storage voltage applied thereto that is indicative of the analog value. The saturation and storage voltages decay over time in accordance with a known decay function that is used to recover the original analog value when the pair of FFETs is read.

  5. Analog Nonvolatile Computer Memory Circuits

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd

    2007-01-01

    In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value

  6. Electric field mediated non-volatile tuning magnetism in CoPt/PMN-PT heterostructure for magnetoelectric memory devices

    NASA Astrophysics Data System (ADS)

    Yang, Y. T.; Li, J.; Peng, X. L.; Wang, X. Q.; Wang, D. H.; Cao, Q. Q.; Du, Y. W.

    2016-02-01

    We report a power efficient non-volatile magnetoelectric memory in the CoPt/(011)PMN-PT heterostructure. Two reversible and stable electric field induced coercivity states (i.e., high-HC or low-HC) are obtained due to the strain mediated converse magnetoelectric effect. The reading process of the different coercive field information written by electric fields is demonstrated by using a magnetoresistance read head. This result shows good prospects in the application of novel multiferroic devices.

  7. Resistive Switching in Al/Al2O3/TiO2/Al/PES Flexible Device for Nonvolatile Memory Application.

    PubMed

    Lin, Chun-Chieh; Lee, Wang-Ying; Lee, Han-Tang

    2016-05-01

    Resistive switching memory devices with superior properties are possibly used in next-generation nonvolatile memory to replace the flash memory. In addition, flexible electronics has also attracted much attention because of its light-weight and flexibility. Therefore, an Al/Al2O3/TiO2/Al/PES flexible resistive switching memory is employed in this study. The resistive switching characteristics and stability of the flexible device are improved by inserting the Al2O3 film. The resistive switching of the flexible device can be repeated over hundreds of times after the bending test. A possible resistive switching model of the flexible device is also proposed. In addition, the non-volatility of the flexible device is demonstrated. Based on our research results, the proposed Al2O3/TiO2-based resistive switching memory is possibly used in next-generation flexible electronics and nonvolatile memory applications. PMID:27483828

  8. Multi-floor cascading ferroelectric nanostructures: multiple data writing-based multi-level non-volatile memory devices.

    PubMed

    Hyun, Seung; Kwon, Owoong; Lee, Bom-Yi; Seol, Daehee; Park, Beomjin; Lee, Jae Yong; Lee, Ju Hyun; Kim, Yunseok; Kim, Jin Kon

    2016-01-21

    Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process. PMID:26695561

  9. Nonvolatile random access memory

    NASA Technical Reports Server (NTRS)

    Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor); Katti, Romney R. (Inventor)

    1994-01-01

    A nonvolatile magnetic random access memory can be achieved by an array of magnet-Hall effect (M-H) elements. The storage function is realized with a rectangular thin-film ferromagnetic material having an in-plane, uniaxial anisotropy and inplane bipolar remanent magnetization states. The thin-film magnetic element is magnetized by a local applied field, whose direction is used to form either a 0 or 1 state. The element remains in the 0 or 1 state until a switching field is applied to change its state. The stored information is detcted by a Hall-effect sensor which senses the fringing field from the magnetic storage element. The circuit design for addressing each cell includes transistor switches for providing a current of selected polarity to store a binary digit through a separate conductor overlying the magnetic element of the cell. To read out a stored binary digit, transistor switches are employed to provide a current through a row of Hall-effect sensors connected in series and enabling a differential voltage amplifier connected to all Hall-effect sensors of a column in series. To avoid read-out voltage errors due to shunt currents through resistive loads of the Hall-effect sensors of other cells in the same column, at least one transistor switch is provided between every pair of adjacent cells in every row which are not turned on except in the row of the selected cell.

  10. Non-volatile memory for checkpoint storage

    SciTech Connect

    Blumrich, Matthias A.; Chen, Dong; Cipolla, Thomas M.; Coteus, Paul W.; Gara, Alan; Heidelberger, Philip; Jeanson, Mark J.; Kopcsay, Gerard V.; Ohmacht, Martin; Takken, Todd E.

    2014-07-22

    A system, method and computer program product for supporting system initiated checkpoints in high performance parallel computing systems and storing of checkpoint data to a non-volatile memory storage device. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity. In one embodiment, the non-volatile memory is a pluggable flash memory card.

  11. Nonvolatile Memory Technology for Space Applications

    NASA Technical Reports Server (NTRS)

    Oldham, Timothy R.; Irom, Farokh; Friendlich, Mark; Nguyen, Duc; Kim, Hak; Berg, Melanie; LaBel, Kenneth A.

    2010-01-01

    This slide presentation reviews several forms of nonvolatile memory for use in space applications. The intent is to: (1) Determine inherent radiation tolerance and sensitivities, (2) Identify challenges for future radiation hardening efforts, (3) Investigate new failure modes and effects, and technology modeling programs. Testing includes total dose, single event (proton, laser, heavy ion), and proton damage (where appropriate). Test vehicles are expected to be a variety of non-volatile memory devices as available including Flash (NAND and NOR), Charge Trap, Nanocrystal Flash, Magnetic Memory (MRAM), Phase Change--Chalcogenide, (CRAM), Ferroelectric (FRAM), CNT, and Resistive RAM.

  12. Functionalized Graphitic Carbon Nitride for Metal-free, Flexible and Rewritable Nonvolatile Memory Device via Direct Laser-Writing

    PubMed Central

    Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

    2014-01-01

    Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 105, which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices. PMID:25073687

  13. Functionalized graphitic carbon nitride for metal-free, flexible and rewritable nonvolatile memory device via direct laser-writing.

    PubMed

    Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

    2014-07-30

    Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 10(5), which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices.

  14. Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

    NASA Astrophysics Data System (ADS)

    Hong, Augustin Jinwoo

    Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

  15. SEMICONDUCTOR DEVICES Density-controllable nonvolatile memory devices having metal nanocrystals through chemical synthesis and assembled by spin-coating technique

    NASA Astrophysics Data System (ADS)

    Guangli, Wang; Yubin, Chen; Yi, Shi; Lin, Pu; Lijia, Pan; Rong, Zhang; Youdou, Zheng

    2010-12-01

    A novel two-step method is employed, for the first time, to fabricate nonvolatile memory devices that have metal nanocrystals. First, size-averaged Au nanocrystals are synthesized chemically; second, they are assembled into memory devices by a spin-coating technique at room temperature. This attractive approach makes it possible to tailor the diameter and control the density of nanocrystals individually. In addition, processes at room temperature prevent Au diffusion, which is a main concern for the application of metal nanocrystal-based memory. The experimental results, both the morphology characterization and the electrical measurements, reveal that there is an optimum density of nanocrystal monolayer to balance between long data retention and a large hysteresis memory window. At the same time, density-controllable devices could also feed the preferential emphasis on either memory window or retention time. All these facts confirm the advantages and novelty of our two-step method.

  16. Nonvolatile multilevel data storage memory device from controlled ambipolar charge trapping mechanism.

    PubMed

    Zhou, Ye; Han, Su-Ting; Sonar, Prashant; Roy, V A L

    2013-01-01

    The capability of storing multi-bit information is one of the most important challenges in memory technologies. An ambipolar polymer which intrinsically has the ability to transport electrons and holes as a semiconducting layer provides an opportunity for the charge trapping layer to trap both electrons and holes efficiently. Here, we achieved large memory window and distinct multilevel data storage by utilizing the phenomena of ambipolar charge trapping mechanism. As fabricated flexible memory devices display five well-defined data levels with good endurance and retention properties showing potential application in printed electronics.

  17. Overview of emerging nonvolatile memory technologies.

    PubMed

    Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  18. Overview of emerging nonvolatile memory technologies

    PubMed Central

    2014-01-01

    Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new

  19. Nonvolatile Memory Based on Nonlinear Magnetoelectric Effects

    NASA Astrophysics Data System (ADS)

    Shen, Jianxin; Cong, Junzhuang; Chai, Yisheng; Shang, Dashan; Shen, Shipeng; Zhai, Kun; Tian, Ying; Sun, Young

    2016-08-01

    The magnetoelectric effects in multiferroics have a great potential in creating next-generation memory devices. We use an alternative concept of nonvolatile memory based, on a type of nonlinear magnetoelectric effects showing a butterfly-shaped hysteresis loop. The principle is to utilize the states of the magnetoelectric coefficient, instead of magnetization, electric polarization, or resistance, to store binary information. Our experiments in a device made of the PMN-PT/Terfenol-D multiferroic heterostructure clearly demonstrate that the sign of the magnetoelectric coefficient can be repeatedly switched between positive and negative by applying electric fields, confirming the feasibility of this principle. This kind of nonvolatile memory has outstanding practical virtues such as simple structure, easy operation in writing and reading, low power, fast speed, and diverse materials available.

  20. In-chip optical CD measurements for non-volatile memory devices

    NASA Astrophysics Data System (ADS)

    Vasconi, Mauro; Kremer, Stephanie; Polli, M.; Severgnini, Ermes; Trovati, Silvia S.

    2006-03-01

    A potential limitation to a wider usage of the scatterometry technique for CD evaluation comes from its requirement of dedicated regular measurement gratings, located in wafer scribe lanes. In fact, the simplification of the original chip layout that is often requested to design these gratings may impact on their printed dimension and shape. Etched gratings might also suffer from micro-loading effects other than in the circuit. For all these reasons, measurements collected therein may not represent the real behavior of the device. On the other hand, memory devices come with large sectors that usually possess the characteristics required for a proper scatterometry evaluation. In particular, for a leading edge flash process this approach is in principle feasible for the most critical process steps. The impact of potential drawbacks, mainly lack of pattern regularity within the tool probe area, is investigated. More, a very large sampling plan on features with equal nominal CD and density spread over the same exposure shot becomes feasible, thus yielding a deeper insight of the overall lithographic process window and a quantitative method to evaluate process equipment performance along time by comparison to acceptance data and/or last preventive maintenance. All the results gathered in the device main array are compared to those collected in standard scatterometry targets, tailored to the characteristics of the considered layers in terms of designed CD, pitch, stack and orientation.

  1. Superior endurance performance of nonvolatile memory devices based on discrete storage in surface-nitrided Si nanocrystals

    NASA Astrophysics Data System (ADS)

    Yu, Jie; Chen, Kunji; Ma, Zhongyuan; Zhang, Xinxin; Jiang, Xiaofan; Huang, Xinfan; Zhang, Yongxing; Wang, Lingling

    2016-01-01

    The surface-nitrided silicon nanocrystals (Si-NCs) floating gate nonvolatile memory (NVM) devices were fabricated by 0.13 μm node CMOS technology. The surface-nitrided Si-NCs were formed in-situ by low-pressure chemical vapor deposition and followed by nitridation treatment in NH3 ambient. It is found that the nitridation treatment not only enhances the control effect of gate voltage on channel carriers by passivation of the Si-NCs surface defects but also suppresses releasing of the stored carriers among the neighboring Si-NCs and leakage from Si-NCs to channel through the tunneling oxide by a silicon nitride cover layer acted as potential barrier. Consequently, the storage carriers are fully discrete in the Si-NCs, which are different from that in the conventional poly-crystal Si or SONOS floating gate NVM devices. The surface-nitrided Si-NCs NVM devices show lower subthreshold swing value of 0.13 V/decade, faster P/E speed characteristics of 1 μs at ±7 V, and good retention characteristics at room temperature. Furthermore, due to the improvement of the tunneling oxide quality by nitridation treatment, the stable memory window of 1.7 V has been kept after 107 P/E cycles, showing superior endurance characteristics with the good retention characteristics. Our fabrication of surface-nitrided Si-NCs floating gate NVM is compatible with the standard CMOS technology, which may be employed in the 3-D NAND technology to further improve the device performance.

  2. Cellulose Nanofiber Paper as an Ultra Flexible Nonvolatile Memory

    PubMed Central

    Nagashima, Kazuki; Koga, Hirotaka; Celano, Umberto; Zhuge, Fuwei; Kanai, Masaki; Rahong, Sakon; Meng, Gang; He, Yong; De Boeck, Jo; Jurczak, Malgorzata; Vandervorst, Wilfried; Kitaoka, Takuya; Nogi, Masaya; Yanagida, Takeshi

    2014-01-01

    On the development of flexible electronics, a highly flexible nonvolatile memory, which is an important circuit component for the portability, is necessary. However, the flexibility of existing nonvolatile memory has been limited, e.g. the smallest radius into which can be bent has been millimeters range, due to the difficulty in maintaining memory properties while bending. Here we propose the ultra flexible resistive nonvolatile memory using Ag-decorated cellulose nanofiber paper (CNP). The Ag-decorated CNP devices showed the stable nonvolatile memory effects with 6 orders of ON/OFF resistance ratio and the small standard deviation of switching voltage distribution. The memory performance of CNP devices can be maintained without any degradation when being bent down to the radius of 350 μm, which is the smallest value compared to those of existing any flexible nonvolatile memories. Thus the present device using abundant and mechanically flexible CNP offers a highly flexible nonvolatile memory for portable flexible electronics. PMID:24985164

  3. Multilevel characteristics and memory mechanisms for nonvolatile memory devices based on CuInS{sub 2} quantum dot-polymethylmethacrylate nanocomposites

    SciTech Connect

    Zhou, Yang; Yun, Dong Yeol; Kim, Tae Whan; Kim, Sang Wook

    2014-12-08

    Nonvolatile memory devices based on CuInS{sub 2} (CIS) quantum dots (QDs) embedded in a polymethylmethacrylate (PMMA) layer were fabricated using spin-coating method. The memory window widths of the capacitance-voltage (C-V) curves for the Al/CIS QDs embedded in PMMA layer/p-Si devices were 0.3, 0.6, and 1.0 V for sweep voltages of ±3, ±5, and ±7 V, respectively. Capacitance-cycle data demonstrated that the charge-trapping capability of the devices with an ON/OFF ratio value of 2.81 × 10{sup −10} was maintained for 8 × 10{sup 3} cycles without significant degradation and that the extrapolation of the ON/OFF ratio value to 1 × 10{sup 6} cycles converged to 2.40 × 10{sup −10}, indicative of the good stability of the devices. The memory mechanisms for the devices are described on the basis of the C-V curves and the energy-band diagrams.

  4. Black phosphorus nonvolatile transistor memory.

    PubMed

    Lee, Dain; Choi, Yongsuk; Hwang, Euyheon; Kang, Moon Sung; Lee, Seungwoo; Cho, Jeong Ho

    2016-04-28

    We demonstrated nanofloating gate transistor memory devices (NFGTMs) using mechanically-exfoliated few-layered black phosphorus (BP) channels and gold nanoparticle (AuNPs) charge trapping layers. The resulting BP-NFGTMs exhibited excellent memory performances, including the five-level data storage, large memory window (58.2 V), stable retention (10(4) s), and cyclic endurance (1000 cycles). PMID:27074903

  5. Black phosphorus nonvolatile transistor memory

    NASA Astrophysics Data System (ADS)

    Lee, Dain; Choi, Yongsuk; Hwang, Euyheon; Kang, Moon Sung; Lee, Seungwoo; Cho, Jeong Ho

    2016-04-01

    We demonstrated nanofloating gate transistor memory devices (NFGTMs) using mechanically-exfoliated few-layered black phosphorus (BP) channels and gold nanoparticle (AuNPs) charge trapping layers. The resulting BP-NFGTMs exhibited excellent memory performances, including the five-level data storage, large memory window (58.2 V), stable retention (104 s), and cyclic endurance (1000 cycles).We demonstrated nanofloating gate transistor memory devices (NFGTMs) using mechanically-exfoliated few-layered black phosphorus (BP) channels and gold nanoparticle (AuNPs) charge trapping layers. The resulting BP-NFGTMs exhibited excellent memory performances, including the five-level data storage, large memory window (58.2 V), stable retention (104 s), and cyclic endurance (1000 cycles). Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr02078j

  6. Securing non-volatile memory regions

    DOEpatents

    Faraboschi, Paolo; Ranganathan, Parthasarathy; Muralimanohar, Naveen

    2013-08-20

    Methods, apparatus and articles of manufacture to secure non-volatile memory regions are disclosed. An example method disclosed herein comprises associating a first key pair and a second key pair different than the first key pair with a process, using the first key pair to secure a first region of a non-volatile memory for the process, and using the second key pair to secure a second region of the non-volatile memory for the same process, the second region being different than the first region.

  7. Core-Shell Zn x Cd1- x Se/Zn y Cd1- y Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

    NASA Astrophysics Data System (ADS)

    Al-Amoody, Fuad; Suarez, Ernesto; Rodriguez, Angel; Heller, E.; Huang, Wenli; Jain, F.

    2011-08-01

    This paper presents a floating quantum dot (QD) gate nonvolatile memory device using high-energy-gap Zn y Cd1- y Se-cladded Zn x Cd1- x Se quantum dots ( y > x) with tunneling layers comprising nearly lattice-matched semiconductors (e.g., ZnS/ZnMgS) on Si channels. Also presented is the fabrication of an electroluminescent (EL) device with embedded cladded ZnCdSe quantum dots. These ZnCdSe quantum dots were embedded between indium tin oxide (ITO) on glass and a top Schottky metal electrode deposited on a thin CsF barrier. These QDs, which were nucleated in a photo-assisted microwave plasma (PMP) metalorganic chemical vapor deposition (MOCVD) reactor, were grown between the source and drain regions on a p-type silicon substrate of the nonvolatile memory device. The composition of QD cladding, which relates to the value of y in Zn y Cd1- y Se, was engineered by the intensity of ultraviolet light, which controlled the incorporation of zinc in ZnCdSe. The QD quality is comparable to those deposited by other methods. Characteristics and modeling of the II-VI quantum dots as well as two diverse types of devices are presented in this paper.

  8. Flexible non-volatile optical memory thin-film transistor device with over 256 distinct levels based on an organic bicomponent blend.

    PubMed

    Leydecker, Tim; Herder, Martin; Pavlica, Egon; Bratina, Gvido; Hecht, Stefan; Orgiu, Emanuele; Samorì, Paolo

    2016-09-01

    Organic nanomaterials are attracting a great deal of interest for use in flexible electronic applications such as logic circuits, displays and solar cells. These technologies have already demonstrated good performances, but flexible organic memories are yet to deliver on all their promise in terms of volatility, operational voltage, write/erase speed, as well as the number of distinct attainable levels. Here, we report a multilevel non-volatile flexible optical memory thin-film transistor based on a blend of a reference polymer semiconductor, namely poly(3-hexylthiophene), and a photochromic diarylethene, switched with ultraviolet and green light irradiation. A three-terminal device featuring over 256 (8 bit storage) distinct current levels was fabricated, the memory states of which could be switched with 3 ns laser pulses. We also report robustness over 70 write-erase cycles and non-volatility exceeding 500 days. The device was implemented on a flexible polyethylene terephthalate substrate, validating the concept for integration into wearable electronics and smart nanodevices.

  9. Flexible non-volatile optical memory thin-film transistor device with over 256 distinct levels based on an organic bicomponent blend.

    PubMed

    Leydecker, Tim; Herder, Martin; Pavlica, Egon; Bratina, Gvido; Hecht, Stefan; Orgiu, Emanuele; Samorì, Paolo

    2016-09-01

    Organic nanomaterials are attracting a great deal of interest for use in flexible electronic applications such as logic circuits, displays and solar cells. These technologies have already demonstrated good performances, but flexible organic memories are yet to deliver on all their promise in terms of volatility, operational voltage, write/erase speed, as well as the number of distinct attainable levels. Here, we report a multilevel non-volatile flexible optical memory thin-film transistor based on a blend of a reference polymer semiconductor, namely poly(3-hexylthiophene), and a photochromic diarylethene, switched with ultraviolet and green light irradiation. A three-terminal device featuring over 256 (8 bit storage) distinct current levels was fabricated, the memory states of which could be switched with 3 ns laser pulses. We also report robustness over 70 write-erase cycles and non-volatility exceeding 500 days. The device was implemented on a flexible polyethylene terephthalate substrate, validating the concept for integration into wearable electronics and smart nanodevices. PMID:27323302

  10. Flexible non-volatile optical memory thin-film transistor device with over 256 distinct levels based on an organic bicomponent blend

    NASA Astrophysics Data System (ADS)

    Leydecker, Tim; Herder, Martin; Pavlica, Egon; Bratina, Gvido; Hecht, Stefan; Orgiu, Emanuele; Samorì, Paolo

    2016-09-01

    Organic nanomaterials are attracting a great deal of interest for use in flexible electronic applications such as logic circuits, displays and solar cells. These technologies have already demonstrated good performances, but flexible organic memories are yet to deliver on all their promise in terms of volatility, operational voltage, write/erase speed, as well as the number of distinct attainable levels. Here, we report a multilevel non-volatile flexible optical memory thin-film transistor based on a blend of a reference polymer semiconductor, namely poly(3-hexylthiophene), and a photochromic diarylethene, switched with ultraviolet and green light irradiation. A three-terminal device featuring over 256 (8 bit storage) distinct current levels was fabricated, the memory states of which could be switched with 3 ns laser pulses. We also report robustness over 70 write-erase cycles and non-volatility exceeding 500 days. The device was implemented on a flexible polyethylene terephthalate substrate, validating the concept for integration into wearable electronics and smart nanodevices.

  11. Flexible non-volatile optical memory thin-film transistor device with over 256 distinct levels based on an organic bicomponent blend

    NASA Astrophysics Data System (ADS)

    Leydecker, Tim; Herder, Martin; Pavlica, Egon; Bratina, Gvido; Hecht, Stefan; Orgiu, Emanuele; Samorì, Paolo

    2016-09-01

    Organic nanomaterials are attracting a great deal of interest for use in flexible electronic applications such as logic circuits, displays and solar cells. These technologies have already demonstrated good performances, but flexible organic memories are yet to deliver on all their promise in terms of volatility, operational voltage, write/erase speed, as well as the number of distinct attainable levels. Here, we report a multilevel non-volatile flexible optical memory thin-film transistor based on a blend of a reference polymer semiconductor, namely poly(3-hexylthiophene), and a photochromic diarylethene, switched with ultraviolet and green light irradiation. A three-terminal device featuring over 256 (8 bit storage) distinct current levels was fabricated, the memory states of which could be switched with 3 ns laser pulses. We also report robustness over 70 write–erase cycles and non-volatility exceeding 500 days. The device was implemented on a flexible polyethylene terephthalate substrate, validating the concept for integration into wearable electronics and smart nanodevices.

  12. A light incident angle switchable ZnO nanorod memristor: reversible switching behavior between two non-volatile memory devices.

    PubMed

    Park, Jinjoo; Lee, Seunghyup; Lee, Junghan; Yong, Kijung

    2013-11-26

    A light incident angle selectivity of a memory device is demonstrated. As a model system, the ZnO resistive switching device has been selected. Electrical signal is reversibly switched between memristor and resistor behaviors by modulating the light incident angle on the device. Moreover, a liquid passivation layer is introduced to achieve stable and reversible exchange between the memristor and WORM behaviors.

  13. Non-volatile memory based on the ferroelectric photovoltaic effect

    PubMed Central

    Guo, Rui; You, Lu; Zhou, Yang; Shiuh Lim, Zhi; Zou, Xi; Chen, Lang; Ramesh, R.; Wang, Junling

    2013-01-01

    The quest for a solid state universal memory with high-storage density, high read/write speed, random access and non-volatility has triggered intense research into new materials and novel device architectures. Though the non-volatile memory market is dominated by flash memory now, it has very low operation speed with ~10 μs programming and ~10 ms erasing time. Furthermore, it can only withstand ~105 rewriting cycles, which prevents it from becoming the universal memory. Here we demonstrate that the significant photovoltaic effect of a ferroelectric material, such as BiFeO3 with a band gap in the visible range, can be used to sense the polarization direction non-destructively in a ferroelectric memory. A prototype 16-cell memory based on the cross-bar architecture has been prepared and tested, demonstrating the feasibility of this technique. PMID:23756366

  14. Non-volatile memory based on the ferroelectric photovoltaic effect

    NASA Astrophysics Data System (ADS)

    Guo, Rui; You, Lu; Zhou, Yang; Shiuh Lim, Zhi; Zou, Xi; Chen, Lang; Ramesh, R.; Wang, Junling

    2013-06-01

    The quest for a solid state universal memory with high-storage density, high read/write speed, random access and non-volatility has triggered intense research into new materials and novel device architectures. Though the non-volatile memory market is dominated by flash memory now, it has very low operation speed with ~10 μs programming and ~10 ms erasing time. Furthermore, it can only withstand ~105 rewriting cycles, which prevents it from becoming the universal memory. Here we demonstrate that the significant photovoltaic effect of a ferroelectric material, such as BiFeO3 with a band gap in the visible range, can be used to sense the polarization direction non-destructively in a ferroelectric memory. A prototype 16-cell memory based on the cross-bar architecture has been prepared and tested, demonstrating the feasibility of this technique.

  15. Nonvolatile Rad-Hard Holographic Memory

    NASA Technical Reports Server (NTRS)

    Chao, Tien-Hsin; Zhou, Han-Ying; Reyes, George; Dragoi, Danut; Hanna, Jay

    2001-01-01

    We are investigating a nonvolatile radiation-hardened (rad-hard) holographic memory technology. Recently, a compact holographic data storage (CHDS) breadboard utilizing an innovative electro-optic scanner has been built and demonstrated for high-speed holographic data storage and retrieval. The successful integration of this holographic memory breadboard has paved the way for follow-on radiation resistance test of the photorefractive (PR) crystal, Fe:LiNbO3. We have also started the investigation of using two-photon PR crystals that are doubly doped with atoms of iron group (Ti, Cr, Mn, Cu) and of rare-earth group (Nd, Tb) for nonvolatile holographic recordings.

  16. GaAs metal-oxide-semiconductor based non-volatile flash memory devices with InAs quantum dots as charge storage nodes

    SciTech Connect

    Islam, Sk Masiul Chowdhury, Sisir; Sarkar, Krishnendu; Nagabhushan, B.; Banerji, P.; Chakraborty, S.

    2015-06-24

    Ultra-thin InP passivated GaAs metal-oxide-semiconductor based non-volatile flash memory devices were fabricated using InAs quantum dots (QDs) as charge storing elements by metal organic chemical vapor deposition technique to study the efficacy of the QDs as charge storage elements. The grown QDs were embedded between two high-k dielectric such as HfO{sub 2} and ZrO{sub 2}, which were used for tunneling and control oxide layers, respectively. The size and density of the QDs were found to be 5 nm and 1.8×10{sup 11} cm{sup −2}, respectively. The device with a structure Metal/ZrO{sub 2}/InAs QDs/HfO{sub 2}/GaAs/Metal shows maximum memory window equivalent to 6.87 V. The device also exhibits low leakage current density of the order of 10{sup −6} A/cm{sup 2} and reasonably good charge retention characteristics. The low value of leakage current in the fabricated memory device is attributed to the Coulomb blockade effect influenced by quantum confinement as well as reduction of interface trap states by ultra-thin InP passivation on GaAs prior to HfO{sub 2} deposition.

  17. Device and Circuit Modeling and Development of a Non-Volatile Random Access Memory Cell, Utilizing AN Amorphous Silicon Thin-Film Floating-Gate Transistor Based Technology.

    NASA Astrophysics Data System (ADS)

    Riggio, Salvatore Richard, Jr.

    1994-01-01

    High density storage mechanisms are generally created using either magnetic or optical implementation techniques. Both of these techniques require mechanical transport of the medium and, therefore, have low reliability factors. These devices also generate unwanted low level ambient noise, which is of particular concern when considering modern quiet office standards. Additionally, optical techniques tend to be read-only in nature. Both mechanisms exhibit random access times that are measured in milli-seconds, rather than in micro-seconds. Therefore, the creation of a non-volatile random access memory as a replacement for the above mentioned storage techniques would be of great advantage in terms of access time, reliability, and ambient noise level. Described within are the device and circuit modeling and fabrication techniques used to develop a non-volatile random access memory cell from an amorphous silicon thin -film transistor based technology. Amorphous silicon thin-film transistors are fabricated by depositing the metal, the insulator and the semiconductor materials with a sputtering mechanism in a vacuum at 220 degrees centigrade, rather than by diffusion at 2000 degrees centigrade, as is done with crystalline silicon. By depositing a metal in the insulator, which is located between the gate and the channel, and by using an insulator material with extremely high resistivity, one can store charge in the gate region for a long period of time without external power. For example, this period of time can be as little as one week or as long as over one year. With a periodic refresh, one can extend the memory time of this storage mechanism indefinitely. Thin-film transistors can be deposited on a variety of materials such as glass, quartz or plastic by means of a stationary or continuous motion fabrication system. This material can be either rigid or flexible, and can be comparatively large in size. This allows for much greater circuit density than a standard

  18. SONOS Nonvolatile Memory Cell Programming Characteristics

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

    2010-01-01

    Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory is gaining favor over conventional EEPROM FLASH memory technology. This paper characterizes the SONOS write operation using a nonquasi-static MOSFET model. This includes floating gate charge and voltage characteristics as well as tunneling current, voltage threshold and drain current characterization. The characterization of the SONOS memory cell predicted by the model closely agrees with experimental data obtained from actual SONOS memory cells. The tunnel current, drain current, threshold voltage and read drain current all closely agreed with empirical data.

  19. EDITORIAL: Non-volatile memory based on nanostructures Non-volatile memory based on nanostructures

    NASA Astrophysics Data System (ADS)

    Kalinin, Sergei; Yang, J. Joshua; Demming, Anna

    2011-06-01

    Non-volatile memory refers to the crucial ability of computers to store information once the power source has been removed. Traditionally this has been achieved through flash, magnetic computer storage and optical discs, and in the case of very early computers paper tape and punched cards. While computers have advanced considerably from paper and punched card memory devices, there are still limits to current non-volatile memory devices that restrict them to use as secondary storage from which data must be loaded and carefully saved when power is shut off. Denser, faster, low-energy non-volatile memory is highly desired and nanostructures are the critical enabler. This special issue on non-volatile memory based on nanostructures describes some of the new physics and technology that may revolutionise future computers. Phase change random access memory, which exploits the reversible phase change between crystalline and amorphous states, also holds potential for future memory devices. The chalcogenide Ge2Sb2Te5 (GST) is a promising material in this field because it combines a high activation energy for crystallization and a relatively low crystallization temperature, as well as a low melting temperature and low conductivity, which accommodates localized heating. Doping is often used to lower the current required to activate the phase change or 'reset' GST but this often aggravates other problems. Now researchers in Korea report in-depth studies of SiO2-doped GST and identify ways of optimising the material's properties for phase-change random access memory [1]. Resistance switching is an area that has attracted a particularly high level of interest for non-volatile memory technology, and a great deal of research has focused on the potential of TiO2 as a model system in this respect. Researchers at HP labs in the US have made notable progress in this field, and among the work reported in this special issue they describe means to control the switch resistance and show

  20. Simulation of Nanoscale Two-Bit Not-And-type Silicon-Oxide-Nitride-Oxide-Silicon Nonvolatile Memory Devices with a Separated Double-Gate Fin Field Effect Transistor Structure Containing Different Tunneling Oxide Thicknesses

    NASA Astrophysics Data System (ADS)

    Oh, Se Woong; Park, Sang Su; Kim, Dong Hun; Kim, Hyun Woo; Kim, Tae Whan

    2009-06-01

    Not-and (NAND)-type silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory (NVM) devices with a separated double-gate (SDG) Fin field effect transistor structure were proposed to reduce the unit cell size of such memory devices and increase their memory density in comparison with that of conventional NVM devices. The proposed memory device consisted of a pair of control gates separated along the length of the Fin channel direction. Each SDG had a different thickness of the tunneling oxide to operate the proposed memory device as a two-bit/cell device. A technology computer-aided design simulation was performed to investigate the program/erase and two-bit characteristics. The simulation results show that the proposed devices can be used to increase the scaling down capability and charge storage density of NAND-type SONOS NVM devices.

  1. EDITORIAL: Non-volatile memory based on nanostructures Non-volatile memory based on nanostructures

    NASA Astrophysics Data System (ADS)

    Kalinin, Sergei; Yang, J. Joshua; Demming, Anna

    2011-06-01

    Non-volatile memory refers to the crucial ability of computers to store information once the power source has been removed. Traditionally this has been achieved through flash, magnetic computer storage and optical discs, and in the case of very early computers paper tape and punched cards. While computers have advanced considerably from paper and punched card memory devices, there are still limits to current non-volatile memory devices that restrict them to use as secondary storage from which data must be loaded and carefully saved when power is shut off. Denser, faster, low-energy non-volatile memory is highly desired and nanostructures are the critical enabler. This special issue on non-volatile memory based on nanostructures describes some of the new physics and technology that may revolutionise future computers. Phase change random access memory, which exploits the reversible phase change between crystalline and amorphous states, also holds potential for future memory devices. The chalcogenide Ge2Sb2Te5 (GST) is a promising material in this field because it combines a high activation energy for crystallization and a relatively low crystallization temperature, as well as a low melting temperature and low conductivity, which accommodates localized heating. Doping is often used to lower the current required to activate the phase change or 'reset' GST but this often aggravates other problems. Now researchers in Korea report in-depth studies of SiO2-doped GST and identify ways of optimising the material's properties for phase-change random access memory [1]. Resistance switching is an area that has attracted a particularly high level of interest for non-volatile memory technology, and a great deal of research has focused on the potential of TiO2 as a model system in this respect. Researchers at HP labs in the US have made notable progress in this field, and among the work reported in this special issue they describe means to control the switch resistance and show

  2. Characterization of an Autonomous Non-Volatile Ferroelectric Memory Latch

    NASA Technical Reports Server (NTRS)

    John, Caroline S.; MacLeod, Todd C.; Evans, Joe; Ho, Fat D.

    2011-01-01

    We present the electrical characterization of an autonomous non-volatile ferroelectric memory latch using the principle that when an electric field is applied to a ferroelectriccapacitor,the positive and negative remnant polarization charge states of the capacitor are denoted as either data 0 or data 1. The properties of the ferroelectric material to store an electric polarization in the absence of an electric field make the device non-volatile. Further the memory latch is autonomous as it operates with the ground, power and output node connections, without any externally clocked control line. The unique quality of this latch circuit is that it can be written when powered off. The advantages of this latch over flash memories are: a) It offers unlimited reads/writes b) works on symmetrical read/write cycles. c) The latch is asynchronous. The circuit was initially developed by Radiant Technologies Inc., Albuquerque, New Mexico.

  3. Nonvolatile semiconductor memory having three dimension charge confinement

    DOEpatents

    Dawson, L. Ralph; Osbourn, Gordon C.; Peercy, Paul S.; Weaver, Harry T.; Zipperian, Thomas E.

    1991-01-01

    A layered semiconductor device with a nonvolatile three dimensional memory comprises a storage channel which stores charge carriers. Charge carriers flow laterally through the storage channel from a source to a drain. Isolation material, either a Schottky barrier or a heterojunction, located in a trench of an upper layer controllably retains the charge within the a storage portion determined by the confining means. The charge is retained for a time determined by the isolation materials' nonvolatile characteristics or until a change of voltage on the isolation material and the source and drain permit a read operation. Flow of charge through an underlying sense channel is affected by the presence of charge within the storage channel, thus the presences of charge in the memory can be easily detected.

  4. Fabrication of InGaZnO Nonvolatile Memory Devices at Low Temperature of 150 degrees C for Applications in Flexible Memory Displays and Transparency Coating on Plastic Substrates.

    PubMed

    Hanh, Nguyen Hong; Jang, Kyungsoo; Yi, Junsin

    2016-05-01

    We directly deposited amorphous InGaZnO (a-IGZO) nonvolatile memory (NVM) devices with oxynitride-oxide-dioxide (OOO) stack structures on plastic substrate by a DC pulsed magnetron sputtering and inductively coupled plasma chemical vapor deposition (ICPCVD) system, using a low-temperature of 150 degrees C. The fabricated bottom gate a-IGZO NVM devices have a wide memory window with a low operating voltage during programming and erasing, due to an effective control of the gate dielectrics. In addition, after ten years, the memory device retains a memory window of over 73%, with a programming duration of only 1 ms. Moreover, the a-IGZO films show high optical transmittance of over 85%, and good uniformity with a root mean square (RMS) roughness of 0.26 nm. This film is a promising candidate to achieve flexible displays and transparency on plastic substrates because of the possibility of low-temperature deposition, and the high transparent properties of a-IGZO films. These results demonstrate that the a-IGZO NVM devices obtained at low-temperature have a suitable programming and erasing efficiency for data storage under low-voltage conditions, in combination with excellent charge retention characteristics, and thus show great potential application in flexible memory displays. PMID:27483835

  5. Non-volatile magnetic random access memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Stadler, Henry L. (Inventor); Wu, Jiin-Chuan (Inventor)

    1994-01-01

    Improvements are made in a non-volatile magnetic random access memory. Such a memory is comprised of an array of unit cells, each having a Hall-effect sensor and a thin-film magnetic element made of material having an in-plane, uniaxial anisotropy and in-plane, bipolar remanent magnetization states. The Hall-effect sensor is made more sensitive by using a 1 m thick molecular beam epitaxy grown InAs layer on a silicon substrate by employing a GaAs/AlGaAs/InAlAs superlattice buffering layer. One improvement avoids current shunting problems of matrix architecture. Another improvement reduces the required magnetizing current for the micromagnets. Another improvement relates to the use of GaAs technology wherein high electron-mobility GaAs MESFETs provide faster switching times. Still another improvement relates to a method for configuring the invention as a three-dimensional random access memory.

  6. Ultra-flexible nonvolatile memory based on donor-acceptor diketopyrrolopyrrole polymer blends

    PubMed Central

    Zhou, Ye; Han, Su-Ting; Yan, Yan; Zhou, Li; Huang, Long-Biao; Zhuang, Jiaqing; Sonar, Prashant; Roy, V. A. L.

    2015-01-01

    Flexible memory cell array based on high mobility donor-acceptor diketopyrrolopyrrole polymer has been demonstrated. The memory cell exhibits low read voltage, high cell-to-cell uniformity and good mechanical flexibility, and has reliable retention and endurance memory performance. The electrical properties of the memory devices are systematically investigated and modeled. Our results suggest that the polymer blends provide an important step towards high-density flexible nonvolatile memory devices. PMID:26029856

  7. Ultra-flexible nonvolatile memory based on donor-acceptor diketopyrrolopyrrole polymer blends.

    PubMed

    Zhou, Ye; Han, Su-Ting; Yan, Yan; Zhou, Li; Huang, Long-Biao; Zhuang, Jiaqing; Sonar, Prashant; Roy, V A L

    2015-01-01

    Flexible memory cell array based on high mobility donor-acceptor diketopyrrolopyrrole polymer has been demonstrated. The memory cell exhibits low read voltage, high cell-to-cell uniformity and good mechanical flexibility, and has reliable retention and endurance memory performance. The electrical properties of the memory devices are systematically investigated and modeled. Our results suggest that the polymer blends provide an important step towards high-density flexible nonvolatile memory devices.

  8. Active Flash: Performance-Energy Tradeoffs for Out-of-Core Processing on Non-Volatile Memory Devices

    SciTech Connect

    Boboila, Simona; Kim, Youngjae; Vazhkudai, Sudharshan S; Desnoyers, Peter; Shipman, Galen M

    2012-01-01

    In this abstract, we study the performance and energy tradeoffs involved in migrating data analysis into the flash device, a process we refer to as Active Flash. The Active Flash paradigm is similar to 'active disks', which has received considerable attention. Active Flash allows us to move processing closer to data, thereby minimizing data movement costs and reducing power consumption. It enables true out-of-core computation. The conventional definition of out-of-core solvers refers to an approach to process data that is too large to fit in the main memory and, consequently, requires access to disk. However, in Active Flash, processing outside the host CPU literally frees the core and achieves real 'out-of-core' analysis. Moving analysis to data has long been desirable, not just at this level, but at all levels of the system hierarchy. However, this requires a detailed study on the tradeoffs involved in achieving analysis turnaround under an acceptable energy envelope. To this end, we first need to evaluate if there is enough computing power on the flash device to warrant such an exploration. Flash processors require decent computing power to run the internal logic pertaining to the Flash Translation Layer (FTL), which is responsible for operations such as address translation, garbage collection (GC) and wear-leveling. Modern SSDs are composed of multiple packages and several flash chips within a package. The packages are connected using multiple I/O channels to offer high I/O bandwidth. SSD computing power is also expected to be high enough to exploit such inherent internal parallelism within the drive to increase the bandwidth and to handle fast I/O requests. More recently, SSD devices are being equipped with powerful processing units and are even embedded with multicore CPUs (e.g. ARM Cortex-A9 embedded processor is advertised to reach 2GHz frequency and deliver 5000 DMIPS; OCZ RevoDrive X2 SSD has 4 SandForce controllers, each with 780MHz max frequency

  9. An FPGA-Based Test-Bed for Reliability and Endurance Characterization of Non-Volatile Memory

    NASA Technical Reports Server (NTRS)

    Rao, Vikram; Patel, Jagdish; Patel, Janak; Namkung, Jeffrey

    2001-01-01

    Memory technologies are divided into two categories. The first category, nonvolatile memories, are traditionally used in read-only or read-mostly applications because of limited write endurance and slow write speed. These memories are derivatives of read only memory (ROM) technology, which includes erasable programmable ROM (EPROM), electrically-erasable programmable ROM (EEPROM), Flash, and more recent ferroelectric non-volatile memory technology. Nonvolatile memories are able to retain data in the absence of power. The second category, volatile memories, are random access memory (RAM) devices including SRAM and DRAM. Writing to these memories is fast and write endurance is unlimited, so they are most often used to store data that change frequently, but they cannot store data in the absence of power. Nonvolatile memory technologies with better future potential are FRAM, Chalcogenide, GMRAM, Tunneling MRAM, and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) EEPROM.

  10. Nonvolatile write-once-read-many times memory devices based on the composites of poly(4-vinylphenol)/Vulcan XC-72.

    PubMed

    Song, Sunghoon; Kim, Tae-Wook; Cho, Byungjin; Ji, Yongsung; Lee, Takhee

    2011-05-01

    We fabricated write-once-read-many times (WORM) type organic memory devices in 8 x 8 cross-bar structure. The active material for organic based WORM memory devices is mixture of both poly(4-vinyphenol) (PVP) and Vulcan XC-72s. From the electrical characteristics of the WORM memory devices, we observed two different resistance states, low resistance state and high resistance state, with six orders of ON/OFF ratio (I(ON)/I(OFF) - 10(6)). In addition, the WORM memory devices were maintained for longer than 50000 seconds without any serious degradation.

  11. Radiation and Reliability Concerns for Modern Nonvolatile Memory Technology

    NASA Technical Reports Server (NTRS)

    Oldham, Timothy R.; Friendlich, Mark R.; Kim, Hak S.; Berg, Melanie D.; LaBel, Kenneth A.; Buchner, S. P.; McMorrow, D.; Mavis, D. G.; Eaton, P. H.; Castillo, J.

    2011-01-01

    Commercial nonvolatile memory technology is attractive for space applications, but radiation issues are serious concerns. In addition, we discuss combined radiation/reliability concerns which are only beginning to be addressed.

  12. Non-Volatile Memory Technology Symposium 2000: Proceedings

    NASA Technical Reports Server (NTRS)

    Aranki, Nazeeh (Editor)

    2000-01-01

    This publication contains the proceedings for the Non-Volatile Memory Technology Symposium 2000 that was held on November 15-16, 2000 in Arlington, Virginia. The proceedings contains a wide range of papers that cover the presentations of myriad advances in the nonvolatile memory technology during the recent past including memory cell design, simulations, radiation environment, and emerging memory technologies. The papers presented in the proceedings address the design challenges and applications and deals with newer, emerging memory technologies as well as related issues of radiation environment and die packaging.

  13. Single-crystal C60 needle/CuPc nanoparticle double floating-gate for low-voltage organic transistors based non-volatile memory devices.

    PubMed

    Chang, Hsuan-Chun; Lu, Chien; Liu, Cheng-Liang; Chen, Wen-Chang

    2015-01-01

    Low-voltage organic field-effect transistor memory devices exhibiting a wide memory window, low power consumption, acceptable retention, endurance properties, and tunable memory performance are fabricated. The performance is achieved by employing single-crystal C60 needles and copper phthalocyanine nanoparticles to produce an ambipolar (hole/electron) trapping effect in a double floating-gate architecture. PMID:25358891

  14. Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

    SciTech Connect

    Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong

    2014-10-20

    High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

  15. Organic field-effect transistor nonvolatile memories utilizing sputtered C nanoparticles as nano-floating-gate

    NASA Astrophysics Data System (ADS)

    Liu, Jie; Liu, Chang-Hai; She, Xiao-Jian; Sun, Qi-Jun; Gao, Xu; Wang, Sui-Dong

    2014-10-01

    High-performance organic field-effect transistor nonvolatile memories have been achieved using sputtered C nanoparticles as the nano-floating-gate. The sputtered C nano-floating-gate is prepared with low-cost material and simple process, forming uniform and discrete charge trapping sites covered by a smooth and complete polystyrene layer. The devices show large memory window, excellent retention capability, and programming/reading/erasing/reading endurance. The sputtered C nano-floating-gate can effectively trap both holes and electrons, and it is demonstrated to be suitable for not only p-type but also n-type organic field-effect transistor nonvolatile memories.

  16. Covalent assembly of gold nanoparticles for nonvolatile memory applications.

    PubMed

    Gupta, Raju Kumar; Kusuma, Damar Yoga; Lee, P S; Srinivasan, M P

    2011-12-01

    This work reports a versatile approach for enhancing the stability of nonvolatile memory devices through covalent assembly of functionalized gold nanoparticles. 11-mercapto-1-undecanol functionalized gold nanoparticles (AuNPs) with a narrow size distribution and particle size of about 5 nm were synthesized. Then, the AuNPs were immobilized on a SiO(2) substrate using a functionalized polymer as a surface modifier. Microscopic and spectroscopic techniques were used to characterize the AuNPs and their morphology before and after immobilization. Finally, a metal-insulator-semiconductor (MIS) type memory device with such covalently anchored AuNPs as a charge trapping layer was fabricated. The MIS structure showed well-defined counterclockwise C-V hysteresis curves indicating a good memory effect. The flat band voltage shift was 1.64 V at a swapping voltage between ±7 V. Furthermore, the MIS structure showed a good retention characteristic up to 20,000 s. The present synthetic route to covalently immobilize gold nanoparticles system will be a step towards realization for the nanoparticle-based electronic devices and related applications.

  17. Non-exponential resistive switching in Ag2S memristors: a key to nanometer-scale non-volatile memory devices.

    PubMed

    Gubicza, Agnes; Csontos, Miklós; Halbritter, András; Mihály, György

    2015-03-14

    The dynamics of resistive switchings in nanometer-scale metallic junctions formed between an inert metallic tip and an Ag film covered by a thin Ag2S layer are investigated. Our thorough experimental analysis and numerical simulations revealed that the resistance change upon a switching bias voltage pulse exhibits a strongly non-exponential behaviour yielding markedly different response times at different bias levels. Our results demonstrate the merits of Ag2S nanojunctions as nanometer-scale non-volatile memory cells with stable switching ratios, high endurance as well as fast response to write/erase, and an outstanding stability against read operations at technologically optimal bias and current levels. PMID:25684683

  18. Nonvolatile memory behavior of nanocrystalline cellulose/graphene oxide composite films

    SciTech Connect

    Valentini, L. Cardinali, M.; Fortunati, E.; Kenny, J. M.

    2014-10-13

    With the continuous advance of modern electronics, the demand for nonvolatile memory cells rapidly grows. In order to develop post-silicon electronic devices, it is necessary to find innovative solutions to the eco-sustainability problem of materials for nonvolatile memory cells. In this work, we realized a resistive memory device based on graphene oxide (GO) and GO/cellulose nanocrystals (CNC) thin films. Aqueous solutions of GO and GO with CNC have been prepared and drop cast between two metal electrodes. Such thin-film based devices showed a transition between low and high conductivity states upon the forward and backward sweeping of an external electric field. This reversible current density transition behavior demonstrates a typical memory characteristic. The obtained results open an easy route for electronic information storage based on the integration of nanocrystalline cellulose onto graphene based devices.

  19. Method for refreshing a non-volatile memory

    DOEpatents

    Riekels, James E.; Schlesinger, Samuel

    2008-11-04

    A non-volatile memory and a method of refreshing a memory are described. The method includes allowing an external system to control refreshing operations within the memory. The memory may generate a refresh request signal and transmit the refresh request signal to the external system. When the external system finds an available time to process the refresh request, the external system acknowledges the refresh request and transmits a refresh acknowledge signal to the memory. The memory may also comprise a page register for reading and rewriting a data state back to the memory. The page register may comprise latches in lieu of supplemental non-volatile storage elements, thereby conserving real estate within the memory.

  20. SONOS technology for commercial and military nonvolatile memory applications

    NASA Astrophysics Data System (ADS)

    Adams, D.; Farrell, P.; Jacunski, M.; Williams, D.; Jakubczak, J.; Knoll, M.; Murray, J.

    Silicon Oxide Nitride Oxide Semiconductor (SONOS) technology is well suited for military and commercial nonvolatile memory applications. Excellent long term memory retention, radiation hardness, and endurance has been demonstrated with this technology. This paper summarizes our data in these areas for SONOS technology.

  1. Development of non-volatile semiconductor memory

    NASA Technical Reports Server (NTRS)

    Heikkila, W. W.

    1979-01-01

    A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

  2. Nanopatterned ferroelectrics for ultrahigh density rad-hard nonvolatile memories.

    SciTech Connect

    Brennecka, Geoffrey L.; Stevens, Jeffrey; Scrymgeour, David; Gin, Aaron V.; Tuttle, Bruce Andrew

    2010-09-01

    Radiation hard nonvolatile random access memory (NVRAM) is a crucial component for DOE and DOD surveillance and defense applications. NVRAMs based upon ferroelectric materials (also known as FERAMs) are proven to work in radiation-rich environments and inherently require less power than many other NVRAM technologies. However, fabrication and integration challenges have led to state-of-the-art FERAMs still being fabricated using a 130nm process while competing phase-change memory (PRAM) has been demonstrated with a 20nm process. Use of block copolymer lithography is a promising approach to patterning at the sub-32nm scale, but is currently limited to self-assembly directly on Si or SiO{sub 2} layers. Successful integration of ferroelectrics with discrete and addressable features of {approx}15-20nm would represent a 100-fold improvement in areal memory density and would enable more highly integrated electronic devices required for systems advances. Towards this end, we have developed a technique that allows us to carry out block copolymer self-assembly directly on a huge variety of different materials and have investigated the fabrication, integration, and characterization of electroceramic materials - primarily focused on solution-derived ferroelectrics - with discrete features of {approx}20nm and below. Significant challenges remain before such techniques will be capable of fabricating fully integrated NVRAM devices, but the tools developed for this effort are already finding broader use. This report introduces the nanopatterned NVRAM device concept as a mechanism for motivating the subsequent studies, but the bulk of the document will focus on the platform and technology development.

  3. Physical principles and current status of emerging non-volatile solid state memories

    NASA Astrophysics Data System (ADS)

    Wang, L.; Yang, C.-H.; Wen, J.

    2015-07-01

    Today the influence of non-volatile solid-state memories on persons' lives has become more prominent because of their non-volatility, low data latency, and high robustness. As a pioneering technology that is representative of non-volatile solidstate memories, flash memory has recently seen widespread application in many areas ranging from electronic appliances, such as cell phones and digital cameras, to external storage devices such as universal serial bus (USB) memory. Moreover, owing to its large storage capacity, it is expected that in the near future, flash memory will replace hard-disk drives as a dominant technology in the mass storage market, especially because of recently emerging solid-state drives. However, the rapid growth of the global digital data has led to the need for flash memories to have larger storage capacity, thus requiring a further downscaling of the cell size. Such a miniaturization is expected to be extremely difficult because of the well-known scaling limit of flash memories. It is therefore necessary to either explore innovative technologies that can extend the areal density of flash memories beyond the scaling limits, or to vigorously develop alternative non-volatile solid-state memories including ferroelectric random-access memory, magnetoresistive random-access memory, phase-change random-access memory, and resistive random-access memory. In this paper, we review the physical principles of flash memories and their technical challenges that affect our ability to enhance the storage capacity. We then present a detailed discussion of novel technologies that can extend the storage density of flash memories beyond the commonly accepted limits. In each case, we subsequently discuss the physical principles of these new types of non-volatile solid-state memories as well as their respective merits and weakness when utilized for data storage applications. Finally, we predict the future prospects for the aforementioned solid-state memories for

  4. Numerical simulation study of organic nonvolatile memory with polysilicon floating gate

    NASA Astrophysics Data System (ADS)

    Zhao-wen, Yan; Jiao, Wang; Jian-li, Qiao; Wen-jie, Chen; Pan, Yang; Tong, Xiao; Jian-hong, Yang

    2016-06-01

    A polysilicon-based organic nonvolatile floating-gate memory device with a bottom-gate top-contact configuration is investigated, in which polysilicon is sandwiched between oxide layers as a floating gate. Simulations for the electrical characteristics of the polysilicon floating gate-based memory device are performed. The shifted transfer characteristics and corresponding charge trapping mechanisms during programing and erasing (P/E) operations at various P/E voltages are discussed. The simulated results show that present memory exhibits a large memory window of 57.5 V, and a high read current on/off ratio of ≈ 103. Compared with the reported experimental results, these simulated results indicate that the polysilicon floating gate based memory device demonstrates remarkable memory effects, which shows great promise in device designing and practical application.

  5. Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

    PubMed

    Ng, Tse Nga; Schwartz, David E; Lavery, Leah L; Whiting, Gregory L; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

    2012-01-01

    Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

  6. Non-Volatile Memory Technology Symposium 2001: Proceedings

    NASA Technical Reports Server (NTRS)

    Aranki, Nazeeh; Daud, Taher; Strauss, Karl

    2001-01-01

    This publication contains the proceedings for the Non-Volatile Memory Technology Symposium 2001 that was held on November 7-8, 2001 in San Diego, CA. The proceedings contains a a wide range of papers that cover current and new memory technologies including Flash memories, Magnetic Random Access Memories (MRAM and GMRAM), Ferro-electric RAM (FeRAM), and Chalcogenide RAM (CRAM). The papers presented in the proceedings address the use of these technologies for space applications as well as radiation effects and packaging issues.

  7. Electrostatically transparent graphene quantum-dot trap layers for efficient nonvolatile memory

    SciTech Connect

    Kim, Young Rae; Jo, Yong Eun; Sung, Yeo Hyun; Won, Ui Yeon; Shin, Yong Seon; Kang, Won Tae; Yu, Woo Jong E-mail: micco21@skku.edu; Lee, Young Hee E-mail: micco21@skku.edu

    2015-03-09

    In this study, we have demonstrated nonvolatile memory devices using graphene quantum-dots (GQDs) trap layers with indium zinc oxide (IZO) semiconductor channel. The Fermi-level of GQD was effectively modulated by tunneling electrons near the Dirac point because of limited density of states and weak electrostatic screening in monolayer graphene. As a result, large gate modulation was driven in IZO channel to achieve a subthreshold swing of 5.21 V/dec (300 nm SiO{sub 2} gate insulator), while Au quantum-dots memory shows 15.52 V/dec because of strong electrostatic screening in metal quantum-dots. Together, discrete charge traps of GQDs enable stable performance in the endurance test beyond 800 cycles of programming and erasing. Our study suggests the exciting potential of GQD trap layers to be used for a highly promising material in non-volatile memory devices.

  8. A graphene-based non-volatile memory

    NASA Astrophysics Data System (ADS)

    Loisel, Loïc.; Maurice, Ange; Lebental, Bérengère; Vezzoli, Stefano; Cojocaru, Costel-Sorin; Tay, Beng Kang

    2015-09-01

    We report on the development and characterization of a simple two-terminal non-volatile graphene switch. After an initial electroforming step during which Joule heating leads to the formation of a nano-gap impeding the current flow, the devices can be switched reversibly between two well-separated resistance states. To do so, either voltage sweeps or pulses can be used, with the condition that VSET < VRESET , where SET is the process decreasing the resistance and RESET the process increasing the resistance. We achieve reversible switching on more than 100 cycles with resistance ratio values of 104. This approach of graphene memory is competitive as compared to other graphene approaches such as redox of graphene oxide, or electro-mechanical switches with suspended graphene. We suggest a switching model based on a planar electro-mechanical switch, whereby electrostatic, elastic and friction forces are competing to switch devices ON and OFF, and the stability in the ON state is achieved by the formation of covalent bonds between the two stretched sides of the graphene, hence bridging the nano-gap. Developing a planar electro-mechanical switch enables to obtain the advantages of electro-mechanical switches while avoiding most of their drawbacks.

  9. A review of emerging non-volatile memory (NVM) technologies and applications

    NASA Astrophysics Data System (ADS)

    Chen, An

    2016-11-01

    This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

  10. Low-power non-volatile spintronic memory: STT-RAM and beyond

    NASA Astrophysics Data System (ADS)

    Wang, K. L.; Alzate, J. G.; Khalili Amiri, P.

    2013-02-01

    The quest for novel low-dissipation devices is one of the most critical for the future of semiconductor technology and nano-systems. The development of a low-power, universal memory will enable a new paradigm of non-volatile computation. Here we consider STT-RAM as one of the emerging candidates for low-power non-volatile memory. We show different configurations for STT memory and demonstrate strategies to optimize key performance parameters such as switching current and energy. The energy and scaling limits of STT-RAM are discussed, leading us to argue that alternative writing mechanisms may be required to achieve ultralow power dissipation, a necessary condition for direct integration with CMOS at the gate level for non-volatile logic purposes. As an example, we discuss the use of the giant spin Hall effect as a possible alternative to induce magnetization reversal in magnetic tunnel junctions using pure spin currents. Further, we concentrate on magnetoelectric effects, where electric fields are used instead of spin-polarized currents to manipulate the nanomagnets, as another candidate solution to address the challenges of energy efficiency and density. The possibility of an electric-field-controlled magnetoelectric RAM as a promising candidate for ultralow-power non-volatile memory is discussed in the light of experimental data demonstrating voltage-induced switching of the magnetization and reorientation of the magnetic easy axis by electric fields in nanomagnets.

  11. Coexistence of nonvolatility and volatility in Pt/Nb-doped SrTiO3/In memristive devices

    NASA Astrophysics Data System (ADS)

    Yang, M.; Bao, D. H.; Li, S. W.

    2013-12-01

    Memristive devices are triggering innovations in the fields of nonvolatile memory, digital logic, analogue circuits, neuromorphic engineering, and so on. Creating new memristive devices with unique characteristics would be significant for these emergent applications. Here we report the coexistence of nonvolatility and volatility in Pt/Nb-doped SrTiO3 (NSTO)/In memristive devices. The Pt/NSTO interface contributes a nonvolatile resistive switching behaviour, whereas the NSTO/In interface displays a volatile hysteresis loop. Combining the two interfaces in the Pt/NSTO/In devices leads to the unique coexistence of nonvolatility and volatility. The results imply more opportunities to invent new memristive devices by engineering both interfaces in metal/insulator/metal structures.

  12. Integrated photonics with programmable non-volatile memory.

    PubMed

    Song, Jun-Feng; Luo, Xian-Shu; Lim, Andy Eu-Jin; Li, Chao; Fang, Qing; Liow, Tsung-Yang; Jia, Lian-Xi; Tu, Xiao-Guang; Huang, Ying; Zhou, Hai-Feng; Lo, Guo-Qiang

    2016-01-01

    Silicon photonics integrated circuits (Si-PIC) with well-established active and passive building elements are progressing towards large-scale commercialization in optical communications and high speed optical interconnects applications. However, current Si-PICs do not have memory capabilities, in particular, the non-volatile memory functionality for energy efficient data storage. Here, we propose an electrically programmable, multi-level non-volatile photonics memory cell (PMC) fabricated by standard complementary-metal-oxide-semiconductor (CMOS) compatible processes. A micro-ring resonator (MRR) was built using the PMC to optically read the memory states. Switching energy smaller than 20 pJ was achieved. Additionally, a MRR memory array was employed to demonstrate a four-bit memory read capacity. Theoretically, this can be increased up to ~400 times using a 100 nm free spectral range broadband light source. The fundamental concept of this design provides a route to eliminate the von Neumann bottleneck. The energy-efficient optical storage can complement on-chip optical interconnects for neutral networking, memory input/output interfaces and other computational intensive applications. PMID:26941113

  13. Integrated photonics with programmable non-volatile memory

    NASA Astrophysics Data System (ADS)

    Song, Jun-Feng; Luo, Xian-Shu; Lim, Andy Eu-Jin; Li, Chao; Fang, Qing; Liow, Tsung-Yang; Jia, Lian-Xi; Tu, Xiao-Guang; Huang, Ying; Zhou, Hai-Feng; Lo, Guo-Qiang

    2016-03-01

    Silicon photonics integrated circuits (Si-PIC) with well-established active and passive building elements are progressing towards large-scale commercialization in optical communications and high speed optical interconnects applications. However, current Si-PICs do not have memory capabilities, in particular, the non-volatile memory functionality for energy efficient data storage. Here, we propose an electrically programmable, multi-level non-volatile photonics memory cell (PMC) fabricated by standard complementary-metal-oxide-semiconductor (CMOS) compatible processes. A micro-ring resonator (MRR) was built using the PMC to optically read the memory states. Switching energy smaller than 20 pJ was achieved. Additionally, a MRR memory array was employed to demonstrate a four-bit memory read capacity. Theoretically, this can be increased up to ~400 times using a 100 nm free spectral range broadband light source. The fundamental concept of this design provides a route to eliminate the von Neumann bottleneck. The energy-efficient optical storage can complement on-chip optical interconnects for neutral networking, memory input/output interfaces and other computational intensive applications.

  14. Integrated photonics with programmable non-volatile memory

    PubMed Central

    Song, Jun-Feng; Luo, Xian-Shu; Lim, Andy Eu-Jin; Li, Chao; Fang, Qing; Liow, Tsung-Yang; Jia, Lian-Xi; Tu, Xiao-Guang; Huang, Ying; Zhou, Hai-Feng; Lo, Guo-Qiang

    2016-01-01

    Silicon photonics integrated circuits (Si-PIC) with well-established active and passive building elements are progressing towards large-scale commercialization in optical communications and high speed optical interconnects applications. However, current Si-PICs do not have memory capabilities, in particular, the non-volatile memory functionality for energy efficient data storage. Here, we propose an electrically programmable, multi-level non-volatile photonics memory cell (PMC) fabricated by standard complementary-metal-oxide-semiconductor (CMOS) compatible processes. A micro-ring resonator (MRR) was built using the PMC to optically read the memory states. Switching energy smaller than 20 pJ was achieved. Additionally, a MRR memory array was employed to demonstrate a four-bit memory read capacity. Theoretically, this can be increased up to ~400 times using a 100 nm free spectral range broadband light source. The fundamental concept of this design provides a route to eliminate the von Neumann bottleneck. The energy-efficient optical storage can complement on-chip optical interconnects for neutral networking, memory input/output interfaces and other computational intensive applications. PMID:26941113

  15. Flexible Nonvolatile Polymer Memory Array on Plastic Substrate via Initiated Chemical Vapor Deposition.

    PubMed

    Jang, Byung Chul; Seong, Hyejeong; Kim, Sung Kyu; Kim, Jong Yun; Koo, Beom Jun; Choi, Junhwan; Yang, Sang Yoon; Im, Sung Gap; Choi, Sung-Yool

    2016-05-25

    Resistive random access memory based on polymer thin films has been developed as a promising flexible nonvolatile memory for flexible electronic systems. Memory plays an important role in all modern electronic systems for data storage, processing, and communication; thus, the development of flexible memory is essential for the realization of flexible electronics. However, the existing solution-processed, polymer-based RRAMs have exhibited serious drawbacks in terms of the uniformity, electrical stability, and long-term stability of the polymer thin films. Here, we present poly(1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3)-based RRAM arrays fabricated via the solvent-free technique called initiated chemical vapor deposition (iCVD) process for flexible memory application. Because of the outstanding chemical stability of pV3D3 films, the pV3D3-RRAM arrays can be fabricated by a conventional photolithography process. The pV3D3-RRAM on flexible substrates showed unipolar resistive switching memory with an on/off ratio of over 10(7), stable retention time for 10(5) s, excellent cycling endurance over 10(5) cycles, and robust immunity to mechanical stress. In addition, pV3D3-RRAMs showed good uniformity in terms of device-to-device distribution. The pV3D3-RRAM will pave the way for development of next-generation flexible nonvolatile memory devices. PMID:27142537

  16. A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement.

    PubMed

    Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

    2016-01-01

    Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates.

  17. A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement

    PubMed Central

    Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

    2016-01-01

    Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates. PMID:26763827

  18. A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement.

    PubMed

    Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

    2016-01-01

    Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates. PMID:26763827

  19. Nonvolatile GaAs Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R.; Stadler, Henry L.; Wu, Jiin-Chuan

    1994-01-01

    Proposed random-access integrated-circuit electronic memory offers nonvolatile magnetic storage. Bits stored magnetically and read out with Hall-effect sensors. Advantages include short reading and writing times and high degree of immunity to both single-event upsets and permanent damage by ionizing radiation. Use of same basic material for both transistors and sensors simplifies fabrication process, with consequent benefits in increased yield and reduced cost.

  20. Nonvolatile memory effect of a functional polyimide containing ferrocene as the electroactive moiety

    NASA Astrophysics Data System (ADS)

    Tian, Guofeng; Qi, Shengli; Chen, Fei; Shi, Lei; Hu, Wenping; Wu, Dezhen

    2011-05-01

    A functional polyimide, hexafluoroisopropyl bis(phthalic dianhydride)/4-(bis(4-aminophenyl) methyl)phenol grafted with ferrocene, was synthesized. Electrical characterization results indicate that the sandwiched devices using our synthesized polyimide as the active layer possess electrical bistability and exhibit nonvolatile memory behavior with an ON/OFF current ratio of about 103. Molecular orbitals and electronic properties are investigated by molecular simulation and cyclic voltammetry characterization. The charge transfer mechanisms in the OFF and ON states of the memory device were reasonably interpreted by using the thermionic emission and space-charge-limited-current model, respectively.

  1. Integrated, nonvolatile, high-speed analog random access memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R. (Inventor); Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor)

    1994-01-01

    This invention provides an integrated, non-volatile, high-speed random access memory. A magnetically switchable ferromagnetic or ferrimagnetic layer is sandwiched between an electrical conductor which provides the ability to magnetize the magnetically switchable layer and a magneto resistive or Hall effect material which allows sensing the magnetic field which emanates from the magnetization of the magnetically switchable layer. By using this integrated three-layer form, the writing process, which is controlled by the conductor, is separated from the storage medium in the magnetic layer and from the readback process which is controlled by the magnetoresistive layer. A circuit for implementing the memory in CMOS or the like is disclosed.

  2. A FPGA-based Measurement System for Nonvolatile Semiconductor Memory Characterization

    NASA Astrophysics Data System (ADS)

    Bu, Jiankang; White, Marvin

    2002-03-01

    Low voltage, long retention, high density SONOS nonvolatile semiconductor memory (NVSM) devices are ideally suited for PCMCIA, FLASH and 'smart' cards. The SONOS memory transistor requires characterization with an accurate, rapid measurement system with minimum disturbance to the device. The FPGA-based measurement system includes three parts: 1) a pattern generator implemented with XILINX FPGAs and corresponding software, 2) a high-speed, constant-current, threshold voltage detection circuit, 3) and a data evaluation program, implemented with a LABVIEW program. Fig. 1 shows the general block diagram of the FPGA-based measurement system. The function generator is designed and simulated with XILINX Foundation Software. Under the control of the specific erase/write/read pulses, the analog detect circuit applies operational modes to the SONOS device under test (DUT) and determines the change of the memory-state of the SONOS nonvolatile memory transistor. The TEK460 digitizes the analog threshold voltage output and sends to the PC computer. The data is filtered and averaged with a LABVIEWTM program running on the PC computer and displayed on the monitor in real time. We have implemented the pattern generator with XILINX FPGAs. Fig. 2 shows the block diagram of the pattern generator. We realized the logic control by a method of state machine design. Fig. 3 shows a small part of the state machine. The flexibility of the FPGAs enhances the capabilities of this system and allows measurement variations without hardware changes. The characterization of the nonvolatile memory transistor device under test (DUT), as function of programming voltage and time, is achieved by a high-speed, constant-current threshold voltage detection circuit. The analog detection circuit incorporating fast analog switches controlled digitally with the FPGAs. The schematic circuit diagram is shown in Fig. 4. The various operational modes for the DUT are realized with control signals applied to the

  3. Lateral electric-field-driven non-volatile four-state memory in multiferroic heterostructures

    NASA Astrophysics Data System (ADS)

    Zhou, Cai; Zhang, Chao; Yao, Jinli; Jiang, Changjun

    2016-09-01

    A non-volatile four-state memory is formed using an in-plane side-polarization configuration in a Co/(011) Pb(Mg1/3Nb2/3)O3-PbTiO3 (Co/PMN-PT) heterostructure. The resistivity vs. electric field behavior shows a change from volatile butterfly to looplike to non-volatile butterfly characteristics when the temperature decreases from 290 K to 83 K under an electric field of 10 kV/cm and then increases back to 290 K; this behavior is attributed to the strain-mediated magnetoelectric effect. In addition, the in-plane resistivity of Co film, which was measured using the four-probe technique, can be controlled both electrically and magnetically. Specifically, a non-volatile resistivity is gained by the application of electric field pulses. Additionally, a four-state memory is obtained by co-mediation of the magnetic field and electric field pulses, compared with the two different states achieved under the application of the electric field only, which indicates that our results are highly important for multi-state memory and spintronic devices applications.

  4. Hybrid Flexible Resistive Random Access Memory-Gated Transistor for Novel Nonvolatile Data Storage.

    PubMed

    Han, Su-Ting; Zhou, Ye; Chen, Bo; Wang, Chundong; Zhou, Li; Yan, Yan; Zhuang, Jiaqing; Sun, Qijun; Zhang, Hua; Roy, V A L

    2016-01-20

    Here, a single-device demonstration of novel hybrid architecture is reported to achieve programmable transistor nodes which have analogies to flash memory by incorporating a resistive switching random access memory (RRAM) device as a resistive switch gate for field effect transistor (FET) on a flexible substrate. A high performance flexible RRAM with a three-layered structure is fabricated by utilizing solution-processed MoS2 nanosheets sandwiched between poly(methyl methacrylate) polymer layers. Gate coupling with the pentacene-based transistor can be controlled by the RRAM memory state to produce a nonprogrammed state (inactive) and a programmed state (active) with a well-defined memory window. Compared to the reference flash memory device based on the MoS2 floating gate, the hybrid device presents robust access speed and retention ability. Furthermore, the hybrid RRAM-gated FET is used to build an integrated logic circuit and a wide logic window in inverter logic is achieved. The controllable, well-defined memory window, long retention time, and fast access speed of this novel hybrid device may open up new possibilities of realizing fully functional nonvolatile memory for high-performance flexible electronics.

  5. Hybrid Flexible Resistive Random Access Memory-Gated Transistor for Novel Nonvolatile Data Storage.

    PubMed

    Han, Su-Ting; Zhou, Ye; Chen, Bo; Wang, Chundong; Zhou, Li; Yan, Yan; Zhuang, Jiaqing; Sun, Qijun; Zhang, Hua; Roy, V A L

    2016-01-20

    Here, a single-device demonstration of novel hybrid architecture is reported to achieve programmable transistor nodes which have analogies to flash memory by incorporating a resistive switching random access memory (RRAM) device as a resistive switch gate for field effect transistor (FET) on a flexible substrate. A high performance flexible RRAM with a three-layered structure is fabricated by utilizing solution-processed MoS2 nanosheets sandwiched between poly(methyl methacrylate) polymer layers. Gate coupling with the pentacene-based transistor can be controlled by the RRAM memory state to produce a nonprogrammed state (inactive) and a programmed state (active) with a well-defined memory window. Compared to the reference flash memory device based on the MoS2 floating gate, the hybrid device presents robust access speed and retention ability. Furthermore, the hybrid RRAM-gated FET is used to build an integrated logic circuit and a wide logic window in inverter logic is achieved. The controllable, well-defined memory window, long retention time, and fast access speed of this novel hybrid device may open up new possibilities of realizing fully functional nonvolatile memory for high-performance flexible electronics. PMID:26578160

  6. Highly Stretchable Non-volatile Nylon Thread Memory

    NASA Astrophysics Data System (ADS)

    Kang, Ting-Kuo

    2016-04-01

    Integration of electronic elements into textiles, to afford e-textiles, can provide an ideal platform for the development of lightweight, thin, flexible, and stretchable e-textiles. This approach will enable us to meet the demands of the rapidly growing market of wearable-electronics on arbitrary non-conventional substrates. However the actual integration of the e-textiles that undergo mechanical deformations during both assembly and daily wear or satisfy the requirements of the low-end applications, remains a challenge. Resistive memory elements can also be fabricated onto a nylon thread (NT) for e-textile applications. In this study, a simple dip-and-dry process using graphene-PEDOT:PSS (poly(3,4-ethylenedioxythiophene) polystyrene sulfonate) ink is proposed for the fabrication of a highly stretchable non-volatile NT memory. The NT memory appears to have typical write-once-read-many-times characteristics. The results show that an ON/OFF ratio of approximately 103 is maintained for a retention time of 106 s. Furthermore, a highly stretchable strain and a long-term digital-storage capability of the ON-OFF-ON states are demonstrated in the NT memory. The actual integration of the knitted NT memories into textiles will enable new design possibilities for low-cost and large-area e-textile memory applications.

  7. Highly Stretchable Non-volatile Nylon Thread Memory

    PubMed Central

    Kang, Ting-Kuo

    2016-01-01

    Integration of electronic elements into textiles, to afford e-textiles, can provide an ideal platform for the development of lightweight, thin, flexible, and stretchable e-textiles. This approach will enable us to meet the demands of the rapidly growing market of wearable-electronics on arbitrary non-conventional substrates. However the actual integration of the e-textiles that undergo mechanical deformations during both assembly and daily wear or satisfy the requirements of the low-end applications, remains a challenge. Resistive memory elements can also be fabricated onto a nylon thread (NT) for e-textile applications. In this study, a simple dip-and-dry process using graphene-PEDOT:PSS (poly(3,4-ethylenedioxythiophene) polystyrene sulfonate) ink is proposed for the fabrication of a highly stretchable non-volatile NT memory. The NT memory appears to have typical write-once-read-many-times characteristics. The results show that an ON/OFF ratio of approximately 103 is maintained for a retention time of 106 s. Furthermore, a highly stretchable strain and a long-term digital-storage capability of the ON-OFF-ON states are demonstrated in the NT memory. The actual integration of the knitted NT memories into textiles will enable new design possibilities for low-cost and large-area e-textile memory applications. PMID:27072786

  8. Nonvolatile memory cells based on MoS2/graphene heterostructures.

    PubMed

    Bertolazzi, Simone; Krasnozhon, Daria; Kis, Andras

    2013-04-23

    Memory cells are an important building block of digital electronics. We combine here the unique electronic properties of semiconducting monolayer MoS2 with the high conductivity of graphene to build a 2D heterostructure capable of information storage. MoS2 acts as a channel in an intimate contact with graphene electrodes in a field-effect transistor geometry. Our prototypical all-2D transistor is further integrated with a multilayer graphene charge trapping layer into a device that can be operated as a nonvolatile memory cell. Because of its band gap and 2D nature, monolayer MoS2 is highly sensitive to the presence of charges in the charge trapping layer, resulting in a factor of 10(4) difference between memory program and erase states. The two-dimensional nature of both the contact and the channel can be harnessed for the fabrication of flexible nanoelectronic devices with large-scale integration.

  9. PREFACE: Emerging non-volatile memories: magnetic and resistive technologies Emerging non-volatile memories: magnetic and resistive technologies

    NASA Astrophysics Data System (ADS)

    Dieny, B.; Jagadish, Chennupati

    2013-02-01

    In 2010, the International Technology Roadmap for Semiconductors (ITRS) published an assessment of the potential and maturity of selected emerging research on memory technologies. Eight different technologies of non-volatile memories were compared (ferroelectric gate field-effect transistor, nano-electro-mechanical switch, spin-transfer torque random access memories (STTRAM), various types of resistive RAM, in particular redox RAM, nanothermal phase change RAM, electronic effects RAM, macromolecular memories and molecular RAM). In this report, spin-transfer torque MRAM and redox RRAM were identified as two emerging memory technologies recommended for accelerated research and development leading to scaling and commercialization of non-volatile RAM to and beyond the 16nm generation. Nowadays, there is an intense research and development effort in microelectronics on these two technologies, one based on spintronic phenomena (tunnel magnetoresistance and spin-transfer torque), the other based on migration of vacancies or ions in an insulating matrix driven by oxydo-reduction potentials. Both technologies could be used for standalone or embedded applications. In this context, it appeared timely to publish a cluster of review articles related to these two technologies. In this cluster, the first two articles introduce the general principles of spin-transfer torque RAM and of thermally assisted RAM. The third presents a broader range of applications for this integrated CMOS/magnetic tunnel junction technology for low-power electronics. The fourth paper presents more advanced research on voltage control of magnetization switching with the aim of dramatically reducing the write energy in MRAM. The last two papers deal with two categories of resistive RAM, one based on the migration of cations, the other one based on nanowires. We thank all the authors and reviewers for their contribution to this cluster issue. Our special thanks are due to Dr Olivia Roche, Publisher, and Dr

  10. Progress on a New Non-Volatile Memory for Space Based on Chalcogenide Glass

    SciTech Connect

    Maimon, J.; Hunt, K.; Rodgers, J.; Burcin, L.; Knowles, K.

    2004-02-04

    We report on the progress of a recent addition to non-volatile solid state memory technologies suited for space and other ionizing radiation environments. We summarize the material and processing science behind the current generation of chalcogenide phase-change memories fabricated on CMOS structures. The chalcogenide material used for phase-change applications in rewritable optical storage (Ge2Sb2Te5) has been integrated with a radiation hardened CMOS process to produce 64kbit memory arrays. On selected arrays electrical testing demonstrated up to 100% memory cell yield, 100ns programming and read speeds, and write currents as low as 1mA/bit. Devices functioned normally from - 55 deg. C to 125 deg. C. Write/read endurance has been demonstrated to 1 x 108 before first bit failure. Radiation results show no degradation to the hardened CMOS or effects that can be attributed to the phase-change material. Future applications of the technology are discussed.

  11. Organic one-transistor-type nonvolatile memory gated with thin ionic liquid-polymer film for low voltage operation.

    PubMed

    Hwang, Sun Kak; Park, Tae Joon; Kim, Kang Lib; Cho, Suk Man; Jeong, Beom Jin; Park, Cheolmin

    2014-11-26

    As one of the most emerging next-generation nonvolatile memories, one-transistor (1T)-type nonvolatile memories are of great attention due to their excellent memory performance and simple device architecture suitable for high density memory arrays. In particular, organic 1T-type memories containing both organic semiconductors and insulators are further beneficial because of their mechanical flexibility with low cost fabrication. Here, we demonstrate a new flexible organic 1T-type memory operating at low voltage. The low voltage operation of a memory less than 10 V was obtained by employing a polymer gate insulator solution blended with ionic liquid as a charge storage layer. Ionic liquid homogeneously dissolved in a thin poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) film gave rise to low voltage operation of a device due to its high capacitance. Simultaneously, stable charge trapping of either anions or cations efficiently occurred in the polymer matrix, dependent upon gate bias. Optimization of ionic liquid in PVDF-TrFE thus led to an air-stable and mechanically flexible organic 1T-type nonvolatile memory operating at programming voltage of ±7 V with large ON/OFF current margin of approximately 10(3), reliable time-dependent data retention of more than 10(4) seconds, and write/read endurance cycles of 80.

  12. Organic one-transistor-type nonvolatile memory gated with thin ionic liquid-polymer film for low voltage operation.

    PubMed

    Hwang, Sun Kak; Park, Tae Joon; Kim, Kang Lib; Cho, Suk Man; Jeong, Beom Jin; Park, Cheolmin

    2014-11-26

    As one of the most emerging next-generation nonvolatile memories, one-transistor (1T)-type nonvolatile memories are of great attention due to their excellent memory performance and simple device architecture suitable for high density memory arrays. In particular, organic 1T-type memories containing both organic semiconductors and insulators are further beneficial because of their mechanical flexibility with low cost fabrication. Here, we demonstrate a new flexible organic 1T-type memory operating at low voltage. The low voltage operation of a memory less than 10 V was obtained by employing a polymer gate insulator solution blended with ionic liquid as a charge storage layer. Ionic liquid homogeneously dissolved in a thin poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) film gave rise to low voltage operation of a device due to its high capacitance. Simultaneously, stable charge trapping of either anions or cations efficiently occurred in the polymer matrix, dependent upon gate bias. Optimization of ionic liquid in PVDF-TrFE thus led to an air-stable and mechanically flexible organic 1T-type nonvolatile memory operating at programming voltage of ±7 V with large ON/OFF current margin of approximately 10(3), reliable time-dependent data retention of more than 10(4) seconds, and write/read endurance cycles of 80. PMID:25341965

  13. Graphene-quantum-dot nonvolatile charge-trap flash memories.

    PubMed

    Sin Joo, Soong; Kim, Jungkil; Kang, Soo Seok; Kim, Sung; Choi, Suk-Ho; Hwang, Sung Won

    2014-06-27

    Nonvolatile flash-memory capacitors containing graphene quantum dots (GQDs) of 6, 12, and 27 nm average sizes (d) between SiO2 layers for use as charge traps have been prepared by sequential processes: ion-beam sputtering deposition (IBSD) of 10 nm SiO2 on a p-type wafer, spin-coating of GQDs on the SiO2 layer, and IBSD of 20 nm SiO2 on the GQD layer. The presence of almost a single array of GQDs at a distance of ∼13 nm from the SiO2/Si wafer interface is confirmed by transmission electron microscopy and photoluminescence. The memory window estimated by capacitance-voltage curves is proportional to d for sweep voltages wider than  ± 3 V, and for d = 27 nm the GQD memories show a maximum memory window of 8 V at a sweep voltage of  ± 10 V. The program and erase speeds are largest at d = 12 and 27 nm, respectively, and the endurance and data-retention properties are the best at d = 27 nm. These memory behaviors can be attributed to combined effects of edge state and quantum confinement. PMID:24896068

  14. Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

    SciTech Connect

    Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.

    2013-12-21

    Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

  15. Voltage-controlled nonvolatile molecular memory of an azobenzene monolayer through solution-processed reduced graphene oxide contacts.

    PubMed

    Min, Misook; Seo, Sohyeon; Lee, Sae Mi; Lee, Hyoyoung

    2013-12-23

    The solution-processed fabrication of an azobenzene (ABC10) monolayer-based nonvolatile memory device on a reduced graphene oxide (rGO) electrode is successfully accomplished. Trans--cis isomerizations of ABC10 between two rGO electrodes in a crossbar device are controlled by applied voltage. An rGO soft-contact top electrode plays an important role in the conformational-change-dependent conductance switching process of an ABC10 monolayer.

  16. Electrically Variable Resistive Memory Devices

    NASA Technical Reports Server (NTRS)

    Liu, Shangqing; Wu, Nai-Juan; Ignatiev, Alex; Charlson, E. J.

    2010-01-01

    Nonvolatile electronic memory devices that store data in the form of electrical- resistance values, and memory circuits based on such devices, have been invented. These devices and circuits exploit an electrically-variable-resistance phenomenon that occurs in thin films of certain oxides that exhibit the colossal magnetoresistive (CMR) effect. It is worth emphasizing that, as stated in the immediately preceding article, these devices function at room temperature and do not depend on externally applied magnetic fields. A device of this type is basically a thin film resistor: it consists of a thin film of a CMR material located between, and in contact with, two electrical conductors. The application of a short-duration, low-voltage current pulse via the terminals changes the electrical resistance of the film. The amount of the change in resistance depends on the size of the pulse. The direction of change (increase or decrease of resistance) depends on the polarity of the pulse. Hence, a datum can be written (or a prior datum overwritten) in the memory device by applying a pulse of size and polarity tailored to set the resistance at a value that represents a specific numerical value. To read the datum, one applies a smaller pulse - one that is large enough to enable accurate measurement of resistance, but small enough so as not to change the resistance. In writing, the resistance can be set to any value within the dynamic range of the CMR film. Typically, the value would be one of several discrete resistance values that represent logic levels or digits. Because the number of levels can exceed 2, a memory device of this type is not limited to binary data. Like other memory devices, devices of this type can be incorporated into a memory integrated circuit by laying them out on a substrate in rows and columns, along with row and column conductors for electrically addressing them individually or collectively.

  17. Quasi-unipolar pentacene films embedded with fullerene for non-volatile organic transistor memories

    SciTech Connect

    Lee, Juhee; Lee, Sungpyo; Lee, Moo Hyung; Kang, Moon Sung

    2015-02-09

    Quasi-unipolar non-volatile organic transistor memory (NOTM) can combine the best characteristics of conventional unipolar and ambipolar NOTMs and, as a result, exhibit improved device performance. Unipolar NOTMs typically exhibit a large signal ratio between the programmed and erased current signals but also require a large voltage to program and erase the memory cells. Meanwhile, an ambipolar NOTM can be programmed and erased at lower voltages, but the resulting signal ratio is small. By embedding a discontinuous n-type fullerene layer within a p-type pentacene film, quasi-unipolar NOTMs are fabricated, of which the signal storage utilizes both electrons and holes while the electrical signal relies on only hole conduction. These devices exhibit superior memory performance relative to both pristine unipolar pentacene devices and ambipolar fullerene/pentacene bilayer devices. The quasi-unipolar NOTM exhibited a larger signal ratio between the programmed and erased states while also reducing the voltage required to program and erase a memory cell. This simple approach should be readily applicable for various combinations of advanced organic semiconductors that have been recently developed and thereby should make a significant impact on organic memory research.

  18. Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

    NASA Astrophysics Data System (ADS)

    Wang, Shun; Gao, Xu; Zhong, Ya-Nan; Zhang, Zhong-Da; Xu, Jian-Long; Wang, Sui-Dong

    2016-07-01

    High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio and good memory retention.

  19. Nonvolatile polymer memory with nanoconfinement of ferroelectric crystals.

    PubMed

    Kang, Seok Ju; Bae, Insung; Shin, Yu Jin; Park, Youn Jung; Huh, June; Park, Sang-Min; Kim, Ho-Cheol; Park, Cheolmin

    2011-01-12

    We demonstrate significantly improved performance of a nonvolatile polymeric ferroelectric field effect transistor (FeFET) memory using nanoscopic confinement of poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) within self-assembled organosilicate (OS) lamellae. Periodic OS lamellae with 30 nm in width and 50 nm in periodicity were templated using block copolymer self-assembly. Confined crystallization of PVDF-TrFE not only significantly reduces gate leakage current but also facilitates ferroelectric polarization switching. These benefits are due to the elimination of structural defects and the development of an effective PVDF-TrFE crystal orientation through nanoconfinement. A bottom gate FeFET fabricated using a single-crystalline triisopropylsilylethynyl pentacene channel and PVDF-TrFE/OS hybrid gate insulator shows characteristic source-drain current hysteresis that is fully saturated at a programming voltage of ±8 V with an ON/OFF current ratio and a data retention time of approximately 10(2) and 2 h, respectively.

  20. Electrostatic Switching in Vertically Oriented Nanotubes for Nonvolatile Memory Applications

    NASA Technical Reports Server (NTRS)

    Kaul, Anupama B.; Khan, Paul; Jennings, Andrew T.; Greer, Julia R.; Megerian, Krikor G.; Allmen, Paul von

    2009-01-01

    We have demonstrated electrostatic switching in vertically oriented nanotubes or nanofibers, where a nanoprobe was used as the actuating electrode inside an SEM. When the nanoprobe was manipulated to be in close proximity to a single tube, switching voltages between 10 V - 40 V were observed, depending on the geometrical parameters. The turn-on transitions appeared to be much sharper than the turn-off transitions which were limited by the tube-to-probe contact resistances. In many cases, stiction forces at these dimensions were dominant, since the tube appeared stuck to the probe even after the voltage returned to 0 V, suggesting that such structures are promising for nonvolatile memory applications. The stiction effects, to some extent, can be adjusted by engineering the switch geometry appropriately. Nanoscale mechanical measurements were also conducted on the tubes using a custom-built anoindentor inside an SEM, from which preliminary material parameters, such as the elastic modulus, were extracted. The mechanical measurements also revealed that the tubes appear to be well adhered to the substrate. The material parameters gathered from the mechanical measurements were then used in developing an electrostatic model of the switch using a commercially available finite-element simulator. The calculated pull-in voltages appeared to be in agreement to the experimentally obtained switching voltages to first order.

  1. Effects of Heavy Ion Exposure on Nanocrystal Nonvolatile Memory

    NASA Technical Reports Server (NTRS)

    Oldham, Timothy R.; Suhail, Mohammed; Kuhn, Peter; Prinz, Erwin; Kim, Hak; LaBel, Kenneth A.

    2004-01-01

    We have irradiated engineering samples of Freescale 4M nonvolatile memories with heavy ions. They use Silicon nanocrystals as the storage element, rather than the more common floating gate. The irradiations were performed using the Texas A&M University cyclotron Single Event Effects Test Facility. The chips were tested in the static mode, and in the dynamic read mode, dynamic write (program) mode, and dynamic erase mode. All the errors observed appeared to be due to single, isolated bits, even in the program and erase modes. These errors appeared to be related to the micro-dose mechanism. All the errors corresponded to the loss of electrons from a programmed cell. The underlying physical mechanisms will be discussed in more detail later. There were no errors, which could be attributed to malfunctions of the control circuits. At the highest LET used in the test (85 MeV/mg/sq cm), however, there appeared to be a failure due to gate rupture. Failure analysis is being conducted to confirm this conclusion. There was no unambiguous evidence of latchup under any test conditions. Generally, the results on the nanocrystal technology compare favorably with results on currently available commercial floating gate technology, indicating that the technology is promising for future space applications, both civilian and military.

  2. Nonvolatile Memory Solution for Near-Term NASA Missions

    NASA Technical Reports Server (NTRS)

    Patel, J. U.; Blaes, B. R.; Mojarradi, M. M.

    2001-01-01

    Nonvolatile memory (NVM) system that could reliably function in extreme environments is one of the most critical components for many spacecrafts being developed for NASA missions to be launched in next four to seven years. NVM supports the computer system in saving and updating critical state data required for a warm restart after power cycling or in case of a power bus failure. It also provides a power independent mass storage capacity for the scientific data gathered by the instruments. In some cases the window for gathering such data is very small and occurs only once in a given mission. Commercially popular and fully developed Flash NVM technology is inappropriate for many reasons such as the limited read write cycles with slower access speeds, radiation intolerance, higher Single Event Upsets (SEU) rates, etc. It is desirable to have an NVM system based upon a robust cell technology making it immune to the SEUs and with sufficient radiation hardness. Availability of such NVM system seems to be still 5 to 10 years in the future. Meanwhile, it is possible to provide an interim hybrid solution by combining the existing rad-hard technologies. Additional information is contained in the original extended abstract.

  3. Reconfigurable magnetic logic combined with non-volatile memory in silicon

    NASA Astrophysics Data System (ADS)

    Luo, Zhaochu; Zhang, Xiaozhong

    Silicon-based complementary metal-oxide-semiconductor (CMOS) transistors have achieved great success and become the mainstream of integrated logic circuits. However, the traditional pathway to enhance computational performance and decrease cost by continuous miniaturization is approaching its fundamental limits. The recent emergence of magnetic logic devices, especially magnetic-field-based semiconductor logic devices, shows promise for surpassing the development limits of CMOS logic and arouses profound attentions. Based on our Si based magnetoresistance (MR) device, we proposed a Si based reconfigurable magnetic logic device by coupling nonlinear transport effect and Hall effect in Si, which could do all four basic Boolean logic operations including AND, OR, NOR and NAND combined with non-volatile memory. Further, we developed a Si based current-mode magnetic logic device, which allowed direct communication between different logic devices by current-induced magnetization switch effect without external intermediate magnetic-electric converters. This may result in a memory-logic integrated system leading to a non von Neumann computer.

  4. Nonvolatile memory effects in an orthoconic smectic liquid crystal mixture doped with polymer-capped gold nanoparticles.

    PubMed

    Marino, L; Marino, S; Wang, D; Bruno, E; Scaramuzza, N

    2014-06-01

    Promising applications of liquid crystal nanocomposites have driven extensive efforts to achieve non-volatile memory effects for the realization of electronic storage devices. In this context, non-volatile memory effects in an orthoconic smectic liquid crystal mixture, with and without polymer capped gold nanoparticles, were investigated. The dielectric spectroscopy technique was performed by applying a d.c. bias during the measurement or a d.c. potential before the start of the measurement in order to obtain pre-conditioning of the sample. Both techniques showed the presence of non-volatile memory effects in the pure orthoconic smectic liquid crystal mixture similar to the doped one. The results demonstrate that the addition of gold nanoparticles enhances the memory effect making it permanent. Our experimental evidence underlines the importance of the structure of the host liquid crystal and clearly suggests that the prolonged time memory effect, observed in the doped liquid crystal, is due to the electric field inducing charge transfer from the liquid crystal molecules to the gold nanoparticles, thanks to the polymer-capping which acts as an ionic charge trapper. Such an ionic trap effect is also responsible for strong reduction of total conductivity of the doped system.

  5. Biomolecule nanoparticle-induced nanocomposites with resistive switching nonvolatile memory properties

    NASA Astrophysics Data System (ADS)

    Ko, Yongmin; Ryu, Sook Won; Cho, Jinhan

    2016-04-01

    Resistive switching behavior-based memory devices are considered promising candidates for next-generation data storage because of their simple structure configuration, low power consumption, and rapid operating speed. Here, the resistive switching nonvolatile memory properties of Fe2O3 nanocomposite (NC) films prepared from the thermal calcination of layer-by-layer (LbL) assembled ferritin multilayers were successfully investigated. For this study, negatively charged ferritin nanoparticles were alternately deposited onto the Pt-coated Si substrate with positively charged poly(allylamine hydrochloride) (PAH) by solution-based electrostatic LbL assembly, and the formed multilayers were thermally calcinated to obtain a homogeneous transition metal oxide NC film through the elimination of organic components, including the protein shell of ferritin. The formed memory device exhibits a stable ON/OFF current ratio of approximately 103, with nanosecond switching times under an applied external bias. In addition, these reversible switching properties were kept stable during the repeated cycling tests of above 200 cycles and a test period of approximately 105 s under atmosphere. These solution-based approaches can provide a basis for large-area inorganic nanoparticle-based electric devices through the design of bio-nanomaterials at the molecular level.

  6. Blackcomb: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems

    SciTech Connect

    Schreiber, Robert

    2014-11-26

    Summary of technical results of Blackcomb Memory Devices We explored various different memory technologies (STTRAM, PCRAM, FeRAM, and ReRAM). The progress can be classified into three categories, below. Modeling and Tool Releases Various modeling tools have been developed over the last decade to help in the design of SRAM or DRAM-based memory hierarchies. To explore new design opportunities that NVM technologies can bring to the designers, we have developed similar high-level models for NVM, including PCRAMsim [Dong 2009], NVSim [Dong 2012], and NVMain [Poremba 2012]. NVSim is a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies. On the other side, NVMain is a cycle accurate main memory simulator designed to simulate emerging nonvolatile memories at the architectural level. We have released these models as open source tools and provided contiguous support to them. We also proposed PS3-RAM, which is a fast, portable and scalable statistical STT-RAM reliability analysis model [Wen 2012]. Design Space Exploration and Optimization With the support of these models, we explore different device/circuit optimization techniques. For example, in [Niu 2012a] we studied the power reduction technique for the application of ECC scheme in ReRAM designs and proposed to use ECC code to relax the BER (Bit Error Rate) requirement of a single memory to improve the write energy consumption and latency for both 1T1R and cross-point ReRAM designs. In [Xu 2011], we proposed a methodology to design STT-RAM for different optimization goals such as read performance, write performance and write energy by leveraging the trade-off between write current and write time of MTJ. We also studied the tradeoffs in building a reliable crosspoint Re

  7. Determining the state of non-volatile memory cells with floating gate using scanning probe microscopy

    NASA Astrophysics Data System (ADS)

    Hanzii, D.; Kelm, E.; Luapunov, N.; Milovanov, R.; Molodcova, G.; Yanul, M.; Zubov, D.

    2013-01-01

    During a failure analysis of integrated circuits, containing non-volatile memory, it is often necessary to determine its contents while Standard memory reading procedures are not applicable. This article considers how the state of NVM cells with floating gate can be determined using scanning probe microscopy. Samples preparation and measuring procedure are described with the example of Microchip microcontrollers with the EPROM memory (PIC12C508) and flash-EEPROM memory (PIC16F876A).

  8. Printed dose-recording tag based on organic complementary circuits and ferroelectric nonvolatile memories

    PubMed Central

    Nga Ng, Tse; Schwartz, David E.; Mei, Ping; Krusor, Brent; Kor, Sivkheng; Veres, Janos; Bröms, Per; Eriksson, Torbjörn; Wang, Yong; Hagel, Olle; Karlsson, Christer

    2015-01-01

    We have demonstrated a printed electronic tag that monitors time-integrated sensor signals and writes to nonvolatile memories for later readout. The tag is additively fabricated on flexible plastic foil and comprises a thermistor divider, complementary organic circuits, and two nonvolatile memory cells. With a supply voltage below 30 V, the threshold temperatures can be tuned between 0 °C and 80 °C. The time-temperature dose measurement is calibrated for minute-scale integration. The two memory bits are sequentially written in a thermometer code to provide an accumulated dose record. PMID:26307438

  9. The floating-gate non-volatile semiconductor memory--from invention to the digital age.

    PubMed

    Sze, S M

    2012-10-01

    In the past 45 years (from 1967 to 2012), the non-volatile semiconductor memory (NVSM) has emerged from a floating-gate concept to the prime technology driver of the largest industry in the world-the electronics industry. In this paper, we briefly review the historical development of NVSM and project its future trends to the year 2020. In addition, we consider NVSM's wide-range of applications from the digital cellular phone to tablet computer to digital television. As the device dimension is scaled down to the deca-nanometer regime, we expect that many innovations will be made to meet the scaling challenges, and NVSM-inspired technology will continue to enrich and improve our lives for decades to come. PMID:23421120

  10. Radiation Tests of Highly scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories--Update 2011

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Nguyen, Duc N.

    2011-01-01

    High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) 32Gb and multi-level cell (MLC) 64Gb NAND flash memories manufactured by Micron Technology.

  11. Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2010

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Nguyen, Duc N.

    2010-01-01

    High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) and multi-level cell (MLC) NAND flash memories manufactured by Micron Technology.

  12. Epitaxial Growth of Thin Ferroelectric Polymer Films on Graphene Layer for Fully Transparent and Flexible Nonvolatile Memory.

    PubMed

    Kim, Kang Lib; Lee, Wonho; Hwang, Sun Kak; Joo, Se Hun; Cho, Suk Man; Song, Giyoung; Cho, Sung Hwan; Jeong, Beomjin; Hwang, Ihn; Ahn, Jong-Hyun; Yu, Young-Jun; Shin, Tae Joo; Kwak, Sang Kyu; Kang, Seok Ju; Park, Cheolmin

    2016-01-13

    Enhancing the device performance of organic memory devices while providing high optical transparency and mechanical flexibility requires an optimized combination of functional materials and smart device architecture design. However, it remains a great challenge to realize fully functional transparent and mechanically durable nonvolatile memory because of the limitations of conventional rigid, opaque metal electrodes. Here, we demonstrate ferroelectric nonvolatile memory devices that use graphene electrodes as the epitaxial growth substrate for crystalline poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) polymer. The strong crystallographic interaction between PVDF-TrFE and graphene results in the orientation of the crystals with distinct symmetry, which is favorable for polarization switching upon the electric field. The epitaxial growth of PVDF-TrFE on a graphene layer thus provides excellent ferroelectric performance with high remnant polarization in metal/ferroelectric polymer/metal devices. Furthermore, a fully transparent and flexible array of ferroelectric field effect transistors was successfully realized by adopting transparent poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] semiconducting polymer.

  13. Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

    NASA Astrophysics Data System (ADS)

    Jayanti, Srikant

    Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG

  14. In situ and nonvolatile photoluminescence tuning and nanodomain writing demonstrated by all-solid-state devices based on graphene oxide.

    PubMed

    Tsuchiya, Takashi; Tsuruoka, Tohru; Terabe, Kazuya; Aono, Masakazu

    2015-02-24

    In situ and nonvolatile tuning of photoluminescence (PL) has been achieved based on graphene oxide (GO), the PL of which is receiving much attention because of various potential applications of the oxide (e.g., display, lighting, and nano-biosensor). The technique is based on in situ and nonvolatile tuning of the sp(2) domain fraction to the sp(3) domain fraction (sp(2)/sp(3) fraction) in GO through an electrochemical redox reaction achieved by solid electrolyte thin films. The all-solid-state variable PL device was fabricated by GO and proton-conducting mesoporous SiO2 thin films, which showed an extremely low PL background. The device successfully tuned the PL peak wavelength in a very wide range from 393 to 712 nm, covering that for chemically tuned GO, by adjusting the applied DC voltage within several hundred seconds. We also demonstrate the sp(2)/sp(3) fraction tuning using a conductive atomic force microscope. The device achieved not only writing, but also erasing of the sp(2)/sp(3)-fraction-tuned nanodomain (both directions operation). The combination of these techniques is applicable to a wide range of nano-optoelectronic devices including nonvolatile PL memory devices and on-demand rewritable biosensors that can be integrated into nano- and microtips which are transparent, ultrathin, flexible, and inexpensive.

  15. Multilevel resistive switching nonvolatile memory based on MoS2 nanosheet-embedded graphene oxide

    NASA Astrophysics Data System (ADS)

    Shin, Gwang Hyuk; Kim, Choong-Ki; Bang, Gyeong Sook; Kim, Jong Yun; Jang, Byung Chul; Koo, Beom Jun; Woo, Myung Hun; Choi, Yang-Kyu; Choi, Sung-Yool

    2016-09-01

    An increasing demand for nonvolatile memory has driven extensive research on resistive switching memory because it uses simple structures with high density, fast switching speed, and low power consumption. To improve the storage density, the application of multilevel cells is among the most promising solutions, including three-dimensional cross-point array architectures. Two-dimensional nanomaterials have several advantages as resistive switching media, including flexibility, low cost, and simple fabrication processes. However, few reports exist on multilevel nonvolatile memory and its switching mechanism. We herein present a multilevel resistive switching memory based on graphene oxide (GO) and MoS2 fabricated by a simple spin-coating process. Metallic 1T-MoS2 nanosheets, chemically exfoliated by Li intercalation, were successfully embedded between two GO layers as charge-trapping sites. The resulting stacks of GO/MoS2/GO exhibited excellent nonvolatile memory performance with at least four resistance states, >102 endurance cycles, and >104 s retention time. Furthermore, the charge transport mechanism was systematically investigated through the analysis of low-frequency 1/f noise in various resistance states, which could be modulated by the input voltage bias in the negative differential resistance region. Accordingly, we propose a strategy to achieve multilevel nonvolatile memory in which the stacked layers of two-dimensional nanosheets are utilized as resistive and charge-storage materials.

  16. A Novel Non-Destructive Silicon-on-Insulator Nonvolatile Memory - LDRD 99-0750 Final Report

    SciTech Connect

    DRAPER,BRUCE L.; FLEETWOOD,D. M.; MEISENHEIMER,TIMOTHY L.; MURRAY,JAMES R.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; SMITH,PAUL M.; VANHEUSDEN,KAREL J.; WARREN,WILLIAM L.

    1999-11-01

    Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.

  17. The role of non-volatile memory from an application perspective

    SciTech Connect

    Kettering, Brett M; Nunez, James A

    2010-09-16

    Current, emerging, and future NVM (non-volatile memory) technologies give us hope that we will be able to architect HPC (high performance computing) systems that initially use them in a memory and storage hierarchy, and eventually use them as the memory and storage for the system, complete with ownership and protections as a HDD-based (hard-disk-drive-based) file system provides today.

  18. Nonvolatile Memory Effect in Organic Thin-Film Transistor Based on Aluminum Nanoparticle Floating Gate

    NASA Astrophysics Data System (ADS)

    Wang, Wei; Ma, Dong-Ge

    2010-01-01

    A nonvolatile memory effect was observed in an organic thin-film transistor by introducing a Boating gate structure. The Boating gate was composed of an Al film in a thickness of nanometers, which was thermally deposited on a SiO2 insulator and exposed to air to spontaneously oxidize. It can be seen that the transistors exhibit significant hysteresis behaviors and storage circles in current-voltage characteristics in the dark and under illumination, indicating that the transistors may act as a nonvolatile memory element. The operational mechanism is discussed in the cases of dark and illumination via charge trapping by the Al floating gate.

  19. A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

    NASA Astrophysics Data System (ADS)

    Jovanović, B.; Brum, R. M.; Torres, L.

    2014-04-01

    After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

  20. A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

    SciTech Connect

    Jovanović, B. E-mail: lionel.torres@lirmm.fr; Brum, R. M.; Torres, L.

    2014-04-07

    After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

  1. Low-Dimensional Polyoxometalate Molecules/Tantalum Oxide Hybrids for Non-Volatile Capacitive Memories.

    PubMed

    Balliou, Angelika; Papadimitropoulos, Giorgos; Skoulatakis, George; Kennou, Stella; Davazoglou, Dimitrios; Gardelis, Spiros; Glezos, Nikos

    2016-03-23

    Transition-metal-oxide hybrids composed of high surface-to-volume ratio Ta2O5 matrices and a molecular analogue of transition metal oxides, tungsten polyoxometalates ([PW12O40](3-)), are introduced herein as a charge storage medium in molecular nonvolatile capacitive memory cells. The polyoxometalate molecules are electrostatically self-assembled on a low-dimensional Ta2O5 matrix, functionalized with an aminosilane molecule with primary amines as the anchoring moiety. The charge trapping sites are located onto the metal framework of the electron-accepting molecular entities as well as on the molecule/oxide interfaces which can immobilize negatively charged mobile oxygen vacancies. The memory characteristics of this novel nanocomposite were tested using no blocking oxide for extraction of structure-specific characteristics. The film was formed on top of the 3.1 nm-thick SiO2/n-Si(001) substrates and has been found to serve as both SiO2/Si interface states' reducer (i.e., quality enhancer) and electron storage medium. The device with the polyoxometalates sandwiched between two Ta2O5 films results in enhanced internal scattering of carriers. Thanks to this, it exhibits a significantly larger memory window than the one containing the plain hybrid and comparable retention time, resulting in a memory window of 4.0 V for the write state and a retention time around 10(4) s without blocking medium. Differential distance of molecular trapping centers from the cell's gate and electronic coupling to the space charge region of the underlying Si substrate were identified as critical parameters for enhanced electron trapping for the first time in such devices. Implementing a numerical electrostatic model incorporating structural and electronic characteristics of the molecular nodes derived from scanning probe and spectroscopic characterization, we are able to interpret the hybrid's electrical response and gain some insight into the electrostatics of the trapping medium. PMID

  2. Highly stable, extremely high-temperature, nonvolatile memory based on resistance switching in polycrystalline Pt nanogaps

    NASA Astrophysics Data System (ADS)

    Suga, Hiroshi; Suzuki, Hiroya; Shinomura, Yuma; Kashiwabara, Shota; Tsukagoshi, Kazuhito; Shimizu, Tetsuo; Naitoh, Yasuhisa

    2016-10-01

    Highly stable, nonvolatile, high-temperature memory based on resistance switching was realized using a polycrystalline platinum (Pt) nanogap. The operating temperature of the memory can be drastically increased by the presence of a sharp-edged Pt crystal facet in the nanogap. A short distance between the facet edges maintains the nanogap shape at high temperature, and the sharp shape of the nanogap densifies the electric field to maintain a stable current flow due to field migration. Even at 873 K, which is a significantly higher temperature than feasible for conventional semiconductor memory, the nonvolatility of the proposed memory allows stable ON and OFF currents, with fluctuations of less than or equal to 10%, to be maintained for longer than eight hours. An advantage of this nanogap scheme for high-temperature memory is its secure operation achieved through the assembly and disassembly of a Pt needle in a high electric field.

  3. Highly stable, extremely high-temperature, nonvolatile memory based on resistance switching in polycrystalline Pt nanogaps

    PubMed Central

    Suga, Hiroshi; Suzuki, Hiroya; Shinomura, Yuma; Kashiwabara, Shota; Tsukagoshi, Kazuhito; Shimizu, Tetsuo; Naitoh, Yasuhisa

    2016-01-01

    Highly stable, nonvolatile, high-temperature memory based on resistance switching was realized using a polycrystalline platinum (Pt) nanogap. The operating temperature of the memory can be drastically increased by the presence of a sharp-edged Pt crystal facet in the nanogap. A short distance between the facet edges maintains the nanogap shape at high temperature, and the sharp shape of the nanogap densifies the electric field to maintain a stable current flow due to field migration. Even at 873 K, which is a significantly higher temperature than feasible for conventional semiconductor memory, the nonvolatility of the proposed memory allows stable ON and OFF currents, with fluctuations of less than or equal to 10%, to be maintained for longer than eight hours. An advantage of this nanogap scheme for high-temperature memory is its secure operation achieved through the assembly and disassembly of a Pt needle in a high electric field. PMID:27725705

  4. A New Concept for Non-Volatile Memory: The Electric-Pulse Induced Resistive Change Effect in Colossal Magnetoresistive Thin Films

    NASA Technical Reports Server (NTRS)

    Liu, S. Q.; Wu, N. J.; Ignatiev, A.

    2001-01-01

    A novel electric pulse-induced resistive change (EPIR) effect has been found in thin film colossal magnetoresistive (CMR) materials, and has shown promise for the development of resistive, nonvolatile memory. The EPIR effect is induced by the application of low voltage (< 4 V) and short duration (< 20 ns) electrical pulses across a thin film sample of a CMR material at room temperature and under no applied magnetic field. The pulse can directly either increase or decrease the resistance of the thin film sample depending on pulse polarity. The sample resistance change has been shown to be over two orders of magnitude, and is nonvolatile after pulsing. The sample resistance can also be changed through multiple levels - as many as 50 have been shown. Such a device can provide a way for the development of a new kind of nonvolatile multiple-valued memory with high density, fast write/read speed, low power-consumption, and potential high radiation-hardness.

  5. Memory device using movement of protons

    DOEpatents

    Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.

    2000-01-01

    An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.

  6. Memory device using movement of protons

    DOEpatents

    Warren, W.L.; Vanheusden, K.J.R.; Fleetwood, D.M.; Devine, R.A.B.

    1998-11-03

    An electrically written memory element is disclosed utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element. 19 figs.

  7. Memory device using movement of protons

    DOEpatents

    Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.

    1998-01-01

    An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.

  8. Review of Emerging New Solid-State Non-Volatile Memories

    NASA Astrophysics Data System (ADS)

    Fujisaki, Yoshihisa

    2013-04-01

    The integration limit of flash memories is approaching, and many new types of memory to replace conventional flash memories have been proposed. Unlike flash memories, new nonvolatile memories do not require storage of electric charges. The possibility of phase-change random-access memories (PCRAMs) or resistive-change RAMs (ReRAMs) replacing ultrahigh-density NAND flash memories has been investigated; however, many issues remain to be overcome, making the replacement difficult. Nonetheless, ferroelectric RAMs (FeRAMs) and magnetoresistive RAMs (MRAMs) are gradually penetrating into fields where the shortcomings of flash memories, such as high operating voltage, slow rewriting speed, and limited number of rewrites, make their use inconvenient. For instance, FeRAMs are widely used in ICs that require low power consumption such as smart cards and wireless tags. MRAMs are used in many kinds of controllers in industrial equipment that require high speed and unlimited rewrite operations. For successful application of new non-volatile semiconductor memories, such memories must be practically utilized in new fields in which flash memories are not applicable, and their technologies must be further developed.

  9. Low-field Switching Four-state Nonvolatile Memory Based on Multiferroic Tunnel Junctions

    PubMed Central

    Yau, H. M.; Yan, Z. B.; Chan, N. Y.; Au, K.; Wong, C. M.; Leung, C. W.; Zhang, F.Y.; Gao, X. S.; Dai, J. Y.

    2015-01-01

    Multiferroic tunneling junction based four-state non-volatile memories are very promising for future memory industry since this kind of memories hold the advantages of not only the higher density by scaling down memory cell but also the function of magnetically written and electrically reading. In this work, we demonstrate a success of this four-state memory in a material system of NiFe/BaTiO3/La0.7Sr0.3MnO3 with improved memory characteristics such as lower switching field and larger tunneling magnetoresistance (TMR). Ferroelectric switching induced resistive change memory with OFF/ON ratio of 16 and 0.3% TMR effect have been achieved in this multiferroic tunneling structure. PMID:26239505

  10. Remarkable charge-trapping performance based in Zr0.5Hf0.5O2 with nanocrystal Ba0.6Sr0.4TiO3 blocking layer for nonvolatile memory device

    NASA Astrophysics Data System (ADS)

    Yan, X. B.; Jia, X. L.; Yang, T.; Zhao, J. H.; Li, Y. C.; Zhou, Z. Y.; Zhang, Y. Y.

    2016-10-01

    Two kinds of charge trapping memory device with Au/Zr0.5Hf0.5O2(ZHO)/SiO2/p-Si and Au/Ba0.6Sr0.4TiO3(BST)/Zr0.5Hf0.5O2/SiO2/p-Si structure were fabricated and investigated. The double BST/ZHO films exhibit a larger memory window of 7.36 V under ±14 V sweeping voltages in its C-V curve and the device has good charge retention properties with only small charge loss of ∼ 5% after more than 104 s. The good characteristics are attributed to the inter-diffusion between BST and ZHO where more deep defect sites were created after RTA treatment, which provides high potential barriers for the trapped charges to tunnel back to the silicon substrate. Furthermore, the nanocrystal in the BST layer increases the tunneling barrier of tunneling current into the gate and effectively restrains the leakage of storage charge from blocking layer, which improves the charge retention characteristic.

  11. Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

    SciTech Connect

    Han, Jinhua; Wang, Wei Ying, Jun; Xie, Wenfa

    2014-01-06

    An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

  12. Non-volatile, high density, high speed, Micromagnet-Hall effect Random Access Memory (MHRAM)

    NASA Technical Reports Server (NTRS)

    Wu, Jiin C.; Katti, Romney R.; Stadler, Henry L.

    1991-01-01

    The micromagnetic Hall effect random access memory (MHRAM) has the potential of replacing ROMs, EPROMs, EEPROMs, and SRAMs because of its ability to achieve non-volatility, radiation hardness, high density, and fast access times, simultaneously. Information is stored magnetically in small magnetic elements (micromagnets), allowing unlimited data retention time, unlimited numbers of rewrite cycles, and inherent radiation hardness and SEU immunity, making the MHRAM suitable for ground based as well as spaceflight applications. The MHRAM device design is not affected by areal property fluctuations in the micromagnet, so high operating margins and high yield can be achieved in large scale integrated circuit (IC) fabrication. The MHRAM has short access times (less than 100 nsec). Write access time is short because on-chip transistors are used to gate current quickly, and magnetization reversal in the micromagnet can occur in a matter of a few nanoseconds. Read access time is short because the high electron mobility sensor (InAs or InSb) produces a large signal voltage in response to the fringing magnetic field from the micromagnet. High storage density is achieved since a unit cell consists only of two transistors and one micromagnet Hall effect element. By comparison, a DRAM unit cell has one transistor and one capacitor, and a SRAM unit cell has six transistors.

  13. Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

    NASA Astrophysics Data System (ADS)

    Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui

    2016-07-01

    Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

  14. A Radiation-Tolerant, Low-Power Non-Volatile Memory Based on Silicon Nanocrystal Quantum Dots

    NASA Technical Reports Server (NTRS)

    Bell, L. D.; Boer, E. A.; Ostraat, M. L.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; deBlauwe, J.; Green, M. L.

    2001-01-01

    Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO2 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled in program/erase threshold voltage swing was seen during 100,000 program and erase cycles. Additional near-term goals for this project include extensive testing for radiation hardness and the development of artificial layered tunnel barrier heterostructures which have the potential for large speed enhancements for read/write of nanocrystal memory elements, compared with conventional flash devices. Additional information is contained in the original extended abstract.

  15. High-G testing of MEMS mechanical non-volatile memory and silicon re-entry switch.

    SciTech Connect

    Baker, Michael Sean; Pohl, Kenneth Roy

    2005-10-01

    Two different Sandia MEMS devices have been tested in a high-g environment to determine their performance and survivability. The first test was performed using a drop-table to produce a peak acceleration load of 1792 g's over a period of 1.5 ms. For the second test the MEMS devices were assembled in a gun-fired penetrator and shot into a cement target at the Army Waterways Experiment Station in Vicksburg Mississippi. This test resulted in a peak acceleration of 7191 g's for a duration of 5.5 ms. The MEMS devices were instrumented using the MEMS Diagnostic Extraction System (MDES), which is capable of driving the devices and recording the device output data during the high-g event, providing in-flight data to assess the device performance. A total of six devices were monitored during the experiments, four mechanical non-volatile memory devices (MNVM) and two Silicon Reentry Switches (SiRES). All six devices functioned properly before, during, and after each high-g test without a single failure. This is the first known test under flight conditions of an active, powered MEMS device at Sandia.

  16. Synchronous semiconductor memory device

    SciTech Connect

    Onno, C.; Hirata, M.

    1989-11-21

    This patent describes a synchronous semiconductor memory device. It comprises: first latch means for latching a write command in synchronism with clock signal; second latch means for latching a write data in synchronism with the clock signal and for outputting two write process signals based on the write data latched thereby; pulse generating means for generating an internal write pulse signal based on the write command latched by the first latch means. The internal write pulse signal having a semiconductor memory device; write control means supplied with the internal write pulse signal and the write process signals for controlling write and read operations of the synchronous semiconductor memory device; memory means for storing the write data latched by the second latch means; and noise preventing means coupled to the second latch means and the write control means for supplying the write process signals to the write control means only in the write mode responsive to the internal write pulse signal and for setting the write process signals to fixed potentials during a time other than the write mode.

  17. Improving reliability of non-volatile memory technologies through circuit level techniques and error control coding

    NASA Astrophysics Data System (ADS)

    Yang, Chengen; Emre, Yunus; Cao, Yu; Chakrabarti, Chaitali

    2012-12-01

    Non-volatile resistive memories, such as phase-change RAM (PRAM) and spin transfer torque RAM (STT-RAM), have emerged as promising candidates because of their fast read access, high storage density, and very low standby power. Unfortunately, in scaled technologies, high storage density comes at a price of lower reliability. In this article, we first study in detail the causes of errors for PRAM and STT-RAM. We see that while for multi-level cell (MLC) PRAM, the errors are due to resistance drift, in STT-RAM they are due to process variations and variations in the device geometry. We develop error models to capture these effects and propose techniques based on tuning of circuit level parameters to mitigate some of these errors. Unfortunately for reliable memory operation, only circuit-level techniques are not sufficient and so we propose error control coding (ECC) techniques that can be used on top of circuit-level techniques. We show that for STT-RAM, a combination of voltage boosting and write pulse width adjustment at the circuit-level followed by a BCH-based ECC scheme can reduce the block failure rate (BFR) to 10-8. For MLC-PRAM, a combination of threshold resistance tuning and BCH-based product code ECC scheme can achieve the same target BFR of 10-8. The product code scheme is flexible; it allows migration to a stronger code to guarantee the same target BFR when the raw bit error rate increases with increase in the number of programming cycles.

  18. Memory device using movement of protons

    DOEpatents

    Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.; Archer, Leo B.; Brown, George A.; Wallace, Robert M.

    2000-01-01

    An enhancement of an electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure during an anneal in an atmosphere containing hydrogen gas. Device operation is enhanced by concluding this anneal step with a sudden cooling. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronics elements on the same silicon substrate.

  19. Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

    SciTech Connect

    Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin E-mail: chilf@suda.edu.cn Chi, Li-Feng E-mail: chilf@suda.edu.cn Wang, Sui-Dong E-mail: chilf@suda.edu.cn

    2015-03-23

    Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

  20. Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

    SciTech Connect

    Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

    2009-11-30

    We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgO{sub x} and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgO{sub x} gate operates under low voltage write-erase (WR-ER) pulse of {+-}20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of {+-}70 V for WR and ER states. Both devices stably operated under visible illuminations.

  1. Thin dielectric technology and memory devices

    NASA Astrophysics Data System (ADS)

    King, Ya-Chin

    With advances in technology and scaling, silicon Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based VLSI circuits have remained dominant in data processing and memory applications. Perpetuated by the demand for high-performance and low-cost integrated circuits, the lateral dimensions of the MOSFETs are being aggressively scaled. This in turn demands scaling of the gate oxide thickness as well. Thin gate oxides present both challenges to the modeling and design device of the classical MOSFET and opportunities to explore new device designs and applications. This study investigates the effect of inversion layer quantization on the capacitance and current characteristics of thin-gate-oxide MOS transistors. In addition, this study explores the possibility of employing thin tunnel oxide for new quasi-nonvolatile memory devices. The performance limitation of a thin dielectric floating gate memory device as well as its potential for dynamic memory applications are discussed. An alternative device structure (i.e. charge-trap based memory cells) is examined by the single charge tunneling model governed by Coulomb Blockade theory. Two methods of forming charge storage nodes embedded in the gate dielectric are investigated. The resulting devices are then characterized. The first proposed device contains a charge trapping layer of silicon rich oxide (SRO) for dynamic/non-volatile memory application. This device has a similar structure as a MONOS device with SRO instead of silicon nitride for charge trapping on top of a very thin tunneling oxide (<2nm). Since it uses charge trapped in the oxide to create threshold voltage shift, the SRO memory cell is a non-destructive-read device. A new process of depositing SRO and high temperature oxide (HTO) in a single furnace step is developed to better top the control oxide thickness and improve data retention. This device achieved write and erase speeds comparable to that of a DRAM cell and longer data retention time than

  2. Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

    NASA Astrophysics Data System (ADS)

    Suarez, Ernesto; Chan, Pik-Yiu; Lingalugari, Murali; Ayers, John E.; Heller, Evan; Jain, Faquir

    2013-11-01

    This paper describes the use of II-VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II-VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

  3. Effects of thickness and geometric variations in the oxide gate stack on the nonvolatile memory behaviors of charge-trap memory thin-film transistors

    NASA Astrophysics Data System (ADS)

    Bak, Jun Yong; Kim, So-Jung; Byun, Chun-Won; Pi, Jae-Eun; Ryu, Min-Ki; Hwang, Chi Sun; Yoon, Sung-Min

    2015-09-01

    Device designs of charge-trap oxide memory thin-film transistors (CTM-TFTs) were investigated to enhance their nonvolatile memory performances. The first strategy was to optimize the film thicknesses of the tunneling and charge-trap (CT) layers in order to meet requirements of both higher operation speed and longer retention time. While the program speed and memory window were improved for the device with a thinner tunneling layer, a long retention time was obtained only for the device with a tunneling layer thicker than 5 nm. The carrier concentration and charge-trap densities were optimized in the 30-nm-thick CT layer. It was observed that 10-nm-thick tunneling, 30-nm-thick CT, and 50-nm-thick blocking layers were the best configuration for our proposed CTM-TFTs, where a memory on/off margin higher than 107 was obtained, and a memory margin of 6.6 × 103 was retained even after the lapse of 105 s. The second strategy was to examine the effects of the geometrical relations between the CT and active layers for the applications of memory elements embedded in circuitries. The CTM-TFTs fabricated without an overlap between the CT layer and the drain electrode showed an enhanced program speed by the reduced parasitic capacitance. The drain-bias disturbance for the memory off-state was effectively suppressed even when a higher read-out drain voltage was applied. Appropriate device design parameters, such as the film thicknesses of each component layer and the geometrical relations between them, can improve the memory performances and expand the application fields of the proposed CTM-TFTs.

  4. Multifunctional organic phototransistor-based nonvolatile memory achieved by UV/ozone treatment of the Ta₂O₅ gate dielectric.

    PubMed

    Liu, Xiaohui; Zhao, Haoyan; Dong, Guifang; Duan, Lian; Li, Dong; Wang, Liduo; Qiu, Yong

    2014-06-11

    An organic phototransistor (OPT) shows nonvolatile memory effect due to its novel optical writing and electrical erasing processes. In this work, we utilize an organic light-emitting diode (OLED) as the light source to investigate OPT-based memory (OPTM) performance. It is found that the OPTM can be used as either flash memory or write-once read-many-times memory by adjusting the properties of the Ta2O5 gate dielectric layer. UV/ozone treatment is applied to effectively change dielectric properties of the Ta2O5 film. The mechanisms for this are examined by X-ray photoelectron spectroscopy and capacitance-voltage measurement. It turns out that the densities of oxygen vacancies and defects in the first 1.8 nm Ta2O5 films near the Ta2O5/semiconductor interface are reduced. Furthermore, for the first time, we use this multifunctional OPTM, which unites the photosensitive and memory properties in one single device, as an optical feedback system to tune the brightness of the OLED. Our study suggests that these OPTMs have potential applications in tuning the brightness uniformity, improving the display quality and prolonging the lifetime of flat panel displays.

  5. Non-Volatile Flash Memory Characteristics of Tetralayer Nickel-Germanide Nanocrystals Embedded Structure.

    PubMed

    Panda, D; Panda, M

    2016-01-01

    Formation of tetralayer memory structure having nickel-germanide nanocrystals using a Ge/Ni multilayers is proposed. X-ray diffraction study shows the NiGe (002) phase formation after proper annealing. Cross sectional HRTEM clearly shows the sharpness and the size (~4-6 nm) of the stacked nanocrystals embedded in the oxide matrix. A large anti-clockwise hysteresis memory win- dow of 13.4 Volt at ± 15 Volt is observed for the optimized samples. This large memory window indicates for the MLC applications. Frequency independent C-V curve confirms about the charge storage in the nanocrystals. A good charge retention and endurance characteristics are exhibited upto 125 °C for the nonvolatile memory application. PMID:27398590

  6. 5 V driving organic non-volatile memory transistors with poly(vinyl alcohol) gate insulator and poly(3-hexylthiophene) channel layers

    NASA Astrophysics Data System (ADS)

    Nam, Sungho; Seo, Jooyeok; Kim, Hwajeong; Kim, Youngkyoo

    2015-10-01

    Organic non-volatile memory devices were fabricated by employing organic field-effect transistors (OFETs) with poly(vinyl alcohol) (PVA) and poly(3-hexylthiophene) as a gate insulating layer and a channel layer, respectively. The 10-nm-thick nickel layers were inserted for better charge injection between the channel layer and the top source/drain electrodes. The fabricated PVA-OFET memory devices could be operated at low voltages (≤5 V) and showed pronounced hysteresis characteristics in the transfer curves, even though very small hysteresis was measured from the output curves. The degree of hysteresis was considerably dependent on the ratio of channel width (W) to channel length (L). The PVA-OFET memory device with the smaller W/L ratio (25) exhibited better retention characteristics upon 700 cycles of writing-reading-erasing-reading operations, which was assigned to the stability of charged states in devices.

  7. Effect of electrode material on characteristics of non-volatile resistive memory consisting of Ag2S nanoparticles

    NASA Astrophysics Data System (ADS)

    Jang, Jaewon

    2016-07-01

    In this study, Ag2S nanoparticles are synthesized and used as the active material for two-terminal resistance switching memory devices. Sintered Ag2S films are successfully crystallized on plastic substrates with synthesized Ag2S nanoparticles, after a relatively low-temperature sintering process (200 °C). After the sintering process, the crystallite size is increased from 6.8 nm to 80.3 nm. The high ratio of surface atoms to inner atoms of nanoparticles reduces the melting point temperature, deciding the sintering process temperature. In order to investigate the resistance switching characteristics, metal/Ag2S/metal structures are fabricated and tested. The effect of the electrode material on the non-volatile resistive memory characteristics is studied. The bottom electrochemically inert materials, such as Au and Pt, were critical for maintaining stable memory characteristics. By using Au and Pt inert bottom electrodes, we are able to significantly improve the memory endurance and retention to more than 103 cycles and 104 sec, respectively.

  8. Characterization of single-sided gate-to-drain non-overlapped implantation nMOSFETs for multi-functional non-volatile memory applications

    NASA Astrophysics Data System (ADS)

    Jeng, E. S.; Chen, Y. F.; Chang, C. C.; Peng, K. M.; Chou, S. W.; Ho, C. W.; Huang, C. F.; Gong, J.

    2012-02-01

    Novel single-sided non-overlapped implantation (SNOI) nMOSFETs are characterized for their capability of multiple programmable memory functions. These devices can be operated as mask ROMs, EEPROMs or anti-fuses by using a pure logic processing. To function as mask ROMs, they can be mask-coded with the source drain extension (SDE) implantation. They can also be used as EEPROM devices by trapping charges in the side-wall nitride spacers. Furthermore, SNOI devices can be used as antifuses by introducing the punch-through stress at the drain side. The SNOI devices were successfully demonstrated for antifuse operations with an extremely high program/initial readout current ratio exceeding 10 9 and a program speed as high as 1 μs. These novel SNOI devices not only provide non-volatile memory solutions in standard CMOS processing but also give a flexible choice among mask ROM, antifuse and EEPROM functions.

  9. Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2012

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Allen, Gregory R.

    2012-01-01

    The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.

  10. Characteristics of a Nonvolatile SRAM Memory Cell Utilizing a Ferroelectric Transistor

    NASA Technical Reports Server (NTRS)

    Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

    2011-01-01

    The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.

  11. Electrical Bistabilities and Conduction Mechanisms of Nonvolatile Memories Based on a Polymethylsilsesquioxane Insulating Layer Containing CdSe/ZnS Quantum Dots

    NASA Astrophysics Data System (ADS)

    Ma, Zehao; Ooi, Poh Choon; Li, Fushan; Yun, Dong Yeol; Kim, Tae Whan

    2015-10-01

    Nonvolatile memory (NVM) devices based on a metal-insulator-metal structure consisting of CdSe/ZnS quantum dots embedded in polymethylsilsesquioxane dielectric layers were fabricated. The current-voltage ( I- V) curves showed a bistable current behavior and the presence of hysteresis. The current-time ( I- t) curves showed that the fabricated NVM memory devices were stable up to 1 × 104 s with a distinct ON/OFF ratio of 104 and were reprogrammable when the endurance test was performed. The extrapolation of the I- t curve to 105 s with corresponding current ON/OFF ratio 1 × 105 indicated a long performance stability of the NVM devices. Schottky emission, Poole-Frenkel emission, trapped-charge limited-current and Child-Langmuir law were proposed as the dominant conduction mechanisms for the fabricated NVM devices based on the obtained I- V characteristics.

  12. Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

    SciTech Connect

    Wang, Wei Han, Jinhua; Ying, Jun; Xiang, Lanyi; Xie, Wenfa

    2014-09-22

    Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm{sup 2}/V s. The unidirectional shift of turn-on voltage (V{sub on}) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V{sub P}/V{sub E}) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm{sup 2}/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V{sub P}/V{sub E} of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V{sub on} shift. As a result, an enlarged memory window of 28.6 V at the V{sub P}/V{sub E} of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

  13. High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

    SciTech Connect

    Nedic, Stanko; Welland, Mark E-mail: mew10@cam.ac.uk; Tea Chun, Young; Chu, Daping E-mail: mew10@cam.ac.uk; Hong, Woong-Ki

    2014-01-20

    A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ∼16.5 V, a high drain current on/off ratio of ∼10{sup 5}, a gate leakage current below ∼300 pA, and excellent retention characteristics for over 10{sup 4} s.

  14. Iii-V Compound Semiconductor Integrated Charge Storage Structures for Dynamic and Non-Volatile Memory Elements

    NASA Astrophysics Data System (ADS)

    Hetherington, Dale Laird

    This thesis presents an investigation into a novel group of GaAs charge storage devices. These devices, which are an integration of bipolar and junction field effect transistor structures were conceived, designed, fabricated, and tested within this study. The purpose was to analyse new types of charge storage devices, which are suitable for fabrication and lead to the development of dynamic and nonvolatile memories in III-V compound semiconductors. Currently, III-V semiconductor storage devices consist only of capacitors, where data is destroyed during reading and electrical erasure is difficult. In this work, four devices types were demonstrated that exhibit nondestructive reading, and three of the prototypes can be electrically erased. All types use the junction field effect transistor (JFET) for charge sensing, with each having different bipolar or epitaxial layer structure controlling the junction gate. The bottom epitaxial layer in each case served as the JFET channel. Two of the device types have three alternately doped layers, while the remaining two have four alternately doped layers. In all cases, removal of majority carriers from the middle layers constitutes stored charge. The missing carriers deplete the current carrying a region of the JFET channel. Drain current of the JFET becomes an indicator of stored charge. The basic function of each JFET memory element type is independent of interchanging n- and p- type doping within the structure type. Some performance advantage can be realized, however, by sensing with an n-type channel as compared to p- type due to increased carrier mobility. All device types exhibit storage time characteristics of order ten seconds. Devices are constructed in epitaxial layers grown by molecular beam epitaxy (MBE) reactors. The design of the epitaxial layers is an intrinsic part, together with the electrical design, of the storage device concept. These concepts are implemented first with photolithography masks which are used

  15. Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

    NASA Astrophysics Data System (ADS)

    Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

    2016-01-01

    Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

  16. Graphene–ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

    PubMed Central

    Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

    2016-01-01

    Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer. PMID:26813710

  17. Normally-off type nonvolatile static random access memory with perpendicular spin torque transfer-magnetic random access memory cells and smallest number of transistors

    NASA Astrophysics Data System (ADS)

    Tanaka, Chika; Abe, Keiko; Noguchi, Hiroki; Nomura, Kumiko; Ikegami, Kazutaka; Fujita, Shinobu

    2014-01-01

    In this paper, we present a novel nonvolatile-random access memory (RAM) cell design based on a “normally-off memory architecture” using a perpendicular spin torque transfer-magnetic random access memory (STT-MRAM) based on a four-transistors static random access memory (SRAM) in order to reduce the operating power of mobile processors. After the cell design concept and basic operation are proposed, a stable and reliable operation for read/write is confirmed by circuit simulation.

  18. Capacitance-voltage measurement in memory devices using ferroelectric polymer

    NASA Astrophysics Data System (ADS)

    Nguyen, Chien A.; Lee, Pooi See

    2006-01-01

    Application of thin polymer film as storing mean for non-volatile memory devices is investigated. Capacitance-voltage (C-V) measurement of metal-ferroelectric-metal device using ferroelectric copolymer P(VDF-TrFE) as dielectric layer shows stable 'butter-fly' curve. The two peaks in C-V measurement corresponding to the largest capacitance are coincidental at the coercive voltages that give rise to zero polarization in the polarization hysteresis measurement. By comparing data of C-V and P-E measurement, a correlation between two types of hysteresis is established in which it reveals simultaneous electrical processes occurring inside the device. These processes are caused by the response of irreversible and reversible polarization to the applied electric field that can be used to present a memory window. The memory effect of ferroelectric copolymer is further demonstrated for fabricating polymeric non-volatile memory devices using metal-ferroelectric-insulator-semiconductor structure (MFIS). By applying different sweeping voltages at the gate, bidirectional flat-band voltage shift is observed in the ferroelectric capacitor. The asymmetrical shift after negative sweeping is resulted from charge accumulation at the surface of Si substrate caused by the dipole direction in the polymer layer. The effect is reversed for positive voltage sweeping.

  19. Forced ion migration for chalcogenide phase change memory device

    NASA Technical Reports Server (NTRS)

    Campbell, Kristy A. (Inventor)

    2011-01-01

    Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more that two data states.

  20. Forced ion migration for chalcogenide phase change memory device

    NASA Technical Reports Server (NTRS)

    Campbell, Kristy A. (Inventor)

    2012-01-01

    Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

  1. Forced Ion Migration for Chalcogenide Phase Change Memory Device

    NASA Technical Reports Server (NTRS)

    Campbell, Kristy A (Inventor)

    2013-01-01

    Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge2Se3/SnTe, and Ge2Se3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

  2. Memory bistable mechanisms of organic memory devices

    NASA Astrophysics Data System (ADS)

    Lee, Ching-Ting; Yu, Li-Zhen; Chen, Hung-Chun

    2010-07-01

    To investigate the memory bistable mechanisms of organic memory devices, the structure of [top Au anode/9,10-di(2-naphthyl)anthracene (ADN) active layer/bottom Au cathode] was deposited using a thermal deposition system. The Au atoms migrated into the ADN active layer was observed from the secondary ion mass spectrometry. The density of 9.6×1016 cm-3 and energy level of 0.553 eV of the induced trapping centers caused by the migrated Au atoms in the ADN active layer were calculated. The induced trapping centers did not influence the carrier injection barrier height between Au and ADN active layer. Therefore, the memory bistable behaviors of the organic memory devices were attributed to the induced trapping centers. The energy diagram was established to verify the mechanisms.

  3. Controlled fabrication of Si nanocrystal delta-layers in thin SiO{sub 2} layers by plasma immersion ion implantation for nonvolatile memories

    SciTech Connect

    Bonafos, C.; Ben-Assayag, G.; Groenen, J.; Carrada, M.; Spiegel, Y.; Torregrosa, F.; Normand, P.; Dimitrakis, P.; Kapetanakis, E.; Sahu, B. S.; Slaoui, A.

    2013-12-16

    Plasma Immersion Ion Implantation (PIII) is a promising alternative to beam line implantation to produce a single layer of nanocrystals (NCs) in the gate insulator of metal-oxide semiconductor devices. We report herein the fabrication of two-dimensional Si-NCs arrays in thin SiO{sub 2} films using PIII and rapid thermal annealing. The effect of plasma and implantation conditions on the structural properties of the NC layers is examined by transmission electron microscopy. A fine tuning of the NCs characteristics is possible by optimizing the oxide thickness, implantation energy, and dose. Electrical characterization revealed that the PIII-produced-Si NC structures are appealing for nonvolatile memories.

  4. Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II-VI Tunnel Insulators

    NASA Astrophysics Data System (ADS)

    Suarez, E.; Gogna, M.; Al-Amoody, F.; Karmakar, S.; Ayers, J.; Heller, E.; Jain, F.

    2010-07-01

    This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn0.95Mg0.05S/ZnS tunnel insulators. The GeO x -cladded Ge and SiO x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II-VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II-VI stack serves both as a tunnel insulator and a high- κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si3N4 and SiO2 layers grown by plasma- enhanced chemical vapor deposition.

  5. A Compute Capable SSD Architecture for Next-Generation Non-volatile Memories

    SciTech Connect

    De, Arup

    2014-01-01

    Existing storage technologies (e.g., disks and ash) are failing to cope with the processor and main memory speed and are limiting the overall perfor- mance of many large scale I/O or data-intensive applications. Emerging fast byte-addressable non-volatile memory (NVM) technologies, such as phase-change memory (PCM), spin-transfer torque memory (STTM) and memristor are very promising and are approaching DRAM-like performance with lower power con- sumption and higher density as process technology scales. These new memories are narrowing down the performance gap between the storage and the main mem- ory and are putting forward challenging problems on existing SSD architecture, I/O interface (e.g, SATA, PCIe) and software. This dissertation addresses those challenges and presents a novel SSD architecture called XSSD. XSSD o oads com- putation in storage to exploit fast NVMs and reduce the redundant data tra c across the I/O bus. XSSD o ers a exible RPC-based programming framework that developers can use for application development on SSD without dealing with the complication of the underlying architecture and communication management. We have built a prototype of XSSD on the BEE3 FPGA prototyping system. We implement various data-intensive applications and achieve speedup and energy ef- ciency of 1.5-8.9 and 1.7-10.27 respectively. This dissertation also compares XSSD with previous work on intelligent storage and intelligent memory. The existing ecosystem and these new enabling technologies make this system more viable than earlier ones.

  6. Ultrathin flexible memory devices based on organic ferroelectric transistors

    NASA Astrophysics Data System (ADS)

    Sugano, Ryo; Hirai, Yoshinori; Tashiro, Tomoya; Sekine, Tomohito; Fukuda, Kenjiro; Kumaki, Daisuke; Domingues dos Santos, Fabrice; Miyabo, Atsushi; Tokito, Shizuo

    2016-10-01

    Here, we demonstrate ultrathin, flexible nonvolatile memory devices with excellent durability under compressive strain. Ferroelectric-gate field-effect transistors (FeFETs) employing organic semiconductor and polymer ferroelectric layers are fabricated on a 1-µm-thick plastic film substrate. The FeFETs are characterized by measuring their transfer characteristics, programming time, and data retention time. The data retention time is almost unchanged even when a 50% compressive strain is applied to the devices. To clarify the origin of the excellent durability of the devices against compressive strain, an intermediate plane is calculated. From the calculation result, the intermediate plane is placed close to the channel region of the FeFETs. The high flexibility of the ferroelectric polymer and ultrathin device structure contributes to achieving a bending radius of 0.8 µm without the degradation of memory characteristics.

  7. Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

    PubMed

    Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

    2015-03-01

    Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

  8. Characterization of a high-quality and UV-transparent PECVD silicon nitride film for nonvolatile memory applications

    NASA Astrophysics Data System (ADS)

    Wang, Chin K.; Ying, T. L.; Wei, C. S.; Liu, L. M.; Cheng, Huang-Chung; Lin, M. S.

    1994-09-01

    A high quality and UV-transparent plasma enhanced chemical vapor deposition (PECVD) silicon nitride film is well developed to form a passivation layer for non-volatile memory devices. The dependence of the film properties on process parameters has been studied by factorial designed experiments. The deposition rate, uniformity, stress, refractive index, wet etching rate, density, step coverage, and UV-transmittance are the items used to evaluate the film properties. Rutherfold backside scattering (RBS) and hydrogen forward scattering (HFS) are used to measure the film composition and total hydrogen composition, respectively. Compared to the traditional PECVD nitride (PE-SiN) film known to have tensile stress and opacity to ultra-violet light (UV light), the developed PE-SiN film with very low compressive stress (< 1E9 dynes/cm*2) and excellent UV-transmittance (> 70% for 1.6 micrometers - thick film) can be achieved. The developed film has higher density, lower hydrogen content, and high N/Si inside film. Based on RBS/HFS, UV-transmittance and Fourier transform infrared spectrum (FTIR) results, the material and optical properties of the developed PE-SiN film are well investigated. This developed PE-SiN film is successfully applied to EPROM devices, and very good electrical and reliability performances have been demonstrated.

  9. Nonvolatile Ferroelectric Memory Circuit Using Black Phosphorus Nanosheet-Based Field-Effect Transistors with P(VDF-TrFE) Polymer.

    PubMed

    Lee, Young Tack; Kwon, Hyeokjae; Kim, Jin Sung; Kim, Hong-Hee; Lee, Yun Jae; Lim, Jung Ah; Song, Yong-Won; Yi, Yeonjin; Choi, Won-Kook; Hwang, Do Kyung; Im, Seongil

    2015-10-27

    Two-dimensional van der Waals (2D vdWs) materials are a class of new materials that can provide important resources for future electronics and materials sciences due to their unique physical properties. Among 2D vdWs materials, black phosphorus (BP) has exhibited significant potential for use in electronic and optoelectronic applications because of its allotropic properties, high mobility, and direct and narrow band gap. Here, we demonstrate a few-layered BP-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. Experiments showed that our BP-based ferroelectric transistors operate satisfactorily at room temperature in ambient air and exhibit a clear memory window. Unlike conventional ambipolar BP transistors, our ferroelectric transistors showed only p-type characteristics due to the carbon-fluorine (C-F) dipole effect of the P(VDF-TrFE) layer, as well as the highest linear mobility value of 1159 cm(2) V(-1) s(-1) with a 10(3) on/off current ratio. For more advanced memory applications beyond unit memory devices, we implemented two memory inverter circuits, a resistive-load inverter circuit and a complementary inverter circuit, combined with an n-type molybdenum disulfide (MoS2) nanosheet. Our memory inverter circuits displayed a clear memory window of 15 V and memory output voltage efficiency of 95%.

  10. Solution-processed Al-chelated gelatin for highly transparent non-volatile memory applications

    SciTech Connect

    Chang, Yu-Chi; Wang, Yeong-Her

    2015-03-23

    Using the biomaterial of Al-chelated gelatin (ACG) prepared by sol-gel method in the ITO/ACG/ITO structure, a highly transparent resistive random access memory (RRAM) was obtained. The transmittance of the fabricated device is approximately 83% at 550 nm while that of Al/gelatin/ITO is opaque. As to the ITO/gelatin/ITO RRAM, no resistive switching behavior can be seen. The ITO/ACG/ITO RRAM shows high ON/OFF current ratio (>10{sup 5}), low operation voltage, good uniformity, and retention characteristics at room temperature and 85 °C. The mechanism of the ACG-based memory devices is presented. The enhancement of these electrical properties can be attributed to the chelate effect of Al ions with gelatin. Results show that transparent ACG-based memory devices possess the potential for next-generation resistive memories and bio-electronic applications.

  11. A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires.

    PubMed

    Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

    2016-06-09

    The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

  12. A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

    NASA Astrophysics Data System (ADS)

    Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

    2016-06-01

    The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

  13. A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

    PubMed Central

    Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

    2016-01-01

    The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques. PMID:27279431

  14. New memory devices based on the proton transfer process.

    PubMed

    Wierzbowska, Małgorzata

    2016-01-01

    Memory devices operating due to the fast proton transfer (PT) process are proposed by the means of first-principles calculations. Writing  information is performed using the electrostatic potential of scanning tunneling microscopy (STM). Reading information is based on the effect of the local magnetization induced at the zigzag graphene nanoribbon (Z-GNR) edge-saturated with oxygen or the hydroxy group-and can be realized with the use of giant magnetoresistance (GMR), a magnetic tunnel junction or spin-transfer torque devices. The energetic barriers for the hop forward and backward processes can be tuned by the distance and potential of the STM tip; this thus enables us to tailor the non-volatile logic states. The proposed system enables very dense packing of the logic cells and could be used in random access and flash memory devices. PMID:26596910

  15. New memory devices based on the proton transfer process

    NASA Astrophysics Data System (ADS)

    Wierzbowska, Małgorzata

    2016-01-01

    Memory devices operating due to the fast proton transfer (PT) process are proposed by the means of first-principles calculations. Writing information is performed using the electrostatic potential of scanning tunneling microscopy (STM). Reading information is based on the effect of the local magnetization induced at the zigzag graphene nanoribbon (Z-GNR) edge—saturated with oxygen or the hydroxy group—and can be realized with the use of giant magnetoresistance (GMR), a magnetic tunnel junction or spin-transfer torque devices. The energetic barriers for the hop forward and backward processes can be tuned by the distance and potential of the STM tip; this thus enables us to tailor the non-volatile logic states. The proposed system enables very dense packing of the logic cells and could be used in random access and flash memory devices.

  16. Subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory for nonvolatile operation

    NASA Astrophysics Data System (ADS)

    Huh, In; Cheon, Woo Young; Choi, Woo Young

    2016-04-01

    A subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory (SAT RAM) has been proposed and fabricated for low-power nonvolatile memory applications. The proposed SAT RAM cell demonstrates adjustable subthreshold swing (SS) depending on stored information: small SS in the erase state ("1" state) and large SS in the program state ("0" state). Thus, SAT RAM cells can achieve low read voltage (Vread) with a large memory window in addition to the effective suppression of ambipolar behavior. These unique features of the SAT RAM are originated from the locally stored charge, which modulates the tunneling barrier width (Wtun) of the source-to-channel tunneling junction.

  17. Three-terminal resistive switching memory in a transparent vertical-configuration device

    SciTech Connect

    Ungureanu, Mariana; Llopis, Roger; Casanova, Fèlix; Hueso, Luis E.

    2014-01-06

    The resistive switching phenomenon has attracted much attention recently for memory applications. It describes the reversible change in the resistance of a dielectric between two non-volatile states by the application of electrical pulses. Typical resistive switching memories are two-terminal devices formed by an oxide layer placed between two metal electrodes. Here, we report on the fabrication and operation of a three-terminal resistive switching memory that works as a reconfigurable logic component and offers an increased logic density on chip. The three-terminal memory device we present is transparent and could be further incorporated in transparent computing electronic technologies.

  18. Metal-oxide-semiconductor diodes containing C60 fullerenes for non-volatile memory applications

    NASA Astrophysics Data System (ADS)

    Beckmeier, Daniel; Baumgärtner, Hermann

    2013-01-01

    For non-volatile memories, silicon-oxide-nitride-oxide-silicon or floating gate structures are used to store information by charging and discharging electronic states reversibly. In this article, we propose to replace the floating gate by C60 molecules. This would allow more defined programming voltages because of the discrete molecular energy levels and a higher resistance to tunneling oxide defects because of the weak electrical connection between the single molecules. Such C60 MOS diode structures are produced and their electrical properties are analyzed regarding current transport and charging mechanism of the molecules. To create the MOS structures, C60 molecules (5% of a monolayer) are evaporated onto a part of a clean silicon wafer and covered by amorphous silicon in situ in an ultra high vacuum system. Then the wafer is oxidized in wet atmosphere at just 710 °C through the C60 layer. The goal is to produce a clean oxide above and under the molecules without destroying them. Aluminum gate contacts are defined on top of these layers to perform complementary capacitance voltage (CV) and current voltage (IV) measurements. First, the gate voltage is swept to analyze the injection current, then CV measurements are performed after each sweep to analyze the charge state of the C60 layer and the oxide quality. Reference diodes without C60 on the same wafer show an identical Fowler-Nordheim (FN) tunneling behavior for currents injected from silicon or from aluminum, respectively. In the CV curves, no pronounced flatband voltage shift is observable. In diodes with C60, for negative gate voltages, a classical FN tunneling is observed and compared to theory. The electron injection from silicon shows a different tunneling current behavior. It starts at a lower electric field and has a smaller slope then a FN current would have. It is identified as a trap-assisted tunneling (TAT) current caused by oxidation-induced traps under the C60 layer. It is modeled by an

  19. Unipolar resistive switching in metal oxide/organic semiconductor non-volatile memories as a critical phenomenon

    SciTech Connect

    Bory, Benjamin F.; Meskers, Stefan C. J.; Rocha, Paulo R. F.; Gomes, Henrique L.; Leeuw, Dago M. de

    2015-11-28

    Diodes incorporating a bilayer of an organic semiconductor and a wide bandgap metal oxide can show unipolar, non-volatile memory behavior after electroforming. The prolonged bias voltage stress induces defects in the metal oxide with an areal density exceeding 10{sup 17 }m{sup −2}. We explain the electrical bistability by the coexistence of two thermodynamically stable phases at the interface between an organic semiconductor and metal oxide. One phase contains mainly ionized defects and has a low work function, while the other phase has mainly neutral defects and a high work function. In the diodes, domains of the phase with a low work function constitute current filaments. The phase composition and critical temperature are derived from a 2D Ising model as a function of chemical potential. The model predicts filamentary conduction exhibiting a negative differential resistance and nonvolatile memory behavior. The model is expected to be generally applicable to any bilayer system that shows unipolar resistive switching.

  20. Development of a Tritium Cleanup System for a Large Helical Device Using Nonvolatile Getter Materials

    SciTech Connect

    Kawano, Takao; Sakuma, Yoichi; Kabutomori, Toshiki; Shibuya, Mamoru

    2000-01-15

    A tritium cleanup system has been conceptually developed for the large helical device (LHD) at the National Institute for Fusion Science. The system is a processing device employed to remove tritium from exhaust gas. In the exhaust gas discharged from the LHD in normal operation, the major part of tritium constituents should be in a form of hydrogen molecules because the fuel used in plasma experiments with the LHD is hydrogen molecules. From this viewpoint, we have designed a tritium cleanup system, which is characterized by tritium being removed and stored in a form of hydrogen molecules with less impurities, like oxygen and carbon, and its decomposition and the separation processes are introduced to convert various tritiated compounds into a form of hydrogen molecules of high purity. Besides these, there is another aspect in that getter materials are applied in both decomposition of tritiated compounds and storage of hydrogen molecules containing tritium.The system design is composed of three essential component parts: a hydrogen separator, a hydrogen absorbing vessel, and a decomposition process vessel. The hydrogen separator and the decomposition process vessel make a process loop repeat to remove hydrogen into a form of hydrogen molecules with less impurities. It is important that 'less impurities' means having a less bad influence on hydrogen-absorbing materials used in the storage vessel.We think that the hydrogen separator will be manufactured by employing a palladium hydrogen purifier system, which is available in the marketplace, and the hydrogen storage vessel will also be manufactured by using hydrogen-absorbing alloys like titanium. Thus, the serious problem imposed on us is how to realize the decomposition process vessel. To develop the decomposition process vessel, we thought nonvolatile getter materials were promising and carried out performance tests of methane decomposition by the nonvolatile getter materials, where methane was used because it is

  1. High Performance Nonvolatile Transistor Memories Utilizing Functional Polyimide-Based Supramolecular Electrets.

    PubMed

    Tung, Wei-Yao; Li, Meng-Hsien; Wu, Hung-Chin; Liu, Hsin-Yu; Hsieh, Yun-Ting; Chen, Wen-Chang

    2016-05-20

    We report pentacene-based organic field-effect transistor memory devices utilizing supramolecular electrets, consisting of a polyimide, PI(6FOH-ODPA), containing hydroxyl groups for hydrogen bonding with amine functionalized aromatic rings (AM) of 1-aniline (AM1), 2-naphthylamine (AM2), 2-aminoanthracene (AM3), and 1-aminopyrene (AM4). The effect of the phenyl ring size and composition of AM1-AM4 on the hole-trapping capability of the fabricated devices was investigated systematically. Under an operating voltage under ±40 V, the prepared devices using the electrets of 100 % AM1-AM4/PI ratios exhibited a memory window of 0, 8.59, 25.97, and 29.95 V, respectively, suggesting that the hole-trapping capability increased with enhancing phenyl ring size. The memory window was enhanced as the amount of AM in PI increased. Furthermore, the devices showed a long charge-retention time of 10(4)  s with an ON/OFF current ratio of around 10(3) -10(4) and multiple switching stability over 100 cycles. This study demonstrated that the electrical characteristics of the OFET memory devices could be manipulated through the chemical compositions of the supramolecular electrets.

  2. A Synthetic Multicellular Memory Device.

    PubMed

    Urrios, Arturo; Macia, Javier; Manzoni, Romilde; Conde, Núria; Bonforti, Adriano; de Nadal, Eulàlia; Posas, Francesc; Solé, Ricard

    2016-08-19

    Changing environments pose a challenge to living organisms. Cells need to gather and process incoming information, adapting to changes in predictable ways. This requires in particular the presence of memory, which allows different internal states to be stored. Biological memory can be stored by switches that retain information on past and present events. Synthetic biologists have implemented a number of memory devices for biological applications, mostly in single cells. It has been shown that the use of multicellular consortia provides interesting advantages to implement biological circuits. Here we show how to build a synthetic biological memory switch using an eukaryotic consortium. We engineered yeast cells that can communicate and retain memory of changes in the extracellular environment. These cells were able to produce and secrete a pheromone and sense a different pheromone following NOT logic. When the two strains were cocultured, they behaved as a double-negative-feedback motif with memory. In addition, we showed that memory can be effectively changed by the use of external inputs. Further optimization of these modules and addition of other cells could lead to new multicellular circuits that exhibit memory over a broad range of biological inputs. PMID:27439436

  3. Fast, Capacious Disk Memory Device

    NASA Technical Reports Server (NTRS)

    Muller, Ronald M.

    1990-01-01

    Device for recording digital data on, and playing back data from, memory disks has high recording or playback rate and utilizes available recording area more fully. Two disks, each with own reading/writing head, used to record data at same time. Head on disk A operates on one of tracks numbered from outside in; head on disk B operates on track of same number in sequence from inside out. Underlying concept of device applicable to magnetic or optical disks.

  4. Resistance switching of Au-implanted-ZrO2 film for nonvolatile memory application

    NASA Astrophysics Data System (ADS)

    Liu, Qi; Guan, Weihua; Long, Shibing; Liu, Ming; Zhang, Sen; Wang, Qin; Chen, Junning

    2008-12-01

    The resistive switching characteristics and switching mechanisms of the Au-implanted-ZrO2 film are extensively investigated for nonvolatile memory applications. Reversible resistance-switching behavior from a high resistance to low resistance state can be traced by dc voltage and pulse voltage. After more than 200 dc switching cycles, the resistance ratio between the high and low resistance states is more than 180 times under 0.7 V readout bias. In the voltage pulse test, the "write" and "erase" speeds can be as fast as 50 and 100 ns, respectively. No data loss is observed for more than 106 s. The formation and rupture of conducting filamentary paths related to the implanted Au ions are suggested to be responsible for the resistive switching phenomenon. The dependence of resistance on temperature indicates that the variable-range hopping conduction mechanism is dominated in the low-resistance state, while the current characteristics are governed by the trap-controlled space limited conduction mechanism in the high-resistance state.

  5. Investigation of resistive switching in Cu-doped HfO2 thin film for multilevel non-volatile memory applications

    NASA Astrophysics Data System (ADS)

    Wang, Yan; Liu, Qi; Long, Shibing; Wang, Wei; Wang, Qin; Zhang, Manhong; Zhang, Sen; Li, Yingtao; Zuo, Qingyun; Yang, Jianhong; Liu, Ming

    2010-01-01

    In this paper, the resistive switching characteristics in a Cu/HfO2:Cu/Pt sandwiched structure is investigated for multilevel non-volatile memory applications. The device shows excellent resistive switching performance, including good endurance, long retention time, fast operation speed and a large storage window (ROFF/RON>107). Based on the temperature-dependent test results, the formation of Cu conducting filaments is believed to be the reason for the resistance switching from the OFF state to the ON state. By integrating the resistive switching mechanism study and the device fabrication, different resistance values are achieved using different compliance currents in the program process. These resistance values can be easily distinguished in a large temperature range, and can be maintained over 10 years by extrapolating retention data at room temperature. The integrated experiment and mechanism studies set up the foundation for the development of high-performance multilevel RRAM.

  6. Control over variability in nonvolatile hafnium-oxide resistive-switching memory based on modeling of the switching processes

    NASA Astrophysics Data System (ADS)

    Butcher, Brian Jerad

    Resistive random access memory (ReRAM) technology presents an attractive option for embedded non-volatile (NV) memory systems if its variability (cycle-to-cycle and device-to-device) can be controlled. This dissertation has focused on investigations to identify key mechanisms and parameters which dominate ReRAM variability, and the development of subsequent experimental and simulation-based tools to address this variability. The first component of these efforts entailed identification of the modern-day non-volatile memory technological gaps that have driven the operational requirements and challenges for resistive memory as an emerging NV memory. Initial research confirmed the critical requirement of a sub-stoichiometric (HfO2-x) dielectric regarding the enablement of stable switching and suggested a defect-driven mechanism, which is discussed in detail. Preliminary experimental work was focused on the fabrication of a durable current-limiting (1T1R) testing structure; which was utilized to enable ReRAM device characterization, reduce unwanted parasitic capacitances, and overshoot-current. Initial electrical and physical characterization confirmed a filamentary based (defect-driven) mechanism based on ReRAM scalability-trends (in device sizes ranging from 50x50nm2 to 7x7microm2). Physical analysis (AFM, TEM and EELS) verified a `dominant-filament mechanism' in transmission-metal-oxide (specifically HfO2-x) based ReRAM. A novel characterization and analysis protocol for key electrical parameters affecting filament formation for HfO2-x-based ReRAMs was developed, focusing on the roles of current, voltage, and temperature. This protocol included characterization of the high-resistive-state (HRS) dependence on the maximum FORMING current (seen during 1st RESET Imax) and the characterization of low-power endurance. This characterization protocol was employed to investigate and develop an approach for ReRAM filament formation at elevated temperatures (hot FORMING) to

  7. A triple quantum dot based nano-electromechanical memory device

    SciTech Connect

    Pozner, R.; Lifshitz, E.; Peskin, U.

    2015-09-14

    Colloidal quantum dots (CQDs) are free-standing nano-structures with chemically tunable electronic properties. This tunability offers intriguing possibilities for nano-electromechanical devices. In this work, we consider a nano-electromechanical nonvolatile memory (NVM) device incorporating a triple quantum dot (TQD) cluster. The device operation is based on a bias induced motion of a floating quantum dot (FQD) located between two bound quantum dots (BQDs). The mechanical motion is used for switching between two stable states, “ON” and “OFF” states, where ligand-mediated effective interdot forces between the BQDs and the FQD serve to hold the FQD in each stable position under zero bias. Considering realistic microscopic parameters, our quantum-classical theoretical treatment of the TQD reveals the characteristics of the NVM.

  8. Oxygen plasma immersion ion implantation treatment to enhance data retention of tungsten nanocrystal nonvolatile memory

    SciTech Connect

    Wang, Jer-Chyi Chang, Wei-Cheng; Lai, Chao-Sung; Chang, Li-Chun; Ai, Chi-Fong; Tsai, Wen-Fa

    2014-03-15

    Data retention characteristics of tungsten nanocrystal (W-NC) memory devices using an oxygen plasma immersion ion implantation (PIII) treatment are investigated. With an increase of oxygen PIII bias voltage and treatment time, the capacitance–voltage hysteresis memory window is increased but the data retention characteristics become degraded. High-resolution transmission electron microscopy images show that this poor data retention is a result of plasma damage on the tunneling oxide layer, which can be prevented by lowering the bias voltage to 7 kV. In addition, by using the elevated temperature retention measurement technique, the effective charge trapping level of the WO{sub 3} film surrounding the W-NCs can be extracted. This measurement reveals that a higher oxygen PIII bias voltage and treatment time induces more shallow traps within the WO{sub 3} film, degrading the retention behavior of the W-NC memory.

  9. Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

    PubMed

    Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

    2016-09-19

    Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands. PMID:27661912

  10. Design of a Multi-Level/Analog Ferroelectric Memory Device

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

    2006-01-01

    Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

  11. Evaluation of Radiation Effects in Flash Memories

    NASA Technical Reports Server (NTRS)

    Miyahira, T.; Swift, G.

    1998-01-01

    Features of flash memories: Flash memories are non-volatile; that is they do not require power to retain the information in its memory. They can be erased and written to while the device is still in the circuit.

  12. Colossal Electroresistive Properties Of CSD Grown Pr{sub 0.7}Ca{sub 0.3}MnO{sub 3} Films For Nonvolatile Memory Applications

    SciTech Connect

    Bhavsar, K. H.; Joshi, U. S.

    2010-12-01

    Colossal electroresistance effects upon application of electric field in perovskite oxide Pr{sub 0.7}Ca{sub 0.3}MnO{sub 3}(PCMO) thin films, which is a promising candidate for resistance random access memory (RRAM) device have been investigated. Nanocrystalline PCMO films were grown on SiO{sub 2} substrates by chemical solution deposition and crystallized at 700 deg. C under different gas atmospheres. Four terminal current voltage characteristics of Ag/PCMO/Ag planar geometry exhibited a sharp transition from a low resistance state (LRS) to a high resistance state (HRS) with a resistance switching ratio of as high as 1100% at room temperature. Nonvolatility and high retention was confirmed by electric pulse induced resistive switching measurements. The resistance switching ratios were found to depend on the annealing conditions, suggesting an interaction between the nonlattice oxygen and oxygen vacancies and/or the cationic vacancy.

  13. Integration of lead-free ferroelectric on HfO2/Si (100) for high performance non-volatile memory applications

    PubMed Central

    Kundu, Souvik; Maurya, Deepam; Clavel, Michael; Zhou, Yuan; Halder, Nripendra N.; Hudait, Mantu K.; Banerji, Pallab; Priya, Shashank

    2015-01-01

    We introduce a novel lead-free ferroelectric thin film (1-x)BaTiO3-xBa(Cu1/3Nb2/3)O3 (x = 0.025) (BT-BCN) integrated on to HfO2 buffered Si for non-volatile memory (NVM) applications. Piezoelectric force microscopy (PFM), x-ray diffraction, and high resolution transmission electron microscopy were employed to establish the ferroelectricity in BT-BCN thin films. PFM study reveals that the domains reversal occurs with 180° phase change by applying external voltage, demonstrating its effectiveness for NVM device applications. X-ray photoelectron microscopy was used to investigate the band alignments between atomic layer deposited HfO2 and pulsed laser deposited BT-BCN films. Programming and erasing operations were explained on the basis of band-alignments. The structure offers large memory window, low leakage current, and high and low capacitance values that were easily distinguishable even after ~106 s, indicating strong charge storage potential. This study explains a new approach towards the realization of ferroelectric based memory devices integrated on Si platform and also opens up a new possibility to embed the system within current complementary metal-oxide-semiconductor processing technology. PMID:25683062

  14. High mechanical endurance RRAM based on amorphous gadolinium oxide for flexible nonvolatile memory application

    NASA Astrophysics Data System (ADS)

    Zhao, Hongbin; Tu, Hailing; Wei, Feng; Shi, Zhitian; Xiong, Yuhua; Zhang, Yan; Du, Jun

    2015-05-01

    In this paper, we use amorphous Gd2O3 as the switching layer for fabricated RRAM devices with novel high performance, excellent flexibility, and mechanical endurance properties as potential candidate memory for flexible electronics applications. The obtained Cu/Gd2O3/Pt devices on flexible polyethylene terephthalate (PET) substrates show bipolar switching characteristics, low voltage operation (<2 V) and long retention time (>106 s). No performance degradation occurs, and the stored information is not lost after the device has been bent to different angles and up to 104 times in the bending tests. Based on temperature-dependent switching characteristics, the formation of Cu conducting filaments stemming from electrochemical reactions is believed to be the reason for the resistance switching from a high resistance state to a low resistance state. The studies of the integrated experiment and mechanism lay the foundation for the development of high-performance flexible RRAM.

  15. Voltage-impulse-induced non-volatile ferroelastic switching of ferromagnetic resonance for reconfigurable magnetoelectric microwave devices.

    PubMed

    Liu, Ming; Howe, Brandon M; Grazulis, Lawrence; Mahalingam, Krishnamurthy; Nan, Tianxiang; Sun, Nian X; Brown, Gail J

    2013-09-20

    A critical challenge in realizing magnetoelectrics based on reconfigurable microwave devices, which is the ability to switch between distinct ferromagnetic resonances (FMR) in a stable, reversible and energy efficient manner, has been addressed. In particular, a voltage-impulse-induced two-step ferroelastic switching pathway can be used to in situ manipulate the magnetic anisotropy and enable non-volatile FMR tuning in FeCoB/PMN-PT (011) multiferroic heterostructures. PMID:23857709

  16. From silicon to organic nanoparticle memory devices.

    PubMed

    Tsoukalas, D

    2009-10-28

    After introducing the operational principle of nanoparticle memory devices, their current status in silicon technology is briefly presented in this work. The discussion then focuses on hybrid technologies, where silicon and organic materials have been combined together in a nanoparticle memory device, and finally concludes with the recent development of organic nanoparticle memories. The review is focused on the nanoparticle memory concept as an extension of the current flash memory device. Organic nanoparticle memories are at a very early stage of research and have not yet found applications. When this happens, it is expected that they will not directly compete with mature silicon technology but will find their own areas of application.

  17. Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array

    PubMed Central

    Eryilmaz, Sukru B.; Kuzum, Duygu; Jeyasingh, Rakesh; Kim, SangBum; BrightSky, Matthew; Lam, Chung; Wong, H.-S. Philip

    2014-01-01

    Recent advances in neuroscience together with nanoscale electronic device technology have resulted in huge interests in realizing brain-like computing hardwares using emerging nanoscale memory devices as synaptic elements. Although there has been experimental work that demonstrated the operation of nanoscale synaptic element at the single device level, network level studies have been limited to simulations. In this work, we demonstrate, using experiments, array level associative learning using phase change synaptic devices connected in a grid like configuration similar to the organization of the biological brain. Implementing Hebbian learning with phase change memory cells, the synaptic grid was able to store presented patterns and recall missing patterns in an associative brain-like fashion. We found that the system is robust to device variations, and large variations in cell resistance states can be accommodated by increasing the number of training epochs. We illustrated the tradeoff between variation tolerance of the network and the overall energy consumption, and found that energy consumption is decreased significantly for lower variation tolerance. PMID:25100936

  18. Investigating the bistability characteristics of GaN/AlN resonant tunneling diodes for ultrafast nonvolatile memory

    NASA Astrophysics Data System (ADS)

    Nagase, Masanori; Takahashi, Tokio; Shimizu, Mitsuaki

    2015-03-01

    The bistability characteristics of GaN/AlN resonant tunneling diodes (RTDs) grown on a sapphire substrate by metalorganic vapor phase epitaxy (MOVPE) were investigated to better understand their physical origin and explore their use in nonvolatile memories. The bistability current-voltage (I-V) characteristics of GaN/AlN RTDs, which were due to intersubband transitions and electron accumulation in the quantum well, were clearly observed over a wide temperature range between 50 and 300 K. However, the I-V characteristics sometimes degraded at temperatures above 250 K. Complex staircase structures were observed in the voltage region showing a negative differential resistance in the I-V curve, and the forward current increased or decreased rapidly as the forward-bias voltage increased. Repeated measurements of the I-V characteristics over the wide temperature range between 50 and 300 K revealed that the bistability characteristics of GaN/AlN RTDs degraded owing to the leakage of electrons accumulating in the quantum well through a deep level in the AlN barrier associated with crystal defects such as dislocations and impurities. Therefore, reduction in crystal defect and impurity densities in the AlN barrier, and a careful design that considers deep levels are important for realizing realize ultrafast nonvolatile memories based on the bistability characteristics of GaN/AlN RTDs.

  19. Investigation of a High Quality and Ultraviolet-Light Transparent Plasma-Enhanced Chemical Vapor Deposition Silicon Nitride Film for Non-Volatile Memory Application

    NASA Astrophysics Data System (ADS)

    Wang, Chin-Kun; Ying, Tser-Liang; Wei, Chih-Shih; Liu, Lu-Min; Cheng, Huang-Chung; Lin, Mou-Shiung

    1995-09-01

    A high quality and ultraviolet-light transparent (UV-transparent) plasma enhanced chemical vapor deposition (PECVD) silicon nitride ( SiN x) film is developed to form passivation layer for non-volatile memory devices. Comparing to the conventional PECVD SiN x film known to have tensile stress and opacity to ultraviolet-light (UV-light), the proposed SiN x film with very low compressive stress ( <1×109 dyn/cm2) and excellent UV-transmittance (>70% for 1.6 µ m-thick film) can be achieved. The film stress is strongly related to RF input power during deposition process. The UV-transmittance is influenced by pressure and SiH4/NH3 flow ratio. It is also shown that the UV-transmittance is closely correlated to refractive index (RI), film density as well as N/Si ratio inside the film. This SiN x film has been successfully applied to erasable programming read-only memory (EPROM's) devices, and very good UV-erasability and reliability performances are demonstrated.

  20. Charge trapping characteristics of Au nanocrystals embedded in remote plasma atomic layer-deposited Al{sub 2}O{sub 3} film as the tunnel and blocking oxides for nonvolatile memory applications

    SciTech Connect

    Lee, Jaesang; Kim, Hyungchul; Park, Taeyong; Ko, Youngbin; Ryu, Jaehun; Jeon, Heeyoung; Park, Jingyu; Jeon, Hyeongtag

    2012-01-15

    Remote plasma atomic layer deposited (RPALD) Al{sub 2}O{sub 3} films were investigated to apply as tunnel and blocking layers in the metal-oxide-semiconductor capacitor memory utilizing Au nanocrystals (NCs) for nonvolatile memory applications. The interface stability of an Al{sub 2}O{sub 3} film deposited by RPALD was studied to observe the effects of remote plasma on the interface. The interface formed during RPALD process has high oxidation states such as Si{sup +3} and Si{sup +4}, indicating that RPALD process can grow more stable interface which has a small amount of fixed oxide trap charge. The significant memory characteristics were also observed in this memory device through the electrical measurement. The memory device exhibited a relatively large memory window of 5.6 V under a 10/-10 V program/erase voltage and also showed the relatively fast programming/erasing speed and a competitive retention characteristic after 10{sup 4} s. These results indicate that Al{sub 2}O{sub 3} films deposited via RPALD can be applied as the tunnel and blocking oxides for next-generation flash memory devices.

  1. Laser-induced nondestructive patterning of a thin ferroelectric polymer film with controlled crystals using Ge8Sb2Te11 alloy layer for nonvolatile memory.

    PubMed

    Bae, Insung; Kim, Richard Hahnkee; Hwang, Sun Kak; Kang, Seok Ju; Park, Cheolmin

    2014-09-10

    We present a simple but robust nondestructive process for fabricating micropatterns of thin ferroelectric polymer films with controlled crystals. Our method is based on utilization of localized heat arising from thin Ge(8)Sb(2)Te(11) (GST) alloy layer upon exposure of 650 nm laser. The heat was generated on GST layer within a few hundred of nanosecond exposure and subsequently transferred to a thin poly(vinylidene fluoride-co-trifluoroethylene) film deposited on GST layer. By controlling exposure time and power of the scanned laser, ferroelectric patterns of one or two microns in size are fabricated with various shape. In the micropatterned regions, ferroelectric polymer crystals were efficiently controlled in both degree of the crystallinity and the molecular orientations. Nonvolatile memory devices with laser scanned ferroelectric polymer layers exhibited excellent device performance of large remnant polarization, ON/OFF current ratio and data retention. The results are comparable with devices containing ferroelectric films thermally annealed at least for 2 h, making our process extremely efficient for saving time. Furthermore, our approach can be conveniently combined with a number of other functional organic materials for the future electronic applications.

  2. Laser-induced nondestructive patterning of a thin ferroelectric polymer film with controlled crystals using Ge8Sb2Te11 alloy layer for nonvolatile memory.

    PubMed

    Bae, Insung; Kim, Richard Hahnkee; Hwang, Sun Kak; Kang, Seok Ju; Park, Cheolmin

    2014-09-10

    We present a simple but robust nondestructive process for fabricating micropatterns of thin ferroelectric polymer films with controlled crystals. Our method is based on utilization of localized heat arising from thin Ge(8)Sb(2)Te(11) (GST) alloy layer upon exposure of 650 nm laser. The heat was generated on GST layer within a few hundred of nanosecond exposure and subsequently transferred to a thin poly(vinylidene fluoride-co-trifluoroethylene) film deposited on GST layer. By controlling exposure time and power of the scanned laser, ferroelectric patterns of one or two microns in size are fabricated with various shape. In the micropatterned regions, ferroelectric polymer crystals were efficiently controlled in both degree of the crystallinity and the molecular orientations. Nonvolatile memory devices with laser scanned ferroelectric polymer layers exhibited excellent device performance of large remnant polarization, ON/OFF current ratio and data retention. The results are comparable with devices containing ferroelectric films thermally annealed at least for 2 h, making our process extremely efficient for saving time. Furthermore, our approach can be conveniently combined with a number of other functional organic materials for the future electronic applications. PMID:25127181

  3. NVL-C: Static Analysis Techniques for Efficient, Correct Programming of Non-Volatile Main Memory Systems

    SciTech Connect

    Lee, Seyong; Vetter, Jeffrey S

    2016-01-01

    Computer architecture experts expect that non-volatile memory (NVM) hierarchies will play a more significant role in future systems including mobile, enterprise, and HPC architectures. With this expectation in mind, we present NVL-C: a novel programming system that facilitates the efficient and correct programming of NVM main memory systems. The NVL-C programming abstraction extends C with a small set of intuitive language features that target NVM main memory, and can be combined directly with traditional C memory model features for DRAM. We have designed these new features to enable compiler analyses and run-time checks that can improve performance and guard against a number of subtle programming errors, which, when left uncorrected, can corrupt NVM-stored data. Moreover, to enable recovery of data across application or system failures, these NVL-C features include a flexible directive for specifying NVM transactions. So that our implementation might be extended to other compiler front ends and languages, the majority of our compiler analyses are implemented in an extended version of LLVM's intermediate representation (LLVM IR). We evaluate NVL-C on a number of applications to show its flexibility, performance, and correctness.

  4. Polymer ferroelectric field-effect memory device with SnO channel layer exhibits record hole mobility

    NASA Astrophysics Data System (ADS)

    Caraveo-Frescas, J. A.; Khan, M. A.; Alshareef, H. N.

    2014-06-01

    Here we report for the first time a hybrid p-channel polymer ferroelectric field-effect transistor memory device with record mobility. The memory device, fabricated at 200°C on both plastic polyimide and glass substrates, uses ferroelectric polymer P(VDF-TrFE) as the gate dielectric and transparent p-type oxide (SnO) as the active channel layer. A record mobility of 3.3 cm2V-1s-1, large memory window (~16 V), low read voltages (~-1 V), and excellent retention characteristics up to 5000 sec have been achieved. The mobility achieved in our devices is over 10 times higher than previously reported polymer ferroelectric field-effect transistor memory with p-type channel. This demonstration opens the door for the development of non-volatile memory devices based on dual channel for emerging transparent and flexible electronic devices.

  5. Multi-Bit Nano-Electromechanical Nonvolatile Memory Cells (Zigzag T Cells) for the Suppression of Bit-to-Bit Interference.

    PubMed

    Choi, Woo Young; Han, Jae Hwan; Cha, Tae Min

    2016-05-01

    Multi-bit nano-electromechanical (NEM) nonvolatile memory cells such as T cells were proposed for higher memory density. However, they suffered from bit-to-bit interference (BI). In order to suppress BI without sacrificing cell size, this paper proposes zigzag T cell structures. The BI suppression of the proposed zigzag T cell is verified by finite-element modeling (FEM). Based on the FEM results, the design of zigzag T cells is optimized.

  6. Shape memory polymer medical device

    DOEpatents

    Maitland, Duncan; Benett, William J.; Bearinger, Jane P.; Wilson, Thomas S.; Small, IV, Ward; Schumann, Daniel L.; Jensen, Wayne A.; Ortega, Jason M.; Marion, III, John E.; Loge, Jeffrey M.

    2010-06-29

    A system for removing matter from a conduit. The system includes the steps of passing a transport vehicle and a shape memory polymer material through the conduit, transmitting energy to the shape memory polymer material for moving the shape memory polymer material from a first shape to a second and different shape, and withdrawing the transport vehicle and the shape memory polymer material through the conduit carrying the matter.

  7. Resistive Switching of Individual Dislocations in Insulating Perovskites -- A Potential Route Towards Nanoscale Non-Volatile Memories.

    NASA Astrophysics Data System (ADS)

    Szot, Krzystof; Speier, Wolfgang; Bihlmayer, Gustav; Waser, Rainer

    2006-03-01

    dislocations. Switching in our case corresponds then to an electrochemical ``closing'' or ``opening'' of the single dislocation in the uppermost portion of the network. Our results show that the switching behaviour in single-crystalline SrTiO3 is an inherent property of the material and can be easily activated by external stimuli. Due to the availability of dislocation densities up to 10^12 cm-2 in single crystals and thin film, one can even envisage to approach the Tbit regime, as long as the dislocations can be successfully arranged into registered superstructures. In summary, evidence is given that the electrical conductance of individual dislocations in a prototype perovskite, SrTiO3, can be switched between a low and a high conducting state by the application of an electrical field. We demonstrate on the basis of ab initio calculations and measurements with a scanning probe microscope SPM that the modulation of the electrical properties is related to the induced change in oxygen stoichiometry and the self-doping capability with a local insulator- metal transition along the core of the dislocations. A model is presented based on a three-dimensional network of such a filamentary structure to analyze the bi-stable resistive switching in the macroscopic metal-insulator-metal (MIM) structure. Our results show that electrically addressing individual dislocations in single crystals as well as epitaxial thin films provides a dynamic range for switching between low and high conducting states which covers several orders of magnitude in resistance and can be of technological interest for the application in Tbit non-volatile memory devices..

  8. Nb-doped Gd2O3 as charge-trapping layer for nonvolatile memory applications

    NASA Astrophysics Data System (ADS)

    Shi, R. P.; Huang, X. D.; Sin, Johnny K. O.; Lai, P. T.

    2015-10-01

    The charge-trapping properties of Gd2O3 with different Nb doping levels are investigated using an Al/Al2O3/Gd2O3/SiO2/Si structure. Compared with the memory device with pure Gd2O3, the one with lightly Nb-doped Gd2O3 shows better charge-trapping characteristics, including higher programming speed (6.5 V at +12 V programming voltage for 10 ms) and better retention property (92% retained charge at 85 °C after 104 s), due to its higher trapping efficiency that resulted from higher trap density and suppressed formation of a silicate interlayer at the Gd2O3/SiO2 interface induced by the Nb doping. Moreover, the one with heavily Nb-doped Gd2O3 shows improvement in erasing behavior but worse retention and lower programming speed than the one with lightly Nb-doped Gd2O3. Further analysis reveals that the Nb-doping level determines the type of dominant trap in the Nb-doped Gd2O3, thus leading to different charge-loss mechanisms and charge-trapping characteristics.

  9. Projected phase-change memory devices

    NASA Astrophysics Data System (ADS)

    Koelmans, Wabe W.; Sebastian, Abu; Jonnalagadda, Vara Prasad; Krebs, Daniel; Dellmann, Laurent; Eleftheriou, Evangelos

    2015-09-01

    Nanoscale memory devices, whose resistance depends on the history of the electric signals applied, could become critical building blocks in new computing paradigms, such as brain-inspired computing and memcomputing. However, there are key challenges to overcome, such as the high programming power required, noise and resistance drift. Here, to address these, we present the concept of a projected memory device, whose distinguishing feature is that the physical mechanism of resistance storage is decoupled from the information-retrieval process. We designed and fabricated projected memory devices based on the phase-change storage mechanism and convincingly demonstrate the concept through detailed experimentation, supported by extensive modelling and finite-element simulations. The projected memory devices exhibit remarkably low drift and excellent noise performance. We also demonstrate active control and customization of the programming characteristics of the device that reliably realize a multitude of resistance states.

  10. Projected phase-change memory devices.

    PubMed

    Koelmans, Wabe W; Sebastian, Abu; Jonnalagadda, Vara Prasad; Krebs, Daniel; Dellmann, Laurent; Eleftheriou, Evangelos

    2015-01-01

    Nanoscale memory devices, whose resistance depends on the history of the electric signals applied, could become critical building blocks in new computing paradigms, such as brain-inspired computing and memcomputing. However, there are key challenges to overcome, such as the high programming power required, noise and resistance drift. Here, to address these, we present the concept of a projected memory device, whose distinguishing feature is that the physical mechanism of resistance storage is decoupled from the information-retrieval process. We designed and fabricated projected memory devices based on the phase-change storage mechanism and convincingly demonstrate the concept through detailed experimentation, supported by extensive modelling and finite-element simulations. The projected memory devices exhibit remarkably low drift and excellent noise performance. We also demonstrate active control and customization of the programming characteristics of the device that reliably realize a multitude of resistance states. PMID:26333363

  11. Electronic device aspects of neural network memories

    NASA Technical Reports Server (NTRS)

    Lambe, J.; Moopenn, A.; Thakoor, A. P.

    1985-01-01

    The basic issues related to the electronic implementation of the neural network model (NNM) for content addressable memories are examined. A brief introduction to the principles of the NNM is followed by an analysis of the information storage of the neural network in the form of a binary connection matrix and the recall capability of such matrix memories based on a hardware simulation study. In addition, materials and device architecture issues involved in the future realization of such networks in VLSI-compatible ultrahigh-density memories are considered. A possible space application of such devices would be in the area of large-scale information storage without mechanical devices.

  12. Resistive switching memory devices based on electrical conductance tuning in poly(4-vinyl phenol)-oxadiazole composites.

    PubMed

    Sun, Yanmei; Miao, Fengjuan; Li, Rui; Wen, Dianzhong

    2015-11-28

    Nonvolatile memory devices, based on electrical conductance tuning in thin films of poly(4-vinyl phenol) (PVP) and 2-(4-tert-butylphenyl)-5-(4-biphenylyl)-1,3,4-oxadiazole (PBD) composites, are fabricated. The current-voltage characteristics of the fabricated devices show different electrical conductance behaviors, such as the write-once read-many-times (WORM) memory effect, the rewritable flash memory effect and insulator behavior, which depend on the content of PBD in the PVP + PBD composites. The OFF and ON states of the WORM and rewritable flash memory devices are stable under a constant voltage stress or a continuous pulse voltage stress at a read voltage. The memory mechanism is deduced from the modeling of the nature of currents in both states in the devices. PMID:26490192

  13. Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

    NASA Astrophysics Data System (ADS)

    Che, Yongli; Zhang, Yating; Cao, Xiaolong; Song, Xiaoxian; Cao, Mingxuan; Dai, Haitao; Yang, Junbo; Zhang, Guizhong; Yao, Jianquan

    2016-07-01

    Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔVth ˜ 15 V) and a long retention time (>105 s). The magnitude of ΔVth depended on both P/E voltages and the bias voltage (VDS): ΔVth was a cubic function to VP/E and linearly depended on VDS. Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.

  14. Bipolar resistive switching characteristics in tantalum nitride-based resistive random access memory devices

    SciTech Connect

    Kim, Myung Ju; Jeon, Dong Su; Park, Ju Hyun; Kim, Tae Geun

    2015-05-18

    This paper reports the bipolar resistive switching characteristics of TaN{sub x}-based resistive random access memory (ReRAM). The conduction mechanism is explained by formation and rupture of conductive filaments caused by migration of nitrogen ions and vacancies; this mechanism is in good agreement with either Ohmic conduction or the Poole-Frenkel emission model. The devices exhibit that the reset voltage varies from −0.82 V to −0.62 V, whereas the set voltage ranges from 1.01 V to 1.30 V for 120 DC sweep cycles. In terms of reliability, the devices exhibit good retention (>10{sup 5 }s) and pulse-switching endurance (>10{sup 6} cycles) properties. These results indicate that TaN{sub x}-based ReRAM devices have a potential for future nonvolatile memory devices.

  15. Nonvolatile modulation of electronic structure and correlative magnetism of L10-FePt films using significant strain induced by shape memory substrates.

    PubMed

    Feng, Chun; Zhao, Jiancheng; Yang, Feng; Gong, Kui; Hao, Shijie; Cao, Yi; Hu, Chen; Zhang, Jingyan; Wang, Zhongqiang; Chen, Lei; Li, Sirui; Sun, Li; Cui, Lishan; Yu, Guanghua

    2016-02-01

    Tuning the lattice strain (εL) is a novel approach to manipulate the magnetic, electronic, and transport properties of spintronic materials. Achievable εL in thin film samples induced by traditional ferroelectric or flexible substrates is usually volatile and well below 1%. Such limits in the tuning capability cannot meet the requirements for nonvolatile applications of spintronic materials. This study answers to the challenge of introducing significant amount of elastic strain in deposited thin films so that noticeable tuning of the spintronic characteristics can be realized. Based on subtle elastic strain engineering of depositing L10-FePt films on pre-stretched NiTi(Nb) shape memory alloy substrates, steerable and nonvolatile lattice strain up to 2.18% has been achieved in the L10-FePt films by thermally controlling the shape memory effect of the substrates. Introduced strains at this level significantly modify the electronic density of state, orbital overlap, and spin-orbit coupling (SOC) strength in the FePt film, leading to nonvolatile modulation of magnetic anisotropy and magnetization reversal characteristics. This finding not only opens an efficient avenue for the nonvolatile tuning of SOC based magnetism and spintronic effects, but also helps to clarify the physical nature of pure strain effect.

  16. Nonvolatile modulation of electronic structure and correlative magnetism of L10-FePt films using significant strain induced by shape memory substrates

    NASA Astrophysics Data System (ADS)

    Feng, Chun; Zhao, Jiancheng; Yang, Feng; Gong, Kui; Hao, Shijie; Cao, Yi; Hu, Chen; Zhang, Jingyan; Wang, Zhongqiang; Chen, Lei; Li, Sirui; Sun, Li; Cui, Lishan; Yu, Guanghua

    2016-02-01

    Tuning the lattice strain (εL) is a novel approach to manipulate the magnetic, electronic, and transport properties of spintronic materials. Achievable εL in thin film samples induced by traditional ferroelectric or flexible substrates is usually volatile and well below 1%. Such limits in the tuning capability cannot meet the requirements for nonvolatile applications of spintronic materials. This study answers to the challenge of introducing significant amount of elastic strain in deposited thin films so that noticeable tuning of the spintronic characteristics can be realized. Based on subtle elastic strain engineering of depositing L10-FePt films on pre-stretched NiTi(Nb) shape memory alloy substrates, steerable and nonvolatile lattice strain up to 2.18% has been achieved in the L10-FePt films by thermally controlling the shape memory effect of the substrates. Introduced strains at this level significantly modify the electronic density of state, orbital overlap, and spin-orbit coupling (SOC) strength in the FePt film, leading to nonvolatile modulation of magnetic anisotropy and magnetization reversal characteristics. This finding not only opens an efficient avenue for the nonvolatile tuning of SOC based magnetism and spintronic effects, but also helps to clarify the physical nature of pure strain effect.

  17. Nonvolatile modulation of electronic structure and correlative magnetism of L10-FePt films using significant strain induced by shape memory substrates.

    PubMed

    Feng, Chun; Zhao, Jiancheng; Yang, Feng; Gong, Kui; Hao, Shijie; Cao, Yi; Hu, Chen; Zhang, Jingyan; Wang, Zhongqiang; Chen, Lei; Li, Sirui; Sun, Li; Cui, Lishan; Yu, Guanghua

    2016-01-01

    Tuning the lattice strain (εL) is a novel approach to manipulate the magnetic, electronic, and transport properties of spintronic materials. Achievable εL in thin film samples induced by traditional ferroelectric or flexible substrates is usually volatile and well below 1%. Such limits in the tuning capability cannot meet the requirements for nonvolatile applications of spintronic materials. This study answers to the challenge of introducing significant amount of elastic strain in deposited thin films so that noticeable tuning of the spintronic characteristics can be realized. Based on subtle elastic strain engineering of depositing L10-FePt films on pre-stretched NiTi(Nb) shape memory alloy substrates, steerable and nonvolatile lattice strain up to 2.18% has been achieved in the L10-FePt films by thermally controlling the shape memory effect of the substrates. Introduced strains at this level significantly modify the electronic density of state, orbital overlap, and spin-orbit coupling (SOC) strength in the FePt film, leading to nonvolatile modulation of magnetic anisotropy and magnetization reversal characteristics. This finding not only opens an efficient avenue for the nonvolatile tuning of SOC based magnetism and spintronic effects, but also helps to clarify the physical nature of pure strain effect. PMID:26830325

  18. Nonvolatile modulation of electronic structure and correlative magnetism of L10-FePt films using significant strain induced by shape memory substrates

    PubMed Central

    Feng, Chun; Zhao, Jiancheng; Yang, Feng; Gong, Kui; Hao, Shijie; Cao, Yi; Hu, Chen; Zhang, Jingyan; Wang, Zhongqiang; Chen, Lei; Li, Sirui; Sun, Li; Cui, Lishan; Yu, Guanghua

    2016-01-01

    Tuning the lattice strain (εL) is a novel approach to manipulate the magnetic, electronic, and transport properties of spintronic materials. Achievable εL in thin film samples induced by traditional ferroelectric or flexible substrates is usually volatile and well below 1%. Such limits in the tuning capability cannot meet the requirements for nonvolatile applications of spintronic materials. This study answers to the challenge of introducing significant amount of elastic strain in deposited thin films so that noticeable tuning of the spintronic characteristics can be realized. Based on subtle elastic strain engineering of depositing L10-FePt films on pre-stretched NiTi(Nb) shape memory alloy substrates, steerable and nonvolatile lattice strain up to 2.18% has been achieved in the L10-FePt films by thermally controlling the shape memory effect of the substrates. Introduced strains at this level significantly modify the electronic density of state, orbital overlap, and spin-orbit coupling (SOC) strength in the FePt film, leading to nonvolatile modulation of magnetic anisotropy and magnetization reversal characteristics. This finding not only opens an efficient avenue for the nonvolatile tuning of SOC based magnetism and spintronic effects, but also helps to clarify the physical nature of pure strain effect. PMID:26830325

  19. System for simultaneously loading program to master computer memory devices and corresponding slave computer memory devices

    NASA Technical Reports Server (NTRS)

    Hall, William A. (Inventor)

    1993-01-01

    A bus programmable slave module card for use in a computer control system is disclosed which comprises a master computer and one or more slave computer modules interfacing by means of a bus. Each slave module includes its own microprocessor, memory, and control program for acting as a single loop controller. The slave card includes a plurality of memory means (S1, S2...) corresponding to a like plurality of memory devices (C1, C2...) in the master computer, for each slave memory means its own communication lines connectable through the bus with memory communication lines of an associated memory device in the master computer, and a one-way electronic door which is switchable to either a closed condition or a one-way open condition. With the door closed, communication lines between master computer memory (C1, C2...) and slave memory (S1, S2...) are blocked. In the one-way open condition invention, the memory communication lines or each slave memory means (S1, S2...) connect with the memory communication lines of its associated memory device (C1, C2...) in the master computer, and the memory devices (C1, C2...) of the master computer and slave card are electrically parallel such that information seen by the master's memory is also seen by the slave's memory. The slave card is also connectable to a switch for electronically removing the slave microprocessor from the system. With the master computer and the slave card in programming mode relationship, and the slave microprocessor electronically removed from the system, loading a program in the memory devices (C1, C2...) of the master accomplishes a parallel loading into the memory devices (S1, S2...) of the slave.

  20. Status and Prospects of ZnO-Based Resistive Switching Memory Devices.

    PubMed

    Simanjuntak, Firman Mangasa; Panda, Debashis; Wei, Kung-Hwa; Tseng, Tseung-Yuen

    2016-12-01

    In the advancement of the semiconductor device technology, ZnO could be a prospective alternative than the other metal oxides for its versatility and huge applications in different aspects. In this review, a thorough overview on ZnO for the application of resistive switching memory (RRAM) devices has been conducted. Various efforts that have been made to investigate and modulate the switching characteristics of ZnO-based switching memory devices are discussed. The use of ZnO layer in different structure, the different types of filament formation, and the different types of switching including complementary switching are reported. By considering the huge interest of transparent devices, this review gives the concrete overview of the present status and prospects of transparent RRAM devices based on ZnO. ZnO-based RRAM can be used for flexible memory devices, which is also covered here. Another challenge in ZnO-based RRAM is that the realization of ultra-thin and low power devices. Nevertheless, ZnO not only offers decent memory properties but also has a unique potential to be used as multifunctional nonvolatile memory devices. The impact of electrode materials, metal doping, stack structures, transparency, and flexibility on resistive switching properties and switching parameters of ZnO-based resistive switching memory devices are briefly compared. This review also covers the different nanostructured-based emerging resistive switching memory devices for low power scalable devices. It may give a valuable insight on developing ZnO-based RRAM and also should encourage researchers to overcome the challenges. PMID:27541816

  1. Status and Prospects of ZnO-Based Resistive Switching Memory Devices

    NASA Astrophysics Data System (ADS)

    Simanjuntak, Firman Mangasa; Panda, Debashis; Wei, Kung-Hwa; Tseng, Tseung-Yuen

    2016-08-01

    In the advancement of the semiconductor device technology, ZnO could be a prospective alternative than the other metal oxides for its versatility and huge applications in different aspects. In this review, a thorough overview on ZnO for the application of resistive switching memory (RRAM) devices has been conducted. Various efforts that have been made to investigate and modulate the switching characteristics of ZnO-based switching memory devices are discussed. The use of ZnO layer in different structure, the different types of filament formation, and the different types of switching including complementary switching are reported. By considering the huge interest of transparent devices, this review gives the concrete overview of the present status and prospects of transparent RRAM devices based on ZnO. ZnO-based RRAM can be used for flexible memory devices, which is also covered here. Another challenge in ZnO-based RRAM is that the realization of ultra-thin and low power devices. Nevertheless, ZnO not only offers decent memory properties but also has a unique potential to be used as multifunctional nonvolatile memory devices. The impact of electrode materials, metal doping, stack structures, transparency, and flexibility on resistive switching properties and switching parameters of ZnO-based resistive switching memory devices are briefly compared. This review also covers the different nanostructured-based emerging resistive switching memory devices for low power scalable devices. It may give a valuable insight on developing ZnO-based RRAM and also should encourage researchers to overcome the challenges.

  2. Membraneless Gas-Separation Microfluidic Paper-Based Analytical Devices for Direct Quantitation of Volatile and Nonvolatile Compounds.

    PubMed

    Phansi, Piyawan; Sumantakul, Saichon; Wongpakdee, Thinnapong; Fukana, Nutnaree; Ratanawimarnwong, Nuanlaor; Sitanurak, Jirayu; Nacapricha, Duangjai

    2016-09-01

    This work presents new chemical sensing devices called "membraneless gas-separation microfluidic paper-based analytical devices" (MBL-GS μPADs). MBL-GS μPADs were designed to make fabrication of the devices simple and user-friendly. MBL-GS μPADs offer direct quantitative analysis of volatile and nonvolatile compounds. Porous hydrophobic membrane is not needed for gas-separation, which makes fabrication of the device simple, rapid and low-cost. A MBL-GS μPAD consists of three layers: "donor layer", "spacer layer", and "acceptor layer". The donor and acceptor layers are made of filter paper with a printed pattern. The donor and acceptor layers are mounted together with a spacer layer in between. This spacer is a two-sided mounting tape, 0.8 mm thick, with a small disc cut out for the gas from the donor zone to diffuse to the acceptor zone. Photographic image of the color that is formed by the reagent in the acceptor layer is analyzed using the ImageJ program for quantitation. Proof of concept of the MBL-GS μPADs was demonstrated by analyzing standard solutions of ethanol, sulfide, and ammonium. Optimization of the MBL-GS μPADs was carried out for direct determination of ammonium in wastewaters and fertilizers to demonstrate the applicability of the system to real samples. PMID:27464645

  3. Membraneless Gas-Separation Microfluidic Paper-Based Analytical Devices for Direct Quantitation of Volatile and Nonvolatile Compounds.

    PubMed

    Phansi, Piyawan; Sumantakul, Saichon; Wongpakdee, Thinnapong; Fukana, Nutnaree; Ratanawimarnwong, Nuanlaor; Sitanurak, Jirayu; Nacapricha, Duangjai

    2016-09-01

    This work presents new chemical sensing devices called "membraneless gas-separation microfluidic paper-based analytical devices" (MBL-GS μPADs). MBL-GS μPADs were designed to make fabrication of the devices simple and user-friendly. MBL-GS μPADs offer direct quantitative analysis of volatile and nonvolatile compounds. Porous hydrophobic membrane is not needed for gas-separation, which makes fabrication of the device simple, rapid and low-cost. A MBL-GS μPAD consists of three layers: "donor layer", "spacer layer", and "acceptor layer". The donor and acceptor layers are made of filter paper with a printed pattern. The donor and acceptor layers are mounted together with a spacer layer in between. This spacer is a two-sided mounting tape, 0.8 mm thick, with a small disc cut out for the gas from the donor zone to diffuse to the acceptor zone. Photographic image of the color that is formed by the reagent in the acceptor layer is analyzed using the ImageJ program for quantitation. Proof of concept of the MBL-GS μPADs was demonstrated by analyzing standard solutions of ethanol, sulfide, and ammonium. Optimization of the MBL-GS μPADs was carried out for direct determination of ammonium in wastewaters and fertilizers to demonstrate the applicability of the system to real samples.

  4. Performance Measurement of a Multi-Level/Analog Ferroelectric Memory Device Design

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

    2007-01-01

    Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determinethe amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

  5. A high performance triboelectric nanogenerator for self-powered non-volatile ferroelectric transistor memory

    NASA Astrophysics Data System (ADS)

    Fang, Huajing; Li, Qiang; He, Wenhui; Li, Jing; Xue, Qingtang; Xu, Chao; Zhang, Lijing; Ren, Tianling; Dong, Guifang; Chan, H. L. W.; Dai, Jiyan; Yan, Qingfeng

    2015-10-01

    We demonstrate an integrated module of self-powered ferroelectric transistor memory based on the combination of a ferroelectric FET and a triboelectric nanogenerator (TENG). The novel TENG was made of a self-assembled polystyrene nanosphere array and a poly(vinylidene fluoride) porous film. Owing to this unique structure, it exhibits an outstanding performance with an output voltage as high as 220 V per cycle. Meanwhile, the arch-shaped TENG is shown to be able to pole a bulk ferroelectric 0.65Pb(Mg1/3Nb2/3)O3-0.35PbTiO3 (PMN-PT) single crystal directly. Based on this effect, a bottom gate ferroelectric FET was fabricated using pentacene as the channel material and a PMN-PT single crystal as the gate insulator. Systematic tests illustrate that the ON/OFF current ratio of this transistor memory element is approximately 103. More importantly, we demonstrate the feasibility to switch the polarization state of this FET gate insulator, namely the stored information, by finger tapping the TENG with a designed circuit. These results may open up a novel application of TENGs in the field of self-powered memory systems.We demonstrate an integrated module of self-powered ferroelectric transistor memory based on the combination of a ferroelectric FET and a triboelectric nanogenerator (TENG). The novel TENG was made of a self-assembled polystyrene nanosphere array and a poly(vinylidene fluoride) porous film. Owing to this unique structure, it exhibits an outstanding performance with an output voltage as high as 220 V per cycle. Meanwhile, the arch-shaped TENG is shown to be able to pole a bulk ferroelectric 0.65Pb(Mg1/3Nb2/3)O3-0.35PbTiO3 (PMN-PT) single crystal directly. Based on this effect, a bottom gate ferroelectric FET was fabricated using pentacene as the channel material and a PMN-PT single crystal as the gate insulator. Systematic tests illustrate that the ON/OFF current ratio of this transistor memory element is approximately 103. More importantly, we demonstrate the

  6. Moving-wire device for carbon isotopic analyses of nanogram quantities of nonvolatile organic carbon.

    PubMed

    Sessions, Alex L; Sylva, Sean P; Hayes, John M

    2005-10-15

    We describe a moving-wire analyzer for measuring 13C in dissolved, involatile organic materials. Liquid samples are first deposited and dried on a continuously spooling nickel wire. The residual sample is then combusted as the wire moves through a furnace, and the evolved CO2 is analyzed by continuous-flow isotope ratio mass spectrometry. A typical analysis requires 1 microL of sample solution and produces a CO2 peak approximately 5 s wide. The system can measure "bulk" delta13C values of approximately 10 nmol of organic carbon with precision better than 0.2 per thousand. For samples containing approximately 1 nmol of C, precision is approximately 1 per thousand. Precision and sensitivity are limited mainly by background noise derived from carbon within the wire. Instrument conditions minimizing that background are discussed in detail. Accuracy is better than 0.5 per thousand for nearly all dissolved analytes tested, including lipids, proteins, nucleic acids, sugars, halocarbons, and hydrocarbons. The sensitivity demonstrated here for 13C measurements represents a approximately 1000-fold improvement relative to existing elemental analyzers and should allow the use of many new preparative techniques for collecting and purifying nonvolatile biochemicals for isotopic analysis.

  7. Novel synaptic memory device for neuromorphic computing.

    PubMed

    Mandal, Saptarshi; El-Amin, Ammaarah; Alexander, Kaitlyn; Rajendran, Bipin; Jha, Rashmi

    2014-06-18

    This report discusses the electrical characteristics of two-terminal synaptic memory devices capable of demonstrating an analog change in conductance in response to the varying amplitude and pulse-width of the applied signal. The devices are based on Mn doped HfO₂ material. The mechanism behind reconfiguration was studied and a unified model is presented to explain the underlying device physics. The model was then utilized to show the application of these devices in speech recognition. A comparison between a 20 nm × 20 nm sized synaptic memory device with that of a state-of-the-art VLSI SRAM synapse showed ~10× reduction in area and >10(6) times reduction in the power consumption per learning cycle.

  8. Novel synaptic memory device for neuromorphic computing

    PubMed Central

    Mandal, Saptarshi; El-Amin, Ammaarah; Alexander, Kaitlyn; Rajendran, Bipin; Jha, Rashmi

    2014-01-01

    This report discusses the electrical characteristics of two-terminal synaptic memory devices capable of demonstrating an analog change in conductance in response to the varying amplitude and pulse-width of the applied signal. The devices are based on Mn doped HfO2 material. The mechanism behind reconfiguration was studied and a unified model is presented to explain the underlying device physics. The model was then utilized to show the application of these devices in speech recognition. A comparison between a 20 nm × 20 nm sized synaptic memory device with that of a state-of-the-art VLSI SRAM synapse showed ~10× reduction in area and >106 times reduction in the power consumption per learning cycle. PMID:24939247

  9. A high performance triboelectric nanogenerator for self-powered non-volatile ferroelectric transistor memory.

    PubMed

    Fang, Huajing; Li, Qiang; He, Wenhui; Li, Jing; Xue, Qingtang; Xu, Chao; Zhang, Lijing; Ren, Tianling; Dong, Guifang; Chan, H L W; Dai, Jiyan; Yan, Qingfeng

    2015-11-01

    We demonstrate an integrated module of self-powered ferroelectric transistor memory based on the combination of a ferroelectric FET and a triboelectric nanogenerator (TENG). The novel TENG was made of a self-assembled polystyrene nanosphere array and a poly(vinylidene fluoride) porous film. Owing to this unique structure, it exhibits an outstanding performance with an output voltage as high as 220 V per cycle. Meanwhile, the arch-shaped TENG is shown to be able to pole a bulk ferroelectric 0.65Pb(Mg1/3Nb2/3)O3-0.35PbTiO3 (PMN-PT) single crystal directly. Based on this effect, a bottom gate ferroelectric FET was fabricated using pentacene as the channel material and a PMN-PT single crystal as the gate insulator. Systematic tests illustrate that the ON/OFF current ratio of this transistor memory element is approximately 10(3). More importantly, we demonstrate the feasibility to switch the polarization state of this FET gate insulator, namely the stored information, by finger tapping the TENG with a designed circuit. These results may open up a novel application of TENGs in the field of self-powered memory systems. PMID:26350823

  10. Combating Memory Corruption Attacks On Scada Devices

    NASA Astrophysics Data System (ADS)

    Bellettini, Carlo; Rrushi, Julian

    Memory corruption attacks on SCADA devices can cause significant disruptions to control systems and the industrial processes they operate. However, despite the presence of numerous memory corruption vulnerabilities, few, if any, techniques have been proposed for addressing the vulnerabilities or for combating memory corruption attacks. This paper describes a technique for defending against memory corruption attacks by enforcing logical boundaries between potentially hostile data and safe data in protected processes. The technique encrypts all input data using random keys; the encrypted data is stored in main memory and is decrypted according to the principle of least privilege just before it is processed by the CPU. The defensive technique affects the precision with which attackers can corrupt control data and pure data, protecting against code injection and arc injection attacks, and alleviating problems posed by the incomparability of mitigation techniques. An experimental evaluation involving the popular Modbus protocol demonstrates the feasibility and efficiency of the defensive technique.

  11. Resistively heated shape memory polymer device

    DOEpatents

    Marion, III, John E.; Bearinger, Jane P.; Wilson, Thomas S.; Maitland, Duncan J.

    2016-10-25

    A resistively heated shape memory polymer device is made by providing a rod, sheet or substrate that includes a resistive medium. The rod, sheet or substrate is coated with a first shape memory polymer providing a coated intermediate unit. The coated intermediate unit is in turn coated with a conductive material providing a second intermediate unit. The second coated intermediate unit is in turn coated with an outer shape memory polymer. The rod, sheet or substrate is exposed and an electrical lead is attached to the rod, sheet or substrate. The conductive material is exposed and an electrical lead is attached to the conductive material.

  12. Flash drive memory apparatus and method

    NASA Technical Reports Server (NTRS)

    Hinchey, Michael G. (Inventor)

    2010-01-01

    A memory apparatus includes a non-volatile computer memory, a USB mass storage controller connected to the non-volatile computer memory, the USB mass storage controller including a daisy chain component, a male USB interface connected to the USB mass storage controller, and at least one other interface for a memory device, other than a USB interface, the at least one other interface being connected to the USB mass storage controller.

  13. Skin-Inspired Haptic Memory Arrays with an Electrically Reconfigurable Architecture.

    PubMed

    Zhu, Bowen; Wang, Hong; Liu, Yaqing; Qi, Dianpeng; Liu, Zhiyuan; Wang, Hua; Yu, Jiancan; Sherburne, Matthew; Wang, Zhaohui; Chen, Xiaodong

    2016-02-24

    Skin-inspired haptic-memory devices, which can retain pressure information after the removel of external pressure by virtue of the nonvolatile nature of the memory devices, are achieved. The rise of haptic-memory devices will allow for mimicry of human sensory memory, opening new avenues for the design of next-generation high-performance sensing devices and systems.

  14. Formation of Ru nanocrystals by plasma enhanced atomic layer deposition for nonvolatile memory applications

    SciTech Connect

    Yim, Sung-Soo; Lee, Moon-Sang; Kim, Ki-Su; Kim, Ki-Bum

    2006-08-28

    The formation of Ru nanocrystals is demonstrated on a SiO{sub 2} substrate by plasma enhanced atomic layer deposition using diethylcyclopentadienyl ruthenium and NH{sub 3} plasma. The island growth of Ru was observed at the initial stages of the film formation up to a nominal thickness of 11.1 nm. A maximum Ru nanocrystal spatial density of 9.7x10{sup 11} /cm{sup 2} was achieved with an average size of 3.5 nm and standard deviation of the size of 20%. Electron charging/discharging effect in the Ru nanocrystals is demonstrated by measuring the flatband voltage shift in the capacitance-voltage measurement of metal-oxide-semiconductor memory capacitor structure.

  15. Unipolar resistive switching behavior of amorphous YCrO{sub 3} films for nonvolatile memory applications

    SciTech Connect

    Sharma, Yogesh E-mail: rkatiyar@uprrp.edu; Misra, Pankaj; Katiyar, Ram S. E-mail: rkatiyar@uprrp.edu

    2014-08-28

    Amorphous YCrO{sub 3} (YCO) films were prepared on Pt/TiO{sub 2}/SiO{sub 2}/Si substrate by pulsed laser deposition in order to investigate resistive switching (RS) phenomenon. The Pt/YCO/Pt device showed stable unipolar RS with resistance ratio of ∼10{sup 5} between low and high resistance states, excellent endurance and retention characteristics, as well as, non-overlapping switching voltages with narrow dispersions. Based on the x-ray photoelectron spectroscopy and temperature dependent switching characteristics, observed RS was mainly ascribed to the oxygen vacancies. Moreover, current-voltage characteristics of the device in low and high resistance states were described by Ohmic and trap controlled space–charge limited conduction mechanisms, respectively.

  16. Optimizing the performance of advanced nonvolatile memories using differentiated cell source and drain implants

    NASA Astrophysics Data System (ADS)

    Duncan, Martin; Pansana, P.

    1995-09-01

    In order to satisfy the twin requirements of increased performance at low cost, a novel architecture that allows the differentiation of the source and drain implants of an EPROM cell without any additional processing steps has been developed. This cell is more immune to electrical stress than a standard cell during both programming and read cycles. In addition, this cell is inherently electrically shorter and therefore can be used to reduce die size in advanced EPROM devices.

  17. Fabrication of poly(methyl methacrylate)-MoS2/graphene heterostructure for memory device application

    NASA Astrophysics Data System (ADS)

    Shinde, Sachin M.; Kalita, Golap; Tanemura, Masaki

    2014-12-01

    Combination of two dimensional graphene and semi-conducting molybdenum disulfide (MoS2) is of great interest for various electronic device applications. Here, we demonstrate fabrication of a hybridized structure with the chemical vapor deposited graphene and MoS2 crystals to configure a memory device. Elongated hexagonal and rhombus shaped MoS2 crystals are synthesized by sulfurization of thermally evaporated molybdenum oxide (MoO3) thin film. Scanning transmission electron microscope studies reveal atomic level structure of the synthesized high quality MoS2 crystals. In the prospect of a memory device fabrication, poly(methyl methacrylate) (PMMA) is used as an insulating dielectric material as well as a supporting layer to transfer the MoS2 crystals. In the fabricated device, PMMA-MoS2 and graphene layers act as the functional and electrode materials, respectively. Distinctive bistable electrical switching and nonvolatile rewritable memory effect is observed in the fabricated PMMA-MoS2/graphene heterostructure. The developed material system and demonstrated memory device fabrication can be significant for next generation data storage applications.

  18. High reliable and stable organic field-effect transistor nonvolatile memory with a poly(4-vinyl phenol) charge trapping layer based on a pn-heterojunction active layer

    NASA Astrophysics Data System (ADS)

    Xiang, Lanyi; Ying, Jun; Han, Jinhua; Zhang, Letian; Wang, Wei

    2016-04-01

    In this letter, we demonstrate a high reliable and stable organic field-effect transistor (OFET) based nonvolatile memory (NVM) with a polymer poly(4-vinyl phenol) (PVP) as the charge trapping layer. In the unipolar OFETs, the inreversible shifts of the turn-on voltage (Von) and severe degradation of the memory window (ΔVon) at programming (P) and erasing (E) voltages, respectively, block their application in NVMs. The obstacle is overcome by using a pn-heterojunction as the active layer in the OFET memory, which supplied a holes and electrons accumulating channel at the supplied P and E voltages, respectively. Both holes and electrons transferring from the channels to PVP layer and overwriting the trapped charges with an opposite polarity result in the reliable bidirectional shifts of Von at P and E voltages, respectively. The heterojunction OFET exhibits excellent nonvolatile memory characteristics, with a large ΔVon of 8.5 V, desired reading (R) voltage at 0 V, reliable P/R/E/R dynamic endurance over 100 cycles and a long retention time over 10 years.

  19. Organic Memory Devices: 2D Mica Crystal as Electret in Organic Field-Effect Transistors for Multistate Memory (Adv. Mater. 19/2016).

    PubMed

    Zhang, Xiaotao; He, Yudong; Li, Rongjin; Dong, Huanli; Hu, Wenping

    2016-05-01

    R. Li, H. Dong, and co-workers describe the exfoliation of cheap and abundant minerals, such as mica, into nanometer-thick 2D crystals with atomically flat surfaces. As described on page 3755, the application of the 2D electret in organic field-effect transistors is well-suited for flexible nonvolatile memory devices. Stored information can be retrieved even after power cycling. Moreover, the devices can be used as full-function transistors with a low-resistance and a high-resistance state.

  20. Structural Phase Transition Effect on Resistive Switching Behavior of MoS2 -Polyvinylpyrrolidone Nanocomposites Films for Flexible Memory Devices.

    PubMed

    Zhang, Peng; Gao, Cunxu; Xu, Benhua; Qi, Lin; Jiang, Changjun; Gao, Meizhen; Xue, Desheng

    2016-04-01

    The 2H phase and 1T phase coexisting in the same molybdenum disulfide (MoS2 ) nanosheets can influence the electronic properties of the materials. The 1T phase of MoS2 is introduced into the 2H-MoS2 nanosheets by two-step hydrothermal synthetic methods. Two types of nonvolatile memory effects, namely write-once read-many times memory and rewritable memory effect, are observed in the flexible memory devices with the configuration of Al/1T@2H-MoS2 -polyvinylpyrrolidone (PVP)/indium tin oxide (ITO)/polyethylene terephthalate (PET) and Al/2H-MoS2 -PVP/ITO/PET, respectively. It is observed that structural phase transition in MoS2 nanosheets plays an important role on the resistive switching behaviors of the MoS2 -based device. It is hoped that our results can offer a general route for the preparation of various promising nanocomposites based on 2D nanosheets of layered transition metal dichalcogenides for fabricating the high performance and flexible nonvolatile memory devices through regulating the phase structure in the 2D nanosheets.

  1. High temperature polyimide containing anthracene moiety and its structure, interface, and nonvolatile memory behavior.

    PubMed

    Park, Samdae; Kim, Kyungtae; Kim, Dong Min; Kwon, Wonsang; Choi, Junman; Ree, Moonhor

    2011-03-01

    A high temperature polyimide bearing anthracene moieties, poly(3,3'-di(9-anthracenemethoxy)-4,4'-biphenylene hexafluoroisopropylidenediphthalimide) (6F-HAB-AM PI) was synthesized. The polymer exhibits excellent thermal stability up to around 410 °C. This polymer is amorphous but orients preferentially in the plane of nanoscale thin films. In device fabrications of its nanoscale thin films with metal top and bottom electrodes, no diffusion of the metal atoms or ions between the polymer and electrodes was found; however, the aluminum bottom electrode had somewhat undergone oxide layer (about 1.2 nm thick) formation at the surface during the post polymer layer formation process, which was confirmed to have no significant influence on the device performance. The polymer thin film exhibited excellent unipolar and bipolar switching behaviors over a very small voltage range, less than ±2 V. Further, the PI films show repeatable writing, reading, and erasing ability with long reliability and high ON/OFF current ratio (up to 10(7)) in air ambient conditions as well as even at temperatures up to 200 °C. PMID:21338065

  2. Resistive switching behavior of La-doped ZnO films for nonvolatile memory applications

    NASA Astrophysics Data System (ADS)

    Tang, M. H.; Zeng, Z. Q.; Li, J. C.; Wang, Z. P.; Xu, X. L.; Wang, G. Y.; Zhang, L. B.; Yang, S. B.; Xiao, Y. G.; Jiang, B.

    2011-09-01

    Rare earth element La-doped ZnO polycrystalline films are prepared on Pt/Ti/SiO 2/Si substrate and p-Si substrate by chemical solution deposition (CSD) method. High ROFF/ RON ratios, low operation voltages within 150 switching cycles of test and long retention measurement are obtained, which indicate that the two different structure devices exhibit reversible, controllable and remarkable reliability unipolar resistive switching (RS) behaviors. The RS mechanism is related to the different substrate of the samples. The filament theory and the interface effect are suggested to be responsible for the RS phenomenon for the Pt/Ti/SiO 2/Si substrate and p-Si substrate, respectively.

  3. Controlled charge trapping by molybdenum disulphide and graphene in ultrathin heterostructured memory devices.

    PubMed

    Choi, Min Sup; Lee, Gwan-Hyoung; Yu, Young-Jun; Lee, Dae-Yeong; Lee, Seung Hwan; Kim, Philip; Hone, James; Yoo, Won Jong

    2013-01-01

    Atomically thin two-dimensional materials have emerged as promising candidates for flexible and transparent electronic applications. Here we show non-volatile memory devices, based on field-effect transistors with large hysteresis, consisting entirely of stacked two-dimensional materials. Graphene and molybdenum disulphide were employed as both channel and charge-trapping layers, whereas hexagonal boron nitride was used as a tunnel barrier. In these ultrathin heterostructured memory devices, the atomically thin molybdenum disulphide or graphene-trapping layer stores charge tunnelled through hexagonal boron nitride, serving as a floating gate to control the charge transport in the graphene or molybdenum disulphide channel. By varying the thicknesses of two-dimensional materials and modifying the stacking order, the hysteresis and conductance polarity of the field-effect transistor can be controlled. These devices show high mobility, high on/off current ratio, large memory window and stable retention, providing a promising route towards flexible and transparent memory devices utilizing atomically thin two-dimensional materials. PMID:23535645

  4. Shape Memory Polymer Therapeutic Devices for Stroke

    SciTech Connect

    Wilson, T S; Small IV, W; Benett, W J; Bearinger, J P; Maitland, D J

    2005-10-11

    Shape memory polymers (SMPs) are attracting a great deal of interest in the scientific community for their use in applications ranging from light weight structures in space to micro-actuators in MEMS devices. These relatively new materials can be formed into a primary shape, reformed into a stable secondary shape, and then controllably actuated to recover their primary shape. The first part of this presentation will be a brief review of the types of polymeric structures which give rise to shape memory behavior in the context of new shape memory polymers with highly regular network structures recently developed at LLNL for biomedical devices. These new urethane SMPs have improved optical and physical properties relative to commercial SMPs, including improved clarity, high actuation force, and sharper actuation transition. In the second part of the presentation we discuss the development of SMP based devices for mechanically removing neurovascular occlusions which result in ischemic stroke. These devices are delivered to the site of the occlusion in compressed form, are pushed through the occlusion, actuated (usually optically) to take on an expanded conformation, and then used to dislodge and grip the thrombus while it is withdrawn through the catheter.

  5. Resistive switching memory based on bioinspired natural solid polymer electrolytes.

    PubMed

    Raeis Hosseini, Niloufar; Lee, Jang-Sik

    2015-01-27

    A solution-processed, chitosan-based resistive-switching memory device is demonstrated with Pt/Ag-doped chitosan/Ag structure. The memory device shows reproducible and reliable bipolar resistive switching characteristics. A memory device based on natural organic material is a promising device toward the next generation of nonvolatile nanoelectronics. The memory device based on chitosan as a natural solid polymer electrolyte can be switched reproducibly between high and low resistance states. In addition, the data retention measurement confirmed the reliability of the chitosan-based nonvolatile memory device. The transparent Ag-embedded chitosan film showed an acceptable and comparable resistive switching behavior on the flexible plastic substrate as well. A cost-effective, environmentally benign memory device using chitosan satisfies the functional requirements of nonvolatile memory operations.

  6. Defect states and charge trapping characteristics of HfO{sub 2} films for high performance nonvolatile memory applications

    SciTech Connect

    Zhang, Y.; Shao, Y. Y.; Lu, X. B. Zeng, M.; Zhang, Z.; Gao, X. S.; Zhang, X. J.; Liu, J.-M.; Dai, J. Y.

    2014-10-27

    In this work, we present significant charge trapping memory effects of the metal-hafnium oxide-SiO{sub 2}-Si (MHOS) structure. The devices based on 800 °C annealed HfO{sub 2} film exhibit a large memory window of ∼5.1 V under ±10 V sweeping voltages and excellent charge retention properties with only small charge loss of ∼2.6% after more than 10{sup 4 }s retention. The outstanding memory characteristics are attributed to the high density of deep defect states in HfO{sub 2} films. We investigated the defect states in the HfO{sub 2} films by photoluminescence and photoluminescence excitation measurements and found that the defect states distributed in deep energy levels ranging from 1.1 eV to 2.9 eV below the conduction band. Our work provides further insights for the charge trapping mechanisms of the HfO{sub 2} based MHOS devices.

  7. High Performance Transparent Transistor Memory Devices Using Nano-Floating Gate of Polymer/ZnO Nanocomposites

    PubMed Central

    Shih, Chien-Chung; Lee, Wen-Ya; Chiu, Yu-Cheng; Hsu, Han-Wen; Chang, Hsuan-Chun; Liu, Cheng-Liang; Chen, Wen-Chang

    2016-01-01

    Nano-floating gate memory devices (NFGM) using metal nanoparticles (NPs) covered with an insulating polymer have been considered as a promising electronic device for the next-generation nonvolatile organic memory applications NPs. However, the transparency of the device with metal NPs is restricted to 60~70% due to the light absorption in the visible region caused by the surface plasmon resonance effects of metal NPs. To address this issue, we demonstrate a novel NFGM using the blends of hole-trapping poly (9-(4-vinylphenyl) carbazole) (PVPK) and electron-trapping ZnO NPs as the charge storage element. The memory devices exhibited a remarkably programmable memory window up to 60 V during the program/erase operations, which was attributed to the trapping/detrapping of charge carriers in ZnO NPs/PVPK composite. Furthermore, the devices showed the long-term retention time (>105 s) and WRER test (>200 cycles), indicating excellent electrical reliability and stability. Additionally, the fabricated transistor memory devices exhibited a relatively high transparency of 90% at the wavelength of 500 nm based on the spray-coated PEDOT:PSS as electrode, suggesting high potential for transparent organic electronic memory devices. PMID:26831222

  8. Reversible strain-induced magnetization switching in FeGa nanomagnets: Pathway to a rewritable, non-volatile, non-toggle, extremely low energy straintronic memory

    NASA Astrophysics Data System (ADS)

    Ahmad, Hasnain; Atulasimha, Jayasimha; Bandyopadhyay, Supriyo

    2015-12-01

    We report reversible strain-induced magnetization switching between two stable/metastable states in ~300 nm sized FeGa nanomagnets delineated on a piezoelectric PMN-PT substrate. Voltage of one polarity applied across the substrate generates compressive strain in a nanomagnet and switches its magnetization to one state, while voltage of the opposite polarity generates tensile strain and switches the magnetization back to the original state. The two states can encode the two binary bits, and, using the right voltage polarity, one can write either bit deterministically. This portends an ultra-energy-efficient non-volatile “non-toggle” memory.

  9. Reversible strain-induced magnetization switching in FeGa nanomagnets: Pathway to a rewritable, non-volatile, non-toggle, extremely low energy straintronic memory

    PubMed Central

    Ahmad, Hasnain; Atulasimha, Jayasimha; Bandyopadhyay, Supriyo

    2015-01-01

    We report reversible strain-induced magnetization switching between two stable/metastable states in ~300 nm sized FeGa nanomagnets delineated on a piezoelectric PMN-PT substrate. Voltage of one polarity applied across the substrate generates compressive strain in a nanomagnet and switches its magnetization to one state, while voltage of the opposite polarity generates tensile strain and switches the magnetization back to the original state. The two states can encode the two binary bits, and, using the right voltage polarity, one can write either bit deterministically. This portends an ultra-energy-efficient non-volatile “non-toggle” memory. PMID:26657829

  10. Reversible strain-induced magnetization switching in FeGa nanomagnets: Pathway to a rewritable, non-volatile, non-toggle, extremely low energy straintronic memory.

    PubMed

    Ahmad, Hasnain; Atulasimha, Jayasimha; Bandyopadhyay, Supriyo

    2015-01-01

    We report reversible strain-induced magnetization switching between two stable/metastable states in ~300 nm sized FeGa nanomagnets delineated on a piezoelectric PMN-PT substrate. Voltage of one polarity applied across the substrate generates compressive strain in a nanomagnet and switches its magnetization to one state, while voltage of the opposite polarity generates tensile strain and switches the magnetization back to the original state. The two states can encode the two binary bits, and, using the right voltage polarity, one can write either bit deterministically. This portends an ultra-energy-efficient non-volatile "non-toggle" memory. PMID:26657829

  11. Nanodot-based organic memory devices

    NASA Astrophysics Data System (ADS)

    Liu, Zhengchun

    2006-04-01

    In this study, resistor-type, diode-type, and transistor-type organic memory devices were investigated, aiming at the low-cost plastic integrated circuit applications. A series of solution-processing techniques including spin-coating, inkjet printing, and self-assembly were employed to fabricate these devices. The organic resistive memory device is based on a novel molecular complex film composed of tetracyanoquinodimethane (TCNQ) and a soluble methanofullerene derivative [6,6]-phenyl C61-butyric acid methyl ester (PCBM). It has an Al/molecules/Al sandwich structure. The molecular layer was formed by spin-coating technique instead of expensive vacuum deposition method. The current-voltage characteristics show that the device switches from the initial 'low' conduction state to 'high' conduction state upon application of external electric field at room temperature and return to 'low' conduction state when a high current pulse is applied. The on/off ratio is over 106. Each state has been found to remain stable for more than five months, even after the external electric field is removed. The PCBM nanodots wrapped by TCNQ molecules can form potential wells for charge trapping, and are believed to be responsible for the memory effects. A rewritable diode memory device was achieved in an improved configuration, i.e., ITO-PEDOT:PSS-PCBM/TCNQ-Al, where a semiconductor polymer PEDOT:PSS is used to form p+-N heterojunction with PCBM/TCNQ. It exhibits a diode characteristic (low conductive) before switching to a high-conductive Poole-Frenkel regime upon applying a positive external bias to ITO. The on/off ratio at +1.0 V is up to 105. Simulation results from Taurus-Medici are in qualitative agreement with the experimental results and the proposed charge storage model. The transistor-type memory device is fabricated on a heavily doped n-type silicon (n+-Si) substrate with a 100 nm thick thermally-grown oxide layer. The n+-Si serves as the gate electrode, while the oxide layer

  12. Novel spintronics devices for memory and logic: prospects and challenges for room temperature all spin computing

    NASA Astrophysics Data System (ADS)

    Wang, Jian-Ping

    An energy efficient memory and logic device for the post-CMOS era has been the goal of a variety of research fields. The limits of scaling, which we expect to reach by the year 2025, demand that future advances in computational power will not be realized from ever-shrinking device sizes, but rather by innovative designs and new materials and physics. Magnetoresistive based devices have been a promising candidate for future integrated magnetic computation because of its unique non-volatility and functionalities. The application of perpendicular magnetic anisotropy for potential STT-RAM application was demonstrated and later has been intensively investigated by both academia and industry groups, but there is no clear path way how scaling will eventually work for both memory and logic applications. One of main reasons is that there is no demonstrated material stack candidate that could lead to a scaling scheme down to sub 10 nm. Another challenge for the usage of magnetoresistive based devices for logic application is its available switching speed and writing energy. Although a good progress has been made to demonstrate the fast switching of a thermally stable magnetic tunnel junction (MTJ) down to 165 ps, it is still several times slower than its CMOS counterpart. In this talk, I will review the recent progress by my research group and my C-SPIN colleagues, then discuss the opportunities, challenges and some potential path ways for magnetoresitive based devices for memory and logic applications and their integration for room temperature all spin computing system.

  13. Solid-state non-volatile electronically programmable reversible variable resistance device

    NASA Technical Reports Server (NTRS)

    Ramesham, Rajeshuni (Inventor); Thakoor, Sarita (Inventor); Daud, Taher (Inventor); Thakoor, Aniklumar P. (Inventor)

    1989-01-01

    A solid-state variable resistance device (10) whose resistance can be repeatedly altered by a control signal over a wide range, and which will remain stable after the signal is removed, is formed on an insulated layer (14), supported on a substrate (12) and comprises a set of electrodes (16a, 16b) connected by a layer (18) of material, which changes from an insulator to a conductor upon the injection of ions, covered by a layer (22) of material with insulating properties which permit the passage of ions, overlaid by an ion donor material (20). The ion donor material is overlaid by an insulating layer (24) upon which is deposited a control gate (26) located above the contacts. In a preferred embodiment, the variable resistance material comprises WO.sub.3, the ion donor layer comprises Cr.sub.2 O.sub.3, and the layers sandwiching the ion donor layer comprise silicon monoxide. When a voltage is applied to the gate, the resistance between the electrode contacts changes, decreasing with positive voltage and increasing with negative voltage.

  14. Garnet Random-Access Memory

    NASA Technical Reports Server (NTRS)

    Katti, Romney R.

    1995-01-01

    Random-access memory (RAM) devices of proposed type exploit magneto-optical properties of magnetic garnets exhibiting perpendicular anisotropy. Magnetic writing and optical readout used. Provides nonvolatile storage and resists damage by ionizing radiation. Because of basic architecture and pinout requirements, most likely useful as small-capacity memory devices.

  15. A complementary switching mechanism for organic memory devices to regulate the conductance of binary states

    NASA Astrophysics Data System (ADS)

    Vyas, Giriraj; Dagar, Parveen; Sahu, Satyajit

    2016-06-01

    We have fabricated an organic non-volatile memory device wherein the ON/OFF current ratio has been controlled by varying the concentration of a small organic molecule, 2,3-Dichloro-5,6-dicyano-p-benzoquinone (DDQ), in an insulating matrix of a polymer Poly(4-vinylphenol) (PVP). A maximum ON-OFF ratio of 106 is obtained when the concentration of DDQ is half or 10 wt. % of PVP. In this process, the switching direction for the devices has also been altered, indicating the disparity in conduction mechanism. Conduction due to metal filament formation through the active material and the voltage dependent conformational change of the organic molecule seem to be the motivation behind the gradual change in the switching direction.

  16. The Stand-Alone Pressure Measurement Device, a digital memory telemeter for assessing Shuttle structural dynamics

    NASA Astrophysics Data System (ADS)

    Havey, Gary; Tanji, Todd; Olson, Richard; Wald, Jerry

    The Stand-Alone Pressure Measurement Device (SAPMD) is a microminiaturized recorder which has in association with the requisite miniature sensor been used to collect absolute Space Shuttle pressure data over various points of the Orbiter's surface during ascent. The SAPMD is entirely self-contained, incorporating its own sensor, power supply, self-starting sensor, nonvolatile memory for sensor data, and a real-time clock for time reference; it is also sufficiently small, at 6.28 x 1.5 x 0.5 in., to be mounted beneath The Shuttle Orbiter's thermal protection system tiles. Data acquired during Shuttle ascent is recovered after the mission without removal of the SAPMD. Strain gages, vibration gages, and differential pressure gages can be incorporated by the device.

  17. Ferroelectric-carbon nanotube memory devices

    NASA Astrophysics Data System (ADS)

    Kumar, Ashok; Shivareddy, Sai G.; Correa, Margarita; Resto, Oscar; Choi, Youngjin; Cole, Matthew T.; Katiyar, Ram S.; Scott, James F.; Amaratunga, Gehan A. J.; Lu, Haidong; Gruverman, Alexei

    2012-04-01

    One-dimensional ferroelectric nanostructures, carbon nanotubes (CNT) and CNT-inorganic oxides have recently been studied due to their potential applications for microelectronics. Here, we report coating of a registered array of aligned multi-wall carbon nanotubes (MWCNT) grown on silicon substrates by functional ferroelectric Pb(Zr,Ti)O3 (PZT) which produces structures suitable for commercial prototype memories. Microstructural analysis reveals the crystalline nature of PZT with small nanocrystals aligned in different directions. First-order Raman modes of MWCNT and PZT/MWCNT/n-Si show the high structural quality of CNT before and after PZT deposition at elevated temperature. PZT exists mostly in the monoclinic Cc/Cm phase, which is the origin of the high piezoelectric response in the system. Low-loss square piezoelectric hysteresis obtained for the 3D bottom-up structure confirms the switchability of the device. Current-voltage mapping of the device by conducting atomic force microscopy (c-AFM) indicates very low transient current. Fabrication and functional properties of these hybrid ferroelectric-carbon nanotubes is the first step towards miniaturization for future nanotechnology sensors, actuators, transducers and memory devices.

  18. Application of nanomaterials in two-terminal resistive-switching memory devices

    PubMed Central

    Ouyang, Jianyong

    2010-01-01

    Nanometer materials have been attracting strong attention due to their interesting structure and properties. Many important practical applications have been demonstrated for nanometer materials based on their unique properties. This article provides a review on the fabrication, electrical characterization, and memory application of two-terminal resistive-switching devices using nanomaterials as the active components, including metal and semiconductor nanoparticles (NPs), nanotubes, nanowires, and graphenes. There are mainly two types of device architectures for the two-terminal devices with NPs. One has a triple-layer structure with a metal film sandwiched between two organic semiconductor layers, and the other has a single polymer film blended with NPs. These devices can be electrically switched between two states with significant different resistances, i.e. the ‘ON’ and ‘OFF’ states. These render the devices important application as two-terminal non-volatile memory devices. The electrical behavior of these devices can be affected by the materials in the active layer and the electrodes. Though the mechanism for the electrical switches has been in argument, it is generally believed that the resistive switches are related to charge storage on the NPs. Resistive switches were also observed on crossbars formed by nanotubes, nanowires, and graphene ribbons. The resistive switches are due to nanoelectromechanical behavior of the materials. The Coulombic interaction of transient charges on the nanomaterials affects the configurable gap of the crossbars, which results into significant change in current through the crossbars. These nanoelectromechanical devices can be used as fast-response and high-density memory devices as well. PMID:22110862

  19. Charge-trapping characteristics of fluorinated thin ZrO{sub 2} film for nonvolatile memory applications

    SciTech Connect

    Huang, X. D. E-mail: laip@eee.hku.hk; Shi, R. P.; Lai, P. T. E-mail: laip@eee.hku.hk

    2014-04-21

    The effects of fluorine treatment on the charge-trapping characteristics of thin ZrO{sub 2} film are investigated by physical and electrical characterization techniques. The formation of silicate interlayer at the ZrO{sub 2}/SiO{sub 2} interface is effectively suppressed by fluorine passivation. However, excessive fluorine diffusion into the Si substrate deteriorates the quality of the SiO{sub 2}/Si interface. Compared with the ZrO{sub 2}-based memory devices with no or excessive fluorine treatment, the one with suitable fluorine-treatment time shows higher operating speed and better retention due to less resistance of built-in electric field (formed by trapped electrons) against electron injection from the substrate and smaller trap-assisted tunneling leakage, resulting from improved ZrO{sub 2}/SiO{sub 2} and SiO{sub 2}/Si interfaces.

  20. Lead-free epitaxial ferroelectric material integration on semiconducting (100) Nb-doped SrTiO3 for low-power non-volatile memory and efficient ultraviolet ray detection

    NASA Astrophysics Data System (ADS)

    Kundu, Souvik; Clavel, Michael; Biswas, Pranab; Chen, Bo; Song, Hyun-Cheol; Kumar, Prashant; Halder, Nripendra N.; Hudait, Mantu K.; Banerji, Pallab; Sanghadasa, Mohan; Priya, Shashank

    2015-07-01

    We report lead-free ferroelectric based resistive switching non-volatile memory (NVM) devices with epitaxial (1-x)BaTiO3-xBiFeO3 (x = 0.725) (BT-BFO) film integrated on semiconducting (100) Nb (0.7%) doped SrTiO3 (Nb:STO) substrates. The piezoelectric force microscopy (PFM) measurement at room temperature demonstrated ferroelectricity in the BT-BFO thin film. PFM results also reveal the repeatable polarization inversion by poling, manifesting its potential for read-write operation in NVM devices. The electroforming-free and ferroelectric polarization coupled electrical behaviour demonstrated excellent resistive switching with high retention time, cyclic endurance, and low set/reset voltages. X-ray photoelectron spectroscopy was utilized to determine the band alignment at the BT-BFO and Nb:STO heterojunction, and it exhibited staggered band alignment. This heterojunction is found to behave as an efficient ultraviolet photo-detector with low rise and fall time. The architecture also demonstrates half-wave rectification under low and high input signal frequencies, where the output distortion is minimal. The results provide avenue for an electrical switch that can regulate the pixels in low or high frequency images. Combined this work paves the pathway towards designing future generation low-power ferroelectric based microelectronic devices by merging both electrical and photovoltaic properties of BT-BFO materials.

  1. Lead-free epitaxial ferroelectric material integration on semiconducting (100) Nb-doped SrTiO3 for low-power non-volatile memory and efficient ultraviolet ray detection.

    PubMed

    Kundu, Souvik; Clavel, Michael; Biswas, Pranab; Chen, Bo; Song, Hyun-Cheol; Kumar, Prashant; Halder, Nripendra N; Hudait, Mantu K; Banerji, Pallab; Sanghadasa, Mohan; Priya, Shashank

    2015-01-01

    We report lead-free ferroelectric based resistive switching non-volatile memory (NVM) devices with epitaxial (1-x)BaTiO3-xBiFeO3 (x = 0.725) (BT-BFO) film integrated on semiconducting (100) Nb (0.7%) doped SrTiO3 (Nb:STO) substrates. The piezoelectric force microscopy (PFM) measurement at room temperature demonstrated ferroelectricity in the BT-BFO thin film. PFM results also reveal the repeatable polarization inversion by poling, manifesting its potential for read-write operation in NVM devices. The electroforming-free and ferroelectric polarization coupled electrical behaviour demonstrated excellent resistive switching with high retention time, cyclic endurance, and low set/reset voltages. X-ray photoelectron spectroscopy was utilized to determine the band alignment at the BT-BFO and Nb:STO heterojunction, and it exhibited staggered band alignment. This heterojunction is found to behave as an efficient ultraviolet photo-detector with low rise and fall time. The architecture also demonstrates half-wave rectification under low and high input signal frequencies, where the output distortion is minimal. The results provide avenue for an electrical switch that can regulate the pixels in low or high frequency images. Combined this work paves the pathway towards designing future generation low-power ferroelectric based microelectronic devices by merging both electrical and photovoltaic properties of BT-BFO materials.

  2. Analysis of a Memory Device Failure

    NASA Technical Reports Server (NTRS)

    Nicolas, David P.; Devaney, John; Gores, Mark; Dicken, Howard

    1998-01-01

    The recent failure of a vintage memory device presented a unique challenge to failure analysts. Normally device layouts, fabrication parameters and other technical information were available to assist the analyst in the analysis. However, this device was out of production for many years and the manufacturer was no longer in business, so the information was not available. To further complicate this analysis, the package leads were all but removed making additional electrical testing difficult. Under these conditions, new and innovative methods were used to analyze the failure. The external visual exam, radiography, PIND, and leak testing were performed with nominal results. Since electrical testing was precluded by the short lead lengths, the device was delidded to expose the internal structures for microscopic examination. No failure mechanism was identified. The available electrical data suggested an ESD or low level EOS type mechanism which left no visible surface damage. Due to parallel electrical paths, electrical probing on the chip failed to locate the failure site. Two non-destructive Scanning Electron Microscopy techniques, CIVA (Charge Induced Voltage Alteration) and EBIC (Electron Beam Induced Current), and a liquid crystal decoration technique which detects localized heating were employed to aid in the analysis. CIVA and EBIC isolated two faults in the input circuitry, and the liquid crystal technique further localized two hot spots in regions on two input gates. Removal of the glassivation and metallization revealed multiple failure sites located in the gate oxide of two input transistors suggesting machine (testing) induced damage.

  3. CF{sub 4} plasma treatment on nanostructure band engineered Gd{sub 2}O{sub 3}-nanocrystal nonvolatile memory

    SciTech Connect

    Wang, Jer-Chyi; Lin, Chih-Ting

    2011-03-15

    The effects of CF{sub 4} plasma treatment on Gd{sub 2}O{sub 3} nanocrystal (NC) memory were investigated. For material analysis, secondary ion mass spectrometry and x-ray photoelectron spectroscopy analyses were performed to characterize the fluorine depth profile of the Gd{sub 2}O{sub 3}-NC film. In addition, an UV-visible spectrophotometer was used to obtain the Gd{sub 2}O{sub 3} bandgap and analyzed to suggest the modified structure of the energy band. Moreover, the electrical properties, including the memory window, program/erase speed, charge retention, and endurance characteristics were significantly improved depending on the CF{sub 4} plasma treatment conditions. This can be explained by the physical model based on the built-in electric field in the Gd{sub 2}O{sub 3} nanostructure. However, it was observed that too much CF{sub 4} plasma caused large surface roughness induced by the plasma damage, leading to characteristics degradation. It was concluded that with suitable CF{sub 4} plasma treatment, this Gd{sub 2}O{sub 3}-NC memory can be applied to future nonvolatile memory applications.

  4. Memory and Spin Injection Devices Involving Half Metals

    DOE PAGESBeta

    Shaughnessy, M.; Snow, Ryan; Damewood, L.; Fong, C. Y.

    2011-01-01

    We suggest memory and spin injection devices fabricated with half-metallic materials and based on the anomalous Hall effect. Schematic diagrams of the memory chips, in thin film and bulk crystal form, are presented. Spin injection devices made in thin film form are also suggested. These devices do not need any external magnetic field but make use of their own magnetization. Only a gate voltage is needed. The carriers are 100% spin polarized. Memory devices may potentially be smaller, faster, and less volatile than existing ones, and the injection devices may be much smaller and more efficient than existing spin injectionmore » devices.« less

  5. Polymer ferroelectric field-effect memory device with SnO channel layer exhibits record hole mobility

    PubMed Central

    Caraveo-Frescas, J. A.; Khan, M. A.; Alshareef, H. N.

    2014-01-01

    Here we report for the first time a hybrid p-channel polymer ferroelectric field-effect transistor memory device with record mobility. The memory device, fabricated at 200°C on both plastic polyimide and glass substrates, uses ferroelectric polymer P(VDF-TrFE) as the gate dielectric and transparent p-type oxide (SnO) as the active channel layer. A record mobility of 3.3 cm2V−1s−1, large memory window (∼16 V), low read voltages (∼−1 V), and excellent retention characteristics up to 5000 sec have been achieved. The mobility achieved in our devices is over 10 times higher than previously reported polymer ferroelectric field-effect transistor memory with p-type channel. This demonstration opens the door for the development of non-volatile memory devices based on dual channel for emerging transparent and flexible electronic devices. PMID:24912617

  6. Sub-band transport mechanism and switching properties for resistive switching nonvolatile memories with structure of silver/aluminum oxide/p-type silicon

    SciTech Connect

    Liu, Yanhong; Li, La; Wang, Song; Gao, Ping; Pan, Lujun; Zhang, Jialiang; Zhou, Peng; Li, Jinhua; Weng, Zhankun

    2015-02-09

    In this paper, we discuss a model of sub-band in resistive switching nonvolatile memories with a structure of silver/aluminum oxide/p-type silicon (Ag/Al{sub x}O{sub y}/p-Si), in which the sub-band is formed by overlapping of wave functions of electron-occupied oxygen vacancies in Al{sub x}O{sub y} layer deposited by atomic layer deposition technology. The switching processes exhibit the characteristics of the bipolarity, discreteness, and no need of forming process, all of which are discussed deeply based on the model of sub-band. The relationships between the SET voltages and distribution of trap levels are analyzed qualitatively. The semiconductor-like behaviors of ON-state resistance affirm the sub-band transport mechanism instead of the metal filament mechanism.

  7. Four-state memory based on a giant and non-volatile converse magnetoelectric effect in FeAl/PIN-PMN-PT structure

    PubMed Central

    Wei, Yanping; Gao, Cunxu; Chen, Zhendong; Xi, Shibo; Shao, Weixia; Zhang, Peng; Chen, Guilin; Li, Jiangong

    2016-01-01

    We report a stable, tunable and non-volatile converse magnetoelectric effect (ME) in a new type of FeAl/PIN-PMN-PT heterostructure at room temperature, with a giant electrical modulation of magnetization for which the maximum relative magnetization change (ΔM/M) is up to 66%. The 109° ferroelastic domain switching in the PIN-PMN-PT and coupling with the ferromagnetic (FM) film via uniaxial anisotropy originating from the PIN-PMN-PT (011) surface are the key roles in converse ME effect. We also propose here a new, four-state memory through which it is possible to modify the remanent magnetism state by adjusting the electric field. This work represents a helpful approach to securing electric-writing magnetic-reading with low energy consumption for future high-density information storage applications. PMID:27417902

  8. Four-state memory based on a giant and non-volatile converse magnetoelectric effect in FeAl/PIN-PMN-PT structure

    NASA Astrophysics Data System (ADS)

    Wei, Yanping; Gao, Cunxu; Chen, Zhendong; Xi, Shibo; Shao, Weixia; Zhang, Peng; Chen, Guilin; Li, Jiangong

    2016-07-01

    We report a stable, tunable and non-volatile converse magnetoelectric effect (ME) in a new type of FeAl/PIN-PMN-PT heterostructure at room temperature, with a giant electrical modulation of magnetization for which the maximum relative magnetization change (ΔM/M) is up to 66%. The 109° ferroelastic domain switching in the PIN-PMN-PT and coupling with the ferromagnetic (FM) film via uniaxial anisotropy originating from the PIN-PMN-PT (011) surface are the key roles in converse ME effect. We also propose here a new, four-state memory through which it is possible to modify the remanent magnetism state by adjusting the electric field. This work represents a helpful approach to securing electric-writing magnetic-reading with low energy consumption for future high-density information storage applications.

  9. Four-state memory based on a giant and non-volatile converse magnetoelectric effect in FeAl/PIN-PMN-PT structure.

    PubMed

    Wei, Yanping; Gao, Cunxu; Chen, Zhendong; Xi, Shibo; Shao, Weixia; Zhang, Peng; Chen, Guilin; Li, Jiangong

    2016-01-01

    We report a stable, tunable and non-volatile converse magnetoelectric effect (ME) in a new type of FeAl/PIN-PMN-PT heterostructure at room temperature, with a giant electrical modulation of magnetization for which the maximum relative magnetization change (ΔM/M) is up to 66%. The 109° ferroelastic domain switching in the PIN-PMN-PT and coupling with the ferromagnetic (FM) film via uniaxial anisotropy originating from the PIN-PMN-PT (011) surface are the key roles in converse ME effect. We also propose here a new, four-state memory through which it is possible to modify the remanent magnetism state by adjusting the electric field. This work represents a helpful approach to securing electric-writing magnetic-reading with low energy consumption for future high-density information storage applications. PMID:27417902

  10. Memory device for two-dimensional radiant energy array computers

    NASA Technical Reports Server (NTRS)

    Schaefer, D. H.; Strong, J. P., III (Inventor)

    1977-01-01

    A memory device for two dimensional radiant energy array computers was developed, in which the memory device stores digital information in an input array of radiant energy digital signals that are characterized by ordered rows and columns. The memory device contains a radiant energy logic storing device having a pair of input surface locations for receiving a pair of separate radiant energy digital signal arrays and an output surface location adapted to transmit a radiant energy digital signal array. A regenerative feedback device that couples one of the input surface locations to the output surface location in a manner for causing regenerative feedback is also included

  11. PIYAS-proceeding to intelligent service oriented memory allocation for flash based data centric sensor devices in wireless sensor networks.

    PubMed

    Rizvi, Sanam Shahla; Chung, Tae-Sun

    2010-01-01

    Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS). This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks.

  12. PIYAS-Proceeding to Intelligent Service Oriented Memory Allocation for Flash Based Data Centric Sensor Devices in Wireless Sensor Networks

    PubMed Central

    Rizvi, Sanam Shahla; Chung, Tae-Sun

    2010-01-01

    Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS). This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks. PMID:22315541

  13. PIYAS-proceeding to intelligent service oriented memory allocation for flash based data centric sensor devices in wireless sensor networks.

    PubMed

    Rizvi, Sanam Shahla; Chung, Tae-Sun

    2010-01-01

    Flash memory has become a more widespread storage medium for modern wireless devices because of its effective characteristics like non-volatility, small size, light weight, fast access speed, shock resistance, high reliability and low power consumption. Sensor nodes are highly resource constrained in terms of limited processing speed, runtime memory, persistent storage, communication bandwidth and finite energy. Therefore, for wireless sensor networks supporting sense, store, merge and send schemes, an efficient and reliable file system is highly required with consideration of sensor node constraints. In this paper, we propose a novel log structured external NAND flash memory based file system, called Proceeding to Intelligent service oriented memorY Allocation for flash based data centric Sensor devices in wireless sensor networks (PIYAS). This is the extended version of our previously proposed PIYA [1]. The main goals of the PIYAS scheme are to achieve instant mounting and reduced SRAM space by keeping memory mapping information to a very low size of and to provide high query response throughput by allocation of memory to the sensor data by network business rules. The scheme intelligently samples and stores the raw data and provides high in-network data availability by keeping the aggregate data for a longer period of time than any other scheme has done before. We propose effective garbage collection and wear-leveling schemes as well. The experimental results show that PIYAS is an optimized memory management scheme allowing high performance for wireless sensor networks. PMID:22315541

  14. Resistive Switching of Individual Dislocations in Insulating Perovskites -- A Potential Route Towards Nanoscale Non-Volatile Memories.

    NASA Astrophysics Data System (ADS)

    Szot, Krzystof; Speier, Wolfgang; Bihlmayer, Gustav; Waser, Rainer

    2006-03-01

    Electrically controlled resistive switching effects have been reported for a broad variety of binary and multinary oxides in recent years. In particular, titanates, zirconates, and manganites have been in the focus of the studies. In many cases, the mechanism of the switching and the geometrical extension of the phenomenon (filaments vs. bulk) are still under discussion. In this work, we present evidence for a redox-based switching mechanism and we indicate a potential route towards highly scalable non-volatile memories based on this switching effect. The challenge our work is to utilize resistive switching mechanism with the aim to construct active electronic elements on a real nanoscale level, here by reversibly switching the electrical properties of individual dislocations by electrical stimuli. We demonstrate that standard undoped SrTiO3 single crystals, utilized as a model system, exhibit a switching behavior along filaments based on dislocations, mediated by oxygen transport. For this, we employed a three-step procedure: the crystals were, at first, annealed at elevated temperatures under reducing conditions, then exposed to 200mbar O2 pressure at room temperature, and finally subjected to an electric field under ultrahigh vacuum (electroformation). This treatment induced in a metal-insulator (SrTiO3)-metal (MIM) system a transition to metallic state. A hysteretic behavior appears after dynamical polarization of the MIM structure at the maximum electroforming currents. The shape of the I/V curve has the typical signature for bi-stable switching known for these types of perovskites. The positive temperature dependence of the resistance of the low- (LRS) and the high-resistance (HRS) state clearly identifies both states to be metallic in character. The inhomogeneity of the electrical transport becomes directly evident from a simple optical inspection and the conductivity maps as measured by LC-AFM of a planar structure. One can trace the formation of the

  15. Guide wire extension for shape memory polymer occlusion removal devices

    DOEpatents

    Maitland, Duncan J.; Small, IV, Ward; Hartman, Jonathan

    2009-11-03

    A flexible extension for a shape memory polymer occlusion removal device. A shape memory polymer instrument is transported through a vessel via a catheter. A flexible elongated unit is operatively connected to the distal end of the shape memory polymer instrument to enhance maneuverability through tortuous paths en route to the occlusion.

  16. Laser Fabrication of Polymer Ferroelectric Nanostructures for Nonvolatile Organic Memory Devices.

    PubMed

    Martínez-Tong, Daniel E; Rodríguez-Rodríguez, Álvaro; Nogales, Aurora; García-Gutiérrez, Mari-Cruz; Pérez-Murano, Francesc; Llobet, Jordi; Ezquerra, Tiberio A; Rebollar, Esther

    2015-09-01

    Polymer ferroelectric laser-induced periodic surface structures (LIPSS) have been prepared on ferroelectric thin films of a poly(vinylidene fluoride-trifluoroethylene) copolymer. Although this copolymer does not absorb light at the laser wavelength, LIPSS on the copolymer can be obtained by forming a bilayer with other light-absorbing polymers. The ferroelectric nature of the structured bilayer was proven by piezoresponse force microscopy measurements. Ferroelectric hysteresis was found on both the bilayer and the laser-structured bilayer. We show that it is possible to write ferroelectric information at the nanoscale. The laser-structured ferroelectric bilayer showed an increase in the information storage density of an order of magnitude, in comparison to the original bilayer.

  17. Fabrication of poly(methyl methacrylate)-MoS{sub 2}/graphene heterostructure for memory device application

    SciTech Connect

    Shinde, Sachin M.; Tanemura, Masaki; Kalita, Golap

    2014-12-07

    Combination of two dimensional graphene and semi-conducting molybdenum disulfide (MoS{sub 2}) is of great interest for various electronic device applications. Here, we demonstrate fabrication of a hybridized structure with the chemical vapor deposited graphene and MoS{sub 2} crystals to configure a memory device. Elongated hexagonal and rhombus shaped MoS{sub 2} crystals are synthesized by sulfurization of thermally evaporated molybdenum oxide (MoO{sub 3}) thin film. Scanning transmission electron microscope studies reveal atomic level structure of the synthesized high quality MoS{sub 2} crystals. In the prospect of a memory device fabrication, poly(methyl methacrylate) (PMMA) is used as an insulating dielectric material as well as a supporting layer to transfer the MoS{sub 2} crystals. In the fabricated device, PMMA-MoS{sub 2} and graphene layers act as the functional and electrode materials, respectively. Distinctive bistable electrical switching and nonvolatile rewritable memory effect is observed in the fabricated PMMA-MoS{sub 2}/graphene heterostructure. The developed material system and demonstrated memory device fabrication can be significant for next generation data storage applications.

  18. Semiconductor-based, large-area, flexible, electronic devices

    DOEpatents

    Goyal, Amit

    2011-03-15

    Novel articles and methods to fabricate the same resulting in flexible, large-area, triaxially textured, single-crystal or single-crystal-like, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

  19. Photoluminescence of Si nanocrystal memory devices obtained by ion beam synthesis

    SciTech Connect

    Carrada, Marzia; Wellner, Anja; Paillard, Vincent; Bonafos, Caroline; Coffin, Hubert; Claverie, Alain

    2005-12-19

    In this letter, we propose an original method to investigate Si nanocrystal-based nonvolatile memory devices, taking benefit of the photoluminescence (PL) spectroscopy and the specific optoelectronic properties of Si nanocrystals (Si-NCs). Ordered two-dimensional-arrays of Si-NCs were synthesized by ultralow-energy ion implantation in 7-nm-thick SiO{sub 2} and subsequent annealing. The Si-NCs population characteristics (size and density) were adjusted by different oxidizing annealing. This allowed, at the same time, the progressive healing of the oxide matrix. The analysis of the spectra revealed the presence of two PL bands, one due to quantum confinement effects in Si-NCs, and the other one attributed to silicon-rich oxide. Therefore, the evolution in energy and intensity of the PL bands was correlated to the oxidizing conditions, thus to the change of the Si-NCs size and density, and to the formation of stoichiometric SiO{sub 2}. These results are of great interest as being the first step in using PL spectroscopy as a nondestructive method to assess or monitor the electrical performances of the future memory devices, before any step of contact fabrication.

  20. Investigation of the Hydrogen Silsesquioxane (HSQ) Electron Resist as Insulating Material in Phase Change Memory Devices

    NASA Astrophysics Data System (ADS)

    Zhou, Jiao; Ji, Hongkai; Lan, Tian; Yan, Junbing; Zhou, Wenli; Miao, Xiangshui

    2015-01-01

    Phase change random access memory (PCRAM) affords many advantages over conventional solid-state memories due to its nonvolatility, high speed, and scalability. However, high programming current to amorphize the crystalline phase through the melt-quench process of PCRAM, known as the RESET current, poses a critical challenge and has become the most significant obstacle for its widespread commercialization. In this work, an excellent negative tone resist for high resolution electron beam lithography, hydrogen silsesquioxane (HSQ), has been investigated as the insulating material which locally blocks the contact between the bottom electrode and the phase change material in PCRAM devices. Fabrications of the highly scaled HSQ nanopore arrays (as small as 16 nm) are presented. The insulating properties of the HSQ material are studied, especially under e-beam exposure plus thermal curing. Some other critical issues about the thickness adjustment of HSQ films and the influence of the PCRAM electrode on electron scattering in e-beam lithography are discussed. In addition, the HSQ material was successfully integrated into the PCRAM devices, achieving ultra-low RESET current (sub-100 μA), outstanding on/off ratios (~50), and improved endurance at tens of nanometers.

  1. Investigation of the Hydrogen Silsesquioxane (HSQ) Electron Resist as Insulating Material in Phase Change Memory Devices

    NASA Astrophysics Data System (ADS)

    Zhou, Jiao; Ji, Hongkai; Lan, Tian; Yan, Junbing; Zhou, Wenli; Miao, Xiangshui

    2014-09-01

    Phase change random access memory (PCRAM) affords many advantages over conventional solid-state memories due to its nonvolatility, high speed, and scalability. However, high programming current to amorphize the crystalline phase through the melt-quench process of PCRAM, known as the RESET current, poses a critical challenge and has become the most significant obstacle for its widespread commercialization. In this work, an excellent negative tone resist for high resolution electron beam lithography, hydrogen silsesquioxane (HSQ), has been investigated as the insulating material which locally blocks the contact between the bottom electrode and the phase change material in PCRAM devices. Fabrications of the highly scaled HSQ nanopore arrays (as small as 16 nm) are presented. The insulating properties of the HSQ material are studied, especially under e-beam exposure plus thermal curing. Some other critical issues about the thickness adjustment of HSQ films and the influence of the PCRAM electrode on electron scattering in e-beam lithography are discussed. In addition, the HSQ material was successfully integrated into the PCRAM devices, achieving ultra-low RESET current (sub-100 μA), outstanding on/off ratios (~50), and improved endurance at tens of nanometers.

  2. Memory-assisted measurement-device-independent quantum key distribution

    NASA Astrophysics Data System (ADS)

    Panayi, Christiana; Razavi, Mohsen; Ma, Xiongfeng; Lütkenhaus, Norbert

    2014-04-01

    A protocol with the potential of beating the existing distance records for conventional quantum key distribution (QKD) systems is proposed. It borrows ideas from quantum repeaters by using memories in the middle of the link, and that of measurement-device-independent QKD, which only requires optical source equipment at the user's end. For certain memories with short access times, our scheme allows a higher repetition rate than that of quantum repeaters with single-mode memories, thereby requiring lower coherence times. By accounting for various sources of nonideality, such as memory decoherence, dark counts, misalignment errors, and background noise, as well as timing issues with memories, we develop a mathematical framework within which we can compare QKD systems with and without memories. In particular, we show that with the state-of-the-art technology for quantum memories, it is potentially possible to devise memory-assisted QKD systems that, at certain distances of practical interest, outperform current QKD implementations.

  3. Magnetic Random Access Memory based non-volatile asynchronous Muller cell for ultra-low power autonomous applications

    SciTech Connect

    Di Pendina, G. E-mail: eldar.zianbetov@cea.fr Zianbetov, E. E-mail: eldar.zianbetov@cea.fr; Beigne, E. E-mail: eldar.zianbetov@cea.fr

    2015-05-07

    Micro and nano electronic integrated circuit domain is today mainly driven by the advent of the Internet of Things for which the constraints are strong, especially in terms of power consumption and autonomy, not only during the computing phases but also during the standby or idle phases. In such ultra-low power applications, the circuit has to meet new constraints mainly linked to its changing energetic environment: long idle phases, automatic wake up, data back-up when the circuit is sporadically turned off, and ultra-low voltage power supply operation. Such circuits have to be completely autonomous regarding their unstable environment, while remaining in an optimum energetic configuration. Therefore, we propose in this paper the first MRAM-based non-volatile asynchronous Muller cell. This cell has been simulated and characterized in a very advanced 28 nm CMOS fully depleted silicon-on-insulator technology, presenting good power performance results due to an extremely efficient body biasing control together with ultra-wide supply voltage range from 160 mV up to 920 mV. The leakage current can be reduced to 154 pA thanks to reverse body biasing. We also propose an efficient standard CMOS bulk version of this cell in order to be compatible with different fabrication processes.

  4. 76 FR 55417 - In the Matter of Certain Dynamic Random Access Memory and Nand Flash Memory Devices and Products...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-09-07

    ... COMMISSION In the Matter of Certain Dynamic Random Access Memory and Nand Flash Memory Devices and Products... States after importation of certain dynamic random access memory and NAND flash memory devices and... the sale within the United States after importation of certain dynamic random access memory and...

  5. Ferroelectric memory based on nanostructures

    PubMed Central

    2012-01-01

    In the past decades, ferroelectric materials have attracted wide attention due to their applications in nonvolatile memory devices (NVMDs) rendered by the electrically switchable spontaneous polarizations. Furthermore, the combination of ferroelectric and nanomaterials opens a new route to fabricating a nanoscale memory device with ultrahigh memory integration, which greatly eases the ever increasing scaling and economic challenges encountered in the traditional semiconductor industry. In this review, we summarize the recent development of the nonvolatile ferroelectric field effect transistor (FeFET) memory devices based on nanostructures. The operating principles of FeFET are introduced first, followed by the discussion of the real FeFET memory nanodevices based on oxide nanowires, nanoparticles, semiconductor nanotetrapods, carbon nanotubes, and graphene. Finally, we present the opportunities and challenges in nanomemory devices and our views on the future prospects of NVMDs. PMID:22655750

  6. Light-bias coupling erase process for non-volatile zinc tin oxide TFT memory with a nickel nanocrystals charge trap layer

    NASA Astrophysics Data System (ADS)

    Li, Jeng-Ting; Liu, Li-Chih; Ke, Po-Hsien; Chen, Jen-Sue; Jeng, Jiann-Shing

    2016-03-01

    A nonvolatile charge trapping memory is demonstrated on a thin film transistor (TFT) using a solution processed ultra-thin (~7 nm) zinc tin oxide (ZTO) semiconductor layer with an Al2O3/Ni-nanocrystals (NCs)/SiO2 dielectric stack. A positive threshold voltage (V TH) shift of 7 V is achieved at gate programming voltage of 40 V for 1 s but the state will not be erased by applying negative gate voltage. However, the programmed V TH shift can be expediently erased by applying a gate voltage of  -10 V in conjunction with visible light illumination for 1 s. It is found that the sub-threshold swing (SS) deteriorates slightly under light illumination, indicating that photo-ionized oxygen vacancies (V\\text{o}+ and/or V\\text{o}++ ) are trapped at the interface between Al2O3 and ZTO, which assists the capture of electrons discharged from the Ni NCs charge trapping layer. The light-bias coupling action and the role of ultra-thin ZTO thickness are discussed to elucidate the efficient erasing mechanism.

  7. Determination of the optimal cation composition of ferroelectric (ZnxCd1-x)S thin films for applications to silicon-based nonvolatile memories

    NASA Astrophysics Data System (ADS)

    Hotta, Y.; Rokuta, E.; Jhoi, J.-H.; Tabata, H.; Kobayashi, H.; Kawai, T.

    2002-04-01

    Thin films of ferroelectric binary mixed II-VI compounds such as (ZnxCd1-x)S, as well as (ZnyCd1-y)Te and (ZnzCd1-z)Se (0⩽x,y,z⩽1), were examined from the standpoint of the application to Si-based nonvolatile memories. Electronic-band discontinuities at the ferroelectric-Si interface decreased significantly with increase in the atomic number of the constituent chalcogenide atoms, which favored (ZnxCd1-x)S as the most potential gate ferroelectrics among the three compounds. Polarization-field (P-E) characteristics of the (ZnxCd1-x)S films were found to largely depend on the cation composition. No hysteretic behaviors in the P-E curves were observed for high-Zn concentrations above x=0.5, while the P-E curves traced hysteretic loops due to the ferroelectricity for x<0.5. The remnant polarization was greatly dependent on the Zn concentration, and yielded a maximum of 0.03 μC/cm2 for x=0.3. On the other hand, the coercive field was not composition dependent, and was approximately 12 kV/cm.

  8. Surface modification of a ferroelectric polymer insulator for low-voltage readable nonvolatile memory in an organic field-effect transistor

    NASA Astrophysics Data System (ADS)

    Kim, Won-Ho; Bae, Jin-Hyuk; Kim, Min-Hoi; Keum, Chang-Min; Park, Jaehoon; Lee, Sin-Doo

    2011-01-01

    We demonstrate that the sequential surface modification of a ferroelectric polymer insulator plays an essential role in both the enhancement of the carrier mobility and the shift in the turn-on voltage (Von) in an organic ferroelectric field-effect transistor (FeFET) for nonvolatile memory. The surface of a ferroelectric polymer insulator, poly(vinylidene fluoride-trifluoroethylene), is physicochemically modified by the successive treatments of ultraviolet-ozone (UVO) and CF4 plasma to understand how the surface morphology and the hydrophobicity affect the grain size, the mobility, and Von in the FeFET. In a pentacene-based FeFET, the CF4 plasma irradiation leads to the mobility enhancement by a factor of about 5 as well as the shift in Von toward a positive voltage direction while the UVO treatment results in only the shift in Von toward a negative voltage direction. It is found that the sequence of the two successive treatments is critical for tailoring interfacial interactions between the ferroelectric polymer insulator and the pentacene layer. The underlying mechanism for the mobility enhancement and the shift in Von is described in terms of the surface morphology and the nature of the built-in electric field.

  9. Semiconductor-based, large-area, flexible, electronic devices on {110}<100> oriented substrates

    DOEpatents

    Goyal, Amit

    2014-08-05

    Novel articles and methods to fabricate the same resulting in flexible, oriented, semiconductor-based, electronic devices on {110}<100> textured substrates are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

  10. [100] or [110] aligned, semiconductor-based, large-area, flexible, electronic devices

    DOEpatents

    Goyal, Amit

    2015-03-24

    Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

  11. Coding with Side Information for Radiation-Tolerant Memory Devices

    NASA Astrophysics Data System (ADS)

    Hwang, E.; Jeon, S.; Negi, R.; Vijaya Kumar, B. V. K.; Cheng, M. K.

    2011-11-01

    Memory devices aboard spacecraft experience radiation-induced errors either in the form of temporary upsets (soft errors) or permanent defects (hard or stuck-at errors). Error-correcting codes (ECCs) are used to recover memory content from errors where defective cells are either regarded as erasures by the decoder or entire blocks containing defective cells are marked as unusable. In this article, alternative coding schemes are investigated for memory devices in space, where the encoder is provided with the locations of the defective cells, denoted by side information. This coding approach has the potential to improve the overall storage capacity of memory devices, since the information theoretic capacity of a channel where side information is only available at the encoder is the same as the capacity where side information is available at both the encoder and decoder. Spacecraft memory controllers typically scrub memory devices periodically for errors. Partial side information can be obtained during this scrubbing process by comparing the ECC decoder output with its input and thereby avoid the need for additional cell tests or storage overhead. In between scrubbings, the encoder can use this partial side information to account for permanent defects to improve reliability or to increase the storage capacity of onboard memory devices. In order to achieve performance gains for practical memory systems, several coding schemes that adaptively incorporate the codeword with the known side information are proposed in this article. The proposed coding schemes are evaluated by numerical simulations on a memory channel model characterized by soft and hard errors. Simulation results show that while coding with complete side information at the encoder offers the most performance gain compared to when coding without side information is used, coding with partial side information can close the gap between the optimal and current approach without incurring much additional overhead

  12. Organic memory device with polyaniline nanoparticles embedded as charging elements

    NASA Astrophysics Data System (ADS)

    Kim, Yo-Han; Kim, Minkeun; Oh, Sewook; Jung, Hunsang; Kim, Yejin; Yoon, Tae-Sik; Kim, Yong-Sang; Ho Lee, Hyun

    2012-04-01

    Polyaniline nanoparticles (PANI NPs) were synthesized and fabricated as charging elements for organic memory devices. The PANI NPs charging layer was self-assembled by epoxy-amine bonds between 3-glycidylpropyl trimethoxysilane functionalized dielectrics and PANI NPs. A memory window of 5.8 V (ΔVFB) represented by capacitance-voltage hysteresis was obtained for metal-pentacene-insulator-silicon capacitor. In addition, program/erase operations controlled by gate bias (-/+90 V) were demonstrated in the PANI NPs embedded pentacene thin film transistor device with polyvinylalcohol dielectric on flexible polyimide substrate. These results can be extended to development of fully organic-based electronic device.

  13. High Density Memory Based on Quantum Device Technology

    NASA Technical Reports Server (NTRS)

    vanderWagt, Paul; Frazier, Gary; Tang, Hao

    1995-01-01

    We explore the feasibility of ultra-high density memory based on quantum devices. Starting from overall constraints on chip area, power consumption, access speed, and noise margin, we deduce boundaries on single cell parameters such as required operating voltage and standby current. Next, the possible role of quantum devices is examined. Since the most mature quantum device, the resonant tunneling diode (RTD) can easily be integrated vertically, it naturally leads to the issue of 3D integrated memory. We propose a novel method of addressing vertically integrated bistable two-terminal devices, such as resonant tunneling diodes (RTD) and Esaki diodes, that avoids individual physical contacts. The new concept has been demonstrated experimentally in memory cells of field effect transistors (FET's) and stacked RTD's.

  14. Effect of Mechanical Loads on Stability of Nanodomains in Ferroelectric Ultrathin Films: Towards Flexible Erasing of the Non-Volatile Memories

    PubMed Central

    Chen, W. J.; Zheng, Yue; Xiong, W. M.; Feng, Xue; Wang, Biao; Wang, Ying

    2014-01-01

    Intensive investigations have been drawn on nanoscale ferroelectrics for their prospective applications such as developing memory devices. In contrast with the commonly used electrical means to process (i.e., read, write or erase) the information carried by ferroelectric domains, at present, mechanisms of non-electrical processing ferroelectric domains are relatively lacking. Here we make a systematical investigation on the stability of 180° cylindrical domains in ferroelectric nanofilms subjected to macroscopic mechanical loads, and explore the possibility of mechanical erasing. Effects of domain size, film thickness, temperature and different mechanical loads, including uniform strain, cylindrical bending and wavy bending, have been revealed. It is found that the stability of a cylindrical domain depends on its radius, temperature and film thickness. More importantly, mechanical loads have great controllability on the stability of cylindrical domains, with the critical radius nonlinearly sensitive to both strain and strain gradient. This indicates that erasing cylindrical domain can be achieved by changing the strain state of nanofilm. Based on the calculated phase diagrams, we successfully simulate several mechanical erasing processes on 4 × 4 bits memory devices. Our study sheds light on prospective device applications of ferroelectrics involving mechanical loads, such as flexible memory devices and other micro-electromechanical systems. PMID:24938187

  15. Effect of Mechanical Loads on Stability of Nanodomains in Ferroelectric Ultrathin Films: Towards Flexible Erasing of the Non-Volatile Memories

    NASA Astrophysics Data System (ADS)

    Chen, W. J.; Zheng, Yue; Xiong, W. M.; Feng, Xue; Wang, Biao; Wang, Ying

    2014-06-01

    Intensive investigations have been drawn on nanoscale ferroelectrics for their prospective applications such as developing memory devices. In contrast with the commonly used electrical means to process (i.e., read, write or erase) the information carried by ferroelectric domains, at present, mechanisms of non-electrical processing ferroelectric domains are relatively lacking. Here we make a systematical investigation on the stability of 180° cylindrical domains in ferroelectric nanofilms subjected to macroscopic mechanical loads, and explore the possibility of mechanical erasing. Effects of domain size, film thickness, temperature and different mechanical loads, including uniform strain, cylindrical bending and wavy bending, have been revealed. It is found that the stability of a cylindrical domain depends on its radius, temperature and film thickness. More importantly, mechanical loads have great controllability on the stability of cylindrical domains, with the critical radius nonlinearly sensitive to both strain and strain gradient. This indicates that erasing cylindrical domain can be achieved by changing the strain state of nanofilm. Based on the calculated phase diagrams, we successfully simulate several mechanical erasing processes on 4 × 4 bits memory devices. Our study sheds light on prospective device applications of ferroelectrics involving mechanical loads, such as flexible memory devices and other micro-electromechanical systems.

  16. Electrically Variable or Programmable Nonvolatile Capacitors

    NASA Technical Reports Server (NTRS)

    Shangqing, Liu; NaiJuan, Wu; Ignatieu, Alex; Jianren, Li

    2009-01-01

    Electrically variable or programmable capacitors based on the unique properties of thin perovskite films are undergoing development. These capacitors show promise of overcoming two important deficiencies of prior electrically programmable capacitors: Unlike in the case of varactors, it is not necessary to supply power continuously to make these capacitors retain their capacitance values. Hence, these capacitors may prove useful as components of nonvolatile analog and digital electronic memories. Unlike in the case of ferroelectric capacitors, it is possible to measure the capacitance values of these capacitors without changing the values. In other words, whereas readout of ferroelectric capacitors is destructive, readout of these capacitors can be nondestructive. A capacitor of this type is a simple two terminal device. It includes a thin film of a suitable perovskite as the dielectric layer, sandwiched between two metal or metal oxide electrodes (for example, see Figure 1). The utility of this device as a variable capacitor is based on a phenomenon, known as electrical-pulse-induced capacitance (EPIC), that is observed in thin perovskite films and especially in those thin perovskite films that exhibit the colossal magnetoresistive (CMR) effect. In EPIC, the application of one or more electrical pulses that exceed a threshold magnitude (typically somewhat less than 1 V) gives rise to a nonvolatile change in capacitance. The change in capacitance depends on the magnitude duration, polarity, and number of pulses. It is not necessary to apply a magnetic field or to cool the device below (or heat it above) room temperature to obtain EPIC. Examples of suitable CMR perovskites include Pr(1-x)Ca(x)MnO3, La(1-x)S-r(x)MnO3,and Nb(1-x)Ca(x)MnO3. Figure 2 is a block diagram showing an EPIC capacitor connected to a circuit that can vary the capacitance, measure the capacitance, and/or measure the resistance of the capacitor.

  17. {100}<100> or 45.degree.-rotated {100}<100>, semiconductor-based, large-area, flexible, electronic devices

    DOEpatents

    Goyal, Amit

    2012-05-15

    Novel articles and methods to fabricate the same resulting in flexible, {100}<100> or 45.degree.-rotated {100}<100> oriented, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

  18. Physical and electrical properties of band-engineered SiO2/(TiO2) x (SiO2)1- x stacks for nonvolatile memory applications

    NASA Astrophysics Data System (ADS)

    Oh, Jinho; Na, Heedo; Mok, In-Su; Kim, Jonggi; Lee, Kyumin; Sohn, Hyunchul

    2012-09-01

    In our study, the physical properties of (TiO2) x (SiO2)1- x , including band-gap, band-offset, and thermal stability and the electrical properties of band-engineered SiO2/(TiO2) x (SiO2)1- x tunnel barrier stacks, including the tunneling current and charge-trapping characteristics for applications to nonvolatile memory devices were investigated. It was observed that the band-gap and band-offset of (TiO2) x (SiO2)1- x can be controlled by adjustment in the composition of the (TiO2) x (SiO2)1- x films. Ti-silicate film with TiO2:SiO2 cycle ratio of 1:5 was maintained in an amorphous phase, even after annealing at 950 °C. The tunneling current of the band-engineered SiO2/(TiO2) x (SiO2)1- x stacked tunnel barrier was larger than that of a single SiO2 barrier under a higher external bias, while the tunneling current of a SiO2/(TiO2) x (SiO2)1- x stacked tunnel barrier under a lower external bias was smaller. Charge-trapping tests showed that the voltage shift for SiO2/(TiO2) x (SiO2)1- x is slightly larger than that for single SiO2.

  19. Impacts of annealing temperature on charge trapping performance in Zr0.5Hf0.5O2 for nonvolatile memory

    NASA Astrophysics Data System (ADS)

    Zhao, J. H.; Yan, X. B.; Li, Y. C.; Yang, T.; Jia, X. L.; Zhou, Z. Y.; Zhang, Y. Y.

    2016-10-01

    In this study, Zr0.5Hf0.5O2 films were fabricated on Si substrate and were annealed at different temperatures by rapid thermal annealing (RTA) process. The charge trapping memory devices based on Zr0.5Hf0.5O2/SiO2/Si simple structure were investigated in detail. The memory device annealing at 690 °C shows the best property with a memory window of 5.6 V under ±12 V sweeping voltages in its capacitance-voltage curve and a better retention property. The high resolved transmission electron microscopy shows the generated SiO2 working as tunneling layer after RTA process, whose thickness increases with the rise of temperature. Combined with the TEM results, the photoluminescence spectrum and in situ angle resolved photoemission spectroscopy results further verify that oxygen vacancies and inter-diffusion layer also play a crucial role in charge trapping performance. This work provides direct insights for the charge trapping mechanisms based on high-k Zr0.5Hf0.5O2 films devices.

  20. Pattern recognition with magnonic holographic memory device

    SciTech Connect

    Kozhevnikov, A.; Dudko, G.; Filimonov, Y.; Gertz, F.; Khitun, A.

    2015-04-06

    In this work, we present experimental data demonstrating the possibility of using magnonic holographic devices for pattern recognition. The prototype eight-terminal device consists of a magnetic matrix with micro-antennas placed on the periphery of the matrix to excite and detect spin waves. The principle of operation is based on the effect of spin wave interference, which is similar to the operation of optical holographic devices. Input information is encoded in the phases of the spin waves generated on the edges of the magnonic matrix, while the output corresponds to the amplitude of the inductive voltage produced by the interfering spin waves on the other side of the matrix. The level of the output voltage depends on the combination of the input phases as well as on the internal structure of the magnonic matrix. Experimental data collected for several magnonic matrixes show the unique output signatures in which maxima and minima correspond to specific input phase patterns. Potentially, magnonic holographic devices may provide a higher storage density compare to optical counterparts due to a shorter wavelength and compatibility with conventional electronic devices. The challenges and shortcoming of the magnonic holographic devices are also discussed.

  1. Two-Bit/Cell Programming Characteristics of High-Density NOR-Type Flash Memory Device with Recessed Channel Structure and Spacer-Type Nitride Layer

    NASA Astrophysics Data System (ADS)

    Han, Kyoung-Rok; Lee, Jong-Ho

    2006-10-01

    The structure of novel 2-bit/cell silicon-oxide-nitride-oxide-silicon (SONOS) flash memory device was proposed and characterized for sub-50 nm non-volatile memory (NVM) technology. A proposed memory cell has spacer-type storage nodes on both sidewalls in a recessed channel region. It was shown that counter channel doping near the bottom of the recessed channel is very important and can improve the Vth margin for 2-bit/cell operation by ˜2.5 times. By controlling doping profiles of the channel doping and the counter channel doping in the recessed channel region, we could obtain the Vth margin more than ˜1.5 V.

  2. Power reduction by power gating in differential pair type spin-transfer-torque magnetic random access memories for low-power nonvolatile cache memories

    NASA Astrophysics Data System (ADS)

    Ohsawa, Takashi; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

    2014-01-01

    Array operation currents in spin-transfer-torque magnetic random access memories (STT-MRAMs) that use four differential pair type magnetic tunnel junction (MTJ)-based memory cells (4T2MTJ, two 6T2MTJs and 8T2MTJ) are simulated and compared with that in SRAM. With L3 cache applications in mind, it is assumed that the memories are composed of 32 Mbyte capacity to be accessed in 64 byte in parallel. All the STT-MRAMs except for the 8T2MTJ one are designed with 32 bit fine-grained power gating scheme applied to eliminate static currents in the memory cells that are not accessed. The 8T2MTJ STT-MRAM, the cell’s design concept being not suitable for the fine-grained power gating, loads and saves 32 Mbyte data in 64 Mbyte unit per 1 Mbit sub-array in 2 × 103 cycles. It is shown that the array operation current of the 4T2MTJ STT-MRAM is 70 mA averaged in 15 ns write cycles at Vdd = 0.9 V. This is the smallest among the STT-MRAMs, about the half of the low standby power (LSTP) SRAM whose array operation current is totally dominated by the cells’ subthreshold leakage.

  3. Programmable Analog Memory Resistors For Electronic Neural Networks

    NASA Technical Reports Server (NTRS)

    Ramesham, Rajeshuni; Thakoor, Sarita; Daud, Taher; Thakoor, Anilkumar P.

    1990-01-01

    Electrical resistance of new solid-state device altered repeatedly by suitable control signals, yet remains at steady value when control signal removed. Resistance set at low value ("on" state), high value ("off" state), or at any convenient intermediate value and left there until new value desired. Circuits of this type particularly useful in nonvolatile, associative electronic memories based on models of neural networks. Such programmable analog memory resistors ideally suited as synaptic interconnects in "self-learning" neural nets. Operation of device depends on electrochromic property of WO3, which when pure is insulator. Potential uses include nonvolatile, erasable, electronically programmable read-only memories.

  4. Automatic memory management policies for low power, memory limited, and delay intolerant devices

    NASA Astrophysics Data System (ADS)

    Jahid, Md. Abu

    Mobile devices such as smartphones and tablets are energy and memory limited, and implement graphical user interfaces that are intolerant of computational delays. Mobile device platforms supporting apps implemented in languages that require automatic memory management, such as the Dalvik (Java) virtual machine within Google's Android, have become dominant. It is essential that automatic memory management avoid causing unacceptable interface delays while responsibly managing energy and memory resource usage. Dalvik's automatic memory management policies for heap growth and garbage collection scheduling utilize heuristics tuned to minimize memory footprint. These policies result in only marginally acceptable response times and garbage collection signicantly contributes to apps' CPU time and therefore energy consumption. The primary contributions of this research include a characterization of Dalvik's "baseline" automatic memory management policy, the development of a new "adaptive" policy, and an investigation of the performance of this policy. The investigation indicates that this adaptive policy consumes less CPU time and improves interactive performance at the cost of increasing memory footprint size by an acceptable amount.

  5. Camera memory study for large space telescope. [charge coupled devices

    NASA Technical Reports Server (NTRS)

    Hoffman, C. P.; Brewer, J. E.; Brager, E. A.; Farnsworth, D. L.

    1975-01-01

    Specifications were developed for a memory system to be used as the storage media for camera detectors on the large space telescope (LST) satellite. Detectors with limited internal storage time such as intensities charge coupled devices and silicon intensified targets are implied. The general characteristics are reported of different approaches to the memory system with comparisons made within the guidelines set forth for the LST application. Priority ordering of comparisons is on the basis of cost, reliability, power, and physical characteristics. Specific rationales are provided for the rejection of unsuitable memory technologies. A recommended technology was selected and used to establish specifications for a breadboard memory. Procurement scheduling is provided for delivery of system breadboards in 1976, prototypes in 1978, and space qualified units in 1980.

  6. Nonvolatile optically-erased colloidal memristors

    NASA Astrophysics Data System (ADS)

    Huebner, Christopher F.; Tsyalkovsky, Volodymyr; Bandera, Yuriy; Burdette, Mary K.; Shetzline, Jamie A.; Tonkin, Charles; Creager, Stephen E.; Foulger, Stephen H.

    2015-01-01

    A nonconjugated methacrylate terpolymer containing carbazole moieties (electron donors), 1,3,4-oxadiazole moieties (electron acceptors), and Coumarin-6 in the pendant groups was synthesized via free radical copolymerization of methacrylate monomers containing the respective functional groups. The terpolymer was formed into 57 nm particles through a mini-emulsion route. For a thin 100 nm film of the fused particles sandwiched between an indium-tin oxide (ITO) electrode and an Al electrode, the structure behaved as a nonvolatile flash (rewritable) memory with accessible electronic states that could be written, read, and optically erased. The device exhibited a turn-on voltage of ca. -4.5 VDC and a 106 current ratio. A device in the ON high conductance state could be reverted to the OFF state with a short exposure to a 360 nm light source. The development of semiconducting colloidal inks that can be converted into electroactive devices through a continuous processing method is a critical step in the widespread adoption of these 2D manufacturing technologies for printed electronics.

  7. Micro devices using shape memory polymer patches for mated connections

    DOEpatents

    Lee, Abraham P.; Fitch, Joseph P.

    2000-01-01

    A method and micro device for repositioning or retrieving miniature devices located in inaccessible areas, such as medical devices (e.g., stents, embolic coils, etc.) located in a blood vessel. The micro repositioning or retrieving device and method uses shape memory polymer (SMP) patches formed into mating geometries (e.g., a hoop and a hook) for re-attachment of the deposited medical device to a catheter or guidewire. For example, SMP or other material hoops are formed on the medical device to be deposited in a blood vessel, and SMP hooks are formed on the micro device attached to a guidewire, whereby the hooks on the micro device attach to the hoops on the medical device, or vice versa, enabling deposition, movement, re-deposit, or retrieval of the medical device. By changing the temperature of the SMP hooks, the hooks can be attached to or released from the hoops located on the medical device. An exemplary method for forming the hooks and hoops involves depositing a sacrificial thin film on a substrate, patterning and processing the thin film to form openings therethrough, depositing or bonding SMP materials in the openings so as to be attached to the substrate, and removing the sacrificial thin film.

  8. Computational design of digital and memory biological devices

    PubMed Central

    Rodrigo, Guillermo

    2008-01-01

    The use of combinatorial optimization techniques with computational design allows the development of automated methods to design biological systems. Automatic design integrates design principles in an unsupervised algorithm to sample a larger region of the biological network space, at the topology and parameter levels. The design of novel synthetic transcriptional networks with targeted behaviors will be key to understand the design principles underlying biological networks. In this work, we evolve transcriptional networks towards a targeted dynamics, by using a library of promoters and coding sequences, to design a complex biological memory device. The designed sequential transcription network implements a JK-Latch, which is fully predictable and richer than other memory devices. Furthermore, we present designs of transcriptional devices behaving as logic gates, and we show how to create digital behavior from analog promoters. Our procedure allows us to propose a scenario for the evolution of multi-functional genetic networks. In addition, we discuss the decomposability of regulatory networks in terms of genetic modules to develop a given cellular function. Summary. We show how to use an automated procedure to design logic and sequential transcription circuits. This methodology will allow advancing the rational design of biological devices to more complex systems, and we propose the first design of a biological JK-latch memory device. Electronic supplementary material The online version of this article (doi:10.1007/s11693-008-9017-0) contains supplementary material, which is available to authorized users. PMID:19003443

  9. Multilevel conductance switching of memory device through photoelectric effect.

    PubMed

    Ye, Changqing; Peng, Qian; Li, Mingzhu; Luo, Jia; Tang, Zhengming; Pei, Jian; Chen, Jianming; Shuai, Zhigang; Jiang, Lei; Song, Yanlin

    2012-12-12

    A photoelectronic switch of a multilevel memory device has been achieved using a meta-conjugated donor-bridge-acceptor (DBA) molecule. Such a DBA optoelectronic molecule responds to both the optical and electrical stimuli. The device exhibits good electrical bistable switching behaviors under dark, with a large ON/OFF ratio more than 10(6). In cooperation with the UV light, photoelectronic ternary states are addressable in a bistable switching system. On the basis of the CV measurement, charge carriers transport modeling, quantum chemical calculation, and absorption spectra analysis, the mechanism of the DBA memory is suggested to be attributed to the substep charge transfer transition process. The capability of tailoring photoelectrical properties is a very promising strategy to explore the multilevel storage, and it will give a new opportunity for designing multifunctional devices.

  10. Photoresponsive memory device based on Graphene/Boron Nitride heterostructure

    NASA Astrophysics Data System (ADS)

    Kahn, Salman; Velasco, Jairo, Jr.; Ju, Long; Wong, Dillon; Lee, Juwon; Tsai, Hsin Zon; Taniguchi, Takashi; Watanabe, Kenji; Zettl, Alex; Wang, Feng; Crommie, Michael

    2015-03-01

    Recent technological advancements have allowed the stacking of two dimensional layered material in order to create van der Waals heterostructures (VDH), enabling the design of novel properties by exploiting the proximal interaction between layers with different electronic properties. We report the creation of an optoelectronic memory device using a Graphene/Boron Nitride (hBN) heterostructure. Using the photo-induced doping phenomenon, we are able to spatially ``write'' a doping profile on graphene and ``read'' the profile through electrical transport and local probe techniques. We then utilize defect engineering to enhance the optoelectronic response of graphene and explore the effect of defects in hBN. Our work introduces a simple device architecture to create an optoelectronic memory device and contributes towards understanding the proximal effects of hBN on Graphene.

  11. Some Improvements in Utilization of Flash Memory Devices

    NASA Technical Reports Server (NTRS)

    Gender, Thomas K.; Chow, James; Ott, William E.

    2009-01-01

    Two developments improve the utilization of flash memory devices in the face of the following limitations: (1) a flash write element (page) differs in size from a flash erase element (block), (2) a block must be erased before its is rewritten, (3) lifetime of a flash memory is typically limited to about 1,000,000 erases, (4) as many as 2 percent of the blocks of a given device may fail before the expected end of its life, and (5) to ensure reliability of reading and writing, power must not be interrupted during minimum specified reading and writing times. The first development comprises interrelated software components that regulate reading, writing, and erasure operations to minimize migration of data and unevenness in wear; perform erasures during idle times; quickly make erased blocks available for writing; detect and report failed blocks; maintain the overall state of a flash memory to satisfy real-time performance requirements; and detect and initialize a new flash memory device. The second development is a combination of hardware and software that senses the failure of a main power supply and draws power from a capacitive storage circuit designed to hold enough energy to sustain operation until reading or writing is completed.

  12. A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

    NASA Astrophysics Data System (ADS)

    Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

    2016-04-01

    A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70 nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20 MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 µs using 128-dimension bag-of-feature patterns, and the measured average operation power of the entire processor core is only 600 µW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.

  13. Modulation of surface trap induced resistive switching by electrode annealing in individual PbS micro/nanowire-based devices for resistance random access memory.

    PubMed

    Zheng, Jianping; Cheng, Baochang; Wu, Fuzhang; Su, Xiaohui; Xiao, Yanhe; Guo, Rui; Lei, Shuijin

    2014-12-10

    Bipolar resistive switching (RS) devices are commonly believed as a promising candidate for next generation nonvolatile resistance random access memory (RRAM). Here, two-terminal devices based on individual PbS micro/nanowires with Ag electrodes are constructed, whose electrical transport depends strongly on the abundant surface and bulk trap states in micro/nanostructures. The surface trap states can be filled/emptied effectively at negative/positive bias voltage, respectively, and the corresponding rise/fall of the Fermi level induces a variation in a degenerate/nondegenerate state, resulting in low/high resistance. Moreover, the filling/emptying of trap states can be utilized as RRAM. After annealing, the surface trap state can almost be eliminated completely; while most of the bulk trap states can still remain. In the devices unannealed and annealed at both ends, therefore, the symmetrical back-to-back Fowler-Nordheim tunneling with large ON/OFF resistance ratio and Poole-Frenkel emission with poor hysteresis can be observed under cyclic sweep voltage, respectively. However, a typical bipolar RS behavior can be observed effectively in the devices annealed at one end. The acquirement of bipolar RS and nonvolatile RRAM by the modulation of electrode annealing demonstrates the abundant trap states in micro/nanomaterials will be advantageous to the development of new type electronic components.

  14. 76 FR 73676 - Certain Dynamic Random Access Memory Devices, and Products Containing Same; Receipt of Complaint...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-11-29

    ... COMMISSION Certain Dynamic Random Access Memory Devices, and Products Containing Same; Receipt of Complaint... complaint entitled In Re Certain Dynamic Random Access Memory Devices, and Products Containing Same, DN 2859... within the United States after importation of certain dynamic random access memory devices, and...

  15. 76 FR 80964 - Certain Dynamic Random Access Memory Devices, and Products Containing Same; Institution of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-12-27

    ... COMMISSION Certain Dynamic Random Access Memory Devices, and Products Containing Same; Institution of... States after importation of certain dynamic random access memory devices, and products containing same by... dynamic random access memory devices, and products containing same that infringe one or more of claims...

  16. RFID and Memory Devices Fabricated Integrally on Substrates

    NASA Technical Reports Server (NTRS)

    Schramm, Harry F.

    2004-01-01

    Electronic identification devices containing radio-frequency identification (RFID) circuits and antennas would be fabricated integrally with the objects to be identified, according to a proposal. That is to say, the objects to be identified would serve as substrates for the deposition and patterning of the materials of the devices used to identify them, and each identification device would be bonded to the identified object at the molecular level. Vacuum arc vapor deposition (VAVD) is the NASA derived process for depositing layers of material on the substrate. This proposal stands in contrast to the current practice of fabricating RFID and/or memory devices as wafer-based, self-contained integrated-circuit chips that are subsequently embedded in or attached to plastic cards to make smart account-information cards and identification badges. If one relies on such a chip to store data on the history of an object to be tracked and the chip falls off or out of the object, then one loses both the historical data and the means to track the object and verify its identity electronically. Also, in contrast is the manufacturing philosophy in use today to make many memory devices. Today s methods involve many subtractive processes such as etching. This proposal only uses additive methods, building RFID and memory devices from the substrate up in thin layers. VAVD is capable of spraying silicon, copper, and other materials commonly used in electronic devices. The VAVD process sprays most metals and some ceramics. The material being sprayed has a very strong bond with the substrate, whether that substrate is metal, ceramic, or even wood, rock, glass, PVC, or paper. An object to be tagged with an identification device according to the proposal must be compatible with a vacuum deposition process. Temperature is seldom an issue as the substrate rarely reaches 150 F (66 C) during the deposition process. A portion of the surface of the object would be designated as a substrate for

  17. Coexistence of diode-like volatile and multilevel nonvolatile resistive switching in a ZrO2/TiO2 stack structure

    NASA Astrophysics Data System (ADS)

    Li, Yingtao; Yuan, Peng; Fu, Liping; Li, Rongrong; Gao, Xiaoping; Tao, Chunlan

    2015-10-01

    Diode-like volatile resistive switching as well as nonvolatile resistive switching behaviors in a Cu/ZrO2/TiO2/Ti stack are investigated. Depending on the current compliance during the electroforming process, either volatile resistive switching or nonvolatile resistive switching is observed. With a lower current compliance (<10 μA), the Cu/ZrO2/TiO2/Ti device exhibits diode-like volatile resistive switching with a rectifying ratio over 106. The permanent transition from volatile to nonvolatile resistive switching can be obtained by applying a higher current compliance of 100 μA. Furthermore, by using different reset voltages, the Cu/ZrO2/TiO2/Ti device exhibits multilevel memory characteristics with high uniformity. The coexistence of nonvolatile multilevel memory and diode-like volatile resistive switching behaviors in the same Cu/ZrO2/TiO2/Ti device opens areas of applications in high-density storage, logic circuits, neural networks, and passive crossbar memory selectors.

  18. Coexistence of diode-like volatile and multilevel nonvolatile resistive switching in a ZrO2/TiO2 stack structure.

    PubMed

    Li, Yingtao; Yuan, Peng; Fu, Liping; Li, Rongrong; Gao, Xiaoping; Tao, Chunlan

    2015-10-01

    Diode-like volatile resistive switching as well as nonvolatile resistive switching behaviors in a Cu/ZrO₂/TiO₂/Ti stack are investigated. Depending on the current compliance during the electroforming process, either volatile resistive switching or nonvolatile resistive switching is observed. With a lower current compliance (<10 μA), the Cu/ZrO₂/TiO₂/Ti device exhibits diode-like volatile resistive switching with a rectifying ratio over 10(6). The permanent transition from volatile to nonvolatile resistive switching can be obtained by applying a higher current compliance of 100 μA. Furthermore, by using different reset voltages, the Cu/ZrO₂/TiO₂/Ti device exhibits multilevel memory characteristics with high uniformity. The coexistence of nonvolatile multilevel memory and diode-like volatile resistive switching behaviors in the same Cu/ZrO₂/TiO₂/Ti device opens areas of applications in high-density storage, logic circuits, neural networks, and passive crossbar memory selectors.

  19. A flexible organic resistance memory device for wearable biomedical applications

    NASA Astrophysics Data System (ADS)

    Cai, Yimao; Tan, Jing; YeFan, Liu; Lin, Min; Huang, Ru

    2016-07-01

    Parylene is a Food and Drug Administration (FDA)-approved material which can be safely used within the human body and it is also offers chemically inert and flexible merits. Here, we present a flexible parylene-based organic resistive random access memory (RRAM) device suitable for wearable biomedical application. The proposed device is fabricated through standard lithography and pattern processes at room temperature, exhibiting the feasibility of integration with CMOS circuits. This organic RRAM device offers a high storage window (>104), superior retention ability and immunity to disturbing. In addition, brilliant mechanical and electrical stabilities of this device are demonstrated when under harsh bending (bending cycle >500, bending radius <10 mm). Finally, the underlying mechanism for resistance switching of this kind of device is discussed, and metallic conducting filament formation and annihilation related to oxidization/redox of Al and Al anions migrating in the parylene layer can be attributed to resistance switching in this device. These advantages reveal the significant potential of parylene-based flexible RRAM devices for wearable biomedical applications.

  20. A flexible organic resistance memory device for wearable biomedical applications.

    PubMed

    Cai, Yimao; Tan, Jing; YeFan, Liu; Lin, Min; Huang, Ru

    2016-07-01

    Parylene is a Food and Drug Administration (FDA)-approved material which can be safely used within the human body and it is also offers chemically inert and flexible merits. Here, we present a flexible parylene-based organic resistive random access memory (RRAM) device suitable for wearable biomedical application. The proposed device is fabricated through standard lithography and pattern processes at room temperature, exhibiting the feasibility of integration with CMOS circuits. This organic RRAM device offers a high storage window (>10(4)), superior retention ability and immunity to disturbing. In addition, brilliant mechanical and electrical stabilities of this device are demonstrated when under harsh bending (bending cycle >500, bending radius <10 mm). Finally, the underlying mechanism for resistance switching of this kind of device is discussed, and metallic conducting filament formation and annihilation related to oxidization/redox of Al and Al anions migrating in the parylene layer can be attributed to resistance switching in this device. These advantages reveal the significant potential of parylene-based flexible RRAM devices for wearable biomedical applications. PMID:27242345

  1. Multilevel non-volatile data storage utilizing common current hysteresis of networked single walled carbon nanotubes

    NASA Astrophysics Data System (ADS)

    Hwang, Ihn; Wang, Wei; Hwang, Sun Kak; Cho, Sung Hwan; Kim, Kang Lib; Jeong, Beomjin; Huh, June; Park, Cheolmin

    2016-05-01

    The characteristic source-drain current hysteresis frequently observed in field-effect transistors with networked single walled carbon-nanotube (NSWNT) channels is problematic for the reliable switching and sensing performance of devices. But the two distinct current states of the hysteresis curve at a zero gate voltage can be useful for memory applications. In this work, we demonstrate a novel non-volatile transistor memory with solution-processed NSWNTs which are suitable for multilevel data programming and reading. A polymer passivation layer with a small amount of water employed on the top of the NSWNT channel serves as an efficient gate voltage dependent charge trapping and de-trapping site. A systematic investigation evidences that the water mixed in a polymer passivation solution is critical for reliable non-volatile memory operation. The optimized device is air-stable and temperature-resistive up to 80 °C and exhibits excellent non-volatile memory performance with an on/off current ratio greater than 104, a switching time less than 100 ms, data retention longer than 4000 s, and write/read endurance over 100 cycles. Furthermore, the gate voltage dependent charge injection mediated by water in the passivation layer allowed for multilevel operation of our memory in which 4 distinct current states were programmed repetitively and preserved over a long time period.The characteristic source-drain current hysteresis frequently observed in field-effect transistors with networked single walled carbon-nanotube (NSWNT) channels is problematic for the reliable switching and sensing performance of devices. But the two distinct current states of the hysteresis curve at a zero gate voltage can be useful for memory applications. In this work, we demonstrate a novel non-volatile transistor memory with solution-processed NSWNTs which are suitable for multilevel data programming and reading. A polymer passivation layer with a small amount of water employed on the top of the

  2. Resistive switching characteristics and mechanisms in silicon oxide memory devices

    NASA Astrophysics Data System (ADS)

    Chang, Yao-Feng; Fowler, Burt; Chen, Ying-Chen; Zhou, Fei; Wu, Xiaohan; Chen, Yen-Ting; Wang, Yanzhen; Xue, Fei; Lee, Jack C.

    2016-05-01

    Intrinsic unipolar SiOx-based resistance random access memories (ReRAM) characterization, switching mechanisms, and applications have been investigated. Device structures, material compositions, and electrical characteristics are identified that enable ReRAM cells with high ON/OFF ratio, low static power consumption, low switching power, and high readout-margin using complementary metal-oxide semiconductor transistor (CMOS)-compatible SiOx-based materials. These ideas are combined with the use of horizontal and vertical device structure designs, composition optimization, electrical control, and external factors to help understand resistive switching (RS) mechanisms. Measured temperature effects, pulse response, and carrier transport behaviors lead to compact models of RS mechanisms and energy band diagrams in order to aid the development of computer-aided design for ultralarge-v scale integration. This chapter presents a comprehensive investigation of SiOx-based RS characteristics and mechanisms for the post-CMOS device era.

  3. Effect of annealing treatment on the electrical characteristics of Pt/Cr-embedded ZnO/Pt resistance random access memory devices

    SciTech Connect

    Chang, Li-Chun; Kao, Hsuan-Ling; Liu, Keng-Hao

    2014-03-15

    ZnO/Cr/ZnO trilayer films sandwiched with Pt electrodes were prepared for nonvolatile resistive memory applications. The threshold voltage of a ZnO device embedded with a 3-nm Cr interlayer was approximately 50% lower than that of a ZnO monolayer device. This study investigated threshold voltage as a function of Cr thickness. Both the ZnO monolayer device and the Cr-embedded ZnO device structures exhibited resistance switching under electrical bias both before and after rapid thermal annealing (RTA) treatment, but resistive switching effects in the two cases exhibited distinct characteristics. Compared with the as-fabricated device, the memory cell after RTA demonstrated remarkable device parameter improvements, including a lower threshold voltage, a lower write current, and a higher R{sub off}/R{sub on} ratio. Both transmission electron microscope observations and Auger electron spectroscopy revealed that the Cr charge trapping layer in Cr-embedded ZnO dispersed uniformly into the storage medium after RTA, and x-ray diffraction and x-ray photoelectron spectroscopy analyses demonstrated that the Cr atoms lost electrons to become Cr{sup 3+} ions after dispersion. These results indicated that the altered status of Cr in ZnO/Cr/ZnO trilayer films during RTA treatment was responsible for the switching mechanism transition.

  4. Self-assembled nanostructured resistive switching memory devices fabricated by templated bottom-up growth

    NASA Astrophysics Data System (ADS)

    Song, Ji-Min; Lee, Jang-Sik

    2016-01-01

    Metal-oxide-based resistive switching memory device has been studied intensively due to its potential to satisfy the requirements of next-generation memory devices. Active research has been done on the materials and device structures of resistive switching memory devices that meet the requirements of high density, fast switching speed, and reliable data storage. In this study, resistive switching memory devices were fabricated with nano-template-assisted bottom up growth. The electrochemical deposition was adopted to achieve the bottom-up growth of nickel nanodot electrodes. Nickel oxide layer was formed by oxygen plasma treatment of nickel nanodots at low temperature. The structures of fabricated nanoscale memory devices were analyzed with scanning electron microscope and atomic force microscope (AFM). The electrical characteristics of the devices were directly measured using conductive AFM. This work demonstrates the fabrication of resistive switching memory devices using self-assembled nanoscale masks and nanomateirals growth from bottom-up electrochemical deposition.

  5. Self-assembled nanostructured resistive switching memory devices fabricated by templated bottom-up growth

    PubMed Central

    Song, Ji-Min; Lee, Jang-Sik

    2016-01-01

    Metal-oxide-based resistive switching memory device has been studied intensively due to its potential to satisfy the requirements of next-generation memory devices. Active research has been done on the materials and device structures of resistive switching memory devices that meet the requirements of high density, fast switching speed, and reliable data storage. In this study, resistive switching memory devices were fabricated with nano-template-assisted bottom up growth. The electrochemical deposition was adopted to achieve the bottom-up growth of nickel nanodot electrodes. Nickel oxide layer was formed by oxygen plasma treatment of nickel nanodots at low temperature. The structures of fabricated nanoscale memory devices were analyzed with scanning electron microscope and atomic force microscope (AFM). The electrical characteristics of the devices were directly measured using conductive AFM. This work demonstrates the fabrication of resistive switching memory devices using self-assembled nanoscale masks and nanomateirals growth from bottom-up electrochemical deposition. PMID:26739122

  6. An ultra-low-power area-efficient non-volatile memory in a 0.18 μm single-poly CMOS process for passive RFID tags

    NASA Astrophysics Data System (ADS)

    Xiaoyun, Jia; Peng, Feng; Shengguang, Zhang; Nanjian, Wu; Baiqin, Zhao; Su, Liu

    2013-08-01

    This paper presents an ultra-low-power area-efficient non-volatile memory (NVM) in a 0.18 μm single-poly standard CMOS process for passive radio frequency identification (RFID) tags. In the memory cell, a novel low-power operation method is proposed to realize bi-directional Fowler—Nordheim tunneling during write operation. Furthermore, the cell is designed with PMOS transistors and coupling capacitors to minimize its area. In order to improve its reliability, the cell consists of double floating gates to store the data, and the 1 kbit NVM was implemented in a 0.18 μm single-poly standard CMOS process. The area of the memory cell and 1 kbit memory array is 96 μm2 and 0.12 mm2, respectively. The measured results indicate that the program/erase voltage ranges from 5 to 6 V The power consumption of the read/write operation is 0.19 μW/0.69 μW at a read/write rate of (268 kb/s)/(3.0 kb/s).

  7. Impact of device size and thickness of Al2O 3 film on the Cu pillar and resistive switching characteristics for 3D cross-point memory application.

    PubMed

    Panja, Rajeswar; Roy, Sourav; Jana, Debanjan; Maikap, Siddheswar

    2014-12-01

    Impact of the device size and thickness of Al2O3 film on the Cu pillars and resistive switching memory characteristics of the Al/Cu/Al2O3/TiN structures have been investigated for the first time. The memory device size and thickness of Al2O3 of 18 nm are observed by transmission electron microscope image. The 20-nm-thick Al2O3 films have been used for the Cu pillar formation (i.e., stronger Cu filaments) in the Al/Cu/Al2O3/TiN structures, which can be used for three-dimensional (3D) cross-point architecture as reported previously Nanoscale Res. Lett.9:366, 2014. Fifty randomly picked devices with sizes ranging from 8 × 8 to 0.4 × 0.4 μm(2) have been measured. The 8-μm devices show 100% yield of Cu pillars, whereas only 74% successful is observed for the 0.4-μm devices, because smaller size devices have higher Joule heating effect and larger size devices show long read endurance of 10(5) cycles at a high read voltage of -1.5 V. On the other hand, the resistive switching memory characteristics of the 0.4-μm devices with a 2-nm-thick Al2O3 film show superior as compared to those of both the larger device sizes and thicker (10 nm) Al2O3 film, owing to higher Cu diffusion rate for the larger size and thicker Al2O3 film. In consequence, higher device-to-device uniformity of 88% and lower average RESET current of approximately 328 μA are observed for the 0.4-μm devices with a 2-nm-thick Al2O3 film. Data retention capability of our memory device of >48 h makes it a promising one for future nanoscale nonvolatile application. This conductive bridging resistive random access memory (CBRAM) device is forming free at a current compliance (CC) of 30 μA (even at a lowest CC of 0.1 μA) and operation voltage of ±3 V at a high resistance ratio of >10(4). PMID:26088986

  8. Interface-engineered templates for molecular spin memory devices.

    PubMed

    Raman, Karthik V; Kamerbeek, Alexander M; Mukherjee, Arup; Atodiresei, Nicolae; Sen, Tamal K; Lazić, Predrag; Caciuc, Vasile; Michel, Reent; Stalke, Dietmar; Mandal, Swadhin K; Blügel, Stefan; Münzenberg, Markus; Moodera, Jagadeesh S

    2013-01-24

    The use of molecular spin state as a quantum of information for storage, sensing and computing has generated considerable interest in the context of next-generation data storage and communication devices, opening avenues for developing multifunctional molecular spintronics. Such ideas have been researched extensively, using single-molecule magnets and molecules with a metal ion or nitrogen vacancy as localized spin-carrying centres for storage and for realizing logic operations. However, the electronic coupling between the spin centres of these molecules is rather weak, which makes construction of quantum memory registers a challenging task. In this regard, delocalized carbon-based radical species with unpaired spin, such as phenalenyl, have shown promise. These phenalenyl moieties, which can be regarded as graphene fragments, are formed by the fusion of three benzene rings and belong to the class of open-shell systems. The spin structure of these molecules responds to external stimuli (such as light, and electric and magnetic fields), which provides novel schemes for performing spin memory and logic operations. Here we construct a molecular device using such molecules as templates to engineer interfacial spin transfer resulting from hybridization and magnetic exchange interaction with the surface of a ferromagnet; the device shows an unexpected interfacial magnetoresistance of more than 20 per cent near room temperature. Moreover, we successfully demonstrate the formation of a nanoscale magnetic molecule with a well-defined magnetic hysteresis on ferromagnetic surfaces. Owing to strong magnetic coupling with the ferromagnet, such independent switching of an adsorbed magnetic molecule has been unsuccessful with single-molecule magnets. Our findings suggest the use of chemically amenable phenalenyl-based molecules as a viable and scalable platform for building molecular-scale quantum spin memory and processors for technological development.

  9. Ferroelectric Memory Capacitors For Neural Networks

    NASA Technical Reports Server (NTRS)

    Thakoor, Sarita; Moopenn, Alexander W.; Stadler, Henry L.

    1991-01-01

    Thin-film ferroelectric capacitors proposed as nonvolatile analog memory devices. Intended primarily for use as synaptic connections in electronic neural networks. Connection strengths (synaptic weights) stored as nonlinear remanent polarizations of ferroelectric films. Ferroelectric memory and interrogation capacitors combined into memory devices in vertical or lateral configurations. Photoconductive layer modulated by light provides variable resistance to alter bias signal applied to memory capacitor. Features include nondestructive readout, simplicity, and resistance to ionizing radiation. Interrogated without destroying stored analog data. Also amenable to very-large-scale integration. Allows use of ac coupling, eliminating errors caused by dc offsets in amplifier circuits of neural networks.

  10. Bipolar resistive switching performance of the nonvolatile memory cells based on (AgI){sub 0.2}(Ag{sub 2}MoO{sub 4}){sub 0.8} solid electrolyte films

    SciTech Connect

    Yan, X. B.; Guo, H. X.; Su, Y.; Xu, B.; Li, H. T.; Xia, Y. D.; Liu, Z. G.; Yin, J.; Yan, D. W.

    2009-09-01

    Resistive switching memory cells with polycrystalline (AgI){sub 0.2}(Ag{sub 2}MoO{sub 4}){sub 0.8} (AIMO) solid electrolyte films as storage medium were fabricated on SiO{sub 2}/Pt/Ti/Si substrates by using pulse laser deposition technique and focused ion beam lithography. X-ray diffraction, scanning electron microscopy, and energy dispersive x-ray analysis have been employed to investigate the structure, the surface morphology, and the composition of AIMO thin films. The Ag/AIMO/Pt memory cells with sandwich structure exhibit stable, reproducible, and reliable resistive switching characteristics. The ratio of resistance between high resistance states and low resistance states can reach approx10{sup 5}. Moreover, the low resistance is approx500 OMEGA at a compliance current of 0.5 mA, which is favorable to reduce the power dissipation of the entire circuit. The switching-on mechanism has been discussed and the metallic conduction characteristic has also been verified. The fast response speed and the good retention properties further indicate that polycrystalline AIMO thin film is a potential candidate for the next generation nonvolatile memory.

  11. Nonvolatile Array Of Synapses For Neural Network

    NASA Technical Reports Server (NTRS)

    Tawel, Raoul

    1993-01-01

    Elements of array programmed with help of ultraviolet light. A 32 x 32 very-large-scale integrated-circuit array of electronic synapses serves as building-block chip for analog neural-network computer. Synaptic weights stored in nonvolatile manner. Makes information content of array invulnerable to loss of power, and, by eliminating need for circuitry to refresh volatile synaptic memory, makes architecture simpler and more compact.

  12. Radiation Test Challenges for Scaled Commerical Memories

    NASA Technical Reports Server (NTRS)

    LaBel, Kenneth A.; Ladbury, Ray L.; Cohn, Lewis M.; Oldham, Timothy

    2007-01-01

    As sub-100nm CMOS technologies gather interest, the radiation effects performance of these technologies provide a significant challenge. In this talk, we shall discuss the radiation testing challenges as related to commercial memory devices. The focus will be on complex test and failure modes emerging in state-of-the-art Flash non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs), which are volatile. Due to their very high bit density, these device types are highly desirable for use in the natural space environment. In this presentation, we shall discuss these devices with emphasis on considerations for test and qualification methods required.

  13. Study on immersion lithography defectivity improvement in memory device manufacturing

    NASA Astrophysics Data System (ADS)

    He, Weiming; Hu, Huayong; Wu, Qiang

    2015-03-01

    As integrated circuit (IC) industry steps into immersion lithography's era, defectivity in photolithography becomes more complex which requires more efforts in the analysis and solution finding when compared to traditional dry lithographic process. In this paper, we focus on one type of immersion defect from memory or flash memory devices with typical mask layouts. Since the use of self-aligned double patterning (SADP) or other double patterning techniques, the original single pattern layer has to be split into 2 mask layers: logic area vs cell area. One characteristic of such split process is that the total mask transmission rate (TR) is above 70%, with extended open area and a pattern area with a transmission rate close to 50%. This indicates that it may have special defect mechanism and type compared to logic devices. We have found one type of residue defect with center ring-like map. We have studied this defect with different development recipes and analyzed their underlying mechanisms. We have also studied the effect of different immersion photoresists including types with top-coating and without top-coating, as well as the effect of bottom anti-reflection coating (BARC) substrate (organic-BARC/Si-BARC). The results of our study will be presented and discussed.

  14. Novel nano materials for high performance logic and memory devices

    NASA Astrophysics Data System (ADS)

    Das, Saptarshi

    After decades of relentless progress, the silicon CMOS industry is approaching a stall in device performance for both logic and memory devices due to fundamental scaling limitations. In order to reinforce the accelerating pace, novel materials with unique properties are being proposed on an urgent basis. This list includes one dimensional nanotubes, quasi one dimensional nanowires, two dimensional atomistically thin layered materials like graphene, hexagonal boron nitride and the more recently the rich family of transition metal di-chalcogenides comprising of MoS2, WSe2, WS2 and many more for logic applications and organic and inorganic ferroelectrics, phase change materials and magnetic materials for memory applications. Only time will tell who will win, but exploring these novel materials allow us to revisit the fundamentals and strengthen our understanding which will ultimately be beneficial for high performance device design. While there has been growing interest in two-dimensional (2D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancies due to the lack of a complete picture of their performance potential. The fact that the 2-D layered semiconducting di-chalcogenides need to be connected to the "outside" world in order to capitalize on their ultimate potential immediately emphasizes the importance of a thorough understanding of the contacts. This thesis demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2D material can be harvested. A comprehensive experimental study on the dependence of carrier mobility on the layer thickness of back gated multilayer MoS 2 field effect transistors is also provided. A resistor network model that comprises of Thomas-Fermi charge screening and interlayer coupling is used to explain the non-monotonic trend in the extracted field effect

  15. Reversible and Nonvolatile Modulations of Magnetization Switching Characteristic and Domain Configuration in L10-FePt Films via Nonelectrically Controlled Strain Engineering.

    PubMed

    Feng, Chun; Zhao, Jiancheng; Yang, Feng; Hao, Shijie; Gong, Kui; Hu, Di; Cao, Yi; Jiang, Xumin; Wang, Zhongqiang; Chen, Lei; Li, Sirui; Sun, Li; Cui, Lishan; Yu, Guanghua

    2016-03-23

    Reversible and nonvolatile modulation of magnetization switching characteristic in ferromagnetic materials is crucial in developing spintronic devices with low power consumption. It is recently discovered that strain engineering can be an active and effective approach in tuning the magnetic/transport properties of thin films. The primary method in strain modulation is via the converse piezoelectric effect of ferroelectrics, which is usually volatile due to the reliance of the required electric field. Also the maximum amount of deformation in ferroelectrics is usually limited to be less than 1%, and the corresponding magnetoelastic strain energy introduced to ferromagnetic films is on the order of 10(4) J/m(3), not enough to overcome magnetocrystalline anisotropy energy (Ku) in many materials. Different from using conventional strain inducing substrates, this paper reports on the significantly large, reversible, and nonvolatile lattice strain in the L10-FePt films (up to 2.18%) using nonelectrically controlled shape memory alloy substrates. Introduced lattice strain can be large enough to effectively affect domain structure and magnetic reversal in FePt. A noticeable decrease of coercivity field by 80% is observed. Moreover, the coercivity field tunability using such substrates is nonvolatile at room temperature and is also reversible due to the characteristics of the shape memory effect. This finding provides an efficient avenue for developing strain assisted spintronic devices such as logic memory device, magnetoresistive random-access memory, and memristor.

  16. Transistor memory devices with large memory windows, using multi-stacking of densely packed, hydrophobic charge trapping metal nanoparticle array.

    PubMed

    Cho, Ikjun; Kim, Beom Joon; Ryu, Sook Won; Cho, Jeong Ho; Cho, Jinhan

    2014-12-19

    Organic field-effect transistor (OFET) memories have rapidly evolved from low-cost and flexible electronics with relatively low-memory capacities to memory devices that require high-capacity memory such as smart memory cards or solid-state hard drives. Here, we report the high-capacity OFET memories based on the multilayer stacking of densely packed hydrophobic metal NP layers in place of the traditional transistor memory systems based on a single charge trapping layer. We demonstrated that the memory performances of devices could be significantly enhanced by controlling the adsorption isotherm behavior, multilayer stacking structure and hydrophobicity of the metal NPs. For this study, tetraoctylammonium (TOA)-stabilized Au nanoparticles (TOA-Au(NPs)) were consecutively layer-by-layer (LbL) assembled with an amine-functionalized poly(amidoamine) dendrimer (PAD). The formed (PAD/TOA-Au(NP))(n) films were used as a multilayer stacked charge trapping layer at the interface between the tunneling dielectric layer and the SiO2 gate dielectric layer. For a single AuNP layer (i.e. PAD/TOA-Au(NP))1) with a number density of 1.82 × 10(12) cm(-2), the memory window of the OFET memory device was measured to be approximately 97 V. The multilayer stacked OFET memory devices prepared with four Au(NP) layers exhibited excellent programmable memory properties (i.e. a large memory window (ΔV(th)) exceeding 145 V, a fast switching speed (1 μs), a high program/erase (P/E) current ratio (greater than 10(6)) and good electrical reliability) during writing and erasing over a relatively short time scale under an operation voltage of 100 V applied at the gate.

  17. Transistor memory devices with large memory windows, using multi-stacking of densely packed, hydrophobic charge trapping metal nanoparticle array

    NASA Astrophysics Data System (ADS)

    Cho, Ikjun; Kim, Beom Joon; Ryu, Sook Won; Cho, Jeong Ho; Cho, Jinhan

    2014-12-01

    Organic field-effect transistor (OFET) memories have rapidly evolved from low-cost and flexible electronics with relatively low-memory capacities to memory devices that require high-capacity memory such as smart memory cards or solid-state hard drives. Here, we report the high-capacity OFET memories based on the multilayer stacking of densely packed hydrophobic metal NP layers in place of the traditional transistor memory systems based on a single charge trapping layer. We demonstrated that the memory performances of devices could be significantly enhanced by controlling the adsorption isotherm behavior, multilayer stacking structure and hydrophobicity of the metal NPs. For this study, tetraoctylammonium (TOA)-stabilized Au nanoparticles (TOA-AuNPs) were consecutively layer-by-layer (LbL) assembled with an amine-functionalized poly(amidoamine) dendrimer (PAD). The formed (PAD/TOA-AuNP)n films were used as a multilayer stacked charge trapping layer at the interface between the tunneling dielectric layer and the SiO2 gate dielectric layer. For a single AuNP layer (i.e. PAD/TOA-AuNP)1) with a number density of 1.82 × 1012 cm-2, the memory window of the OFET memory device was measured to be approximately 97 V. The multilayer stacked OFET memory devices prepared with four AuNP layers exhibited excellent programmable memory properties (i.e. a large memory window (ΔVth) exceeding 145 V, a fast switching speed (1 μs), a high program/erase (P/E) current ratio (greater than 106) and good electrical reliability) during writing and erasing over a relatively short time scale under an operation voltage of 100 V applied at the gate.

  18. Transistor memory devices with large memory windows, using multi-stacking of densely packed, hydrophobic charge trapping metal nanoparticle array.

    PubMed

    Cho, Ikjun; Kim, Beom Joon; Ryu, Sook Won; Cho, Jeong Ho; Cho, Jinhan

    2014-12-19

    Organic field-effect transistor (OFET) memories have rapidly evolved from low-cost and flexible electronics with relatively low-memory capacities to memory devices that require high-capacity memory such as smart memory cards or solid-state hard drives. Here, we report the high-capacity OFET memories based on the multilayer stacking of densely packed hydrophobic metal NP layers in place of the traditional transistor memory systems based on a single charge trapping layer. We demonstrated that the memory performances of devices could be significantly enhanced by controlling the adsorption isotherm behavior, multilayer stacking structure and hydrophobicity of the metal NPs. For this study, tetraoctylammonium (TOA)-stabilized Au nanoparticles (TOA-Au(NPs)) were consecutively layer-by-layer (LbL) assembled with an amine-functionalized poly(amidoamine) dendrimer (PAD). The formed (PAD/TOA-Au(NP))(n) films were used as a multilayer stacked charge trapping layer at the interface between the tunneling dielectric layer and the SiO2 gate dielectric layer. For a single AuNP layer (i.e. PAD/TOA-Au(NP))1) with a number density of 1.82 × 10(12) cm(-2), the memory window of the OFET memory device was measured to be approximately 97 V. The multilayer stacked OFET memory devices prepared with four Au(NP) layers exhibited excellent programmable memory properties (i.e. a large memory window (ΔV(th)) exceeding 145 V, a fast switching speed (1 μs), a high program/erase (P/E) current ratio (greater than 10(6)) and good electrical reliability) during writing and erasing over a relatively short time scale under an operation voltage of 100 V applied at the gate. PMID:25426661

  19. Nonvolatile Bio-Memristor Fabricated with Egg Albumen Film

    PubMed Central

    Chen, Ying-Chih; Yu, Hsin-Chieh; Huang, Chun-Yuan; Chung, Wen-Lin; Wu, San-Lein; Su, Yan-Kuin

    2015-01-01

    This study demonstrates the fabrication and characterization of chicken egg albumen-based bio-memristors. By introducing egg albumen as an insulator to fabricate memristor devices comprising a metal/insulator/metal sandwich structure, significant bipolar resistive switching behavior can be observed. The 1/f noise characteristics of the albumen devices were measured, and results suggested that their memory behavior results from the formation and rupture of conductive filaments. Oxygen diffusion and electrochemical redox reaction of metal ions under a sufficiently large electric field are the principal physical mechanisms of the formation and rupture of conductive filaments; these mechanisms were observed by analysis of the time-of-flight secondary ion mass spectrometry (TOF-SIMS) and resistance–temperature (R–T) measurement results. The switching property of the devices remarkably improved by heat-denaturation of proteins; reliable switching endurance of over 500 cycles accompanied by an on/off current ratio (Ion/off) of higher than 103 were also observed. Both resistance states could be maintained for a suitably long time (>104 s). Taking the results together, the present study reveals for the first time that chicken egg albumen is a promising material for nonvolatile memory applications. PMID:25950812

  20. Nonvolatile bio-memristor fabricated with egg albumen film.

    PubMed

    Chen, Ying-Chih; Yu, Hsin-Chieh; Huang, Chun-Yuan; Chung, Wen-Lin; Wu, San-Lein; Su, Yan-Kuin

    2015-05-07

    This study demonstrates the fabrication and characterization of chicken egg albumen-based bio-memristors. By introducing egg albumen as an insulator to fabricate memristor devices comprising a metal/insulator/metal sandwich structure, significant bipolar resistive switching behavior can be observed. The 1/f noise characteristics of the albumen devices were measured, and results suggested that their memory behavior results from the formation and rupture of conductive filaments. Oxygen diffusion and electrochemical redox reaction of metal ions under a sufficiently large electric field are the principal physical mechanisms of the formation and rupture of conductive filaments; these mechanisms were observed by analysis of the time-of-flight secondary ion mass spectrometry (TOF-SIMS) and resistance-temperature (R-T) measurement results. The switching property of the devices remarkably improved by heat-denaturation of proteins; reliable switching endurance of over 500 cycles accompanied by an on/off current ratio (Ion/off) of higher than 10(3) were also observed. Both resistance states could be maintained for a suitably long time (>10(4) s). Taking the results together, the present study reveals for the first time that chicken egg albumen is a promising material for nonvolatile memory applications.

  1. Nonvolatile Bio-Memristor Fabricated with Egg Albumen Film

    NASA Astrophysics Data System (ADS)

    Chen, Ying-Chih; Yu, Hsin-Chieh; Huang, Chun-Yuan; Chung, Wen-Lin; Wu, San-Lein; Su, Yan-Kuin

    2015-05-01

    This study demonstrates the fabrication and characterization of chicken egg albumen-based bio-memristors. By introducing egg albumen as an insulator to fabricate memristor devices comprising a metal/insulator/metal sandwich structure, significant bipolar resistive switching behavior can be observed. The 1/f noise characteristics of the albumen devices were measured, and results suggested that their memory behavior results from the formation and rupture of conductive filaments. Oxygen diffusion and electrochemical redox reaction of metal ions under a sufficiently large electric field are the principal physical mechanisms of the formation and rupture of conductive filaments; these mechanisms were observed by analysis of the time-of-flight secondary ion mass spectrometry (TOF-SIMS) and resistance-temperature (R-T) measurement results. The switching property of the devices remarkably improved by heat-denaturation of proteins; reliable switching endurance of over 500 cycles accompanied by an on/off current ratio (Ion/off) of higher than 103 were also observed. Both resistance states could be maintained for a suitably long time (>104 s). Taking the results together, the present study reveals for the first time that chicken egg albumen is a promising material for nonvolatile memory applications.

  2. The future of memory

    NASA Astrophysics Data System (ADS)

    Marinella, M.

    In the not too distant future, the traditional memory and storage hierarchy of may be replaced by a single Storage Class Memory (SCM) device integrated on or near the logic processor. Traditional magnetic hard drives, NAND flash, DRAM, and higher level caches (L2 and up) will be replaced with a single high performance memory device. The Storage Class Memory paradigm will require high speed (< 100 ns read/write), excellent endurance (> 1012), nonvolatility (retention > 10 years), and low switching energies (< 10 pJ per switch). The International Technology Roadmap for Semiconductors (ITRS) has recently evaluated several potential candidates SCM technologies, including Resistive (or Redox) RAM, Spin Torque Transfer RAM (STT-MRAM), and phase change memory (PCM). All of these devices show potential well beyond that of current flash technologies and research efforts are underway to improve the endurance, write speeds, and scalabilities to be on-par with DRAM. This progress has interesting implications for space electronics: each of these emerging device technologies show excellent resistance to the types of radiation typically found in space applications. Commercially developed, high density storage class memory-based systems may include a memory that is physically radiation hard, and suitable for space applications without major shielding efforts. This paper reviews the Storage Class Memory concept, emerging memory devices, and possible applicability to radiation hardened electronics for space.

  3. Method and device for maximizing memory system bandwidth by accessing data in a dynamically determined order

    NASA Technical Reports Server (NTRS)

    Wulf, William A. (Inventor); McKee, Sally A. (Inventor); Klenke, Robert (Inventor); Schwab, Andrew J. (Inventor); Moyer, Stephen A. (Inventor); Aylor, James (Inventor); Hitchcock, Charles Young (Inventor)

    2000-01-01

    A data processing system is disclosed which comprises a data processor and memory control device for controlling the access of information from the memory. The memory control device includes temporary storage and decision ability for determining what order to execute the memory accesses. The compiler detects the requirements of the data processor and selects the data to stream to the memory control device which determines a memory access order. The order in which to access said information is selected based on the location of information stored in the memory. The information is repeatedly accessed from memory and stored in the temporary storage until all streamed information is accessed. The information is stored until required by the data processor. The selection of the order in which to access information maximizes bandwidth and decreases the retrieval time.

  4. Nonvolatile data storage using mechanical force-induced polarization switching in ferroelectric polymer

    SciTech Connect

    Chen, Xin; Tang, Xin; Chen, Xiang-Zhong; Chen, Yu-Lei; Shen, Qun-Dong; Guo, Xu; Ge, Hai-Xiong

    2015-01-26

    Ferroelectric polymers offer the promise of low-cost and flexible electronic products. They are attractive for information storage due to their spontaneous polarization which is usually switched by electric field. Here, we demonstrate that electrical signals can be readily written on ultra-thin ferroelectric polymer films by strain gradient-induced polarization switching (flexoelectric effect). A force with magnitude as small as 64nN is enough to induce highly localized (40 nm feature size) change in the polarization states. The methodology is capable of realizing nonvolatile memory devices with miniaturized cell size and storage density of tens to hundreds Gbit per square inch.

  5. Novel nano materials for high performance logic and memory devices

    NASA Astrophysics Data System (ADS)

    Das, Saptarshi

    After decades of relentless progress, the silicon CMOS industry is approaching a stall in device performance for both logic and memory devices due to fundamental scaling limitations. In order to reinforce the accelerating pace, novel materials with unique properties are being proposed on an urgent basis. This list includes one dimensional nanotubes, quasi one dimensional nanowires, two dimensional atomistically thin layered materials like graphene, hexagonal boron nitride and the more recently the rich family of transition metal di-chalcogenides comprising of MoS2, WSe2, WS2 and many more for logic applications and organic and inorganic ferroelectrics, phase change materials and magnetic materials for memory applications. Only time will tell who will win, but exploring these novel materials allow us to revisit the fundamentals and strengthen our understanding which will ultimately be beneficial for high performance device design. While there has been growing interest in two-dimensional (2D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancies due to the lack of a complete picture of their performance potential. The fact that the 2-D layered semiconducting di-chalcogenides need to be connected to the "outside" world in order to capitalize on their ultimate potential immediately emphasizes the importance of a thorough understanding of the contacts. This thesis demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2D material can be harvested. A comprehensive experimental study on the dependence of carrier mobility on the layer thickness of back gated multilayer MoS 2 field effect transistors is also provided. A resistor network model that comprises of Thomas-Fermi charge screening and interlayer coupling is used to explain the non-monotonic trend in the extracted field effect

  6. Effect of glycerol on retention time and electrical properties of polymer bistable memory devices based on glycerol-modified PEDOT:PSS.

    PubMed

    Park, Boongik; Lee, Junhwan; Kim, Ohyun

    2012-01-01

    The addition of glycerol to Poly(3,4-ethylenedioxythiophene):Poly(styrene sulfonate) (PEDOT:PSS) films affected the bipolar switching characteristics of nonvolatile polymer memory devices (PMDs). Increasing the glycerol/PEDOT:PSS ratio caused increase in the OFF-current of the PMDs, but did not affect the ON-current levels. This result demonstrates that highly-conductive current paths occur in the ON-state. The write-read-erase-read cycle test was operated > 10(5) times. And, the ON-retention time is largely dependent on the glycerol to PEDOT:PSS ratio and annealing temperature. In addition, AFM analysis on the G-PEDOT:PSS films to see how the surface morphology of G-PEDOT:PSS layer influences the retention time properties was carried out. PMID:22524004

  7. 2D Mica Crystal as Electret in Organic Field-Effect Transistors for Multistate Memory.

    PubMed

    Zhang, Xiaotao; He, Yudong; Li, Rongjin; Dong, Huanli; Hu, Wenping

    2016-05-01

    Organic nonvolatile multistate storage devices based on organic field-effect transistors using mica as the 2D single-crystal electrets are developed. A4-paper-sized 2D mica crystals with flat surface are prepared successfully. Devices with mica electrets exhibit a typical memory effect and show ideal output curves on both the on and the off states.

  8. Coexistence of memory resistance and memory capacitance in TiO2 solid-state devices

    PubMed Central

    2014-01-01

    This work exploits the coexistence of both resistance and capacitance memory effects in TiO2-based two-terminal cells. Our Pt/TiO2/TiO x /Pt devices exhibit an interesting combination of hysteresis and non-zero crossing in their current-voltage (I-V) characteristic that indicates the presence of capacitive states. Our experimental results demonstrate that both resistance and capacitance states can be simultaneously set via either voltage cycling and/or voltage pulses. We argue that these state modulations occur due to bias-induced reduction of the TiO x active layer via the displacement of ionic species. PMID:25298759

  9. Coexistence of memory resistance and memory capacitance in TiO2 solid-state devices.

    PubMed

    Salaoru, Iulia; Li, Qingjiang; Khiat, Ali; Prodromakis, Themistoklis

    2014-01-01

    This work exploits the coexistence of both resistance and capacitance memory effects in TiO2-based two-terminal cells. Our Pt/TiO2/TiO x /Pt devices exhibit an interesting combination of hysteresis and non-zero crossing in their current-voltage (I-V) characteristic that indicates the presence of capacitive states. Our experimental results demonstrate that both resistance and capacitance states can be simultaneously set via either voltage cycling and/or voltage pulses. We argue that these state modulations occur due to bias-induced reduction of the TiO x active layer via the displacement of ionic species. PMID:25298759

  10. Organic nano-floating-gate transistor memory with metal nanoparticles

    NASA Astrophysics Data System (ADS)

    Van Tho, Luu; Baeg, Kang-Jun; Noh, Yong-Young

    2016-04-01

    Organic non-volatile memory is advanced topics for various soft electronics applications as lightweight, low-cost, flexible, and printable solid-state data storage media. As a key building block, organic field-effect transistors (OFETs) with a nano-floating gate are widely used and promising structures to store digital information stably in a memory cell. Different types of nano-floating-gates and their various synthesis methods have been developed and applied to fabricate nanoparticle-based non-volatile memory devices. In this review, recent advances in the classes of nano-floating-gate OFET memory devices using metal nanoparticles as charge-trapping sites are briefly reviewed. Details of device fabrication, characterization, and operation mechanisms are reported based on recent research activities reported in the literature.

  11. SEMICONDUCTOR DEVICES: Reducing the influence of STI on SONOS memory through optimizing added boron implantation technology

    NASA Astrophysics Data System (ADS)

    Yue, Xu; Feng, Yan; Zhiguo, Li; Fan, Yang; Yonggang, Wang; Jianguang, Chang

    2010-09-01

    The influence of shallow trench isolation (STI) on a 90 nm polysilicon-oxide-nitride-oxide-silicon structure non-volatile memory has been studied based on experiments. It has been found that the performance of edge memory cells adjacent to STI deteriorates remarkably. The compressive stress and boron segregation induced by STI are thought to be the main causes of this problem. In order to mitigate the STI impact, an added boron implantation in the STI region is developed as a new solution. Four kinds of boron implantation experiments have been implemented to evaluate the impact of STI on edge cells, respectively. The experimental results show that the performance of edge cells can be greatly improved through optimizing added boron implantation technology.

  12. An overview of Experimental Condensed Matter Physics in Argentina by 2014, and Oxides for Non Volatile Memory Devices: The MeMOSat Project

    NASA Astrophysics Data System (ADS)

    Levy, Pablo

    2015-03-01

    In the first part of my talk, I will describe the status of the experimental research in Condensed Matter Physics in Argentina, biased towards developments related to micro and nanotechnology. In the second part, I will describe the MeMOSat Project, a consortium aimed at producing non-volatile memory devices to work in aggressive environments, like those found in the aerospace and nuclear industries. Our devices rely on the Resistive Switching mechanism, which produces a permanent but reversible change in the electrical resistance across a metal-insulator-metal structure by means of a pulsed protocol of electrical stimuli. Our project is devoted to the study of Memory Mechanisms in Oxides (MeMO) in order to establish a technological platform that tests the Resistive RAM (ReRAM) technology for aerospace applications. A review of MeMOSat's activities is presented, covering the initial Proof of Concept in ceramic millimeter sized samples; the study of different oxide-metal couples including (LaPr)2/3Ca1/3MnO, La2/3Ca1/3MnO3, YBa2Cu3O7, TiO2, HfO2, MgO and CuO; and recent miniaturized arrays of micrometer sized devices controlled by in-house designed electronics, which were launched with the BugSat01 satellite in June2014 by the argentinian company Satellogic.

  13. Overview of Non-Volatile Testing and Screening Methods

    NASA Technical Reports Server (NTRS)

    Irom, Farokh

    2001-01-01

    Testing methods for memories and non-volatile memories have become increasingly sophisticated as they become denser and more complex. High frequency and faster rewrite times as well as smaller feature sizes have led to many testing challenges. This paper outlines several testing issues posed by novel memories and approaches to testing for radiation and reliability effects. We discuss methods for measurements of Total Ionizing Dose (TID).

  14. Architectural Techniques For Managing Non-volatile Caches

    SciTech Connect

    Mittal, Sparsh

    2013-01-01

    As chip power dissipation becomes a critical challenge in scaling processor performance, computer architects are forced to fundamentally rethink the design of modern processors and hence, the chip-design industry is now at a major inflection point in its hardware roadmap. The high leakage power and low density of SRAM poses serious obstacles in its use for designing large on-chip caches and for this reason, researchers are exploring non-volatile memory (NVM) devices, such as spin torque transfer RAM, phase change RAM and resistive RAM. However, since NVMs are not strictly superior to SRAM, effective architectural techniques are required for making them a universal memory solution. This book discusses techniques for designing processor caches using NVM devices. It presents algorithms and architectures for improving their energy efficiency, performance and lifetime. It also provides both qualitative and quantitative evaluation to help the reader gain insights and motivate them to explore further. This book will be highly useful for beginners as well as veterans in computer architecture, chip designers, product managers and technical marketing professionals.

  15. Investigation of three-terminal organic-based devices with memory effect and negative differential resistance

    NASA Astrophysics Data System (ADS)

    Yu, Li-Zhen; Lee, Ching-Ting

    2009-09-01

    The current-voltage characteristics of the gate-controlled three-terminal organic-based devices with memory effect and negative differential resistances (NDR) were studied. Gold and 9,10-di(2-naphthyl)anthracene (ADN) were used as the metal electrode and active channel layer of the devices, respectively. By using various gate-source voltages, the memory and NDR characteristics of the devices can be modulated. The memory and NDR characteristics of the devices were attributed to the formation of trapping sites in the interface between Au electrode and ADN active layer caused by the defects, when Au metal deposited on the ADN active layer.

  16. Modeling of Sonos Memory Cell Erase Cycle

    NASA Technical Reports Server (NTRS)

    Phillips, Thomas A.; MacLeond, Todd C.; Ho, Fat D.

    2010-01-01

    Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memories (NVSMS) have many advantages. These memories are electrically erasable programmable read-only memories (EEPROMs). They utilize low programming voltages, endure extended erase/write cycles, are inherently resistant to radiation, and are compatible with high-density scaled CMOS for low power, portable electronics. The SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. The SONOS floating gate charge and voltage, tunneling current, threshold voltage, and drain current were characterized during an erase cycle. Comparisons were made between the model predictions and experimental device data.

  17. Mechanical memory

    DOEpatents

    Gilkey, Jeffrey C.; Duesterhaus, Michelle A.; Peter, Frank J.; Renn, Rosemarie A.; Baker, Michael S.

    2006-08-15

    A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of memory cells, with each memory cell having a beam which can be bowed in either of two directions of curvature to indicate two different logic states for that memory cell. The memory cells can be arranged around a wheel which operates as a clocking actuator to serially shift data from one memory cell to the next. The mechanical memory can be formed using conventional surface micromachining, and can be formed as either a nonvolatile memory or as a volatile memory.

  18. Mechanical memory

    DOEpatents

    Gilkey, Jeffrey C.; Duesterhaus, Michelle A.; Peter, Frank J.; Renn, Rosemarie A.; Baker, Michael S.

    2006-05-16

    A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of memory cells, with each memory cell having a beam which can be bowed in either of two directions of curvature to indicate two different logic states for that memory cell. The memory cells can be arranged around a wheel which operates as a clocking actuator to serially shift data from one memory cell to the next. The mechanical memory can be formed using conventional surface micromachining, and can be formed as either a nonvolatile memory or as a volatile memory.

  19. Carbon Nanotube Memory Elements

    SciTech Connect

    Meunier, Vincent; Sumpter, Bobby G

    2010-01-01

    Carbon nanotubes are among the most cited prototypical materials for nanoelectronics and information storage devices, a dominant position that originates from their intrinsic structural and electronic properties. In this chapter we review the developments in memory elements that directly exploit the unique properties of carbon nanotubes. Fundamental operational principles and characteristics are examined for the different types of carbon nanotube-based memory devices along with the current status of experimental fabrication and scalability. These include memory elements based on carbon nanotube field-effect transistors (CNFET), nanoelectromechanical systems (NEMS), and electromigration. Many of these devices show tremendous promise for providing enhanced densities, lower power requirements, more efficient read/write processes, and non-volatility of data.

  20. Performance Improvements of Metal-Oxide-Nitride-Oxide-Silicon Nonvolatile Memory with ZrO2 Charge-Trapping Layer by Using Nitrogen Incorporation

    NASA Astrophysics Data System (ADS)

    Chen, Jian-Xiong; Xu, Jing-Ping; Liu, Lu; Lai, Pui-To

    2013-08-01

    The properties of ZrO2 and ZrON as the charge-trapping layer (CTL) of metal-oxide-nitride-oxide-silicon memory are investigated. The microstructure and chemical bonding are examined by X-ray diffraction and X-ray photoelectron spectroscopy. It is found that nitrogen incorporation in ZrO2 can induce more charge-trapping sites, effectively suppress the formation of zirconium silicate (leading to better interface quality between the CTL and the SiO2 tunneling layer), and increase the dielectric constant of ZrO2, thus improving the memory performances (large memory window, high program/erase speed, good endurance characteristics, and small charge loss).

  1. Impacts of Co doping on ZnO transparent switching memory device characteristics

    NASA Astrophysics Data System (ADS)

    Simanjuntak, Firman Mangasa; Prasad, Om Kumar; Panda, Debashis; Lin, Chun-An; Tsai, Tsung-Ling; Wei, Kung-Hwa; Tseng, Tseung-Yuen

    2016-05-01

    The resistive switching characteristics of indium tin oxide (ITO)/Zn1-xCoxO/ITO transparent resistive memory devices were investigated. An appropriate amount of cobalt dopant in ZnO resistive layer demonstrated sufficient memory window and switching stability. In contrast, pure ZnO devices demonstrated a poor memory window, and using an excessive dopant concentration led to switching instability. To achieve suitable memory performance, relying only on controlling defect concentrations is insufficient; the grain growth orientation of the resistive layer must also be considered. Stable endurance with an ON/OFF ratio of more than one order of magnitude during 5000 cycles confirmed that the Co-doped ZnO device is a suitable candidate for resistive random access memory application. Additionally, fully transparent devices with a high transmittance of up to 90% at wavelength of 550 nm have been fabricated.

  2. La{sub 0.5}Sr{sub 0.5}CoO{sub 3} electrode technology for Pb(Zr, Ti)O{sub 3} thin film nonvolatile memories

    SciTech Connect

    Tuttle, B.A.; Al-Shareef, H.N.; Warren, W.L.; Raymond, M.V.; Headley, T.J.; Voigt, J.A.

    1995-07-01

    Oxide electrode technology is investigated for optimization of Pb(Zr,Ti)O{sub 3} (PZT) thin film capacitor properties for high density nonvolatile memory applications. PZT thin film capacitors with RF sputter deposited La{sub 0.5}Sr{sub 0.5}CoO{sub 3} (LSCO) electrodes have been characterized with respect to the following parameters: initial dielectric hysteresis loop characteristics, fatigue performance, microstructure and imprint behavior. Our studies have determined that the fatigue of PZT capacitors with LSCO electrodes is less sensitive to B site cation ratio and underlying electrode stack technology than with RuO{sub 2} electrodes. Doping PZT thin films with Nb (PNZT) improves imprint behavior of LSCO//PZT//LSCO capacitors considerably. We have demonstrated that PNZT 4/30/70 // LSCO capacitors thermally processed at either 550{degrees}C or 675{degrees}C have almost identical initial hysteresis properties and exhibit essentially no fatigue out to approximately 10{sup 10} cycles.

  3. Polarization control for enhanced defect detection on advanced memory devices

    NASA Astrophysics Data System (ADS)

    Lee, Byoung-Ho; Ihm, Dong-Chul; Yeo, Jeong-Ho; Gluk, Yael; Meshulach, Doron

    2006-03-01

    Dense repetitive wafer structures, such as memory cells, with a pitch below the wavelength of the illumination light may take on effective birefringent properties, especially in layers of high refractive index materials such as silicon or conductors. Such induced "form birefringence" effects may result in dependency of the optical response on the illumination polarization and direction. In such structures, control over the polarization of the light becomes important to enhance signal-to-noise ratio (SNR) of pattern defects. We present defect detection results and analysis using DUV laser illumination for different polarization configurations and collection perspectives on Flash RAM devices. Improvement in detection SNR of bridge defect type is observed with linear illumination polarization perpendicular to the pattern lines. Generally, for small design rules (smaller than wavelength) polarization effects become more evident. Also, for smaller defect sizes, detection strongly depends on control of the illumination polarization. Linear polarization perpendicular to the pattern showed penetration into the structure even though the pitch is smaller than the illumination wavelength.

  4. SHADE: A Shape-Memory-Activated Device Promoting Ankle Dorsiflexion

    NASA Astrophysics Data System (ADS)

    Pittaccio, S.; Viscuso, S.; Rossini, M.; Magoni, L.; Pirovano, S.; Villa, E.; Besseghini, S.; Molteni, F.

    2009-08-01

    Acute post-stroke rehabilitation protocols include passive mobilization as a means to prevent contractures. A device (SHADE) that provides repetitive passive motion to a flaccid ankle by using shape memory alloy actuators could be of great help in providing this treatment. A suitable actuator was designed as a cartridge of approximately 150 × 20 × 15 mm, containing 2.5 m of 0.25 mm diameter NiTi wire. This actuator was activated by Joule’s effect employing a 7 s current input at 0.7 A, which provided 10 N through 76 mm displacement. Cooling and reset by natural convection took 30 s. A prototype of SHADE was assembled with two thermoplastic shells hinged together at the ankle and strapped on the shin and foot. Two actuators were fixed on the upper shell while an inextensible thread connected each NiTi wire to the foot shell. The passive ankle motion (passive range of motion, PROM) generated by SHADE was evaluated optoelectronically on three flaccid patients (58 ± 5 years old); acceptability was assessed by a questionnaire presented to further three flaccid patients (44 ± 11.5 years old) who used SHADE for 5 days, 30 min a day. SHADE was well accepted by all patients, produced good PROM, and caused no pain. The results prove that suitable limb mobilization can be produced by SMA actuators.

  5. Sub-nanosecond threshold-switching dynamics and set process of In3SbTe2 phase-change memory devices

    NASA Astrophysics Data System (ADS)

    Pandey, Shivendra Kumar; Manivannan, Anbarasu

    2016-06-01

    Phase-change materials show promising features for high-speed, non-volatile, random access memory, however achieving a fast electrical switching is a key challenge. We report here, the dependence of electrical switching dynamics including transient parameters such as delay time, switching time, etc., on the applied voltage and the set process of In3SbTe2 phase-change memory devices at the picosecond (ps) timescale. These devices are found to exhibit threshold-switching at a critical voltage called threshold-voltage, VT of 1.9 ± 0.1 V, having a delay time of 25 ns. Further, the delay time decreases exponentially to a remarkably smaller value, as short as 300 ± 50 ps upon increasing the applied voltage up to 1.1VT. Furthermore, we demonstrate a rapid phase-change behavior from amorphous (˜10 MΩ) to poly-crystalline (˜10 kΩ) phase using time-resolved measurements revealing an ultrafast set process, which is primarily initiated by the threshold-switching process within 550 ps for an applied voltage pulse with a pulse-width of 1.5 ns and an amplitude of 2.3 V.

  6. Configurable memory system and method for providing atomic counting operations in a memory device

    DOEpatents

    Bellofatto, Ralph E.; Gara, Alan G.; Giampapa, Mark E.; Ohmacht, Martin

    2010-09-14

    A memory system and method for providing atomic memory-based counter operations to operating systems and applications that make most efficient use of counter-backing memory and virtual and physical address space, while simplifying operating system memory management, and enabling the counter-backing memory to be used for purposes other than counter-backing storage when desired. The encoding and address decoding enabled by the invention provides all this functionality through a combination of software and hardware.

  7. Data-Intensive Memory-Map simulator and runtime

    SciTech Connect

    Essen, B. B.

    2012-05-01

    DI-MMAP is a simulator for modeling the performance of next generation non-volatile random access memory technologies (NVRAM) and a high-perfromance memory-map runtime for the Linux operating system. It is implemented as a device driver for the Linux operating system. It will be used by algorithm designers to unserstand the impact of future NVRAM on their algorithms and will be used by application developers for high-performance access to NVRAM storage.

  8. Hardware implementation of associative memory characteristics with analogue-type resistive-switching device

    NASA Astrophysics Data System (ADS)

    Moon, Kibong; Park, Sangsu; Jang, Junwoo; Lee, Daeseok; Woo, Jiyong; Cha, Euijun; Lee, Sangheon; Park, Jaesung; Song, Jeonghwan; Koo, Yunmo; Hwang, Hyunsang

    2014-12-01

    We have investigated the analogue memory characteristics of an oxide-based resistive-switching device under an electrical pulse to mimic biological spike-timing-dependent plasticity synapse characteristics. As a synaptic device, a TiN/Pr0.7Ca0.3MnO3-based resistive-switching device exhibiting excellent analogue memory characteristics was used to control the synaptic weight by applying various pulse amplitudes and cycles. Furthermore, potentiation and depression characteristics with the same spikes can be achieved by applying negative and positive pulses, respectively. By adopting complementary metal-oxide-semiconductor devices as neurons and TiN/PCMO devices as synapses, we implemented neuromorphic hardware that mimics associative memory characteristics in real time for the first time. Owing to their excellent scalability, resistive-switching devices, shows promise for future high-density neuromorphic applications.

  9. Acoustically assisted spin-transfer-torque switching of nanomagnets: An energy-efficient hybrid writing scheme for non-volatile memory

    SciTech Connect

    Biswas, Ayan K.; Bandyopadhyay, Supriyo; Atulasimha, Jayasimha

    2013-12-02

    We show that the energy dissipated to write bits in spin-transfer-torque random access memory can be reduced by an order of magnitude if a surface acoustic wave (SAW) is launched underneath the magneto-tunneling junctions (MTJs) storing the bits. The SAW-generated strain rotates the magnetization of every MTJs' soft magnet from the easy towards the hard axis, whereupon passage of a small spin-polarized current through a target MTJ selectively switches it to the desired state with > 99.99% probability at room temperature, thereby writing the bit. The other MTJs return to their original states at the completion of the SAW cycle.

  10. Resistive switching properties of Ce and Mn co-doped BiFeO3 thin films for nonvolatile memory application

    NASA Astrophysics Data System (ADS)

    Tang, Zhenhua; Zeng, Jia; Xiong, Ying; Tang, Minghua; Xu, Dinglin; Cheng, Chuanpin; Xiao, Yongguang; Zhou, Yichun

    2013-12-01

    The Ce and Mn co-doped BiFeO3 (BCFMO) thin films were synthesized on Pt/Ti/SiO2/Si substrates using a sol-gel method. The unipolar resistive switching (URS) and bipolar resistive switching (BRS) behaviors were observed in the Pt/BCFMO/Pt device structure, which was attributed to the formation/rupture of metal filaments. The fabricated device exhibits a large ROFF/RON ratio (>80), long retention time (>105 s) and low programming voltages (<1.5 V). Analysis of linear fitting current-voltage curves suggests that the space charge limited leakage current (SCLC) and Schottky emission were observed as the conduction mechanisms of the devices.

  11. Resistive switching properties of Ce and Mn co-doped BiFeO{sub 3} thin films for nonvolatile memory application

    SciTech Connect

    Tang, Zhenhua; Zeng, Jia; Tang, Minghua Xu, Dinglin; Cheng, Chuanpin; Xiao, Yongguang; Zhou, Yichun; Xiong, Ying

    2013-12-15

    The Ce and Mn co-doped BiFeO{sub 3} (BCFMO) thin films were synthesized on Pt/Ti/SiO{sub 2}/Si substrates using a sol-gel method. The unipolar resistive switching (URS) and bipolar resistive switching (BRS) behaviors were observed in the Pt/BCFMO/Pt device structure, which was attributed to the formation/rupture of metal filaments. The fabricated device exhibits a large R{sub OFF}/R{sub ON} ratio (>80), long retention time (>10{sup 5} s) and low programming voltages (<1.5 V). Analysis of linear fitting current-voltage curves suggests that the space charge limited leakage current (SCLC) and Schottky emission were observed as the conduction mechanisms of the devices.

  12. Development of Curie point switching for thin film, random access, memory device

    NASA Technical Reports Server (NTRS)

    Lewicki, G. W.; Tchernev, D. I.

    1967-01-01

    Managanese bismuthide films are used in the development of a random access memory device of high packing density and nondestructive readout capability. Memory entry is by Curie point switching using a laser beam. Readout is accomplished by microoptical or micromagnetic scanning.

  13. Memory Hooks and Other Mnemonic Devices: A Brief Overview for Language Teachers.

    ERIC Educational Resources Information Center

    Nyikos, Martha

    A mnemonic device is any technique or system to improve or aid the memory by use of formulas. Memory aids enjoyed great popularity in ancient times, but with the advent of literacy, the need for memorization was lessened and mnemonics were not taught regularly. However, recent research in cognitive psychology suggests that mnemonics, taught and…

  14. Open coil structure for bubble-memory-device packaging

    NASA Technical Reports Server (NTRS)

    Chen, T. T.; Ypma, J. E.

    1975-01-01

    Concept has several important advantages over close-wound system: memory and coil chips are separate and interchangeable; interconnections in coil level are eliminated by packing memory chip and electronics in single structure; and coil size can be adjusted to optimum value in terms of power dissipation and field uniformity.

  15. Design of a Molecular Memory Device: The Electron Transfer Shift Register Memory

    NASA Technical Reports Server (NTRS)

    Beratan, D.

    1993-01-01

    A molecular shift register memory at the molecular level is described. The memory elements consist of molecules can exit in either an oxidized or reduced state and the bits are shifted between the cells with photoinduced electron transfer reactions.

  16. Organic ferroelectric/semiconducting nanowire hybrid layer for memory storage.

    PubMed

    Cai, Ronggang; Kassa, Hailu G; Haouari, Rachid; Marrani, Alessio; Geerts, Yves H; Ruzié, Christian; van Breemen, Albert J J M; Gelinck, Gerwin H; Nysten, Bernard; Hu, Zhijun; Jonas, Alain M

    2016-03-21

    Ferroelectric materials are important components of sensors, actuators and non-volatile memories. However, possible device configurations are limited due to the need to provide screening charges to ferroelectric interfaces to avoid depolarization. Here we show that, by alternating ferroelectric and semiconducting nanowires over an insulating substrate, the ferroelectric dipole moment can be stabilized by injected free charge carriers accumulating laterally in the neighboring semiconducting nanowires. This lateral electrostatic coupling between ferroelectric and semiconducting nanowires offers new opportunities to design new device architectures. As an example, we demonstrate the fabrication of an elementary non-volatile memory device in a transistor-like configuration, of which the source-drain current exhibits a typical hysteretic behavior with respect to the poling voltage. The potential for size reduction intrinsic to the nanostructured hybrid layer offers opportunities for the development of strongly miniaturized ferroelectric and piezoelectric devices.

  17. Ferroelectric switching of poly(vinylidene difluoride-trifluoroethylene) in metal-ferroelectric-semiconductor non-volatile memories with an amorphous oxide semiconductor

    SciTech Connect

    Gelinck, G. H.; Breemen, A. J. J. M. van; Cobb, B.

    2015-03-02

    Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

  18. Ferroelectric switching of poly(vinylidene difluoride-trifluoroethylene) in metal-ferroelectric-semiconductor non-volatile memories with an amorphous oxide semiconductor

    NASA Astrophysics Data System (ADS)

    Gelinck, G. H.; van Breemen, A. J. J. M.; Cobb, B.

    2015-03-01

    Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

  19. Memory operation devices based on light-illumination ambipolar carbon-nanotube thin-film-transistors

    SciTech Connect

    Aïssa, B.; Nedil, M.; Kroeger, J.; Haddad, T.; Rosei, F.

    2015-09-28

    We report the memory operation behavior of a light illumination ambipolar single-walled carbon nanotube thin film field-effect transistors devices. In addition to the high electronic-performance, such an on/off transistor-switching ratio of 10{sup 4} and an on-conductance of 18 μS, these memory devices have shown a high retention time of both hole and electron-trapping modes, reaching 2.8 × 10{sup 4} s at room temperature. The memory characteristics confirm that light illumination and electrical field can act as an independent programming/erasing operation method. This could be a fundamental step toward achieving high performance and stable operating nanoelectronic memory devices.

  20. Organic ferroelectric/semiconducting nanowire hybrid layer for memory storage

    NASA Astrophysics Data System (ADS)

    Cai, Ronggang; Kassa, Hailu G.; Haouari, Rachid; Marrani, Alessio; Geerts, Yves H.; Ruzié, Christian; van Breemen, Albert J. J. M.; Gelinck, Gerwin H.; Nysten, Bernard; Hu, Zhijun; Jonas, Alain M.

    2016-03-01

    Ferroelectric materials are important components of sensors, actuators and non-volatile memories. However, possible device configurations are limited due to the need to provide screening charges to ferroelectric interfaces to avoid depolarization. Here we show that, by alternating ferroelectric and semiconducting nanowires over an insulating substrate, the ferroelectric dipole moment can be stabilized by injected free charge carriers accumulating laterally in the neighboring semiconducting nanowires. This lateral electrostatic coupling between ferroelectric and semiconducting nanowires offers new opportunities to design new device architectures. As an example, we demonstrate the fabrication of an elementary non-volatile memory device in a transistor-like configuration, of which the source-drain current exhibits a typical hysteretic behavior with respect to the poling voltage. The potential for size reduction intrinsic to the nanostructured hybrid layer offers opportunities for the development of strongly miniaturized ferroelectric and piezoelectric devices.Ferroelectric materials are important components of sensors, actuators and non-volatile memories. However, possible device configurations are limited due to the need to provide screening charges to ferroelectric interfaces to avoid depolarization. Here we show that, by alternating ferroelectric and semiconducting nanowires over an insulating substrate, the ferroelectric dipole moment can be stabilized by injected free charge carriers accumulating laterally in the neighboring semiconducting nanowires. This lateral electrostatic coupling between ferroelectric and semiconducting nanowires offers new opportunities to design new device architectures. As an example, we demonstrate the fabrication of an elementary non-volatile memory device in a transistor-like configuration, of which the source-drain current exhibits a typical hysteretic behavior with respect to the poling voltage. The potential for size reduction

  1. Role of the hippocampus in memory formation: restorative encoding memory integration neural device as a cognitive neural prosthesis.

    PubMed

    Berger, Theodore; Song, Dong; Chan, Rosa; Shin, Dae; Marmarelis, Vasilis; Hampson, Robert; Sweatt, Andrew; Heck, Christi; Liu, Charles; Wills, Jack; Lacoss, Jeff; Granacki, John; Gerhardt, Greg; Deadwyler, Sam

    2012-01-01

    Remind, which stands for "restorative encoding memory integration neural device," is a Defense Advanced Research Projects Agency (DARPA)-sponsored program to construct the first-ever cognitive prosthesis to replace lost memory function and enhance the existing memory capacity in animals and, ultimately, in humans. Reaching this goal involves understanding something fundamental about the brain that has not been understood previously: how the brain internally codes memories. In developing a hippocampal prosthesis for the rat, we have been able to demonstrate a multiple-input, multiple- output (MIMO) nonlinear model that predicts in real time the spatiotemporal codes for specific memories required for correct performance on a standard learning/memory task, i.e., delayed-nonmatch-to-sample (DNMS) memory. The MIMO model has been tested successfully in a number of contexts; most notably, in animals with a pharmacologically disabled hippocampus, we were able to reinstate long-term memories necessary for correct DNMS behavior by substituting a MIMO model-predicted code, delivered by electrical stimulation to the hippocampus through an array of electrodes, resulting in spatiotemporal hippocampal activity that is normally generated endogenously. We also have shown that delivering the same model-predicted code to electrode-implanted control animals with a normally functioning hippocampus substantially enhances animals memory capacity above control levels. These results in rodents have formed the basis for extending the MIMO model to nonhuman primates; this is now underway as the last step of the REMIND program before developing a MIMO-based cognitive prosthesis for humans.

  2. Logic with memory: and gates made of organic and inorganic memristive devices

    NASA Astrophysics Data System (ADS)

    Baldi, G.; Battistoni, S.; Attolini, G.; Bosi, M.; Collini, C.; Iannotta, S.; Lorenzelli, L.; Mosca, R.; Ponraj, J. S.; Verucchi, R.; Erokhin, V.

    2014-10-01

    Logic elements endowed with memory are realized with two types of memristors: organic and inorganic ones. The organic devices are based on a polyaniline/polyethylene oxide heterostructure, while the inorganic ones are based on a Pt/Al2O3/Ti heterostructure. The memristors are characterized by measuring cyclic voltage-current characteristics. They are then used to make AND gates showing memory abilities, exhibiting different behaviors. In the case of the inorganic devices the OFF/ON transitions are very fast when two inputs are applied simultaneously, while they are slow, with a gradual increase of the conductivity, in the case of the organic devices. The two types of devices are suggested as logic elements for future neuromorphic computers combining memory and processing properties.

  3. Pluto's Nonvolatile Chemical Compounds

    NASA Astrophysics Data System (ADS)

    Grundy, William M.; Binzel, Richard; Cook, Jason C.; Cruikshank, Dale P.; Dalle Ore, Cristina M.; Earle, Alissa M.; Ennico, Kimberly; Jennings, Donald; Howett, Carly; Kaiser, Ralf-Ingo; Linscott, Ivan; Lunsford, A. W.; Olkin, Catherine B.; Parker, Alex Harrison; Parker, Joel Wm.; Philippe, Sylvain; Protopapa, Silvia; Quirico, Eric; Reuter, D. C.; Schmitt, Bernard; Singer, Kelsi N.; Spencer, John R.; Stansberry, John A.; Stern, S. Alan; Tsang, Constantine; Verbiscer, Anne J.; Weaver, Harold A.; Weigle, G. E.; Young, Leslie

    2016-10-01

    Despite the migration of Pluto's volatile ices (N2, CO, and CH4) around the surface on seasonal timescales, the planet's non-volatile materials are not completely hidden from view. They occur in a variety of provinces formed over a wide range of timescales, including rugged mountains and chasms, the floors of mid-latitude craters, and an equatorial belt of especially dark and reddish material typified by the informally named Cthulhu Regio. NASA's New Horizons probe observed several of these regions at spatial resolutions as fine as 3 km/pixel with its LEISA imaging spectrometer, covering wavelengths from 1.25 to 2.5 microns. Various compounds that are much lighter than the tholin-like macromolecules responsible for the reddish coloration, but that are not volatile at Pluto surface temperatures such as methanol (CH3OH) and ethane (C2H6) have characteristic absorption bands within LEISA's wavelength range. This presentation will describe their geographic distributions and attempt to constrain their origins. Possibilities include an inheritance from Pluto's primordial composition (the likely source of H2O ice seen on Pluto's surface) or ongoing production from volatile precursors through photochemistry in Pluto's atmosphere or through radiolysis on Pluto's surface. New laboratory data inform the analysis.This work was supported by NASA's New Horizons project.

  4. Non-volatile Clocked Spin Wave Interconnect for Beyond-CMOS Nanomagnet Pipelines

    PubMed Central

    Dutta, Sourav; Chang, Sou-Chi; Kani, Nickvash; Nikonov, Dmitri E.; Manipatruni, Sasikanth; Young, Ian A.; Naeemi, Azad

    2015-01-01

    The possibility of using spin waves for information transmission and processing has been an area of active research due to the unique ability to manipulate the amplitude and phase of the spin waves for building complex logic circuits with less physical resources and low power consumption. Previous proposals on spin wave logic circuits have suggested the idea of utilizing the magneto-electric effect for spin wave amplification and amplitude- or phase-dependent switching of magneto-electric cells. Here, we propose a comprehensive scheme for building a clocked non-volatile spin wave device by introducing a charge-to-spin converter that translates information from electrical domain to spin domain, magneto-electric spin wave repeaters that operate in three different regimes - spin wave transmitter, non-volatile memory and spin wave detector, and a novel clocking scheme that ensures sequential transmission of information and non-reciprocity. The proposed device satisfies the five essential requirements for logic application: nonlinearity, amplification, concatenability, feedback prevention, and complete set of Boolean operations. PMID:25955353

  5. Magnetic Resonance Flow Velocity and Temperature Mapping of a Shape Memory Polymer Foam Device

    SciTech Connect

    Small IV, W; Gjersing, E; Herberg, J L; Wilson, T S; Maitland, D J

    2008-10-29

    Interventional medical devices based on thermally responsive shape memory polymer (SMP) are under development to treat stroke victims. The goals of these catheter-delivered devices include re-establishing blood flow in occluded arteries and preventing aneurysm rupture. Because these devices alter the hemodynamics and dissipate thermal energy during the therapeutic procedure, a first step in the device development process is to investigate fluid velocity and temperature changes following device deployment. A laser-heated SMP foam device was deployed in a simplified in vitro vascular model. Magnetic resonance imaging (MRI) techniques were used to assess the fluid dynamics and thermal changes associated with device deployment. Spatial maps of the steady-state fluid velocity and temperature change inside and outside the laser-heated SMP foam device were acquired. Though non-physiological conditions were used in this initial study, the utility of MRI in the development of a thermally-activated SMP foam device has been demonstrated.

  6. Memory Attacks on Device-Independent Quantum Cryptography

    NASA Astrophysics Data System (ADS)

    Barrett, Jonathan; Colbeck, Roger; Kent, Adrian

    2013-01-01

    Device-independent quantum cryptographic schemes aim to guarantee security to users based only on the output statistics of any components used, and without the need to verify their internal functionality. Since this would protect users against untrustworthy or incompetent manufacturers, sabotage, or device degradation, this idea has excited much interest, and many device-independent schemes have been proposed. Here we identify a critical weakness of device-independent protocols that rely on public communication between secure laboratories. Untrusted devices may record their inputs and outputs and reveal information about them via publicly discussed outputs during later runs. Reusing devices thus compromises the security of a protocol and risks leaking secret data. Possible defenses include securely destroying or isolating used devices. However, these are costly and often impractical. We propose other more practical partial defenses as well as a new protocol structure for device-independent quantum key distribution that aims to achieve composable security in the case of two parties using a small number of devices to repeatedly share keys with each other (and no other party).

  7. Memory attacks on device-independent quantum cryptography.

    PubMed

    Barrett, Jonathan; Colbeck, Roger; Kent, Adrian

    2013-01-01

    Device-independent quantum cryptographic schemes aim to guarantee security to users based only on the output statistics of any components used, and without the need to verify their internal functionality. Since this would protect users against untrustworthy or incompetent manufacturers, sabotage, or device degradation, this idea has excited much interest, and many device-independent schemes have been proposed. Here we identify a critical weakness of device-independent protocols that rely on public communication between secure laboratories. Untrusted devices may record their inputs and outputs and reveal information about them via publicly discussed outputs during later runs. Reusing devices thus compromises the security of a protocol and risks leaking secret data. Possible defenses include securely destroying or isolating used devices. However, these are costly and often impractical. We propose other more practical partial defenses as well as a new protocol structure for device-independent quantum key distribution that aims to achieve composable security in the case of two parties using a small number of devices to repeatedly share keys with each other (and no other party). PMID:23383767

  8. Memory attacks on device-independent quantum cryptography.

    PubMed

    Barrett, Jonathan; Colbeck, Roger; Kent, Adrian

    2013-01-01

    Device-independent quantum cryptographic schemes aim to guarantee security to users based only on the output statistics of any components used, and without the need to verify their internal functionality. Since this would protect users against untrustworthy or incompetent manufacturers, sabotage, or device degradation, this idea has excited much interest, and many device-independent schemes have been proposed. Here we identify a critical weakness of device-independent protocols that rely on public communication between secure laboratories. Untrusted devices may record their inputs and outputs and reveal information about them via publicly discussed outputs during later runs. Reusing devices thus compromises the security of a protocol and risks leaking secret data. Possible defenses include securely destroying or isolating used devices. However, these are costly and often impractical. We propose other more practical partial defenses as well as a new protocol structure for device-independent quantum key distribution that aims to achieve composable security in the case of two parties using a small number of devices to repeatedly share keys with each other (and no other party).

  9. Flexible Hybrid Organic-Inorganic Perovskite Memory.

    PubMed

    Gu, Chungwan; Lee, Jang-Sik

    2016-05-24

    Active research has been done on hybrid organic-inorganic perovskite materials for application to solar cells with high power conversion efficiency. However, this material often shows hysteresis, which is undesirable, shift in the current-voltage curve. The hysteresis may come from formation of defects and their movement in perovskite materials. Here, we utilize the defects in perovskite materials to be used in memory operations. We demonstrate flexible nonvolatile memory devices based on hybrid organic-inorganic perovskite as the resistive switching layer on a plastic substrate. A uniform perovskite layer is formed on a transparent electrode-coated plastic substrate by solvent engineering. Flexible nonvolatile memory based on the perovskite layer shows reproducible and reliable memory characteristics in terms of program/erase operations, data retention, and endurance properties. The memory devices also show good mechanical flexibility. It is suggested that resistive switching is done by migration of vacancy defects and formation of conducting filaments under the electric field in the perovskite layer. It is believed that organic-inorganic perovskite materials have great potential to be used in high-performance, flexible memory devices. PMID:27093096

  10. The effectiveness of music as a mnemonic device on recognition memory for people with multiple sclerosis.

    PubMed

    Moore, Kimberly Sena; Peterson, David A; O'Shea, Geoffrey; McIntosh, Gerald C; Thaut, Michael H

    2008-01-01

    Research shows that people with multiple sclerosis exhibit learning and memory difficulties and that music can be used successfully as a mnemonic device to aid in learning and memory. However, there is currently no research investigating the effectiveness of music mnemonics as a compensatory learning strategy for people with multiple sclerosis. Participants with clinically definitive multiple sclerosis (N = 38) were given a verbal learning and memory test. Results from a recognition memory task were analyzed that compared learning through music (n = 20) versus learning through speech (n = 18). Preliminary baseline neuropsychological data were collected that measured executive functioning skills, learning and memory abilities, sustained attention, and level of disability. An independent samples t test showed no significant difference between groups on baseline neuropsychological functioning or on recognition task measures. Correlation analyses suggest that music mnemonics may facilitate learning for people who are less impaired by the disease. Implications for future research are discussed.

  11. Modular nonvolatile solid state recorder (MONSSTR) update

    NASA Astrophysics Data System (ADS)

    Klang, Mark R.; Small, Martin B.; Beams, Tom

    2001-12-01

    Solid state recorders have begun replacing traditional tape recorders in fulfilling the requirement to record images on airborne platforms. With the advances in electro-optical, IR, SAR, Multi and Hyper-spectral sensors and video recording requirements, solid state recorders have become the recorder of choice. Solid state recorders provide the additional storage, higher sustained bandwidth, less power, less weight and smaller footprint to meet the current and future recording requirements. CALCULEX, Inc., manufactures a non-volatile flash memory solid state recorder called the MONSSTR (Modular Non-volatile Solid State Recorder). MONSSTR is being used to record images from many different digital sensors on high performance aircraft such as the RF- 4, F-16 and the Royal Air Force Tornado. MONSSTR, with its internal multiplexer, is also used to record instrumentation data. This includes multiple streams of PCM and multiple channels of 1553 data. Instrumentation data is being recorded by MONSSTR systems in a range of platforms including F-22, F-15, F-16, Comanche Helicopter and US Navy torpedos. MONSSTR can also be used as a cockpit video recorder. This paper will provide an update of the MONSSTR.

  12. Photo-enhanced polymer memory device based on polyimide containing spiropyran

    NASA Astrophysics Data System (ADS)

    Seok, Woong Chul; Son, Seok Ho; An, Tae Kyu; Kim, Se Hyun; Lee, Seung Woo

    2016-07-01

    This paper reports the synthesis of a new polyimide (PI) containing a spiropyran moiety in the side chain and its applications to the switchable polymer memory before and after UV exposure. UV exposure allows memory using spiropyran-based PI as an active layer with a higher current and lower switching-ON voltage compared to the unexposed device due to the structural changes in the spiropyran moiety after UV exposure. In addition, this study examined the effects of UV exposure on the performance of the memory containing spiropyran-based PI using the UV-Vis absorption spectra and space-charge limited conduction (SCLC) model. [Figure not available: see fulltext.

  13. Design and fabrication of a perpendicular magnetic tunnel junction based nonvolatile programmable switch achieving 40% less area using shared-control transistor structure

    NASA Astrophysics Data System (ADS)

    Suzuki, D.; Natsui, M.; Mochizuki, A.; Miura, S.; Honjo, H.; Kinoshita, K.; Fukami, S.; Sato, H.; Ikeda, S.; Endoh, T.; Ohno, H.; Hanyu, T.

    2014-05-01

    A compact nonvolatile programmable switch (NVPS) using 90 nm CMOS technology together with perpendicular magnetic tunnel junction (p-MTJ) devices is fabricated for zero-standby-power field-programmable gate array. Because routing information does not change once it is programmed into an NVPS, high-speed read and write accesses are not required and a write-control transistor can be shared among all the NVPSs, which greatly simplifies structure of the NVPS. In fact, the effective area of the proposed NVPS is reduced by 40% compared to that of a conventional MTJ-based NVPS. The instant on/off behavior without external nonvolatile memory access is also demonstrated using the fabricated test chip.

  14. A chiral-based magnetic memory device without a permanent magnet

    PubMed Central

    Dor, Oren Ben; Yochelis, Shira; Mathew, Shinto P.; Naaman, Ron; Paltiel, Yossi

    2013-01-01

    Several technologies are currently in use for computer memory devices. However, there is a need for a universal memory device that has high density, high speed and low power requirements. To this end, various types of magnetic-based technologies with a permanent magnet have been proposed. Recent charge-transfer studies indicate that chiral molecules act as an efficient spin filter. Here we utilize this effect to achieve a proof of concept for a new type of chiral-based magnetic-based Si-compatible universal memory device without a permanent magnet. More specifically, we use spin-selective charge transfer through a self-assembled monolayer of polyalanine to magnetize a Ni layer. This magnitude of magnetization corresponds to applying an external magnetic field of 0.4 T to the Ni layer. The readout is achieved using low currents. The presented technology has the potential to overcome the limitations of other magnetic-based memory technologies to allow fabricating inexpensive, high-density universal memory-on-chip devices. PMID:23922081

  15. Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

    NASA Technical Reports Server (NTRS)

    LaBel, Kenneth A.; Cohn, Lewis M.

    2008-01-01

    At GOMAC 2007, we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art memory technologies. This included FLASH non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs). In this presentation, we extend this discussion in device packaging and complexity as well as single event upset (SEU) mechanisms using several technology areas as examples including: system-on-a-chip (SOC) devices and photonic or fiber optic systems. The underlying goal is intended to provoke thought for understanding the limitations and interpretation of radiation testing results.

  16. Stochastic switching of TiO2-based memristive devices with identical initial memory states

    PubMed Central

    2014-01-01

    In this work, we show that identical TiO2-based memristive devices that possess the same initial resistive states are only phenomenologically similar as their internal structures may vary significantly, which could render quite dissimilar switching dynamics. We experimentally demonstrated that the resistive switching of practical devices with similar initial states could occur at different programming stimuli cycles. We argue that similar memory states can be transcribed via numerous distinct active core states through the dissimilar reduced TiO2-x filamentary distributions. Our hypothesis was finally verified via simulated results of the memory state evolution, by taking into account dissimilar initial filamentary distribution. PMID:24994953

  17. Gold nanoparticle charge trapping and relation to organic polymer memory devices.

    PubMed

    Prime, D; Paul, S; Josephs-Franks, P W

    2009-10-28

    Nanoparticle-based polymer memory devices (PMDs) are a promising technology that could replace conventional silicon-based electronic memory, offering fast operating speeds, simple device structures and low costs. Here we report on the current state of nanoparticle PMDs and review some of the problems that are still present in the field. We also present new data regarding the charging of gold nanoparticles in metal-insulator-semiconductor capacitors, showing that charging is possible under the application of an electric field with a trapped charge density due to the nanoparticles of 3.3 x 10(12) cm(-2).

  18. Charge trap memory based on few-layer black phosphorus.

    PubMed

    Feng, Qi; Yan, Faguang; Luo, Wengang; Wang, Kaiyou

    2016-02-01

    Atomically thin layered two-dimensional materials, including transition-metal dichalcogenide (TMDC) and black phosphorus (BP), have been receiving much attention, because of their promising physical properties and potential applications in flexible and transparent electronic devices. Here, for the first time we show nonvolatile charge-trap memory devices, based on field-effect transistors with large hysteresis, consisting of a few-layer black phosphorus channel and a three dimensional (3D) Al2O3/HfO2/Al2O3 charge-trap gate stack. An unprecedented memory window exceeding 12 V is observed, due to the extraordinary trapping ability of the high-k HfO2. The device shows a high endurance of over 120 cycles and a stable retention of ∼30% charge loss after 10 years, even lower than the reported MoS2 flash memory. The high program/erase current ratio, large memory window, stable retention and high on/off current ratio, provide a promising route towards flexible and transparent memory devices utilising atomically thin two-dimensional materials. The combination of 2D materials with traditional high-k charge-trap gate stacks opens up an exciting field of nonvolatile memory devices.

  19. Charge trap memory based on few-layer black phosphorus

    NASA Astrophysics Data System (ADS)

    Feng, Qi; Yan, Faguang; Luo, Wengang; Wang, Kaiyou

    2016-01-01

    Atomically thin layered two-dimensional materials, including transition-metal dichalcogenide (TMDC) and black phosphorus (BP), have been receiving much attention, because of their promising physical properties and potential applications in flexible and transparent electronic devices. Here, for the first time we show nonvolatile charge-trap memory devices, based on field-effect transistors with large hysteresis, consisting of a few-layer black phosphorus channel and a three dimensional (3D) Al2O3/HfO2/Al2O3 charge-trap gate stack. An unprecedented memory window exceeding 12 V is observed, due to the extraordinary trapping ability of the high-k HfO2. The device shows a high endurance of over 120 cycles and a stable retention of ~30% charge loss after 10 years, even lower than the reported MoS2 flash memory. The high program/erase current ratio, large memory window, stable retention and high on/off current ratio, provide a promising route towards flexible and transparent memory devices utilising atomically thin two-dimensional materials. The combination of 2D materials with traditional high-k charge-trap gate stacks opens up an exciting field of nonvolatile memory devices.

  20. CMOS compatible electrode materials selection in oxide-based memory devices

    NASA Astrophysics Data System (ADS)

    Zhuo, V. Y.-Q.; Li, M.; Guo, Y.; Wang, W.; Yang, Y.; Jiang, Y.; Robertson, J.

    2016-07-01

    Electrode materials selection guidelines for oxide-based memory devices are constructed from the combined knowledge of observed device operation characteristics, ab-initio calculations, and nano-material characterization. It is demonstrated that changing the top electrode material from Ge to Cr to Ta in the Ta2O5-based memory devices resulted in a reduction of the operation voltages and current. Energy Dispersed X-ray (EDX) Spectrometer analysis clearly shows that the different top electrode materials scavenge oxygen ions from the Ta2O5 memory layer at various degrees, leading to different oxygen vacancy concentrations within the Ta2O5, thus the observed trends in the device performance. Replacing the Pt bottom electrode material with CMOS compatible materials (Ru and Ir) further reduces the power consumption and can be attributed to the modification of the Schottky barrier height and oxygen vacancy concentration at the electrode/oxide interface. Both trends in the device performance and EDX results are corroborated by the ab-initio calculations which reveal that the electrode material tunes the oxygen vacancy concentration via the oxygen chemical potential and defect formation energy. This experimental-theoretical approach strongly suggests that the proper selection of CMOS compatible electrode materials will create the critical oxygen vacancy concentration to attain low power memory performance.

  1. Code division in optical memory devices based on photon echo

    NASA Astrophysics Data System (ADS)

    Kalachev, Alexey A.; Vlasova, Daria D.

    2006-03-01

    The theory of multi-channel optical memory based on photon echo is developed. It is shown that under long-lived photon echo regime the writing and reading of information with code division is possible using phase modulation of reference and reading pulses. A simple method for construction of a system of noise-like signals, which is based on the segmentation of Frank sequence is proposed. It is shown that in comparison to the system of random biphase signals this system leads to the efficient decreasing of mutual influence of channels and increasing of random/noise ratio under reading of information.

  2. Modeling and simulation of floating gate nanocrystal FET devices and circuits

    NASA Astrophysics Data System (ADS)

    Hasaneen, El-Sayed A. M.

    The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to

  3. Non-Hebbian Learning Implementation in Light-Controlled Resistive Memory Devices

    PubMed Central

    Ungureanu, Mariana; Stoliar, Pablo; Llopis, Roger; Casanova, Fèlix; Hueso, Luis E.

    2012-01-01

    Non-Hebbian learning is often encountered in different bio-organisms. In these processes, the strength of a synapse connecting two neurons is controlled not only by the signals exchanged between the neurons, but also by an additional factor external to the synaptic structure. Here we show the implementation of non-Hebbian learning in a single solid-state resistive memory device. The output of our device is controlled not only by the applied voltages, but also by the illumination conditions under which it operates. We demonstrate that our metal/oxide/semiconductor device learns more efficiently at higher applied voltages but also when light, an external parameter, is present during the information writing steps. Conversely, memory erasing is more efficiently at higher applied voltages and in the dark. Translating neuronal activity into simple solid-state devices could provide a deeper understanding of complex brain processes and give insight into non-binary computing possibilities. PMID:23251679

  4. How to Use Removable Mass Storage Memory Devices

    ERIC Educational Resources Information Center

    Branzburg, Jeffrey

    2004-01-01

    Mass storage refers to the variety of ways to keep large amounts of information that are used on a computer. Over the years, the removable storage devices have grown smaller, increased in capacity, and transferred the information to the computer faster. The 8" floppy disk of the 1960s stored 100 kilobytes, or about 60 typewritten, double-spaced…

  5. Oxygenated amorphous carbon for resistive memory applications

    NASA Astrophysics Data System (ADS)

    Santini, Claudia A.; Sebastian, Abu; Marchiori, Chiara; Jonnalagadda, Vara Prasad; Dellmann, Laurent; Koelmans, Wabe W.; Rossell, Marta D.; Rossel, Christophe P.; Eleftheriou, Evangelos

    2015-10-01

    Carbon-based electronics is a promising alternative to traditional silicon-based electronics as it could enable faster, smaller and cheaper transistors, interconnects and memory devices. However, the development of carbon-based memory devices has been hampered either by the complex fabrication methods of crystalline carbon allotropes or by poor performance. Here we present an oxygenated amorphous carbon (a-COx) produced by physical vapour deposition that has several properties in common with graphite oxide. Moreover, its simple fabrication method ensures excellent reproducibility and tuning of its properties. Memory devices based on a-COx exhibit outstanding non-volatile resistive memory performance, such as switching times on the order of 10 ns and cycling endurance in excess of 104 times. A detailed investigation of the pristine, SET and RESET states indicates a switching mechanism based on the electrochemical redox reaction of carbon. These results suggest that a-COx could play a key role in non-volatile memory technology and carbon-based electronics.

  6. Optical memory effect in ZnO nanowire based organic bulk heterojunction devices

    NASA Astrophysics Data System (ADS)

    Santhanakrishna, Anand Kumar; Takshi, Arash

    2015-09-01

    Due to the required established field to separate photogenerated electrons and holes, the current- voltage (I-V) characteristic in almost all photovoltaic devices in dark is an exponential curve. Upon illumination, the shape of the curve remains almost the same, but the current shifts due to the photocurrent. Also, because of the lack of any storage mechanism, the I-V curve returns to the dark characteristic immediately after light cessation. Here, we are reporting a case study performed on a photo-electric memory effect in an organic bulk hetrojuction device made of ZnO nanowires as the electron transport layer under ambient conditions and within a sealed transfer box filled with nitrogen. The I-V characteristic in dark and light showed a unique change from a rectifying response in dark to a resistive behavior in light. Additionally, after light cessation, a memory effect was observed with a slow transition from the resistive to rectifying response same as the original dark characteristic. The memory effect and its I-V characteristics were tested for the two cases. For practical applications as a photo memory device, further experiments are required to gain a better understanding of the mechanism behind the observed memory effect for the two different cases.

  7. Electro-optical switching and memory display device

    DOEpatents

    Skotheim, T.A.; O'Grady, W.E.; Linkous, C.A.

    1983-12-29

    An electro-optical display device having a housing with wall means including one transparent wall and at least one other wall. Counter electrodes are positioned on the transparent wall and display electrodes are positioned on the other wall with both electrodes in electrically conductive relationship with an electrolyte. Circuits means are connected to the display and counter electrodes to apply different predetermined control potentials between them. The display electrodes are covered with a thin electrically conductive polymer film that is characterized according to the invention by having embedded in it pigment molecules as counter ions. The display device is operable to be switched to a plurality of different visual color states at an exceptionally rapid switching rate while each of the color states is characterized by possessing good color intensity and definition.

  8. Electro-optical switching and memory display device

    DOEpatents

    Skotheim, Terje A.; O'Grady, William E.; Linkous, Clovis A.

    1986-01-01

    An electro-optical display device having a housing with wall means including one transparent wall and at least one other wall. Counter electrodes are positioned on the transparent wall and display electrodes are positioned on the other wall with both electrodes in electrically conductive relationship with an electrolyte. Circuit means are connected to the display and counter electrodes to apply different predetermined control potentials between them. The display electrodes are covered with a thin electrically conductive polymer film that is characterized according to the invention by having embedded in it pigment molecules as counter ions. The display device is operable to be switched to a plurality of different visual color states at an exceptionally rapid switching rate while each of the color states is characterized by possessing good color intensity and definition.

  9. 76 FR 4375 - In the Matter of Certain MLC Flash Memory Devices and Products Containing Same; Notice of...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-01-25

    ...''). 74 FR 43723-4 (August 27, 2009). The complaint, as amended and supplemented, alleges violations of... COMMISSION In the Matter of Certain MLC Flash Memory Devices and Products Containing Same; Notice of... flash memory devices and products containing same by reason of infringement of certain claims of...

  10. Origin of multi-level switching and telegraphic noise in organic nanocomposite memory devices

    PubMed Central

    Song, Younggul; Jeong, Hyunhak; Chung, Seungjun; Ahn, Geun Ho; Kim, Tae-Young; Jang, Jingon; Yoo, Daekyoung; Jeong, Heejun; Javey, Ali; Lee, Takhee

    2016-01-01

    The origin of negative differential resistance (NDR) and its derivative intermediate resistive states (IRSs) of nanocomposite memory systems have not been clearly analyzed for the past decade. To address this issue, we investigate the current fluctuations of organic nanocomposite memory devices with NDR and the IRSs under various temperature conditions. The 1/f noise scaling behaviors at various temperature conditions in the IRSs and telegraphic noise in NDR indicate the localized current pathways in the organic nanocomposite layers for each IRS. The clearly observed telegraphic noise with a long characteristic time in NDR at low temperature indicates that the localized current pathways for the IRSs are attributed to trapping/de-trapping at the deep trap levels in NDR. This study will be useful for the development and tuning of multi-bit storable organic nanocomposite memory device systems. PMID:27659298

  11. Realization of transient memory-loss with NiO-based resistive switching device

    NASA Astrophysics Data System (ADS)

    Hu, S. G.; Liu, Y.; Chen, T. P.; Liu, Z.; Yu, Q.; Deng, L. J.; Yin, Y.; Hosaka, Sumio

    2012-11-01

    A resistive switching device based on a nickel-rich nickel oxide thin film, which exhibits inherent learning and memory-loss abilities, is reported in this work. The conductance of the device gradually increases and finally saturates with the number of voltage pulses (or voltage sweepings), which is analogous to the behavior of the short-term and long-term memory in the human brain. Furthermore, the number of the voltage pulses (or sweeping cycles) required to achieve a given conductance state increases with the interval between two consecutive voltage pulses (or sweeping cycles), which is attributed to the heat diffusion in the material of the conductive filaments formed in the nickel oxide thin film. The phenomenon resembles the behavior of the human brain, i.e., forgetting starts immediately after an impression, a larger interval of the impressions leads to more memory loss, thus the memorization needs more impressions to enhance.

  12. A bio-inspired memory device based on interfacing Physarum polycephalum with an organic semiconductor

    SciTech Connect

    Romeo, Agostino; Dimonte, Alice; Tarabella, Giuseppe; D’Angelo, Pasquale E-mail: iannotta@imem.cnr.it; Erokhin, Victor; Iannotta, Salvatore E-mail: iannotta@imem.cnr.it

    2015-01-01

    The development of devices able to detect and record ion fluxes is a crucial point in order to understand the mechanisms that regulate communication and life of organisms. Here, we take advantage of the combined electronic and ionic conduction properties of a conducting polymer to develop a hybrid organic/living device with a three-terminal configuration, using the Physarum polycephalum Cell (PPC) slime mould as a living bio-electrolyte. An over-oxidation process induces a conductivity switch in the polymer, due to the ionic flux taking place at the PPC/polymer interface. This behaviour endows a current-depending memory effect to the device.

  13. Recent development in magnetic-bubble memory

    NASA Astrophysics Data System (ADS)

    Suzuki, Ryo

    1986-11-01

    The magnetic-bubble memory - the new solid-state nonvolatile memory - has taken a prominent place in today's memory market. It is widely used in industrial and information area, because it is reliable, maintenance-free, and durable. Improvements on bubble materials, processing, and chip design, especially Permalloy tracks, led magnetic-bubble memory to 4-Mbit devices which are now commercially available. Conventional Permalloy tracks are, however, not suitable for higher bit density devices because they require a large driving field. To overcome this problem, ion-implanted tracks have been developed. Physics of ion-implantation to garnets and the ion-implanted tracks have been studied and understood. The ion-implanted devices have been developed as 16-Mbit hybrid devices. The ion-implanted bubble technology is promising for 64-Mbit devices in the near future. In packaging, the innovative development has been done. The PFC (Picture Frame Core) packages reduce the device size drastically. In the future, the Bloch line memory - an ultra-high density memory will be developed, based on bubble memory technology. This paper reviews these technologies in detail.

  14. Memory effects in a Al/Ti:HfO2/CuPc metal-oxide-semiconductor device

    NASA Astrophysics Data System (ADS)

    Tripathi, Udbhav; Kaur, Ramneek

    2016-05-01

    Metal oxide semiconductor structured organic memory device has been successfully fabricated. Ti doped hafnium oxide (Ti:HfO2) nanoparticles has been fabricated by precipitation method and further calcinated at 800 °C. Copper phthalocyanine, a hole transporting material has been utilized as an organic semiconductor. The electrical properties of the fabricated device have been studied by measuring the current-voltage and capacitance-voltage characteristics. The amount of charge stored in the nanoparticles has been calculated by using flat band condition. This simple approach for fabricating MOS memory device has opens up opportunities for the development of next generation memory devices.

  15. Stacked-Gate FET's For Analog Memory Elements

    NASA Technical Reports Server (NTRS)

    Thakoor, Anilkumar P.; Moopenn, Alexander W.

    1991-01-01

    Three-terminal, double-stacked-gate field-effect transistor (FET), developed as analog memory element. Particularly suited for use as synapse with variable connection strength in electronic neural network. Provides programmable, nonvolatile resistive connection, somewhat in manner of porous-gate FET described in "Porous-Floating-Gate Field-Effect Transistor" (NPO-17532). Resembles commercial erasable programmable read-only memory (EPROM) device, except for thickness of layers of silicon dioxide electrically isolating gates. Either p-channel or n-channel device.

  16. Feasibility study of molecular memory device based on DNA using methylation to store information

    NASA Astrophysics Data System (ADS)

    Jiang, Liming; Qiu, Wanzhi; Al-Dirini, Feras; Hossain, Faruque M.; Evans, Robin; Skafidas, Efstratios

    2016-07-01

    DNA, because of its robustness and dense information storage capability, has been proposed as a potential candidate for next-generation storage media. However, encoding information into the DNA sequence requires molecular synthesis technology, which to date is costly and prone to synthesis errors. Reading the DNA strand information is also complex. Ideally, DNA storage will provide methods for modifying stored information. Here, we conduct a feasibility study investigating the use of the DNA 5-methylcytosine (5mC) methylation state as a molecular memory to store information. We propose a new 1-bit memory device and study, based on the density functional theory and non-equilibrium Green's function method, the feasibility of electrically reading the information. Our results show that changes to methylation states lead to changes in the peak of negative differential resistance which can be used to interrogate memory state. Our work demonstrates a new memory concept based on methylation state which can be beneficial in the design of next generation DNA based molecular electronic memory devices.

  17. Electric field tuning of non-volatile three-state magnetoelectric memory in FeCo-NiFe2O4/Pb(Mg1/3Nb2/3)0.7Ti0.3O3 heterostructures

    NASA Astrophysics Data System (ADS)

    Jiang, Changjun; Zhang, Chao; Dong, Chunhui; Guo, Dangwei; Xue, Desheng

    2015-03-01

    We demonstrate electric field impulse-induced reversible tristable magnetization switching in FeCo-NiFe2O4/Pb(Mg1/3Nb2/3)0.7Ti0.3O3 (PMN-PT) heterostructures at room temperature. The magnetic properties of the FeCo-NiFe2O4 film can be changed reversibly by the strain-mediated magnetoelectric coupling effect. Three piezostrain-mediated reversible and stable electric resistance states were obtained in the FeCo-NiFe2O4 film when different electric field impulses were applied, including large positive and negative fields and an impulse that was smaller than the electric coercive field. Consequently, reversible electric field impulse tuning of the tristable resistance state, which is related to the different magnetization switching properties of the materials, was realized. These results provide a promising approach for low loss multistate magnetoelectric memory devices for information storage applications.

  18. Multi-layered nanocomposite dielectrics for high density organic memory devices

    NASA Astrophysics Data System (ADS)

    Kang, Moonyeong; Chung, Kyungwha; Baeg, Kang-Jun; Kim, Dong Ha; Kim, Choongik

    2015-01-01

    We fabricated organic memory devices with metal-pentacene-insulator-silicon structure which contain double dielectric layers comprising 3D pattern of Au nanoparticles (Au NPs) and block copolymer (PS-b-P2VP). The role of Au NPs is to charge/discharge carriers upon applied voltage, while block copolymer helps to form highly ordered Au NP patterns in the dielectric layer. Double-layered nanocomposite dielectrics enhanced the charge trap density (i.e., trapped charge per unit area) by Au NPs, resulting in increase of the memory window (ΔVth).

  19. Solution processed molecular floating gate for flexible flash memories

    PubMed Central

    Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

    2013-01-01

    Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices. PMID:24172758

  20. Resistive switching effect of Ag/MoS2/FTO device

    NASA Astrophysics Data System (ADS)

    Sun, Bai; Zhao, Wenxi; Liu, Yonghong; Chen, Peng

    2015-09-01

    The electric-pulse-driven resistance change of metal/oxides/metal structure, which is called resistive switching effect, is a fascinating phenomenon for the development of next generation non-volatile memory. In this work, an outstanding bipolar resistive switching behavior of Ag/MoS2/fluorine-doped tin oxide (FTO) device is demonstrated. The device can maintain superior reversible stability over 100 cycles with an OFF/ON-state resistance ratio of about 103 at room temperature.

  1. Non-Volatile Ferroelectric Switching of Ferromagnetic Resonance in NiFe/PLZT Multiferroic Thin Film Heterostructures

    PubMed Central

    Hu, Zhongqiang; Wang, Xinjun; Nan, Tianxiang; Zhou, Ziyao; Ma, Beihai; Chen, Xiaoqin; Jones, John G.; Howe, Brandon M.; Brown, Gail J.; Gao, Yuan; Lin, Hwaider; Wang, Zhiguang; Guo, Rongdi; Chen, Shuiyuan; Shi, Xiaoling; Shi, Wei; Sun, Hongzhi; Budil, David; Liu, Ming; Sun, Nian X.

    2016-01-01

    Magnetoelectric effect, arising from the interfacial coupling between magnetic and electrical order parameters, has recently emerged as a robust means to electrically manipulate the magnetic properties in multiferroic heterostructures. Challenge remains as finding an energy efficient way to modify the distinct magnetic states in a reliable, reversible, and non-volatile manner. Here we report ferroelectric switching of ferromagnetic resonance in multiferroic bilayers consisting of ultrathin ferromagnetic NiFe and ferroelectric Pb0.92La0.08Zr0.52Ti0.48O3 (PLZT) films, where the magnetic anisotropy of NiFe can be electrically modified by low voltages. Ferromagnetic resonance measurements confirm that the interfacial charge-mediated magnetoelectric effect is dominant in NiFe/PLZT heterostructures. Non-volatile modification of ferromagnetic resonance field is demonstrated by applying voltage pulses. The ferroelectric switching of magnetic anisotropy exhibits extensive applications in energy-efficient electronic devices such as magnetoelectric random access memories, magnetic field sensors, and tunable radio frequency (RF)/microwave devices. PMID:27581071

  2. Non-Volatile Ferroelectric Switching of Ferromagnetic Resonance in NiFe/PLZT Multiferroic Thin Film Heterostructures

    NASA Astrophysics Data System (ADS)

    Hu, Zhongqiang; Wang, Xinjun; Nan, Tianxiang; Zhou, Ziyao; Ma, Beihai; Chen, Xiaoqin; Jones, John G.; Howe, Brandon M.; Brown, Gail J.; Gao, Yuan; Lin, Hwaider; Wang, Zhiguang; Guo, Rongdi; Chen, Shuiyuan; Shi, Xiaoling; Shi, Wei; Sun, Hongzhi; Budil, David; Liu, Ming; Sun, Nian X.

    2016-09-01

    Magnetoelectric effect, arising from the interfacial coupling between magnetic and electrical order parameters, has recently emerged as a robust means to electrically manipulate the magnetic properties in multiferroic heterostructures. Challenge remains as finding an energy efficient way to modify the distinct magnetic states in a reliable, reversible, and non-volatile manner. Here we report ferroelectric switching of ferromagnetic resonance in multiferroic bilayers consisting of ultrathin ferromagnetic NiFe and ferroelectric Pb0.92La0.08Zr0.52Ti0.48O3 (PLZT) films, where the magnetic anisotropy of NiFe can be electrically modified by low voltages. Ferromagnetic resonance measurements confirm that the interfacial charge-mediated magnetoelectric effect is dominant in NiFe/PLZT heterostructures. Non-volatile modification of ferromagnetic resonance field is demonstrated by applying voltage pulses. The ferroelectric switching of magnetic anisotropy exhibits extensive applications in energy-efficient electronic devices such as magnetoelectric random access memories, magnetic field sensors, and tunable radio frequency (RF)/microwave devices.

  3. An error-resilient non-volatile magneto-elastic universal logic gate with ultralow energy-delay product

    PubMed Central

    Biswas, Ayan K.; Atulasimha, Jayasimha; Bandyopadhyay, Supriyo

    2014-01-01

    A long-standing goal of computer technology is to process and store digital information with the same device in order to implement new architectures. One way to accomplish this is to use nanomagnetic logic gates that can perform Boolean operations and then store the output data in the magnetization states of nanomagnets, thereby doubling as both logic and memory. Unfortunately, many of these nanomagnetic devices do not possess the seven essential characteristics of a Boolean logic gate : concatenability, non-linearity, isolation between input and output, gain, universal logic implementation, scalability and error resilience. More importantly, their energy-delay products and error rates tend to vastly exceed that of conventional transistor-based logic gates, which is unacceptable. Here, we propose a non-volatile voltage-controlled nanomagnetic logic gate that possesses all the necessary characteristics of a logic gate and whose energy-delay product is two orders of magnitude less than that of other nanomagnetic (non-volatile) logic gates. The error rate is also superior. PMID:25532757

  4. Non-Volatile Ferroelectric Switching of Ferromagnetic Resonance in NiFe/PLZT Multiferroic Thin Film Heterostructures.

    PubMed

    Hu, Zhongqiang; Wang, Xinjun; Nan, Tianxiang; Zhou, Ziyao; Ma, Beihai; Chen, Xiaoqin; Jones, John G; Howe, Brandon M; Brown, Gail J; Gao, Yuan; Lin, Hwaider; Wang, Zhiguang; Guo, Rongdi; Chen, Shuiyuan; Shi, Xiaoling; Shi, Wei; Sun, Hongzhi; Budil, David; Liu, Ming; Sun, Nian X

    2016-01-01

    Magnetoelectric effect, arising from the interfacial coupling between magnetic and electrical order parameters, has recently emerged as a robust means to electrically manipulate the magnetic properties in multiferroic heterostructures. Challenge remains as finding an energy efficient way to modify the distinct magnetic states in a reliable, reversible, and non-volatile manner. Here we report ferroelectric switching of ferromagnetic resonance in multiferroic bilayers consisting of ultrathin ferromagnetic NiFe and ferroelectric Pb0.92La0.08Zr0.52Ti0.48O3 (PLZT) films, where the magnetic anisotropy of NiFe can be electrically modified by low voltages. Ferromagnetic resonance measurements confirm that the interfacial charge-mediated magnetoelectric effect is dominant in NiFe/PLZT heterostructures. Non-volatile modification of ferromagnetic resonance field is demonstrated by applying voltage pulses. The ferroelectric switching of magnetic anisotropy exhibits extensive applications in energy-efficient electronic devices such as magnetoelectric random access memories, magnetic field sensors, and tunable radio frequency (RF)/microwave devices. PMID:27581071

  5. Gate controllable resistive random access memory devices using reduced graphene oxide

    NASA Astrophysics Data System (ADS)

    Hazra, Preetam; Resmi, A. N.; Jinesh, K. B.

    2016-04-01

    The biggest challenge in the resistive random access memory (ReRAM) technology is that the basic operational parameters, such as the set and reset voltages, the current on-off ratios (hence the power), and their operational speeds, strongly depend on the active and electrode materials and their processing methods. Therefore, for its actual technological implementations, the unification of the operational parameters of the ReRAM devices appears to be a difficult task. In this letter, we show that by fabricating a resistive memory device in a thin film transistor configuration and thus applying an external gate bias, we can control the switching voltage very accurately. Taking partially reduced graphene oxide, the gate controllable switching is demonstrated, and the possible mechanisms are discussed.

  6. Digital memory device based on tobacco mosaic virus conjugated with nanoparticles.

    PubMed

    Tseng, Ricky J; Tsai, Chunglin; Ma, Liping; Ouyang, Jianyong; Ozkan, Cengiz S; Yang, Yang

    2006-10-01

    Nanostructured viruses are attractive for use as templates for ordering quantum dots to make self-assembled building blocks for next-generation electronic devices. So far, only a few types of electronic devices have been fabricated from biomolecules due to the lack of charge transport through biomolecular junctions. Here, we show a novel electronic memory effect by incorporating platinum nanoparticles into tobacco mosaic virus. The memory effect is based on conductance switching, which leads to the occurrence of bistable states with an on/off ratio larger than three orders of magnitude. The mechanism of this process is attributed to charge trapping in the nanoparticles for data storage and a tunnelling process in the high conductance state. Such hybrid bio-inorganic nanostructures show promise for applications in future nanoelectronics.

  7. Low-energy Resistive Random Access Memory Devices with No Need for a Compliance Current

    PubMed Central

    Xu, Zedong; Yu, Lina; Wu, Yong; Dong, Chang; Deng, Ning; Xu, Xiaoguang; Miao, J.; Jiang, Yong

    2015-01-01

    A novel resistive random access memory device is designed with SrTiO3/ La2/3Sr1/3MnO3 (LSMO)/MgAl2O4 (MAO)/Cu structure, in which metallic epitaxial LSMO is employed as the bottom electrode rather than traditional metal materials. In this device, the critical external compliance current is no longer necessary due to the high self-resistance of LSMO. The LMSO bottom electrode can act as a series resistor to offer a compliance current during the set process. Besides, the device also has excellent switching features which are originated in the formation of Cu filaments under external voltage. Therefore it provides the possibility of reducing power consumption and accelerating the commercialization of resistive switching devices. PMID:25982101

  8. Low-energy Resistive Random Access Memory Devices with No Need for a Compliance Current

    NASA Astrophysics Data System (ADS)

    Xu, Zedong; Yu, Lina; Wu, Yong; Dong, Chang; Deng, Ning; Xu, Xiaoguang; Miao, J.; Jiang, Yong

    2015-05-01

    A novel resistive random access memory device is designed with SrTiO3/ La2/3Sr1/3MnO3 (LSMO)/MgAl2O4 (MAO)/Cu structure, in which metallic epitaxial LSMO is employed as the bottom electrode rather than traditional metal materials. In this device, the critical external compliance current is no longer necessary due to the high self-resistance of LSMO. The LMSO bottom electrode can act as a series resistor to offer a compliance current during the set process. Besides, the device also has excellent switching features which are originated in the formation of Cu filaments under external voltage. Therefore it provides the possibility of reducing power consumption and accelerating the commercialization of resistive switching devices.

  9. A source-side injection erasable programmable read-only-memory (SI-EPROM) device

    NASA Astrophysics Data System (ADS)

    Wu, A. T.; Chan, T. Y.; Ko, P. K.; Hu, C.

    1986-09-01

    A new erasable programmable read-only memory (EPROM) device with promise for low-voltage high-speed programming is described. This device is an asymmetrical n-channel stacked-gate MOSFET, with a short weak gate-control channel region introduced close to the source. At high gate bias, a strong channel electric field is created in this local region even at a relatively low drain voltage. Furthermore, the gate oxide field in this region also aids the injection of hot electrons into the floating gate. As a result, the source-side injection EPROM has shown 10-microsec programming speed at a drain voltage of 5 V.

  10. Metal oxide resistive random access memory based synaptic devices for brain-inspired computing

    NASA Astrophysics Data System (ADS)

    Gao, Bin; Kang, Jinfeng; Zhou, Zheng; Chen, Zhe; Huang, Peng; Liu, Lifeng; Liu, Xiaoyan

    2016-04-01

    The traditional Boolean computing paradigm based on the von Neumann architecture is facing great challenges for future information technology applications such as big data, the Internet of Things (IoT), and wearable devices, due to the limited processing capability issues such as binary data storage and computing, non-parallel data processing, and the buses requirement between memory units and logic units. The brain-inspired neuromorphic computing paradigm is believed to be one of the promising solutions for realizing more complex functions with a lower cost. To perform such brain-inspired computing with a low cost and low power consumption, novel devices for use as electronic synapses are needed. Metal oxide resistive random access memory (ReRAM) devices have emerged as the leading candidate for electronic synapses. This paper comprehensively addresses the recent work on the design and optimization of metal oxide ReRAM-based synaptic devices. A performance enhancement methodology and optimized operation scheme to achieve analog resistive switching and low-energy training behavior are provided. A three-dimensional vertical synapse network architecture is proposed for high-density integration and low-cost fabrication. The impacts of the ReRAM synaptic device features on the performances of neuromorphic systems are also discussed on the basis of a constructed neuromorphic visual system with a pattern recognition function. Possible solutions to achieve the high recognition accuracy and efficiency of neuromorphic systems are presented.

  11. Interfacial behavior of resistive switching in ITO-PVK-Al WORM memory devices

    NASA Astrophysics Data System (ADS)

    Whitcher, T. J.; Woon, K. L.; Wong, W. S.; Chanlek, N.; Nakajima, H.; Saisopa, T.; Songsiriritthigul, P.

    2016-02-01

    Understanding the mechanism of resistive switching in a memory device is fundamental in order to improve device performance. The mechanism of current switching in a basic organic write-once read-many (WORM) memory device is investigated by determining the energy level alignments of indium tin oxide (ITO), poly(9-vinylcarbazole) (PVK) and aluminum (Al) using x-ray and ultraviolet photoelectron spectroscopy, current-voltage characterization and Auger depth profiling. The current switching mechanism was determined to be controlled by the interface between the ITO and the PVK. The electric field applied across the device causes the ITO from the uneven surface of the anode to form metallic filaments through the PVK, causing a shorting effect within the device leading to increased conduction. This was found to be independent of the PVK thickness, although the switch-on voltage was non-linearly dependent on the thickness. The formation of these filaments also caused the destruction of the interfacial dipole at the PVK-Al interface.

  12. Well-defined star-shaped donor-acceptor conjugated molecules for organic resistive memory devices.

    PubMed

    Wu, Hung-Chin; Zhang, Jicheng; Bo, Zhishan; Chen, Wen-Chang

    2015-09-28

    Solution processable star-shaped donor-acceptor (D-A) conjugated molecules (TPA-T-NI and TPA-3T-NI) with an electron-donating triphenylamine (TPA) core, three thienylene or terthienylene spacers, and three 1.8-naphthalimide (NI) electron-withdrawing end-groups are explored for the first time as charge storage materials for resistor-type memory devices owing to the efficient electric charge transfer and trapping.

  13. Well-defined star-shaped donor-acceptor conjugated molecules for organic resistive memory devices.

    PubMed

    Wu, Hung-Chin; Zhang, Jicheng; Bo, Zhishan; Chen, Wen-Chang

    2015-09-28

    Solution processable star-shaped donor-acceptor (D-A) conjugated molecules (TPA-T-NI and TPA-3T-NI) with an electron-donating triphenylamine (TPA) core, three thienylene or terthienylene spacers, and three 1.8-naphthalimide (NI) electron-withdrawing end-groups are explored for the first time as charge storage materials for resistor-type memory devices owing to the efficient electric charge transfer and trapping. PMID:26255879

  14. Graphene gate electrode for MOS structure-based electronic devices.

    PubMed

    Park, Jong Kyung; Song, Seung Min; Mun, Jeong Hun; Cho, Byung Jin

    2011-12-14

    We demonstrate that the use of a monolayer graphene as a gate electrode on top of a high-κ gate dielectric eliminates mechanical-stress-induced-gate dielectric degradation, resulting in a quantum leap of gate dielectric reliability. The high work function of hole-doped graphene also helps reduce the quantum mechanical tunneling current from the gate electrode. This concept is applied to nonvolatile Flash memory devices, whose performance is critically affected by the quality of the gate dielectric. Charge-trap flash (CTF) memory with a graphene gate electrode shows superior data retention and program/erase performance that current CTF devices cannot achieve. The findings of this study can lead to new applications of graphene, not only for Flash memory devices but also for other high-performance and mass-producible electronic devices based on MOS structure which is the mainstream of the electronic device industry.

  15. INVESTIGATION OF ZrxLa1-xOy NANOCRYSTALLITES IN METAL-HIGH-k OXIDE-SILICON-TYPE NONVOLATILE MEMORY DEVICES

    NASA Astrophysics Data System (ADS)

    Bahari, Ali; Gholipur, Reza

    2012-12-01

    To investigate characterization of ZrxLa1-xOy nanocrystallites as a buffer oxide in forming the metal-oxide-semiconductor field effect transistors (MOSFETs) structure, we synthesized ZrxLa1-xOy nanocrystallites by sol-gel method. Moreover, from the solution prepared, thin films on silicon wafer substrates have been realized by "dip-coating" with a pulling out speed of 5 cm min-1. The structure, morphology, electrical properties of thin film was examined by X-ray diffraction (XRD), scanning electron microscopy (SEM), atomic force microscopy (AFM) and transmission electron microscopy (TEM) techniques. Electrical property characterization was performed with metal-oxide-semiconductor (MOS) structures through capacitance-voltage (C-V) and current density-voltage (J-V) measurements. The leakage current density was below 1.0 ×10-6A/cm2 at 1 MV/cm.

  16. Charging effect in Au nanoparticle memory device with biomolecule binding mechanism.

    PubMed

    Jung, Sung Mok; Kim, Hyung-Jun; Kim, Bong-Jin; Yoon, Tae-Sik; Kim, Yong-Sang; Lee, Hyun Ho

    2011-07-01

    Organic memory device having gold nanoparticle (Au NPs) has been introduced in the structure of metal-pentacene-insulator-silicon (MPIS) capacitor device, where the Au NPs layer was formed by a new bonding method. Biomolecule binding mechanism between streptavidin and biotin was used as a strong binding method for the formation of monolayered Au NPs on polymeric dielectric of poly vinyl alcohol (PVA). The self-assembled Au NPs was functioned to show storages of charge in the MPIS device. The binding by streptavidin and biotin was confirmed by AFM and UV-VIS. The UV-VIS absorption of the Au NPs was varied at 515 nm and 525 nm depending on the coating of streptavidin. The AFM image showed no formation of multi-stacked layers of the streptavidin-capped Au NPs on biotin-NHS layer. Capacitance-voltage (C-V) performance of the memory device was measured to investigate the charging effect from Au NPs. In addition, charge retention by the Au NPs storage was tested to show 10,000 s in the C-V curve.

  17. Physical aspects of low power synapses based on phase change memory devices

    NASA Astrophysics Data System (ADS)

    Suri, Manan; Bichler, Olivier; Querlioz, Damien; Traoré, Boubacar; Cueto, Olga; Perniola, Luca; Sousa, Veronique; Vuillaume, Dominique; Gamrat, Christian; DeSalvo, Barbara

    2012-09-01

    In this work, we demonstrate how phase change memory (PCM) devices can be used to emulate biologically inspired synaptic functions in particular, potentiation and depression, important for implementing neuromorphic hardware. PCM devices with different chalcogenide materials are fabricated and characterized. The asymmetry between the potentiation and depression behaviors of the PCM is stressed. Detailed multi-physical simulations are performed to study the underlying physics of the synaptic behavior of PCM. A versatile behavioral model and a multi-level circuit-compatible model are developed for system and circuit-level neuromorphic simulations. We propose a unique low-power methodology named the 2-PCM Synapse, to use PCM devices as synapses in large scale neuromorphic systems. To show the strength of our proposed solution, we efficiently simulated fully connected feed-forward spiking neural network capable of complex visual pattern extraction from real world data.

  18. Investigation of edge- and bulk-related resistive switching behaviors and backward-scan effects in SiOx-based resistive switching memory

    NASA Astrophysics Data System (ADS)

    Chang, Yao-Feng; Ji, Li; Wang, Yanzhen; Chen, Pai-Yu; Zhou, Fei; Xue, Fei; Fowler, Burt; Yu, Edward T.; Lee, Jack C.

    2013-11-01

    Switching characteristics of edge and bulk device structures and an unusual backward-scan effect are investigated in SiOx-based resistive memory. Adding external resistance is found to dramatically affect reset voltage, providing insight into the unique unipolar operation. Non-edge, bulk SiOx-based devices allow flexibility in the fabrication process and hydrogen incorporation improves electroforming and device yield. A backward-scan phenomenon is examined by investigating the DC and AC pulse responses, which defines requirements for ON and OFF programming duration. Circuit-level simulation using a Verilog-A model aids device characterization and programming strategy development for future nonvolatile memory applications.

  19. Analog memory and spike-timing-dependent plasticity characteristics of a nanoscale titanium oxide bilayer resistive switching device.

    PubMed

    Seo, Kyungah; Kim, Insung; Jung, Seungjae; Jo, Minseok; Park, Sangsu; Park, Jubong; Shin, Jungho; Biju, Kuyyadi P; Kong, Jaemin; Lee, Kwanghee; Lee, Byounghun; Hwang, Hyunsang

    2011-06-24

    We demonstrated analog memory, synaptic plasticity, and a spike-timing-dependent plasticity (STDP) function with a nanoscale titanium oxide bilayer resistive switching device with a simple fabrication process and good yield uniformity. We confirmed the multilevel conductance and analog memory characteristics as well as the uniformity and separated states for the accuracy of conductance change. Finally, STDP and a biological triple model were analyzed to demonstrate the potential of titanium oxide bilayer resistive switching device as synapses in neuromorphic devices. By developing a simple resistive switching device that can emulate a synaptic function, the unique characteristics of synapses in the brain, e.g. combined memory and computing in one synapse and adaptation to the outside environment, were successfully demonstrated in a solid state device. PMID:21572200

  20. Electrical Characteristics of TiO(2-x)/TiO2 Resistive Switching Memory Fabricated by Atomic Layer Deposition.

    PubMed

    Heo, Kwan-Jun; Kim, Won-You; Kim, Sung-Jin

    2016-06-01

    The rewritable low-power operated nonvolatile resistive random access memory device composed of Al(top)/TiO(2-x)/TiO2/Al(bottom) are demonstrated. The active component, the TiO2 layer of the device, is fabricated by atomic layer deposition. The oxygen vacancy TiO(2-x)/TiO2 layer annealed at 600 degrees C using rapid thermal annealing and it was proven to be in the rutile phase by X-ray diffraction analysis. The device exhibits nonvolatile memory behavior consistent with resistive switching properties, demonstrates an ON/OFF ratio of approximately 1,000:1, requires range of low voltage less than 0.4 V, and is still operational more than 120 times. PMID:27427707

  1. Organic bistable light-emitting devices

    NASA Astrophysics Data System (ADS)

    Ma, Liping; Liu, Jie; Pyo, Seungmoon; Yang, Yang

    2002-01-01

    An organic bistable device, with a unique trilayer structure consisting of organic/metal/organic sandwiched between two outmost metal electrodes, has been invented. [Y. Yang, L. P. Ma, and J. Liu, U.S. Patent Pending, U.S. 01/17206 (2001)]. When the device is biased with voltages beyond a critical value (for example 3 V), the device suddenly switches from a high-impedance state to a low-impedance state, with a difference in injection current of more than 6 orders of magnitude. When the device is switched to the low-impedance state, it remains in that state even when the power is off. (This is called "nonvolatile" phenomenon in memory devices.) The high-impedance state can be recovered by applying a reverse bias; therefore, this bistable device is ideal for memory applications. In order to increase the data read-out rate of this type of memory device, a regular polymer light-emitting diode has been integrated with the organic bistable device, such that it can be read out optically. These features make the organic bistable light-emitting device a promising candidate for several applications, such as digital memories, opto-electronic books, and recordable papers.

  2. Time-resolved analysis of the set process in an electrical phase-change memory device

    NASA Astrophysics Data System (ADS)

    Kang, Dae-Hwan; Cheong, Byung-ki; Jeong, Jeung-hyun; Lee, Taek Sung; Kim, In Ho; Kim, Won Mok; Huh, Joo-Youl

    2005-12-01

    An experimental investigation was carried out on the kinetic nature of the set process in a phase change memory device by combined analyses of set voltage wave forms and time-resolved low-field resistances. As it turned out, the progress of a set process may be measured in terms of three characteristic times in sequence i.e., threshold switching time tth, incubation time for crystallization tinc, and complete set time tset. These characteristic times are supposed to demarcate, in some measure, different stages of crystallization in the memory material during a set process. Each of these times has a strong dependence on input pulse voltage and particularly threshold switching time tth was found to have an exponentially decaying dependence. The latter may be related to the decreasing capacitance of an amorphous phase-change material with approaching threshold switching.

  3. Comparison of single event upset rates for microelectronic memory devices during interplanetary solar particle events

    NASA Technical Reports Server (NTRS)

    Mckerracher, P. L.; Kinnison, J. D.; Maurer, R. H.

    1993-01-01

    Variability in the methods and models used for single event upset calculations in microelectronic memory devices can lead to a range of possible upset rates. Using heavy ion and proton data for selected DRAM and SRAM memories, we have calculated an array of upset rates in order to compare the Adams worst case interplanetary solar flare model to a model proposed by scientists at the Jet Propulsion Laboratory. In addition, methods of upset rate calculation are compared: the Cosmic Ray Effects on Microelectronics CREME code and a Monte Carlo algorithm developed at the Applied Physics Laboratory. The results show that use of a more realistic, although still conservative, model of the space environment can have significant cost saving benefits.

  4. Enhanced non-volatile resistive switching in suspended single-crystalline ZnO nanowire with controllable multiple states

    NASA Astrophysics Data System (ADS)

    Zhang, Rui; Pang, Wei; Zhang, Qing; Chen, Yan; Chen, Xuejiao; Feng, Zhihong; Yang, Jianhua; Zhang, Daihua

    2016-08-01

    Resistive switching nanostructures are a promising candidate for next-generation non-volatile memories. In this report, we investigate the switching behaviors of single-crystalline ZnO nanowires suspended in air. They exhibit significantly higher current density, lower switching voltage, and more pronounced multiple conductance states compared to nanowires in direct contact with substrate. We attribute the effect to enhanced Joule heating efficiency, reduced surface scattering, and more significantly, the positive feedback established between the current density and local temperature in the suspended nanowires. The proposed mechanism has been quantitatively examined by finite element simulations. We have also demonstrated an innovative approach to initiating the current–temperature mutual enhancement through illumination by ultraviolet light, which further confirmed our hypothesis and enabled even greater enhancement. Our work provides further insight into the resistive switching mechanism of single-crystalline one-dimensional nanostructures, and suggests an effective means of performance enhancement and device optimization.

  5. Enhanced non-volatile resistive switching in suspended single-crystalline ZnO nanowire with controllable multiple states

    NASA Astrophysics Data System (ADS)

    Zhang, Rui; Pang, Wei; Zhang, Qing; Chen, Yan; Chen, Xuejiao; Feng, Zhihong; Yang, Jianhua; Zhang, Daihua

    2016-08-01

    Resistive switching nanostructures are a promising candidate for next-generation non-volatile memories. In this report, we investigate the switching behaviors of single-crystalline ZnO nanowires suspended in air. They exhibit significantly higher current density, lower switching voltage, and more pronounced multiple conductance states compared to nanowires in direct contact with substrate. We attribute the effect to enhanced Joule heating efficiency, reduced surface scattering, and more significantly, the positive feedback established between the current density and local temperature in the suspended nanowires. The proposed mechanism has been quantitatively examined by finite element simulations. We have also demonstrated an innovative approach to initiating the current-temperature mutual enhancement through illumination by ultraviolet light, which further confirmed our hypothesis and enabled even greater enhancement. Our work provides further insight into the resistive switching mechanism of single-crystalline one-dimensional nanostructures, and suggests an effective means of performance enhancement and device optimization.

  6. An annulus fibrosus closure device based on a biodegradable shape-memory polymer network.

    PubMed

    Sharifi, Shahriar; van Kooten, Theo G; Kranenburg, Hendrik-Jan C; Meij, Björn P; Behl, Marc; Lendlein, Andreas; Grijpma, Dirk W

    2013-11-01

    Injuries to the intervertebral disc caused by degeneration or trauma often lead to tearing of the annulus fibrosus (AF) and extrusion of the nucleus pulposus (NP). This can compress nerves and cause lower back pain. In this study, the characteristics of poly(D,L-lactide-co-trimethylene carbonate) networks with shape-memory properties have been evaluated in order to prepare biodegradable AF closure devices that can be implanted minimally invasively. Four different macromers with (D,L-lactide) to trimethylene carbonate (DLLA:TMC) molar ratios of 80:20, 70:30, 60:40 and 40:60 with terminal methacrylate groups and molecular weights of approximately 30 kg mol(-1) were used to prepare the networks by photo-crosslinking. The mechanical properties of the samples and their shape-memory properties were determined at temperatures of 0 °C and 40 °C by tensile tests- and cyclic, thermo-mechanical measurements. At 40 °C all networks showed rubber-like behavior and were flexible with elastic modulus values of 1.7-2.5 MPa, which is in the range of the modulus values of human annulus fibrosus tissue. The shape-memory characteristics of the networks were excellent with values of the shape-fixity and the shape-recovery ratio higher than 98 and 95%, respectively. The switching temperatures were between 10 and 39 °C. In vitro culture and qualitative immunocytochemistry of human annulus fibrosus cells on shape-memory films with DLLA:TMC molar ratios of 60:40 showed very good ability of the networks to support the adhesion and growth of human AF cells. When the polymer network films were coated by adsorption of fibronectin, cell attachment, cell spreading, and extracellular matrix production was further improved. Annulus fibrosus closure devices were prepared from these AF cell-compatible materials by photo-polymerizing the reactive precursors in a mold. Insertion of the multifunctional implant in the disc of a cadaveric canine spine showed that these shape-memory devices could be

  7. Inductively Heated Shape Memory Polymer for the Magnetic Actuation of Medical Devices

    SciTech Connect

    Buckley, P; Mckinley, G; Wilson, T; Small, W; Benett, W; Bearinger, J; McElfresh, M; Maitland, D

    2005-09-06

    Presently there is interest in making medical devices such as expandable stents and intravascular microactuators from shape memory polymer (SMP). One of the key challenges in realizing SMP medical devices is the implementation of a safe and effective method of thermally actuating various device geometries in vivo. A novel scheme of actuation by Curie-thermoregulated inductive heating is presented. Prototype medical devices made from SMP loaded with Nickel Zinc ferrite ferromagnetic particles were actuated in air by applying an alternating magnetic field to induce heating. Dynamic mechanical thermal analysis was performed on both the particle-loaded and neat SMP materials to assess the impact of the ferrite particles on the mechanical properties of the samples. Calorimetry was used to quantify the rate of heat generation as a function of particle size and volumetric loading of ferrite particles in the SMP. These tests demonstrated the feasibility of SMP actuation by inductive heating. Rapid and uniform heating was achieved in complex device geometries and particle loading up to 10% volume content did not interfere with the shape recovery of the SMP.

  8. Isolated nanographene crystals for nano-floating gate in charge trapping memory.

    PubMed

    Yang, Rong; Zhu, Chenxin; Meng, Jianling; Huo, Zongliang; Cheng, Meng; Liu, Donghua; Yang, Wei; Shi, Dongxia; Liu, Ming; Zhang, Guangyu

    2013-01-01

    Graphene exhibits unique electronic properties, and its low dimensionality, structural robustness, and high work-function make it very promising as the charge storage media for memory applications. Along with the development of miniaturized and scaled up devices, nanostructured graphene emerges as an ideal material candidate. Here we proposed a novel non-volatile charge trapping memory utilizing isolate and uniformly distributed nanographene crystals as nano-floating gate with controllable capacity and excellent uniformity. Nanographene charge trapping memory shows large memory window (4.5 V) at low operation voltage (±8 V), good retention (>10 years), chemical and thermal stability (1000°C), as well as tunable memory performance employing with different tunneling layers. The fabrication of such memory structure is compatible with existing semiconductor processing thus has promise on low-cost integrated nanoscale memory applications.

  9. Investigation of Hafnium oxide/Copper resistive memory for advanced encryption applications

    NASA Astrophysics Data System (ADS)

    Beland, Laurent Karim

    The Advanced Encryption Standard (AES) is a widely used encryption algorithm to protect data and communications in today's digital age. Modern AES CMOS implementations require large amounts of dedicated logic and must be tuned for either performance or power consumption. A high throughput, low power, and low die area AES implementation is required in the growing mobile sector. An emerging non-volatile memory device known as resistive memory (ReRAM) is a simple metal-insulator-metal capacitor device structure with the ability to switch between two stable resistance states. Currently, ReRAM is targeted as a non-volatile memory replacement technology to eventually replace flash. Its advantages over flash include ease of fabrication, speed, and lower power consumption. In addition to memory, ReRAM can also be used in advanced logic implementations given its purely resistive behavior. The combination of a new non-volatile memory element ReRAM along with high performance, low power CMOS opens new avenues for logic implementations. This dissertation will cover the design and process implementation of a ReRAM-CMOS hybrid circuit, built using IBM's 10LPe process, for the improvement of hardware AES implementations. Further the device characteristics of ReRAM, specifically the HfO2/Cu memory system, and mechanisms for operation are not fully correlated. Of particular interest to this work is the role of material properties such as the stoichiometry, crystallinity, and doping of the HfO2 layer and their effect on the switching characteristics of resistive memory. Material properties were varied by a combination of atomic layer deposition and reactive sputtering of the HfO2 layer. Several studies will be discussed on how the above mentioned material properties influence switching parameters, and change the underlying physics of device operation.

  10. Memory

    MedlinePlus

    ... it has to decide what is worth remembering. Memory is the process of storing and then remembering this information. There are different types of memory. Short-term memory stores information for a few ...

  11. Precessional reversal in orthogonal spin transfer magnetic random access memory devices

    NASA Astrophysics Data System (ADS)

    Liu, H.; Bedau, D.; Backes, D.; Katine, J. A.; Kent, A. D.

    2012-07-01

    Single-shot time-resolved resistance measurements have been used to determine the magnetization reversal mechanisms of orthogonal spin transfer magnetic random access memory (OST-MRAM) devices at nanosecond time scales. There is a strong asymmetry between antiparallel (AP) to parallel (P) and P to AP transitions under the same pulse conditions. P to AP transitions are shown to occur by precession of the free layer magnetization, while the AP to P transition is typically direct, occurring in less than 200 ps. We associate the asymmetry with spin torques perpendicular to the plane of the free layer, an important characteristic of OST-MRAM bit cells that can be used to optimize device performance.

  12. Stretchable carbon nanotube charge-trap floating-gate memory and logic devices for wearable electronics.

    PubMed

    Son, Donghee; Koo, Ja Hoon; Song, Jun-Kyul; Kim, Jaemin; Lee, Mincheol; Shim, Hyung Joon; Park, Minjoon; Lee, Minbaek; Kim, Ji Hoon; Kim, Dae-Hyeong

    2015-05-26

    Electronics for wearable applications require soft, flexible, and stretchable materials and designs to overcome the mechanical mismatch between the human body and devices. A key requirement for such wearable electronics is reliable operation with high performance and robustness during various deformations induced by motions. Here, we present materials and device design strategies for the core elements of wearable electronics, such as transistors, charge-trap floating-gate memory units, and various logic gates, with stretchable form factors. The use of semiconducting carbon nanotube networks designed for integration with charge traps and ultrathin dielectric layers meets the performance requirements as well as reliability, proven by detailed material and electrical characterizations using statistics. Serpentine interconnections and neutral mechanical plane layouts further enhance the deformability required for skin-based systems. Repetitive stretching tests and studies in mechanics corroborate the validity of the current approaches.

  13. The role of the inserted layer in resistive random access memory device

    NASA Astrophysics Data System (ADS)

    Zhang, Dainan; Ma, Guokun; Zhang, Huaiwu; Tang, Xiaoli; Zhong, Zhiyong; Jie, Li; Su, Hua

    2016-07-01

    NiO resistive switching devices were fabricated by reactive DC magnetron sputtering at room temperature containing different inserted layers. From measurements, we demonstrated the filaments were made up by metal Co rather than the oxygen defect or other metal. A current jumping phenomenon in the SET process was observed, evidencing that the filament generating procedure was changed due to the inserted layers. In this process, we demonstrate the current jumping appeared in higher voltage region when the position of inserted layer was close to the bottom electrode. The I-V curves shifted to the positive direction as the thickness of inserted layer increasing. With the change of the number of inserted layers, SET voltages varied while the RESET voltage kept stable. According to the electrochemical metallization memory mechanism, detailed explanations on all the phenomena were addressed. This discovery is supposed of great potentials in the use of designing multi-layer RRAM devices.

  14. Chemical insight into origin of forming-free resistive random-access memory devices

    NASA Astrophysics Data System (ADS)

    Wu, X.; Fang, Z.; Li, K.; Bosman, M.; Raghavan, N.; Li, X.; Yu, H. Y.; Singh, N.; Lo, G. Q.; Zhang, X. X.; Pey, K. L.

    2011-09-01

    We demonstrate the realization of a forming-step free resistive random access memory (RRAM) device using a HfOx/TiOx/HfOx/TiOx multilayer structure, as a replacement for the conventional HfOx-based single layer structure. High-resolution transmission electron microscopy (HRTEM), along with electron energy loss spectroscopy (EELS) analysis has been carried out to identify the distribution and the role played by Ti in the RRAM stack. Our results show that Ti out-diffusion into the HfOx layer is the chemical cause of forming-free behavior. Moreover, the capability of Ti to change its ionic state in HfOx eases the reduction-oxidation (redox) reaction, thus lead to the RRAM devices performance improvements.

  15. Memory characteristics of flexible resistive switching devices with triangular-shaped silicon nanowire bottom electrodes

    NASA Astrophysics Data System (ADS)

    Park, Sukhyung; Cho, Kyoungah; Kim, Sangsig

    2015-05-01

    In this paper, we demonstrate the bipolar resistive switching characteristics of flexible resistive random access memory (ReRAM) devices, whose bottom electrodes are made of silicon nanowires (Si NWs) with a triangular structure, which offer preferential sites for the filaments. The temperature dependence of the low resistance state (LRS) of the resistive Al2O3/ZnO bilayers of ReRAM devices reveals that Ag filaments originating from the top Ag electrodes are responsible for bipolar resistive switching. With respect to the endurance characteristics of the LRS, resistance fluctuation is negligible because of the filaments generated at the specific sites of the vertices of the Si NW bottom electrodes. In addition, the resistive switching characteristics are maintained even after 1000 bending cycles.

  16. Metal oxide-resistive memory using graphene-edge electrodes

    NASA Astrophysics Data System (ADS)

    Lee, Seunghyun; Sohn, Joon; Jiang, Zizhen; Chen, Hong-Yu; Philip Wong, H.-S.

    2015-09-01

    The emerging paradigm of `abundant-data' computing requires real-time analytics on enormous quantities of data collected by a mushrooming network of sensors. Todays computing technology, however, cannot scale to satisfy such big data applications with the required throughput and energy efficiency. The next technology frontier will be monolithically integrated chips with three-dimensionally interleaved memory and logic for unprecedented data bandwidth with reduced energy consumption. In this work, we exploit the atomically thin nature of the graphene edge to assemble a resistive memory (~3 Å thick) stacked in a vertical three-dimensional structure. We report some of the lowest power and energy consumption among the emerging non-volatile memories due to an extremely thin electrode with unique properties, low programming voltages, and low current. Circuit analysis of the three-dimensional architecture using experimentally measured device properties show higher storage potential for graphene devices compared that of metal based devices.

  17. Metal oxide-resistive memory using graphene-edge electrodes.

    PubMed

    Lee, Seunghyun; Sohn, Joon; Jiang, Zizhen; Chen, Hong-Yu; Philip Wong, H-S

    2015-01-01

    The emerging paradigm of 'abundant-data' computing requires real-time analytics on enormous quantities of data collected by a mushrooming network of sensors. Todays computing technology, however, cannot scale to satisfy such big data applications with the required throughput and energy efficiency. The next technology frontier will be monolithically integrated chips with three-dimensionally interleaved memory and logic for unprecedented data bandwidth with reduced energy consumption. In this work, we exploit the atomically thin nature of the graphene edge to assemble a resistive memory (∼ 3 Å thick) stacked in a vertical three-dimensional structure. We report some of the lowest power and energy consumption among the emerging non-volatile memories due to an extremely thin electrode with unique properties, low programming voltages, and low current. Circuit analysis of the three-dimensional architecture using experimentally measured device properties show higher storage potential for graphene devices compared that of metal based devices.

  18. Ultralow-power switching via defect engineering in germanium telluride phase-change memory devices

    PubMed Central

    Nukala, Pavan; Lin, Chia-Chun; Composto, Russell; Agarwal, Ritesh

    2016-01-01

    Crystal–amorphous transformation achieved via the melt-quench pathway in phase-change memory involves fundamentally inefficient energy conversion events; and this translates to large switching current densities, responsible for chemical segregation and device degradation. Alternatively, introducing defects in the crystalline phase can engineer carrier localization effects enhancing carrier–lattice coupling; and this can efficiently extract work required to introduce bond distortions necessary for amorphization from input electrical energy. Here, by pre-inducing extended defects and thus carrier localization effects in crystalline GeTe via high-energy ion irradiation, we show tremendous improvement in amorphization current densities (0.13–0.6 MA cm−2) compared with the melt-quench strategy (∼50 MA cm−2). We show scaling behaviour and good reversibility on these devices, and explore several intermediate resistance states that are accessible during both amorphization and recrystallization pathways. Existence of multiple resistance states, along with ultralow-power switching and scaling capabilities, makes this approach promising in context of low-power memory and neuromorphic computation. PMID:26805748

  19. Ultralow-power switching via defect engineering in germanium telluride phase-change memory devices

    NASA Astrophysics Data System (ADS)

    Nukala, Pavan; Lin, Chia-Chun; Composto, Russell; Agarwal, Ritesh

    2016-01-01

    Crystal-amorphous transformation achieved via the melt-quench pathway in phase-change memory involves fundamentally inefficient energy conversion events; and this translates to large switching current densities, responsible for chemical segregation and device degradation. Alternatively, introducing defects in the crystalline phase can engineer carrier localization effects enhancing carrier-lattice coupling; and this can efficiently extract work required to introduce bond distortions necessary for amorphization from input electrical energy. Here, by pre-inducing extended defects and thus carrier localization effects in crystalline GeTe via high-energy ion irradiation, we show tremendous improvement in amorphization current densities (0.13-0.6 MA cm-2) compared with the melt-quench strategy (~50 MA cm-2). We show scaling behaviour and good reversibility on these devices, and explore several intermediate resistance states that are accessible during both amorphization and recrystallization pathways. Existence of multiple resistance states, along with ultralow-power switching and scaling capabilities, makes this approach promising in context of low-power memory and neuromorphic computation.

  20. Unusual magnetic behavior in a chiral-based magnetic memory device

    NASA Astrophysics Data System (ADS)

    Ben-Dor, Oren; Yochelis, Shira; Felner, Israel; Paltiel, Yossi

    2016-01-01

    In recent years chiral molecules were found to act as efficient spin filters. Using a multilayer structure with chiral molecules magnetic memory was realized. Observed rare magnetic phenomena in a chiral-based magnetic memory device was reported by O-Ben Dor et. al in Nature Commun, 4, 2256 (2013). This multi-layered device is built from α-helix L-polyalanine (AHPA-L) adsorbed on gold, Al2O3 (7 nm) and Ni (30 nm) layers. It was shown that certain temperature range the FC branch crosses the magnetic peak (at 55 K) observed in the ZFC curve thus ZFC>FC. We show here that in another similar multi-layered material, at low applied field, the ZFC curve lies above the FC one up to 70 K. The two features have the same origin and the crucial necessary components to exhibit them are: AHPA-L and 30 nm Ni layered thick. Similar effects were also reported in sulfur doped amorphous carbon. A comparison between the two systems and the ingredients for these peculiar observations is discussed.

  1. Scalability of valence change memory: From devices to tip-induced filaments

    NASA Astrophysics Data System (ADS)

    Celano, U.; Fantini, A.; Degraeve, R.; Jurczak, M.; Goux, L.; Vandervorst, W.

    2016-08-01

    Since the early days of the investigation on resistive switching (RS), the independence of the ON-state resistance with actual cell area has been a trademark of filamentary-switching. However, with the continuous downscaling of the memory cell down to 10 x 10 nm2 and below, the persistence of this phenomena raises intriguing questions on the conductive filaments (CFs) and its dimensions. Particularly, the cell functionality demonstrated at relatively high switching current (> 100 μA) implies a high current density (> 106 A/cm2) inside a CF supposedly confined in few hundreds on nm3. We previously demonstrated a methodology for the direct observation of CFs in integrated devices namely scalpel SPM, which overcomes most of the characterization challenges imposed by the device structure and the small CF lateral dimensions. In this letter, we use scalpel SPM to clarify the scaling potential of HfO2-based valence change memory (VCM) by characterization of CFs programmed at relatively high switching current and by AFM tip-induced RS experiments. Besides the demonstration of a remarkable scaling potential for the VCM technology, our results are also used to clarify the present understanding on the AFM-based experiments.

  2. Inadvertently programmed bits in Samsung 128 Mbit flash devices: a flaky investigation

    NASA Technical Reports Server (NTRS)

    Swift, G.

    2002-01-01

    JPL's X2000 avionics design pioneers new territory by specifying a non-volatile memory (NVM) board based on flash memories. The Samsung 128Mb device chosen was found to demonstrate bit errors (mostly program disturbs) and block-erase failures that increase with cycling. Low temperature, certain pseudo- random patterns, and, probably, higher bias increase the observable bit errors. An experiment was conducted to determine the wearout dependence of the bit errors to 100k cycles at cold temperature using flight-lot devices (some pre-irradiated). The results show an exponential growth rate, a wide part-to-part variation, and some annealing behavior.

  3. Impacts of Ion Irradiation on Hafnium oxide-based Resistive Random Access Memory Devices

    NASA Astrophysics Data System (ADS)

    He, Xiaoli

    The impacts of ion irradiation on so-called vacancy-change mechanism (VCM) and electrochemical-metallization mechanism (ECM) ReRAM devices based on HfO2 are investigated using various ion sources: H + (1 MeV), He+ (1 MeV), N+ (1 MeV), Ne+ (1.6 MeV) and Ar+ (2.75 MeV) over a range of total doses (105 -- 1011 rad(Si)) and fluences (1012 -- 1015 cm-2). VCM-ReRAM devices show robust resistive switching function after all irradiation experiments. VCM resistive switching parameters including set voltage (V set), reset voltage (Vreset), on-state resistance (R on) and off-state resistance (Roff) exhibited, in most cases, modest changes after irradiation. Decreases in forming voltage (Vf) and initial resistance (Rfresh) of fresh devices were observed after all irradiation experiments on VCM-ReRAM devices with the exception of Ar+ irradiation at the highest fluence (10 15 cm-2). In that case Rfresh increased by an order of magnitude. For VCM-ReRAM devices it was also observed that irradiation beyond a dose threshold of approximately 5 Grad(Si) could induce off-to-on state transition events. This behavior could lead to errors in a VCM-ReRAM memory system. ECM-ReRAM devices (based on HfO2) were also subjected to ion irradiation. Under proton irradiation ECM-ReRAM devices remained functional, but with relatively large positive variations (20-40%) in Vset, Vreset and Ron and large negative variations (˜ -60%) in Roff. In contrast to VCM HfO2-ReRAMs, ECM-based devices exhibited increased V f after irradiation, and no off-to-on transitions were observed. Interestingly, for ECM-ReRAM devices, high-fluence Ar irradiation resulted in a transition of the electrical conduction mechanism associated with the conductive filament forming process from a Poole-Frenkel conduction mechanism (pre-irradiation) to ionic conduction (post-Ar irradiation). ECM-ReRAM devices irradiated with lighter ions did not exhibit this effect. The different ion irradiation responses of the two types of HfO2-Re

  4. Nonvolatile, reversible electric-field controlled switching of remanent magnetization in multifunctional ferromagnetic/ferroelectric hybrids

    NASA Astrophysics Data System (ADS)

    Brandlmaier, A.; Geprägs, S.; Woltersdorf, G.; Gross, R.; Goennenwein, S. T. B.

    2011-08-01

    In spin-mechanics, the magnetoelastic coupling in ferromagnetic/ferroelectric hybrid devices is exploited in order to realize an electric-voltage control of magnetization orientation. To this end, different voltage-induced elastic strain states are used to generate different magnetization orientations. In our approach, we take advantage of the hysteretic expansion and contraction of a commercial piezoelectric actuator as a function of electrical voltage to deterministically select one of two electro-remanent elastic strain states. We investigate the resulting magnetic response in a nickel thin film/piezoelectric actuator hybrid device at room temperature, using simultaneous magneto-optical Kerr effect and magnetotransport measurements. The magnetic properties of the hybrid can be consistently described in a macrospin model, i.e., in terms of a single magnetic domain. At zero external magnetic field, the magnetization orientation in the two electro-remanent strain states differs by 15°, which corresponds to a magnetoresistance change of 0.5%. These results demonstrate that the spin-mechanics scheme indeed enables a nonvolatile electrically read- and writable memory bit where the information is encoded in a magnetic property.

  5. Non-volatile resistive photo-switches for flexible image detector arrays

    NASA Astrophysics Data System (ADS)

    Nau, Sebastian; Wolf, Christoph; Sax, Stefan; List-Kratochvil, Emil J. W.

    2015-09-01

    The increasing quest to find lightweight, conformable or flexible image detectors for machine vision or medical imaging brings organic electronics into the spotlight for these fields of application. Here were we introduce a unique imaging device concept and its utilization in an organic, flexible detector array with simple passive matrix wiring. We present a flexible organic image detector array built up from non-volatile resistive multi-bit photo-switchable elements. This unique realization is based on an organic photodiode combined with an organic resistive memory device wired in a simple crossbar configuration. The presented concept exhibits significant advantages compared to present organic and inorganic detector array technologies, facilitating the detection and simultaneous storage of the image information in one detector pixel, yet also allowing for simple read-out of the information from a simple passive-matrix crossbar wiring. This concept is demonstrated for single photo-switchable pixels as well as for arrays with sizes up to 32 by 32 pixels (1024 bit). The presented results pave the way for a versatile flexible and easy-to-fabricate sensor array technology. In a final step, the concept was expanded to detection of x-rays.

  6. Memory.

    ERIC Educational Resources Information Center

    McKean, Kevin

    1983-01-01

    Discusses current research (including that involving amnesiacs and snails) into the nature of the memory process, differentiating between and providing examples of "fact" memory and "skill" memory. Suggests that three brain parts (thalamus, fornix, mammilary body) are involved in the memory process. (JN)

  7. Evidence of Filamentary Switching in Oxide-based Memory Devices via Weak Programming and Retention Failure Analysis.

    PubMed

    Younis, Adnan; Chu, Dewei; Li, Sean

    2015-01-01

    Further progress in high-performance microelectronic devices relies on the development of novel materials and device architectures. However, the components and designs that are currently in use have reached their physical limits. Intensive research efforts, ranging from device fabrication to performance evaluation, are required to surmount these limitations. In this paper, we demonstrate that the superior bipolar resistive switching characteristics of a CeO2:Gd-based memory device can be manipulated by means of UV radiation, serving as a new degree of freedom. Furthermore, the metal oxide-based (CeO2:Gd) memory device was found to possess electrical and neuromorphic multifunctionalities. To investigate the underlying switching mechanism of the device, its plasticity behaviour was studied by imposing weak programming conditions. In addition, a short-term to long-term memory transition analogous to the forgetting process in the human brain, which is regarded as a key biological synaptic function for information processing and data storage, was realized. Based on a careful examination of the device's retention behaviour at elevated temperatures, the filamentary nature of switching in such devices can be understood from a new perspective. PMID:26324073

  8. CMOS Interface Circuits for Spin Tunneling Junction Based Magnetic Random Access Memories

    SciTech Connect

    Ganesh Saripalli

    2002-12-31

    Magneto resistive memories (MRAM) are non-volatile memories which use magnetic instead of electrical structures to store data. These memories, apart from being non-volatile, offer a possibility to achieve densities better than DRAMs and speeds faster than SRAMs. MRAMs could potentially replace all computer memory RAM technologies in use today, leading to future applications like instan-on computers and longer battery life for pervasive devices. Such rapid development was made possible due to the recent discovery of large magnetoresistance in Spin tunneling junction devices. Spin tunneling junctions (STJ) are composite structures consisting of a thin insulating layer sandwiched between two magnetic layers. This thesis research is targeted towards these spin tunneling junction based Magnetic memories. In any memory, some kind of an interface circuit is needed to read the logic states. In this thesis, four such circuits are proposed and designed for Magnetic memories (MRAM). These circuits interface to the Spin tunneling junctions and act as sense amplifiers to read their magnetic states. The physical structure and functional characteristics of these circuits are discussed in this thesis. Mismatch effects on the circuits and proper design techniques are also presented. To demonstrate the functionality of these interface structures, test circuits were designed and fabricated in TSMC 0.35{micro} CMOS process. Also circuits to characterize the process mismatches were fabricated and tested. These results were then used in Matlab programs to aid in design process and to predict interface circuit's yields.

  9. Electron Transport in Silicon Nanocrystal Devices: From Memory Applications to Silicon Photonics

    NASA Astrophysics Data System (ADS)

    Miller, Gerald M.

    The push to integrate the realms of microelectronics and photonics on the silicon platform is currently lacking an efficient, electrically pumped silicon light source. One promising material system for photonics on the silicon platform is erbium-doped silicon nanoclusters (Er:Si-nc), which uses silicon nanoclusters to sensitize erbium ions in a SiO2 matrix. This medium can be pumped electrically, and this thesis focuses primarily on the electrical properties of Er:Si-nc films and their possible development as a silicon light source in the erbium emission band around 1.5 micrometers. Silicon nanocrystals can also be used as the floating gate in a flash memory device, and work is also presented examining charge transport in novel systems for flash memory applications. To explore silicon nanocrystals as a potential replacement for metallic floating gates in flash memory, the charging dynamics in silicon nanocrystal films are first studied using UHV-AFM. This approach uses a non-contact AFM tip to locally charge a layer of nanocrystals. Subsequent imaging allows the injected charge to be observed in real time as it moves through the layer. Simulation of this interaction allows the quantication of the charge in the layer, where we find that each nanocrystal is only singly charged after injection, while holes are retained in the film for hours. Work towards developing a dielectric stack with a voltage-tunable barrier is presented, with applications for flash memory and hyperspectral imaging. For hyperspectral imaging applications, film stacks containing various dielectrics are studied using I-V, TEM, and internal photoemission, with barrier tunability demonstrated in the Sc2O3/SiO2 system. To study Er:Si-nc as a potential lasing medium for silicon photonics, a theoretical approach is presented where Er:Si-nc is the gain medium in a silicon slot waveguide. By accounting for the local density of optical states effect on the emitters, and carrier absorption due to

  10. Design of Logic Module Based on Magnetic-Tunnel-Junction Elements for Nonvolatile Field-Programmable Gate Array

    NASA Astrophysics Data System (ADS)

    Lee, Hyunjoo; Kim, Sojeong; Lee, Seungyeon; Lee, Seungjun; Shin, Hyungsoon

    2009-04-01

    Magnetologic using a magnetic-tunnel-junction (MTJ) element is a very hopeful candidate for universal logic technology because it can be used to build both logic circuits and nonvolatile memories. A structure of single-layer (SL) MTJ with a novel current driver previously presented by the authors improved both functional flexibility and uniformity of magnetologic. In this paper, the design of a nonvolatile logic module using SL MTJ is presented, which can be used as a basic logic cell for nonvolatile field-programmable gate arrays (FPGAs). The S-module is a basic logic cell for Act3 family of FPGAs by Actel, which can implement arbitrary five-input logic functions. We designed an S-module using SL MTJ elements such that it can work as a programmable logic module with nonvolatility. The functional verification has been carried out by HSPICE simulator on the basis of a macro-model of SL MTJ.

  11. (Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

    DOE PAGESBeta

    Gao, X.; Mamaluy, D.; Cyr, E. C.; Marinella, M. J.

    2016-05-10

    As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

  12. GA-based optimum design of a shape memory alloy device for seismic response mitigation

    NASA Astrophysics Data System (ADS)

    Ozbulut, O. E.; Roschke, P. N.; Y Lin, P.; Loh, C. H.

    2010-06-01

    Damping systems discussed in this work are optimized so that a three-story steel frame structure and its shape memory alloy (SMA) bracing system minimize response metrics due to a custom-tailored earthquake excitation. Multiple-objective numerical optimization that simultaneously minimizes displacements and accelerations of the structure is carried out with a genetic algorithm (GA) in order to optimize SMA bracing elements within the structure. After design of an optimal SMA damping system is complete, full-scale experimental shake table tests are conducted on a large-scale steel frame that is equipped with the optimal SMA devices. A fuzzy inference system is developed from data collected during the testing to simulate the dynamic material response of the SMA bracing subcomponents. Finally, nonlinear analyses of a three-story braced frame are carried out to evaluate the performance of comparable SMA and commonly used steel braces under dynamic loading conditions and to assess the effectiveness of GA-optimized SMA bracing design as compared to alternative designs of SMA braces. It is shown that peak displacement of a structure can be reduced without causing significant acceleration response amplification through a judicious selection of physical characteristics of the SMA devices. Also, SMA devices provide a recentering mechanism for the structure to return to its original position after a seismic event.

  13. Bipolar switching in chalcogenide phase change memory

    PubMed Central

    Ciocchini, N.; Laudato, M.; Boniardi, M.; Varesi, E.; Fantini, P.; Lacaita, A. L.; Ielmini, D.

    2016-01-01

    Phase change materials based on chalcogenides are key enabling technologies for optical storage, such as rewritable CD and DVD, and recently also electrical nonvolatile memory, named phase change memory (PCM). In a PCM, the amorphous or crystalline phase affects the material band structure, hence the device resistance. Although phase transformation is extremely fast and repeatable, the amorphous phase suffers structural relaxation and crystallization at relatively low temperatures, which may affect the temperature stability of PCM state. To improve the time/temperature stability of the PCM, novel operation modes of the device should be identified. Here, we present bipolar switching operation of PCM, which is interpreted by ion migration in the solid state induced by elevated temperature and electric field similar to the bipolar switching in metal oxides. The temperature stability of the high resistance state is demonstrated and explained based on the local depletion of chemical species from the electrode region. PMID:27377822

  14. Bipolar switching in chalcogenide phase change memory.

    PubMed

    Ciocchini, N; Laudato, M; Boniardi, M; Varesi, E; Fantini, P; Lacaita, A L; Ielmini, D

    2016-01-01

    Phase change materials based on chalcogenides are key enabling technologies for optical storage, such as rewritable CD and DVD, and recently also electrical nonvolatile memory, named phase change memory (PCM). In a PCM, the amorphous or crystalline phase affects the material band structure, hence the device resistance. Although phase transformation is extremely fast and repeatable, the amorphous phase suffers structural relaxation and crystallization at relatively low temperatures, which may affect the temperature stability of PCM state. To improve the time/temperature stability of the PCM, novel operation modes of the device should be identified. Here, we present bipolar switching operation of PCM, which is interpreted by ion migration in the solid state induced by elevated temperature and electric field similar to the bipolar switching in metal oxides. The temperature stability of the high resistance state is demonstrated and explained based on the local depletion of chemical species from the electrode region. PMID:27377822

  15. Bipolar switching in chalcogenide phase change memory

    NASA Astrophysics Data System (ADS)

    Ciocchini, N.; Laudato, M.; Boniardi, M.; Varesi, E.; Fantini, P.; Lacaita, A. L.; Ielmini, D.

    2016-07-01

    Phase change materials based on chalcogenides are key enabling technologies for optical storage, such as rewritable CD and DVD, and recently also electrical nonvolatile memory, named phase change memory (PCM). In a PCM, the amorphous or crystalline phase affects the material band structure, hence the device resistance. Although phase transformation is extremely fast and repeatable, the amorphous phase suffers structural relaxation and crystallization at relatively low temperatures, which may affect the temperature stability of PCM state. To improve the time/temperature stability of the PCM, novel operation modes of the device should be identified. Here, we present bipolar switching operation of PCM, which is interpreted by ion migration in the solid state induced by elevated temperature and electric field similar to the bipolar switching in metal oxides. The temperature stability of the high resistance state is demonstrated and explained based on the local depletion of chemical species from the electrode region.

  16. Evidence of Filamentary Switching in Oxide-based Memory Devices via Weak Programming and Retention Failure Analysis

    PubMed Central

    Younis, Adnan; Chu, Dewei; Li, Sean

    2015-01-01

    Further progress in high-performance microelectronic devices relies on the development of novel materials and device architectures. However, the components and designs that are currently in use have reached their physical limits. Intensive research efforts, ranging from device fabrication to performance evaluation, are required to surmount these limitations. In this paper, we demonstrate that the superior bipolar resistive switching characteristics of a CeO2:Gd-based memory device can be manipulated by means of UV radiation, serving as a new degree of freedom. Furthermore, the metal oxide-based (CeO2:Gd) memory device was found to possess electrical and neuromorphic multifunctionalities. To investigate the underlying switching mechanism of the device, its plasticity behaviour was studied by imposing weak programming conditions. In addition, a short-term to long-term memory transition analogous to the forgetting process in the human brain, which is regarded as a key biological synaptic function for information processing and data storage, was realized. Based on a careful examination of the device’s retention behaviour at elevated temperatures, the filamentary nature of switching in such devices can be understood from a new perspective. PMID:26324073

  17. Evidence of Filamentary Switching in Oxide-based Memory Devices via Weak Programming and Retention Failure Analysis

    NASA Astrophysics Data System (ADS)

    Younis, Adnan; Chu, Dewei; Li, Sean

    2015-09-01

    Further progress in high-performance microelectronic devices relies on the development of novel materials and device architectures. However, the components and designs that are currently in use have reached their physical limits. Intensive research efforts, ranging from device fabrication to performance evaluation, are required to surmount these limitations. In this paper, we demonstrate that the superior bipolar resistive switching characteristics of a CeO2:Gd-based memory device can be manipulated by means of UV radiation, serving as a new degree of freedom. Furthermore, the metal oxide-based (CeO2:Gd) memory device was found to possess electrical and neuromorphic multifunctionalities. To investigate the underlying switching mechanism of the device, its plasticity behaviour was studied by imposing weak programming conditions. In addition, a short-term to long-term memory transition analogous to the forgetting process in the human brain, which is regarded as a key biological synaptic function for information processing and data storage, was realized. Based on a careful examination of the device’s retention behaviour at elevated temperatures, the filamentary nature of switching in such devices can be understood from a new perspective.

  18. Diode-less bilayer oxide (WO(x)-NbO(x)) device for cross-point resistive memory applications.

    PubMed

    Liu, Xinjun; Sadaf, Sharif Md; Son, Myungwoo; Shin, Jungho; Park, Jubong; Lee, Joonmyoung; Park, Sangsu; Hwang, Hyunsang

    2011-11-25

    The combination of a threshold switching device and a resistive switching (RS) device was proposed to suppress the undesired sneak current for the integration of bipolar RS cells in a cross-point array type memory. A simulation for this hybrid-type device shows that the matching of key parameters between switch element and memory element is an important issue. Based on the threshold switching oxides, a conceptual structure with a simple metal-oxide 1-oxide 2-metal stack was provided to accommodate the evolution trend. We show that electroformed W-NbO(x)-Pt devices can simultaneously exhibit both threshold switching and memory switching. A qualitative model was suggested to elucidate the unique properties in a W-NbO(x)-Pt stack, where threshold switching is associated with a localized metal-insulator transition in the NbO(x) bulk, and the bipolar RS derives from a redox at the tip of the localized filament at the WO(x)-NbO(x) interface. Such a simple metal-oxide-metal structure, with functionally separated bulk and interface effects, provides a fabrication advantage for future high-density cross-point memory devices.

  19. Wavelet analysis and HHG in nanorings: their applications in logic gates and memory mass devices

    NASA Astrophysics Data System (ADS)

    Cricchio, Dario; Fiordilino, Emilio

    2016-01-01

    We study the application of one nanoring driven by a laser field in different states of polarization in logic circuits. In particular we show that assigning Boolean values to different states of the incident laser field and to the emitted signals, we can create logic gates such as OR, XOR and AND. We also show the possibility of making logic circuits such as half-adder and full-adder using one and two nanorings respectively. Using two nanorings we made the Toffoli gate. Finally we use the final angular momentum acquired by the electron to store information and hence show the possibility of using an array of nanorings as a mass memory device.

  20. Ultra-low power, highly uniform polymer memory by inserted multilayer graphene electrode

    NASA Astrophysics Data System (ADS)

    Jang, Byung Chul; Seong, Hyejeong; Kim, Jong Yun; Koo, Beom Jun; Kim, Sung Kyu; Yang, Sang Yoon; Gap Im, Sung; Choi, Sung-Yool

    2015-12-01

    Filament type resistive random access memory (RRAM) based on polymer thin films is a promising device for next generation, flexible nonvolatile memory. However, the resistive switching nonuniformity and the high power consumption found in the general filament type RRAM devices present critical issues for practical memory applications. Here, we introduce a novel approach not only to reduce the power consumption but also to improve the resistive switching uniformity in RRAM devices based on poly(1,3,5-trimethyl-3,4,5-trivinyl cyclotrisiloxane) by inserting multilayer graphene (MLG) at the electrode/polymer interface. The resistive switching uniformity was thereby significantly improved, and the power consumption was markedly reduced by 250 times. Furthermore, the inserted MLG film enabled a transition of the resistive switching operation from unipolar resistive switching to bipolar resistive switching and induced self-compliance behavior. The findings of this study can pave the way toward a new area of application for graphene in electronic devices.