Distributed Micro-Processor Applications to Guidance and Control Systems.

DTIC Science & Technology

1982-07-01

nanoseconds compared with 22 milliseconds for the older type of NMOS non-volatile RAM. This non-volatile RAM is estimated to hold its memory for 100 years...illustrated in figure 1.4.3.3 and compared with the traditional permalog chevron bubble structure. The contiguous element bubble structure is being developed ...M for its 8086 based Digital Advanced Avionics System (DAAS) developed for NASA Ames, but rejected it as being unsuitable. Ada is the new DoD

Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

NASA Astrophysics Data System (ADS)

Riente, Fabrizio; Ziemys, Grazvydas; Mattersdorfer, Clemens; Boche, Silke; Turvani, Giovanna; Raberg, Wolfgang; Luber, Sebastian; Breitkreutz-v. Gamm, Stephan

2017-05-01

Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML) is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

Non-volatile magnetic random access memory

NASA Technical Reports Server (NTRS)

Katti, Romney R. (Inventor); Stadler, Henry L. (Inventor); Wu, Jiin-Chuan (Inventor)

1994-01-01

Improvements are made in a non-volatile magnetic random access memory. Such a memory is comprised of an array of unit cells, each having a Hall-effect sensor and a thin-film magnetic element made of material having an in-plane, uniaxial anisotropy and in-plane, bipolar remanent magnetization states. The Hall-effect sensor is made more sensitive by using a 1 m thick molecular beam epitaxy grown InAs layer on a silicon substrate by employing a GaAs/AlGaAs/InAlAs superlattice buffering layer. One improvement avoids current shunting problems of matrix architecture. Another improvement reduces the required magnetizing current for the micromagnets. Another improvement relates to the use of GaAs technology wherein high electron-mobility GaAs MESFETs provide faster switching times. Still another improvement relates to a method for configuring the invention as a three-dimensional random access memory.

On-chip photonic memory elements employing phase-change materials.

PubMed

Rios, Carlos; Hosseini, Peiman; Wright, C David; Bhaskaran, Harish; Pernice, Wolfram H P

2014-03-05

Phase-change materials integrated into nanophotonic circuits provide a flexible way to realize tunable optical components. Relying on the enormous refractive-index contrast between the amorphous and crystalline states, such materials are promising candidates for on-chip photonic memories. Nonvolatile memory operation employing arrays of microring resonators is demonstrated as a route toward all-photonic chipscale information processing. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Securing non-volatile memory regions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Faraboschi, Paolo; Ranganathan, Parthasarathy; Muralimanohar, Naveen

Methods, apparatus and articles of manufacture to secure non-volatile memory regions are disclosed. An example method disclosed herein comprises associating a first key pair and a second key pair different than the first key pair with a process, using the first key pair to secure a first region of a non-volatile memory for the process, and using the second key pair to secure a second region of the non-volatile memory for the same process, the second region being different than the first region.

Ferroelectric Memory Devices and a Proposed Standardized Test System Design

DTIC Science & Technology

1992-06-01

positive clock transition. This provides automatic data protection in case of power loss. The device is being evaluated for applications such as automobile ...systems requiring nonvolatile memory and as these systems become more complex, the demand for reprogrammable nonvolatile memory increases. The...complexity and cost in making conventional nonvolatile memory reprogrammable also increases, so the potential for using ferroelectric memory as a replacement

An associative capacitive network based on nanoscale complementary resistive switches for memory-intensive computing

NASA Astrophysics Data System (ADS)

Kavehei, Omid; Linn, Eike; Nielen, Lutz; Tappertzhofen, Stefan; Skafidas, Efstratios; Valov, Ilia; Waser, Rainer

2013-05-01

We report on the implementation of an Associative Capacitive Network (ACN) based on the nondestructive capacitive readout of two Complementary Resistive Switches (2-CRSs). ACNs are capable of performing a fully parallel search for Hamming distances (i.e. similarity) between input and stored templates. Unlike conventional associative memories where charge retention is a key function and hence, they require frequent refresh cycles, in ACNs, information is retained in a nonvolatile resistive state and normal tasks are carried out through capacitive coupling between input and output nodes. Each device consists of two CRS cells and no selective element is needed, therefore, CMOS circuitry is only required in the periphery, for addressing and read-out. Highly parallel processing, nonvolatility, wide interconnectivity and low-energy consumption are significant advantages of ACNs over conventional and emerging associative memories. These characteristics make ACNs one of the promising candidates for applications in memory-intensive and cognitive computing, switches and routers as binary and ternary Content Addressable Memories (CAMs) and intelligent data processing.

Semiconductor diode with external field modulation

DOEpatents

Nasby, Robert D.

2000-01-01

A non-destructive-readout nonvolatile semiconductor diode switching device that may be used as a memory element is disclosed. The diode switching device is formed with a ferroelectric material disposed above a rectifying junction to control the conduction characteristics therein by means of a remanent polarization. The invention may be used for the formation of integrated circuit memories for the storage of information.

Organic non-volatile resistive photo-switches for flexible image detector arrays.

PubMed

Nau, Sebastian; Wolf, Christoph; Sax, Stefan; List-Kratochvil, Emil J W

2015-02-01

A unique implementation of an organic image detector using resistive photo-switchable pixels is presented. This resistive photo-switch comprises the vertical integration of an organic photodiode and an organic resistive switching memory element. The photodiodes act as a photosensitive element while the resistive switching elements simultaneously store the detected light information. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Memory device using movement of protons

DOEpatents

Warren, W.L.; Vanheusden, K.J.R.; Fleetwood, D.M.; Devine, R.A.B.

1998-11-03

An electrically written memory element is disclosed utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element. 19 figs.

Memory device using movement of protons

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.

1998-01-01

An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.

Memory device using movement of protons

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.

2000-01-01

An electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure laterally through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronic elements on the same silicon substrate. With the addition of an optically active layer, the memory element becomes an electrically written, optically read optical memory element.

Evolutionary Metal Oxide Clusters for Novel Applications: Toward High-Density Data Storage in Nonvolatile Memories.

PubMed

Chen, Xiaoli; Zhou, Ye; Roy, Vellaisamy A L; Han, Su-Ting

2018-01-01

Because of current fabrication limitations, miniaturizing nonvolatile memory devices for managing the explosive increase in big data is challenging. Molecular memories constitute a promising candidate for next-generation memories because their properties can be readily modulated through chemical synthesis. Moreover, these memories can be fabricated through mild solution processing, which can be easily scaled up. Among the various materials, polyoxometalate (POM) molecules have attracted considerable attention for use as novel data-storage nodes for nonvolatile memories. Here, an overview of recent advances in the development of POMs for nonvolatile memories is presented. The general background knowledge of the structure and property diversity of POMs is also summarized. Finally, the challenges and perspectives in the application of POMs in memories are discussed. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Peripheral Ferroelectric Domain Switching and Polarization Fatigue in Nonvolatile Memory Elements of Continuous Pt/SrBi2Ta2O9/Pt Thin-Film Capacitors

NASA Astrophysics Data System (ADS)

Chen, Min-Chuan; Jiang, An-Quan

2011-07-01

We verify the domain sideway motion around the peripheral regions of the crossed capacitors of top and bottom electrode bars without electrode coverage. To avoid the crosstalk problem between adjacent memory cells, the safe distance between adjacent elements of Pt/SrBi2Ta2O9/Pt thin-film capacitors is estimated to be 0.156 μm. Moreover, the fatigue of Pt/SrBi2Ta2O9/Pt thin-film capacitors is independent of the individual memory size due to the absence of etching damage.

Investing the effectiveness of retention performance in a non-volatile floating gate memory device with a core-shell structure of CdSe nanoparticles

NASA Astrophysics Data System (ADS)

Lee, Dong-Hoon; Kim, Jung-Min; Lim, Ki-Tae; Cho, Hyeong Jun; Bang, Jin Ho; Kim, Yong-Sang

2016-03-01

In this paper, we empirically investigate the retention performance of organic non-volatile floating gate memory devices with CdSe nanoparticles (NPs) as charge trapping elements. Core-structured CdSe NPs or core-shell-structured ZnS/CdSe NPs were mixed in PMMA and their performance in pentacene based device was compared. The NPs and self-organized thin tunneling PMMA inside the devices exhibited hysteresis by trapping hole during capacitance-voltage characterization. Despite of core-structured NPs showing a larger memory window, the retention time was too short to be adopted by an industry. By contrast core-shell structured NPs showed an improved retention time of >10000 seconds than core-structure NCs. Based on these results and the energy band structure, we propose the retention mechanism of each NPs. This investigation of retention performance provides a comparative and systematic study of the charging/discharging behaviors of NPs based memory devices. [Figure not available: see fulltext.

Non-Volatile Memory Technology Symposium 2000: Proceedings

NASA Technical Reports Server (NTRS)

Aranki, Nazeeh (Editor)

2000-01-01

This publication contains the proceedings for the Non-Volatile Memory Technology Symposium 2000 that was held on November 15-16, 2000 in Arlington, Virginia. The proceedings contains a wide range of papers that cover the presentations of myriad advances in the nonvolatile memory technology during the recent past including memory cell design, simulations, radiation environment, and emerging memory technologies. The papers presented in the proceedings address the design challenges and applications and deals with newer, emerging memory technologies as well as related issues of radiation environment and die packaging.

Effect of Atomic Layer Depositions (ALD)-Deposited Titanium Oxide (TiO2) Thickness on the Performance of Zr40Cu35Al15Ni10 (ZCAN)/TiO2/Indium (In)-Based Resistive Random Access Memory (RRAM) Structures

DTIC Science & Technology

2015-08-01

metal structures, memristors, resistive random access memory, RRAM, titanium dioxide, Zr40Cu35Al15Ni10, ZCAN, resistive memory, tunnel junction 16...TiO2 thickness ........................6 1 1. Introduction Resistive-switching memory elements based on metal-insulator-metal (MIM) diodes ...have attracted great interest due to their potential as components for simple, inexpensive, and high-density non-volatile storage devices. MIM diodes

TiO2-based memristors and ReRAM: materials, mechanisms and models (a review)

NASA Astrophysics Data System (ADS)

Gale, Ella

2014-10-01

The memristor is the fundamental nonlinear circuit element, with uses in computing and computer memory. Resistive Random Access Memory (ReRAM) is a resistive switching memory proposed as a non-volatile memory. In this review we shall summarize the state of the art for these closely-related fields, concentrating on titanium dioxide, the well-utilized and archetypal material for both. We shall cover material properties, switching mechanisms and models to demonstrate what ReRAM and memristor scientists can learn from each other and examine the outlook for these technologies.

GaAs metal-oxide-semiconductor based non-volatile flash memory devices with InAs quantum dots as charge storage nodes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Islam, Sk Masiul, E-mail: masiulelt@gmail.com; Chowdhury, Sisir; Sarkar, Krishnendu

2015-06-24

Ultra-thin InP passivated GaAs metal-oxide-semiconductor based non-volatile flash memory devices were fabricated using InAs quantum dots (QDs) as charge storing elements by metal organic chemical vapor deposition technique to study the efficacy of the QDs as charge storage elements. The grown QDs were embedded between two high-k dielectric such as HfO{sub 2} and ZrO{sub 2}, which were used for tunneling and control oxide layers, respectively. The size and density of the QDs were found to be 5 nm and 1.8×10{sup 11} cm{sup −2}, respectively. The device with a structure Metal/ZrO{sub 2}/InAs QDs/HfO{sub 2}/GaAs/Metal shows maximum memory window equivalent to 6.87 V. Themore » device also exhibits low leakage current density of the order of 10{sup −6} A/cm{sup 2} and reasonably good charge retention characteristics. The low value of leakage current in the fabricated memory device is attributed to the Coulomb blockade effect influenced by quantum confinement as well as reduction of interface trap states by ultra-thin InP passivation on GaAs prior to HfO{sub 2} deposition.« less

Investigation of Hafnium oxide/Copper resistive memory for advanced encryption applications

NASA Astrophysics Data System (ADS)

Briggs, Benjamin D.

The Advanced Encryption Standard (AES) is a widely used encryption algorithm to protect data and communications in today's digital age. Modern AES CMOS implementations require large amounts of dedicated logic and must be tuned for either performance or power consumption. A high throughput, low power, and low die area AES implementation is required in the growing mobile sector. An emerging non-volatile memory device known as resistive memory (ReRAM) is a simple metal-insulator-metal capacitor device structure with the ability to switch between two stable resistance states. Currently, ReRAM is targeted as a non-volatile memory replacement technology to eventually replace flash. Its advantages over flash include ease of fabrication, speed, and lower power consumption. In addition to memory, ReRAM can also be used in advanced logic implementations given its purely resistive behavior. The combination of a new non-volatile memory element ReRAM along with high performance, low power CMOS opens new avenues for logic implementations. This dissertation will cover the design and process implementation of a ReRAM-CMOS hybrid circuit, built using IBM's 10LPe process, for the improvement of hardware AES implementations. Further the device characteristics of ReRAM, specifically the HfO2/Cu memory system, and mechanisms for operation are not fully correlated. Of particular interest to this work is the role of material properties such as the stoichiometry, crystallinity, and doping of the HfO2 layer and their effect on the switching characteristics of resistive memory. Material properties were varied by a combination of atomic layer deposition and reactive sputtering of the HfO2 layer. Several studies will be discussed on how the above mentioned material properties influence switching parameters, and change the underlying physics of device operation.

Physical principles and current status of emerging non-volatile solid state memories

NASA Astrophysics Data System (ADS)

Wang, L.; Yang, C.-H.; Wen, J.

2015-07-01

Today the influence of non-volatile solid-state memories on persons' lives has become more prominent because of their non-volatility, low data latency, and high robustness. As a pioneering technology that is representative of non-volatile solidstate memories, flash memory has recently seen widespread application in many areas ranging from electronic appliances, such as cell phones and digital cameras, to external storage devices such as universal serial bus (USB) memory. Moreover, owing to its large storage capacity, it is expected that in the near future, flash memory will replace hard-disk drives as a dominant technology in the mass storage market, especially because of recently emerging solid-state drives. However, the rapid growth of the global digital data has led to the need for flash memories to have larger storage capacity, thus requiring a further downscaling of the cell size. Such a miniaturization is expected to be extremely difficult because of the well-known scaling limit of flash memories. It is therefore necessary to either explore innovative technologies that can extend the areal density of flash memories beyond the scaling limits, or to vigorously develop alternative non-volatile solid-state memories including ferroelectric random-access memory, magnetoresistive random-access memory, phase-change random-access memory, and resistive random-access memory. In this paper, we review the physical principles of flash memories and their technical challenges that affect our ability to enhance the storage capacity. We then present a detailed discussion of novel technologies that can extend the storage density of flash memories beyond the commonly accepted limits. In each case, we subsequently discuss the physical principles of these new types of non-volatile solid-state memories as well as their respective merits and weakness when utilized for data storage applications. Finally, we predict the future prospects for the aforementioned solid-state memories for the next generation of data-storage devices based on a comparison of their performance. [Figure not available: see fulltext.

Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

NASA Astrophysics Data System (ADS)

Hong, Augustin Jinwoo

Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

Nonvolatile Memory Technology for Space Applications

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; Irom, Farokh; Friendlich, Mark; Nguyen, Duc; Kim, Hak; Berg, Melanie; LaBel, Kenneth A.

2010-01-01

This slide presentation reviews several forms of nonvolatile memory for use in space applications. The intent is to: (1) Determine inherent radiation tolerance and sensitivities, (2) Identify challenges for future radiation hardening efforts, (3) Investigate new failure modes and effects, and technology modeling programs. Testing includes total dose, single event (proton, laser, heavy ion), and proton damage (where appropriate). Test vehicles are expected to be a variety of non-volatile memory devices as available including Flash (NAND and NOR), Charge Trap, Nanocrystal Flash, Magnetic Memory (MRAM), Phase Change--Chalcogenide, (CRAM), Ferroelectric (FRAM), CNT, and Resistive RAM.

Nonvolatile random access memory

NASA Technical Reports Server (NTRS)

Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor); Katti, Romney R. (Inventor)

1994-01-01

A nonvolatile magnetic random access memory can be achieved by an array of magnet-Hall effect (M-H) elements. The storage function is realized with a rectangular thin-film ferromagnetic material having an in-plane, uniaxial anisotropy and inplane bipolar remanent magnetization states. The thin-film magnetic element is magnetized by a local applied field, whose direction is used to form either a 0 or 1 state. The element remains in the 0 or 1 state until a switching field is applied to change its state. The stored information is detcted by a Hall-effect sensor which senses the fringing field from the magnetic storage element. The circuit design for addressing each cell includes transistor switches for providing a current of selected polarity to store a binary digit through a separate conductor overlying the magnetic element of the cell. To read out a stored binary digit, transistor switches are employed to provide a current through a row of Hall-effect sensors connected in series and enabling a differential voltage amplifier connected to all Hall-effect sensors of a column in series. To avoid read-out voltage errors due to shunt currents through resistive loads of the Hall-effect sensors of other cells in the same column, at least one transistor switch is provided between every pair of adjacent cells in every row which are not turned on except in the row of the selected cell.

Carbon nanomaterials for non-volatile memories

NASA Astrophysics Data System (ADS)

Ahn, Ethan C.; Wong, H.-S. Philip; Pop, Eric

2018-03-01

Carbon can create various low-dimensional nanostructures with remarkable electronic, optical, mechanical and thermal properties. These features make carbon nanomaterials especially interesting for next-generation memory and storage devices, such as resistive random access memory, phase-change memory, spin-transfer-torque magnetic random access memory and ferroelectric random access memory. Non-volatile memories greatly benefit from the use of carbon nanomaterials in terms of bit density and energy efficiency. In this Review, we discuss sp2-hybridized carbon-based low-dimensional nanostructures, such as fullerene, carbon nanotubes and graphene, in the context of non-volatile memory devices and architectures. Applications of carbon nanomaterials as memory electrodes, interfacial engineering layers, resistive-switching media, and scalable, high-performance memory selectors are investigated. Finally, we compare the different memory technologies in terms of writing energy and time, and highlight major challenges in the manufacturing, integration and understanding of the physical mechanisms and material properties.

SONOS technology for commercial and military nonvolatile memory applications

NASA Astrophysics Data System (ADS)

Adams, D.; Farrell, P.; Jacunski, M.; Williams, D.; Jakubczak, J.; Knoll, M.; Murray, J.

Silicon Oxide Nitride Oxide Semiconductor (SONOS) technology is well suited for military and commercial nonvolatile memory applications. Excellent long term memory retention, radiation hardness, and endurance has been demonstrated with this technology. This paper summarizes our data in these areas for SONOS technology.

Investigation of multilayer WS2 flakes as charge trapping stack layers in non-volatile memories

NASA Astrophysics Data System (ADS)

Wang, Hong; Ren, Deliang; Lu, Chao; Yan, Xiaobing

2018-06-01

In this study, the non-volatile flash memory devices utilize tungsten sulfide flakes as the charge trapping stack layers were fabricated. The sandwiched structure of Pd/ZHO/WS2/ZHO/WS2/SiO2/Si manifests a memory window of 2.26 V and a high density of trapped charges 4.88 × 1012/cm2 under a ±5 V gate sweeping voltage. Moreover, the data retention results of as-fabricated non-volatile memories demonstrate that the high and low capacitance states are enhanced by 3.81% and 3.11%, respectively, after a measurement duration of 1.20 × 104 s. These remarkable achievements are probably attributed to the defects and band gap of WS2 flakes. Besides, the proposed memory fabrication is not only compatible with CMOS manufacturing processes but also gets rid of the high-temperature annealing process. Overall, this proposed non-volatile memory is highly attractive for low voltage, long data retention applications.

High-Performance Nonvolatile Organic Field-Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers.

PubMed

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Yi, Mingdong; Wang, Laiyuan; Wu, Dequn; Xie, Linghai; Huang, Wei

2017-08-01

Nonvolatile organic field-effect transistor (OFET) memory devices based on pentacene/ N , N '-ditridecylperylene-3,4,9,10-tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n-type P13 embedded in p-type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well-like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge-trapping property of the poly(4-vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high-performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory.

High‐Performance Nonvolatile Organic Field‐Effect Transistor Memory Based on Organic Semiconductor Heterostructures of Pentacene/P13/Pentacene as Both Charge Transport and Trapping Layers

PubMed Central

Li, Wen; Guo, Fengning; Ling, Haifeng; Zhang, Peng; Wang, Laiyuan; Wu, Dequn

2017-01-01

Nonvolatile organic field‐effect transistor (OFET) memory devices based on pentacene/N,N′‐ditridecylperylene‐3,4,9,10‐tetracarboxylic diimide (P13)/pentacene trilayer organic heterostructures have been proposed. The discontinuous n‐type P13 embedded in p‐type pentacene layers can not only provide electrons in the semiconductor layer that facilitates electron trapping process; it also works as charge trapping sites, which is attributed to the quantum well‐like pentacene/P13/pentacene organic heterostructures. The synergistic effects of charge trapping in the discontinuous P13 and the charge‐trapping property of the poly(4‐vinylphenol) (PVP) layer remarkably improve the memory performance. In addition, the trilayer organic heterostructures have also been successfully applied to multilevel and flexible nonvolatile memory devices. The results provide a novel design strategy to achieve high‐performance nonvolatile OFET memory devices and allow potential applications for different combinations of various organic semiconductor materials in OFET memory. PMID:28852619

Printed dose-recording tag based on organic complementary circuits and ferroelectric nonvolatile memories

PubMed Central

Nga Ng, Tse; Schwartz, David E.; Mei, Ping; Krusor, Brent; Kor, Sivkheng; Veres, Janos; Bröms, Per; Eriksson, Torbjörn; Wang, Yong; Hagel, Olle; Karlsson, Christer

2015-01-01

We have demonstrated a printed electronic tag that monitors time-integrated sensor signals and writes to nonvolatile memories for later readout. The tag is additively fabricated on flexible plastic foil and comprises a thermistor divider, complementary organic circuits, and two nonvolatile memory cells. With a supply voltage below 30 V, the threshold temperatures can be tuned between 0 °C and 80 °C. The time-temperature dose measurement is calibrated for minute-scale integration. The two memory bits are sequentially written in a thermometer code to provide an accumulated dose record. PMID:26307438

Evaluation of switchable organic devices for nonvolatile memory applications

NASA Astrophysics Data System (ADS)

Campbell Scott, J.

2007-03-01

Many organic electronic devices exhibit switching behavior and have therefore been proposed as the basis for a nonvolatile memory technology. In particular, bistable resistive elements, in which a high or low current state is selected by application of a specific voltage, may be used as the elements of a crosspoint memory array. This architecture places very stringent requirements on the electrical response of the individual devices, in terms of on-state current density, switching and retention times, cycling endurance, rectification and size-scaling. In this talk, I will describe the progress that we and others have made towards satisfying these requirements. In many cases, the mechanisms responsible for conduction and switching are not fully understood. In some devices, it has been shown that current flows in a few highly localized regions. These so-called ``filaments'' are not necessarily metallic bridges between the electrodes, but may be associated with chains of nanoparticles introduced into the organic matrix either deliberately or accidentally. Coulomb blockade effects can then explain the switching behavior observed in some devices. This work was done in collaboration with L. D. Bozano, M. Beinhoff, K. R. Carter, V. R. Deline, B. W. Kean, G. M. McClelland, D. C. Miller, P. M. Rice, J. R. Salem, and S. A. Swanson.

Radiation and Reliability Concerns for Modern Nonvolatile Memory Technology

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; Friendlich, Mark R.; Kim, Hak S.; Berg, Melanie D.; LaBel, Kenneth A.; Buchner, S. P.; McMorrow, D.; Mavis, D. G.; Eaton, P. H.; Castillo, J.

2011-01-01

Commercial nonvolatile memory technology is attractive for space applications, but radiation issues are serious concerns. In addition, we discuss combined radiation/reliability concerns which are only beginning to be addressed.

A flexible nonvolatile resistive switching memory device based on ZnO film fabricated on a foldable PET substrate.

PubMed

Sun, Bai; Zhang, Xuejiao; Zhou, Guangdong; Yu, Tian; Mao, Shuangsuo; Zhu, Shouhui; Zhao, Yong; Xia, Yudong

2018-06-15

In this work, a flexible resistive switching memory device based on ZnO film was fabricated using a foldable Polyethylene terephthalate (PET) film as substrate while Ag and Ti acts top and bottom electrode. Our as-prepared device represents an outstanding nonvolatile memory behavior with good "write-read-erase-read" stability at room temperature. Finally, a physical model of Ag conductive filament is constructed to understanding the observed memory characteristics. The work provides a new way for the preparation of flexible memory devices based on ZnO films, and especially provides an experimental basis for the exploration of high-performance and portable nonvolatile resistance random memory (RRAM). Copyright © 2018 Elsevier Inc. All rights reserved.

Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2010

NASA Technical Reports Server (NTRS)

Irom, Farokh; Nguyen, Duc N.

2010-01-01

High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) and multi-level cell (MLC) NAND flash memories manufactured by Micron Technology.

Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Y.; Zhong, Y. P.; Deng, Y. F.

2013-12-21

Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

40 CFR 1042.110 - Recording reductant use and other diagnostic functions.

Code of Federal Regulations, 2010 CFR

2010-07-01

...) The onboard computer log must record in nonvolatile computer memory all incidents of engine operation... such operation in nonvolatile computer memory. You are not required to monitor NOX concentrations...

Binary synaptic connections based on memory switching in a-Si:H for artificial neural networks

NASA Technical Reports Server (NTRS)

Thakoor, A. P.; Lamb, J. L.; Moopenn, A.; Khanna, S. K.

1987-01-01

A scheme for nonvolatile associative electronic memory storage with high information storage density is proposed which is based on neural network models and which uses a matrix of two-terminal passive interconnections (synapses). It is noted that the massive parallelism in the architecture would require the ON state of a synaptic connection to be unusually weak (highly resistive). Memory switching using a-Si:H along with ballast resistors patterned from amorphous Ge-metal alloys is investigated for a binary programmable read only memory matrix. The fabrication of a 1600 synapse test array of uniform connection strengths and a-Si:H switching elements is discussed.

Radiation Tests of Highly scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories--Update 2011

NASA Technical Reports Server (NTRS)

Irom, Farokh; Nguyen, Duc N.

2011-01-01

High-density, commercial, nonvolatile flash memories with NAND architecture are now available from several manufacturers. This report examines SEE effects and TID response in single-level cell (SLC) 32Gb and multi-level cell (MLC) 64Gb NAND flash memories manufactured by Micron Technology.

Flash drive memory apparatus and method

NASA Technical Reports Server (NTRS)

Hinchey, Michael G. (Inventor)

2010-01-01

A memory apparatus includes a non-volatile computer memory, a USB mass storage controller connected to the non-volatile computer memory, the USB mass storage controller including a daisy chain component, a male USB interface connected to the USB mass storage controller, and at least one other interface for a memory device, other than a USB interface, the at least one other interface being connected to the USB mass storage controller.

Non-volatile memory based on the ferroelectric photovoltaic effect

PubMed Central

Guo, Rui; You, Lu; Zhou, Yang; Shiuh Lim, Zhi; Zou, Xi; Chen, Lang; Ramesh, R.; Wang, Junling

2013-01-01

The quest for a solid state universal memory with high-storage density, high read/write speed, random access and non-volatility has triggered intense research into new materials and novel device architectures. Though the non-volatile memory market is dominated by flash memory now, it has very low operation speed with ~10 μs programming and ~10 ms erasing time. Furthermore, it can only withstand ~105 rewriting cycles, which prevents it from becoming the universal memory. Here we demonstrate that the significant photovoltaic effect of a ferroelectric material, such as BiFeO3 with a band gap in the visible range, can be used to sense the polarization direction non-destructively in a ferroelectric memory. A prototype 16-cell memory based on the cross-bar architecture has been prepared and tested, demonstrating the feasibility of this technique. PMID:23756366

Flexible graphene-PZT ferroelectric nonvolatile memory.

PubMed

Lee, Wonho; Kahya, Orhan; Toh, Chee Tat; Ozyilmaz, Barbaros; Ahn, Jong-Hyun

2013-11-29

We report the fabrication of a flexible graphene-based nonvolatile memory device using Pb(Zr0.35,Ti0.65)O3 (PZT) as the ferroelectric material. The graphene and PZT ferroelectric layers were deposited using chemical vapor deposition and sol–gel methods, respectively. Such PZT films show a high remnant polarization (Pr) of 30 μC cm−2 and a coercive voltage (Vc) of 3.5 V under a voltage loop over ±11 V. The graphene–PZT ferroelectric nonvolatile memory on a plastic substrate displayed an on/off current ratio of 6.7, a memory window of 6 V and reliable operation. In addition, the device showed one order of magnitude lower operation voltage range than organic-based ferroelectric nonvolatile memory after removing the anti-ferroelectric behavior incorporating an electrolyte solution. The devices showed robust operation in bent states of bending radii up to 9 mm and in cycling tests of 200 times. The devices exhibited remarkable mechanical properties and were readily integrated with plastic substrates for the production of flexible circuits.

Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2015-07-21

Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

NASA Astrophysics Data System (ADS)

Suarez, Ernesto; Chan, Pik-Yiu; Lingalugari, Murali; Ayers, John E.; Heller, Evan; Jain, Faquir

2013-11-01

This paper describes the use of II-VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II-VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

Ferroelectric memory evaluation and development system

NASA Astrophysics Data System (ADS)

Bondurant, David W.

Attention is given to the Ramtron FEDS-1, an IBM PC/AT compatible single-board 16-b microcomputer with 8-kbyte program/data memory implemented with nonvolatile ferroelectric dynamic RAM. This is the first demonstration of a new type of solid state nonvolatile read/write memory, the ferroelectric RAM (FRAM). It is suggested that this memory technology will have a significant impact on avionics system performance and reliability.

Design of a memory-access controller with 3.71-times-enhanced energy efficiency for Internet-of-Things-oriented nonvolatile microcontroller unit

NASA Astrophysics Data System (ADS)

Natsui, Masanori; Hanyu, Takahiro

2018-04-01

In realizing a nonvolatile microcontroller unit (MCU) for sensor nodes in Internet-of-Things (IoT) applications, it is important to solve the data-transfer bottleneck between the central processing unit (CPU) and the nonvolatile memory constituting the MCU. As one circuit-oriented approach to solving this problem, we propose a memory access minimization technique for magnetoresistive-random-access-memory (MRAM)-embedded nonvolatile MCUs. In addition to multiplexing and prefetching of memory access, the proposed technique realizes efficient instruction fetch by eliminating redundant memory access while considering the code length of the instruction to be fetched and the transition of the memory address to be accessed. As a result, the performance of the MCU can be improved while relaxing the performance requirement for the embedded MRAM, and compact and low-power implementation can be performed as compared with the conventional cache-based one. Through the evaluation using a system consisting of a general purpose 32-bit CPU and embedded MRAM, it is demonstrated that the proposed technique increases the peak efficiency of the system up to 3.71 times, while a 2.29-fold area reduction is achieved compared with the cache-based one.

Non-volatile memory for checkpoint storage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blumrich, Matthias A.; Chen, Dong; Cipolla, Thomas M.

A system, method and computer program product for supporting system initiated checkpoints in high performance parallel computing systems and storing of checkpoint data to a non-volatile memory storage device. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity. In one embodiment, themore » non-volatile memory is a pluggable flash memory card.« less

Investigation of field induced trapping on floating gates

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1975-01-01

The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

The Glass Computer

ERIC Educational Resources Information Center

Paesler, M. A.

2009-01-01

Digital computers use different kinds of memory, each of which is either volatile or nonvolatile. On most computers only the hard drive memory is nonvolatile, i.e., it retains all information stored on it when the power is off. When a computer is turned on, an operating system stored on the hard drive is loaded into the computer's memory cache and…

Titanium oxide nonvolatile memory device and its application

NASA Astrophysics Data System (ADS)

Wang, Wei

In recent years, the semiconductor memory industry has seen an ever-increasing demand for nonvolatile memory (NVM), which is fueled by portable consumer electronic applications like the mobile phone and MP3 player. FLASH memory has been the most widely used nonvolatile memories in these systems, and has successfully kept up with CMOS scaling for many generations. However, as FLASH memory faces major scaling challenges beyond 22nm, non-charge-based nonvolatile memories are widely researched as candidates to replace FLASH. Titanium oxide (TiOx) nonvolatile memory device is considered to be a promising choice due to its controllable nonvolatile memory switching, good scalability, compatibility with CMOS processing and potential for 3D stacking. However, several major issues need to be overcome before TiOx NVM device can be adopted in manufacturing. First, there exists a highly undesirable high-voltage stress initiation process (FORMING) before the device can switch between high and low resistance states repeatedly. By analyzing the conductive behaviors of the memory device before and after FORMING, we propose that FORMING involves breaking down an interfacial layer between its Pt electrode and the TiOx thin film, and that FORMING is not needed if the Pt-TiOx interface can be kept clean during fabrication. An in-situ fabrication process is developed for cross-point TiOx NVM device, which enables in-situ deposition of the critical layers of the memory device and thus achieves clean interfaces between Pt electrodes and TiOx film. Testing results show that FORMING is indeed eliminated for memory devices made with the in-situ fabrication process. It verifies the significance of in-situ deposition without vacuum break in the fabrication of TiOx NVM devices. Switching parameters statistics of TiOx NVM devices are studied and compared for unipolar and bipolar switching modes. RESET mechanisms are found to be different for the two switching modes: unipolar switching can be explained by thermal dissolution model, and bipolar switching by local redox reaction model. Since it is generally agreed that the memory switching of TiOx NVM devices is based on conductive filaments, reusability of these conductive filaments becomes an intriguing issue to determine the memory device's endurance. A 1X3 cross-point test structure is built to investigate whether conductive filaments can be reused after RESET. It is found that the conductive filament is destroyed during unipolar switching, while can be reused during bipolar switching. The result is a good indication that bipolar switching should have better endurance than unipolar switching. Finally a novel application of the two-terminal resistive switching NVM devices is demonstrated. To reduce SRAM leakage power, we propose a nonvolatile SRAM cell with two back-up NVM devices. This novel cell offers nonvolatile storage, thus allowing selected blocks of SRAM to be powered down during operation. There is no area penalty in this approach. Only a slight performance penalty is expected.

Active non-volatile memory post-processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kannan, Sudarsun; Milojicic, Dejan S.; Talwar, Vanish

A computing node includes an active Non-Volatile Random Access Memory (NVRAM) component which includes memory and a sub-processor component. The memory is to store data chunks received from a processor core, the data chunks comprising metadata indicating a type of post-processing to be performed on data within the data chunks. The sub-processor component is to perform post-processing of said data chunks based on said metadata.

Coexistence of diode-like volatile and multilevel nonvolatile resistive switching in a ZrO2/TiO2 stack structure.

PubMed

Li, Yingtao; Yuan, Peng; Fu, Liping; Li, Rongrong; Gao, Xiaoping; Tao, Chunlan

2015-10-02

Diode-like volatile resistive switching as well as nonvolatile resistive switching behaviors in a Cu/ZrO₂/TiO₂/Ti stack are investigated. Depending on the current compliance during the electroforming process, either volatile resistive switching or nonvolatile resistive switching is observed. With a lower current compliance (<10 μA), the Cu/ZrO₂/TiO₂/Ti device exhibits diode-like volatile resistive switching with a rectifying ratio over 10(6). The permanent transition from volatile to nonvolatile resistive switching can be obtained by applying a higher current compliance of 100 μA. Furthermore, by using different reset voltages, the Cu/ZrO₂/TiO₂/Ti device exhibits multilevel memory characteristics with high uniformity. The coexistence of nonvolatile multilevel memory and diode-like volatile resistive switching behaviors in the same Cu/ZrO₂/TiO₂/Ti device opens areas of applications in high-density storage, logic circuits, neural networks, and passive crossbar memory selectors.

Evaluation of Magnetoresistive RAM for Space Applications

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2014-01-01

Magnetoresistive random-access memory (MRAM) is a non-volatile memory that exploits electronic spin, rather than charge, to store data. Instead of moving charge on and off a floating gate to alter the threshold voltage of a CMOS transistor (creating different bit states), MRAM uses magnetic fields to flip the polarization of a ferromagnetic material thus switching its resistance and bit state. These polarized states are immune to radiation-induced upset, thus making MRAM very attractive for space application. These magnetic memory elements also have infinite data retention and erase/program endurance. Presented here are results of reliability testing of two space-qualified MRAM products from Aeroflex and Honeywell.

Non-Volatile Memory Technology Symposium 2001: Proceedings

NASA Technical Reports Server (NTRS)

Aranki, Nazeeh; Daud, Taher; Strauss, Karl

2001-01-01

This publication contains the proceedings for the Non-Volatile Memory Technology Symposium 2001 that was held on November 7-8, 2001 in San Diego, CA. The proceedings contains a a wide range of papers that cover current and new memory technologies including Flash memories, Magnetic Random Access Memories (MRAM and GMRAM), Ferro-electric RAM (FeRAM), and Chalcogenide RAM (CRAM). The papers presented in the proceedings address the use of these technologies for space applications as well as radiation effects and packaging issues.

SONOS Nonvolatile Memory Cell Programming Characteristics

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2010-01-01

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory is gaining favor over conventional EEPROM FLASH memory technology. This paper characterizes the SONOS write operation using a nonquasi-static MOSFET model. This includes floating gate charge and voltage characteristics as well as tunneling current, voltage threshold and drain current characterization. The characterization of the SONOS memory cell predicted by the model closely agrees with experimental data obtained from actual SONOS memory cells. The tunnel current, drain current, threshold voltage and read drain current all closely agreed with empirical data.

A review of emerging non-volatile memory (NVM) technologies and applications

NASA Astrophysics Data System (ADS)

Chen, An

2016-11-01

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

High-performance black phosphorus top-gate ferroelectric transistor for nonvolatile memory applications

NASA Astrophysics Data System (ADS)

Lee, Young Tack; Hwang, Do Kyung; Choi, Won Kook

2016-10-01

Two-dimensional (2D) van der Waals (vdW) atomic crystals have been extensively studied and significant progress has been made. The newest 2D vdW material, called black phosphorus (BP), has attracted considerable attention due to its unique physical properties, such as its being a singlecomponent material like graphene, and its having a high mobility and direct band gap. Here, we report on a high-performance BP nanosheet based ferroelectric field effect transistor (FeFET) with a poly(vinylidenefluoride-trifluoroethylene) top-gate insulator for a nonvolatile memory application. The BP FeFETs show the highest linear hole mobility of 563 cm2/Vs and a clear memory window of more than 15 V. For more advanced nonvolatile memory circuit applications, two different types of resistive-load and complementary ferroelectric memory inverters were implemented, which showed distinct memory on/off switching characteristics.

Unified random access memory (URAM) by integration of a nanocrystal floating gate for nonvolatile memory and a partially depleted floating body for capacitorless 1T-DRAM

NASA Astrophysics Data System (ADS)

Ryu, Seong-Wan; Han, Jin-Woo; Kim, Chung-Jin; Kim, Sungho; Choi, Yang-Kyu

2009-03-01

This paper describes a unified memory (URAM) that utilizes a nanocrystal SOI MOSFET for multi-functional applications of both nonvolatile memory (NVM) and capacitorless 1T-DRAM. By using a discrete storage node (Ag nanocrystal) as the floating gate of the NVM, high defect immunity and 2-bit/cell operation were achieved. The embedded nanocrystal NVM also showed 1T-DRAM operation (program/erase time = 100 ns) characteristics, which were realized by storing holes in the floating body of the SOI MOSFET, without requiring an external capacitor. Three-bit/cell operation was accomplished for different applications - 2-bits for nonvolatility and 1-bit for fast operation.

Implementation of Ferroelectric Memories for Space Applications

NASA Technical Reports Server (NTRS)

Philpy, Stephen C.; Derbenwick, Gary F.; Kamp, David A.; Isaacson, Alan F.

2000-01-01

Ferroelectric random access semiconductor memories (FeRAMs) are an ideal nonvolatile solution for space applications. These memories have low power performance, high endurance and fast write times. By combining commercial ferroelectric memory technology with radiation hardened CMOS technology, nonvolatile semiconductor memories for space applications can be attained. Of the few radiation hardened semiconductor manufacturers, none have embraced the development of radiation hardened FeRAMs, due a limited commercial space market and funding limitations. Government funding may be necessary to assure the development of radiation hardened ferroelectric memories for space applications.

Nonvolatile memory behavior of nanocrystalline cellulose/graphene oxide composite films

NASA Astrophysics Data System (ADS)

Valentini, L.; Cardinali, M.; Fortunati, E.; Kenny, J. M.

2014-10-01

With the continuous advance of modern electronics, the demand for nonvolatile memory cells rapidly grows. In order to develop post-silicon electronic devices, it is necessary to find innovative solutions to the eco-sustainability problem of materials for nonvolatile memory cells. In this work, we realized a resistive memory device based on graphene oxide (GO) and GO/cellulose nanocrystals (CNC) thin films. Aqueous solutions of GO and GO with CNC have been prepared and drop cast between two metal electrodes. Such thin-film based devices showed a transition between low and high conductivity states upon the forward and backward sweeping of an external electric field. This reversible current density transition behavior demonstrates a typical memory characteristic. The obtained results open an easy route for electronic information storage based on the integration of nanocrystalline cellulose onto graphene based devices.

Extraction of the gate capacitance coupling coefficient in floating gate non-volatile memories: Statistical study of the effect of mismatching between floating gate memory and reference transistor in dummy cell extraction methods

NASA Astrophysics Data System (ADS)

Rafhay, Quentin; Beug, M. Florian; Duane, Russell

2007-04-01

This paper presents an experimental comparison of dummy cell extraction methods of the gate capacitance coupling coefficient for floating gate non-volatile memory structures from different geometries and technologies. These results show the significant influence of mismatching floating gate devices and reference transistors on the extraction of the gate capacitance coupling coefficient. In addition, it demonstrates the accuracy of the new bulk bias dummy cell extraction method and the importance of the β function, introduced recently in [Duane R, Beug F, Mathewson A. Novel capacitance coupling coefficient measurement methodology for floating gate non-volatile memory devices. IEEE Electr Dev Lett 2005;26(7):507-9], to determine matching pairs of floating gate memory and reference transistor.

Bistable microelectromechanical actuator

DOEpatents

Fleming, James G.

1999-01-01

A bistable microelectromechanical (MEM) actuator is formed on a substrate and includes a stressed membrane of generally rectangular shape that upon release assumes a curvilinear cross-sectional shape due to attachment at a midpoint to a resilient member and at opposing edges to a pair of elongate supports. The stressed membrane can be electrostatically switched between a pair of mechanical states having mirror-image symmetry, with the MEM actuator remaining in a quiescent state after a programming voltage is removed. The bistable MEM actuator according to various embodiments of the present invention can be used to form a nonvolatile memory element, an optical modulator (with a pair of mirrors supported above the membrane and moving in synchronism as the membrane is switched), a switchable mirror (with a single mirror supported above the membrane at the midpoint thereof) and a latching relay (with a pair of contacts that open and close as the membrane is switched). Arrays of bistable MEM actuators can be formed for applications including nonvolatile memories, optical displays and optical computing.

Bistable microelectromechanical actuator

DOEpatents

Fleming, J.G.

1999-02-02

A bistable microelectromechanical (MEM) actuator is formed on a substrate and includes a stressed membrane of generally rectangular shape that upon release assumes a curvilinear cross-sectional shape due to attachment at a midpoint to a resilient member and at opposing edges to a pair of elongate supports. The stressed membrane can be electrostatically switched between a pair of mechanical states having mirror-image symmetry, with the MEM actuator remaining in a quiescent state after a programming voltage is removed. The bistable MEM actuator according to various embodiments of the present invention can be used to form a nonvolatile memory element, an optical modulator (with a pair of mirrors supported above the membrane and moving in synchronism as the membrane is switched), a switchable mirror (with a single mirror supported above the membrane at the midpoint thereof) and a latching relay (with a pair of contacts that open and close as the membrane is switched). Arrays of bistable MEM actuators can be formed for applications including nonvolatile memories, optical displays and optical computing. 49 figs.

Overview of Non-Volatile Testing and Screening Methods

NASA Technical Reports Server (NTRS)

Irom, Farokh

2001-01-01

Testing methods for memories and non-volatile memories have become increasingly sophisticated as they become denser and more complex. High frequency and faster rewrite times as well as smaller feature sizes have led to many testing challenges. This paper outlines several testing issues posed by novel memories and approaches to testing for radiation and reliability effects. We discuss methods for measurements of Total Ionizing Dose (TID).

Overview of emerging nonvolatile memory technologies

PubMed Central

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices. PMID:25278820

Overview of emerging nonvolatile memory technologies.

PubMed

Meena, Jagan Singh; Sze, Simon Min; Chand, Umesh; Tseng, Tseung-Yuen

2014-01-01

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices.

Memory device using movement of protons

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Fleetwood, Daniel M.; Devine, Roderick A. B.; Archer, Leo B.; Brown, George A.; Wallace, Robert M.

2000-01-01

An enhancement of an electrically written memory element utilizing the motion of protons within a dielectric layer surrounded by layers on either side to confine the protons within the dielectric layer with electrode means attached to the surrounding layers to change the spatial position of the protons within the dielectric layer. The device is preferably constructed as a silicon-silicon dioxide-silicon layered structure with the protons being introduced to the structure during an anneal in an atmosphere containing hydrogen gas. Device operation is enhanced by concluding this anneal step with a sudden cooling. The device operates at low power, is preferably nonvolatile, is radiation tolerant, and is compatible with convention silicon MOS processing for integration with other microelectronics elements on the same silicon substrate.

Characterization of Au/PbTi0.5Fe0.5O3/Si structure for possible multiferroic based non-volatile memory applications

NASA Astrophysics Data System (ADS)

Nawaz, S.; Roy, S.; Tulapurkar, A. A.; Palkar, V. R.

2017-03-01

Magnetoelectric multiferroic PbTi0.5Fe0.5O3 films are deposited on a ⟨100⟩ conducting p-Si substrate without any buffer layer by using pulsed laser deposition and characterized for possible non-volatile memory applications. Their crystalline structure and surface morphology were characterized by using x-ray diffraction and AFM techniques. HRTEM was employed to determine the film-substrate interface. The electronic structure of the film was investigated by XPS, and no signature of metal was found for all the elements. The chemical shift of the Ti 2p XPS peak is attributed to the replacement of Ti with Fe in the PbTiO3 matrix. Piezoelectric force microscopy (PFM) results indicate the 180° phase shift of ferroelectric polarization. The upward self-polarization phenomenon is also observed in the PFM study. Magnetic and magneto-electric coupling measurements were carried out to confirm the magnetic nature and electro-magnetic coupling characteristics. C-V measurements exhibit clock-wise hysteresis loops with a maximum memory window of 1.2 V and a sweep voltage of ±7 V. This study could influence the fabrication of silicon compatible multiple memory device structures.

Nanoscale CuO solid-electrolyte-based conductive-bridging, random-access memory cell with a TiN liner

NASA Astrophysics Data System (ADS)

Lee, Jong-Sun; Kim, Dong-Won; Kim, Hea-Jee; Jin, Soo-Min; Song, Myung-Jin; Kwon, Ki-Hyun; Park, Jea-Gun; Jalalah, Mohammed; Al-Hajry, Ali

2018-01-01

The Conductive-bridge random-access memory (CBRAM) cell is a promising candidate for a terabit-level non-volatile memory due to its remarkable advantages. We present for the first time TiN as a diffusion barrier in CBRAM cells for enhancing their reliability. CuO solid-electrolyte-based CBRAM cells implemented with a 0.1-nm TiN liner demonstrated better non-volatile memory characteristics such as 106 AC write/erase endurance cycles with 100-μs AC pulse width and a long retention time of 7.4-years at 85 °C. In addition, the analysis of Ag diffusion in the CBRAM cell suggests that the morphology of the Ag filaments in the electrolyte can be effectively controlled by tuning the thickness of the TiN liner. These promising results pave the way for faster commercialization of terabit-level non-volatile memories.

Nonvolatile memory behavior of nanocrystalline cellulose/graphene oxide composite films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Valentini, L., E-mail: luca.valentini@unipg.it; Cardinali, M.; Fortunati, E.

2014-10-13

With the continuous advance of modern electronics, the demand for nonvolatile memory cells rapidly grows. In order to develop post-silicon electronic devices, it is necessary to find innovative solutions to the eco-sustainability problem of materials for nonvolatile memory cells. In this work, we realized a resistive memory device based on graphene oxide (GO) and GO/cellulose nanocrystals (CNC) thin films. Aqueous solutions of GO and GO with CNC have been prepared and drop cast between two metal electrodes. Such thin-film based devices showed a transition between low and high conductivity states upon the forward and backward sweeping of an external electricmore » field. This reversible current density transition behavior demonstrates a typical memory characteristic. The obtained results open an easy route for electronic information storage based on the integration of nanocrystalline cellulose onto graphene based devices.« less

An upconverted photonic nonvolatile memory.

PubMed

Zhou, Ye; Han, Su-Ting; Chen, Xian; Wang, Feng; Tang, Yong-Bing; Roy, V A L

2014-08-21

Conventional flash memory devices are voltage driven and found to be unsafe for confidential data storage. To ensure the security of the stored data, there is a strong demand for developing novel nonvolatile memory technology for data encryption. Here we show a photonic flash memory device, based on upconversion nanocrystals, which is light driven with a particular narrow width of wavelength in addition to voltage bias. With the help of near-infrared light, we successfully manipulate the multilevel data storage of the flash memory device. These upconverted photonic flash memory devices exhibit high ON/OFF ratio, long retention time and excellent rewritable characteristics.

Flexible non-volatile memory devices based on organic semiconductors

NASA Astrophysics Data System (ADS)

Cosseddu, Piero; Casula, Giulia; Lai, Stefano; Bonfiglio, Annalisa

2015-09-01

The possibility of developing fully organic electronic circuits is critically dependent on the ability to realize a full set of electronic functionalities based on organic devices. In order to complete the scene, a fundamental element is still missing, i.e. reliable data storage. Over the past few years, a considerable effort has been spent on the development and optimization of organic polymer based memory elements. Among several possible solutions, transistor-based memories and resistive switching-based memories are attracting a great interest in the scientific community. In this paper, a route for the fabrication of organic semiconductor-based memory devices with performances beyond the state of the art is reported. Both the families of organic memories will be considered. A flexible resistive memory based on a novel combination of materials is presented. In particular, high retention time in ambient conditions are reported. Complementary, a low voltage transistor-based memory is presented. Low voltage operation is allowed by an hybrid, nano-sized dielectric, which is also responsible for the memory effect in the device. Thanks to the possibility of reproducibly fabricating such device on ultra-thin substrates, high mechanical stability is reported.

Metal-organic molecular device for non-volatile memory storage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Radha, B., E-mail: radha.boya@manchester.ac.uk, E-mail: kulkarni@jncasr.ac.in; Sagade, Abhay A.; Kulkarni, G. U., E-mail: radha.boya@manchester.ac.uk, E-mail: kulkarni@jncasr.ac.in

Non-volatile memory devices have been of immense research interest for their use in active memory storage in powered off-state of electronic chips. In literature, various molecules and metal compounds have been investigated in this regard. Molecular memory devices are particularly attractive as they offer the ease of storing multiple memory states in a unique way and also represent ubiquitous choice for miniaturized devices. However, molecules are fragile and thus the device breakdown at nominal voltages during repeated cycles hinders their practical applicability. Here, in this report, a synergetic combination of an organic molecule and an inorganic metal, i.e., a metal-organicmore » complex, namely, palladium hexadecylthiolate is investigated for memory device characteristics. Palladium hexadecylthiolate following partial thermolysis is converted to a molecular nanocomposite of Pd(II), Pd(0), and long chain hydrocarbons, which is shown to exhibit non-volatile memory characteristics with exceptional stability and retention. The devices are all solution-processed and the memory action stems from filament formation across the pre-formed cracks in the nanocomposite film.« less

A FPGA-based Measurement System for Nonvolatile Semiconductor Memory Characterization

NASA Astrophysics Data System (ADS)

Bu, Jiankang; White, Marvin

2002-03-01

Low voltage, long retention, high density SONOS nonvolatile semiconductor memory (NVSM) devices are ideally suited for PCMCIA, FLASH and 'smart' cards. The SONOS memory transistor requires characterization with an accurate, rapid measurement system with minimum disturbance to the device. The FPGA-based measurement system includes three parts: 1) a pattern generator implemented with XILINX FPGAs and corresponding software, 2) a high-speed, constant-current, threshold voltage detection circuit, 3) and a data evaluation program, implemented with a LABVIEW program. Fig. 1 shows the general block diagram of the FPGA-based measurement system. The function generator is designed and simulated with XILINX Foundation Software. Under the control of the specific erase/write/read pulses, the analog detect circuit applies operational modes to the SONOS device under test (DUT) and determines the change of the memory-state of the SONOS nonvolatile memory transistor. The TEK460 digitizes the analog threshold voltage output and sends to the PC computer. The data is filtered and averaged with a LABVIEWTM program running on the PC computer and displayed on the monitor in real time. We have implemented the pattern generator with XILINX FPGAs. Fig. 2 shows the block diagram of the pattern generator. We realized the logic control by a method of state machine design. Fig. 3 shows a small part of the state machine. The flexibility of the FPGAs enhances the capabilities of this system and allows measurement variations without hardware changes. The characterization of the nonvolatile memory transistor device under test (DUT), as function of programming voltage and time, is achieved by a high-speed, constant-current threshold voltage detection circuit. The analog detection circuit incorporating fast analog switches controlled digitally with the FPGAs. The schematic circuit diagram is shown in Fig. 4. The various operational modes for the DUT are realized with control signals applied to the analog switches (SW) as shown in Fig. 5. A LABVIEWTM program, on a PC platform, collects and processes the data. The data is displayed on the monitor in real time. This time-domain filtering reduces the digitizing error. Fig. 6 shows the data processing. SONOS nonvolatile semiconductor memories are characterized by erase/write, retention and endurance measurements. Fig. 7 shows the erase/write characteristics of an n-Channel, 5V prog-rammable SONOS memory transistor. Fig.8 shows the retention characteristic of the same SONOS transistor. We have used this system to characterize SONOS nonvolatile semiconductor memory transistors. The attractive features of the test system design lies in the cost-effectiveness and flexibility of the test pattern implementation, fast read-out of memory state, low power, high precision determination of the device threshold voltage, and perhaps most importantly, minimum disturbance, which is indispensable for nonvolatile memory characterization.

Makalu: fast recoverable allocation of non-volatile memory

DOE PAGES

Bhandari, Kumud; Chakrabarti, Dhruva R.; Boehm, Hans-J.

2016-10-19

Byte addressable non-volatile memory (NVRAM) is likely to supplement, and perhaps eventually replace, DRAM. Applications can then persist data structures directly in memory instead of serializing them and storing them onto a durable block device. However, failures during execution can leave data structures in NVRAM unreachable or corrupt. In this paper, we present Makalu, a system that addresses non-volatile memory management. Makalu offers an integrated allocator and recovery-time garbage collector that maintains internal consistency, avoids NVRAM memory leaks, and is efficient, all in the face of failures. We show that a careful allocator design can support a less restrictive andmore » a much more familiar programming model than existing persistent memory allocators. Our allocator significantly reduces the per allocation persistence overhead by lazily persisting non-essential metadata and by employing a post-failure recovery-time garbage collector. Experimental results show that the resulting online speed and scalability of our allocator are comparable to well-known transient allocators, and significantly better than state-of-the-art persistent allocators.« less

Makalu: fast recoverable allocation of non-volatile memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bhandari, Kumud; Chakrabarti, Dhruva R.; Boehm, Hans-J.

Byte addressable non-volatile memory (NVRAM) is likely to supplement, and perhaps eventually replace, DRAM. Applications can then persist data structures directly in memory instead of serializing them and storing them onto a durable block device. However, failures during execution can leave data structures in NVRAM unreachable or corrupt. In this paper, we present Makalu, a system that addresses non-volatile memory management. Makalu offers an integrated allocator and recovery-time garbage collector that maintains internal consistency, avoids NVRAM memory leaks, and is efficient, all in the face of failures. We show that a careful allocator design can support a less restrictive andmore » a much more familiar programming model than existing persistent memory allocators. Our allocator significantly reduces the per allocation persistence overhead by lazily persisting non-essential metadata and by employing a post-failure recovery-time garbage collector. Experimental results show that the resulting online speed and scalability of our allocator are comparable to well-known transient allocators, and significantly better than state-of-the-art persistent allocators.« less

Highly stable, extremely high-temperature, nonvolatile memory based on resistance switching in polycrystalline Pt nanogaps

PubMed Central

Suga, Hiroshi; Suzuki, Hiroya; Shinomura, Yuma; Kashiwabara, Shota; Tsukagoshi, Kazuhito; Shimizu, Tetsuo; Naitoh, Yasuhisa

2016-01-01

Highly stable, nonvolatile, high-temperature memory based on resistance switching was realized using a polycrystalline platinum (Pt) nanogap. The operating temperature of the memory can be drastically increased by the presence of a sharp-edged Pt crystal facet in the nanogap. A short distance between the facet edges maintains the nanogap shape at high temperature, and the sharp shape of the nanogap densifies the electric field to maintain a stable current flow due to field migration. Even at 873 K, which is a significantly higher temperature than feasible for conventional semiconductor memory, the nonvolatility of the proposed memory allows stable ON and OFF currents, with fluctuations of less than or equal to 10%, to be maintained for longer than eight hours. An advantage of this nanogap scheme for high-temperature memory is its secure operation achieved through the assembly and disassembly of a Pt needle in a high electric field. PMID:27725705

Li-ion synaptic transistor for low power analog computing

DOE PAGES

Fuller, Elliot J.; Gabaly, Farid El; Leonard, Francois; ...

2016-11-22

Nonvolatile redox transistors (NVRTs) based upon Li-ion battery materials are demonstrated as memory elements for neuromorphic computer architectures with multi-level analog states, “write” linearity, low-voltage switching, and low power dissipation. Simulations of back propagation using the device properties reach ideal classification accuracy. Finally, physics-based simulations predict energy costs per “write” operation of <10 aJ when scaled to 200 nm × 200 nm.

MSL-RAD Cruise Operations Concept

NASA Technical Reports Server (NTRS)

Brinza, David E.; Zeitlin, Cary; Hassler, Donald; Weigle, Gerald E.; Boettcher, Stephan; Martin, Cesar; Wimmer-Schweingrubber, Robert

2012-01-01

The Mars Science Laboratory (MSL) payload includes the Radiation Assessment Detector (RAD) instrument, intended to fully characterize the radiation environment for the MSL mission. The RAD instrument operations concept is intended to reduce impact to spacecraft resources and effort for the MSL operations team. By design, RAD autonomously performs regular science observations without the need for frequent commanding from the Rover Compute Element (RCE). RAD operates with pre-defined "sleep" and "observe" periods, with an adjustable duty cycle for meeting power and data volume constraints during the mission. At the start of a new science observation, RAD performs a pre-observation activity to assess count rates for selected RAD detector elements. Based on this assessment, RAD can enter "solar event" mode, in which instrument parameters (including observation duration) are selected to more effectively characterize the environment. At the end of each observation period, RAD stores a time-tagged, fixed length science data packet in its non-volatile mass memory storage. The operating cadence is defined by adjustable parameters, also stored in non-volatile memory within the instrument. Periodically, the RCE executes an on-board sequence to transfer RAD science data packets from the instrument mass storage to the MSL downlink buffer. Infrequently, the RAD instrument operating configuration is modified by updating internal parameter tables and configuration entries.

Non-volatile, high density, high speed, Micromagnet-Hall effect Random Access Memory (MHRAM)

NASA Technical Reports Server (NTRS)

Wu, Jiin C.; Katti, Romney R.; Stadler, Henry L.

1991-01-01

The micromagnetic Hall effect random access memory (MHRAM) has the potential of replacing ROMs, EPROMs, EEPROMs, and SRAMs because of its ability to achieve non-volatility, radiation hardness, high density, and fast access times, simultaneously. Information is stored magnetically in small magnetic elements (micromagnets), allowing unlimited data retention time, unlimited numbers of rewrite cycles, and inherent radiation hardness and SEU immunity, making the MHRAM suitable for ground based as well as spaceflight applications. The MHRAM device design is not affected by areal property fluctuations in the micromagnet, so high operating margins and high yield can be achieved in large scale integrated circuit (IC) fabrication. The MHRAM has short access times (less than 100 nsec). Write access time is short because on-chip transistors are used to gate current quickly, and magnetization reversal in the micromagnet can occur in a matter of a few nanoseconds. Read access time is short because the high electron mobility sensor (InAs or InSb) produces a large signal voltage in response to the fringing magnetic field from the micromagnet. High storage density is achieved since a unit cell consists only of two transistors and one micromagnet Hall effect element. By comparison, a DRAM unit cell has one transistor and one capacitor, and a SRAM unit cell has six transistors.

Signal and noise extraction from analog memory elements for neuromorphic computing.

PubMed

Gong, N; Idé, T; Kim, S; Boybat, I; Sebastian, A; Narayanan, V; Ando, T

2018-05-29

Dense crossbar arrays of non-volatile memory (NVM) can potentially enable massively parallel and highly energy-efficient neuromorphic computing systems. The key requirements for the NVM elements are continuous (analog-like) conductance tuning capability and switching symmetry with acceptable noise levels. However, most NVM devices show non-linear and asymmetric switching behaviors. Such non-linear behaviors render separation of signal and noise extremely difficult with conventional characterization techniques. In this study, we establish a practical methodology based on Gaussian process regression to address this issue. The methodology is agnostic to switching mechanisms and applicable to various NVM devices. We show tradeoff between switching symmetry and signal-to-noise ratio for HfO 2 -based resistive random access memory. Then, we characterize 1000 phase-change memory devices based on Ge 2 Sb 2 Te 5 and separate total variability into device-to-device variability and inherent randomness from individual devices. These results highlight the usefulness of our methodology to realize ideal NVM devices for neuromorphic computing.

Multilevel non-volatile data storage utilizing common current hysteresis of networked single walled carbon nanotubes

NASA Astrophysics Data System (ADS)

Hwang, Ihn; Wang, Wei; Hwang, Sun Kak; Cho, Sung Hwan; Kim, Kang Lib; Jeong, Beomjin; Huh, June; Park, Cheolmin

2016-05-01

The characteristic source-drain current hysteresis frequently observed in field-effect transistors with networked single walled carbon-nanotube (NSWNT) channels is problematic for the reliable switching and sensing performance of devices. But the two distinct current states of the hysteresis curve at a zero gate voltage can be useful for memory applications. In this work, we demonstrate a novel non-volatile transistor memory with solution-processed NSWNTs which are suitable for multilevel data programming and reading. A polymer passivation layer with a small amount of water employed on the top of the NSWNT channel serves as an efficient gate voltage dependent charge trapping and de-trapping site. A systematic investigation evidences that the water mixed in a polymer passivation solution is critical for reliable non-volatile memory operation. The optimized device is air-stable and temperature-resistive up to 80 °C and exhibits excellent non-volatile memory performance with an on/off current ratio greater than 104, a switching time less than 100 ms, data retention longer than 4000 s, and write/read endurance over 100 cycles. Furthermore, the gate voltage dependent charge injection mediated by water in the passivation layer allowed for multilevel operation of our memory in which 4 distinct current states were programmed repetitively and preserved over a long time period.The characteristic source-drain current hysteresis frequently observed in field-effect transistors with networked single walled carbon-nanotube (NSWNT) channels is problematic for the reliable switching and sensing performance of devices. But the two distinct current states of the hysteresis curve at a zero gate voltage can be useful for memory applications. In this work, we demonstrate a novel non-volatile transistor memory with solution-processed NSWNTs which are suitable for multilevel data programming and reading. A polymer passivation layer with a small amount of water employed on the top of the NSWNT channel serves as an efficient gate voltage dependent charge trapping and de-trapping site. A systematic investigation evidences that the water mixed in a polymer passivation solution is critical for reliable non-volatile memory operation. The optimized device is air-stable and temperature-resistive up to 80 °C and exhibits excellent non-volatile memory performance with an on/off current ratio greater than 104, a switching time less than 100 ms, data retention longer than 4000 s, and write/read endurance over 100 cycles. Furthermore, the gate voltage dependent charge injection mediated by water in the passivation layer allowed for multilevel operation of our memory in which 4 distinct current states were programmed repetitively and preserved over a long time period. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr00505e

Nonvolatile semiconductor memory having three dimension charge confinement

DOEpatents

Dawson, L. Ralph; Osbourn, Gordon C.; Peercy, Paul S.; Weaver, Harry T.; Zipperian, Thomas E.

1991-01-01

A layered semiconductor device with a nonvolatile three dimensional memory comprises a storage channel which stores charge carriers. Charge carriers flow laterally through the storage channel from a source to a drain. Isolation material, either a Schottky barrier or a heterojunction, located in a trench of an upper layer controllably retains the charge within the a storage portion determined by the confining means. The charge is retained for a time determined by the isolation materials' nonvolatile characteristics or until a change of voltage on the isolation material and the source and drain permit a read operation. Flow of charge through an underlying sense channel is affected by the presence of charge within the storage channel, thus the presences of charge in the memory can be easily detected.

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

PubMed

Ng, Tse Nga; Schwartz, David E; Lavery, Leah L; Whiting, Gregory L; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

A New Concept for Non-Volatile Memory: The Electric-Pulse Induced Resistive Change Effect in Colossal Magnetoresistive Thin Films

NASA Technical Reports Server (NTRS)

Liu, S. Q.; Wu, N. J.; Ignatiev, A.

2001-01-01

A novel electric pulse-induced resistive change (EPIR) effect has been found in thin film colossal magnetoresistive (CMR) materials, and has shown promise for the development of resistive, nonvolatile memory. The EPIR effect is induced by the application of low voltage (< 4 V) and short duration (< 20 ns) electrical pulses across a thin film sample of a CMR material at room temperature and under no applied magnetic field. The pulse can directly either increase or decrease the resistance of the thin film sample depending on pulse polarity. The sample resistance change has been shown to be over two orders of magnitude, and is nonvolatile after pulsing. The sample resistance can also be changed through multiple levels - as many as 50 have been shown. Such a device can provide a way for the development of a new kind of nonvolatile multiple-valued memory with high density, fast write/read speed, low power-consumption, and potential high radiation-hardness.

Modeling and simulation of floating gate nanocrystal FET devices and circuits

NASA Astrophysics Data System (ADS)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to nanocrystal charge has a strong effect on the memory characteristics. Also, the programming operation of the memory cell has been investigated. The tunneling rate from quantum well channel to quantum dot (nanocrystal) gate is calculated. The calculations include various memory parameters, wavefunctions, and energies of quantum well channel and quantum dot gate. The use of floating gate nanocrystal memory as a transistor with a programmable threshold voltage has been demonstrated. The incorporation of FG-NCFETs to design programmable integrated circuit building blocks has been discussed. This includes the design of programmable current and voltage reference circuits. Finally, we demonstrated the design of tunable gain op-amp incorporating FG-NCFETs. Programmable integrated circuit building blocks can be used in intelligent analog and digital systems.

Review of radiation effects on ReRAM devices and technology

NASA Astrophysics Data System (ADS)

Gonzalez-Velo, Yago; Barnaby, Hugh J.; Kozicki, Michael N.

2017-08-01

A review of the ionizing radiation effects on resistive random access memory (ReRAM) technology and devices is presented in this article. The review focuses on vertical devices exhibiting bipolar resistance switching, devices that have already exhibited interesting properties and characteristics for memory applications and, in particular, for non-volatile memory applications. Non-volatile memories are important devices for any type of electronic and embedded system, as they are for space applications. In such applications, specific environmental issues related to the existence of cosmic rays and Van Allen radiation belts around the Earth contribute to specific failure mechanisms related to the energy deposition induced by such ionizing radiation. Such effects are important in non-volatile memory as the current leading technology, i.e. flash-based technology, is sensitive to the total ionizing dose (TID) and single-event effects. New technologies such as ReRAM, if competing with or complementing the existing non-volatile area of memories from the point of view of performance, also have to exhibit great reliability for use in radiation environments such as space. This has driven research on the radiation effects of such ReRAM technology, on both the conductive-bridge RAM as well as the valence-change memories, or OxRAM variants of the technology. Initial characterizations of ReRAM technology showed a high degree of resilience to TID, developing researchers’ interest in characterizing such resilience as well as investigating the cause of such behavior. The state of the art of such research is reviewed in this article.

A low switching voltage organic-on-inorganic heterojunction memory element utilizing a conductive polymer fuse on a doped silicon substrate

NASA Astrophysics Data System (ADS)

Smith, Shawn; Forrest, Stephen R.

2004-06-01

We present a simple, nonvolatile, write-once-read-many-times (WORM) memory device utilizing an organic-on-inorganic heterojunction (OI-HJ) diode with a conductive polymer fuse consisting of polyethylene dioxythiophene:polysterene sulfonic acid (PEDOT:PSS) forming one side of the rectifying junction. Current transients are used to change the fuse from a conducting to a nonconducting state to record a logical "1" or "0", while the nonlinearity of the OI-HJ allows for passive matrix memory addressing. The device switches at 2 and 4 V for 50 nm thick PEDOT:PSS films on p-type Si and n-type Si, respectively. This is significantly lower than the switching voltage used in PEDOT:PSS/p-i-n Si memory elements [J. Appl Phys. 94, 7811 (2003)]. The switching results in a permanent reduction of forward-bias current by approximately five orders of magnitude. These results suggest that the OI-HJ structure has potential for use in low-cost passive matrix WORM memories for archival storage applications.

Characterization of an Autonomous Non-Volatile Ferroelectric Memory Latch

NASA Technical Reports Server (NTRS)

John, Caroline S.; MacLeod, Todd C.; Evans, Joe; Ho, Fat D.

2011-01-01

We present the electrical characterization of an autonomous non-volatile ferroelectric memory latch using the principle that when an electric field is applied to a ferroelectriccapacitor,the positive and negative remnant polarization charge states of the capacitor are denoted as either data 0 or data 1. The properties of the ferroelectric material to store an electric polarization in the absence of an electric field make the device non-volatile. Further the memory latch is autonomous as it operates with the ground, power and output node connections, without any externally clocked control line. The unique quality of this latch circuit is that it can be written when powered off. The advantages of this latch over flash memories are: a) It offers unlimited reads/writes b) works on symmetrical read/write cycles. c) The latch is asynchronous. The circuit was initially developed by Radiant Technologies Inc., Albuquerque, New Mexico.

A multilevel nonvolatile magnetoelectric memory

NASA Astrophysics Data System (ADS)

Shen, Jianxin; Cong, Junzhuang; Shang, Dashan; Chai, Yisheng; Shen, Shipeng; Zhai, Kun; Sun, Young

2016-09-01

The coexistence and coupling between magnetization and electric polarization in multiferroic materials provide extra degrees of freedom for creating next-generation memory devices. A variety of concepts of multiferroic or magnetoelectric memories have been proposed and explored in the past decade. Here we propose a new principle to realize a multilevel nonvolatile memory based on the multiple states of the magnetoelectric coefficient (α) of multiferroics. Because the states of α depends on the relative orientation between magnetization and polarization, one can reach different levels of α by controlling the ratio of up and down ferroelectric domains with external electric fields. Our experiments in a device made of the PMN-PT/Terfenol-D multiferroic heterostructure confirm that the states of α can be well controlled between positive and negative by applying selective electric fields. Consequently, two-level, four-level, and eight-level nonvolatile memory devices are demonstrated at room temperature. This kind of multilevel magnetoelectric memory retains all the advantages of ferroelectric random access memory but overcomes the drawback of destructive reading of polarization. In contrast, the reading of α is nondestructive and highly efficient in a parallel way, with an independent reading coil shared by all the memory cells.

Non-volatile resistive switching in the Mott insulator (V1-xCrx)2O3

NASA Astrophysics Data System (ADS)

Querré, M.; Tranchant, J.; Corraze, B.; Cordier, S.; Bouquet, V.; Députier, S.; Guilloux-Viry, M.; Besland, M.-P.; Janod, E.; Cario, L.

2018-05-01

The discovery of non-volatile resistive switching in Mott insulators related to an electric-field-induced insulator to metal transition (IMT) has paved the way for their use in a new type of non-volatile memories, the Mott memories. While most of the previous studies were dedicated to uncover the resistive switching mechanism and explore the memory potential of chalcogenide Mott insulators, we present here a comprehensive study of resistive switching in the canonical oxide Mott insulator (V1-xCrx)2O3. Our work demonstrates that this compound undergoes a non-volatile resistive switching under electric field. This resistive switching is induced by a Mott transition at the local scale which creates metallic domains closely related to existing phases of the temperature-pressure phase diagram of (V1-xCrx)2O3. Our work demonstrates also reversible resistive switching in (V1-xCrx)2O3 crystals and thin film devices. Preliminary performances obtained on 880 nm thick layers with 500 nm electrodes show the strong potential of Mott memories based on the Mott insulator (V1-xCrx)2O3.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vanheusden, K.; Warren, W.L.; Devine, R.A.B.

It is shown how mobile H{sup +} ions can be generated thermally inside the oxide layer of Si/SiO{sub 2}/Si structures. The technique involves only standard silicon processing steps: the nonvolatile field effect transistor (NVFET) is based on a standard MOSFET with thermally grown SiO{sub 2} capped with a poly-silicon layer. The capped thermal oxide receives an anneal at {approximately}1100 C that enables the incorporation of the mobile protons into the gate oxide. The introduction of the protons is achieved by a subsequent 500-800 C anneal in a hydrogen-containing ambient, such as forming gas (N{sub 2}:H{sub 2} 95:5). The mobile protonsmore » are stable and entrapped inside the oxide layer, and unlike alkali ions, their space-charge distribution can be controlled and rapidly rearranged at room temperature by an applied electric field. Using this principle, a standard MOS transistor can be converted into a nonvolatile memory transistor that can be switched between normally on and normally off. Switching speed, retention, endurance, and radiation tolerance data are presented showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as the floating gate technologies (e.g. Flash memory).« less

A non-volatile flip-flop based on diode-selected PCM for ultra-low power systems

NASA Astrophysics Data System (ADS)

Ye, Yong; Du, Yuan; Gao, Dan; Kang, Yong; Song, Zhitang; Chen, Bomy

2016-10-01

As the process technology is continuously shrinking, low power consumption is a major issue in VLSI Systems-on-Chip (SoCs), especially for standby-power-critical applications. Recently, the emerging CMOS-compatible non-volatile memories (NVMs), such as Phase Change Memory (PCM), have been used as on-chip storage elements, which can obtain non-volatile processing, nearly-zero standby power and instant-on capability. PCM has been considered as the best candidate for the next generation of NVMs for its low cost, high density and high resistance transformation ratio. In this paper, for the first time, we present a diode-selected PCM based non-volatile flip-flop (NVFF) which is optimized for better power consumption and process variation tolerance. With dual trench isolation process, the diode-selected PCM realizes ultra small area, which is very suitable for multi-context configuration and large scale flip-flops matrix. Since the MOS-selected PCM is hard to shrink further due to large amount of PCM write current, the proposed NVFF achieves higher power efficiency without loss of current driving capability. Using the 40nm manufacturing process, the area of the cell (1D1R) is as small as 0.016 μm2. Simulation results show that the energy consumption during the recall operation is 62 fJ with 1.1 standard supply voltage, which is reduced by 54.9% compared to the previous 2T2R based NVFF. When the supply voltage reduces to 0.7 V, the recall energy is as low as 17 fJ. With the great advantages in cell size and energy, the proposed diode-selected NVFF is very applicable and cost-effective for ULP systems.

A bi-stable nanoelectromechanical non-volatile memory based on van der Waals force

NASA Astrophysics Data System (ADS)

Soon, Bo Woon; Jiaqiang Ng, Eldwin; Qian, You; Singh, Navab; Julius Tsai, Minglin; Lee, Chengkuo

2013-07-01

By using complementary-metal-oxide-semiconductor processes, a silicon based bi-stable nanoelectromechanical non-volatile memory is fabricated and characterized. The main feature of this device is an 80 nm wide and 3 μm high silicon nanofin (SiNF) of a high aspect ratio (1:35). The switching mechanism is realized by electrostatic actuation between two lateral electrodes, i.e., terminals. Bi-stable hysteresis behavior is demonstrated when the SiNF maintains its contact to one of the two terminals by leveraging on van der Waals force even after voltage bias is turned off. The compelling results indicate that this design is promising for realization of high density non-volatile memory application due to its nano-scale footprint and zero on-hold power consumption.

BLACKCOMB2: Hardware-software co-design for non-volatile memory in exascale systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mudge, Trevor

This work was part of a larger project, Blackcomb2, centered at Oak Ridge National Labs (Jeff Vetter PI) to investigate the opportunities for replacing or supplementing DRAM main memory with nonvolatile memory (NVmemory) in Exascale memory systems. The goal was to reduce the energy consumed by in future supercomputer memory systems and to improve their resiliency. Building on the accomplishments of the original Blackcomb Project, funded in 2010, the goal for Blackcomb2 was to identify, evaluate, and optimize the most promising emerging memory technologies, architecture hardware and software technologies, which are essential to provide the necessary memory capacity, performance, resilience,more » and energy efficiency in Exascale systems. Capacity and energy are the key drivers.« less

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

PubMed Central

Ng, Tse Nga; Schwartz, David E.; Lavery, Leah L.; Whiting, Gregory L.; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic. PMID:22900143

Programmable Analog Memory Resistors For Electronic Neural Networks

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni; Thakoor, Sarita; Daud, Taher; Thakoor, Anilkumar P.

1990-01-01

Electrical resistance of new solid-state device altered repeatedly by suitable control signals, yet remains at steady value when control signal removed. Resistance set at low value ("on" state), high value ("off" state), or at any convenient intermediate value and left there until new value desired. Circuits of this type particularly useful in nonvolatile, associative electronic memories based on models of neural networks. Such programmable analog memory resistors ideally suited as synaptic interconnects in "self-learning" neural nets. Operation of device depends on electrochromic property of WO3, which when pure is insulator. Potential uses include nonvolatile, erasable, electronically programmable read-only memories.

Low latency and persistent data storage

DOEpatents

Fitch, Blake G; Franceschini, Michele M; Jagmohan, Ashish; Takken, Todd E

2014-02-18

Persistent data storage is provided by a method that includes receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

Nonvolatile GaAs Random-Access Memory

NASA Technical Reports Server (NTRS)

Katti, Romney R.; Stadler, Henry L.; Wu, Jiin-Chuan

1994-01-01

Proposed random-access integrated-circuit electronic memory offers nonvolatile magnetic storage. Bits stored magnetically and read out with Hall-effect sensors. Advantages include short reading and writing times and high degree of immunity to both single-event upsets and permanent damage by ionizing radiation. Use of same basic material for both transistors and sensors simplifies fabrication process, with consequent benefits in increased yield and reduced cost.

From Secure Memories to Smart Card Security

NASA Astrophysics Data System (ADS)

Handschuh, Helena; Trichina, Elena

Non-volatile memory is essential in most embedded security applications. It will store the key and other sensitive materials for cryptographic and security applications. In this chapter, first an overview is given of current flash memory architectures. Next the standard security features which form the basis of so-called secure memories are described in more detail. Smart cards are a typical embedded application that is very vulnerable to attacks and that at the same time has a high need for secure non-volatile memory. In the next part of this chapter, the secure memories of so-called flash-based high-density smart cards are described. It is followed by a detailed analysis of what the new security challenges for such objects are.

Nonvolatile memory chips: critical technology for high-performance recce systems

NASA Astrophysics Data System (ADS)

Kaufman, Bruce

2000-11-01

Airborne recce systems universally require nonvolatile storage of recorded data. Both present and next generation designs make use of flash memory chips. Flash memory devices are in high volume use for a variety of commercial products ranging form cellular phones to digital cameras. Fortunately, commercial applications call for increasing capacities and fast write times. These parameters are important to the designer of recce recorders. Of economic necessity COTS devices are used in recorders that must perform in military avionics environments. Concurrently, recording rates are moving to $GTR10Gb/S. Thus to capture imagery for even a few minutes of record time, tactically meaningful solid state recorders will require storage capacities in the 100s of Gbytes. Even with memory chip densities at present day 512Mb, such capacities require thousands of chips. The demands on packaging technology are daunting. This paper will consider the differing flash chip architectures, both available and projected and discuss the impact on recorder architecture and performance. Emerging nonvolatile memory technologies, FeRAM AND MIRAM will be reviewed with regard to their potential use in recce recorders.

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

PubMed

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

NAND FLASH Radiation Tolerant Intelligent Memory Stack (RTIMS FLASH)

NASA Astrophysics Data System (ADS)

Sellier, Charles; Wang, Pierre

2014-08-01

The NAND Flash Radiation Tolerant and Intelligent Memory Stack (RTIMS FLASH) is a User's Friendly, Plug-and- Play and Radiation Protected high density NAND Flash Memory. It provides a very high density, radiation hardened by design and non-volatile memory module suitable for all space applications such as commercial or scientific geo-stationary missions, earth observation, navigation, manned space vehicles and deep space scientific exploration. The Intelligent Memory Module embeds a very high density of non-volatile NAND Flash memory and one Intelligent Flash Memory Controller (FMC). The FMC provides the module with a full protection against the radiation effects such as SEL, SEFI and SEU. It's also granting the module with bad block immunity as well as high level service functions that will benefit to the user's applications.

On the origin of resistive switching volatility in Ni/TiO{sub 2}/Ni stacks

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cortese, Simone, E-mail: simone.cortese@soton.ac.uk; Trapatseli, Maria; Khiat, Ali

2016-08-14

Resistive switching and resistive random access memories have attracted huge interest for next generation nonvolatile memory applications, also thought to be able to overcome flash memories limitations when arranged in crossbar arrays. A cornerstone of their potential success is that the toggling between two distinct resistance states, usually a High Resistive State (HRS) and a Low Resistive State (LRS), is an intrinsic non-volatile phenomenon with the two states being thermodynamically stable. TiO{sub 2} is one of the most common materials known to support non-volatile RS. In this paper, we report a volatile resistive switching in a titanium dioxide thin filmmore » sandwiched by two nickel electrodes. The aim of this work is to understand the underlying physical mechanism that triggers the volatile effect, which is ascribed to the presence of a NiO layer at the bottom interface. The NiO layer alters the equilibrium between electric field driven filament formation and thermal enhanced ion diffusion, resulting in the volatile behaviour. Although the volatility is not ideal for non-volatile memory applications, it shows merit for access devices in crossbar arrays due to its high LRS/HRS ratio, which are also briefly discussed.« less

Epitaxial Growth of Thin Ferroelectric Polymer Films on Graphene Layer for Fully Transparent and Flexible Nonvolatile Memory.

PubMed

Kim, Kang Lib; Lee, Wonho; Hwang, Sun Kak; Joo, Se Hun; Cho, Suk Man; Song, Giyoung; Cho, Sung Hwan; Jeong, Beomjin; Hwang, Ihn; Ahn, Jong-Hyun; Yu, Young-Jun; Shin, Tae Joo; Kwak, Sang Kyu; Kang, Seok Ju; Park, Cheolmin

2016-01-13

Enhancing the device performance of organic memory devices while providing high optical transparency and mechanical flexibility requires an optimized combination of functional materials and smart device architecture design. However, it remains a great challenge to realize fully functional transparent and mechanically durable nonvolatile memory because of the limitations of conventional rigid, opaque metal electrodes. Here, we demonstrate ferroelectric nonvolatile memory devices that use graphene electrodes as the epitaxial growth substrate for crystalline poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) polymer. The strong crystallographic interaction between PVDF-TrFE and graphene results in the orientation of the crystals with distinct symmetry, which is favorable for polarization switching upon the electric field. The epitaxial growth of PVDF-TrFE on a graphene layer thus provides excellent ferroelectric performance with high remnant polarization in metal/ferroelectric polymer/metal devices. Furthermore, a fully transparent and flexible array of ferroelectric field effect transistors was successfully realized by adopting transparent poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] semiconducting polymer.

Low latency and persistent data storage

DOEpatents

Fitch, Blake G; Franceschini, Michele M; Jagmohan, Ashish; Takken, Todd

2014-11-04

Persistent data storage is provided by a computer program product that includes computer program code configured for receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

NASA Astrophysics Data System (ADS)

Han, Jinhua; Wang, Wei; Ying, Jun; Xie, Wenfa

2014-01-01

An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

A non-destructive crossbar architecture of multi-level memory-based resistor

NASA Astrophysics Data System (ADS)

Sahebkarkhorasani, Seyedmorteza

Nowadays, researchers are trying to shrink the memory cell in order to increase the capacity of the memory system and reduce the hardware costs. In recent years, there has been a revolution in electronics by using fundamentals of physics to build a new memory for computer application in order to increase the capacity and decrease the power consumption. Increasing the capacity of the memory causes a growth in the chip area. From 1971 to 2012 semiconductor manufacturing process improved from 6mum to 22 mum. In May 2008, S.Williams stated that "it is time to stop shrinking". In his paper, he declared that the process of shrinking memory element has recently become very slow and it is time to use another alternative in order to create memory elements [9]. In this project, we present a new design of a memory array using the new element named Memristor [3]. Memristor is a two-terminal passive electrical element that relates the charge and magnetic flux to each other. The device remained unknown since 1971 when it was discovered by Chua and introduced as the fourth fundamental passive element like capacitor, inductor and resistor [3]. Memristor has a dynamic resistance and it can retain its previous value even after disconnecting the power supply. Due to this interesting behavior of the Memristor, it can be a good replacement for all of the Non-Volatile Memories (NVMs) in the near future. Combination of this newly introduced element with the nanowire crossbar architecture would be a great structure which is called Crossbar Memristor. Some frameworks have recently been introduced in literature that utilized Memristor crossbar array, but there are many challenges to implement the Memristor crossbar array due to fabrication and device limitations. In this work, we proposed a simple design of Memristor crossbar array architecture which uses input feedback in order to preserve its data after each read operation.

Nitrogen-doped partially reduced graphene oxide rewritable nonvolatile memory.

PubMed

Seo, Sohyeon; Yoon, Yeoheung; Lee, Junghyun; Park, Younghun; Lee, Hyoyoung

2013-04-23

As memory materials, two-dimensional (2D) carbon materials such as graphene oxide (GO)-based materials have attracted attention due to a variety of advantageous attributes, including their solution-processability and their potential for highly scalable device fabrication for transistor-based memory and cross-bar memory arrays. In spite of this, the use of GO-based materials has been limited, primarily due to uncontrollable oxygen functional groups. To induce the stable memory effect by ionic charges of a negatively charged carboxylic acid group of partially reduced graphene oxide (PrGO), a positively charged pyridinium N that served as a counterion to the negatively charged carboxylic acid was carefully introduced on the PrGO framework. Partially reduced N-doped graphene oxide (PrGODMF) in dimethylformamide (DMF) behaved as a semiconducting nonvolatile memory material. Its optical energy band gap was 1.7-2.1 eV and contained a sp2 C═C framework with 45-50% oxygen-functionalized carbon density and 3% doped nitrogen atoms. In particular, rewritable nonvolatile memory characteristics were dependent on the proportion of pyridinum N, and as the proportion of pyridinium N atom decreased, the PrGODMF film lost memory behavior. Polarization of charged PrGODMF containing pyridinium N and carboxylic acid under an electric field produced N-doped PrGODMF memory effects that followed voltage-driven rewrite-read-erase-read processes.

Anisotropic modulation of magnetic properties and the memory effect in a wide-band (011)-Pr0.7Sr0.3MnO3/PMN-PT heterostructure.

PubMed

Zhao, Ying-Ying; Wang, Jing; Kuang, Hao; Hu, Feng-Xia; Liu, Yao; Wu, Rong-Rong; Zhang, Xi-Xiang; Sun, Ji-Rong; Shen, Bao-Gen

2015-04-24

Memory effect of electric-field control on magnetic behavior in magnetoelectric composite heterostructures has been a topic of interest for a long time. Although the piezostrain and its transfer across the interface of ferroelectric/ferromagnetic films are known to be important in realizing magnetoelectric coupling, the underlying mechanism for nonvolatile modulation of magnetic behaviors remains a challenge. Here, we report on the electric-field control of magnetic properties in wide-band (011)-Pr0.7Sr0.3MnO3/0.7Pb(Mg1/3Nb2/3)O3-0.3PbTiO3 heterostructures. By introducing an electric-field-induced in-plane anisotropic strain field during the cooling process from room temperature, we observe an in-plane anisotropic, nonvolatile modulation of magnetic properties in a wide-band Pr0.7Sr0.3MnO3 film at low temperatures. We attribute this anisotropic memory effect to the preferential seeding and growth of ferromagnetic (FM) domains under the anisotropic strain field. In addition, we find that the anisotropic, nonvolatile modulation of magnetic properties gradually diminishes as the temperature approaches FM transition, indicating that the nonvolatile memory effect is temperature dependent. By taking into account the competition between thermal energy and the potential barrier of the metastable magnetic state induced by the anisotropic strain field, this distinct memory effect is well explained, which provides a promising approach for designing novel electric-writing magnetic memories.

Different importance of the volatile and non-volatile fractions of an olfactory signature for individual social recognition in rats versus mice and short-term versus long-term memory.

PubMed

Noack, Julia; Richter, Karin; Laube, Gregor; Haghgoo, Hojjat Allah; Veh, Rüdiger W; Engelmann, Mario

2010-11-01

When tested in the olfactory cued social recognition/discrimination test, rats and mice differ in their retention of a recognition memory for a previously encountered conspecific juvenile: Rats are able to recognize a given juvenile for approximately 45 min only whereas mice show not only short-term, but also long-term recognition memory (≥ 24 h). Here we modified the social recognition/social discrimination procedure to investigate the neurobiological mechanism(s) underlying the species differences. We presented a conspecific juvenile repeatedly to the experimental subjects and monitored the investigation duration as a measure for recognition. Presentation of only the volatile fraction of the juvenile olfactory signature was sufficient for both short- and long-term recognition in mice but not rats. Applying additional volatile, mono-molecular odours to the "to be recognized" juveniles failed to affect short-term memory in both species, but interfered with long-term recognition in mice. Finally immunocytochemical analysis of c-Fos as a marker for cellular activation, revealed that juvenile exposure stimulated areas involved in the processing of olfactory signals in both the main and the accessory olfactory bulb in mice. In rats, we measured an increased c-Fos synthesis almost exclusively in cells of the accessory olfactory bulb. Our data suggest that the species difference in the retention of social recognition memory is based on differences in the processing of the volatile versus non-volatile fraction of the individuals' olfactory signature. The non-volatile fraction is sufficient for retaining a short-term social memory only. Long-term social memory - as observed in mice - requires a processing of both the volatile and non-volatile fractions of the olfactory signature. Copyright © 2010 Elsevier Inc. All rights reserved.

Reconfigurable Electronics and Non-Volatile Memory Research

DTIC Science & Technology

2011-10-14

Sources of metal dopants were elemental metals and as well as, metal-Se compounds, and there was no evident difference in the measured Raman and Electron...similar in nature. Intensity of the most of the sample reduces with dopant concentration. This is due to the reduction in Ge-Ge and Ge-Se bonds as...the metal is incorporated into the glass. The metal dopant atoms will bond with the Se atoms [5] reducing the number of Se atoms that are available

Short-Term Plasticity and Long-Term Potentiation in Magnetic Tunnel Junctions: Towards Volatile Synapses

NASA Astrophysics Data System (ADS)

Sengupta, Abhronil; Roy, Kaushik

2016-02-01

Synaptic memory is considered to be the main element responsible for learning and cognition in humans. Although traditionally nonvolatile long-term plasticity changes are implemented in nanoelectronic synapses for neuromorphic applications, recent studies in neuroscience reveal that biological synapses undergo metastable volatile strengthening followed by a long-term strengthening provided that the frequency of the input stimulus is sufficiently high. Such "memory strengthening" and "memory decay" functionalities can potentially lead to adaptive neuromorphic architectures. In this paper, we demonstrate the close resemblance of the magnetization dynamics of a magnetic tunnel junction (MTJ) to short-term plasticity and long-term potentiation observed in biological synapses. We illustrate that, in addition to the magnitude and duration of the input stimulus, the frequency of the stimulus plays a critical role in determining long-term potentiation of the MTJ. Such MTJ synaptic memory arrays can be utilized to create compact, ultrafast, and low-power intelligent neural systems.

Spin torque switching of 20 nm magnetic tunnel junctions with perpendicular anisotropy

NASA Astrophysics Data System (ADS)

Gajek, M.; Nowak, J. J.; Sun, J. Z.; Trouilloud, P. L.; O'Sullivan, E. J.; Abraham, D. W.; Gaidis, M. C.; Hu, G.; Brown, S.; Zhu, Y.; Robertazzi, R. P.; Gallagher, W. J.; Worledge, D. C.

2012-03-01

Spin-transfer torque magnetic random access memory (STT-MRAM) is one of the most promising emerging non-volatile memory technologies. MRAM has so far been demonstrated with a unique combination of density, speed, and non-volatility in a single chip, however, without the capability to replace any single mainstream memory. In this paper, we demonstrate the basic physics of spin torque switching in 20 nm diameter magnetic tunnel junctions with perpendicular magnetic anisotropy materials. This deep scaling capability clearly indicates the STT MRAM device itself may be suitable for integration at much higher densities than previously proven.

Evaluation of Recent Technologies of Nonvolatile RAM

NASA Astrophysics Data System (ADS)

Nuns, Thierry; Duzellier, Sophie; Bertrand, Jean; Hubert, Guillaume; Pouget, Vincent; Darracq, FrÉdÉric; David, Jean-Pierre; Soonckindt, Sabine

2008-08-01

Two types of recent nonvolatile random access memories (NVRAM) were evaluated for radiation effects: total dose and single event upset and latch-up under heavy ions and protons. Complementary irradiation with a laser beam provides information on sensitive areas of the devices.

Nonvolatile gate effect in a ferroelectric-semiconductor quantum well.

PubMed

Stolichnov, Igor; Colla, Enrico; Setter, Nava; Wojciechowski, Tomasz; Janik, Elzbieta; Karczewski, Grzegorz

2006-12-15

Field effect transistors with ferroelectric gates would make ideal rewritable nonvolatile memories were it not for the severe problems in integrating the ferroelectric oxide directly on the semiconductor channel. We propose a powerful way to avoid these problems using a gate material that is ferroelectric and semiconducting simultaneously. First, ferroelectricity in semiconductor (Cd,Zn)Te films is proven and studied using modified piezoforce scanning probe microscopy. Then, a rewritable field effect device is demonstrated by local poling of the (Cd,Zn)Te layer of a (Cd,Zn)Te/CdTe quantum well, provoking a reversible, nonvolatile change in the resistance of the 2D electron gas. The results point to a potential new family of nanoscale one-transistor memories.

Analog Nonvolatile Computer Memory Circuits

NASA Technical Reports Server (NTRS)

MacLeod, Todd

2007-01-01

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

Characteristics of a Nonvolatile SRAM Memory Cell Utilizing a Ferroelectric Transistor

NASA Technical Reports Server (NTRS)

Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2011-01-01

The SRAM cell circuit is a standard for volatile data storage. When utilizing one or more ferroelectric transistors, the hysteresis characteristics give unique properties to the SRAM circuit, providing for investigation into the development of a nonvolatile memory cell. This paper discusses various formations of the SRAM circuit, using ferroelectric transistors, n-channel and p-channel MOSFETs, and resistive loads. With varied source and supply voltages, the effects on the timing and retention characteristics are investigated, including retention times of up to 24 hours.

Evaluation of reinitialization-free nonvolatile computer systems for energy-harvesting Internet of things applications

NASA Astrophysics Data System (ADS)

Onizawa, Naoya; Tamakoshi, Akira; Hanyu, Takahiro

2017-08-01

In this paper, reinitialization-free nonvolatile computer systems are designed and evaluated for energy-harvesting Internet of things (IoT) applications. In energy-harvesting applications, as power supplies generated from renewable power sources cause frequent power failures, data processed need to be backed up when power failures occur. Unless data are safely backed up before power supplies diminish, reinitialization processes are required when power supplies are recovered, which results in low energy efficiencies and slow operations. Using nonvolatile devices in processors and memories can realize a faster backup than a conventional volatile computer system, leading to a higher energy efficiency. To evaluate the energy efficiency upon frequent power failures, typical computer systems including processors and memories are designed using 90 nm CMOS or CMOS/magnetic tunnel junction (MTJ) technologies. Nonvolatile ARM Cortex-M0 processors with 4 kB MRAMs are evaluated using a typical computing benchmark program, Dhrystone, which shows a few order-of-magnitude reductions in energy in comparison with a volatile processor with SRAM.

Integrated, nonvolatile, high-speed analog random access memory

NASA Technical Reports Server (NTRS)

Katti, Romney R. (Inventor); Wu, Jiin-Chuan (Inventor); Stadler, Henry L. (Inventor)

1994-01-01

This invention provides an integrated, non-volatile, high-speed random access memory. A magnetically switchable ferromagnetic or ferrimagnetic layer is sandwiched between an electrical conductor which provides the ability to magnetize the magnetically switchable layer and a magneto resistive or Hall effect material which allows sensing the magnetic field which emanates from the magnetization of the magnetically switchable layer. By using this integrated three-layer form, the writing process, which is controlled by the conductor, is separated from the storage medium in the magnetic layer and from the readback process which is controlled by the magnetoresistive layer. A circuit for implementing the memory in CMOS or the like is disclosed.

Spatial profile of charge storage in organic field-effect transistor nonvolatile memory using polymer electret

NASA Astrophysics Data System (ADS)

She, Xiao-Jian; Liu, Jie; Zhang, Jing-Yu; Gao, Xu; Wang, Sui-Dong

2013-09-01

Spatial profile of the charge storage in the pentacene-based field-effect transistor nonvolatile memories using poly(2-vinyl naphthalene) electret is probed. The electron trapping into the electret after programming can be space dependent with more electron storage in the region closer to the contacts, and reducing the channel length is an effective approach to improve the memory performance. The deficient electron supply in pentacene is proposed to be responsible for the inhomogeneous electron storage in the electret. The hole trapping into the electret after erasing is spatially homogeneous, arising from the sufficient hole accumulation in the pentacene channel.

High performance nonvolatile memory devices based on Cu2-xSe nanowires

NASA Astrophysics Data System (ADS)

Wu, Chun-Yan; Wu, Yi-Liang; Wang, Wen-Jian; Mao, Dun; Yu, Yong-Qiang; Wang, Li; Xu, Jun; Hu, Ji-Gang; Luo, Lin-Bao

2013-11-01

We report on the rational synthesis of one-dimensional Cu2-xSe nanowires (NWs) via a solution method. Electrical analysis of Cu2-xSe NWs based memory device exhibits a stable and reproducible bipolar resistive switching behavior with a low set voltage (0.3-0.6 V), which can enable the device to write and erase data efficiently. Remarkably, the memory device has a record conductance switching ratio of 108, much higher than other devices ever reported. At last, a conducting filaments model is introduced to account for the resistive switching behavior. The totality of this study suggests that the Cu2-xSe NWs are promising building blocks for fabricating high-performance and low-consumption nonvolatile memory devices.

Light-Gated Memristor with Integrated Logic and Memory Functions.

PubMed

Tan, Hongwei; Liu, Gang; Yang, Huali; Yi, Xiaohui; Pan, Liang; Shang, Jie; Long, Shibing; Liu, Ming; Wu, Yihong; Li, Run-Wei

2017-11-28

Memristive devices are able to store and process information, which offers several key advantages over the transistor-based architectures. However, most of the two-terminal memristive devices have fixed functions once made and cannot be reconfigured for other situations. Here, we propose and demonstrate a memristive device "memlogic" (memory logic) as a nonvolatile switch of logic operations integrated with memory function in a single light-gated memristor. Based on nonvolatile light-modulated memristive switching behavior, a single memlogic cell is able to achieve optical and electrical mixed basic Boolean logic of reconfigurable "AND", "OR", and "NOT" operations. Furthermore, the single memlogic cell is also capable of functioning as an optical adder and digital-to-analog converter. All the memlogic outputs are memristive for in situ data storage due to the nonvolatile resistive switching and persistent photoconductivity effects. Thus, as a memdevice, the memlogic has potential for not only simplifying the programmable logic circuits but also building memristive multifunctional optoelectronics.

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

NASA Astrophysics Data System (ADS)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

NASA Astrophysics Data System (ADS)

Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui

2016-07-01

Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

Resistive switching characteristics of polymer non-volatile memory devices in a scalable via-hole structure.

PubMed

Kim, Tae-Wook; Choi, Hyejung; Oh, Seung-Hwan; Jo, Minseok; Wang, Gunuk; Cho, Byungjin; Kim, Dong-Yu; Hwang, Hyunsang; Lee, Takhee

2009-01-14

The resistive switching characteristics of polyfluorene-derivative polymer material in a sub-micron scale via-hole device structure were investigated. The scalable via-hole sub-microstructure was fabricated using an e-beam lithographic technique. The polymer non-volatile memory devices varied in size from 40 x 40 microm(2) to 200 x 200 nm(2). From the scaling of junction size, the memory mechanism can be attributed to the space-charge-limited current with filamentary conduction. Sub-micron scale polymer memory devices showed excellent resistive switching behaviours such as a large ON/OFF ratio (I(ON)/I(OFF) approximately 10(4)), excellent device-to-device switching uniformity, good sweep endurance, and good retention times (more than 10,000 s). The successful operation of sub-micron scale memory devices of our polyfluorene-derivative polymer shows promise to fabricate high-density polymer memory devices.

A fast and low-power microelectromechanical system-based non-volatile memory device

PubMed Central

Lee, Sang Wook; Park, Seung Joo; Campbell, Eleanor E. B.; Park, Yung Woo

2011-01-01

Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices. PMID:21364559

Giant Electroresistance in Edge Metal-Insulator-Metal Tunnel Junctions Induced by Ferroelectric Fringe Fields

PubMed Central

Jung, Sungchul; Jeon, Youngeun; Jin, Hanbyul; Lee, Jung-Yong; Ko, Jae-Hyeon; Kim, Nam; Eom, Daejin; Park, Kibog

2016-01-01

An enormous amount of research activities has been devoted to developing new types of non-volatile memory devices as the potential replacements of current flash memory devices. Theoretical device modeling was performed to demonstrate that a huge change of tunnel resistance in an Edge Metal-Insulator-Metal (EMIM) junction of metal crossbar structure can be induced by the modulation of electric fringe field, associated with the polarization reversal of an underlying ferroelectric layer. It is demonstrated that single three-terminal EMIM/Ferroelectric structure could form an active memory cell without any additional selection devices. This new structure can open up a way of fabricating all-thin-film-based, high-density, high-speed, and low-power non-volatile memory devices that are stackable to realize 3D memory architecture. PMID:27476475

High reliable and stable organic field-effect transistor nonvolatile memory with a poly(4-vinyl phenol) charge trapping layer based on a pn-heterojunction active layer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xiang, Lanyi; Ying, Jun; Han, Jinhua

2016-04-25

In this letter, we demonstrate a high reliable and stable organic field-effect transistor (OFET) based nonvolatile memory (NVM) with a polymer poly(4-vinyl phenol) (PVP) as the charge trapping layer. In the unipolar OFETs, the inreversible shifts of the turn-on voltage (V{sub on}) and severe degradation of the memory window (ΔV{sub on}) at programming (P) and erasing (E) voltages, respectively, block their application in NVMs. The obstacle is overcome by using a pn-heterojunction as the active layer in the OFET memory, which supplied a holes and electrons accumulating channel at the supplied P and E voltages, respectively. Both holes and electronsmore » transferring from the channels to PVP layer and overwriting the trapped charges with an opposite polarity result in the reliable bidirectional shifts of V{sub on} at P and E voltages, respectively. The heterojunction OFET exhibits excellent nonvolatile memory characteristics, with a large ΔV{sub on} of 8.5 V, desired reading (R) voltage at 0 V, reliable P/R/E/R dynamic endurance over 100 cycles and a long retention time over 10 years.« less

Inkjet-printing of non-volatile organic resistive devices and crossbar array structures

NASA Astrophysics Data System (ADS)

Sax, Stefan; Nau, Sebastian; Popovic, Karl; Bluemel, Alexander; Klug, Andreas; List-Kratochvil, Emil J. W.

2015-09-01

Due to the increasing demand for storage capacity in various electronic gadgets like mobile phones or tablets, new types of non-volatile memory devices have gained a lot of attention over the last few years. Especially multilevel conductance switching elements based on organic semiconductors are of great interest due to their relatively simple device architecture and their small feature size. Since organic semiconductors combine the electronic properties of inorganic materials with the mechanical characteristics of polymers, this class of materials is suitable for solution based large area device preparation techniques. Consequently, inkjet based deposition techniques are highly capable of facing preparation related challenges. By gradually replacing the evaporated electrodes with inkjet printed silver, the preparation related influence onto device performance parameters such as the ON/OFF ratio was investigated with IV measurements and high resolution transmission electron microscopy. Due to the electrode surface roughness the solvent load during the printing of the top electrode as well as organic layer inhomogeneity's the utilization in array applications is hampered. As a prototypical example a 1diode-1resistor element and a 2×2 subarray from 5×5 array matrix were fully characterized demonstrating the versatility of inkjet printing for device preparation.

Static Behavior of Chalcogenide Based Programmable Metallization Cells

NASA Astrophysics Data System (ADS)

Rajabi, Saba

Nonvolatile memory (NVM) technologies have been an integral part of electronic systems for the past 30 years. The ideal non-volatile memory have minimal physical size, energy usage, and cost while having maximal speed, capacity, retention time, and radiation hardness. A promising candidate for next-generation memory is ion-conducting bridging RAM which is referred to as programmable metallization cell (PMC), conductive bridge RAM (CBRAM), or electrochemical metallization memory (ECM), which is likely to surpass flash memory in all the ideal memory characteristics. A comprehensive physics-based model is needed to completely understand PMC operation and assist in design optimization. To advance the PMC modeling effort, this thesis presents a precise physical model parameterizing materials associated with both ion-rich and ion-poor layers of the PMC's solid electrolyte, so that captures the static electrical behavior of the PMC in both its low-resistance on-state (LRS) and high resistance off-state (HRS). The experimental data is measured from a chalcogenide glass PMC designed and manufactured at ASU. The static on- and off-state resistance of a PMC device composed of a layered (Ag-rich/Ag-poor) Ge30Se70 ChG film is characterized and modeled using three dimensional simulation code written in Silvaco Atlas finite element analysis software. Calibrating the model to experimental data enables the extraction of device parameters such as material bandgaps, workfunctions, density of states, carrier mobilities, dielectric constants, and affinities. The sensitivity of our modeled PMC to the variation of its prominent achieved material parameters is examined on the HRS and LRS impedance behavior. The obtained accurate set of material parameters for both Ag-rich and Ag-poor ChG systems and process variation verification on electrical characteristics enables greater fidelity in PMC device simulation, which significantly enhances our ability to understand the underlying physics of ChG-based resistive switching memory.

Compact Holographic Data Storage

NASA Technical Reports Server (NTRS)

Chao, T. H.; Reyes, G. F.; Zhou, H.

2001-01-01

NASA's future missions would require massive high-speed onboard data storage capability to Space Science missions. For Space Science, such as the Europa Lander mission, the onboard data storage requirements would be focused on maximizing the spacecraft's ability to survive fault conditions (i.e., no loss in stored science data when spacecraft enters the 'safe mode') and autonomously recover from them during NASA's long-life and deep space missions. This would require the development of non-volatile memory. In order to survive in the stringent environment during space exploration missions, onboard memory requirements would also include: (1) survive a high radiation environment (1 Mrad), (2) operate effectively and efficiently for a very long time (10 years), and (3) sustain at least a billion write cycles. Therefore, memory technologies requirements of NASA's Earth Science and Space Science missions are large capacity, non-volatility, high-transfer rate, high radiation resistance, high storage density, and high power efficiency. JPL, under current sponsorship from NASA Space Science and Earth Science Programs, is developing a high-density, nonvolatile and rad-hard Compact Holographic Data Storage (CHDS) system to enable large-capacity, high-speed, low power consumption, and read/write of data in a space environment. The entire read/write operation will be controlled with electrooptic mechanism without any moving parts. This CHDS will consist of laser diodes, photorefractive crystal, spatial light modulator, photodetector array, and I/O electronic interface. In operation, pages of information would be recorded and retrieved with random access and high-speed. The nonvolatile, rad-hard characteristics of the holographic memory will provide a revolutionary memory technology meeting the high radiation challenge facing the Europa Lander mission. Additional information is contained in the original extended abstract.

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

NASA Astrophysics Data System (ADS)

Nedic, Stanko; Tea Chun, Young; Hong, Woong-Ki; Chu, Daping; Welland, Mark

2014-01-01

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ˜16.5 V, a high drain current on/off ratio of ˜105, a gate leakage current below ˜300 pA, and excellent retention characteristics for over 104 s.

Results from On-Orbit Testing of the Fram Memory Test Experiment on the Fastsat Micro-Satellite

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Sims, W. Herb; Varnavas, Kosta A.; Ho, Fat D.

2011-01-01

NASA is planning on going beyond Low Earth orbit with manned exploration missions. The radiation environment for most Low Earth orbit missions is harsher than at the Earth's surface but much less harsh than deep space. Development of new electronics is needed to meet the requirements of high performance, radiation tolerance, and reliability. The need for both Volatile and Non-volatile memory has been identified. Emerging Non-volatile memory technologies (FRAM, C-RAM,M-RAM, R-RAM, Radiation Tolerant FLASH, SONOS, etc.) need to be investigated for use in Space missions. An opportunity arose to fly a small memory experiment on a high inclination satellite (FASTSAT). An off-the-shelf 512K Ramtron FRAM was chosen to be tested in the experiment.

Nonvolatile Analog Memory

NASA Technical Reports Server (NTRS)

MacLeod, Todd C. (Inventor)

2007-01-01

A nonvolatile analog memory uses pairs of ferroelectric field effect transistors (FFETs). Each pair is defined by a first FFET and a second FFET. When an analog value is to be stored in one of the pairs, the first FFET has a saturation voltage applied thereto, and the second FFET has a storage voltage applied thereto that is indicative of the analog value. The saturation and storage voltages decay over time in accordance with a known decay function that is used to recover the original analog value when the pair of FFETs is read.

A study of selenium nanoparticles as charge storage element for flexible semi-transparent memory devices

NASA Astrophysics Data System (ADS)

Alotaibi, Sattam; Nama Manjunatha, Krishna; Paul, Shashi

2017-12-01

Flexible Semi-Transparent electronic memory would be useful in coming years for integrated flexible transparent electronic devices. However, attaining such flexibility and semi-transparency leads to the boundaries in material composition. Thus, impeding processing speed and device performance. In this work, we present the use of inorganic stable selenium nanoparticles (Se-NPs) as a storage element and hydrogenated amorphous carbon (a-C:H) as an insulating layer in two terminal non-volatile physically flexible and semi-transparent capacitive memory devices (2T-NMDs). Furthermore, a-C:H films can be deposited at very low temperature (<40° C) on a variety of substrates (including many kinds of plastic substrates) by an industrial technique called Plasma Enhanced Chemical Vapour Deposition (PECVD) which is available in many existing fabrication labs. Self-assembled Se-NPs has several unique features including deposition at room temperature by simple vacuum thermal evaporation process without the need for further optimisation. This facilitates the fabrication of memory on a flexible substrate. Moreover, the memory behaviour of the Se-NPs was found to be more distinct than those of the semiconductor and metal nanostructures due to higher work function compared to the commonly used semiconductor and metal species. The memory behaviour was observed from the hysteresis of current-voltage (I-V) measurements while the two distinguishable electrical conductivity states (;0; and "1") were studied by current-time (I-t) measurements.

Programmable computing with a single magnetoresistive element

NASA Astrophysics Data System (ADS)

Ney, A.; Pampuch, C.; Koch, R.; Ploog, K. H.

2003-10-01

The development of transistor-based integrated circuits for modern computing is a story of great success. However, the proved concept for enhancing computational power by continuous miniaturization is approaching its fundamental limits. Alternative approaches consider logic elements that are reconfigurable at run-time to overcome the rigid architecture of the present hardware systems. Implementation of parallel algorithms on such `chameleon' processors has the potential to yield a dramatic increase of computational speed, competitive with that of supercomputers. Owing to their functional flexibility, `chameleon' processors can be readily optimized with respect to any computer application. In conventional microprocessors, information must be transferred to a memory to prevent it from getting lost, because electrically processed information is volatile. Therefore the computational performance can be improved if the logic gate is additionally capable of storing the output. Here we describe a simple hardware concept for a programmable logic element that is based on a single magnetic random access memory (MRAM) cell. It combines the inherent advantage of a non-volatile output with flexible functionality which can be selected at run-time to operate as an AND, OR, NAND or NOR gate.

Opportunities for nonvolatile memory systems in extreme-scale high-performance computing

DOE PAGES

Vetter, Jeffrey S.; Mittal, Sparsh

2015-01-12

For extreme-scale high-performance computing systems, system-wide power consumption has been identified as one of the key constraints moving forward, where DRAM main memory systems account for about 30 to 50 percent of a node's overall power consumption. As the benefits of device scaling for DRAM memory slow, it will become increasingly difficult to keep memory capacities balanced with increasing computational rates offered by next-generation processors. However, several emerging memory technologies related to nonvolatile memory (NVM) devices are being investigated as an alternative for DRAM. Moving forward, NVM devices could offer solutions for HPC architectures. Researchers are investigating how to integratemore » these emerging technologies into future extreme-scale HPC systems and how to expose these capabilities in the software stack and applications. In addition, current results show several of these strategies could offer high-bandwidth I/O, larger main memory capacities, persistent data structures, and new approaches for application resilience and output postprocessing, such as transaction-based incremental checkpointing and in situ visualization, respectively.« less

Electrostatic Switching in Vertically Oriented Nanotubes for Nonvolatile Memory Applications

NASA Technical Reports Server (NTRS)

Kaul, Anupama B.; Khan, Paul; Jennings, Andrew T.; Greer, Julia R.; Megerian, Krikor G.; Allmen, Paul von

2009-01-01

We have demonstrated electrostatic switching in vertically oriented nanotubes or nanofibers, where a nanoprobe was used as the actuating electrode inside an SEM. When the nanoprobe was manipulated to be in close proximity to a single tube, switching voltages between 10 V - 40 V were observed, depending on the geometrical parameters. The turn-on transitions appeared to be much sharper than the turn-off transitions which were limited by the tube-to-probe contact resistances. In many cases, stiction forces at these dimensions were dominant, since the tube appeared stuck to the probe even after the voltage returned to 0 V, suggesting that such structures are promising for nonvolatile memory applications. The stiction effects, to some extent, can be adjusted by engineering the switch geometry appropriately. Nanoscale mechanical measurements were also conducted on the tubes using a custom-built anoindentor inside an SEM, from which preliminary material parameters, such as the elastic modulus, were extracted. The mechanical measurements also revealed that the tubes appear to be well adhered to the substrate. The material parameters gathered from the mechanical measurements were then used in developing an electrostatic model of the switch using a commercially available finite-element simulator. The calculated pull-in voltages appeared to be in agreement to the experimentally obtained switching voltages to first order.

Effects of Heavy Ion Exposure on Nanocrystal Nonvolatile Memory

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; Suhail, Mohammed; Kuhn, Peter; Prinz, Erwin; Kim, Hak; LaBel, Kenneth A.

2004-01-01

We have irradiated engineering samples of Freescale 4M nonvolatile memories with heavy ions. They use Silicon nanocrystals as the storage element, rather than the more common floating gate. The irradiations were performed using the Texas A&M University cyclotron Single Event Effects Test Facility. The chips were tested in the static mode, and in the dynamic read mode, dynamic write (program) mode, and dynamic erase mode. All the errors observed appeared to be due to single, isolated bits, even in the program and erase modes. These errors appeared to be related to the micro-dose mechanism. All the errors corresponded to the loss of electrons from a programmed cell. The underlying physical mechanisms will be discussed in more detail later. There were no errors, which could be attributed to malfunctions of the control circuits. At the highest LET used in the test (85 MeV/mg/sq cm), however, there appeared to be a failure due to gate rupture. Failure analysis is being conducted to confirm this conclusion. There was no unambiguous evidence of latchup under any test conditions. Generally, the results on the nanocrystal technology compare favorably with results on currently available commercial floating gate technology, indicating that the technology is promising for future space applications, both civilian and military.

Direct observation of conductive filament formation in Alq3 based organic resistive memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Busby, Y., E-mail: yan.busby@unamur.be; Pireaux, J.-J.; Nau, S.

2015-08-21

This work explores resistive switching mechanisms in non-volatile organic memory devices based on tris(8-hydroxyquinolie)aluminum (Alq{sub 3}). Advanced characterization tools are applied to investigate metal diffusion in ITO/Alq{sub 3}/Ag memory device stacks leading to conductive filament formation. The morphology of Alq{sub 3}/Ag layers as a function of the metal evaporation conditions is studied by X-ray reflectivity, while depth profile analysis with X-ray photoelectron spectroscopy and time-of-flight secondary ion mass spectrometry is applied to characterize operational memory elements displaying reliable bistable current-voltage characteristics. 3D images of the distribution of silver inside the organic layer clearly point towards the existence of conductive filamentsmore » and allow for the identification of the initial filament formation and inactivation mechanisms during switching of the device. Initial filament formation is suggested to be driven by field assisted diffusion of silver from abundant structures formed during the top electrode evaporation, whereas thermochemical effects lead to local filament inactivation.« less

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement

PubMed Central

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates. PMID:26763827

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement.

PubMed

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates.

Multi-floor cascading ferroelectric nanostructures: multiple data writing-based multi-level non-volatile memory devices.

PubMed

Hyun, Seung; Kwon, Owoong; Lee, Bom-Yi; Seol, Daehee; Park, Beomjin; Lee, Jae Yong; Lee, Ju Hyun; Kim, Yunseok; Kim, Jin Kon

2016-01-21

Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process.

Peroxide induced volatile and non-volatile switching behavior in ZnO-based electrochemical metallization memory cell

NASA Astrophysics Data System (ADS)

Mangasa Simanjuntak, Firman; Chandrasekaran, Sridhar; Pattanayak, Bhaskar; Lin, Chun-Chieh; Tseng, Tseung-Yuen

2017-09-01

We explore the use of cubic-zinc peroxide (ZnO2) as a switching material for electrochemical metallization memory (ECM) cell. The ZnO2 was synthesized with a simple peroxide surface treatment. Devices made without surface treatment exhibits a high leakage current due to the self-doped nature of the hexagonal-ZnO material. Thus, its switching behavior can only be observed when a very high current compliance is employed. The synthetic ZnO2 layer provides a sufficient resistivity to the Cu/ZnO2/ZnO/ITO devices. The high resistivity of ZnO2 encourages the formation of a conducting bridge to activate the switching behavior at a lower operation current. Volatile and non-volatile switching behaviors with sufficient endurance and an adequate memory window are observed in the surface-treated devices. The room temperature retention of more than 104 s confirms the non-volatility behavior of the devices. In addition, our proposed device structure is able to work at a lower operation current among other reported ZnO-based ECM cells.

Kinetics of Domain Switching by Mechanical and Electrical Stimulation in Relaxor-Based Ferroelectrics

NASA Astrophysics Data System (ADS)

Chen, Zibin; Hong, Liang; Wang, Feifei; An, Xianghai; Wang, Xiaolin; Ringer, Simon; Chen, Long-Qing; Luo, Haosu; Liao, Xiaozhou

2017-12-01

Ferroelectric materials have been extensively explored for applications in high-density nonvolatile memory devices because of their ferroelectric-ferroelastic domain-switching behavior under electric loading or mechanical stress. However, the existence of ferroelectric and ferroelastic backswitching would cause significant data loss, which affects the reliability of data storage. Here, we apply in situ transmission electron microscopy and phase-field modeling to explore the unique ferroelastic domain-switching kinetics and the origin of this in relaxor-based Pb (Mg1 /3Nb2 /3)O3-33 % PbTiO3 single-crystal pillars under electrical and mechanical stimulations. Results showed that the electric-mechanical hysteresis loop shifted for relaxor-based single-crystal pillars because of the low energy levels of domains in the material and the constraint on the pillars, resulting in various mechanically reversible and irreversible domain-switching states. The phenomenon can potentially be used for advanced bit writing and reading in nonvolatile memories, which effectively overcomes the backswitching problem and broadens the types of ferroelectric materials for nonvolatile memory applications.

Garnet Random-Access Memory

NASA Technical Reports Server (NTRS)

Katti, Romney R.

1995-01-01

Random-access memory (RAM) devices of proposed type exploit magneto-optical properties of magnetic garnets exhibiting perpendicular anisotropy. Magnetic writing and optical readout used. Provides nonvolatile storage and resists damage by ionizing radiation. Because of basic architecture and pinout requirements, most likely useful as small-capacity memory devices.

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations.

PubMed

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-27

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

NASA Astrophysics Data System (ADS)

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-01

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Ferroelectric FET for nonvolatile memory application with two-dimensional MoSe2 channels

NASA Astrophysics Data System (ADS)

Wang, Xudong; Liu, Chunsen; Chen, Yan; Wu, Guangjian; Yan, Xiao; Huang, Hai; Wang, Peng; Tian, Bobo; Hong, Zhenchen; Wang, Yutao; Sun, Shuo; Shen, Hong; Lin, Tie; Hu, Weida; Tang, Minghua; Zhou, Peng; Wang, Jianlu; Sun, Jinglan; Meng, Xiangjian; Chu, Junhao; Li, Zheng

2017-06-01

Graphene and other two-dimensional materials have received considerable attention regarding their potential applications in nano-electronics. Here, we report top-gate nonvolatile memory field-effect transistors (FETs) with different layers of MoSe2 nanosheets channel gated by ferroelectric film. The conventional gate dielectric of FETs was replaced by a ferroelectric thin film that provides a ferroelectric polarization electric field, and therefore defined as an Fe-FET where the poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) was used as the gate dielectric. Among the devices with MoSe2 channels of different thicknesses, the device with a single layer of MoSe2 exhibited a large hysteresis of electronic transport with an over 105 write/erase ratio, and displayed excellent retention and endurance performance. The possible mechanism of the device’s good properties was qualitatively analyzed using band theory. Additionally, a comprehensive study comparing the memory properties of MoSe2 channels of different thicknesses is presented. Increasing the numbers of MoSe2 layers was found to cause a reduced memory window. However, MoSe2 thickness of 5 nm yielded a write/erase ratio of more than 103. The results indicate that, based on a Fe-FET structure, the combination of two-dimensional semiconductors and organic ferroelectric gate dielectrics shows good promise for future applications in nonvolatile ferroelectric memory.

All oxide semiconductor-based bidirectional vertical p-n-p selectors for 3D stackable crossbar-array electronics

PubMed Central

Bae, Yoon Cheol; Lee, Ah Rahm; Baek, Gwang Ho; Chung, Je Bock; Kim, Tae Yoon; Park, Jea Gun; Hong, Jin Pyo

2015-01-01

Three-dimensional (3D) stackable memory devices including nano-scaled crossbar array are central for the realization of high-density non-volatile memory electronics. However, an essential sneak path issue affecting device performance in crossbar array remains a bottleneck and a grand challenge. Therefore, a suitable bidirectional selector as a two-way switch is required to facilitate a major breakthrough in the 3D crossbar array memory devices. Here, we show the excellent selectivity of all oxide p-/n-type semiconductor-based p-n-p open-based bipolar junction transistors as selectors in crossbar memory array. We report that bidirectional nonlinear characteristics of oxide p-n-p junctions can be highly enhanced by manipulating p-/n-type oxide semiconductor characteristics. We also propose an associated Zener tunneling mechanism that explains the unique features of our p-n-p selector. Our experimental findings are further extended to confirm the profound functionality of oxide p-n-p selectors integrated with several bipolar resistive switching memory elements working as storage nodes. PMID:26289565

Phase-change memory function of correlated electrons in organic conductors

NASA Astrophysics Data System (ADS)

Oike, H.; Kagawa, F.; Ogawa, N.; Ueda, A.; Mori, H.; Kawasaki, M.; Tokura, Y.

2015-01-01

Phase-change memory (PCM), a promising candidate for next-generation nonvolatile memories, exploits quenched glassy and thermodynamically stable crystalline states as reversibly switchable state variables. We demonstrate PCM functions emerging from a charge-configuration degree of freedom in strongly correlated electron systems. Nonvolatile reversible switching between a high-resistivity charge-crystalline (or charge-ordered) state and a low-resistivity quenched state, charge glass, is achieved experimentally via heat pulses supplied by optical or electrical means in organic conductors θ -(BEDT-TTF)2X . Switching that is one order of magnitude faster is observed in another isostructural material that requires faster cooling to kinetically avoid charge crystallization, indicating that the material's critical cooling rate can be useful guidelines for pursuing a faster correlated-electron PCM function.

Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Shun; Gao, Xu, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn; Zhong, Ya-Nan

High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio andmore » good memory retention.« less

High Performance Transparent Transistor Memory Devices Using Nano-Floating Gate of Polymer/ZnO Nanocomposites

NASA Astrophysics Data System (ADS)

Shih, Chien-Chung; Lee, Wen-Ya; Chiu, Yu-Cheng; Hsu, Han-Wen; Chang, Hsuan-Chun; Liu, Cheng-Liang; Chen, Wen-Chang

2016-02-01

Nano-floating gate memory devices (NFGM) using metal nanoparticles (NPs) covered with an insulating polymer have been considered as a promising electronic device for the next-generation nonvolatile organic memory applications NPs. However, the transparency of the device with metal NPs is restricted to 60~70% due to the light absorption in the visible region caused by the surface plasmon resonance effects of metal NPs. To address this issue, we demonstrate a novel NFGM using the blends of hole-trapping poly (9-(4-vinylphenyl) carbazole) (PVPK) and electron-trapping ZnO NPs as the charge storage element. The memory devices exhibited a remarkably programmable memory window up to 60 V during the program/erase operations, which was attributed to the trapping/detrapping of charge carriers in ZnO NPs/PVPK composite. Furthermore, the devices showed the long-term retention time (>105 s) and WRER test (>200 cycles), indicating excellent electrical reliability and stability. Additionally, the fabricated transistor memory devices exhibited a relatively high transparency of 90% at the wavelength of 500 nm based on the spray-coated PEDOT:PSS as electrode, suggesting high potential for transparent organic electronic memory devices.

Phase-change materials for non-volatile memory devices: from technological challenges to materials science issues

NASA Astrophysics Data System (ADS)

Noé, Pierre; Vallée, Christophe; Hippert, Françoise; Fillot, Frédéric; Raty, Jean-Yves

2018-01-01

Chalcogenide phase-change materials (PCMs), such as Ge-Sb-Te alloys, have shown outstanding properties, which has led to their successful use for a long time in optical memories (DVDs) and, recently, in non-volatile resistive memories. The latter, known as PCM memories or phase-change random access memories (PCRAMs), are the most promising candidates among emerging non-volatile memory (NVM) technologies to replace the current FLASH memories at CMOS technology nodes under 28 nm. Chalcogenide PCMs exhibit fast and reversible phase transformations between crystalline and amorphous states with very different transport and optical properties leading to a unique set of features for PCRAMs, such as fast programming, good cyclability, high scalability, multi-level storage capability, and good data retention. Nevertheless, PCM memory technology has to overcome several challenges to definitively invade the NVM market. In this review paper, we examine the main technological challenges that PCM memory technology must face and we illustrate how new memory architecture, innovative deposition methods, and PCM composition optimization can contribute to further improvements of this technology. In particular, we examine how to lower the programming currents and increase data retention. Scaling down PCM memories for large-scale integration means the incorporation of the PCM into more and more confined structures and raises materials science issues in order to understand interface and size effects on crystallization. Other materials science issues are related to the stability and ageing of the amorphous state of PCMs. The stability of the amorphous phase, which determines data retention in memory devices, can be increased by doping the PCM. Ageing of the amorphous phase leads to a large increase of the resistivity with time (resistance drift), which has up to now hindered the development of ultra-high multi-level storage devices. A review of the current understanding of all these issues is provided from a materials science point of view.

Radiation-Hardened Solid-State Drive

NASA Technical Reports Server (NTRS)

Sheldon, Douglas J.

2010-01-01

A method is provided for a radiationhardened (rad-hard) solid-state drive for space mission memory applications by combining rad-hard and commercial off-the-shelf (COTS) non-volatile memories (NVMs) into a hybrid architecture. The architecture is controlled by a rad-hard ASIC (application specific integrated circuit) or a FPGA (field programmable gate array). Specific error handling and data management protocols are developed for use in a rad-hard environment. The rad-hard memories are smaller in overall memory density, but are used to control and manage radiation-induced errors in the main, and much larger density, non-rad-hard COTS memory devices. Small amounts of rad-hard memory are used as error buffers and temporary caches for radiation-induced errors in the large COTS memories. The rad-hard ASIC/FPGA implements a variety of error-handling protocols to manage these radiation-induced errors. The large COTS memory is triplicated for protection, and CRC-based counters are calculated for sub-areas in each COTS NVM array. These counters are stored in the rad-hard non-volatile memory. Through monitoring, rewriting, regeneration, triplication, and long-term storage, radiation-induced errors in the large NV memory are managed. The rad-hard ASIC/FPGA also interfaces with the external computer buses.

Scientific developments of liquid crystal-based optical memory: a review

NASA Astrophysics Data System (ADS)

Prakash, Jai; Chandran, Achu; Biradar, Ashok M.

2017-01-01

The memory behavior in liquid crystals (LCs), although rarely observed, has made very significant headway over the past three decades since their discovery in nematic type LCs. It has gone from a mere scientific curiosity to application in variety of commodities. The memory element formed by numerous LCs have been protected by patents, and some commercialized, and used as compensation to non-volatile memory devices, and as memory in personal computers and digital cameras. They also have the low cost, large area, high speed, and high density memory needed for advanced computers and digital electronics. Short and long duration memory behavior for industrial applications have been obtained from several LC materials, and an LC memory with interesting features and applications has been demonstrated using numerous LCs. However, considerable challenges still exist in searching for highly efficient, stable, and long-lifespan materials and methods so that the development of useful memory devices is possible. This review focuses on the scientific and technological approach of fascinating applications of LC-based memory. We address the introduction, development status, novel design and engineering principles, and parameters of LC memory. We also address how the amalgamation of LCs could bring significant change/improvement in memory effects in the emerging field of nanotechnology, and the application of LC memory as the active component for futuristic and interesting memory devices.

Scientific developments of liquid crystal-based optical memory: a review.

PubMed

Prakash, Jai; Chandran, Achu; Biradar, Ashok M

2017-01-01

The memory behavior in liquid crystals (LCs), although rarely observed, has made very significant headway over the past three decades since their discovery in nematic type LCs. It has gone from a mere scientific curiosity to application in variety of commodities. The memory element formed by numerous LCs have been protected by patents, and some commercialized, and used as compensation to non-volatile memory devices, and as memory in personal computers and digital cameras. They also have the low cost, large area, high speed, and high density memory needed for advanced computers and digital electronics. Short and long duration memory behavior for industrial applications have been obtained from several LC materials, and an LC memory with interesting features and applications has been demonstrated using numerous LCs. However, considerable challenges still exist in searching for highly efficient, stable, and long-lifespan materials and methods so that the development of useful memory devices is possible. This review focuses on the scientific and technological approach of fascinating applications of LC-based memory. We address the introduction, development status, novel design and engineering principles, and parameters of LC memory. We also address how the amalgamation of LCs could bring significant change/improvement in memory effects in the emerging field of nanotechnology, and the application of LC memory as the active component for futuristic and interesting memory devices.

Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

NASA Astrophysics Data System (ADS)

Yamamoto, Shuu'ichirou; Shuto, Yusuke; Sugahara, Satoshi

2013-07-01

We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

Radiation Tests of Highly Scaled, High-Density, Commercial, Nonvolatile NAND Flash Memories - Update 2012

NASA Technical Reports Server (NTRS)

Irom, Farokh; Allen, Gregory R.

2012-01-01

The space radiation environment poses a certain risk to all electronic components on Earth-orbiting and planetary mission spacecraft. In recent years, there has been increased interest in the use of high-density, commercial, nonvolatile flash memories in space because of ever-increasing data volumes and strict power requirements. They are used in a wide variety of spacecraft subsystems. At one end of the spectrum, flash memories are used to store small amounts of mission-critical data such as boot code or configuration files and, at the other end, they are used to construct multi-gigabyte data recorders that record mission science data. This report examines single-event effect (SEE) and total ionizing dose (TID) response in single-level cell (SLC) 32-Gb, multi-level cell (MLC) 64-Gb, and Triple-level (TLC) 64-Gb NAND flash memories manufactured by Micron Technology with feature size of 25 nm.

Electrical and ferroelectric properties of RF sputtered PZT/SBN on silicon for non-volatile memory applications

NASA Astrophysics Data System (ADS)

Singh, Prashant; Jha, Rajesh Kumar; Singh, Rajat Kumar; Singh, B. R.

2018-02-01

We report the integration of multilayer ferroelectric film deposited by RF magnetron sputtering and explore the electrical characteristics for its application as the gate of ferroelectric field effect transistor for non-volatile memories. PZT (Pb[Zr0.35Ti0.65]O3) and SBN (SrBi2Nb2O9) ferroelectric materials were selected for the stack fabrication due to their large polarization and fatigue free properties respectively. Electrical characterization has been carried out to obtain memory window, leakage current density, PUND and endurance characteristics. Fabricated multilayer ferroelectric film capacitor structure shows large memory window of 17.73 V and leakage current density of the order 10-6 A cm-2 for the voltage sweep of -30 to +30 V. This multilayer gate stack of PZT/SBN shows promising endurance property with no degradation in the remnant polarization for the read/write iteration cycles upto 108.

Electrical reliability, multilevel data storage and mechanical stability of MoS2-PMMA nanocomposite-based non-volatile memory device

NASA Astrophysics Data System (ADS)

Bhattacharjee, Snigdha; Sarkar, Pranab Kumar; Prajapat, Manoj; Roy, Asim

2017-07-01

Molybdenum disulfide (MoS2) is of great interest for its applicability in various optoelectronic devices. Here we report the resistive switching properties of polymethylmethacrylate embedding MoS2 nano-crystals. The devices are developed on an ITO-coated PET substrate with copper as the top electrode. Systematic evaluation of resistive switching parameters, on the basis of MoS2 content, suggests non-volatile memory characteristics. A decent ON/OFF ratio, high retention time and long endurance of 3  ×  103, 105 s and 105 cycles are respectively recorded in a device with 1 weight percent (wt%) of MoS2. The bending cyclic measurements confirm the flexibility of the memory devices with good electrical reliability as well as mechanical stability. In addition, multilevel storage has been demonstrated by controlling the current compliance and span of voltage sweeping in the memory device.

Conceptual design and feasibility evaluation model of a 10 to the 8th power bit oligatomic mass memory. Volume 1: Conceptual design

NASA Technical Reports Server (NTRS)

Recksiedler, A. L.; Lutes, C. L.

1972-01-01

The oligatomic (mirror) thin film memory technology is a suitable candidate for general purpose spaceborne applications in the post-1975 time frame. Capacities of around 10 to the 8th power bits can be reliably implemented with systems designed around a 335 million bit module. The recommended mode was determined following an investigation of implementation sizes ranging from an 8,000,000 to 100,000,000 bits per module. Cost, power, weight, volume, reliability, maintainability and speed were investigated. The memory includes random access, NDRO, SEC-DED, nonvolatility, and dual interface characteristics. The applications most suitable for the technology are those involving a large capacity with high speed (no latency), nonvolatility, and random accessing.

Logic computation in phase change materials by threshold and memory switching.

PubMed

Cassinerio, M; Ciocchini, N; Ielmini, D

2013-11-06

Memristors, namely hysteretic devices capable of changing their resistance in response to applied electrical stimuli, may provide new opportunities for future memory and computation, thanks to their scalable size, low switching energy and nonvolatile nature. We have developed a functionally complete set of logic functions including NOR, NAND and NOT gates, each utilizing a single phase-change memristor (PCM) where resistance switching is due to the phase transformation of an active chalcogenide material. The logic operations are enabled by the high functionality of nanoscale phase change, featuring voltage comparison, additive crystallization and pulse-induced amorphization. The nonvolatile nature of memristive states provides the basis for developing reconfigurable hybrid logic/memory circuits featuring low-power and high-speed switching. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Advanced Compact Holographic Data Storage System

NASA Technical Reports Server (NTRS)

Chao, Tien-Hsin; Zhou, Hanying; Reyes, George

2000-01-01

JPL, under current sponsorship from NASA Space Science and Earth Science Programs, is developing a high-density, nonvolatile and rad-hard Advanced Holographic Memory (AHM) system to enable large-capacity, high-speed, low power consumption, and read/write of data in a space environment. The entire read/write operation will be controlled with electro-optic mechanism without any moving parts. This CHDS will consist of laser diodes, photorefractive crystal, spatial light modulator, photodetector array, and I/O electronic interface. In operation, pages of information would be recorded and retrieved with random access and highspeed. The nonvolatile, rad-hard characteristics of the holographic memory will provide a revolutionary memory technology to enhance mission capabilities for all NASA's Earth Science Mission. In this paper, recent technology progress in developing this CHDS at JPL will be presented.

Programmable nanowire circuits for nanoprocessors.

PubMed

Yan, Hao; Choe, Hwan Sung; Nam, SungWoo; Hu, Yongjie; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

2011-02-10

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

A Strategy to Design High-Density Nanoscale Devices utilizing Vapor Deposition of Metal Halide Perovskite Materials.

PubMed

Hwang, Bohee; Lee, Jang-Sik

2017-08-01

The demand for high memory density has increased due to increasing needs of information storage, such as big data processing and the Internet of Things. Organic-inorganic perovskite materials that show nonvolatile resistive switching memory properties have potential applications as the resistive switching layer for next-generation memory devices, but, for practical applications, these materials should be utilized in high-density data-storage devices. Here, nanoscale memory devices are fabricated by sequential vapor deposition of organolead halide perovskite (OHP) CH 3 NH 3 PbI 3 layers on wafers perforated with 250 nm via-holes. These devices have bipolar resistive switching properties, and show low-voltage operation, fast switching speed (200 ns), good endurance, and data-retention time >10 5 s. Moreover, the use of sequential vapor deposition is extended to deposit CH 3 NH 3 PbI 3 as the memory element in a cross-point array structure. This method to fabricate high-density memory devices could be used for memory cells that occupy large areas, and to overcome the scaling limit of existing methods; it also presents a way to use OHPs to increase memory storage capacity. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Super Nonlinear Electrodeposition-Diffusion-Controlled Thin-Film Selector.

PubMed

Ji, Xinglong; Song, Li; He, Wei; Huang, Kejie; Yan, Zhiyuan; Zhong, Shuai; Zhang, Yishu; Zhao, Rong

2018-03-28

Selector elements with high nonlinearity are an indispensable part in constructing high density, large-scale, 3D stackable emerging nonvolatile memory and neuromorphic network. Although significant efforts have been devoted to developing novel thin-film selectors, it remains a great challenge in achieving good switching performance in the selectors to satisfy the stringent electrical criteria of diverse memory elements. In this work, we utilized high-defect-density chalcogenide glass (Ge 2 Sb 2 Te 5 ) in conjunction with high mobility Ag element (Ag-GST) to achieve a super nonlinear selective switching. A novel electrodeposition-diffusion dynamic selector based on Ag-GST exhibits superior selecting performance including excellent nonlinearity (<5 mV/dev), ultra-low leakage (<10 fA), and bidirectional operation. With the solid microstructure evidence and dynamic analyses, we attributed the selective switching to the competition between the electrodeposition and diffusion of Ag atoms in the glassy GST matrix under electric field. A switching model is proposed, and the in-depth understanding of the selective switching mechanism offers an insight of switching dynamics for the electrodeposition-diffusion-controlled thin-film selector. This work opens a new direction of selector designs by combining high mobility elements and high-defect-density chalcogenide glasses, which can be extended to other materials with similar properties.

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

NASA Astrophysics Data System (ADS)

Jovanović, B.; Brum, R. M.; Torres, L.

2014-04-01

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

Multi-floor cascading ferroelectric nanostructures: multiple data writing-based multi-level non-volatile memory devices

NASA Astrophysics Data System (ADS)

Hyun, Seung; Kwon, Owoong; Lee, Bom-Yi; Seol, Daehee; Park, Beomjin; Lee, Jae Yong; Lee, Ju Hyun; Kim, Yunseok; Kim, Jin Kon

2016-01-01

Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process.Multiple data writing-based multi-level non-volatile memory has gained strong attention for next-generation memory devices to quickly accommodate an extremely large number of data bits because it is capable of storing multiple data bits in a single memory cell at once. However, all previously reported devices have failed to store a large number of data bits due to the macroscale cell size and have not allowed fast access to the stored data due to slow single data writing. Here, we introduce a novel three-dimensional multi-floor cascading polymeric ferroelectric nanostructure, successfully operating as an individual cell. In one cell, each floor has its own piezoresponse and the piezoresponse of one floor can be modulated by the bias voltage applied to the other floor, which means simultaneously written data bits in both floors can be identified. This could achieve multi-level memory through a multiple data writing process. Electronic supplementary information (ESI) available. See DOI: 10.1039/c5nr07377d

Voltage-controlled low-energy switching of nanomagnets through Ruderman-Kittel-Kasuya-Yosida interactions for magnetoelectric device applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ghosh, Bahniman, E-mail: bghosh@utexas.edu; Dey, Rik; Register, Leonard F.

2016-07-21

In this article, we consider through simulation low-energy switching of nanomagnets via electrostatically gated inter-magnet Ruderman-Kittel-Kasuya-Yosida (RKKY) interactions on the surface of three-dimensional topological insulators, for possible memory and nonvolatile logic applications. We model the possibility and dynamics of RKKY-based switching of one nanomagnet by coupling to one or more nanomagnets of set orientation. Potential applications to both memory and nonvolatile logic are illustrated. Sub-attojoule switching energies, far below conventional spin transfer torque (STT)-based memories and even below CMOS logic appear possible. Switching times on the order of a few nanoseconds, comparable to times for STT switching, are estimated formore » ferromagnetic nanomagnets, but the approach also appears compatible with the use of antiferromagnets which may allow for faster switching.« less

Recent Advances of Flexible Data Storage Devices Based on Organic Nanoscaled Materials.

PubMed

Zhou, Li; Mao, Jingyu; Ren, Yi; Han, Su-Ting; Roy, Vellaisamy A L; Zhou, Ye

2018-03-01

Following the trend of miniaturization as per Moore's law, and facing the strong demand of next-generation electronic devices that should be highly portable, wearable, transplantable, and lightweight, growing endeavors have been made to develop novel flexible data storage devices possessing nonvolatile ability, high-density storage, high-switching speed, and reliable endurance properties. Nonvolatile organic data storage devices including memory devices on the basis of floating-gate, charge-trapping, and ferroelectric architectures, as well as organic resistive memory are believed to be favorable candidates for future data storage applications. In this Review, typical information on device structure, memory characteristics, device operation mechanisms, mechanical properties, challenges, and recent progress of the above categories of flexible data storage devices based on organic nanoscaled materials is summarized. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Flash Memory Reliability: Read, Program, and Erase Latency Versus Endurance Cycling

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2010-01-01

This report documents the efforts and results of the fiscal year (FY) 2010 NASA Electronic Parts and Packaging Program (NEPP) task for nonvolatile memory (NVM) reliability. This year's focus was to measure latency (read, program, and erase) of NAND Flash memories and determine how these parameters drift with erase/program/read endurance cycling.

Non-exponential resistive switching in Ag2S memristors: a key to nanometer-scale non-volatile memory devices.

PubMed

Gubicza, Agnes; Csontos, Miklós; Halbritter, András; Mihály, György

2015-03-14

The dynamics of resistive switchings in nanometer-scale metallic junctions formed between an inert metallic tip and an Ag film covered by a thin Ag2S layer are investigated. Our thorough experimental analysis and numerical simulations revealed that the resistance change upon a switching bias voltage pulse exhibits a strongly non-exponential behaviour yielding markedly different response times at different bias levels. Our results demonstrate the merits of Ag2S nanojunctions as nanometer-scale non-volatile memory cells with stable switching ratios, high endurance as well as fast response to write/erase, and an outstanding stability against read operations at technologically optimal bias and current levels.

Nonvolatile memory with graphene oxide as a charge storage node in nanowire field-effect transistors

NASA Astrophysics Data System (ADS)

Baek, David J.; Seol, Myeong-Lok; Choi, Sung-Jin; Moon, Dong-Il; Choi, Yang-Kyu

2012-02-01

Through the structural modification of a three-dimensional silicon nanowire field-effect transistor, i.e., a double-gate FinFET, a structural platform was developed which allowed for us to utilize graphene oxide (GO) as a charge trapping layer in a nonvolatile memory device. By creating a nanogap between the gate and the channel, GO was embedded after the complete device fabrication. By applying a proper gate voltage, charge trapping, and de-trapping within the GO was enabled and resulted in large threshold voltage shifts. The employment of GO with FinFET in our work suggests that graphitic materials can potentially play a significant role for future nanoelectronic applications.

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

NASA Astrophysics Data System (ADS)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin; Chi, Li-Feng; Wang, Sui-Dong

2015-03-01

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

A Retina-Like Dual Band Organic Photosensor Array for Filter-Free Near-Infrared-to-Memory Operations.

PubMed

Wang, Hanlin; Liu, Hongtao; Zhao, Qiang; Ni, Zhenjie; Zou, Ye; Yang, Jie; Wang, Lifeng; Sun, Yanqiu; Guo, Yunlong; Hu, Wenping; Liu, Yunqi

2017-08-01

Human eyes use retina photoreceptor cells to absorb and distinguish photons from different wavelengths to construct an image. Mimicry of such a process and extension of its spectral response into the near-infrared (NIR) is indispensable for night surveillance, retinal prosthetics, and medical imaging applications. Currently, NIR organic photosensors demand optical filters to reduce visible interference, thus making filter-free and anti-visible NIR imaging a challenging task. To solve this limitation, a filter-free and conformal, retina-inspired NIR organic photosensor is presented. Featuring an integration of photosensing and floating-gate memory modules, the device possesses an acute color distinguishing capability. In general, the retina-like photosensor transduces NIR (850 nm) into nonvolatile memory and acts as a dynamic photoswitch under green light (550 nm). In doing this, a filter-free but color-distinguishing photosensor is demonstrated that selectively converts NIR optical signals into nonvolatile memory. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Titanium-tungsten nanocrystals embedded in a SiO(2)/Al(2)O(3) gate dielectric stack for low-voltage operation in non-volatile memory.

PubMed

Yang, Shiqian; Wang, Qin; Zhang, Manhong; Long, Shibing; Liu, Jing; Liu, Ming

2010-06-18

Titanium-tungsten nanocrystals (NCs) were fabricated by a self-assembly rapid thermal annealing (RTA) process. Well isolated Ti(0.46)W(0.54) NCs were embedded in the gate dielectric stack of SiO(2)/Al(2)O(3). A metal-oxide-semiconductor (MOS) capacitor was fabricated to investigate its application in a non-volatile memory (NVM) device. It demonstrated a large memory window of 6.2 V in terms of flat-band voltage (V(FB)) shift under a dual-directional sweeping gate voltage of - 10 to 10 V. A 1.1 V V(FB) shift under a low dual-directional sweeping gate voltage of - 4 to 4 V was also observed. The retention characteristic of this MOS capacitor was demonstrated by a 0.5 V memory window after 10(4) s of elapsed time at room temperature. The endurance characteristic was demonstrated by a program/erase cycling test.

Large-area, flexible imaging arrays constructed by light-charge organic memories

PubMed Central

Zhang, Lei; Wu, Ti; Guo, Yunlong; Zhao, Yan; Sun, Xiangnan; Wen, Yugeng; Yu, Gui; Liu, Yunqi

2013-01-01

Existing organic imaging circuits, which offer attractive benefits of light weight, low cost and flexibility, are exclusively based on phototransistor or photodiode arrays. One shortcoming of these photo-sensors is that the light signal should keep invariant throughout the whole pixel-addressing and reading process. As a feasible solution, we synthesized a new charge storage molecule and embedded it into a device, which we call light-charge organic memory (LCOM). In LCOM, the functionalities of photo-sensor and non-volatile memory are integrated. Thanks to the deliberate engineering of electronic structure and self-organization process at the interface, 92% of the stored charges, which are linearly controlled by the quantity of light, retain after 20000 s. The stored charges can also be non-destructively read and erased by a simple voltage program. These results pave the way to large-area, flexible imaging circuits and demonstrate a bright future of small molecular materials in non-volatile memory. PMID:23326636

Stress-based control of magnetic nanowire domain walls in artificial multiferroic systems

NASA Astrophysics Data System (ADS)

Dean, J.; Bryan, M. T.; Schrefl, T.; Allwood, D. A.

2011-01-01

Artificial multiferroic systems, which combine piezoelectric and piezomagnetic materials, offer novel methods of controlling material properties. Here, we use combined structural and magnetic finite element models to show how localized strains in a piezoelectric film coupled to a piezomagnetic nanowire can attract and pin magnetic domain walls. Synchronous switching of addressable contacts enables the controlled movement of pinning sites, and hence domain walls, in the nanowire without applied magnetic field or spin-polarized current, irrespective of domain wall structure. Conversely, domain wall-induced strain in the piezomagnetic material induces a local potential difference in the piezoelectric, providing a mechanism for sensing domain walls. This approach overcomes the problems in magnetic nanowire memories of domain wall structure-dependent behavior and high power consumption. Nonvolatile random access or shift register memories based on these effects can achieve storage densities >1 Gbit/In2, sub-10 ns switching times, and power consumption <100 keV per operation.

Multilevel characteristics and memory mechanisms for nonvolatile memory devices based on CuInS{sub 2} quantum dot-polymethylmethacrylate nanocomposites

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhou, Yang; Yun, Dong Yeol; Kim, Tae Whan, E-mail: twk@hanyang.ac.kr

2014-12-08

Nonvolatile memory devices based on CuInS{sub 2} (CIS) quantum dots (QDs) embedded in a polymethylmethacrylate (PMMA) layer were fabricated using spin-coating method. The memory window widths of the capacitance-voltage (C-V) curves for the Al/CIS QDs embedded in PMMA layer/p-Si devices were 0.3, 0.6, and 1.0 V for sweep voltages of ±3, ±5, and ±7 V, respectively. Capacitance-cycle data demonstrated that the charge-trapping capability of the devices with an ON/OFF ratio value of 2.81 × 10{sup −10} was maintained for 8 × 10{sup 3} cycles without significant degradation and that the extrapolation of the ON/OFF ratio value to 1 × 10{sup 6} cycles converged to 2.40 × 10{sup −10}, indicative ofmore » the good stability of the devices. The memory mechanisms for the devices are described on the basis of the C-V curves and the energy-band diagrams.« less

Effect of electrode material on characteristics of non-volatile resistive memory consisting of Ag{sub 2}S nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jang, Jaewon, E-mail: j1jang@knu.ac.kr

2016-07-15

In this study, Ag{sub 2}S nanoparticles are synthesized and used as the active material for two-terminal resistance switching memory devices. Sintered Ag{sub 2}S films are successfully crystallized on plastic substrates with synthesized Ag{sub 2}S nanoparticles, after a relatively low-temperature sintering process (200 °C). After the sintering process, the crystallite size is increased from 6.8 nm to 80.3 nm. The high ratio of surface atoms to inner atoms of nanoparticles reduces the melting point temperature, deciding the sintering process temperature. In order to investigate the resistance switching characteristics, metal/Ag{sub 2}S/metal structures are fabricated and tested. The effect of the electrode materialmore » on the non-volatile resistive memory characteristics is studied. The bottom electrochemically inert materials, such as Au and Pt, were critical for maintaining stable memory characteristics. By using Au and Pt inert bottom electrodes, we are able to significantly improve the memory endurance and retention to more than 10{sup 3} cycles and 10{sup 4} sec, respectively.« less

Multistate storage nonvolatile memory device based on ferroelectricity and resistive switching effects of SrBi2Ta2O9 films

NASA Astrophysics Data System (ADS)

Song, Zhiwei; Li, Gang; Xiong, Ying; Cheng, Chuanpin; Zhang, Wanli; Tang, Minghua; Li, Zheng; He, Jiangheng

2018-05-01

A memory device with a Pt/SrBi2Ta2O9(SBT)/Pt(111) structure was shown to have excellent combined ferroelectricity and resistive switching properties, leading to higher multistate storage memory capacity in contrast to ferroelectric memory devices. In this device, SBT polycrystalline thin films with significant (115) orientation were fabricated on Pt(111)/Ti/SiO2/Si(100) substrates using CVD (chemical vapor deposition) method. Measurement results of the electric properties exhibit reproducible and reliable ferroelectricity switching behavior and bipolar resistive switching effects (BRS) without an electroforming process. The ON/OFF ratio of the resistive switching was found to be about 103. Switching mechanisms for the low resistance state (LRS) and high resistance state (HRS) currents are likely attributed to the Ohmic and space charge-limited current (SCLC) behavior, respectively. Moreover, the ferroelectricity and resistive switching effects were found to be mutually independent, and the four logic states were obtained by controlling the periodic sweeping voltage. This work holds great promise for nonvolatile multistate memory devices with high capacity and low cost.

Composition-dependent nanoelectronics of amido-phenazines: non-volatile RRAM and WORM memory devices.

PubMed

Maiti, Dilip K; Debnath, Sudipto; Nawaz, Sk Masum; Dey, Bapi; Dinda, Enakhi; Roy, Dipanwita; Ray, Sudipta; Mallik, Abhijit; Hussain, Syed A

2017-10-17

A metal-free three component cyclization reaction with amidation is devised for direct synthesis of DFT-designed amido-phenazine derivative bearing noncovalent gluing interactions to fabricate organic nanomaterials. Composition-dependent organic nanoelectronics for nonvolatile memory devices are discovered using mixed phenazine-stearic acid (SA) nanomaterials. We discovered simultaneous two different types of nonmagnetic and non-moisture sensitive switching resistance properties of fabricated devices utilizing mixed organic nanomaterials: (a) sample-1(8:SA = 1:3) is initially off, turning on at a threshold, but it does not turn off again with the application of any voltage, and (b) sample-2 (8:SA = 3:1) is initially off, turning on at a sharp threshold and off again by reversing the polarity. No negative differential resistance is observed in either type. These samples have different device implementations: sample-1 is attractive for write-once-read-many-times memory devices, such as novel non-editable database, archival memory, electronic voting, radio frequency identification, sample-2 is useful for resistive-switching random access memory application.

Mechanical memory

DOEpatents

Gilkey, Jeffrey C [Albuquerque, NM; Duesterhaus, Michelle A [Albuquerque, NM; Peter, Frank J [Albuquerque, NM; Renn, Rosemarie A [Alburquerque, NM; Baker, Michael S [Albuquerque, NM

2006-08-15

A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of memory cells, with each memory cell having a beam which can be bowed in either of two directions of curvature to indicate two different logic states for that memory cell. The memory cells can be arranged around a wheel which operates as a clocking actuator to serially shift data from one memory cell to the next. The mechanical memory can be formed using conventional surface micromachining, and can be formed as either a nonvolatile memory or as a volatile memory.

Mechanical memory

DOEpatents

Gilkey, Jeffrey C [Albuquerque, NM; Duesterhaus, Michelle A [Albuquerque, NM; Peter, Frank J [Albuquerque, NM; Renn, Rosemarie A [Albuquerque, NM; Baker, Michael S [Albuquerque, NM

2006-05-16

A first-in-first-out (FIFO) microelectromechanical memory apparatus (also termed a mechanical memory) is disclosed. The mechanical memory utilizes a plurality of memory cells, with each memory cell having a beam which can be bowed in either of two directions of curvature to indicate two different logic states for that memory cell. The memory cells can be arranged around a wheel which operates as a clocking actuator to serially shift data from one memory cell to the next. The mechanical memory can be formed using conventional surface micromachining, and can be formed as either a nonvolatile memory or as a volatile memory.

Optically Addressable, Ferroelectric Memory With NDRO

NASA Technical Reports Server (NTRS)

Thakoor, Sarita

1994-01-01

For readout, memory cells addressed via on-chip semiconductor lasers. Proposed thin-film ferroelectric memory device features nonvolatile storage, optically addressable, nondestructive readout (NDRO) with fast access, and low vulnerability to damage by ionizing radiation. Polarization switched during recording and erasure, but not during readout. As result, readout would not destroy contents of memory, and operating life in specific "read-intensive" applications increased up to estimated 10 to the 16th power cycles.

Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

PubMed

Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

2015-03-04

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

Core-Shell Zn x Cd1- x Se/Zn y Cd1- y Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

NASA Astrophysics Data System (ADS)

Al-Amoody, Fuad; Suarez, Ernesto; Rodriguez, Angel; Heller, E.; Huang, Wenli; Jain, F.

2011-08-01

This paper presents a floating quantum dot (QD) gate nonvolatile memory device using high-energy-gap Zn y Cd1- y Se-cladded Zn x Cd1- x Se quantum dots ( y > x) with tunneling layers comprising nearly lattice-matched semiconductors (e.g., ZnS/ZnMgS) on Si channels. Also presented is the fabrication of an electroluminescent (EL) device with embedded cladded ZnCdSe quantum dots. These ZnCdSe quantum dots were embedded between indium tin oxide (ITO) on glass and a top Schottky metal electrode deposited on a thin CsF barrier. These QDs, which were nucleated in a photo-assisted microwave plasma (PMP) metalorganic chemical vapor deposition (MOCVD) reactor, were grown between the source and drain regions on a p-type silicon substrate of the nonvolatile memory device. The composition of QD cladding, which relates to the value of y in Zn y Cd1- y Se, was engineered by the intensity of ultraviolet light, which controlled the incorporation of zinc in ZnCdSe. The QD quality is comparable to those deposited by other methods. Characteristics and modeling of the II-VI quantum dots as well as two diverse types of devices are presented in this paper.

Nonvolatile reconfigurable sequential logic in a HfO2 resistive random access memory array.

PubMed

Zhou, Ya-Xiong; Li, Yi; Su, Yu-Ting; Wang, Zhuo-Rui; Shih, Ling-Yi; Chang, Ting-Chang; Chang, Kuan-Chang; Long, Shi-Bing; Sze, Simon M; Miao, Xiang-Shui

2017-05-25

Resistive random access memory (RRAM) based reconfigurable logic provides a temporal programmable dimension to realize Boolean logic functions and is regarded as a promising route to build non-von Neumann computing architecture. In this work, a reconfigurable operation method is proposed to perform nonvolatile sequential logic in a HfO 2 -based RRAM array. Eight kinds of Boolean logic functions can be implemented within the same hardware fabrics. During the logic computing processes, the RRAM devices in an array are flexibly configured in a bipolar or complementary structure. The validity was demonstrated by experimentally implemented NAND and XOR logic functions and a theoretically designed 1-bit full adder. With the trade-off between temporal and spatial computing complexity, our method makes better use of limited computing resources, thus provides an attractive scheme for the construction of logic-in-memory systems.

Electrical Bistabilities and Conduction Mechanisms of Nonvolatile Memories Based on a Polymethylsilsesquioxane Insulating Layer Containing CdSe/ZnS Quantum Dots

NASA Astrophysics Data System (ADS)

Ma, Zehao; Ooi, Poh Choon; Li, Fushan; Yun, Dong Yeol; Kim, Tae Whan

2015-10-01

Nonvolatile memory (NVM) devices based on a metal-insulator-metal structure consisting of CdSe/ZnS quantum dots embedded in polymethylsilsesquioxane dielectric layers were fabricated. The current-voltage ( I- V) curves showed a bistable current behavior and the presence of hysteresis. The current-time ( I- t) curves showed that the fabricated NVM memory devices were stable up to 1 × 104 s with a distinct ON/OFF ratio of 104 and were reprogrammable when the endurance test was performed. The extrapolation of the I- t curve to 105 s with corresponding current ON/OFF ratio 1 × 105 indicated a long performance stability of the NVM devices. Schottky emission, Poole-Frenkel emission, trapped-charge limited-current and Child-Langmuir law were proposed as the dominant conduction mechanisms for the fabricated NVM devices based on the obtained I- V characteristics.

Indium-oxide nanoparticles for RRAM devices compatible with CMOS back-end-off-line

NASA Astrophysics Data System (ADS)

León Pérez, Edgar A. A.; Guenery, Pierre-Vincent; Abouzaid, Oumaïma; Ayadi, Khaled; Brottet, Solène; Moeyaert, Jérémy; Labau, Sébastien; Baron, Thierry; Blanchard, Nicholas; Baboux, Nicolas; Militaru, Liviu; Souifi, Abdelkader

2018-05-01

We report on the fabrication and characterization of Resistive Random Access Memory (RRAM) devices based on nanoparticles in MIM structures. Our approach is based on the use of indium oxide (In2O3) nanoparticles embedded in a dielectric matrix using CMOS-full-compatible fabrication processes in view of back-end-off-line integration for non-volatile memory (NVM) applications. A bipolar switching behavior has been observed using current-voltage measurements (I-V) for all devices. Very high ION/IOFF ratios have been obtained up to 108. Our results provide insights for further integration of In2O3 nanoparticles-based devices for NVM applications. He is currently a Postdoctoral Researcher in the Institute of Nanotechnologies of Lyon (INL), INSA de Lyon, France, in the Electronics Department. His current research include indium oxide nanoparticles for non-volatile memory applications, and the integrations of these devices in CMOS BEOL.

DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology. [Dual Injector Floating-gate MOS

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1977-01-01

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

Resistive switching effect of N-doped MoS2-PVP nanocomposites films for nonvolatile memory devices

NASA Astrophysics Data System (ADS)

Wu, Zijin; Wang, Tongtong; Sun, Changqi; Liu, Peitao; Xia, Baorui; Zhang, Jingyan; Liu, Yonggang; Gao, Daqiang

2017-12-01

Resistive memory technology is very promising in the field of semiconductor memory devices. According to Liu et al, MoS2-PVP nanocomposite can be used as an active layer material for resistive memory devices due to its bipolar resistive switching behavior. Recent studies have also indicated that the doping of N element can reduce the band gap of MoS2 nanosheets, which is conducive to improving the conductivity of the material. Therefore, in this paper, we prepared N-doped MoS2 nanosheets and then fabricated N-doped MoS2-PVP nanocomposite films by spin coating. Finally, the resistive memory [C. Tan et al., Chem. Soc. Rev. 44, 2615 (2015)], device with ITO/N-doped MoS2-PVP/Pt structure was fabricated. Study on the I-V characteristics shows that the device has excellent resistance switching effect. It is worth mentioning that our device possesses a threshold voltage of 0.75 V, which is much better than 3.5 V reported previously for the undoped counterparts. The above research shows that N-doped MoS2-PVP nanocomposite films can be used as the active layer of resistive switching memory devices, and will make the devices have better performance.

Enhanced fatigue and retention in ferroelectric thin film memory capacitors by post-top electrode anneal treatment

NASA Technical Reports Server (NTRS)

Thakoor, Sarita (Inventor)

1992-01-01

Thin film ferroelectric capacitors comprising a ferroelectric film sandwiched between electrodes for nonvolatile memory operations are rendered more stable by subjecting the capacitors to an anneal following deposition of the top electrode. The anneal is done so as to form the interface between the ferroelectric film and the top electrode. Heating in an air oven, laser annealing, or electron bombardment may be used to form the interface. Heating in an air oven is done at a temperature at least equal to the crystallization temperature of the ferroelectric film. Where the ferroelectric film comprises lead zirconate titanate, annealing is done at about 550 to 600 C for about 10 to 15 minutes. The formation treatment reduces the magnitude of charge associated with the nonswitching pulse in the thin film ferroelectric capacitors. Reduction of this charge leads to significantly more stable nonvolatile memory operations in both digital and analog memory devices. The formation treatment also reduces the ratio of change of the charge associated with the nonswitching pulse as a function of retention time. These improved memory devices exhibit greater performance in retention and reduced fatigue in memory arrays.

Enhanced fatigue and retention in ferroelectric thin film memory capacitors by post-top electrode anneal treatment

NASA Technical Reports Server (NTRS)

Thakoor, Sarita (Inventor)

1994-01-01

Thin film ferroelectric capacitors (10) comprising a ferroelectric film (18) sandwiched between electrodes (16 and 20) for nonvolatile memory operations are rendered more stable by subjecting the capacitors to an anneal following deposition of the top electrode (20). The anneal is done so as to form the interface (22) between the ferroelectric film and the top electrode. Heating in an air oven, laser annealing, or electron bombardment may be used to form the interface. Heating in an air oven is done at a temperature at least equal to the crystallization temperature of the ferroelectric film. Where the ferroelectric film comprises lead zirconate titanate, annealing is done at about 550.degree. to 600.degree. C. for about 10 to 15 minutes. The formation treatment reduces the magnitude of charge associated with the non-switching pulse in the thin film ferroelectric capacitors. Reduction of this charge leads to significantly more stable nonvolatile memory operations in both digital and analog memory devices. The formation treatment also reduces the ratio of change of the charge associated with the non-switching pulse as a function of retention time. These improved memory devices exhibit greater performance in retention and reduced fatigue in memory arrays.

Non-volatile main memory management methods based on a file system.

PubMed

Oikawa, Shuichi

2014-01-01

There are upcoming non-volatile (NV) memory technologies that provide byte addressability and high performance. PCM, MRAM, and STT-RAM are such examples. Such NV memory can be used as storage because of its data persistency without power supply while it can be used as main memory because of its high performance that matches up with DRAM. There are a number of researches that investigated its uses for main memory and storage. They were, however, conducted independently. This paper presents the methods that enables the integration of the main memory and file system management for NV memory. Such integration makes NV memory simultaneously utilized as both main memory and storage. The presented methods use a file system as their basis for the NV memory management. We implemented the proposed methods in the Linux kernel, and performed the evaluation on the QEMU system emulator. The evaluation results show that 1) the proposed methods can perform comparably to the existing DRAM memory allocator and significantly better than the page swapping, 2) their performance is affected by the internal data structures of a file system, and 3) the data structures appropriate for traditional hard disk drives do not always work effectively for byte addressable NV memory. We also performed the evaluation of the effects caused by the longer access latency of NV memory by cycle-accurate full-system simulation. The results show that the effect on page allocation cost is limited if the increase of latency is moderate.

Graphene as a platform for novel nanoelectronic devices

NASA Astrophysics Data System (ADS)

Standley, Brian

Graphene's superlative electrical and mechanical properties, combined with its compatibility with existing planar silicon-based technology, make it an attractive platform for novel nanoelectronic devices. The development of two such devices is reported--a nonvolatile memory element exploiting the nanoscale graphene edge and a field-effect transistor using graphene for both the conducting channel and, in oxidized form, the gate dielectric. These experiments were enabled by custom software written to fully utilize both instrument-based and computer-based data acquisition hardware and provide a simple measurement automation system. Graphene break junctions were studied and found to exhibit switching behavior in response to an electric field. This switching allows the devices to act as nonvolatile memory elements which have demonstrated thousands of writing cycles and long retention times. A model for device operation is proposed based on the formation and breaking of carbon-atom chains that bridge the junctions. Information storage was demonstrated using the concept of rank coding, in which information is stored in the relative conductance of multiple graphene switches in a memory cell. The high mobility and two dimensional nature of graphene make it an attractive material for field-effect transistors. Another ultrathin layered materialmd graphene's insulating analogue, graphite oxidemd was studied as an alternative to bulk gate dielectric materials such as Al2O3 or HfO 2. Transistors were fabricated comprising single or bilayer graphene channels, graphite oxide gate insulators, and metal top-gates. Electron transport measurements reveal minimal leakage through the graphite oxide at room temperature. Its breakdown electric field was found to be comparable to SiO2, typically ˜1-3 x 108 V/m, while its dielectric constant is slightly higher, kappa ≈ 4.3. As nanoelectronics experiments and their associated instrumentation continue to grow in complexity the need for powerful data acquisition software has only increased. This role has traditionally been filled by semiconductor parameter analyzers or desktop computers running LabVIEW. Mezurit 2 represents a hybrid approach, providing basic virtual instruments which can be controlled in concert through a comprehensive scripting interface. Each virtual instrument's model of operation is described and an architectural overview is provided.

Practicality of Evaluating Soft Errors in Commercial sub-90 nm CMOS for Space Applications

NASA Technical Reports Server (NTRS)

Pellish, Jonathan A.; LaBel, Kenneth A.

2010-01-01

The purpose of this presentation is to: Highlight space memory evaluation evolution, Review recent developments regarding low-energy proton direct ionization soft errors, Assess current space memory evaluation challenges, including increase of non-volatile technology choices, and Discuss related testing and evaluation complexities.

Nonvolatile Ferroelectric Memory Circuit Using Black Phosphorus Nanosheet-Based Field-Effect Transistors with P(VDF-TrFE) Polymer.

PubMed

Lee, Young Tack; Kwon, Hyeokjae; Kim, Jin Sung; Kim, Hong-Hee; Lee, Yun Jae; Lim, Jung Ah; Song, Yong-Won; Yi, Yeonjin; Choi, Won-Kook; Hwang, Do Kyung; Im, Seongil

2015-10-27

Two-dimensional van der Waals (2D vdWs) materials are a class of new materials that can provide important resources for future electronics and materials sciences due to their unique physical properties. Among 2D vdWs materials, black phosphorus (BP) has exhibited significant potential for use in electronic and optoelectronic applications because of its allotropic properties, high mobility, and direct and narrow band gap. Here, we demonstrate a few-layered BP-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. Experiments showed that our BP-based ferroelectric transistors operate satisfactorily at room temperature in ambient air and exhibit a clear memory window. Unlike conventional ambipolar BP transistors, our ferroelectric transistors showed only p-type characteristics due to the carbon-fluorine (C-F) dipole effect of the P(VDF-TrFE) layer, as well as the highest linear mobility value of 1159 cm(2) V(-1) s(-1) with a 10(3) on/off current ratio. For more advanced memory applications beyond unit memory devices, we implemented two memory inverter circuits, a resistive-load inverter circuit and a complementary inverter circuit, combined with an n-type molybdenum disulfide (MoS2) nanosheet. Our memory inverter circuits displayed a clear memory window of 15 V and memory output voltage efficiency of 95%.

Fabrication of InGaZnO Nonvolatile Memory Devices at Low Temperature of 150 degrees C for Applications in Flexible Memory Displays and Transparency Coating on Plastic Substrates.

PubMed

Hanh, Nguyen Hong; Jang, Kyungsoo; Yi, Junsin

2016-05-01

We directly deposited amorphous InGaZnO (a-IGZO) nonvolatile memory (NVM) devices with oxynitride-oxide-dioxide (OOO) stack structures on plastic substrate by a DC pulsed magnetron sputtering and inductively coupled plasma chemical vapor deposition (ICPCVD) system, using a low-temperature of 150 degrees C. The fabricated bottom gate a-IGZO NVM devices have a wide memory window with a low operating voltage during programming and erasing, due to an effective control of the gate dielectrics. In addition, after ten years, the memory device retains a memory window of over 73%, with a programming duration of only 1 ms. Moreover, the a-IGZO films show high optical transmittance of over 85%, and good uniformity with a root mean square (RMS) roughness of 0.26 nm. This film is a promising candidate to achieve flexible displays and transparency on plastic substrates because of the possibility of low-temperature deposition, and the high transparent properties of a-IGZO films. These results demonstrate that the a-IGZO NVM devices obtained at low-temperature have a suitable programming and erasing efficiency for data storage under low-voltage conditions, in combination with excellent charge retention characteristics, and thus show great potential application in flexible memory displays.

Functionalized Graphitic Carbon Nitride for Metal-free, Flexible and Rewritable Nonvolatile Memory Device via Direct Laser-Writing

NASA Astrophysics Data System (ADS)

Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

2014-07-01

Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 105, which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices.

Multiple switching modes and multiple level states in memristive devices

NASA Astrophysics Data System (ADS)

Miao, Feng; Yang, J. Joshua; Borghetti, Julien; Strachan, John Paul; Zhang, M.-X.; Goldfarb, Ilan; Medeiros-Ribeiro, Gilberto; Williams, R. Stanley

2011-03-01

As one of the most promising technologies for next generation non-volatile memory, metal oxide based memristive devices have demonstrated great advantages on scalability, operating speed and power consumption. Here we report the observation of multiple switching modes and multiple level states in different memristive systems. The multiple switching modes can be obtained by limiting the current during electroforming, and related transport behaviors, including ionic and electronic motions, are characterized. Such observation can be rationalized by a model of two effective switching layers adjacent to the bottom and top electrodes. Multiple level states, corresponding to different composition of the conducting channel, will also be discussed in the context of multiple-level storage for high density, non-volatile memory applications.

Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

NASA Astrophysics Data System (ADS)

Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

2009-11-01

We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgOx and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgOx gate operates under low voltage write-erase (WR-ER) pulse of ±20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of ±70 V for WR and ER states. Both devices stably operated under visible illuminations.

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II-VI Tunnel Insulators

NASA Astrophysics Data System (ADS)

Suarez, E.; Gogna, M.; Al-Amoody, F.; Karmakar, S.; Ayers, J.; Heller, E.; Jain, F.

2010-07-01

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn0.95Mg0.05S/ZnS tunnel insulators. The GeO x -cladded Ge and SiO x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II-VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II-VI stack serves both as a tunnel insulator and a high- κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si3N4 and SiO2 layers grown by plasma- enhanced chemical vapor deposition.

The floating-gate non-volatile semiconductor memory--from invention to the digital age.

PubMed

Sze, S M

2012-10-01

In the past 45 years (from 1967 to 2012), the non-volatile semiconductor memory (NVSM) has emerged from a floating-gate concept to the prime technology driver of the largest industry in the world-the electronics industry. In this paper, we briefly review the historical development of NVSM and project its future trends to the year 2020. In addition, we consider NVSM's wide-range of applications from the digital cellular phone to tablet computer to digital television. As the device dimension is scaled down to the deca-nanometer regime, we expect that many innovations will be made to meet the scaling challenges, and NVSM-inspired technology will continue to enrich and improve our lives for decades to come.

Modeling of SONOS Memory Cell Erase Cycle

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat H.

2011-01-01

Utilization of Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) nonvolatile semiconductor memories as a flash memory has many advantages. These electrically erasable programmable read-only memories (EEPROMs) utilize low programming voltages, have a high erase/write cycle lifetime, are radiation hardened, and are compatible with high-density scaled CMOS for low power, portable electronics. In this paper, the SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. Comparisons were made between the model predictions and experimental data.

A nonlinear HP-type complementary resistive switch

NASA Astrophysics Data System (ADS)

Radtke, Paul K.; Schimansky-Geier, Lutz

2016-05-01

Resistive Switching (RS) is the change in resistance of a dielectric under the influence of an external current or electric field. This change is non-volatile, and the basis of both the memristor and resistive random access memory. In the latter, high integration densities favor the anti-serial combination of two RS-elements to a single cell, termed the complementary resistive switch (CRS). Motivated by the irregular shape of the filament protruding into the device, we suggest a nonlinearity in the resistance-interpolation function, characterized by a single parameter p. Thereby the original HP-memristor is expanded upon. We numerically simulate and analytically solve this model. Further, the nonlinearity allows for its application to the CRS.

Fast Magnetoresistive Random-Access Memory

NASA Technical Reports Server (NTRS)

Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

1991-01-01

Magnetoresistive binary digital memories of proposed new type expected to feature high speed, nonvolatility, ability to withstand ionizing radiation, high density, and low power. In memory cell, magnetoresistive effect exploited more efficiently by use of ferromagnetic material to store datum and adjacent magnetoresistive material to sense datum for readout. Because relative change in sensed resistance between "zero" and "one" states greater, shorter sampling and readout access times achievable.

Dry writing of highly conductive electrodes on papers by using silver nanoparticle-graphene hybrid pencils.

PubMed

Park, Jun-Ho; Park, Myung-Joo; Lee, Jang-Sik

2017-01-05

The development of paper electronics would enable realization of extremely cheap devices for portable, disposable, and environmentally-benign electronics. Here, we propose a simple dry-writing tool similar to a pencil, which can be used to draw electrically conducting lines on paper for use in paper-based electronic devices. The fabricated pencil is composed of silver nanoparticles decorated on graphene layers to construct layered hybrid nanostructures. This pencil can draw highly conductive lines that are flexible and foldable on conventional papers. Electrodes drawn using this pencil on conventional copy paper are stable during repetitive mechanical folding and highly resistant to moisture/chemicals. This pencil can draw a conductive line where its resistance can be tuned by changing the amount of nanoparticles. A nonvolatile memory device is realized on papers by hand written lines with different resistance. All memory elements are composed of carbons on papers, so complete data security can be achieved by burning the memory papers. This work will provide a new opportunity to fabricate electronic devices on real papers with good conductivity as well as robust mechanical/chemical stability.

Low operation voltage and high thermal stability of a WSi2 nanocrystal memory device using an Al2O3/HfO2/Al2O3 tunnel layer

NASA Astrophysics Data System (ADS)

Uk Lee, Dong; Jun Lee, Hyo; Kyu Kim, Eun; You, Hee-Wook; Cho, Won-Ju

2012-02-01

A WSi2 nanocrystal nonvolatile memory device was fabricated with an Al2O3/HfO2/Al2O3 (AHA) tunnel layer and its electrical characteristics were evaluated at 25, 50, 70, 100, and 125 °C. The program/erase (P/E) speed at 125 °C was approximately 500 μs under threshold voltage shifts of 1 V during voltage sweeping of 8 V/-8 V. When the applied pulse voltage was ±9 V for 1 s for the P/E conditions, the memory window at 125 °C was approximately 1.25 V after 105 s. The activation energies for the charge losses of 5%, 10%, 15%, 20%, 25%, 30%, and 35% were approximately 0.05, 0.11, 0.17, 0.21, 0.23, 0.23, and 0.23 eV, respectively. The charge loss mechanisms were direct tunneling and Pool-Frenkel emission between the WSi2 nanocrystals and the AHA barrier engineered tunneling layer. The WSi2 nanocrystal memory device with multi-stacked high-K tunnel layers showed strong potential for applications in nonvolatile memory devices.

Origami-based tunable truss structures for non-volatile mechanical memory operation.

PubMed

Yasuda, Hiromi; Tachi, Tomohiro; Lee, Mia; Yang, Jinkyu

2017-10-17

Origami has recently received significant interest from the scientific community as a method for designing building blocks to construct metamaterials. However, the primary focus has been placed on their kinematic applications by leveraging the compactness and auxeticity of planar origami platforms. Here, we present volumetric origami cells-specifically triangulated cylindrical origami (TCO)-with tunable stability and stiffness, and demonstrate their feasibility as non-volatile mechanical memory storage devices. We show that a pair of TCO cells can develop a double-well potential to store bit information. What makes this origami-based approach more appealing is the realization of two-bit mechanical memory, in which two pairs of TCO cells are interconnected and one pair acts as a control for the other pair. By assembling TCO-based truss structures, we experimentally verify the tunable nature of the TCO units and demonstrate the operation of purely mechanical one- and two-bit memory storage prototypes.Origami is a popular method to design building blocks for mechanical metamaterials. Here, the authors assemble a volumetric origami-based structure, predict its axial and rotational movements during folding, and demonstrate the operation of mechanical one- and two-bit memory storage.

Capacitance-voltage measurement in memory devices using ferroelectric polymer

NASA Astrophysics Data System (ADS)

Nguyen, Chien A.; Lee, Pooi See

2006-01-01

Application of thin polymer film as storing mean for non-volatile memory devices is investigated. Capacitance-voltage (C-V) measurement of metal-ferroelectric-metal device using ferroelectric copolymer P(VDF-TrFE) as dielectric layer shows stable 'butter-fly' curve. The two peaks in C-V measurement corresponding to the largest capacitance are coincidental at the coercive voltages that give rise to zero polarization in the polarization hysteresis measurement. By comparing data of C-V and P-E measurement, a correlation between two types of hysteresis is established in which it reveals simultaneous electrical processes occurring inside the device. These processes are caused by the response of irreversible and reversible polarization to the applied electric field that can be used to present a memory window. The memory effect of ferroelectric copolymer is further demonstrated for fabricating polymeric non-volatile memory devices using metal-ferroelectric-insulator-semiconductor structure (MFIS). By applying different sweeping voltages at the gate, bidirectional flat-band voltage shift is observed in the ferroelectric capacitor. The asymmetrical shift after negative sweeping is resulted from charge accumulation at the surface of Si substrate caused by the dipole direction in the polymer layer. The effect is reversed for positive voltage sweeping.

Two-dimensional multiferroics in monolayer group IV monochalcogenides

NASA Astrophysics Data System (ADS)

Wang, Hua; Qian, Xiaofeng

2017-03-01

Low-dimensional multiferroic materials hold great promises in miniaturized device applications such as nanoscale transducers, actuators, sensors, photovoltaics, and nonvolatile memories. Here, using first-principles theory we predict that two-dimensional (2D) monolayer group IV monochalcogenides including GeS, GeSe, SnS, and SnSe are a class of 2D semiconducting multiferroics with giant strongly-coupled in-plane spontaneous ferroelectric polarization and spontaneous ferroelastic lattice strain that are thermodynamically stable at room temperature and beyond, and can be effectively modulated by elastic strain engineering. Their optical absorption spectra exhibit strong in-plane anisotropy with visible-spectrum excitonic gaps and sizable exciton binding energies, rendering the unique characteristics of low-dimensional semiconductors. More importantly, the predicted low domain wall energy and small migration barrier together with the coupled multiferroic order and anisotropic electronic structures suggest their great potentials for tunable multiferroic functional devices by manipulating external electrical, mechanical, and optical field to control the internal responses, and enable the development of four device concepts including 2D ferroelectric memory, 2D ferroelastic memory, and 2D ferroelastoelectric nonvolatile photonic memory as well as 2D ferroelectric excitonic photovoltaics.

Reversible Negative Resistive Switching in an Individual Fe@Al2O3 Hybrid Nanotube for Nonvolatile Memory.

PubMed

Ye, Yalong; Zhao, Jie; Xiao, Li; Cheng, Baochang; Xiao, Yanhe; Lei, Shuijin

2018-06-06

Hybrid nanostructures can show enormous potential in different areas because of their unique structural configurations. Herein, Fe@Al 2 O 3 hybrid nanotubes are constructed via a homogeneous coprecipitation method followed by subsequent annealing in a reducing atmosphere. The introduction of zero band gap Fe nanocrystals in the wall of ultrawide band gap Al 2 O 3 insulator nanotubes results in the formation of charge trap centers, and correspondingly a single hybrid nanotube-based two-terminal device can show reversible negative resistive switching (RS) characteristics with symmetrical negative differential resistance (NDR) at relatively high operation bias voltages. At a large bias voltage, holes and electrons can be injected into traps at two ends from electrodes, respectively, and then captured. The bias voltage dependence of asymmetrical filling of charges can lead to a reversible variation of built-in electromotive force, and therefore the symmetrical negative RS with NDR arises from two reversible back-to-back series bipolar RS. At a low readout voltage, the single Fe@Al 2 O 3 hybrid nanotube can show an excellent nonvolatile memory feature with a relatively large switching ratio of ∼30. The bias-governed reversible negative RS with superior stability, reversibility, nondestructive readout, and remarkable cycle performance makes it a potential candidate in next-generation erasable nonvolatile resistive random access memories.

82 FR 28354 - Certain Non-Volatile Memory Devices and Products Containing Same Commission Determination Not To...

Federal Register 2010, 2011, 2012, 2013, 2014

2017-06-21

...Notice is hereby given that the U.S. International Trade Commission has determined not to review an initial determination (``ID'') (Order No. 11) of the presiding administrative law judge (``ALJ'') granting an unopposed motion for leave to amend the complaint and notice of investigation to add Toshiba Memory Corporation of Tokyo, Japan (``Toshiba Memory'') as a respondent to the investigation.

Scandium doped Ge2Sb2Te5 for high-speed and low-power-consumption phase change memory

NASA Astrophysics Data System (ADS)

Wang, Yong; Zheng, Yonghui; Liu, Guangyu; Li, Tao; Guo, Tianqi; Cheng, Yan; Lv, Shilong; Song, Sannian; Ren, Kun; Song, Zhitang

2018-03-01

To bridge the gap of access time between memories and storage systems, the concept of storage class memory has been put forward based on emerging nonvolatile memory technologies. For all the nonvolatile memory candidates, the unpleasant tradeoff between operation speed and retention seems to be inevitable. To promote both the write speed and the retention of phase change memory (PCM), Sc doped Ge2Sb2Te5 (SGST) has been proposed as the storage medium. Octahedral Sc-Te motifs, acting as crystallization precursors to shorten the nucleation incubation period, are the possible reason for the high write speed of 6 ns in PCM cells, five-times faster than that of Ge2Sb2Te5 (GST) cells. Meanwhile, an enhanced 10-year data retention of 119 °C has been achieved. Benefiting from both the increased crystalline resistance and the inhibited formation of the hexagonal phase, the SGST cell has a 77% reduction in power consumption compared to the GST cell. Adhesion of the SGST/SiO2 interface has been strengthened, attributed to the reduced stress by forming smaller grains during crystallization, guaranteeing the reliability of the device. These improvements have made the SGST material a promising candidate for PCM application.

Nonvolatile infrared memory in MoS2/PbS van der Waals heterostructures

PubMed Central

Wen, Yao; Cai, Kaiming; Cheng, Ruiqing; Yin, Lei; Zhang, Yu; Li, Jie; Wang, Zhenxing; Wang, Feng; Wang, Fengmei; Shifa, Tofik Ahmed; Jiang, Chao; Yang, Hyunsoo

2018-01-01

Optoelectronic devices for information storage and processing are at the heart of optical communication technology due to their significant applications in optical recording and computing. The infrared radiations of 850, 1310, and 1550 nm with low energy dissipation in optical fibers are typical optical communication wavebands. However, optoelectronic devices that could convert and store the infrared data into electrical signals, thereby enabling optical data communications, have not yet been realized. We report an infrared memory device using MoS2/PbS van der Waals heterostructures, in which the infrared pulse intrigues a persistent resistance state that hardly relaxes within our experimental time scales (more than 104 s). The device fully retrieves the memory state even after powering off for 3 hours, indicating its potential for nonvolatile storage devices. Furthermore, the device presents a reconfigurable switch of 2000 stable cycles. Supported by a theoretical model with quantitative analysis, we propose that the optical memory and the electrical erasing phenomenon, respectively, originate from the localization of infrared-induced holes in PbS and gate voltage pulse-enhanced tunneling of electrons from MoS2 to PbS. The demonstrated MoS2 heterostructure–based memory devices open up an exciting field for optoelectronic infrared memory and programmable logic devices. PMID:29770356

Nonvolatile memory thin film transistors using CdSe/ZnS quantum dot-poly(methyl methacrylate) composite layer formed by a two-step spin coating technique

NASA Astrophysics Data System (ADS)

Chen, Ying-Chih; Huang, Chun-Yuan; Yu, Hsin-Chieh; Su, Yan-Kuin

2012-08-01

The nonvolatile memory thin film transistors (TFTs) using a core/shell CdSe/ZnS quantum dot (QD)-poly(methyl methacrylate) (PMMA) composite layer as the floating gate have been demonstrated, with the device configuration of n+-Si gate/SiO2 insulator/QD-PMMA composite layer/pentacene channel/Au source-drain being proposed. To achieve the QD-PMMA composite layer, a two-step spin coating technique was used to successively deposit QD-PMMA composite and PMMA on the insulator. After the processes, the variation of crystal quality and surface morphology of the subsequent pentacene films characterized by x-ray diffraction spectra and atomic force microscopy was correlated to the two-step spin coating. The crystalline size of pentacene was improved from 147.9 to 165.2 Å, while the degree of structural disorder was decreased from 4.5% to 3.1% after the adoption of this technique. In pentacene-based TFTs, the improvement of the performance was also significant, besides the appearances of strong memory characteristics. The memory behaviors were attributed to the charge storage/discharge effect in QD-PMMA composite layer. Under the programming and erasing operations, programmable memory devices with the memory window (Δ Vth) = 23 V and long retention time were obtained.

Nonvolatile infrared memory in MoS2/PbS van der Waals heterostructures.

PubMed

Wang, Qisheng; Wen, Yao; Cai, Kaiming; Cheng, Ruiqing; Yin, Lei; Zhang, Yu; Li, Jie; Wang, Zhenxing; Wang, Feng; Wang, Fengmei; Shifa, Tofik Ahmed; Jiang, Chao; Yang, Hyunsoo; He, Jun

2018-04-01

Optoelectronic devices for information storage and processing are at the heart of optical communication technology due to their significant applications in optical recording and computing. The infrared radiations of 850, 1310, and 1550 nm with low energy dissipation in optical fibers are typical optical communication wavebands. However, optoelectronic devices that could convert and store the infrared data into electrical signals, thereby enabling optical data communications, have not yet been realized. We report an infrared memory device using MoS 2 /PbS van der Waals heterostructures, in which the infrared pulse intrigues a persistent resistance state that hardly relaxes within our experimental time scales (more than 10 4 s). The device fully retrieves the memory state even after powering off for 3 hours, indicating its potential for nonvolatile storage devices. Furthermore, the device presents a reconfigurable switch of 2000 stable cycles. Supported by a theoretical model with quantitative analysis, we propose that the optical memory and the electrical erasing phenomenon, respectively, originate from the localization of infrared-induced holes in PbS and gate voltage pulse-enhanced tunneling of electrons from MoS 2 to PbS. The demonstrated MoS 2 heterostructure-based memory devices open up an exciting field for optoelectronic infrared memory and programmable logic devices.

Achieving high mobility, low-voltage operating organic field-effect transistor nonvolatile memory by an ultraviolet-ozone treating ferroelectric terpolymer

PubMed Central

Xiang, Lanyi; Wang, Wei; Xie, Wenfa

2016-01-01

Poly(vinylidene fluoride–trifluoroethylene) has been widely used as a dielectric of the ferroelectric organic field-effect transistor (FE-OFET) nonvolatile memory (NVM). Some critical issues, including low mobility and high operation voltage, existed in these FE-OFET NVMs, should be resolved before considering to their commercial application. In this paper, we demonstrated low-voltage operating FE-OFET NVMs based on a ferroelectric terpolymer poly(vinylidene-fluoride-trifluoroethylene-chlorotrifluoroethylene) [P(VDF-TrFE-CTFE)] owed to its low coercive field. By applying an ultraviolet-ozone (UVO) treatment to modify the surface of P(VDF-TrFE-CTFE) films, the growth model of the pentacene film was changed, which improved the pentacene grain size and the interface morphology of the pentacene/P(VDF-TrFE-CTFE). Thus, the mobility of the FE-OFET was significantly improved. As a result, a high performance FE-OFET NVM, with a high mobility of 0.8 cm2 V−1 s−1, large memory window of 15.4~19.2, good memory on/off ratio of 103, the reliable memory endurance over 100 cycles and stable memory retention ability, was achieved at a low operation voltage of ±15 V. PMID:27824101

Nonvolatile programmable neural network synaptic array

NASA Technical Reports Server (NTRS)

Tawel, Raoul (Inventor)

1994-01-01

A floating-gate metal oxide semiconductor (MOS) transistor is implemented for use as a nonvolatile analog storage element of a synaptic cell used to implement an array of processing synaptic cells. These cells are based on a four-quadrant analog multiplier requiring both X and Y differential inputs, where one Y input is UV programmable. These nonvolatile synaptic cells are disclosed fully connected in a 32 x 32 synaptic cell array using standard very large scale integration (VLSI) complementary MOS (CMOS) technology.

Proposed model for bistability in nanowire nonvolatile memory

NASA Astrophysics Data System (ADS)

Pokalyakin, V.; Tereshin, S.; Varfolomeev, A.; Zaretsky, D.; Baranov, A.; Banerjee, A.; Wang, Y.; Ramanathan, S.; Bandyopadhyay, S.

2005-06-01

Cadmium sulfide nanowires of 10-nm diameter, electrodeposited in porous anodic alumina films, exhibit an electronic bistability that can be harnessed for nonvolatile memory. The current-voltage characteristics of the wires show two stable conductance states that are well separated (conductances differ by more than four orders of magnitude) and long lived (longevity>1yr at room temperature). These two states can encode binary bits 0 and 1. It is possible to switch between them by varying the voltage across the wires, thus "writing" data. Transport behavior of this system has been investigated at different temperatures in an effort to understand the origin of bistability, and a model is presented to explain the observed features. Based on this model, we estimate that about 40 trapped electrons per nanowire are responsible for the bistability.

Non Volatile Flash Memory Radiation Tests

NASA Technical Reports Server (NTRS)

Irom, Farokh; Nguyen, Duc N.; Allen, Greg

2012-01-01

Commercial flash memory industry has experienced a fast growth in the recent years, because of their wide spread usage in cell phones, mp3 players and digital cameras. On the other hand, there has been increased interest in the use of high density commercial nonvolatile flash memories in space because of ever increasing data requirements and strict power requirements. Because of flash memories complex structure; they cannot be treated as just simple memories in regards to testing and analysis. It becomes quite challenging to determine how they will respond in radiation environments.

High-performance a MoS2 nanosheet-based nonvolatile memory transistor with a ferroelectric polymer and graphene source-drain electrode

NASA Astrophysics Data System (ADS)

Lee, Young Tack; Hwang, Do Kyung; Im, Seongil

2015-11-01

Two-dimensional (2D) van der Waals (vdWs) materials are a class of new materials due to their unique physical properties. Of the many 2D vdWs materials, molybdenum disulfide (MoS2) is a representative n-type transition-metal dichalcogenide (TMD) semiconductor. Here, we report on a high-performance MoS2 nanosheet-based nonvolatile memory transistor with a poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) ferroelectric top gate insulator. In order to enhance the ohmic contact property, we use graphene flakes as source/drain electrodes prepared by using the direct imprinting method with an elastomer stamp. The MoS2 ferroelectric field-effect transistor (FeFET) shows the highest linear electron mobility value of 175 cm2/Vs with a high on/off current ratio of more than 107, and a very clear memory window of more than 15 V. The program and erase dynamics and the static retention properties are also well demonstrated.

Biologically active nanocomposite of DNA-PbS nanoparticles: A new material for non-volatile memory devices

NASA Astrophysics Data System (ADS)

Murgunde, B. K.; Rabinal, M. K.; Kalasad, M. N.

2018-01-01

Composite films of deoxyribonucleic acid (DNA) and lead sulfide (PbS) nanoparticles are prepared to fabricate biological memory devices. A simple solution based electrografting is developed to deposit large (few cm2) uniform films of DNA:PbS on conducting substrates. The films are studied by X-ray photoelectron spectroscopy, field emission SEM, FTIR and optical spectroscopy to understand their properties. Charge transport measurements are carried out on ITO-DNA:PbS-metal junctions by cyclic voltage scans, electrical bi-stability is observed with ON/OFF ratio more than ∼104 times with good stability and endurance, such performance being rarely reported. The observed results are interpreted in the light of strong electrostatic binding of nanoparticles and DNA stands, which leads doping of Pb atoms into DNA. As a result, these devices exhibit negative differential resistance (NDR) effect due to oxidation of doped metal atoms. These composites can be the potential materials in the development of new generation non-volatile memory devices.

Electrical bistabilities and memory mechanisms of nonvolatile organic bistable devices based on exfoliated muscovite-type mica nanoparticle/poly(methylmethacrylate) nanocomposites

NASA Astrophysics Data System (ADS)

Lim, Won Gyu; Lee, Dea Uk; Na, Han Gil; Kim, Hyoun Woo; Kim, Tae Whan

2018-02-01

Organic bistable devices (OBDs) with exfoliated mica nanoparticles (NPs) embedded into an insulating poly(methylmethacrylate) (PMMA) layer were fabricated by using a spin-coating method. Current-voltage (I-V) curves for the Al/PMMA/exfoliated mica NP/PMMA/indium-tin-oxide/glass devices at 300 K showed a clockwise current hysteresis behavior due to the existence of the exfoliated muscovite-type mica NPs, which is an essential feature for bistable devices. Write-read-erase-read data showed that the OBDs had rewritable nonvolatile memories and an endurance number of ON/OFF switching for the OBDs of 102 cycles. An ON/OFF ratio of 1 × 103 was maintained for retention times larger than 1 × 104 s. The memory mechanisms of the fabricated OBDs were described by using the trapping and the tunneling processes within a PMMA active layer containing exfoliated muscovite-type mica NPs on the basis of the energy band diagram and the I-V curves.

Functionalized Graphitic Carbon Nitride for Metal-free, Flexible and Rewritable Nonvolatile Memory Device via Direct Laser-Writing

PubMed Central

Zhao, Fei; Cheng, Huhu; Hu, Yue; Song, Long; Zhang, Zhipan; Jiang, Lan; Qu, Liangti

2014-01-01

Graphitic carbon nitride nanosheet (g-C3N4-NS) has layered structure similar with graphene nanosheet and presents unusual physicochemical properties due to the s-triazine fragments. But their electronic and electrochemical applications are limited by the relatively poor conductivity. The current work provides the first example that atomically thick g-C3N4-NSs are the ideal candidate as the active insulator layer with tunable conductivity for achieving the high performance memory devices with electrical bistability. Unlike in conventional memory diodes, the g-C3N4-NSs based devices combined with graphene layer electrodes are flexible, metal-free and low cost. The functionalized g-C3N4-NSs exhibit desirable dispersibility and dielectricity which support the all-solution fabrication and high performance of the memory diodes. Moreover, the flexible memory diodes are conveniently fabricated through the fast laser writing process on graphene oxide/g-C3N4-NSs/graphene oxide thin film. The obtained devices not only have the nonvolatile electrical bistability with great retention and endurance, but also show the rewritable memory effect with a reliable ON/OFF ratio of up to 105, which is the highest among all the metal-free flexible memory diodes reported so far, and even higher than those of metal-containing devices. PMID:25073687

Apparatus for sensing patterns of electrical field variations across a surface

DOE Office of Scientific and Technical Information (OSTI.GOV)

Warren, William L.; Devine, Roderick A. B.

An array of nonvolatile field effect transistors used to sense electric potential variations. The transistors owe their nonvolatility to the movement of protons within the oxide layer that occurs only in response to an externally applied electric potential between the gate on one side of the oxide and the source/drain on the other side. The position of the protons within the oxide layer either creates or destroys a conducting channel in the adjacent source/channel/drain layer below it, the current in the channel being measured as the state of the nonvolatile memory. The protons can also be moved by potentials createdmore » by other instrumentalities, such as charges on fingerprints or styluses above the gates, pressure on a piezoelectric layer above the gates, light shining upon a photoconductive layer above the gates. The invention allows sensing of fingerprints, handwriting, and optical images, which are converted into digitized images thereof in a nonvolatile format.« less

Electric field controlled strain induced reversible switching of magnetization in Galfenol nanomagnets delineated on PMN-PT substrate

NASA Astrophysics Data System (ADS)

Ahmad, Hasnain; Atulasimha, Jayasimha; Bandyopadhyay, Supriyo

We report a non-volatile converse magneto-electric effect in elliptical Galfenol (FeGa) nanomagnets of ~300 nm lateral dimensions and ~10nm thickness delineated on a PMN-PT substrate. This effect can be harnessed for energy-efficient non-volatile memory. The nanomagnets are fabricated with e-beam lithography and sputtering. Their major axes are aligned parallel to the direction in which the substrate is poled and they are magnetized in this direction with a magnetic field. An electric field in the opposite direction generates compressive strain in the piezoelectric substrate which is partially transferred to the nanomagnets and rotates their magnetization away from the major axes to metastable orientations. There they remain after the field is removed, resulting in non-volatility. Reversing the electric field generates tensile strain which returns the magnetization to the original state. The two states can encode two binary bits which can be written using the correct voltage polarity, resulting in non-toggle behavior. Scaled memory fashioned on this effect can exhibit write energy dissipation of only ~2 aJ. Work is supported by NSF under ECCS-1124714 and CCF-1216614. Sputtering was carried out at NIST Gaithersburg.

CMOS-compatible spintronic devices: a review

NASA Astrophysics Data System (ADS)

Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

2016-11-01

For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

Thermal annealing and temperature dependences of memory effect in organic memory transistor

NASA Astrophysics Data System (ADS)

Ren, X. C.; Wang, S. M.; Leung, C. W.; Yan, F.; Chan, P. K. L.

2011-07-01

We investigate the annealing and thermal effects of organic non-volatile memory with floating silver nanoparticles by real-time transfer curve measurements. During annealing, the memory window shows shrinkage of 23% due to structural variation of the nanoparticles. However, by increasing the device operating temperature from 20 to 90 °C after annealing, the memory window demonstrates an enlargement up to 100%. The differences in the thermal responses are explained and confirmed by the co-existence of electron and hole traps. Our findings provide a better understanding of organic memory performances under various operating temperatures and validate their applications for temperature sensing or thermal memories.

Piezoelectric control of magnetoelectric coupling driven non-volatile memory switching and self cooling effects in FE/FSMA multiferroic heterostructures

NASA Astrophysics Data System (ADS)

Singh, Kirandeep; Kaur, Davinder

2017-02-01

The manipulation of magnetic states and materials' spin degree-of-freedom via a control of an electric (E-) field has been recently pursued to develop magnetoelectric (ME) coupling-driven electronic data storage devices with high read/write endurance, fast dynamic response, and low energy dissipation. One major hurdle for this approach is to develop reliable materials which should be compatible with prevailing silicon (Si)-based complementary metal-oxide-semiconductor (CMOS) technology, simultaneously allowing small voltage for the tuning of magnetization switching. In this regard, multiferroic heterostructures where ferromagnetic (FM) and ferroelectric (FE) layers are alternatively grown on conventional Si substrates are promising as the piezoelectric control of magnetization switching is anticipated to be possible by an E-field. In this work, we study the ferromagnetic shape memory alloys based PbZr0.52Ti0.48O3/Ni50Mn35In15 (PZT/Ni-Mn-In) multiferroic heterostructures, and investigate their potential for CMOS compatible non-volatile magnetic data storage applications. We demonstrate the voltage-impulse controlled nonvolatile, reversible, and bistable magnetization switching at room temperature in Si-integrated PZT/Ni-Mn-In thin film multiferroic heterostructures. We also thoroughly unveil the various intriguing features in these materials, such as E-field tuned ME coupling and magnetocaloric effect, shape memory induced ferroelectric modulation, improved fatigue endurance as well as Refrigeration Capacity (RC). This comprehensive study suggests that these novel materials have a great potential for the development of unconventional nanoscale memory and refrigeration devices with self-cooling effect and enhanced refrigeration efficiency, thus providing a new venue for their applications.

Design of a magnetic-tunnel-junction-oriented nonvolatile lookup table circuit with write-operation-minimized data shifting

NASA Astrophysics Data System (ADS)

Suzuki, Daisuke; Hanyu, Takahiro

2018-04-01

A magnetic-tunnel-junction (MTJ)-oriented nonvolatile lookup table (LUT) circuit, in which a low-power data-shift function is performed by minimizing the number of write operations in MTJ devices is proposed. The permutation of the configuration memory cell for read/write access is performed as opposed to conventional direct data shifting to minimize the number of write operations, which results in significant write energy savings in the data-shift function. Moreover, the hardware cost of the proposed LUT circuit is small since the selector is shared between read access and write access. In fact, the power consumption in the data-shift function and the transistor count are reduced by 82 and 52%, respectively, compared with those in a conventional static random-access memory-based implementation using a 90 nm CMOS technology.

Hierarchically Self-Assembled Block Copolymer Blends for Templating Hollow Phase-Change Nanostructures with an Extremely Low Switching Current

DOE PAGES

Park, Woon Ik; Kim, Jong Min; Jeong, Jae Won; ...

2015-03-17

Phase change memory (PCM) is one of the most promising candidates for next-generation nonvolatile memory devices because of its high speed, excellent reliability, and outstanding scalability. But, the high switching current of PCM devices has been a critical hurdle to realize low-power operation. Although one solution is to reduce the switching volume of the memory, the resolution limit of photolithography hinders further miniaturization of device dimensions. Here, we employed unconventional self-assembly geometries obtained from blends of block copolymers (BCPs) to form ring-shaped hollow PCM nanostructures with an ultrasmall contact area between a phase-change material (Ge 2Sb 2Te 5) and amore » heater (TiN) electrode. The high-density (approximately 0.1 terabits per square inch) PCM nanoring arrays showed extremely small switching current of 2-3 mu A. Furthermore, the relatively small reset current of the ring-shaped PCM compared to the pillar-shaped devices is attributed to smaller switching volume, which is well supported by electro-thermal simulation results. Our approach may also be extended to other nonvolatile memory device applications such as resistive switching memory and magnetic storage devices, where the control of nanoscale geometry can significantly affect device performances.« less

Multibit data storage states formed in plasma-treated MoS₂ transistors.

PubMed

Chen, Mikai; Nam, Hongsuk; Wi, Sungjin; Priessnitz, Greg; Gunawan, Ivan Manuel; Liang, Xiaogan

2014-04-22

New multibit memory devices are desirable for improving data storage density and computing speed. Here, we report that multilayer MoS2 transistors, when treated with plasmas, can dramatically serve as low-cost, nonvolatile, highly durable memories with binary and multibit data storage capability. We have demonstrated binary and 2-bit/transistor (or 4-level) data states suitable for year-scale data storage applications as well as 3-bit/transistor (or 8-level) data states for day-scale data storage. This multibit memory capability is hypothesized to be attributed to plasma-induced doping and ripple of the top MoS2 layers in a transistor, which could form an ambipolar charge-trapping layer interfacing the underlying MoS2 channel. This structure could enable the nonvolatile retention of charged carriers as well as the reversible modulation of polarity and amount of the trapped charge, ultimately resulting in multilevel data states in memory transistors. Our Kelvin force microscopy results strongly support this hypothesis. In addition, our research suggests that the programming speed of such memories can be improved by using nanoscale-area plasma treatment. We anticipate that this work would provide important scientific insights for leveraging the unique structural property of atomically layered two-dimensional materials in nanoelectronic applications.

Reconfigurable Electronics and Non-Volatile Memory Research

DTIC Science & Technology

2015-11-10

Kirtland AFB, NM 87117-5776 2 cys Official Record Copy AFRL /RVSE/Arthur Edwards 1 cy... AFRL -RV-PS- AFRL -RV-PS- TR-2015-0151 TR-2015-0151 RECONFIGURABLE ELECTRONICS AND NON- VOLATILE MEMORY RESEARCH Kristy A. Campbell Boise State... KIRTLAND AIR FORCE BASE, NM 87117-5776 NOTICE AND SIGNATURE PAGE Using Government drawings, specifications, or other data included in this document for

Evaluation of Ferroelectric Materials for Memory Applications

DTIC Science & Technology

1990-06-01

as automobile odometers, access counters, and flight time recorders. Detailed product information is provided in Appendix A. 3. Optical Read...volatility but by definition are not reprogrammable , which severely restricts flexibility and makes error correction difficult. Magnetic core is non...battery-backed SRAMs as well. The programs for embedded controllers, such as those increasingly used in automobiles , are kept in nonvolatile memory. The

A Vertical Organic Transistor Architecture for Fast Nonvolatile Memory.

PubMed

She, Xiao-Jian; Gustafsson, David; Sirringhaus, Henning

2017-02-01

A new device architecture for fast organic transistor memory is developed, based on a vertical organic transistor configuration incorporating high-performance ambipolar conjugated polymers and unipolar small molecules as the transport layers, to achieve reliable and fast programming and erasing of the threshold voltage shift in less than 200 ns. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Integration of lead-free ferroelectric on HfO2/Si (100) for high performance non-volatile memory applications

PubMed Central

Kundu, Souvik; Maurya, Deepam; Clavel, Michael; Zhou, Yuan; Halder, Nripendra N.; Hudait, Mantu K.; Banerji, Pallab; Priya, Shashank

2015-01-01

We introduce a novel lead-free ferroelectric thin film (1-x)BaTiO3-xBa(Cu1/3Nb2/3)O3 (x = 0.025) (BT-BCN) integrated on to HfO2 buffered Si for non-volatile memory (NVM) applications. Piezoelectric force microscopy (PFM), x-ray diffraction, and high resolution transmission electron microscopy were employed to establish the ferroelectricity in BT-BCN thin films. PFM study reveals that the domains reversal occurs with 180° phase change by applying external voltage, demonstrating its effectiveness for NVM device applications. X-ray photoelectron microscopy was used to investigate the band alignments between atomic layer deposited HfO2 and pulsed laser deposited BT-BCN films. Programming and erasing operations were explained on the basis of band-alignments. The structure offers large memory window, low leakage current, and high and low capacitance values that were easily distinguishable even after ~106 s, indicating strong charge storage potential. This study explains a new approach towards the realization of ferroelectric based memory devices integrated on Si platform and also opens up a new possibility to embed the system within current complementary metal-oxide-semiconductor processing technology. PMID:25683062

Biomolecule nanoparticle-induced nanocomposites with resistive switching nonvolatile memory properties

NASA Astrophysics Data System (ADS)

Ko, Yongmin; Ryu, Sook Won; Cho, Jinhan

2016-04-01

Resistive switching behavior-based memory devices are considered promising candidates for next-generation data storage because of their simple structure configuration, low power consumption, and rapid operating speed. Here, the resistive switching nonvolatile memory properties of Fe2O3 nanocomposite (NC) films prepared from the thermal calcination of layer-by-layer (LbL) assembled ferritin multilayers were successfully investigated. For this study, negatively charged ferritin nanoparticles were alternately deposited onto the Pt-coated Si substrate with positively charged poly(allylamine hydrochloride) (PAH) by solution-based electrostatic LbL assembly, and the formed multilayers were thermally calcinated to obtain a homogeneous transition metal oxide NC film through the elimination of organic components, including the protein shell of ferritin. The formed memory device exhibits a stable ON/OFF current ratio of approximately 103, with nanosecond switching times under an applied external bias. In addition, these reversible switching properties were kept stable during the repeated cycling tests of above 200 cycles and a test period of approximately 105 s under atmosphere. These solution-based approaches can provide a basis for large-area inorganic nanoparticle-based electric devices through the design of bio-nanomaterials at the molecular level.

Modeling of Sonos Memory Cell Erase Cycle

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memories (NVSMS) have many advantages. These memories are electrically erasable programmable read-only memories (EEPROMs). They utilize low programming voltages, endure extended erase/write cycles, are inherently resistant to radiation, and are compatible with high-density scaled CMOS for low power, portable electronics. The SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. The SONOS floating gate charge and voltage, tunneling current, threshold voltage, and drain current were characterized during an erase cycle. Comparisons were made between the model predictions and experimental device data.

Radiation Issues and Applications of Floating Gate Memories

NASA Technical Reports Server (NTRS)

Scheick, L. Z.; Nguyen, D. N.

2000-01-01

The radiation effects that affect various systems that comprise floating gate memories are presented. The wear-out degradation results of unirradiated flash memories are compared to irradiated flash memories. The procedure analyzes the failure to write and erase caused by wear-out and degradation of internal charge pump circuits. A method is described for characterizing the radiation effects of the floating gate itself. The rate dependence, stopping power dependence, SEU susceptibility and applications of floating gate in radiation environment are presented. The ramifications for dosimetry and cell failure are discussed as well as for the long term use aspects of non-volatile memories.

77 FR 58473 - Minimum Technical Standards for Class II Gaming Systems and Equipment

Federal Register 2010, 2011, 2012, 2013, 2014

2012-09-21

... as printed advertising material that cannot be validated directly by a voucher system. Critical... on that component. EPROM. Erasable Programmable Read Only Memory--a non-volatile storage chip or...

Novel Organic Phototransistor-Based Nonvolatile Memory Integrated with UV-Sensing/Green-Emissive Aggregation Enhanced Emission (AEE)-Active Aromatic Polyamide Electret Layer.

PubMed

Cheng, Shun-Wen; Han, Ting; Huang, Teng-Yung; Chang Chien, Yu-Hsin; Liu, Cheng-Liang; Tang, Ben Zhong; Liou, Guey-Sheng

2018-05-30

A novel aggregation enhanced emission (AEE)-active polyamide TPA-CN-TPE with a high photoluminesence characteristic was successfully synthesized by the direct polymerization of 4-cyanotriphenyl diamine (TPA-CN) and tetraphenylethene (TPE)-containing dicarboxylic acid. The obtained luminescent polyamide plays a significant role as the polymer electret layer in organic field-effect transistors (OFETs)-type memory. The strong green emission of TPA-CN-TPE under ultraviolet (UV) irradiation can be directly absorbed by the pentacene channel, displaying a light-induced programming and voltage-driven erasing organic phototransistor-based nonvolatile memory. Memory window can be effectively manipulated between the programming and erasing states by applying UV light illumination and electrical field, respectively. The photoinduced memory behavior can be maintained for over 10 4 s between these two states with an on/off ratio of 10 4 , and the memory switching can be steadily operated for many cycles. With high photoresponsivity ( R) and photosensitivity ( S), this organic phototransistor integrated with AEE-active polyamide electret layer could serve as an excellent candidate for UV photodetectors in optical applications. For comparison, an AEE-inactive aromatic polyimide TPA-PIS electret with much weaker solid-state emission was also applied in the same OFETs device architecture, but this device did not show any UV-sensitive and UV-induced memory characteristics, which further confirmed the significance of the light-emitting capability of the electret layer.

EDITORIAL: Non-volatile memory based on nanostructures Non-volatile memory based on nanostructures

NASA Astrophysics Data System (ADS)

Kalinin, Sergei; Yang, J. Joshua; Demming, Anna

2011-06-01

Non-volatile memory refers to the crucial ability of computers to store information once the power source has been removed. Traditionally this has been achieved through flash, magnetic computer storage and optical discs, and in the case of very early computers paper tape and punched cards. While computers have advanced considerably from paper and punched card memory devices, there are still limits to current non-volatile memory devices that restrict them to use as secondary storage from which data must be loaded and carefully saved when power is shut off. Denser, faster, low-energy non-volatile memory is highly desired and nanostructures are the critical enabler. This special issue on non-volatile memory based on nanostructures describes some of the new physics and technology that may revolutionise future computers. Phase change random access memory, which exploits the reversible phase change between crystalline and amorphous states, also holds potential for future memory devices. The chalcogenide Ge2Sb2Te5 (GST) is a promising material in this field because it combines a high activation energy for crystallization and a relatively low crystallization temperature, as well as a low melting temperature and low conductivity, which accommodates localized heating. Doping is often used to lower the current required to activate the phase change or 'reset' GST but this often aggravates other problems. Now researchers in Korea report in-depth studies of SiO2-doped GST and identify ways of optimising the material's properties for phase-change random access memory [1]. Resistance switching is an area that has attracted a particularly high level of interest for non-volatile memory technology, and a great deal of research has focused on the potential of TiO2 as a model system in this respect. Researchers at HP labs in the US have made notable progress in this field, and among the work reported in this special issue they describe means to control the switch resistance and show that limiting the current during electroforming leads to the coexistence of two resistance switching modes in TiO2 memristive devices [2]. They also present spectromicroscopic observations and modelling results for the Joule heating during switching, providing insights into the ON/OFF switching process [3]. Researchers in Korea have examined in detail the mechanism of electronic bipolar resistance switching in the Pt/TiO2/Pt structure and show that degradation in switching performance of this system can be explained by the modified distribution of trap densities [4]. The issue also includes studies of TiO2 that demonstrate analog memory, synaptic plasticity, and spike-timing-dependent plasticity functions, work that contributes to the development of neuromorphic devices that have high efficiency and low power consumption [5]. In addition to enabling a wide range of data storage and logic applications, electroresistive non-volatile memories invite us to re-evaluate the long-held paradigms in the condensed matter physics of oxides. In the past three years, much attention has been attracted to polarization-mediated electronic transport [6, 7] and domain wall conduction [8] as the key to the next generation of electronic and spintronic devices based on ferroelectric tunnelling barriers. Typically local probe experiments are performed on an ambient scanning probe microscope platform under conditions of high voltage stresses, conditions highly conducive to electrochemical reactions. Recent experiments [9-13] suggest that ionic motion can heavily contribute to the measured responses and compete with purely physical mechanisms. Electrochemical effects can also be expected in non-ferroelectric materials such as manganites and cobaltites, as well as for thick ferroelectrics under high-field conditions, as in capacitors and tunnelling junctions where the ionic motion could be a major contributor to electric field-induced strain. Such strain, in turn, can affect the effective barrier width in tunnelling experiments, resulting in memristive ionic switching. These phenomena must be differentiated from intrinsic physical polarization switching effects. Similar analysis of solid-state electrochemistry versus physical mechanisms is also important for future research in all areas of oxide materials. In an age where miniaturised computer components can enable GPS tracking, internet access and even the remote operation of machinery from a mobile phone, there is an endearing quaintness associated with images of the large rooms rammed with wires and boxes that comprised early computers. Yet there was a time when these cumbersome devices were state of the art. When the electronic numerical integrator and computer (ENIAC) was developed it achieved speeds one thousand times faster than previous electromechanical machines, a leap in processing power that has not been achieved since. It is easy to imagine future generations looking back on the slow start up and shut down times and high energy consumption of today's computers with a similar wry smile. The articles in this special issue on non-volatile memory based on nanostructures present the very latest research into the next generation's device technology, which may eventually consign today's cutting edge electronics to the history books. References [1] Ryu S W et al 2011 Nanotechnology 22 254005 [2] Miao F, Yang J J, Borghetti J, Medeiros-Ribeiro G and Williams R S 2011 Nanotechnology 22 254007 [3] Strachan J P, Strukov D B, Borghetti J, Yang J J, Medeiros-Ribeiro G and Williams R S 2011 Nanotechnology 22 245015 [4] Kim K M, Choi B J, Lee M H, Kim G H, Song S J, Seok J Y, Yoon J H, Han S and Hwang C S 2011 Nanotechnology 22 254010 [5] Seo K et al 2011 Nanotechnology 22 254023 [6] Garcia V, Fusil S, Bouzehouane K, Enouz-Vedrenne S, Mathur N D, Barthelemy A and Bibes M 2009 Nature 460 81-4 [7] Maksymovych P, Jesse S, Yu P, Ramesh R, Baddorf A P and Kalinin S V 2009 Science 324 1421 [8] Seidel J et al 2009 Nature Mat. 8 229 [9] Tsuruoka T, Terabe K, Hasegawa T, and Aono M 2010 Nanotechnology 21 425205 [10] Waser R and Aono M 2007 Nature Mat. 6 833 [11] Sawa A 2008 Materials Today 11 28 [12] Strukov D B, Snider G S, Stewart D R and Williams R S 2008 Nature 453 80 Changes were made to this Editorial on 16 May 2011. An author was added to the Editorial.

Blackcomb: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schreiber, Robert

Summary of technical results of Blackcomb Memory Devices We explored various different memory technologies (STTRAM, PCRAM, FeRAM, and ReRAM). The progress can be classified into three categories, below. Modeling and Tool Releases Various modeling tools have been developed over the last decade to help in the design of SRAM or DRAM-based memory hierarchies. To explore new design opportunities that NVM technologies can bring to the designers, we have developed similar high-level models for NVM, including PCRAMsim [Dong 2009], NVSim [Dong 2012], and NVMain [Poremba 2012]. NVSim is a circuit-level model for NVM performance, energy, and area estimation, which supports variousmore » NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies. On the other side, NVMain is a cycle accurate main memory simulator designed to simulate emerging nonvolatile memories at the architectural level. We have released these models as open source tools and provided contiguous support to them. We also proposed PS3-RAM, which is a fast, portable and scalable statistical STT-RAM reliability analysis model [Wen 2012]. Design Space Exploration and Optimization With the support of these models, we explore different device/circuit optimization techniques. For example, in [Niu 2012a] we studied the power reduction technique for the application of ECC scheme in ReRAM designs and proposed to use ECC code to relax the BER (Bit Error Rate) requirement of a single memory to improve the write energy consumption and latency for both 1T1R and cross-point ReRAM designs. In [Xu 2011], we proposed a methodology to design STT-RAM for different optimization goals such as read performance, write performance and write energy by leveraging the trade-off between write current and write time of MTJ. We also studied the tradeoffs in building a reliable crosspoint ReRAM array [Niu 2012b]. We have conducted an in depth analysis of the circuit and system level design implications of multi-layer cross-point Resistive RAM (MLCReRAM) from performance, power and reliability perspectives [Xu 2013]. The objective of this study is to understand the design trade-offs of this technology with respect to the MLC Phase Change Memory (MLCPCM).Our MLC ReRAM design at the circuit and system levels indicates that different resistance allocation schemes, programming strategies, peripheral designs, and material selections profoundly affect the area, latency, power, and reliability of MLC ReRAM. Based on this analysis, we conduct two case studies: first we compare MLC ReRAM design against MLC phase-change memory (PCM) and multi-layer cross-point ReRAM design, and point out why multi-level ReRAM is appealing; second we further explore the design space for MLC ReRAM. Architecture and Application We explored hybrid checkpointing using phase-change memory for future exascale systems [Dong 2011] and showed that the use of nonvolatile memory for local checkpointing significantly increases the number of faults covered by local checkpoints and reduces the probability of a global failure in the middle of a global checkpoint to less than 1%. We also proposed a technique called i2WAP to mitigate the write variations in NVM-based last-level cache for the improvement of the NVM lifetime [Wang 2013]. Our wear leveling technique attempts to work around the limitations of write endurance by arranging data access so that write operations can be distributed evenly across all the storage cells. During our intensive research on fault-tolerant NVM design, we found that ECC cannot effectively tolerate hard errors from limited write endurance and process imperfection. Therefore, we devised a novel Point and Discard (PAD) architecture in in [ 2012] as a hard-error-tolerant architecture for ReRAM-based Last Level Caches. PAD improves the lifetime of ReRAM caches by 1.6X-440X under different process variations without performance overhead in the system's early life. We have investigated the applicability of NVM for persistent memory design [Zhao 2013]. New byte addressable NVM enables fast persistent memory that allows in-memory persistent data objects to be updated with much higher throughput. Despite the significant improvement, the performance of these designs is only 50% of the native system with no persistence support, due to the logging or copy-on-write mechanisms used to update the persistent memory. A challenge in this approach is therefore how to efficiently enable atomic, consistent, and durable updates to ensure data persistence that survives application and/or system failures. We have designed a persistent memory system, called Klin, that can provide performance as close as that of the native system. The Klin design adopts a non-volatile cache and a non-volatile main memory for constructing a multi-versioned durable memory system, enabling atomic updates without logging or copy-on-write. Our evaluation shows that the proposed Kiln mechanism can achieve up to 2X of performance improvement to NVRAM-based persistent memory employing write-ahead logging. In addition, our design has numerous practical advantages: a simple and intuitive abstract interface, microarchitecture-level optimizations, fast recovery from failures, and no redundant writes to slow non-volatile storage media. The work was published in MICRO 2013 and received Best Paper Honorable Mentioned Award.« less

Nonvolatile memory with Co-SiO2 core-shell nanocrystals as charge storage nodes in floating gate

NASA Astrophysics Data System (ADS)

Liu, Hai; Ferrer, Domingo A.; Ferdousi, Fahmida; Banerjee, Sanjay K.

2009-11-01

In this letter, we reported nanocrystal floating gate memory with Co-SiO2 core-shell nanocrystal charge storage nodes. By using a water-in-oil microemulsion scheme, Co-SiO2 core-shell nanocrystals were synthesized and closely packed to achieve high density matrix in the floating gate without aggregation. The insulator shell also can help to increase the thermal stability of the nanocrystal metal core during the fabrication process to improve memory performance.

Switching behavior of resistive change memory using oxide nanowires

NASA Astrophysics Data System (ADS)

Aono, Takashige; Sugawa, Kosuke; Shimizu, Tomohiro; Shingubara, Shoso; Takase, Kouichi

2018-06-01

Resistive change random access memory (ReRAM), which is expected to be the next-generation nonvolatile memory, often has wide switching voltage distributions due to many kinds of conductive filaments. In this study, we have tried to suppress the distribution through the structural restriction of the filament-forming area using NiO nanowires. The capacitor with Ni metal nanowires whose surface is oxidized showed good switching behaviors with narrow distributions. The knowledge gained from our study will be very helpful in producing practical ReRAM devices.

An Investigation of Quantum Dot Super Lattice Use in Nonvolatile Memory and Transistors

NASA Astrophysics Data System (ADS)

Mirdha, P.; Parthasarathy, B.; Kondo, J.; Chan, P.-Y.; Heller, E.; Jain, F. C.

2018-02-01

Site-specific self-assembled colloidal quantum dots (QDs) will deposit in two layers only on p-type substrate to form a QD superlattice (QDSL). The QDSL structure has been integrated into the floating gate of a nonvolatile memory component and has demonstrated promising results in multi-bit storage, ease of fabrication, and memory retention. Additionally, multi-valued logic devices and circuits have been created by using QDSL structures which demonstrated ternary and quaternary logic. With increasing use of site-specific self-assembled QDSLs, fundamental understanding of silicon and germanium QDSL charge storage capability, self-assembly on specific surfaces, uniform distribution, and mini-band formation has to be understood for successful implementation in devices. In this work, we investigate the differences in electron charge storage by building metal-oxide semiconductor (MOS) capacitors and using capacitance and voltage measurements to quantify the storage capabilities. The self-assembly process and distribution density of the QDSL is done by obtaining atomic force microscopy (AFM) results on line samples. Additionally, we present a summary of the theoretical density of states in each of the QDSLs.

Reprogrammable logic in memristive crossbar for in-memory computing

NASA Astrophysics Data System (ADS)

Cheng, Long; Zhang, Mei-Yun; Li, Yi; Zhou, Ya-Xiong; Wang, Zhuo-Rui; Hu, Si-Yu; Long, Shi-Bing; Liu, Ming; Miao, Xiang-Shui

2017-12-01

Memristive stateful logic has emerged as a promising next-generation in-memory computing paradigm to address escalating computing-performance pressures in traditional von Neumann architecture. Here, we present a nonvolatile reprogrammable logic method that can process data between different rows and columns in a memristive crossbar array based on material implication (IMP) logic. Arbitrary Boolean logic can be executed with a reprogrammable cell containing four memristors in a crossbar array. In the fabricated Ti/HfO2/W memristive array, some fundamental functions, such as universal NAND logic and data transfer, were experimentally implemented. Moreover, using eight memristors in a 2  ×  4 array, a one-bit full adder was theoretically designed and verified by simulation to exhibit the feasibility of our method to accomplish complex computing tasks. In addition, some critical logic-related performances were further discussed, such as the flexibility of data processing, cascading problem and bit error rate. Such a method could be a step forward in developing IMP-based memristive nonvolatile logic for large-scale in-memory computing architecture.

A CMOS Compatible, Forming Free TaO x ReRAM

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lohn, A. J.; Stevens, J. E.; Mickel, P. R.

2013-08-31

Resistive random access memory (ReRAM) has become a promising candidate for next-generation high-performance non-volatile memory that operates by electrically tuning resistance states via modulating vacancy concentrations. Here, we demonstrate a wafer-scale process for resistive switching in tantalum oxide that is completely CMOS compatible. The resulting devices are forming-free and with greater than 1x10 5 cycle endurance.

Testing and operating a multiprocessor chip with processor redundancy

DOEpatents

Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

2014-10-21

A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

Optically controlled electroresistance and electrically controlled photovoltage in ferroelectric tunnel junctions

PubMed Central

Jin Hu, Wei; Wang, Zhihong; Yu, Weili; Wu, Tom

2016-01-01

Ferroelectric tunnel junctions (FTJs) have recently attracted considerable interest as a promising candidate for applications in the next-generation non-volatile memory technology. In this work, using an ultrathin (3 nm) ferroelectric Sm0.1Bi0.9FeO3 layer as the tunnelling barrier and a semiconducting Nb-doped SrTiO3 single crystal as the bottom electrode, we achieve a tunnelling electroresistance as large as 105. Furthermore, the FTJ memory states could be modulated by light illumination, which is accompanied by a hysteretic photovoltaic effect. These complimentary effects are attributed to the bias- and light-induced modulation of the tunnel barrier, both in height and width, at the semiconductor/ferroelectric interface. Overall, the highly tunable tunnelling electroresistance and the correlated photovoltaic functionalities provide a new route for producing and non-destructively sensing multiple non-volatile electronic states in such FTJs. PMID:26924259

Bipolar resistive switching in graphene oxide based metal insulator metal structure for non-volatile memory applications

NASA Astrophysics Data System (ADS)

Singh, Rakesh; Kumar, Ravi; Kumar, Anil; Kashyap, Rajesh; Kumar, Mukesh; Kumar, Dinesh

2018-05-01

Graphene oxide based devices have attracted much attention recently because of their possible application in next generation electronic devices. In this study, bipolar resistive switching characteristics of graphene oxide based metal insulator metal structure were investigated for nonvolatile memories. The graphene oxide was prepared by the conventional Hummer's method and deposited on ITO coated glass by spin-coating technique. The dominant mechanism of resistive switching is the formation and rupture of the conductive filament inside the graphene oxide. The conduction mechanism for low and high resistance states are dominated by two mechanism the ohmic conduction and space charge limited current (SCLC) mechanism, respectively. Atomic Force Microscopy, X-ray diffraction, Cyclic-Voltammetry were conducted to observe the morphology, structure and behavior of the material. The fabricated device with Al/GO/ITO structure exhibited reliable bipolar resistive switching with set & reset voltage of -2.3 V and 3V respectively.

Controlling the anomalous Hall effect by electric-field-induced piezo-strain in Fe40Pt60/(001)-Pb(Mg1/3Nb2/3)0.67Ti0.33O3 multiferroic heterostructures

NASA Astrophysics Data System (ADS)

Yang, Yuanjun; Yao, Yingxue; Chen, Lei; Huang, Haoliang; Zhang, Benjian; Lin, Hui; Luo, Zhenlin; Gao, Chen; Lu, Y. L.; Li, Xiaoguang; Xiao, Gang; Feng, Ce; Zhao, Y. G.

2018-01-01

Electric-field control of the anomalous Hall effect (AHE) was investigated in Fe40Pt60/(001)-Pb(Mg1/3Nb2/3)0.67Ti0.33O3 (FePt/PMN-PT) multiferroic heterostructures at room temperature. It was observed that a very large Hall resistivity change of up to 23.9% was produced using electric fields under a magnetic field bias of 100 Oe. A pulsed electric field sequence was used to generate nonvolatile strain to manipulate the Hall resistivity. Two corresponding nonvolatile states with distinct Hall resistivities were achieved after the electric fields were removed, thus enabling the encoding of binary information for memory applications. These results demonstrate that the Hall resistivity can be reversibly switched in a nonvolatile manner using programmable electric fields. Two remanent magnetic states that were created by electric-field-induced piezo-strain from the PMN-PT were attributed to the nonvolatile and reversible properties of the AHE. This work suggests that a low-energy-consumption-based approach can be used to create nonvolatile resistance states for spintronic devices based on electric-field control of the AHE.

Piezostrain tuning non-volatile 90° magnetic easy axis rotation in Co2FeAl Heusler alloy film grown on Pb(Mg1/3Nb2/3)O3-PbTiO3 heterostructures

NASA Astrophysics Data System (ADS)

Zhou, Cai; Wang, Fenglong; Dunzhu, Gesang; Yao, Jinli; Jiang, Changjun

2016-11-01

Non-volatile electric field-based control of magnetic anisotropy in Co2FeAl/ Pb(Mg1/3Nb2/3)O3-PbTiO3 (CFA/PMN-PT) heterostructures is investigated at room temperature. The remnant magnetization response under different electric fields shows a asymmetric butterfly-like behavior; specifically, this behavior is consistent with the asymmetric butterfly-like piezostrain versus applied electric field curve. Thus electric field-induced non-volatile 90° magnetic easy axis rotation can be attributed to the piezostrain effect. Further, the result measured by rotating-angle ferromagnetic resonance demonstrates piezostrain-mediated non-volatile 90° magnetic easy axis rotation at the initial state and the two remnant polarization states after application of the poling fields of 10 and  -10 kV cm-1 turned off. The angular dependence of magnetic damping also indicates a 90° phase shift at the above mentioned three different states. Additionally, the piezostrain-mediated non-volatile stable magnetization reversal in the two directions of easy and hard magnetization axes are observed under positive and negative pulsed electric fields, which can be used to improve the performance of low-loss multiple-state memory devices.

Optimization of Phase Change Memory with Thin Metal Inserted Layer on Material Properties

NASA Astrophysics Data System (ADS)

Harnsoongnoen, Sanchai; Sa-Ngiamsak, Chiranut; Siritaratiwat, Apirat

This works reports, for the first time, the thorough study and optimisation of Phase Change Memory (PCM) structure with thin metal inserted chalcogenide via electrical resistivity (ρ) using finite element modeling. PCM is one of the best candidates for next generation non-volatile memory. It has received much attention recently due to its fast write speed, non-destructive readout, superb scalability, and great compatibility with current silicon-based mass fabrication. The setback of PCM is a high reset current typically higher than 1mA based on 180nm lithography. To reduce the reset current and to solve the over-programming failure, PCM with thin metal inserted chalcogenide (bottom chalcogenide/metal inserted/top chalcogenide) structure has been proposed. Nevertheless, reports on optimisation of the electrical resistivity using the finite element method for this new PCM structure have never been published. This work aims to minimize the reset current of this PCM structure by optimizing the level of the electrical resistivity of the PCM profile using the finite element approach. This work clearly shows that PCM characteristics are strongly affected by the electrical resistivity. The 2-D simulation results reveal clearly that the best thermal transfer of and self-joule-heating at the bottom chalcogenide layer can be achieved under conditions; ρ_bottom chalcogenide > ρ_metal inserted > ρ_top chalcogenide More specifically, the optimized electrical resistivity of PCMTMI is attained with ρ_top chalcogenide: ρ_metal inserted: ρ_bottom chalcogenide ratio of 1:6:16 when ρ_top chalcogenide is 10-3 Ωm. In conclusion, high energy efficiency can be obtained with the reset current as low as 0.3mA and with high speed operation of less than 30ns.

Study of the photovoltaic effect in thin film barium titanate

NASA Technical Reports Server (NTRS)

Grannemann, W. W.; Dharmadhikari, V. S.

1983-01-01

The feasibility of making non-volatile digital memory devices of barium titanate, BaTiO3, that are integrated onto a silicon substrate with the required ferroelectric film produced by processing, compatible with silicon technology was examined.

Three-terminal resistive switching memory in a transparent vertical-configuration device

NASA Astrophysics Data System (ADS)

Ungureanu, Mariana; Llopis, Roger; Casanova, Fèlix; Hueso, Luis E.

2014-01-01

The resistive switching phenomenon has attracted much attention recently for memory applications. It describes the reversible change in the resistance of a dielectric between two non-volatile states by the application of electrical pulses. Typical resistive switching memories are two-terminal devices formed by an oxide layer placed between two metal electrodes. Here, we report on the fabrication and operation of a three-terminal resistive switching memory that works as a reconfigurable logic component and offers an increased logic density on chip. The three-terminal memory device we present is transparent and could be further incorporated in transparent computing electronic technologies.

Magnetic vortex racetrack memory

NASA Astrophysics Data System (ADS)

Geng, Liwei D.; Jin, Yongmei M.

2017-02-01

We report a new type of racetrack memory based on current-controlled movement of magnetic vortices in magnetic nanowires with rectangular cross-section and weak perpendicular anisotropy. Data are stored through the core polarity of vortices and each vortex carries a data bit. Besides high density, non-volatility, fast data access, and low power as offered by domain wall racetrack memory, magnetic vortex racetrack memory has additional advantages of no need for constrictions to define data bits, changeable information density, adjustable current magnitude for data propagation, and versatile means of ultrafast vortex core switching. By using micromagnetic simulations, current-controlled motion of magnetic vortices in cobalt nanowire is demonstrated for racetrack memory applications.

Organic memory device with self-assembly monolayered aptamer conjugated nanoparticles

NASA Astrophysics Data System (ADS)

Oh, Sewook; Kim, Minkeun; Kim, Yejin; Jung, Hunsang; Yoon, Tae-Sik; Choi, Young-Jin; Jung Kang, Chi; Moon, Myeong-Ju; Jeong, Yong-Yeon; Park, In-Kyu; Ho Lee, Hyun

2013-08-01

An organic memory structure using monolayered aptamer conjugated gold nanoparticles (Au NPs) as charge storage nodes was demonstrated. Metal-pentacene-insulator-semiconductor device was adopted for the non-volatile memory effect through self assembly monolayer of A10-aptamer conjugated Au NPs, which was formed on functionalized insulator surface with prostate-specific membrane antigen protein. The capacitance versus voltage (C-V) curves obtained for the monolayered Au NPs capacitor exhibited substantial flat-band voltage shift (ΔVFB) or memory window of 3.76 V under (+/-)7 V voltage sweep. The memory device format can be potentially expanded to a highly specific capacitive sensor for the aptamer-specific biomolecule detection.

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

NASA Astrophysics Data System (ADS)

Yu, Jie; Chen, Kun-ji; Ma, Zhong-yuan; Zhang, Xin-xin; Jiang, Xiao-fan; Wu, Yang-qing; Huang, Xin-fan; Oda, Shunri

2016-09-01

Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration. Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

Tuning the Electrical Memory Behavior from Nonvolatile to Volatile in Functional Copolyimides Bearing Varied Fluorene and Pyrene Moieties

NASA Astrophysics Data System (ADS)

Jia, Nanfang; Qi, Shengli; Tian, Guofeng; Wang, Xiaodong; Wu, Dezhen

2017-04-01

For producing polymer based electronics with good memory behavior, a series of functional copolyimides were designed and synthesized in this work by copolymerizing 3,3',4,4'-diphenylsulfonetetracarboxylic dianhydride (DSDA) with (9,9'-bis(4-aminophenyl)fluorene) (BAPF) and N, N-bis(4-aminophenyl) aminopyrene (DAPAP) diamines. The synthesized copolyimides DSDA/(DAPAP/BAPF) were denoted as coPI-DAPAP x ( x = 100, 50, 20, 10, 5, 1, 0), where x% represents the molar fraction of the DAPAP unit in the diamines. Characterization results indicate that the coPI-DAPAP x exhibits tunable electrical switching behaviors from write once read many times (WORM, nonvolatile, coPI-DAPAP100, coPI-DAPAP50, coPI-DAPAP20, coPI-DAPAP10) to the static random access memory (SRAM, volatile, coPI-DAPAP5, coPI-DAPAP1) with the variation of the DAPAP content. Optical and electrochemical characterization show gradually decreasing highest occupied molecular orbital levels and enlarged energy gap with the decrease of the DAPAP moiety, suggesting decreasing charge-transfer effect in the copolyimides, which can account for the observed WORM-SRAM memory conversion. Meanwhile, the charge transfer process was elucidated by quantum chemical calculation at B3LYP/6-31G(d) theory level. This work shows the effect of electron donor content on the memory behavior of polymer electronic materials.

Radiation Test Challenges for Scaled Commerical Memories

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Ladbury, Ray L.; Cohn, Lewis M.; Oldham, Timothy

2007-01-01

As sub-100nm CMOS technologies gather interest, the radiation effects performance of these technologies provide a significant challenge. In this talk, we shall discuss the radiation testing challenges as related to commercial memory devices. The focus will be on complex test and failure modes emerging in state-of-the-art Flash non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs), which are volatile. Due to their very high bit density, these device types are highly desirable for use in the natural space environment. In this presentation, we shall discuss these devices with emphasis on considerations for test and qualification methods required.

Non-volatile, solid state bistable electrical switch

NASA Technical Reports Server (NTRS)

Williams, Roger M. (Inventor)

1994-01-01

A bistable switching element is made of a material whose electrical resistance reversibly decreases in response to intercalation by positive ions. Flow of positive ions between the bistable switching element and a positive ion source is controlled by means of an electrical potential applied across a thermal switching element. The material of the thermal switching element generates heat in response to electrical current flow therethrough, which in turn causes the material to undergo a thermal phase transition from a high electrical resistance state to a low electrical resistance state as the temperature increases above a predetermined value. Application of the electrical potential in one direction renders the thermal switching element conductive to pass electron current out of the ion source. This causes positive ions to flow from the source into the bistable switching element and intercalate the same to produce a non-volatile, low resistance logic state. Application of the electrical potential in the opposite direction causes reverse current flow which de-intercalates the bistable logic switching element and produces a high resistance logic state.

Feasibility and limitations of anti-fuses based on bistable non-volatile switches for power electronic applications

NASA Astrophysics Data System (ADS)

Erlbacher, T.; Huerner, A.; Bauer, A. J.; Frey, L.

2012-09-01

Anti-fuse devices based on non-volatile memory cells and suitable for power electronic applications are demonstrated for the first time using silicon technology. These devices may be applied as stand alone devices or integrated using standard junction-isolation into application-specific and smart-power integrated circuits. The on-resistance of such devices can be permanently switched by nine orders of magnitude by triggering the anti-fuse with a positive voltage pulse. Extrapolation of measurement data and 2D TCAD process and device simulations indicate that 20 A anti-fuses with 10 mΩ can be reliably fabricated in 0.35 μm technology with a footprint of 2.5 mm2. Moreover, this concept offers distinguished added-values compared to existing mechanical relays, e.g. pre-test, temporary and permanent reset functions, gradual turn-on mode, non-volatility, and extendibility to high voltage capability.

A Compute Capable SSD Architecture for Next-Generation Non-volatile Memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

De, Arup

2014-01-01

Existing storage technologies (e.g., disks and ash) are failing to cope with the processor and main memory speed and are limiting the overall perfor- mance of many large scale I/O or data-intensive applications. Emerging fast byte-addressable non-volatile memory (NVM) technologies, such as phase-change memory (PCM), spin-transfer torque memory (STTM) and memristor are very promising and are approaching DRAM-like performance with lower power con- sumption and higher density as process technology scales. These new memories are narrowing down the performance gap between the storage and the main mem- ory and are putting forward challenging problems on existing SSD architecture, I/O interfacemore » (e.g, SATA, PCIe) and software. This dissertation addresses those challenges and presents a novel SSD architecture called XSSD. XSSD o oads com- putation in storage to exploit fast NVMs and reduce the redundant data tra c across the I/O bus. XSSD o ers a exible RPC-based programming framework that developers can use for application development on SSD without dealing with the complication of the underlying architecture and communication management. We have built a prototype of XSSD on the BEE3 FPGA prototyping system. We implement various data-intensive applications and achieve speedup and energy ef- ciency of 1.5-8.9 and 1.7-10.27 respectively. This dissertation also compares XSSD with previous work on intelligent storage and intelligent memory. The existing ecosystem and these new enabling technologies make this system more viable than earlier ones.« less

Self-assembled phase-change nanowire for nonvolatile electronic memory

NASA Astrophysics Data System (ADS)

Jung, Yeonwoong

One of the most important subjects in nanosciences is to identify and exploit the relationship between size and structural/physical properties of materials and to explore novel material properties at a small-length scale. Scale-down of materials is not only advantageous in realizing miniaturized devices but nanometer-sized materials often exhibit intriguing physical/chemical properties that greatly differ from their bulk counterparts. This dissertation studies self-assembled phase-change nanowires for future nonvolatile electronic memories, mainly focusing on their size-dependent memory switching properties. Owing to the one-dimensional, unique geometry coupled with the small and tunable sizes, bottom-designed nanowires offer great opportunities in terms for both fundamental science and practical engineering perspectives, which would be difficult to realize in conventional top-down based approaches. We synthesized chalcogenide phase-change nanowires of different compositions and sizes, and studied their electronic memory switching owing to the structural change between crystalline and amorphous phases. In particular, we investigated nanowire size-dependent memory switching parameters, including writing current, power consumption, and data retention times, as well as studying composition-dependent electronic properties. The observed size and composition-dependent switching and recrystallization kinetics are explained based on the heat transport model and heterogeneous nucleation theories, which help to design phase-change materials with better properties. Moreover, we configured unconventional heterostructured phase-change nanowire memories and studied their multiple memory states in single nanowire devices. Finally, by combining in-situ/ex-situ electron microscopy techniques and electrical measurements, we characterized the structural states involved in electrically-driven phase-change in order to understand the atomistic mechanism that governs the electronic memory switching through phase-change.

A-site- and/or B-site-modified PbZrTiO3 materials and (Pb, Sr, Ca, Ba, Mg) (Zr, Ti, Nb, Ta)O3 films having utility in ferroelectric random access memories and high performance thin film microactuators

NASA Technical Reports Server (NTRS)

Bilodeau, Steven (Inventor); Baum, Thomas H. (Inventor); Roeder, Jeffrey F. (Inventor); Chen, Ing-Shin (Inventor)

2001-01-01

A modified PbZrTiO.sub.3 perovskite crystal material thin film, wherein the PbZrTiO.sub.3 perovskite crystal material includes crystal lattice A-sites and B-sites at least one of which is modified by the presence of a substituent selected from the group consisting of (i) A-site substituents consisting of Sr, Ca, Ba and Mg, and (ii) B-site substituents selected from the group consisting of Nb and Ta. The perovskite crystal thin film material may be formed by liquid delivery MOCVD from metalorganic precursors of the metal components of the thin film, to form PZT and PSZT, and other piezoelectric and ferroelectric thin film materials. The thin films of the invention have utility in non-volatile ferroelectric memory devices (NV-FeRAMs), and in microelectromechanical systems (MEMS) as sensor and/or actuator elements, e.g., high speed digital system actuators requiring low input power levels.

A-SITE-AND/OR B-SITE-MODIFIED PBZRTIO3 MATERIALS AND (PB, SR, CA, BA, MG) (ZR, TI,NB, TA)O3 FILMS HAVING UTILITY IN FERROELECTRIC RANDOM ACCESS MEMORIES AND HIGH PERFORMANCE THIN FILM MICROACTUATORS

NASA Technical Reports Server (NTRS)

Bilodeau, Steven (Inventor); Baum, Thomas H. (Inventor); Roeder, Jeffrey F. (Inventor); Chen, Ing-Shin (Inventor)

2004-01-01

A modified PbZrTiO.sub.3 perovskite crystal material thin film, wherein the PbZrTiO.sub.3 perovskite crystal material includes crystal lattice A-sites and B-sites at least one of which is modified by the presence of a substituent selected from the group consisting of (i) A-site substituents consisting of Sr, Ca, Ba and Mg, and (ii) B-site substituents selected from the group consisting of Nb and Ta. The perovskite crystal thin film material may be formed by liquid delivery MOCVD from metalorganic precursors of the metal components of the thin film, to form PZT and PSZT, and other piezoelectric and ferroelectric thin film materials. The thin films of the invention have utility in non-volatile ferroelectric memory devices (NV-FeRAMs), and in microelectromechanical systems (MEMS) as sensor and/or actuator elements, e.g., high speed digital system actuators requiring low input power levels.

Temperature-driven topological quantum phase transitions in a phase-change material Ge2Sb2Te5.

PubMed

Eremeev, S V; Rusinov, I P; Echenique, P M; Chulkov, E V

2016-12-13

The Ge 2 Sb 2 Te 5 is a phase-change material widely used in optical memory devices and is a leading candidate for next generation non-volatile random access memory devices which are key elements of various electronics and portable systems. Despite the compound is under intense investigation its electronic structure is currently not fully understood. The present work sheds new light on the electronic structure of the Ge 2 Sb 2 Te 5 crystalline phases. We demonstrate by predicting from first-principles calculations that stable crystal structures of Ge 2 Sb 2 Te 5 possess different topological quantum phases: a topological insulator phase is realized in low-temperature structure and Weyl semimetal phase is a characteristic of the high-temperature structure. Since the structural phase transitions are caused by the temperature the switching between different topologically non-trivial phases can be driven by variation of the temperature. The obtained results reveal the rich physics of the Ge 2 Sb 2 Te 5 compound and open previously unexplored possibility for spintronics applications of this material, substantially expanding its application potential.

Investigation of resistive switching behaviours in WO3-based RRAM devices

NASA Astrophysics Data System (ADS)

Li, Ying-Tao; Long, Shi-Bing; Lü, Hang-Bing; Liu, Qi; Wang, Qin; Wang, Yan; Zhang, Sen; Lian, Wen-Tai; Liu, Su; Liu, Ming

2011-01-01

In this paper, a WO3-based resistive random access memory device composed of a thin film of WO3 sandwiched between a copper top and a platinum bottom electrodes is fabricated by electron beam evaporation at room temperature. The reproducible resistive switching, low power consumption, multilevel storage possibility, and good data retention characteristics demonstrate that the Cu/WO3/Pt memory device is very promising for future nonvolatile memory applications. The formation and rupture of localised conductive filaments is suggested to be responsible for the observed resistive switching behaviours.

40 CFR 1042.115 - Other requirements.

Code of Federal Regulations, 2010 CFR

2010-07-01

... 40 Protection of Environment 32 2010-07-01 2010-07-01 false Other requirements. 1042.115 Section 1042.115 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) AIR POLLUTION CONTROLS...). (3) The onboard computer log must record in nonvolatile computer memory all incidents of engine...

Multilevel Resistance Programming in Conductive Bridge Resistive Memory

NASA Astrophysics Data System (ADS)

Mahalanabis, Debayan

This work focuses on the existence of multiple resistance states in a type of emerging non-volatile resistive memory device known commonly as Programmable Metallization Cell (PMC) or Conductive Bridge Random Access Memory (CBRAM), which can be important for applications such as multi-bit memory as well as non-volatile logic and neuromorphic computing. First, experimental data from small signal, quasi-static and pulsed mode electrical characterization of such devices are presented which clearly demonstrate the inherent multi-level resistance programmability property in CBRAM devices. A physics based analytical CBRAM compact model is then presented which simulates the ion-transport dynamics and filamentary growth mechanism that causes resistance change in such devices. Simulation results from the model are fitted to experimental dynamic resistance switching characteristics. The model designed using Verilog-a language is computation-efficient and can be integrated with industry standard circuit simulation tools for design and analysis of hybrid circuits involving both CMOS and CBRAM devices. Three main circuit applications for CBRAM devices are explored in this work. Firstly, the susceptibility of CBRAM memory arrays to single event induced upsets is analyzed via compact model simulation and experimental heavy ion testing data that show possibility of both high resistance to low resistance and low resistance to high resistance transitions due to ion strikes. Next, a non-volatile sense amplifier based flip-flop architecture is proposed which can help make leakage power consumption negligible by allowing complete shutdown of power supply while retaining its output data in CBRAM devices. Reliability and energy consumption of the flip-flop circuit for different CBRAM low resistance levels and supply voltage values are analyzed and compared to CMOS designs. Possible extension of this architecture for threshold logic function computation using the CBRAM devices as re-configurable resistive weights is also discussed. Lastly, Spike timing dependent plasticity (STDP) based gradual resistance change behavior in CBRAM device fabricated in back-end-of-line on a CMOS die containing integrate and fire CMOS neuron circuits is demonstrated for the first time which indicates the feasibility of using CBRAM devices as electronic synapses in spiking neural network hardware implementations for non-Boolean neuromorphic computing.

Development of bubble memory recorder onboard Japan Earth Resources Satellite-1

NASA Astrophysics Data System (ADS)

Araki, Tsunehiko; Ishida, Chu; Ochiai, Kiyoshi; Nozue, Tatsuhiro; Tachibana, Kyozo; Yoshida, Kazutoshi

The Bubble Memory Recorder (BMR) developed for use on the Earth Resources Satellite is described in terms of its design, capabilities, and functions. The specifications of the BMR are given listing memory capacity, functions, and interface types for data, command, and telemetry functions. The BMR has an emergency signal interface to provide contingency recording, and a satellite-separation signal interface can be turned on automatically by signal input. Data are stored in a novolatile memory device so that the memory is retained during power outages. The BMR is characterized by a capability for random access, nonvolatility, and a solid-state design that is useful for space operations since it does not disturb spacecraft attitude.

Exploration of perpendicular magnetic anisotropy material system for application in spin transfer torque - Random access memory

NASA Astrophysics Data System (ADS)

Natarajarathinam, Anusha

Perpendicular magnetic anisotropy (PMA) materials have unique advantages when used in magnetic tunnel junctions (MTJ) which are the most critical part of spin-torque transfer random access memory devices (STT-RAMs) that are being researched intensively as future non-volatile memory technology. They have high magnetoresistance which improves their sensitivity. The STT-RAM has several advantages over competing technologies, for instance, low power consumption, non-volatility, ultra-fast read and write speed and high endurance. In personal computers, it can replace SRAM for high-speed applications, Flash for non-volatility, and PSRAM and DRAM for high-speed program execution. The main aim of this research is to identify and optimize the best perpendicular magnetic anisotropy (PMA) material system for application to STT-RAM technology. Preliminary search for perpendicular magnetic anisotropy (PMA) materials for pinned layer for MTJs started with the exploration and optimization of crystalline alloys such as Co50Pd50 alloy, Mn50Al50 and amorphous alloys such as Tb21Fe72Co7 and are first presented in this work. Further optimization includes the study of Co/[Pd/Pt]x multilayers (ML), and the development of perpendicular synthetic antiferromagnets (SAF) utilizing these multilayers. Focused work on capping and seed layers to evaluate interfacial perpendicular anisotropy in free layers for pMTJs is then discussed. Optimization of the full perpendicular magnetic tunnel junction (pMTJ) includes the CoFeB/MgO/CoFeB trilayer coupled to a pinned/pinning layer with perpendicular Co/[Pd/Pt]x SAF and a thin Ta seeded CoFeB free layer. Magnetometry, simulations, annealing studies, transport measurements and TEM analysis on these samples will then be presented.

Hafnia-based resistive switching devices for non-volatile memory applications and effects of gamma irradiation on device performance

NASA Astrophysics Data System (ADS)

Arun, N.; Kumar, K. Vinod; Pathak, A. P.; Avasthi, D. K.; Nageswara Rao, S. V. S.

2018-04-01

Non-volatile memory (NVM) devices were fabricated as a Metal- Insulator-Metal (MIM) structures by sandwiching Hafnium dioxide (HfO2) thin film in between two metal electrodes. The top and bottom metal electrodes were deposited by using the thermal evaporation, and the oxide layer was deposited by using the RF magnetron sputtering technique. The Resistive Random Access Memory (RRAM) device structures such as Ag/HfO2/Au/Si were fabricated and I-V characteristics for the pristine and gamma-irradiated devices with a dose 24 kGy were measured. Further we have studied the thermal annealing effects, in the range of 100°-400°C in a tubular furnace for the HfO2/Au/Si samples. The X-ray diffraction (XRD), Rutherford Backscattering Spectrometry (RBS), field emission-scanning electron microscopy (FESEM) analysis measurements were performed to determine the thickness, crystallinity and stoichiometry of these films. The electrical characteristics such as resistive switching, endurance, retention time and switching speed were measured by a semiconductor device analyser. The effects of gamma irradiation on the switching properties of these RRAM devices have been studied.

Facile fabrication of highly ordered poly(vinylidene fluoride-trifluoroethylene) nanodot arrays for organic ferroelectric memory

NASA Astrophysics Data System (ADS)

Fang, Huajing; Yan, Qingfeng; Geng, Chong; Chan, Ngai Yui; Au, Kit; Yao, Jianjun; Ng, Sheung Mei; Leung, Chi Wah; Li, Qiang; Guo, Dong; Wa Chan, Helen Lai; Dai, Jiyan

2016-01-01

Nano-patterned ferroelectric materials have attracted significant attention as the presence of two or more thermodynamically equivalent switchable polarization states can be employed in many applications such as non-volatile memory. In this work, a simple and effective approach for fabrication of highly ordered poly(vinylidene fluoride-trifluoroethylene) P(VDF-TrFE) nanodot arrays is demonstrated. By using a soft polydimethylsiloxane mold, we successfully transferred the 2D array pattern from the initial monolayer of colloidal polystyrene nanospheres to the imprinted P(VDF-TrFE) films via nanoimprinting. The existence of a preferred orientation of the copolymer chain after nanoimprinting was confirmed by Fourier transform infrared spectra. Local polarization switching behavior was measured by piezoresponse force microscopy, and each nanodot showed well-formed hysteresis curve and butterfly loop with a coercive field of ˜62.5 MV/m. To illustrate the potential application of these ordered P(VDF-TrFE) nanodot arrays, the writing and reading process as non-volatile memory was demonstrated at a relatively low voltage. As such, our results offer a facile and promising route to produce arrays of ferroelectric polymer nanodots with improved piezoelectric functionality.

Nonvolatile memories using deep traps formed in HfO2 by Nb ion implantation

NASA Astrophysics Data System (ADS)

Choul Kim, Min; Oh Kim, Chang; Taek Oh, Houng; Choi, Suk-Ho; Belay, K.; Elliman, R. G.; Russo, S. P.

2011-03-01

We report nonvolatile memories (NVMs) based on deep-energy trap levels formed in HfO2 by metal ion implantation. A comparison of Nb- and Ta-implanted samples shows that suitable charge-trapping centers are formed in Nb-implanted samples, but not in Ta-implanted samples. This is consistent with density-functional theory calculations which predict that only Nb will form deep-energy levels in the bandgap of HfO2. Photocurrent spectroscopy exhibits characteristics consistent with one of the trap levels predicted in these calculations. Nb-implanted samples showing memory windows in capacitance-voltage (V) curves always exhibit current (I) peaks in I-V curves, indicating that NVM effects result from deep traps in HfO2. In contrast, Ta-implanted samples show dielectric breakdowns during the I-V sweeps between 5 and 11 V, consistent with the fact that no trap levels are present. For a sample implanted with a fluence of 1013 Nb cm-2, the charge losses after 104 s are ˜9.8 and ˜25.5% at room temperature (RT) and 85°C, respectively, and the expected charge loss after 10 years is ˜34% at RT, very promising for commercial NVMs.

Sub-10 nm Ta Channel Responsible for Superior Performance of a HfO 2 Memristor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jiang, Hao; Han, Lili; Lin, Peng

Memristive devices are promising candidates for the next generation non-volatile memory and neuromorphic computing. It has been widely accepted that the motion of oxygen anions leads to the resistance changes for valence-change-memory (VCM) type of materials. Only very recently it was speculated that metal cations could also play an important role, but no direct physical characterizations have been reported yet. We report a Ta/HfO 2/Pt memristor with fast switching speed, record high endurance (120 billion cycles) and reliable retention. We also programmed the device to 24 discrete resistance levels, and also demonstrated over a million (220) epochs of potentiation andmore » depression, suggesting that our devices can be used for both multi-level non-volatile memory and neuromorphic computing applications. More importantly, we directly observed a sub-10 nm Ta-rich and O-deficient conduction channel within the HfO 2 layer that is responsible for the switching. Our work deepens our understanding of the resistance switching mechanism behind oxide-based memristive devices and paves the way for further device performance optimization for a broad spectrum of applications.« less

Giant tunnelling electroresistance in metal/ferroelectric/semiconductor tunnel junctions by engineering the Schottky barrier

PubMed Central

Xi, Zhongnan; Ruan, Jieji; Li, Chen; Zheng, Chunyan; Wen, Zheng; Dai, Jiyan; Li, Aidong; Wu, Di

2017-01-01

Recently, ferroelectric tunnel junctions have attracted much attention due to their potential applications in non-destructive readout non-volatile memories. Using a semiconductor electrode has been proven effective to enhance the tunnelling electroresistance in ferroelectric tunnel junctions. Here we report a systematic investigation on electroresistance of Pt/BaTiO3/Nb:SrTiO3 metal/ferroelectric/semiconductor tunnel junctions by engineering the Schottky barrier on Nb:SrTiO3 surface via varying BaTiO3 thickness and Nb doping concentration. The optimum ON/OFF ratio as great as 6.0 × 106, comparable to that of commercial Flash memories, is achieved in a device with 0.1 wt% Nb concentration and a 4-unit-cell-thick BaTiO3 barrier. With this thinnest BaTiO3 barrier, which shows a negligible resistance to the tunnelling current but is still ferroelectric, the device is reduced to a polarization-modulated metal/semiconductor Schottky junction that exhibits a more efficient control on the tunnelling resistance to produce the giant electroresistance observed. These results may facilitate the design of high performance non-volatile resistive memories. PMID:28513590

Giant tunnelling electroresistance in metal/ferroelectric/semiconductor tunnel junctions by engineering the Schottky barrier

NASA Astrophysics Data System (ADS)

Xi, Zhongnan; Ruan, Jieji; Li, Chen; Zheng, Chunyan; Wen, Zheng; Dai, Jiyan; Li, Aidong; Wu, Di

2017-05-01

Recently, ferroelectric tunnel junctions have attracted much attention due to their potential applications in non-destructive readout non-volatile memories. Using a semiconductor electrode has been proven effective to enhance the tunnelling electroresistance in ferroelectric tunnel junctions. Here we report a systematic investigation on electroresistance of Pt/BaTiO3/Nb:SrTiO3 metal/ferroelectric/semiconductor tunnel junctions by engineering the Schottky barrier on Nb:SrTiO3 surface via varying BaTiO3 thickness and Nb doping concentration. The optimum ON/OFF ratio as great as 6.0 × 106, comparable to that of commercial Flash memories, is achieved in a device with 0.1 wt% Nb concentration and a 4-unit-cell-thick BaTiO3 barrier. With this thinnest BaTiO3 barrier, which shows a negligible resistance to the tunnelling current but is still ferroelectric, the device is reduced to a polarization-modulated metal/semiconductor Schottky junction that exhibits a more efficient control on the tunnelling resistance to produce the giant electroresistance observed. These results may facilitate the design of high performance non-volatile resistive memories.

Redefining the Speed Limit of Phase Change Memory Revealed by Time-resolved Steep Threshold-Switching Dynamics of AgInSbTe Devices

NASA Astrophysics Data System (ADS)

Shukla, Krishna Dayal; Saxena, Nishant; Durai, Suresh; Manivannan, Anbarasu

2016-11-01

Although phase-change memory (PCM) offers promising features for a ‘universal memory’ owing to high-speed and non-volatility, achieving fast electrical switching remains a key challenge. In this work, a correlation between the rate of applied voltage and the dynamics of threshold-switching is investigated at picosecond-timescale. A distinct characteristic feature of enabling a rapid threshold-switching at a critical voltage known as the threshold voltage as validated by an instantaneous response of steep current rise from an amorphous off to on state is achieved within 250 picoseconds and this is followed by a slower current rise leading to crystallization. Also, we demonstrate that the extraordinary nature of threshold-switching dynamics in AgInSbTe cells is independent to the rate of applied voltage unlike other chalcogenide-based phase change materials exhibiting the voltage dependent transient switching characteristics. Furthermore, numerical solutions of time-dependent conduction process validate the experimental results, which reveal the electronic nature of threshold-switching. These findings of steep threshold-switching of ‘sub-50 ps delay time’, opens up a new way for achieving high-speed non-volatile memory for mainstream computing.

Sub-10 nm Ta Channel Responsible for Superior Performance of a HfO 2 Memristor

DOE PAGES

Jiang, Hao; Han, Lili; Lin, Peng; ...

2016-06-23

Memristive devices are promising candidates for the next generation non-volatile memory and neuromorphic computing. It has been widely accepted that the motion of oxygen anions leads to the resistance changes for valence-change-memory (VCM) type of materials. Only very recently it was speculated that metal cations could also play an important role, but no direct physical characterizations have been reported yet. We report a Ta/HfO 2/Pt memristor with fast switching speed, record high endurance (120 billion cycles) and reliable retention. We also programmed the device to 24 discrete resistance levels, and also demonstrated over a million (220) epochs of potentiation andmore » depression, suggesting that our devices can be used for both multi-level non-volatile memory and neuromorphic computing applications. More importantly, we directly observed a sub-10 nm Ta-rich and O-deficient conduction channel within the HfO 2 layer that is responsible for the switching. Our work deepens our understanding of the resistance switching mechanism behind oxide-based memristive devices and paves the way for further device performance optimization for a broad spectrum of applications.« less

The effect of the bottom electrode on ferroelectric tunnel junctions based on CMOS-compatible HfO2.

PubMed

Goh, Youngin; Jeon, Sanghun

2018-08-17

Ferroelectric tunnel junctions (FTJs) have attracted research interest as promising candidates for non-destructive readout non-volatile memories. Unlike conventional perovskite FTJs, hafnia FTJs offer many advantages in terms of scalability and CMOS compatibility. However, so far, hafnia FTJs have shown poor endurance and relatively low resistance ratios and these have remained issues for real device applications. In our study, we fabricated HfZrO(HZO)-based FTJs with various electrodes (TiN, Si, SiGe, Ge) and improved the memory performance of HZO-based FTJs by using the asymmetry of the charge screening lengths of the electrodes. For the HZO-based FTJ with a Ge substrate, the effective barrier afforded by this FTJ can be electrically modulated because of the space charge-limited region formed at the ferroelectric/semiconductor interface. The optimized HZO-based FTJ with a Ge bottom electrode presents excellent ferroelectricity with a high remnant polarization of 18 μC cm -2 , high tunneling electroresistance value of 30, good retention at 85 °C and high endurance of 10 7 . The results demonstrate the great potential of HfO 2 -based FTJs in non-destructive readout non-volatile memories.

Bipolar resistive switching in Cu/AlN/Pt nonvolatile memory device

NASA Astrophysics Data System (ADS)

Chen, C.; Yang, Y. C.; Zeng, F.; Pan, F.

2010-08-01

Highly stable and reproducible bipolar resistive switching effects are reported on Cu/AlN/Pt devices. Memory characteristics including large memory window of 103, long retention time of >106 s and good endurance of >103 were demonstrated. It is concluded that the reset current decreases as compliance current decreases, which provides an approach to suppress power consumption. The dominant conduction mechanisms of low resistance state and high resistance state were verified by Ohmic behavior and trap-controlled space charge limited current, respectively. The memory effect is explained by the model concerning redox reaction mediated formation and rupture of the conducting filament in AlN films.

Solution-processed flexible NiO resistive random access memory device

NASA Astrophysics Data System (ADS)

Kim, Soo-Jung; Lee, Heon; Hong, Sung-Hoon

2018-04-01

Non-volatile memories (NVMs) using nanocrystals (NCs) as active materials can be applied to soft electronic devices requiring a low-temperature process because NCs do not require a heat treatment process for crystallization. In addition, memory devices can be implemented simply by using a patterning technique using a solution process. In this study, a flexible NiO ReRAM device was fabricated using a simple NC patterning method that controls the capillary force and dewetting of a NiO NC solution at low temperature. The switching behavior of a NiO NC based memory was clearly observed by conductive atomic force microscopy (c-AFM).

Unidirectional threshold switching in Ag/Si-based electrochemical metallization cells for high-density bipolar RRAM applications

NASA Astrophysics Data System (ADS)

Wang, Chao; Song, Bing; Li, Qingjiang; Zeng, Zhongming

2018-03-01

We herein present a novel unidirectional threshold selector for cross-point bipolar RRAM array. The proposed Ag/amorphous Si based threshold selector showed excellent threshold characteristics in positive field, such as high selectivity ( 105), steep slope (< 5 mV/decade) and low off-state current (< 300 pA). Meanwhile, the selector exhibited rectifying characteristics in the high resistance state as well and the rectification ratio was as high as 103 at ± 1.5 V. Nevertheless, due to the high reverse current about 9 mA at - 3 V, this unidirectional threshold selector can be used as a selection element for bipolar-type RRAM. By integrating a bipolar RRAM device with the selector, experiments showed that the undesired sneak was significantly suppressed, indicating its potentiality for high-density integrated nonvolatile memory applications.

Vortex-Core Reversal Dynamics: Towards Vortex Random Access Memory

NASA Astrophysics Data System (ADS)

Kim, Sang-Koog

2011-03-01

An energy-efficient, ultrahigh-density, ultrafast, and nonvolatile solid-state universal memory is a long-held dream in the field of information-storage technology. The magnetic random access memory (MRAM) along with a spin-transfer-torque switching mechanism is a strong candidate-means of realizing that dream, given its nonvolatility, infinite endurance, and fast random access. Magnetic vortices in patterned soft magnetic dots promise ground-breaking applications in information-storage devices, owing to the very stable twofold ground states of either their upward or downward core magnetization orientation and plausible core switching by in-plane alternating magnetic fields or spin-polarized currents. However, two technologically most important but very challenging issues --- low-power recording and reliable selection of each memory cell with already existing cross-point architectures --- have not yet been resolved for the basic operations in information storage, that is, writing (recording) and readout. Here, we experimentally demonstrate a magnetic vortex random access memory (VRAM) in the basic cross-point architecture. This unique VRAM offers reliable cell selection and low-power-consumption control of switching of out-of-plane core magnetizations using specially designed rotating magnetic fields generated by two orthogonal and unipolar Gaussian-pulse currents along with optimized pulse width and time delay. Our achievement of a new device based on a new material, that is, a medium composed of patterned vortex-state disks, together with the new physics on ultrafast vortex-core switching dynamics, can stimulate further fruitful research on MRAMs that are based on vortex-state dot arrays.

47 CFR 15.611 - General technical requirements.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 47 Telecommunication 1 2010-10-01 2010-10-01 false General technical requirements. 15.611 Section 15.611 Telecommunication FEDERAL COMMUNICATIONS COMMISSION GENERAL RADIO FREQUENCY DEVICES Access... shut-off procedure, by the use of a non-volatile memory, or some other method, to immediately restore...

Four-state non-volatile memory in a multiferroic spin filter tunnel junction

NASA Astrophysics Data System (ADS)

Ruan, Jieji; Li, Chen; Yuan, Zhoushen; Wang, Peng; Li, Aidong; Wu, Di

2016-12-01

We report a spin filter type multiferroic tunnel junction with a ferromagnetic/ferroelectric bilayer barrier. Memory functions of a spin filter magnetic tunnel junction and a ferroelectric tunnel junction are combined in this single device, producing four non-volatile resistive states that can be read out in a non-destructive manner. This concept is demonstrated in a LaNiO3/Pr0.8Ca0.2MnO3/BaTiO3/La0.7Sr0.3MnO3 all-oxide tunnel junction. The ferromagnetic insulator Pr0.8Ca0.2MnO3 serves as the spin filter and the ferromagnetic metal La0.7Sr0.3MnO3 is the spin analyzer. The ferroelectric polarization reversal in the BaTiO3 barrier switches the tunneling barrier height to produce a tunneling electroresistance. The ferroelectric switching also modulates the spin polarization and the spin filtering efficiency in Pr0.8Ca0.2MnO3.

Opportunity of spinel ferrite materials in nonvolatile memory device applications based on their resistive switching performances.

PubMed

Hu, Wei; Qin, Ni; Wu, Guangheng; Lin, Yanting; Li, Shuwei; Bao, Dinghua

2012-09-12

The opportunity of spinel ferrites in nonvolatile memory device applications has been demonstrated by the resistive switching performance characteristics of a Pt/NiFe(2)O(4)/Pt structure, such as low operating voltage, high device yield, long retention time (up to 10(5) s), and good endurance (up to 2.2 × 10(4) cycles). The dominant conduction mechanisms are Ohmic conduction in the low-resistance state and in the lower-voltage region of the high-resistance state and Schottky emission in the higher-voltage region of the high-resistance state. On the basis of measurements of the temperature dependence of the resistances and magnetic properties in different resistance states, we explain the physical mechanism of resistive switching of Pt/NiFe(2)O(4)/Pt devices using the model of formation and rupture of conducting filaments by considering the thermal effect of oxygen vacancies and changes in the valences of cations due to the redox effect.

Radiation Testing, Characterization and Qualification Challenges for Modern Microelectronics and Photonics Devices and Technologies

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.; Cohn, Lewis M.

2008-01-01

At GOMAC 2007, we discussed a selection of the challenges for radiation testing of modern semiconductor devices focusing on state-of-the-art memory technologies. This included FLASH non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs). In this presentation, we extend this discussion in device packaging and complexity as well as single event upset (SEU) mechanisms using several technology areas as examples including: system-on-a-chip (SOC) devices and photonic or fiber optic systems. The underlying goal is intended to provoke thought for understanding the limitations and interpretation of radiation testing results.

Two-dimensional non-volatile programmable p-n junctions

NASA Astrophysics Data System (ADS)

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M.; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe2/hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 104 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Non-Volatile Ferroelectric Switching of Ferromagnetic Resonance in NiFe/PLZT Multiferroic Thin Film Heterostructures.

PubMed

Hu, Zhongqiang; Wang, Xinjun; Nan, Tianxiang; Zhou, Ziyao; Ma, Beihai; Chen, Xiaoqin; Jones, John G; Howe, Brandon M; Brown, Gail J; Gao, Yuan; Lin, Hwaider; Wang, Zhiguang; Guo, Rongdi; Chen, Shuiyuan; Shi, Xiaoling; Shi, Wei; Sun, Hongzhi; Budil, David; Liu, Ming; Sun, Nian X

2016-09-01

Magnetoelectric effect, arising from the interfacial coupling between magnetic and electrical order parameters, has recently emerged as a robust means to electrically manipulate the magnetic properties in multiferroic heterostructures. Challenge remains as finding an energy efficient way to modify the distinct magnetic states in a reliable, reversible, and non-volatile manner. Here we report ferroelectric switching of ferromagnetic resonance in multiferroic bilayers consisting of ultrathin ferromagnetic NiFe and ferroelectric Pb0.92La0.08Zr0.52Ti0.48O3 (PLZT) films, where the magnetic anisotropy of NiFe can be electrically modified by low voltages. Ferromagnetic resonance measurements confirm that the interfacial charge-mediated magnetoelectric effect is dominant in NiFe/PLZT heterostructures. Non-volatile modification of ferromagnetic resonance field is demonstrated by applying voltage pulses. The ferroelectric switching of magnetic anisotropy exhibits extensive applications in energy-efficient electronic devices such as magnetoelectric random access memories, magnetic field sensors, and tunable radio frequency (RF)/microwave devices.

Non-Volatile Ferroelectric Switching of Ferromagnetic Resonance in NiFe/PLZT Multiferroic Thin Film Heterostructures

PubMed Central

Hu, Zhongqiang; Wang, Xinjun; Nan, Tianxiang; Zhou, Ziyao; Ma, Beihai; Chen, Xiaoqin; Jones, John G.; Howe, Brandon M.; Brown, Gail J.; Gao, Yuan; Lin, Hwaider; Wang, Zhiguang; Guo, Rongdi; Chen, Shuiyuan; Shi, Xiaoling; Shi, Wei; Sun, Hongzhi; Budil, David; Liu, Ming; Sun, Nian X.

2016-01-01

Magnetoelectric effect, arising from the interfacial coupling between magnetic and electrical order parameters, has recently emerged as a robust means to electrically manipulate the magnetic properties in multiferroic heterostructures. Challenge remains as finding an energy efficient way to modify the distinct magnetic states in a reliable, reversible, and non-volatile manner. Here we report ferroelectric switching of ferromagnetic resonance in multiferroic bilayers consisting of ultrathin ferromagnetic NiFe and ferroelectric Pb0.92La0.08Zr0.52Ti0.48O3 (PLZT) films, where the magnetic anisotropy of NiFe can be electrically modified by low voltages. Ferromagnetic resonance measurements confirm that the interfacial charge-mediated magnetoelectric effect is dominant in NiFe/PLZT heterostructures. Non-volatile modification of ferromagnetic resonance field is demonstrated by applying voltage pulses. The ferroelectric switching of magnetic anisotropy exhibits extensive applications in energy-efficient electronic devices such as magnetoelectric random access memories, magnetic field sensors, and tunable radio frequency (RF)/microwave devices. PMID:27581071

Non-Volatile Ferroelectric Switching of Ferromagnetic Resonance in NiFe/PLZT Multiferroic Thin Film Heterostructures

NASA Astrophysics Data System (ADS)

Hu, Zhongqiang; Wang, Xinjun; Nan, Tianxiang; Zhou, Ziyao; Ma, Beihai; Chen, Xiaoqin; Jones, John G.; Howe, Brandon M.; Brown, Gail J.; Gao, Yuan; Lin, Hwaider; Wang, Zhiguang; Guo, Rongdi; Chen, Shuiyuan; Shi, Xiaoling; Shi, Wei; Sun, Hongzhi; Budil, David; Liu, Ming; Sun, Nian X.

2016-09-01

Magnetoelectric effect, arising from the interfacial coupling between magnetic and electrical order parameters, has recently emerged as a robust means to electrically manipulate the magnetic properties in multiferroic heterostructures. Challenge remains as finding an energy efficient way to modify the distinct magnetic states in a reliable, reversible, and non-volatile manner. Here we report ferroelectric switching of ferromagnetic resonance in multiferroic bilayers consisting of ultrathin ferromagnetic NiFe and ferroelectric Pb0.92La0.08Zr0.52Ti0.48O3 (PLZT) films, where the magnetic anisotropy of NiFe can be electrically modified by low voltages. Ferromagnetic resonance measurements confirm that the interfacial charge-mediated magnetoelectric effect is dominant in NiFe/PLZT heterostructures. Non-volatile modification of ferromagnetic resonance field is demonstrated by applying voltage pulses. The ferroelectric switching of magnetic anisotropy exhibits extensive applications in energy-efficient electronic devices such as magnetoelectric random access memories, magnetic field sensors, and tunable radio frequency (RF)/microwave devices.

Two-dimensional non-volatile programmable p-n junctions.

PubMed

Li, Dong; Chen, Mingyuan; Sun, Zhengzong; Yu, Peng; Liu, Zheng; Ajayan, Pulickel M; Zhang, Zengxing

2017-09-01

Semiconductor p-n junctions are the elementary building blocks of most electronic and optoelectronic devices. The need for their miniaturization has fuelled the rapid growth of interest in two-dimensional (2D) materials. However, the performance of a p-n junction considerably degrades as its thickness approaches a few nanometres and traditional technologies, such as doping and implantation, become invalid at the nanoscale. Here we report stable non-volatile programmable p-n junctions fabricated from the vertically stacked all-2D semiconductor/insulator/metal layers (WSe 2 /hexagonal boron nitride/graphene) in a semifloating gate field-effect transistor configuration. The junction exhibits a good rectifying behaviour with a rectification ratio of 10 4 and photovoltaic properties with a power conversion efficiency up to 4.1% under a 6.8 nW light. Based on the non-volatile programmable properties controlled by gate voltages, the 2D p-n junctions have been exploited for various electronic and optoelectronic applications, such as memories, photovoltaics, logic rectifiers and logic optoelectronic circuits.

Non-volatile Clocked Spin Wave Interconnect for Beyond-CMOS Nanomagnet Pipelines

PubMed Central

Dutta, Sourav; Chang, Sou-Chi; Kani, Nickvash; Nikonov, Dmitri E.; Manipatruni, Sasikanth; Young, Ian A.; Naeemi, Azad

2015-01-01

The possibility of using spin waves for information transmission and processing has been an area of active research due to the unique ability to manipulate the amplitude and phase of the spin waves for building complex logic circuits with less physical resources and low power consumption. Previous proposals on spin wave logic circuits have suggested the idea of utilizing the magneto-electric effect for spin wave amplification and amplitude- or phase-dependent switching of magneto-electric cells. Here, we propose a comprehensive scheme for building a clocked non-volatile spin wave device by introducing a charge-to-spin converter that translates information from electrical domain to spin domain, magneto-electric spin wave repeaters that operate in three different regimes - spin wave transmitter, non-volatile memory and spin wave detector, and a novel clocking scheme that ensures sequential transmission of information and non-reciprocity. The proposed device satisfies the five essential requirements for logic application: nonlinearity, amplification, concatenability, feedback prevention, and complete set of Boolean operations. PMID:25955353

A novel architecture of non-volatile magnetic arithmetic logic unit using magnetic tunnel junctions

NASA Astrophysics Data System (ADS)

Guo, Wei; Prenat, Guillaume; Dieny, Bernard

2014-04-01

Complementary metal-oxide-semiconductor (CMOS) technology is facing increasingly difficult obstacles such as power consumption and interconnection delay. Novel hybrid technologies and architectures are being investigated with the aim to circumvent some of these limits. In particular, hybrid CMOS/magnetic technology based on magnetic tunnel junctions (MTJs) is considered as a very promising approach thanks to the full compatibility of MTJs with CMOS technology. By tightly merging the conventional electronics with magnetism, both logic and memory functions can be implemented in the same device. As a result, non-volatility is directly brought into logic circuits, yielding significant improvement of device performances and new functionalities as well. We have conceived an innovative methodology to construct non-volatile magnetic arithmetic logic units (MALUs) combining spin-transfer torque MTJs with MOS transistors. The present 4-bit MALU utilizes 4 MTJ pairs to store its operation code (opcode). Its operations and performances have been confirmed and evaluated through electrical simulations.

Improved memory characteristics by NH3-nitrided GdO as charge storage layer for nonvolatile memory applications

NASA Astrophysics Data System (ADS)

Liu, L.; Xu, J. P.; Ji, F.; Chen, J. X.; Lai, P. T.

2012-07-01

Charge-trapping memory capacitor with nitrided gadolinium oxide (GdO) as charge storage layer (CSL) is fabricated, and the influence of post-deposition annealing in NH3 on its memory characteristics is investigated. Transmission electron microscopy, x-ray photoelectron spectroscopy, and x-ray diffraction are used to analyze the cross-section and interface quality, composition, and crystallinity of the stack gate dielectric, respectively. It is found that nitrogen incorporation can improve the memory window and achieve a good trade-off among the memory properties due to NH3-annealing-induced reasonable distribution profile of a large quantity of deep-level bulk traps created in the nitrided GdO film and reduction of shallow traps near the CSL/SiO2 interface.

Low-voltage all-inorganic perovskite quantum dot transistor memory

NASA Astrophysics Data System (ADS)

Chen, Zhiliang; Zhang, Yating; Zhang, Heng; Yu, Yu; Song, Xiaoxian; Zhang, Haiting; Cao, Mingxuan; Che, Yongli; Jin, Lufan; Li, Yifan; Li, Qingyan; Dai, Haitao; Yang, Junbo; Yao, Jianquan

2018-05-01

An all-inorganic cesium lead halide quantum dot (QD) based Au nanoparticle (NP) floating-gate memory with a solution processed layer-by-layer method is demonstrated. Easy synthesis at room temperature and excellent stability make all-inorganic CsPbBr3 perovskite QDs suitable as a semiconductor layer in low voltage nonvolatile transistor memory. The bipolarity of QDs has both electrons and holes stored in the Au NP floating gate, resulting in bidirectional shifts of initial threshold voltage according to the applied programing and erasing pulses. Under low operation voltage (±5 V), the memory achieved a great memory window (˜2.4 V), long retention time (>105 s), and stable endurance properties after 200 cycles. So the proposed memory device based on CsPbBr3 perovskite QDs has a great potential in the flash memory market.

Physical unclonable functions: A primer

DOE PAGES

Bauer, Todd; Hamlet, Jason

2014-11-01

Physical unclonable functions (PUFs) make use of the measurable intrinsic randomness of physical systems to establish signatures for those systems. Thus, PUFs provide a means to generate unique keys that don't need to be stored in nonvolatile memory, and they offer exciting opportunities for new authentication and supply chain security technologies.

Solution processed molecular floating gate for flexible flash memories

NASA Astrophysics Data System (ADS)

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-10-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices.

Solution processed molecular floating gate for flexible flash memories

PubMed Central

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-01-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices. PMID:24172758

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications

NASA Astrophysics Data System (ADS)

Liu, Chunsen; Yan, Xiao; Song, Xiongfei; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-05-01

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

Impact of process parameters on the structural and electrical properties of metal/PZT/Al2O3/silicon gate stack for non-volatile memory applications

NASA Astrophysics Data System (ADS)

Singh, Prashant; Jha, Rajesh Kumar; Singh, Rajat Kumar; Singh, B. R.

2018-02-01

In this paper, we present the structural and electrical properties of the Al2O3 buffer layer on non-volatile memory behavior using Metal/PZT/Al2O3/Silicon structures. Metal/PZT/Silicon and Metal/Al2O3/Silicon structures were also fabricated and characterized to obtain capacitance and leakage current parameters. Lead zirconate titanate (PZT::35:65) and Al2O3 films were deposited by sputtering on the silicon substrate. Memory window, PUND, endurance, breakdown voltage, effective charges, flat-band voltage and leakage current density parameters were measured and the effects of process parameters on the structural and electrical characteristics were investigated. X-ray data show dominant (110) tetragonal phase of the PZT film, which crystallizes at 500 °C. The sputtered Al2O3 film annealed at different temperatures show dominant (312) orientation and amorphous nature at 425 °C. Multiple angle laser ellipsometric analysis reveals the temperature dependence of PZT film refractive index and extinction coefficient. Electrical characterization shows the maximum memory window of 3.9 V and breakdown voltage of 25 V for the Metal/Ferroelectric/Silicon (MFeS) structures annealed at 500 °C. With 10 nm Al2O3 layer in the Metal/Ferroelectric/Insulator/Silicon (MFeIS) structure, the memory window and breakdown voltage was improved to 7.21 and 35 V, respectively. Such structures show high endurance with no significant reduction polarization charge for upto 2.2 × 109 iteration cycles.

A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

NASA Astrophysics Data System (ADS)

Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2017-04-01

A high-density nonvolatile associative memory (NV-AM) based on spin transfer torque magnetoresistive random access memory (STT-MRAM), which achieves highly concurrent and ultralow-power nearest neighbor search with full adaptivity of the template data format, has been proposed and fabricated using the 90 nm CMOS/70 nm perpendicular-magnetic-tunnel-junction hybrid process. A truly compact current-mode circuitry is developed to realize flexibly controllable and high-parallel similarity evaluation, which makes the NV-AM adaptable to any dimensionality and component-bit of template data. A compact dual-stage time-domain minimum searching circuit is also developed, which can freely extend the system for more template data by connecting multiple NM-AM cores without additional circuits for integrated processing. Both the embedded STT-MRAM module and the computing circuit modules in this NV-AM chip are synchronously power-gated to completely eliminate standby power and maximally reduce operation power by only activating the currently accessed circuit blocks. The operations of a prototype chip at 40 MHz are demonstrated by measurement. The average operation power is only 130 µW, and the circuit density is less than 11 µm2/bit. Compared with the latest conventional works in both volatile and nonvolatile approaches, more than 31.3% circuit area reductions and 99.2% power improvements are achieved, respectively. Further power performance analyses are discussed, which verify the special superiority of the proposed NV-AM in low-power and large-memory-based VLSIs.

Recent Advances on Neuromorphic Systems Using Phase-Change Materials

NASA Astrophysics Data System (ADS)

Wang, Lei; Lu, Shu-Ren; Wen, Jing

2017-05-01

Realization of brain-like computer has always been human's ultimate dream. Today, the possibility of having this dream come true has been significantly boosted due to the advent of several emerging non-volatile memory devices. Within these innovative technologies, phase-change memory device has been commonly regarded as the most promising candidate to imitate the biological brain, owing to its excellent scalability, fast switching speed, and low energy consumption. In this context, a detailed review concerning the physical principles of the neuromorphic circuit using phase-change materials as well as a comprehensive introduction of the currently available phase-change neuromorphic prototypes becomes imperative for scientists to continuously progress the technology of artificial neural networks. In this paper, we first present the biological mechanism of human brain, followed by a brief discussion about physical properties of phase-change materials that recently receive a widespread application on non-volatile memory field. We then survey recent research on different types of neuromorphic circuits using phase-change materials in terms of their respective geometrical architecture and physical schemes to reproduce the biological events of human brain, in particular for spike-time-dependent plasticity. The relevant virtues and limitations of these devices are also evaluated. Finally, the future prospect of the neuromorphic circuit based on phase-change technologies is envisioned.

Giant Electroresistive Ferroelectric Diode on 2DEG

PubMed Central

Kim, Shin-Ik; Jin Gwon, Hyo; Kim, Dai-Hong; Keun Kim, Seong; Choi, Ji-Won; Yoon, Seok-Jin; Jung Chang, Hye; Kang, Chong-Yun; Kwon, Beomjin; Bark, Chung-Wung; Hong, Seong-Hyeon; Kim, Jin-Sang; Baek, Seung-Hyub

2015-01-01

Manipulation of electrons in a solid through transmitting, storing, and switching is the fundamental basis for the microelectronic devices. Recently, the electroresistance effect in the ferroelectric capacitors has provided a novel way to modulate the electron transport by polarization reversal. Here, we demonstrate a giant electroresistive ferroelectric diode integrating a ferroelectric capacitor into two-dimensional electron gas (2DEG) at oxide interface. As a model system, we fabricate an epitaxial Au/Pb(Zr0.2Ti0.8)O3/LaAlO3/SrTiO3 heterostructure, where 2DEG is formed at LaAlO3/SrTiO3 interface. This device functions as a two-terminal, non-volatile memory of 1 diode-1 resistor with a large I+/I− ratio (>108 at ±6 V) and Ion/Ioff ratio (>107). This is attributed to not only Schottky barrier modulation at metal/ferroelectric interface by polarization reversal but also the field-effect metal-insulator transition of 2DEG. Moreover, using this heterostructure, we can demonstrate a memristive behavior for an artificial synapse memory, where the resistance can be continuously tuned by partial polarization switching, and the electrons are only unidirectionally transmitted. Beyond non-volatile memory and logic devices, our results will provide new opportunities to emerging electronic devices such as multifunctional nanoelectronics and neuromorphic electronics. PMID:26014446

Low-voltage operating flexible ferroelectric organic field-effect transistor nonvolatile memory with a vertical phase separation P(VDF-TrFE-CTFE)/PS dielectric

NASA Astrophysics Data System (ADS)

Xu, Meili; Xiang, Lanyi; Xu, Ting; Wang, Wei; Xie, Wenfa; Zhou, Dayu

2017-10-01

Future flexible electronic systems require memory devices combining low-power operation and mechanical bendability. However, high programming/erasing voltages, which are universally needed to switch the storage states in previously reported ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memories (NVMs), severely prevent their practical applications. In this work, we develop a route to achieve a low-voltage operating flexible Fe-OFET NVM. Utilizing vertical phase separation, an ultrathin self-organized poly(styrene) (PS) buffering layer covers the surface of the ferroelectric polymer layer by one-step spin-coating from their blending solution. The ferroelectric polymer with a low coercive field contributes to low-voltage operation in the Fe-OFET NVM. The polymer PS contributes to the improvement of mobility, attributing to screening the charge scattering and decreasing the surface roughness. As a result, a high performance flexible Fe-OFET NVM is achieved at the low P/E voltages of ±10 V, with a mobility larger than 0.2 cm2 V-1 s-1, a reliable P/E endurance over 150 cycles, stable data storage retention capability over 104 s, and excellent mechanical bending durability with a slight performance degradation after 1000 repetitive tensile bending cycles at a curvature radius of 5.5 mm.

Recent Advances on Neuromorphic Systems Using Phase-Change Materials.

PubMed

Wang, Lei; Lu, Shu-Ren; Wen, Jing

2017-12-01

Realization of brain-like computer has always been human's ultimate dream. Today, the possibility of having this dream come true has been significantly boosted due to the advent of several emerging non-volatile memory devices. Within these innovative technologies, phase-change memory device has been commonly regarded as the most promising candidate to imitate the biological brain, owing to its excellent scalability, fast switching speed, and low energy consumption. In this context, a detailed review concerning the physical principles of the neuromorphic circuit using phase-change materials as well as a comprehensive introduction of the currently available phase-change neuromorphic prototypes becomes imperative for scientists to continuously progress the technology of artificial neural networks. In this paper, we first present the biological mechanism of human brain, followed by a brief discussion about physical properties of phase-change materials that recently receive a widespread application on non-volatile memory field. We then survey recent research on different types of neuromorphic circuits using phase-change materials in terms of their respective geometrical architecture and physical schemes to reproduce the biological events of human brain, in particular for spike-time-dependent plasticity. The relevant virtues and limitations of these devices are also evaluated. Finally, the future prospect of the neuromorphic circuit based on phase-change technologies is envisioned.

Nonvolatile ferroelectric memory based on PbTiO3 gated single-layer MoS2 field-effect transistor

NASA Astrophysics Data System (ADS)

Shin, Hyun Wook; Son, Jong Yeog

2018-01-01

We fabricated ferroelectric non-volatile random access memory (FeRAM) based on a field effect transistor (FET) consisting of a monolayer MoS2 channel and a ferroelectric PbTiO3 (PTO) thin film of gate insulator. An epitaxial PTO thin film was deposited on a Nb-doped SrTiO3 (Nb:STO) substrate via pulsed laser deposition. A monolayer MoS2 sheet was exfoliated from a bulk crystal and transferred to the surface of the PTO/Nb:STO. Structural and surface properties of the PTO thin film were characterized by X-ray diffraction and atomic force microscopy, respectively. Raman spectroscopy analysis was performed to identify the single-layer MoS2 sheet on the PTO/Nb:STO. We obtained mobility value (327 cm2/V·s) of the MoS2 channel at room temperature. The MoS2-PTO FeRAM FET showed a wide memory window with 17 kΩ of resistance variation which was attributed to high remnant polarization of the epitaxially grown PTO thin film. According to the fatigue resistance test for the FeRAM FET, however, the resistance states gradually varied during the switching cycles of 109. [Figure not available: see fulltext.

Thermoelectric La-doped SrTiO3 epitaxial layers with single-crystal quality: from nano to micrometers

NASA Astrophysics Data System (ADS)

Apreutesei, Mihai; Debord, Régis; Bouras, Mohamed; Regreny, Philippe; Botella, Claude; Benamrouche, Aziz; Carretero-Genevrier, Adrian; Gazquez, Jaume; Grenet, Geneviève; Pailhès, Stéphane; Saint-Girons, Guillaume; Bachelet, Romain

2017-12-01

High-quality thermoelectric La0.2Sr0.8TiO3 (LSTO) films, with thicknesses ranging from 20 nm to 0.7 μm, have been epitaxially grown on SrTiO3(001) substrates by enhanced solid-source oxide molecular-beam epitaxy. All films are atomically flat (with rms roughness < 0.2 nm), with low mosaicity (<0.1°), and present very low electrical resistivity (<5 × 10-4 Ω cm at room temperature), one order of magnitude lower than standard commercial Nb-doped SrTiO3 single-crystalline substrate. The conservation of transport properties within this thickness range has been confirmed by thermoelectric measurements where Seebeck coefficients of approximately -60 μV/K have been recorded for all films. These LSTO films can be integrated on Si for non-volatile memory structures or opto-microelectronic devices, functioning as transparent conductors or thermoelectric elements.

Towards Terabit Memories

NASA Astrophysics Data System (ADS)

Hoefflinger, Bernd

Memories have been the major yardstick for the continuing validity of Moore's law. In single-transistor-per-Bit dynamic random-access memories (DRAM), the number of bits per chip pretty much gives us the number of transistors. For decades, DRAM's have offered the largest storage capacity per chip. However, DRAM does not scale any longer, both in density and voltage, severely limiting its power efficiency to 10 fJ/b. A differential DRAM would gain four-times in density and eight-times in energy. Static CMOS RAM (SRAM) with its six transistors/cell is gaining in reputation because it scales well in cell size and operating voltage so that its fundamental advantage of speed, non-destructive read-out and low-power standby could lead to just 2.5 electrons/bit in standby and to a dynamic power efficiency of 2aJ/b. With a projected 2020 density of 16 Gb/cm², the SRAM would be as dense as normal DRAM and vastly better in power efficiency, which would mean a major change in the architecture and market scenario for DRAM versus SRAM. Non-volatile Flash memory have seen two quantum jumps in density well beyond the roadmap: Multi-Bit storage per transistor and high-density TSV (through-silicon via) technology. The number of electrons required per Bit on the storage gate has been reduced since their first realization in 1996 by more than an order of magnitude to 400 electrons/Bit in 2010 for a complexity of 32Gbit per chip at the 32 nm node. Chip stacking of eight chips with TSV has produced a 32GByte solid-state drive (SSD). A stack of 32 chips with 2 b/cell at the 16 nm node will reach a density of 2.5 Terabit/cm². Non-volatile memory with a density of 10 × 10 nm²/Bit is the target for widespread development. Phase-change memory (PCM) and resistive memory (RRAM) lead in cell density, and they will reach 20 Gb/cm² in 2D and higher with 3D chip stacking. This is still almost an order-of-magnitude less than Flash. However, their read-out speed is ~10-times faster, with as yet little data on their energy/b. As a read-out memory with unparalleled retention and lifetime, the ROM with electron-beam direct-write-lithography (Chap. 8) should be considered for its projected 2D density of 250 Gb/cm², a very small read energy of 0.1 μW/Gb/s. The lithography write-speed 10 ms/Terabit makes this ROM a serious contentender for the optimum in non-volatile, tamper-proof storage.

Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited)

NASA Astrophysics Data System (ADS)

Ando, K.; Fujita, S.; Ito, J.; Yuasa, S.; Suzuki, Y.; Nakatani, Y.; Miyazaki, T.; Yoda, H.

2014-05-01

Most parts of present computer systems are made of volatile devices, and the power to supply them to avoid information loss causes huge energy losses. We can eliminate this meaningless energy loss by utilizing the non-volatile function of advanced spin-transfer torque magnetoresistive random-access memory (STT-MRAM) technology and create a new type of computer, i.e., normally off computers. Critical tasks to achieve normally off computers are implementations of STT-MRAM technologies in the main memory and low-level cache memories. STT-MRAM technology for applications to the main memory has been successfully developed by using perpendicular STT-MRAMs, and faster STT-MRAM technologies for applications to the cache memory are now being developed. The present status of STT-MRAMs and challenges that remain for normally off computers are discussed.

Direct Observation of Conducting Filaments in Tungsten Oxide Based Transparent Resistive Switching Memory.

PubMed

Qian, Kai; Cai, Guofa; Nguyen, Viet Cuong; Chen, Tupei; Lee, Pooi See

2016-10-05

Transparent nonvolatile memory has great potential in integrated transparent electronics. Here, we present highly transparent resistive switching memory using stoichiometric WO 3 film produced by cathodic electrodeposition with indium tin oxide electrodes. The memory device demonstrates good optical transmittance, excellent operative uniformity, low operating voltages (+0.25 V/-0.42 V), and long retention time (>10 4 s). Conductive atomic force microscopy, ex situ transmission electron microscopy, and X-ray photoelectron spectroscopy experiments directly confirm that the resistive switching effects occur due to the electric field-induced formation and annihilation of the tungsten-rich conductive channel between two electrodes. Information on the physical and chemical nature of conductive filaments offers insightful design strategies for resistive switching memories with excellent performances. Moreover, we demonstrate the promising applicability of the cathodic electrodeposition method for future resistive memory devices.

A study on carbon nanotube bridge as a electromechanical memory device

NASA Astrophysics Data System (ADS)

Kang, Jeong Won; Ha Lee, Jun; Joo Lee, Hoong; Hwang, Ho Jung

2005-04-01

A nanoelectromechanical (NEM) nanotube random access memory (NRAM) device based on carbon nanotube (CNT) was investigated using atomistic simulations. For the CNT-based NEM memory, the mechanical properties of the CNT-bridge and van der Waals interactions between the CNT-bridge and substrate were very important. The critical amplitude of the CNT-bridge was 16% of the length of the CNT-bridge. As molecular dynamics time increased, the CNT-bridge went to the steady state under the electrostatic force with the damping of the potential and the kinetic energies of the CNT-bridge. The interatomic interaction between the CNT-bridge and substrate, value of the CNT-bridge slack, and damping rate of the CNT-bridge were very important for the operation of the NEM memory device as a nonvolatile memory.

Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

NASA Astrophysics Data System (ADS)

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Bhansali, Unnat. S.; Alshareef, H. N.

2012-06-01

High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin film transistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectric transistors, which is very promising for low-power non-volatile memory applications.

Analogue spin-orbit torque device for artificial-neural-network-based associative memory operation

NASA Astrophysics Data System (ADS)

Borders, William A.; Akima, Hisanao; Fukami, Shunsuke; Moriya, Satoshi; Kurihara, Shouta; Horio, Yoshihiko; Sato, Shigeo; Ohno, Hideo

2017-01-01

We demonstrate associative memory operations reminiscent of the brain using nonvolatile spintronics devices. Antiferromagnet-ferromagnet bilayer-based Hall devices, which show analogue-like spin-orbit torque switching under zero magnetic fields and behave as artificial synapses, are used. An artificial neural network is used to associate memorized patterns from their noisy versions. We develop a network consisting of a field-programmable gate array and 36 spin-orbit torque devices. An effect of learning on associative memory operations is successfully confirmed for several 3 × 3-block patterns. A discussion on the present approach for realizing spintronics-based artificial intelligence is given.

Low-power embedded read-only memory using atom switch and silicon-on-thin-buried-oxide transistor

NASA Astrophysics Data System (ADS)

Sakamoto, Toshitsugu; Tada, Munehiro; Tsuji, Yukihide; Makiyama, Hideki; Hasegawa, Takumi; Yamamoto, Yoshiki; Okanishi, Shinobu; Banno, Naoki; Miyamura, Makoto; Okamoto, Koichiro; Iguchi, Noriyuki; Ogasahara, Yasuhiro; Oda, Hidekazu; Kamohara, Shiro; Yamagata, Yasushi; Sugii, Nobuyuki; Hada, Hiromitsu

2015-04-01

We developed an atom-switch read-only memory (ROM) fabricated on silicon-on-thin-buried-oxide (SOTB) for use in a low-power microcontroller for the first time. An atom switch with a low programming voltage and large ON/OFF conductance ratio is suitable for low-power nonvolatile memory. The atom-switch ROM using an SOTB transistor uses a 0.34-1.2 V operating voltage and 12 µA/MHz active current (or 4.5 µW/MHz active power). Furthermore, the sleep current is as low as 0.4 µA when a body bias voltage is applied to the SOTB.

Models for Total-Dose Radiation Effects in Non-Volatile Memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Campbell, Philip Montgomery; Wix, Steven D.

The objective of this work is to develop models to predict radiation effects in non- volatile memory: flash memory and ferroelectric RAM. In flash memory experiments have found that the internal high-voltage generators (charge pumps) are the most sensitive to radiation damage. Models are presented for radiation effects in charge pumps that demonstrate the experimental results. Floating gate models are developed for the memory cell in two types of flash memory devices by Intel and Samsung. These models utilize Fowler-Nordheim tunneling and hot electron injection to charge and erase the floating gate. Erase times are calculated from the models andmore » compared with experimental results for different radiation doses. FRAM is less sensitive to radiation than flash memory, but measurements show that above 100 Krad FRAM suffers from a large increase in leakage current. A model for this effect is developed which compares closely with the measurements.« less

Thermally efficient and highly scalable In2Se3 nanowire phase change memory

NASA Astrophysics Data System (ADS)

Jin, Bo; Kang, Daegun; Kim, Jungsik; Meyyappan, M.; Lee, Jeong-Soo

2013-04-01

The electrical characteristics of nonvolatile In2Se3 nanowire phase change memory are reported. Size-dependent memory switching behavior was observed in nanowires of varying diameters and the reduction in set/reset threshold voltage was as low as 3.45 V/6.25 V for a 60 nm nanowire, which is promising for highly scalable nanowire memory applications. Also, size-dependent thermal resistance of In2Se3 nanowire memory cells was estimated with values as high as 5.86×1013 and 1.04×106 K/W for a 60 nm nanowire memory cell in amorphous and crystalline phases, respectively. Such high thermal resistances are beneficial for improvement of thermal efficiency and thus reduction in programming power consumption based on Fourier's law. The evaluation of thermal resistance provides an avenue to develop thermally efficient memory cell architecture.

A Low Cost Microcomputer Laboratory for Investigating Computer Architecture.

ERIC Educational Resources Information Center

Mitchell, Eugene E., Ed.

1980-01-01

Described is a microcomputer laboratory at the United States Military Academy at West Point, New York, which provides easy access to non-volatile memory and a single input/output file system for 16 microcomputer laboratory positions. A microcomputer network that has a centralized data base is implemented using the concepts of computer network…

Architectural Techniques For Managing Non-volatile Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh

As chip power dissipation becomes a critical challenge in scaling processor performance, computer architects are forced to fundamentally rethink the design of modern processors and hence, the chip-design industry is now at a major inflection point in its hardware roadmap. The high leakage power and low density of SRAM poses serious obstacles in its use for designing large on-chip caches and for this reason, researchers are exploring non-volatile memory (NVM) devices, such as spin torque transfer RAM, phase change RAM and resistive RAM. However, since NVMs are not strictly superior to SRAM, effective architectural techniques are required for making themmore » a universal memory solution. This book discusses techniques for designing processor caches using NVM devices. It presents algorithms and architectures for improving their energy efficiency, performance and lifetime. It also provides both qualitative and quantitative evaluation to help the reader gain insights and motivate them to explore further. This book will be highly useful for beginners as well as veterans in computer architecture, chip designers, product managers and technical marketing professionals.« less

Intrinsic Ferroelasticity and/or Multiferroicity in Two-Dimensional Phosphorene and Phosphorene Analogues.

PubMed

Wu, Menghao; Zeng, Xiao Cheng

2016-05-11

Phosphorene and phosphorene analogues such as SnS and SnSe monolayers are promising nanoelectronic materials with desired bandgap, high carrier mobility, and anisotropic structures. Here, we show first-principles calculation evidence that these monolayers are potentially the long-sought two-dimensional (2D) materials that can combine electronic transistor characteristic with nonvolatile memory readable/writeable capability at ambient condition. Specifically, phosphorene is predicted to be a 2D intrinsic ferroelastic material with ultrahigh reversible strain, whereas SnS, SnSe, GeS, and GeSe monolayers are multiferroic with coupled ferroelectricity and ferroelasticity. Moreover, their low-switching barriers render room-temperature nonvolatile memory accessible, and their notable structural anisotropy enables ferroelastic or ferroelectric switching readily readable via electrical, thermal, optical, mechanical, or even spintronic detection upon the swapping of the zigzag and armchair direction. In addition, it is predicted that the GeS and GeSe monolayers as well as bulk SnS and SnSe can maintain their ferroelasticity and ferroelectricity (anti-ferroelectricity) beyond the room temperature, suggesting high potential for practical device application.

Homogeneous-oxide stack in IGZO thin-film transistors for multi-level-cell NAND memory application

NASA Astrophysics Data System (ADS)

Ji, Hao; Wei, Yehui; Zhang, Xinlei; Jiang, Ran

2017-11-01

A nonvolatile charge-trap-flash memory that is based on amorphous indium-gallium-zinc-oxide thin film transistors was fabricated with a homogeneous-oxide structure for a multi-level-cell application. All oxide layers, i.e., tunneling layer, charge trapping layer, and blocking layer, were fabricated with Al2O3 films. The fabrication condition (including temperature and deposition method) of the charge trapping layer was different from those of the other oxide layers. This device demonstrated a considerable large memory window of 4 V between the states fully erased and programmed with the operation voltage less than 14 V. This kind of device shows a good prospect for multi-level-cell memory applications.

Surface engineering of ferroelectric polymer for the enhanced electrical performance of organic transistor memory

NASA Astrophysics Data System (ADS)

Kim, Do-Kyung; Lee, Gyu-Jeong; Lee, Jae-Hyun; Kim, Min-Hoi; Bae, Jin-Hyuk

2018-05-01

We suggest a viable surface control method to improve the electrical properties of organic nonvolatile memory transistors. For viable surface control, the surface of the ferroelectric insulator in the memory field-effect transistors was modified using a smooth-contact-curing process. For the modification of the ferroelectric polymer, during the curing of the ferroelectric insulators, the smooth surface of a soft elastomer contacts intimately with the ferroelectric surface. This smooth-contact-curing process reduced the surface roughness of the ferroelectric insulator without degrading its ferroelectric properties. The reduced roughness of the ferroelectric insulator increases the mobility of the organic field-effect transistor by approximately eight times, which results in a high memory on–off ratio and a low-voltage reading operation.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

NASA Astrophysics Data System (ADS)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG in the form of PVD TaN was investigated along with high-k blocking dielectric. The material properties of TaN metal and high-k / low-k dielectric engineering were systematically studied. And the resulting memory structures exhibit excellent memory characteristics and scalability of the metal FG down to ˜1nm, which is promising in order to reduce the unwanted FG-FG interferences. In the later part of the study, the thermal stability of the combined stack was examined and various approaches to improve the stability and understand the cause of instability were explored. The performance of the high-k IPD metal FG memory structure was observed to degrade with higher annealing conditions and the deteriorated behavior was attributed to the leakage instability of the high-k /TaN capacitor. While the degradation is pronounced in both MIM and MIS capacitors, a higher leakage increment was seen in MIM, which was attributed to the higher degree of dielectric crystallization. In an attempt to improve the thermal stability, the trade-off in using amorphous interlayers to reduce the enhanced dielectric crystallization on metal was highlighted. Also, the effect of oxygen vacancies and grain growth on the dielectric leakage was studied through a multi-deposition-multi-anneal technique. Multi step deposition and annealing in a more electronegative ambient was observed to have a positive impact on the dielectric performance.

RESTOP: Retaining External Peripheral State in Intermittently-Powered Sensor Systems.

PubMed

Rodriguez Arreola, Alberto; Balsamo, Domenico; Merrett, Geoff V; Weddell, Alex S

2018-01-10

Energy harvesting sensor systems typically incorporate energy buffers (e.g., rechargeable batteries and supercapacitors) to accommodate fluctuations in supply. However, the presence of these elements limits the miniaturization of devices. In recent years, researchers have proposed a new paradigm, transient computing, where systems operate directly from the energy harvesting source and allow computation to span across power cycles, without adding energy buffers. Various transient computing approaches have addressed the challenge of power intermittency by retaining the processor's state using non-volatile memory. However, no generic approach has yet been proposed to retain the state of peripherals external to the processing element. This paper proposes RESTOP, flexible middleware which retains the state of multiple external peripherals that are connected to a computing element (i.e., a microcontroller) through protocols such as SPI or I 2 C. RESTOP acts as an interface between the main application and the peripheral, which keeps a record, at run-time, of the transmitted data in order to restore peripheral configuration after a power interruption. RESTOP is practically implemented and validated using three digitally interfaced peripherals, successfully restoring their configuration after power interruptions, imposing a maximum time overhead of 15% when configuring a peripheral. However, this represents an overhead of only 0.82% during complete execution of our typical sensing application, which is substantially lower than existing approaches.

Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Wei, E-mail: wwei99@jlu.edu.cn; Han, Jinhua; Ying, Jun

2014-09-22

Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm{sup 2}/V s. The unidirectional shift of turn-on voltage (V{sub on}) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V{sub P}/V{sub E}) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered moleculemore » orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm{sup 2}/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V{sub P}/V{sub E} of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V{sub on} shift. As a result, an enlarged memory window of 28.6 V at the V{sub P}/V{sub E} of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.« less

Feedforward, high density, programmable read only neural network based memory system

NASA Technical Reports Server (NTRS)

Daud, Taher; Moopenn, Alex; Lamb, James; Thakoor, Anil; Khanna, Satish

1988-01-01

Neural network-inspired, nonvolatile, programmable associative memory using thin-film technology is demonstrated. The details of the architecture, which uses programmable resistive connection matrices in synaptic arrays and current summing and thresholding amplifiers as neurons, are described. Several synapse configurations for a high-density array of a binary connection matrix are also described. Test circuits are evaluated for operational feasibility and to demonstrate the speed of the read operation. The results are discussed to highlight the potential for a read data rate exceeding 10 megabits/sec.

Modular nonvolatile solid state recorder (MONSSTR) update

NASA Astrophysics Data System (ADS)

Klang, Mark R.; Small, Martin B.; Beams, Tom

2001-12-01

Solid state recorders have begun replacing traditional tape recorders in fulfilling the requirement to record images on airborne platforms. With the advances in electro-optical, IR, SAR, Multi and Hyper-spectral sensors and video recording requirements, solid state recorders have become the recorder of choice. Solid state recorders provide the additional storage, higher sustained bandwidth, less power, less weight and smaller footprint to meet the current and future recording requirements. CALCULEX, Inc., manufactures a non-volatile flash memory solid state recorder called the MONSSTR (Modular Non-volatile Solid State Recorder). MONSSTR is being used to record images from many different digital sensors on high performance aircraft such as the RF- 4, F-16 and the Royal Air Force Tornado. MONSSTR, with its internal multiplexer, is also used to record instrumentation data. This includes multiple streams of PCM and multiple channels of 1553 data. Instrumentation data is being recorded by MONSSTR systems in a range of platforms including F-22, F-15, F-16, Comanche Helicopter and US Navy torpedos. MONSSTR can also be used as a cockpit video recorder. This paper will provide an update of the MONSSTR.

Effect of AlN layer on the bipolar resistive switching behavior in TiN thin film based ReRAM device for non-volatile memory application

NASA Astrophysics Data System (ADS)

Prakash, Ravi; Kaur, Davinder

2018-05-01

The effect of an additional AlN layer in the Cu/TiN/AlN/Pt stack configuration deposited using sputtering has been investigated. The Cu/TiN/AlN/Pt device shows a tristate resistive switching. Multilevel switching is facilitated by ionic and metallic filament formation, and the nature of the filaments formed is confirmed by performing a resistance vs. temperature measurement. Ohmic behaviour and trap controlled space charge limited current (SCLC) conduction mechanisms are confirmed as dominant conduction mechanism at low resistance state (LRS) and high resistance state (HRS). High resistance ratio (102) corresponding to HRS and LRS, good write/erase endurance (105) and non-volatile long retention (105s) are also observed. Higher thermal conductivity of the AlN layer is the main reasons for the enhancement of resistive switching performance in Cu/TiN/AlN/Pt cell. The above result suggests the feasibility of Cu/TiN/AlN/Pt devices for multilevel nonvolatile ReRAM application.

Impact of gate work-function on memory characteristics in Al2O3/HfOx/Al2O3/graphene charge-trap memory devices

NASA Astrophysics Data System (ADS)

Lee, Sejoon; Song, Emil B.; Kim, Sungmin; Seo, David H.; Seo, Sunae; Won Kang, Tae; Wang, Kang L.

2012-01-01

Graphene-based non-volatile memory devices composed of a single-layer graphene channel and an Al2O3/HfOx/Al2O3 charge-storage layer exhibit memory functionality. The impact of the gate material's work-function (Φ) on the memory characteristics is investigated using different types of metals [Ti (ΦTi = 4.3 eV) and Ni (ΦNi = 5.2 eV)]. The ambipolar carrier conduction of graphene results in an enlargement of memory window (ΔVM), which is ˜4.5 V for the Ti-gate device and ˜9.1 V for the Ni-gate device. The increase in ΔVM is attributed to the change in the flat-band condition and the suppression of electron back-injection within the gate stack.

Air-stable memory array of bistable rectifying diodes based on ferroelectric-semiconductor polymer blends

NASA Astrophysics Data System (ADS)

Kumar, Manasvi; Sharifi Dehsari, Hamed; Anwar, Saleem; Asadi, Kamal

2018-03-01

Organic bistable diodes based on phase-separated blends of ferroelectric and semiconducting polymers have emerged as promising candidates for non-volatile information storage for low-cost solution processable electronics. One of the bottlenecks impeding upscaling is stability and reliable operation of the array in air. Here, we present a memory array fabricated with an air-stable amine-based semiconducting polymer. Memory diode fabrication and full electrical characterizations were carried out in atmospheric conditions (23 °C and 45% relative humidity). The memory diodes showed on/off ratios greater than 100 and further exhibited robust and stable performance upon continuous write-read-erase-read cycles. Moreover, we demonstrate a 4-bit memory array that is free from cross-talk with a shelf-life of several months. Demonstration of the stability and reliable air operation further strengthens the feasibility of the resistance switching in ferroelectric memory diodes for low-cost applications.

In situ and nonvolatile photoluminescence tuning and nanodomain writing demonstrated by all-solid-state devices based on graphene oxide.

PubMed

Tsuchiya, Takashi; Tsuruoka, Tohru; Terabe, Kazuya; Aono, Masakazu

2015-02-24

In situ and nonvolatile tuning of photoluminescence (PL) has been achieved based on graphene oxide (GO), the PL of which is receiving much attention because of various potential applications of the oxide (e.g., display, lighting, and nano-biosensor). The technique is based on in situ and nonvolatile tuning of the sp(2) domain fraction to the sp(3) domain fraction (sp(2)/sp(3) fraction) in GO through an electrochemical redox reaction achieved by solid electrolyte thin films. The all-solid-state variable PL device was fabricated by GO and proton-conducting mesoporous SiO2 thin films, which showed an extremely low PL background. The device successfully tuned the PL peak wavelength in a very wide range from 393 to 712 nm, covering that for chemically tuned GO, by adjusting the applied DC voltage within several hundred seconds. We also demonstrate the sp(2)/sp(3) fraction tuning using a conductive atomic force microscope. The device achieved not only writing, but also erasing of the sp(2)/sp(3)-fraction-tuned nanodomain (both directions operation). The combination of these techniques is applicable to a wide range of nano-optoelectronic devices including nonvolatile PL memory devices and on-demand rewritable biosensors that can be integrated into nano- and microtips which are transparent, ultrathin, flexible, and inexpensive.

Nanogap-Engineerable Electromechanical System for Ultralow Power Memory.

PubMed

Zhang, Jian; Deng, Ya; Hu, Xiao; Nshimiyimana, Jean Pierre; Liu, Siyu; Chi, Xiannian; Wu, Pei; Dong, Fengliang; Chen, Peipei; Chu, Weiguo; Zhou, Haiqing; Sun, Lianfeng

2018-02-01

Nanogap engineering of low-dimensional nanomaterials has received considerable interest in a variety of fields, ranging from molecular electronics to memories. Creating nanogaps at a certain position is of vital importance for the repeatable fabrication of the devices. Here, a rational design of nonvolatile memories based on sub-5 nm nanogaped single-walled carbon nanotubes (SWNTs) via the electromechanical motion is reported. The nanogaps are readily realized by electroburning in a partially suspended SWNT device with nanoscale region. The SWNT memory devices are applicable for both metallic and semiconducting SWNTs, resolving the challenge of separation of semiconducting SWNTs from metallic ones. Meanwhile, the memory devices exhibit excellent performance: ultralow writing energy (4.1 × 10 -19 J bit -1 ), ON/OFF ratio of 10 5 , stable switching ON operations, and over 30 h retention time in ambient conditions.

Bulk heterojunction polymer memory devices with reduced graphene oxide as electrodes.

PubMed

Liu, Juqing; Yin, Zongyou; Cao, Xiehong; Zhao, Fei; Lin, Anping; Xie, Linghai; Fan, Quli; Boey, Freddy; Zhang, Hua; Huang, Wei

2010-07-27

A unique device structure with a configuration of reduced graphene oxide (rGO) /P3HT:PCBM/Al has been designed for the polymer nonvolatile memory device. The current-voltage (I-V) characteristics of the fabricated device showed the electrical bistability with a write-once-read-many-times (WORM) memory effect. The memory device exhibits a high ON/OFF ratio (10(4)-10(5)) and low switching threshold voltage (0.5-1.2 V), which are dependent on the sheet resistance of rGO electrode. Our experimental results confirm that the carrier transport mechanisms in the OFF and ON states are dominated by the thermionic emission current and ohmic current, respectively. The polarization of PCBM domains and the localized internal electrical field formed among the adjacent domains are proposed to explain the electrical transition of the memory device.

Nanogap‐Engineerable Electromechanical System for Ultralow Power Memory

PubMed Central

Zhang, Jian; Deng, Ya; Hu, Xiao; Nshimiyimana, Jean Pierre; Liu, Siyu; Chi, Xiannian; Wu, Pei; Dong, Fengliang; Chen, Peipei

2017-01-01

Abstract Nanogap engineering of low‐dimensional nanomaterials has received considerable interest in a variety of fields, ranging from molecular electronics to memories. Creating nanogaps at a certain position is of vital importance for the repeatable fabrication of the devices. Here, a rational design of nonvolatile memories based on sub‐5 nm nanogaped single‐walled carbon nanotubes (SWNTs) via the electromechanical motion is reported. The nanogaps are readily realized by electroburning in a partially suspended SWNT device with nanoscale region. The SWNT memory devices are applicable for both metallic and semiconducting SWNTs, resolving the challenge of separation of semiconducting SWNTs from metallic ones. Meanwhile, the memory devices exhibit excellent performance: ultralow writing energy (4.1 × 10−19 J bit−1), ON/OFF ratio of 105, stable switching ON operations, and over 30 h retention time in ambient conditions. PMID:29619307

PMMA interlayer-modulated memory effects by space charge polarization in resistive switching based on CuSCN-nanopyramids/ZnO-nanorods p-n heterojunction

PubMed Central

Cheng, Baochang; Zhao, Jie; Xiao, Li; Cai, Qiangsheng; Guo, Rui; Xiao, Yanhe; Lei, Shuijin

2015-01-01

Resistive switching (RS) devices are commonly believed as a promising candidate for next generation nonvolatile resistance random access memory. Here, polymethylmethacrylate (PMMA) interlayer was introduced at the heterointerface of p-CuSCN hollow nanopyramid arrays and n-ZnO nanorod arrays, resulting in a typical bipolar RS behavior. We propose the mechanism of nanostructure trap-induced space charge polarization modulated by PMMA interlayer. At low reverse bias, PMMA insulator can block charges through the heterointerface, and and trapped states are respectively created on both sides of PMMA, resulting in a high resistance state (HRS) due to wider depletion region. At high reverse bias, however, electrons and holes can cross PMMA interlayer by Fowler-Nordeim tunneling due to a massive tilt of energy band, and then inject into the traps of ZnO and CuSCN, respectively. and trapped states are created, resulting in the formation of degenerate semiconductors on both sides of PMMA. Therefore, quantum tunneling and space charge polarization lead to a low resistance state (LRS). At relatively high forward bias, subsequently, the trapped states of and are recreated due to the opposite injection of charges, resulting in a recovery of HRS. The introduction of insulating interlayer at heterointerface, point a way to develop next-generation nonvolatile memories. PMID:26648249

On-chip phase-change photonic memory and computing

NASA Astrophysics Data System (ADS)

Cheng, Zengguang; Ríos, Carlos; Youngblood, Nathan; Wright, C. David; Pernice, Wolfram H. P.; Bhaskaran, Harish

2017-08-01

The use of photonics in computing is a hot topic of interest, driven by the need for ever-increasing speed along with reduced power consumption. In existing computing architectures, photonic data storage would dramatically improve the performance by reducing latencies associated with electrical memories. At the same time, the rise of `big data' and `deep learning' is driving the quest for non-von Neumann and brain-inspired computing paradigms. To succeed in both aspects, we have demonstrated non-volatile multi-level photonic memory avoiding the von Neumann bottleneck in the existing computing paradigm and a photonic synapse resembling the biological synapses for brain-inspired computing using phase-change materials (Ge2Sb2Te5).

Enhanced organic memory devices (OMEM) with a photochromic perhydro DTE as a transduction layer (Conference Presentation)

NASA Astrophysics Data System (ADS)

Cordes, Sandra; Kranz, Darius; Maibach, Eduard; Kempf, Maxim; Meerholz, Klaus

2016-09-01

In modern electronic systems memory elements are of fundamental importance for data storage. Especially solution-processable nonvolatile organic memories, which are inexpensive and can be manufactured on flexible substrates, are a promising alternative to brittle inorganic devices. Organic photochromic switchable compounds, mostly dithienylethenes (DTEs), are thermally stable, fatigue resistant and can undergo an electrically- or/and photo-induced ring-opening and -closing reaction which results in a change of energy levels. Due to the energetic difference in the highest occupied molecular orbital (HOMO) between the open and closed isomer, the DTE layer can be exploited as a switchable hole injection barrier that controls the electrical current in the diode. We demonstrated that a light-emitting organic memory (LE-OMEM) device with a perfluoro DTE transduction layer can be switched electrically via high current densities pulses and optically by irradiated light, with impressive current ON/OFF Ratios (OOR) of 10Λ2, 10Λ4 respectively. Currently we aim to minimize the barrier of the ON state and maximize the barrier of the OFF state by designing DTE molecules with larger differences in the HOMO energies of the two isomers yielding improved OOR values. By synthesizing perhydro derivates of DTE we achieved molecules with high HOMO levels and large ΔHOMO energies providing OMEM devices with excellent physical properties (OOR 1.4 x higher than perfluoro DTE). Due to the high HOMO level of the perhydro DTE utilization of hole transport layers (HTLs) is not necessary and thus manufacturing of OMEM devices is simplified.

Nanopatterned ferroelectrics for ultrahigh density rad-hard nonvolatile memories.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Brennecka, Geoffrey L.; Stevens, Jeffrey; Scrymgeour, David

2010-09-01

Radiation hard nonvolatile random access memory (NVRAM) is a crucial component for DOE and DOD surveillance and defense applications. NVRAMs based upon ferroelectric materials (also known as FERAMs) are proven to work in radiation-rich environments and inherently require less power than many other NVRAM technologies. However, fabrication and integration challenges have led to state-of-the-art FERAMs still being fabricated using a 130nm process while competing phase-change memory (PRAM) has been demonstrated with a 20nm process. Use of block copolymer lithography is a promising approach to patterning at the sub-32nm scale, but is currently limited to self-assembly directly on Si or SiO{submore » 2} layers. Successful integration of ferroelectrics with discrete and addressable features of {approx}15-20nm would represent a 100-fold improvement in areal memory density and would enable more highly integrated electronic devices required for systems advances. Towards this end, we have developed a technique that allows us to carry out block copolymer self-assembly directly on a huge variety of different materials and have investigated the fabrication, integration, and characterization of electroceramic materials - primarily focused on solution-derived ferroelectrics - with discrete features of {approx}20nm and below. Significant challenges remain before such techniques will be capable of fabricating fully integrated NVRAM devices, but the tools developed for this effort are already finding broader use. This report introduces the nanopatterned NVRAM device concept as a mechanism for motivating the subsequent studies, but the bulk of the document will focus on the platform and technology development.« less

Layer-by-layer charging in non-volatile memory devices using embedded sub-2 nm platinum nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ramalingam, Balavinayagam; Zheng, Haisheng; Gangopadhyay, Shubhra, E-mail: gangopadhyays@missouri.edu

In this work, we demonstrate multi-level operation of a non-volatile memory metal oxide semiconductor capacitor by controlled layer-by-layer charging of platinum nanoparticle (PtNP) floating gate devices with defined gate voltage bias ranges. The device consists of two layers of ultra-fine, sub-2 nm PtNPs integrated between Al{sub 2}O{sub 3} tunneling and separation layers. PtNP size and interparticle distance were varied to control the particle self-capacitance and associated Coulomb charging energy. Likewise, the tunneling layer thicknesses were also varied to control electron tunneling to the first and second PtNP layers. The final device configuration with optimal charging behavior and multi-level programming was attainedmore » with a 3 nm Al{sub 2}O{sub 3} initial tunneling layer, initial PtNP layer with particle size 0.54 ± 0.12 nm and interparticle distance 4.65 ± 2.09 nm, 3 nm Al{sub 2}O{sub 3} layer to separate the PtNP layers, and second particle layer with 1.11 ± 0.28 nm PtNP size and interparticle distance 2.75 ± 1.05 nm. In this device, the memory window of the first PtNP layer saturated over a programming bias range of 7 V to 14 V, after which the second PtNP layer starts charging, exhibiting a multi-step memory window with layer-by-layer charging.« less

Switching mechanism transition induced by annealing treatment in nonvolatile Cu/ZnO/Cu/ZnO/Pt resistive memory: From carrier trapping/detrapping to electrochemical metallization

NASA Astrophysics Data System (ADS)

Yang, Y. C.; Pan, F.; Zeng, F.; Liu, M.

2009-12-01

ZnO/Cu/ZnO trilayer films sandwiched between Cu and Pt electrodes were prepared for nonvolatile resistive memory applications. These structures show resistance switching under electrical bias both before and after a rapid thermal annealing (RTA) treatment, while it is found that the resistive switching effects in the two cases exhibit distinct characteristics. Compared with the as-fabricated device, the memory cell after RTA demonstrates remarkable device parameter improvements including lower threshold voltages, lower write current, and higher Roff/Ron ratio. A high-voltage forming process is avoided in the annealed device as well. Furthermore, the RTA treatment has triggered a switching mechanism transition from a carrier trapping/detrapping type to an electrochemical-redox-reaction-controlled conductive filament formation/rupture process, as indicated by different features in current-voltage characteristics. Both scanning electron microscopy observations and Auger electron spectroscopy depth profiles reveal that the Cu charge trapping layer in ZnO/Cu/ZnO disperses uniformly into the storage medium after RTA, while x-ray diffraction and x-ray photoelectron spectroscopy analyses demonstrate that the Cu atoms have lost electrons to become Cu2+ ions after dispersion. The above experimental facts indicate that the altered status of Cu in the ZnO/Cu/ZnO trilayer films during RTA treatment should be responsible for the switching mechanism transition. This study is envisioned to open the door for understanding the interrelation between different mechanisms that currently exist in the field of resistive memories.

Research of influence of the underlayer material on the growth rate of carbon nanotube arrays for manufacturing non-volatile memory elements with high speed

NASA Astrophysics Data System (ADS)

Klimin, V. S.; Il'ina, M. V.; Il'in, O. I.; Rudyk, N. N.; Ageev, O. A.

2017-11-01

This experimental work is devoted to the regimes of obtaining arrays of carbon nanotubes. Arrays of perpendicular nanotubes perpendicular to the surface were obtained by the method of Plasma-enhanced chemical vapor deposition. In this paper, geometric and electronic parameters of carbon nanotubes were investigated depending on the material of the sublayer. The rates of growth of carbon nanotubes on various structures were also determined. In the experiments for growth, structures such as Ni-Al-Si, Ni-V-Si, Ni-Ti-Si, Ni-Cr-Si were used. The growth rates for the intensive section were for the Ni-Cr-Si structure, the growth rate is about 1 μm / min, for the Ni-V-Si structure it is 0.55 μm / min. The growth rates for the saturation region for the Ni-Cr-Si structure, the growth rate is about 0.2 μm / min, for the Ni-V-Si structure 0.16 μm / min. The results obtained in this paper can be used to optimize the growth regimes perpendicularly oriented to the substrate carbon nanotubes, which are used as various elements in modern nanoelectronics.

Future Development of Dense Ferroelectric Memories for Space Applications

NASA Technical Reports Server (NTRS)

Philpy, Stephen C.; Derbenwick, Gary F.

2001-01-01

The availability of high density, radiation tolerant, nonvolatile memories is critical for space applications. Ferroelectric memories, when fabricated with radiation hardened complementary metal oxide semiconductors (CMOS), can be manufactured and packaged to provide high density replacements for Flash memory, which is not radiation tolerant. Previous work showed ferroelectric memory cells to be resistant to single event upsets and proton irradiation, and ferroelectric storage capacitors to be resistant to neutron exposure. In addition to radiation hardness, the fast programming times, virtually unlimited endurance, and low voltage, low power operation make ferroelectric memories ideal for space missions. Previously, a commercial double level metal 64-kilobit ferroelectric memory was presented. Although the capabilities of radiation hardened wafer fabrication facilities lag behind those of the most modern commercial wafer fabrication facilities, several paths to achieving radiation tolerant, dense ferroelectric memories are emerging. Both short and long term solutions are presented in this paper. Although worldwide major semiconductor companies are introducing commercial ferroelectric memories, funding limitations must be overcome to proceed with the development of high density, radiation tolerant ferroelectric memories.

Robust resistive memory devices using solution-processable metal-coordinated azo aromatics

NASA Astrophysics Data System (ADS)

Goswami, Sreetosh; Matula, Adam J.; Rath, Santi P.; Hedström, Svante; Saha, Surajit; Annamalai, Meenakshi; Sengupta, Debabrata; Patra, Abhijeet; Ghosh, Siddhartha; Jani, Hariom; Sarkar, Soumya; Motapothula, Mallikarjuna Rao; Nijhuis, Christian A.; Martin, Jens; Goswami, Sreebrata; Batista, Victor S.; Venkatesan, T.

2017-12-01

Non-volatile memories will play a decisive role in the next generation of digital technology. Flash memories are currently the key player in the field, yet they fail to meet the commercial demands of scalability and endurance. Resistive memory devices, and in particular memories based on low-cost, solution-processable and chemically tunable organic materials, are promising alternatives explored by the industry. However, to date, they have been lacking the performance and mechanistic understanding required for commercial translation. Here we report a resistive memory device based on a spin-coated active layer of a transition-metal complex, which shows high reproducibility (~350 devices), fast switching (<=30 ns), excellent endurance (~1012 cycles), stability (>106 s) and scalability (down to ~60 nm2). In situ Raman and ultraviolet-visible spectroscopy alongside spectroelectrochemistry and quantum chemical calculations demonstrate that the redox state of the ligands determines the switching states of the device whereas the counterions control the hysteresis. This insight may accelerate the technological deployment of organic resistive memories.

Investigations of Photovoltaic Ferroelectric-Semiconductor Nonvolatile Memory.

DTIC Science & Technology

1981-03-01

HEWLETT-PACKARD BOX 3310 100 MARKET ST APT 1 3404 EAST HARMONY RD2U ATTN J. M. KIRSCH, MTS ATTN R. SCHAEFER ATTN L. W. JAMES, MTS FULLERTON, CA 92633...RADIO SYS SPERRY UNICORN 1300 S ROGERS 367 ORCHARD STREET 52-21 65 PL AT’rN J. F. PRATHER, MGR CEN ATTN I. A. PAULL, ES ATTN W. BURSTEIN, ENGR

Improved Operation Characteristics for Nonvolatile Charge-Trapping Memory Capacitors with High-κ Dielectrics and SiGe Epitaxial Substrates

NASA Astrophysics Data System (ADS)

Hou, Zhao-Zhao; Wang, Gui-Lei; Xiang, Jin-Juan; Yao, Jia-Xin; Wu, Zhen-Hua; Zhang, Qing-Zhu; Yin, Hua-Xiang

2017-08-01

Not Available Supported by the National Science and Technology Major Project of China under Grant No 2013ZX02303007, the National Key Research and Development Program of China under Grant No 2016YFA0301701, and the Youth Innovation Promotion Association of the Chinese Academy of Sciences under Grant No 2016112.

Electrical Study of Trapped Charges in Copper-Doped Zinc Oxide Films by Scanning Probe Microscopy for Nonvolatile Memory Applications

PubMed Central

Su, Ting; Zhang, Haifeng

2017-01-01

Charge trapping properties of electrons and holes in copper-doped zinc oxide (ZnO:Cu) films have been studied by scanning probe microscopy. We investigated the surface potential dependence on the voltage and duration applied to the copper-doped ZnO films by Kelvin probe force microscopy. It is found that the Fermi Level of the 8 at.% Cu-doped ZnO films shifted by 0.53 eV comparing to undoped ZnO films. This shift indicates significant change in the electronic structure and energy balance in Cu-doped ZnO films. The Fermi Level (work function) of zinc oxide films can be tuned by Cu doping, which are important for developing this functional material. In addition, Kelvin probe force microscopy measurements demonstrate that the nature of contact at Pt-coated tip/ZnO:Cu interface is changed from Schottky contact to Ohmic contact by increasing sufficient amount of Cu ions. The charge trapping property of the ZnO films enhance greatly by Cu doping (~10 at.%). The improved stable bipolar charge trapping properties indicate that copper-doped ZnO films are promising for nonvolatile memory applications. PMID:28135335

Microwave-Assisted Size Control of Colloidal Nickel Nanocrystals for Colloidal Nanocrystals-Based Non-volatile Memory Devices

NASA Astrophysics Data System (ADS)

Yadav, Manoj; Velampati, Ravi Shankar R.; Mandal, D.; Sharma, Rohit

2018-03-01

Colloidal synthesis and size control of nickel (Ni) nanocrystals (NCs) below 10 nm are reported using a microwave synthesis method. The synthesised colloidal NCs have been characterized using x-ray diffraction, transmission electron microscopy (TEM) and dynamic light scattering (DLS). XRD analysis highlights the face centred cubic crystal structure of synthesised NCs. The size of NCs observed using TEM and DLS have a distribution between 2.6 nm and 10 nm. Furthermore, atomic force microscopy analysis of spin-coated NCs over a silicon dioxide surface has been carried out to identify an optimum spin condition that can be used for the fabrication of a metal oxide semiconductor (MOS) non-volatile memory (NVM) capacitor. Subsequently, the fabrication of a MOS NVM capacitor is reported to demonstrate the potential application of colloidal synthesized Ni NCs in NVM devices. We also report the capacitance-voltage (C-V) and capacitance-time (C-t) response of the fabricated MOS NVM capacitor. The C-V and C-t characteristics depict a large flat band voltage shift (V FB) and high retention time, respectively, which indicate that colloidal Ni NCs are excellent candidates for applications in next-generation NVM devices.

Ferroelectric-field-effect-enhanced electroresistance in metal/ferroelectric/semiconductor tunnel junctions

NASA Astrophysics Data System (ADS)

Wen, Zheng; Li, Chen; Wu, Di; Li, Aidong; Ming, Naiben

2013-07-01

Ferroelectric tunnel junctions (FTJs), composed of two metal electrodes separated by an ultrathin ferroelectric barrier, have attracted much attention as promising candidates for non-volatile resistive memories. Theoretical and experimental works have revealed that the tunnelling resistance switching in FTJs originates mainly from a ferroelectric modulation on the barrier height. However, in these devices, modulation on the barrier width is very limited, although the tunnelling transmittance depends on it exponentially as well. Here we propose a novel tunnelling heterostructure by replacing one of the metal electrodes in a normal FTJ with a heavily doped semiconductor. In these metal/ferroelectric/semiconductor FTJs, not only the height but also the width of the barrier can be electrically modulated as a result of a ferroelectric field effect, leading to a greatly enhanced tunnelling electroresistance. This idea is implemented in Pt/BaTiO3/Nb:SrTiO3 heterostructures, in which an ON/OFF conductance ratio above 104, about one to two orders greater than those reported in normal FTJs, can be achieved at room temperature. The giant tunnelling electroresistance, reliable switching reproducibility and long data retention observed in these metal/ferroelectric/semiconductor FTJs suggest their great potential in non-destructive readout non-volatile memories.

Octonary resistance states in La 0.7Sr 0.3MnO 3/BaTiO 3/La 0.7Sr 0.3MnO 3 multiferroic tunnel junctions

DOE PAGES

Yue -Wei Yin; Tao, Jing; Huang, Wei -Chuan; ...

2015-10-06

General drawbacks of current electronic/spintronic devices are high power consumption and low density storage. A multiferroic tunnel junction (MFTJ), employing a ferroelectric barrier layer sandwiched between two ferromagnetic layers, presents four resistance states in a single device and therefore provides an alternative way to achieve high density memories. Here, an MFTJ device with eight nonvolatile resistance states by further integrating the design of noncollinear magnetization alignments between the ferromagnetic layers is demonstrated. Through the angle-resolved tunneling magnetoresistance investigations on La 0.7Sr 0.3MnO 3/BaTiO 3/La 0.7Sr 0.3MnO 3 junctions, it is found that, besides collinear parallel/antiparallel magnetic configurations, the MFTJ showsmore » at least two other stable noncollinear (45° and 90°) magnetic configurations. As a result, combining the tunneling electroresistance effect caused by the ferroelectricity reversal of the BaTiO 3 barrier, an octonary memory device is obtained, representing potential applications in high density nonvolatile storage in the future.« less

A graphene-based non-volatile memory

NASA Astrophysics Data System (ADS)

Loisel, Loïc.; Maurice, Ange; Lebental, Bérengère; Vezzoli, Stefano; Cojocaru, Costel-Sorin; Tay, Beng Kang

2015-09-01

We report on the development and characterization of a simple two-terminal non-volatile graphene switch. After an initial electroforming step during which Joule heating leads to the formation of a nano-gap impeding the current flow, the devices can be switched reversibly between two well-separated resistance states. To do so, either voltage sweeps or pulses can be used, with the condition that VSET < VRESET , where SET is the process decreasing the resistance and RESET the process increasing the resistance. We achieve reversible switching on more than 100 cycles with resistance ratio values of 104. This approach of graphene memory is competitive as compared to other graphene approaches such as redox of graphene oxide, or electro-mechanical switches with suspended graphene. We suggest a switching model based on a planar electro-mechanical switch, whereby electrostatic, elastic and friction forces are competing to switch devices ON and OFF, and the stability in the ON state is achieved by the formation of covalent bonds between the two stretched sides of the graphene, hence bridging the nano-gap. Developing a planar electro-mechanical switch enables to obtain the advantages of electro-mechanical switches while avoiding most of their drawbacks.

Nonvolatile Bio-Memristor Fabricated with Egg Albumen Film

NASA Astrophysics Data System (ADS)

Chen, Ying-Chih; Yu, Hsin-Chieh; Huang, Chun-Yuan; Chung, Wen-Lin; Wu, San-Lein; Su, Yan-Kuin

2015-05-01

This study demonstrates the fabrication and characterization of chicken egg albumen-based bio-memristors. By introducing egg albumen as an insulator to fabricate memristor devices comprising a metal/insulator/metal sandwich structure, significant bipolar resistive switching behavior can be observed. The 1/f noise characteristics of the albumen devices were measured, and results suggested that their memory behavior results from the formation and rupture of conductive filaments. Oxygen diffusion and electrochemical redox reaction of metal ions under a sufficiently large electric field are the principal physical mechanisms of the formation and rupture of conductive filaments; these mechanisms were observed by analysis of the time-of-flight secondary ion mass spectrometry (TOF-SIMS) and resistance-temperature (R-T) measurement results. The switching property of the devices remarkably improved by heat-denaturation of proteins; reliable switching endurance of over 500 cycles accompanied by an on/off current ratio (Ion/off) of higher than 103 were also observed. Both resistance states could be maintained for a suitably long time (>104 s). Taking the results together, the present study reveals for the first time that chicken egg albumen is a promising material for nonvolatile memory applications.

Solution-processed Al-chelated gelatin for highly transparent non-volatile memory applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang, Yu-Chi; Wang, Yeong-Her, E-mail: yhw@ee.ncku.edu.tw

2015-03-23

Using the biomaterial of Al-chelated gelatin (ACG) prepared by sol-gel method in the ITO/ACG/ITO structure, a highly transparent resistive random access memory (RRAM) was obtained. The transmittance of the fabricated device is approximately 83% at 550 nm while that of Al/gelatin/ITO is opaque. As to the ITO/gelatin/ITO RRAM, no resistive switching behavior can be seen. The ITO/ACG/ITO RRAM shows high ON/OFF current ratio (>10{sup 5}), low operation voltage, good uniformity, and retention characteristics at room temperature and 85 °C. The mechanism of the ACG-based memory devices is presented. The enhancement of these electrical properties can be attributed to the chelate effect ofmore » Al ions with gelatin. Results show that transparent ACG-based memory devices possess the potential for next-generation resistive memories and bio-electronic applications.« less

Low-power, high-uniform, and forming-free resistive memory based on Mg-deficient amorphous MgO film with rough surface

NASA Astrophysics Data System (ADS)

Guo, Jiajun; Ren, Shuxia; Wu, Liqian; Kang, Xin; Chen, Wei; Zhao, Xu

2018-03-01

Saving energy and reducing operation parameter fluctuations remain crucial for enabling resistive random access memory (RRAM) to emerge as a universal memory. In this work, we report a resistive memory device based on an amorphous MgO (a-MgO) film that not only exhibits ultralow programming voltage (just 0.22 V) and low power consumption (less than 176.7 μW) but also shows excellent operative uniformity (the coefficient of variation is only 1.7% and 2.2% for SET and RESET voltage, respectively). Moreover, it also shows a forming-free characteristic. Further analysis indicates that these distinctive properties can be attributed to the unstable local structures and the rough surface of the Mg-deficient a-MgO film. These findings show the potential of using a-MgO in high-performance nonvolatile memory applications.

Interplanetary dust - Trace element analysis of individual particles by neutron activation

NASA Technical Reports Server (NTRS)

Ganapathy, R.; Brownlee, D. E.

1979-01-01

Although micrometeorites of cometary origin are thought to be the dominant component of interplanetary dust, it has never been possible to positively identify such micrometer-sized particles. Two such particles have been identified as definitely micrometeorites since their abundances of volatile and nonvolatile trace elements closely match those of primitive solar system material.

Study of Ag/RGO/ITO sandwich structure for resistive switching behavior deposited on plastic substrate

NASA Astrophysics Data System (ADS)

Vartak, Rajdeep; Rag, Adarsh; De, Shounak; Bhat, Somashekhara

2018-05-01

We report here the use of facile and environmentally benign way synthesized reduced graphene oxide (RGO) for low-voltage non-volatile memory device as charge storing element. The RGO solutions have been synthesized using electrochemical exfoliation of battery electrode. The solution processed based RGO solution is suitable for large area and low-cost processing on plastic substrate. Room-temperature current-voltage characterisation has been carried out in Ag/RGO/ITO PET sandwich configuration to study the type of trap distribution. It is observed that in the low-voltage sweep, ohmic current is the main mechanism of current flow and trap filled/assisted conduction is observed at high-sweep voltage region. The Ag/RGO/ITO PET sandwich structure showed bipolar resistive switching behavior. These mechanisms can be analyzed based on oxygen availability and vacancies in the RGO giving rise to continuous least resistive path (conductive) and high resistance path along the structure. An Ag/RGO/ITO arrangement demonstrates long retention time with low operating voltage, low set/reset voltage, good ON/OFF ratio of 103 (switching transition between lower resistance state and higher resistance state and decent switching performance. The RGO memory showed decent results with an almost negligible degradation in switching properties which can be used for low-voltage and low-cost advanced flexible electronics.

Highly conducting leakage-free electrolyte for SrCoOx-based non-volatile memory device

NASA Astrophysics Data System (ADS)

Katase, Takayoshi; Suzuki, Yuki; Ohta, Hiromichi

2017-10-01

The electrochemical switching of SrCoOx-based non-volatile memory with a thin-film-transistor structure was examined by using liquid-leakage-free electrolytes with different conductivities (σ) as the gate insulator. We first examined leakage-free water, which is incorporated in the amorphous (a-) 12CaO.7Al2O3 film with a nanoporous structure (Calcium Aluminate with Nanopore), but the electrochemical oxidation/reduction of the SrCoOx layer required the application of a high gate voltage (Vg) up to 20 V for a very long current-flowing-time (t) ˜40 min, primarily due to the low σ [2.0 × 10-8 S cm-1 at room temperature (RT)] of leakage-free water. We then controlled the σ of the leakage-free electrolyte, infiltrated in the a-NaxTaO3 film with a nanopillar array structure, from 8.0 × 10-8 S cm-1 to 2.5 × 10-6 S cm-1 at RT by changing the x = 0.01-1.0. As the result, the t, required for the metallization of the SrCoOx layer under small Vg = -3 V, becomes two orders of magnitude shorter with increase of the σ of the a-NaxTaO3 leakage-free electrolyte. These results indicate that the ion migration in the leakage-free electrolyte is the rate-determining step for the electrochemical switching, compared to the other electrochemical process, and the high σ of the leakage-free electrolyte is the key factor for the development of the non-volatile SrCoOx-based electro-magnetic phase switching device.

E-field induced resistive switch in metal/praseodymium calcium manganite interfaces: A model for future nonvolatile memory devices

NASA Astrophysics Data System (ADS)

Das, Nilanjan

Among the various candidates for non-volatile random access memory (RAM), interfacial resistive switch in Ag/Pr0.7Ca0.3 MnO3 (PCMO) configuration has drawn major attention in recent years due to its potential as a high storage density (˜ terabyte) device. However, the diverse nature of the resistive switch in different systems makes the development of a unifying model for its underlying physics very difficult. This dissertation will address both issues, namely, characterization of switches for device applications and development of a system-independent generic model, in detail. In our work, we have studied the properties electric pulse induced interfacial switch in electrode/PCMO system. A very fast speed ("write speed") of 100 ns, threshold ("programming voltage") as low as 2 V (for micro electrodes), and non-volatility ("data retention") of switched states have been achieved. A clear distinction between fast switch and sub-threshold slow quasistatic-dc switch has been made. Results obtained from time-dependence studies and impedance spectroscopy suggest that defect creation/annihilation, such as broken bonds (under very high field at interface, 107V/cm), is likely the mechanism for the sub-micros fast switching. On the other hand, slow accumulative process, such as electromigration of point defects, are responsible for the subthreshold quasi-dc switch. Scanning probe imaging has revealed the nanoscale inhomogeneity of the switched surfaces, essential for observing a resistive switch. Evolution of such structures has been observed under surface pre-training. Device scalability has been tested by creating reversible modification of surface conductivities with atomic force microscopy, thus creating the "nano-switch" (limited to a region of 10--100 nm).

Electric-field-controlled interface dipole modulation for Si-based memory devices.

PubMed

Miyata, Noriyuki

2018-05-31

Various nonvolatile memory devices have been investigated to replace Si-based flash memories or emulate synaptic plasticity for next-generation neuromorphic computing. A crucial criterion to achieve low-cost high-density memory chips is material compatibility with conventional Si technologies. In this paper, we propose and demonstrate a new memory concept, interface dipole modulation (IDM) memory. IDM can be integrated as a Si field-effect transistor (FET) based memory device. The first demonstration of this concept employed a HfO 2 /Si MOS capacitor where the interface monolayer (ML) TiO 2 functions as a dipole modulator. However, this configuration is unsuitable for Si-FET-based devices due to its large interface state density (D it ). Consequently, we propose, a multi-stacked amorphous HfO 2 /1-ML TiO 2 /SiO 2 IDM structure to realize a low D it and a wide memory window. Herein we describe the quasi-static and pulse response characteristics of multi-stacked IDM MOS capacitors and demonstrate flash-type and analog memory operations of an IDM FET device.

Resistive switching in TiO2 nanocolumn arrays electrochemically grown

NASA Astrophysics Data System (ADS)

Marik, M.; Mozalev, A.; Hubalek, J.; Bendova, M.

2017-04-01

Resistive switching in metal oxides, especially in TiO2, has been intensively investigated for potential application in non-volatile memory microdevices. As one of the working mechanisms, a conducting filament consisting of a substoichiometric oxide phase is created within the oxide layer. With the aim of investigating the filament formation in spatially confined elements, we fabricate arrays of self-ordered TiO2 nanocolumns by porous-anodic-alumina (PAA)-assisted anodizing, incorporate them into solid-state microdevices, study their electron transport properties, and reveal that this anodizing approach is suitable for growing TiO2 nanostructures exhibiting resistive switching. The electrical properties and resistive switching behavior are both dependent on the electrolytic formation conditions, influencing the concentration and distribution of oxygen vacancies in the nanocolumn material during the film growth. Therefore, the PAA-assisted TiO2 nanocolumn arrays can be considered as a platform for investigating various phenomena related to resistive switching in valve metal oxides at the nanoscale.

Spin-Transfer Studies in Magnetic Multilayer Nanostructures

NASA Astrophysics Data System (ADS)

Emley, N. C.; Albert, F. J.; Ryan, E. M.; Krivorotov, I. N.; Ralph, D. C.; Buhrman, R. A.

2003-03-01

Numerous experiments have demonstrated current-induced magnetization reversal in ferromagnet/paramagnet/ferromagnet nanostructures with the current in the CPP geometry. The primary mechanism for this reversal is the transfer of angular momentum from the spin-polarized conduction electrons to the nanomagnet moment the spin transfer effect. This phenomenon has potential application in nanoscale, current-controlled non-volatile memory elements, but several challenges must be overcome for realistic device implementation. Typical Co/Cu/Co nanopillar devices, although effective for fundamental studies, are not advantageous for technological applications because of their large switching currents Ic ( 3-10 mA) and small R·A (< 1 mΩ·µm^2). Here we report initial results testing some possible approaches for enhancing spin-transfer device performance which involve the addition of more layers, and hence, more complexity, to the simple Co/Cu/Co trilayer structure. These additions include synthetic antiferromagnet layers (SAF), exchange biased layers, nano-oxide layers (NOL), and additional magnetic layers. Research supported by NSF and DARPA

Room temperature ferroelectricity in one-dimensional single chain molecular magnets [{M(Δ)M(Λ)}(ox)2(phen)2]n (M = Fe and Mn)

NASA Astrophysics Data System (ADS)

Bhatt, Pramod; Mukadam, M. D.; Meena, S. S.; Mishra, S. K.; Mittal, R.; Sastry, P. U.; Mandal, B. P.; Yusuf, S. M.

2017-03-01

The ferroelectric materials are mainly focused on pure inorganic oxides; however, the organic molecule based materials have recently attracted great attention because of their multifunctional properties. The mixing of oxalate and phenanthroline ligands with metal ions (Fe or Mn) at room temperature followed by hydrothermal treatment results in the formation of one-dimensional single chain molecular magnets which exhibit room temperature dielectric and ferroelectric behavior. The compounds are chiral in nature, and exhibit a ferroelectric behavior, attributed to the polar point group C2, in which they crystallized. The compounds are also associated with a dielectric loss and thus a relaxation process. The observed electric dipole moment, essential for a ferroelectricity, has been understood quantitatively in terms of lattice distortions at two different lattice sites within the crystal structure. The studied single chain molecular magnetic materials with room temperature ferroelectric and dielectric properties could be of great technological importance in non-volatile memory elements, and high-performance insulators.

Thermoelectric La-doped SrTiO3 epitaxial layers with single-crystal quality: from nano to micrometers

PubMed Central

Apreutesei, Mihai; Debord, Régis; Bouras, Mohamed; Regreny, Philippe; Botella, Claude; Benamrouche, Aziz; Carretero-Genevrier, Adrian; Gazquez, Jaume; Grenet, Geneviève; Pailhès, Stéphane; Saint-Girons, Guillaume; Bachelet, Romain

2017-01-01

Abstract High-quality thermoelectric La0.2Sr0.8TiO3 (LSTO) films, with thicknesses ranging from 20 nm to 0.7 μm, have been epitaxially grown on SrTiO3(001) substrates by enhanced solid-source oxide molecular-beam epitaxy. All films are atomically flat (with rms roughness < 0.2 nm), with low mosaicity (<0.1°), and present very low electrical resistivity (<5 × 10−4 Ω cm at room temperature), one order of magnitude lower than standard commercial Nb-doped SrTiO3 single-crystalline substrate. The conservation of transport properties within this thickness range has been confirmed by thermoelectric measurements where Seebeck coefficients of approximately –60 μV/K have been recorded for all films. These LSTO films can be integrated on Si for non-volatile memory structures or opto-microelectronic devices, functioning as transparent conductors or thermoelectric elements. PMID:28740558

Thermoelectric La-doped SrTiO3 epitaxial layers with single-crystal quality: from nano to micrometers.

PubMed

Apreutesei, Mihai; Debord, Régis; Bouras, Mohamed; Regreny, Philippe; Botella, Claude; Benamrouche, Aziz; Carretero-Genevrier, Adrian; Gazquez, Jaume; Grenet, Geneviève; Pailhès, Stéphane; Saint-Girons, Guillaume; Bachelet, Romain

2017-01-01

High-quality thermoelectric La 0.2 Sr 0.8 TiO 3 (LSTO) films, with thicknesses ranging from 20 nm to 0.7 μm, have been epitaxially grown on SrTiO 3 (001) substrates by enhanced solid-source oxide molecular-beam epitaxy. All films are atomically flat (with rms roughness < 0.2 nm), with low mosaicity (<0.1°), and present very low electrical resistivity (<5 × 10 -4 Ω cm at room temperature), one order of magnitude lower than standard commercial Nb-doped SrTiO 3 single-crystalline substrate. The conservation of transport properties within this thickness range has been confirmed by thermoelectric measurements where Seebeck coefficients of approximately -60 μV/K have been recorded for all films. These LSTO films can be integrated on Si for non-volatile memory structures or opto-microelectronic devices, functioning as transparent conductors or thermoelectric elements.

Twin-bit via resistive random access memory in 16 nm FinFET logic technologies

NASA Astrophysics Data System (ADS)

Shih, Yi-Hong; Hsu, Meng-Yin; King, Ya-Chin; Lin, Chrong Jung

2018-04-01

A via resistive random access memory (RRAM) cell fully compatible with the standard CMOS logic process has been successfully demonstrated for high-density logic nonvolatile memory (NVM) modules in advanced FinFET circuits. In this new cell, the transition metal layers are formed on both sides of a via, given two storage bits per via. In addition to its compact cell area (1T + 14 nm × 32 nm), the twin-bit via RRAM cell features a low operation voltage, a large read window, good data retention, and excellent cycling capability. As fine alignments between mask layers become possible, the twin-bit via RRAM cell is expected to be highly scalable in advanced FinFET technology.

Nanocrystal floating gate memory with solution-processed indium-zinc-tin-oxide channel and colloidal silver nanocrystals

NASA Astrophysics Data System (ADS)

Hu, Quanli; Ha, Sang-Hyub; Lee, Hyun Ho; Yoon, Tae-Sik

2011-12-01

A nanocrystal (NC) floating gate memory with solution-processed indium-zinc-tin-oxide (IZTO) channel and silver (Ag) NCs embedded in thin gate dielectric layer (SiO2(30 nm)/Al2O3(3 nm)) was fabricated. Both the IZTO channel and colloidal Ag NC layers were prepared by spin-coating and subsequent annealing, and dip-coating process, respectively. A threshold voltage shift up to ~0.9 V, corresponding to the electron density of 6.5 × 1011 cm-2, at gate pulsing <=10 V was achieved by the charging of high density NCs. These results present the successful non-volatile memory characteristics of an oxide-semiconductor transistor fabricated through solution processes.

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

NASA Astrophysics Data System (ADS)

Sargentis, Ch.; Giannakopoulos, K.; Travlos, A.; Tsamakis, D.

2007-04-01

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO 2 layer and are then fully covered by a HfO 2 layer. The HfO 2 is a high- k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance-voltage and conductance-voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.

Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

PubMed

Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

2016-09-19

Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

NASA Astrophysics Data System (ADS)

Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

2016-10-01

The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

Fault-tolerant NAND-flash memory module for next-generation scientific instruments

NASA Astrophysics Data System (ADS)

Lange, Tobias; Michel, Holger; Fiethe, Björn; Michalik, Harald; Walter, Dietmar

2015-10-01

Remote sensing instruments on today's space missions deliver a high amount of data which is typically evaluated on ground. Especially for deep space missions the telemetry downlink is very limited which creates the need for the scientific evaluation and thereby a reduction of data volume already on-board the spacecraft. A demanding example is the Polarimetric and Helioseismic Imager (PHI) instrument on Solar Orbiter. To enable on-board offline processing for data reduction, the instrument has to be equipped with a high capacity memory module. The module is based on non-volatile NAND-Flash technology, which requires more advanced operation than volatile DRAM. Unlike classical mass memories, the module is integrated into the instrument and allows readback of data for processing. The architecture and safe operation of such kind of memory module is described in the following paper.

Carrier transport mechanisms of nonvolatile write-once-read-many-times memory devices with InP-ZnS core-shell nanoparticles embedded in a polymethyl methacrylate layer

NASA Astrophysics Data System (ADS)

Ham, Jung Hoon; Oh, Do Hyun; Cho, Sung Hwan; Jung, Jae Hun; Kim, Tae Whan; Ryu, Eui Dock; Kim, Sang Wook

2009-03-01

Current-voltage (I-V) curves at 300 K for Al/InP-ZnS nanoparticles embedded in a polymethyl methacrylate layer/Al devices showed electrical bistability for write-once-read-many-times (WORM) memory devices. From the I-V curves, the ON/OFF ratio for the device with InP-ZnS nanoparticles was significantly larger than that for the device without InP-ZnS nanoparticles, indicative of the existence of charge capture in the InP nanoparticles. The estimated retention time of the ON state for the WORM memory device was more than 10 years. The carrier transport mechanisms for the WORM memory devices are described by using several models to fit the experimental I-V data.

Ultra-fast three terminal perpendicular spin-orbit torque MRAM (Presentation Recording)

NASA Astrophysics Data System (ADS)

Boulle, Olivier; Cubukcu, Murat; Hamelin, Claire; Lamard, Nathalie; Buda-Prejbeanu, Liliana; Mikuszeit, Nikolai; Garello, Kevin; Gambardella, Pietro; Langer, Juergen; Ocker, Berthold; Miron, Mihai; Gaudin, Gilles

2015-09-01

The discovery that a current flowing in a heavy metal can exert a torque on a neighboring ferromagnet has opened a new way to manipulate the magnetization at the nanoscale. This "spin orbit torque" (SOT) has been demonstrated in ultrathin magnetic multilayers with structural inversion asymmetry (SIA) and high spin orbit coupling, such as Pt/Co/AlOx multilayers. We have shown that this torque can lead to the magnetization switching of a perpendicularly magnetized nanomagnet by an in-plane current injection. The manipulation of magnetization by SOT has led to a novel concept of magnetic RAM memory, the SOT-MRAM, which combines non volatility, high speed, reliability and large endurance. These features make the SOT-MRAM a good candidate to replace SRAM for non-volatile cache memory application. We will present the proof of concept of a perpendicular SOT-MRAM cell composed of a Ta/FeCoB/MgO/FeCoB magnetic tunnel junction and demonstrate ultra-fast (down to 300 ps) deterministic bipolar magnetization switching. Macrospin and micromagnetic simulations including SOT cannot reproduce the experimental results, which suggests that additional physical mechanisms are at stacks. Our results show that SOT-MRAM is fast, reliable and low power, which is promising for non-volatile cache memory application. We will also discuss recent experiments of magnetization reversal in ultrathin multilayers Pt/Co/AlOx by very short (<200 ps) current pulses. We will show that in this material, the Dzyaloshinskii-Moryia interaction plays a key role in the reversal process.

Nonvolatile memory characteristics of organic thin film transistors using poly(2-hydroxyethyl methacrylate)-based polymer multilayer dielectric

NASA Astrophysics Data System (ADS)

Chen, Ying-Chih; Su, Yan-Kuin; Yu, Hsin-Chieh; Huang, Chun-Yuan; Huang, Tsung-Syun

2011-10-01

A wide hysteresis width characteristic (memory window) was observed in the organic thin film transistors (OTFTs) using poly(2-hydroxyethyl methacrylate) (PHEMA)-based polymer multilayers. In this study, a strong memory effect was also found in the pentacene-based OTFTs and the electric characteristics were improved by introducing PHEMA/poly(methyl methacrylate) (PMMA)/PHEMA trilayer to replace the conventional PHEMA monolayer or PMMA/PHEMA and PHEMA/PMMA bilayer as the dielectric layers of OTFTs. The memory effect was originated from the electron trapping and slow polarization of the dielectrics. The hydroxyl (-OH) groups inside the polymer dielectric were the main charge storage sites of the electrons. This charge-storage phenomenon could lead to a wide flat-band voltage shift (memory window, △VFB = 22 V) which is essential for the OTFTs' memory-related applications. Moreover, the fabricated transistors also exhibited significant switchable channel current due to the charge-storage and slow charge relaxation.

Flexible and twistable non-volatile memory cell array with all-organic one diode-one resistor architecture.

PubMed

Ji, Yongsung; Zeigler, David F; Lee, Dong Su; Choi, Hyejung; Jen, Alex K-Y; Ko, Heung Cho; Kim, Tae-Wook

2013-01-01

Flexible organic memory devices are one of the integral components for future flexible organic electronics. However, high-density all-organic memory cell arrays on malleable substrates without cross-talk have not been demonstrated because of difficulties in their fabrication and relatively poor performances to date. Here we demonstrate the first flexible all-organic 64-bit memory cell array possessing one diode-one resistor architectures. Our all-organic one diode-one resistor cell exhibits excellent rewritable switching characteristics, even during and after harsh physical stresses. The write-read-erase-read output sequence of the cells perfectly correspond to the external pulse signal regardless of substrate deformation. The one diode-one resistor cell array is clearly addressed at the specified cells and encoded letters based on the standard ASCII character code. Our study on integrated organic memory cell arrays suggests that the all-organic one diode-one resistor cell architecture is suitable for high-density flexible organic memory applications in the future.

RESTOP: Retaining External Peripheral State in Intermittently-Powered Sensor Systems

PubMed Central

Rodriguez Arreola, Alberto; Balsamo, Domenico

2018-01-01

Energy harvesting sensor systems typically incorporate energy buffers (e.g., rechargeable batteries and supercapacitors) to accommodate fluctuations in supply. However, the presence of these elements limits the miniaturization of devices. In recent years, researchers have proposed a new paradigm, transient computing, where systems operate directly from the energy harvesting source and allow computation to span across power cycles, without adding energy buffers. Various transient computing approaches have addressed the challenge of power intermittency by retaining the processor’s state using non-volatile memory. However, no generic approach has yet been proposed to retain the state of peripherals external to the processing element. This paper proposes RESTOP, flexible middleware which retains the state of multiple external peripherals that are connected to a computing element (i.e., a microcontroller) through protocols such as SPI or I2C. RESTOP acts as an interface between the main application and the peripheral, which keeps a record, at run-time, of the transmitted data in order to restore peripheral configuration after a power interruption. RESTOP is practically implemented and validated using three digitally interfaced peripherals, successfully restoring their configuration after power interruptions, imposing a maximum time overhead of 15% when configuring a peripheral. However, this represents an overhead of only 0.82% during complete execution of our typical sensing application, which is substantially lower than existing approaches. PMID:29320441

Fabrication of cross-shaped Cu-nanowire resistive memory devices using a rapid, scalable, and designable inorganic-nanowire-digital-alignment technique (Conference Presentation)

NASA Astrophysics Data System (ADS)

Xu, Wentao; Lee, Yeongjun; Min, Sung-Yong; Park, Cheolmin; Lee, Tae-Woo

2016-09-01

Resistive random-access memory (RRAM) is a candidate next generation nonvolatile memory due to its high access speed, high density and ease of fabrication. Especially, cross-point-access allows cross-bar arrays that lead to high-density cells in a two-dimensional planar structure. Use of such designs could be compatible with the aggressive scaling down of memory devices, but existing methods such as optical or e-beam lithographic approaches are too complicated. One-dimensional inorganic nanowires (i-NWs) are regarded as ideal components of nanoelectronics to circumvent the limitations of conventional lithographic approaches. However, post-growth alignment of these i-NWs precisely on a large area with individual control is still a difficult challenge. Here, we report a simple, inexpensive, and rapid method to fabricate two-dimensional arrays of perpendicularly-aligned, individually-conductive Cu-NWs with a nanometer-scale CuxO layer sandwiched at each cross point, by using an inorganic-nanowire-digital-alignment technique (INDAT) and a one-step reduction process. In this approach, the oxide layer is self-formed and patterned, so conventional deposition and lithography are not necessary. INDAT eliminates the difficulties of alignment and scalable fabrication that are encountered when using currently-available techniques that use inorganic nanowires. This simple process facilitates fabrication of cross-point nonvolatile memristor arrays. Fabricated arrays had reproducible resistive switching behavior, high on/off current ratio (Ion/Ioff) 10 6 and extensive cycling endurance. This is the first report of memristors with the resistive switching oxide layer self-formed, self-patterned and self-positioned; we envision that the new features of the technique will provide great opportunities for future nano-electronic circuits.

Ultra-Wideband Multi-Dye-Sensitized Upconverting Nanoparticles for Information Security Application.

PubMed

Lee, Jongha; Yoo, Byeongjun; Lee, Hakyong; Cha, Gi Doo; Lee, Hee-Su; Cho, Youngho; Kim, Sang Yeon; Seo, Hyunseon; Lee, Woongchan; Son, Donghee; Kang, Myungjoo; Kim, Hyung Min; Park, Yong Il; Hyeon, Taeghwan; Kim, Dae-Hyeong

2017-01-01

Multi-dye-sensitized upconverting nanoparticles (UCNPs), which harvest photons of wide wavelength range (450-975 nm) are designed and synthesized. The UCNPs embedded in a photo-acid generating layer are integrated on destructible nonvolatile resistive memory device. Upon illumination of light, the system permanently erases stored data, achieving enhanced information security. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

White-light-controlled resistive switching in ZnO/BaTiO3/C multilayer layer at room temperature

NASA Astrophysics Data System (ADS)

Wang, Junshuai; Liang, Dandan; Wu, Liangchen; Li, Xiaoping; Chen, Peng

2018-07-01

The bipolar resistance switching effect is observed in ZnO/BaTiO3/C structure. The resistance switching behavior can be modulated by white light. The resistance switch states and threshold voltage can be changed when subjected to white light. This research can help explore multi-functional materials and applications in nonvolatile memory device.

Hydraulic Universal Display Processor System (HUDPS).

DTIC Science & Technology

1981-11-21

emphasis on smart alphanumeric devices in Task II. Volatile and non-volatile memory components were utilized along with the Intel 8748 microprocessor...system. 1.2 TASK 11 Fault display methods for ground support personnel were investigated during Phase II with emphasis on smart alphanumeric devices...CONSIDERATIONS Methods of display fault indication for ground support personnel have been investigated with emphasis on " smart " alphanumeric devices

Oxide Structure Dependence of SiO2/SiOx/3C-SiC/n-Type Si Nonvolatile Resistive Memory on Memory Operation Characteristics

NASA Astrophysics Data System (ADS)

Yamaguchi, Yuichiro; Shouji, Masatsugu; Suda, Yoshiyuki

2012-11-01

We have investigated the dependence of the oxide layer structure of our previously proposed metal/SiO2/SiOx/3C-SiC/n-Si/metal metal-insulator-semiconductor (MIS) resistive memory device on the memory operation characteristics. The current-voltage (I-V) measurement and X-ray photoemission spectroscopy results suggest that SiOx defect states mainly caused by the oxidation of 3C-SiC at temperatures below 1000 °C are related to the hysteresis memory behavior in the I-V curve. By restricting the SiOx interface region, the number of switching cycles and the on/off current ratio are more enhanced. Compared with a memory device formed by one-step or two-step oxidation of 3C-SiC, a memory device formed by one-step oxidation of Si/3C-SiC exhibits a more restrictive SiOx interface with a more definitive SiO2 layer and higher memory performances for both the endurance switching cycle and on/off current ratio.

Realisation of all 16 Boolean logic functions in a single magnetoresistance memory cell

NASA Astrophysics Data System (ADS)

Gao, Shuang; Yang, Guang; Cui, Bin; Wang, Shouguo; Zeng, Fei; Song, Cheng; Pan, Feng

2016-06-01

Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future.Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr03169b

Eliminating Overerase Behavior by Designing Energy Band in High-Speed Charge-Trap Memory Based on WSe2.

PubMed

Liu, Chunsen; Yan, Xiao; Wang, Jianlu; Ding, Shijin; Zhou, Peng; Zhang, David Wei

2017-05-01

Atomic crystal charge trap memory, as a new concept of nonvolatile memory, possesses an atomic level flatness interface, which makes them promising candidates for replacing conventional FLASH memory in the future. Here, a 2D material WSe 2 and a 3D Al 2 O 3 /HfO 2 /Al 2 O 3 charge-trap stack are combined to form a charge-trap memory device with a separation of control gate and memory stack. In this device, the charges are erased/written by built-in electric field, which significantly enhances the write speed to 1 µs. More importantly, owing to the elaborate design of the energy band structure, the memory only captures electrons with a large electron memory window over 20 V and trap selectivity about 13, both of them are the state-of-the-art values ever reported in FLASH memory based on 2D materials. Therefore, it is demonstrated that high-performance charge trap memory based on WSe 2 without the fatal overerase issue in conventional FLASH memory can be realized to practical application. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Electrical Switching of Perovskite Thin-Film Resistors

NASA Technical Reports Server (NTRS)

Liu, Shangqing; Wu, Juan; Ignatiev, Alex

2010-01-01

Electronic devices that exploit electrical switching of physical properties of thin films of perovskite materials (especially colossal magnetoresistive materials) have been invented. Unlike some related prior devices, these devices function at room temperature and do not depend on externally applied magnetic fields. Devices of this type can be designed to function as sensors (exhibiting varying electrical resistance in response to varying temperature, magnetic field, electric field, and/or mechanical pressure) and as elements of electronic memories. The underlying principle is that the application of one or more short electrical pulse(s) can induce a reversible, irreversible, or partly reversible change in the electrical, thermal, mechanical, and magnetic properties of a thin perovskite film. The energy in the pulse must be large enough to induce the desired change but not so large as to destroy the film. Depending on the requirements of a specific application, the pulse(s) can have any of a large variety of waveforms (e.g., square, triangular, or sine) and be of positive, negative, or alternating polarity. In some applications, it could be necessary to use multiple pulses to induce successive incremental physical changes. In one class of applications, electrical pulses of suitable shapes, sizes, and polarities are applied to vary the detection sensitivities of sensors. Another class of applications arises in electronic circuits in which certain resistance values are required to be variable: Incorporating the affected resistors into devices of the present type makes it possible to control their resistances electrically over wide ranges, and the lifetimes of electrically variable resistors exceed those of conventional mechanically variable resistors. Another and potentially the most important class of applications is that of resistance-based nonvolatile-memory devices, such as a resistance random access memory (RRAM) described in the immediately following article, Electrically Variable Resistive Memory Devices (MFS-32511-1).

Investigation of the environmental implications of the CNT switch through its life cycle

NASA Astrophysics Data System (ADS)

Dahlben, Lindsay Johanna

Carbon nanotubes (CNTs) are unique allotropes of carbon that have high tensile strength, a high Young's modulus, good thermal conductivity, and depending on the CNT chirality can be metallic or semiconducting. These mechanical, thermal, and electrical properties make CNTs an attractive element in electronic applications such as conductive films, photovoltaics, non-volatile memory devices, batteries, sensors, and displays. Although commercialization of CNT-enabled products is increasing, there remains a significant lack of information regarding the health effects and environmental impacts of CNTs. Some studies have even shown that the behavior, toxicity, and persistence of CNTs may differ from bulk heterogeneous carbon. Given these uncertainties, it is prudent to assess the environmental attributes of CNT products and processes now to discover and potentially prevent adverse effects. This study investigates the environmental implications of a non-volatile bi-stable electromechanical CNT switch through its life cycle. Life cycle assessment (LCA) methodology is used to track the environmental impacts of the CNT switch through its fabrication and expected use and end-of-life (EOL) stages. Process parameters, energy consumption, input materials, output emissions, and yield efficiencies are determined for the laboratory and full-scale manufacture environments. The Ecoinvent(TM) inventory database and Eco-indicator 1999(TM) method are utilized for the impact assessment. Results for the fabrication stage are reported for highest contributions to environmental impact such as airborne inorganics, land use, and fossil fuels due to Au refining processes and electricity consumption. Extension of the LCA scope is evaluated for the potential replacement of CNT switches to current field-effect transistors (FETs) in flash memory for a cellular phone application. First-order predictions are made for the functionality and performance of the CNT switch during the use stage through an environmental perspective. Existing cellular phone EOL management options including recycling and direct disposal to landfill and incineration are evaluated for potential limitations, concerns, and environmental releases that may occur from the assimilation of CNT switch-enabled phones into the waste stream. In this manner, potential environmental effects of the CNT switch throughout its life cycle stages can be addressed alongside its technological development to ensure safe, sustainable, and successful CNT products.

Interface engineered ferrite@ferroelectric core-shell nanostructures: A facile approach to impart superior magneto-electric coupling

NASA Astrophysics Data System (ADS)

Abraham, Ann Rose; Raneesh, B.; Das, Dipankar; Oluwafemi, Oluwatobi Samuel; Thomas, Sabu; Kalarikkal, Nandakumar

2018-04-01

The electric field control of magnetism in multiferroics is attractive for the realization of ultra-fast and miniaturized low power device applications like nonvolatile memories. Room temperature hybrid multiferroic heterostructures with core-shell (0-0) architecture (ferrite core and ferroelectric shell) were developed via a two-step method. High-Resolution Transmission Electron Microscopy (HRTEM) images confirm the core-shell structure. The temperature dependant magnetization measurements and Mossbauer spectra reveal superparamagnetic nature of the core-shell sample. The ferroelectric hysteresis loops reveal leaky nature of the samples. The results indicate the promising applications of the samples for magneto-electric memories and spintronics.

Inadvertently programmed bits in Samsung 128 Mbit flash devices: a flaky investigation

NASA Technical Reports Server (NTRS)

Swift, G.

2002-01-01

JPL's X2000 avionics design pioneers new territory by specifying a non-volatile memory (NVM) board based on flash memories. The Samsung 128Mb device chosen was found to demonstrate bit errors (mostly program disturbs) and block-erase failures that increase with cycling. Low temperature, certain pseudo- random patterns, and, probably, higher bias increase the observable bit errors. An experiment was conducted to determine the wearout dependence of the bit errors to 100k cycles at cold temperature using flight-lot devices (some pre-irradiated). The results show an exponential growth rate, a wide part-to-part variation, and some annealing behavior.

Systems and methods for rapid processing and storage of data

DOEpatents

Stalzer, Mark A.

2017-01-24

Systems and methods of building massively parallel computing systems using low power computing complexes in accordance with embodiments of the invention are disclosed. A massively parallel computing system in accordance with one embodiment of the invention includes at least one Solid State Blade configured to communicate via a high performance network fabric. In addition, each Solid State Blade includes a processor configured to communicate with a plurality of low power computing complexes interconnected by a router, and each low power computing complex includes at least one general processing core, an accelerator, an I/O interface, and cache memory and is configured to communicate with non-volatile solid state memory.

Face classification using electronic synapses

NASA Astrophysics Data System (ADS)

Yao, Peng; Wu, Huaqiang; Gao, Bin; Eryilmaz, Sukru Burc; Huang, Xueyao; Zhang, Wenqiang; Zhang, Qingtian; Deng, Ning; Shi, Luping; Wong, H.-S. Philip; Qian, He

2017-05-01

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system.

A Trustworthy Key Generation Prototype Based on DDR3 PUF for Wireless Sensor Networks

PubMed Central

Liu, Wenchao; Zhang, Zhenhua; Li, Miaoxin; Liu, Zhenglin

2014-01-01

Secret key leakage in wireless sensor networks (WSNs) is a high security risk especially when sensor nodes are deployed in hostile environment and physically accessible to attackers. With nowadays semi/fully-invasive attack techniques attackers can directly derive the cryptographic key from non-volatile memory (NVM) storage. Physically Unclonable Function (PUF) is a promising technology to resist node capture attacks, and it also provides a low cost and tamper-resistant key provisioning solution. In this paper, we designed a PUF based on double-data-rate SDRAM Type 3 (DDR3) memory by exploring its memory decay characteristics. We also described a prototype of 128-bit key generation based on DDR3 PUF with integrated fuzzy extractor. Due to the wide adoption of DDR3 memory in WSN, our proposed DDR3 PUF technology with high security levels and no required hardware changes is suitable for a wide range of WSN applications. PMID:24984058

Device and methods for writing and erasing analog information in small memory units via voltage pulses

DOEpatents

El Gabaly Marquez, Farid; Talin, Albert Alec

2018-04-17

Devices and methods for non-volatile analog data storage are described herein. In an exemplary embodiment, an analog memory device comprises a potential-carrier source layer, a barrier layer deposited on the source layer, and at least two storage layers deposited on the barrier layer. The memory device can be prepared to write and read data via application of a biasing voltage between the source layer and the storage layers, wherein the biasing voltage causes potential-carriers to migrate into the storage layers. After initialization, data can be written to the memory device by application of a voltage pulse between two storage layers that causes potential-carriers to migrate from one storage layer to another. A difference in concentration of potential carriers caused by migration of potential-carriers between the storage layers results in a voltage that can be measured in order to read the written data.

Face classification using electronic synapses.

PubMed

Yao, Peng; Wu, Huaqiang; Gao, Bin; Eryilmaz, Sukru Burc; Huang, Xueyao; Zhang, Wenqiang; Zhang, Qingtian; Deng, Ning; Shi, Luping; Wong, H-S Philip; Qian, He

2017-05-12

Conventional hardware platforms consume huge amount of energy for cognitive learning due to the data movement between the processor and the off-chip memory. Brain-inspired device technologies using analogue weight storage allow to complete cognitive tasks more efficiently. Here we present an analogue non-volatile resistive memory (an electronic synapse) with foundry friendly materials. The device shows bidirectional continuous weight modulation behaviour. Grey-scale face classification is experimentally demonstrated using an integrated 1024-cell array with parallel online training. The energy consumption within the analogue synapses for each iteration is 1,000 × (20 ×) lower compared to an implementation using Intel Xeon Phi processor with off-chip memory (with hypothetical on-chip digital resistive random access memory). The accuracy on test sets is close to the result using a central processing unit. These experimental results consolidate the feasibility of analogue synaptic array and pave the way toward building an energy efficient and large-scale neuromorphic system.

Enabling universal memory by overcoming the contradictory speed and stability nature of phase-change materials.

PubMed

Wang, Weijie; Loke, Desmond; Shi, Luping; Zhao, Rong; Yang, Hongxin; Law, Leong-Tat; Ng, Lung-Tat; Lim, Kian-Guan; Yeo, Yee-Chia; Chong, Tow-Chong; Lacaita, Andrea L

2012-01-01

The quest for universal memory is driving the rapid development of memories with superior all-round capabilities in non-volatility, high speed, high endurance and low power. Phase-change materials are highly promising in this respect. However, their contradictory speed and stability properties present a key challenge towards this ambition. We reveal that as the device size decreases, the phase-change mechanism changes from the material inherent crystallization mechanism (either nucleation- or growth-dominated), to the hetero-crystallization mechanism, which resulted in a significant increase in PCRAM speeds. Reducing the grain size can further increase the speed of phase-change. Such grain size effect on speed becomes increasingly significant at smaller device sizes. Together with the nano-thermal and electrical effects, fast phase-change, good stability and high endurance can be achieved. These findings lead to a feasible solution to achieve a universal memory.

Enabling Universal Memory by Overcoming the Contradictory Speed and Stability Nature of Phase-Change Materials

PubMed Central

Wang, Weijie; Loke, Desmond; Shi, Luping; Zhao, Rong; Yang, Hongxin; Law, Leong-Tat; Ng, Lung-Tat; Lim, Kian-Guan; Yeo, Yee-Chia; Chong, Tow-Chong; Lacaita, Andrea L.

2012-01-01

The quest for universal memory is driving the rapid development of memories with superior all-round capabilities in non-volatility, high speed, high endurance and low power. Phase-change materials are highly promising in this respect. However, their contradictory speed and stability properties present a key challenge towards this ambition. We reveal that as the device size decreases, the phase-change mechanism changes from the material inherent crystallization mechanism (either nucleation- or growth-dominated), to the hetero-crystallization mechanism, which resulted in a significant increase in PCRAM speeds. Reducing the grain size can further increase the speed of phase-change. Such grain size effect on speed becomes increasingly significant at smaller device sizes. Together with the nano-thermal and electrical effects, fast phase-change, good stability and high endurance can be achieved. These findings lead to a feasible solution to achieve a universal memory. PMID:22496956

Oxygen plasma immersion ion implantation treatment to enhance data retention of tungsten nanocrystal nonvolatile memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Jer-Chyi, E-mail: jcwang@mail.cgu.edu.tw; Chang, Wei-Cheng; Lai, Chao-Sung, E-mail: cslai@mail.cgu.edu.tw

Data retention characteristics of tungsten nanocrystal (W-NC) memory devices using an oxygen plasma immersion ion implantation (PIII) treatment are investigated. With an increase of oxygen PIII bias voltage and treatment time, the capacitance–voltage hysteresis memory window is increased but the data retention characteristics become degraded. High-resolution transmission electron microscopy images show that this poor data retention is a result of plasma damage on the tunneling oxide layer, which can be prevented by lowering the bias voltage to 7 kV. In addition, by using the elevated temperature retention measurement technique, the effective charge trapping level of the WO{sub 3} film surrounding themore » W-NCs can be extracted. This measurement reveals that a higher oxygen PIII bias voltage and treatment time induces more shallow traps within the WO{sub 3} film, degrading the retention behavior of the W-NC memory.« less

Recent trends in hardware security exploiting hybrid CMOS-resistive memory circuits

NASA Astrophysics Data System (ADS)

Sahay, Shubham; Suri, Manan

2017-12-01

This paper provides a comprehensive review and insight of recent trends in the field of random number generator (RNG) and physically unclonable function (PUF) circuits implemented using different types of emerging resistive non-volatile (NVM) memory devices. We present a detailed review of hybrid RNG/PUF implementations based on the use of (i) Spin-Transfer Torque (STT-MRAM), and (ii) metal-oxide based (OxRAM), NVM devices. Various approaches on Hybrid CMOS-NVM RNG/PUF circuits are considered, followed by a discussion on different nanoscale device phenomena. Certain nanoscale device phenomena (variability/stochasticity etc), which are otherwise undesirable for reliable memory and storage applications, form the basis for low power and highly scalable RNG/PUF circuits. Detailed qualitative comparison and benchmarking of all implementations is performed.

Electrically-controlled nonlinear switching and multi-level storage characteristics in WOx film-based memory cells

NASA Astrophysics Data System (ADS)

Duan, W. J.; Wang, J. B.; Zhong, X. L.

2018-05-01

Resistive switching random access memory (RRAM) is considered as a promising candidate for the next generation memory due to its scalability, high integration density and non-volatile storage characteristics. Here, the multiple electrical characteristics in Pt/WOx/Pt cells are investigated. Both of the nonlinear switching and multi-level storage can be achieved by setting different compliance current in the same cell. The correlations among the current, time and temperature are analyzed by using contours and 3D surfaces. The switching mechanism is explained in terms of the formation and rupture of conductive filament which is related to oxygen vacancies. The experimental results show that the non-stoichiometric WOx film-based device offers a feasible way for the applications of oxide-based RRAMs.

The role of EEPROM devices in upcoming ISDN applications

NASA Astrophysics Data System (ADS)

Nette, Herbert L.

1991-02-01

Integrated Services Digital Network (ISDN) equipments are rapidly becoming a major market for semiconductor chips. Although at first glance this growing market appears to be geared at logic chips, nonvolatile memories represent important support chips and will become a significant segment of this market. Challenges in these applications consist in operating EEPROMs at lower voltages and lower power and embedding them on ever more complex communications processor chips.

A CCD Monolithic LMS Adaptive Analog Signal Processor Integrated Circuit.

DTIC Science & Technology

1980-03-01

adaptive filter with electrically- reprogrammable MOS analog conductance weights. I The analog and digital peripheral MOS on-chip circuits are provided with...electrically reprogrammable analog weights at tap positions along a CCD analog delay line in order to form a basic linear combiner for adaptive filtering...electrically reprogrammable analog conductance weights was introduced with the use of non-volatile MNOS memory 6-7 transistors biased in their triode

Ferroelectric behavior and reproducible Bi-stable resistance switching property in K-doped ZnO thin films as candidate for application in non-volatile memories

NASA Astrophysics Data System (ADS)

Lee, J. W.; Subramaniam, N. G.; Kang, T. W.; Shon, Yoon; Kim, E. K.

2015-05-01

Potassium-doped ZnO thin films electrodeposited on indium tin oxide (ITO) coated glass substrates exhibited ferroelectric behavior with a remnant polarization of 0.2 μC/cm2. Especially, wave forms showing the applied input voltage Vi and output voltage Vo were obtained for Al/ZnO:K/ITO structure. It exhibits a superposition of Vi (input) and Vo (output) signal from Al/ZnO:K/ITO structure with a clear phase shift between the two wave forms which again confirms that the observed ferroelectric hysteresis curve is not related to leaky dielectric materials. The current-voltage characteristics of Al/ZnO:K/ITO structures measured for several cycles revealed bi-stable switching characteristics. The reproducible bi-stable switching characteristics for the mentioned structures had good retention in one particular resistance state. Around one order of switching was realized between low and high resistance states. The switching property thought to be polarization induced originating out from the ferroelectric properties of the potassium doped ZnO thin film. The switching between ZnO:K/ITO interface is assumed to be critical for stability in switching for several cycles. Possible application of this structure in non-volatile memories is explored.

Nonvolatile Memory Materials for Neuromorphic Intelligent Machines.

PubMed

Jeong, Doo Seok; Hwang, Cheol Seong

2018-04-18

Recent progress in deep learning extends the capability of artificial intelligence to various practical tasks, making the deep neural network (DNN) an extremely versatile hypothesis. While such DNN is virtually built on contemporary data centers of the von Neumann architecture, physical (in part) DNN of non-von Neumann architecture, also known as neuromorphic computing, can remarkably improve learning and inference efficiency. Particularly, resistance-based nonvolatile random access memory (NVRAM) highlights its handy and efficient application to the multiply-accumulate (MAC) operation in an analog manner. Here, an overview is given of the available types of resistance-based NVRAMs and their technological maturity from the material- and device-points of view. Examples within the strategy are subsequently addressed in comparison with their benchmarks (virtual DNN in deep learning). A spiking neural network (SNN) is another type of neural network that is more biologically plausible than the DNN. The successful incorporation of resistance-based NVRAM in SNN-based neuromorphic computing offers an efficient solution to the MAC operation and spike timing-based learning in nature. This strategy is exemplified from a material perspective. Intelligent machines are categorized according to their architecture and learning type. Also, the functionality and usefulness of NVRAM-based neuromorphic computing are addressed. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Resistive Switching in All-Printed, Flexible and Hybrid MoS2-PVA Nanocomposite based Memristive Device Fabricated by Reverse Offset

PubMed Central

Rehman, Muhammad Muqeet; Siddiqui, Ghayas Uddin; Gul, Jahan Zeb; Kim, Soo-Wan; Lim, Jong Hwan; Choi, Kyung Hyun

2016-01-01

Owing to the increasing interest in the nonvolatile memory devices, resistive switching based on hybrid nanocomposite of a 2D material, molybdenum disulphide (MoS2) and polyvinyl alcohol (PVA) is explored in this work. As a proof of concept, we have demonstrated the fabrication of a memory device with the configuration of PET/Ag/MoS2-PVA/Ag via an all printed, hybrid, and state of the art fabrication approach. Bottom Ag electrodes, active layer of hybrid MoS2-PVA nanocomposite and top Ag electrode are deposited by reverse offset, electrohydrodynamic (EHD) atomization and electrohydrodynamic (EHD) patterning respectively. The fabricated device displayed characteristic bistable, nonvolatile and rewritable resistive switching behavior at a low operating voltage. A decent off/on ratio, high retention time, and large endurance of 1.28 × 102, 105 sec and 1000 voltage sweeps were recorded respectively. Double logarithmic curve satisfy the trap controlled space charge limited current (TCSCLC) model in high resistance state (HRS) and ohmic model in low resistance state (LRS). Bendability test at various bending diameters (50-2 mm) for 1500 cycles was carried out to show the mechanical robustness of fabricated device. PMID:27811977

Polarization-coupled tunable resistive behavior in oxide ferroelectric heterostructures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gruverman, Alexei; Tsymbal, Evgeny Y.; Eom, Chang-Beom

2017-05-03

This research focuses on investigation of the physical mechanism of the electrically and mechanically tunable resistive behavior in oxide ferroelectric heterostructures with engineered interfaces realized via a strong coupling of ferroelectric polarization with tunneling electroresistance and metal-insulator (M-I) transitions. This report describes observation of electrically conductive domain walls in semiconducting ferroelectrics, voltage-free control of resistive switching and demonstration of a new mechanism of electrical control of 2D electron gas (2DEG) at oxide interfaces. The research goals are achieved by creating strong synergy between cutting-edge fabrication of epitaxial single-crystalline complex oxides, nanoscale electrical characterization by scanning probe microscopy and theoretical modelingmore » of the observed phenomena. The concept of the ferroelectric devices with electrically and mechanically tunable nonvolatile resistance represents a new paradigm shift in realization of the next-generation of non-volatile memory devices and low-power logic switches.« less

Investigation of the non-volatile resistance change in noncentrosymmetric compounds

PubMed Central

Herng, T. S.; Kumar, A.; Ong, C. S.; Feng, Y. P.; Lu, Y. H.; Zeng, K. Y.; Ding, J.

2012-01-01

Coexistence of polarization and resistance-switching characteristics in single compounds has been long inspired scientific and technological interests. Here, we report the non-volatile resistance change in noncentrosymmetric compounds investigated by using defect nanotechnology and contact engineering. Using a noncentrosymmetric material of ZnO as example, we first transformed ZnO into high resistance state. Then ZnO electrical polarization was probed and its domains polarized 180° along the [001]-axis with long-lasting memory effect (>25 hours). Based on our experimental observations, we have developed a vacancy-mediated pseudoferroelectricity model. Our first-principle calculations propose that vacancy defects initiate a spontaneous inverted domains nucleation at grain boundaries, and then they grow in the presence of an electrical field. The propagation of inverted domains follows the scanning tip motion under applied electrical field, leading to the growth of polarized domains over large areas. PMID:22905318

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S; Li, Dong

Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large increase in the size of on-chip caches. Since SRAM has low density and consumes large amount of leakage power, its use in designing on-chip caches has become more challenging. To address this issue, researchers are exploring the use of several emerging memory technologies, such as embedded DRAM, spin transfer torque RAM, resistive RAM, phase change RAM and domain wall memory. In this paper, we survey the architectural approaches proposed for designing memory systems and, specifically, caches with these emerging memory technologies. To highlight theirmore » similarities and differences, we present a classification of these technologies and architectural approaches based on their key characteristics. We also briefly summarize the challenges in using these technologies for architecting caches. We believe that this survey will help the readers gain insights into the emerging memory device technologies, and their potential use in designing future computing systems.« less

Electrochromic conductive polymer fuses for hybrid organic/inorganic semiconductor memories

NASA Astrophysics Data System (ADS)

Möller, Sven; Forrest, Stephen R.; Perlov, Craig; Jackson, Warren; Taussig, Carl

2003-12-01

We demonstrate a nonvolatile, write-once-read-many-times (WORM) memory device employing a hybrid organic/inorganic semiconductor architecture consisting of thin film p-i-n silicon diode on a stainless steel substrate integrated in series with a conductive polymer fuse. The nonlinearity of the silicon diodes enables a passive matrix memory architecture, while the conductive polyethylenedioxythiophene:polystyrene sulfonic acid polymer serves as a reliable switch with fuse-like behavior for data storage. The polymer can be switched at ˜2 μs, resulting in a permanent decrease of conductivity of the memory pixel by up to a factor of 103. The switching mechanism is primarily due to a current and thermally dependent redox reaction in the polymer, limited by the double injection of both holes and electrons. The switched device performance does not degrade after many thousand read cycles in ambient at room temperature. Our results suggest that low cost, organic/inorganic WORM memories are feasible for light weight, high density, robust, and fast archival storage applications.

Demonstration of the Potential of Magnetic Tunnel Junctions for a Universal RAM Technology

NASA Astrophysics Data System (ADS)

Gallagher, William J.

2000-03-01

Over the past four years, tunnel junctions with magnetic electrodes have emerged as promising devices for future magnetoresistive sensing and for information storage. This talk will review advances in these devices, focusing particularly on the use of magnetic tunnel junctions for magnetic random access memory (MRAM). Exchange-biased versions of magnetic tunnel junctions (MTJs) in particular will be shown to have useful properties for forming magnetic memory storage elements in a novel cross-point architecture. Exchange-biased MTJ elements have been made with areas as small as 0.1 square microns and have shown magnetoresistance values exceeding 40 The potential of exchange-biased MTJs for MRAM has been most seriously explored in a demonstration experiment involving the integration of 0.25 micron CMOS technology with a special magnetic tunnel junction "back end." The magnetic back end is based upon multi-layer magnetic tunnel junction growth technology which was developed using research-scale equipment and one-inch size substrates. For the demonstration, the CMOS wafers processed through two metal layers were cut into one-inch squares for depositions of bottom-pinned exchange-biased magnetic tunnel junctions. The samples were then processed through four additional lithographic levels to complete the circuits. The demonstration focused attention on a number of processing and device issues that were addressed successfully enough that key performance aspects of MTJ MRAM were demonstrated in 1 K bit arrays, including reads and writes in less than 10 ns and nonvolatility. While other key issues remain to be addressed, these results suggest that MTJ MRAM might simultaneously provide much of the functionality now provided separately by SRAM, DRAM, and NVRAM.

Theoretical potential for low energy consumption phase change memory utilizing electrostatically-induced structural phase transitions in 2D materials

NASA Astrophysics Data System (ADS)

Rehn, Daniel A.; Li, Yao; Pop, Eric; Reed, Evan J.

2018-01-01

Structural phase-change materials are of great importance for applications in information storage devices. Thermally driven structural phase transitions are employed in phase-change memory to achieve lower programming voltages and potentially lower energy consumption than mainstream nonvolatile memory technologies. However, the waste heat generated by such thermal mechanisms is often not optimized, and could present a limiting factor to widespread use. The potential for electrostatically driven structural phase transitions has recently been predicted and subsequently reported in some two-dimensional materials, providing an athermal mechanism to dynamically control properties of these materials in a nonvolatile fashion while achieving potentially lower energy consumption. In this work, we employ DFT-based calculations to make theoretical comparisons of the energy required to drive electrostatically-induced and thermally-induced phase transitions. Determining theoretical limits in monolayer MoTe2 and thin films of Ge2Sb2Te5, we find that the energy consumption per unit volume of the electrostatically driven phase transition in monolayer MoTe2 at room temperature is 9% of the adiabatic lower limit of the thermally driven phase transition in Ge2Sb2Te5. Furthermore, experimentally reported phase change energy consumption of Ge2Sb2Te5 is 100-10,000 times larger than the adiabatic lower limit due to waste heat flow out of the material, leaving the possibility for energy consumption in monolayer MoTe2-based devices to be orders of magnitude smaller than Ge2Sb2Te5-based devices.

On volatile element trends in gas-rich meteorites

NASA Technical Reports Server (NTRS)

Bart, G.; Lipschutz, M. E.

1979-01-01

Ten volatile elements (and non-volatile Co) in co-existing light and dark portions of 5 gas-rich chondrites were studied. Patterns of distinct but non-uniform enrichment by dark admixing material are revealed. The dark admixing material is enriched in Cs; Bi and Tl covary in it. It is compositionally unique from known types of primitive materials and is apparently not derived by secondary processes from such materials.

Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Che, Yongli; Zhang, Yating, E-mail: yating@tju.edu.cn; Song, Xiaoxian

2016-07-04

Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV{sub th} ∼ 15 V) and a long retention time (>10{sup 5 }s). The magnitude of ΔV{sub th} depended on both P/E voltages and the bias voltage (V{sub DS}): ΔV{sub th}more » was a cubic function to V{sub P/E} and linearly depended on V{sub DS}. Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.« less

A study of the switching mechanism and electrode material of fully CMOS compatible tungsten oxide ReRAM

NASA Astrophysics Data System (ADS)

Chien, W. C.; Chen, Y. C.; Lai, E. K.; Lee, F. M.; Lin, Y. Y.; Chuang, Alfred T. H.; Chang, K. P.; Yao, Y. D.; Chou, T. H.; Lin, H. M.; Lee, M. H.; Shih, Y. H.; Hsieh, K. Y.; Lu, Chih-Yuan

2011-03-01

Tungsten oxide (WO X ) resistive memory (ReRAM), a two-terminal CMOS compatible nonvolatile memory, has shown promise to surpass the existing flash memory in terms of scalability, switching speed, and potential for 3D stacking. The memory layer, WO X , can be easily fabricated by down-stream plasma oxidation (DSPO) or rapid thermal oxidation (RTO) of W plugs universally used in CMOS circuits. Results of conductive AFM (C-AFM) experiment suggest the switching mechanism is dominated by the REDOX (Reduction-oxidation) reaction—the creation of conducting filaments leads to a low resistance state and the rupturing of the filaments results in a high resistance state. Our experimental results show that the reactions happen at the TE/WO X interface. With this understanding in mind, we proposed two approaches to boost the memory performance: (i) using DSPO to treat the RTO WO X surface and (ii) using Pt TE, which forms a Schottky barrier with WO X . Both approaches, especially the latter, significantly reduce the forming current and enlarge the memory window.

Forced Ion Migration for Chalcogenide Phase Change Memory Device

NASA Technical Reports Server (NTRS)

Campbell, Kristy A (Inventor)

2013-01-01

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge2Se3/SnTe, and Ge2Se3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

Forced ion migration for chalcogenide phase change memory device

NASA Technical Reports Server (NTRS)

Campbell, Kristy A. (Inventor)

2011-01-01

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more that two data states.

Forced ion migration for chalcogenide phase change memory device

NASA Technical Reports Server (NTRS)

Campbell, Kristy A. (Inventor)

2012-01-01

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase-change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase-change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase-change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more than two data states.

Semiconductor-based, large-area, flexible, electronic devices

DOEpatents

Goyal, Amit [Knoxville, TN

2011-03-15

Novel articles and methods to fabricate the same resulting in flexible, large-area, triaxially textured, single-crystal or single-crystal-like, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Semiconductor-based, large-area, flexible, electronic devices on {110}<100> oriented substrates

DOEpatents

Goyal, Amit

2014-08-05

Novel articles and methods to fabricate the same resulting in flexible, oriented, semiconductor-based, electronic devices on {110}<100> textured substrates are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

[100] or [110] aligned, semiconductor-based, large-area, flexible, electronic devices

DOEpatents

Goyal, Amit

2015-03-24

Novel articles and methods to fabricate the same resulting in flexible, large-area, [100] or [110] textured, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Foundry Technologies Focused on Environmental and Ecological Applications

NASA Astrophysics Data System (ADS)

Roizin, Ya.; Lisiansky, M.; Pikhay, E.

Solutions allowing fabrication of remote control systems with integrated sensors (motes) were introduced as a part of CMOS foundry production platform and verified on silicon. The integrated features include sensors employing principles previously verified in the development of ultra-low power consuming non-volatile memories (C-Flash, MRAM) and components allowing low-power energy harvesting (low voltage rectifiers, high -voltage solar cells). The developed systems are discussed with emphasis on their environmental and security applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhu, H. X.; Zhang, T.; Wang, R. X.

A nano-floating gate memory structure based on Ni nanocrystals (NCs) embedded HfO{sub x} film is deposited by means of radio-frequency magnetron sputtering. Microstructure investigations reveal that self-organized Ni-NCs with diameters of 4-8 nm are well dispersed in amorphous HfO{sub x} matrix. Pt/Ni-NCs embedded HfO{sub x}/Si/Ag capacitor structures exhibit voltage-dependent capacitance-voltage hysteresis, and a maximum flat-band voltage shift of 1.5 V, corresponding to a charge storage density of 6.0 × 10{sup 12} electrons/cm{sup 2}, is achieved. These capacitor memory cells exhibit good endurance characteristic up to 4 × 10{sup 4} cycles and excellent retention performance of 10{sup 5} s, fulfilling themore » requirements of next generation non-volatile memory devices. Schottky tunneling is proven to be responsible for electrons tunneling in these capacitors.« less

Charge storage and tunneling mechanism of Ni nanocrystals embedded HfOx film

NASA Astrophysics Data System (ADS)

Zhu, H. X.; Zhang, T.; Wang, R. X.; Zhang, Y. Y.; Li, L. T.; Qiu, X. Y.

2016-05-01

A nano-floating gate memory structure based on Ni nanocrystals (NCs) embedded HfOx film is deposited by means of radio-frequency magnetron sputtering. Microstructure investigations reveal that self-organized Ni-NCs with diameters of 4-8 nm are well dispersed in amorphous HfOx matrix. Pt/Ni-NCs embedded HfOx/Si/Ag capacitor structures exhibit voltage-dependent capacitance-voltage hysteresis, and a maximum flat-band voltage shift of 1.5 V, corresponding to a charge storage density of 6.0 × 1012 electrons/cm2, is achieved. These capacitor memory cells exhibit good endurance characteristic up to 4 × 104 cycles and excellent retention performance of 105 s, fulfilling the requirements of next generation non-volatile memory devices. Schottky tunneling is proven to be responsible for electrons tunneling in these capacitors.

Spatial nonuniformity in resistive-switching memory effects of NiO.

PubMed

Oka, Keisuke; Yanagida, Takeshi; Nagashima, Kazuki; Kanai, Masaki; Kawai, Tomoji; Kim, Jin-Soo; Park, Bae Ho

2011-08-17

Electrically driven resistance change phenomenon in metal/NiO/metal junctions, so-called resistive switching (RS), is a candidate for next-generation universal nonvolatile memories. However, the knowledge as to RS mechanisms is unfortunately far from comprehensive, especially the spatial switching location, which is crucial information to design reliable devices. In this communication, we demonstrate the identification of the spatial switching location of bipolar RS by introducing asymmetrically passivated planar NiO nanowire junctions. We have successfully identified that the bipolar RS in NiO occurs near the cathode rather than the anode. This trend can be interpreted in terms of an electrochemical redox model based on ion migration and p-type conduction.

Acoustically assisted spin-transfer-torque switching of nanomagnets: An energy-efficient hybrid writing scheme for non-volatile memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Biswas, Ayan K.; Bandyopadhyay, Supriyo; Atulasimha, Jayasimha

We show that the energy dissipated to write bits in spin-transfer-torque random access memory can be reduced by an order of magnitude if a surface acoustic wave (SAW) is launched underneath the magneto-tunneling junctions (MTJs) storing the bits. The SAW-generated strain rotates the magnetization of every MTJs' soft magnet from the easy towards the hard axis, whereupon passage of a small spin-polarized current through a target MTJ selectively switches it to the desired state with > 99.99% probability at room temperature, thereby writing the bit. The other MTJs return to their original states at the completion of the SAW cycle.

The future of memory

NASA Astrophysics Data System (ADS)

Marinella, M.

In the not too distant future, the traditional memory and storage hierarchy of may be replaced by a single Storage Class Memory (SCM) device integrated on or near the logic processor. Traditional magnetic hard drives, NAND flash, DRAM, and higher level caches (L2 and up) will be replaced with a single high performance memory device. The Storage Class Memory paradigm will require high speed (< 100 ns read/write), excellent endurance (> 1012), nonvolatility (retention > 10 years), and low switching energies (< 10 pJ per switch). The International Technology Roadmap for Semiconductors (ITRS) has recently evaluated several potential candidates SCM technologies, including Resistive (or Redox) RAM, Spin Torque Transfer RAM (STT-MRAM), and phase change memory (PCM). All of these devices show potential well beyond that of current flash technologies and research efforts are underway to improve the endurance, write speeds, and scalabilities to be on-par with DRAM. This progress has interesting implications for space electronics: each of these emerging device technologies show excellent resistance to the types of radiation typically found in space applications. Commercially developed, high density storage class memory-based systems may include a memory that is physically radiation hard, and suitable for space applications without major shielding efforts. This paper reviews the Storage Class Memory concept, emerging memory devices, and possible applicability to radiation hardened electronics for space.

Wall-loss distribution of charge breeding ions in an electron cyclotron resonance ion source

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jeong, S. C.; Oyaizu, M.; Imai, N.

2011-03-15

The ion loss distribution in an electron cyclotron resonance ion source (ECRIS) was investigated to understand the element dependence of the charge breeding efficiency in an electron cyclotron resonance (ECR) charge breeder. The radioactive {sup 111}In{sup 1+} and {sup 140}Xe{sup 1+} ions (typical nonvolatile and volatile elements, respectively) were injected into the ECR charge breeder at the Tokai Radioactive Ion Accelerator Complex to breed their charge states. Their respective residual activities on the sidewall of the cylindrical plasma chamber of the source were measured after charge breeding as functions of the azimuthal angle and longitudinal position and two-dimensional distributions ofmore » ions lost during charge breeding in the ECRIS were obtained. These distributions had different azimuthal symmetries. The origins of these different azimuthal symmetries are qualitatively discussed by analyzing the differences and similarities in the observed wall-loss patterns. The implications for improving the charge breeding efficiencies of nonvolatile elements in ECR charge breeders are described. The similarities represent universal ion loss characteristics in an ECR charge breeder, which are different from the loss patterns of electrons on the ECRIS wall.« less

Development of novel nonvolatile memory devices using the colossal magnetoresistive oxide praseodymium-calcium-manganese trioxide

NASA Astrophysics Data System (ADS)

Papagianni, Christina

Pr0.7Ca0.3MnO3 (PCMO) manganese oxide belongs in the family of materials known as transition metal oxides. These compounds have received increased attention due to their perplexing properties such as Colossal Magnetoresistance effect, Charge-Ordered phase, existence of phase-separated states etc. In addition, it was recently discovered that short electrical pulses in amplitude and duration are sufficient to induce reversible and non-volatile resistance changes in manganese perovskite oxide thin films at room temperature, known as the EPIR effect. The existence of the EPIR effect in PCMO thin films at room temperature opens a viable way for the realization of fast, high-density, low power non-volatile memory devices in the near future. The purpose of this study is to investigate, optimize and understand the properties of Pr0.7Ca0.3MnO 3 (PCMO) thin film devices and to identify how these properties affect the EPIR effect. PCMO thin films were deposited on various substrates, such as metals, and conducting and insulating oxides, by pulsed laser and radio frequency sputtering methods. Our objective was to understand and compare the induced resistive states. We attempted to identify the induced resistance changes by considering two resistive models to be equivalent to our devices. Impedance spectroscopy was also utilized in a wide temperature range that was extended down to 70K. Fitted results of the temperature dependence of the resistance states were also included in this study. In the same temperature range, we probed the resistance changes in PCMO thin films and we examined whether the phase transitions affect the EPIR effect. In addition, we included a comparison of devices with electrodes consisting of different size and different materials. We demonstrated a direct relation between the EPIR effect and the phase diagram of bulk PCMO samples. A model that could account for the observed EPIR effect is presented.

Space Radiation Effects in Advanced Flash Memories

NASA Technical Reports Server (NTRS)

Johnston, A. H.

2001-01-01

Memory storage requirements in space systems have steadily increased, much like storage requirements in terrestrial systems. Large arrays of dynamic memories (DRAMs) have been used in solid-state recorders, relying on a combination of shielding and error-detection-and correction (EDAC) to overcome the extreme sensitivity of DRAMs to space radiation. For example, a 2-Gbit memory (with 4-Mb DRAMs) used on the Clementine mission functioned perfectly during its moon mapping mission, in spite of an average of 71 memory bit flips per day from heavy ions. Although EDAC worked well with older types of memory circuits, newer DRAMs use extremely complex internal architectures which has made it increasingly difficult to implement EDAC. Some newer DRAMs have also exhibited catastrophic latchup. Flash memories are an intriguing alternative to DRAMs because of their nonvolatile storage and extremely high storage density, particularly for applications where writing is done relatively infrequently. This paper discusses radiation effects in advanced flash memories, including general observations on scaling and architecture as well as the specific experience obtained at the Jet Propulsion Laboratory in evaluating high-density flash memories for use on the NASA mission to Europa, one of Jupiter's moons. This particular mission must pass through the Jovian radiation belts, which imposes a very demanding radiation requirement.

{100}<100> or 45.degree.-rotated {100}<100>, semiconductor-based, large-area, flexible, electronic devices

DOEpatents

Goyal, Amit [Knoxville, TN

2012-05-15

Novel articles and methods to fabricate the same resulting in flexible, {100}<100> or 45.degree.-rotated {100}<100> oriented, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices.

Nonvolatile and Cryogenic-compatible Quantum Memory Devices (QuMEM)

DTIC Science & Technology

2016-06-01

construction including: • 4” SiO2 /Si substrates and wafer/sample holders • Tweezers and wafer scribe • Safety glasses , gloves, and fab wipes • Probe tips...Cleaving of NbSe2 with Scotch™ Tape method ............................................................ 56 59. Transfer of NbSe2 atomic crystals to SiO2 ...O2 plasma + optional CF4 5 Top superconductor electrode evaporation Thermal Evaporation at SDSU MEMS Lab P+ Si Handle Wafer SiO2 (Oxide

Nonvolatile and Cryogenic-Compatible Quantum Memory Devices (QuMEM)

DTIC Science & Technology

2016-06-01

construction including: • 4” SiO2 /Si substrates and wafer/sample holders • Tweezers and wafer scribe • Safety glasses , gloves, and fab wipes • Probe tips...Cleaving of NbSe2 with Scotch™ Tape method ............................................................ 56 59. Transfer of NbSe2 atomic crystals to SiO2 ...O2 plasma + optional CF4 5 Top superconductor electrode evaporation Thermal Evaporation at SDSU MEMS Lab P+ Si Handle Wafer SiO2 (Oxide

Lead-free epitaxial ferroelectric material integration on semiconducting (100) Nb-doped SrTiO3 for low-power non-volatile memory and efficient ultraviolet ray detection

PubMed Central

Kundu, Souvik; Clavel, Michael; Biswas, Pranab; Chen, Bo; Song, Hyun-Cheol; Kumar, Prashant; Halder, Nripendra N.; Hudait, Mantu K.; Banerji, Pallab; Sanghadasa, Mohan; Priya, Shashank

2015-01-01

We report lead-free ferroelectric based resistive switching non-volatile memory (NVM) devices with epitaxial (1-x)BaTiO3-xBiFeO3 (x = 0.725) (BT-BFO) film integrated on semiconducting (100) Nb (0.7%) doped SrTiO3 (Nb:STO) substrates. The piezoelectric force microscopy (PFM) measurement at room temperature demonstrated ferroelectricity in the BT-BFO thin film. PFM results also reveal the repeatable polarization inversion by poling, manifesting its potential for read-write operation in NVM devices. The electroforming-free and ferroelectric polarization coupled electrical behaviour demonstrated excellent resistive switching with high retention time, cyclic endurance, and low set/reset voltages. X-ray photoelectron spectroscopy was utilized to determine the band alignment at the BT-BFO and Nb:STO heterojunction, and it exhibited staggered band alignment. This heterojunction is found to behave as an efficient ultraviolet photo-detector with low rise and fall time. The architecture also demonstrates half-wave rectification under low and high input signal frequencies, where the output distortion is minimal. The results provide avenue for an electrical switch that can regulate the pixels in low or high frequency images. Combined this work paves the pathway towards designing future generation low-power ferroelectric based microelectronic devices by merging both electrical and photovoltaic properties of BT-BFO materials. PMID:26202946

Excellent Resistive Switching Performance of Cu-Se-Based Atomic Switch Using Lanthanide Metal Nanolayer at the Cu-Se/Al2O3 Interface.

PubMed

Woo, Hyunsuk; Vishwanath, Sujaya Kumar; Jeon, Sanghun

2018-03-07

The next-generation electronic society is dependent on the performance of nonvolatile memory devices, which has been continuously improving. In the last few years, many memory devices have been introduced. However, atomic switches are considered to be a simple and reliable basis for next-generation nonvolatile devices. In general, atomic switch-based resistive switching is controlled by electrochemical metallization. However, excess ion injection from the entire area of the active electrode into the switching layer causes device nonuniformity and degradation of reliability. Here, we propose the fabrication of a high-performance atomic switch based on Cu x -Se 1- x by inserting lanthanide (Ln) metal buffer layers such as neodymium (Nd), samarium (Sm), dysprosium (Dy), or lutetium (Lu) between the active metal layer and the electrolyte. Current-atomic force microscopy results confirm that Cu ions penetrate through the Ln-buffer layer and form thin conductive filaments inside the switching layer. Compared with the Pt/Cu x -Se 1- x /Al 2 O 3 /Pt device, the optimized Pt/Cu x -Se 1- x /Ln/Al 2 O 3 /Pt devices show improvement in the on/off resistance ratio (10 2 -10 7 ), retention (10 years/85 °C), endurance (∼10 000 cycles), and uniform resistance state distribution.

Self-Positioned Nanosized Mask for Transparent and Flexible Ferroelectric Polymer Nanodiodes Array.

PubMed

Hyun, Seung; Kwon, Owoong; Choi, Chungryong; Vincent Joseph, Kanniyambatti L; Kim, Yunseok; Kim, Jin Kon

2016-10-12

High density arrays of ferroelectric polymer nanodiodes have gained strong attention for next-generation transparent and flexible nonvolatile resistive memory. Here, we introduce a facile and innovative method to fabricate ferroelectric polymer nanodiode array on an ITO-coated poly(ethylene terephthalate) (PET) substrate by using block copolymer self-assembly and oxygen plasma etching. First, polystyrene-block-poly(2-vinylpyridine) copolymer (PS-b-P2VP) micelles were spin-coated on poly(vinylidene fluoride-ran-trifluoroethylene) copolymer (P(VDF-TrFE)) film/ITO-coated PET substrate. After the sample was immersed in a gold precursor (HAuCl 4 ) containing solution, which strongly coordinates with nitrogen group in P2VP, oxygen plasma etching was performed. During the plasma etching, coordinated gold precursors became gold nanoparticles (GNPs), which successfully acted as self-positioned etching mask to fabricate a high density array of P(VDF-TrFE)) nanoislands with GNP at the top. Each nanoisland shows clearly individual diode property, as confirmed by current-voltage (I-V) curve. Furthermore, due to the transparent and flexible nature of P(VDF-TrFE)) nanoisland as well as the substrate, the P(VDF-TrFE) nanodiode array was highly tranparent, and the diode property was maintained even after a large number of bendings (for instance, 1000 times). The array could be used as the next-generation tranparent and flexible nonvolatile memory device.

Lead-free epitaxial ferroelectric material integration on semiconducting (100) Nb-doped SrTiO3 for low-power non-volatile memory and efficient ultraviolet ray detection.

PubMed

Kundu, Souvik; Clavel, Michael; Biswas, Pranab; Chen, Bo; Song, Hyun-Cheol; Kumar, Prashant; Halder, Nripendra N; Hudait, Mantu K; Banerji, Pallab; Sanghadasa, Mohan; Priya, Shashank

2015-07-23

We report lead-free ferroelectric based resistive switching non-volatile memory (NVM) devices with epitaxial (1-x)BaTiO3-xBiFeO3 (x = 0.725) (BT-BFO) film integrated on semiconducting (100) Nb (0.7%) doped SrTiO3 (Nb:STO) substrates. The piezoelectric force microscopy (PFM) measurement at room temperature demonstrated ferroelectricity in the BT-BFO thin film. PFM results also reveal the repeatable polarization inversion by poling, manifesting its potential for read-write operation in NVM devices. The electroforming-free and ferroelectric polarization coupled electrical behaviour demonstrated excellent resistive switching with high retention time, cyclic endurance, and low set/reset voltages. X-ray photoelectron spectroscopy was utilized to determine the band alignment at the BT-BFO and Nb:STO heterojunction, and it exhibited staggered band alignment. This heterojunction is found to behave as an efficient ultraviolet photo-detector with low rise and fall time. The architecture also demonstrates half-wave rectification under low and high input signal frequencies, where the output distortion is minimal. The results provide avenue for an electrical switch that can regulate the pixels in low or high frequency images. Combined this work paves the pathway towards designing future generation low-power ferroelectric based microelectronic devices by merging both electrical and photovoltaic properties of BT-BFO materials.

Ultra-low power, highly uniform polymer memory by inserted multilayer graphene electrode

NASA Astrophysics Data System (ADS)

Jang, Byung Chul; Seong, Hyejeong; Kim, Jong Yun; Koo, Beom Jun; Kim, Sung Kyu; Yang, Sang Yoon; Gap Im, Sung; Choi, Sung-Yool

2015-12-01

Filament type resistive random access memory (RRAM) based on polymer thin films is a promising device for next generation, flexible nonvolatile memory. However, the resistive switching nonuniformity and the high power consumption found in the general filament type RRAM devices present critical issues for practical memory applications. Here, we introduce a novel approach not only to reduce the power consumption but also to improve the resistive switching uniformity in RRAM devices based on poly(1,3,5-trimethyl-3,4,5-trivinyl cyclotrisiloxane) by inserting multilayer graphene (MLG) at the electrode/polymer interface. The resistive switching uniformity was thereby significantly improved, and the power consumption was markedly reduced by 250 times. Furthermore, the inserted MLG film enabled a transition of the resistive switching operation from unipolar resistive switching to bipolar resistive switching and induced self-compliance behavior. The findings of this study can pave the way toward a new area of application for graphene in electronic devices.

Ga-doped indium oxide nanowire phase change random access memory cells

NASA Astrophysics Data System (ADS)

Jin, Bo; Lim, Taekyung; Ju, Sanghyun; Latypov, Marat I.; Kim, Hyoung Seop; Meyyappan, M.; Lee, Jeong-Soo

2014-02-01

Phase change random access memory (PCRAM) devices are usually constructed using tellurium based compounds, but efforts to seek other materials providing desirable memory characteristics have continued. We have fabricated PCRAM devices using Ga-doped In2O3 nanowires with three different Ga compositions (Ga/(In+Ga) atomic ratio: 2.1%, 11.5% and 13.0%), and investigated their phase switching properties. The nanowires (˜40 nm in diameter) can be repeatedly switched between crystalline and amorphous phases, and Ga concentration-dependent memory switching behavior in the nanowires was observed with ultra-fast set/reset rates of 80 ns/20 ns, which are faster than for other competitive phase change materials. The observations of fast set/reset rates and two distinct states with a difference in resistance of two to three orders of magnitude appear promising for nonvolatile information storage. Moreover, we found that increasing the Ga concentration can reduce the power consumption and resistance drift; however, too high a level of Ga doping may cause difficulty in achieving the phase transition.

Highly reliable top-gated thin-film transistor memory with semiconducting, tunneling, charge-trapping, and blocking layers all of flexible polymers.

PubMed

Wang, Wei; Hwang, Sun Kak; Kim, Kang Lib; Lee, Ju Han; Cho, Suk Man; Park, Cheolmin

2015-05-27

The core components of a floating-gate organic thin-film transistor nonvolatile memory (OTFT-NVM) include the semiconducting channel layer, tunneling layer, floating-gate layer, and blocking layer, besides three terminal electrodes. In this study, we demonstrated OTFT-NVMs with all four constituent layers made of polymers based on consecutive spin-coating. Ambipolar charges injected and trapped in a polymer electret charge-controlling layer upon gate program and erase field successfully allowed for reliable bistable channel current levels at zero gate voltage. We have observed that the memory performance, in particular the reliability of a device, significantly depends upon the thickness of both blocking and tunneling layers, and with an optimized layer thickness and materials selection, our device exhibits a memory window of 15.4 V, on/off current ratio of 2 × 10(4), read and write endurance cycles over 100, and time-dependent data retention of 10(8) s, even when fabricated on a mechanically flexible plastic substrate.

Realisation of all 16 Boolean logic functions in a single magnetoresistance memory cell.

PubMed

Gao, Shuang; Yang, Guang; Cui, Bin; Wang, Shouguo; Zeng, Fei; Song, Cheng; Pan, Feng

2016-07-07

Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future.

Two-dimensional molybdenum disulphide nanosheet-covered metal nanoparticle array as a floating gate in multi-functional flash memories

NASA Astrophysics Data System (ADS)

Han, Su-Ting; Zhou, Ye; Chen, Bo; Zhou, Li; Yan, Yan; Zhang, Hua; Roy, V. A. L.

2015-10-01

Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure.Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure. Electronic supplementary information (ESI) available: Energy-dispersive X-ray spectroscopy (EDS) spectra of the metal NPs, SEM image of MoS2 on Au NPs, erasing operations of the metal NPs-MoS2 memory device, transfer characteristics of the standard FET devices and Ag NP devices under programming operation, tapping-mode AFM height image of the fabricated MoS2 film for pristine MoS2 flash memory, gate signals used for programming the Au NPs-MoS2 and Pt NPs-MoS2 flash memories, and data levels recorded for 100 sequential cycles. See DOI: 10.1039/c5nr05054e

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Juhee; Lee, Sungpyo; Lee, Moo Hyung

Quasi-unipolar non-volatile organic transistor memory (NOTM) can combine the best characteristics of conventional unipolar and ambipolar NOTMs and, as a result, exhibit improved device performance. Unipolar NOTMs typically exhibit a large signal ratio between the programmed and erased current signals but also require a large voltage to program and erase the memory cells. Meanwhile, an ambipolar NOTM can be programmed and erased at lower voltages, but the resulting signal ratio is small. By embedding a discontinuous n-type fullerene layer within a p-type pentacene film, quasi-unipolar NOTMs are fabricated, of which the signal storage utilizes both electrons and holes while themore » electrical signal relies on only hole conduction. These devices exhibit superior memory performance relative to both pristine unipolar pentacene devices and ambipolar fullerene/pentacene bilayer devices. The quasi-unipolar NOTM exhibited a larger signal ratio between the programmed and erased states while also reducing the voltage required to program and erase a memory cell. This simple approach should be readily applicable for various combinations of advanced organic semiconductors that have been recently developed and thereby should make a significant impact on organic memory research.« less

Organic transistor memory with a charge storage molecular double-floating-gate monolayer.

PubMed

Tseng, Chiao-Wei; Huang, Ding-Chi; Tao, Yu-Tai

2015-05-13

A flexible, low-voltage, and nonvolatile memory device was fabricated by implanting a functional monolayer on an aluminum oxide dielectric surface in a pentacene-based organic transistor. The monolayer-forming molecule contains a phosphonic acid group as the anchoring moiety and a charge-trapping core group flanked between two alkyl chain spacers as the charge trapping site. The memory characteristics strongly depend on the monolayer used due to the localized charge-trapping capability for different core groups, including the diacetylenic (DA) unit as the hole carrier trap, the naphthalenetetracarboxyldiimide (ND) unit as the electron carrier trap, and the one with both DA and ND units present, respectively. The device with the monolayer carrying both DA and ND groups has a larger memory window than that for the one containing DA only and a longer retention time than that for the one containing DA or ND only, giving a memory window of 1.4 V and a retention time around 10(9) s. This device with hybrid organic monolayer/inorganic dielectrics also exhibited rather stable device characteristics upon bending of the polymeric substrate.

A graphene integrated highly transparent resistive switching memory device

NASA Astrophysics Data System (ADS)

Dugu, Sita; Pavunny, Shojan P.; Limbu, Tej B.; Weiner, Brad R.; Morell, Gerardo; Katiyar, Ram S.

2018-05-01

We demonstrate the hybrid fabrication process of a graphene integrated highly transparent resistive random-access memory (TRRAM) device. The indium tin oxide (ITO)/Al2O3/graphene nonvolatile memory device possesses a high transmittance of >82% in the visible region (370-700 nm) and exhibits stable and non-symmetrical bipolar switching characteristics with considerably low set and reset voltages (<±1 V). The vertical two-terminal device shows an excellent resistive switching behavior with a high on-off ratio of ˜5 × 103. We also fabricated a ITO/Al2O3/Pt device and studied its switching characteristics for comparison and a better understanding of the ITO/Al2O3/graphene device characteristics. The conduction mechanisms in high and low resistance states were analyzed, and the observed polarity dependent resistive switching is explained based on electro-migration of oxygen ions.

Organic bistable memory devices based on MoO3 nanoparticle embedded Alq3 structures.

PubMed

Abhijith, T; Kumar, T V Arun; Reddy, V S

2017-03-03

Organic bistable memory devices were fabricated by embedding a thin layer of molybdenum trioxide (MoO 3 ) between two tris-(8-hydroxyquinoline)aluminum (Alq 3 ) layers. The device exhibited excellent switching characteristics with an ON/OFF current ratio of 1.15 × 10 3 at a read voltage of 1 V. The device showed repeatable write-erase capability and good stability in both the conductance states. These conductance states are non-volatile in nature and can be obtained by applying appropriate voltage pulses. The effect of MoO 3 layer thickness and its location in the Alq 3 matrix on characteristics of the memory device was investigated. The field emission scanning electron microscopy (FE-SEM) images of the MoO 3 layer revealed the presence of isolated nanoparticles. Based on the experimental results, a mechanism has been proposed for explaining the conductance switching of fabricated devices.

Filamentary model in resistive switching materials

NASA Astrophysics Data System (ADS)

Jasmin, Alladin C.

2017-12-01

The need for next generation computer devices is increasing as the demand for efficient data processing increases. The amount of data generated every second also increases which requires large data storage devices. Oxide-based memory devices are being studied to explore new research frontiers thanks to modern advances in nanofabrication. Various oxide materials are studied as active layers for non-volatile memory. This technology has potential application in resistive random-access-memory (ReRAM) and can be easily integrated in CMOS technologies. The long term perspective of this research field is to develop devices which mimic how the brain processes information. To realize such application, a thorough understanding of the charge transport and switching mechanism is important. A new perspective in the multistate resistive switching based on current-induced filament dynamics will be discussed. A simple equivalent circuit of the device gives quantitative information about the nature of the conducting filament at different resistance states.

Adaptive microwave impedance memory effect in a ferromagnetic insulator.

PubMed

Lee, Hanju; Friedman, Barry; Lee, Kiejin

2016-12-14

Adaptive electronics, which are often referred to as memristive systems as they often rely on a memristor (memory resistor), are an emerging technology inspired by adaptive biological systems. Dissipative systems may provide a proper platform to implement an adaptive system due to its inherent adaptive property that parameters describing the system are optimized to maximize the entropy production for a given environment. Here, we report that a non-volatile and reversible adaptive microwave impedance memory device can be realized through the adaptive property of the dissipative structure of the driven ferromagnetic system. Like the memristive device, the microwave impedance of the device is modulated as a function of excitation microwave passing through the device. This kind of new device may not only helpful to implement adaptive information processing technologies, but also may be useful to investigate and understand the underlying mechanism of spontaneous formation of complex and ordered structures.

Organic bistable memory devices based on MoO3 nanoparticle embedded Alq3 structures

NASA Astrophysics Data System (ADS)

Abhijith, T.; Kumar, T. V. Arun; Reddy, V. S.

2017-03-01

Organic bistable memory devices were fabricated by embedding a thin layer of molybdenum trioxide (MoO3) between two tris-(8-hydroxyquinoline)aluminum (Alq3) layers. The device exhibited excellent switching characteristics with an ON/OFF current ratio of 1.15 × 103 at a read voltage of 1 V. The device showed repeatable write-erase capability and good stability in both the conductance states. These conductance states are non-volatile in nature and can be obtained by applying appropriate voltage pulses. The effect of MoO3 layer thickness and its location in the Alq3 matrix on characteristics of the memory device was investigated. The field emission scanning electron microscopy (FE-SEM) images of the MoO3 layer revealed the presence of isolated nanoparticles. Based on the experimental results, a mechanism has been proposed for explaining the conductance switching of fabricated devices.

Feasibility of self-structured current accessed bubble devices in spacecraft recording systems

NASA Technical Reports Server (NTRS)

Nelson, G. L.; Krahn, D. R.; Dean, R. H.; Paul, M. C.; Lo, D. S.; Amundsen, D. L.; Stein, G. A.

1985-01-01

The self-structured, current aperture approach to magnetic bubble memory is described. Key results include: (1) demonstration that self-structured bubbles (a lattice of strongly interacting bubbles) will slip by one another in a storage loop at spacings of 2.5 bubble diameters, (2) the ability of self-structured bubbles to move past international fabrication defects (missing apertures) in the propagation conductors (defeat tolerance), and (3) moving bubbles at mobility limited speeds. Milled barriers in the epitaxial garnet are discussed for containment of the bubble lattice. Experimental work on input/output tracks, storage loops, gates, generators, and magneto-resistive detectors for a prototype device are discussed. Potential final device architectures are described with modeling of power consumption, data rates, and access times. Appendices compare the self-structured bubble memory from the device and system perspectives with other non-volatile memory technologies.

Adaptive microwave impedance memory effect in a ferromagnetic insulator

PubMed Central

Lee, Hanju; Friedman, Barry; Lee, Kiejin

2016-01-01

Adaptive electronics, which are often referred to as memristive systems as they often rely on a memristor (memory resistor), are an emerging technology inspired by adaptive biological systems. Dissipative systems may provide a proper platform to implement an adaptive system due to its inherent adaptive property that parameters describing the system are optimized to maximize the entropy production for a given environment. Here, we report that a non-volatile and reversible adaptive microwave impedance memory device can be realized through the adaptive property of the dissipative structure of the driven ferromagnetic system. Like the memristive device, the microwave impedance of the device is modulated as a function of excitation microwave passing through the device. This kind of new device may not only helpful to implement adaptive information processing technologies, but also may be useful to investigate and understand the underlying mechanism of spontaneous formation of complex and ordered structures. PMID:27966536

Synaptic plasticity functions in an organic electrochemical transistor

NASA Astrophysics Data System (ADS)

Gkoupidenis, Paschalis; Schaefer, Nathan; Strakosas, Xenofon; Fairfield, Jessamyn A.; Malliaras, George G.

2015-12-01

Synaptic plasticity functions play a crucial role in the transmission of neural signals in the brain. Short-term plasticity is required for the transmission, encoding, and filtering of the neural signal, whereas long-term plasticity establishes more permanent changes in neural microcircuitry and thus underlies memory and learning. The realization of bioinspired circuits that can actually mimic signal processing in the brain demands the reproduction of both short- and long-term aspects of synaptic plasticity in a single device. Here, we demonstrate the implementation of neuromorphic functions similar to biological memory, such as short- to long-term memory transition, in non-volatile organic electrochemical transistors (OECTs). Depending on the training of the OECT, the device displays either short- or long-term plasticity, therefore, exhibiting non von Neumann characteristics with merged processing and storing functionalities. These results are a first step towards the implementation of organic-based neuromorphic circuits.

An assessment of memristor intrinsic fluctuations: a measurement of single atomic motion

NASA Astrophysics Data System (ADS)

Borghetti, Julien; Yang, J. Joshua; Medeiros-Ribeiro, Gilberto; Williams, R. Stanley

2010-03-01

Memristors provides electrically tunable resistance for upcoming non-volatile memory and future neuromorphic computing. One of the key benefits of such a device is its scalability, which can be demonstrated from an architectural perspective as well as from a fundamental physics limit. 4D addressing schemes utilizing cross bar structures that can be stacked several layers high above the chip embodies unlimited addressing space. On the other limit, the basic operating principles of memristive devices allow one to reach storage of information in a single atom. In this report of nanoscale (sub 50nm) devices, we detect single atom fluctuations, which would then represent the ultimate limit for noise sources thus delineating the boundary conditions for circuit design. We show that electrically induced individual atom migrations do not affect the overall device atomic configuration until a critical bias where a single local fluctuation triggers a general atomic reconfiguration. This instability illustrates the robustness of the device non-volatility upon small electrical stress.

EqualChance: Addressing Intra-set Write Variation to Increase Lifetime of Non-volatile Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S

To address the limitations of SRAM such as high-leakage and low-density, researchers have explored use of non-volatile memory (NVM) devices, such as ReRAM (resistive RAM) and STT-RAM (spin transfer torque RAM) for designing on-chip caches. A crucial limitation of NVMs, however, is that their write endurance is low and the large intra-set write variation introduced by existing cache management policies may further exacerbate this problem, thereby reducing the cache lifetime significantly. We present EqualChance, a technique to increase cache lifetime by reducing intra-set write variation. EqualChance works by periodically changing the physical cache-block location of a write-intensive data item withinmore » a set to achieve wear-leveling. Simulations using workloads from SPEC CPU2006 suite and HPC (high-performance computing) field show that EqualChance improves the cache lifetime by 4.29X. Also, its implementation overhead is small, and it incurs very small performance and energy loss.« less

Development and characterization of a ferroelectric non-volatile memory for flexible electronics

NASA Astrophysics Data System (ADS)

Mao, Duo

Flexible electronics have received significant attention recently because of the potential applications in displays, sensors, radio frequency identification (RFID) tags and other integrated circuits. Electrically addressable non-volatile memory is a key component for these applications. The major challenges are to fabricate the memory at a low temperature compatible with plastic substrates while maintaining good device reliability, by being compatible with process as needed to integrate with other electronic components for system-on-chip applications. In this work, ferroelectric capacitors fabricated at low temperature were developed. Based on that, a ferroelectric random access memory (FRAM) for flexible electronics was developed and characterized. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] copolymer was used as a ferroelectric material and a photolithographic process was developed to fabricate ferroelectric capacitors. Different characterization methods including atomic force microscopy, x-ray diffraction and Fourier-transform infrared reflection-absorption spectroscopy were used to study the material properties of the P(VDF-TrFE) film. The material properties were correlated with the electrical characteristics of the ferroelectric capacitors. To understand the polarization switching behavior of the P(VDF-TrFE) ferroelectric capacitors, a Nucleation-Limited-Switching (NLS) model was used to study the switching kinetics. The switching kinetics were characterized over the temperature range from -60 °C to 100 °C. Fatigue characteristics were studied at different electrical stress voltages and frequencies to evaluate the reliability of the ferroelectric capacitor. The degradation mechanism is attributed to the increase of the activation field and the suppression of the switchable polarization. To develop a FRAM circuit for flexible electronics, an n-channel thin film transistor (TFT) based on CdS as the semiconductor was integrated with a P(VDF-TrFE) ferroelectric capacitor for a one-transistor-one-capacitor (1T1C) memory cell. The 1T1C devices were fabricated at low temperature and demonstrated a memory window (DeltaVBL) of 2.3 V and 3.5 V, depending on the device dimensions. Next, FRAM arrays (4-bit, 16-bit and 64-bit) based on the two-transistor-two-capacitor (2T2C) memory cell architecture were designed and fabricated using a photolithographic process with 9 masks. The fabricated FRAM arrays were packaged in 28-pin ceramic packages. The read/write schemes were developed and the FRAM arrays show successful program and erase with a memory window of approximately 1 V at the output of the sense amplifier.

A complementary switching mechanism for organic memory devices to regulate the conductance of binary states

NASA Astrophysics Data System (ADS)

Vyas, Giriraj; Dagar, Parveen; Sahu, Satyajit

2016-06-01

We have fabricated an organic non-volatile memory device wherein the ON/OFF current ratio has been controlled by varying the concentration of a small organic molecule, 2,3-Dichloro-5,6-dicyano-p-benzoquinone (DDQ), in an insulating matrix of a polymer Poly(4-vinylphenol) (PVP). A maximum ON-OFF ratio of 106 is obtained when the concentration of DDQ is half or 10 wt. % of PVP. In this process, the switching direction for the devices has also been altered, indicating the disparity in conduction mechanism. Conduction due to metal filament formation through the active material and the voltage dependent conformational change of the organic molecule seem to be the motivation behind the gradual change in the switching direction.

Impact of total ionizing dose irradiation on Pt/SrBi2Ta2O9/HfTaO/Si memory capacitors

NASA Astrophysics Data System (ADS)

Yan, S. A.; Zhao, W.; Guo, H. X.; Xiong, Y.; Tang, M. H.; Li, Z.; Xiao, Y. G.; Zhang, W. L.; Ding, H.; Chen, J. W.; Zhou, Y. C.

2015-01-01

In this work, metal-ferroelectric-insulator-semiconductor (MFIS) structure capacitors with SrBi2Ta2O9 (300 nm) as ferroelectric thin film and HfTaO (6 nm, 8 nm, 10 nm, and 12 nm) as insulating buffer layer were proposed and investigated. The prepared capacitors were fabricated and characterized before radiation and then subjected to 60Co gamma irradiation in steps of two dose levels. Significant irradiation-induced degradation of the electrical characteristics was observed. The radiation experimental results indicated that stability and reliability of as-fabricated MFIS capacitors for nonvolatile memory applications could become uncontrollable under strong irradiation dose and/or long irradiation time.

Organic nonvolatile resistive memory devices based on thermally deposited Au nanoparticle

NASA Astrophysics Data System (ADS)

Jin, Zhiwen; Liu, Guo; Wang, Jizheng

2013-05-01

Uniform Au nanoparticles (NPs) are formed by thermally depositing nominal 2-nm thick Au film on a 10-nm thick polyimide film formed on a Al electrode, and then covered by a thin polymer semiconductor film, which acts as an energy barrier for electrons to be injected from the other Al electrode (on top of polymer film) into the Au NPs, which are energetically electron traps in such a resistive random access memory (RRAM) device. The Au NPs based RRAM device exhibits estimated retention time of 104 s, cycle times of more than 100, and ON-OFF ratio of 102 to 103. The carrier transport properties are also analyzed by fitting the measured I-V curves with several conduction models.

On the challenge of a century lifespan satellite

NASA Astrophysics Data System (ADS)

Gonzalo, Jesús; Domínguez, Diego; López, Deibi

2014-10-01

This paper provides a review of the main issues affecting satellite survivability, including a discussion on the technologies to mitigate the risks and to enhance system reliability. The feasibility of a 100-year lifespan space mission is taken as the guiding thread for the discussion. Such a mission, defined with a few preliminary requirements, could be used to deliver messages to our descendants regardless of the on-ground contingencies. After the analysis of the main threats for long endurance in space, including radiation, debris and micrometeoroids, atmospheric drag and thermal environment, the available solutions are investigated. A trade-off study analyses orbital profiles from the point of view of radiation, thermal stability and decay rate, providing best locations to maximize lifespan. Special attention is also paid to on-board power, in terms of energy harvesting and accumulation, highlighting the limitations of current assets, i.e. solar panels and batteries, and revealing possible future solutions. Furthermore, the review includes electronics, non-volatile memories and communication elements, which need extra hardening against radiation and thermal cycling if extra-long endurance is required. As a result of the analysis, a century-lifetime mission is depicted by putting together all the reviewed concepts. The satellite, equipped with reliability enhanced elements and system-level solutions such as smart hibernation policies, could provide limited but still useful performance after a 100-year flight.

Improved speed and data retention characteristics in flash memory using a stacked HfO2/Ta2O5 charge-trapping layer

NASA Astrophysics Data System (ADS)

Zheng, Zhiwei; Huo, Zongliang; Zhang, Manhong; Zhu, Chenxin; Liu, Jing; Liu, Ming

2011-10-01

This paper reports the simultaneous improvements in erase speed and data retention characteristics in flash memory using a stacked HfO2/Ta2O5 charge-trapping layer. In comparison to a memory capacitor with a single HfO2 trapping layer, the erase speed of a memory capacitor with a stacked HfO2/Ta2O5 charge-trapping layer is 100 times faster and its memory window is enlarged from 2.7 to 4.8 V for the same ±16 V sweeping voltage range. With the same initial window of ΔVFB = 4 V, the device with a stacked HfO2/Ta2O5 charge-trapping layer has a 3.5 V extrapolated 10-year retention window, while the control device with a single HfO2 trapping layer has only 2.5 V for the extrapolated 10-year window. The present results demonstrate that the device with the stacked HfO2/Ta2O5 charge-trapping layer has a strong potential for future high-performance nonvolatile memory application.

Inverse Resistance Change Cr2Ge2Te6-Based PCRAM Enabling Ultralow-Energy Amorphization.

PubMed

Hatayama, Shogo; Sutou, Yuji; Shindo, Satoshi; Saito, Yuta; Song, Yun-Heub; Ando, Daisuke; Koike, Junichi

2018-01-24

Phase-change random access memory (PCRAM) has attracted much attention for next-generation nonvolatile memory that can replace flash memory and can be used for storage-class memory. Generally, PCRAM relies on the change in the electrical resistance of a phase-change material between high-resistance amorphous (reset) and low-resistance crystalline (set) states. Herein, we present an inverse resistance change PCRAM with Cr 2 Ge 2 Te 6 (CrGT) that shows a high-resistance crystalline reset state and a low-resistance amorphous set state. The inverse resistance change was found to be due to a drastic decrease in the carrier density upon crystallization, which causes a large increase in contact resistivity between CrGT and the electrode. The CrGT memory cell was demonstrated to show fast reversible resistance switching with a much lower operating energy for amorphization than a Ge 2 Sb 2 Te 5 memory cell. This low operating energy in CrGT should be due to a small programmed amorphous volume, which can be realized by a high-resistance crystalline matrix and a dominant contact resistance. Simultaneously, CrGT can break the trade-off relationship between the crystallization temperature and operating speed.

Cost aware cache replacement policy in shared last-level cache for hybrid memory based fog computing

NASA Astrophysics Data System (ADS)

Jia, Gangyong; Han, Guangjie; Wang, Hao; Wang, Feng

2018-04-01

Fog computing requires a large main memory capacity to decrease latency and increase the Quality of Service (QoS). However, dynamic random access memory (DRAM), the commonly used random access memory, cannot be included into a fog computing system due to its high consumption of power. In recent years, non-volatile memories (NVM) such as Phase-Change Memory (PCM) and Spin-transfer torque RAM (STT-RAM) with their low power consumption have emerged to replace DRAM. Moreover, the currently proposed hybrid main memory, consisting of both DRAM and NVM, have shown promising advantages in terms of scalability and power consumption. However, the drawbacks of NVM, such as long read/write latency give rise to potential problems leading to asymmetric cache misses in the hybrid main memory. Current last level cache (LLC) policies are based on the unified miss cost, and result in poor performance in LLC and add to the cost of using NVM. In order to minimize the cache miss cost in the hybrid main memory, we propose a cost aware cache replacement policy (CACRP) that reduces the number of cache misses from NVM and improves the cache performance for a hybrid memory system. Experimental results show that our CACRP behaves better in LLC performance, improving performance up to 43.6% (15.5% on average) compared to LRU.

Tamper indicating bolt

DOEpatents

Blagin, Sergei V.; Barkanov, Boris P.

2004-09-14

A tamper-indicating fastener has a cylindrical body with threads extending from one end along a portion of the body, and a tamper indicating having a transducer for converting physical properties of the body into electronic data; electronics for recording the electronic data; and means for communicating the recorded information to a remote location from said fastener. The electronics includes a capacitor that varies as a function of force applied by the fastener, and non-volatile memory for recording instances when the capacitance varies, providing an indication of unauthorized access.

Recovery of the Space Shuttle Columbia Avionics

NASA Technical Reports Server (NTRS)

Hames, Kevin L.

2003-01-01

Lessons Learned: a) Avionics data can playa critical role in the investigation of a "close call" or accident. b) Avionics designers should think about the role their systems might play in an investigation. c) Know your data, down to the bit level. d) Know your spacecraft - follow the data. e) Internal placement of circuit cards can affect their survivability. f) Think about how to reconstruct nonvolatile memory (e.g. serialize IC's, etc.) g) Use of external assets can aid in extracting data from avionics.

Nonvolatile RRAM cells from polymeric composites embedding recycled SiC powders.

PubMed

De Girolamo Del Mauro, Anna; Nenna, Giuseppe; Miscioscia, Riccardo; Freda, Cesare; Portofino, Sabrina; Galvagno, Sergio; Minarini, Carla

2014-10-21

Silicon carbide powders have been synthesized from tires utilizing a patented recycling process. Dynamic light scattering, Raman spectroscopy, SEM microscopy, and X-ray diffraction have been carried out to gather knowledge about powders and the final composite structure. The obtained powder has been proven to induce resistive switching in a PMMA polymer-based composite device. Memory effect has been detected in two-terminal devices having coplanar contacts and quantified by read-write-erase measurements in terms of level separation and persistence.

A Study on Reactive Ion Etching of Barium Strontium Titanate Films Using Mixtures of Argon (Ar), Carbon Tetrafluoride (CF4), and Sulfur Hexafluoride (SF6)

DTIC Science & Technology

2014-07-01

BST) is a complex oxide material with ferroic properties which has been considered for applications ranging from non-volatile memory to microwave...utilizing self-aligned etching to create metal-insulator-metal (MIM) varactors . As part of this method we employed reactive ion etching (RIE) to remove BST...of BST removed vs. etch time for Ar:SF6. .........................................................4 Figure 3. SEM cross-section of varactor showing

Elucidation and Optimization of Resistive Random Access Memory Switching Behavior for Advanced Computing Applications

NASA Astrophysics Data System (ADS)

Alamgir, Zahiruddin

RRAM has recently emerged as a strong candidate for non-volatile memory (NVM). Beyond memory applications, RRAM holds promise for use in performing logic functions, mimicking neuromorphic activities, enabling multi-level switching, and as one of the key elements of hardware based encryption or signal processing systems. It has been shown previously that RRAM resistance levels can be changed by adjusting compliance current or voltage level. This characteristic makes RRAM suitable for use in setting the synaptic weight in neuromorphic computing circuits. RRAM is also considered as a key element in hardware encryption systems, to produce unique and reproducible signals. However, a key challenge to implement RRAM in these applications is significant cycle to cycle performance variability. We sought to develop RRAM that can be tuned to different resistance levels gradually, with high reliability, and low variability. To achieve this goal, we focused on elucidating the conduction mechanisms underlying the resistive switching behavior for these devices. Electrical conduction mechanisms were determined by curve fitting I-V data using different current conduction equations. Temperature studies were also performed to corroborate these data. It was found that Schottky barrier height and width modulation was one of the key parameters that could be tuned to achieve different resistance levels, and for switching resistance states, primarily via oxygen vacancy movement. Oxygen exchange layers with different electronegativity were placed between top electrode and the oxide layer of TaOx devices to determine the effect of oxygen vacancy concentrations and gradients in these devices. It was found that devices with OELs with lower electronegativity tend to yield greater separation in the OFF vs. ON state resistance levels. As an extension of this work, TaOx based RRAM with Hf as the OEL was fabricated and could be tuned to different resistance level using pulse width and height modulation, yielding excellent uniformity and reliability. These findings improve our understanding of conduction within TaO x-based RRAM devices, providing a physical basis for switching in these devices. The value of this work lies in the demonstration of devices with excellent performance and demonstrated devices constitute a significant step toward real-world applications.

Optimization of Ferroelectric Ceramics by Design at the Microstructure Level

NASA Astrophysics Data System (ADS)

Jayachandran, K. P.; Guedes, J. M.; Rodrigues, H. C.

2010-05-01

Ferroelectric materials show remarkable physical behaviors that make them essential for many devices and have been extensively studied for their applications of nonvolatile random access memory (NvRAM) and high-speed random access memories. Although ferroelectric ceramics (polycrystals) present ease in manufacture and in compositional modifications and represent the widest application area of materials, computational and theoretical studies are sparse owing to many reasons including the large number of constituent atoms. Macroscopic properties of ferroelectric polycrystals are dominated by the inhomogeneities at the crystallographic domain/grain level. Orientation of grains/domains is critical to the electromechanical response of the single crystalline and polycrystalline materials. Polycrystalline materials have the potential of exhibiting better performance at a macroscopic scale by design of the domain/grain configuration at the domain-size scale. This suggests that piezoelectric properties can be optimized by a proper choice of the parameters which control the distribution of grain orientations. Nevertheless, this choice is complicated and it is impossible to analyze all possible combinations of the distribution parameters or the angles themselves. Hence we have implemented the stochastic optimization technique of simulated annealing combined with the homogenization for the optimization problem. The mathematical homogenization theory of a piezoelectric medium is implemented in the finite element method (FEM) by solving the coupled equilibrium electrical and mechanical fields. This implementation enables the study of the dependence of the macroscopic electromechanical properties of a typical crystalline and polycrystalline ferroelectric ceramic on the grain orientation.

Ferroelectricity in Covalently functionalized Two-dimensional Materials: Integration of High-mobility Semiconductors and Nonvolatile Memory.

PubMed

Wu, Menghao; Dong, Shuai; Yao, Kailun; Liu, Junming; Zeng, Xiao Cheng

2016-11-09

Realization of ferroelectric semiconductors by conjoining ferroelectricity with semiconductors remains a challenging task because most present-day ferroelectric materials are unsuitable for such a combination due to their wide bandgaps. Herein, we show first-principles evidence toward the realization of a new class of two-dimensional (2D) ferroelectric semiconductors through covalent functionalization of many prevailing 2D materials. Members in this new class of 2D ferroelectric semiconductors include covalently functionalized germanene, and stanene (Nat. Commun. 2014, 5, 3389), as well as MoS 2 monolayer (Nat. Chem. 2015, 7, 45), covalent functionalization of the surface of bulk semiconductors such as silicon (111) (J. Phys. Chem. B 2006, 110 , 23898), and the substrates of oxides such as silica with self-assembly monolayers (Nano Lett. 2014, 14, 1354). The newly predicted 2D ferroelectric semiconductors possess high mobility, modest bandgaps, and distinct ferroelectricity that can be exploited for developing various heterostructural devices with desired functionalities. For example, we propose applications of the 2D materials as 2D ferroelectric field-effect transistors with ultrahigh on/off ratio, topological transistors with Dirac Fermions switchable between holes and electrons, ferroelectric junctions with ultrahigh electro-resistance, and multiferroic junctions for controlling spin by electric fields. All these heterostructural devices take advantage of the combination of high-mobility semiconductors with fast writing and nondestructive reading capability of nonvolatile memory, thereby holding great potential for the development of future multifunctional devices.

A triple quantum dot based nano-electromechanical memory device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pozner, R.; Lifshitz, E.; Solid State Institute, Technion-Israel Institute of Technology, Haifa 32000

Colloidal quantum dots (CQDs) are free-standing nano-structures with chemically tunable electronic properties. This tunability offers intriguing possibilities for nano-electromechanical devices. In this work, we consider a nano-electromechanical nonvolatile memory (NVM) device incorporating a triple quantum dot (TQD) cluster. The device operation is based on a bias induced motion of a floating quantum dot (FQD) located between two bound quantum dots (BQDs). The mechanical motion is used for switching between two stable states, “ON” and “OFF” states, where ligand-mediated effective interdot forces between the BQDs and the FQD serve to hold the FQD in each stable position under zero bias. Consideringmore » realistic microscopic parameters, our quantum-classical theoretical treatment of the TQD reveals the characteristics of the NVM.« less

Development of non-volatile semiconductor memory

NASA Technical Reports Server (NTRS)

Heikkila, W. W.

1979-01-01

A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

83 FR 22712 - Certain Non-Volatile Memory Devices and Products Containing the Same; Notice of Request for...

Federal Register 2010, 2011, 2012, 2013, 2014

2018-05-16

...Notice is hereby given that the presiding administrative law judge has issued a Final Initial Determination and Recommended Determination on Remedy and Bonding in the above-captioned investigation. The Commission is soliciting comments on public interest issues raised by the recommended relief, specifically a limited exclusion order directed to respondents Toshiba Corporation of Tokyo, Japan; Toshiba Memory Corporation of Tokyo, Japan; Toshiba America, Inc. of New York, New York; Toshiba America Electronic Components, Inc. of Irvine, California; Toshiba America Information Systems, Inc. of Irvine, California; and Toshiba Information Equipment (Philippines), Inc. of Binan, Philippines, and cease and desist orders directed to the domestic respondents. This notice is soliciting public interest comments from the public only. Parties are to file public interest submissions pursuant to Commission rules.

Hysteresis in Lanthanide Aluminum Oxides Observed by Fast Pulse CV Measurement

PubMed Central

Zhao, Chun; Zhao, Ce Zhou; Lu, Qifeng; Yan, Xiaoyi; Taylor, Stephen; Chalker, Paul R.

2014-01-01

Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). A novel characterization (pulse capacitance-voltage) method was proposed in detail. The pulse capacitance-voltage technique was employed to characterize oxide traps of high-k dielectrics based on the Metal Oxide Semiconductor (MOS) capacitor structure. The variation of flat-band voltages of the MOS structure was observed and discussed accordingly. Some interesting trapping/detrapping results related to the lanthanide aluminum oxide traps were identified for possible application in Flash memory technology. After understanding the trapping/detrapping mechanism of the high-k oxides, a solid foundation was prepared for further exploration into charge-trapping non-volatile memory in the future. PMID:28788225

Topological computation based on direct magnetic logic communication.

PubMed

Zhang, Shilei; Baker, Alexander A; Komineas, Stavros; Hesjedal, Thorsten

2015-10-28

Non-uniform magnetic domains with non-trivial topology, such as vortices and skyrmions, are proposed as superior state variables for nonvolatile information storage. So far, the possibility of logic operations using topological objects has not been considered. Here, we demonstrate numerically that the topology of the system plays a significant role for its dynamics, using the example of vortex-antivortex pairs in a planar ferromagnetic film. Utilising the dynamical properties and geometrical confinement, direct logic communication between the topological memory carriers is realised. This way, no additional magnetic-to-electrical conversion is required. More importantly, the information carriers can spontaneously travel up to ~300 nm, for which no spin-polarised current is required. The derived logic scheme enables topological spintronics, which can be integrated into large-scale memory and logic networks capable of complex computations.

Software/hardware distributed processing network supporting the Ada environment

NASA Astrophysics Data System (ADS)

Wood, Richard J.; Pryk, Zen

1993-09-01

A high-performance, fault-tolerant, distributed network has been developed, tested, and demonstrated. The network is based on the MIPS Computer Systems, Inc. R3000 Risc for processing, VHSIC ASICs for high speed, reliable, inter-node communications and compatible commercial memory and I/O boards. The network is an evolution of the Advanced Onboard Signal Processor (AOSP) architecture. It supports Ada application software with an Ada- implemented operating system. A six-node implementation (capable of expansion up to 256 nodes) of the RISC multiprocessor architecture provides 120 MIPS of scalar throughput, 96 Mbytes of RAM and 24 Mbytes of non-volatile memory. The network provides for all ground processing applications, has merit for space-qualified RISC-based network, and interfaces to advanced Computer Aided Software Engineering (CASE) tools for application software development.

Giant electroresistance of super-tetragonal BiFeO3-based ferroelectric tunnel junctions.

PubMed

Yamada, Hiroyuki; Garcia, Vincent; Fusil, Stéphane; Boyn, Sören; Marinova, Maya; Gloter, Alexandre; Xavier, Stéphane; Grollier, Julie; Jacquet, Eric; Carrétéro, Cécile; Deranlot, Cyrile; Bibes, Manuel; Barthélémy, Agnès

2013-06-25

Ferroelectric tunnel junctions enable a nondestructive readout of the ferroelectric state via a change of resistance induced by switching the ferroelectric polarization. We fabricated submicrometer solid-state ferroelectric tunnel junctions based on a recently discovered polymorph of BiFeO3 with giant axial ratio ("T-phase"). Applying voltage pulses to the junctions leads to the highest resistance changes (OFF/ON ratio >10,000) ever reported with ferroelectric tunnel junctions. Along with the good retention properties, this giant effect reinforces the interest in nonvolatile memories based on ferroelectric tunnel junctions. We also show that the changes in resistance scale with the nucleation and growth of ferroelectric domains in the ultrathin BiFeO3 (imaged by piezoresponse force microscopy), thereby suggesting potential as multilevel memory cells and memristors.

Realization of Minimum and Maximum Gate Function in Ta2O5-based Memristive Devices

NASA Astrophysics Data System (ADS)

Breuer, Thomas; Nielen, Lutz; Roesgen, Bernd; Waser, Rainer; Rana, Vikas; Linn, Eike

2016-04-01

Redox-based resistive switching devices (ReRAM) are considered key enablers for future non-volatile memory and logic applications. Functionally enhanced ReRAM devices could enable new hardware concepts, e.g. logic-in-memory or neuromorphic applications. In this work, we demonstrate the implementation of ReRAM-based fuzzy logic gates using Ta2O5 devices to enable analogous Minimum and Maximum operations. The realized gates consist of two anti-serially connected ReRAM cells offering two inputs and one output. The cells offer an endurance up to 106 cycles. By means of exemplary input signals, each gate functionality is verified and signal constraints are highlighted. This realization could improve the efficiency of analogous processing tasks such as sorting networks in the future.

Voltage switching of a VO{sub 2} memory metasurface using ionic gel

DOE Office of Scientific and Technical Information (OSTI.GOV)

Goldflam, M. D.; Liu, M. K.; Chapler, B. C.

2014-07-28

We demonstrate an electrolyte-based voltage tunable vanadium dioxide (VO{sub 2}) memory metasurface. Large spatial scale, low voltage, non-volatile switching of terahertz (THz) metasurface resonances is achieved through voltage application using an ionic gel to drive the insulator-to-metal transition in an underlying VO{sub 2} layer. Positive and negative voltage application can selectively tune the metasurface resonance into the “off” or “on” state by pushing the VO{sub 2} into a more conductive or insulating regime respectively. Compared to graphene based control devices, the relatively long saturation time of resonance modification in VO{sub 2} based devices suggests that this voltage-induced switching originates primarilymore » from electrochemical effects related to oxygen migration across the electrolyte–VO{sub 2} interface.« less

Resistive switching effect in the planar structure of all-printed, flexible and rewritable memory device based on advanced 2D nanocomposite of graphene quantum dots and white graphene flakes

NASA Astrophysics Data System (ADS)

Muqeet Rehman, Muhammad; Uddin Siddiqui, Ghayas; Kim, Sowon; Choi, Kyung Hyun

2017-08-01

Pursuit of the most appropriate materials and fabrication methods is essential for developing a reliable, rewritable and flexible memory device. In this study, we have proposed an advanced 2D nanocomposite of white graphene (hBN) flakes embedded with graphene quantum dots (GQDs) as the functional layer of a flexible memory device owing to their unique electrical, chemical and mechanical properties. Unlike the typical sandwich type structure of a memory device, we developed a cost effective planar structure, to simplify device fabrication and prevent sneak current. The entire device fabrication was carried out using printing technology followed by encapsulation in an atomically thin layer of aluminum oxide (Al2O3) for protection against environmental humidity. The proposed memory device exhibited attractive bipolar switching characteristics of high switching ratio, large electrical endurance and enhanced lifetime, without any crosstalk between adjacent memory cells. The as-fabricated device showed excellent durability for several bending cycles at various bending diameters without any degradation in bistable resistive states. The memory mechanism was deduced to be conductive filamentary; this was validated by illustrating the temperature dependence of bistable resistive states. Our obtained results pave the way for the execution of promising 2D material based next generation flexible and non-volatile memory (NVM) applications.

A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5-x/TaO2-x bilayer structures

NASA Astrophysics Data System (ADS)

Lee, Myoung-Jae; Lee, Chang Bum; Lee, Dongsoo; Lee, Seung Ryul; Chang, Man; Hur, Ji Hyun; Kim, Young-Bae; Kim, Chang-Jung; Seo, David H.; Seo, Sunae; Chung, U.-In; Yoo, In-Kyeong; Kim, Kinam

2011-08-01

Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaOx-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 1012. Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.