Method for refreshing a non-volatile memory

DOEpatents

Riekels, James E.; Schlesinger, Samuel

2008-11-04

A non-volatile memory and a method of refreshing a memory are described. The method includes allowing an external system to control refreshing operations within the memory. The memory may generate a refresh request signal and transmit the refresh request signal to the external system. When the external system finds an available time to process the refresh request, the external system acknowledges the refresh request and transmits a refresh acknowledge signal to the memory. The memory may also comprise a page register for reading and rewriting a data state back to the memory. The page register may comprise latches in lieu of supplemental non-volatile storage elements, thereby conserving real estate within the memory.

Memory Forensics: Review of Acquisition and Analysis Techniques

DTIC Science & Technology

2013-11-01

Management Overview Processes running on modern multitasking operating systems operate on an abstraction of RAM, called virtual memory [7]. In these systems...information such as user names, email addresses and passwords [7]. Analysts also use tools such as WinHex to identify headers or other suspicious data within

78 FR 23866 - Airworthiness Directives; the Boeing Company

Federal Register 2010, 2011, 2012, 2013, 2014

2013-04-23

... operational software in the cabin management system, and loading new software into the mass memory card. The...-200 and -300 series airplanes. The proposed AD would have required installing new operational software in the cabin management system, and loading new software into the mass memory card. Since the...

Through the Immune Looking Glass: A Model for Brain Memory Strategies

PubMed Central

Sánchez-Ramón, Silvia; Faure, Florence

2016-01-01

The immune system (IS) and the central nervous system (CNS) are complex cognitive networks involved in defining the identity (self) of the individual through recognition and memory processes that enable one to anticipate responses to stimuli. Brain memory has traditionally been classified as either implicit or explicit on psychological and anatomical grounds, with reminiscences of the evolutionarily-based innate-adaptive IS responses. Beyond the multineuronal networks of the CNS, we propose a theoretical model of brain memory integrating the CNS as a whole. This is achieved by analogical reasoning between the operational rules of recognition and memory processes in both systems, coupled to an evolutionary analysis. In this new model, the hippocampus is no longer specifically ascribed to explicit memory but rather it both becomes part of the innate (implicit) memory system and tightly controls the explicit memory system. Alike the antigen presenting cells for the IS, the hippocampus would integrate transient and pseudo-specific (i.e., danger-fear) memories and would drive the formation of long-term and highly specific or explicit memories (i.e., the taste of the Proust’s madeleine cake) by the more complex and recent, evolutionarily speaking, neocortex. Experimental and clinical evidence is provided to support the model. We believe that the singularity of this model’s approximation could help to gain a better understanding of the mechanisms operating in brain memory strategies from a large-scale network perspective. PMID:26869886

Method and apparatus for faulty memory utilization

DOEpatents

Cher, Chen-Yong; Andrade Costa, Carlos H.; Park, Yoonho; Rosenburg, Bryan S.; Ryu, Kyung D.

2016-04-19

A method for faulty memory utilization in a memory system includes: obtaining information regarding memory health status of at least one memory page in the memory system; determining an error tolerance of the memory page when the information regarding memory health status indicates that a failure is predicted to occur in an area of the memory system affecting the memory page; initiating a migration of data stored in the memory page when it is determined that the data stored in the memory page is non-error-tolerant; notifying at least one application regarding a predicted operating system failure and/or a predicted application failure when it is determined that data stored in the memory page is non-error-tolerant and cannot be migrated; and notifying at least one application regarding the memory failure predicted to occur when it is determined that data stored in the memory page is error-tolerant.

RAPID: A random access picture digitizer, display, and memory system

NASA Technical Reports Server (NTRS)

Yakimovsky, Y.; Rayfield, M.; Eskenazi, R.

1976-01-01

RAPID is a system capable of providing convenient digital analysis of video data in real-time. It has two modes of operation. The first allows for continuous digitization of an EIA RS-170 video signal. Each frame in the video signal is digitized and written in 1/30 of a second into RAPID's internal memory. The second mode leaves the content of the internal memory independent of the current input video. In both modes of operation the image contained in the memory is used to generate an EIA RS-170 composite video output signal representing the digitized image in the memory so that it can be displayed on a monitor.

Memory protection

NASA Technical Reports Server (NTRS)

Denning, Peter J.

1988-01-01

Accidental overwriting of files or of memory regions belonging to other programs, browsing of personal files by superusers, Trojan horses, and viruses are examples of breakdowns in workstations and personal computers that would be significantly reduced by memory protection. Memory protection is the capability of an operating system and supporting hardware to delimit segments of memory, to control whether segments can be read from or written into, and to confine accesses of a program to its segments alone. The absence of memory protection in many operating systems today is the result of a bias toward a narrow definition of performance as maximum instruction-execution rate. A broader definition, including the time to get the job done, makes clear that cost of recovery from memory interference errors reduces expected performance. The mechanisms of memory protection are well understood, powerful, efficient, and elegant. They add to performance in the broad sense without reducing instruction execution rate.

System for processing an encrypted instruction stream in hardware

DOE Office of Scientific and Technical Information (OSTI.GOV)

Griswold, Richard L.; Nickless, William K.; Conrad, Ryan C.

A system and method of processing an encrypted instruction stream in hardware is disclosed. Main memory stores the encrypted instruction stream and unencrypted data. A central processing unit (CPU) is operatively coupled to the main memory. A decryptor is operatively coupled to the main memory and located within the CPU. The decryptor decrypts the encrypted instruction stream upon receipt of an instruction fetch signal from a CPU core. Unencrypted data is passed through to the CPU core without decryption upon receipt of a data fetch signal.

Declarative and nondeclarative memory: multiple brain systems supporting learning and memory.

PubMed

Squire, L R

1992-01-01

Abstract The topic of multiple forms of memory is considered from a biological point of view. Fact-and-event (declarative, explicit) memory is contrasted with a collection of non conscious (non-declarative, implicit) memory abilities including skills and habits, priming, and simple conditioning. Recent evidence is reviewed indicating that declarative and non declarative forms of memory have different operating characteristics and depend on separate brain systems. A brain-systems framework for understanding memory phenomena is developed in light of lesion studies involving rats, monkeys, and humans, as well as recent studies with normal humans using the divided visual field technique, event-related potentials, and positron emission tomography (PET).

Evaluation of the Cedar memory system: Configuration of 16 by 16

NASA Technical Reports Server (NTRS)

Gallivan, K.; Jalby, W.; Wijshoff, H.

1991-01-01

Some basic results on the performance of the Cedar multiprocessor system are presented. Empirical results on the 16 processor 16 memory bank system configuration, which show the behavior of the Cedar system under different modes of operation are presented.

New Maximally Entangled States for Pattern-Association Through Evolutionary Processes in a Two-Qubit System

NASA Astrophysics Data System (ADS)

Singh, Manu Pratap; Rajput, Balwant S.

2017-04-01

New set of maximally entangled states (Singh-Rajput MES), constituting orthonormal eigen bases, has been revisited and its superiority and suitability in pattern-association (Quantum Associative Memory, QuAM) have been demonstrated. Using these MES as memory states in the evolutionary process of pattern storage in a two-qubit system, it has been shown that the first two states of Singh-Rajput MES are useful for storing the pattern |11> and the last two of these MES are useful in storing the pattern |10> Recall operations of quantum associate memory (QuAM) have been conducted through evolutionary process in terms of unitary operators by separately choosing Singh-Rajput MES and Bell's MES as memory states and it has been shown that Singh-Rajput MES as valid memory states for recalling the patterns in a two-qubit system are much more suitable than Bell's MES.

Distributed Saturation

NASA Technical Reports Server (NTRS)

Chung, Ming-Ying; Ciardo, Gianfranco; Siminiceanu, Radu I.

2007-01-01

The Saturation algorithm for symbolic state-space generation, has been a recent break-through in the exhaustive veri cation of complex systems, in particular globally-asyn- chronous/locally-synchronous systems. The algorithm uses a very compact Multiway Decision Diagram (MDD) encoding for states and the fastest symbolic exploration algo- rithm to date. The distributed version of Saturation uses the overall memory available on a network of workstations (NOW) to efficiently spread the memory load during the highly irregular exploration. A crucial factor in limiting the memory consumption during the symbolic state-space generation is the ability to perform garbage collection to free up the memory occupied by dead nodes. However, garbage collection over a NOW requires a nontrivial communication overhead. In addition, operation cache policies become critical while analyzing large-scale systems using the symbolic approach. In this technical report, we develop a garbage collection scheme and several operation cache policies to help on solving extremely complex systems. Experiments show that our schemes improve the performance of the original distributed implementation, SmArTNow, in terms of time and memory efficiency.

Effect of circadian phase on memory acquisition and recall: operant conditioning vs. classical conditioning.

PubMed

Garren, Madeleine V; Sexauer, Stephen B; Page, Terry L

2013-01-01

There have been several studies on the role of circadian clocks in the regulation of associative learning and memory processes in both vertebrate and invertebrate species. The results have been quite variable and at present it is unclear to what extent the variability observed reflects species differences or differences in methodology. Previous results have shown that following differential classical conditioning in the cockroach, Rhyparobia maderae, in an olfactory discrimination task, formation of the short-term and long-term memory is under strict circadian control. In contrast, there appeared to be no circadian regulation of the ability to recall established memories. In the present study, we show that following operant conditioning of the same species in a very similar olfactory discrimination task, there is no impact of the circadian system on either short-term or long-term memory formation. On the other hand, ability to recall established memories is strongly tied to the circadian phase of training. On the basis of these data and those previously reported for phylogenetically diverse species, it is suggested that there may be fundamental differences in the way the circadian system regulates learning and memory in classical and operant conditioning.

Effect of Circadian Phase on Memory Acquisition and Recall: Operant Conditioning vs. Classical Conditioning

PubMed Central

Garren, Madeleine V.; Sexauer, Stephen B.; Page, Terry L.

2013-01-01

There have been several studies on the role of circadian clocks in the regulation of associative learning and memory processes in both vertebrate and invertebrate species. The results have been quite variable and at present it is unclear to what extent the variability observed reflects species differences or differences in methodology. Previous results have shown that following differential classical conditioning in the cockroach, Rhyparobia maderae, in an olfactory discrimination task, formation of the short-term and long-term memory is under strict circadian control. In contrast, there appeared to be no circadian regulation of the ability to recall established memories. In the present study, we show that following operant conditioning of the same species in a very similar olfactory discrimination task, there is no impact of the circadian system on either short-term or long-term memory formation. On the other hand, ability to recall established memories is strongly tied to the circadian phase of training. On the basis of these data and those previously reported for phylogenetically diverse species, it is suggested that there may be fundamental differences in the way the circadian system regulates learning and memory in classical and operant conditioning. PMID:23533587

Low latency memory access and synchronization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.

A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processormore » only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.« less

Low latency memory access and synchronization

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blumrich, Matthias A.; Chen, Dong; Coteus, Paul W.

A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Bach processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processormore » only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.« less

Flash memory management system and method utilizing multiple block list windows

NASA Technical Reports Server (NTRS)

Chow, James (Inventor); Gender, Thomas K. (Inventor)

2005-01-01

The present invention provides a flash memory management system and method with increased performance. The flash memory management system provides the ability to efficiently manage and allocate flash memory use in a way that improves reliability and longevity, while maintaining good performance levels. The flash memory management system includes a free block mechanism, a disk maintenance mechanism, and a bad block detection mechanism. The free block mechanism provides efficient sorting of free blocks to facilitate selecting low use blocks for writing. The disk maintenance mechanism provides for the ability to efficiently clean flash memory blocks during processor idle times. The bad block detection mechanism provides the ability to better detect when a block of flash memory is likely to go bad. The flash status mechanism stores information in fast access memory that describes the content and status of the data in the flash disk. The new bank detection mechanism provides the ability to automatically detect when new banks of flash memory are added to the system. Together, these mechanisms provide a flash memory management system that can improve the operational efficiency of systems that utilize flash memory.

GPU-Accelerated Forward and Back-Projections with Spatially Varying Kernels for 3D DIRECT TOF PET Reconstruction.

PubMed

Ha, S; Matej, S; Ispiryan, M; Mueller, K

2013-02-01

We describe a GPU-accelerated framework that efficiently models spatially (shift) variant system response kernels and performs forward- and back-projection operations with these kernels for the DIRECT (Direct Image Reconstruction for TOF) iterative reconstruction approach. Inherent challenges arise from the poor memory cache performance at non-axis aligned TOF directions. Focusing on the GPU memory access patterns, we utilize different kinds of GPU memory according to these patterns in order to maximize the memory cache performance. We also exploit the GPU instruction-level parallelism to efficiently hide long latencies from the memory operations. Our experiments indicate that our GPU implementation of the projection operators has slightly faster or approximately comparable time performance than FFT-based approaches using state-of-the-art FFTW routines. However, most importantly, our GPU framework can also efficiently handle any generic system response kernels, such as spatially symmetric and shift-variant as well as spatially asymmetric and shift-variant, both of which an FFT-based approach cannot cope with.

GPU-Accelerated Forward and Back-Projections With Spatially Varying Kernels for 3D DIRECT TOF PET Reconstruction

NASA Astrophysics Data System (ADS)

Ha, S.; Matej, S.; Ispiryan, M.; Mueller, K.

2013-02-01

We describe a GPU-accelerated framework that efficiently models spatially (shift) variant system response kernels and performs forward- and back-projection operations with these kernels for the DIRECT (Direct Image Reconstruction for TOF) iterative reconstruction approach. Inherent challenges arise from the poor memory cache performance at non-axis aligned TOF directions. Focusing on the GPU memory access patterns, we utilize different kinds of GPU memory according to these patterns in order to maximize the memory cache performance. We also exploit the GPU instruction-level parallelism to efficiently hide long latencies from the memory operations. Our experiments indicate that our GPU implementation of the projection operators has slightly faster or approximately comparable time performance than FFT-based approaches using state-of-the-art FFTW routines. However, most importantly, our GPU framework can also efficiently handle any generic system response kernels, such as spatially symmetric and shift-variant as well as spatially asymmetric and shift-variant, both of which an FFT-based approach cannot cope with.

A room-temperature non-volatile CNT-based molecular memory cell

NASA Astrophysics Data System (ADS)

Ye, Senbin; Jing, Qingshen; Han, Ray P. S.

2013-04-01

Recent experiments with a carbon nanotube (CNT) system confirmed that the innertube can oscillate back-and-forth even under a room-temperature excitation. This demonstration of relative motion suggests that it is now feasible to build a CNT-based molecular memory cell (MC), and the key to bring the concept to reality is the precision control of the moving tube for sustained and reliable read/write (RW) operations. Here, we show that by using a 2-section outertube design, we are able to suitably recalibrate the system energetics and obtain the designed performance characteristics of a MC. Further, the resulting energy modification enables the MC to operate as a non-volatile memory element at room temperatures. Our paper explores a fundamental understanding of a MC and its response at the molecular level to roadmap a novel approach in memory technologies that can be harnessed to overcome the miniaturization limit and memory volatility in memory technologies.

NRAM: a disruptive carbon-nanotube resistance-change memory.

PubMed

Gilmer, D C; Rueckes, T; Cleveland, L

2018-04-03

Advanced memory technology based on carbon nanotubes (CNTs) (NRAM) possesses desired properties for implementation in a host of integrated systems due to demonstrated advantages of its operation including high speed (nanotubes can switch state in picoseconds), high endurance (over a trillion), and low power (with essential zero standby power). The applicable integrated systems for NRAM have markets that will see compound annual growth rates (CAGR) of over 62% between 2018 and 2023, with an embedded systems CAGR of 115% in 2018-2023 (http://bccresearch.com/pressroom/smc/bcc-research-predicts:-nram-(finally)-to-revolutionize-computer-memory). These opportunities are helping drive the realization of a shift from silicon-based to carbon-based (NRAM) memories. NRAM is a memory cell made up of an interlocking matrix of CNTs, either touching or slightly separated, leading to low or higher resistance states respectively. The small movement of atoms, as opposed to moving electrons for traditional silicon-based memories, renders NRAM with a more robust endurance and high temperature retention/operation which, along with high speed/low power, is expected to blossom in this memory technology to be a disruptive replacement for the current status quo of DRAM (dynamic RAM), SRAM (static RAM), and NAND flash memories.

NRAM: a disruptive carbon-nanotube resistance-change memory

NASA Astrophysics Data System (ADS)

Gilmer, D. C.; Rueckes, T.; Cleveland, L.

2018-04-01

Advanced memory technology based on carbon nanotubes (CNTs) (NRAM) possesses desired properties for implementation in a host of integrated systems due to demonstrated advantages of its operation including high speed (nanotubes can switch state in picoseconds), high endurance (over a trillion), and low power (with essential zero standby power). The applicable integrated systems for NRAM have markets that will see compound annual growth rates (CAGR) of over 62% between 2018 and 2023, with an embedded systems CAGR of 115% in 2018-2023 (http://bccresearch.com/pressroom/smc/bcc-research-predicts:-nram-(finally)-to-revolutionize-computer-memory). These opportunities are helping drive the realization of a shift from silicon-based to carbon-based (NRAM) memories. NRAM is a memory cell made up of an interlocking matrix of CNTs, either touching or slightly separated, leading to low or higher resistance states respectively. The small movement of atoms, as opposed to moving electrons for traditional silicon-based memories, renders NRAM with a more robust endurance and high temperature retention/operation which, along with high speed/low power, is expected to blossom in this memory technology to be a disruptive replacement for the current status quo of DRAM (dynamic RAM), SRAM (static RAM), and NAND flash memories.

A study of the viability of exploiting memory content similarity to improve resilience to memory errors

DOE PAGES

Levy, Scott; Ferreira, Kurt B.; Bridges, Patrick G.; ...

2014-12-09

Building the next-generation of extreme-scale distributed systems will require overcoming several challenges related to system resilience. As the number of processors in these systems grow, the failure rate increases proportionally. One of the most common sources of failure in large-scale systems is memory. In this paper, we propose a novel runtime for transparently exploiting memory content similarity to improve system resilience by reducing the rate at which memory errors lead to node failure. We evaluate the viability of this approach by examining memory snapshots collected from eight high-performance computing (HPC) applications and two important HPC operating systems. Based on themore » characteristics of the similarity uncovered, we conclude that our proposed approach shows promise for addressing system resilience in large-scale systems.« less

Priming Effects in Word-Fragment Completion Are Independent of Recognition Memory.

ERIC Educational Resources Information Center

Tulving, Endel; And Others

1982-01-01

Since the priming effects described in this article were independent of episodic memory, and since there were problems with their interpretation in terms of modifications of semantic memory, it is felt that they reflect the operation of some other, as yet little understood, memory system. (Author/PN)

Shape memory polymer actuator and catheter

DOEpatents

Maitland, Duncan J.; Lee, Abraham P.; Schumann, Daniel L.; Matthews, Dennis L.; Decker, Derek E.; Jungreis, Charles A.

2004-05-25

An actuator system is provided for acting upon a material in a vessel. The system includes an optical fiber and a shape memory polymer material operatively connected to the optical fiber. The shape memory polymer material is adapted to move from a first shape for moving through said vessel to a second shape where it can act upon said material.

Shape memory polymer actuator and catheter

DOEpatents

Maitland, Duncan J.; Lee, Abraham P.; Schumann, Daniel L.; Matthews, Dennis L.; Decker, Derek E.; Jungreis, Charles A.

2007-11-06

An actuator system is provided for acting upon a material in a vessel. The system includes an optical fiber and a shape memory polymer material operatively connected to the optical fiber. The shape memory polymer material is adapted to move from a first shape for moving through said vessel to a second shape where it can act upon said material.

Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong (Inventor); Herath, Jeffrey A. (Inventor)

2010-01-01

An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.

From Brown-Peterson to continual distractor via operation span: A SIMPLE account of complex span.

PubMed

Neath, Ian; VanWormer, Lisa A; Bireta, Tamra J; Surprenant, Aimée M

2014-09-01

Three memory tasks-Brown-Peterson, complex span, and continual distractor-all alternate presentation of a to-be-remembered item and a distractor activity, but each task is associated with a different memory system, short-term memory, working memory, and long-term memory, respectively. SIMPLE, a relative local distinctiveness model, has previously been fit to data from both the Brown-Peterson and continual distractor tasks; here we use the same version of the model to fit data from a complex span task. Despite the many differences between the tasks, including unpredictable list length, SIMPLE fit the data well. Because SIMPLE posits a single memory system, these results constitute yet another demonstration that performance on tasks originally thought to tap different memory systems can be explained without invoking multiple memory systems.

Memory Interference as a Determinant of Language Comprehension

PubMed Central

Van Dyke, Julie A.; Johns, Clinton L.

2012-01-01

The parameters of the human memory system constrain the operation of language comprehension processes. In the memory literature, both decay and interference have been proposed as causes of forgetting; however, while there is a long history of research establishing the nature of interference effects in memory, the effects of decay are much more poorly supported. Nevertheless, research investigating the limitations of the human sentence processing mechanism typically focus on decay-based explanations, emphasizing the role of capacity, while the role of interference has received comparatively little attention. This paper reviews both accounts of difficulty in language comprehension by drawing direct connections to research in the memory domain. Capacity-based accounts are found to be untenable, diverging substantially from what is known about the operation of the human memory system. In contrast, recent research investigating comprehension difficulty using a retrieval-interference paradigm is shown to be wholly consistent with both behavioral and neuropsychological memory phenomena. The implications of adopting a retrieval-interference approach to investigating individual variation in language comprehension are discussed. PMID:22773927

Context controls access to working and reference memory in the pigeon (Columba livia).

PubMed

Roberts, William A; Macpherson, Krista; Strang, Caroline

2016-01-01

The interaction between working and reference memory systems was examined under conditions in which salient contextual cues were presented during memory retrieval. Ambient colored lights (red or green) bathed the operant chamber during the presentation of comparison stimuli in delayed matching-to-sample training (working memory) and during the presentation of the comparison stimuli as S+ and S- cues in discrimination training (reference memory). Strong competition between memory systems appeared when the same contextual cue appeared during working and reference memory training. When different contextual cues were used, however, working memory was completely protected from reference memory interference. © 2016 Society for the Experimental Analysis of Behavior.

Detailed Design and Implementation of a Multiprogramming Operating System for Sixteen-Bit Microprocessors.

DTIC Science & Technology

1983-12-01

4 Multiuser Support ...... .......... 11-5 User Interface . .. .. ................ .. 11- 7 Inter -user Communications ................ 11- 7 Memory...user will greatly help facilitate the learning process. Inter -User Communication The inter -user communications of the operating system can be done using... inter -user communications would be met by using one or both of them. AMemory and File Management Memory and file management is concerned with four basic

Memory: Organization and Control

PubMed Central

Eichenbaum, Howard

2017-01-01

A major goal of memory research is to understand how cognitive processes in memory are supported at the level of brain systems and network representations. Especially promising in this direction are new findings in humans and animals that converge in indicating a key role for the hippocampus in the systematic organization of memories. New findings also indicate that the prefrontal cortex may play an equally important role in the active control of memory organization during both encoding and retrieval. Observations about the dialog between the hippocampus and prefrontal cortex provide new insights into the operation of the larger brain system that serves memory. PMID:27687117

A Network Architecture for Data-Driven Systems

DTIC Science & Technology

1985-07-01

ELABORATION. ..... ..... 26 Real - Time Operating System . ....... ......... 26 Secondary Memory Utilization. ........ ....... 26 Data Flow Graphical...discussions followed by a flight simulator exam~ple. REAL - TIME OPERATING SYSTEM An operating system needs to be designed exclusively for real-time...Assessment. (SDWA) module. The SDWA module is tightly coupled to the real - time operating system . This module must determine the sensitivity to

A fast and low-power microelectromechanical system-based non-volatile memory device

PubMed Central

Lee, Sang Wook; Park, Seung Joo; Campbell, Eleanor E. B.; Park, Yung Woo

2011-01-01

Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices. PMID:21364559

[Classification of memory systems: a revision].

PubMed

Agrest, M

2001-12-01

The present paper exposes the arguments against considering memory as a monolytic entity and how is it to be divided into several systems in order to understand its operation. Historically this division was acknowledge by different authors but in the last few decades it received the confirmation from the scientific research. The most accepted taxonomy establishes the existence of two major memory systems: declarative and non declarative memory. The article also presents the arguments for and against this kind of division, as well as an alternative classification in five major systems: procedural, perceptual representation, semantic, primary and episodic.

Addressable configurations of DNA nanostructures for rewritable memory

PubMed Central

Levchenko, Oksana; Patel, Dhruv S.; MacIsaac, Molly

2017-01-01

Abstract DNA serves as nature's information storage molecule, and has been the primary focus of engineered systems for biological computing and data storage. Here we combine recent efforts in DNA self-assembly and toehold-mediated strand displacement to develop a rewritable multi-bit DNA memory system. The system operates by encoding information in distinct and reversible conformations of a DNA nanoswitch and decoding by gel electrophoresis. We demonstrate a 5-bit system capable of writing, erasing, and rewriting binary representations of alphanumeric symbols, as well as compatibility with ‘OR’ and ‘AND’ logic operations. Our strategy is simple to implement, requiring only a single mixing step at room temperature for each operation and standard gel electrophoresis to read the data. We envision such systems could find use in covert product labeling and barcoding, as well as secure messaging and authentication when combined with previously developed encryption strategies. Ultimately, this type of memory has exciting potential in biomedical sciences as data storage can be coupled to sensing of biological molecules. PMID:28977499

Stochastic memory: getting memory out of noise

NASA Astrophysics Data System (ADS)

Stotland, Alexander; di Ventra, Massimiliano

2011-03-01

Memory circuit elements, namely memristors, memcapacitors and meminductors, can store information without the need of a power source. These systems are generally defined in terms of deterministic equations of motion for the state variables that are responsible for memory. However, in real systems noise sources can never be eliminated completely. One would then expect noise to be detrimental for memory. Here, we show that under specific conditions on the noise intensity memory can actually be enhanced. We illustrate this phenomenon using a physical model of a memristor in which the addition of white noise into the state variable equation improves the memory and helps the operation of the system. We discuss under which conditions this effect can be realized experimentally, discuss its implications on existing memory systems discussed in the literature, and also analyze the effects of colored noise. Work supported in part by NSF.

A Decision Model for Selection of Microcomputers and Operating Systems.

DTIC Science & Technology

1984-06-01

is resilting in application software (for microccmputers) being developed almost exclu- sively tor the IBM PC and compatiole systems. NAVDAC ielt that...location can be indepen- dently accessed. RAN memory is also often called read/ write memory, hecause new information can be written into and read from...when power is lost; this is also read/ write memory. Bubble memory, however, has significantly slower access times than RAM or RON and also is not preva

Working Memory Systems in the Rat.

PubMed

Bratch, Alexander; Kann, Spencer; Cain, Joshua A; Wu, Jie-En; Rivera-Reyes, Nilda; Dalecki, Stefan; Arman, Diana; Dunn, Austin; Cooper, Shiloh; Corbin, Hannah E; Doyle, Amanda R; Pizzo, Matthew J; Smith, Alexandra E; Crystal, Jonathon D

2016-02-08

A fundamental feature of memory in humans is the ability to simultaneously work with multiple types of information using independent memory systems. Working memory is conceptualized as two independent memory systems under executive control [1, 2]. Although there is a long history of using the term "working memory" to describe short-term memory in animals, it is not known whether multiple, independent memory systems exist in nonhumans. Here, we used two established short-term memory approaches to test the hypothesis that spatial and olfactory memory operate as independent working memory resources in the rat. In the olfactory memory task, rats chose a novel odor from a gradually incrementing set of old odors [3]. In the spatial memory task, rats searched for a depleting food source at multiple locations [4]. We presented rats with information to hold in memory in one domain (e.g., olfactory) while adding a memory load in the other domain (e.g., spatial). Control conditions equated the retention interval delay without adding a second memory load. In a further experiment, we used proactive interference [5-7] in the spatial domain to compromise spatial memory and evaluated the impact of adding an olfactory memory load. Olfactory and spatial memory are resistant to interference from the addition of a memory load in the other domain. Our data suggest that olfactory and spatial memory draw on independent working memory systems in the rat. Copyright © 2016 Elsevier Ltd. All rights reserved.

A Distributed Operating System for BMD Applications.

DTIC Science & Technology

1982-01-01

Defense) applications executing on distributed hardware with local and shared memories. The objective was to develop real - time operating system functions...make the Basic Real - Time Operating System , and the set of new EPL language primitives that provide BMD application processes with efficient mechanisms

Acute Sleep Deprivation Blocks Short- and Long-Term Operant Memory in Aplysia

PubMed Central

Krishnan, Harini C.; Gandour, Catherine E.; Ramos, Joshua L.; Wrinkle, Mariah C.; Sanchez-Pacheco, Joseph J.; Lyons, Lisa C.

2016-01-01

Study Objectives: Insufficient sleep in individuals appears increasingly common due to the demands of modern work schedules and technology use. Consequently, there is a growing need to understand the interactions between sleep deprivation and memory. The current study determined the effects of acute sleep deprivation on short and long-term associative memory using the marine mollusk Aplysia californica, a relatively simple model system well known for studies of learning and memory. Methods: Aplysia were sleep deprived for 9 hours using context changes and tactile stimulation either prior to or after training for the operant learning paradigm, learning that food is inedible (LFI). The effects of sleep deprivation on short-term (STM) and long-term memory (LTM) were assessed. Results: Acute sleep deprivation prior to LFI training impaired the induction of STM and LTM with persistent effects lasting at least 24 h. Sleep deprivation immediately after training blocked the consolidation of LTM. However, sleep deprivation following the period of molecular consolidation did not affect memory recall. Memory impairments were independent of handling-induced stress, as daytime handled control animals demonstrated no memory deficits. Additional training immediately after sleep deprivation failed to rescue the induction of memory, but additional training alleviated the persistent impairment in memory induction when training occurred 24 h following sleep deprivation. Conclusions: Acute sleep deprivation inhibited the induction and consolidation, but not the recall of memory. These behavioral studies establish Aplysia as an effective model system for studying the interactions between sleep and memory formation. Citation: Krishnan HC, Gandour CE, Ramos JL, Wrinkle MC, Sanchez-Pacheco JJ, Lyons LC. Acute sleep deprivation blocks short- and long-term operant memory in Aplysia. SLEEP 2016;39(12):2161–2171. PMID:27748243

OS friendly microprocessor architecture: Hardware level computer security

NASA Astrophysics Data System (ADS)

Jungwirth, Patrick; La Fratta, Patrick

2016-05-01

We present an introduction to the patented OS Friendly Microprocessor Architecture (OSFA) and hardware level computer security. Conventional microprocessors have not tried to balance hardware performance and OS performance at the same time. Conventional microprocessors have depended on the Operating System for computer security and information assurance. The goal of the OS Friendly Architecture is to provide a high performance and secure microprocessor and OS system. We are interested in cyber security, information technology (IT), and SCADA control professionals reviewing the hardware level security features. The OS Friendly Architecture is a switched set of cache memory banks in a pipeline configuration. For light-weight threads, the memory pipeline configuration provides near instantaneous context switching times. The pipelining and parallelism provided by the cache memory pipeline provides for background cache read and write operations while the microprocessor's execution pipeline is running instructions. The cache bank selection controllers provide arbitration to prevent the memory pipeline and microprocessor's execution pipeline from accessing the same cache bank at the same time. This separation allows the cache memory pages to transfer to and from level 1 (L1) caching while the microprocessor pipeline is executing instructions. Computer security operations are implemented in hardware. By extending Unix file permissions bits to each cache memory bank and memory address, the OSFA provides hardware level computer security.

Method for prefetching non-contiguous data structures

DOEpatents

Blumrich, Matthias A [Ridgefield, CT; Chen, Dong [Croton On Hudson, NY; Coteus, Paul W [Yorktown Heights, NY; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Heidelberger, Philip [Cortlandt Manor, NY; Hoenicke, Dirk [Ossining, NY; Ohmacht, Martin [Brewster, NY; Steinmacher-Burow, Burkhard D [Mount Kisco, NY; Takken, Todd E [Mount Kisco, NY; Vranas, Pavlos M [Bedford Hills, NY

2009-05-05

A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple perfecting for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefect rather than some other predictive algorithm. This enables hardware to effectively prefect memory access patterns that are non-contiguous, but repetitive.

The Effect of NUMA Tunings on CPU Performance

NASA Astrophysics Data System (ADS)

Hollowell, Christopher; Caramarcu, Costin; Strecker-Kellogg, William; Wong, Antonio; Zaytsev, Alexandr

2015-12-01

Non-Uniform Memory Access (NUMA) is a memory architecture for symmetric multiprocessing (SMP) systems where each processor is directly connected to separate memory. Indirect access to other CPU's (remote) RAM is still possible, but such requests are slower as they must also pass through that memory's controlling CPU. In concert with a NUMA-aware operating system, the NUMA hardware architecture can help eliminate the memory performance reductions generally seen in SMP systems when multiple processors simultaneously attempt to access memory. The x86 CPU architecture has supported NUMA for a number of years. Modern operating systems such as Linux support NUMA-aware scheduling, where the OS attempts to schedule a process to the CPU directly attached to the majority of its RAM. In Linux, it is possible to further manually tune the NUMA subsystem using the numactl utility. With the release of Red Hat Enterprise Linux (RHEL) 6.3, the numad daemon became available in this distribution. This daemon monitors a system's NUMA topology and utilization, and automatically makes adjustments to optimize locality. As the number of cores in x86 servers continues to grow, efficient NUMA mappings of processes to CPUs/memory will become increasingly important. This paper gives a brief overview of NUMA, and discusses the effects of manual tunings and numad on the performance of the HEPSPEC06 benchmark, and ATLAS software.

Quantum memory operations in a flux qubit - spin ensemble hybrid system

NASA Astrophysics Data System (ADS)

Saito, S.; Zhu, X.; Amsuss, R.; Matsuzaki, Y.; Kakuyanagi, K.; Shimo-Oka, T.; Mizuochi, N.; Nemoto, K.; Munro, W. J.; Semba, K.

2014-03-01

Superconducting quantum bits (qubits) are one of the most promising candidates for a future large-scale quantum processor. However for larger scale realizations the currently reported coherence times of these macroscopic objects (superconducting qubits) has not yet reached those of microscopic systems (electron spins, nuclear spins, etc). In this context, a superconductor-spin ensemble hybrid system has attracted considerable attention. The spin ensemble could operate as a quantum memory for superconducting qubits. We have experimentally demonstrated quantum memory operations in a superconductor-diamond hybrid system. An excited state and a superposition state prepared in the flux qubit can be transferred to, stored in and retrieved from the NV spin ensemble in diamond. From these experiments, we have found the coherence time of the spin ensemble is limited by the inhomogeneous broadening of the electron spin (4.4 MHz) and by the hyperfine coupling to nitrogen nuclear spins (2.3 MHz). In the future, spin echo techniques could eliminate these effects and elongate the coherence time. Our results are a significant first step in utilizing the spin ensemble as long-lived quantum memory for superconducting flux qubits. This work was supported by the FIRST program and NICT.

Development of 3-Year Roadmap to Transform the Discipline of Systems Engineering

DTIC Science & Technology

2010-03-31

quickly humans could physically construct them. Indeed, magnetic core memory was entirely constructed by human hands until it was superseded by...For their mainframe computers, IBM develops the applications, operating system, computer hardware and microprocessors (off the shelf standard memory ...processor developers work on potential computational and memory pipelines to support the required performance capabilities and use the available transistors

Plated wire memory subsystem

NASA Technical Reports Server (NTRS)

Carpenter, K. H.

1974-01-01

The design, construction, and test history of a 4096 word by 18 bit random access NDRO Plated Wire Memory for use in conjunction with a spacecraft input/output and central processing unit is reported. A technical and functional description is given along with diagrams illustrating layout and systems operation. Test data is shown on the procedures and results of system level and memory stack testing, and hybrid circuit screening. A comparison of the most significant physical and performance characteristics of the memory unit versus the specified requirements is also included.

Applications of Singh-Rajput Mes in Recall Operations of Quantum Associative Memory for a Two- Qubit System

NASA Astrophysics Data System (ADS)

Singh, Manu Pratap; Rajput, B. S.

2016-03-01

Recall operations of quantum associative memory (QuAM) have been conducted separately through evolutionary as well as non-evolutionary processes in terms of unitary and non- unitary operators respectively by separately choosing our recently derived maximally entangled states (Singh-Rajput MES) and Bell's MES as memory states for various queries and it has been shown that in each case the choices of Singh-Rajput MES as valid memory states are much more suitable than those of Bell's MES. it has been demonstrated that in both the types of recall processes the first and the fourth states of Singh-Rajput MES are most suitable choices as memory states for the queries `11' and `00' respectively while none of the Bell's MES is a suitable choice as valid memory state in these recall processes. It has been demonstrated that all the four states of Singh-Rajput MES are suitable choice as valid memory states for the queries `1?', `?1', `?0' and `0?' while none of the Bell's MES is suitable choice as the valid memory state for these queries also.

A model for memory systems based on processing modes rather than consciousness.

PubMed

Henke, Katharina

2010-07-01

Prominent models of human long-term memory distinguish between memory systems on the basis of whether learning and retrieval occur consciously or unconsciously. Episodic memory formation requires the rapid encoding of associations between different aspects of an event which, according to these models, depends on the hippocampus and on consciousness. However, recent evidence indicates that the hippocampus mediates rapid associative learning with and without consciousness in humans and animals, for long-term and short-term retention. Consciousness seems to be a poor criterion for differentiating between declarative (or explicit) and non declarative (or implicit) types of memory. A new model is therefore required in which memory systems are distinguished based on the processing operations involved rather than by consciousness.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

PubMed Central

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-01-01

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced. PMID:27834352

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic.

PubMed

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-11-11

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

NASA Astrophysics Data System (ADS)

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-11-01

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

Bubble memory module for spacecraft application

NASA Technical Reports Server (NTRS)

Hayes, P. J.; Looney, K. T.; Nichols, C. D.

1985-01-01

Bubble domain technology offers an all-solid-state alternative for data storage in onboard data systems. A versatile modular bubble memory concept was developed. The key module is the bubble memory module which contains all of the storage devices and circuitry for accessing these devices. This report documents the bubble memory module design and preliminary hardware designs aimed at memory module functional demonstration with available commercial bubble devices. The system architecture provides simultaneous operation of bubble devices to attain high data rates. Banks of bubble devices are accessed by a given bubble controller to minimize controller parts. A power strobing technique is discussed which could minimize the average system power dissipation. A fast initialization method using EEPROM (electrically erasable, programmable read-only memory) devices promotes fast access. Noise and crosstalk problems and implementations to minimize these are discussed. Flight memory systems which incorporate the concepts and techniques of this work could now be developed for applications.

Sleep Supports Inhibitory Operant Conditioning Memory in "Aplysia"

ERIC Educational Resources Information Center

Vorster, Albrecht P. A.; Born, Jan

2017-01-01

Sleep supports memory consolidation as shown in mammals and invertebrates such as bees and "Drosophila." Here, we show that sleep's memory function is preserved in "Aplysia californica" with an even simpler nervous system. Animals performed on an inhibitory conditioning task ("learning that a food is inedible") three…

Sparse distributed memory overview

NASA Technical Reports Server (NTRS)

Raugh, Mike

1990-01-01

The Sparse Distributed Memory (SDM) project is investigating the theory and applications of massively parallel computing architecture, called sparse distributed memory, that will support the storage and retrieval of sensory and motor patterns characteristic of autonomous systems. The immediate objectives of the project are centered in studies of the memory itself and in the use of the memory to solve problems in speech, vision, and robotics. Investigation of methods for encoding sensory data is an important part of the research. Examples of NASA missions that may benefit from this work are Space Station, planetary rovers, and solar exploration. Sparse distributed memory offers promising technology for systems that must learn through experience and be capable of adapting to new circumstances, and for operating any large complex system requiring automatic monitoring and control. Sparse distributed memory is a massively parallel architecture motivated by efforts to understand how the human brain works. Sparse distributed memory is an associative memory, able to retrieve information from cues that only partially match patterns stored in the memory. It is able to store long temporal sequences derived from the behavior of a complex system, such as progressive records of the system's sensory data and correlated records of the system's motor controls.

Optical memory development. Volume 1: prototype memory system

NASA Technical Reports Server (NTRS)

Cosentino, L. S.; Mezrich, R. S.; Nagle, E. M.; Stewart, W. C.; Wendt, F. S.

1972-01-01

The design, development, and implementation of a prototype, partially populated, million bit read-write holographic memory system using state-of-the-art components are described. The system employs an argon ion laser, acoustooptic beam deflectors, a holographic beam splitter (hololens), a nematic liquid crystal page composer, a photoconductor-thermoplastic erasable storage medium, a silicon P-I-N photodiode array, with lenses and electronics of both conventional and custom design. Operation of the prototype memory system was successfully demonstrated. Careful attention is given to the analysis from which the design criteria were developed. Specifications for the major components are listed, along with the details of their construction and performance. The primary conclusion resulting from this program is that the basic principles of read-write holographic memory system are well understood and are reducible to practice.

High efficiency coherent optical memory with warm rubidium vapour

PubMed Central

Hosseini, M.; Sparkes, B.M.; Campbell, G.; Lam, P.K.; Buchler, B.C.

2011-01-01

By harnessing aspects of quantum mechanics, communication and information processing could be radically transformed. Promising forms of quantum information technology include optical quantum cryptographic systems and computing using photons for quantum logic operations. As with current information processing systems, some form of memory will be required. Quantum repeaters, which are required for long distance quantum key distribution, require quantum optical memory as do deterministic logic gates for optical quantum computing. Here, we present results from a coherent optical memory based on warm rubidium vapour and show 87% efficient recall of light pulses, the highest efficiency measured to date for any coherent optical memory suitable for quantum information applications. We also show storage and recall of up to 20 pulses from our system. These results show that simple warm atomic vapour systems have clear potential as a platform for quantum memory. PMID:21285952

High efficiency coherent optical memory with warm rubidium vapour.

PubMed

Hosseini, M; Sparkes, B M; Campbell, G; Lam, P K; Buchler, B C

2011-02-01

By harnessing aspects of quantum mechanics, communication and information processing could be radically transformed. Promising forms of quantum information technology include optical quantum cryptographic systems and computing using photons for quantum logic operations. As with current information processing systems, some form of memory will be required. Quantum repeaters, which are required for long distance quantum key distribution, require quantum optical memory as do deterministic logic gates for optical quantum computing. Here, we present results from a coherent optical memory based on warm rubidium vapour and show 87% efficient recall of light pulses, the highest efficiency measured to date for any coherent optical memory suitable for quantum information applications. We also show storage and recall of up to 20 pulses from our system. These results show that simple warm atomic vapour systems have clear potential as a platform for quantum memory.

System for loading executable code into volatile memory in a downhole tool

DOEpatents

Hall, David R.; Bartholomew, David B.; Johnson, Monte L.

2007-09-25

A system for loading an executable code into volatile memory in a downhole tool string component comprises a surface control unit comprising executable code. An integrated downhole network comprises data transmission elements in communication with the surface control unit and the volatile memory. The executable code, stored in the surface control unit, is not permanently stored in the downhole tool string component. In a preferred embodiment of the present invention, the downhole tool string component comprises boot memory. In another embodiment, the executable code is an operating system executable code. Preferably, the volatile memory comprises random access memory (RAM). A method for loading executable code to volatile memory in a downhole tool string component comprises sending the code from the surface control unit to a processor in the downhole tool string component over the network. A central processing unit writes the executable code in the volatile memory.

Face Encoding and Recognition in the Human Brain

NASA Astrophysics Data System (ADS)

Haxby, James V.; Ungerleider, Leslie G.; Horwitz, Barry; Maisog, Jose Ma.; Rapoport, Stanley I.; Grady, Cheryl L.

1996-01-01

A dissociation between human neural systems that participate in the encoding and later recognition of new memories for faces was demonstrated by measuring memory task-related changes in regional cerebral blood flow with positron emission tomography. There was almost no overlap between the brain structures associated with these memory functions. A region in the right hippocampus and adjacent cortex was activated during memory encoding but not during recognition. The most striking finding in neocortex was the lateralization of prefrontal participation. Encoding activated left prefrontal cortex, whereas recognition activated right prefrontal cortex. These results indicate that the hippocampus and adjacent cortex participate in memory function primarily at the time of new memory encoding. Moreover, face recognition is not mediated simply by recapitulation of operations performed at the time of encoding but, rather, involves anatomically dissociable operations.

On Using the Volatile Mem-Capacitive Effect of TiO2 Resistive Random Access Memory to Mimic the Synaptic Forgetting Process

NASA Astrophysics Data System (ADS)

Sarkar, Biplab; Mills, Steven; Lee, Bongmook; Pitts, W. Shepherd; Misra, Veena; Franzon, Paul D.

2018-02-01

In this work, we report on mimicking the synaptic forgetting process using the volatile mem-capacitive effect of a resistive random access memory (RRAM). TiO2 dielectric, which is known to show volatile memory operations due to migration of inherent oxygen vacancies, was used to achieve the volatile mem-capacitive effect. By placing the volatile RRAM candidate along with SiO2 at the gate of a MOS capacitor, a volatile capacitance change resembling the forgetting nature of a human brain is demonstrated. Furthermore, the memory operation in the MOS capacitor does not require a current flow through the gate dielectric indicating the feasibility of obtaining low power memory operations. Thus, the mem-capacitive effect of volatile RRAM candidates can be attractive to the future neuromorphic systems for implementing the forgetting process of a human brain.

ATLAS from Data Research Associates: A Fully Integrated Automation System.

ERIC Educational Resources Information Center

Mellinger, Michael J.

1987-01-01

This detailed description of a fully integrated, turnkey library system includes a complete profile of the system (functions, operational characteristics, hardware, operating system, minimum memory and pricing); history of the technologies involved; and descriptions of customer services and availability. (CLB)

Addressable configurations of DNA nanostructures for rewritable memory.

PubMed

Chandrasekaran, Arun Richard; Levchenko, Oksana; Patel, Dhruv S; MacIsaac, Molly; Halvorsen, Ken

2017-11-02

DNA serves as nature's information storage molecule, and has been the primary focus of engineered systems for biological computing and data storage. Here we combine recent efforts in DNA self-assembly and toehold-mediated strand displacement to develop a rewritable multi-bit DNA memory system. The system operates by encoding information in distinct and reversible conformations of a DNA nanoswitch and decoding by gel electrophoresis. We demonstrate a 5-bit system capable of writing, erasing, and rewriting binary representations of alphanumeric symbols, as well as compatibility with 'OR' and 'AND' logic operations. Our strategy is simple to implement, requiring only a single mixing step at room temperature for each operation and standard gel electrophoresis to read the data. We envision such systems could find use in covert product labeling and barcoding, as well as secure messaging and authentication when combined with previously developed encryption strategies. Ultimately, this type of memory has exciting potential in biomedical sciences as data storage can be coupled to sensing of biological molecules. © The Author(s) 2017. Published by Oxford University Press on behalf of Nucleic Acids Research.

ELECTROSTATIC MEMORY SYSTEM

DOEpatents

Chu, J.C.

1958-09-23

An improved electrostatic memory system is de scribed fer a digital computer wherein a plarality of storage tubes are adapted to operate in either of two possible modes. According to the present irvention, duplicate storage tubes are provided fur each denominational order of the several binary digits. A single discriminator system is provided between corresponding duplicate tubes to determine the character of the infurmation stored in each. If either tube produces the selected type signal, corresponding to binazy "1" in the preferred embodiment, a "1" is regenerated in both tubes. In one mode of operation each bit of information is stored in two corresponding tubes, while in the other mode of operation each bit is stored in only one tube in the conventional manner.

Hypercluster Parallel Processor

NASA Technical Reports Server (NTRS)

Blech, Richard A.; Cole, Gary L.; Milner, Edward J.; Quealy, Angela

1992-01-01

Hypercluster computer system includes multiple digital processors, operation of which coordinated through specialized software. Configurable according to various parallel-computing architectures of shared-memory or distributed-memory class, including scalar computer, vector computer, reduced-instruction-set computer, and complex-instruction-set computer. Designed as flexible, relatively inexpensive system that provides single programming and operating environment within which one can investigate effects of various parallel-computing architectures and combinations on performance in solution of complicated problems like those of three-dimensional flows in turbomachines. Hypercluster software and architectural concepts are in public domain.

Global positioning system recorder and method

DOEpatents

Hayes, D.W.; Hofstetter, K.J.; Eakle, R.F. Jr.; Reeves, G.E.

1998-12-22

A global positioning system recorder (GPSR) is disclosed in which operational parameters and recorded positional data are stored on a transferable memory element. Through this transferrable memory element, the user of the GPSR need have no knowledge of GPSR devices other than that the memory element needs to be inserted into the memory element slot and the GPSR must be activated. The use of the data element also allows for minimal downtime of the GPSR and the ability to reprogram the GPSR and download data therefrom, without having to physically attach it to another computer. 4 figs.

Global positioning system recorder and method government rights

DOEpatents

Hayes, David W.; Hofstetter, Kenneth J.; Eakle, Jr., Robert F.; Reeves, George E.

1998-01-01

A global positioning system recorder (GPSR) is disclosed in which operational parameters and recorded positional data are stored on a transferable memory element. Through this transferrable memory element, the user of the GPSR need have no knowledge of GPSR devices other than that the memory element needs to be inserted into the memory element slot and the GPSR must be activated. The use of the data element also allows for minimal downtime of the GPSR and the ability to reprogram the GPSR and download data therefrom, without having to physically attach it to another computer.

Toshiba TDF-500 High Resolution Viewing And Analysis System

NASA Astrophysics Data System (ADS)

Roberts, Barry; Kakegawa, M.; Nishikawa, M.; Oikawa, D.

1988-06-01

A high resolution, operator interactive, medical viewing and analysis system has been developed by Toshiba and Bio-Imaging Research. This system provides many advanced features including high resolution displays, a very large image memory and advanced image processing capability. In particular, the system provides CRT frame buffers capable of update in one frame period, an array processor capable of image processing at operator interactive speeds, and a memory system capable of updating multiple frame buffers at frame rates whilst supporting multiple array processors. The display system provides 1024 x 1536 display resolution at 40Hz frame and 80Hz field rates. In particular, the ability to provide whole or partial update of the screen at the scanning rate is a key feature. This allows multiple viewports or windows in the display buffer with both fixed and cine capability. To support image processing features such as windowing, pan, zoom, minification, filtering, ROI analysis, multiplanar and 3D reconstruction, a high performance CPU is integrated into the system. This CPU is an array processor capable of up to 400 million instructions per second. To support the multiple viewer and array processors' instantaneous high memory bandwidth requirement, an ultra fast memory system is used. This memory system has a bandwidth capability of 400MB/sec and a total capacity of 256MB. This bandwidth is more than adequate to support several high resolution CRT's and also the fast processing unit. This fully integrated approach allows effective real time image processing. The integrated design of viewing system, memory system and array processor are key to the imaging system. It is the intention to describe the architecture of the image system in this paper.

Architecture of security management unit for safe hosting of multiple agents

NASA Astrophysics Data System (ADS)

Gilmont, Tanguy; Legat, Jean-Didier; Quisquater, Jean-Jacques

1999-04-01

In such growing areas as remote applications in large public networks, electronic commerce, digital signature, intellectual property and copyright protection, and even operating system extensibility, the hardware security level offered by existing processors is insufficient. They lack protection mechanisms that prevent the user from tampering critical data owned by those applications. Some devices make exception, but have not enough processing power nor enough memory to stand up to such applications (e.g. smart cards). This paper proposes an architecture of secure processor, in which the classical memory management unit is extended into a new security management unit. It allows ciphered code execution and ciphered data processing. An internal permanent memory can store cipher keys and critical data for several client agents simultaneously. The ordinary supervisor privilege scheme is replaced by a privilege inheritance mechanism that is more suited to operating system extensibility. The result is a secure processor that has hardware support for extensible multitask operating systems, and can be used for both general applications and critical applications needing strong protection. The security management unit and the internal permanent memory can be added to an existing CPU core without loss of performance, and do not require it to be modified.

The MNESIS model: Memory systems and processes, identity and future thinking.

PubMed

Eustache, Francis; Viard, Armelle; Desgranges, Béatrice

2016-07-01

The Memory NEo-Structural Inter-Systemic model (MNESIS; Eustache and Desgranges, Neuropsychology Review, 2008) is a macromodel based on neuropsychological data which presents an interactive construction of memory systems and processes. Largely inspired by Tulving's SPI model, MNESIS puts the emphasis on the existence of different memory systems in humans and their reciprocal relations, adding new aspects, such as the episodic buffer proposed by Baddeley. The more integrative comprehension of brain dynamics offered by neuroimaging has contributed to rethinking the existence of memory systems. In the present article, we will argue that understanding the concept of memory by dividing it into systems at the functional level is still valid, but needs to be considered in the light of brain imaging. Here, we reinstate the importance of this division in different memory systems and illustrate, with neuroimaging findings, the links that operate between memory systems in response to task demands that constrain the brain dynamics. During a cognitive task, these memory systems interact transiently to rapidly assemble representations and mobilize functions to propose a flexible and adaptative response. We will concentrate on two memory systems, episodic and semantic memory, and their links with autobiographical memory. More precisely, we will focus on interactions between episodic and semantic memory systems in support of 1) self-identity in healthy aging and in brain pathologies and 2) the concept of the prospective brain during future projection. In conclusion, this MNESIS global framework may help to get a general representation of human memory and its brain implementation with its specific components which are in constant interaction during cognitive processes. Copyright © 2016 Elsevier Ltd. All rights reserved.

Data Telemetry and Acquisition System for Acoustic Signal Processing Investigations.

DTIC Science & Technology

1996-02-20

were VME- based computer systems operating under the VxWorks real - time operating system . Each system shared a common hardware and software... real - time operating system . It interfaces to the Berg PCM Decommutator board, which searches for the embedded synchronization word in the data and re...software were built on top of this architecture. The multi-tasking, message queue and memory management facilities of the VxWorks real - time operating system are

Hybrid associative memory using an incoherent correlation system

NASA Astrophysics Data System (ADS)

Taniguchi, Masaki; Ichioka, Yoshiki; Matsuoka, Katsunori

1990-10-01

A hybrid heteroassociative memory is presented that uses an incoherent system in which two correlators and a nonlinear element form a nonlinear feedback system. This system can recall any pattern from an input pattern without cross-talk or ghosts by properly designing a pair of filters installed in the correlators. Experiments on a simple hybrid system were performed to ensure the operation of the system and to demonstrate the usefulness of this proposed system.

Fabry-Perot confocal resonator optical associative memory

NASA Astrophysics Data System (ADS)

Burns, Thomas J.; Rogers, Steven K.; Vogel, George A.

1993-03-01

A unique optical associative memory architecture is presented that combines the optical processing environment of a Fabry-Perot confocal resonator with the dynamic storage and recall properties of volume holograms. The confocal resonator reduces the size and complexity of previous associative memory architectures by folding a large number of discrete optical components into an integrated, compact optical processing environment. Experimental results demonstrate the system is capable of recalling a complete object from memory when presented with partial information about the object. A Fourier optics model of the system's operation shows it implements a spatially continuous version of a discrete, binary Hopfield neural network associative memory.

Acute Sleep Deprivation Blocks Short- and Long-Term Operant Memory in Aplysia.

PubMed

Krishnan, Harini C; Gandour, Catherine E; Ramos, Joshua L; Wrinkle, Mariah C; Sanchez-Pacheco, Joseph J; Lyons, Lisa C

2016-12-01

Insufficient sleep in individuals appears increasingly common due to the demands of modern work schedules and technology use. Consequently, there is a growing need to understand the interactions between sleep deprivation and memory. The current study determined the effects of acute sleep deprivation on short and long-term associative memory using the marine mollusk Aplysia californica , a relatively simple model system well known for studies of learning and memory. Aplysia were sleep deprived for 9 hours using context changes and tactile stimulation either prior to or after training for the operant learning paradigm, learning that food is inedible (LFI). The effects of sleep deprivation on short-term (STM) and long-term memory (LTM) were assessed. Acute sleep deprivation prior to LFI training impaired the induction of STM and LTM with persistent effects lasting at least 24 h. Sleep deprivation immediately after training blocked the consolidation of LTM. However, sleep deprivation following the period of molecular consolidation did not affect memory recall. Memory impairments were independent of handling-induced stress, as daytime handled control animals demonstrated no memory deficits. Additional training immediately after sleep deprivation failed to rescue the induction of memory, but additional training alleviated the persistent impairment in memory induction when training occurred 24 h following sleep deprivation. Acute sleep deprivation inhibited the induction and consolidation, but not the recall of memory. These behavioral studies establish Aplysia as an effective model system for studying the interactions between sleep and memory formation. © 2016 Associated Professional Sleep Societies, LLC.

Achieving enlightenment: what do we know about the implicit learning system and its interaction with explicit knowledge?

PubMed

Vidoni, Eric D; Boyd, Lara A

2007-09-01

Two major memory and learning systems operate in the brain: one for facts and ideas (ie, the declarative or explicit system), one for habits and behaviors (ie, the procedural or implicit system). Broadly speaking these two memory systems can operate either in concert or entirely independently of one another during the performance and learning of skilled motor behaviors. This Special Issue article has two parts. In the first, we present a review of implicit motor skill learning that is largely centered on the interactions between declarative and procedural learning and memory. Because distinct neuroanatomical substrates support unique aspects of learning and memory and thus focal injury can cause impairments that are dependent on lesion location, we also broadly consider which brain regions mediate implicit and explicit learning and memory. In the second part of this article, the interactive nature of these two memory systems is illustrated by the presentation of new data that reveal that both learning implicitly and acquiring explicit knowledge through physical practice lead to motor sequence learning. In our new data, we discovered that for healthy individuals use of the implicit versus explicit memory system differently affected variability of performance during acquisition practice; variability was higher early in practice for the implicit group and later in practice for the acquired explicit group. Despite the difference in performance variability, by retention both groups demonstrated comparable change in tracking accuracy and thus, motor sequence learning. Clinicians should be aware of the potential effects of implicit and explicit interactions when designing rehabilitation interventions, particularly when delivering explicit instructions before task practice, working with individuals with focal brain damage, and/or adjusting therapeutic parameters based on acquisition performance variability.

Real-Time Reconfigurable Adaptive Speech Recognition Command and Control Apparatus and Method

NASA Technical Reports Server (NTRS)

Salazar, George A. (Inventor); Haynes, Dena S. (Inventor); Sommers, Marc J. (Inventor)

1998-01-01

An adaptive speech recognition and control system and method for controlling various mechanisms and systems in response to spoken instructions and in which spoken commands are effective to direct the system into appropriate memory nodes, and to respective appropriate memory templates corresponding to the voiced command is discussed. Spoken commands from any of a group of operators for which the system is trained may be identified, and voice templates are updated as required in response to changes in pronunciation and voice characteristics over time of any of the operators for which the system is trained. Provisions are made for both near-real-time retraining of the system with respect to individual terms which are determined not be positively identified, and for an overall system training and updating process in which recognition of each command and vocabulary term is checked, and in which the memory templates are retrained if necessary for respective commands or vocabulary terms with respect to an operator currently using the system. In one embodiment, the system includes input circuitry connected to a microphone and including signal processing and control sections for sensing the level of vocabulary recognition over a given period and, if recognition performance falls below a given level, processing audio-derived signals for enhancing recognition performance of the system.

A quantitative theory of the functions of the hippocampal CA3 network in memory

PubMed Central

Rolls, Edmund T.

2013-01-01

A quantitative computational theory of the operation of the hippocampal CA3 system as an autoassociation or attractor network used in episodic memory system is described. In this theory, the CA3 system operates as a single attractor or autoassociation network to enable rapid, one-trial, associations between any spatial location (place in rodents, or spatial view in primates) and an object or reward, and to provide for completion of the whole memory during recall from any part. The theory is extended to associations between time and object or reward to implement temporal order memory, also important in episodic memory. The dentate gyrus (DG) performs pattern separation by competitive learning to produce sparse representations suitable for setting up new representations in CA3 during learning, producing for example neurons with place-like fields from entorhinal cortex grid cells. The dentate granule cells produce by the very small number of mossy fiber (MF) connections to CA3 a randomizing pattern separation effect important during learning but not recall that separates out the patterns represented by CA3 firing to be very different from each other, which is optimal for an unstructured episodic memory system in which each memory must be kept distinct from other memories. The direct perforant path (pp) input to CA3 is quantitatively appropriate to provide the cue for recall in CA3, but not for learning. Tests of the theory including hippocampal subregion analyses and hippocampal NMDA receptor knockouts are described, and support the theory. PMID:23805074

Quantum memories with zero-energy Majorana modes and experimental constraints

NASA Astrophysics Data System (ADS)

Ippoliti, Matteo; Rizzi, Matteo; Giovannetti, Vittorio; Mazza, Leonardo

2016-06-01

In this work we address the problem of realizing a reliable quantum memory based on zero-energy Majorana modes in the presence of experimental constraints on the operations aimed at recovering the information. In particular, we characterize the best recovery operation acting only on the zero-energy Majorana modes and the memory fidelity that can be therewith achieved. In order to understand the effect of such restriction, we discuss two examples of noise models acting on the topological system and compare the amount of information that can be recovered by accessing either the whole system, or the zero modes only, with particular attention to the scaling with the size of the system and the energy gap. We explicitly discuss the case of a thermal bosonic environment inducing a parity-preserving Markovian dynamics in which the memory fidelity achievable via a read-out of the zero modes decays exponentially in time, independent from system size. We argue, however, that even in the presence of said experimental limitations, the Hamiltonian gap is still beneficial to the storage of information.

Asset surveillance system: apparatus and method

NASA Technical Reports Server (NTRS)

Bickford, Randall L. (Inventor)

2007-01-01

System and method for providing surveillance of an asset comprised of numerically fitting at least one mathematical model to obtained residual data correlative to asset operation; storing at least one mathematical model in a memory; obtaining a current set of signal data from the asset; retrieving at least one mathematical model from the memory, using the retrieved mathematical model in a sequential hypothesis test for determining if the current set of signal data is indicative of a fault condition; determining an asset fault cause correlative to a determined indication of a fault condition; providing an indication correlative to a determined fault cause, and an action when warranted. The residual data can be mode partitioned, a current mode of operation can be determined from the asset, and at least one mathematical model can be retrieved from the memory as a function of the determined mode of operation.

An adaptive learning control system for aircraft

NASA Technical Reports Server (NTRS)

Mekel, R.; Nachmias, S.

1978-01-01

A learning control system and its utilization as a flight control system for F-8 Digital Fly-By-Wire (DFBW) research aircraft is studied. The system has the ability to adjust a gain schedule to account for changing plant characteristics and to improve its performance and the plant's performance in the course of its own operation. Three subsystems are detailed: (1) the information acquisition subsystem which identifies the plant's parameters at a given operating condition; (2) the learning algorithm subsystem which relates the identified parameters to predetermined analytical expressions describing the behavior of the parameters over a range of operating conditions; and (3) the memory and control process subsystem which consists of the collection of updated coefficients (memory) and the derived control laws. Simulation experiments indicate that the learning control system is effective in compensating for parameter variations caused by changes in flight conditions.

Two Unipolar Terminal-Attractor-Based Associative Memories

NASA Technical Reports Server (NTRS)

Liu, Hua-Kuang; Wu, Chwan-Hwa

1995-01-01

Two unipolar mathematical models of electronic neural network functioning as terminal-attractor-based associative memory (TABAM) developed. Models comprise sets of equations describing interactions between time-varying inputs and outputs of neural-network memory, regarded as dynamical system. Simplifies design and operation of optoelectronic processor to implement TABAM performing associative recall of images. TABAM concept described in "Optoelectronic Terminal-Attractor-Based Associative Memory" (NPO-18790). Experimental optoelectronic apparatus that performed associative recall of binary images described in "Optoelectronic Inner-Product Neural Associative Memory" (NPO-18491).

The Glass Computer

ERIC Educational Resources Information Center

Paesler, M. A.

2009-01-01

Digital computers use different kinds of memory, each of which is either volatile or nonvolatile. On most computers only the hard drive memory is nonvolatile, i.e., it retains all information stored on it when the power is off. When a computer is turned on, an operating system stored on the hard drive is loaded into the computer's memory cache and…

Multiple Memory Stores and Operant Conditioning: A Rationale for Memory's Complexity

ERIC Educational Resources Information Center

Meeter, Martijn; Veldkamp, Rob; Jin, Yaochu

2009-01-01

Why does the brain contain more than one memory system? Genetic algorithms can play a role in elucidating this question. Here, model animals were constructed containing a dorsal striatal layer that controlled actions, and a ventral striatal layer that controlled a dopaminergic learning signal. Both layers could gain access to three modeled memory…

Memory and Energy Optimization Strategies for Multithreaded Operating System on the Resource-Constrained Wireless Sensor Node

PubMed Central

Liu, Xing; Hou, Kun Mean; de Vaulx, Christophe; Xu, Jun; Yang, Jianfeng; Zhou, Haiying; Shi, Hongling; Zhou, Peng

2015-01-01

Memory and energy optimization strategies are essential for the resource-constrained wireless sensor network (WSN) nodes. In this article, a new memory-optimized and energy-optimized multithreaded WSN operating system (OS) LiveOS is designed and implemented. Memory cost of LiveOS is optimized by using the stack-shifting hybrid scheduling approach. Different from the traditional multithreaded OS in which thread stacks are allocated statically by the pre-reservation, thread stacks in LiveOS are allocated dynamically by using the stack-shifting technique. As a result, memory waste problems caused by the static pre-reservation can be avoided. In addition to the stack-shifting dynamic allocation approach, the hybrid scheduling mechanism which can decrease both the thread scheduling overhead and the thread stack number is also implemented in LiveOS. With these mechanisms, the stack memory cost of LiveOS can be reduced more than 50% if compared to that of a traditional multithreaded OS. Not is memory cost optimized, but also the energy cost is optimized in LiveOS, and this is achieved by using the multi-core “context aware” and multi-core “power-off/wakeup” energy conservation approaches. By using these approaches, energy cost of LiveOS can be reduced more than 30% when compared to the single-core WSN system. Memory and energy optimization strategies in LiveOS not only prolong the lifetime of WSN nodes, but also make the multithreaded OS feasible to run on the memory-constrained WSN nodes. PMID:25545264

Processes of Quantum Associative Memory (QuAM) Through New Maximally Entangled States (Singh-Rajput MES)

NASA Astrophysics Data System (ADS)

Singh, Manu Pratap; Rajput, B. S.

2016-07-01

Using Singh-Rajput MES as memory states in the evolutionary process of pattern storage and the non-evolutionary process of pattern recall (the two fundamental constituents of QuAM), the suitability and superiority of these MES over Bell's MES have been demonstrated in both these processes. It has been shown that, under the operations of all the possible memorization operators for a two-qubit system, the first two states of Singh-Rajput MES are useful for storing the pattern |11> and the last two of these MES are useful in storing the pattern |10> while Bell's MES are not much suitable as memory states in a valid memorization process. The recall operations have also been conducted by separately choosing Singh-Rajput MES and Bell's MES as memory states for possible various queries and it has been shown that in each case the choices of Singh-Rajput MES as valid memory states are much more suitable than those of Bell's MES.

Multiple memory stores and operant conditioning: a rationale for memory's complexity.

PubMed

Meeter, Martijn; Veldkamp, Rob; Jin, Yaochu

2009-02-01

Why does the brain contain more than one memory system? Genetic algorithms can play a role in elucidating this question. Here, model animals were constructed containing a dorsal striatal layer that controlled actions, and a ventral striatal layer that controlled a dopaminergic learning signal. Both layers could gain access to three modeled memory stores, but such access was penalized as energy expenditure. Model animals were then selected on their fitness in simulated operant conditioning tasks. Results suggest that having access to multiple memory stores and their representations is important in learning to regulate dopamine release, as well as in contextual discrimination. For simple operant conditioning, as well as stimulus discrimination, hippocampal compound representations turned out to suffice, a counterintuitive result given findings that hippocampal lesions tend not to affect performance in such tasks. We argue that there is in fact evidence to support a role for compound representations and the hippocampus in even the simplest conditioning tasks.

Unconditional polarization qubit quantum memory at room temperature

NASA Astrophysics Data System (ADS)

Namazi, Mehdi; Kupchak, Connor; Jordaan, Bertus; Shahrokhshahi, Reihaneh; Figueroa, Eden

2016-05-01

The creation of global quantum key distribution and quantum communication networks requires multiple operational quantum memories. Achieving a considerable reduction in experimental and cost overhead in these implementations is thus a major challenge. Here we present a polarization qubit quantum memory fully-operational at 330K, an unheard frontier in the development of useful qubit quantum technology. This result is achieved through extensive study of how optical response of cold atomic medium is transformed by the motion of atoms at room temperature leading to an optimal characterization of room temperature quantum light-matter interfaces. Our quantum memory shows an average fidelity of 86.6 +/- 0.6% for optical pulses containing on average 1 photon per pulse, thereby defeating any classical strategy exploiting the non-unitary character of the memory efficiency. Our system significantly decreases the technological overhead required to achieve quantum memory operation and will serve as a building block for scalable and technologically simpler many-memory quantum machines. The work was supported by the US-Navy Office of Naval Research, Grant Number N00141410801 and the Simons Foundation, Grant Number SBF241180. B. J. acknowledges financial assistance of the National Research Foundation (NRF) of South Africa.

Canadian Association of Neurosciences Review: learning at a snail's pace.

PubMed

Parvez, Kashif; Rosenegger, David; Martens, Kara; Orr, Michael; Lukowiak, Ken

2006-11-01

While learning and memory are related, they are distinct processes each with different forms of expression and underlying molecular mechanisms. An invertebrate model system, Lymnaea stagnalis, is used to study memory formation of a non-declarative memory. We have done so because: (1) We have discovered the neural circuit that mediates an interesting and tractable behaviour; (2) This behaviour can be operantly conditioned and intermediate-term and long-term memory can be demonstrated; and (3) It is possible to demonstrate that a single neuron in the model system is a necessary site of memory formation. This article reviews how Lymnaea has been used in the study of behavioural and molecular mechanisms underlying consolidation, reconsolidation, extinction and forgetting.

How Limited Systematicity Emerges: A Computational Cognitive Neuroscience Approach (Author’s Manuscript)

DTIC Science & Technology

2014-09-01

not losing track of the original facts of the situation. However, hippocampal episodic memory also has limitations – it operates one memory at a...ability to strategically control the use of episodic memory . Specific areas of PFC are implicated as these episodic control structures, including...certainly start by encoding the problem into hippocampal episodic memory , so they can retrieve it when interference overtakes the system and they

Programmable Direct-Memory-Access Controller

NASA Technical Reports Server (NTRS)

Hendry, David F.

1990-01-01

Proposed programmable direct-memory-access controller (DMAC) operates with computer systems of 32000 series, which have 32-bit data buses and use addresses of 24 (or potentially 32) bits. Controller functions with or without help of central processing unit (CPU) and starts itself. Includes such advanced features as ability to compare two blocks of memory for equality and to search block of memory for specific value. Made as single very-large-scale integrated-circuit chip.

Partitioned key-value store with atomic memory operations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bent, John M.; Faibish, Sorin; Grider, Gary

A partitioned key-value store is provided that supports atomic memory operations. A server performs a memory operation in a partitioned key-value store by receiving a request from an application for at least one atomic memory operation, the atomic memory operation comprising a memory address identifier; and, in response to the atomic memory operation, performing one or more of (i) reading a client-side memory location identified by the memory address identifier and storing one or more key-value pairs from the client-side memory location in a local key-value store of the server; and (ii) obtaining one or more key-value pairs from themore » local key-value store of the server and writing the obtained one or more key-value pairs into the client-side memory location identified by the memory address identifier. The server can perform functions obtained from a client-side memory location and return a result to the client using one or more of the atomic memory operations.« less

DESIGN PRINCIPLES FOR AN ON-LINE INFORMATION RETRIEVAL SYSTEM. TECHNICAL REPORT.

ERIC Educational Resources Information Center

LOWE, THOMAS C.

AREAS INVESTIGATED INCLUDE SLOW MEMORY DATA STORAGE, THE PROBLEM OF DECODING FROM AN INDEX TO A SLOW MEMORY ADDRESS, THE STRUCTURE OF DATA LISTS AND DATA LIST OPERATORS, COMMUNICATIONS BETWEEN THE HUMAN USER AND THE SYSTEM, PROCESSING OF RETRIEVAL REQUESTS, AND THE USER'S CONTROL OVER THE RETURN OF INFORMATION RETRIEVED. LINEAR, LINKED AND…

Virtual data

NASA Astrophysics Data System (ADS)

Bjorklund, E.

1994-12-01

In the 1970s, when computers were memory limited, operating system designers created the concept of "virtual memory", which gave users the ability to address more memory than physically existed. In the 1990s, many large control systems have the potential of becoming data limited. We propose that many of the principles behind virtual memory systems (working sets, locality, caching and clustering) can also be applied to data-limited systems, creating, in effect, "virtual data systems". At the Los Alamos National Laboratory's Clinton P. Anderson Meson Physics Facility (LAMPF), we have applied these principles to a moderately sized (10 000 data points) data acquisition and control system. To test the principles, we measured the system's performance during tune-up, production, and maintenance periods. In this paper, we present a general discussion of the principles of a virtual data system along with some discussion of our own implementation and the results of our performance measurements.

A Fully Automated Drosophila Olfactory Classical Conditioning and Testing System for Behavioral Learning and Memory Assessment

PubMed Central

Jiang, Hui; Hanna, Eriny; Gatto, Cheryl L.; Page, Terry L.; Bhuva, Bharat; Broadie, Kendal

2016-01-01

Background Aversive olfactory classical conditioning has been the standard method to assess Drosophila learning and memory behavior for decades, yet training and testing are conducted manually under exceedingly labor-intensive conditions. To overcome this severe limitation, a fully automated, inexpensive system has been developed, which allows accurate and efficient Pavlovian associative learning/memory analyses for high-throughput pharmacological and genetic studies. New Method The automated system employs a linear actuator coupled to an odorant T-maze with airflow-mediated transfer of animals between training and testing stages. Odorant, airflow and electrical shock delivery are automatically administered and monitored during training trials. Control software allows operator-input variables to define parameters of Drosophila learning, short-term memory and long-term memory assays. Results The approach allows accurate learning/memory determinations with operational fail-safes. Automated learning indices (immediately post-training) and memory indices (after 24 hours) are comparable to traditional manual experiments, while minimizing experimenter involvement. Comparison with Existing Methods The automated system provides vast improvements over labor-intensive manual approaches with no experimenter involvement required during either training or testing phases. It provides quality control tracking of airflow rates, odorant delivery and electrical shock treatments, and an expanded platform for high-throughput studies of combinational drug tests and genetic screens. The design uses inexpensive hardware and software for a total cost of ~$500US, making it affordable to a wide range of investigators. Conclusions This study demonstrates the design, construction and testing of a fully automated Drosophila olfactory classical association apparatus to provide low-labor, high-fidelity, quality-monitored, high-throughput and inexpensive learning and memory behavioral assays. PMID:26703418

A fully automated Drosophila olfactory classical conditioning and testing system for behavioral learning and memory assessment.

PubMed

Jiang, Hui; Hanna, Eriny; Gatto, Cheryl L; Page, Terry L; Bhuva, Bharat; Broadie, Kendal

2016-03-01

Aversive olfactory classical conditioning has been the standard method to assess Drosophila learning and memory behavior for decades, yet training and testing are conducted manually under exceedingly labor-intensive conditions. To overcome this severe limitation, a fully automated, inexpensive system has been developed, which allows accurate and efficient Pavlovian associative learning/memory analyses for high-throughput pharmacological and genetic studies. The automated system employs a linear actuator coupled to an odorant T-maze with airflow-mediated transfer of animals between training and testing stages. Odorant, airflow and electrical shock delivery are automatically administered and monitored during training trials. Control software allows operator-input variables to define parameters of Drosophila learning, short-term memory and long-term memory assays. The approach allows accurate learning/memory determinations with operational fail-safes. Automated learning indices (immediately post-training) and memory indices (after 24h) are comparable to traditional manual experiments, while minimizing experimenter involvement. The automated system provides vast improvements over labor-intensive manual approaches with no experimenter involvement required during either training or testing phases. It provides quality control tracking of airflow rates, odorant delivery and electrical shock treatments, and an expanded platform for high-throughput studies of combinational drug tests and genetic screens. The design uses inexpensive hardware and software for a total cost of ∼$500US, making it affordable to a wide range of investigators. This study demonstrates the design, construction and testing of a fully automated Drosophila olfactory classical association apparatus to provide low-labor, high-fidelity, quality-monitored, high-throughput and inexpensive learning and memory behavioral assays. Copyright © 2015 Elsevier B.V. All rights reserved.

Guidance system operations plan for manned CSM earth orbital and lunar missions using program COLOSSUS 3. Section 7: Erasable memory programs

NASA Technical Reports Server (NTRS)

Hamilton, M. H.

1972-01-01

Erasable-memory programs designed for guidance computers used in command and lunar modules are presented. The purpose, functional description, assumptions, restrictions, and imitations are given for each program.

Making the case that episodic recollection is attributable to operations occurring at retrieval rather than to content stored in a dedicated subsystem of long-term memory.

PubMed

Klein, Stanley B

2013-01-01

Episodic memory often is conceptualized as a uniquely human system of long-term memory that makes available knowledge accompanied by the temporal and spatial context in which that knowledge was acquired. Retrieval from episodic memory entails a form of first-person subjectivity called autonoetic consciousness that provides a sense that a recollection was something that took place in the experiencer's personal past. In this paper I expand on this definition of episodic memory. Specifically, I suggest that (1) the core features assumed unique to episodic memory are shared by semantic memory, (2) episodic memory cannot be fully understood unless one appreciates that episodic recollection requires the coordinated function of a number of distinct, yet interacting, "enabling" systems. Although these systems-ownership, self, subjective temporality, and agency-are not traditionally viewed as memorial in nature, each is necessary for episodic recollection and jointly they may be sufficient, and (3) the type of subjective awareness provided by episodic recollection (autonoetic) is relational rather than intrinsic-i.e., it can be lost in certain patient populations, thus rendering episodic memory content indistinguishable from the content of semantic long-term memory.

Eight microprocessor-based instrument data systems in the Galileo Orbiter spacecraft

NASA Technical Reports Server (NTRS)

Barry, R. C.

1980-01-01

Instrument data systems consist of a microprocessor, 3K bytes of Read Only Memory and 3K bytes of Random Access Memory. It interfaces with the spacecraft data bus through an isolated user interface with a direct memory access bus adaptor, and/or parallel data from instrument devices such as registers, buffers, analog to digital converters, multiplexers, and solid state sensors. These data systems support the spacecraft hardware and software communication protocol, decode and process instrument commands, generate continuous instrument operating modes, control the instrument mechanisms, acquire, process, format, and output instrument science data.

Advanced Compact Holographic Data Storage System

NASA Technical Reports Server (NTRS)

Chao, Tien-Hsin; Zhou, Hanying; Reyes, George

2000-01-01

JPL, under current sponsorship from NASA Space Science and Earth Science Programs, is developing a high-density, nonvolatile and rad-hard Advanced Holographic Memory (AHM) system to enable large-capacity, high-speed, low power consumption, and read/write of data in a space environment. The entire read/write operation will be controlled with electro-optic mechanism without any moving parts. This CHDS will consist of laser diodes, photorefractive crystal, spatial light modulator, photodetector array, and I/O electronic interface. In operation, pages of information would be recorded and retrieved with random access and highspeed. The nonvolatile, rad-hard characteristics of the holographic memory will provide a revolutionary memory technology to enhance mission capabilities for all NASA's Earth Science Mission. In this paper, recent technology progress in developing this CHDS at JPL will be presented.

Magellan spacecraft and memory state tracking: Lessons learned, future thoughts

NASA Technical Reports Server (NTRS)

Bucher, Allen W.

1993-01-01

Numerous studies have been dedicated to improving the two main elements of Spacecraft Mission Operations: Command and Telemetry. As a result, not much attention has been given to other tasks that can become tedious, repetitive, and error prone. One such task is Spacecraft and Memory State Tracking, the process by which the status of critical spacecraft components, parameters, and the contents of on-board memory are managed on the ground to maintain knowledge of spacecraft and memory states for future testing, anomaly investigation, and on-board memory reconstruction. The task of Spacecraft and Memory State Tracking has traditionally been a manual task allocated to Mission Operations Procedures. During nominal Mission Operations this job is tedious and error prone. Because the task is not complex and can be accomplished manually, the worth of a sophisticated software tool is often questioned. However, in the event of an anomaly which alters spacecraft components autonomously or a memory anomaly such as a corrupt memory or flight software error, an accurate ground image that can be reconstructed quickly is a priceless commodity. This study explores the process of Spacecraft and Memory State Tracking used by the Magellan Spacecraft Team highlighting its strengths as well as identifying lessons learned during the primary and extended missions, two memory anomalies, and other hardships encountered due to incomplete knowledge of spacecraft states. Ideas for future state tracking tools that require minimal user interaction and are integrated into the Ground Data System will also be discussed.

Magellan spacecraft and memory state tracking: Lessons learned, future thoughts

NASA Astrophysics Data System (ADS)

Bucher, Allen W.

1993-03-01

Numerous studies have been dedicated to improving the two main elements of Spacecraft Mission Operations: Command and Telemetry. As a result, not much attention has been given to other tasks that can become tedious, repetitive, and error prone. One such task is Spacecraft and Memory State Tracking, the process by which the status of critical spacecraft components, parameters, and the contents of on-board memory are managed on the ground to maintain knowledge of spacecraft and memory states for future testing, anomaly investigation, and on-board memory reconstruction. The task of Spacecraft and Memory State Tracking has traditionally been a manual task allocated to Mission Operations Procedures. During nominal Mission Operations this job is tedious and error prone. Because the task is not complex and can be accomplished manually, the worth of a sophisticated software tool is often questioned. However, in the event of an anomaly which alters spacecraft components autonomously or a memory anomaly such as a corrupt memory or flight software error, an accurate ground image that can be reconstructed quickly is a priceless commodity. This study explores the process of Spacecraft and Memory State Tracking used by the Magellan Spacecraft Team highlighting its strengths as well as identifying lessons learned during the primary and extended missions, two memory anomalies, and other hardships encountered due to incomplete knowledge of spacecraft states. Ideas for future state tracking tools that require minimal user interaction and are integrated into the Ground Data System will also be discussed.

The neural basis of implicit learning and memory: a review of neuropsychological and neuroimaging research.

PubMed

Reber, Paul J

2013-08-01

Memory systems research has typically described the different types of long-term memory in the brain as either declarative versus non-declarative or implicit versus explicit. These descriptions reflect the difference between declarative, conscious, and explicit memory that is dependent on the medial temporal lobe (MTL) memory system, and all other expressions of learning and memory. The other type of memory is generally defined by an absence: either the lack of dependence on the MTL memory system (nondeclarative) or the lack of conscious awareness of the information acquired (implicit). However, definition by absence is inherently underspecified and leaves open questions of how this type of memory operates, its neural basis, and how it differs from explicit, declarative memory. Drawing on a variety of studies of implicit learning that have attempted to identify the neural correlates of implicit learning using functional neuroimaging and neuropsychology, a theory of implicit memory is presented that describes it as a form of general plasticity within processing networks that adaptively improve function via experience. Under this model, implicit memory will not appear as a single, coherent, alternative memory system but will instead be manifested as a principle of improvement from experience based on widespread mechanisms of cortical plasticity. The implications of this characterization for understanding the role of implicit learning in complex cognitive processes and the effects of interactions between types of memory will be discussed for examples within and outside the psychology laboratory. Copyright © 2013 Elsevier Ltd. All rights reserved.

Inhibition of protein synthesis but not β-adrenergic receptors blocks reconsolidation of a cocaine-associated cue memory

PubMed Central

Dunbar, Amber B.

2016-01-01

Previously consolidated memories have the potential to enter a state of lability upon memory recall, during which time the memory can be altered before undergoing an additional consolidation-like process and being stored again as a long-term memory. Blocking reconsolidation of aberrant memories has been proposed as a potential treatment for psychiatric disorders including addiction. Here we investigated of the effect of systemically administering the protein synthesis inhibitor cycloheximide or the β-adrenergic antagonist propranolol on reconsolidation. Rats were trained to self-administer cocaine, during which each lever press resulted in the presentation of a cue paired with an intravenous infusion of cocaine. After undergoing lever press extinction to reduce operant responding, the cue memory was reactivated and rats were administered systemic injections of propranolol, cycloheximide, or vehicle. Post-reactivation cycloheximide, but not propranolol, resulted in a reactivation-dependent decrease in cue-induced reinstatement, indicative of reconsolidation blockade by protein synthesis inhibition. The present data indicate that systemically targeting protein synthesis as opposed to the β-adrenergic system may more effectively attenuate the reconsolidation of a drug-related memory and decrease drug-seeking behavior. PMID:27421890

Inhibition of protein synthesis but not β-adrenergic receptors blocks reconsolidation of a cocaine-associated cue memory.

PubMed

Dunbar, Amber B; Taylor, Jane R

2016-08-01

Previously consolidated memories have the potential to enter a state of lability upon memory recall, during which time the memory can be altered before undergoing an additional consolidation-like process and being stored again as a long-term memory. Blocking reconsolidation of aberrant memories has been proposed as a potential treatment for psychiatric disorders including addiction. Here we investigated of the effect of systemically administering the protein synthesis inhibitor cycloheximide or the β-adrenergic antagonist propranolol on reconsolidation. Rats were trained to self-administer cocaine, during which each lever press resulted in the presentation of a cue paired with an intravenous infusion of cocaine. After undergoing lever press extinction to reduce operant responding, the cue memory was reactivated and rats were administered systemic injections of propranolol, cycloheximide, or vehicle. Post-reactivation cycloheximide, but not propranolol, resulted in a reactivation-dependent decrease in cue-induced reinstatement, indicative of reconsolidation blockade by protein synthesis inhibition. The present data indicate that systemically targeting protein synthesis as opposed to the β-adrenergic system may more effectively attenuate the reconsolidation of a drug-related memory and decrease drug-seeking behavior. © 2016 Dunbar and Taylor; Published by Cold Spring Harbor Laboratory Press.

Interaction between basal ganglia and limbic circuits in learning and memory processes.

PubMed

Calabresi, Paolo; Picconi, Barbara; Tozzi, Alessandro; Ghiglieri, Veronica

2016-01-01

Hippocampus and striatum play distinctive roles in memory processes since declarative and non-declarative memory systems may act independently. However, hippocampus and striatum can also be engaged to function in parallel as part of a dynamic system to integrate previous experience and adjust behavioral responses. In these structures the formation, storage, and retrieval of memory require a synaptic mechanism that is able to integrate multiple signals and to translate them into persistent molecular traces at both the corticostriatal and hippocampal/limbic synapses. The best cellular candidate for this complex synthesis is represented by long-term potentiation (LTP). A common feature of LTP expressed in these two memory systems is the critical requirement of convergence and coincidence of glutamatergic and dopaminergic inputs to the dendritic spines of the neurons expressing this form of synaptic plasticity. In experimental models of Parkinson's disease abnormal accumulation of α-synuclein affects these two memory systems by altering two major synaptic mechanisms underlying cognitive functions in cholinergic striatal neurons, likely implicated in basal ganglia dependent operative memory, and in the CA1 hippocampal region, playing a central function in episodic/declarative memory processes. Copyright © 2015 Elsevier Ltd. All rights reserved.

Avionics Architecture Standards as an Approach to Obsolescence Management

DTIC Science & Technology

2000-10-01

and goals is one method of system. The term System Architecture refers to a achieving the necessary critical mass of skilled and consistent set of such...Processing Module (GPM), Mass Memory Module executed on the modules within an ASAAC system will (MMM) and Power Conversion Module (PCM). be stored in a central...location, the Mass Memory * MOS -Module Support Layer to Operating System Module (MMM). Therefore, if modules are to be The purpose of the MOS

A High Performance VLSI Computer Architecture For Computer Graphics

NASA Astrophysics Data System (ADS)

Chin, Chi-Yuan; Lin, Wen-Tai

1988-10-01

A VLSI computer architecture, consisting of multiple processors, is presented in this paper to satisfy the modern computer graphics demands, e.g. high resolution, realistic animation, real-time display etc.. All processors share a global memory which are partitioned into multiple banks. Through a crossbar network, data from one memory bank can be broadcasted to many processors. Processors are physically interconnected through a hyper-crossbar network (a crossbar-like network). By programming the network, the topology of communication links among processors can be reconfigurated to satisfy specific dataflows of different applications. Each processor consists of a controller, arithmetic operators, local memory, a local crossbar network, and I/O ports to communicate with other processors, memory banks, and a system controller. Operations in each processor are characterized into two modes, i.e. object domain and space domain, to fully utilize the data-independency characteristics of graphics processing. Special graphics features such as 3D-to-2D conversion, shadow generation, texturing, and reflection, can be easily handled. With the current high density interconnection (MI) technology, it is feasible to implement a 64-processor system to achieve 2.5 billion operations per second, a performance needed in most advanced graphics applications.

X-LUNA: Extending Free/Open Source Real Time Executive for On-Board Space Applications

NASA Astrophysics Data System (ADS)

Braga, P.; Henriques, L.; Zulianello, M.

2008-08-01

In this paper we present xLuna, a system based on the RTEMS [1] Real-Time Operating System that is able to run on demand a GNU/Linux Operating System [2] as RTEMS' lowest priority task. Linux runs in user-mode and in a different memory partition. This allows running Hard Real-Time tasks and Linux applications on the same system sharing the Hardware resources while keeping a safe isolation and the Real-Time characteristics of RTEMS. Communication between both Systems is possible through a loose coupled mechanism based on message queues. Currently only SPARC LEON2 processor with Memory Management Unit (MMU) is supported. The advantage in having two isolated systems is that non critical components are quickly developed or simply ported reducing time-to-market and budget.

Integrated information storage and transfer with a coherent magnetic device

PubMed Central

Jia, Ning; Banchi, Leonardo; Bayat, Abolfazl; Dong, Guangjiong; Bose, Sougato

2015-01-01

Quantum systems are inherently dissipation-less, making them excellent candidates even for classical information processing. We propose to use an array of large-spin quantum magnets for realizing a device which has two modes of operation: memory and data-bus. While the weakly interacting low-energy levels are used as memory to store classical information (bits), the high-energy levels strongly interact with neighboring magnets and mediate the spatial movement of information through quantum dynamics. Despite the fact that memory and data-bus require different features, which are usually prerogative of different physical systems – well isolation for the memory cells, and strong interactions for the transmission – our proposal avoids the notorious complexity of hybrid structures. The proposed mechanism can be realized with different setups. We specifically show that molecular magnets, as the most promising technology, can implement hundreds of operations within their coherence time, while adatoms on surfaces probed by a scanning tunneling microscope is a future possibility. PMID:26347152

The Efficiency and the Scalability of an Explicit Operator on an IBM POWER4 System

NASA Technical Reports Server (NTRS)

Frumkin, Michael; Biegel, Bryan A. (Technical Monitor)

2002-01-01

We present an evaluation of the efficiency and the scalability of an explicit CFD operator on an IBM POWER4 system. The POWER4 architecture exhibits a common trend in HPC architectures: boosting CPU processing power by increasing the number of functional units, while hiding the latency of memory access by increasing the depth of the memory hierarchy. The overall machine performance depends on the ability of the caches-buses-fabric-memory to feed the functional units with the data to be processed. In this study we evaluate the efficiency and scalability of one explicit CFD operator on an IBM POWER4. This operator performs computations at the points of a Cartesian grid and involves a few dozen floating point numbers and on the order of 100 floating point operations per grid point. The computations in all grid points are independent. Specifically, we estimate the efficiency of the RHS operator (SP of NPB) on a single processor as the observed/peak performance ratio. Then we estimate the scalability of the operator on a single chip (2 CPUs), a single MCM (8 CPUs), 16 CPUs, and the whole machine (32 CPUs). Then we perform the same measurements for a chache-optimized version of the RHS operator. For our measurements we use the HPM (Hardware Performance Monitor) counters available on the POWER4. These counters allow us to analyze the obtained performance results.

Bistable Microvalve For Use With Microcatheter System

DOEpatents

Seward, Kirk Patrick

2003-12-16

A bistable microvalve of shape memory material is operatively connected to a microcatheter. The bistable microvalve includes a tip that can be closed off until it is in the desired position. Once it is in position it can be opened and closed. The system uses heat and pressure to open and close the microvalve. The shape memory material will change stiffness and shape when heated above a transition temperature. The shape memory material is adapted to move from a first shape to a second shape, either open or closed, where it can perform a desired function.

Bistable microvalve and microcatheter system

DOEpatents

Seward, Kirk Patrick

2003-05-20

A bistable microvalve of shape memory material is operatively connected to a microcatheter. The bistable microvalve includes a tip that can be closed off until it is in the desired position. Once it is in position it can opened and closed. The system uses heat and pressure to open and close the microvalve. The shape memory material will change stiffness and shape when heated above a transition temperature. The shape memory material is adapted to move from a first shape to a second shape, either open or closed, where it can perform a desired function.

Unconditional room-temperature quantum memory

NASA Astrophysics Data System (ADS)

Hosseini, M.; Campbell, G.; Sparkes, B. M.; Lam, P. K.; Buchler, B. C.

2011-10-01

Just as classical information systems require buffers and memory, the same is true for quantum information systems. The potential that optical quantum information processing holds for revolutionizing computation and communication is therefore driving significant research into developing optical quantum memory. A practical optical quantum memory must be able to store and recall quantum states on demand with high efficiency and low noise. Ideally, the platform for the memory would also be simple and inexpensive. Here, we present a complete tomographic reconstruction of quantum states that have been stored in the ground states of rubidium in a vapour cell operating at around 80°C. Without conditional measurements, we show recall fidelity up to 98% for coherent pulses containing around one photon. To unambiguously verify that our memory beats the quantum no-cloning limit we employ state-independent verification using conditional variance and signal-transfer coefficients.

Two semiconductor ring lasers coupled by a single-waveguide for optical memory operation

NASA Astrophysics Data System (ADS)

Van der Sande, Guy; Coomans, Werner; Gelens, Lendert

2014-05-01

Semiconductor ring lasers are semiconductor lasers where the laser cavity consists of a ring-shaped waveguide. SRLs are highly integrable and scalable, making them ideal candidates for key components in photonic integrated circuits. SRLs can generate light in two counterpropagating directions between which bistability has been demonstrated. Hence, information can be coded into the emission direction. This bistable operation allows SRLs to be used in systems for all-optical switching and as all-optical memories. For the demonstration of fast optical flip-flop operation, Hill et al. [Nature 432, 206 (2004)] fabricated two SRLs coupled by a single waveguide, rather than a solitary SRL. Nevertheless, the literature shows that a single SRL can also function perfectly as an all-optical memory. In our recent paper [W. Coomans et al., Phys. Rev. A 88, 033813, (2013)], we have raised the question whether coupling two SRLs to realize a single optical memory has any advantage over using a solitary SRL, taking into account the obvious disadvantage of a doubled footprint and power consumption. To provide the answer, we have presented in that paper a numerical study of the dynamical behavior of semiconductor ring lasers coupled by a single bus waveguide, both when weakly coupled and when strongly coupled. We have provided a detailed analysis of the multistable landscape in the coupled system, analyzed the stability of all solutions and related the internal dynamics in the individual lasers to the field effectively measured at the output of the waveguide. We have shown which coupling phases generally promote instabilities and therefore need to be avoided in the design. Regarding all-optical memory operation, we have demonstrated that there is no real advantage for bistable memory operation compared to using a solitary SRL. An increased power suppression ratio has been found to be mainly due to the destructive interference of the SRL fields at the low power port. Also, multistability between several modal configurations has been shown to remain unavoidable.

Adaptive powertrain control for plugin hybrid electric vehicles

DOEpatents

Kedar-Dongarkar, Gurunath; Weslati, Feisel

2013-10-15

A powertrain control system for a plugin hybrid electric vehicle. The system comprises an adaptive charge sustaining controller; at least one internal data source connected to the adaptive charge sustaining controller; and a memory connected to the adaptive charge sustaining controller for storing data generated by the at least one internal data source. The adaptive charge sustaining controller is operable to select an operating mode of the vehicle's powertrain along a given route based on programming generated from data stored in the memory associated with that route. Further described is a method of adaptively controlling operation of a plugin hybrid electric vehicle powertrain comprising identifying a route being traveled, activating stored adaptive charge sustaining mode programming for the identified route and controlling operation of the powertrain along the identified route by selecting from a plurality of operational modes based on the stored adaptive charge sustaining mode programming.

Transferring multiqubit entanglement onto memory qubits in a decoherence-free subspace

NASA Astrophysics Data System (ADS)

He, Xiao-Ling; Yang, Chui-Ping

2017-03-01

Different from the previous works on generating entangled states, this work is focused on how to transfer the prepared entangled states onto memory qubits for protecting them against decoherence. We here consider a physical system consisting of n operation qubits and 2 n memory qubits placed in a cavity or coupled to a resonator. A method is presented for transferring n-qubit Greenberger-Horne-Zeilinger (GHZ) entangled states from the operation qubits (i.e., information processing cells) onto the memory qubits (i.e., information memory elements with long decoherence time). The transferred GHZ states are encoded in a decoherence-free subspace against collective dephasing and thus can be immune from decoherence induced by a dephasing environment. In addition, the state transfer procedure has nothing to do with the number of qubits, the operation time does not increase with the number of qubits, and no measurement is needed for the state transfer. This proposal can be applied to a wide range of hybrid qubits such as natural atoms and artificial atoms (e.g., various solid-state qubits).

Explicit pre-training instruction does not improve implicit perceptual-motor sequence learning

PubMed Central

Sanchez, Daniel J.; Reber, Paul J.

2012-01-01

Memory systems theory argues for separate neural systems supporting implicit and explicit memory in the human brain. Neuropsychological studies support this dissociation, but empirical studies of cognitively healthy participants generally observe that both kinds of memory are acquired to at least some extent, even in implicit learning tasks. A key question is whether this observation reflects parallel intact memory systems or an integrated representation of memory in healthy participants. Learning of complex tasks in which both explicit instruction and practice is used depends on both kinds of memory, and how these systems interact will be an important component of the learning process. Theories that posit an integrated, or single, memory system for both types of memory predict that explicit instruction should contribute directly to strengthening task knowledge. In contrast, if the two types of memory are independent and acquired in parallel, explicit knowledge should have no direct impact and may serve in a “scaffolding” role in complex learning. Using an implicit perceptual-motor sequence learning task, the effect of explicit pre-training instruction on skill learning and performance was assessed. Explicit pre-training instruction led to robust explicit knowledge, but sequence learning did not benefit from the contribution of pre-training sequence memorization. The lack of an instruction benefit suggests that during skill learning, implicit and explicit memory operate independently. While healthy participants will generally accrue parallel implicit and explicit knowledge in complex tasks, these types of information appear to be separately represented in the human brain consistent with multiple memory systems theory. PMID:23280147

Advanced Control Systems for Aircraft Powerplants

DTIC Science & Technology

1980-02-01

production of high- integrity software. 1.0 INTRODUCTION Work on full-authority digital control for gas turbines was started at Rolls- Royce Limited... INTRODUCTION In order to fully understand the operation of the Secondary Power System Control Unit - abbreviated SPSCU - we must first take a close look at...Only Memory EPROM -- Erasable Read Only Memory PLA -- Power Lever Angle LVDT -- Linear Variable Differential Transformer INTRODUCTION Preliminary design

Computer Sciences and Data Systems, volume 1

NASA Technical Reports Server (NTRS)

1987-01-01

Topics addressed include: software engineering; university grants; institutes; concurrent processing; sparse distributed memory; distributed operating systems; intelligent data management processes; expert system for image analysis; fault tolerant software; and architecture research.

Working memory overload: fronto-limbic interactions and effects on subsequent working memory function.

PubMed

Yun, Richard J; Krystal, John H; Mathalon, Daniel H

2010-03-01

The human working memory system provides an experimentally useful model for examination of neural overload effects on subsequent functioning of the overloaded system. This study employed functional magnetic resonance imaging in conjunction with a parametric working memory task to characterize the behavioral and neural effects of cognitive overload on subsequent cognitive performance, with particular attention to cognitive-limbic interactions. Overloading the working memory system was associated with varying degrees of subsequent decline in performance accuracy and reduced activation of brain regions central to both task performance and suppression of negative affect. The degree of performance decline was independently predicted by three separate factors operating during the overload condition: the degree of task failure, the degree of amygdala activation, and the degree of inverse coupling between the amygdala and dorsolateral prefrontal cortex. These findings suggest that vulnerability to overload effects in cognitive functioning may be mediated by reduced amygdala suppression and subsequent amygdala-prefrontal interaction.

Programs for Testing Processor-in-Memory Computing Systems

NASA Technical Reports Server (NTRS)

Katz, Daniel S.

2006-01-01

The Multithreaded Microbenchmarks for Processor-In-Memory (PIM) Compilers, Simulators, and Hardware are computer programs arranged in a series for use in testing the performances of PIM computing systems, including compilers, simulators, and hardware. The programs at the beginning of the series test basic functionality; the programs at subsequent positions in the series test increasingly complex functionality. The programs are intended to be used while designing a PIM system, and can be used to verify that compilers, simulators, and hardware work correctly. The programs can also be used to enable designers of these system components to examine tradeoffs in implementation. Finally, these programs can be run on non-PIM hardware (either single-threaded or multithreaded) using the POSIX pthreads standard to verify that the benchmarks themselves operate correctly. [POSIX (Portable Operating System Interface for UNIX) is a set of standards that define how programs and operating systems interact with each other. pthreads is a library of pre-emptive thread routines that comply with one of the POSIX standards.

[Proposal for a physiologic concept of thought based on the results of stereotaxic psychosurgery].

PubMed

Nádvorník, P; Pogády, J; Bernadic, M

2003-05-01

Authors have fifty years long experience with psychostereotactic surgery. On the bases of 209 operations of different types of mentally ill patients, authors built their own physiological conception of the central nervous system function. The new conception is described using block operators of thinking at the level of hypothalamus, limbic system, and neocortex in the hierarchic order. The basic physiological hypothalamic block contains two operators: stimulus evaluation and decision to act. Both operators together form reasonable, objective substantiation of thinking, which is transformed into psychological, subjective description at higher cerebral levels. New operator is added to the block diagram at the level of the limbic system: the choice of response base on experience stored in the high capacity memory. Vast neocortical memory creates a model of the individual world and it enables a new operator to be involved: prediction of the future events. Thinking, originally based on concrete images, is using abstract terms, subjected to the principles of grammar. Physiological basis of thinking enables the convergence of subjective and objective.

Digital Equipment Corporation VAX/VMS Version 4.3

DTIC Science & Technology

1986-07-30

operating system performs process-oriented paging that allows execution of programs that may be larger than the physical memory allocated to them... to higher privileged modes. (For an explanation of how the four access modes provide memory access protection see page 9, "Memory Management".) A... to optimize program performance for real-time applications or interactive environments. July 30, 1986 - 4 - Final Evaluation Report Digital VAX/VMS

Design, fabrication, testing and delivery of a feasibility model laminated ferrite memory

NASA Technical Reports Server (NTRS)

Heckler, H. C.

1973-01-01

The effect of using multiword addressing with laminated ferrite arrays was made. Both a reduction in the number of components, and a reduction in power consumption was obtained for memory capacities between one million bits and one million words. An investigation into the effect of variations in the processing steps resulted in a number of process modifications that improved the quality of the arrays. A feasibility model laminated ferrite memory system was constructed by modifying a commercial plated wire memory system to operate with laminated ferrite arrays. To provide flexibility for the testing of the laminated ferrite memory, an exerciser has been constructed to automatically control the loading and recirculation of arbitrary size checkerboard patterns of one's and zero's and to display the patterns of stored information on a CRT screen.

Team performance in networked supervisory control of unmanned air vehicles: effects of automation, working memory, and communication content.

PubMed

McKendrick, Ryan; Shaw, Tyler; de Visser, Ewart; Saqer, Haneen; Kidwell, Brian; Parasuraman, Raja

2014-05-01

Assess team performance within a net-worked supervisory control setting while manipulating automated decision aids and monitoring team communication and working memory ability. Networked systems such as multi-unmanned air vehicle (UAV) supervision have complex properties that make prediction of human-system performance difficult. Automated decision aid can provide valuable information to operators, individual abilities can limit or facilitate team performance, and team communication patterns can alter how effectively individuals work together. We hypothesized that reliable automation, higher working memory capacity, and increased communication rates of task-relevant information would offset performance decrements attributed to high task load. Two-person teams performed a simulated air defense task with two levels of task load and three levels of automated aid reliability. Teams communicated and received decision aid messages via chat window text messages. Task Load x Automation effects were significant across all performance measures. Reliable automation limited the decline in team performance with increasing task load. Average team spatial working memory was a stronger predictor than other measures of team working memory. Frequency of team rapport and enemy location communications positively related to team performance, and word count was negatively related to team performance. Reliable decision aiding mitigated team performance decline during increased task load during multi-UAV supervisory control. Team spatial working memory, communication of spatial information, and team rapport predicted team success. An automated decision aid can improve team performance under high task load. Assessment of spatial working memory and the communication of task-relevant information can help in operator and team selection in supervisory control systems.

Multiple channel data acquisition system

DOEpatents

Crawley, H. Bert; Rosenberg, Eli I.; Meyer, W. Thomas; Gorbics, Mark S.; Thomas, William D.; McKay, Roy L.; Homer, Jr., John F.

1990-05-22

A multiple channel data acquisition system for the transfer of large amounts of data from a multiplicity of data channels has a plurality of modules which operate in parallel to convert analog signals to digital data and transfer that data to a communications host via a FASTBUS. Each module has a plurality of submodules which include a front end buffer (FEB) connected to input circuitry having an analog to digital converter with cache memory for each of a plurality of channels. The submodules are interfaced with the FASTBUS via a FASTBUS coupler which controls a module bus and a module memory. The system is triggered to effect rapid parallel data samplings which are stored to the cache memories. The cache memories are uploaded to the FEBs during which zero suppression occurs. The data in the FEBs is reformatted and compressed by a local processor during transfer to the module memory. The FASTBUS coupler is used by the communications host to upload the compressed and formatted data from the module memory. The local processor executes programs which are downloaded to the module memory through the FASTBUS coupler.

Multiple channel data acquisition system

DOEpatents

Crawley, H.B.; Rosenberg, E.I.; Meyer, W.T.; Gorbics, M.S.; Thomas, W.D.; McKay, R.L.; Homer, J.F. Jr.

1990-05-22

A multiple channel data acquisition system for the transfer of large amounts of data from a multiplicity of data channels has a plurality of modules which operate in parallel to convert analog signals to digital data and transfer that data to a communications host via a FASTBUS. Each module has a plurality of submodules which include a front end buffer (FEB) connected to input circuitry having an analog to digital converter with cache memory for each of a plurality of channels. The submodules are interfaced with the FASTBUS via a FASTBUS coupler which controls a module bus and a module memory. The system is triggered to effect rapid parallel data samplings which are stored to the cache memories. The cache memories are uploaded to the FEBs during which zero suppression occurs. The data in the FEBs is reformatted and compressed by a local processor during transfer to the module memory. The FASTBUS coupler is used by the communications host to upload the compressed and formatted data from the module memory. The local processor executes programs which are downloaded to the module memory through the FASTBUS coupler. 25 figs.

On a model of electromagnetic field propagation in ferroelectric media

NASA Astrophysics Data System (ADS)

Picard, Rainer

2007-04-01

The Maxwell system in an anisotropic, inhomogeneous medium with non-linear memory effect produced by a Maxwell type system for the polarization is investigated under low regularity assumptions on data and domain. The particular form of memory in the system is motivated by a model for electromagnetic wave propagation in ferromagnetic materials suggested by Greenberg, MacCamy and Coffman [J.M. Greenberg, R.C. MacCamy, C.V. Coffman, On the long-time behavior of ferroelectric systems, Phys. D 134 (1999) 362-383]. To avoid unnecessary regularity requirements the problem is approached as a system of space-time operator equation in the framework of extrapolation spaces (Sobolev lattices), a theoretical framework developed in [R. Picard, Evolution equations as space-time operator equations, Math. Anal. Appl. 173 (2) (1993) 436-458; R. Picard, Evolution equations as operator equations in lattices of Hilbert spaces, Glasnik Mat. 35 (2000) 111-136]. A solution theory for a large class of ferromagnetic materials confined to an arbitrary open set (with suitably generalized boundary conditions) is obtained.

Key Technologies of Phone Storage Forensics Based on ARM Architecture

NASA Astrophysics Data System (ADS)

Zhang, Jianghan; Che, Shengbing

2018-03-01

Smart phones are mainly running Android, IOS and Windows Phone three mobile platform operating systems. The android smart phone has the best market shares and its processor chips are almost ARM software architecture. The chips memory address mapping mechanism of ARM software architecture is different with x86 software architecture. To forensics to android mart phone, we need to understand three key technologies: memory data acquisition, the conversion mechanism from virtual address to the physical address, and find the system’s key data. This article presents a viable solution which does not rely on the operating system API for a complete solution to these three issues.

A comparison of the Cray-2 performance before and after the installation of memory pseudo-banking

NASA Technical Reports Server (NTRS)

Schmickley, Ronald D.; Bailey, David H.

1987-01-01

A suite of 13 large Fortran benchmark codes were run on a Cray-2 configured with memory pseudo-banking circuits, and floating point operation rates were measured for each under a variety of system load configurations. These were compared with similar flop measurements taken on the same system before installation of the pseudo-banking. A useful memory access efficiency parameter was defined and calculated for both sets of performance rates, allowing a crude quantitative measure of the improvement in efficiency due to pseudo-banking. Programs were categorized as either highly scalar (S) or highly vectorized (V) and either memory-intensive or register-intensive, giving 4 categories: S-memory, S-register, V-memory, and V-register. Using flop rates as a simple quantifier of these 4 categories, a scatter plot of efficiency gain vs Mflops roughly illustrates the improvement in floating point processing speed due to pseudo-banking. On the Cray-2 system tested this improvement ranged from 1 percent for S-memory codes to about 12 percent for V-memory codes. No significant gains were made for V-register codes, which was to be expected.

Helicopter In-Flight Monitoring System Second Generation (HIMS II).

DTIC Science & Technology

1983-08-01

acquisition cycle. B. Computer Chassis CPU (DEC LSI-II/2) -- Executes instructions contained in the memory. 32K memory (DEC MSVII-DD) --Contains program...when the operator executes command #2, 3, or 5 (display data). New cartridges can be inserted as required for truly unlimited, continuous data...is called bootstrapping. The software, which is stored on a tape cartridge, is loaded into memory by execution of a small program stored in read-only

A data acquisition system for coincidence imaging using a conventional dual head gamma camera

NASA Astrophysics Data System (ADS)

Lewellen, T. K.; Miyaoka, R. S.; Jansen, F.; Kaplan, M. S.

1997-06-01

A low cost data acquisition system (DAS) was developed to acquire coincidence data from an unmodified General Electric Maxxus dual head scintillation camera. A high impedance pick-off circuit provides position and energy signals to the DAS without interfering with normal camera operation. The signals are pulse-clipped to reduce pileup effects. Coincidence is determined with fast timing signals derived from constant fraction discriminators. A charge-integrating FERA 16 channel ADC feeds position and energy data to two CAMAC FERA memories operated as ping-pong buffers. A Macintosh PowerPC running Labview controls the system and reads the CAMAC memories. A CAMAC 12-channel scaler records singles and coincidence rate data. The system dead-time is approximately 10% at a coincidence rate of 4.0 kHz.

Quantum Landauer erasure with a molecular nanomagnet

NASA Astrophysics Data System (ADS)

Gaudenzi, R.; Burzurí, E.; Maegawa, S.; van der Zant, H. S. J.; Luis, F.

2018-06-01

The erasure of a bit of information is an irreversible operation whose minimal entropy production of kB ln 2 is set by the Landauer limit1. This limit has been verified in a variety of classical systems, including particles in traps2,3 and nanomagnets4. Here, we extend it to the quantum realm by using a crystal of molecular nanomagnets as a quantum spin memory and showing that its erasure is still governed by the Landauer principle. In contrast to classical systems, maximal energy efficiency is achieved while preserving fast operation owing to its high-speed spin dynamics. The performance of our spin register in terms of energy-time cost is orders of magnitude better than existing memory devices to date. The result shows that thermodynamics sets a limit on the energy cost of certain quantum operations and illustrates a way to enhance classical computations by using a quantum system.

Epicatechin, a component of dark chocolate, enhances memory formation if applied during the memory consolidation period.

PubMed

Fernell, Maria; Swinton, Cayley; Lukowiak, Ken

2016-01-01

Epicatechin (Epi), a flavanol found in foods such as dark chocolate has previously been shown to enhance memory formation in our model system, operant conditioning of aerial respiration in Lymnaea. In those experiments snails were trained in Epi. Here we ask whether snails exposed to Epi before training, during the consolidation period immediately following training, or 1 h after training would enhance memory formation. We report here that Epi is only able to enhance memory if snails are placed in Epi-containing pond water immediately after training. That is, Epi enhances memory formation if it is applied during the memory consolidation period as well as if snails are trained in Epi-containing pond water.

Epicatechin, a component of dark chocolate, enhances memory formation if applied during the memory consolidation period

PubMed Central

Fernell, Maria; Swinton, Cayley; Lukowiak, Ken

2016-01-01

ABSTRACT Epicatechin (Epi), a flavanol found in foods such as dark chocolate has previously been shown to enhance memory formation in our model system, operant conditioning of aerial respiration in Lymnaea. In those experiments snails were trained in Epi. Here we ask whether snails exposed to Epi before training, during the consolidation period immediately following training, or 1 h after training would enhance memory formation. We report here that Epi is only able to enhance memory if snails are placed in Epi-containing pond water immediately after training. That is, Epi enhances memory formation if it is applied during the memory consolidation period as well as if snails are trained in Epi-containing pond water. PMID:27574544

Apparatus and Method for Low-Temperature Training of Shape Memory Alloys

NASA Technical Reports Server (NTRS)

Swanger, A. M.; Fesmire, J. E.; Trigwell, S.; Gibson, T. L.; Williams, M. K.; Benafan, O.

2015-01-01

An apparatus and method for the low-temperature thermo-mechanical training of shape memory alloys (SMA) has been developed. The experimental SMA materials are being evaluated as prototypes for applicability in novel thermal management systems for future cryogenic applications. Alloys providing two-way actuation at cryogenic temperatures are the chief target. The mechanical training regimen was focused on the controlled movement of rectangular strips, with S-bend configurations, at temperatures as low as 30 K. The custom holding fixture included temperature sensors and a low heat-leak linear actuator with a magnetic coupling. The fixture was mounted to a Gifford-McMahon cryocooler providing up to 25 W of cooling power at 20 K and housed within a custom vacuum chamber. Operations included both training cycles and verification of shape memory movement. The system design and operation are discussed. Results of the training for select prototype alloys are presented.

Apparatus and method for low-temperature training of shape memory alloys

NASA Astrophysics Data System (ADS)

Swanger, A. M.; Fesmire, J. E.; Trigwell, S.; Gibson, T. L.; Williams, M. K.; Benafan, O.

2015-12-01

An apparatus and method for the low-temperature thermo-mechanical training of shape memory alloys (SMA) has been developed. The experimental SMA materials are being evaluated as prototypes for applicability in novel thermal management systems for future cryogenic applications. Alloys providing two-way actuation at cryogenic temperatures are the chief target. The mechanical training regimen was focused on the controlled movement of rectangular strips, with S-bend configurations, at temperatures as low as 30 K. The custom holding fixture included temperature sensors and a low heat-leak linear actuator with a magnetic coupling. The fixture was mounted to a Gifford-McMahon cryocooler providing up to 25 W of cooling power at 20 K and housed within a custom vacuum chamber. Operations included both training cycles and verification of shape memory movement. The system design and operation are discussed. Results of the training for select prototype alloys are presented.

Support for non-locking parallel reception of packets belonging to a single memory reception FIFO

DOEpatents

Chen, Dong [Yorktown Heights, NY; Heidelberger, Philip [Yorktown Heights, NY; Salapura, Valentina [Yorktown Heights, NY; Senger, Robert M [Yorktown Heights, NY; Steinmacher-Burow, Burkhard [Boeblingen, DE; Sugawara, Yutaka [Yorktown Heights, NY

2011-01-27

A method and apparatus for distributed parallel messaging in a parallel computing system. A plurality of DMA engine units are configured in a multiprocessor system to operate in parallel, one DMA engine unit for transferring a current packet received at a network reception queue to a memory location in a memory FIFO (rmFIFO) region of a memory. A control unit implements logic to determine whether any prior received packet destined for that rmFIFO is still in a process of being stored in the associated memory by another DMA engine unit of the plurality, and prevent the one DMA engine unit from indicating completion of storing the current received packet in the reception memory FIFO (rmFIFO) until all prior received packets destined for that rmFIFO are completely stored by the other DMA engine units. Thus, there is provided non-locking support so that multiple packets destined for a single rmFIFO are transferred and stored in parallel to predetermined locations in a memory.

Distributed Mission Operations: Training Today’s Warfighters for Tomorrow’s Conflicts

DTIC Science & Technology

2016-02-01

systems or include dissimilar weapons systems to rehearse more complex mission sets. In addition to networking geographically separated simulators...over the past decade. Today, distributed mission operations can facilitate the rehearsal of theater wide operations, integrating all the anticipated...effective that many aviators earn their basic aircraft qualification before their first flight in the airplane.11 Computer memory was once a

DOE Office of Scientific and Technical Information (OSTI.GOV)

Braiman, Yehuda; Neschke, Brendan; Nair, Niketh S.

Here, we study memory states of a circuit consisting of a small inductively coupled Josephson junction array and introduce basic (write, read, and reset) memory operations logics of the circuit. The presented memory operation paradigm is fundamentally different from conventional single quantum flux operation logics. We calculate stability diagrams of the zero-voltage states and outline memory states of the circuit. We also calculate access times and access energies for basic memory operations.

Efficacy of Code Optimization on Cache-based Processors

NASA Technical Reports Server (NTRS)

VanderWijngaart, Rob F.; Chancellor, Marisa K. (Technical Monitor)

1997-01-01

The current common wisdom in the U.S. is that the powerful, cost-effective supercomputers of tomorrow will be based on commodity (RISC) micro-processors with cache memories. Already, most distributed systems in the world use such hardware as building blocks. This shift away from vector supercomputers and towards cache-based systems has brought about a change in programming paradigm, even when ignoring issues of parallelism. Vector machines require inner-loop independence and regular, non-pathological memory strides (usually this means: non-power-of-two strides) to allow efficient vectorization of array operations. Cache-based systems require spatial and temporal locality of data, so that data once read from main memory and stored in high-speed cache memory is used optimally before being written back to main memory. This means that the most cache-friendly array operations are those that feature zero or unit stride, so that each unit of data read from main memory (a cache line) contains information for the next iteration in the loop. Moreover, loops ought to be 'fat', meaning that as many operations as possible are performed on cache data-provided instruction caches do not overflow and enough registers are available. If unit stride is not possible, for example because of some data dependency, then care must be taken to avoid pathological strides, just ads on vector computers. For cache-based systems the issues are more complex, due to the effects of associativity and of non-unit block (cache line) size. But there is more to the story. Most modern micro-processors are superscalar, which means that they can issue several (arithmetic) instructions per clock cycle, provided that there are enough independent instructions in the loop body. This is another argument for providing fat loop bodies. With these restrictions, it appears fairly straightforward to produce code that will run efficiently on any cache-based system. It can be argued that although some of the important computational algorithms employed at NASA Ames require different programming styles on vector machines and cache-based machines, respectively, neither architecture class appeared to be favored by particular algorithms in principle. Practice tells us that the situation is more complicated. This report presents observations and some analysis of performance tuning for cache-based systems. We point out several counterintuitive results that serve as a cautionary reminder that memory accesses are not the only factors that determine performance, and that within the class of cache-based systems, significant differences exist.

Programmable fuzzy associative memory processor

NASA Astrophysics Data System (ADS)

Shao, Lan; Liu, Liren; Li, Guoqiang

1996-02-01

An optical system based on the method of spatial area-coding and multiple image scheme is proposed for fuzzy associative memory processing. Fuzzy maximum operation is accomplished by a ferroelectric liquid crystal PROM instead of a computer-based approach. A relative subsethood is introduced here to be used as a criterion for the recall evaluation.

The Determination of a Useful Frequency for Refreshing Memories for Procedures among a Collegiate Population.

ERIC Educational Resources Information Center

Zambon, Franco

This study sought to determine a useful frequency for refreshing students' memories of complex procedures that involved a formal computer language. Students were required to execute the Microsoft Disc Operating System (MS-DOS) commands for "copy,""backup," and "restore." A total of 126 college students enrolled in six…

Verbal Dominant Memory Impairment and Low Risk for Post-operative Memory Worsening in Both Left and Right Temporal Lobe Epilepsy Associated with Hippocampal Sclerosis.

PubMed

Khalil, Amr Farid; Iwasaki, Masaki; Nishio, Yoshiyuki; Jin, Kazutaka; Nakasato, Nobukazu; Tominaga, Teiji

2016-11-15

Post-operative memory changes after temporal lobe surgery have been established mainly by group analysis of cognitive outcome. This study investigated individual patient-based memory outcome in surgically-treated patients with mesial temporal lobe epilepsy (TLE). This study included 84 consecutive patients with intractable TLE caused by unilateral hippocampal sclerosis (HS) who underwent epilepsy surgery (47 females, 41 left [Lt] TLE). Memory functions were evaluated with the Wechsler Memory Scale-Revised before and at 1 year after surgery. Pre-operative memory function was classified into three patterns: verbal dominant memory impairment (Verb-D), visual dominant impairment (Vis-D), and no material-specific impairment. Post-operative changes in verbal and visual memory indices were classified into meaningful improvement, worsening, or no significant changes. Pre-operative patterns and post-operative changes in verbal and visual memory function were compared between the Lt and right (Rt) TLE groups. Pre-operatively, Verb-D was the most common type of impairment in both the Lt and Rt TLE groups (65.9 and 48.8%), and verbal memory indices were lower than visual memory indices, especially in the Lt compared with Rt TLE group. Vis-D was observed only in 11.6% of Rt and 7.3% of Lt TLE patients. Post-operatively, meaningful improvement of memory indices was observed in 23.3-36.6% of the patients, and the memory improvement was equivalent between Lt and Rt TLE groups and between verbal and visual materials. In conclusion, Verb-D is most commonly observed in patients with both the Lt and Rt TLE associated with HS. Hippocampectomy can improve memory indices in such patients regardless of the side of surgery and the function impaired.

Transfers and Enhancements of the Teleconferencing System and Support of the Special Operations Planning Aids

DTIC Science & Technology

1984-10-31

five colors , page forward, page back, erase, clear the page, store previously annotated material, and later retrieve it. From this developed a four...system to secure sites. These * enchancements are discussed below. -2- .7- -. . . --. J -. . . . .. . . . . . . . ..- . _77 . -.- 2.1 Enhancements to the...and large cache memory of the Winchester drive allows the SGWS software to run much faster when doing file access or direct memory access (DMA) than

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

DOEpatents

Asaad, Sameh W.; Kapur, Mohit

2016-03-15

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Operant conditioning of autobiographical memory retrieval.

PubMed

Debeer, Elise; Raes, Filip; Williams, J Mark G; Craeynest, Miet; Hermans, Dirk

2014-01-01

Functional avoidance is considered as one of the key mechanisms underlying overgeneral autobiographical memory (OGM). According to this view OGM is regarded as a learned cognitive avoidance strategy, based on principles of operant conditioning; i.e., individuals learn to avoid the emotionally painful consequences associated with the retrieval of specific negative memories. The aim of the present study was to test one of the basic assumptions of the functional avoidance account, namely that autobiographical memory retrieval can be brought under operant control. Here 41 students were instructed to retrieve personal memories in response to 60 emotional cue words. Depending on the condition, they were punished with an aversive sound for the retrieval of specific or nonspecific memories in an operant conditioning procedure. Analyzes showed that the course of memory specificity significantly differed between conditions. After the procedure participants punished for nonspecific memories retrieved significantly more specific memories compared to participants punished for specific memories. However, whereas memory specificity significantly increased in participants punished for specific memories, it did not significantly decrease in participants punished for nonspecific memories. Thus, while our findings indicate that autobiographical memory retrieval can be brought under operant control, they do not support a functional avoidance view on OGM.

Optical Associative Processors For Visual Perception"

NASA Astrophysics Data System (ADS)

Casasent, David; Telfer, Brian

1988-05-01

We consider various associative processor modifications required to allow these systems to be used for visual perception, scene analysis, and object recognition. For these applications, decisions on the class of the objects present in the input image are required and thus heteroassociative memories are necessary (rather than the autoassociative memories that have been given most attention). We analyze the performance of both associative processors and note that there is considerable difference between heteroassociative and autoassociative memories. We describe associative processors suitable for realizing functions such as: distortion invariance (using linear discriminant function memory synthesis techniques), noise and image processing performance (using autoassociative memories in cascade with with a heteroassociative processor and with a finite number of autoassociative memory iterations employed), shift invariance (achieved through the use of associative processors operating on feature space data), and the analysis of multiple objects in high noise (which is achieved using associative processing of the output from symbolic correlators). We detail and provide initial demonstrations of the use of associative processors operating on iconic, feature space and symbolic data, as well as adaptive associative processors.

Protecting solid-state spins from a strongly coupled environment

NASA Astrophysics Data System (ADS)

Chen, Mo; Calvin Sun, Won Kyu; Saha, Kasturi; Jaskula, Jean-Christophe; Cappellaro, Paola

2018-06-01

Quantum memories are critical for solid-state quantum computing devices and a good quantum memory requires both long storage time and fast read/write operations. A promising system is the nitrogen-vacancy (NV) center in diamond, where the NV electronic spin serves as the computing qubit and a nearby nuclear spin as the memory qubit. Previous works used remote, weakly coupled 13C nuclear spins, trading read/write speed for long storage time. Here we focus instead on the intrinsic strongly coupled 14N nuclear spin. We first quantitatively understand its decoherence mechanism, identifying as its source the electronic spin that acts as a quantum fluctuator. We then propose a scheme to protect the quantum memory from the fluctuating noise by applying dynamical decoupling on the environment itself. We demonstrate a factor of 3 enhancement of the storage time in a proof-of-principle experiment, showing the potential for a quantum memory that combines fast operation with long coherence time.

Hippocampal contributions to recollection in retrograde and anterograde amnesia.

PubMed

Gilboa, Asaf; Winocur, Gordon; Rosenbaum, R Shayna; Poreh, Amir; Gao, Fuqiang; Black, Sandra E; Westmacott, Robyn; Moscovitch, Morris

2006-01-01

Lesions restricted to the hippocampal formation and/or extended hippocampal system (hippocampal formation, fornix, mammillary bodies, and anterior thalamic nuclei) can disrupt conscious recollection in anterograde amnesia, while leaving familiarity-based memory relatively intact. Familiarity may be supported by extra-hippocampal medial temporal lobe (MTL) structures. Within-task dissociations in recognition memory best exemplify this distinction in anterograde amnesia. The authors report for the first time comparable dissociations within recognition memory in retrograde amnesia. An amnesic patient (A.D.) with bilateral fornix and septal nuclei lesions failed to recognize details pertaining to personal past events only when recollection was required, during recognition of episodic details. His intact recognition of generic and semantic details pertaining to the same events was ascribed to intact familiarity processes. Recollective processes in the controls were reflected by asymmetrical Receiver's Operating Characteristic curves, whereas the patient's Receiver's Operating Characteristic was symmetrical, suggesting that his inferior recognition performance on episodic details was reliant on familiarity processes. Anterograde and retrograde memories were equally affected, with no temporal gradient for retrograde memories. By comparison, another amnesic person (K.C.) with extensive MTL damage (involving extra-hippocampal MTL structures in addition to hippocampal and fornix lesions) had very poor recognition and no recollection of either episodic or generic/semantic details. These data suggest that the extended hippocampal system is required to support recollection for both anterograde and retrograde memories, regardless of their age.

Systems Suitable for Information Professionals.

ERIC Educational Resources Information Center

Blair, John C., Jr.

1983-01-01

Describes computer operating systems applicable to microcomputers, noting hardware components, advantages and disadvantages of each system, local area networks, distributed processing, and a fully configured system. Lists of hardware components (disk drives, solid state disk emulators, input/output and memory components, and processors) and…

Visuospatial declarative learning despite profound verbal declarative amnesia in Korsakoff's syndrome.

PubMed

Oudman, Erik; Postma, Albert; Nijboer, Tanja C W; Wijnia, Jan W; Van der Stigchel, Stefan

2017-03-20

Korsakoff's syndrome (KS) is a neuropsychiatric disorder characterised by severe amnesia. Although the presence of impairments in memory has long been acknowledged, there is a lack of knowledge about the precise characteristics of declarative memory capacities in order to implement memory rehabilitation. In this study, we investigated the extent to which patients diagnosed with KS have preserved declarative memory capacities in working memory, long-term memory encoding or long-term memory recall operations, and whether these capacities are most preserved for verbal or visuospatial content. The results of this study demonstrate that patients with KS have compromised declarative memory functioning on all memory indices. Performance was lowest for the encoding operation compared to the working memory and delayed recall operation. With respect to the content, visuospatial memory was relatively better preserved than verbal memory. All memory operations functioned suboptimally, although the most pronounced disturbance was found in verbal memory encoding. Based on the preserved declarative memory capacities in patients, visuospatial memory can form a more promising target for compensatory memory rehabilitation than verbal memory. It is therefore relevant to increase the number of spatial cues in memory rehabilitation for KS patients.

Solitonic Josephson-based meminductive systems

NASA Astrophysics Data System (ADS)

Guarcello, Claudio; Solinas, Paolo; di Ventra, Massimiliano; Giazotto, Francesco

2017-04-01

Memristors, memcapacitors, and meminductors represent an innovative generation of circuit elements whose properties depend on the state and history of the system. The hysteretic behavior of one of their constituent variables, is their distinctive fingerprint. This feature endows them with the ability to store and process information on the same physical location, a property that is expected to benefit many applications ranging from unconventional computing to adaptive electronics to robotics. Therefore, it is important to find appropriate memory elements that combine a wide range of memory states, long memory retention times, and protection against unavoidable noise. Although several physical systems belong to the general class of memelements, few of them combine these important physical features in a single component. Here, we demonstrate theoretically a superconducting memory based on solitonic long Josephson junctions. Moreover, since solitons are at the core of its operation, this system provides an intrinsic topological protection against external perturbations. We show that the Josephson critical current behaves hysteretically as an external magnetic field is properly swept. Accordingly, long Josephson junctions can be used as multi-state memories, with a controllable number of available states, and in other emerging areas such as memcomputing, i.e., computing directly in/by the memory.

Mechanisms for widespread hippocampal involvement in cognition

PubMed Central

Shohamy, Daphna; Turk-Browne, Nicholas B.

2014-01-01

The quintessential memory system in the human brain — the hippocampus and surrounding medial temporal lobe (MTL) — is often treated as a module for the formation of conscious, or declarative memories. However, growing evidence suggests that the hippocampus plays a broader role in memory and cognition and that theories organizing memory into strictly dedicated systems may need to be updated. We first consider the historical evidence for the specialized role of the hippocampus in declarative memory. Then, we describe the serendipitous encounter that motivated this special section, based on parallel research from our labs that suggested a more pervasive contribution of the hippocampus to cognition beyond declarative memory. Finally, we develop a theoretical framework that describes two general mechanisms for how the hippocampus interacts with other brain systems and cognitive processes: the Memory Modulation Hypothesis, in which mnemonic representations in the hippocampus modulate the operation of other systems, and the Adaptive Function Hypothesis, in which specialized computations in the hippocampus are recruited as a component of both mnemonic and non-mnemonic functions. This framework is consistent with an emerging view that the most fertile ground for discovery in cognitive psychology and neuroscience lies at the interface between parts of the mind and brain that have traditionally been studied in isolation. PMID:24246058

Redundant single event upset supression system

DOEpatents

Hoff, James R.

2006-04-04

CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further as a memory that can overcome the effects of radiation. As an SR-flip flop, the invention can be altered into any known type of latch or flip-flop by the application of external logic, thereby extending radiation tolerance to devices previously incapable of radiation tolerance. Numerous registers can be logically connected and replicated thereby being electronically configured to operate as a redundant circuit.

Chip architecture - A revolution brewing

NASA Astrophysics Data System (ADS)

Guterl, F.

1983-07-01

Techniques being explored by microchip designers and manufacturers to both speed up memory access and instruction execution while protecting memory are discussed. Attention is given to hardwiring control logic, pipelining for parallel processing, devising orthogonal instruction sets for interchangeable instruction fields, and the development of hardware for implementation of virtual memory and multiuser systems to provide memory management and protection. The inclusion of microcode in mainframes eliminated logic circuits that control timing and gating of the CPU. However, improvements in memory architecture have reduced access time to below that needed for instruction execution. Hardwiring the functions as a virtual memory enhances memory protection. Parallelism involves a redundant architecture, which allows identical operations to be performed simultaneously, and can be directed with microcode to avoid abortion of intermediate instructions once on set of instructions has been completed.

Silent store detection and recording in memory storage

DOEpatents

Bose, Pradip; Cher, Chen-Yong; Nair, Ravi

2017-03-07

An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.

Silent store detection and recording in memory storage

DOEpatents

Bose, Pradip; Cher, Chen-Yong; Nair, Ravi

2016-09-20

An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.

40 CFR 1033.112 - Emission diagnostics for SCR systems.

Code of Federal Regulations, 2013 CFR

2013-07-01

.... This section does not apply for SCR systems using the engine's fuel as the reductant. (a) The... computer memory all incidents of engine operation with inadequate reductant injection or reductant quality...

Fault tolerant computing: A preamble for assuring viability of large computer systems

NASA Technical Reports Server (NTRS)

Lim, R. S.

1977-01-01

The need for fault-tolerant computing is addressed from the viewpoints of (1) why it is needed, (2) how to apply it in the current state of technology, and (3) what it means in the context of the Phoenix computer system and other related systems. To this end, the value of concurrent error detection and correction is described. User protection, program retry, and repair are among the factors considered. The technology of algebraic codes to protect memory systems and arithmetic codes to protect memory systems and arithmetic codes to protect arithmetic operations is discussed.

Ada Compiler Validation Summary Report: Certificate Number: 900121S1. 10251 Computer Sciences Corporation MC Ada V1.2.Beta/Concurrent Computer Corporation Concurrent/Masscomp 5600 Host To Concurrent/Masscomp 5600 (Dual 68020 Processor Configuration) Target

DTIC Science & Technology

1990-04-23

developed Ada Real - Time Operating System (ARTOS) for bare machine environments(Target), ACW 1.1I0. " ; - -M.UIECTTERMS Ada programming language, Ada...configuration) Operating System: CSC developed Ada Real - Time Operating System (ARTOS) for bare machine environments Memory Size: 4MB 2.2...Test Method Testing of the MC Ado V1.2.beta/ Concurrent Computer Corporation compiler and the CSC developed Ada Real - Time Operating System (ARTOS) for

An Adaptive Memory Interface Controller for Improving Bandwidth Utilization of Hybrid and Reconfigurable Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Castellana, Vito G.; Tumeo, Antonino; Ferrandi, Fabrizio

Emerging applications such as data mining, bioinformatics, knowledge discovery, social network analysis are irregular. They use data structures based on pointers or linked lists, such as graphs, unbalanced trees or unstructures grids, which generates unpredictable memory accesses. These data structures usually are large, but difficult to partition. These applications mostly are memory bandwidth bounded and have high synchronization intensity. However, they also have large amounts of inherent dynamic parallelism, because they potentially perform a task for each one of the element they are exploring. Several efforts are looking at accelerating these applications on hybrid architectures, which integrate general purpose processorsmore » with reconfigurable devices. Some solutions, which demonstrated significant speedups, include custom-hand tuned accelerators or even full processor architectures on the reconfigurable logic. In this paper we present an approach for the automatic synthesis of accelerators from C, targeted at irregular applications. In contrast to typical High Level Synthesis paradigms, which construct a centralized Finite State Machine, our approach generates dynamically scheduled hardware components. While parallelism exploitation in typical HLS-generated accelerators is usually bound within a single execution flow, our solution allows concurrently running multiple execution flow, thus also exploiting the coarser grain task parallelism of irregular applications. Our approach supports multiple, multi-ported and distributed memories, and atomic memory operations. Its main objective is parallelizing as many memory operations as possible, independently from their execution time, to maximize the memory bandwidth utilization. This significantly differs from current HLS flows, which usually consider a single memory port and require precise scheduling of memory operations. A key innovation of our approach is the generation of a memory interface controller, which dynamically maps concurrent memory accesses to multiple ports. We present a case study on a typical irregular kernel, Graph Breadth First search (BFS), exploring different tradeoffs in terms of parallelism and number of memories.« less

A FPGA-based Measurement System for Nonvolatile Semiconductor Memory Characterization

NASA Astrophysics Data System (ADS)

Bu, Jiankang; White, Marvin

2002-03-01

Low voltage, long retention, high density SONOS nonvolatile semiconductor memory (NVSM) devices are ideally suited for PCMCIA, FLASH and 'smart' cards. The SONOS memory transistor requires characterization with an accurate, rapid measurement system with minimum disturbance to the device. The FPGA-based measurement system includes three parts: 1) a pattern generator implemented with XILINX FPGAs and corresponding software, 2) a high-speed, constant-current, threshold voltage detection circuit, 3) and a data evaluation program, implemented with a LABVIEW program. Fig. 1 shows the general block diagram of the FPGA-based measurement system. The function generator is designed and simulated with XILINX Foundation Software. Under the control of the specific erase/write/read pulses, the analog detect circuit applies operational modes to the SONOS device under test (DUT) and determines the change of the memory-state of the SONOS nonvolatile memory transistor. The TEK460 digitizes the analog threshold voltage output and sends to the PC computer. The data is filtered and averaged with a LABVIEWTM program running on the PC computer and displayed on the monitor in real time. We have implemented the pattern generator with XILINX FPGAs. Fig. 2 shows the block diagram of the pattern generator. We realized the logic control by a method of state machine design. Fig. 3 shows a small part of the state machine. The flexibility of the FPGAs enhances the capabilities of this system and allows measurement variations without hardware changes. The characterization of the nonvolatile memory transistor device under test (DUT), as function of programming voltage and time, is achieved by a high-speed, constant-current threshold voltage detection circuit. The analog detection circuit incorporating fast analog switches controlled digitally with the FPGAs. The schematic circuit diagram is shown in Fig. 4. The various operational modes for the DUT are realized with control signals applied to the analog switches (SW) as shown in Fig. 5. A LABVIEWTM program, on a PC platform, collects and processes the data. The data is displayed on the monitor in real time. This time-domain filtering reduces the digitizing error. Fig. 6 shows the data processing. SONOS nonvolatile semiconductor memories are characterized by erase/write, retention and endurance measurements. Fig. 7 shows the erase/write characteristics of an n-Channel, 5V prog-rammable SONOS memory transistor. Fig.8 shows the retention characteristic of the same SONOS transistor. We have used this system to characterize SONOS nonvolatile semiconductor memory transistors. The attractive features of the test system design lies in the cost-effectiveness and flexibility of the test pattern implementation, fast read-out of memory state, low power, high precision determination of the device threshold voltage, and perhaps most importantly, minimum disturbance, which is indispensable for nonvolatile memory characterization.

Android Protection Mechanism: A Signed Code Security Mechanism for Smartphone Applications

DTIC Science & Technology

2011-03-01

status registers, exceptions, endian support, unaligned access support, synchronization primitives , the Jazelle Extension, and saturated integer...supports comprehensive non-blocking shared-memory synchronization primitives that scale for multiple-processor system designs. This is an improvement... synchronization . Memory semaphores can be loaded and altered without interruption because the load and store operations are atomic. Processor

MHD Flow Control

DTIC Science & Technology

2006-09-01

Umj) flj + GjE(Umj)flyjI A S + fS do (3.7)I This system (3.6) is integrated in time using explicit low-memory Runge-Kutta method: I U o=U" Ui =UO - ci At...signals are registered by the four-channel digital memory oscilloscopes Tektronix TDS 2414 and ASK 3107. Scheme of operation The scheme of the experiment is

Feedforward, high density, programmable read only neural network based memory system

NASA Technical Reports Server (NTRS)

Daud, Taher; Moopenn, Alex; Lamb, James; Thakoor, Anil; Khanna, Satish

1988-01-01

Neural network-inspired, nonvolatile, programmable associative memory using thin-film technology is demonstrated. The details of the architecture, which uses programmable resistive connection matrices in synaptic arrays and current summing and thresholding amplifiers as neurons, are described. Several synapse configurations for a high-density array of a binary connection matrix are also described. Test circuits are evaluated for operational feasibility and to demonstrate the speed of the read operation. The results are discussed to highlight the potential for a read data rate exceeding 10 megabits/sec.

Episodic but not semantic order memory difficulties in autism spectrum disorder: evidence from the Historical Figures Task.

PubMed

Gaigg, Sebastian B; Bowler, Dermot M; Gardiner, John M

2014-01-01

Considerable evidence suggests that the episodic memory system operates abnormally in autism spectrum disorder (ASD) whereas the functions of the semantic memory system are relatively preserved. Here we show that the same dissociation also applies to the domain of order memory. We asked adult participants to order the names of famous historical figures either according to their chronological order in history (probing semantic memory) or according to a random sequence shown once on a screen (probing episodic memory). As predicted, adults with ASD performed less well than age- and IQ-matched comparison individuals only on the episodic task. This observation is of considerable importance in the context of developmental theory because semantic and episodic order memory abilities can be dissociated in typically developing infants before they reach the age at which the behavioural markers associated with ASD are first apparent. This raises the possibility that early emerging memory abnormalities play a role in shaping the developmental trajectory of the disorder. We discuss the broader implications of this possibility and highlight the urgent need for greater scrutiny of memory competences in ASD early in development.

Making the case that episodic recollection is attributable to operations occurring at retrieval rather than to content stored in a dedicated subsystem of long-term memory

PubMed Central

Klein, Stanley B.

2013-01-01

Episodic memory often is conceptualized as a uniquely human system of long-term memory that makes available knowledge accompanied by the temporal and spatial context in which that knowledge was acquired. Retrieval from episodic memory entails a form of first–person subjectivity called autonoetic consciousness that provides a sense that a recollection was something that took place in the experiencer's personal past. In this paper I expand on this definition of episodic memory. Specifically, I suggest that (1) the core features assumed unique to episodic memory are shared by semantic memory, (2) episodic memory cannot be fully understood unless one appreciates that episodic recollection requires the coordinated function of a number of distinct, yet interacting, “enabling” systems. Although these systems—ownership, self, subjective temporality, and agency—are not traditionally viewed as memorial in nature, each is necessary for episodic recollection and jointly they may be sufficient, and (3) the type of subjective awareness provided by episodic recollection (autonoetic) is relational rather than intrinsic—i.e., it can be lost in certain patient populations, thus rendering episodic memory content indistinguishable from the content of semantic long-term memory. PMID:23378832

Solar energy system performance evaluation - Seasonal Report for Seeco Lincoln, Lincoln, Nebraska

DOE Office of Scientific and Technical Information (OSTI.GOV)

None

1980-06-01

The SEECO Lincoln Solar Energy System was designed to provide 60 percent of the space heating for the 50 seat Hyde Memorial Observatory in Lincoln, Nebraska. The system consists of nine SEECO Mod 1 flat plate air collectors (481 square feet), a 347 cubic foot rock storage bin, blowers, controls and air ducting. An auxiliary natural gas furnace provides additional energy when the solar energy is not adequate to meet the space heating demand. The system has five modes of operation. System description, typical system operation, system operating sequence, performance assessment, system performance, subsystem performance (collector array, storage, space heating),more » operating energy, energy savings and maintenance are discussed.« less

Post-traumatic stress disorder and head injury as a dual diagnosis: "islands" of memory as a mechanism.

PubMed Central

King, N S

1997-01-01

This case study describes post-traumatic stress disorder (PTSD) and head injury after a road traffic accident involving a pedestrian. Previous studies have proposed two mechanisms by which this dual diagnosis may occur: (1) when post-traumatic amnesia and retrograde amnesia are small or non-existent and (2) when non-declarative memory systems for the traumatic event are in operation. This case study demonstrates a third mechanism--"islands" of memory within post-traumatic amnesia. PMID:9010405

Post-traumatic stress disorder and head injury as a dual diagnosis: "islands" of memory as a mechanism.

PubMed

King, N S

1997-01-01

This case study describes post-traumatic stress disorder (PTSD) and head injury after a road traffic accident involving a pedestrian. Previous studies have proposed two mechanisms by which this dual diagnosis may occur: (1) when post-traumatic amnesia and retrograde amnesia are small or non-existent and (2) when non-declarative memory systems for the traumatic event are in operation. This case study demonstrates a third mechanism--"islands" of memory within post-traumatic amnesia.

Performance Analysis of the NAS Y-MP Workload

NASA Technical Reports Server (NTRS)

Bergeron, Robert J.; Kutler, Paul (Technical Monitor)

1997-01-01

This paper describes the performance characteristics of the computational workloads on the NAS Cray Y-MP machines, a Y-MP 832 and later a Y-MP 8128. Hardware measurements indicated that the Y-MP workload performance matured over time, ultimately sustaining an average throughput of 0.8 GFLOPS and a vector operation fraction of 87%. The measurements also revealed an operation rate exceeding 1 per clock period, a well-balanced architecture featuring a strong utilization of vector functional units, and an efficient memory organization. Introduction of the larger memory 8128 increased throughput by allowing a more efficient utilization of CPUs. Throughput also depended on the metering of the batch queues; low-idle Saturday workloads required a buffer of small jobs to prevent memory starvation of the CPU. UNICOS required about 7% of total CPU time to service the 832 workloads; this overhead decreased to 5% for the 8128 workloads. While most of the system time went to service I/O requests, efficient scheduling prevented excessive idle due to I/O wait. System measurements disclosed no obvious bottlenecks in the response of the machine and UNICOS to the workloads. In most cases, Cray-provided software tools were- quite sufficient for measuring the performance of both the machine and operating, system.

The performance of disk arrays in shared-memory database machines

NASA Technical Reports Server (NTRS)

Katz, Randy H.; Hong, Wei

1993-01-01

In this paper, we examine how disk arrays and shared memory multiprocessors lead to an effective method for constructing database machines for general-purpose complex query processing. We show that disk arrays can lead to cost-effective storage systems if they are configured from suitably small formfactor disk drives. We introduce the storage system metric data temperature as a way to evaluate how well a disk configuration can sustain its workload, and we show that disk arrays can sustain the same data temperature as a more expensive mirrored-disk configuration. We use the metric to evaluate the performance of disk arrays in XPRS, an operational shared-memory multiprocessor database system being developed at the University of California, Berkeley.

Tuning collective communication for Partitioned Global Address Space programming models

DOE PAGES

Nishtala, Rajesh; Zheng, Yili; Hargrove, Paul H.; ...

2011-06-12

Partitioned Global Address Space (PGAS) languages offer programmers the convenience of a shared memory programming style combined with locality control necessary to run on large-scale distributed memory systems. Even within a PGAS language programmers often need to perform global communication operations such as broadcasts or reductions, which are best performed as collective operations in which a group of threads work together to perform the operation. In this study we consider the problem of implementing collective communication within PGAS languages and explore some of the design trade-offs in both the interface and implementation. In particular, PGAS collectives have semantic issues thatmore » are different than in send–receive style message passing programs, and different implementation approaches that take advantage of the one-sided communication style in these languages. We present an implementation framework for PGAS collectives as part of the GASNet communication layer, which supports shared memory, distributed memory and hybrids. The framework supports a broad set of algorithms for each collective, over which the implementation may be automatically tuned. In conclusion, we demonstrate the benefit of optimized GASNet collectives using application benchmarks written in UPC, and demonstrate that the GASNet collectives can deliver scalable performance on a variety of state-of-the-art parallel machines including a Cray XT4, an IBM BlueGene/P, and a Sun Constellation system with InfiniBand interconnect.« less

Common oscillatory mechanisms across multiple memory systems

NASA Astrophysics Data System (ADS)

Headley, Drew B.; Paré, Denis

2017-01-01

The cortex, hippocampus, and striatum support dissociable forms of memory. While each of these regions contains specialized circuitry supporting their respective functions, all structure their activities across time with delta, theta, and gamma rhythms. We review how these oscillations are generated and how they coordinate distinct memory systems during encoding, consolidation, and retrieval. First, gamma oscillations occur in all regions and coordinate local spiking, compressing it into short population bursts. Second, gamma oscillations are modulated by delta and theta oscillations. Third, oscillatory dynamics in these memory systems can operate in either a "slow" or "fast" mode. The slow mode happens during slow-wave sleep and is characterized by large irregular activity in the hippocampus and delta oscillations in cortical and striatal circuits. The fast mode occurs during active waking and rapid eye movement (REM) sleep and is characterized by theta oscillations in the hippocampus and its targets, along with gamma oscillations in the rest of cortex. In waking, the fast mode is associated with the efficacious encoding and retrieval of declarative and procedural memories. Theta and gamma oscillations have similar relationships with encoding and retrieval across multiple forms of memory and brain regions, despite regional differences in microcircuitry and information content. Differences in the oscillatory coordination of memory systems during sleep might explain why the consolidation of some forms of memory is sensitive to slow-wave sleep, while others depend on REM. In particular, theta oscillations appear to support the consolidation of certain types of procedural memories during REM, while delta oscillations during slow-wave sleep seem to promote declarative and procedural memories.

Concurrent array-based queue

DOEpatents

Heidelberger, Philip; Steinmacher-Burow, Burkhard

2015-01-06

According to one embodiment, a method for implementing an array-based queue in memory of a memory system that includes a controller includes configuring, in the memory, metadata of the array-based queue. The configuring comprises defining, in metadata, an array start location in the memory for the array-based queue, defining, in the metadata, an array size for the array-based queue, defining, in the metadata, a queue top for the array-based queue and defining, in the metadata, a queue bottom for the array-based queue. The method also includes the controller serving a request for an operation on the queue, the request providing the location in the memory of the metadata of the queue.

A Fault-Tolerant Radiation-Robust Mass Storage Concept for Highly Scaled Flash Memory

NASA Astrophysics Data System (ADS)

Fuchs, Cristian M.; Trinitis, Carsten; Appel, Nicolas; Langer, Martin

2015-09-01

Future spacemissions will require vast amounts of data to be stored and processed aboard spacecraft. While satisfying operational mission requirements, storage systems must guarantee data integrity and recover damaged data throughout the mission. NAND-flash memories have become popular for space-borne high performance mass memory scenarios, though future storage concepts will rely upon highly scaled flash or other memory technologies. With modern flash memory, single bit erasure coding and RAID based concepts are insufficient. Thus, a fully run-time configurable, high performance, dependable storage concept, requiring a minimal set of logic or software. The solution is based on composite erasure coding and can be adjusted for altered mission duration or changing environmental conditions.

Implementing an ADA Kernel on NEBULA.

DTIC Science & Technology

1983-08-01

physical address(es). No instruction supports directly semaphore operations , or spin-locks, or other entities used in the synchronisation of tasks...these operations It is found that NEBULA supports admirably the control structures oil Ada, but its Memory Mamagement system is not very suitable. Entry... operating system . With the advent of Ada, in theory at least, the whole program can be written in Ada in a manner that is independent of the computer and of

Study and Design of Flight Data Recording Systems for Military Aircraft

DTIC Science & Technology

1976-06-01

minicomputer (PDP-11/ 40 ) with 24K of core memory and a disk operating system. Peripherals include a CRT terminal, two 9-track magnetic tape drives, a 19 high...in question-answer mode. The NTSB plans to adapt an existing routine to the PDP 11/ 40 which will prepare a ground track of the aircraft from the...20 microseconds). Like PMOS memory, multiple power supplies were required. The next generation of microprocessors were implemented on a 40 pin package

Integrating Software Modules For Robot Control

NASA Technical Reports Server (NTRS)

Volpe, Richard A.; Khosla, Pradeep; Stewart, David B.

1993-01-01

Reconfigurable, sensor-based control system uses state variables in systematic integration of reusable control modules. Designed for open-architecture hardware including many general-purpose microprocessors, each having own local memory plus access to global shared memory. Implemented in software as extension of Chimera II real-time operating system. Provides transparent computing mechanism for intertask communication between control modules and generic process-module architecture for multiprocessor realtime computation. Used to control robot arm. Proves useful in variety of other control and robotic applications.

Non-Markovian quantum processes: Complete framework and efficient characterization

NASA Astrophysics Data System (ADS)

Pollock, Felix A.; Rodríguez-Rosario, César; Frauenheim, Thomas; Paternostro, Mauro; Modi, Kavan

2018-01-01

Currently, there is no systematic way to describe a quantum process with memory solely in terms of experimentally accessible quantities. However, recent technological advances mean we have control over systems at scales where memory effects are non-negligible. The lack of such an operational description has hindered advances in understanding physical, chemical, and biological processes, where often unjustified theoretical assumptions are made to render a dynamical description tractable. This has led to theories plagued with unphysical results and no consensus on what a quantum Markov (memoryless) process is. Here, we develop a universal framework to characterize arbitrary non-Markovian quantum processes. We show how a multitime non-Markovian process can be reconstructed experimentally, and that it has a natural representation as a many-body quantum state, where temporal correlations are mapped to spatial ones. Moreover, this state is expected to have an efficient matrix-product-operator form in many cases. Our framework constitutes a systematic tool for the effective description of memory-bearing open-system evolutions.

Systems and methods for detecting a failure event in a field programmable gate array

NASA Technical Reports Server (NTRS)

Ng, Tak-Kwong (Inventor); Herath, Jeffrey A. (Inventor)

2009-01-01

An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.

Organisational Structure and Information Technology (IT): Exploring the Implications of IT for Future Military Structures

DTIC Science & Technology

2006-07-01

4 Abbreviations AI Artificial Intelligence AM Artificial Memory CAD Computer Aided...memory (AM), artificial intelligence (AI), and embedded knowledge systems it is possible to expand the “effective span of competence” of...Technology J Joint J2 Joint Intelligence J3 Joint Operations NATO North Atlantic Treaty Organisation NCW Network Centric Warfare NHS National Health

Associative Processes in Intuitive Judgment

PubMed Central

Morewedge, Carey K.; Kahneman, Daniel

2014-01-01

Dual-system models of reasoning attribute errors of judgment to two failures. The automatic operations of a “System 1” generate a faulty intuition, which the controlled operations of a “System 2” fail to detect and correct. We identify System 1 with the automatic operations of associative memory and draw on research in the priming paradigm to describe how it operates. We explain how three features of associative memory—associative coherence, attribute substitution, and processing fluency—give rise to major biases of intuitive judgment. Our article highlights both the ability of System 1 to create complex and skilled judgments and the role of the system as a source of judgment errors. PMID:20696611

Multi-processor including data flow accelerator module

DOEpatents

Davidson, George S.; Pierce, Paul E.

1990-01-01

An accelerator module for a data flow computer includes an intelligent memory. The module is added to a multiprocessor arrangement and uses a shared tagged memory architecture in the data flow computer. The intelligent memory module assigns locations for holding data values in correspondence with arcs leading to a node in a data dependency graph. Each primitive computation is associated with a corresponding memory cell, including a number of slots for operands needed to execute a primitive computation, a primitive identifying pointer, and linking slots for distributing the result of the cell computation to other cells requiring that result as an operand. Circuitry is provided for utilizing tag bits to determine automatically when all operands required by a processor are available and for scheduling the primitive for execution in a queue. Each memory cell of the module may be associated with any of the primitives, and the particular primitive to be executed by the processor associated with the cell is identified by providing an index, such as the cell number for the primitive, to the primitive lookup table of starting addresses. The module thus serves to perform functions previously performed by a number of sections of data flow architectures and coexists with conventional shared memory therein. A multiprocessing system including the module operates in a hybrid mode, wherein the same processing modules are used to perform some processing in a sequential mode, under immediate control of an operating system, while performing other processing in a data flow mode.

Evaluation of 1.5-T Cell Flash Memory Total Ionizing Dose Response

NASA Astrophysics Data System (ADS)

Clark, Lawrence T.; Holbert, Keith E.; Adams, James W.; Navale, Harshad; Anderson, Blake C.

2015-12-01

Flash memory is an essential part of systems used in harsh environments, experienced by both terrestrial and aerospace TID applications. This paper presents studies of COTS flash memory TID hardness. While there is substantial literature on flash memory TID response, this work focuses for the first time on 1.5 transistor per cell flash memory. The experimental results show hardness varying from about 100 krad(Si) to over 250 krad(Si) depending on the usage model. We explore the circuit and device aspects of the results, based on the extensive reliability literature for this flash memory type. Failure modes indicate both device damage and circuit marginalities. Sector erase failure limits, but read only operation allows TID exceeding 200 krad(Si). The failures are analyzed by type.

AIRNET: A real-time comunications network for aircraft

NASA Technical Reports Server (NTRS)

Weaver, Alfred C.; Cain, Brendan G.; Colvin, M. Alexander; Simoncic, Robert

1990-01-01

A real-time local area network was developed for use on aircraft and space vehicles. It uses token ring technology to provide high throughput, low latency, and high reliability. The system was implemented on PCs and PC/ATs operating on PCbus, and on Intel 8086/186/286/386s operating on Multibus. A standard IEEE 802.2 logical link control interface was provided to (optional) upper layer software; this permits the controls designer to utilize standard communications protocols (e.g., ISO, TCP/IP) if time permits, or to utilize a very fast link level protocol directly if speed is critical. Both unacknowledged datagram and reliable virtual circuit services are supported. A station operating an 8 MHz Intel 286 as a host can generate a sustained load of 1.8 megabits per second per station, and a 100-byte message can be delivered from the transmitter's user memory to the receiver's user memory, including all operating system and network overhead, in under 4 milliseconds.

Experimental test of Landauer’s principle in single-bit operations on nanomagnetic memory bits

PubMed Central

Hong, Jeongmin; Lambson, Brian; Dhuey, Scott; Bokor, Jeffrey

2016-01-01

Minimizing energy dissipation has emerged as the key challenge in continuing to scale the performance of digital computers. The question of whether there exists a fundamental lower limit to the energy required for digital operations is therefore of great interest. A well-known theoretical result put forward by Landauer states that any irreversible single-bit operation on a physical memory element in contact with a heat bath at a temperature T requires at least kBT ln(2) of heat be dissipated from the memory into the environment, where kB is the Boltzmann constant. We report an experimental investigation of the intrinsic energy loss of an adiabatic single-bit reset operation using nanoscale magnetic memory bits, by far the most ubiquitous digital storage technology in use today. Through sensitive, high-precision magnetometry measurements, we observed that the amount of dissipated energy in this process is consistent (within 2 SDs of experimental uncertainty) with the Landauer limit. This result reinforces the connection between “information thermodynamics” and physical systems and also provides a foundation for the development of practical information processing technologies that approach the fundamental limit of energy dissipation. The significance of the result includes insightful direction for future development of information technology. PMID:26998519

Using a Cray Y-MP as an array processor for a RISC Workstation

NASA Technical Reports Server (NTRS)

Lamaster, Hugh; Rogallo, Sarah J.

1992-01-01

As microprocessors increase in power, the economics of centralized computing has changed dramatically. At the beginning of the 1980's, mainframes and super computers were often considered to be cost-effective machines for scalar computing. Today, microprocessor-based RISC (reduced-instruction-set computer) systems have displaced many uses of mainframes and supercomputers. Supercomputers are still cost competitive when processing jobs that require both large memory size and high memory bandwidth. One such application is array processing. Certain numerical operations are appropriate to use in a Remote Procedure Call (RPC)-based environment. Matrix multiplication is an example of an operation that can have a sufficient number of arithmetic operations to amortize the cost of an RPC call. An experiment which demonstrates that matrix multiplication can be executed remotely on a large system to speed the execution over that experienced on a workstation is described.

Feasibility of self-correcting quantum memory and thermal stability of topological order

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yoshida, Beni, E-mail: rouge@mit.edu

2011-10-15

Recently, it has become apparent that the thermal stability of topologically ordered systems at finite temperature, as discussed in condensed matter physics, can be studied by addressing the feasibility of self-correcting quantum memory, as discussed in quantum information science. Here, with this correspondence in mind, we propose a model of quantum codes that may cover a large class of physically realizable quantum memory. The model is supported by a certain class of gapped spin Hamiltonians, called stabilizer Hamiltonians, with translation symmetries and a small number of ground states that does not grow with the system size. We show that themore » model does not work as self-correcting quantum memory due to a certain topological constraint on geometric shapes of its logical operators. This quantum coding theoretical result implies that systems covered or approximated by the model cannot have thermally stable topological order, meaning that systems cannot be stable against both thermal fluctuations and local perturbations simultaneously in two and three spatial dimensions. - Highlights: > We define a class of physically realizable quantum codes. > We determine their coding and physical properties completely. > We establish the connection between topological order and self-correcting memory. > We find they do not work as self-correcting quantum memory. > We find they do not have thermally stable topological order.« less

Programming for energy monitoring/display system in multicolor lidar system research

NASA Technical Reports Server (NTRS)

Alvarado, R. C., Jr.; Allen, R. J.

1982-01-01

The Z80 microprocessor based computer program that directs and controls the operation of the six channel energy monitoring/display system that is a part of the NASA Multipurpose Airborne Differential Absorption Lidar (DIAL) system is described. The program is written in the Z80 assembly language and is located on EPROM memories. All source and assembled listings of the main program, five subroutines, and two service routines along with flow charts and memory maps are included. A combinational block diagram shows the interfacing (including port addresses) between the six power sensors, displays, front panel controls, the main general purpose minicomputer, and this dedicated microcomputer system.

Acute transient cognitive dysfunction and acute brain injury induced by systemic inflammation occur by dissociable IL-1-dependent mechanisms.

PubMed

Skelly, Donal T; Griffin, Éadaoin W; Murray, Carol L; Harney, Sarah; O'Boyle, Conor; Hennessy, Edel; Dansereau, Marc-Andre; Nazmi, Arshed; Tortorelli, Lucas; Rawlins, J Nicholas; Bannerman, David M; Cunningham, Colm

2018-06-06

Systemic inflammation can impair cognition with relevance to dementia, delirium and post-operative cognitive dysfunction. Episodes of delirium also contribute to rates of long-term cognitive decline, implying that these acute events induce injury. Whether systemic inflammation-induced acute dysfunction and acute brain injury occur by overlapping or discrete mechanisms remains unexplored. Here we show that systemic inflammation, induced by bacterial LPS, produces both working-memory deficits and acute brain injury in the degenerating brain and that these occur by dissociable IL-1-dependent processes. In normal C57BL/6 mice, LPS (100 µg/kg) did not affect working memory but impaired long-term memory consoliodation. However prior hippocampal synaptic loss left mice selectively vulnerable to LPS-induced working memory deficits. Systemically administered IL-1 receptor antagonist (IL-1RA) was protective against, and systemic IL-1β replicated, these working memory deficits. Dexamethasone abolished systemic cytokine synthesis and was protective against working memory deficits, without blocking brain IL-1β synthesis. Direct application of IL-1β to ex vivo hippocampal slices induced non-synaptic depolarisation and irrevesible loss of membrane potential in CA1 neurons from diseased animals and systemic LPS increased apoptosis in the degenerating brain, in an IL-1RI -/- -dependent fashion. The data suggest that LPS induces working memory dysfunction via circulating IL-1β but direct hippocampal action of IL-1β causes neuronal dysfunction and may drive neuronal death. The data suggest that acute systemic inflammation produces both reversible cognitive deficits, resembling delirium, and acute brain injury contributing to long-term cognitive impairment but that these events are mechanistically dissociable. These data have significant implications for management of cognitive dysfunction during acute illness.

Noninvasive Quantum Measurement of Arbitrary Operator Order by Engineered Non-Markovian Detectors

NASA Astrophysics Data System (ADS)

Bülte, Johannes; Bednorz, Adam; Bruder, Christoph; Belzig, Wolfgang

2018-04-01

The development of solid-state quantum technologies requires the understanding of quantum measurements in interacting, nonisolated quantum systems. In general, a permanent coupling of detectors to a quantum system leads to memory effects that have to be taken into account in interpreting the measurement results. We analyze a generic setup of two detectors coupled to a quantum system and derive a compact formula in the weak-measurement limit that interpolates between an instantaneous (text-book type) and almost continuous—detector dynamics-dependent—measurement. A quantum memory effect that we term "system-mediated detector-detector interaction" is crucial to observe noncommuting observables simultaneously. Finally, we propose a mesoscopic double-dot detector setup in which the memory effect is tunable and that can be used to explore the transition to non-Markovian quantum measurements experimentally.

Holding multiple items in short term memory: a neural mechanism.

PubMed

Rolls, Edmund T; Dempere-Marco, Laura; Deco, Gustavo

2013-01-01

Human short term memory has a capacity of several items maintained simultaneously. We show how the number of short term memory representations that an attractor network modeling a cortical local network can simultaneously maintain active is increased by using synaptic facilitation of the type found in the prefrontal cortex. We have been able to maintain 9 short term memories active simultaneously in integrate-and-fire simulations where the proportion of neurons in each population, the sparseness, is 0.1, and have confirmed the stability of such a system with mean field analyses. Without synaptic facilitation the system can maintain many fewer memories active in the same network. The system operates because of the effectively increased synaptic strengths formed by the synaptic facilitation just for those pools to which the cue is applied, and then maintenance of this synaptic facilitation in just those pools when the cue is removed by the continuing neuronal firing in those pools. The findings have implications for understanding how several items can be maintained simultaneously in short term memory, how this may be relevant to the implementation of language in the brain, and suggest new approaches to understanding and treating the decline in short term memory that can occur with normal aging.

Holding Multiple Items in Short Term Memory: A Neural Mechanism

PubMed Central

Rolls, Edmund T.; Dempere-Marco, Laura; Deco, Gustavo

2013-01-01

Human short term memory has a capacity of several items maintained simultaneously. We show how the number of short term memory representations that an attractor network modeling a cortical local network can simultaneously maintain active is increased by using synaptic facilitation of the type found in the prefrontal cortex. We have been able to maintain 9 short term memories active simultaneously in integrate-and-fire simulations where the proportion of neurons in each population, the sparseness, is 0.1, and have confirmed the stability of such a system with mean field analyses. Without synaptic facilitation the system can maintain many fewer memories active in the same network. The system operates because of the effectively increased synaptic strengths formed by the synaptic facilitation just for those pools to which the cue is applied, and then maintenance of this synaptic facilitation in just those pools when the cue is removed by the continuing neuronal firing in those pools. The findings have implications for understanding how several items can be maintained simultaneously in short term memory, how this may be relevant to the implementation of language in the brain, and suggest new approaches to understanding and treating the decline in short term memory that can occur with normal aging. PMID:23613789

Feedforward-Feedback Hybrid Control for Magnetic Shape Memory Alloy Actuators Based on the Krasnosel'skii-Pokrovskii Model

PubMed Central

Zhou, Miaolei; Zhang, Qi; Wang, Jingyuan

2014-01-01

As a new type of smart material, magnetic shape memory alloy has the advantages of a fast response frequency and outstanding strain capability in the field of microdrive and microposition actuators. The hysteresis nonlinearity in magnetic shape memory alloy actuators, however, limits system performance and further application. Here we propose a feedforward-feedback hybrid control method to improve control precision and mitigate the effects of the hysteresis nonlinearity of magnetic shape memory alloy actuators. First, hysteresis nonlinearity compensation for the magnetic shape memory alloy actuator is implemented by establishing a feedforward controller which is an inverse hysteresis model based on Krasnosel'skii-Pokrovskii operator. Secondly, the paper employs the classical Proportion Integration Differentiation feedback control with feedforward control to comprise the hybrid control system, and for further enhancing the adaptive performance of the system and improving the control accuracy, the Radial Basis Function neural network self-tuning Proportion Integration Differentiation feedback control replaces the classical Proportion Integration Differentiation feedback control. Utilizing self-learning ability of the Radial Basis Function neural network obtains Jacobian information of magnetic shape memory alloy actuator for the on-line adjustment of parameters in Proportion Integration Differentiation controller. Finally, simulation results show that the hybrid control method proposed in this paper can greatly improve the control precision of magnetic shape memory alloy actuator and the maximum tracking error is reduced from 1.1% in the open-loop system to 0.43% in the hybrid control system. PMID:24828010

Feedforward-feedback hybrid control for magnetic shape memory alloy actuators based on the Krasnosel'skii-Pokrovskii model.

PubMed

Zhou, Miaolei; Zhang, Qi; Wang, Jingyuan

2014-01-01

As a new type of smart material, magnetic shape memory alloy has the advantages of a fast response frequency and outstanding strain capability in the field of microdrive and microposition actuators. The hysteresis nonlinearity in magnetic shape memory alloy actuators, however, limits system performance and further application. Here we propose a feedforward-feedback hybrid control method to improve control precision and mitigate the effects of the hysteresis nonlinearity of magnetic shape memory alloy actuators. First, hysteresis nonlinearity compensation for the magnetic shape memory alloy actuator is implemented by establishing a feedforward controller which is an inverse hysteresis model based on Krasnosel'skii-Pokrovskii operator. Secondly, the paper employs the classical Proportion Integration Differentiation feedback control with feedforward control to comprise the hybrid control system, and for further enhancing the adaptive performance of the system and improving the control accuracy, the Radial Basis Function neural network self-tuning Proportion Integration Differentiation feedback control replaces the classical Proportion Integration Differentiation feedback control. Utilizing self-learning ability of the Radial Basis Function neural network obtains Jacobian information of magnetic shape memory alloy actuator for the on-line adjustment of parameters in Proportion Integration Differentiation controller. Finally, simulation results show that the hybrid control method proposed in this paper can greatly improve the control precision of magnetic shape memory alloy actuator and the maximum tracking error is reduced from 1.1% in the open-loop system to 0.43% in the hybrid control system.

Operating systems. [of computers

NASA Technical Reports Server (NTRS)

Denning, P. J.; Brown, R. L.

1984-01-01

A counter operating system creates a hierarchy of levels of abstraction, so that at a given level all details concerning lower levels can be ignored. This hierarchical structure separates functions according to their complexity, characteristic time scale, and level of abstraction. The lowest levels include the system's hardware; concepts associated explicitly with the coordination of multiple tasks appear at intermediate levels, which conduct 'primitive processes'. Software semaphore is the mechanism controlling primitive processes that must be synchronized. At higher levels lie, in rising order, the access to the secondary storage devices of a particular machine, a 'virtual memory' scheme for managing the main and secondary memories, communication between processes by way of a mechanism called a 'pipe', access to external input and output devices, and a hierarchy of directories cataloguing the hardware and software objects to which access must be controlled.

Parallel machine architecture for production rule systems

DOEpatents

Allen, Jr., John D.; Butler, Philip L.

1989-01-01

A parallel processing system for production rule programs utilizes a host processor for storing production rule right hand sides (RHS) and a plurality of rule processors for storing left hand sides (LHS). The rule processors operate in parallel in the recognize phase of the system recognize -Act Cycle to match their respective LHS's against a stored list of working memory elements (WME) in order to find a self consistent set of WME's. The list of WME is dynamically varied during the Act phase of the system in which the host executes or fires rule RHS's for those rules for which a self-consistent set has been found by the rule processors. The host transmits instructions for creating or deleting working memory elements as dictated by the rule firings until the rule processors are unable to find any further self-consistent working memory element sets at which time the production rule system is halted.

Effect of virtual memory on efficient solution of two model problems

NASA Technical Reports Server (NTRS)

Lambiotte, J. J., Jr.

1977-01-01

Computers with virtual memory architecture allow programs to be written as if they were small enough to be contained in memory. Two types of problems are investigated to show that this luxury can lead to quite an inefficient performance if the programmer does not interact strongly with the characteristics of the operating system when developing the program. The two problems considered are the simultaneous solutions of a large linear system of equations by Gaussian elimination and a model three-dimensional finite-difference problem. The Control Data STAR-100 computer runs are made to demonstrate the inefficiencies of programming the problems in the manner one would naturally do if the problems were indeed, small enough to be contained in memory. Program redesigns are presented which achieve large improvements in performance through changes in the computational procedure and the data base arrangement.

Performance measurements of the first RAID prototype

NASA Technical Reports Server (NTRS)

Chervenak, Ann L.

1990-01-01

The performance is examined of Redundant Arrays of Inexpensive Disks (RAID) the First, a prototype disk array. A hierarchy of bottlenecks was discovered in the system that limit overall performance. The most serious is the memory system contention on the Sun 4/280 host CPU, which limits array bandwidth to 2.3 MBytes/sec. The array performs more successfully on small random operations, achieving nearly 300 I/Os per second before the Sun 4/280 becomes CPU limited. Other bottlenecks in the system are the VME backplane, bandwidth on the disk controller, and overheads associated with the SCSI protocol. All are examined in detail. The main conclusion is that to achieve the potential bandwidth of arrays, more powerful CPU's alone will not suffice. Just as important are adequate host memory bandwidth and support for high bandwidth on disk controllers. Current disk controllers are more often designed to achieve large numbers of small random operations, rather than high bandwidth. Operating systems also need to change to support high bandwidth from disk arrays. In particular, they should transfer data in larger blocks, and should support asynchronous I/O to improve sequential write performance.

Minimizing the Disruptive Effects of Prospective Memory in Simulated Air Traffic Control

PubMed Central

Loft, Shayne; Smith, Rebekah E.; Remington, Roger

2015-01-01

Prospective memory refers to remembering to perform an intended action in the future. Failures of prospective memory can occur in air traffic control. In two experiments, we examined the utility of external aids for facilitating air traffic management in a simulated air traffic control task with prospective memory requirements. Participants accepted and handed-off aircraft and detected aircraft conflicts. The prospective memory task involved remembering to deviate from a routine operating procedure when accepting target aircraft. External aids that contained details of the prospective memory task appeared and flashed when target aircraft needed acceptance. In Experiment 1, external aids presented either adjacent or non-adjacent to each of the 20 target aircraft presented over the 40min test phase reduced prospective memory error by 11% compared to a condition without external aids. In Experiment 2, only a single target aircraft was presented a significant time (39min–42min) after presentation of the prospective memory instruction, and the external aids reduced prospective memory error by 34%. In both experiments, costs to the efficiency of non-prospective memory air traffic management (non-target aircraft acceptance response time, conflict detection response time) were reduced by non-adjacent aids compared to no aids or adjacent aids. In contrast, in both experiments, the efficiency of the prospective memory air traffic management (target aircraft acceptance response time) was facilitated by adjacent aids compared to non-adjacent aids. Together, these findings have potential implications for the design of automated alerting systems to maximize multi-task performance in work settings where operators monitor and control demanding perceptual displays. PMID:24059825

75 FR 57375 - Establishment of Class E Airspace; Toledo, WA

Federal Register 2010, 2011, 2012, 2013, 2014

2010-09-21

... System (GPS) Standard Instrument Approach Procedure (SIAP) at Ed Carlson Memorial Field-South Lewis County Airport. This will improve the safety and management of Instrument Flight Rules (IFR) operations... is necessary for the safety and management of IFR operations. The FAA has determined this regulation...

Operating systems and network protocols for wireless sensor networks.

PubMed

Dutta, Prabal; Dunkels, Adam

2012-01-13

Sensor network protocols exist to satisfy the communication needs of diverse applications, including data collection, event detection, target tracking and control. Network protocols to enable these services are constrained by the extreme resource scarcity of sensor nodes-including energy, computing, communications and storage-which must be carefully managed and multiplexed by the operating system. These challenges have led to new protocols and operating systems that are efficient in their energy consumption, careful in their computational needs and miserly in their memory footprints, all while discovering neighbours, forming networks, delivering data and correcting failures.

Performing an allreduce operation using shared memory

DOEpatents

Archer, Charles J [Rochester, MN; Dozsa, Gabor [Ardsley, NY; Ratterman, Joseph D [Rochester, MN; Smith, Brian E [Rochester, MN

2012-04-17

Methods, apparatus, and products are disclosed for performing an allreduce operation using shared memory that include: receiving, by at least one of a plurality of processing cores on a compute node, an instruction to perform an allreduce operation; establishing, by the core that received the instruction, a job status object for specifying a plurality of shared memory allreduce work units, the plurality of shared memory allreduce work units together performing the allreduce operation on the compute node; determining, by an available core on the compute node, a next shared memory allreduce work unit in the job status object; and performing, by that available core on the compute node, that next shared memory allreduce work unit.

Performing an allreduce operation using shared memory

DOEpatents

Archer, Charles J; Dozsa, Gabor; Ratterman, Joseph D; Smith, Brian E

2014-06-10

Methods, apparatus, and products are disclosed for performing an allreduce operation using shared memory that include: receiving, by at least one of a plurality of processing cores on a compute node, an instruction to perform an allreduce operation; establishing, by the core that received the instruction, a job status object for specifying a plurality of shared memory allreduce work units, the plurality of shared memory allreduce work units together performing the allreduce operation on the compute node; determining, by an available core on the compute node, a next shared memory allreduce work unit in the job status object; and performing, by that available core on the compute node, that next shared memory allreduce work unit.

Airport Noise Control Strategies,

DTIC Science & Technology

1986-05-01

MONICA SMX SANTA MARIA PUBLIC, SANTA MARIA SNA JOHN WAYNE/ORANGE COUNTY, SANTA ANA SOL LAN CARLOS, SAN CARLOS CTS SONOMA COUNTY , SANTA ROSA SZP SANTA...RUNWAY SYSTEM TOTAL OPERATIONS 174827 CONTACT. NA STS SONOMA COUNTY SANTA ROSA, CA PREFERENTIAL RUNWAY SYSTEM INFORMAL FLIGHT OPERATION RESTRICTION...STS SONOMA COUNTY SANTA ROSA. CA SUN FRIEDMAN MEMORIAL HAILEY, ID SWF STEWART NEWBURGH, NY TED TETERBORO TETERBORO, NJ TLH TALLAHASSEE MUNICIPAL

Air Support Control Officer Individual Position Training Simulation

DTIC Science & Technology

2017-06-01

Analysis design development implementation evaluation ASCO Air support control officer ASLT Air support liaison team ASNO Air support net operator...Instructional system design LSTM Long-short term memory MACCS Marine Air Command and Control System MAGTF Marine Air Ground Task Force MASS Marine Air...information to designated MACCS agencies. ASCOs play an important part in facilitating the safe and successful conduct of air operations in DASC- controlled

MIROS: A Hybrid Real-Time Energy-Efficient Operating System for the Resource-Constrained Wireless Sensor Nodes

PubMed Central

Liu, Xing; Hou, Kun Mean; de Vaulx, Christophe; Shi, Hongling; Gholami, Khalid El

2014-01-01

Operating system (OS) technology is significant for the proliferation of the wireless sensor network (WSN). With an outstanding OS; the constrained WSN resources (processor; memory and energy) can be utilized efficiently. Moreover; the user application development can be served soundly. In this article; a new hybrid; real-time; memory-efficient; energy-efficient; user-friendly and fault-tolerant WSN OS MIROS is designed and implemented. MIROS implements the hybrid scheduler and the dynamic memory allocator. Real-time scheduling can thus be achieved with low memory consumption. In addition; it implements a mid-layer software EMIDE (Efficient Mid-layer Software for User-Friendly Application Development Environment) to decouple the WSN application from the low-level system. The application programming process can consequently be simplified and the application reprogramming performance improved. Moreover; it combines both the software and the multi-core hardware techniques to conserve the energy resources; improve the node reliability; as well as achieve a new debugging method. To evaluate the performance of MIROS; it is compared with the other WSN OSes (TinyOS; Contiki; SOS; openWSN and mantisOS) from different OS concerns. The final evaluation results prove that MIROS is suitable to be used even on the tight resource-constrained WSN nodes. It can support the real-time WSN applications. Furthermore; it is energy efficient; user friendly and fault tolerant. PMID:25248069

MIROS: a hybrid real-time energy-efficient operating system for the resource-constrained wireless sensor nodes.

PubMed

Liu, Xing; Hou, Kun Mean; de Vaulx, Christophe; Shi, Hongling; El Gholami, Khalid

2014-09-22

Operating system (OS) technology is significant for the proliferation of the wireless sensor network (WSN). With an outstanding OS; the constrained WSN resources (processor; memory and energy) can be utilized efficiently. Moreover; the user application development can be served soundly. In this article; a new hybrid; real-time; memory-efficient; energy-efficient; user-friendly and fault-tolerant WSN OS MIROS is designed and implemented. MIROS implements the hybrid scheduler and the dynamic memory allocator. Real-time scheduling can thus be achieved with low memory consumption. In addition; it implements a mid-layer software EMIDE (Efficient Mid-layer Software for User-Friendly Application Development Environment) to decouple the WSN application from the low-level system. The application programming process can consequently be simplified and the application reprogramming performance improved. Moreover; it combines both the software and the multi-core hardware techniques to conserve the energy resources; improve the node reliability; as well as achieve a new debugging method. To evaluate the performance of MIROS; it is compared with the other WSN OSes (TinyOS; Contiki; SOS; openWSN and mantisOS) from different OS concerns. The final evaluation results prove that MIROS is suitable to be used even on the tight resource-constrained WSN nodes. It can support the real-time WSN applications. Furthermore; it is energy efficient; user friendly and fault tolerant.

System Safety Management Lessons Learned

DTIC Science & Technology

1989-05-01

DISCLAIMER This report was prepared as an account of work sponsored by an agency of the United States Government . Neither the United States Government nor... Government or any agency thereof, or Battelle Memorial Institute. The views and opinions of authors expressed herein do not necessarily state or reflect...those of the United States Government or any agency thereof. PACIFIC NORTHWEST LABORATORY operated by BATTELLE MEMORIAL INSTITUTE for the UNITED

FPGA Flash Memory High Speed Data Acquisition

NASA Technical Reports Server (NTRS)

Gonzalez, April

2013-01-01

The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

A light writable microfluidic "flash memory": optically addressed actuator array with latched operation for microfluidic applications.

PubMed

Hua, Zhishan; Pal, Rohit; Srivannavit, Onnop; Burns, Mark A; Gulari, Erdogan

2008-03-01

This paper presents a novel optically addressed microactuator array (microfluidic "flash memory") with latched operation. Analogous to the address-data bus mediated memory address protocol in electronics, the microactuator array consists of individual phase-change based actuators addressed by localized heating through focused light patterns (address bus), which can be provided by a modified projector or high power laser pointer. A common pressure manifold (data bus) for the entire array is used to generate large deflections of the phase change actuators in the molten phase. The use of phase change material as the working media enables latched operation of the actuator array. After the initial light "writing" during which the phase is temporarily changed to molten, the actuated status is self-maintained by the solid phase of the actuator without power and pressure inputs. The microfluidic flash memory can be re-configured by a new light illumination pattern and common pressure signal. The proposed approach can achieve actuation of arbitrary units in a large-scale array without the need for complex external equipment such as solenoid valves and electrical modules, which leads to significantly simplified system implementation and compact system size. The proposed work therefore provides a flexible, energy-efficient, and low cost multiplexing solution for microfluidic applications based on physical displacements. As an example, the use of the latched microactuator array as "normally closed" or "normally open" microvalves is demonstrated. The phase-change wax is fully encapsulated and thus immune from contamination issues in fluidic environments.

Kinetic energy classification and smoothing for compact B-spline basis sets in quantum Monte Carlo

DOE PAGES

Krogel, Jaron T.; Reboredo, Fernando A.

2018-01-25

Quantum Monte Carlo calculations of defect properties of transition metal oxides have become feasible in recent years due to increases in computing power. As the system size has grown, availability of on-node memory has become a limiting factor. Saving memory while minimizing computational cost is now a priority. The main growth in memory demand stems from the B-spline representation of the single particle orbitals, especially for heavier elements such as transition metals where semi-core states are present. Despite the associated memory costs, splines are computationally efficient. In this paper, we explore alternatives to reduce the memory usage of splined orbitalsmore » without significantly affecting numerical fidelity or computational efficiency. We make use of the kinetic energy operator to both classify and smooth the occupied set of orbitals prior to splining. By using a partitioning scheme based on the per-orbital kinetic energy distributions, we show that memory savings of about 50% is possible for select transition metal oxide systems. Finally, for production supercells of practical interest, our scheme incurs a performance penalty of less than 5%.« less

Kinetic energy classification and smoothing for compact B-spline basis sets in quantum Monte Carlo

DOE Office of Scientific and Technical Information (OSTI.GOV)

Krogel, Jaron T.; Reboredo, Fernando A.

Quantum Monte Carlo calculations of defect properties of transition metal oxides have become feasible in recent years due to increases in computing power. As the system size has grown, availability of on-node memory has become a limiting factor. Saving memory while minimizing computational cost is now a priority. The main growth in memory demand stems from the B-spline representation of the single particle orbitals, especially for heavier elements such as transition metals where semi-core states are present. Despite the associated memory costs, splines are computationally efficient. In this paper, we explore alternatives to reduce the memory usage of splined orbitalsmore » without significantly affecting numerical fidelity or computational efficiency. We make use of the kinetic energy operator to both classify and smooth the occupied set of orbitals prior to splining. By using a partitioning scheme based on the per-orbital kinetic energy distributions, we show that memory savings of about 50% is possible for select transition metal oxide systems. Finally, for production supercells of practical interest, our scheme incurs a performance penalty of less than 5%.« less

Kinetic energy classification and smoothing for compact B-spline basis sets in quantum Monte Carlo

NASA Astrophysics Data System (ADS)

Krogel, Jaron T.; Reboredo, Fernando A.

2018-01-01

Quantum Monte Carlo calculations of defect properties of transition metal oxides have become feasible in recent years due to increases in computing power. As the system size has grown, availability of on-node memory has become a limiting factor. Saving memory while minimizing computational cost is now a priority. The main growth in memory demand stems from the B-spline representation of the single particle orbitals, especially for heavier elements such as transition metals where semi-core states are present. Despite the associated memory costs, splines are computationally efficient. In this work, we explore alternatives to reduce the memory usage of splined orbitals without significantly affecting numerical fidelity or computational efficiency. We make use of the kinetic energy operator to both classify and smooth the occupied set of orbitals prior to splining. By using a partitioning scheme based on the per-orbital kinetic energy distributions, we show that memory savings of about 50% is possible for select transition metal oxide systems. For production supercells of practical interest, our scheme incurs a performance penalty of less than 5%.

Network Centric Operations NCO Case Study. The British Approach to Low-Intensity Operations: Part I

DTIC Science & Technology

2007-02-12

Army’s institutional memory of jungle warfare (during WW2 ) had dissipated by 1948. Nonetheless, individuals within the Army who had experienced such...with a specially stabilised TV camera mounting. It also fitted infrared surveillance systems to its Beaver spotter planes, which helped detect

Silent store detection and recording in memory storage

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bose, Pradip; Cher, Chen-Yong; Nair, Ravi

An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memorymore » location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.« less

Co-design of application software and NAND flash memory in solid-state drive for relational database storage system

NASA Astrophysics Data System (ADS)

Miyaji, Kousuke; Sun, Chao; Soga, Ayumi; Takeuchi, Ken

2014-01-01

A relational database management system (RDBMS) is designed based on NAND flash solid-state drive (SSD) for storage. By vertically integrating the storage engine (SE) and the flash translation layer (FTL), system performance is maximized and the internal SSD overhead is minimized. The proposed RDBMS SE utilizes physical information about the NAND flash memory which is supplied from the FTL. The query operation is also optimized for SSD. By these treatments, page-copy-less garbage collection is achieved and data fragmentation in the NAND flash memory is suppressed. As a result, RDBMS performance increases by 3.8 times, power consumption of SSD decreases by 46% and SSD life time is increased by 61%. The effectiveness of the proposed scheme increases with larger erase block sizes, which matches the future scaling trend of three-dimensional (3D-) NAND flash memories. The preferable row data size of the proposed scheme is below 500 byte for 16 kbyte page size.

Aggregation server for grid-integrated vehicles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kempton, Willett

2015-05-26

Methods, systems, and apparatus for aggregating electric power flow between an electric grid and electric vehicles are disclosed. An apparatus for aggregating power flow may include a memory and a processor coupled to the memory to receive electric vehicle equipment (EVE) attributes from a plurality of EVEs, aggregate EVE attributes, predict total available capacity based on the EVE attributes, and dispatch at least a portion of the total available capacity to the grid. Power flow may be aggregated by receiving EVE operational parameters from each EVE, aggregating the received EVE operational parameters, predicting total available capacity based on the aggregatedmore » EVE operational parameters, and dispatching at least a portion of the total available capacity to the grid.« less

A space release/deployment system actuated by shape memory wires

NASA Astrophysics Data System (ADS)

Fragnito, Marino; Vetrella and, Sergio

2002-11-01

In this paper, the design of an innovative hold down/release and deployment device actuated by shape memory wires, to be used for the first time for the S MA RT microsatellite solar wings is shown. The release and deployment mechanisms are actuated by a Shape Memory wire (Nitinol), which allows a complete symmetrical and synchronous release, in a very short time, of the four wings in pairs. The hold down kinematic mechanism is preloaded to avoid vibration nonlinearities and unwanted deployment at launch. The deployment mechanism is a simple pulley system. The stiffness of the deployed panel-hinge system needs to be dimensioned in order to meet the on-orbit requirement for attitude control. One-way roller clutches are used to keep the panel at the desired angle during the mission. An ad hoc software has been developed to simulate both the release and deployment operations, coupling the SMA wire behavior with the system mechanics.

Data General Corporation Advanced Operating System/Virtual Storage (AOS/ VS). Revision 7.60

DTIC Science & Technology

1989-02-22

control list for each directory and data file. An access control list includes the users who can and cannot access files as well as the access...and any required data, it can -5- February 22, 1989 Final Evaluation Report Data General AOS/VS SYSTEM OVERVIEW operate asynchronously and in parallel...memory. The IOC can perform the data transfer without further interventiin from the CPU. The I/O channels interface with the processor or system

LANDSAT-D flight segment operations manual. Appendix B: OBC software operations

NASA Technical Reports Server (NTRS)

Talipsky, R.

1981-01-01

The LANDSAT 4 satellite contains two NASA standard spacecraft computers and 65,536 words of memory. Onboard computer software is divided into flight executive and applications processors. Both applications processors and the flight executive use one or more of 67 system tables to obtain variables, constants, and software flags. Output from the software for monitoring operation is via 49 OBC telemetry reports subcommutated in the spacecraft telemetry. Information is provided about the flight software as it is used to control the various spacecraft operations and interpret operational OBC telemetry. Processor function descriptions, processor operation, software constraints, processor system tables, processor telemetry, and processor flow charts are presented.

CMOS imager for pointing and tracking applications

NASA Technical Reports Server (NTRS)

Sun, Chao (Inventor); Pain, Bedabrata (Inventor); Yang, Guang (Inventor); Heynssens, Julie B. (Inventor)

2006-01-01

Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

Implementation of Parallel Dynamic Simulation on Shared-Memory vs. Distributed-Memory Environments

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Shuangshuang; Chen, Yousu; Wu, Di

2015-12-09

Power system dynamic simulation computes the system response to a sequence of large disturbance, such as sudden changes in generation or load, or a network short circuit followed by protective branch switching operation. It consists of a large set of differential and algebraic equations, which is computational intensive and challenging to solve using single-processor based dynamic simulation solution. High-performance computing (HPC) based parallel computing is a very promising technology to speed up the computation and facilitate the simulation process. This paper presents two different parallel implementations of power grid dynamic simulation using Open Multi-processing (OpenMP) on shared-memory platform, and Messagemore » Passing Interface (MPI) on distributed-memory clusters, respectively. The difference of the parallel simulation algorithms and architectures of the two HPC technologies are illustrated, and their performances for running parallel dynamic simulation are compared and demonstrated.« less

Computationally Efficient Modeling and Simulation of Large Scale Systems

NASA Technical Reports Server (NTRS)

Jain, Jitesh (Inventor); Koh, Cheng-Kok (Inventor); Balakrishnan, Vankataramanan (Inventor); Cauley, Stephen F (Inventor); Li, Hong (Inventor)

2014-01-01

A system for simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof, including a processor, and a memory, the processor configured to perform obtaining a matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure, the element values for each matrix including inductance L and inverse capacitance P, obtaining an adjacency matrix A associated with the interconnect structure, storing the matrices X, Y, and A in the memory, and performing numerical integration to solve first and second equations.

Stochastic dynamics of time correlation in complex systems with discrete time

NASA Astrophysics Data System (ADS)

Yulmetyev, Renat; Hänggi, Peter; Gafarov, Fail

2000-11-01

In this paper we present the concept of description of random processes in complex systems with discrete time. It involves the description of kinetics of discrete processes by means of the chain of finite-difference non-Markov equations for time correlation functions (TCFs). We have introduced the dynamic (time dependent) information Shannon entropy Si(t) where i=0,1,2,3,..., as an information measure of stochastic dynamics of time correlation (i=0) and time memory (i=1,2,3,...). The set of functions Si(t) constitute the quantitative measure of time correlation disorder (i=0) and time memory disorder (i=1,2,3,...) in complex system. The theory developed started from the careful analysis of time correlation involving dynamics of vectors set of various chaotic states. We examine two stochastic processes involving the creation and annihilation of time correlation (or time memory) in details. We carry out the analysis of vectors' dynamics employing finite-difference equations for random variables and the evolution operator describing their natural motion. The existence of TCF results in the construction of the set of projection operators by the usage of scalar product operation. Harnessing the infinite set of orthogonal dynamic random variables on a basis of Gram-Shmidt orthogonalization procedure tends to creation of infinite chain of finite-difference non-Markov kinetic equations for discrete TCFs and memory functions (MFs). The solution of the equations above thereof brings to the recurrence relations between the TCF and MF of senior and junior orders. This offers new opportunities for detecting the frequency spectra of power of entropy function Si(t) for time correlation (i=0) and time memory (i=1,2,3,...). The results obtained offer considerable scope for attack on stochastic dynamics of discrete random processes in a complex systems. Application of this technique on the analysis of stochastic dynamics of RR intervals from human ECG's shows convincing evidence for a non-Markovian phenomemena associated with a peculiarities in short- and long-range scaling. This method may be of use in distinguishing healthy from pathologic data sets based in differences in these non-Markovian properties.

Operating Systems for Wireless Sensor Networks: A Survey

PubMed Central

Farooq, Muhammad Omer; Kunz, Thomas

2011-01-01

This paper presents a survey on the current state-of-the-art in Wireless Sensor Network (WSN) Operating Systems (OSs). In recent years, WSNs have received tremendous attention in the research community, with applications in battlefields, industrial process monitoring, home automation, and environmental monitoring, to name but a few. A WSN is a highly dynamic network because nodes die due to severe environmental conditions and battery power depletion. Furthermore, a WSN is composed of miniaturized motes equipped with scarce resources e.g., limited memory and computational abilities. WSNs invariably operate in an unattended mode and in many scenarios it is impossible to replace sensor motes after deployment, therefore a fundamental objective is to optimize the sensor motes’ life time. These characteristics of WSNs impose additional challenges on OS design for WSN, and consequently, OS design for WSN deviates from traditional OS design. The purpose of this survey is to highlight major concerns pertaining to OS design in WSNs and to point out strengths and weaknesses of contemporary OSs for WSNs, keeping in mind the requirements of emerging WSN applications. The state-of-the-art in operating systems for WSNs has been examined in terms of the OS Architecture, Programming Model, Scheduling, Memory Management and Protection, Communication Protocols, Resource Sharing, Support for Real-Time Applications, and additional features. These features are surveyed for both real-time and non-real-time WSN operating systems. PMID:22163934

Operating systems for wireless sensor networks: a survey.

PubMed

Farooq, Muhammad Omer; Kunz, Thomas

2011-01-01

This paper presents a survey on the current state-of-the-art in Wireless Sensor Network (WSN) Operating Systems (OSs). In recent years, WSNs have received tremendous attention in the research community, with applications in battlefields, industrial process monitoring, home automation, and environmental monitoring, to name but a few. A WSN is a highly dynamic network because nodes die due to severe environmental conditions and battery power depletion. Furthermore, a WSN is composed of miniaturized motes equipped with scarce resources e.g., limited memory and computational abilities. WSNs invariably operate in an unattended mode and in many scenarios it is impossible to replace sensor motes after deployment, therefore a fundamental objective is to optimize the sensor motes' life time. These characteristics of WSNs impose additional challenges on OS design for WSN, and consequently, OS design for WSN deviates from traditional OS design. The purpose of this survey is to highlight major concerns pertaining to OS design in WSNs and to point out strengths and weaknesses of contemporary OSs for WSNs, keeping in mind the requirements of emerging WSN applications. The state-of-the-art in operating systems for WSNs has been examined in terms of the OS Architecture, Programming Model, Scheduling, Memory Management and Protection, Communication Protocols, Resource Sharing, Support for Real-Time Applications, and additional features. These features are surveyed for both real-time and non-real-time WSN operating systems.

ICE System: Interruptible control expert system. M.S. Thesis

NASA Technical Reports Server (NTRS)

Vezina, James M.

1990-01-01

The Interruptible Control Expert (ICE) System is based on an architecture designed to provide a strong foundation for real-time production rule expert systems. Three principles are adopted to guide the development of ICE. A practical delivery platform must be provided, no specialized hardware can be used to solve deficiencies in the software design. Knowledge of the environment and the rule-base is exploited to improve the performance of a delivered system. The third principle of ICE is to respond to the most critical event, at the expense of the more trivial tasks. Minimal time is spent on classifying the potential importance of environmental events with the majority of the time used for finding the responses. A feature of the system, derived from all three principles, is the lack of working memory. By using a priori information, a fixed amount of memory can be specified for the hardware platform. The absence of working memory removes the dangers of garbage collection during the continuous operation of the controller.

Control Transfer in Operating System Kernels

DTIC Science & Technology

1994-05-13

microkernel system that runs less code in the kernel address space. To realize the performance benefit of allocating stacks in unmapped kseg0 memory, the...review how I modified the Mach 3.0 kernel to use continuations. Because of Mach’s message-passing microkernel structure, interprocess communication was...critical control transfer paths, deeply- nested call chains are undesirable in any case because of the function call overhead. 4.1.3 Microkernel Operating

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bose, Pradip; Cher, Chen-Yong; Nair, Ravi

An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memorymore » location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.« less

Programmable DMA controller

NASA Technical Reports Server (NTRS)

Hendry, David F. (Inventor)

1993-01-01

In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of the I/O devices to the memory, a direct memory access (DMA) controller regulating access of each of the I/O devices to the bus, including a priority register storing priorities of bus access requests from the I/O devices, an interrupt register storing bus access requests of the I/O devices, a resolver for selecting one of the I/O devices to have access to the bus, a pointer register storing addresses of locations in the memory for communication with the one I/O device via the bus, a sequence register storing an address of a location in the memory containing a channel program instruction which is to be executed next, an ALU for incrementing and decrementing addresses stored in the pointer register, computing the next address to be stored in the sequence register, computing an initial contents of each of the register. The memory contains a sequence of channel program instructions defining a set up operation wherein the contents of each of the registers in the channel register is initialized in accordance with the initial contents computed by the ALU and an access operation wherein data is transferred on the bus between a location in the memory whose address is currently stored in the pointer register and the one I/O device enabled by the resolver.

Human Cognition and Information Display in C3I System Tasks.

DTIC Science & Technology

1988-12-01

goes without saying that rule-based tasks are the easiest to automate, but for reasons discussed earlier, they still merit our attention . Moreover...selective attention task. Since selective attention must operate after memory retrieval, it is only when different responses are elicited that the...stimuli that is processed by impairing the memory traces of signals that originally attract less attention . Although the research reviewed above gives

Extending Mondrian Memory Protection

DTIC Science & Technology

2010-11-01

a kernel semaphore is locked or unlocked. In addition, we extended the system call interface to receive notifications about user-land locking...operations (such as calls to the mutex and semaphore code provided by the C library). By patching the dynamically loadable GLibC5, we are able to test... semaphores , and spinlocks. RTO-MP-IST-091 10- 9 Extending Mondrian Memory Protection to loading extension plugins. This prevents any untrusted code

CMOS Camera Array With Onboard Memory

NASA Technical Reports Server (NTRS)

Gat, Nahum

2009-01-01

A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

Coherence time of over a second in a telecom-compatible quantum memory storage material

NASA Astrophysics Data System (ADS)

Rančić, Miloš; Hedges, Morgan P.; Ahlefeldt, Rose L.; Sellars, Matthew J.

2018-01-01

Quantum memories for light will be essential elements in future long-range quantum communication networks. These memories operate by reversibly mapping the quantum state of light onto the quantum transitions of a material system. For networks, the quantum coherence times of these transitions must be long compared to the network transmission times, approximately 100 ms for a global communication network. Due to a lack of a suitable storage material, a quantum memory that operates in the 1,550 nm optical fibre communication band with a storage time greater than 1 μs has not been demonstrated. Here we describe the spin dynamics of 167Er3+: Y2SiO5 in a high magnetic field and demonstrate that this material has the characteristics for a practical quantum memory in the 1,550 nm communication band. We observe a hyperfine coherence time of 1.3 s. We also demonstrate efficient spin pumping of the entire ensemble into a single hyperfine state, a requirement for broadband spin-wave storage. With an absorption of 70 dB cm-1 at 1,538 nm and Λ transitions enabling spin-wave storage, this material is the first candidate identified for an efficient, broadband quantum memory at telecommunication wavelengths.

Solitonic Josephson-based meminductive systems

DOE PAGES

Guarcello, Claudio; Solinas, Paolo; Di Ventra, Massimiliano; ...

2017-04-24

Memristors, memcapacitors, and meminductors represent an innovative generation of circuit elements whose properties depend on the state and history of the system. The hysteretic behavior of one of their constituent variables, is their distinctive fingerprint. This feature endows them with the ability to store and process information on the same physical location, a property that is expected to benefit many applications ranging from unconventional computing to adaptive electronics to robotics. Therefore, it is important to find appropriate memory elements that combine a wide range of memory states, long memory retention times, and protection against unavoidable noise. Although several physical systemsmore » belong to the general class of memelements, few of them combine these important physical features in a single component. Here in this paper, we demonstrate theoretically a superconducting memory based on solitonic long Josephson junctions. Moreover, since solitons are at the core of its operation, this system provides an intrinsic topological protection against external perturbations. We show that the Josephson critical current behaves hysteretically as an external magnetic field is properly swept. Accordingly, long Josephson junctions can be used as multi-state memories, with a controllable number of available states, and in other emerging areas such as memcomputing, i.e., computing directly in/by the memory.« less

Solitonic Josephson-based meminductive systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Guarcello, Claudio; Solinas, Paolo; Di Ventra, Massimiliano

Memristors, memcapacitors, and meminductors represent an innovative generation of circuit elements whose properties depend on the state and history of the system. The hysteretic behavior of one of their constituent variables, is their distinctive fingerprint. This feature endows them with the ability to store and process information on the same physical location, a property that is expected to benefit many applications ranging from unconventional computing to adaptive electronics to robotics. Therefore, it is important to find appropriate memory elements that combine a wide range of memory states, long memory retention times, and protection against unavoidable noise. Although several physical systemsmore » belong to the general class of memelements, few of them combine these important physical features in a single component. Here in this paper, we demonstrate theoretically a superconducting memory based on solitonic long Josephson junctions. Moreover, since solitons are at the core of its operation, this system provides an intrinsic topological protection against external perturbations. We show that the Josephson critical current behaves hysteretically as an external magnetic field is properly swept. Accordingly, long Josephson junctions can be used as multi-state memories, with a controllable number of available states, and in other emerging areas such as memcomputing, i.e., computing directly in/by the memory.« less

Spaceborne Processor Array

NASA Technical Reports Server (NTRS)

Chow, Edward T.; Schatzel, Donald V.; Whitaker, William D.; Sterling, Thomas

2008-01-01

A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

Health Hazard Evaluation Report HETA 84-145-1604, Porter Memorial Hospital, Valparaiso, Indiana. [Anesthetic gases and ethylene oxide

DOE Office of Scientific and Technical Information (OSTI.GOV)

Behrens, V.; Burroughs, G.E.; Crandall, M.

1985-07-01

Environmental and breathing-zone samples were analyzed for nitrous oxide, halogenated anesthetic gases, and ethylene-oxide at Porter Memorial Hospital, Valparaiso, Indiana in April, 1984. The evaluation was requested by the Indiana Occupational Safety and Health Administration to investigate the exposure of operating room personnel to anesthetic gases and central supply employees to ethylene-oxide. The authors conclude that some of the operating room personnel are overexposed to halogenated anesthetic gases and nitrous-oxide. Recommendations include performing better maintenance of the anesthesia equipment, improving the work practices of the anesthesiologists, and periodically checking the ethylene-oxide sterilizer system for leaks.

Combating Memory Corruption Attacks On Scada Devices

NASA Astrophysics Data System (ADS)

Bellettini, Carlo; Rrushi, Julian

Memory corruption attacks on SCADA devices can cause significant disruptions to control systems and the industrial processes they operate. However, despite the presence of numerous memory corruption vulnerabilities, few, if any, techniques have been proposed for addressing the vulnerabilities or for combating memory corruption attacks. This paper describes a technique for defending against memory corruption attacks by enforcing logical boundaries between potentially hostile data and safe data in protected processes. The technique encrypts all input data using random keys; the encrypted data is stored in main memory and is decrypted according to the principle of least privilege just before it is processed by the CPU. The defensive technique affects the precision with which attackers can corrupt control data and pure data, protecting against code injection and arc injection attacks, and alleviating problems posed by the incomparability of mitigation techniques. An experimental evaluation involving the popular Modbus protocol demonstrates the feasibility and efficiency of the defensive technique.

The Effects of Working Memory on Brain-Computer Interface Performance

PubMed Central

Sprague, Samantha A.; McBee, Matthew; Sellers, Eric W.

2015-01-01

Objective The purpose of the present study is to evaluate the relationship between working memory and BCI performance. Methods Participants took part in two separate sessions. The first session consisted of three computerized tasks. The LSWM was used to measure working memory, the TPVT was used to measure general intelligence, and the DCCS was used to measure executive function, specifically cognitive flexibility. The second session consisted of a P300-based BCI copy-spelling task. Results The results indicate that both working memory and general intelligence are significant predictors of BCI performance. Conclusions This suggests that working memory training could be used to improve performance on a BCI task. Significance Working memory training may help to reduce a portion of the individual differences that exist in BCI performance allowing for a wider range of users to successfully operate the BCI system as well as increase the BCI performance of current users. PMID:26620822

Long-term associative learning predicts verbal short-term memory performance.

PubMed

Jones, Gary; Macken, Bill

2018-02-01

Studies using tests such as digit span and nonword repetition have implicated short-term memory across a range of developmental domains. Such tests ostensibly assess specialized processes for the short-term manipulation and maintenance of information that are often argued to enable long-term learning. However, there is considerable evidence for an influence of long-term linguistic learning on performance in short-term memory tasks that brings into question the role of a specialized short-term memory system separate from long-term knowledge. Using natural language corpora, we show experimentally and computationally that performance on three widely used measures of short-term memory (digit span, nonword repetition, and sentence recall) can be predicted from simple associative learning operating on the linguistic environment to which a typical child may have been exposed. The findings support the broad view that short-term verbal memory performance reflects the application of long-term language knowledge to the experimental setting.

Sleep-dependent memory triage: Evolving generalization through selective processing

PubMed Central

Stickgold, Robert; Walker, Matthew P.

2018-01-01

The brain does not retain all the information it encodes in a day. Much is forgotten, and of those memories retained, their subsequent “evolution” can follow any of a number of pathways. Emerging data makes clear that sleep is a compelling candidate for performing many of these operations. But how does the sleeping brain know which information to preserve and which to forget? What should sleep do with that information it chooses to keep? For information that is retained, sleep can integrate it into existing memory networks, look for common patterns and distill overarching rules, or simply stabilize and strengthen the memory exactly as it was learned. We suggest such “memory triage” lies at the heart of a sleep-dependent memory processing system that selects new information, in a discriminatory manner, and assimilates it into the brain’s vast armamentarium of evolving knowledge, helping guide each organism through its own, unique life. PMID:23354387

Simple and Efficient Single Photon Filter for a Rb-based Quantum Memory

NASA Astrophysics Data System (ADS)

Stack, Daniel; Li, Xiao; Quraishi, Qudsia

2015-05-01

Distribution of entangled quantum states over significant distances is important to the development of future quantum technologies such as long-distance cryptography, networks of atomic clocks, distributed quantum computing, etc. Long-lived quantum memories and single photons are building blocks for systems capable of realizing such applications. The ability to store and retrieve quantum information while filtering unwanted light signals is critical to the operation of quantum memories based on neutral-atom ensembles. We report on an efficient frequency filter which uses a glass cell filled with 85Rb vapor to attenuate noise photons by an order of magnitude with little loss to the single photons associated with the operation of our cold 87Rb quantum memory. An Ar buffer gas is required to differentiate between signal and noise photons or similar statement. Our simple, passive filter requires no optical pumping or external frequency references and provides an additional 18 dB attenuation of our pump laser for every 1 dB loss of the single photon signal. We observe improved non-classical correlations and our data shows that the addition of a frequency filter increases the non-classical correlations and readout efficiency of our quantum memory by ~ 35%.

Feature conjunctions and auditory sensory memory.

PubMed

Sussman, E; Gomes, H; Nousak, J M; Ritter, W; Vaughan, H G

1998-05-18

This study sought to obtain additional evidence that transient auditory memory stores information about conjunctions of features on an automatic basis. The mismatch negativity of event-related potentials was employed because its operations are based on information that is stored in transient auditory memory. The mismatch negativity was found to be elicited by a tone that differed from standard tones in a combination of its perceived location and frequency. The result lends further support to the hypothesis that the system upon which the mismatch negativity relies processes stimuli in an holistic manner. Copyright 1998 Elsevier Science B.V.

Applications considerations in the system design of highly concurrent multiprocessors

NASA Technical Reports Server (NTRS)

Lundstrom, Stephen F.

1987-01-01

A flow model processor approach to parallel processing is described, using very-high-performance individual processors, high-speed circuit switched interconnection networks, and a high-speed synchronization capability to minimize the effect of the inherently serial portions of applications on performance. Design studies related to the determination of the number of processors, the memory organization, and the structure of the networks used to interconnect the processor and memory resources are discussed. Simulations indicate that applications centered on the large shared data memory should be able to sustain over 500 million floating point operations per second.

Embedded real-time operating system micro kernel design

NASA Astrophysics Data System (ADS)

Cheng, Xiao-hui; Li, Ming-qiang; Wang, Xin-zheng

2005-12-01

Embedded systems usually require a real-time character. Base on an 8051 microcontroller, an embedded real-time operating system micro kernel is proposed consisting of six parts, including a critical section process, task scheduling, interruption handle, semaphore and message mailbox communication, clock managent and memory managent. Distributed CPU and other resources are among tasks rationally according to the importance and urgency. The design proposed here provides the position, definition, function and principle of micro kernel. The kernel runs on the platform of an ATMEL AT89C51 microcontroller. Simulation results prove that the designed micro kernel is stable and reliable and has quick response while operating in an application system.

40 CFR 1033.112 - Emission diagnostics for SCR systems.

Code of Federal Regulations, 2010 CFR

2010-07-01

... 40 Protection of Environment 32 2010-07-01 2010-07-01 false Emission diagnostics for SCR systems. 1033.112 Section 1033.112 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) AIR... computer memory all incidents of engine operation with inadequate reductant injection or reductant quality...

Operating System For Numerically Controlled Milling Machine

NASA Technical Reports Server (NTRS)

Ray, R. B.

1992-01-01

OPMILL program is operating system for Kearney and Trecker milling machine providing fast easy way to program manufacture of machine parts with IBM-compatible personal computer. Gives machinist "equation plotter" feature, which plots equations that define movements and converts equations to milling-machine-controlling program moving cutter along defined path. System includes tool-manager software handling up to 25 tools and automatically adjusts to account for each tool. Developed on IBM PS/2 computer running DOS 3.3 with 1 MB of random-access memory.

Development of a Low-Latency, High Data Rate, Differential GPS Relative Positioning System for UAV Formation Flight Control

DTIC Science & Technology

2006-09-01

spiral development cycle involved transporting the software processes from a Windows XP / MATLAB environment to a Linux / C++ environment. This...tested on. Additionally, in the case of the GUMSTIX PC boards, the LINUX operating system is burned into the read-only memory. Lastly, both PC-104 and...both the real-time environment and the post-processed en - vironment. When the system operates in real-time mode, an output file is generated which

Systematic construction and control of stereo nerve vision network in intelligent manufacturing

NASA Astrophysics Data System (ADS)

Liu, Hua; Wang, Helong; Guo, Chunjie; Ding, Quanxin; Zhou, Liwei

2017-10-01

A system method of constructing stereo vision by using neural network is proposed, and the operation and control mechanism in actual operation are proposed. This method makes effective use of the neural network in learning and memory function, by after training with samples. Moreover, the neural network can learn the nonlinear relationship in the stereoscopic vision system and the internal and external orientation elements. These considerations are Worthy of attention, which includes limited constraints, the scientific of critical group, the operating speed and the operability in technical aspects. The results support our theoretical forecast.

Automatic generation of reports at the TELECOM SCC

NASA Astrophysics Data System (ADS)

Beltan, Thierry; Jalbaud, Myriam; Fronton, Jean Francois

In-orbit satellite follow-up produces a certain amount of reports on a regular basis (daily, weekly, quarterly, annually). Most of these documents use the information of former issues with the increments of the last period of time. They are made up of text, tables, graphs or pictures. The system presented here is the SGMT (Systeme de Gestion de la Memoire Technique), which means Technical Memory Mangement System. It provides the system operators with tools to generate the greatest part of these reports, as automatically as possible. It gives an easy access to the reports and the large amount of available memory enables the user to consult data on the complete lifetime of a satellite family.

PLZT block data composers operated in differential phase mode. [lanthanum-modified lead zirconate titanate ceramic device for digital holographic memory

NASA Technical Reports Server (NTRS)

Drake, M. D.; Klingler, D. E.

1973-01-01

The use of PLZT ceramics with the 7/65/35 composition in block data composer (BDC) input devices for holographic memory systems has previously been described for operation in the strain biased, scattering, and edge effect modes. A new and promising mode of BDC operation is the differential phase mode in which each element of a matrix array BDC acts as a phase modulator. The phase modulation results from a phase difference in the optical path length between the electrically poled and depoled states of the PLZT. It is shown that a PLZT BDC can be used as a matrix-type phase modulator to record and process digital data by the differential phase mode in a holographic recording/processing system with readout contrast ratios of between 10:1 and 15:1. The differential phase mode has the advantages that strain bias is not required and that the thickness and strain variations in the PLZT are cancelled out.

Spermidine Suppresses Age-Associated Memory Impairment by Preventing Adverse Increase of Presynaptic Active Zone Size and Release

PubMed Central

Gupta, Varun K.; Pech, Ulrike; Fulterer, Andreas; Ender, Anatoli; Mauermann, Stephan F.; Andlauer, Till F. M.; Beuschel, Christine; Thriene, Kerstin; Quentin, Christine; Schwärzel, Martin; Mielke, Thorsten; Madeo, Frank; Dengjel, Joern; Fiala, André; Sigrist, Stephan J.

2016-01-01

Memories are assumed to be formed by sets of synapses changing their structural or functional performance. The efficacy of forming new memories declines with advancing age, but the synaptic changes underlying age-induced memory impairment remain poorly understood. Recently, we found spermidine feeding to specifically suppress age-dependent impairments in forming olfactory memories, providing a mean to search for synaptic changes involved in age-dependent memory impairment. Here, we show that a specific synaptic compartment, the presynaptic active zone (AZ), increases the size of its ultrastructural elaboration and releases significantly more synaptic vesicles with advancing age. These age-induced AZ changes, however, were fully suppressed by spermidine feeding. A genetically enforced enlargement of AZ scaffolds (four gene-copies of BRP) impaired memory formation in young animals. Thus, in the Drosophila nervous system, aging AZs seem to steer towards the upper limit of their operational range, limiting synaptic plasticity and contributing to impairment of memory formation. Spermidine feeding suppresses age-dependent memory impairment by counteracting these age-dependent changes directly at the synapse. PMID:27684064

VOP memory management in MPEG-4

NASA Astrophysics Data System (ADS)

Vaithianathan, Karthikeyan; Panchanathan, Sethuraman

2001-03-01

MPEG-4 is a multimedia standard that requires Video Object Planes (VOPs). Generation of VOPs for any kind of video sequence is still a challenging problem that largely remains unsolved. Nevertheless, if this problem is treated by imposing certain constraints, solutions for specific application domains can be found. MPEG-4 applications in mobile devices is one such domain where the opposite goals namely low power and high throughput are required to be met. Efficient memory management plays a major role in reducing the power consumption. Specifically, efficient memory management for VOPs is difficult because the lifetimes of these objects vary and these life times may be overlapping. Varying life times of the objects requires dynamic memory management where memory fragmentation is a key problem that needs to be addressed. In general, memory management systems address this problem by following a combination of strategy, policy and mechanism. For MPEG4 based mobile devices that lack instruction processors, a hardware based memory management solution is necessary. In MPEG4 based mobile devices that have a RISC processor, using a Real time operating system (RTOS) for this memory management task is not expected to be efficient because the strategies and policies used by the ROTS is often tuned for handling memory segments of smaller sizes compared to object sizes. Hence, a memory management scheme specifically tuned for VOPs is important. In this paper, different strategies, policies and mechanisms for memory management are considered and an efficient combination is proposed for the case of VOP memory management along with a hardware architecture, which can handle the proposed combination.

The storage system of PCM based on random access file system

NASA Astrophysics Data System (ADS)

Han, Wenbing; Chen, Xiaogang; Zhou, Mi; Li, Shunfen; Li, Gezi; Song, Zhitang

2016-10-01

Emerging memory technologies such as Phase change memory (PCM) tend to offer fast, random access to persistent storage with better scalability. It's a hot topic of academic and industrial research to establish PCM in storage hierarchy to narrow the performance gap. However, the existing file systems do not perform well with the emerging PCM storage, which access storage medium via a slow, block-based interface. In this paper, we propose a novel file system, RAFS, to bring about good performance of PCM, which is built in the embedded platform. We attach PCM chips to the memory bus and build RAFS on the physical address space. In the proposed file system, we simplify traditional system architecture to eliminate block-related operations and layers. Furthermore, we adopt memory mapping and bypassed page cache to reduce copy overhead between the process address space and storage device. XIP mechanisms are also supported in RAFS. To the best of our knowledge, we are among the first to implement file system on real PCM chips. We have analyzed and evaluated its performance with IOZONE benchmark tools. Our experimental results show that the RAFS on PCM outperforms Ext4fs on SDRAM with small record lengths. Based on DRAM, RAFS is significantly faster than Ext4fs by 18% to 250%.

Reactive Goal Decomposition Hierarchies for On-Board Autonomy

NASA Astrophysics Data System (ADS)

Hartmann, L.

2002-01-01

As our experience grows, space missions and systems are expected to address ever more complex and demanding requirements with fewer resources (e.g., mass, power, budget). One approach to accommodating these higher expectations is to increase the level of autonomy to improve the capabilities and robustness of on- board systems and to simplify operations. The goal decomposition hierarchies described here provide a simple but powerful form of goal-directed behavior that is relatively easy to implement for space systems. A goal corresponds to a state or condition that an operator of the space system would like to bring about. In the system described here goals are decomposed into simpler subgoals until the subgoals are simple enough to execute directly. For each goal there is an activation condition and a set of decompositions. The decompositions correspond to different ways of achieving the higher level goal. Each decomposition contains a gating condition and a set of subgoals to be "executed" sequentially or in parallel. The gating conditions are evaluated in order and for the first one that is true, the corresponding decomposition is executed in order to achieve the higher level goal. The activation condition specifies global conditions (i.e., for all decompositions of the goal) that need to hold in order for the goal to be achieved. In real-time, parameters and state information are passed between goals and subgoals in the decomposition; a termination indication (success, failure, degree) is passed up when a decomposition finishes executing. The lowest level decompositions include servo control loops and finite state machines for generating control signals and sequencing i/o. Semaphores and shared memory are used to synchronize and coordinate decompositions that execute in parallel. The goal decomposition hierarchy is reactive in that the generated behavior is sensitive to the real-time state of the system and the environment. That is, the system is able to react to state and environment and in general can terminate the execution of a decomposition and attempt a new decomposition at any level in the hierarchy. This goal decomposition system is suitable for workstation, microprocessor and fpga implementation and thus is able to support the full range of prototyping activities, from mission design in the laboratory to development of the fpga firmware for the flight system. This approach is based on previous artificial intelligence work including (1) Brooks' subsumption architecture for robot control, (2) Firby's Reactive Action Package System (RAPS) for mediating between high level automated planning and low level execution and (3) hierarchical task networks for automated planning. Reactive goal decomposition hierarchies can be used for a wide variety of on-board autonomy applications including automating low level operation sequences (such as scheduling prerequisite operations, e.g., heaters, warm-up periods, monitoring power constraints), coordinating multiple spacecraft as in formation flying and constellations, robot manipulator operations, rendez-vous, docking, servicing, assembly, on-orbit maintenance, planetary rover operations, solar system and interstellar probes, intelligent science data gathering and disaster early warning. Goal decomposition hierarchies can support high level fault tolerance. Given models of on-board resources and goals to accomplish, the decomposition hierarchy could allocate resources to goals taking into account existing faults and in real-time reallocating resources as new faults arise. Resources to be modeled include memory (e.g., ROM, FPGA configuration memory, processor memory, payload instrument memory), processors, on-board and interspacecraft network nodes and links, sensors, actuators (e.g., attitude determination and control, guidance and navigation) and payload instruments. A goal decomposition hierarchy could be defined to map mission goals and tasks to available on-board resources. As faults occur and are detected the resource allocation is modified to avoid using the faulty resource. Goal decomposition hierarchies can implement variable autonomy (in which the operator chooses to command the system at a high or low level, mixed initiative planning (in which the system is able to interact with the operator, e.g, to request operator intervention when a working envelope is exceeded) and distributed control (in which, for example, multiple spacecraft cooperate to accomplish a task without a fixed master). The full paper will describe in greater detail how goal decompositions work, how they can be implemented, techniques for implementing a candidate application and the current state of the fpga implementation.

Solar heating and hot water system installed at Charlotte Memorial Hospital, Charlotte, North Carolina

NASA Technical Reports Server (NTRS)

1981-01-01

Detailed information regarding the design and installation of a heating and hot water system in a commercial application is given. This information includes descriptions of system and building, design philosophy, control logic operation modes, design and installation drawing and a brief description of problems encountered and their solutions.

JANUS: A Compilation System for Balancing Parallelism and Performance in OpenVX

NASA Astrophysics Data System (ADS)

Omidian, Hossein; Lemieux, Guy G. F.

2018-04-01

Embedded systems typically do not have enough on-chip memory for entire an image buffer. Programming systems like OpenCV operate on entire image frames at each step, making them use excessive memory bandwidth and power. In contrast, the paradigm used by OpenVX is much more efficient; it uses image tiling, and the compilation system is allowed to analyze and optimize the operation sequence, specified as a compute graph, before doing any pixel processing. In this work, we are building a compilation system for OpenVX that can analyze and optimize the compute graph to take advantage of parallel resources in many-core systems or FPGAs. Using a database of prewritten OpenVX kernels, it automatically adjusts the image tile size as well as using kernel duplication and coalescing to meet a defined area (resource) target, or to meet a specified throughput target. This allows a single compute graph to target implementations with a wide range of performance needs or capabilities, e.g. from handheld to datacenter, that use minimal resources and power to reach the performance target.

Response of the Ubiquitin-Proteasome System to Memory Retrieval After Extended-Access Cocaine or Saline Self-Administration.

PubMed

Werner, Craig T; Milovanovic, Mike; Christian, Daniel T; Loweth, Jessica A; Wolf, Marina E

2015-12-01

The ubiquitin-proteasome system (UPS) has been implicated in the retrieval-induced destabilization of cocaine- and fear-related memories in Pavlovian paradigms. However, nothing is known about its role in memory retrieval after self-administration of cocaine, an operant paradigm, or how the length of withdrawal from cocaine may influence retrieval mechanisms. Here, we examined UPS activity after an extended-access cocaine self-administration regimen that leads to withdrawal-dependent incubation of cue-induced cocaine craving. Controls self-administered saline. In initial experiments, memory retrieval was elicited via a cue-induced seeking/retrieval test on withdrawal day (WD) 50-60, when craving has incubated. We found that retrieval of cocaine- and saline-associated memories produced similar increases in polyubiquitinated proteins in the nucleus accumbens (NAc), compared with rats that did not undergo a seeking/retrieval test. Measures of proteasome catalytic activity confirmed similar activation of the UPS after retrieval of saline and cocaine memories. However, in a subsequent experiment in which testing was conducted on WD1, proteasome activity in the NAc was greater after retrieval of cocaine memory than saline memory. Analysis of other brain regions confirmed that effects of cocaine memory retrieval on proteasome activity, relative to saline memory retrieval, depend on withdrawal time. These results, combined with prior studies, suggest that the relationship between UPS activity and memory retrieval depends on training paradigm, brain region, and time elapsed between training and retrieval. The observation that mechanisms underlying cocaine memory retrieval change depending on the age of the memory has implications for development of memory destabilization therapies for cue-induced relapse in cocaine addicts.

Simultaneous Cognitive Operations in Working Memory After Dual-Task Practice

ERIC Educational Resources Information Center

Oberauer, Klaus; Kliegl, Reinhold

2004-01-01

The authors tested the hypothesis that with adequate practice, people can execute 2 cognitive operations in working memory simultaneously. In Experiment 1, 6 students practiced updating 2 items in working memory through 2 sequences of operations (1 numerical, 1 spatial). In different blocks, imperative stimuli for the 2 sequences of operations…

Bipolar and Monopolar Lithium-Ion Battery Technology at Yardney

NASA Technical Reports Server (NTRS)

Russell, P.; Flynn, J.; Reddy, T.

1996-01-01

Lithium-ion battery systems offer several advantages: intrinsically safe; long cycle life; environmentally friendly; high energy density; wide operating temperature range; good discharge rate capability; low self-discharge; and no memory effect.

Accelerating functional verification of an integrated circuit

DOEpatents

Deindl, Michael; Ruedinger, Jeffrey Joseph; Zoellin, Christian G.

2015-10-27

Illustrative embodiments include a method, system, and computer program product for accelerating functional verification in simulation testing of an integrated circuit (IC). Using a processor and a memory, a serial operation is replaced with a direct register access operation, wherein the serial operation is configured to perform bit shifting operation using a register in a simulation of the IC. The serial operation is blocked from manipulating the register in the simulation of the IC. Using the register in the simulation of the IC, the direct register access operation is performed in place of the serial operation.

Review on open source operating systems for internet of things

NASA Astrophysics Data System (ADS)

Wang, Zhengmin; Li, Wei; Dong, Huiliang

2017-08-01

Internet of Things (IoT) is an environment in which everywhere and every device became smart in a smart world. Internet of Things is growing vastly; it is an integrated system of uniquely identifiable communicating devices which exchange information in a connected network to provide extensive services. IoT devices have very limited memory, computational power, and power supply. Traditional operating systems (OS) have no way to meet the needs of IoT systems. In this paper, we thus analyze the challenges of IoT OS and survey applicable open source OSs.

Method and apparatus for single-stepping coherence events in a multiprocessor system under software control

DOEpatents

Blumrich, Matthias A.; Salapura, Valentina

2010-11-02

An apparatus and method are disclosed for single-stepping coherence events in a multiprocessor system under software control in order to monitor the behavior of a memory coherence mechanism. Single-stepping coherence events in a multiprocessor system is made possible by adding one or more step registers. By accessing these step registers, one or more coherence requests are processed by the multiprocessor system. The step registers determine if the snoop unit will operate by proceeding in a normal execution mode, or operate in a single-step mode.

Operation of a quantum dot in the finite-state machine mode: Single-electron dynamic memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Klymenko, M. V.; Klein, M.; Levine, R. D.

2016-07-14

A single electron dynamic memory is designed based on the non-equilibrium dynamics of charge states in electrostatically defined metallic quantum dots. Using the orthodox theory for computing the transfer rates and a master equation, we model the dynamical response of devices consisting of a charge sensor coupled to either a single and or a double quantum dot subjected to a pulsed gate voltage. We show that transition rates between charge states in metallic quantum dots are characterized by an asymmetry that can be controlled by the gate voltage. This effect is more pronounced when the switching between charge states correspondsmore » to a Markovian process involving electron transport through a chain of several quantum dots. By simulating the dynamics of electron transport we demonstrate that the quantum box operates as a finite-state machine that can be addressed by choosing suitable shapes and switching rates of the gate pulses. We further show that writing times in the ns range and retention memory times six orders of magnitude longer, in the ms range, can be achieved on the double quantum dot system using experimentally feasible parameters, thereby demonstrating that the device can operate as a dynamic single electron memory.« less

Airborne Tactical Data Network Gateways: Evaluating EPLRS’ Ability to Integrate With Wireless Meshed Networks

DTIC Science & Technology

2005-09-01

Computer Memory Card International Association PHY Physical PLI Position Location Information PLRS Position Location Reporting System PoP Point of...it is widely acknowledged that the JTRS program will not be providing any sustentative operational capability prior to FY’09. This reality has...Figure 5, and a man-packed antenna (AS- 3448/PSQ-4). Back-up (cryptographic key) memory is maintained by a traditional 9v 24

The effects of working memory on brain-computer interface performance.

PubMed

Sprague, Samantha A; McBee, Matthew T; Sellers, Eric W

2016-02-01

The purpose of the present study is to evaluate the relationship between working memory and BCI performance. Participants took part in two separate sessions. The first session consisted of three computerized tasks. The List Sorting Working Memory Task was used to measure working memory, the Picture Vocabulary Test was used to measure general intelligence, and the Dimensional Change Card Sort Test was used to measure executive function, specifically cognitive flexibility. The second session consisted of a P300-based BCI copy-spelling task. The results indicate that both working memory and general intelligence are significant predictors of BCI performance. This suggests that working memory training could be used to improve performance on a BCI task. Working memory training may help to reduce a portion of the individual differences that exist in BCI performance allowing for a wider range of users to successfully operate the BCI system as well as increase the BCI performance of current users. Copyright © 2015 International Federation of Clinical Neurophysiology. Published by Elsevier Ireland Ltd. All rights reserved.

A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters

NASA Astrophysics Data System (ADS)

Cristoloveanu, S.; Lee, K. H.; Parihar, M. S.; El Dirani, H.; Lacord, J.; Martinie, S.; Le Royer, C.; Barbe, J.-Ch.; Mescot, X.; Fonteneau, P.; Galy, Ph.; Gamiz, F.; Navarro, C.; Cheng, B.; Duan, M.; Adamu-Lema, F.; Asenov, A.; Taur, Y.; Xu, Y.; Kim, Y.-T.; Wan, J.; Bawedin, M.

2018-05-01

The band-modulation and sharp-switching mechanisms in Z2-FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments and simulations. This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10 nm thick SOI films. It offers low leakage current, high current margin, long retention, low operating voltage especially for programming, and high speed. The Z2-FET is suitable for embedded memory applications.

Method and apparatus of parallel computing with simultaneously operating stream prefetching and list prefetching engines

DOEpatents

Boyle, Peter A.; Christ, Norman H.; Gara, Alan; Mawhinney, Robert D.; Ohmacht, Martin; Sugavanam, Krishnan

2012-12-11

A prefetch system improves a performance of a parallel computing system. The parallel computing system includes a plurality of computing nodes. A computing node includes at least one processor and at least one memory device. The prefetch system includes at least one stream prefetch engine and at least one list prefetch engine. The prefetch system operates those engines simultaneously. After the at least one processor issues a command, the prefetch system passes the command to a stream prefetch engine and a list prefetch engine. The prefetch system operates the stream prefetch engine and the list prefetch engine to prefetch data to be needed in subsequent clock cycles in the processor in response to the passed command.

Large-scale hydropower system optimization using dynamic programming and object-oriented programming: the case of the Northeast China Power Grid.

PubMed

Li, Ji-Qing; Zhang, Yu-Shan; Ji, Chang-Ming; Wang, Ai-Jing; Lund, Jay R

2013-01-01

This paper examines long-term optimal operation using dynamic programming for a large hydropower system of 10 reservoirs in Northeast China. Besides considering flow and hydraulic head, the optimization explicitly includes time-varying electricity market prices to maximize benefit. Two techniques are used to reduce the 'curse of dimensionality' of dynamic programming with many reservoirs. Discrete differential dynamic programming (DDDP) reduces the search space and computer memory needed. Object-oriented programming (OOP) and the ability to dynamically allocate and release memory with the C++ language greatly reduces the cumulative effect of computer memory for solving multi-dimensional dynamic programming models. The case study shows that the model can reduce the 'curse of dimensionality' and achieve satisfactory results.

Nanogap-Engineerable Electromechanical System for Ultralow Power Memory.

PubMed

Zhang, Jian; Deng, Ya; Hu, Xiao; Nshimiyimana, Jean Pierre; Liu, Siyu; Chi, Xiannian; Wu, Pei; Dong, Fengliang; Chen, Peipei; Chu, Weiguo; Zhou, Haiqing; Sun, Lianfeng

2018-02-01

Nanogap engineering of low-dimensional nanomaterials has received considerable interest in a variety of fields, ranging from molecular electronics to memories. Creating nanogaps at a certain position is of vital importance for the repeatable fabrication of the devices. Here, a rational design of nonvolatile memories based on sub-5 nm nanogaped single-walled carbon nanotubes (SWNTs) via the electromechanical motion is reported. The nanogaps are readily realized by electroburning in a partially suspended SWNT device with nanoscale region. The SWNT memory devices are applicable for both metallic and semiconducting SWNTs, resolving the challenge of separation of semiconducting SWNTs from metallic ones. Meanwhile, the memory devices exhibit excellent performance: ultralow writing energy (4.1 × 10 -19 J bit -1 ), ON/OFF ratio of 10 5 , stable switching ON operations, and over 30 h retention time in ambient conditions.

Nanogap‐Engineerable Electromechanical System for Ultralow Power Memory

PubMed Central

Zhang, Jian; Deng, Ya; Hu, Xiao; Nshimiyimana, Jean Pierre; Liu, Siyu; Chi, Xiannian; Wu, Pei; Dong, Fengliang; Chen, Peipei

2017-01-01

Abstract Nanogap engineering of low‐dimensional nanomaterials has received considerable interest in a variety of fields, ranging from molecular electronics to memories. Creating nanogaps at a certain position is of vital importance for the repeatable fabrication of the devices. Here, a rational design of nonvolatile memories based on sub‐5 nm nanogaped single‐walled carbon nanotubes (SWNTs) via the electromechanical motion is reported. The nanogaps are readily realized by electroburning in a partially suspended SWNT device with nanoscale region. The SWNT memory devices are applicable for both metallic and semiconducting SWNTs, resolving the challenge of separation of semiconducting SWNTs from metallic ones. Meanwhile, the memory devices exhibit excellent performance: ultralow writing energy (4.1 × 10−19 J bit−1), ON/OFF ratio of 105, stable switching ON operations, and over 30 h retention time in ambient conditions. PMID:29619307

Design structure for in-system redundant array repair in integrated circuits

DOEpatents

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

2008-11-25

A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Ultralow-fatigue shape memory alloy films

NASA Astrophysics Data System (ADS)

Chluba, Christoph; Ge, Wenwei; Lima de Miranda, Rodrigo; Strobel, Julian; Kienle, Lorenz; Quandt, Eckhard; Wuttig, Manfred

2015-05-01

Functional shape memory alloys need to operate reversibly and repeatedly. Quantitative measures of reversibility include the relative volume change of the participating phases and compatibility matrices for twinning. But no similar argument is known for repeatability. This is especially crucial for many future applications, such as artificial heart valves or elastocaloric cooling, in which more than 10 million transformation cycles will be required. We report on the discovery of an ultralow-fatigue shape memory alloy film system based on TiNiCu that allows at least 10 million transformation cycles. We found that these films contain Ti2Cu precipitates embedded in the base alloy that serve as sentinels to ensure complete and reproducible transformation in the course of each memory cycle.

Light-erasable embedded charge-trapping memory based on MoS2 for system-on-panel applications

NASA Astrophysics Data System (ADS)

He, Long-Fei; Zhu, Hao; Xu, Jing; Liu, Hao; Nie, Xin-Ran; Chen, Lin; Sun, Qing-Qing; Xia, Yang; Wei Zhang, David

2017-11-01

The continuous scaling and challenges in device integrations in modern portable electronic products have aroused many scientific interests, and a great deal of effort has been made in seeking solutions towards a more microminiaturized package assembled with smaller and more powerful components. In this study, an embedded light-erasable charge-trapping memory with a high-k dielectric stack (Al2O3/HfO2/Al2O3) and an atomically thin MoS2 channel has been fabricated and fully characterized. The memory exhibits a sufficient memory window, fast programming and erasing (P/E) speed, and high On/Off current ratio up to 107. Less than 25% memory window degradation is observed after projected 10-year retention, and the device functions perfectly after 8000 P/E operation cycles. Furthermore, the programmed device can be fully erased by incident light without electrical assistance. Such excellent memory performance originates from the intrinsic properties of two-dimensional (2D) MoS2 and the engineered back-gate dielectric stack. Our integration of 2D semiconductors in the infrastructure of light-erasable charge-trapping memory is very promising for future system-on-panel applications like storage of metadata and flexible imaging arrays.

Posttraining Epinephrine Reverses Memory Deficits Produced by Traumatic Brain Injury in Rats

PubMed Central

Lorón-Sánchez, Alejandro; Torras-Garcia, Meritxell; Coll-Andreu, Margalida; Costa-Miserachs, David; Portell-Cortés, Isabel

2016-01-01

The aim of this research is to evaluate whether posttraining systemic epinephrine is able to improve object recognition memory in rats with memory deficits produced by traumatic brain injury. Forty-nine two-month-old naïve male Wistar rats were submitted to surgical procedures to induce traumatic brain injury (TBI) or were sham-operated. Rats were trained in an object recognition task and, immediately after training, received an intraperitoneal injection of distilled water (Sham-Veh and TBI-Veh group) or 0.01 mg/kg epinephrine (TBI-Epi group) or no injection (TBI-0 and Sham-0 groups). Retention was tested 3 h and 24 h after acquisition. The results showed that brain injury produced severe memory deficits and that posttraining administration of epinephrine was able to reverse them. Systemic administration of distilled water also had an enhancing effect, but of a lower magnitude. These data indicate that posttraining epinephrine and, to a lesser extent, vehicle injection reduce memory deficits associated with TBI, probably through induction of a low-to-moderate emotional arousal. PMID:27127685

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications

NASA Astrophysics Data System (ADS)

Liu, Chunsen; Yan, Xiao; Song, Xiongfei; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-05-01

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

Neural Network Model For Fast Learning And Retrieval

NASA Astrophysics Data System (ADS)

Arsenault, Henri H.; Macukow, Bohdan

1989-05-01

An approach to learning in a multilayer neural network is presented. The proposed network learns by creating interconnections between the input layer and the intermediate layer. In one of the new storage prescriptions proposed, interconnections are excitatory (positive) only and the weights depend on the stored patterns. In the intermediate layer each mother cell is responsible for one stored pattern. Mutually interconnected neurons in the intermediate layer perform a winner-take-all operation, taking into account correlations between stored vectors. The performance of networks using this interconnection prescription is compared with two previously proposed schemes, one using inhibitory connections at the output and one using all-or-nothing interconnections. The network can be used as a content-addressable memory or as a symbolic substitution system that yields an arbitrarily defined output for any input. The training of a model to perform Boolean logical operations is also described. Computer simulations using the network as an autoassociative content-addressable memory show the model to be efficient. Content-addressable associative memories and neural logic modules can be combined to perform logic operations on highly corrupted data.

Computational Models of Human Performance: Validation of Memory and Procedural Representation in Advanced Air/Ground Simulation

NASA Technical Reports Server (NTRS)

Corker, Kevin M.; Labacqz, J. Victor (Technical Monitor)

1997-01-01

The Man-Machine Interaction Design and Analysis System (MIDAS) under joint U.S. Army and NASA cooperative is intended to assist designers of complex human/automation systems in successfully incorporating human performance capabilities and limitations into decision and action support systems. MIDAS is a computational representation of multiple human operators, selected perceptual, cognitive, and physical functions of those operators, and the physical/functional representation of the equipment with which they operate. MIDAS has been used as an integrated predictive framework for the investigation of human/machine systems, particularly in situations with high demands on the operators. We have extended the human performance models to include representation of both human operators and intelligent aiding systems in flight management, and air traffic service. The focus of this development is to predict human performance in response to aiding system developed to identify aircraft conflict and to assist in the shared authority for resolution. The demands of this application requires representation of many intelligent agents sharing world-models, coordinating action/intention, and cooperative scheduling of goals and action in an somewhat unpredictable world of operations. In recent applications to airborne systems development, MIDAS has demonstrated an ability to predict flight crew decision-making and procedural behavior when interacting with automated flight management systems and Air Traffic Control. In this paper, we describe two enhancements to MIDAS. The first involves the addition of working memory in the form of an articulatory buffer for verbal communication protocols and a visuo-spatial buffer for communications via digital datalink. The second enhancement is a representation of multiple operators working as a team. This enhanced model was used to predict the performance of human flight crews and their level of compliance with commercial aviation communication procedures. We show how the data produced by MIDAS compares with flight crew performance data from full mission simulations. Finally, we discuss the use of these features to study communication issues connected with aircraft-based separation assurance.

Man-Machine Interaction Design and Analysis System (MIDAS): Memory Representation and Procedural Implications for Airborne Communication Modalities

NASA Technical Reports Server (NTRS)

Corker, Kevin M.; Pisanich, Gregory M.; Lebacqz, Victor (Technical Monitor)

1996-01-01

The Man-Machine Interaction Design and Analysis System (MIDAS) has been under development for the past ten years through a joint US Army and NASA cooperative agreement. MIDAS represents multiple human operators and selected perceptual, cognitive, and physical functions of those operators as they interact with simulated systems. MIDAS has been used as an integrated predictive framework for the investigation of human/machine systems, particularly in situations with high demands on the operators. Specific examples include: nuclear power plant crew simulation, military helicopter flight crew response, and police force emergency dispatch. In recent applications to airborne systems development, MIDAS has demonstrated an ability to predict flight crew decision-making and procedural behavior when interacting with automated flight management systems and Air Traffic Control. In this paper we describe two enhancements to MIDAS. The first involves the addition of working memory in the form of an articulatory buffer for verbal communication protocols and a visuo-spatial buffer for communications via digital datalink. The second enhancement is a representation of multiple operators working as a team. This enhanced model was used to predict the performance of human flight crews and their level of compliance with commercial aviation communication procedures. We show how the data produced by MIDAS compares with flight crew performance data from full mission simulations. Finally, we discuss the use of these features to study communications issues connected with aircraft-based separation assurance.

A malicious pattern detection engine for embedded security systems in the Internet of Things.

PubMed

Oh, Doohwan; Kim, Deokho; Ro, Won Woo

2014-12-16

With the emergence of the Internet of Things (IoT), a large number of physical objects in daily life have been aggressively connected to the Internet. As the number of objects connected to networks increases, the security systems face a critical challenge due to the global connectivity and accessibility of the IoT. However, it is difficult to adapt traditional security systems to the objects in the IoT, because of their limited computing power and memory size. In light of this, we present a lightweight security system that uses a novel malicious pattern-matching engine. We limit the memory usage of the proposed system in order to make it work on resource-constrained devices. To mitigate performance degradation due to limitations of computation power and memory, we propose two novel techniques, auxiliary shifting and early decision. Through both techniques, we can efficiently reduce the number of matching operations on resource-constrained systems. Experiments and performance analyses show that our proposed system achieves a maximum speedup of 2.14 with an IoT object and provides scalable performance for a large number of patterns.

Digital Image Display Control System, DIDCS. [for astronomical analysis

NASA Technical Reports Server (NTRS)

Fischel, D.; Klinglesmith, D. A., III

1979-01-01

DIDCS is an interactive image display and manipulation system that is used for a variety of astronomical image reduction and analysis operations. The hardware system consists of a PDP 11/40 main frame with 32K of 16-bit core memory; 96K of 16-bit MOS memory; two 9 track 800 BPI tape drives; eight 2.5 million byte RKO5 type disk packs, three user terminals, and a COMTAL 8000-S display system which has sufficient memory to store and display three 512 x 512 x 8 bit images along with an overlay plane and function table for each image, a pseudo color table and the capability for displaying true color. The software system is based around the language FORTH, which will permit an open ended dictionary of user level words for image analyses and display. A description of the hardware and software systems will be presented along with examples of the types of astronomical research that are being performed. Also a short discussion of the commonality and exchange of this type of image analysis system will be given.

A Program Structure for Event-Based Speech Synthesis by Rules within a Flexible Segmental Framework.

ERIC Educational Resources Information Center

Hill, David R.

1978-01-01

A program structure based on recently developed techniques for operating system simulation has the required flexibility for use as a speech synthesis algorithm research framework. This program makes synthesis possible with less rigid time and frequency-component structure than simpler schemes. It also meets real-time operation and memory-size…

Dynamic Forest: An Efficient Index Structure for NAND Flash Memory

NASA Astrophysics Data System (ADS)

Yang, Chul-Woong; Yong Lee, Ki; Ho Kim, Myoung; Lee, Yoon-Joon

In this paper, we present an efficient index structure for NAND flash memory, called the Dynamic Forest (D-Forest). Since write operations incur high overhead on NAND flash memory, D-Forest is designed to minimize write operations for index updates. The experimental results show that D-Forest significantly reduces write operations compared to the conventional B+-tree.

Conceptual design and feasibility evaluation model of a 10 to the 8th power bit oligatomic mass memory. Volume 3: Operation manual

NASA Technical Reports Server (NTRS)

Horst, R. L.; Nordstrom, M. J.

1972-01-01

An operation manual is presented for the oligatomic mass memory feasibility model. It includes a brief description of the memory and exerciser units, a description of the controls and their functions, the operating procedures, the test points and adjustments, and the circuit diagram.

Salience of working-memory maintenance and manipulation deficits in schizophrenia

PubMed Central

Hill, S. K.; Griffin, G. B.; Miura, T. Kazuto; Herbener, E. S.; Sweeney, J. A.

2011-01-01

Background Encoding and maintenance of information in working memory, followed by internal manipulation of that information for planning adaptive behavior, are two key components of working-memory systems. Both processes have been reported to be impaired in schizophrenia, but few studies have directly compared the relative severity of these abnormalities, or the degree to which manipulation deficits might be secondary to alterations in maintenance processes. Method Clinically stable schizophrenia patients (n=25) and a demographically similar healthy comparison group (n=24) were administered a verbal span task with three levels of working-memory load. Maintenance was assessed using sequential position questions. Manipulation processes were assessed by requiring comparison of the relative sequential position of test items, which entailed simultaneous serial search strategies regarding item order. Results Both groups showed reduced accuracy and increased reaction time for manipulation compared with maintenance processing. There were significant patient impairments across working-memory loads. There was no differential deficit in manipulation processing, and effect sizes of relative deficit in the patient group were higher for maintenance than manipulation processing. Conclusions The strong correlation for maintenance and manipulation deficits suggest that impairments in the ability to internally manipulate information stored in working-memory systems are not greater than alterations in the encoding and maintaining of information in working memory and that disturbances in maintenance processing may contribute to deficits in higher-order working-memory operations. PMID:20214839

Modification of existing human motor memories is enabled by primary cortical processing during memory reactivation.

PubMed

Censor, Nitzan; Dimyan, Michael A; Cohen, Leonardo G

2010-09-14

One of the most challenging tasks of the brain is to constantly update the internal neural representations of existing memories. Animal studies have used invasive methods such as direct microfusion of protein inhibitors to designated brain areas, in order to study the neural mechanisms underlying modification of already existing memories after their reactivation during recall [1-4]. Because such interventions are not possible in humans, it is not known how these neural processes operate in the human brain. In a series of experiments we show here that when an existing human motor memory is reactivated during recall, modification of the memory is blocked by virtual lesion [5] of the related primary cortical human brain area. The virtual lesion was induced by noninvasive repetitive transcranial magnetic stimulation guided by a frameless stereotactic brain navigation system and each subject's brain image. The results demonstrate that primary cortical processing in the human brain interacting with pre-existing reactivated memory traces is critical for successful modification of the existing related memory. Modulation of reactivated memories by noninvasive cortical stimulation may have important implications for human memory research and have far-reaching clinical applications. Copyright © 2010 Elsevier Ltd. All rights reserved.

Revising psychoanalytic interpretations of the past. An examination of declarative and non-declarative memory processes.

PubMed

Davis, J T

2001-06-01

The author reviews a contemporary cognitive psychology perspective on memory that views memory as being composed of multiple separate systems. Most researchers draw a fundamental distinction between declarative/explicit and non-declarative/implicit forms of memory. Declarative memory is responsible for the conscious recollection of facts and events--what is typically meant by the everyday and the common psychoanalytic use of the word 'memory'. Non-declarative forms of memory, in contrast, are specialised processes that influence experience and behaviour without representing the past in terms of any consciously accessible content. They operate outside of an individual's awareness, but are not repressed or otherwise dynamically unconscious. Using this theoretical framework, the question of how childhood relationship experiences are carried forward from the past to influence the present is examined. It is argued that incorporating a conceptualisation of non-declarative memory processing into psychoanalytic theory is essential. Non-declarative memory processes are capable of forming complex and sophisticated representations of the interpersonal world. These non-declarative memory processes exert a major impact on interpersonal experience and behaviour that needs to be analysed on its own terms and not mistakenly viewed as a form of resistance.

UNIX-based operating systems robustness evaluation

NASA Technical Reports Server (NTRS)

Chang, Yu-Ming

1996-01-01

Robust operating systems are required for reliable computing. Techniques for robustness evaluation of operating systems not only enhance the understanding of the reliability of computer systems, but also provide valuable feed- back to system designers. This thesis presents results from robustness evaluation experiments on five UNIX-based operating systems, which include Digital Equipment's OSF/l, Hewlett Packard's HP-UX, Sun Microsystems' Solaris and SunOS, and Silicon Graphics' IRIX. Three sets of experiments were performed. The methodology for evaluation tested (1) the exception handling mechanism, (2) system resource management, and (3) system capacity under high workload stress. An exception generator was used to evaluate the exception handling mechanism of the operating systems. Results included exit status of the exception generator and the system state. Resource management techniques used by individual operating systems were tested using programs designed to usurp system resources such as physical memory and process slots. Finally, the workload stress testing evaluated the effect of the workload on system performance by running a synthetic workload and recording the response time of local and remote user requests. Moderate to severe performance degradations were observed on the systems under stress.

KITTEN Lightweight Kernel 0.1 Beta

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pedretti, Kevin; Levenhagen, Michael; Kelly, Suzanne

2007-12-12

The Kitten Lightweight Kernel is a simplified OS (operating system) kernel that is intended to manage a compute node's hardware resources. It provides a set of mechanisms to user-level applications for utilizing hardware resources (e.g., allocating memory, creating processes, accessing the network). Kitten is much simpler than general-purpose OS kernels, such as Linux or Windows, but includes all of the esssential functionality needed to support HPC (high-performance computing) MPI, PGAS and OpenMP applications. Kitten provides unique capabilities such as physically contiguous application memory, transparent large page support, and noise-free tick-less operation, which enable HPC applications to obtain greater efficiency andmore » scalability than with general purpose OS kernels.« less

A sparse matrix algorithm on the Boolean vector machine

NASA Technical Reports Server (NTRS)

Wagner, Robert A.; Patrick, Merrell L.

1988-01-01

VLSI technology is being used to implement a prototype Boolean Vector Machine (BVM), which is a large network of very small processors with equally small memories that operate in SIMD mode; these use bit-serial arithmetic, and communicate via cube-connected cycles network. The BVM's bit-serial arithmetic and the small memories of individual processors are noted to compromise the system's effectiveness in large numerical problem applications. Attention is presently given to the implementation of a basic matrix-vector iteration algorithm for space matrices of the BVM, in order to generate over 1 billion useful floating-point operations/sec for this iteration algorithm. The algorithm is expressed in a novel language designated 'BVM'.

GraphReduce: Processing Large-Scale Graphs on Accelerator-Based Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sengupta, Dipanjan; Song, Shuaiwen; Agarwal, Kapil

2015-11-15

Recent work on real-world graph analytics has sought to leverage the massive amount of parallelism offered by GPU devices, but challenges remain due to the inherent irregularity of graph algorithms and limitations in GPU-resident memory for storing large graphs. We present GraphReduce, a highly efficient and scalable GPU-based framework that operates on graphs that exceed the device’s internal memory capacity. GraphReduce adopts a combination of edge- and vertex-centric implementations of the Gather-Apply-Scatter programming model and operates on multiple asynchronous GPU streams to fully exploit the high degrees of parallelism in GPUs with efficient graph data movement between the host andmore » device.« less

DIGIMEN, optical mass memory investigations, volume 2

NASA Technical Reports Server (NTRS)

1977-01-01

The DIGIMEM phase of the Optical Mass Memory Investigation Program addressed problems related to the analysis, design, and implementation of a direct digital optical recorder/reproducer. Effort was placed on developing an operational archival mass storage system to support one or more key NASA missions. The primary activity of the DIGIMEM program phase was the design, fabrication, and test and evaluation of a breadboard digital optical recorder/reproducer. Starting with technology and subsystem perfected during the HOLOMEM program phase, a fully operational optical spot recording breadboard that met or exceeded all program goals was evaluated. A thorough evaluation of several high resolution electrophotographic recording films was performed and a preliminary data base management/end user requirements survey was completed.

Blanket Gate Would Address Blocks Of Memory

NASA Technical Reports Server (NTRS)

Lambe, John; Moopenn, Alexander; Thakoor, Anilkumar P.

1988-01-01

Circuit-chip area used more efficiently. Proposed gate structure selectively allows and restricts access to blocks of memory in electronic neural-type network. By breaking memory into independent blocks, gate greatly simplifies problem of reading from and writing to memory. Since blocks not used simultaneously, share operational amplifiers that prompt and read information stored in memory cells. Fewer operational amplifiers needed, and chip area occupied reduced correspondingly. Cost per bit drops as result.

Integral Images: Efficient Algorithms for Their Computation and Storage in Resource-Constrained Embedded Vision Systems

PubMed Central

Ehsan, Shoaib; Clark, Adrian F.; ur Rehman, Naveed; McDonald-Maier, Klaus D.

2015-01-01

The integral image, an intermediate image representation, has found extensive use in multi-scale local feature detection algorithms, such as Speeded-Up Robust Features (SURF), allowing fast computation of rectangular features at constant speed, independent of filter size. For resource-constrained real-time embedded vision systems, computation and storage of integral image presents several design challenges due to strict timing and hardware limitations. Although calculation of the integral image only consists of simple addition operations, the total number of operations is large owing to the generally large size of image data. Recursive equations allow substantial decrease in the number of operations but require calculation in a serial fashion. This paper presents two new hardware algorithms that are based on the decomposition of these recursive equations, allowing calculation of up to four integral image values in a row-parallel way without significantly increasing the number of operations. An efficient design strategy is also proposed for a parallel integral image computation unit to reduce the size of the required internal memory (nearly 35% for common HD video). Addressing the storage problem of integral image in embedded vision systems, the paper presents two algorithms which allow substantial decrease (at least 44.44%) in the memory requirements. Finally, the paper provides a case study that highlights the utility of the proposed architectures in embedded vision systems. PMID:26184211

Integral Images: Efficient Algorithms for Their Computation and Storage in Resource-Constrained Embedded Vision Systems.

PubMed

Ehsan, Shoaib; Clark, Adrian F; Naveed ur Rehman; McDonald-Maier, Klaus D

2015-07-10

The integral image, an intermediate image representation, has found extensive use in multi-scale local feature detection algorithms, such as Speeded-Up Robust Features (SURF), allowing fast computation of rectangular features at constant speed, independent of filter size. For resource-constrained real-time embedded vision systems, computation and storage of integral image presents several design challenges due to strict timing and hardware limitations. Although calculation of the integral image only consists of simple addition operations, the total number of operations is large owing to the generally large size of image data. Recursive equations allow substantial decrease in the number of operations but require calculation in a serial fashion. This paper presents two new hardware algorithms that are based on the decomposition of these recursive equations, allowing calculation of up to four integral image values in a row-parallel way without significantly increasing the number of operations. An efficient design strategy is also proposed for a parallel integral image computation unit to reduce the size of the required internal memory (nearly 35% for common HD video). Addressing the storage problem of integral image in embedded vision systems, the paper presents two algorithms which allow substantial decrease (at least 44.44%) in the memory requirements. Finally, the paper provides a case study that highlights the utility of the proposed architectures in embedded vision systems.

Memory efficient solution of the primitive equations for numerical weather prediction on the CYBER 205

NASA Technical Reports Server (NTRS)

Tuccillo, J. J.

1984-01-01

Numerical Weather Prediction (NWP), for both operational and research purposes, requires only fast computational speed but also large memory. A technique for solving the Primitive Equations for atmospheric motion on the CYBER 205, as implemented in the Mesoscale Atmospheric Simulation System, which is fully vectorized and requires substantially less memory than other techniques such as the Leapfrog or Adams-Bashforth Schemes is discussed. The technique presented uses the Euler-Backard time marching scheme. Also discussed are several techniques for reducing computational time of the model by replacing slow intrinsic routines by faster algorithms which use only hardware vector instructions.

The Naturalistic Flight Deck System: An Integrated System Concept for Improved Single-Pilot Operations

NASA Technical Reports Server (NTRS)

Schutte, Paul C.; Goodrich, Kenneth H.; Cox, David E.; Jackson, Bruce; Palmer, Michael T.; Pope, Alan T.; Schlecht, Robin W.; Tedjojuwono, Ken K.; Trujillo, Anna C.; Williams, Ralph A.;

Hardware support for collecting performance counters directly to memory

DOEpatents

Gara, Alan; Salapura, Valentina; Wisniewski, Robert W.

2012-09-25

Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.

Future applications of associative processor systems to operational KSC systems for optimizing cost and enhancing performance characteristics

NASA Technical Reports Server (NTRS)

Perkinson, J. A.

1974-01-01

The application of associative memory processor equipment to conventional host processors type systems is discussed. Efforts were made to demonstrate how such application relieves the task burden of conventional systems, and enhance system speed and efficiency. Data cover comparative theoretical performance analysis, demonstration of expanded growth capabilities, and demonstrations of actual hardware in simulated environment.

Performance analysis of sliding window filtering of two dimensional signals based on stream data processing systems

NASA Astrophysics Data System (ADS)

Kazanskiy, Nikolay; Protsenko, Vladimir; Serafimovich, Pavel

2016-03-01

This research article contains an experiment with implementation of image filtering task in Apache Storm and IBM InfoSphere Streams stream data processing systems. The aim of presented research is to show that new technologies could be effectively used for sliding window filtering of image sequences. The analysis of execution was focused on two parameters: throughput and memory consumption. Profiling was performed on CentOS operating systems running on two virtual machines for each system. The experiment results showed that IBM InfoSphere Streams has about 1.5 to 13.5 times lower memory footprint than Apache Storm, but could be about 2.0 to 2.5 slower on a real hardware.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Katti, Amogh; Di Fatta, Giuseppe; Naughton, Thomas

Future extreme-scale high-performance computing systems will be required to work under frequent component failures. The MPI Forum s User Level Failure Mitigation proposal has introduced an operation, MPI Comm shrink, to synchronize the alive processes on the list of failed processes, so that applications can continue to execute even in the presence of failures by adopting algorithm-based fault tolerance techniques. This MPI Comm shrink operation requires a failure detection and consensus algorithm. This paper presents three novel failure detection and consensus algorithms using Gossiping. The proposed algorithms were implemented and tested using the Extreme-scale Simulator. The results show that inmore » all algorithms the number of Gossip cycles to achieve global consensus scales logarithmically with system size. The second algorithm also shows better scalability in terms of memory and network bandwidth usage and a perfect synchronization in achieving global consensus. The third approach is a three-phase distributed failure detection and consensus algorithm and provides consistency guarantees even in very large and extreme-scale systems while at the same time being memory and bandwidth efficient.« less

Optical memory development. Volume 3: The membrane light value page composer

NASA Technical Reports Server (NTRS)

Cosentino, L. S.; Nagle, E. M.; Stewart, W. C.

1972-01-01

The feasibility of producing a page composer for optical memory systems using thin, deformable, membrane-mirror elements as light valves was investigated. The electromechanical and optical performances of such elements were determined both analytically and experimentally. It was found that fast switching (approximately 10 microseconds), high-contrast (10 or greater), fatigue-free operation over missions of cycles, and efficient utilization of input light could be obtained with membrane light valves. Several arrays of 64 elements were made on substrates with feedthroughs, allowing access to individual elements from the backside of the substrate. Single light valves on such arrays were successfully operated with the transistors designed and produced for selection and storage at each bit location. This simulated the operation of a prototype page composer with semiconductor chips beam-lead bonded to the back of the substrate.

Perceptual Organization and Operative Thought: A Study of Coherence in Memory.

ERIC Educational Resources Information Center

Heindel, Patricia; Kose, Gary

Examined in three studies were the influence of perceptual organization on children's memory and the relationship between operational thought and memory performance. In the first study, 72 children at 5, 7, and 9 years of age were given a series of Piagetian tasks and a memory task. Subjects were presented with 10 color-shape pairs depicted in…

Filtering Data Based on Human-Inspired Forgetting.

PubMed

Freedman, S T; Adams, J A

2011-12-01

Robots are frequently presented with vast arrays of diverse data. Unfortunately, perfect memory and recall provides a mixed blessing. While flawless recollection of episodic data allows increased reasoning, photographic memory can hinder a robot's ability to operate in real-time dynamic environments. Human-inspired forgetting methods may enable robotic systems to rid themselves of out-dated, irrelevant, and erroneous data. This paper presents the use of human-inspired forgetting to act as a filter, removing unnecessary, erroneous, and out-of-date information. The novel ActSimple forgetting algorithm has been developed specifically to provide effective forgetting capabilities to robotic systems. This paper presents the ActSimple algorithm and how it was optimized and tested in a WiFi signal strength estimation task. The results generated by real-world testing suggest that human-inspired forgetting is an effective means of improving the ability of mobile robots to move and operate within complex and dynamic environments.

Strategies for concurrent processing of complex algorithms in data driven architectures

NASA Technical Reports Server (NTRS)

Stoughton, John W.; Mielke, Roland R.

1988-01-01

The purpose is to document research to develop strategies for concurrent processing of complex algorithms in data driven architectures. The problem domain consists of decision-free algorithms having large-grained, computationally complex primitive operations. Such are often found in signal processing and control applications. The anticipated multiprocessor environment is a data flow architecture containing between two and twenty computing elements. Each computing element is a processor having local program memory, and which communicates with a common global data memory. A new graph theoretic model called ATAMM which establishes rules for relating a decomposed algorithm to its execution in a data flow architecture is presented. The ATAMM model is used to determine strategies to achieve optimum time performance and to develop a system diagnostic software tool. In addition, preliminary work on a new multiprocessor operating system based on the ATAMM specifications is described.

Implicit Memory in Korsakoff’s Syndrome: A Review of Procedural Learning and Priming Studies

PubMed Central

Hayes, Scott M.; Fortier, Catherine B.; Levine, Andrea; Milberg, William P.; McGlinchey, Regina

2013-01-01

Korsakoff’s syndrome (KS) is characterized by dense anterograde amnesia resulting from damage to the diencephalon region, typically resulting from chronic alcohol abuse and thiamine deficiency. This review assesses the integrity of the implicit memory system in KS, focusing on studies of procedural learning and priming. KS patients are impaired on several measures of procedural memory, most likely due to impairment in cognitive functions associated with alcohol-related neural damage outside of the diencephalon. The pattern of performance on tasks of implicit priming suggests reliance on a residual, non-flexible memory operating more or less in an automatic fashion. Our review concludes that whether measures of implicit memory reveal intact or impaired performance in individuals with KS depends heavily on specific task parameters and demands, including timing between stimuli, the specific nature of the stimuli used in a task, and the integrity of supportive cognitive functions necessary for performance. PMID:22592661

Josephson Thermal Memory

NASA Astrophysics Data System (ADS)

Guarcello, Claudio; Solinas, Paolo; Braggio, Alessandro; Di Ventra, Massimiliano; Giazotto, Francesco

2018-01-01

We propose a superconducting thermal memory device that exploits the thermal hysteresis in a flux-controlled temperature-biased superconducting quantum-interference device (SQUID). This system reveals a flux-controllable temperature bistability, which can be used to define two well-distinguishable thermal logic states. We discuss a suitable writing-reading procedure for these memory states. The time of the memory writing operation is expected to be on the order of approximately 0.2 ns for a Nb-based SQUID in thermal contact with a phonon bath at 4.2 K. We suggest a noninvasive readout scheme for the memory states based on the measurement of the effective resonance frequency of a tank circuit inductively coupled to the SQUID. The proposed device paves the way for a practical implementation of thermal logic and computation. The advantage of this proposal is that it represents also an example of harvesting thermal energy in superconducting circuits.

Memory Effects and Nonequilibrium Correlations in the Dynamics of Open Quantum Systems

NASA Astrophysics Data System (ADS)

Morozov, V. G.

2018-01-01

We propose a systematic approach to the dynamics of open quantum systems in the framework of Zubarev's nonequilibrium statistical operator method. The approach is based on the relation between ensemble means of the Hubbard operators and the matrix elements of the reduced statistical operator of an open quantum system. This key relation allows deriving master equations for open systems following a scheme conceptually identical to the scheme used to derive kinetic equations for distribution functions. The advantage of the proposed formalism is that some relevant dynamical correlations between an open system and its environment can be taken into account. To illustrate the method, we derive a non-Markovian master equation containing the contribution of nonequilibrium correlations associated with energy conservation.

Impact of workstations on criticality analyses at ABB combustion engineering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tarko, L.B.; Freeman, R.S.; O'Donnell, P.F.

1993-01-01

During 1991, ABB Combustion Engineering (ABB C-E) made the transition from a CDC Cyber 990 mainframe for nuclear criticality safety analyses to Hewlett Packard (HP)/Apollo workstations. The primary motivation for this change was improved economics of the workstation and maintaining state-of-the-art technology. The Cyber 990 utilized the NOS operating system with a 60-bit word size. The CPU memory size was limited to 131 100 words of directly addressable memory with an extended 250000 words available. The Apollo workstation environment at ABB consists of HP/Apollo-9000/400 series desktop units used by most application engineers, networked with HP/Apollo DN10000 platforms that use 32-bitmore » word size and function as the computer servers and network administrative CPUS, providing a virtual memory system.« less

The memory effect of magnetoelectric coupling in FeGaB/NiTi/PMN-PT multiferroic heterostructure

PubMed Central

Zhou, Ziyao; Zhao, Shishun; Gao, Yuan; Wang, Xinjun; Nan, Tianxiang; Sun, Nian X.; Yang, Xi; Liu, Ming

2016-01-01

Magnetoelectric coupling effect has provided a power efficient approach in controlling the magnetic properties of ferromagnetic materials. However, one remaining issue of ferromagnetic/ferroelectric magnetoelectric bilayer composite is that the induced effective anisotropy disappears with the removal of the electric field. The introducing of the shape memory alloys may prevent such problem by taking the advantage of its shape memory effect. Additionally, the shape memory alloy can also “store” the magnetoelectric coupling before heat release, which introduces more functionality to the system. In this paper, we study a FeGaB/NiTi/PMN-PT multiferroic heterostructure, which can be operating in different states with electric field and temperature manipulation. Such phenomenon is promising for tunable multiferroic devices with multi-functionalities. PMID:26847469

Scalable quantum memory in the ultrastrong coupling regime.

PubMed

Kyaw, T H; Felicetti, S; Romero, G; Solano, E; Kwek, L-C

2015-03-02

Circuit quantum electrodynamics, consisting of superconducting artificial atoms coupled to on-chip resonators, represents a prime candidate to implement the scalable quantum computing architecture because of the presence of good tunability and controllability. Furthermore, recent advances have pushed the technology towards the ultrastrong coupling regime of light-matter interaction, where the qubit-resonator coupling strength reaches a considerable fraction of the resonator frequency. Here, we propose a qubit-resonator system operating in that regime, as a quantum memory device and study the storage and retrieval of quantum information in and from the Z2 parity-protected quantum memory, within experimentally feasible schemes. We are also convinced that our proposal might pave a way to realize a scalable quantum random-access memory due to its fast storage and readout performances.

Scalable quantum memory in the ultrastrong coupling regime

PubMed Central

Kyaw, T. H.; Felicetti, S.; Romero, G.; Solano, E.; Kwek, L.-C.

2015-01-01

Circuit quantum electrodynamics, consisting of superconducting artificial atoms coupled to on-chip resonators, represents a prime candidate to implement the scalable quantum computing architecture because of the presence of good tunability and controllability. Furthermore, recent advances have pushed the technology towards the ultrastrong coupling regime of light-matter interaction, where the qubit-resonator coupling strength reaches a considerable fraction of the resonator frequency. Here, we propose a qubit-resonator system operating in that regime, as a quantum memory device and study the storage and retrieval of quantum information in and from the Z2 parity-protected quantum memory, within experimentally feasible schemes. We are also convinced that our proposal might pave a way to realize a scalable quantum random-access memory due to its fast storage and readout performances. PMID:25727251

Spacecraft On-Board Information Extraction Computer (SOBIEC)

NASA Technical Reports Server (NTRS)

Eisenman, David; Decaro, Robert E.; Jurasek, David W.

1994-01-01

The Jet Propulsion Laboratory is the Technical Monitor on an SBIR Program issued for Irvine Sensors Corporation to develop a highly compact, dual use massively parallel processing node known as SOBIEC. SOBIEC couples 3D memory stacking technology provided by nCUBE. The node contains sufficient network Input/Output to implement up to an order-13 binary hypercube. The benefit of this network, is that it scales linearly as more processors are added, and it is a superset of other commonly used interconnect topologies such as: meshes, rings, toroids, and trees. In this manner, a distributed processing network can be easily devised and supported. The SOBIEC node has sufficient memory for most multi-computer applications, and also supports external memory expansion and DMA interfaces. The SOBIEC node is supported by a mature set of software development tools from nCUBE. The nCUBE operating system (OS) provides configuration and operational support for up to 8000 SOBIEC processors in an order-13 binary hypercube or any subset or partition(s) thereof. The OS is UNIX (USL SVR4) compatible, with C, C++, and FORTRAN compilers readily available. A stand-alone development system is also available to support SOBIEC test and integration.

Statistical modelling of networked human-automation performance using working memory capacity.

PubMed

Ahmed, Nisar; de Visser, Ewart; Shaw, Tyler; Mohamed-Ameen, Amira; Campbell, Mark; Parasuraman, Raja

2014-01-01

This study examines the challenging problem of modelling the interaction between individual attentional limitations and decision-making performance in networked human-automation system tasks. Analysis of real experimental data from a task involving networked supervision of multiple unmanned aerial vehicles by human participants shows that both task load and network message quality affect performance, but that these effects are modulated by individual differences in working memory (WM) capacity. These insights were used to assess three statistical approaches for modelling and making predictions with real experimental networked supervisory performance data: classical linear regression, non-parametric Gaussian processes and probabilistic Bayesian networks. It is shown that each of these approaches can help designers of networked human-automated systems cope with various uncertainties in order to accommodate future users by linking expected operating conditions and performance from real experimental data to observable cognitive traits like WM capacity. Practitioner Summary: Working memory (WM) capacity helps account for inter-individual variability in operator performance in networked unmanned aerial vehicle supervisory tasks. This is useful for reliable performance prediction near experimental conditions via linear models; robust statistical prediction beyond experimental conditions via Gaussian process models and probabilistic inference about unknown task conditions/WM capacities via Bayesian network models.

Shape memory alloy actuated accumulator for ultra-deepwater oil and gas exploration

NASA Astrophysics Data System (ADS)

Patil, Devendra; Song, Gangbing

2016-04-01

As offshore oil and gas exploration moves further offshore and into deeper waters to reach hydrocarbon reserves, it is becoming essential for the industry to develop more reliable and efficient hydraulic accumulators to supply pressured hydraulic fluid for various control and actuation operations, such as closing rams of blowout preventers and controlling subsea valves on the seafloor. By utilizing the shape memory effect property of nitinol, which is a type of shape memory alloy (SMA), an innovative SMA actuated hydraulic accumulator prototype has been developed and successfully tested at Smart Materials and Structure Laboratory at the University of Houston. Absence of gas in the developed SMA accumulator prototype makes it immune to hydrostatic head loss caused by water depth and thus reduces the number of accumulators required in deep water operations. Experiments with a feedback control have demonstrated that the proposed SMA actuated accumulator can provide precisely regulated pressurized fluids. Furthermore the potential use of ultracapacitors along with an embedded system to control the electric power supplied to SMA allows this accumulator to be an autonomous device for deployment. The developed SMA accumulator will make deepwater oil extraction systems more compact and cost effective.

Mini-Ckpts: Surviving OS Failures in Persistent Memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fiala, David; Mueller, Frank; Ferreira, Kurt Brian

Concern is growing in the high-performance computing (HPC) community on the reliability of future extreme-scale systems. Current efforts have focused on application fault-tolerance rather than the operating system (OS), despite the fact that recent studies have suggested that failures in OS memory are more likely. The OS is critical to a system's correct and efficient operation of the node and processes it governs -- and in HPC also for any other nodes a parallelized application runs on and communicates with: Any single node failure generally forces all processes of this application to terminate due to tight communication in HPC. Therefore,more » the OS itself must be capable of tolerating failures. In this work, we introduce mini-ckpts, a framework which enables application survival despite the occurrence of a fatal OS failure or crash. Mini-ckpts achieves this tolerance by ensuring that the critical data describing a process is preserved in persistent memory prior to the failure. Following the failure, the OS is rejuvenated via a warm reboot and the application continues execution effectively making the failure and restart transparent. The mini-ckpts rejuvenation and recovery process is measured to take between three to six seconds and has a failure-free overhead of between 3-5% for a number of key HPC workloads. In contrast to current fault-tolerance methods, this work ensures that the operating and runtime system can continue in the presence of faults. This is a much finer-grained and dynamic method of fault-tolerance than the current, coarse-grained, application-centric methods. Handling faults at this level has the potential to greatly reduce overheads and enables mitigation of additional fault scenarios.« less

Memory and neural networks on the basis of color centers in solids.

PubMed

Winnacker, Albrecht; Osvet, Andres

2009-11-01

Optical data recording is one of the most widely used and efficient systems of memory in the non-living world. The application of color centers in this context offers not only systems of high speed in writing and read-out due to a high degree of parallelism in data handling but also a possibility to set up models of neural networks. In this way, systems with a high potential for image processing, pattern recognition and logical operations can be constructed. A limitation to storage density is given by the diffraction limit of optical data recording. It is shown that this limitation can at least in principle be overcome by the principle of spectral hole burning, which results in systems of storage capacities close to the human brain system.

Scaling to Nanotechnology Limits with the PIMS Computer Architecture and a new Scaling Rule

DOE Office of Scientific and Technical Information (OSTI.GOV)

Debenedictis, Erik P.

2015-02-01

We describe a new approach to computing that moves towards the limits of nanotechnology using a newly formulated sc aling rule. This is in contrast to the current computer industry scali ng away from von Neumann's original computer at the rate of Moore's Law. We extend Moore's Law to 3D, which l eads generally to architectures that integrate logic and memory. To keep pow er dissipation cons tant through a 2D surface of the 3D structure requires using adiabatic principles. We call our newly proposed architecture Processor In Memory and Storage (PIMS). We propose a new computational model that integratesmore » processing and memory into "tiles" that comprise logic, memory/storage, and communications functions. Since the programming model will be relatively stable as a system scales, programs repr esented by tiles could be executed in a PIMS system built with today's technology or could become the "schematic diagram" for implementation in an ultimate 3D nanotechnology of the future. We build a systems software approach that offers advantages over and above the technological and arch itectural advantages. Firs t, the algorithms may be more efficient in the conventional sens e of having fewer steps. Second, the algorithms may run with higher power efficiency per operation by being a better match for the adiabatic scaling ru le. The performance analysis based on demonstrated ideas in physical science suggests 80,000 x improvement in cost per operation for the (arguably) gene ral purpose function of emulating neurons in Deep Learning.« less

Microscopic derivation of particle-based coarse-grained dynamics: Exact expression for memory function

NASA Astrophysics Data System (ADS)

Izvekov, Sergei

2017-03-01

We consider the generalized Langevin equations of motion describing exactly the particle-based coarse-grained dynamics in the classical microscopic ensemble that were derived recently within the Mori-Zwanzig formalism based on new projection operators [S. Izvekov, J. Chem. Phys. 138(13), 134106 (2013)]. The fundamental difference between the new family of projection operators and the standard Zwanzig projection operator used in the past to derive the coarse-grained equations of motion is that the new operators average out the explicit irrelevant trajectories leading to the possibility of solving the projected dynamics exactly. We clarify the definition of the projection operators and revisit the formalism to compute the projected dynamics exactly for the microscopic system in equilibrium. The resulting expression for the projected force is in the form of a "generalized additive fluctuating force" describing the departure of the generalized microscopic force associated with the coarse-grained coordinate from its projection. Starting with this key expression, we formulate a new exact formula for the memory function in terms of microscopic and coarse-grained conservative forces. We conclude by studying two independent limiting cases of practical importance: the Markov limit (vanishing correlations of projected force) and the limit of weak dependence of the memory function on the particle momenta. We present computationally affordable expressions which can be efficiently evaluated from standard molecular dynamics simulations.

A model for the control mode man-computer interface dialogue

NASA Technical Reports Server (NTRS)

Chafin, R. L.

1981-01-01

A four stage model is presented for the control mode man-computer interface dialogue. It consists of context development, semantic development syntactic development, and command execution. Each stage is discussed in terms of the operator skill levels (naive, novice, competent, and expert) and pertinent human factors issues. These issues are human problem solving, human memory, and schemata. The execution stage is discussed in terms of the operators typing skills. This model provides an understanding of the human process in command mode activity for computer systems and a foundation for relating system characteristics to operator characteristics.

Thermal annealing and temperature dependences of memory effect in organic memory transistor

NASA Astrophysics Data System (ADS)

Ren, X. C.; Wang, S. M.; Leung, C. W.; Yan, F.; Chan, P. K. L.

2011-07-01

We investigate the annealing and thermal effects of organic non-volatile memory with floating silver nanoparticles by real-time transfer curve measurements. During annealing, the memory window shows shrinkage of 23% due to structural variation of the nanoparticles. However, by increasing the device operating temperature from 20 to 90 °C after annealing, the memory window demonstrates an enlargement up to 100%. The differences in the thermal responses are explained and confirmed by the co-existence of electron and hole traps. Our findings provide a better understanding of organic memory performances under various operating temperatures and validate their applications for temperature sensing or thermal memories.

Low-voltage operating flexible ferroelectric organic field-effect transistor nonvolatile memory with a vertical phase separation P(VDF-TrFE-CTFE)/PS dielectric

NASA Astrophysics Data System (ADS)

Xu, Meili; Xiang, Lanyi; Xu, Ting; Wang, Wei; Xie, Wenfa; Zhou, Dayu

2017-10-01

Future flexible electronic systems require memory devices combining low-power operation and mechanical bendability. However, high programming/erasing voltages, which are universally needed to switch the storage states in previously reported ferroelectric organic field-effect transistor (Fe-OFET) nonvolatile memories (NVMs), severely prevent their practical applications. In this work, we develop a route to achieve a low-voltage operating flexible Fe-OFET NVM. Utilizing vertical phase separation, an ultrathin self-organized poly(styrene) (PS) buffering layer covers the surface of the ferroelectric polymer layer by one-step spin-coating from their blending solution. The ferroelectric polymer with a low coercive field contributes to low-voltage operation in the Fe-OFET NVM. The polymer PS contributes to the improvement of mobility, attributing to screening the charge scattering and decreasing the surface roughness. As a result, a high performance flexible Fe-OFET NVM is achieved at the low P/E voltages of ±10 V, with a mobility larger than 0.2 cm2 V-1 s-1, a reliable P/E endurance over 150 cycles, stable data storage retention capability over 104 s, and excellent mechanical bending durability with a slight performance degradation after 1000 repetitive tensile bending cycles at a curvature radius of 5.5 mm.

Ground Software Maintenance Facility (GSMF) user's manual. Appendices NASA-CR-178806 NAS 1.26:178806 Rept-41849-G159-026-App HC A05/MF A01

NASA Technical Reports Server (NTRS)

Aquila, V.; Derrig, D.; Griffith, G.

1986-01-01

Procedures are presented that allow the user to assemble tasks, link, compile, backup the system, generate/establish/print display pages, cancel tasks in memory, and to TET an assembly task without having to enter the commands every time. A list of acronyms is provided. Software identification, payload checkout unit operating system services, data base generation, and MITRA operating procedures are also discussed.

Personal Computer and Workstation Operating Systems Tutorial

DTIC Science & Technology

1994-03-01

to a RAM area where it is executed by the CPU. The program consists of instructions that perform operations on data. The CPU will perform two basic...memory to improve system performance. More often the user will buy a new fixed disk so the computer will hold more programs internally. The trend today...MHZ. Another way to view how fast the information is going into the register is in a time domain rather than a frequency domain knowing that time and

IMAGES: A digital computer program for interactive modal analysis and gain estimation for eigensystem synthesis

NASA Technical Reports Server (NTRS)

Jones, R. L.

1984-01-01

An interactive digital computer program for modal analysis and gain estimation for eigensystem synthesis was written. Both mathematical and operation considerations are described; however, the mathematical presentation is limited to those concepts essential to the operational capability of the program. The program is capable of both modal and spectral synthesis of multi-input control systems. It is user friendly, has scratchpad capability and dynamic memory, and can be used to design either state or output feedback systems.

Error Characterization and Mitigation for 16Nm MLC NAND Flash Memory Under Total Ionizing Dose Effect

NASA Technical Reports Server (NTRS)

Li, Yue (Inventor); Bruck, Jehoshua (Inventor)

2018-01-01

A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count.

A Real-Time Image Acquisition And Processing System For A RISC-Based Microcomputer

NASA Astrophysics Data System (ADS)

Luckman, Adrian J.; Allinson, Nigel M.

1989-03-01

A low cost image acquisition and processing system has been developed for the Acorn Archimedes microcomputer. Using a Reduced Instruction Set Computer (RISC) architecture, the ARM (Acorn Risc Machine) processor provides instruction speeds suitable for image processing applications. The associated improvement in data transfer rate has allowed real-time video image acquisition without the need for frame-store memory external to the microcomputer. The system is comprised of real-time video digitising hardware which interfaces directly to the Archimedes memory, and software to provide an integrated image acquisition and processing environment. The hardware can digitise a video signal at up to 640 samples per video line with programmable parameters such as sampling rate and gain. Software support includes a work environment for image capture and processing with pixel, neighbourhood and global operators. A friendly user interface is provided with the help of the Archimedes Operating System WIMP (Windows, Icons, Mouse and Pointer) Manager. Windows provide a convenient way of handling images on the screen and program control is directed mostly by pop-up menus.

Distributed Sensor Networks

DTIC Science & Technology

1979-09-30

University, Pittsburgh, Pennsylvania (1976). 14. R. L. Kirby, "ULISP for PDP-11s with Memory Management ," Report MCS-76-23763, University of Maryland...teletVpe or 9 raphIc S output. The recor iuL, po , uitist il so mon itot its owvn ( Onmand queue and a( knowlede commands Sent to It hN the UsCtr interfa I...kernel. By a net- work kernel we mean a multicomputer distributed operating system kernel that includes proces- sor schedulers, "core" memory managers , and

Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor

DTIC Science & Technology

2007-06-01

requires a significant deviation from previous work. For instance, we find that using the relaxed input replication model from Reunion incurs a...Circuit Width Delay Count CRC-16 16 6.65 754 CRC- SDLC -16 16 6.10 888 CRC-32 16 7.28 2260 CRC-32 32 8.60 4240 Table 1. FO4 delay and transistor count for...the operation of our proposed system is the same in all other respects. 4.4 Compatibility Across Memory Consis- tency Models The memory consistency

Terminal attractors for addressable memory in neural networks

NASA Technical Reports Server (NTRS)

Zak, Michail

1988-01-01

A new type of attractors - terminal attractors - for an addressable memory in neural networks operating in continuous time is introduced. These attractors represent singular solutions of the dynamical system. They intersect (or envelope) the families of regular solutions while each regular solution approaches the terminal attractor in a finite time period. It is shown that terminal attractors can be incorporated into neural networks such that any desired set of these attractors with prescribed basins is provided by an appropriate selection of the weight matrix.

Interfacing laboratory instruments to multiuser, virtual memory computers

NASA Technical Reports Server (NTRS)

Generazio, Edward R.; Stang, David B.; Roth, Don J.

1989-01-01

Incentives, problems and solutions associated with interfacing laboratory equipment with multiuser, virtual memory computers are presented. The major difficulty concerns how to utilize these computers effectively in a medium sized research group. This entails optimization of hardware interconnections and software to facilitate multiple instrument control, data acquisition and processing. The architecture of the system that was devised, and associated programming and subroutines are described. An example program involving computer controlled hardware for ultrasonic scan imaging is provided to illustrate the operational features.

A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

NASA Astrophysics Data System (ADS)

Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2017-04-01

A high-density nonvolatile associative memory (NV-AM) based on spin transfer torque magnetoresistive random access memory (STT-MRAM), which achieves highly concurrent and ultralow-power nearest neighbor search with full adaptivity of the template data format, has been proposed and fabricated using the 90 nm CMOS/70 nm perpendicular-magnetic-tunnel-junction hybrid process. A truly compact current-mode circuitry is developed to realize flexibly controllable and high-parallel similarity evaluation, which makes the NV-AM adaptable to any dimensionality and component-bit of template data. A compact dual-stage time-domain minimum searching circuit is also developed, which can freely extend the system for more template data by connecting multiple NM-AM cores without additional circuits for integrated processing. Both the embedded STT-MRAM module and the computing circuit modules in this NV-AM chip are synchronously power-gated to completely eliminate standby power and maximally reduce operation power by only activating the currently accessed circuit blocks. The operations of a prototype chip at 40 MHz are demonstrated by measurement. The average operation power is only 130 µW, and the circuit density is less than 11 µm2/bit. Compared with the latest conventional works in both volatile and nonvolatile approaches, more than 31.3% circuit area reductions and 99.2% power improvements are achieved, respectively. Further power performance analyses are discussed, which verify the special superiority of the proposed NV-AM in low-power and large-memory-based VLSIs.

A memory efficient user interface for CLIPS micro-computer applications

NASA Technical Reports Server (NTRS)

Sterle, Mark E.; Mayer, Richard J.; Jordan, Janice A.; Brodale, Howard N.; Lin, Min-Jin

1990-01-01

The goal of the Integrated Southern Pine Beetle Expert System (ISPBEX) is to provide expert level knowledge concerning treatment advice that is convenient and easy to use for Forest Service personnel. ISPBEX was developed in CLIPS and delivered on an IBM PC AT class micro-computer, operating with an MS/DOS operating system. This restricted the size of the run time system to 640K. In order to provide a robust expert system, with on-line explanation, help, and alternative actions menus, as well as features that allow the user to back up or execute 'what if' scenarios, a memory efficient menuing system was developed to interface with the CLIPS programs. By robust, we mean an expert system that (1) is user friendly, (2) provides reasonable solutions for a wide variety of domain specific problems, (3) explains why some solutions were suggested but others were not, and (4) provides technical information relating to the problem solution. Several advantages were gained by using this type of user interface (UI). First, by storing the menus on the hard disk (instead of main memory) during program execution, a more robust system could be implemented. Second, since the menus were built rapidly, development time was reduced. Third, the user may try a new scenario by backing up to any of the input screens and revising segments of the original input without having to retype all the information. And fourth, asserting facts from the menus provided for a dynamic and flexible fact base. This UI technology has been applied successfully in expert systems applications in forest management, agriculture, and manufacturing. This paper discusses the architecture of the UI system, human factors considerations, and the menu syntax design.

Bottlenecks of Motion Processing during a Visual Glance: The Leaky Flask Model

PubMed Central

Öğmen, Haluk; Ekiz, Onur; Huynh, Duong; Bedell, Harold E.; Tripathy, Srimant P.

2013-01-01

Where do the bottlenecks for information and attention lie when our visual system processes incoming stimuli? The human visual system encodes the incoming stimulus and transfers its contents into three major memory systems with increasing time scales, viz., sensory (or iconic) memory, visual short-term memory (VSTM), and long-term memory (LTM). It is commonly believed that the major bottleneck of information processing resides in VSTM. In contrast to this view, we show major bottlenecks for motion processing prior to VSTM. In the first experiment, we examined bottlenecks at the stimulus encoding stage through a partial-report technique by delivering the cue immediately at the end of the stimulus presentation. In the second experiment, we varied the cue delay to investigate sensory memory and VSTM. Performance decayed exponentially as a function of cue delay and we used the time-constant of the exponential-decay to demarcate sensory memory from VSTM. We then decomposed performance in terms of quality and quantity measures to analyze bottlenecks along these dimensions. In terms of the quality of information, two thirds to three quarters of the motion-processing bottleneck occurs in stimulus encoding rather than memory stages. In terms of the quantity of information, the motion-processing bottleneck is distributed, with the stimulus-encoding stage accounting for one third of the bottleneck. The bottleneck for the stimulus-encoding stage is dominated by the selection compared to the filtering function of attention. We also found that the filtering function of attention is operating mainly at the sensory memory stage in a specific manner, i.e., influencing only quantity and sparing quality. These results provide a novel and more complete understanding of information processing and storage bottlenecks for motion processing. PMID:24391806

Bottlenecks of motion processing during a visual glance: the leaky flask model.

PubMed

Öğmen, Haluk; Ekiz, Onur; Huynh, Duong; Bedell, Harold E; Tripathy, Srimant P

2013-01-01

Where do the bottlenecks for information and attention lie when our visual system processes incoming stimuli? The human visual system encodes the incoming stimulus and transfers its contents into three major memory systems with increasing time scales, viz., sensory (or iconic) memory, visual short-term memory (VSTM), and long-term memory (LTM). It is commonly believed that the major bottleneck of information processing resides in VSTM. In contrast to this view, we show major bottlenecks for motion processing prior to VSTM. In the first experiment, we examined bottlenecks at the stimulus encoding stage through a partial-report technique by delivering the cue immediately at the end of the stimulus presentation. In the second experiment, we varied the cue delay to investigate sensory memory and VSTM. Performance decayed exponentially as a function of cue delay and we used the time-constant of the exponential-decay to demarcate sensory memory from VSTM. We then decomposed performance in terms of quality and quantity measures to analyze bottlenecks along these dimensions. In terms of the quality of information, two thirds to three quarters of the motion-processing bottleneck occurs in stimulus encoding rather than memory stages. In terms of the quantity of information, the motion-processing bottleneck is distributed, with the stimulus-encoding stage accounting for one third of the bottleneck. The bottleneck for the stimulus-encoding stage is dominated by the selection compared to the filtering function of attention. We also found that the filtering function of attention is operating mainly at the sensory memory stage in a specific manner, i.e., influencing only quantity and sparing quality. These results provide a novel and more complete understanding of information processing and storage bottlenecks for motion processing.

An Evaluation Methodology for Protocol Analysis Systems

DTIC Science & Technology

2007-03-01

Main Memory Requirement NS: Needham-Schroeder NSL: Needham-Schroeder-Lowe OCaml : Objective Caml POSIX: Portable Operating System...methodology is needed. A. PROTOCOL ANALYSIS FIELD As with any field, there is a specialized language used within the protocol analysis community. Figure...ProVerif requires that Objective Caml ( OCaml ) be installed on the system, OCaml version 3.09.3 was installed. C. WINDOWS CONFIGURATION OS

JPRS Report Science & Technology Europe.

DTIC Science & Technology

1992-10-22

Potatoes for More Sugar [Frankfurt/Main FRANKFURTER ALLEGEMEINE, 12 Aug 92] 26 COMPUTERS French Devise Operating System for Parallel, Failure...Tolerant and Real-Time Systems [Munich COMPUTER WOCHE, 5 Jun 92] 27 Germany Markets External Mass Memory for IBM-Compatible Parallel Interfaces...Infrared Detection System [Thierry Lucas; Paris L’USINE NOUVELLE TECHNOLOGIES, 16 Jul 92] 28 Streamlined ACE Fighter Airplane Approved [Paris AFP

Contention Modeling for Multithreaded Distributed Shared Memory Machines: The Cray XMT

DOE Office of Scientific and Technical Information (OSTI.GOV)

Secchi, Simone; Tumeo, Antonino; Villa, Oreste

Distributed Shared Memory (DSM) machines are a wide class of multi-processor computing systems where a large virtually-shared address space is mapped on a network of physically distributed memories. High memory latency and network contention are two of the main factors that limit performance scaling of such architectures. Modern high-performance computing DSM systems have evolved toward exploitation of massive hardware multi-threading and fine-grained memory hashing to tolerate irregular latencies, avoid network hot-spots and enable high scaling. In order to model the performance of such large-scale machines, parallel simulation has been proved to be a promising approach to achieve good accuracy inmore » reasonable times. One of the most critical factors in solving the simulation speed-accuracy trade-off is network modeling. The Cray XMT is a massively multi-threaded supercomputing architecture that belongs to the DSM class, since it implements a globally-shared address space abstraction on top of a physically distributed memory substrate. In this paper, we discuss the development of a contention-aware network model intended to be integrated in a full-system XMT simulator. We start by measuring the effects of network contention in a 128-processor XMT machine and then investigate the trade-off that exists between simulation accuracy and speed, by comparing three network models which operate at different levels of accuracy. The comparison and model validation is performed by executing a string-matching algorithm on the full-system simulator and on the XMT, using three datasets that generate noticeably different contention patterns.« less

Memory Operations and Structures in Sentence Comprehension: Evidence from Ellipsis

ERIC Educational Resources Information Center

Martin, Andrea Eyleen

2010-01-01

Natural language often contains dependencies that span words, phrases, or even sentences. Thus, language comprehension relies on recovering recently processed information from memory for subsequent interpretation. This dissertation investigates the memory operations that subserve dependency resolution through the lens of "verb-phrase ellipsis"…

Memory and law: what can cognitive neuroscience contribute?

PubMed

Schacter, Daniel L; Loftus, Elizabeth F

2013-02-01

A recent decision in the United States by the New Jersey Supreme Court has led to improved jury instructions that incorporate psychological research showing that memory does not operate like a video recording. Here we consider how cognitive neuroscience could contribute to addressing memory in the courtroom. We discuss conditions in which neuroimaging can distinguish true and false memories in the laboratory and note reasons to be skeptical about its use in courtroom cases. We also discuss neuroscience research concerning false and imagined memories, misinformation effects and reconsolidation phenomena that may enhance understanding of why memory does not operate like a video recording.

Combination of chronic stress and ovariectomy causes conditioned fear memory deficits and hippocampal cholinergic neuronal loss in mice.

PubMed

Takuma, K; Mizoguchi, H; Funatsu, Y; Hoshina, Y; Himeno, Y; Fukuzaki, E; Kitahara, Y; Arai, S; Ibi, D; Kamei, H; Matsuda, T; Koike, K; Inoue, M; Nagai, T; Yamada, K

2012-04-05

We have recently found that the combination of ovariectomy (OVX) and chronic restraint stress (CS) causes hippocampal pyramidal cell loss and cognitive dysfunction in female rats and that estrogen replacement prevents the OVX/CS-induced morphological and behavioral changes. In this study, to clarify the mechanisms underlying the OVX/CS-mediated memory impairment further, we examined the roles of cholinergic systems in the OVX/CS-induced memory impairment in mice. Female Slc:ICR strain mice were randomly divided into two groups: OVX and sham-operated groups. Two weeks after the operation, the mice of each group were further assigned to CS (6 h/day) or non-stress group. Following the 3-week-stress period, all mice were subjected to contextual fear conditioning, and context- and tone-dependent memory tests were conducted 1 or 24 h after the conditioning. Overburden with 3 weeks of CS from 2 weeks after OVX impaired context- and tone-dependent freezing and the OVX/CS caused significant Nissl-stained neuron-like cell loss in the hippocampal CA3 region, although OVX and CS alone did not cause such behavioral and histological changes. Replacement of 17β-estradiol for 5 weeks after OVX suppressed OVX/CS-induced memory impairment and hippocampal Nissl-positive cell loss. Furthermore, the OVX/CS mice exhibited a significant decrease in choline acetyltransferase in the hippocampus compared with other groups. The cholinesterase inhibitors donepezil and galantamine ameliorated OVX/CS-induced memory impairment. These data suggest that cholinergic dysfunction may be involved in the OVX/CS-induced conditioned fear memory impairment. Overall, our findings suggest that the OVX/CS mouse model is useful to study the mechanisms underlying estrogen loss-induced memory deficits. Copyright © 2012 IBRO. Published by Elsevier Ltd. All rights reserved.

Investigation of Hafnium oxide/Copper resistive memory for advanced encryption applications

NASA Astrophysics Data System (ADS)

Briggs, Benjamin D.

The Advanced Encryption Standard (AES) is a widely used encryption algorithm to protect data and communications in today's digital age. Modern AES CMOS implementations require large amounts of dedicated logic and must be tuned for either performance or power consumption. A high throughput, low power, and low die area AES implementation is required in the growing mobile sector. An emerging non-volatile memory device known as resistive memory (ReRAM) is a simple metal-insulator-metal capacitor device structure with the ability to switch between two stable resistance states. Currently, ReRAM is targeted as a non-volatile memory replacement technology to eventually replace flash. Its advantages over flash include ease of fabrication, speed, and lower power consumption. In addition to memory, ReRAM can also be used in advanced logic implementations given its purely resistive behavior. The combination of a new non-volatile memory element ReRAM along with high performance, low power CMOS opens new avenues for logic implementations. This dissertation will cover the design and process implementation of a ReRAM-CMOS hybrid circuit, built using IBM's 10LPe process, for the improvement of hardware AES implementations. Further the device characteristics of ReRAM, specifically the HfO2/Cu memory system, and mechanisms for operation are not fully correlated. Of particular interest to this work is the role of material properties such as the stoichiometry, crystallinity, and doping of the HfO2 layer and their effect on the switching characteristics of resistive memory. Material properties were varied by a combination of atomic layer deposition and reactive sputtering of the HfO2 layer. Several studies will be discussed on how the above mentioned material properties influence switching parameters, and change the underlying physics of device operation.

FinFET memory cell improvements for higher immunity against single event upsets

NASA Astrophysics Data System (ADS)

Sajit, Ahmed Sattar

The 21st century is witnessing a tremendous demand for transistors. Life amenities have incorporated the transistor in every aspect of daily life, ranging from toys to rocket science. Day by day, scaling down the transistor is becoming an imperious necessity. However, it is not a straightforward process; instead, it faces overwhelming challenges. Due to these scaling changes, new technologies, such as FinFETs for example, have emerged as alternatives to the conventional bulk-CMOS technology. FinFET has more control over the channel, therefore, leakage current is reduced. FinFET could bridge the gap between silicon devices and non-silicon devices. The semiconductor industry is now incorporating FinFETs in systems and subsystems. For example, Intel has been using them in their newest processors, delivering potential saving powers and increased speeds to memory circuits. Memory sub-systems are considered a vital component in the digital era. In memory, few rows are read or written at a time, while the most rows are static; hence, reducing leakage current increases the performance. However, as a transistor shrinks, it becomes more vulnerable to the effects from radioactive particle strikes. If a particle hits a node in a memory cell, the content might flip; consequently, leading to corrupting stored data. Critical fields, such as medical and aerospace, where there are no second chances and cannot even afford to operate at 99.99% accuracy, has induced me to find a rigid circuit in a radiated working environment. This research focuses on a wide spectrum of memories such as 6T SRAM, 8T SRAM, and DICE memory cells using FinFET technology and finding the best platform in terms of Read and Write delay, susceptibility level of SNM, RSNM, leakage current, energy consumption, and Single Event Upsets (SEUs). This research has shown that the SEU tolerance that 6T and 8T FinFET SRAMs provide may not be acceptable in medical and aerospace applications where there is a very high likelihood of SEUs. Consequently, FinFET DICE memory can be a good candidate due to its high ability to tolerate SEUs of different amplitudes and long periods for both read and hold operations.

Chronic sleep deprivation differentially affects short and long-term operant memory in Aplysia.

PubMed

Krishnan, Harini C; Noakes, Eric J; Lyons, Lisa C

2016-10-01

The induction, formation and maintenance of memory represent dynamic processes modulated by multiple factors including the circadian clock and sleep. Chronic sleep restriction has become common in modern society due to occupational and social demands. Given the impact of cognitive impairments associated with sleep deprivation, there is a vital need for a simple animal model in which to study the interactions between chronic sleep deprivation and memory. We used the marine mollusk Aplysia californica, with its simple nervous system, nocturnal sleep pattern and well-characterized learning paradigms, to assess the effects of two chronic sleep restriction paradigms on short-term (STM) and long-term (LTM) associative memory. The effects of sleep deprivation on memory were evaluated using the operant learning paradigm, learning that food is inedible, in which the animal associates a specific netted seaweed with failed swallowing attempts. We found that two nights of 6h sleep deprivation occurring during the first or last half of the night inhibited both STM and LTM. Moreover, the impairment in STM persisted for more than 24h. A milder, prolonged sleep deprivation paradigm consisting of 3 consecutive nights of 4h sleep deprivation also blocked STM, but had no effect on LTM. These experiments highlight differences in the sensitivity of STM and LTM to chronic sleep deprivation. Moreover, these results establish Aplysia as a valid model for studying the interactions between chronic sleep deprivation and associative memory paving the way for future studies delineating the mechanisms through which sleep restriction affects memory formation. Copyright © 2016 Elsevier Inc. All rights reserved.

Chronic Sleep Deprivation Differentially Affects Short and Long-term Operant Memory in Aplysia

PubMed Central

Krishnan, Harini C.; Noakes, Eric J.; Lyons, Lisa C.

2016-01-01

The induction, formation and maintenance of memory represent dynamic processes modulated by multiple factors including the circadian clock and sleep. Chronic sleep restriction has become common in modern society due to occupational and social demands. Given the impact of cognitive impairments associated with sleep deprivation, there is a vital need for a simple animal model in which to study the interactions between chronic sleep deprivation and memory. We used the marine mollusk Aplysia californica, with its simple nervous system, nocturnal sleep pattern and well-characterized learning paradigms, to assess the effects of two chronic sleep restriction paradigms on short-term (STM) and long-term (LTM) associative memory. The effects of sleep deprivation on memory were evaluated using the operant learning paradigm, learning that food is inedible, in which the animal associates a specific netted seaweed with failed swallowing attempts. We found that two nights of 6 h sleep deprivation occurring during the first or last half of the night inhibited both STM and LTM. Moreover, the impairment in STM persisted for more than 24 hours. A milder, prolonged sleep deprivation paradigm consisting of 3 consecutive nights of 4 h sleep deprivation also blocked STM, but had no effect on LTM. These experiments highlight differences in the sensitivity of STM and LTM to chronic sleep deprivation. Moreover, these results establish Aplysia as a valid model for studying the interactions between chronic sleep deprivation and associative memory paving the way for future studies delineating the mechanisms through which sleep restriction affects memory formation. PMID:27555235

Implementing asyncronous collective operations in a multi-node processing system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Dong; Eisley, Noel A.; Heidelberger, Philip

A method, system, and computer program product are disclosed for implementing an asynchronous collective operation in a multi-node data processing system. In one embodiment, the method comprises sending data to a plurality of nodes in the data processing system, broadcasting a remote get to the plurality of nodes, and using this remote get to implement asynchronous collective operations on the data by the plurality of nodes. In one embodiment, each of the nodes performs only one task in the asynchronous operations, and each nodes sets up a base address table with an entry for a base address of a memorymore » buffer associated with said each node. In another embodiment, each of the nodes performs a plurality of tasks in said collective operations, and each task of each node sets up a base address table with an entry for a base address of a memory buffer associated with the task.« less

The organization and neural substrates of human memory.

PubMed

Squire, L R

The neurology of memory has been illuminated by parallel studies of patients with circumscribed memory impairment and animal models of human amnesia. Human amnesia can occur as an isolated cognitive deficit that impairs the ability to learn new facts and episodes. In addition, memory can be affected for material learned many years prior to the onset of amnesia. The finding that some memory abilities are intact in amnesia (e.g., skill learning, word priming, and adaptation-level effects) has suggested that memory can be divided into two or more separate processes. Declarative memory affords the ability to store information explicitly and to retrieve it later as a conscious recollection. This form of memory depends on the integrity of the structures damaged in amnesia. Other, non-declarative kinds of memory afford the ability to change as the result of experience, but the information is available only through performance. Recent studies of a favorable human case provided strong evidence that the hippocampus is a critical component of the declarative memory system. Extensive convergent and divergent projections link the hippocampus to many areas of neocortex where processing and storage of new information is likely to occur. It is perhaps by way of these connections that the hippocampus operates upon and participates in declarative representations.

GraphReduce: Large-Scale Graph Analytics on Accelerator-Based HPC Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sengupta, Dipanjan; Agarwal, Kapil; Song, Shuaiwen

2015-09-30

Recent work on real-world graph analytics has sought to leverage the massive amount of parallelism offered by GPU devices, but challenges remain due to the inherent irregularity of graph algorithms and limitations in GPU-resident memory for storing large graphs. We present GraphReduce, a highly efficient and scalable GPU-based framework that operates on graphs that exceed the device’s internal memory capacity. GraphReduce adopts a combination of both edge- and vertex-centric implementations of the Gather-Apply-Scatter programming model and operates on multiple asynchronous GPU streams to fully exploit the high degrees of parallelism in GPUs with efficient graph data movement between the hostmore » and the device.« less

Composing Data Parallel Code for a SPARQL Graph Engine

DOE Office of Scientific and Technical Information (OSTI.GOV)

Castellana, Vito G.; Tumeo, Antonino; Villa, Oreste

Big data analytics process large amount of data to extract knowledge from them. Semantic databases are big data applications that adopt the Resource Description Framework (RDF) to structure metadata through a graph-based representation. The graph based representation provides several benefits, such as the possibility to perform in memory processing with large amounts of parallelism. SPARQL is a language used to perform queries on RDF-structured data through graph matching. In this paper we present a tool that automatically translates SPARQL queries to parallel graph crawling and graph matching operations. The tool also supports complex SPARQL constructs, which requires more than basicmore » graph matching for their implementation. The tool generates parallel code annotated with OpenMP pragmas for x86 Shared-memory Multiprocessors (SMPs). With respect to commercial database systems such as Virtuoso, our approach reduces memory occupation due to join operations and provides higher performance. We show the scaling of the automatically generated graph-matching code on a 48-core SMP.« less

Clinical significance of knowledge about the structure, function, and impairments of working memory

PubMed Central

Brodziak, Andrzej; Brewczyński, Adam; Bajor, Grzegorz

2013-01-01

A review of contemporary research on the working memory system (WMS) is important, both due to the need to focus the discussion on further necessary investigations on the structure and function of this key part of the human brain, as well as to share this knowledge with clinicians. In our introduction we try to clarify the actual terminology and provide an intuitively understandable model for 3 basic cognitive operations: perception, recognition, imagery, and manipulation of recalled mental images. We emphasize the importance of knowledge of the structure and function of the WMS for the possibility to demonstrate the links between genetic polymorphisms and the prevalence to some mental disorders. We also review current knowledge of working memory dysfunction in the most common diseases and specific clinical situations such as maturation and aging. Finally, we briefly discuss methods for assessment of WMS capacity. This article establishes a kind of compendium of knowledge for clinicians who are not familiar with the structure and operation of the WMS. PMID:23645218

ASIC-based architecture for the real-time computation of 2D convolution with large kernel size

NASA Astrophysics Data System (ADS)

Shao, Rui; Zhong, Sheng; Yan, Luxin

2015-12-01

Bidimensional convolution is a low-level processing algorithm of interest in many areas, but its high computational cost constrains the size of the kernels, especially in real-time embedded systems. This paper presents a hardware architecture for the ASIC-based implementation of 2-D convolution with medium-large kernels. Aiming to improve the efficiency of storage resources on-chip, reducing off-chip bandwidth of these two issues, proposed construction of a data cache reuse. Multi-block SPRAM to cross cached images and the on-chip ping-pong operation takes full advantage of the data convolution calculation reuse, design a new ASIC data scheduling scheme and overall architecture. Experimental results show that the structure can achieve 40× 32 size of template real-time convolution operations, and improve the utilization of on-chip memory bandwidth and on-chip memory resources, the experimental results show that the structure satisfies the conditions to maximize data throughput output , reducing the need for off-chip memory bandwidth.

Low-voltage-operated organic one-time programmable memory using printed organic thin-film transistors and antifuse capacitors.

PubMed

Jung, Soon-Won; Na, Bock Soon; Park, Chan Woo; Koo, Jae Bon

2014-11-01

We demonstrate an organic one-time programmable memory cell formed entirely at plastic-compatible temperatures. All the processes are performed at below 130 degrees C. Our memory cell consists of a printed organic transistor and an organic capacitor. Inkjet-printed organic transistors are fabricated by using high-k polymer dielectric blends comprising poly(vinylidenefluoride-trifluoroethylene) [P(VDF-TrFE)] and poly(methyl methacrylate) (PMMA) for low-voltage operation. P(NDI2OD-T2) transistors have a high field-effect mobility of 0.2 cm2/Vs and a low operation gate voltage of less than 10 V. The operation voltage effectively decreases owing to the high permittivity of the P(VDF-TrFE):PMMA blended film. The data in the memory cell are programmed by electrically breaking the organic capacitor. The organic capacitor acts like an antifuse capacitor, because it is initially open, and it becomes permanently short-circuited by applying a high voltage. The organic memory cells are programmed with 4 V, and they are read out with 2 V. The memory data are read out by sensing the current in the memory cell. The printed organic one-time programmable memory is suitable for applications storing small amount of data, such as low-cost radio-frequency identification (RFID) tag.

Regional information guidance system based on hypermedia concept

NASA Astrophysics Data System (ADS)

Matoba, Hiroshi; Hara, Yoshinori; Kasahara, Yutako

1990-08-01

A regional information guidance system has been developed on an image workstation. Two main features of this system are hypermedia data structure and friendly visual interface realized by the full-color frame memory system. As the hypermedia data structure manages regional information such as maps, pictures and explanations of points of interest, users can retrieve those information one by one, next to next according to their interest change. For example, users can retrieve explanation of a picture through the link between pictures and text explanations. Users can also traverse from one document to another by using keywords as cross reference indices. The second feature is to utilize a full-color, high resolution and wide space frame memory for visual interface design. This frame memory system enables real-time operation of image data and natural scene representation. The system also provides half tone representing function which enables fade-in/out presentations. This fade-in/out functions used in displaying and erasing menu and image data, makes visual interface soft for human eyes. The system we have developed is a typical example of multimedia applications. We expect the image workstation will play an important role as a platform for multimedia applications.

A Malicious Pattern Detection Engine for Embedded Security Systems in the Internet of Things

PubMed Central

Oh, Doohwan; Kim, Deokho; Ro, Won Woo

2014-01-01

With the emergence of the Internet of Things (IoT), a large number of physical objects in daily life have been aggressively connected to the Internet. As the number of objects connected to networks increases, the security systems face a critical challenge due to the global connectivity and accessibility of the IoT. However, it is difficult to adapt traditional security systems to the objects in the IoT, because of their limited computing power and memory size. In light of this, we present a lightweight security system that uses a novel malicious pattern-matching engine. We limit the memory usage of the proposed system in order to make it work on resource-constrained devices. To mitigate performance degradation due to limitations of computation power and memory, we propose two novel techniques, auxiliary shifting and early decision. Through both techniques, we can efficiently reduce the number of matching operations on resource-constrained systems. Experiments and performance analyses show that our proposed system achieves a maximum speedup of 2.14 with an IoT object and provides scalable performance for a large number of patterns. PMID:25521382

Using Rollback Avoidance to Mitigate Failures in Next-Generation Extreme-Scale Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Levy, Scott N.

2016-05-01

High-performance computing (HPC) systems enable scientists to numerically model complex phenomena in many important physical systems. The next major milestone in the development of HPC systems is the construction of the rst supercomputer capable executing more than an exa op, 10 18 oating point operations per second. On systems of this scale, failures will occur much more frequently than on current systems. As a result, resilience is a key obstacle to building next-generation extremescale systems. Coordinated checkpointing is currently the most widely-used mechanism for handling failures on HPC systems. Although coordinated checkpointing remains e ective on current systems, increasing themore » scale of today's systems to build next-generation systems will increase the cost of fault tolerance as more and more time is taken away from the application to protect against or recover from failure. Rollback avoidance techniques seek to mitigate the cost of checkpoint/restart by allowing an application to continue its execution rather than rolling back to an earlier checkpoint when failures occur. These techniqes include failure prediction and preventive migration, replicated computation, fault-tolerant algorithms, and softwarebased memory fault correction. In this thesis, we examine how rollback avoidance techniques can be used to address failures on extreme-scale systems. Using a combination of analytic modeling and simulation, we evaluate the potential impact of rollback avoidance on these systems. We then present a novel rollback avoidance technique that exploits similarities in application memory. Finally, we examine the feasibility of using this technique to protect against memory faults in kernel memory.« less

HTMT-class Latency Tolerant Parallel Architecture for Petaflops Scale Computation

NASA Technical Reports Server (NTRS)

Sterling, Thomas; Bergman, Larry

2000-01-01

Computational Aero Sciences and other numeric intensive computation disciplines demand computing throughputs substantially greater than the Teraflops scale systems only now becoming available. The related fields of fluids, structures, thermal, combustion, and dynamic controls are among the interdisciplinary areas that in combination with sufficient resolution and advanced adaptive techniques may force performance requirements towards Petaflops. This will be especially true for compute intensive models such as Navier-Stokes are or when such system models are only part of a larger design optimization computation involving many design points. Yet recent experience with conventional MPP configurations comprising commodity processing and memory components has shown that larger scale frequently results in higher programming difficulty and lower system efficiency. While important advances in system software and algorithms techniques have had some impact on efficiency and programmability for certain classes of problems, in general it is unlikely that software alone will resolve the challenges to higher scalability. As in the past, future generations of high-end computers may require a combination of hardware architecture and system software advances to enable efficient operation at a Petaflops level. The NASA led HTMT project has engaged the talents of a broad interdisciplinary team to develop a new strategy in high-end system architecture to deliver petaflops scale computing in the 2004/5 timeframe. The Hybrid-Technology, MultiThreaded parallel computer architecture incorporates several advanced technologies in combination with an innovative dynamic adaptive scheduling mechanism to provide unprecedented performance and efficiency within practical constraints of cost, complexity, and power consumption. The emerging superconductor Rapid Single Flux Quantum electronics can operate at 100 GHz (the record is 770 GHz) and one percent of the power required by convention semiconductor logic. Wave Division Multiplexing optical communications can approach a peak per fiber bandwidth of 1 Tbps and the new Data Vortex network topology employing this technology can connect tens of thousands of ports providing a bi-section bandwidth on the order of a Petabyte per second with latencies well below 100 nanoseconds, even under heavy loads. Processor-in-Memory (PIM) technology combines logic and memory on the same chip exposing the internal bandwidth of the memory row buffers at low latency. And holographic storage photorefractive storage technologies provide high-density memory with access a thousand times faster than conventional disk technologies. Together these technologies enable a new class of shared memory system architecture with a peak performance in the range of a Petaflops but size and power requirements comparable to today's largest Teraflops scale systems. To achieve high-sustained performance, HTMT combines an advanced multithreading processor architecture with a memory-driven coarse-grained latency management strategy called "percolation", yielding high efficiency while reducing the much of the parallel programming burden. This paper will present the basic system architecture characteristics made possible through this series of advanced technologies and then give a detailed description of the new percolation approach to runtime latency management.

Context Effects on Children's Memory of Piagetian Concepts.

ERIC Educational Resources Information Center

King, Mary Ann; Yuille, John C.

This paper is concerned with two questions derived from Piaget and Inhelder's (1973) work on the relationship between memory and the developing intelligence of the child. First, can children retain operatively advanced information through the use of a non-operative mnemonic? Secondly, can the salience of operative versus non-operative information…

Crystallographic and general use programs for the XDS Sigma 5 computer

NASA Technical Reports Server (NTRS)

Snyder, R. L.

1973-01-01

Programs in basic FORTRAN 4 are described, which fall into three catagories: (1) interactive programs to be executed under time sharing (BTM); (2) non interactive programs which are executed in batch processing mode (BPM); and (3) large non interactive programs which require more memory than is available in the normal BPM/BTM operating system and must be run overnight on a special system called XRAY which releases about 45,000 words of memory to the user. Programs in catagories (1) and (2) are stored as FORTRAN source files in the account FSNYDER. Programs in catagory (3) are stored in the XRAY system as load modules. The type of file in account FSNYDER is identified by the first two letters in the name.

GaAs Supercomputing: Architecture, Language, And Algorithms For Image Processing

NASA Astrophysics Data System (ADS)

Johl, John T.; Baker, Nick C.

1988-10-01

The application of high-speed GaAs processors in a parallel system matches the demanding computational requirements of image processing. The architecture of the McDonnell Douglas Astronautics Company (MDAC) vector processor is described along with the algorithms and language translator. Most image and signal processing algorithms can utilize parallel processing and show a significant performance improvement over sequential versions. The parallelization performed by this system is within each vector instruction. Since each vector has many elements, each requiring some computation, useful concurrent arithmetic operations can easily be performed. Balancing the memory bandwidth with the computation rate of the processors is an important design consideration for high efficiency and utilization. The architecture features a bus-based execution unit consisting of four to eight 32-bit GaAs RISC microprocessors running at a 200 MHz clock rate for a peak performance of 1.6 BOPS. The execution unit is connected to a vector memory with three buses capable of transferring two input words and one output word every 10 nsec. The address generators inside the vector memory perform different vector addressing modes and feed the data to the execution unit. The functions discussed in this paper include basic MATRIX OPERATIONS, 2-D SPATIAL CONVOLUTION, HISTOGRAM, and FFT. For each of these algorithms, assembly language programs were run on a behavioral model of the system to obtain performance figures.

Development of land based radar polarimeter processor system

NASA Technical Reports Server (NTRS)

Kronke, C. W.; Blanchard, A. J.

1983-01-01

The processing subsystem of a land based radar polarimeter was designed and constructed. This subsystem is labeled the remote data acquisition and distribution system (RDADS). The radar polarimeter, an experimental remote sensor, incorporates the RDADS to control all operations of the sensor. The RDADS uses industrial standard components including an 8-bit microprocessor based single board computer, analog input/output boards, a dynamic random access memory board, and power supplis. A high-speed digital electronics board was specially designed and constructed to control range-gating for the radar. A complete system of software programs was developed to operate the RDADS. The software uses a powerful real time, multi-tasking, executive package as an operating system. The hardware and software used in the RDADS are detailed. Future system improvements are recommended.

Unified random access memory (URAM) by integration of a nanocrystal floating gate for nonvolatile memory and a partially depleted floating body for capacitorless 1T-DRAM

NASA Astrophysics Data System (ADS)

Ryu, Seong-Wan; Han, Jin-Woo; Kim, Chung-Jin; Kim, Sungho; Choi, Yang-Kyu

2009-03-01

This paper describes a unified memory (URAM) that utilizes a nanocrystal SOI MOSFET for multi-functional applications of both nonvolatile memory (NVM) and capacitorless 1T-DRAM. By using a discrete storage node (Ag nanocrystal) as the floating gate of the NVM, high defect immunity and 2-bit/cell operation were achieved. The embedded nanocrystal NVM also showed 1T-DRAM operation (program/erase time = 100 ns) characteristics, which were realized by storing holes in the floating body of the SOI MOSFET, without requiring an external capacitor. Three-bit/cell operation was accomplished for different applications - 2-bits for nonvolatility and 1-bit for fast operation.

Energy consumption estimation of an OMAP-based Android operating system

NASA Astrophysics Data System (ADS)

González, Gabriel; Juárez, Eduardo; Castro, Juan José; Sanz, César

2011-05-01

System-level energy optimization of battery-powered multimedia embedded systems has recently become a design goal. The poor operational time of multimedia terminals makes computationally demanding applications impractical in real scenarios. For instance, the so-called smart-phones are currently unable to remain in operation longer than several hours. The OMAP3530 processor basically consists of two processing cores, a General Purpose Processor (GPP) and a Digital Signal Processor (DSP). The former, an ARM Cortex-A8 processor, is aimed to run a generic Operating System (OS) while the latter, a DSP core based on the C64x+, has architecture optimized for video processing. The BeagleBoard, a commercial prototyping board based on the OMAP processor, has been used to test the Android Operating System and measure its performance. The board has 128 MB of SDRAM external memory, 256 MB of Flash external memory and several interfaces. Note that the clock frequency of the ARM and DSP OMAP cores is 600 MHz and 430 MHz, respectively. This paper describes the energy consumption estimation of the processes and multimedia applications of an Android v1.6 (Donut) OS on the OMAP3530-Based BeagleBoard. In addition, tools to communicate the two processing cores have been employed. A test-bench to profile the OS resource usage has been developed. As far as the energy estimates concern, the OMAP processor energy consumption model provided by the manufacturer has been used. The model is basically divided in two energy components. The former, the baseline core energy, describes the energy consumption that is independent of any chip activity. The latter, the module active energy, describes the energy consumed by the active modules depending on resource usage.

Practopoiesis: or how life fosters a mind.

PubMed

Nikolić, Danko

2015-05-21

The mind is a biological phenomenon. Thus, biological principles of organization should also be the principles underlying mental operations. Practopoiesis states that the key for achieving intelligence through adaptation is an arrangement in which mechanisms laying at a lower level of organization, by their operations and interaction with the environment, enable creation of mechanisms laying at a higher level of organization. When such an organizational advance of a system occurs, it is called a traverse. A case of traverse is when plasticity mechanisms (at a lower level of organization), by their operations, create a neural network anatomy (at a higher level of organization). Another case is the actual production of behavior by that network, whereby the mechanisms of neuronal activity operate to create motor actions. Practopoietic theory explains why the adaptability of a system increases with each increase in the number of traverses. With a larger number of traverses, a system can be relatively small and yet, produce a higher degree of adaptive/intelligent behavior than a system with a lower number of traverses. The present analyses indicate that the two well-known traverses - neural plasticity and neural activity - are not sufficient to explain human mental capabilities. At least one additional traverse is needed, which is named anapoiesis for its contribution in reconstructing knowledge e.g., from long-term memory into working memory. The conclusions bear implications for brain theory, the mind-body explanatory gap, and developments of artificial intelligence technologies. Copyright © 2015 The Author. Published by Elsevier Ltd.. All rights reserved.

Applications Performance on NAS Intel Paragon XP/S - 15#

NASA Technical Reports Server (NTRS)

Saini, Subhash; Simon, Horst D.; Copper, D. M. (Technical Monitor)

1994-01-01

The Numerical Aerodynamic Simulation (NAS) Systems Division received an Intel Touchstone Sigma prototype model Paragon XP/S- 15 in February, 1993. The i860 XP microprocessor with an integrated floating point unit and operating in dual -instruction mode gives peak performance of 75 million floating point operations (NIFLOPS) per second for 64 bit floating point arithmetic. It is used in the Paragon XP/S-15 which has been installed at NAS, NASA Ames Research Center. The NAS Paragon has 208 nodes and its peak performance is 15.6 GFLOPS. Here, we will report on early experience using the Paragon XP/S- 15. We have tested its performance using both kernels and applications of interest to NAS. We have measured the performance of BLAS 1, 2 and 3 both assembly-coded and Fortran coded on NAS Paragon XP/S- 15. Furthermore, we have investigated the performance of a single node one-dimensional FFT, a distributed two-dimensional FFT and a distributed three-dimensional FFT Finally, we measured the performance of NAS Parallel Benchmarks (NPB) on the Paragon and compare it with the performance obtained on other highly parallel machines, such as CM-5, CRAY T3D, IBM SP I, etc. In particular, we investigated the following issues, which can strongly affect the performance of the Paragon: a. Impact of the operating system: Intel currently uses as a default an operating system OSF/1 AD from the Open Software Foundation. The paging of Open Software Foundation (OSF) server at 22 MB to make more memory available for the application degrades the performance. We found that when the limit of 26 NIB per node out of 32 MB available is reached, the application is paged out of main memory using virtual memory. When the application starts paging, the performance is considerably reduced. We found that dynamic memory allocation can help applications performance under certain circumstances. b. Impact of data cache on the i860/XP: We measured the performance of the BLAS both assembly coded and Fortran coded. We found that the measured performance of assembly-coded BLAS is much less than what memory bandwidth limitation would predict. The influence of data cache on different sizes of vectors is also investigated using one-dimensional FFTs. c. Impact of processor layout: There are several different ways processors can be laid out within the two-dimensional grid of processors on the Paragon. We have used the FFT example to investigate performance differences based on processors layout.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jones, J.P.; Bangs, A.L.; Butler, P.L.

Hetero Helix is a programming environment which simulates shared memory on a heterogeneous network of distributed-memory computers. The machines in the network may vary with respect to their native operating systems and internal representation of numbers. Hetero Helix presents a simple programming model to developers, and also considers the needs of designers, system integrators, and maintainers. The key software technology underlying Hetero Helix is the use of a compiler'' which analyzes the data structures in shared memory and automatically generates code which translates data representations from the format native to each machine into a common format, and vice versa. Themore » design of Hetero Helix was motivated in particular by the requirements of robotics applications. Hetero Helix has been used successfully in an integration effort involving 27 CPUs in a heterogeneous network and a body of software totaling roughly 100,00 lines of code. 25 refs., 6 figs.« less

Fusion PIC code performance analysis on the Cori KNL system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Koskela, Tuomas S.; Deslippe, Jack; Friesen, Brian

We study the attainable performance of Particle-In-Cell codes on the Cori KNL system by analyzing a miniature particle push application based on the fusion PIC code XGC1. We start from the most basic building blocks of a PIC code and build up the complexity to identify the kernels that cost the most in performance and focus optimization efforts there. Particle push kernels operate at high AI and are not likely to be memory bandwidth or even cache bandwidth bound on KNL. Therefore, we see only minor benefits from the high bandwidth memory available on KNL, and achieving good vectorization ismore » shown to be the most beneficial optimization path with theoretical yield of up to 8x speedup on KNL. In practice we are able to obtain up to a 4x gain from vectorization due to limitations set by the data layout and memory latency.« less

Storing and managing information artifacts collected by information analysts using a computing device

DOEpatents

Pike, William A; Riensche, Roderick M; Best, Daniel M; Roberts, Ian E; Whyatt, Marie V; Hart, Michelle L; Carr, Norman J; Thomas, James J

2012-09-18

Systems and computer-implemented processes for storage and management of information artifacts collected by information analysts using a computing device. The processes and systems can capture a sequence of interactive operation elements that are performed by the information analyst, who is collecting an information artifact from at least one of the plurality of software applications. The information artifact can then be stored together with the interactive operation elements as a snippet on a memory device, which is operably connected to the processor. The snippet comprises a view from an analysis application, data contained in the view, and the sequence of interactive operation elements stored as a provenance representation comprising operation element class, timestamp, and data object attributes for each interactive operation element in the sequence.

Detecting Cyber Attacks On Nuclear Power Plants

NASA Astrophysics Data System (ADS)

Rrushi, Julian; Campbell, Roy

This paper proposes an unconventional anomaly detection approach that provides digital instrumentation and control (I&C) systems in a nuclear power plant (NPP) with the capability to probabilistically discern between legitimate protocol frames and attack frames. The stochastic activity network (SAN) formalism is used to model the fusion of protocol activity in each digital I&C system and the operation of physical components of an NPP. SAN models are employed to analyze links between protocol frames as streams of bytes, their semantics in terms of NPP operations, control data as stored in the memory of I&C systems, the operations of I&C systems on NPP components, and NPP processes. Reward rates and impulse rewards are defined in the SAN models based on the activity-marking reward structure to estimate NPP operation profiles. These profiles are then used to probabilistically estimate the legitimacy of the semantics and payloads of protocol frames received by I&C systems.

Precision Pointing in Space Using Arrays of Shape Memory Based Linear Actuators

NASA Astrophysics Data System (ADS)

Sonawane, Nikhil

Space systems such as communication satellites, earth observation satellites and telescope require accurate pointing to observe fixed targets over prolonged time. These systems typically use reaction wheels to slew the spacecraft and gimballing systems containing motors to achieve precise pointing. Motor based actuators have limited life as they contain moving parts that require lubrication in space. Alternate methods have utilized piezoelectric actuators. This paper presents Shape memory alloys (SMA) actuators for control of a deployable antenna placed on a satellite. The SMAs are operated as a series of distributed linear actuators. These distributed linear actuators are not prone to single point failures and although each individual actuator is imprecise due to hysteresis and temperature variation, the system as a whole achieves reliable results. The SMAs can be programmed to perform a series of periodic motion and operate as a mechanical guidance system that is not prone to damage from radiation or space weather. Efforts are focused on developing a system that can achieve 1 degree pointing accuracy at first, with an ultimate goal of achieving a few arc seconds accuracy. Bench top model of the actuator system has been developed and working towards testing the system under vacuum. A demonstration flight of the technology is planned aboard a CubeSat.

SCaLeM: A Framework for Characterizing and Analyzing Execution Models

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chavarría-Miranda, Daniel; Manzano Franco, Joseph B.; Krishnamoorthy, Sriram

2014-10-13

As scalable parallel systems evolve towards more complex nodes with many-core architectures and larger trans-petascale & upcoming exascale deployments, there is a need to understand, characterize and quantify the underlying execution models being used on such systems. Execution models are a conceptual layer between applications & algorithms and the underlying parallel hardware and systems software on which those applications run. This paper presents the SCaLeM (Synchronization, Concurrency, Locality, Memory) framework for characterizing and execution models. SCaLeM consists of three basic elements: attributes, compositions and mapping of these compositions to abstract parallel systems. The fundamental Synchronization, Concurrency, Locality and Memory attributesmore » are used to characterize each execution model, while the combinations of those attributes in the form of compositions are used to describe the primitive operations of the execution model. The mapping of the execution model’s primitive operations described by compositions, to an underlying abstract parallel system can be evaluated quantitatively to determine its effectiveness. Finally, SCaLeM also enables the representation and analysis of applications in terms of execution models, for the purpose of evaluating the effectiveness of such mapping.« less

A keyboard control method for loop measurement

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, Z.W.

1994-12-31

This paper describes a keyboard control mode based on the DEC VAX computer. The VAX Keyboard code can be found under running of a program was developed. During the loop measurement or multitask operation, it ables to be distinguished from a keyboard code to stop current operation or transfer to another operation while previous information can be held. The combining of this mode, the author successfully used one key control loop measurement for test Dual Input Memory module which is used in a rearrange Energy Trigger system for LEP 8 Bunch operation.

Neural network based system for equipment surveillance

DOEpatents

Vilim, Richard B.; Gross, Kenneth C.; Wegerich, Stephan W.

1998-01-01

A method and system for performing surveillance of transient signals of an industrial device to ascertain the operating state. The method and system involves the steps of reading into a memory training data, determining neural network weighting values until achieving target outputs close to the neural network output. If the target outputs are inadequate, wavelet parameters are determined to yield neural network outputs close to the desired set of target outputs and then providing signals characteristic of an industrial process and comparing the neural network output to the industrial process signals to evaluate the operating state of the industrial process.

Neural network based system for equipment surveillance

DOEpatents

Vilim, R.B.; Gross, K.C.; Wegerich, S.W.

1998-04-28

A method and system are disclosed for performing surveillance of transient signals of an industrial device to ascertain the operating state. The method and system involves the steps of reading into a memory training data, determining neural network weighting values until achieving target outputs close to the neural network output. If the target outputs are inadequate, wavelet parameters are determined to yield neural network outputs close to the desired set of target outputs and then providing signals characteristic of an industrial process and comparing the neural network output to the industrial process signals to evaluate the operating state of the industrial process. 33 figs.

PKG-Mediated MAPK Signaling Is Necessary for Long-Term Operant Memory in "Aplysia"

ERIC Educational Resources Information Center

Michel, Maximilian; Green, Charity L.; Eskin, Arnold; Lyons, Lisa C.

2011-01-01

Signaling pathways necessary for memory formation, such as the mitogen-activated protein kinase (MAPK) pathway, appear highly conserved across species and paradigms. Learning that food is inedible (LFI) represents a robust form of associative, operant learning that induces short- (STM) and long-term memory (LTM) in "Aplysia." We investigated the…

Operation mode switchable charge-trap memory based on few-layer MoS2

NASA Astrophysics Data System (ADS)

Hou, Xiang; Yan, Xiao; Liu, Chunsen; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-03-01

Ultrathin layered two-dimensional (2D) semiconductors like MoS2 and WSe2 have received a lot of attention because of their excellent electrical properties and potential applications in electronic devices. We demonstrate a charge-trap memory with two different tunable operation modes based on a few-layer MoS2 channel and an Al2O3/HfO2/Al2O3 charge storage stack. Our device shows excellent memory properties under the traditional three-terminal operation mode. More importantly, unlike conventional charge-trap devices, this device can also realize the memory performance with just two terminals (drain and source) because of the unique atomic crystal electrical characteristics. Under the two-terminal operation mode, the erase/program current ratio can reach up to 104 with a stable retention property. Our study indicates that the conventional charge-trap memory cell can also realize the memory performance without the gate terminal based on novel two dimensional materials, which is meaningful for low power consumption and high integration density applications.

Modeling and simulation of floating gate nanocrystal FET devices and circuits

NASA Astrophysics Data System (ADS)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to nanocrystal charge has a strong effect on the memory characteristics. Also, the programming operation of the memory cell has been investigated. The tunneling rate from quantum well channel to quantum dot (nanocrystal) gate is calculated. The calculations include various memory parameters, wavefunctions, and energies of quantum well channel and quantum dot gate. The use of floating gate nanocrystal memory as a transistor with a programmable threshold voltage has been demonstrated. The incorporation of FG-NCFETs to design programmable integrated circuit building blocks has been discussed. This includes the design of programmable current and voltage reference circuits. Finally, we demonstrated the design of tunable gain op-amp incorporating FG-NCFETs. Programmable integrated circuit building blocks can be used in intelligent analog and digital systems.

Host-Based Systemic Network Obfuscation System for Windows

DTIC Science & Technology

2011-06-01

speed, CPU speed, and memory size. These additional parameters are control variables and do not change throughout the experiment. The applications...physical median that passes the network traffic, such as a wireless signal or Ethernet cable and does not need obfuscation. The colored layers in Figure...Gul09] Ron Gula, “ Enchanced Operating System Identification with Nessus.” [Online]. Available: http://blog.tenablesecurity.com/2009/02

Multicore Architecture-aware Scientific Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Srinivasa, Avinash

Modern high performance systems are becoming increasingly complex and powerful due to advancements in processor and memory architecture. In order to keep up with this increasing complexity, applications have to be augmented with certain capabilities to fully exploit such systems. These may be at the application level, such as static or dynamic adaptations or at the system level, like having strategies in place to override some of the default operating system polices, the main objective being to improve computational performance of the application. The current work proposes two such capabilites with respect to multi-threaded scientific applications, in particular a largemore » scale physics application computing ab-initio nuclear structure. The first involves using a middleware tool to invoke dynamic adaptations in the application, so as to be able to adjust to the changing computational resource availability at run-time. The second involves a strategy for effective placement of data in main memory, to optimize memory access latencies and bandwidth. These capabilties when included were found to have a significant impact on the application performance, resulting in average speedups of as much as two to four times.« less

78 FR 9587 - Drawbridge Operation Regulation; Cape Fear River, Wilmington, NC

Federal Register 2010, 2011, 2012, 2013, 2014

2013-02-11

... Operation Regulation; Cape Fear River, Wilmington, NC AGENCY: Coast Guard, DHS. ACTION: Notice of deviation... operating schedule that governs the operation of the Cape Fear River Memorial Bridge, across the Cape Fear.... The Cape Fear River Memorial Bridge, at mile 26.8, at Wilmington, NC, has vertical clearances in the...

System reliability, performance and trust in adaptable automation.

PubMed

Chavaillaz, Alain; Wastell, David; Sauer, Jürgen

2016-01-01

The present study examined the effects of reduced system reliability on operator performance and automation management in an adaptable automation environment. 39 operators were randomly assigned to one of three experimental groups: low (60%), medium (80%), and high (100%) reliability of automation support. The support system provided five incremental levels of automation which operators could freely select according to their needs. After 3 h of training on a simulated process control task (AutoCAMS) in which the automation worked infallibly, operator performance and automation management were measured during a 2.5-h testing session. Trust and workload were also assessed through questionnaires. Results showed that although reduced system reliability resulted in lower levels of trust towards automation, there were no corresponding differences in the operators' reliance on automation. While operators showed overall a noteworthy ability to cope with automation failure, there were, however, decrements in diagnostic speed and prospective memory with lower reliability. Copyright © 2015. Published by Elsevier Ltd.

Machine vision for real time orbital operations

NASA Technical Reports Server (NTRS)

Vinz, Frank L.

1988-01-01

Machine vision for automation and robotic operation of Space Station era systems has the potential for increasing the efficiency of orbital servicing, repair, assembly and docking tasks. A machine vision research project is described in which a TV camera is used for inputing visual data to a computer so that image processing may be achieved for real time control of these orbital operations. A technique has resulted from this research which reduces computer memory requirements and greatly increases typical computational speed such that it has the potential for development into a real time orbital machine vision system. This technique is called AI BOSS (Analysis of Images by Box Scan and Syntax).

Mathematical Logic in the Human Brain: Semantics

PubMed Central

Friedrich, Roland M.; Friederici, Angela D.

2013-01-01

As a higher cognitive function in humans, mathematics is supported by parietal and prefrontal brain regions. Here, we give an integrative account of the role of the different brain systems in processing the semantics of mathematical logic from the perspective of macroscopic polysynaptic networks. By comparing algebraic and arithmetic expressions of identical underlying structure, we show how the different subparts of a fronto-parietal network are modulated by the semantic domain, over which the mathematical formulae are interpreted. Within this network, the prefrontal cortex represents a system that hosts three major components, namely, control, arithmetic-logic, and short-term memory. This prefrontal system operates on data fed to it by two other systems: a premotor-parietal top-down system that updates and transforms (external) data into an internal format, and a hippocampal bottom-up system that either detects novel information or serves as an access device to memory for previously acquired knowledge. PMID:23301101

Mathematical logic in the human brain: semantics.

PubMed

Friedrich, Roland M; Friederici, Angela D

2013-01-01

As a higher cognitive function in humans, mathematics is supported by parietal and prefrontal brain regions. Here, we give an integrative account of the role of the different brain systems in processing the semantics of mathematical logic from the perspective of macroscopic polysynaptic networks. By comparing algebraic and arithmetic expressions of identical underlying structure, we show how the different subparts of a fronto-parietal network are modulated by the semantic domain, over which the mathematical formulae are interpreted. Within this network, the prefrontal cortex represents a system that hosts three major components, namely, control, arithmetic-logic, and short-term memory. This prefrontal system operates on data fed to it by two other systems: a premotor-parietal top-down system that updates and transforms (external) data into an internal format, and a hippocampal bottom-up system that either detects novel information or serves as an access device to memory for previously acquired knowledge.

Simulation of n-qubit quantum systems. III. Quantum operations

NASA Astrophysics Data System (ADS)

Radtke, T.; Fritzsche, S.

2007-05-01

During the last decade, several quantum information protocols, such as quantum key distribution, teleportation or quantum computation, have attracted a lot of interest. Despite the recent success and research efforts in quantum information processing, however, we are just at the beginning of understanding the role of entanglement and the behavior of quantum systems in noisy environments, i.e. for nonideal implementations. Therefore, in order to facilitate the investigation of entanglement and decoherence in n-qubit quantum registers, here we present a revised version of the FEYNMAN program for working with quantum operations and their associated (Jamiołkowski) dual states. Based on the implementation of several popular decoherence models, we provide tools especially for the quantitative analysis of quantum operations. Apart from the implementation of different noise models, the current program extension may help investigate the fragility of many quantum states, one of the main obstacles in realizing quantum information protocols today. Program summaryTitle of program: Feynman Catalogue identifier: ADWE_v3_0 Program summary URL:http://cpc.cs.qub.ac.uk/summaries/ADWE_v3_0 Program obtainable from: CPC Program Library, Queen's University of Belfast, N. Ireland Licensing provisions: None Operating systems: Any system that supports MAPLE; tested under Microsoft Windows XP, SuSe Linux 10 Program language used:MAPLE 10 Typical time and memory requirements: Most commands that act upon quantum registers with five or less qubits take ⩽10 seconds of processor time (on a Pentium 4 processor with ⩾2 GHz or equivalent) and 5-20 MB of memory. Especially when working with symbolic expressions, however, the memory and time requirements critically depend on the number of qubits in the quantum registers, owing to the exponential dimension growth of the associated Hilbert space. For example, complex (symbolic) noise models (with several Kraus operators) for multi-qubit systems often result in very large symbolic expressions that dramatically slow down the evaluation of measures or other quantities. In these cases, MAPLE's assume facility sometimes helps to reduce the complexity of symbolic expressions, but often only numerical evaluation is possible. Since the complexity of the FEYNMAN commands is very different, no general scaling law for the CPU time and memory usage can be given. No. of bytes in distributed program including test data, etc.: 799 265 No. of lines in distributed program including test data, etc.: 18 589 Distribution format: tar.gz Reasons for new version: While the previous program versions were designed mainly to create and manipulate the state of quantum registers, the present extension aims to support quantum operations as the essential ingredient for studying the effects of noisy environments. Does this version supersede the previous version: Yes Nature of the physical problem: Today, entanglement is identified as the essential resource in virtually all aspects of quantum information theory. In most practical implementations of quantum information protocols, however, decoherence typically limits the lifetime of entanglement. It is therefore necessary and highly desirable to understand the evolution of entanglement in noisy environments. Method of solution: Using the computer algebra system MAPLE, we have developed a set of procedures that support the definition and manipulation of n-qubit quantum registers as well as (unitary) logic gates and (nonunitary) quantum operations that act on the quantum registers. The provided hierarchy of commands can be used interactively in order to simulate and analyze the evolution of n-qubit quantum systems in ideal and nonideal quantum circuits.

Compact Holographic Data Storage

NASA Technical Reports Server (NTRS)

Chao, T. H.; Reyes, G. F.; Zhou, H.

2001-01-01

NASA's future missions would require massive high-speed onboard data storage capability to Space Science missions. For Space Science, such as the Europa Lander mission, the onboard data storage requirements would be focused on maximizing the spacecraft's ability to survive fault conditions (i.e., no loss in stored science data when spacecraft enters the 'safe mode') and autonomously recover from them during NASA's long-life and deep space missions. This would require the development of non-volatile memory. In order to survive in the stringent environment during space exploration missions, onboard memory requirements would also include: (1) survive a high radiation environment (1 Mrad), (2) operate effectively and efficiently for a very long time (10 years), and (3) sustain at least a billion write cycles. Therefore, memory technologies requirements of NASA's Earth Science and Space Science missions are large capacity, non-volatility, high-transfer rate, high radiation resistance, high storage density, and high power efficiency. JPL, under current sponsorship from NASA Space Science and Earth Science Programs, is developing a high-density, nonvolatile and rad-hard Compact Holographic Data Storage (CHDS) system to enable large-capacity, high-speed, low power consumption, and read/write of data in a space environment. The entire read/write operation will be controlled with electrooptic mechanism without any moving parts. This CHDS will consist of laser diodes, photorefractive crystal, spatial light modulator, photodetector array, and I/O electronic interface. In operation, pages of information would be recorded and retrieved with random access and high-speed. The nonvolatile, rad-hard characteristics of the holographic memory will provide a revolutionary memory technology meeting the high radiation challenge facing the Europa Lander mission. Additional information is contained in the original extended abstract.

Computations in the deep vs superficial layers of the cerebral cortex.

PubMed

Rolls, Edmund T; Mills, W Patrick C

2017-11-01

A fundamental question is how the cerebral neocortex operates functionally, computationally. The cerebral neocortex with its superficial and deep layers and highly developed recurrent collateral systems that provide a basis for memory-related processing might perform somewhat different computations in the superficial and deep layers. Here we take into account the quantitative connectivity within and between laminae. Using integrate-and-fire neuronal network simulations that incorporate this connectivity, we first show that attractor networks implemented in the deep layers that are activated by the superficial layers could be partly independent in that the deep layers might have a different time course, which might because of adaptation be more transient and useful for outputs from the neocortex. In contrast the superficial layers could implement more prolonged firing, useful for slow learning and for short-term memory. Second, we show that a different type of computation could in principle be performed in the superficial and deep layers, by showing that the superficial layers could operate as a discrete attractor network useful for categorisation and feeding information forward up a cortical hierarchy, whereas the deep layers could operate as a continuous attractor network useful for providing a spatially and temporally smooth output to output systems in the brain. A key advance is that we draw attention to the functions of the recurrent collateral connections between cortical pyramidal cells, often omitted in canonical models of the neocortex, and address principles of operation of the neocortex by which the superficial and deep layers might be specialized for different types of attractor-related memory functions implemented by the recurrent collaterals. Copyright © 2017 Elsevier Inc. All rights reserved.

Memory for Details with Self-Referencing

PubMed Central

Serbun, Sarah J.; Shih, Joanne Y.; Gutchess, Angela H.

2011-01-01

Self-referencing benefits item memory, but little is known about the ways in which referencing the self affects memory for details. Experiment 1 assessed whether the effects of self-referencing operate only at the item, or general, level or also enhance memory for specific visual details of objects. Participants incidentally encoded objects by making judgments in reference to the self, a close other (one’s mother), or a familiar other (Bill Clinton). Results indicate that referencing the self or a close other enhances both specific and general memory. Experiments 2 and 3 assessed verbal memory for source in a task that relied on distinguishing between different mental operations (internal sources). Results indicate that self-referencing disproportionately enhances source memory, relative to conditions referencing other people, semantic, or perceptual information. We conclude that self-referencing not only enhances specific memory for both visual and verbal information, but can disproportionately improve memory for specific internal source details as well. PMID:22092106

Memory for details with self-referencing.

PubMed

Serbun, Sarah J; Shih, Joanne Y; Gutchess, Angela H

2011-11-01

Self-referencing benefits item memory, but little is known about the ways in which referencing the self affects memory for details. Experiment 1 assessed whether the effects of self-referencing operate only at the item, or general, level or whether they also enhance memory for specific visual details of objects. Participants incidentally encoded objects by making judgements in reference to the self, a close other (one's mother), or a familiar other (Bill Clinton). Results indicate that referencing the self or a close other enhances both specific and general memory. Experiments 2 and 3 assessed verbal memory for source in a task that relied on distinguishing between different mental operations (internal sources). The results indicate that self-referencing disproportionately enhances source memory, relative to conditions referencing other people, semantic, or perceptual information. We conclude that self-referencing not only enhances specific memory for both visual and verbal information, but can also disproportionately improve memory for specific internal source details.

The Impact of Software Structure and Policy on CPU and Memory System Performance

DTIC Science & Technology

1994-05-01

Mach 3.0 is that Ultrix is a monolithic or integrated system, and Mach 3.0 is a microkernel or kernelized system. In a monolithic system, all system...services are implemented in a single system context, the monolithic kernel . In a microkernel system such as Mach 3.0, primitive abstractions such as...separate protection domain as a server. Many current operating system text books discuss microkernel and monolithic kernel design. (See [17, 73, 77].) The

Epidemic failure detection and consensus for extreme parallelism

DOE PAGES

Katti, Amogh; Di Fatta, Giuseppe; Naughton, Thomas; ...

2017-02-01

Future extreme-scale high-performance computing systems will be required to work under frequent component failures. The MPI Forum s User Level Failure Mitigation proposal has introduced an operation, MPI Comm shrink, to synchronize the alive processes on the list of failed processes, so that applications can continue to execute even in the presence of failures by adopting algorithm-based fault tolerance techniques. This MPI Comm shrink operation requires a failure detection and consensus algorithm. This paper presents three novel failure detection and consensus algorithms using Gossiping. The proposed algorithms were implemented and tested using the Extreme-scale Simulator. The results show that inmore » all algorithms the number of Gossip cycles to achieve global consensus scales logarithmically with system size. The second algorithm also shows better scalability in terms of memory and network bandwidth usage and a perfect synchronization in achieving global consensus. The third approach is a three-phase distributed failure detection and consensus algorithm and provides consistency guarantees even in very large and extreme-scale systems while at the same time being memory and bandwidth efficient.« less

Reduced-Density-Matrix Description of Decoherence and Relaxation Processes for Electron-Spin Systems

NASA Astrophysics Data System (ADS)

Jacobs, Verne

2017-04-01

Electron-spin systems are investigated using a reduced-density-matrix description. Applications of interest include trapped atomic systems in optical lattices, semiconductor quantum dots, and vacancy defect centers in solids. Complimentary time-domain (equation-of-motion) and frequency-domain (resolvent-operator) formulations are self-consistently developed. The general non-perturbative and non-Markovian formulations provide a fundamental framework for systematic evaluations of corrections to the standard Born (lowest-order-perturbation) and Markov (short-memory-time) approximations. Particular attention is given to decoherence and relaxation processes, as well as spectral-line broadening phenomena, that are induced by interactions with photons, phonons, nuclear spins, and external electric and magnetic fields. These processes are treated either as coherent interactions or as environmental interactions. The environmental interactions are incorporated by means of the general expressions derived for the time-domain and frequency-domain Liouville-space self-energy operators, for which the tetradic-matrix elements are explicitly evaluated in the diagonal-resolvent, lowest-order, and Markov (short-memory time) approximations. Work supported by the Office of Naval Research through the Basic Research Program at The Naval Research Laboratory.

Observation of quantum-memory-assisted entropic uncertainty relation under open systems, and its steering

NASA Astrophysics Data System (ADS)

Chen, Peng-Fei; Sun, Wen-Yang; Ming, Fei; Huang, Ai-Jun; Wang, Dong; Ye, Liu

2018-01-01

Quantum objects are susceptible to noise from their surrounding environments, interaction with which inevitably gives rise to quantum decoherence or dissipation effects. In this work, we examine how different types of local noise under an open system affect entropic uncertainty relations for two incompatible measurements. Explicitly, we observe the dynamics of the entropic uncertainty in the presence of quantum memory under two canonical categories of noisy environments: unital (phase flip) and nonunital (amplitude damping). Our study shows that the measurement uncertainty exhibits a non-monotonic dynamical behavior—that is, the amount of the uncertainty will first inflate, and subsequently decrease, with the growth of decoherence strengths in the two channels. In contrast, the uncertainty decreases monotonically with the growth of the purity of the initial state shared in prior. In order to reduce the measurement uncertainty in noisy environments, we put forward a remarkably effective strategy to steer the magnitude of uncertainty by means of a local non-unitary operation (i.e. weak measurement) on the qubit of interest. It turns out that this non-unitary operation can greatly reduce the entropic uncertainty, upon tuning the operation strength. Our investigations might thereby offer an insight into the dynamics and steering of entropic uncertainty in open systems.

Progress towards broadband Raman quantum memory in Bose-Einstein condensates

NASA Astrophysics Data System (ADS)

Saglamyurek, Erhan; Hrushevskyi, Taras; Smith, Benjamin; Leblanc, Lindsay

2017-04-01

Optical quantum memories are building blocks for quantum information technologies. Efficient and long-lived storage in combination with high-speed (broadband) operation are key features required for practical applications. While the realization has been a great challenge, Raman memory in Bose-Einstein condensates (BECs) is a promising approach, due to negligible decoherence from diffusion and collisions that leads to seconds-scale memory times, high efficiency due to large atomic density, the possibility for atom-chip integration with micro photonics, and the suitability of the far off-resonant Raman approach with storage of broadband photons (over GHz) [5]. Here we report our progress towards Raman memory in a BEC. We describe our apparatus recently built for producing BEC with 87Rb atoms, and present the observation of nearly pure BEC with 5x105 atoms at 40 nK. After showing our initial characterizations, we discuss the suitability of our system for Raman-based light storage in our BEC.

Sentinel 2 MMFU: The first European Mass Memory System Based on NAND-Flash Storage Technology

NASA Astrophysics Data System (ADS)

Staehle, M.; Cassel, M.; Lonsdorfer, U.; Gliem, F.; Walter, D.; Fichna, T.

2011-08-01

Sentinel-2 is the multispectral optical mission of the EU-ESA GMES (Global Monitoring for Environment and Security) program, currently under development by Astrium-GmbH in Friedrichshafen (Germany) for a launch in 2013. The mission features a 490 Mbit/s optical sensor operating at high duty cycles, requiring in turn a large 2.4 Tbit on-board storage capacity.The required storage capacity motivated the selection of the NAND-Flash technology which was already secured by a lengthy period (2004-2009) of detailed testing, analysis and qualification by Astrium GmbH, IDA and ESTEC. The mass memory system is currently being realized by Astrium GmbH.

Systems and methods to control multiple peripherals with a single-peripheral application code

DOEpatents

Ransom, Ray M.

2013-06-11

Methods and apparatus are provided for enhancing the BIOS of a hardware peripheral device to manage multiple peripheral devices simultaneously without modifying the application software of the peripheral device. The apparatus comprises a logic control unit and a memory in communication with the logic control unit. The memory is partitioned into a plurality of ranges, each range comprising one or more blocks of memory, one range being associated with each instance of the peripheral application and one range being reserved for storage of a data pointer related to each peripheral application of the plurality. The logic control unit is configured to operate multiple instances of the control application by duplicating one instance of the peripheral application for each peripheral device of the plurality and partitioning a memory device into partitions comprising one or more blocks of memory, one partition being associated with each instance of the peripheral application. The method then reserves a range of memory addresses for storage of a data pointer related to each peripheral device of the plurality, and initializes each of the plurality of peripheral devices.

Contexts and Control Operations Used in Accessing List-Specific, Generalized, and Semantic Memories

ERIC Educational Resources Information Center

Humphreys, Michael S.; Murray, Krista L.; Maguire, Angela M.

2009-01-01

The human ability to focus memory retrieval operations on a particular list, episode or memory structure has not been fully appreciated or documented. In Experiment 1-3, we make it increasingly difficult for participants to switch between a less recent list (multiple study opportunities), and a more recent list (single study opportunity). Task…

Deployment of 802.15.4 Sensor Networks for C4ISR Operations

DTIC Science & Technology

2006-06-01

43 Figure 20.MSP410CA Dense Grid Monitoring (Crossbow User’s Manual, 2005). ....................................44 Figure 21.(a)MICA2 without...Deployment of Sensor Grid (COASTS OPORD, 2006). ...56 Figure 27.Topology View of Two Nodes and Base Station .......57 Figure 28.Nodes Employing Multi...Random Access Memory TCP/IP Transmission Control Protocol/Internet Protocol TinyOS Tiny Micro Threading Operating System UARTs Universal

A MATLAB/Simulink based GUI for the CERES Simulator

NASA Technical Reports Server (NTRS)

Valencia, Luis H.

1995-01-01

The Clouds and The Earth's Radiant Energy System (CERES) simulator will allow flight operational familiarity with the CERES instrument prior to launch. It will provide a CERES instrument simulation facility for NASA Langley Research Center. NASA Goddard Space Flight Center and TRW. One of the objectives of building this simulator would be for use as a testbed for functionality checking of atypical memory uploads and for anomaly investigation. For instance, instrument malfunction due to memory damage requires troubleshooting on a simulator to determine the nature of the problem and to find a solution.

Work and information processing in a solvable model of Maxwell's demon.

PubMed

Mandal, Dibyendu; Jarzynski, Christopher

2012-07-17

We describe a minimal model of an autonomous Maxwell demon, a device that delivers work by rectifying thermal fluctuations while simultaneously writing information to a memory register. We solve exactly for the steady-state behavior of our model, and we construct its phase diagram. We find that our device can also act as a "Landauer eraser", using externally supplied work to remove information from the memory register. By exposing an explicit, transparent mechanism of operation, our model offers a simple paradigm for investigating the thermodynamics of information processing by small systems.

1/f Noise in Bak-Tang-Wiesenfeld Models on Narrow Stripes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maslov, S.; Tang, C.; Zhang, Y.

We report our findings of a 1/f power spectrum for the total amount of sand in directed and undirected Bak-Tang-Wiesenfeld models confined to narrow stripes and driven locally. The underlying mechanism for the 1/f noise in these systems is an exponentially long configuration memory giving rise to a very broad distribution of time scales. Both models are solved analytically with the help of an operator algebra to explicitly show the appearance of the long configuration memory. {copyright} {ital 1999} {ital The American Physical Society}

Content-addressable read/write memories for image analysis

NASA Technical Reports Server (NTRS)

Snyder, W. E.; Savage, C. D.

1982-01-01

The commonly encountered image analysis problems of region labeling and clustering are found to be cases of search-and-rename problem which can be solved in parallel by a system architecture that is inherently suitable for VLSI implementation. This architecture is a novel form of content-addressable memory (CAM) which provides parallel search and update functions, allowing speed reductions down to constant time per operation. It has been proposed in related investigations by Hall (1981) that, with VLSI, CAM-based structures with enhanced instruction sets for general purpose processing will be feasible.

Implementing a High-Assurance Smart-Card OS

NASA Astrophysics Data System (ADS)

Karger, Paul A.; Toll, David C.; Palmer, Elaine R.; McIntosh, Suzanne K.; Weber, Samuel; Edwards, Jonathan W.

Building a high-assurance, secure operating system for memory constrained systems, such as smart cards, introduces many challenges. The increasing power of smart cards has made their use feasible in applications such as electronic passports, military and public sector identification cards, and cell-phone based financial and entertainment applications. Such applications require a secure environment, which can only be provided with sufficient hardware and a secure operating system. We argue that smart cards pose additional security challenges when compared to traditional computer platforms. We discuss our design for a secure smart card operating system, named Caernarvon, and show that it addresses these challenges, which include secure application download, protection of cryptographic functions from malicious applications, resolution of covert channels, and assurance of both security and data integrity in the face of arbitrary power losses.

Configurable unitary transformations and linear logic gates using quantum memories.

PubMed

Campbell, G T; Pinel, O; Hosseini, M; Ralph, T C; Buchler, B C; Lam, P K

2014-08-08

We show that a set of optical memories can act as a configurable linear optical network operating on frequency-multiplexed optical states. Our protocol is applicable to any quantum memories that employ off-resonant Raman transitions to store optical information in atomic spins. In addition to the configurability, the protocol also offers favorable scaling with an increasing number of modes where N memories can be configured to implement arbitrary N-mode unitary operations during storage and readout. We demonstrate the versatility of this protocol by showing an example where cascaded memories are used to implement a conditional cz gate.

The correlational research among serum CXCL13 levels, circulating plasmablasts and memory B cells in patients with systemic lupus erythematosus: A STROBE-compliant article.

PubMed

Fang, Chenglong; Luo, Tingting; Lin, Ling

2017-12-01

We investigated whether serum CXC ligand 13 protein (CXCL13) levels correlate with the circulating plasmablasts and memory B-cells alteration in systemic lupus erythematosus (SLE) patients. The diagnostic use of CXCL13 concentrations in active lupus was also analyzed.A total of 36 SLE patients and 18 healthy controls were included. Serum CXCL13 levels were examined by enzyme-linked immunosorbent assay. The frequency and absolute count of circulating plasmablasts and memory B cells were analyzed by flow cytometry. Receiver operating characteristic curves (ROC curves) were generated to analyze the utility of serum CXCL13 level and plasmablasts frequency as tools for the recognition of active SLE.Elevation of serum CXCL13 levels, higher plasmablasts frequency, and reduction of memory B-cells count were observed in SLE patients, compared with healthy controls. Interestingly, correlational analyses showed not only significantly positive association between CXCL13 levels and SLE Disease Activity Index (SLEDAI) or plasmablasts frequency, but an inverse correlation between CXCL13 concentration and memory B-cell count. ROC curves showed that serum CXCL13 level and plasmablasts frequency were practical in identifying active disease from overall SLE patients, with considerable accuracy.Serum CXCL13 levels correlate with the alteration of plasmablasts and memory B cells in SLE. CXCL13 may be used as a practical tool in judgment of active SLE.

Operating characteristics of the implicit learning system supporting serial interception sequence learning.

PubMed

Sanchez, Daniel J; Reber, Paul J

2012-04-01

The memory system that supports implicit perceptual-motor sequence learning relies on brain regions that operate separately from the explicit, medial temporal lobe memory system. The implicit learning system therefore likely has distinct operating characteristics and information processing constraints. To attempt to identify the limits of the implicit sequence learning mechanism, participants performed the serial interception sequence learning (SISL) task with covertly embedded repeating sequences that were much longer than most previous studies: ranging from 30 to 60 (Experiment 1) and 60 to 90 (Experiment 2) items in length. Robust sequence-specific learning was observed for sequences up to 80 items in length, extending the known capacity of implicit sequence learning. In Experiment 3, 12-item repeating sequences were embedded among increasing amounts of irrelevant nonrepeating sequences (from 20 to 80% of training trials). Despite high levels of irrelevant trials, learning occurred across conditions. A comparison of learning rates across all three experiments found a surprising degree of constancy in the rate of learning regardless of sequence length or embedded noise. Sequence learning appears to be constant with the logarithm of the number of sequence repetitions practiced during training. The consistency in learning rate across experiments and conditions implies that the mechanisms supporting implicit sequence learning are not capacity-constrained by very long sequences nor adversely affected by high rates of irrelevant sequences during training.

PLAT: An Automated Fault and Behavioural Anomaly Detection Tool for PLC Controlled Manufacturing Systems.

PubMed

Ghosh, Arup; Qin, Shiming; Lee, Jooyeoun; Wang, Gi-Nam

2016-01-01

Operational faults and behavioural anomalies associated with PLC control processes take place often in a manufacturing system. Real time identification of these operational faults and behavioural anomalies is necessary in the manufacturing industry. In this paper, we present an automated tool, called PLC Log-Data Analysis Tool (PLAT) that can detect them by using log-data records of the PLC signals. PLAT automatically creates a nominal model of the PLC control process and employs a novel hash table based indexing and searching scheme to satisfy those purposes. Our experiments show that PLAT is significantly fast, provides real time identification of operational faults and behavioural anomalies, and can execute within a small memory footprint. In addition, PLAT can easily handle a large manufacturing system with a reasonable computing configuration and can be installed in parallel to the data logging system to identify operational faults and behavioural anomalies effectively.

PLAT: An Automated Fault and Behavioural Anomaly Detection Tool for PLC Controlled Manufacturing Systems

PubMed Central

Ghosh, Arup; Qin, Shiming; Lee, Jooyeoun

2016-01-01

Operational faults and behavioural anomalies associated with PLC control processes take place often in a manufacturing system. Real time identification of these operational faults and behavioural anomalies is necessary in the manufacturing industry. In this paper, we present an automated tool, called PLC Log-Data Analysis Tool (PLAT) that can detect them by using log-data records of the PLC signals. PLAT automatically creates a nominal model of the PLC control process and employs a novel hash table based indexing and searching scheme to satisfy those purposes. Our experiments show that PLAT is significantly fast, provides real time identification of operational faults and behavioural anomalies, and can execute within a small memory footprint. In addition, PLAT can easily handle a large manufacturing system with a reasonable computing configuration and can be installed in parallel to the data logging system to identify operational faults and behavioural anomalies effectively. PMID:27974882

AEP Ohio gridSMART Demonstration Project Real-Time Pricing Demonstration Analysis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Widergren, Steven E.; Subbarao, Krishnappa; Fuller, Jason C.

2014-02-01

This report contributes initial findings from an analysis of significant aspects of the gridSMART® Real-Time Pricing (RTP) – Double Auction demonstration project. Over the course of four years, Pacific Northwest National Laboratory (PNNL) worked with American Electric Power (AEP), Ohio and Battelle Memorial Institute to design, build, and operate an innovative system to engage residential consumers and their end-use resources in a participatory approach to electric system operations, an incentive-based approach that has the promise of providing greater efficiency under normal operating conditions and greater flexibility to react under situations of system stress. The material contained in this report supplementsmore » the findings documented by AEP Ohio in the main body of the gridSMART report. It delves into three main areas: impacts on system operations, impacts on households, and observations about the sensitivity of load to price changes.« less

Electrophysiological Repetition Effects in Persons with Mild Cognitive Impairment depend upon Working Memory Demand.

PubMed

Broster, Lucas S; Jenkins, Shonna L; Holmes, Sarah D; Edwards, Matthew G; Jicha, Gregory A; Jiang, Yang

2018-05-07

Forms of implicit memory, including repetition effects, are preserved relative to explicit memory in clinical Alzheimer's disease. Consequently, cognitive interventions for persons with Alzheimer's disease have been developed that leverage this fact. However, despite the clinical robustness of behavioral repetition effects, altered neural mechanisms of repetition effects are studied as biomarkers of both clinical Alzheimer's disease and pre-morbid Alzheimer's changes in the brain. We hypothesized that the clinical preservation of behavioral repetition effects results in part from concurrent operation of discrete memory systems. We developed two experiments that included probes of emotional repetition effects differing in that one included an embedded working memory task. We found that neural repetition effects manifested in patients with amnestic mild cognitive impairment, the earliest form of clinical Alzheimer's disease, during emotional working memory tasks, but they did not manifest during the task that lacked the embedded working memory manipulation. Specifically, the working memory task evoked neural repetition effects in the P600 time-window, but the same neural mechanism was only minimally implicated in the task without a working memory component. We also found that group differences in behavioral repetition effects were smaller in the experiment with a working memory task. We suggest that cross-domain cognitive challenge can expose "defunct" neural capabilities of individuals with amnestic mild cognitive impairment. Copyright © 2018. Published by Elsevier Ltd.

Rapid prototyping prosthetic hand acting by a low-cost shape-memory-alloy actuator.

PubMed

Soriano-Heras, Enrique; Blaya-Haro, Fernando; Molino, Carlos; de Agustín Del Burgo, José María

2018-06-01

The purpose of this article is to develop a new concept of modular and operative prosthetic hand based on rapid prototyping and a novel shape-memory-alloy (SMA) actuator, thus minimizing the manufacturing costs. An underactuated mechanism was needed for the design of the prosthesis to use only one input source. Taking into account the state of the art, an underactuated mechanism prosthetic hand was chosen so as to implement the modifications required for including the external SMA actuator. A modular design of a new prosthesis was developed which incorporated a novel SMA actuator for the index finger movement. The primary objective of the prosthesis is achieved, obtaining a modular and functional low-cost prosthesis based on additive manufacturing executed by a novel SMA actuator. The external SMA actuator provides a modular system which allows implementing it in different systems. This paper combines rapid prototyping and a novel SMA actuator to develop a new concept of modular and operative low-cost prosthetic hand.

Method and apparatus for efficiently tracking queue entries relative to a timestamp

DOEpatents

Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Heidelberger, Philip; Ohmacht, Martin; Salapura, Velentina; Vranas, Pavlos

2014-06-17

An apparatus and method for tracking coherence event signals transmitted in a multiprocessor system. The apparatus comprises a coherence logic unit, each unit having a plurality of queue structures with each queue structure associated with a respective sender of event signals transmitted in the system. A timing circuit associated with a queue structure controls enqueuing and dequeuing of received coherence event signals, and, a counter tracks a number of coherence event signals remaining enqueued in the queue structure and dequeued since receipt of a timestamp signal. A counter mechanism generates an output signal indicating that all of the coherence event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued. In one embodiment, the timestamp signal is asserted at the start of a memory synchronization operation and, the output signal indicates that all coherence events present when the timestamp signal was asserted have completed. This signal can then be used as part of the completion condition for the memory synchronization operation.

Engineering non-linear resonator mode interactions in circuit QED by continuous driving: Manipulation of a photonic quantum memory

NASA Astrophysics Data System (ADS)

Reagor, Matthew; Pfaff, Wolfgang; Heeres, Reinier; Ofek, Nissim; Chou, Kevin; Blumoff, Jacob; Leghtas, Zaki; Touzard, Steven; Sliwa, Katrina; Holland, Eric; Albert, Victor V.; Frunzio, Luigi; Devoret, Michel H.; Jiang, Liang; Schoelkopf, Robert J.

2015-03-01

Recent advances in circuit QED have shown great potential for using microwave resonators as quantum memories. In particular, it is possible to encode the state of a quantum bit in non-classical photonic states inside a high-Q linear resonator. An outstanding challenge is to perform controlled operations on such a photonic state. We demonstrate experimentally how a continuous drive on a transmon qubit coupled to a high-Q storage resonator can be used to induce non-linear dynamics of the resonator. Tailoring the drive properties allows us to cancel or enhance non-linearities in the system such that we can manipulate the state stored in the cavity. This approach can be used to either counteract undesirable evolution due to the bare Hamiltonian of the system or, ultimately, to perform logical operations on the state encoded in the cavity field. Our method provides a promising pathway towards performing universal control for quantum states stored in high-coherence resonators in the circuit QED platform.

[Memory assessment by means of virtual reality: its present and future].

PubMed

Diaz-Orueta, Unai; Climent, Gema; Cardas-Ibanez, Jaione; Alonso, Laura; Olmo-Osa, Juan; Tirapu-Ustarroz, Javier

2016-01-16

The human memory is a complex cognitive system whose close relationship with executive functions implies that, in many occasions, a mnemonic deficit comprises difficulties to operate with correctly stored contents. Traditional memory tests, more focused in the information storage than in its processing, may be poorly sensitive both to subjects' daily life functioning and to changes originated by rehabilitation programs. In memory assessment, there is plenty evidence with regards to the need of improving it by means of tests which offer a higher ecological validity, with information that may be presented in various sensorial modalities and produced in a simultaneous way. Virtual reality reproduces three-dimensional environments with which the patient interacts in a dynamic way, with a sense of immersion in the environment similar to the presence and exposure to a real environment, and in which presentation of such stimuli, distractors and other variables may be systematically controlled. The current review aims to go deeply into the trajectory of neuropsychological assessment of memory based in virtual reality environments, making a tour through existing tests designed for assessing learning, prospective, episodic and spatial memory, as well as the most recent attempts to perform a comprehensive evaluation of all memory components.

Examination of long-term visual memorization capacity in the Clark's nutcracker (Nucifraga columbiana).

PubMed

Qadri, Muhammad A J; Leonard, Kevin; Cook, Robert G; Kelly, Debbie M

2018-02-15

Clark's nutcrackers exhibit remarkable cache recovery behavior, remembering thousands of seed locations over the winter. No direct laboratory test of their visual memory capacity, however, has yet been performed. Here, two nutcrackers were tested in an operant procedure used to measure different species' visual memory capacities. The nutcrackers were incrementally tested with an ever-expanding pool of pictorial stimuli in a two-alternative discrimination task. Each picture was randomly assigned to either a right or a left choice response, forcing the nutcrackers to memorize each picture-response association. The nutcrackers' visual memorization capacity was estimated at a little over 500 pictures, and the testing suggested effects of primacy, recency, and memory decay over time. The size of this long-term visual memory was less than the approximately 800-picture capacity established for pigeons. These results support the hypothesis that nutcrackers' spatial memory is a specialized adaptation tied to their natural history of food-caching and recovery, and not to a larger long-term, general memory capacity. Furthermore, despite millennia of separate and divergent evolution, the mechanisms of visual information retention seem to reflect common memory systems of differing capacities across the different species tested in this design.

Simulation of n-qubit quantum systems. I. Quantum registers and quantum gates

NASA Astrophysics Data System (ADS)

Radtke, T.; Fritzsche, S.

2005-12-01

During recent years, quantum computations and the study of n-qubit quantum systems have attracted a lot of interest, both in theory and experiment. Apart from the promise of performing quantum computations, however, these investigations also revealed a great deal of difficulties which still need to be solved in practice. In quantum computing, unitary and non-unitary quantum operations act on a given set of qubits to form (entangled) states, in which the information is encoded by the overall system often referred to as quantum registers. To facilitate the simulation of such n-qubit quantum systems, we present the FEYNMAN program to provide all necessary tools in order to define and to deal with quantum registers and quantum operations. Although the present version of the program is restricted to unitary transformations, it equally supports—whenever possible—the representation of the quantum registers both, in terms of their state vectors and density matrices. In addition to the composition of two or more quantum registers, moreover, the program also supports their decomposition into various parts by applying the partial trace operation and the concept of the reduced density matrix. Using an interactive design within the framework of MAPLE, therefore, we expect the FEYNMAN program to be helpful not only for teaching the basic elements of quantum computing but also for studying their physical realization in the future. Program summaryTitle of program:FEYNMAN Catalogue number:ADWE Program summary URL:http://cpc.cs.qub.ac.uk/summaries/ADWE Program obtainable from:CPC Program Library, Queen's University of Belfast, N. Ireland Licensing provisions:None Computers for which the program is designed:All computers with a license of the computer algebra system MAPLE [Maple is a registered trademark of Waterlo Maple Inc.] Operating systems or monitors under which the program has been tested:Linux, MS Windows XP Programming language used:MAPLE 9.5 (but should be compatible with 9.0 and 8.0, too) Memory and time required to execute with typical data:Storage and time requirements critically depend on the number of qubits, n, in the quantum registers due to the exponential increase of the associated Hilbert space. In particular, complex algebraic operations may require large amounts of memory even for small qubit numbers. However, most of the standard commands (see Section 4 for simple examples) react promptly for up to five qubits on a normal single-processor machine ( ⩾1GHz with 512 MB memory) and use less than 10 MB memory. No. of lines in distributed program, including test data, etc.: 8864 No. of bytes in distributed program, including test data, etc.: 493 182 Distribution format: tar.gz Nature of the physical problem:During the last decade, quantum computing has been found to provide a revolutionary new form of computation. The algorithms by Shor [P.W. Shor, SIAM J. Sci. Statist. Comput. 26 (1997) 1484] and Grover [L.K. Grover, Phys. Rev. Lett. 79 (1997) 325. [2

Sleep supports inhibitory operant conditioning memory in Aplysia.

PubMed

Vorster, Albrecht P A; Born, Jan

2017-06-01

Sleep supports memory consolidation as shown in mammals and invertebrates such as bees and Drosophila. Here, we show that sleep's memory function is preserved in Aplysia californica with an even simpler nervous system. Animals performed on an inhibitory conditioning task ("learning that a food is inedible") three times, at Training, Retrieval 1, and Retrieval 2, with 17-h intervals between tests. Compared with Wake animals, remaining awake between Training and Retrieval 1, Sleep animals with undisturbed post-training sleep, performed significantly better at Retrieval 1 and 2. Control experiments testing retrieval only after ∼34 h, confirmed the consolidating effect of sleep occurring within 17 h after training. © 2017 Vorster and Born; Published by Cold Spring Harbor Laboratory Press.

The impact of multiple memory formation on dendritic complexity in the hippocampus and anterior cingulate cortex assessed at recent and remote time points

PubMed Central

Wartman, Brianne C.; Holahan, Matthew R.

2014-01-01

Consolidation processes, involving synaptic and systems level changes, are suggested to stabilize memories once they are formed. At the synaptic level, dendritic structural changes are associated with long-term memory storage. At the systems level, memory storage dynamics between the hippocampus and anterior cingulate cortex (ACC) may be influenced by the number of sequentially encoded memories. The present experiment utilized Golgi-Cox staining and neuron reconstruction to examine recent and remote structural changes in the hippocampus and ACC following training on three different behavioral procedures. Rats were trained on one hippocampal-dependent task only (a water maze task), two hippocampal-dependent tasks (a water maze task followed by a radial arm maze task), or one hippocampal-dependent and one non-hippocampal-dependent task (a water maze task followed by an operant conditioning task). Rats were euthanized recently or remotely. Brains underwent Golgi-Cox processing and neurons were reconstructed using Neurolucida software (MicroBrightField, Williston, VT, USA). Rats trained on two hippocampal-dependent tasks displayed increased dendritic complexity compared to control rats, in neurons examined in both the ACC and hippocampus at recent and remote time points. Importantly, this behavioral group showed consistent, significant structural differences in the ACC compared to the control group at the recent time point. These findings suggest that taxing the demand placed upon the hippocampus, by training rats on two hippocampal-dependent tasks, engages synaptic and systems consolidation processes in the ACC at an accelerated rate for recent and remote storage of spatial memories. PMID:24795581

Precipitation-Strengthened, High-Temperature, High-Force Shape Memory Alloys

NASA Technical Reports Server (NTRS)

Noebe, Ronald D.; Draper, Susan L.; Nathal, Michael V.; Crombie, Edwin A.

2008-01-01

Shape memory alloys (SMAs) are an enabling component in the development of compact, lightweight, durable, high-force actuation systems particularly for use where hydraulics or electrical motors are not practical. However, commercial shape memory alloys based on NiTi are only suitable for applications near room temperature, due to their relatively low transformation temperatures, while many potential applications require higher temperature capability. Consequently, a family of (Ni,Pt)(sub 1-x)Ti(sub x) shape memory alloys with Ti concentrations ranging from about 15 to 25 at.% have been developed for applications in which there are requirements for SMA actuators to exert high forces at operating temperatures higher than those of conventional binary NiTi SMAs. These alloys can be heat treated in the range of 500 C to produce a series of fine precipitate phases that increase the strength of alloy while maintaining a high transformation temperature, even in Ti-lean compositions.

Artificial Induction of Associative Olfactory Memory by Optogenetic and Thermogenetic Activation of Olfactory Sensory Neurons and Octopaminergic Neurons in Drosophila Larvae

PubMed Central

Honda, Takato; Lee, Chi-Yu; Honjo, Ken; Furukubo-Tokunaga, Katsuo

2016-01-01

The larval brain of Drosophila melanogaster provides an excellent system for the study of the neurocircuitry mechanism of memory. Recent development of neurogenetic techniques in fruit flies enables manipulations of neuronal activities in freely behaving animals. This protocol describes detailed steps for artificial induction of olfactory associative memory in Drosophila larvae. In this protocol, the natural reward signal is substituted by thermogenetic activation of octopaminergic neurons in the brain. In parallel, the odor signal is substituted by optogenetic activation of a specific class of olfactory receptor neurons. Association of reward and odor stimuli is achieved with the concomitant application of blue light and heat that leads to activation of both sets of neurons in living transgenic larvae. Given its operational simplicity and robustness, this method could be utilized to further our knowledge on the neurocircuitry mechanism of memory in the fly brain. PMID:27445732

Reed Solomon codes for error control in byte organized computer memory systems

NASA Technical Reports Server (NTRS)

Lin, S.; Costello, D. J., Jr.

1984-01-01

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation are presented. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial.

A fast low-power optical memory based on coupled micro-ring lasers

NASA Astrophysics Data System (ADS)

Hill, Martin T.; Dorren, Harmen J. S.; de Vries, Tjibbe; Leijtens, Xaveer J. M.; den Besten, Jan Hendrik; Smalbrugge, Barry; Oei, Yok-Siang; Binsma, Hans; Khoe, Giok-Djan; Smit, Meint K.

2004-11-01

The increasing speed of fibre-optic-based telecommunications has focused attention on high-speed optical processing of digital information. Complex optical processing requires a high-density, high-speed, low-power optical memory that can be integrated with planar semiconductor technology for buffering of decisions and telecommunication data. Recently, ring lasers with extremely small size and low operating power have been made, and we demonstrate here a memory element constructed by interconnecting these microscopic lasers. Our device occupies an area of 18 × 40µm2 on an InP/InGaAsP photonic integrated circuit, and switches within 20ps with 5.5fJ optical switching energy. Simulations show that the element has the potential for much smaller dimensions and switching times. Large numbers of such memory elements can be densely integrated and interconnected on a photonic integrated circuit: fast digital optical information processing systems employing large-scale integration should now be viable.

Apollo guidance, navigation and control: Guidance system operations plans for manned LM earth orbital and lunar missions using Program COLOSSUS 3. Section 7: Erasable memory programs

NASA Technical Reports Server (NTRS)

Hamilton, M. H.

1972-01-01

Erasable-memory programs (EMPs) designed for the guidance computers used in the command (CMC) and lunar modules (LGC) are described. CMC programs are designated COLOSSUS 3, and the associated EMPs are identified by a three-digit number beginning with 5. LGC programs are designated LUMINARY 1E, and the associated EMPs are identified, with one exception, by a three-digit number beginning with 1. The exception is EMP 99. The EMPs vary in complexity from a simple flagbit setting to a long and intricate logical structure. They all, however, cause the computer to behave in a way not intended in the original design of the programs; they accomplish this off-nominal behavior by some alteration of erasable memory to interface with existing fixed-memory programs to effect a desired result.

Superior memory efficiency of quantum devices for the simulation of continuous-time stochastic processes

NASA Astrophysics Data System (ADS)

Elliott, Thomas J.; Gu, Mile

2018-03-01

Continuous-time stochastic processes pervade everyday experience, and the simulation of models of these processes is of great utility. Classical models of systems operating in continuous-time must typically track an unbounded amount of information about past behaviour, even for relatively simple models, enforcing limits on precision due to the finite memory of the machine. However, quantum machines can require less information about the past than even their optimal classical counterparts to simulate the future of discrete-time processes, and we demonstrate that this advantage extends to the continuous-time regime. Moreover, we show that this reduction in the memory requirement can be unboundedly large, allowing for arbitrary precision even with a finite quantum memory. We provide a systematic method for finding superior quantum constructions, and a protocol for analogue simulation of continuous-time renewal processes with a quantum machine.

A Comprehensive Study on Energy Efficiency and Performance of Flash-based SSD

DOE Office of Scientific and Technical Information (OSTI.GOV)

Park, Seon-Yeon; Kim, Youngjae; Urgaonkar, Bhuvan

2011-01-01

Use of flash memory as a storage medium is becoming popular in diverse computing environments. However, because of differences in interface, flash memory requires a hard-disk-emulation layer, called FTL (flash translation layer). Although the FTL enables flash memory storages to replace conventional hard disks, it induces significant computational and space overhead. Despite the low power consumption of flash memory, this overhead leads to significant power consumption in an overall storage system. In this paper, we analyze the characteristics of flash-based storage devices from the viewpoint of power consumption and energy efficiency by using various methodologies. First, we utilize simulation tomore » investigate the interior operation of flash-based storage of flash-based storages. Subsequently, we measure the performance and energy efficiency of commodity flash-based SSDs by using microbenchmarks to identify the block-device level characteristics and macrobenchmarks to reveal their filesystem level characteristics.« less

Towards a Quantum Memory assisted MDI-QKD node

NASA Astrophysics Data System (ADS)

Namazi, Mehdi; Vallone, Giuseppe; Jordaan, Bertus; Goham, Connor; Shahrokhshahi, Reihaneh; Villoresi, Paolo; Figueroa, Eden

2017-04-01

The creation of large quantum network that permits the communication of quantum states and the secure distribution of cryptographic keys requires multiple operational quantum memories. In this work we present our progress towards building a prototypical quantum network that performs the memory-assisted measurement device independent QKD protocol. Currently our network combines the quantum part of the BB84 protocol with room-temperature quantum memory operation, while still maintaining relevant quantum bit error rates for single-photon level operation. We will also discuss our efforts to use a network of two room temperature quantum memories, receiving, storing and transforming randomly polarized photons in order to realize Bell state measurements. The work was supported by the US-Navy Office of Naval Research, Grant Number N00141410801, the National Science Foundation, Grant Number PHY-1404398 and the Simons Foundation, Grant Number SBF241180.

Measurement-based analysis of error latency. [in computer operating system

NASA Technical Reports Server (NTRS)

Chillarege, Ram; Iyer, Ravishankar K.

1987-01-01

This paper demonstrates a practical methodology for the study of error latency under a real workload. The method is illustrated with sampled data on the physical memory activity, gathered by hardware instrumentation on a VAX 11/780 during the normal workload cycle of the installation. These data are used to simulate fault occurrence and to reconstruct the error discovery process in the system. The technique provides a means to study the system under different workloads and for multiple days. An approach to determine the percentage of undiscovered errors is also developed and a verification of the entire methodology is performed. This study finds that the mean error latency, in the memory containing the operating system, varies by a factor of 10 to 1 (in hours) between the low and high workloads. It is found that of all errors occurring within a day, 70 percent are detected in the same day, 82 percent within the following day, and 91 percent within the third day. The increase in failure rate due to latency is not so much a function of remaining errors but is dependent on whether or not there is a latent error.

Multifunctional wearable devices for diagnosis and therapy of movement disorders.

PubMed

Son, Donghee; Lee, Jongha; Qiao, Shutao; Ghaffari, Roozbeh; Kim, Jaemin; Lee, Ji Eun; Song, Changyeong; Kim, Seok Joo; Lee, Dong Jun; Jun, Samuel Woojoo; Yang, Shixuan; Park, Minjoon; Shin, Jiho; Do, Kyungsik; Lee, Mincheol; Kang, Kwanghun; Hwang, Cheol Seong; Lu, Nanshu; Hyeon, Taeghwan; Kim, Dae-Hyeong

2014-05-01

Wearable systems that monitor muscle activity, store data and deliver feedback therapy are the next frontier in personalized medicine and healthcare. However, technical challenges, such as the fabrication of high-performance, energy-efficient sensors and memory modules that are in intimate mechanical contact with soft tissues, in conjunction with controlled delivery of therapeutic agents, limit the wide-scale adoption of such systems. Here, we describe materials, mechanics and designs for multifunctional, wearable-on-the-skin systems that address these challenges via monolithic integration of nanomembranes fabricated with a top-down approach, nanoparticles assembled by bottom-up methods, and stretchable electronics on a tissue-like polymeric substrate. Representative examples of such systems include physiological sensors, non-volatile memory and drug-release actuators. Quantitative analyses of the electronics, mechanics, heat-transfer and drug-diffusion characteristics validate the operation of individual components, thereby enabling system-level multifunctionalities.

Holography and optical information processing; Proceedings of the Soviet-Chinese Joint Seminar, Bishkek, Kyrgyzstan, Sept. 21-26, 1991

NASA Astrophysics Data System (ADS)

Mikaelian, Andrei L.

Attention is given to data storage, devices, architectures, and implementations of optical memory and neural networks; holographic optical elements and computer-generated holograms; holographic display and materials; systems, pattern recognition, interferometry, and applications in optical information processing; and special measurements and devices. Topics discussed include optical immersion as a new way to increase information recording density, systems for data reading from optical disks on the basis of diffractive lenses, a new real-time optical associative memory system, an optical pattern recognition system based on a WTA model of neural networks, phase diffraction grating for the integral transforms of coherent light fields, holographic recording with operated sensitivity and stability in chalcogenide glass layers, a compact optical logic processor, a hybrid optical system for computing invariant moments of images, optical fiber holographic inteferometry, and image transmission through random media in single pass via optical phase conjugation.

Symptom validity test performance and consistency of self-reported memory functioning of Operation Enduring Freedom/Operation Iraqi freedom veterans with positive Veteran Health Administration Comprehensive Traumatic Brain Injury evaluations.

PubMed

Russo, Arthur C

2012-12-01

Operation Enduring Freedom and Operation Iraqi Freedom combat veterans given definite diagnoses of mild Traumatic Brain Injury (TBI) during the Veteran Health Administration (VHA) Comprehensive TBI evaluation and reporting no post-deployment head injury were examined to assess (a) consistency of self-reported memory impairment and (b) symptom validity test (SVT) performance via a two-part study. Study 1 found that while 49 of 50 veterans reported moderate to very severe memory impairment during the VHA Comprehensive TBI evaluation, only 7 had reported any memory problem at the time of their Department of Defense (DOD) post-deployment health assessment. Study 2 found that of 38 veterans referred for neuropsychological evaluations following a positive VHA Comprehensive TBI evaluation, 68.4% failed the Word Memory Test, a forced choice memory recognition symptom validity task. Together, these studies raise questions concerning the use of veteran symptom self-report for TBI assessments and argue for the inclusion of SVTs and the expanded use of contemporaneous DOD records to improve the diagnostic accuracy of the VHA Comprehensive TBI evaluation.

Discrete Serotonin Systems Mediate Memory Enhancement and Escape Latencies after Unpredicted Aversive Experience in Drosophila Place Memory

PubMed Central

Sitaraman, Divya; Kramer, Elizabeth F.; Kahsai, Lily; Ostrowski, Daniela; Zars, Troy

2017-01-01

Feedback mechanisms in operant learning are critical for animals to increase reward or reduce punishment. However, not all conditions have a behavior that can readily resolve an event. Animals must then try out different behaviors to better their situation through outcome learning. This form of learning allows for novel solutions and with positive experience can lead to unexpected behavioral routines. Learned helplessness, as a type of outcome learning, manifests in part as increases in escape latency in the face of repeated unpredicted shocks. Little is known about the mechanisms of outcome learning. When fruit fly Drosophila melanogaster are exposed to unpredicted high temperatures in a place learning paradigm, flies both increase escape latencies and have a higher memory when given control of a place/temperature contingency. Here we describe discrete serotonin neuronal circuits that mediate aversive reinforcement, escape latencies, and memory levels after place learning in the presence and absence of unexpected aversive events. The results show that two features of learned helplessness depend on the same modulatory system as aversive reinforcement. Moreover, changes in aversive reinforcement and escape latency depend on local neural circuit modulation, while memory enhancement requires larger modulation of multiple behavioral control circuits. PMID:29321732

40 CFR 1042.110 - Recording reductant use and other diagnostic functions.

Code of Federal Regulations, 2010 CFR

2010-07-01

...) The onboard computer log must record in nonvolatile computer memory all incidents of engine operation... such operation in nonvolatile computer memory. You are not required to monitor NOX concentrations...

Memory operations in Au nanoparticle single-electron transistors with floating gate electrodes

NASA Astrophysics Data System (ADS)

Azuma, Yasuo; Sakamoto, Masanori; Teranishi, Toshiharu; Majima, Yutaka

2016-11-01

Floating gate memory operations are demonstrated in a single-electron transistor (SET) fabricated by a chemical assembly using the Au nanogap electrodes and the chemisorbed Au nanoparticles. By applying pulse voltages to the control gate, phase shifts were clearly and stably observed both in the Coulomb oscillations and in the Coulomb diamonds. Writing and erasing operations on the floating gate memory were reproducibly observed, and the charges on the floating gate electrodes were maintained for at least 12 h. By considering the capacitance of the floating gate electrode, the number of electrons in the floating gate electrode was estimated as 260. Owing to the stability of the fabricated SET, these writing and erasing operations on the floating gate memory can be applied to reconfigurable SET circuits fabricated by a chemically assembled technique.

Memory loss and memory reorganization patterns in temporal lobe epilepsy patients undergoing anterior temporal lobe resection, as demonstrated by pre-versus post-operative functional MRI.

PubMed

Limotai, Chusak; McLachlan, Richard S; Hayman-Abello, Susan; Hayman-Abello, Brent; Brown, Suzan; Bihari, Frank; Mirsattari, Seyed M

2018-06-19

This study was aimed to longitudinally assess memory function and whole-brain memory circuit reorganization in patients with temporal lobe epilepsy (TLE) by comparing activation potentials before versus after anterior temporal lobe (ATL) resection. Nineteen patients with medically-intractable TLE (10 left TLE, 9 right TLE) and 15 healthy controls were enrolled. Group analyses were conducted pre- and post-ATL of a novelty complex scene-encoding paradigm comparing areas of blood oxygen-level-dependent (BOLD) signal activations on functional magnetic resonance imaging (fMRI). None of the pre-operative patient characteristics we studied predicted the extent of pre- to post-operative memory loss. On fMRI, extra-temporal activations were detected pre-operatively in both LTLE and RTLE, particularly in the frontal lobe. Greater activations also were noted in the contralateral hippocampus and parahippocampus in both groups. Performing within-subject comparisons, post-op relative to pre-op, pronounced ipsilateral activations were identified in the left parahippocampal gyrus in LTLE, versus the right middle temporal gyrus in RTLE patients. Memory function was impaired pre-operatively but declined after ATL resection in both RTLE and LTLE patients. Post-operative fMRI results indicate possible functional adaptations to ATL loss, primarily occurring within the left parahippocampal gyrus versus right middle temporal gyrus in LTLE versus RTLE patients, respectively. Copyright © 2018 Elsevier Ltd. All rights reserved.

Developing infrared array controller with software real time operating system

NASA Astrophysics Data System (ADS)

Sako, Shigeyuki; Miyata, Takashi; Nakamura, Tomohiko; Motohara, Kentaro; Uchimoto, Yuka Katsuno; Onaka, Takashi; Kataza, Hirokazu

2008-07-01

Real-time capabilities are required for a controller of a large format array to reduce a dead-time attributed by readout and data transfer. The real-time processing has been achieved by dedicated processors including DSP, CPLD, and FPGA devices. However, the dedicated processors have problems with memory resources, inflexibility, and high cost. Meanwhile, a recent PC has sufficient resources of CPUs and memories to control the infrared array and to process a large amount of frame data in real-time. In this study, we have developed an infrared array controller with a software real-time operating system (RTOS) instead of the dedicated processors. A Linux PC equipped with a RTAI extension and a dual-core CPU is used as a main computer, and one of the CPU cores is allocated to the real-time processing. A digital I/O board with DMA functions is used for an I/O interface. The signal-processing cores are integrated in the OS kernel as a real-time driver module, which is composed of two virtual devices of the clock processor and the frame processor tasks. The array controller with the RTOS realizes complicated operations easily, flexibly, and at a low cost.

Operating experience with a VMEbus multiprocessor system for data acquisition and reduction in nuclear physics

NASA Astrophysics Data System (ADS)

Kutt, P. H.; Balamuth, D. P.

1989-10-01

Summary form only given, as follows. A multiprocessor system based on commercially available VMEbus components has been developed for the acquisition and reduction of event-mode data in nuclear physics experiments. The system contains seven 68000 CPUs and 14 Mbyte of memory. A minimal operating system handles data transfer and task allocation, and a compiler for a specially designed event analysis language produces code for the processors. The system has been in operation for four years at the University of Pennsylvania Tandem Accelerator Laboratory. Computation rates over three times that of a MicroVAX II have been achieved at a fraction of the cost. The use of WORM optical disks for event recording allows the processing of gigabyte data sets without operator intervention. A more powerful system is being planned which will make use of recently developed RISC (reduced instruction set computer) processors to obtain an order of magnitude increase in computing power per node.

The contaminant analysis automation robot implementation for the automated laboratory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Younkin, J.R.; Igou, R.E.; Urenda, T.D.

1995-12-31

The Contaminant Analysis Automation (CAA) project defines the automated laboratory as a series of standard laboratory modules (SLM) serviced by a robotic standard support module (SSM). These SLMs are designed to allow plug-and-play integration into automated systems that perform standard analysis methods (SAM). While the SLMs are autonomous in the execution of their particular chemical processing task, the SAM concept relies on a high-level task sequence controller (TSC) to coordinate the robotic delivery of materials requisite for SLM operations, initiate an SLM operation with the chemical method dependent operating parameters, and coordinate the robotic removal of materials from the SLMmore » when its commands and events has been established to allow ready them for transport operations as well as performing the Supervisor and Subsystems (GENISAS) software governs events from the SLMs and robot. The Intelligent System Operating Environment (ISOE) enables the inter-process communications used by GENISAS. CAA selected the Hewlett-Packard Optimized Robot for Chemical Analysis (ORCA) and its associated Windows based Methods Development Software (MDS) as the robot SSM. The MDS software is used to teach the robot each SLM position and required material port motions. To allow the TSC to command these SLM motions, a hardware and software implementation was required that allowed message passing between different operating systems. This implementation involved the use of a Virtual Memory Extended (VME) rack with a Force CPU-30 computer running VxWorks; a real-time multitasking operating system, and a Radiuses PC compatible VME computer running MDS. A GENISAS server on The Force computer accepts a transport command from the TSC, a GENISAS supervisor, over Ethernet and notifies software on the RadiSys PC of the pending command through VMEbus shared memory. The command is then delivered to the MDS robot control software using a Windows Dynamic Data Exchange conversation.« less

HEC Applications on Columbia Project

NASA Technical Reports Server (NTRS)

Taft, Jim

2004-01-01

NASA's Columbia system consists of a cluster of twenty 512 processor SGI Altix systems. Each of these systems is 3 TFLOP/s in peak performance - approximately the same as the entire compute capability at NAS just one year ago. Each 512p system is a single system image machine with one Linunx O5, one high performance file system, and one globally shared memory. The NAS Terascale Applications Group (TAG) is chartered to assist in scaling NASA's mission critical codes to at least 512p in order to significantly improve emergency response during flight operations, as well as provide significant improvements in the codes. and rate of scientific discovery across the scientifc disciplines within NASA's Missions. Recent accomplishments are 4x improvements to codes in the ocean modeling community, 10x performance improvements in a number of computational fluid dynamics codes used in aero-vehicle design, and 5x improvements in a number of space science codes dealing in extreme physics. The TAG group will continue its scaling work to 2048p and beyond (10240 cpus) as the Columbia system becomes fully operational and the upgrades to the SGI NUMAlink memory fabric are in place. The NUMlink uprades dramatically improve system scalability for a single application. These upgrades will allow a number of codes to execute faster at higher fidelity than ever before on any other system, thus increasing the rate of scientific discovery even further

Digital Holographic Data Storage with Fast Access

NASA Astrophysics Data System (ADS)

Ma, J.; Chang, T.; Choi, S.; Hong, J.

Recent investigations in holographic mass memory systems have produced proof of concept demonstrations that have highlighted their potential for providing unprecedented capacity, data transfer rates and fast random access performance [1-4]. The exploratory nature of most such investigations has been largely confined to benchtop experiments in which the practical constraints of packaging and environmental concerns have been ignored. We have embarked on an effort to demonstrate the holographic mass memory concept by developing a compact prototype system geared for avionics and similar applications, which demand the following features (mostly interdependent factors): (1) solid-state design (no moving parts), (2) fast data-seek time, (3) robustness with respect to environmental factors (temperature, vibration, shock). In this chapter, we report on the development and demonstration of two systems, one with 100 Mbytes and the other with more than 1 Gbyte of storage capacity. Both systems feature solid-state design with the addressing mechanism realized with acousto-optic deflectors that are capable of better than 50 µs data seek time. Since the basic designs for the two systems are similar, we describe only the larger system in detail. The operation of the smaller system has been demonstrated in various environments, including hand-held operation and thermal/mechanical shock, and a photograph of the smaller system is provided as well as actual digital data retrieved from the same system.

Packaged digital holographic data storage with fast access

NASA Astrophysics Data System (ADS)

Ma, Jian; Chang, Tallis Y.; Choi, Sung; Hong, John H.

1998-11-01

Recent investigations in holographic mass memory systems have produced proof of concept demonstrations that have highlighted their potential for providing unprecedented capacity, data transfer rates and fast random access performance. The exploratory nature of most such investigations have been largely confined to benchtop experiments in which the practical constraints of packaging and environmental concerns have been ignored. We have embarked on an effort to demonstrate the holographic mass memory concept by developing a compact prototype system geared for avionics and similar applications which demand the following features (mostly interdependent factors): (1) solid state design (no moving parts), (2) fast data seek time, (3) robust with respect to environmental factors (temperature, vibration, shock). In this paper, we report on the development and demonstration of two systems, one with 100 Mbytes and the other with more than 1 Gbyte of storage capacity. Both systems feature solid state design with the addressing mechanism realized with acousto- optic deflectors that are capable of better than 50 microseconds data seek time. Since the basic designs for the two systems are similar, we describe only the larger system in detail. The operation of the smaller system has been demonstrated in various environments including hand-held operation and thermal/mechanical shock and a photograph of the smaller system is provided as well as actual digital data retrieved from the same system.

Technology for organization of the onboard system for processing and storage of ERS data for ultrasmall spacecraft

NASA Astrophysics Data System (ADS)

Strotov, Valery V.; Taganov, Alexander I.; Konkin, Yuriy V.; Kolesenkov, Aleksandr N.

2017-10-01

Task of processing and analysis of obtained Earth remote sensing data on ultra-small spacecraft board is actual taking into consideration significant expenditures of energy for data transfer and low productivity of computers. Thereby, there is an issue of effective and reliable storage of the general information flow obtained from onboard systems of information collection, including Earth remote sensing data, into a specialized data base. The paper has considered peculiarities of database management system operation with the multilevel memory structure. For storage of data in data base the format has been developed that describes a data base physical structure which contains required parameters for information loading. Such structure allows reducing a memory size occupied by data base because it is not necessary to store values of keys separately. The paper has shown architecture of the relational database management system oriented into embedment into the onboard ultra-small spacecraft software. Data base for storage of different information, including Earth remote sensing data, can be developed by means of such database management system for its following processing. Suggested database management system architecture has low requirements to power of the computer systems and memory resources on the ultra-small spacecraft board. Data integrity is ensured under input and change of the structured information.

Performance Evaluation and Improvement of Ferroelectric Field-Effect Transistor Memory

NASA Astrophysics Data System (ADS)

Yu, Hyung Suk

Flash memory is reaching scaling limitations rapidly due to reduction of charge in floating gates, charge leakage and capacitive coupling between cells which cause threshold voltage fluctuations, short retention times, and interference. Many new memory technologies are being considered as alternatives to flash memory in an effort to overcome these limitations. Ferroelectric Field-Effect Transistor (FeFET) is one of the main emerging candidates because of its structural similarity to conventional FETs and fast switching speed. Nevertheless, the performance of FeFETs have not been systematically compared and analyzed against other competing technologies. In this work, we first benchmark the intrinsic performance of FeFETs and other memories by simulations in order to identify the strengths and weaknesses of FeFETs. To simulate realistic memory applications, we compare memories on an array structure. For the comparisons, we construct an accurate delay model and verify it by benchmarking against exact HSPICE simulations. Second, we propose an accurate model for FeFET memory window since the existing model has limitations. The existing model assumes symmetric operation voltages but it is not valid for the practical asymmetric operation voltages. In this modeling, we consider practical operation voltages and device dimensions. Also, we investigate realistic changes of memory window over time and retention time of FeFETs. Last, to improve memory window and subthreshold swing, we suggest nonplanar junctionless structures for FeFETs. Using the suggested structures, we study the dimensional dependences of crucial parameters like memory window and subthreshold swing and also analyze key interference mechanisms.

PANDA: A distributed multiprocessor operating system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chubb, P.

1989-01-01

PANDA is a design for a distributed multiprocessor and an operating system. PANDA is designed to allow easy expansion of both hardware and software. As such, the PANDA kernel provides only message passing and memory and process management. The other features needed for the system (device drivers, secondary storage management, etc.) are provided as replaceable user tasks. The thesis presents PANDA's design and implementation, both hardware and software. PANDA uses multiple 68010 processors sharing memory on a VME bus, each such node potentially connected to others via a high speed network. The machine is completely homogeneous: there are no differencesmore » between processors that are detectable by programs running on the machine. A single two-processor node has been constructed. Each processor contains memory management circuits designed to allow processors to share page tables safely. PANDA presents a programmers' model similar to the hardware model: a job is divided into multiple tasks, each having its own address space. Within each task, multiple processes share code and data. Tasks can send messages to each other, and set up virtual circuits between themselves. Peripheral devices such as disc drives are represented within PANDA by tasks. PANDA divides secondary storage into volumes, each volume being accessed by a volume access task, or VAT. All knowledge about the way that data is stored on a disc is kept in its volume's VAT. The design is such that PANDA should provide a useful testbed for file systems and device drivers, as these can be installed without recompiling PANDA itself, and without rebooting the machine.« less

Combined Arms in the Electro-Magnetic Spectrum: Integrating Non-kinetic Operations

DTIC Science & Technology

2013-05-23

Greene , Robert. The 33 Strategies of War. New York: Penguin, 2007. Halpern, Jason. IP Telephony Security in Depth. Cisco Systems, 2003...Theory of John Boyd. New York, NY: Routledge, 2007. Paiget, J., & Inhelder, B. Memory and Intelligence. London: Routledge and Kegan Paul, 1973. Qiao

How to Program the Principal's Office for the Computer Age.

ERIC Educational Resources Information Center

Frankel, Steven

1983-01-01

Explains why principals' offices need computers and discusses the characteristics of inexpensive personal business computers, including their operating systems, disk drives, memory, and compactness. Reviews software available for word processing, accounting, database management, and communications, and compares the Kaypro II, Morrow, and Osborne I…

75 FR 12974 - Establishment of Class E Airspace; Hailey, ID

Federal Register 2010, 2011, 2012, 2013, 2014

2010-03-18

... airspace at Hailey, ID, to accommodate aircraft using the Area Navigation (RNAV) Global Positioning System (GPS) Standard Instrument Approach Procedure (SIAP) at Friedman Memorial Airport. This will improve the safety of Instrument Flight Rules (IFR) operations at the airport. DATES: Effective Date: 0901 UTC, June...

Looking Ahead: A Report on the Latest Survey Results.

ERIC Educational Resources Information Center

Technology & Learning, 1995

1995-01-01

Reports on the results of a survey of software publishers and market researchers for educators that was conducted to determine development, purchasing, and upgrading plans for educational computer technology. Highlights include operating systems, including Macintosh, DOS, and Windows; equipment needs, including memory, monitors, and special…

Human learning and memory.

PubMed

Johnson, M K; Hasher, L

1987-01-01

There have been several notable recent trends in the area of learning and memory. Problems with the episodic/semantic distinction have become more apparent, and new efforts have been made (exemplar models, distributed-memory models) to represent general knowledge without assuming a separate semantic system. Less emphasis is being placed on stable, prestored prototypes and more emphasis on a flexible memory system that provides the basis for a multitude of categories or frames of reference, derived on the spot as tasks demand. There is increasing acceptance of the idea that mental models are constructed and stored in memory in addition to, rather than instead of, memorial representations that are more closely tied to perceptions. This gives rise to questions concerning the conditions that permit inferences to be drawn and mental models to be constructed, and to questions concerning the similarities and differences in the nature of the representations in memory of perceived and generated information and in their functions. There has also been a swing from interest in deliberate strategies to interest in automatic, unconscious (even mechanistic!) processes, reflecting an appreciation that certain situations (e.g. recognition, frequency judgements, savings in indirect tasks, aspects of skill acquisition, etc) seem not to depend much on the products of strategic, effortful or reflective processes. There is a lively interest in relations among memory measures and attempts to characterize memory representations and/or processes that could give rise to dissociations among measures. Whether the pattern of results reflects the operation of functional subsystems of memory and, if so, what the "modules" are is far from clear. This issue has been fueled by work with amnesics and has contributed to a revival of interaction between researchers studying learning and memory in humans and those studying learning and memory in animals. Thus, neuroscience rivals computer science as a source of interdisciplinary stimulation. Research on topics such as memory for spatial location, the relation between memory and affect, and autobiographical memory reminds us that general theories of memory based on studies of verbal materials alone are limited. Investigating how people remember complex natural events should provide us with a larger set of memory phenomena to explain and consequently insight into a wider range of memory principles or a deeper understanding of the ones we already accept (e.g. the role of repetition, encoding specificity), including their functional significance for human behavior.(ABSTRACT TRUNCATED AT 400 WORDS)

Integration and High-Temperature Characterization of Ferroelectric Vanadium-Doped Bismuth Titanate Thin Films on Silicon Carbide

NASA Astrophysics Data System (ADS)

Ekström, Mattias; Khartsev, Sergiy; Östling, Mikael; Zetterling, Carl-Mikael

2017-07-01

4H-SiC electronics can operate at high temperature (HT), e.g., 300°C to 500°C, for extended times. Systems using sensors and amplifiers that operate at HT would benefit from microcontrollers which can also operate at HT. Microcontrollers require nonvolatile memory (NVM) for computer programs. In this work, we demonstrate the possibility of integrating ferroelectric vanadium-doped bismuth titanate (BiTV) thin films on 4H-SiC for HT memory applications, with BiTV ferroelectric capacitors providing memory functionality. Film deposition was achieved by laser ablation on Pt (111)/TiO2/4H-SiC substrates, with magnetron-sputtered Pt used as bottom electrode and thermally evaporated Au as upper contacts. Film characterization by x-ray diffraction analysis revealed predominately (117) orientation. P- E hysteresis loops measured at room temperature showed maximum 2 P r of 48 μC/cm2, large enough for wide read margins. P- E loops were measurable up to 450°C, with losses limiting measurements above 450°C. The phase-transition temperature was determined to be about 660°C from the discontinuity in dielectric permittivity, close to what is achieved for ceramics. These BiTV ferroelectric capacitors demonstrate potential for use in HT NVM applications for SiC digital electronics.

The Royal Road to Time: How Understanding of the Evolution of Time in the Brain Addresses Memory, Dreaming, Flow, and Other Psychological Phenomena.

PubMed

Hancock, Peter A

2015-01-01

It has been claimed that dreams are the royal road to the unconscious mind. The present work argues that dreams and associated brain states such as memory, attention, flow, and perhaps even consciousness itself arise from diverse conflicts over control of time in the brain. Dreams are the brain's offline efforts to distill projections of the future, while memory represents the vestiges of the past successes and survived failures of those and other conscious projections. Memory thus acts to inform and improve the prediction of possible future states through the use of conscious prospects (planning) and unconscious prospective memory (dreams). When successful, these prospects result in states of flow for conscious planning and déjà vu for its unconscious comparator. In consequence, and contrary to normal expectation, memory is overwhelmingly oriented to deal with the future. Consciousness is the comparable process operating in the present moment. Thus past, present, and future are homeomorphic with the parts of memory (episodic and autobiographical) that recall a personal past, consciousness, and the differing dimensions of prospective memory to plan for future circumstances, respectively. Dreaming (i.e., unconscious prospective memory), has the luxury to run multiple "what if" simulations of many possible futures, essentially offline. I explicate these propositions and their relations to allied constructs such as déjà vu and flow. More generally, I propose that what appear to us as a range of normal psychological experiences are actually manifestations of an ongoing pathological battle for control within the brain. The landscape of this conflict is time. I suggest that there are at least 3 general systems bidding for this control, and in the process of evolution, each system has individually conferred a sequentially increasing survival advantage, but only at the expense of a still incomplete functional integration. Through juxtaposition of these respective brain systems, I endeavor to resolve some fundamental paradoxes and conundrums expressed in the basic psychological and behavioral processes of sleep, consciousness, and memory. The implication of this conceptual framework for the overall conception of time is then briefly adumbrated.

Research principles and the construction of mnemonic diagrams

NASA Technical Reports Server (NTRS)

Venda, V. F.; Mitkin, A. A.

1973-01-01

Mnemonic diagrams are defined as a variety of information display devices, the essential element of which is conventional graphical presentation of technological or functional-operational links in a controlled system or object. Graphically displaying the operational structure of an object, the interd dependence between different parameters, and the interdependence between indicators and control organs, the mneomonic diagram reduces the load on the operator's memory and facilitates perception and reprocessing of information and decision making, while at the same time playing the role of visual support to the information activity of the operator. The types of mnemonic diagrams are listed.

Renormalization of Seasonals in the Additive Seasonal Model: Is it Necessary?

DTIC Science & Technology

1984-02-01

recommended that qlass, headliqhts, and parkinq liqhts, the radiator, and other parts of the automobile which may be damaqed be covered with plywood...34Flying Automobile ", the AIR-6, and then a two-place monoplane, the AIR-7. A. S. Yakovlev was assigned as Supervisor of the Design Bureau for...operational unit, the microprogrammed control unit, the operating, permanent, and reprogrammable memory, the input-output unit, and the system of

Variable Order and Distributed Order Fractional Operators

NASA Technical Reports Server (NTRS)

Lorenzo, Carl F.; Hartley, Tom T.

2002-01-01

Many physical processes appear to exhibit fractional order behavior that may vary with time or space. The continuum of order in the fractional calculus allows the order of the fractional operator to be considered as a variable. This paper develops the concept of variable and distributed order fractional operators. Definitions based on the Riemann-Liouville definitions are introduced and behavior of the operators is studied. Several time domain definitions that assign different arguments to the order q in the Riemann-Liouville definition are introduced. For each of these definitions various characteristics are determined. These include: time invariance of the operator, operator initialization, physical realization, linearity, operational transforms. and memory characteristics of the defining kernels. A measure (m2) for memory retentiveness of the order history is introduced. A generalized linear argument for the order q allows the concept of "tailored" variable order fractional operators whose a, memory may be chosen for a particular application. Memory retentiveness (m2) and order dynamic behavior are investigated and applications are shown. The concept of distributed order operators where the order of the time based operator depends on an additional independent (spatial) variable is also forwarded. Several definitions and their Laplace transforms are developed, analysis methods with these operators are demonstrated, and examples shown. Finally operators of multivariable and distributed order are defined in their various applications are outlined.

Decision Support Systems for Launch and Range Operations Using Jess

NASA Technical Reports Server (NTRS)

Thirumalainambi, Rajkumar

2007-01-01

The virtual test bed for launch and range operations developed at NASA Ames Research Center consists of various independent expert systems advising on weather effects, toxic gas dispersions and human health risk assessment during space-flight operations. An individual dedicated server supports each expert system and the master system gather information from the dedicated servers to support the launch decision-making process. Since the test bed is based on the web system, reducing network traffic and optimizing the knowledge base is critical to its success of real-time or near real-time operations. Jess, a fast rule engine and powerful scripting environment developed at Sandia National Laboratory has been adopted to build the expert systems providing robustness and scalability. Jess also supports XML representation of knowledge base with forward and backward chaining inference mechanism. Facts added - to working memory during run-time operations facilitates analyses of multiple scenarios. Knowledge base can be distributed with one inference engine performing the inference process. This paper discusses details of the knowledge base and inference engine using Jess for a launch and range virtual test bed.

Context-sensitive autoassociative memories as expert systems in medical diagnosis

PubMed Central

Pomi, Andrés; Olivera, Fernando

2006-01-01

Background The complexity of our contemporary medical practice has impelled the development of different decision-support aids based on artificial intelligence and neural networks. Distributed associative memories are neural network models that fit perfectly well to the vision of cognition emerging from current neurosciences. Methods We present the context-dependent autoassociative memory model. The sets of diseases and symptoms are mapped onto a pair of basis of orthogonal vectors. A matrix memory stores the associations between the signs and symptoms, and their corresponding diseases. A minimal numerical example is presented to show how to instruct the memory and how the system works. In order to provide a quick appreciation of the validity of the model and its potential clinical relevance we implemented an application with real data. A memory was trained with published data of neonates with suspected late-onset sepsis in a neonatal intensive care unit (NICU). A set of personal clinical observations was used as a test set to evaluate the capacity of the model to discriminate between septic and non-septic neonates on the basis of clinical and laboratory findings. Results We show here that matrix memory models with associations modulated by context can perform automatic medical diagnosis. The sequential availability of new information over time makes the system progress in a narrowing process that reduces the range of diagnostic possibilities. At each step the system provides a probabilistic map of the different possible diagnoses to that moment. The system can incorporate the clinical experience, building in that way a representative database of historical data that captures geo-demographical differences between patient populations. The trained model succeeds in diagnosing late-onset sepsis within the test set of infants in the NICU: sensitivity 100%; specificity 80%; percentage of true positives 91%; percentage of true negatives 100%; accuracy (true positives plus true negatives over the totality of patients) 93,3%; and Cohen's kappa index 0,84. Conclusion Context-dependent associative memories can operate as medical expert systems. The model is presented in a simple and tutorial way to encourage straightforward implementations by medical groups. An application with real data, presented as a primary evaluation of the validity and potentiality of the model in medical diagnosis, shows that the model is a highly promising alternative in the development of accuracy diagnostic tools. PMID:17121675

Method for suppressing noise in measurements

NASA Technical Reports Server (NTRS)

Carson, Paul L. (Inventor); Madsen, Louis A. (Inventor); Leskowitz, Garett M. (Inventor); Weitekamp, Daniel P. (Inventor)

2000-01-01

Methods for suppressing noise in measurements by correlating functions based on at least two different measurements of a system at two different times. In one embodiment, a measurement operation is performed on at least a portion of a system that has a memory. A property of the system is measured during a first measurement period to produce a first response indicative of a first state of the system. Then the property of the system is measured during a second measurement period to produce a second response indicative of a second state of the system. The second measurement is performed after an evolution duration subsequent to the first measurement period when the system still retains a degree of memory of an aspect of the first state. Next, a first function of the first response is combined with a second function of the second response to form a second-order correlation function. Information of the system is then extracted from the second-order correlation function.

Processing Semblances Induced through Inter-Postsynaptic Functional LINKs, Presumed Biological Parallels of K-Lines Proposed for Building Artificial Intelligence

PubMed Central

Vadakkan, Kunjumon I.

2011-01-01

The internal sensation of memory, which is available only to the owner of an individual nervous system, is difficult to analyze for its basic elements of operation. We hypothesize that associative learning induces the formation of functional LINK between the postsynapses. During memory retrieval, the activation of either postsynapse re-activates the functional LINK evoking a semblance of sensory activity arriving at its opposite postsynapse, nature of which defines the basic unit of internal sensation – namely, the semblion. In neuronal networks that undergo continuous oscillatory activity at certain levels of their organization re-activation of functional LINKs is expected to induce semblions, enabling the system to continuously learn, self-organize, and demonstrate instantiation, features that can be utilized for developing artificial intelligence (AI). This paper also explains suitability of the inter-postsynaptic functional LINKs to meet the expectations of Minsky’s K-lines, basic elements of a memory theory generated to develop AI and methods to replicate semblances outside the nervous system. PMID:21845180

[Development of a video image system for wireless capsule endoscopes based on DSP].

PubMed

Yang, Li; Peng, Chenglin; Wu, Huafeng; Zhao, Dechun; Zhang, Jinhua

2008-02-01

A video image recorder to record video picture for wireless capsule endoscopes was designed. TMS320C6211 DSP of Texas Instruments Inc. is the core processor of this system. Images are periodically acquired from Composite Video Broadcast Signal (CVBS) source and scaled by video decoder (SAA7114H). Video data is transported from high speed buffer First-in First-out (FIFO) to Digital Signal Processor (DSP) under the control of Complex Programmable Logic Device (CPLD). This paper adopts JPEG algorithm for image coding, and the compressed data in DSP was stored to Compact Flash (CF) card. TMS320C6211 DSP is mainly used for image compression and data transporting. Fast Discrete Cosine Transform (DCT) algorithm and fast coefficient quantization algorithm are used to accelerate operation speed of DSP and decrease the executing code. At the same time, proper address is assigned for each memory, which has different speed;the memory structure is also optimized. In addition, this system uses plenty of Extended Direct Memory Access (EDMA) to transport and process image data, which results in stable and high performance.

PKA increases in the olfactory bulb act as unconditioned stimuli and provide evidence for parallel memory systems: pairing odor with increased PKA creates intermediate- and long-term, but not short-term, memories.

PubMed

Grimes, Matthew T; Harley, Carolyn W; Darby-King, Andrea; McLean, John H

2012-02-21

Neonatal odor-preference memory in rat pups is a well-defined associative mammalian memory model dependent on cAMP. Previous work from this laboratory demonstrates three phases of neonatal odor-preference memory: short-term (translation-independent), intermediate-term (translation-dependent), and long-term (transcription- and translation-dependent). Here, we use neonatal odor-preference learning to explore the role of olfactory bulb PKA in these three phases of mammalian memory. PKA activity increased normally in learning animals 10 min after a single training trial. Inhibition of PKA by Rp-cAMPs blocked intermediate-term and long-term memory, with no effect on short-term memory. PKA inhibition also prevented learning-associated CREB phosphorylation, a transcription factor implicated in long-term memory. When long-term memory was rescued through increased β-adrenoceptor activation, CREB phosphorylation was restored. Intermediate-term and long-term, but not short-term odor-preference memories were generated by pairing odor with direct PKA activation using intrabulbar Sp-cAMPs, which bypasses β-adrenoceptor activation. Higher levels of Sp-cAMPs enhanced memory by extending normal 24-h retention to 48-72 h. These results suggest that increased bulbar PKA is necessary and sufficient for the induction of intermediate-term and long-term odor-preference memory, and suggest that PKA activation levels also modulate memory duration. However, short-term memory appears to use molecular mechanisms other than the PKA/CREB pathway. These mechanisms, which are also recruited by β-adrenoceptor activation, must operate in parallel with PKA activation.

Parameter optimization for transitions between memory states in small arrays of Josephson junctions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rezac, Jacob D.; Imam, Neena; Braiman, Yehuda

Coupled arrays of Josephson junctions possess multiple stable zero voltage states. Such states can store information and consequently can be utilized for cryogenic memory applications. Basic memory operations can be implemented by sending a pulse to one of the junctions and studying transitions between the states. In order to be suitable for memory operations, such transitions between the states have to be fast and energy efficient. Here in this article we employed simulated annealing, a stochastic optimization algorithm, to study parameter optimization of array parameters which minimizes times and energies of transitions between specifically chosen states that can be utilizedmore » for memory operations (Read, Write, and Reset). Simulation results show that such transitions occur with access times on the order of 10–100 ps and access energies on the order of 10 -19–5×10 -18 J. Numerical simulations are validated with approximate analytical results.« less

Neurotoxic impact of mercury on the central nervous system evaluated by neuropsychological tests and on the autonomic nervous system evaluated by dynamic pupillometry.

PubMed

Milioni, Ana Luiza V; Nagy, Balázs V; Moura, Ana Laura A; Zachi, Elaine C; Barboni, Mirella T S; Ventura, Dora F

2017-03-01

Mercury vapor is highly toxic to the human body. The present study aimed to investigate the occurrence of neuropsychological dysfunction in former workers of fluorescent lamps factories that were exposed to mercury vapor (years after cessation of exposure), diagnosed with chronic mercurialism, and to investigate the effects of such exposure on the Autonomic Nervous System (ANS) using the non-invasive method of dynamic pupillometry. The exposed group and a control group matched by age and educational level were evaluated by the Beck Depression Inventory and with the computerized neuropsychological battery CANTABeclipse - subtests of working memory (Spatial Span), spatial memory (Spatial Recognition Memory), visual memory (Pattern Recognition Memory) and action planning (Stockings of Cambridge). The ANS was assessed by dynamic pupillometry, which provides information on the operation on both the sympathetic and parasympathetic functions. Depression scores were significantly higher among the former workers when compared with the control group. The exposed group also showed significantly worse performance in most of the cognitive functions assessed. In the dynamic pupillometry test, former workers showed significantly lower response than the control group in the sympathetic response parameter (time of 75% of pupillary recovery at 10cd/m 2 luminance). Our study found indications that are suggestive of cognitive deficits and losses in sympathetic autonomic activity among patients occupationally exposed to mercury vapor. Copyright © 2016 Elsevier B.V. All rights reserved.

Aerospace Ground Equipment for model 4080 sequence programmer. A standard computer terminal is adapted to provide convenient operator to device interface

NASA Technical Reports Server (NTRS)

Nissley, L. E.

1979-01-01

The Aerospace Ground Equipment (AGE) provides an interface between a human operator and a complete spaceborne sequence timing device with a memory storage program. The AGE provides a means for composing, editing, syntax checking, and storing timing device programs. The AGE is implemented with a standard Hewlett-Packard 2649A terminal system and a minimum of special hardware. The terminal's dual tape interface is used to store timing device programs and to read in special AGE operating system software. To compose a new program for the timing device the keyboard is used to fill in a form displayed on the screen.

Reconfigurable Fault Tolerance for FPGAs

NASA Technical Reports Server (NTRS)

Shuler, Robert, Jr.

2010-01-01

The invention allows a field-programmable gate array (FPGA) or similar device to be efficiently reconfigured in whole or in part to provide higher capacity, non-redundant operation. The redundant device consists of functional units such as adders or multipliers, configuration memory for the functional units, a programmable routing method, configuration memory for the routing method, and various other features such as block RAM, I/O (random access memory, input/output) capability, dedicated carry logic, etc. The redundant device has three identical sets of functional units and routing resources and majority voters that correct errors. The configuration memory may or may not be redundant, depending on need. For example, SRAM-based FPGAs will need some type of radiation-tolerant configuration memory, or they will need triple-redundant configuration memory. Flash or anti-fuse devices will generally not need redundant configuration memory. Some means of loading and verifying the configuration memory is also required. These are all components of the pre-existing redundant FPGA. This innovation modifies the voter to accept a MODE input, which specifies whether ordinary voting is to occur, or if redundancy is to be split. Generally, additional routing resources will also be required to pass data between sections of the device created by splitting the redundancy. In redundancy mode, the voters produce an output corresponding to the two inputs that agree, in the usual fashion. In the split mode, the voters select just one input and convey this to the output, ignoring the other inputs. In a dual-redundant system (as opposed to triple-redundant), instead of a voter, there is some means to latch or gate a state update only when both inputs agree. In this case, the invention would require modification of the latch or gate so that it would operate normally in redundant mode, and would separately latch or gate the inputs in non-redundant mode.

The MK VI - A second generation attitude control system

NASA Astrophysics Data System (ADS)

Meredith, P. J.

1986-10-01

The MK VI, a new multipurpose attitude control system for the exoatmospheric attitude control of sounding rocket payloads, is described. The system employs reprogrammable microcomputer memory for storage of basic control logic and for specific mission event control data. The paper includes descriptions of MK VI specifications and configuration; sensor characteristics; the electronic, analog, and digital sections; the pneumatic system; ground equipment; the system operation; and software. A review of the MK VI performance for the Comet Halley flight is presented. Block diagrams are included.

MEMORY SYSTEMS STUDY. Annual Report No. 2, November 16, 1962 to November 15, 1963

DOE Office of Scientific and Technical Information (OSTI.GOV)

Peterson, G R; DeVries, R C; Melsa, J L

1964-10-31

S>Results of theoretical studies of learning control systems are presented. The need for definitions is discussed and definitions of successful, adaptive, and learning control systems are presented. The basic structural elements of learning control systems are discussed. The environmental characteristics of control situations in which learning may be applicable are discussed. Learning control systems are classified in accordance with the environmental situation in which they might operate. The structure and components suitable to various environmental situations are discussed. (auth)

Recall of patterns using binary and gray-scale autoassociative morphological memories

NASA Astrophysics Data System (ADS)

Sussner, Peter

2005-08-01

Morphological associative memories (MAM's) belong to a class of artificial neural networks that perform the operations erosion or dilation of mathematical morphology at each node. Therefore we speak of morphological neural networks. Alternatively, the total input effect on a morphological neuron can be expressed in terms of lattice induced matrix operations in the mathematical theory of minimax algebra. Neural models of associative memories are usually concerned with the storage and the retrieval of binary or bipolar patterns. Thus far, the emphasis in research on morphological associative memory systems has been on binary models, although a number of notable features of autoassociative morphological memories (AMM's) such as optimal absolute storage capacity and one-step convergence have been shown to hold in the general, gray-scale setting. In previous papers, we gained valuable insight into the storage and recall phases of AMM's by analyzing their fixed points and basins of attraction. We have shown in particular that the fixed points of binary AMM's correspond to the lattice polynomials in the original patterns. This paper extends these results in the following ways. In the first place, we provide an exact characterization of the fixed points of gray-scale AMM's in terms of combinations of the original patterns. Secondly, we present an exact expression for the fixed point attractor that represents the output of either a binary or a gray-scale AMM upon presentation of a certain input. The results of this paper are confirmed in several experiments using binary patterns and gray-scale images.

Biologically inspired autonomous structural materials with controlled toughening and healing

NASA Astrophysics Data System (ADS)

Garcia, Michael E.; Sodano, Henry A.

2010-04-01

The field of structural health monitoring (SHM) has made significant contributions in the field of prognosis and damage detection in the past decade. The advantageous use of this technology has not been integrated into operational structures to prevent damage from propagating or to heal injured regions under real time loading conditions. Rather, current systems relay this information to a central processor or human operator, who then determines a course of action such as altering the mission or scheduling repair maintenance. Biological systems exhibit advanced sensory and healing traits that can be applied to the design of material systems. For instance, bone is the major structural component in vertebrates; however, unlike modern structural materials, bone has many properties that make it effective for arresting the propagation of cracks and subsequent healing of the fractured area. The foremost goal for the development of future adaptive structures is to mimic biological systems, similar to bone, such that the material system can detect damage and deploy defensive traits to impede damage from propagating, thus preventing catastrophic failure while in operation. After sensing and stalling the propagation of damage, the structure must then be repaired autonomously using self healing mechanisms motivated by biological systems. Here a novel autonomous system is developed using shape memory polymers (SMPs), that employs an optical fiber network as both a damage detection sensor and a network to deliver stimulus to the damage site initiating adaptation and healing. In the presence of damage the fiber optic fractures allowing a high power laser diode to deposit a controlled level of thermal energy at the fractured sight locally reducing the modulus and blunting the crack tip, which significantly slows the crack growth rate. By applying a pre-induced strain field and utilizing the shape memory recovery effect, thermal energy can be deployed to close the crack and return the system to its original operating state. The entire system will effectively detect, self toughen, and subsequently heal damage as biological materials such as bone does.

78 FR 44881 - Drawbridge Operation Regulation; York River, Between Yorktown and Gloucester Point, VA

Federal Register 2010, 2011, 2012, 2013, 2014

2013-07-25

... deviation from the operating schedule that governs the operation of the Coleman Memorial Bridge (US 17/George P. Coleman Memorial Swing Bridge) across the York River, mile 7.0, between Gloucester Point and Yorktown, VA. This deviation is necessary to facilitate maintenance work on the moveable spans on the...

An Ultralow-Power Sleep Spindle Detection System on Chip.

PubMed

Iranmanesh, Saam; Rodriguez-Villegas, Esther

2017-08-01

This paper describes a full system-on-chip to automatically detect sleep spindle events from scalp EEG signals. These events, which are known to play an important role on memory consolidation during sleep, are also characteristic of a number of neurological diseases. The operation of the system is based on a previously reported algorithm, which used the Teager energy operator, together with the Spectral Edge Frequency (SEF50) achieving more than 70% sensitivity and 98% specificity. The algorithm is now converted into a hardware analog based customized implementation in order to achieve extremely low levels of power. Experimental results prove that the system, which is fabricated in a 0.18 μm CMOS technology, is able to operate from a 1.25 V power supply consuming only 515 nW, with an accuracy that is comparable to its software counterpart.

Avoiding and tolerating latency in large-scale next-generation shared-memory multiprocessors

NASA Technical Reports Server (NTRS)

Probst, David K.

1993-01-01

A scalable solution to the memory-latency problem is necessary to prevent the large latencies of synchronization and memory operations inherent in large-scale shared-memory multiprocessors from reducing high performance. We distinguish latency avoidance and latency tolerance. Latency is avoided when data is brought to nearby locales for future reference. Latency is tolerated when references are overlapped with other computation. Latency-avoiding locales include: processor registers, data caches used temporally, and nearby memory modules. Tolerating communication latency requires parallelism, allowing the overlap of communication and computation. Latency-tolerating techniques include: vector pipelining, data caches used spatially, prefetching in various forms, and multithreading in various forms. Relaxing the consistency model permits increased use of avoidance and tolerance techniques. Each model is a mapping from the program text to sets of partial orders on program operations; it is a convention about which temporal precedences among program operations are necessary. Information about temporal locality and parallelism constrains the use of avoidance and tolerance techniques. Suitable architectural primitives and compiler technology are required to exploit the increased freedom to reorder and overlap operations in relaxed models.

Considerations in Physiological Metric Selection for Online Detection of Operator State: A Case Study

DTIC Science & Technology

2016-07-17

e.g., we omit functional magnetic resonance imaging; fMRI ). Researchers have investigated fatigue and related constructs using several different...integration and links to underlying memory systems. Personality and So- cial Psychology Review, 4(2), 108–131. 26. Prinzel, L. J., Freeman, F. G

Hardware packet pacing using a DMA in a parallel computer

DOEpatents

Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

2013-08-13

Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.

Cognitive Theory within the Framework of an Information Processing Model and Learning Hierarchy: Viable Alternative to the Bloom-Mager System.

ERIC Educational Resources Information Center

Stahl, Robert J.

This review of the current status of the human information processing model presents the Stahl Perceptual Information Processing and Operations Model (SPInPrOM) as a model of how thinking, memory, and the processing of information take place within the individual learner. A related system, the Domain of Cognition, is presented as an alternative to…

Models of Physiology/Cognition Relations: Their Prevalence in the Literature and Their Utility in Examining the Effect of Blood Pressure on Vocabulary and Memory for Designs.

ERIC Educational Resources Information Center

Sinnott, Jan D.; And Others

Interest in physiology/cognition relations is increasing, in step with the realization that the individual ages as a whole, adaptive, living system. If a physiological system declines, a person's cognitive abilities may be reduced, unless some compensatory mechanism operates. Understanding this set of relationships permits potential interventions.…

ART/Ada design project, phase 1: Project plan

NASA Technical Reports Server (NTRS)

Allen, Bradley P.

1988-01-01

The plan and schedule for Phase 1 of the Ada based ESBT Design Research Project is described. The main platform for the project is a DEC Ada compiler on VAX mini-computers and VAXstations running the Virtual Memory System (VMS) operating system. The Ada effort and lines of code are given in tabular form. A chart is given of the entire project life cycle.

Working Memory and Reinforcement Schedule Jointly Determine Reinforcement Learning in Children: Potential Implications for Behavioral Parent Training

PubMed Central

Segers, Elien; Beckers, Tom; Geurts, Hilde; Claes, Laurence; Danckaerts, Marina; van der Oord, Saskia

2018-01-01

Introduction: Behavioral Parent Training (BPT) is often provided for childhood psychiatric disorders. These disorders have been shown to be associated with working memory impairments. BPT is based on operant learning principles, yet how operant principles shape behavior (through the partial reinforcement (PRF) extinction effect, i.e., greater resistance to extinction that is created when behavior is reinforced partially rather than continuously) and the potential role of working memory therein is scarcely studied in children. This study explored the PRF extinction effect and the role of working memory therein using experimental tasks in typically developing children. Methods: Ninety-seven children (age 6–10) completed a working memory task and an operant learning task, in which children acquired a response-sequence rule under either continuous or PRF (120 trials), followed by an extinction phase (80 trials). Data of 88 children were used for analysis. Results: The PRF extinction effect was confirmed: We observed slower acquisition and extinction in the PRF condition as compared to the continuous reinforcement (CRF) condition. Working memory was negatively related to acquisition but not extinction performance. Conclusion: Both reinforcement contingencies and working memory relate to acquisition performance. Potential implications for BPT are that decreasing working memory load may enhance the chance of optimally learning through reinforcement. PMID:29643822

A compact superconducting nanowire memory element operated by nanowire cryotrons

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; Toomey, Emily A.; Butters, Brenden A.; McCaughan, Adam N.; Dane, Andrew E.; Nam, Sae-Woo; Berggren, Karl K.

2018-07-01

A superconducting loop stores persistent current without any ohmic loss, making it an ideal platform for energy efficient memories. Conventional superconducting memories use an architecture based on Josephson junctions (JJs) and have demonstrated access times less than 10 ps and power dissipation as low as 10-19 J. However, their scalability has been slow to develop due to the challenges in reducing the dimensions of JJs and minimizing the area of the superconducting loops. In addition to the memory itself, complex readout circuits require additional JJs and inductors for coupling signals, increasing the overall area. Here, we have demonstrated a superconducting memory based solely on lithographic nanowires. The small dimensions of the nanowire ensure that the device can be fabricated in a dense area in multiple layers, while the high kinetic inductance makes the loop essentially independent of geometric inductance, allowing it to be scaled down without sacrificing performance. The memory is operated by a group of nanowire cryotrons patterned alongside the storage loop, enabling us to reduce the entire memory cell to 3 μm × 7 μm in our proof-of-concept device. In this work we present the operation principles of a superconducting nanowire memory (nMem) and characterize its bit error rate, speed, and power dissipation.