Effects of ultrathin oxides in conducting MIS structures on GaAs

NASA Technical Reports Server (NTRS)

Childs, R. B.; Ruths, J. M.; Sullivan, T. E.; Fonash, S. J.

1978-01-01

Schottky barrier-type GaAs baseline devices (semiconductor surface etched and then immediately metalized) and GaAs conducting metal oxide-semiconductor devices are fabricated and characterized. The baseline surfaces (no purposeful oxide) are prepared by a basic or an acidic etch, while the surface for the MIS devices are prepared by oxidizing after the etch step. The metallizations used are thin-film Au, Ag, Pd, and Al. It is shown that the introduction of purposeful oxide into these Schottky barrier-type structures examined on n-type GaAs modifies the barrier formation, and that thin interfacial layers can modify barrier formation through trapping and perhaps chemical reactions. For Au- and Pd-devices, enhanced photovoltaic performance of the MIS configuration is due to increased barrier height.

Efficient semiconductor light-emitting device and method

DOEpatents

Choquette, Kent D.; Lear, Kevin L.; Schneider, Jr., Richard P.

1996-01-01

A semiconductor light-emitting device and method. The semiconductor light-emitting device is provided with at least one control layer or control region which includes an annular oxidized portion thereof to channel an injection current into the active region, and to provide a lateral refractive index profile for index guiding the light generated within the device. A periodic composition grading of at least one of the mirror stacks in the device provides a reduced operating voltage of the device. The semiconductor light-emitting device has a high efficiency for light generation, and may be formed either as a resonant-cavity light-emitting diode (RCLED) or as a vertical-cavity surface-emitting laser (VCSEL).

Efficient semiconductor light-emitting device and method

DOEpatents

Choquette, K.D.; Lear, K.L.; Schneider, R.P. Jr.

1996-02-20

A semiconductor light-emitting device and method are disclosed. The semiconductor light-emitting device is provided with at least one control layer or control region which includes an annular oxidized portion thereof to channel an injection current into the active region, and to provide a lateral refractive index profile for index guiding the light generated within the device. A periodic composition grading of at least one of the mirror stacks in the device provides a reduced operating voltage of the device. The semiconductor light-emitting device has a high efficiency for light generation, and may be formed either as a resonant-cavity light-emitting diode (RCLED) or as a vertical-cavity surface-emitting laser (VCSEL). 12 figs.

Ionic Liquid Activation of Amorphous Metal-Oxide Semiconductors for Flexible Transparent Electronic Devices

DOE PAGES

Pudasaini, Pushpa Raj; Noh, Joo Hyon; Wong, Anthony T.; ...

2016-02-09

To begin this abstract, amorphous metal-oxide semiconductors offer the high carrier mobilities and excellent large-area uniformity required for high performance, transparent, flexible electronic devices; however, a critical bottleneck to their widespread implementation is the need to activate these materials at high temperatures which are not compatible with flexible polymer substrates. The highly controllable activation of amorphous indium gallium zinc oxide semiconductor channels using ionic liquid gating at room temperature is reported. Activation is controlled by electric field-induced oxygen migration across the ionic liquid-semiconductor interface. In addition to activation of unannealed devices, it is shown that threshold voltages of a transistormore » can be linearly tuned between the enhancement and depletion modes. Finally, the first ever example of transparent flexible thin film metal oxide transistor on a polyamide substrate created using this simple technique is demonstrated. Finally, this study demonstrates the potential of field-induced activation as a promising alternative to traditional postdeposition thermal annealing which opens the door to wide scale implementation into flexible electronic applications.« less

Multi-layer MOS capacitor based polarization insensitive electro-optic intensity modulator.

PubMed

Qiu, Xiaoming; Ruan, Xiaoke; Li, Yanping; Zhang, Fan

2018-05-28

In this study, a multi-layer metal-oxide-semiconductor capacitor (MLMOSC) polarization insensitive modulator is proposed. The design is validated by numerical simulation with commercial software LUMERICAL SOLUTION. Based on the epsilon-near-zero (ENZ) effect of indium tin oxide (ITO), the device manages to uniformly modulate both the transverse electric (TE) and the transverse magnetic (TM) modes. With a 20μm-long double-layer metal-oxide-semiconductor capacitor (DLMOSC) polarization insensitive modulator, in which two metal-oxide-semiconductor (MOS) structures are formed by the n-doped Si/HfO 2 /ITO/HfO 2 / n-doped Si stack, the extinction ratios (ERs) of both the TE and the TM modes can be over 20dB. The polarization dependent losses of the device can be as low as 0.05dB for the "OFF" state and 0.004dB for the "ON" state. Within 1dB polarization dependent loss, the device can operate with over 20dB ERs at the S, C, and L bands. The polarization insensitive modulator offers various merits including ultra-compact size, broadband spectrum, and complementary metal oxide semiconductor (CMOS) compatibility.

Radiation hardening of MOS devices by boron. [for stabilizing gate threshold potential of field effect device

NASA Technical Reports Server (NTRS)

Danchenko, V. (Inventor)

1974-01-01

A technique is described for radiation hardening of MOS devices and specifically for stabilizing the gate threshold potential at room temperature of a radiation subjected MOS field-effect device with a semiconductor substrate, an insulating layer of oxide on the substrate, and a gate electrode disposed on the insulating layer. The boron is introduced within a layer of the oxide of about 100 A-300 A thickness immediately adjacent the semiconductor-insulator interface. The concentration of boron in the oxide layer is preferably maintained on the order of 10 to the 18th power atoms/cu cm. The technique serves to reduce and substantially annihilate radiation induced positive gate charge accumulations.

Band-Gap Engineering at a Semiconductor-Crystalline Oxide Interface

DOE PAGES

Jahangir-Moghadam, Mohammadreza; Ahmadi-Majlan, Kamyar; Shen, Xuan; ...

2015-02-09

The epitaxial growth of crystalline oxides on semiconductors provides a pathway to introduce new functionalities to semiconductor devices. Key to integrating the functionalities of oxides onto semiconductors is controlling the band alignment at interfaces between the two materials. Here we apply principles of band gap engineering traditionally used at heterojunctions between conventional semiconductors to control the band offset between a single crystalline oxide and a semiconductor. Reactive molecular beam epitaxy is used to realize atomically abrupt and structurally coherent interfaces between SrZr xTi 1-xO₃ and Ge, in which the band gap of the former is enhanced with Zr content x.more » We present structural and electrical characterization of SrZr xTi 1-xO₃-Ge heterojunctions and demonstrate a type-I band offset can be achieved. These results demonstrate that band gap engineering can be exploited to realize functional semiconductor crystalline oxide heterojunctions.« less

Electrical Characterization of Semiconductor Materials and Devices

NASA Astrophysics Data System (ADS)

Deen, M.; Pascal, Fabien

Semiconductor materials and devices continue to occupy a preeminent technological position due to their importance when building integrated electronic systems used in a wide range of applications from computers, cell-phones, personal digital assistants, digital cameras and electronic entertainment systems, to electronic instrumentation for medical diagnositics and environmental monitoring. Key ingredients of this technological dominance have been the rapid advances made in the quality and processing of materials - semiconductors, conductors and dielectrics - which have given metal oxide semiconductor device technology its important characteristics of negligible standby power dissipation, good input-output isolation, surface potential control and reliable operation. However, when assessing material quality and device reliability, it is important to have fast, nondestructive, accurate and easy-to-use electrical characterization techniques available, so that important parameters such as carrier doping density, type and mobility of carriers, interface quality, oxide trap density, semiconductor bulk defect density, contact and other parasitic resistances and oxide electrical integrity can be determined. This chapter describes some of the more widely employed and popular techniques that are used to determine these important parameters. The techniques presented in this chapter range in both complexity and test structure requirements from simple current-voltage measurements to more sophisticated low-frequency noise, charge pumping and deep-level transient spectroscopy techniques.

Analysis of fluctuations in semiconductor devices

NASA Astrophysics Data System (ADS)

Andrei, Petru

The random nature of ion implantation and diffusion processes as well as inevitable tolerances in fabrication result in random fluctuations of doping concentrations and oxide thickness in semiconductor devices. These fluctuations are especially pronounced in ultrasmall (nanoscale) semiconductor devices when the spatial scale of doping and oxide thickness variations become comparable with the geometric dimensions of devices. In the dissertation, the effects of these fluctuations on device characteristics are analyzed by using a new technique for the analysis of random doping and oxide thickness induced fluctuations. This technique is universal in nature in the sense that it is applicable to any transport model (drift-diffusion, semiclassical transport, quantum transport etc.) and it can be naturally extended to take into account random fluctuations of the oxide (trapped) charges and channel length. The technique is based on linearization of the transport equations with respect to the fluctuating quantities. It is computationally much (a few orders of magnitude) more efficient than the traditional Monte-Carlo approach and it yields information on the sensitivity of fluctuations of parameters of interest (e.g. threshold voltage, small-signal parameters, cut-off frequencies, etc.) to the locations of doping and oxide thickness fluctuations. For this reason, it can be very instrumental in the design of fluctuation-resistant structures of semiconductor devices. Quantum mechanical effects are taken into account by using the density-gradient model as well as through self-consistent Poisson-Schrodinger computations. Special attention is paid to the presenting of the technique in a form that is suitable for implementation on commercial device simulators. The numerical implementation of the technique is discussed in detail and numerous computational results are presented and compared with those previously published in literature.

Water soluble nano-scale transient material germanium oxide for zero toxic waste based environmentally benign nano-manufacturing

NASA Astrophysics Data System (ADS)

Almuslem, A. S.; Hanna, A. N.; Yapici, T.; Wehbe, N.; Diallo, E. M.; Kutbee, A. T.; Bahabry, R. R.; Hussain, M. M.

2017-02-01

In the recent past, with the advent of transient electronics for mostly implantable and secured electronic applications, the whole field effect transistor structure has been dissolved in a variety of chemicals. Here, we show simple water soluble nano-scale (sub-10 nm) germanium oxide (GeO2) as the dissolvable component to remove the functional structures of metal oxide semiconductor devices and then reuse the expensive germanium substrate again for functional device fabrication. This way, in addition to transiency, we also show an environmentally friendly manufacturing process for a complementary metal oxide semiconductor (CMOS) technology. Every year, trillions of complementary metal oxide semiconductor (CMOS) electronics are manufactured and billions are disposed, which extend the harmful impact to our environment. Therefore, this is a key study to show a pragmatic approach for water soluble high performance electronics for environmentally friendly manufacturing and bioresorbable electronic applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moghadam, Reza M.; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to low-power field-effect devices that can be used for logic or memory. Essential to realizing such field-effect devices is the development of ferroelectric metal-oxide-semiconductor (MOS) capacitors, in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel. Here we demonstrate that ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x= 0.7) that has been epitaxially grown on Ge. We find that themore » ferroelectric properties of SrZrxTi1-xO3 are exceptionally robust, as gate layers as thin as 5 nm give rise to hysteretic capacitance-voltage characteristics that are 2 V in width. The development of ferroelectric MOS capacitors with gate thicknesses that are technologically relevant opens a pathway to realize scalable ferroelectric field-effect devices.« less

All oxide semiconductor-based bidirectional vertical p-n-p selectors for 3D stackable crossbar-array electronics

PubMed Central

Bae, Yoon Cheol; Lee, Ah Rahm; Baek, Gwang Ho; Chung, Je Bock; Kim, Tae Yoon; Park, Jea Gun; Hong, Jin Pyo

2015-01-01

Three-dimensional (3D) stackable memory devices including nano-scaled crossbar array are central for the realization of high-density non-volatile memory electronics. However, an essential sneak path issue affecting device performance in crossbar array remains a bottleneck and a grand challenge. Therefore, a suitable bidirectional selector as a two-way switch is required to facilitate a major breakthrough in the 3D crossbar array memory devices. Here, we show the excellent selectivity of all oxide p-/n-type semiconductor-based p-n-p open-based bipolar junction transistors as selectors in crossbar memory array. We report that bidirectional nonlinear characteristics of oxide p-n-p junctions can be highly enhanced by manipulating p-/n-type oxide semiconductor characteristics. We also propose an associated Zener tunneling mechanism that explains the unique features of our p-n-p selector. Our experimental findings are further extended to confirm the profound functionality of oxide p-n-p selectors integrated with several bipolar resistive switching memory elements working as storage nodes. PMID:26289565

Electrical properties of solid-solution SrZrxTi1-xO3 grown epitaxially on Ge by molecular beam epitaxy

NASA Astrophysics Data System (ADS)

Moghadam, Reza; Ahmadi, Kamyar; Xiao, Z.-Y.; Hong, Xia; Ngai, Joseph

The epitaxial growth of crystalline oxides on semiconductors enables new functionalities to be introduced to semiconductor devices. In particular, dielectric and ferroelectric oxides grown epitaxially on semiconductors provide a pathway to realize ultra-low power logic and memory devices. Here we present electrical characterization of solid-solution SrZrxTi1-xO3 grown epitaxially on Ge through oxide molecular beam epitaxy. SrZrxTi1-xO3 is of particular interest since the band offset with respect to the semiconductor can be tuned through Zr content x. We will present current-voltage, capacitance-voltage and piezoforce microscopy characterization of SrZrxTi1-xO3 -Ge heterojunctions. In particular, we will discuss how the electrical characteristics of SrZrxTi1-xO3 -Ge heterojunctions evolve with respect to composition, annealing and film thickness.

Photovoltaic devices comprising zinc stannate buffer layer and method for making

DOEpatents

Wu, Xuanzhi; Sheldon, Peter; Coutts, Timothy J.

2001-01-01

A photovoltaic device has a buffer layer zinc stannate Zn.sub.2 SnO.sub.4 disposed between the semiconductor junction structure and the transparent conducting oxide (TCO) layer to prevent formation of localized junctions with the TCO through a thin window semiconductor layer, to prevent shunting through etched grain boundaries of semiconductors, and to relieve stresses and improve adhesion between these layers.

ROLE OF THE NETWORK FORMER IN SEMICONDUCTING OXIDE GLASSES.

DTIC Science & Technology

SEMICONDUCTOR DEVICES, * GLASS ), (*ELECTRICAL NETWORKS, GLASS ), ELECTRICAL PROPERTIES, SEEBECK EFFECT, BORATES, PHOSPHATES, ELECTRICAL RESISTANCE, X RAY DIFFRACTION, ANNEALING, OXIDATION, OXIDES, ELECTRODES, VANADIUM

Metal oxide semiconductor thin-film transistors for flexible electronics

NASA Astrophysics Data System (ADS)

Petti, Luisa; Münzenrieder, Niko; Vogt, Christian; Faber, Hendrik; Büthe, Lars; Cantarella, Giuseppe; Bottacchi, Francesca; Anthopoulos, Thomas D.; Tröster, Gerhard

2016-06-01

The field of flexible electronics has rapidly expanded over the last decades, pioneering novel applications, such as wearable and textile integrated devices, seamless and embedded patch-like systems, soft electronic skins, as well as imperceptible and transient implants. The possibility to revolutionize our daily life with such disruptive appliances has fueled the quest for electronic devices which yield good electrical and mechanical performance and are at the same time light-weight, transparent, conformable, stretchable, and even biodegradable. Flexible metal oxide semiconductor thin-film transistors (TFTs) can fulfill all these requirements and are therefore considered the most promising technology for tomorrow's electronics. This review reflects the establishment of flexible metal oxide semiconductor TFTs, from the development of single devices, large-area circuits, up to entirely integrated systems. First, an introduction on metal oxide semiconductor TFTs is given, where the history of the field is revisited, the TFT configurations and operating principles are presented, and the main issues and technological challenges faced in the area are analyzed. Then, the recent advances achieved for flexible n-type metal oxide semiconductor TFTs manufactured by physical vapor deposition methods and solution-processing techniques are summarized. In particular, the ability of flexible metal oxide semiconductor TFTs to combine low temperature fabrication, high carrier mobility, large frequency operation, extreme mechanical bendability, together with transparency, conformability, stretchability, and water dissolubility is shown. Afterward, a detailed analysis of the most promising metal oxide semiconducting materials developed to realize the state-of-the-art flexible p-type TFTs is given. Next, the recent progresses obtained for flexible metal oxide semiconductor-based electronic circuits, realized with both unipolar and complementary technology, are reported. In particular, the realization of large-area digital circuitry like flexible near field communication tags and analog integrated circuits such as bendable operational amplifiers is presented. The last topic of this review is devoted for emerging flexible electronic systems, from foldable displays, power transmission elements to integrated systems for large-area sensing and data storage and transmission. Finally, the conclusions are drawn and an outlook over the field with a prediction for the future is provided.

Metal oxide semiconductor thin-film transistors for flexible electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Petti, Luisa; Vogt, Christian; Büthe, Lars

The field of flexible electronics has rapidly expanded over the last decades, pioneering novel applications, such as wearable and textile integrated devices, seamless and embedded patch-like systems, soft electronic skins, as well as imperceptible and transient implants. The possibility to revolutionize our daily life with such disruptive appliances has fueled the quest for electronic devices which yield good electrical and mechanical performance and are at the same time light-weight, transparent, conformable, stretchable, and even biodegradable. Flexible metal oxide semiconductor thin-film transistors (TFTs) can fulfill all these requirements and are therefore considered the most promising technology for tomorrow's electronics. This reviewmore » reflects the establishment of flexible metal oxide semiconductor TFTs, from the development of single devices, large-area circuits, up to entirely integrated systems. First, an introduction on metal oxide semiconductor TFTs is given, where the history of the field is revisited, the TFT configurations and operating principles are presented, and the main issues and technological challenges faced in the area are analyzed. Then, the recent advances achieved for flexible n-type metal oxide semiconductor TFTs manufactured by physical vapor deposition methods and solution-processing techniques are summarized. In particular, the ability of flexible metal oxide semiconductor TFTs to combine low temperature fabrication, high carrier mobility, large frequency operation, extreme mechanical bendability, together with transparency, conformability, stretchability, and water dissolubility is shown. Afterward, a detailed analysis of the most promising metal oxide semiconducting materials developed to realize the state-of-the-art flexible p-type TFTs is given. Next, the recent progresses obtained for flexible metal oxide semiconductor-based electronic circuits, realized with both unipolar and complementary technology, are reported. In particular, the realization of large-area digital circuitry like flexible near field communication tags and analog integrated circuits such as bendable operational amplifiers is presented. The last topic of this review is devoted for emerging flexible electronic systems, from foldable displays, power transmission elements to integrated systems for large-area sensing and data storage and transmission. Finally, the conclusions are drawn and an outlook over the field with a prediction for the future is provided.« less

The influence of interfacial defects on fast charge trapping in nanocrystalline oxide-semiconductor thin film transistors

NASA Astrophysics Data System (ADS)

Kim, Taeho; Hur, Jihyun; Jeon, Sanghun

2016-05-01

Defects in oxide semiconductors not only influence the initial device performance but also affect device reliability. The front channel is the major carrier transport region during the transistor turn-on stage, therefore an understanding of defects located in the vicinity of the interface is very important. In this study, we investigated the dynamics of charge transport in a nanocrystalline hafnium-indium-zinc-oxide thin-film transistor (TFT) by short pulse I-V, transient current and 1/f noise measurement methods. We found that the fast charging behavior of the tested device stems from defects located in both the front channel and the interface, following a multi-trapping mechanism. We found that a silicon-nitride stacked hafnium-indium-zinc-oxide TFT is vulnerable to interfacial charge trapping compared with silicon-oxide counterpart, causing significant mobility degradation and threshold voltage instability. The 1/f noise measurement data indicate that the carrier transport in a silicon-nitride stacked TFT device is governed by trapping/de-trapping processes via defects in the interface, while the silicon-oxide device follows the mobility fluctuation model.

Oxide semiconductor thin-film transistors: a review of recent advances.

PubMed

Fortunato, E; Barquinha, P; Martins, R

2012-06-12

Transparent electronics is today one of the most advanced topics for a wide range of device applications. The key components are wide bandgap semiconductors, where oxides of different origins play an important role, not only as passive component but also as active component, similar to what is observed in conventional semiconductors like silicon. Transparent electronics has gained special attention during the last few years and is today established as one of the most promising technologies for leading the next generation of flat panel display due to its excellent electronic performance. In this paper the recent progress in n- and p-type oxide based thin-film transistors (TFT) is reviewed, with special emphasis on solution-processed and p-type, and the major milestones already achieved with this emerging and very promising technology are summarizeed. After a short introduction where the main advantages of these semiconductors are presented, as well as the industry expectations, the beautiful history of TFTs is revisited, including the main landmarks in the last 80 years, finishing by referring to some papers that have played an important role in shaping transparent electronics. Then, an overview is presented of state of the art n-type TFTs processed by physical vapour deposition methods, and finally one of the most exciting, promising, and low cost but powerful technologies is discussed: solution-processed oxide TFTs. Moreover, a more detailed focus analysis will be given concerning p-type oxide TFTs, mainly centred on two of the most promising semiconductor candidates: copper oxide and tin oxide. The most recent data related to the production of complementary metal oxide semiconductor (CMOS) devices based on n- and p-type oxide TFT is also be presented. The last topic of this review is devoted to some emerging applications, finalizing with the main conclusions. Related work that originated at CENIMAT|I3N during the last six years is included in more detail, which has led to the fabrication of high performance n- and p-type oxide transistors as well as the fabrication of CMOS devices with and on paper. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High-performance all-printed amorphous oxide FETs and logics with electronically compatible electrode/ channel interface.

PubMed

Sharma, Bhupendra Kumar; Stoesser, Anna; Mondal, Sandeep Kumar; Garlapati, Suresh K; Fawey, Mohammed H; Chakravadhanula, Venkata Sai Kiran; Kruk, Robert; Hahn, Horst; Dasgupta, Subho

2018-06-12

Oxide semiconductors typically show superior device performance compared to amorphous silicon or organic counterparts, especially, when they are physical vapor deposited. However, it is not easy to reproduce identical device characteristics when the oxide field-effect transistors (FETs) are solution-processed/ printed; the level of complexity further intensifies with the need to print the passive elements as well. Here, we developed a protocol for designing the most electronically compatible electrode/ channel interface based on the judicious material selection. Exploiting this newly developed fabrication schemes, we are now able to demonstrate high-performance all-printed FETs and logic circuits using amorphous indium-gallium-zinc oxide (a-IGZO) semiconductor, indium tin oxide (ITO) as electrodes and composite solid polymer electrolyte as the gate insulator. Interestingly, all-printed FETs demonstrate an optimal electrical performance in terms of threshold voltages and device mobility and may very well be compared with devices fabricated using sputtered ITO electrodes. This observation originates from the selection of electrode/ channel materials from the same transparent semiconductor oxide family, resulting in the formation of In-Sn-Zn-O (ITZO) based diffused a-IGZO/ ITO interface that controls doping density while ensuring high electrical performance. Compressive spectroscopic studies reveal that Sn doping mediated excellent band alignment of IGZO with ITO electrodes is responsible for the excellent device performance observed. All-printed n-MOS based logic circuits have also been demonstrated towards new-generation portable electronics.

Semiconductor/High-Tc-Superconductor Hybrid ICs

NASA Technical Reports Server (NTRS)

Burns, Michael J.

1995-01-01

Hybrid integrated circuits (ICs) containing both Si-based semiconducting and YBa(2)Cu(3)O(7-x) superconducting circuit elements on sapphire substrates developed. Help to prevent diffusion of Cu from superconductors into semiconductors. These hybrid ICs combine superconducting and semiconducting features unavailable in superconducting or semiconducting circuitry alone. For example, complementary metal oxide/semiconductor (CMOS) readout and memory devices integrated with fast-switching Josephson-junction super-conducting logic devices and zero-resistance interconnections.

Methods to Account for Accelerated Semi-Conductor Device Wearout in Longlife Aerospace Applications

DTIC Science & Technology

2003-01-01

Vasi, “Device scalling effects on hot-carrier induced interface and oxide-trappoing charge distributions in MOSFETs,” IEEE Transactions on Electron...Symposium Proceedings, pp. 248–254, 2002. [104] S. I. A. ( SIA ), “International technology roadmap for semiconductors.” <www.semichips.org>, 1999. 113

Damage free Ar ion plasma surface treatment on In{sub 0.53}Ga{sub 0.47}As-on-silicon metal-oxide-semiconductor device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Koh, Donghyi; Shin, Seung Heon; Ahn, Jaehyun

2015-11-02

In this paper, we investigated the effect of in-situ Ar ion plasma surface pre-treatment in order to improve the interface properties of In{sub 0.53}Ga{sub 0.47}As for high-κ top-gate oxide deposition. X-ray photoelectron spectroscopy (XPS) and metal-oxide-semiconductor capacitors (MOSCAPs) demonstrate that Ar ion treatment removes the native oxide on In{sub 0.53}Ga{sub 0.47}As. The XPS spectra of Ar treated In{sub 0.53}Ga{sub 0.47}As show a decrease in the AsO{sub x} and GaO{sub x} signal intensities, and the MOSCAPs show higher accumulation capacitance (C{sub acc}), along with reduced frequency dispersion. In addition, Ar treatment is found to suppress the interface trap density (D{sub it}),more » which thereby led to a reduction in the threshold voltage (V{sub th}) degradation during constant voltage stress and relaxation. These results outline the potential of surface treatment for III-V channel metal-oxide-semiconductor devices and application to non-planar device process.« less

Zinc oxide and related compounds: order within the disorder

NASA Astrophysics Data System (ADS)

Martins, R.; Pereira, Luisa; Barquinha, P.; Ferreira, I.; Prabakaran, R.; Goncalves, G.; Goncalves, A.; Fortunato, E.

2009-02-01

This paper discusses the effect of order and disorder on the electrical and optical performance of ionic oxide semiconductors based on zinc oxide. These materials are used as active thin films in electronic devices such as pn heterojunction solar cells and thin-film transistors. Considering the expected conduction mechanism in ordered and disordered semiconductors the role of the spherical symmetry of the s electron conduction bands will be analyzed and compared to covalent semiconductors. The obtained results show p-type c-Si/a-IZO/poly-ZGO solar cells exhibiting efficiencies above 14%, in device areas of about 2.34 cm2. Amorphous oxide TFTs based on the Ga-Zn-Sn-O system demonstrate superior performance than the polycrystalline TFTs based on ZnO, translated by ION/IOFF ratio exceeding 107, turn-on voltage below 1-2 V and saturation mobility above 25 cm2/Vs. Apart from that, preliminary data on p-type oxide TFT based on the Zn-Cu-O system will also be presented.

Low temperature processed complementary metal oxide semiconductor (CMOS) device by oxidation effect from capping layer.

PubMed

Wang, Zhenwei; Al-Jawhari, Hala A; Nayak, Pradipta K; Caraveo-Frescas, J A; Wei, Nini; Hedhili, M N; Alshareef, H N

2015-04-20

In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190 °C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

PubMed Central

Wang, Zhenwei; Al-Jawhari, Hala A.; Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wei, Nini; Hedhili, M. N.; Alshareef, H. N.

2015-01-01

In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field. PMID:25892711

Low-voltage organic electronics based on a gate-tunable injection barrier in vertical graphene-organic semiconductor heterostructures.

PubMed

Hlaing, Htay; Kim, Chang-Hyun; Carta, Fabio; Nam, Chang-Yong; Barton, Rob A; Petrone, Nicholas; Hone, James; Kymissis, Ioannis

2015-01-14

The vertical integration of graphene with inorganic semiconductors, oxide semiconductors, and newly emerging layered materials has recently been demonstrated as a promising route toward novel electronic and optoelectronic devices. Here, we report organic thin film transistors based on vertical heterojunctions of graphene and organic semiconductors. In these thin heterostructure devices, current modulation is accomplished by tuning of the injection barriers at the semiconductor/graphene interface with the application of a gate voltage. N-channel devices fabricated with a thin layer of C60 show a room temperature on/off ratio >10(4) and current density of up to 44 mAcm(-2). Because of the ultrashort channel intrinsic to the vertical structure, the device is fully operational at a driving voltage of 200 mV. A complementary p-channel device is also investigated, and a logic inverter based on two complementary transistors is demonstrated. The vertical integration of graphene with organic semiconductors via simple, scalable, and low-temperature fabrication processes opens up new opportunities to realize flexible, transparent organic electronic, and optoelectronic devices.

Self bleaching photoelectrochemical-electrochromic device

DOEpatents

Bechinger, Clemens S.; Gregg, Brian A.

2002-04-09

A photoelectrochemical-electrochromic device comprising a first transparent electrode and a second transparent electrode in parallel, spaced relation to each other. The first transparent electrode is electrically connected to the second transparent electrode. An electrochromic material is applied to the first transparent electrode and a nanoporous semiconductor film having a dye adsorbed therein is applied to the second transparent electrode. An electrolyte layer contacts the electrochromic material and the nanoporous semiconductor film. The electrolyte layer has a redox couple whereby upon application of light, the nanoporous semiconductor layer dye absorbs the light and the redox couple oxidizes producing an electric field across the device modulating the effective light transmittance through the device.

Control of GaAs Microwave Schottky Diode Electrical Characteristics by Contact Geometry: The Gap Diode.

DTIC Science & Technology

1982-05-01

semiconductor Schottky-barrier contacts are used in many semiconductor devices, including switches, rectifiers, varactors , IMPATTs, mixer and detector...ionic materials such as most of the II-VI compound semiconductors (e.g. ZnS and ZnO) and the transition-metal oxides , the barrier height is strongly...the alloying process described above is nonuniformity, due to the incomplete removal of residual surface oxides prior to the evaporation of the metal

Ferroelectric switching of poly(vinylidene difluoride-trifluoroethylene) in metal-ferroelectric-semiconductor non-volatile memories with an amorphous oxide semiconductor

NASA Astrophysics Data System (ADS)

Gelinck, G. H.; van Breemen, A. J. J. M.; Cobb, B.

2015-03-01

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

A hard oxide semiconductor with a direct and narrow bandgap and switchable p-n electrical conduction.

PubMed

Ovsyannikov, Sergey V; Karkin, Alexander E; Morozova, Natalia V; Shchennikov, Vladimir V; Bykova, Elena; Abakumov, Artem M; Tsirlin, Alexander A; Glazyrin, Konstantin V; Dubrovinsky, Leonid

2014-12-23

An oxide semiconductor (perovskite-type Mn2 O3 ) is reported which has a narrow and direct bandgap of 0.45 eV and a high Vickers hardness of 15 GPa. All the known materials with similar electronic band structures (e.g., InSb, PbTe, PbSe, PbS, and InAs) play crucial roles in the semiconductor industry. The perovskite-type Mn2 O3 described is much stronger than the above semiconductors and may find useful applications in different semiconductor devices, e.g., in IR detectors. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Efficient Suppression of Defects and Charge Trapping in High Density In-Sn-Zn-O Thin Film Transistor Prepared using Microwave-Assisted Sputter.

PubMed

Goh, Youngin; Ahn, Jaehan; Lee, Jeong Rak; Park, Wan Woo; Ko Park, Sang-Hee; Jeon, Sanghun

2017-10-25

Amorphous oxide semiconductor-based thin film transistors (TFTs) have been considered as excellent switching elements for driving active-matrix organic light-emitting diodes (AMOLED) owing to their high mobility and process compatibility. However, oxide semiconductors have inherent defects, causing fast transient charge trapping and device instability. For the next-generation displays such as flexible, wearable, or transparent displays, an active semiconductor layer with ultrahigh mobility and high reliability at low deposition temperature is required. Therefore, we introduced high density plasma microwave-assisted (MWA) sputtering method as a promising deposition tool for the formation of high density and high-performance oxide semiconductor films. In this paper, we present the effect of the MWA sputtering method on the defects and fast charge trapping in In-Sn-Zn-O (ITZO) TFTs using various AC device characterization methodologies including fast I-V, pulsed I-V, transient current, low frequency noise, and discharge current analysis. Using these methods, we were able to analyze the charge trapping mechanism and intrinsic electrical characteristics, and extract the subgap density of the states of oxide TFTs quantitatively. In comparison to conventional sputtered ITZO, high density plasma MWA-sputtered ITZO exhibits outstanding electrical performance, negligible charge trapping characteristics and low subgap density of states. High-density plasma MWA sputtering method has high deposition rate even at low working pressure and control the ion bombardment energy, resulting in forming low defect generation in ITZO and presenting high performance ITZO TFT. We expect the proposed high density plasma sputtering method to be applicable to a wide range of oxide semiconductor device applications.

Control of Ga-oxide interlayer growth and Ga diffusion in SiO2/GaN stacks for high-quality GaN-based metal-oxide-semiconductor devices with improved gate dielectric reliability

NASA Astrophysics Data System (ADS)

Yamada, Takahiro; Watanabe, Kenta; Nozaki, Mikito; Yamada, Hisashi; Takahashi, Tokio; Shimizu, Mitsuaki; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-01-01

A simple and feasible method for fabricating high-quality and highly reliable GaN-based metal-oxide-semiconductor (MOS) devices was developed. The direct chemical vapor deposition of SiO2 films on GaN substrates forming Ga-oxide interlayers was carried out to fabricate SiO2/GaO x /GaN stacked structures. Although well-behaved hysteresis-free GaN-MOS capacitors with extremely low interface state densities below 1010 cm-2 eV-1 were obtained by postdeposition annealing, Ga diffusion into overlying SiO2 layers severely degraded the dielectric breakdown characteristics. However, this problem was found to be solved by rapid thermal processing, leading to the superior performance of the GaN-MOS devices in terms of interface quality, insulating property, and gate dielectric reliability.

CMOS Image Sensor Using SOI-MOS/Photodiode Composite Photodetector Device

NASA Astrophysics Data System (ADS)

Uryu, Yuko; Asano, Tanemasa

2002-04-01

A new photodetector device composed of a lateral junction photodiode and a metal-oxide-semiconductor field-effect-transistor (MOSFET), in which the output of the diode is fed through the body of the MOSFET, has been investigated. It is shown that the silicon-on-insulator (SOI)-MOSFET amplifies the junction photodiode current due to the lateral bipolar action. It is also shown that the presence of the electrically floating gate enhances the current amplification factor of the SOI-MOSFET. The output current of this composite device linearly responds by four orders of illumination intensity. As an application of the composite device, a complementary-metal-oxide-semiconductor (CMOS) line sensor incorporating the composite device is fabricated and its operation is demonstrated. The output signal of the line sensor using the composite device was two times larger than that using the lateral photodiode.

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

NASA Astrophysics Data System (ADS)

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-02-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters.

Temperature-dependent mechanical behavior of silicon dioxide, gold and gold-vanadium thin films for VLSI integrated circuits and MicroElectroMechanical systems (MEMs)

NASA Astrophysics Data System (ADS)

Lin, Ming-Tzer

The Semiconductor Industry has grown rapidly in the last twenty years. The national technology roadmap for semiconductors plans for developing the complexity and packing density of semiconductor devices into the next decade, allowing ever smaller and more densely packed structures to be fabricated. Recently, MEMS (Micro-Electro-Mechanical Systems) have become important in modern technology. The goal of MEMs is to integrate many types of miniature devices on a single chip, creating a new micro-world. The oxidation of silicon is one of the most important processes in semiconductor technology. Producing high-quality IC's and MEMS devices requires an understanding of the basic oxidation mechanism. In addition, for the reliability of IC's and MEMS devices, the mechanical properties of the oxide play a critical role. There has been an apparent convergence of opinion on the relevant mechanism leading to the "standard computational model" for stress effects on silicon oxidation. This model has recently become suspect. Most of the reasonably direct experimental data on the flow properties of SiO 2 thin film do not support a stress-dependent viscosity of the sort envisioned by the model. Gold and gold vanadium alloys are used in electrical interconnections and in radio frequency switch contacts for the semiconductor industry, MEMs sensors for the aerospace industry and also in brain probes by the bioelectronics mechanical industry. Despite the strong potential usage of gold and gold vanadium thin films at the small scale, very little is known about their mechanical properties. Our goal was to experimentally investigate stress and its influence on SiO2 thin films and the mechanical properties of gold and gold vanadium thin films at room temperature and at elevated temperature of different vanadium concentration. We found that the application of relatively small amounts of bending to an oxidizing silicon substrate leads to significant decreases in oxide thickness in the ultrathin oxide regime. Both tensile and compressive bending retard oxide growth, although compressive bending results in somewhat thinner oxides than does tensile bending. We also determined the modulus of gold and gold vanadium, and discovered that there is some evidence for a vanadium concentration dependence of the mechanical properties.

Monolithic integration of GaN-based light-emitting diodes and metal-oxide-semiconductor field-effect transistors.

PubMed

Lee, Ya-Ju; Yang, Zu-Po; Chen, Pin-Guang; Hsieh, Yung-An; Yao, Yung-Chi; Liao, Ming-Han; Lee, Min-Hung; Wang, Mei-Tan; Hwang, Jung-Min

2014-10-20

In this study, we report a novel monolithically integrated GaN-based light-emitting diode (LED) with metal-oxide-semiconductor field-effect transistor (MOSFET). Without additionally introducing complicated epitaxial structures for transistors, the MOSFET is directly fabricated on the exposed n-type GaN layer of the LED after dry etching, and serially connected to the LED through standard semiconductor-manufacturing technologies. Such monolithically integrated LED/MOSFET device is able to circumvent undesirable issues that might be faced by other kinds of integration schemes by growing a transistor on an LED or vice versa. For the performances of resulting device, our monolithically integrated LED/MOSFET device exhibits good characteristics in the modulation of gate voltage and good capability of driving injected current, which are essential for the important applications such as smart lighting, interconnection, and optical communication.

Development of p-type oxide semiconductors based on tin oxide and its alloys: application to thin film transistors

NASA Astrophysics Data System (ADS)

Barros, Ana Raquel Xarouco de

In spite of the recent p-type oxide TFTs developments based on SnOx and CuxO, the results achieved so far refer to devices processed at high temperatures and are limited by a low hole mobility and a low On-Off ratio and still there is no report on p-type oxide TFTs with performance similar to n-type, especially when comparing their field-effect mobility values, which are at least one order of magnitude higher on n-type oxide TFTs. Achieving high performance p-type oxide TFTs will definitely promote a new era for electronics in rigid and flexible substrates, away from silicon. None of the few reported p-channel oxide TFTs is suitable for practical applications, which demand significant improvements in the device engineering to meet the real-world electronic requirements, where low processing temperatures together with high mobility and high On-Off ratio are required for TFT and CMOS applications. The present thesis focuses on the study and optimization of p-type thin film transistors based on oxide semiconductors deposited by r.f. magnetron sputtering without intentional substrate heating. In this work several p-type oxide semiconductors were studied and optimized based on undoped tin oxide, Cu-doped SnOx and In-doped SnO2.

High performance printed oxide field-effect transistors processed using photonic curing.

PubMed

Garlapati, Suresh Kumar; Marques, Gabriel Cadilha; Gebauer, Julia Susanne; Dehm, Simone; Bruns, Michael; Winterer, Markus; Tahoori, Mehdi Baradaran; Aghassi-Hagmann, Jasmin; Hahn, Horst; Dasgupta, Subho

2018-06-08

Oxide semiconductors are highly promising candidates for the most awaited, next-generation electronics, namely, printed electronics. As a fabrication route for the solution-processed/printed oxide semiconductors, photonic curing is becoming increasingly popular, as compared to the conventional thermal curing method; the former offers numerous advantages over the latter, such as low process temperatures and short exposure time and thereby, high throughput compatibility. Here, using dissimilar photonic curing concepts (UV-visible light and UV-laser), we demonstrate facile fabrication of high performance In 2 O 3 field-effect transistors (FETs). Beside the processing related issues (temperature, time etc.), the other known limitation of oxide electronics is the lack of high performance p-type semiconductors, which can be bypassed using unipolar logics from high mobility n-type semiconductors alone. Interestingly, here we have found that our chosen distinct photonic curing methods can offer a large variation in threshold voltage, when they are fabricated from the same precursor ink. Consequently, both depletion and enhancement-mode devices have been achieved which can be used as the pull-up and pull-down transistors in unipolar inverters. The present device fabrication recipe demonstrates fast processing of low operation voltage, high performance FETs with large threshold voltage tunability.

High performance printed oxide field-effect transistors processed using photonic curing

NASA Astrophysics Data System (ADS)

Garlapati, Suresh Kumar; Cadilha Marques, Gabriel; Gebauer, Julia Susanne; Dehm, Simone; Bruns, Michael; Winterer, Markus; Baradaran Tahoori, Mehdi; Aghassi-Hagmann, Jasmin; Hahn, Horst; Dasgupta, Subho

2018-06-01

Oxide semiconductors are highly promising candidates for the most awaited, next-generation electronics, namely, printed electronics. As a fabrication route for the solution-processed/printed oxide semiconductors, photonic curing is becoming increasingly popular, as compared to the conventional thermal curing method; the former offers numerous advantages over the latter, such as low process temperatures and short exposure time and thereby, high throughput compatibility. Here, using dissimilar photonic curing concepts (UV–visible light and UV-laser), we demonstrate facile fabrication of high performance In2O3 field-effect transistors (FETs). Beside the processing related issues (temperature, time etc.), the other known limitation of oxide electronics is the lack of high performance p-type semiconductors, which can be bypassed using unipolar logics from high mobility n-type semiconductors alone. Interestingly, here we have found that our chosen distinct photonic curing methods can offer a large variation in threshold voltage, when they are fabricated from the same precursor ink. Consequently, both depletion and enhancement-mode devices have been achieved which can be used as the pull-up and pull-down transistors in unipolar inverters. The present device fabrication recipe demonstrates fast processing of low operation voltage, high performance FETs with large threshold voltage tunability.

Thin Film Complementary Metal Oxide Semiconductor (CMOS) Device Using a Single-Step Deposition of the Channel Layer

PubMed Central

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wang, Zhenwei; Hedhili, M. N.; Wang, Q. X.; Alshareef, H. N.

2014-01-01

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n- and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350°C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications. PMID:24728223

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

1995-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Active pixel sensor with intra-pixel charge transfer

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2004-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Recent progress in tungsten oxides based memristors and their neuromorphological applications

NASA Astrophysics Data System (ADS)

Qu, Bo; Younis, Adnan; Chu, Dewei

2016-09-01

The advance in conventional silicon based semiconductor industry is now becoming indeterminacy as it still along the road of Moore's Law and concomitant problems associated with it are the emergence of a number of practical issues such as short channel effect. In terms of memory applications, it is generally believed that transistors based memory devices will approach to their scaling limits up to 2018. Therefore, one of the most prominent challenges today in semiconductor industry is the need of a new memory technology which is able to combine the best characterises of current devices. The resistive switching memories which are regarded as "memristors" thus gain great attentions thanks to their specific nonlinear electrical properties. More importantly, their behaviour resembles with the transmission characteristic of synapse in biology. Therefore, the research of synapses biomimetic devices based on memristor will certainly bring a great research prospect in studying synapse emulation as well as building artificial neural networks. Tungsten oxides (WO x ) exhibits many essential characteristics as a great candidate for memristive devices including: accredited endurance (over 105 cycles), stoichiometric flexibility, complimentary metal-oxide-semiconductor (CMOS) process compatibility and configurable properties including non-volatile rectification, memorization and learning functions. Herein, recent progress on Tungsten oxide based materials and its associating memory devices had been reviewed. The possible implementation of this material as a bio-inspired artificial synapse is also highlighted. The penultimate section summaries the current research progress for tungsten oxide based biological synapses and end up with several proposals that have been suggested for possible future developments.

Transparent Oxide Thin-Film Transistors: Production, Characterization and Integration

NASA Astrophysics Data System (ADS)

Barquinha, Pedro Miguel Candido

This dissertation is devoted to the study of the emerging area of transparent electronics, summarizing research work regarding the development of n-type thin-film transistors (TFTs) based on sputtered oxide semiconductors. All the materials are produced without intentional substrate heating, with annealing temperatures of only 150-200 °C being used to optimize transistor performance. The work is based on the study and optimization of active semiconductors from the gallium-indium-zinc oxide system, including both the binary compounds Ga2O3, In2O3 and ZnO, as well as ternary and quaternary oxides based on mixtures of those, such as IZO and GIZO with different atomic ratios. Several topics are explored, including the study and optimization of the oxide semiconductor thin films, their application as channel layers on TFTs and finally the implementation of the optimized processes to fabricate active matrix backplanes to be integrated in liquid crystal display (LCD) prototypes. Sputtered amorphous dielectrics with high dielectric constant (high-kappa) based on mixtures of tantalum-silicon or tantalum-aluminum oxides are also studied and used as the dielectric layers on fully transparent TFTs. These devices also include transparent and highly conducting IZO thin films as source, drain and gate electrodes. Given the flexibility of the sputtering technique, oxide semiconductors are analyzed regarding several deposition parameters, such as oxygen partial pressure and deposition pressure, as well as target composition. One of the most interesting features of multicomponent oxides such as IZO and GIZO is that, due to their unique electronic configuration and carrier transport mechanism, they allow to obtain amorphous structures with remarkable electrical properties, such as high hall-effect mobility that exceeds 60 cm2 V -1 s-1 for IZO. These properties can be easily tuned by changing the processing conditions and the atomic ratios of the multicomponent oxides, allowing to have amorphous oxides suitable to be used either as transparent semiconductors or as highly conducting electrodes. The amorphous structure, which is maintained even if the thin films are annealed at 500 °C, brings great advantages concerning interface quality and uniformity in large areas. A complete study comprising different deposition conditions of the semiconductor layer is also made regarding TFT electrical performance. Optimized devices present outstanding electrical performance, such as field-effect mobility (muFE) exceeding 20 cm2 V -1 s-1, turn-on voltage (Von) between -1 and 1 V, subthreshold slope (S) lower than 0.25 V dec-1 and On-Off ratio above 107 . Devices employing amorphous multicomponent oxides present largely improved properties when compared with the ones based on polycrystalline ZnO, mostly in terms of muFE. Within the compositional range where IZO and GIZO films are amorphous, TFT performance can be largely adjusted: for instance, high indium contents favor large mu FE but also highly negative Von, which can be compensated by proper amounts of zinc and gallium. Large oxygen concentrations during oxide semiconductor sputtering are found to be deleterious, decreasing muFE, shifting Von towards high values and turning the devices electrically unstable. It is also shown that semiconductor thickness (ds) has a very important role: for instance, by reducing ds to 10 nm it is possible to produce TFTs with Von≈0 V even using deposition conditions and/or target compositions that normally yield highly conducting films. Given the low ds of the films, this behavior is mostly related with surface states existent at the oxide semiconductor air-exposed back-surface, where depletion layers that can extend towards the dielectric/semiconductor interface are created due to the interaction with atmospheric oxygen. Different passivation layers on top of this air-exposed surface are studied, with SU-8 revealing to be to most effective one. Other important topics are source-drain contact resistance assessment and the effect of different annealing temperatures ( TA), being the properties of the TFTs dominated by TA rather than by the deposition conditions as TA increases. Fully transparent TFTs employing sputtered amorphous multicomponent dielectrics produced without intentional substrate heating present excellent electrical properties, that approach those exhibited by devices using PECVD SiO2 produced at 400 °C. Gate leakage current can be greatly reduced by using tantalum-silicon or tantalum-aluminum oxides rather than Ta2O5. A section of this dissertation is also devoted to the analysis of current stress stability and aging effects of the TFTs, being found that optimal devices exhibit recoverable threshold voltage shifts lower than 0.50 V after 24 h stress with constant drain current of 10 muA, as well as negligible aging effects during 18 months. The research work of this dissertation culminates in the fabrication of a backplane employing transparent TFTs and subsequent integration with a LCD frontplane by Hewlett-Packard. The successful operation of this initial 2.8h prototype with 128x128 pixels provides a solid demonstration that oxide semiconductor-based TFTs have the potential to largely contribute to a novel electronics era, where semiconductor materials away from conventional silicon are used to create fascinating applications, such as transparent electronic products.

Characterization of Interface State in Silicon Carbide Metal Oxide Semiconductor Capacitors

NASA Astrophysics Data System (ADS)

Kao, Wei-Chieh

Silicon carbide (SiC) has always been considered as an excellent material for high temperature and high power devices. Since SiC is the only compound semiconductor whose native oxide is silicon dioxide (SiO2), it puts SiC in a unique position. Although SiC metal oxide semiconductor (MOS) technology has made significant progress in recent years, there are still a number of issues to be overcome before more commercial SiC devices can enter the market. The prevailing issues surrounding SiC MOSFET devices are the low channel mobility, the low quality of the oxide layer and the high interface state density at the SiC/SiO2 interface. Consequently, there is a need for research to be performed in order to have a better understanding of the factors causing the poor SiC/SiO2 interface properties. In this work, we investigated the generation lifetime in SiC materials by using the pulsed metal oxide semiconductor (MOS) capacitor method and measured the interface state density distribution at the SiC/SiO2 interface by using the conductance measurement and the high-low frequency capacitance technique. These measurement techniques have been performed on n-type and p-type SiC MOS capacitors. In the course of our investigation, we observed fast interface states at semiconductor-dielectric interfaces in SiC MOS capacitors that underwent three different interface passivation processes, such states were detected in the nitrided samples but not observed in PSG-passivated samples. This result indicate that the lack of fast states at PSG-passivated interface is one of the main reasons for higher channel mobility in PSG MOSFETs. In addition, the effect of mobile ions in the oxide on the response time of interface states has been investigated. In the last chapter we propose additional methods of investigation that can help elucidate the origin of the particular interface states, enabling a more complete understanding of the SiC/SiO2 material system.

CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES: Switching Characteristics of Phase Change Memory Cell Integrated with Metal-Oxide Semiconductor Field Effect Transistor

NASA Astrophysics Data System (ADS)

Xu, Cheng; Liu, Bo; Chen, Yi-Feng; Liang, Shuang; Song, Zhi-Tang; Feng, Song-Lin; Wan, Xu-Dong; Yang, Zuo-Ya; Xie, Joseph; Chen, Bomy

2008-05-01

A Ge2Sb2Te5 based phase change memory device cell integrated with metal-oxide semiconductor field effect transistor (MOSFET) is fabricated using standard 0. 18 μm complementary metal-oxide semiconductor process technology. It shows steady switching characteristics in the dc current-voltage measurement. The phase changing phenomenon from crystalline state to amorphous state with a voltage pulse altitude of 2.0 V and pulse width of 50 ns is also obtained. These results show the feasibility of integrating phase change memory cell with MOSFET.

Magneto-Optical Thin Films for On-Chip Monolithic Integration of Non-Reciprocal Photonic Devices

PubMed Central

Bi, Lei; Hu, Juejun; Jiang, Peng; Kim, Hyun Suk; Kim, Dong Hun; Onbasli, Mehmet Cengiz; Dionne, Gerald F.; Ross, Caroline A.

2013-01-01

Achieving monolithic integration of nonreciprocal photonic devices on semiconductor substrates has been long sought by the photonics research society. One way to achieve this goal is to deposit high quality magneto-optical oxide thin films on a semiconductor substrate. In this paper, we review our recent research activity on magneto-optical oxide thin films toward the goal of monolithic integration of nonreciprocal photonic devices on silicon. We demonstrate high Faraday rotation at telecommunication wavelengths in several novel magnetooptical oxide thin films including Co substituted CeO2−δ, Co- or Fe-substituted SrTiO3−δ, as well as polycrystalline garnets on silicon. Figures of merit of 3~4 deg/dB and 21 deg/dB are achieved in epitaxial Sr(Ti0.2Ga0.4Fe0.4)O3−δ and polycrystalline (CeY2)Fe5O12 films, respectively. We also demonstrate an optical isolator on silicon, based on a racetrack resonator using polycrystalline (CeY2)Fe5O12/silicon strip-loaded waveguides. Our work demonstrates that physical vapor deposited magneto-optical oxide thin films on silicon can achieve high Faraday rotation, low optical loss and high magneto-optical figure of merit, therefore enabling novel high-performance non-reciprocal photonic devices monolithically integrated on semiconductor substrates. PMID:28788379

Self-cleaning and surface chemical reactions during hafnium dioxide atomic layer deposition on indium arsenide.

PubMed

Timm, Rainer; Head, Ashley R; Yngman, Sofie; Knutsson, Johan V; Hjort, Martin; McKibbin, Sarah R; Troian, Andrea; Persson, Olof; Urpelainen, Samuli; Knudsen, Jan; Schnadt, Joachim; Mikkelsen, Anders

2018-04-12

Atomic layer deposition (ALD) enables the ultrathin high-quality oxide layers that are central to all modern metal-oxide-semiconductor circuits. Crucial to achieving superior device performance are the chemical reactions during the first deposition cycle, which could ultimately result in atomic-scale perfection of the semiconductor-oxide interface. Here, we directly observe the chemical reactions at the surface during the first cycle of hafnium dioxide deposition on indium arsenide under realistic synthesis conditions using photoelectron spectroscopy. We find that the widely used ligand exchange model of the ALD process for the removal of native oxide on the semiconductor and the simultaneous formation of the first hafnium dioxide layer must be significantly revised. Our study provides substantial evidence that the efficiency of the self-cleaning process and the quality of the resulting semiconductor-oxide interface can be controlled by the molecular adsorption process of the ALD precursors, rather than the subsequent oxide formation.

Valorization of GaN based metal-organic chemical vapor deposition dust a semiconductor power device industry waste through mechanochemical oxidation and leaching: A sustainable green process.

PubMed

Swain, Basudev; Mishra, Chinmayee; Lee, Chan Gi; Park, Kyung-Soo; Lee, Kun-Jae

2015-07-01

Dust generated during metal organic vapor deposition (MOCVD) process of GaN based semiconductor power device industry contains significant amounts of gallium and indium. These semiconductor power device industry wastes contain gallium as GaN and Ga0.97N0.9O0.09 is a concern for the environment which can add value through recycling. In the present study, this waste is recycled through mechanochemical oxidation and leaching. For quantitative recovery of gallium, two different mechanochemical oxidation leaching process flow sheets are proposed. In one process, first the Ga0.97N0.9O0.09 of the MOCVD dust is leached at the optimum condition. Subsequently, the leach residue is mechanochemically treated, followed by oxidative annealing and finally re-leached. In the second process, the MOCVD waste dust is mechanochemically treated, followed by oxidative annealing and finally leached. Both of these treatment processes are competitive with each other, appropriate for gallium leaching and treatment of the waste MOCVD dust. Without mechanochemical oxidation, 40.11 and 1.86 w/w% of gallium and Indium are leached using 4M HCl, 100°C and pulp density of 100 kg/m(3,) respectively. After mechanochemical oxidation, both these processes achieved 90 w/w% of gallium and 1.86 w/w% of indium leaching at their optimum condition. Copyright © 2015 Elsevier Inc. All rights reserved.

Electronic structure and relative stability of the coherent and semi-coherent HfO2/III-V interfaces

NASA Astrophysics Data System (ADS)

Lahti, A.; Levämäki, H.; Mäkelä, J.; Tuominen, M.; Yasir, M.; Dahl, J.; Kuzmin, M.; Laukkanen, P.; Kokko, K.; Punkkinen, M. P. J.

2018-01-01

III-V semiconductors are prominent alternatives to silicon in metal oxide semiconductor devices. Hafnium dioxide (HfO2) is a promising oxide with a high dielectric constant to replace silicon dioxide (SiO2). The potentiality of the oxide/III-V semiconductor interfaces is diminished due to high density of defects leading to the Fermi level pinning. The character of the harmful defects has been intensively debated. It is very important to understand thermodynamics and atomic structures of the interfaces to interpret experiments and design methods to reduce the defect density. Various realistic gap defect state free models for the HfO2/III-V(100) interfaces are presented. Relative energies of several coherent and semi-coherent oxide/III-V semiconductor interfaces are determined for the first time. The coherent and semi-coherent interfaces represent the main interface types, based on the Ga-O bridges and As (P) dimers, respectively.

Estimation of carrier mobility and charge behaviors of organic semiconductor films in metal-insulator-semiconductor diodes consisting of high-k oxide/organic semiconductor double layers

NASA Astrophysics Data System (ADS)

Chosei, Naoya; Itoh, Eiji

2018-02-01

We have comparatively studied the charge behaviors of organic semiconductor films based on charge extraction by linearly increasing voltage in a metal-insulator-semiconductor (MIS) diode structure (MIS-CELIV) and by classical capacitance-voltage measurement. The MIS-CELIV technique allows the selective measurement of electron and hole mobilities of n- and p-type organic films with thicknesses representative of those of actual devices. We used an anodic oxidized sputtered Ta or Hf electrode as a high-k layer, and it effectively blocked holes at the insulator/semiconductor interface. We estimated the hole mobilities of the polythiophene derivatives regioregular poly(3-hexylthiophene) (P3HT) and poly(3,3‧‧‧-didodecylquarterthiophene) (PQT-12) before and after heat treatment in the ITO/high-k/(thin polymer insulator)/semiconductor/MoO3/Ag device structure. The hole mobility of PQT-12 was improved from 1.1 × 10-5 to 2.1 × 10-5 cm2 V-1 s-1 by the heat treatment of the device at 100 °C for 30 min. An almost two orders of magnitude higher mobility was obtained in MIS diodes with P3HT as the p-type layer. We also determined the capacitance from the displacement current in MIS diodes at a relatively low-voltage sweep, and it corresponded well to the classical capacitance-voltage and frequency measurement results.

Hetero-junction photovoltaic device and method of fabricating the device

DOEpatents

Aytug, Tolga; Christen, David K; Paranthaman, Mariappan Parans; Polat, Ozgur

2014-02-10

A hetero-junction device and fabrication method in which phase-separated n-type and p-type semiconductor pillars define vertically-oriented p-n junctions extending above a substrate. Semiconductor materials are selected for the p-type and n-type pillars that are thermodynamically stable and substantially insoluble in one another. An epitaxial deposition process is employed to form the pillars on a nucleation layer and the mutual insolubility drives phase separation of the materials. During the epitaxial deposition process, the orientation is such that the nucleation layer initiates propagation of vertical columns resulting in a substantially ordered, three-dimensional structure throughout the deposited material. An oxidation state of at least a portion of one of the p-type or the n-type semiconductor materials is altered relative to the other, such that the band-gap energy of the semiconductor materials differ with respect to stoichiometric compositions and the device preferentially absorbs particular selected bands of radiation.

Heavy-ion induced single-event upset in integrated circuits

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.

1991-01-01

The cosmic ray environment in space can affect the operation of Integrated Circuit (IC) devices via the phenomenon of Single Event Upset (SEU). In particular, heavy ions passing through an IC can induce sufficient integrated current (charge) to alter the state of a bistable circuit, for example a memory cell. The SEU effect is studied in great detail in both static and dynamic memory devices, as well as microprocessors fabricated from bipolar, Complementary Metal Oxide Semiconductor (CMOS) and N channel Metal Oxide Semiconductor (NMOS) technologies. Each device/process reflects its individual characteristics (minimum scale geometry/process parameters) via a unique response to the direct ionization of electron hole pairs by heavy ion tracks. A summary of these analytical and experimental SEU investigations is presented.

Method of acquiring an image from an optical structure having pixels with dedicated readout circuits

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra (Inventor); Kemeny, Sabrina E. (Inventor)

2006-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Chemically Derivatized Semiconductor Photoelectrodes.

ERIC Educational Resources Information Center

Wrighton, Mark S.

1983-01-01

Deliberate modification of semiconductor photoelectrodes to improve durability and enhance rate of desirable interfacial redox processes is discussed for a variety of systems. Modification with molecular-based systems or with metals/metal oxides yields results indicating an important role for surface modification in devices for fundamental study…

A CMOS-Compatible Poly-Si Nanowire Device with Hybrid Sensor/Memory Characteristics for System-on-Chip Applications

PubMed Central

Chen, Min-Cheng; Chen, Hao-Yu; Lin, Chia-Yi; Chien, Chao-Hsin; Hsieh, Tsung-Fan; Horng, Jim-Tong; Qiu, Jian-Tai; Huang, Chien-Chao; Ho, Chia-Hua; Yang, Fu-Liang

2012-01-01

This paper reports a versatile nano-sensor technology using “top-down” poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n type polysilicon nanowire FETs have positive pH sensitivity (100 mV/pH) and sensitive deoxyribonucleic acid (DNA) detection ability (100 pM) at normal system operation voltages. Specially designed oxide-nitride-oxide buried oxide nanowire realizes an electrically Vth-adjustable sensor to compensate device variation. These nanowire FETs also enable non-volatile memory application for a large and steady Vth adjustment window (>2 V Programming/Erasing window). The CMOS-compatible manufacturing technique of polysilicon nanowire FETs offers a possible solution for commercial System-on-Chip biosensor application, which enables portable physiology monitoring and in situ recording. PMID:22666012

Sustained hole inversion layer in a wide-bandgap metal-oxide semiconductor with enhanced tunnel current

PubMed Central

Shoute, Gem; Afshar, Amir; Muneshwar, Triratna; Cadien, Kenneth; Barlage, Douglas

2016-01-01

Wide-bandgap, metal-oxide thin-film transistors have been limited to low-power, n-type electronic applications because of the unipolar nature of these devices. Variations from the n-type field-effect transistor architecture have not been widely investigated as a result of the lack of available p-type wide-bandgap inorganic semiconductors. Here, we present a wide-bandgap metal-oxide n-type semiconductor that is able to sustain a strong p-type inversion layer using a high-dielectric-constant barrier dielectric when sourced with a heterogeneous p-type material. A demonstration of the utility of the inversion layer was also investigated and utilized as the controlling element in a unique tunnelling junction transistor. The resulting electrical performance of this prototype device exhibited among the highest reported current, power and transconductance densities. Further utilization of the p-type inversion layer is critical to unlocking the previously unexplored capability of metal-oxide thin-film transistors, such applications with next-generation display switches, sensors, radio frequency circuits and power converters. PMID:26842997

Protection of inorganic semiconductors for sustained, efficient photoelectrochemical water oxidation

DOE PAGES

Lichterman, Michael F.; Sun, Ke; Hu, Shu; ...

2015-10-25

Small-band-gap (E g < 2 eV) semiconductors must be stabilized for use in integrated devices that convert solar energy into the bonding energy of a reduced fuel, specifically H 2 (g) or a reduced-carbon species such as CH 3 OH or CH 4 . To sustainably and scalably complete the fuel cycle, electrons must be liberated through the oxidation of water to O 2 (g). Strongly acidic or strongly alkaline electrolytes are needed to enable efficient and intrinsically safe operation of a full solar-driven water-splitting system. But, under water-oxidation conditions, the small-band-gap semiconductors required for efficient cell operation aremore » unstable, either dissolving or forming insulating surface oxides. Here, we describe herein recent progress in the protection of semiconductor photoanodes under such operational conditions. We specifically describe the properties of two protective overlayers, TiO 2 /Ni and NiO x , both of which have demonstrated the ability to protect otherwise unstable semiconductors for > 100 h of continuous solar-driven water oxidation when in contact with a highly alkaline aqueous electrolyte (1.0 M KOH(aq)). Furthermore, the stabilization of various semiconductor photoanodes is reviewed in the context of the electronic characteristics and a mechanistic analysis of the TiO 2 films, along with a discussion of the optical, catalytic, and electronic nature of NiO x films for stabilization of semiconductor photoanodes for water oxidation.« less

High mobility and high stability glassy metal-oxynitride materials and devices

NASA Astrophysics Data System (ADS)

Lee, Eunha; Kim, Taeho; Benayad, Anass; Hur, Jihyun; Park, Gyeong-Su; Jeon, Sanghun

2016-04-01

In thin film technology, future semiconductor and display products with high performance, high density, large area, and ultra high definition with three-dimensional functionalities require high performance thin film transistors (TFTs) with high stability. Zinc oxynitride, a composite of zinc oxide and zinc nitride, has been conceded as a strong substitute to conventional semiconductor film such as silicon and indium gallium zinc oxide due to high mobility value. However, zinc oxynitride has been suffered from poor reproducibility due to relatively low binding energy of nitrogen with zinc, resulting in the instability of composition and its device performance. Here we performed post argon plasma process on zinc oxynitride film, forming nano-crystalline structure in stable amorphous matrix which hampers the reaction of oxygen with zinc. Therefore, material properties and device performance of zinc oxynitride are greatly enhanced, exhibiting robust compositional stability even exposure to air, uniform phase, high electron mobility, negligible fast transient charging and low noise characteristics. Furthermore, We expect high mobility and high stability zinc oxynitride customized by plasma process to be applicable to a broad range of semiconductor and display devices.

Wide-band-gap, alkaline-earth-oxide semiconductor and devices utilizing same

DOEpatents

Abraham, Marvin M.; Chen, Yok; Kernohan, Robert H.

1981-01-01

This invention relates to novel and comparatively inexpensive semiconductor devices utilizing semiconducting alkaline-earth-oxide crystals doped with alkali metal. The semiconducting crystals are produced by a simple and relatively inexpensive process. As a specific example, a high-purity lithium-doped MgO crystal is grown by conventional techniques. The crystal then is heated in an oxygen-containing atmosphere to form many [Li].degree. defects therein, and the resulting defect-rich hot crystal is promptly quenched to render the defects stable at room temperature and temperatures well above the same. Quenching can be effected conveniently by contacting the hot crystal with room-temperature air.

Flexible Electronics Powered by Mixed Metal Oxide Thin Film Transistors

NASA Astrophysics Data System (ADS)

Marrs, Michael

A low temperature amorphous oxide thin film transistor (TFT) and amorphous silicon PIN diode backplane technology for large area flexible digital x-ray detectors has been developed to create 7.9-in. diagonal backplanes. The critical steps in the evolution of the backplane process include the qualification and optimization of the low temperature (200 °C) metal oxide TFT and a-Si PIN photodiode process, the stability of the devices under forward and reverse bias stress, the transfer of the process to flexible plastic substrates, and the fabrication and assembly of the flexible detectors. Mixed oxide semiconductor TFTs on flexible plastic substrates suffer from performance and stability issues related to the maximum processing temperature limitation of the polymer. A novel device architecture based upon a dual active layer improves both the performance and stability. Devices are directly fabricated below 200 ºC on a polyethylene naphthalate (PEN) substrate using mixed metal oxides of either zinc indium oxide (ZIO) or indium gallium zinc oxide (IGZO) as the active semiconductor. The dual active layer architecture allows for adjustment to the saturation mobility and threshold voltage stability without the requirement of high temperature annealing, which is not compatible with flexible plastic substrates like PEN. The device performance and stability is strongly dependent upon the composition of the mixed metal oxide; this dependency provides a simple route to improving the threshold voltage stability and drive performance. By switching from a single to a dual active layer, the saturation mobility increases from 1.2 cm2/V-s to 18.0 cm2/V-s, while the rate of the threshold voltage shift decreases by an order of magnitude. This approach could assist in enabling the production of devices on flexible substrates using amorphous oxide semiconductors. Low temperature (200°C) processed amorphous silicon photodiodes were developed successfully by balancing the tradeoffs between low temperature and low stress (less than -70 MPa compressive) and device performance. Devices with a dark current of less than 1.0 pA/mm2 and a quantum efficiency of 68% have been demonstrated. Alternative processing techniques, such as pixelating the PIN diode and using organic photodiodes have also been explored for applications where extreme flexibility is desired.

Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor.

PubMed

Nomura, Kenji; Ohta, Hiromichi; Ueda, Kazushige; Kamiya, Toshio; Hirano, Masahiro; Hosono, Hideo

2003-05-23

We report the fabrication of transparent field-effect transistors using a single-crystalline thin-film transparent oxide semiconductor, InGaO3(ZnO)5, as an electron channel and amorphous hafnium oxide as a gate insulator. The device exhibits an on-to-off current ratio of approximately 106 and a field-effect mobility of approximately 80 square centimeters per volt per second at room temperature, with operation insensitive to visible light irradiation. The result provides a step toward the realization of transparent electronics for next-generation optoelectronics.

Positive and negative gain exceeding unity magnitude in silicon quantum well metal-oxide-semiconductor transistors

NASA Astrophysics Data System (ADS)

Hu, Gangyi; Wijesinghe, Udumbara; Naquin, Clint; Maggio, Ken; Edwards, H. L.; Lee, Mark

2017-10-01

Intrinsic gain (AV) measurements on Si quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors show that these devices can have |AV| > 1 in quantum transport negative transconductance (NTC) operation at room temperature. QW NMOS devices were fabricated using an industrial 45 nm technology node process incorporating ion implanted potential barriers to define a lateral QW in the conduction channel under the gate. While NTC at room temperature arising from transport through gate-controlled QW bound states has been previously established, it was unknown whether the quantum NTC mechanism could support gain magnitude exceeding unity. Bias conditions were found giving both positive and negative AV with |AV| > 1 at room temperature. This result means that QW NMOS devices could be useful in amplifier and oscillator applications.

Defect-related electroluminescence from metal-oxide-semiconductor devices with ZrO2 films on silicon

NASA Astrophysics Data System (ADS)

Lv, Chunyan; Zhu, Chen; Wang, Canxing; Li, Dongsheng; Ma, Xiangyang; Yang, Deren

2016-11-01

Defect-related electroluminescence (EL) from ZrO2 films annealed under different atmosphere has been realized by means of electrical pumping scheme of metal-oxide-semiconductor (MOS) devices. At the same injection current, the acquired EL from the MOS device with the vacuum-annealed ZrO2 film is much stronger than that from the counterpart with the oxygen-annealed ZrO2 film. This is because the vacuum-annealed ZrO2 film contains more oxygen vacancies and Zr3+ ions. Analysis on the current-voltage characteristic of the ZrO2-based MOS devices indicates the P-F conduction mechanism dominates the electron transportation at the EL-enabling voltages under forward bias. It is tentatively proposed that the recombination of the electrons trapped in multiple oxygen-vacancy-related states with the holes in the defect level pertaining to Zr3+ ions brings about the EL emissions.

High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

2014-05-21

We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

Tungsten coating for improved wear resistance and reliability of microelectromechanical devices

DOEpatents

Fleming, James G.; Mani, Seethambal S.; Sniegowski, Jeffry J.; Blewer, Robert S.

2001-01-01

A process is disclosed whereby a 5-50-nanometer-thick conformal tungsten coating can be formed over exposed semiconductor surfaces (e.g. silicon, germanium or silicon carbide) within a microelectromechanical (MEM) device for improved wear resistance and reliability. The tungsten coating is formed after cleaning the semiconductor surfaces to remove any organic material and oxide film from the surface. A final in situ cleaning step is performed by heating a substrate containing the MEM device to a temperature in the range of 200-600 .degree. C. in the presence of gaseous nitrogen trifluoride (NF.sub.3). The tungsten coating can then be formed by a chemical reaction between the semiconductor surfaces and tungsten hexafluoride (WF.sub.6) at an elevated temperature, preferably about 450.degree. C. The tungsten deposition process is self-limiting and covers all exposed semiconductor surfaces including surfaces in close contact. The present invention can be applied to many different types of MEM devices including microrelays, micromirrors and microengines. Additionally, the tungsten wear-resistant coating of the present invention can be used to enhance the hardness, wear resistance, electrical conductivity, optical reflectivity and chemical inertness of one or more semiconductor surfaces within a MEM device.

Metal-insulator-semiconductor capacitors with bismuth oxide as insulator

NASA Astrophysics Data System (ADS)

Raju, T. A.; Talwai, A. S.

1981-07-01

Metal-insulator-semiconductor capacitors using aluminum Bi2O3 and silicon have been studied for varactor applications. Reactively sputtered Bi2O3 films which under suitable proportions of oxygen and argon and had high resistivity suitable for device applications showed a dielectric constant of 25.

Comprehensive electrical analysis of metal/Al2O3/O-terminated diamond capacitance

NASA Astrophysics Data System (ADS)

Pham, T. T.; Maréchal, A.; Muret, P.; Eon, D.; Gheeraert, E.; Rouger, N.; Pernot, J.

2018-04-01

Metal oxide semiconductor capacitors were fabricated using p - type oxygen-terminated (001) diamond and Al2O3 deposited by atomic layer deposition at two different temperatures 250 °C and 380 °C. Current voltage I(V), capacitance voltage C(V), and capacitance frequency C(f) measurements were performed and analyzed for frequencies ranging from 1 Hz to 1 MHz and temperatures from 160 K to 360 K. A complete model for the Metal-Oxide-Semiconductor Capacitors electrostatics, leakage current mechanisms through the oxide into the semiconductor and small a.c. signal equivalent circuit of the device is proposed and discussed. Interface states densities are then evaluated in the range of 1012eV-1cm-2 . The strong Fermi level pinning is demonstrated to be induced by the combined effects of the leakage current through the oxide and the presence of diamond/oxide interface states.

Scalable ferroelectric MOS capacitors comprised of single crystalline SrZrxTi1-xO3 on Ge.

NASA Astrophysics Data System (ADS)

Moghadam, Reza; Xiao, Z.-Y.; Ahmadi-Majlan, K.; Grimley, E.; Ong, P. V.; Lebeau, J. M.; Chambers, S. A.; Hong, X.; Sushko, P.; Ngai, J. H.

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to field-effect devices that require very little power to operate, or that possess both logic and memory functionalities. The development of metal-oxide-semiconductor (MOS) capacitors in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel is essential in order to realize such field-effect devices. Here we demonstrate that scalable, ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x = 0.7) that has been epitaxially grown on Ge. Single crystalline SrZrxTi1-xO3 exhibits characteristics that are ideal for a ferroelectric gate material, namely, a type-I band offset with respect to Ge, large coercive fields and polarization that can be enhanced with electric field. The latter characteristic stems from the relaxor nature of SrZrxTi1-xO3. These properties enable MOS capacitors with 5 nm thick SrZrxTi1-xO3 layers to exhibit a nearly 2 V wide hysteretic window in the capacitance-voltage characteristics. The realization of ferroelectric MOS capacitors with technologically relevant gate thicknesses opens the pathway to practical field effect devices. NSF DMR 1508530.

Tracking ion irradiation effects using buried interface devices

NASA Astrophysics Data System (ADS)

Cutshall, D. B.; Kulkarni, D. D.; Miller, A. J.; Harriss, J. E.; Harrell, W. R.; Sosolik, C. E.

2018-05-01

We discuss how a buried interface device, specifically a metal-oxide-semiconductor (MOS) capacitor, can be utilized to track effects of ion irradiation on insulators. We show that the exposure of oxides within unfinished capacitor devices to ions can lead to significant changes in the capacitance of the finished devices. For multicharged ions, these capacitive effects can be traced to defect production within the oxide and ultimately point to a role for charge-dependent energy loss. In particular, we attribute the stretchout of the capacitance-voltage curves of MOS devices that include an irradiated oxide to the ion irradiation. The stretchout shows a power law dependence on the multicharged ion charge state (Q) that is similar to that observed for multicharged ion energy loss in other systems.

Optical temperature sensor using thermochromic semiconductors

DOEpatents

Kronberg, James W.

1996-01-01

An optical temperature measuring device utilizes thermochromic semiconductors which vary in color in response to changes in temperature. The thermochromic material is sealed in a glass matrix which allows the temperature sensor to detect high temperatures without breakdown. Cuprous oxide and cadmium sulfide are among the semiconductor materials which provide the best results. The changes in color may be detected visually or by utilizing an optical fiber and an electrical sensing circuit.

Optical temperature sensor using thermochromic semiconductors

DOEpatents

Kronberg, James W.

1998-01-01

An optical temperature measuring device utilizes thermochromic semiconductors which vary in color in response to changes in temperature. The thermochromic material is sealed in a glass matrix which allows the temperature sensor to detect high temperatures without breakdown. Cuprous oxide and cadmium sulfide are among the semiconductor materials which provide the best results. The changes in color may be detected visually using a sensor chip and an accompanying color card.

Optical temperature sensor using thermochromic semiconductors

DOEpatents

Kronberg, J.W.

1998-06-30

An optical temperature measuring device utilizes thermochromic semiconductors which vary in color in response to changes in temperature. The thermochromic material is sealed in a glass matrix which allows the temperature sensor to detect high temperatures without breakdown. Cuprous oxide and cadmium sulfide are among the semiconductor materials which provide the best results. The changes in color may be detected visually using a sensor chip and an accompanying color card. 8 figs.

Nanophotonic Hot Electron Solar-Blind Ultraviolet Detectors with a Metal-Oxide-Semiconductor Structure

NASA Astrophysics Data System (ADS)

Wang, Zhiyuan

Solar-blind ultraviolet detection refers to photon detection specifically in the wavelength range of 200 nm to 320 nm. Without background noises from solar radiation, it has broad applications from homeland security to environmental monitoring. In this thesis, we design and fabricate a nanophotonic metal-oxide-semiconductor device for solar-blind UV detection. Instead of using semiconductors as the active absorber, we use metal Sn nano- grating structures to absorb UV photons and generate hot electrons for internal photoemission across the Sn/SiO 2 interfacial barrier, thereby generating photocurrent between metal and semiconductor region upon UV excitation. The large metal/oxide interfacial energy barrier enables solar-blind UV detection by blocking the less energetic electrons excited by visible photons. With optimized design, 85% UV absorption and hot electron excitation can be achieved within the mean free path of 20 nm from the metal/oxide interface. This feature greatly enhances hot electron transport across the interfacial barrier to generate photocurrent. Various fabrication techniques have been developed for preparing nano gratings. For nominally 20 nm-thick deposited Sn, the self- formed pseudo-periodic nanostructure help achieve 75% UV absorption from lambda=200 nm to 300 nm. With another layer of nominally 20 nm-thick Sn, similar UV absorption is maintained while conductivity is improved, which is beneficial for overall device efficiency. The Sn/SiO2/Si MOS devices show good solar-blind character while achieving 13% internal quantum efficiency for 260 nm UV with only 20 nm-thick Sn and some devices demonstrate much higher (even >100%) internal quantum efficiency. While a more accurate estimation of device effective area is needed for proving our calculation, these results indeed show a great potential for this type of hot-electron-based photodetectors and for Sn nanostructure as an effective UV absorber. The simple geometry of the self- assembled Sn nano-gratings and MOS structure make this novel type of device easy to fabricate and integrate with Si ROICs compared to existing solar-blind UV detection schemes. The presented device structure also breaks through the conventional notion that photon absorption by metal is always a loss in solid-state photodetectors, and it can potentially be extended to other active metal photonic devices.

Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures

DOEpatents

Seager, C.H.; Evans, J.T. Jr.

1998-11-24

A method is described for counteracting increases in resistivity encountered when Indium Oxide resistive layers are subjected to high temperature annealing steps during semiconductor device fabrication. The method utilizes a recovery annealing step which returns the Indium Oxide layer to its original resistivity after a high temperature annealing step has caused the resistivity to increase. The recovery anneal comprises heating the resistive layer to a temperature between 100 C and 300 C for a period of time that depends on the annealing temperature. The recovery is observed even when the Indium Oxide layer is sealed under a dielectric layer. 1 fig.

Method for restoring the resistance of indium oxide semiconductors after heating while in sealed structures

DOEpatents

Seager, Carleton H.; Evans, Jr., Joseph Tate

1998-01-01

A method for counteracting increases in resistivity encountered when Indium Oxide resistive layers are subjected to high temperature annealing steps during semiconductor device fabrication. The method utilizes a recovery annealing step which returns the Indium Oxide layer to its original resistivity after a high temperature annealing step has caused the resistivity to increase. The recovery anneal comprises heating the resistive layer to a temperature between 100.degree. C. and 300.degree. C. for a period of time that depends on the annealing temperature. The recovery is observed even when the Indium Oxide layer is sealed under a dielectric layer.

Fabrication of a P3HT-ZnO Nanowires Gas Sensor Detecting Ammonia Gas

PubMed Central

Kuo, Chin-Guo; Chen, Jung-Hsuan; Chao, Yi-Chieh; Chen, Po-Lin

2017-01-01

In this study, an organic-inorganic semiconductor gas sensor was fabricated to detect ammonia gas. An inorganic semiconductor was a zinc oxide (ZnO) nanowire array produced by atomic layer deposition (ALD) while an organic material was a p-type semiconductor, poly(3-hexylthiophene) (P3HT). P3HT was suitable for the gas sensing application due to its high hole mobility, good stability, and good electrical conductivity. In this work, P3HT was coated on the zinc oxide nanowires by the spin coating to form an organic-inorganic heterogeneous interface of the gas sensor for detecting ammonia gas. The thicknesses of the P3HT were around 462 nm, 397 nm, and 277 nm when the speeds of the spin coating were 4000 rpm, 5000 rpm, and 6000 rpm, respectively. The electrical properties and sensing characteristics of the gas sensing device at room temperature were evaluated by Hall effect measurement and the sensitivity of detecting ammonia gas. The results of Hall effect measurement for the P3HT-ZnO nanowires semiconductor with 462 nm P3HT film showed that the carrier concentration and the mobility were 2.7 × 1019 cm−3 and 24.7 cm2∙V−1∙s−1 respectively. The gas sensing device prepared by the P3HT-ZnO nanowires semiconductor had better sensitivity than the device composed of the ZnO film and P3HT film. Additionally, this gas sensing device could reach a maximum sensitivity around 11.58 per ppm. PMID:29295573

Fabrication of a P3HT-ZnO Nanowires Gas Sensor Detecting Ammonia Gas.

PubMed

Kuo, Chin-Guo; Chen, Jung-Hsuan; Chao, Yi-Chieh; Chen, Po-Lin

2017-12-25

In this study, an organic-inorganic semiconductor gas sensor was fabricated to detect ammonia gas. An inorganic semiconductor was a zinc oxide (ZnO) nanowire array produced by atomic layer deposition (ALD) while an organic material was a p-type semiconductor, poly(3-hexylthiophene) (P3HT). P3HT was suitable for the gas sensing application due to its high hole mobility, good stability, and good electrical conductivity. In this work, P3HT was coated on the zinc oxide nanowires by the spin coating to form an organic-inorganic heterogeneous interface of the gas sensor for detecting ammonia gas. The thicknesses of the P3HT were around 462 nm, 397 nm, and 277 nm when the speeds of the spin coating were 4000 rpm, 5000 rpm, and 6000 rpm, respectively. The electrical properties and sensing characteristics of the gas sensing device at room temperature were evaluated by Hall effect measurement and the sensitivity of detecting ammonia gas. The results of Hall effect measurement for the P3HT-ZnO nanowires semiconductor with 462 nm P3HT film showed that the carrier concentration and the mobility were 2.7 × 10 19 cm -3 and 24.7 cm²∙V -1 ∙s -1 respectively. The gas sensing device prepared by the P3HT-ZnO nanowires semiconductor had better sensitivity than the device composed of the ZnO film and P3HT film. Additionally, this gas sensing device could reach a maximum sensitivity around 11.58 per ppm.

Ionic behavior of organic-inorganic metal halide perovskite based metal-oxide-semiconductor capacitors.

PubMed

Wang, Yucheng; Zhang, Yuming; Pang, Tiqiang; Xu, Jie; Hu, Ziyang; Zhu, Yuejin; Tang, Xiaoyan; Luan, Suzhen; Jia, Renxu

2017-05-24

Organic-inorganic metal halide perovskites are promising semiconductors for optoelectronic applications. Despite the achievements in device performance, the electrical properties of perovskites have stagnated. Ion migration is speculated to be the main contributing factor for the many unusual electrical phenomena in perovskite-based devices. Here, to understand the intrinsic electrical behavior of perovskites, we constructed metal-oxide-semiconductor (MOS) capacitors based on perovskite films and performed capacitance-voltage (C-V) and current-voltage (I-V) measurements of the capacitors. The results provide direct evidence for the mixed ionic-electronic transport behavior within perovskite films. In the dark, there is electrical hysteresis in both the C-V and I-V curves because the mobile negative ions take part in charge transport despite frequency modulation. However, under illumination, the large amount of photoexcited free carriers screens the influence of the mobile ions with a low concentration, which is responsible for the normal C-V properties. Validation of ion migration for the gate-control ability of MOS capacitors is also helpful for the investigation of perovskite MOS transistors and other gate-control photovoltaic devices.

Inhibition of unintentional extra carriers by Mn valence change for high insulating devices

PubMed Central

Guo, Daoyou; Li, Peigang; Wu, Zhenping; Cui, Wei; Zhao, Xiaolong; Lei, Ming; Li, Linghong; Tang, Weihua

2016-01-01

For intrinsic oxide semiconductors, oxygen vacancies served as the electron donors have long been, and inevitably still are, attributed as the primary cause of conductivity, making oxide semiconductors seem hard to act as high insulating materials. Meanwhile, the presence of oxygen vacancies often leads to a persistent photoconductivity phenomenon which is not conducive to the practical use in the fast photoelectric response devices. Herein, we propose a possible way to reduce the influence of oxygen vacancies by introducing a valence change doping in the monoclinic β-Ga2O3 epitaxial thin film. The unintentional extra electrons induced by oxygen vacancies can be strongly suppressed by the change valence of the doped Mn ions from +3 to +2. The resistance for the Mn-doped Ga2O3 increases two orders of magnitude in compared with the pure Ga2O3. As a result, photodetector based on Mn-doped Ga2O3 thin films takes on a lower dark current, a higher sensitivity, and a faster photoresponse time, exhibiting a promising candidate using in high performance solar-blind photodetector. The study presents that the intentional doping of Mn may provide a convenient and reliable method of obtaining high insulating thin film in oxide semiconductor for the application of specific device. PMID:27068227

Antimonene Oxides: Emerging Tunable Direct Bandgap Semiconductor and Novel Topological Insulator.

PubMed

Zhang, Shengli; Zhou, Wenhan; Ma, Yandong; Ji, Jianping; Cai, Bo; Yang, Shengyuan A; Zhu, Zhen; Chen, Zhongfang; Zeng, Haibo

2017-06-14

Highly stable antimonene, as the cousin of phosphorene from group-VA, has opened up exciting realms in the two-dimensional (2D) materials family. However, pristine antimonene is an indirect band gap semiconductor, which greatly restricts its applications for optoelectronics devices. Identifying suitable materials, both responsive to incident photons and efficient for carrier transfer, is urgently needed for ultrathin devices. Herein, by means of first-principles computations we found that it is rather feasible to realize a new class of 2D materials with a direct bandgap and high carrier mobility, namely antimonene oxides with different content of oxygen. Moreover, these tunable direct bandgaps cover a wide range from 0 to 2.28 eV, which are crucial for solar cell and photodetector applications. Especially, the antimonene oxide (18Sb-18O) is a 2D topological insulator with a sizable global bandgap of 177 meV, which has a nontrivial Z 2 topological invariant in the bulk and the topological states on the edge. Our findings not only introduce new vitality into 2D group-VA materials family and enrich available candidate materials in this field but also highlight the potential of these 2D semiconductors as appealing ultrathin materials for future flexible electronics and optoelectronics devices.

Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

PubMed Central

Pavunny, Shojan P.; Scott, James F.; Katiyar, Ram S.

2014-01-01

A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS) specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS), bipolar (Bi) and BiCMOS chips applications, is presented in this review article. PMID:28788589

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2000-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Investigation of structural and electrical properties on substrate material for high frequency metal-oxide-semiconductor (MOS) devices

NASA Astrophysics Data System (ADS)

Kumar, M.; Yang, Sung-Hyun; Janardhan Reddy, K.; JagadeeshChandra, S. V.

2017-04-01

Hafnium oxide (HfO2) thin films were grown on cleaned P-type <1 0 0> Ge and Si substrates by using atomic layer deposition technique (ALD) with thickness of 8 nm. The composition analysis of as-deposited and annealed HfO2 films was characterized by XPS, further electrical measurements; we fabricated the metal-oxide-semiconductor (MOS) devices with Pt electrode. Post deposition annealing in O2 ambient at 500 °C for 30 min was carried out on both Ge and Si devices. Capacitance-voltage (C-V) and conductance-voltage (G-V) curves measured at 1 MHz. The Ge MOS devices showed improved interfacial and electrical properties, high dielectric constant (~19), smaller EOT value (0.7 nm), and smaller D it value as Si MOS devices. The C-V curves shown significantly high accumulation capacitance values from Ge devices, relatively when compare with the Si MOS devices before and after annealing. It could be due to the presence of very thin interfacial layer at HfO2/Ge stacks than HfO2/Si stacks conformed by the HRTEM images. Besides, from current-voltage (I-V) curves of the Ge devices exhibited similar leakage current as Si devices. Therefore, Ge might be a reliable substrate material for structural, electrical and high frequency applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lichterman, Michael F.; Sun, Ke; Hu, Shu

Small-band-gap (E g < 2 eV) semiconductors must be stabilized for use in integrated devices that convert solar energy into the bonding energy of a reduced fuel, specifically H 2 (g) or a reduced-carbon species such as CH 3 OH or CH 4 . To sustainably and scalably complete the fuel cycle, electrons must be liberated through the oxidation of water to O 2 (g). Strongly acidic or strongly alkaline electrolytes are needed to enable efficient and intrinsically safe operation of a full solar-driven water-splitting system. But, under water-oxidation conditions, the small-band-gap semiconductors required for efficient cell operation aremore » unstable, either dissolving or forming insulating surface oxides. Here, we describe herein recent progress in the protection of semiconductor photoanodes under such operational conditions. We specifically describe the properties of two protective overlayers, TiO 2 /Ni and NiO x , both of which have demonstrated the ability to protect otherwise unstable semiconductors for > 100 h of continuous solar-driven water oxidation when in contact with a highly alkaline aqueous electrolyte (1.0 M KOH(aq)). Furthermore, the stabilization of various semiconductor photoanodes is reviewed in the context of the electronic characteristics and a mechanistic analysis of the TiO 2 films, along with a discussion of the optical, catalytic, and electronic nature of NiO x films for stabilization of semiconductor photoanodes for water oxidation.« less

Coaxial metal-oxide-semiconductor (MOS) Au/Ga2O3/GaN nanowires.

PubMed

Hsieh, Chin-Hua; Chang, Mu-Tung; Chien, Yu-Jen; Chou, Li-Jen; Chen, Lih-Juann; Chen, Chii-Dong

2008-10-01

Coaxial metal-oxide-semiconductor (MOS) Au-Ga2O3-GaN heterostructure nanowires were successfully fabricated by an in situ two-step process. The Au-Ga2O3 core-shell nanowires were first synthesized by the reaction of Ga powder, a mediated Au thin layer, and a SiO2 substrate at 800 degrees C. Subsequently, these core-shell nanowires were nitridized in ambient ammonia to form a GaN coating layer at 600 degrees C. The GaN shell is a single crystal, an atomic flat interface between the oxide and semiconductor that ensures that the high quality of the MOS device is achieved. These novel 1D nitride-based MOS nanowires may have promise as building blocks to the future nitride-based vertical nanodevices.

Optical temperature sensor using thermochromic semiconductors

DOEpatents

Kronberg, J.W.

1996-08-20

An optical temperature measuring device utilizes thermochromic semiconductors which vary in color in response to changes in temperature. The thermochromic material is sealed in a glass matrix which allows the temperature sensor to detect high temperatures without breakdown. Cuprous oxide and cadmium sulfide are among the semiconductor materials which provide the best results. The changes in color may be detected visually or by utilizing an optical fiber and an electrical sensing circuit. 7 figs.

Titanium-dioxide nanotube p-n homojunction diode

NASA Astrophysics Data System (ADS)

Alivov, Yahya; Ding, Yuchen; Singh, Vivek; Nagpal, Prashant

2014-12-01

Application of semiconductors in functional optoelectronic devices requires precise control over their doping and formation of junction between p- and n-doped semiconductors. While doped thin films have led to several semiconductor devices, need for high-surface area nanostructured devices for photovoltaic, photoelectrochemical, and photocatalytic applications has been hindered by lack of desired doping in nanostructures. Here, we show titanium-dioxide (TiO2) nanotubes doped with nitrogen (N) and niobium (Nb) as acceptors and donors, respectively, and formation of TiO2 nanotubes p-n homojunction. This TiO2:N/TiO2:Nb homojunction showed distinct diode-like behaviour with rectification ratio of 1115 at ±5 V and exhibited good photoresponse for ultraviolet light (λ = 365 nm) with sensitivity of 0.19 A/W at reverse bias of -5 V. These results can have important implications for development of nanostructured metal-oxide solar-cells, photodiodes, LED's, photocatalysts, and photoelectrochemical devices.

p-i-n heterojunctions with BiFeO3 perovskite nanoparticles and p- and n-type oxides: photovoltaic properties.

PubMed

Chatterjee, Soumyo; Bera, Abhijit; Pal, Amlan J

2014-11-26

We formed p-i-n heterojunctions based on a thin film of BiFeO3 nanoparticles. The perovskite acting as an intrinsic semiconductor was sandwiched between a p-type and an n-type oxide semiconductor as hole- and electron-collecting layer, respectively, making the heterojunction act as an all-inorganic oxide p-i-n device. We have characterized the perovskite and carrier collecting materials, such as NiO and MoO3 nanoparticles as p-type materials and ZnO nanoparticles as the n-type material, with scanning tunneling spectroscopy; from the spectrum of the density of states, we could locate the band edges to infer the nature of the active semiconductor materials. The energy level diagram of p-i-n heterojunctions showed that type-II band alignment formed at the p-i and i-n interfaces, favoring carrier separation at both of them. We have compared the photovoltaic properties of the perovskite in p-i-n heterojunctions and also in p-i and i-n junctions. From current-voltage characteristics and impedance spectroscopy, we have observed that two depletion regions were formed at the p-i and i-n interfaces of a p-i-n heterojunction. The two depletion regions operative at p-i-n heterojunctions have yielded better photovoltaic properties as compared to devices having one depletion region in the p-i or the i-n junction. The results evidenced photovoltaic devices based on all-inorganic oxide, nontoxic, and perovskite materials.

Collective Poisson process with periodic rates: applications in physics from micro-to nanodevices.

PubMed

da Silva, Roberto; Lamb, Luis C; Wirth, Gilson Inacio

2011-01-28

Continuous reductions in the dimensions of semiconductor devices have led to an increasing number of noise sources, including random telegraph signals (RTS) due to the capture and emission of electrons by traps at random positions between oxide and semiconductor. The models traditionally used for microscopic devices become of limited validity in nano- and mesoscale systems since, in such systems, distributed quantities such as electron and trap densities, and concepts like electron mobility, become inadequate to model electrical behaviour. In addition, current experimental works have shown that RTS in semiconductor devices based on carbon nanotubes lead to giant current fluctuations. Therefore, the physics of this phenomenon and techniques to decrease the amplitudes of RTS need to be better understood. This problem can be described as a collective Poisson process under different, but time-independent, rates, τ(c) and τ(e), that control the capture and emission of electrons by traps distributed over the oxide. Thus, models that consider calculations performed under time-dependent periodic capture and emission rates should be of interest in order to model more efficient devices. We show a complete theoretical description of a model that is capable of showing a noise reduction of current fluctuations in the time domain, and a reduction of the power spectral density in the frequency domain, in semiconductor devices as predicted by previous experimental work. We do so through numerical integrations and a novel Monte Carlo Markov chain (MCMC) algorithm based on microscopic discrete values. The proposed model also handles the ballistic regime, relevant in nano- and mesoscale devices. Finally, we show that the ballistic regime leads to nonlinearity in the electrical behaviour.

European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (5th)

DTIC Science & Technology

1994-10-07

Characterisation and Modelling WEDNESDAY 5th OCTOBER Session C Hot Carriers Session D Oxide States Session E Power Devices Workshop 2 Power Devices Session F...Medium Enterprises .......... 17 W2 Power Devices Workshop "Reliability of Power Semiconductors for Traction Applications...New Mexico, USA Sandia National Laboratories, Albuquerque, New Mexico, USA SESSION E Power Devices El Reliability Issues in New Technology

Active pixel sensor pixel having a photodetector whose output is coupled to an output transistor gate

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Nakamura, Junichi (Inventor); Kemeny, Sabrina E. (Inventor)

2005-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. A Simple Floating Gate (SFG) pixel structure could also be employed in the imager to provide a non-destructive readout and smaller pixel sizes.

Radiation induced failures of complementary metal oxide semiconductor containing pacemakers: a potentially lethal complication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lewin, A.A.; Serago, C.F.; Schwade, J.G.

1984-10-01

New multi-programmable pacemakers frequently employ complementary metal oxide semiconductors (CMOS). This circuitry appears more sensitive to the effects of ionizing radiation when compared to the semiconductor circuits used in older pacemakers. A case of radiation induced runaway pacemaker in a CMOS device is described. Because of this and other recent reports of radiation therapy-induced CMOS type pacemaker failure, these pacemakers should not be irradiated. If necessary, the pacemaker can be shielded or moved to a site which can be shielded before institution of radiation therapy. This is done to prevent damage to the CMOS circuit and the life threatening arrythmiasmore » which may result from such damage.« less

MOSFET analog memory circuit achieves long duration signal storage

NASA Technical Reports Server (NTRS)

1966-01-01

Memory circuit maintains the signal voltage at the output of an analog signal amplifier when the input signal is interrupted or removed. The circuit uses MOSFET /Metal Oxide Semiconductor Field Effect Transistor/ devices as voltage-controlled switches, triggered by an external voltage-sensing device.

Defect-Rich Dopant-Free ZrO2 Nanostructures with Superior Dilute Ferromagnetic Semiconductor Properties.

PubMed

Rahman, Md Anisur; Rout, S; Thomas, Joseph P; McGillivray, Donald; Leung, Kam Tong

2016-09-14

Control of the spin degree of freedom of an electron has brought about a new era in spin-based applications, particularly spin-based electronics, with the potential to outperform the traditional charge-based semiconductor technology for data storage and information processing. However, the realization of functional spin-based devices for information processing remains elusive due to several fundamental challenges such as the low Curie temperature of group III-V and II-VI semiconductors (<200 K), and the low spin-injection efficiencies of existing III-V, II-VI, and transparent conductive oxide semiconductors in a multilayer device structure, which are caused by precipitation and migration of dopants from the host layer to the adjacent layers. Here, we use catalyst-assisted pulsed laser deposition to grow, for the first time, oxygen vacancy defect-rich, dopant-free ZrO2 nanostructures with high TC (700 K) and high magnetization (5.9 emu/g). The observed magnetization is significantly greater than both doped and defect-rich transparent conductive oxide nanomaterials reported to date. We also provide the first experimental evidence that it is the amounts and types of oxygen vacancy defects in, and not the phase of ZrO2 that control the ferromagnetic order in undoped ZrO2 nanostructures. To explain the origin of ferromagnetism in these ZrO2 nanostructures, we hypothesize a new defect-induced bound polaron model, which is generally applicable to other defect-rich, dopant-free transparent conductive oxide nanostructures. These results provide new insights into magnetic ordering in undoped dilute ferromagnetic semiconductor oxides and contribute to the design of exotic magnetic and novel multifunctional materials.

Low temperature mobility in hafnium-oxide gated germanium p-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Beer, Chris; Whall, Terry; Parker, Evan; Leadley, David; De Jaeger, Brice; Nicholas, Gareth; Zimmerman, Paul; Meuris, Marc; Szostak, Slawomir; Gluszko, Grzegorz; Lukasiak, Lidia

2007-12-01

Effective mobility measurements have been made at 4.2K on high performance high-k gated germanium p-type metal-oxide-semiconductor field effect transistors with a range of Ge/gate dielectric interface state densities. The mobility is successfully modelled by assuming surface roughness and interface charge scattering at the SiO2 interlayer/Ge interface. The deduced interface charge density is approximately equal to the values obtained from the threshold voltage and subthreshold slope measurements on each device. A hydrogen anneal reduces both the interface state density and the surface root mean square roughness by 20%.

Pulse I-V characterization of a nano-crystalline oxide device with sub-gap density of states

NASA Astrophysics Data System (ADS)

Kim, Taeho; Hur, Ji-Hyun; Jeon, Sanghun

2016-05-01

Understanding the charge trapping nature of nano-crystalline oxide semiconductor thin film transistors (TFTs) is one of the most important requirements for their successful application. In our investigation, we employed a fast-pulsed I-V technique for understanding the charge trapping phenomenon and for characterizing the intrinsic device performance of an amorphous/nano-crystalline indium-hafnium-zinc-oxide semiconductor TFT with varying density of states in the bulk. Because of the negligible transient charging effect with a very short pulse, the source-to-drain current obtained with the fast-pulsed I-V measurement was higher than that measured by the direct-current characterization method. This is because the fast-pulsed I-V technique provides a charge-trap free environment, suggesting that it is a representative device characterization methodology of TFTs. In addition, a pulsed source-to-drain current versus time plot was used to quantify the dynamic trapping behavior. We found that the charge trapping phenomenon in amorphous/nano-crystalline indium-hafnium-zinc-oxide TFTs is attributable to the charging/discharging of sub-gap density of states in the bulk and is dictated by multiple trap-to-trap processes.

Pulse I-V characterization of a nano-crystalline oxide device with sub-gap density of states.

PubMed

Kim, Taeho; Hur, Ji-Hyun; Jeon, Sanghun

2016-05-27

Understanding the charge trapping nature of nano-crystalline oxide semiconductor thin film transistors (TFTs) is one of the most important requirements for their successful application. In our investigation, we employed a fast-pulsed I-V technique for understanding the charge trapping phenomenon and for characterizing the intrinsic device performance of an amorphous/nano-crystalline indium-hafnium-zinc-oxide semiconductor TFT with varying density of states in the bulk. Because of the negligible transient charging effect with a very short pulse, the source-to-drain current obtained with the fast-pulsed I-V measurement was higher than that measured by the direct-current characterization method. This is because the fast-pulsed I-V technique provides a charge-trap free environment, suggesting that it is a representative device characterization methodology of TFTs. In addition, a pulsed source-to-drain current versus time plot was used to quantify the dynamic trapping behavior. We found that the charge trapping phenomenon in amorphous/nano-crystalline indium-hafnium-zinc-oxide TFTs is attributable to the charging/discharging of sub-gap density of states in the bulk and is dictated by multiple trap-to-trap processes.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gelinck, G. H., E-mail: Gerwin.Gelinck@tno.nl; Department of Applied Physics, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven; Breemen, A. J. J. M. van

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

Chip-scale fluorescence microscope based on a silo-filter complementary metal-oxide semiconductor image sensor.

PubMed

Ah Lee, Seung; Ou, Xiaoze; Lee, J Eugene; Yang, Changhuei

2013-06-01

We demonstrate a silo-filter (SF) complementary metal-oxide semiconductor (CMOS) image sensor for a chip-scale fluorescence microscope. The extruded pixel design with metal walls between neighboring pixels guides fluorescence emission through the thick absorptive filter to the photodiode of a pixel. Our prototype device achieves 13 μm resolution over a wide field of view (4.8 mm × 4.4 mm). We demonstrate bright-field and fluorescence longitudinal imaging of living cells in a compact, low-cost configuration.

Spin-dependent transport and current modulation in a current-in-plane spin-valve field-effect transistor

NASA Astrophysics Data System (ADS)

Kanaki, Toshiki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2016-10-01

We propose a current-in-plane spin-valve field-effect transistor (CIP-SV-FET), which is composed of a ferromagnet/nonferromagnet/ferromagnet trilayer structure and a gate electrode. This is a promising device alternative to spin metal-oxide-semiconductor field-effect transistors. Here, we fabricate a ferromagnetic-semiconductor GaMnAs-based CIP-SV-FET and demonstrate its basic operation of the resistance modulation both by the magnetization configuration and by the gate electric field. Furthermore, we present the electric-field-assisted magnetization reversal in this device.

A study to investigate the chemical stability of gallium phosphate oxide/gallium arsenide phosphide

NASA Technical Reports Server (NTRS)

Kuhlman, G. J.

1979-01-01

The elemental composition with depth into the oxide films was examined using secondary ion mass spectrometry. Results indicate that the layers are arsenic-deficient through the bulk of the oxide and arsenic-rich near both the oxide surface and the oxide-semiconductor interface region. Phosphorus is incorporated into the oxide in an approximately uniform manner. The MIS capacitor structures exhibited deep-depletion characteristics and hysteresis indicative of electron trapping at the oxide-semiconductor interface. Post-oxidation annealing of the films in argon or nitrogen generally results in slightly increased dielectric leakage currents and decreased C-V hysteresis effects, and is associated with arsenic loss at the oxide surface. The results of bias-temperature stress experiments indicate that the major instability effects are due to changes in the electron trapping behavior. No changes were observed in the elemental profiles following electrical stressing, indicating that the grown films are chemically stable under device operating conditions.

New Material Transistor with Record-High Field-Effect Mobility among Wide-Band-Gap Semiconductors.

PubMed

Shih, Cheng Wei; Chin, Albert

2016-08-03

At an ultrathin 5 nm, we report a new high-mobility tin oxide (SnO2) metal-oxide-semiconductor field-effect transistor (MOSFET) exhibiting extremely high field-effect mobility values of 279 and 255 cm(2)/V-s at 145 and 205 °C, respectively. These values are the highest reported mobility values among all wide-band-gap semiconductors of GaN, SiC, and metal-oxide MOSFETs, and they also exceed those of silicon devices at the aforementioned elevated temperatures. For the first time among existing semiconductor transistors, a new device physical phenomenon of a higher mobility value was measured at 45-205 °C than at 25 °C, which is due to the lower optical phonon scattering by the large SnO2 phonon energy. Moreover, the high on-current/off-current of 4 × 10(6) and the positive threshold voltage of 0.14 V at 25 °C are significantly better than those of a graphene transistor. This wide-band-gap SnO2 MOSFET exhibits high mobility in a 25-205 °C temperature range, a wide operating voltage of 1.5-20 V, and the ability to form on an amorphous substrate, rendering it an ideal candidate for multifunctional low-power integrated circuit (IC), display, and brain-mimicking three-dimensional IC applications.

GaAs metal-oxide-semiconductor based non-volatile flash memory devices with InAs quantum dots as charge storage nodes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Islam, Sk Masiul, E-mail: masiulelt@gmail.com; Chowdhury, Sisir; Sarkar, Krishnendu

2015-06-24

Ultra-thin InP passivated GaAs metal-oxide-semiconductor based non-volatile flash memory devices were fabricated using InAs quantum dots (QDs) as charge storing elements by metal organic chemical vapor deposition technique to study the efficacy of the QDs as charge storage elements. The grown QDs were embedded between two high-k dielectric such as HfO{sub 2} and ZrO{sub 2}, which were used for tunneling and control oxide layers, respectively. The size and density of the QDs were found to be 5 nm and 1.8×10{sup 11} cm{sup −2}, respectively. The device with a structure Metal/ZrO{sub 2}/InAs QDs/HfO{sub 2}/GaAs/Metal shows maximum memory window equivalent to 6.87 V. Themore » device also exhibits low leakage current density of the order of 10{sup −6} A/cm{sup 2} and reasonably good charge retention characteristics. The low value of leakage current in the fabricated memory device is attributed to the Coulomb blockade effect influenced by quantum confinement as well as reduction of interface trap states by ultra-thin InP passivation on GaAs prior to HfO{sub 2} deposition.« less

Investigation of Short Channel Effects on Device Performance for 60nm NMOS Transistor

NASA Astrophysics Data System (ADS)

Chinnappan, U.; Sanudin, R.

2017-08-01

In the aggressively scaled complementary metal oxide semiconductor (CMOS) devices, shallower p-n junctions and low sheet resistances are essential for short-channel effect (SCE) control and high device performance. The SCE are attributed to two physical phenomena that are the limitation imposed on electron drift characteristics in channel and the modification of the threshold voltage (Vth) due to the shortening channel length. The decrement of Vth with decrement in gate length is a well-known attribute in SCE known as “threshold voltage roll-off’. In this research, the Technology Computer Aided Design (TCAD) was used to model the SCE phenomenon effect on 60nm n-type metal oxide semiconductor (NMOS) transistor. There are three parameters being investigated, which are the oxide thickness (Tox), gate length (L), acceptor concentration (Na). The simulation data were used to visualise the effect of SCE on the 60nm NMOS transistor. Simulation data suggest that all three parameters have significant effect on Vth, and hence on the transistor performance. It is concluded that there is a trade-off among these three parameters to obtain an optimized transistor performance.

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

Room temperature electrical spin injection into GaAs by an oxide spin injector

PubMed Central

Bhat, Shwetha G.; Kumar, P. S. Anil

2014-01-01

Spin injection, manipulation and detection are the integral parts of spintronics devices and have attracted tremendous attention in the last decade. It is necessary to judiciously choose the right combination of materials to have compatibility with the existing semiconductor technology. Conventional metallic magnets were the first choice for injecting spins into semiconductors in the past. So far there is no success in using a magnetic oxide material for spin injection, which is very important for the development of oxide based spintronics devices. Here we demonstrate the electrical spin injection from an oxide magnetic material Fe3O4, into GaAs with the help of tunnel barrier MgO at room temperature using 3-terminal Hanle measurement technique. A spin relaxation time τ ~ 0.9 ns for n-GaAs at 300 K is observed along with expected temperature dependence of τ. Spin injection using Fe3O4/MgO system is further established by injecting spins into p-GaAs and a τ of ~0.32 ns is obtained at 300 K. Enhancement of spin injection efficiency is seen with barrier thickness. In the field of spin injection and detection, our work using an oxide magnetic material establishes a good platform for the development of room temperature oxide based spintronics devices. PMID:24998440

Low-Temperature UV-Assisted Fabrication of Metal Oxide Thin Film Transistor

NASA Astrophysics Data System (ADS)

Zhu, Shuanglin

Solution processed metal oxide semiconductors have attracted intensive attention in the last several decades and have emerged as a promising candidate for the application of thin film transistor (TFT) due to their nature of transparency, flexibility, high mobility, simple processing technique and potential low manufacturing cost. However, metal oxide thin film fabricated by solution process usually requires a high temperature (over 300 °C), which is above the glass transition temperature of some conventional polymer substrates. In order to fabricate the flexible electronic device on polymer substrates, it is necessary to find a facile approach to lower the fabrication temperature and minimize defects in metal oxide thin film. In this thesis, the electrical properties dependency on temperature is discussed and an UV-assisted annealing method incorporating Deep ultraviolet (DUV)-decomposable additives is demonstrated, which can effectively improve electrical properties solution processed metal oxide semiconductors processed at temperature as low as 220 °C. By studying a widely used indium oxide (In2O3) TFT as a model system, it is worth noted that compared with the sample without UV treatment, the linear mobility and saturation mobility of UV-annealing sample are improved by 56% and 40% respectively. Meanwhile, the subthreshold swing is decreased by 32%, indicating UV-treated device could turn on and off more efficiently. In addition to pure In2O3 film, the similar phenomena have also been observed in indium oxide based Indium-Gallium-Zinc Oxide (IGZO) system. These finding presented in this thesis suggest that the UV assisted annealing process open a new route to fabricate high performance metal oxide semiconductors under low temperatures.

Nanostructure and optoelectronic phenomena in germanium-transparent conductive oxide (Ge:TCO) composites

NASA Astrophysics Data System (ADS)

Shih, Grace Hwei-Pyng

Nanostructured composites are attracting intense interest for electronic and optoelectronic device applications, specifically as active elements in thin film photovoltaic (PV) device architectures. These systems implement fundamentally different concepts of enhancing energy conversion efficiencies compared to those seen in current commercial devices. This is possible through considerable flexibility in the manipulation of device-relevant properties through control of the interplay between the nanostructure and the optoelectronic response. In the present work, inorganic nanocomposites of semiconductor Ge embedded in transparent conductive indium tin oxide (ITO) as well as Ge in zinc oxide (ZnO) were produced by a single step RF-magnetron sputter deposition process. It is shown that, by controlling the design of the nanocomposites as well as heat treatment conditions, decreases in the physical dimensions of Ge nanophase size provided an effective tuning of the optical absorption and charge transport properties. This effect of changes in the optical properties of nanophase semiconductors with respect to size is known as the quantum confinement effect. Variation in the embedding matrix material between ITO and ZnO with corresponding characterization of optoelectronic properties exhibit notable differences in the presence and evolution of an interfacial oxide within these composites. Further studies of interfacial structures were performed using depth-profiling XPS and Raman spectroscopy, while study of the corresponding electronic effects were performed using room temperature and temperature-dependent Hall Effect. Optical absorption was noted to shift to higher onset energies upon heat treatment with a decrease in the observed Ge domain size, indicating quantum confinement effects within these systems. This contrasts to previous investigations that have involved the introduction of nanoscale Ge into insulating, amorphous oxides. Comparison of these different matrix chemistries highlights the overarching role of interfacial structures on quantum-size characteristics. The opportunity to tune the spectral response of these PV materials, via control of semiconductor phase assembly in the nanocomposite, directly impacts the potential for the use of these materials as sensitizing elements for enhanced solar cell conversion efficiency.

Review of recent progresses on flexible oxide semiconductor thin film transistors based on atomic layer deposition processes

NASA Astrophysics Data System (ADS)

Sheng, Jiazhen; Han, Ki-Lim; Hong, TaeHyun; Choi, Wan-Ho; Park, Jin-Seong

2018-01-01

The current article is a review of recent progress and major trends in the field of flexible oxide thin film transistors (TFTs), fabricating with atomic layer deposition (ALD) processes. The ALD process offers accurate controlling of film thickness and composition as well as ability of achieving excellent uniformity over large areas at relatively low temperatures. First, an introduction is provided on what is the definition of ALD, the difference among other vacuum deposition techniques, and the brief key factors of ALD on flexible devices. Second, considering functional layers in flexible oxide TFT, the ALD process on polymer substrates may improve device performances such as mobility and stability, adopting as buffer layers over the polymer substrate, gate insulators, and active layers. Third, this review consists of the evaluation methods of flexible oxide TFTs under various mechanical stress conditions. The bending radius and repetition cycles are mostly considering for conventional flexible devices. It summarizes how the device has been degraded/changed under various stress types (directions). The last part of this review suggests a potential of each ALD film, including the releasing stress, the optimization of TFT structure, and the enhancement of device performance. Thus, the functional ALD layers in flexible oxide TFTs offer great possibilities regarding anti-mechanical stress films, along with flexible display and information storage application fields. Project supported by the National Research Foundation of Korea (NRF) (No. NRF-2017R1D1A1B03034035), the Ministry of Trade, Industry & Energy (No. #10051403), and the Korea Semiconductor Research Consortium.

Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal-oxide-semiconductor devices

NASA Astrophysics Data System (ADS)

Jia, Yifan; Lv, Hongliang; Niu, Yingxi; Li, Ling; Song, Qingwen; Tang, Xiaoyan; Li, Chengzhan; Zhao, Yanli; Xiao, Li; Wang, Liangyong; Tang, Guangming; Zhang, Yimen; Zhang, Yuming

2016-09-01

The effect of nitric oxide (NO) annealing on charge traps in the oxide insulator and transition layer in n-type 4H-SiC metal-oxide-semiconductor (MOS) devices has been investigated using the time-dependent bias stress (TDBS), capacitance-voltage (C-V), and secondary ion mass spectroscopy (SIMS). It is revealed that two main categories of charge traps, near interface oxide traps (Nniot) and oxide traps (Not), have different responses to the TDBS and C-V characteristics in NO-annealed and Ar-annealed samples. The Nniot are mainly responsible for the hysteresis occurring in the bidirectional C-V characteristics, which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor. However, Not is mainly responsible for the TDBS induced C-V shifts. Electrons tunneling into the Not are hardly released quickly when suffering TDBS, resulting in the problem of the threshold voltage stability. Compared with the Ar-annealed sample, Nniot can be significantly suppressed by the NO annealing, but there is little improvement of Not. SIMS results demonstrate that the Nniot are distributed within the transition layer, which correlated with the existence of the excess silicon. During the NO annealing process, the excess Si atoms incorporate into nitrogen in the transition layer, allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot. Project supported by the National Natural Science Foundation of China (Grant Nos. 61404098 and 61274079), the Doctoral Fund of Ministry of Education of China (Grant No. 20130203120017), the National Key Basic Research Program of China (Grant No. 2015CB759600), the National Grid Science & Technology Project, China (Grant No. SGRI-WD-71-14-018), and the Key Specific Project in the National Science & Technology Program, China (Grant Nos. 2013ZX02305002-002 and 2015CB759600).

Valorization of GaN based metal-organic chemical vapor deposition dust a semiconductor power device industry waste through mechanochemical oxidation and leaching: A sustainable green process

DOE Office of Scientific and Technical Information (OSTI.GOV)

Swain, Basudev, E-mail: Swain@iae.re.kr; Mishra, Chinmayee; Lee, Chan Gi

2015-07-15

Dust generated during metal organic vapor deposition (MOCVD) process of GaN based semiconductor power device industry contains significant amounts of gallium and indium. These semiconductor power device industry wastes contain gallium as GaN and Ga{sub 0.97}N{sub 0.9}O{sub 0.09} is a concern for the environment which can add value through recycling. In the present study, this waste is recycled through mechanochemical oxidation and leaching. For quantitative recovery of gallium, two different mechanochemical oxidation leaching process flow sheets are proposed. In one process, first the Ga{sub 0.97}N{sub 0.9}O{sub 0.09} of the MOCVD dust is leached at the optimum condition. Subsequently, the leachmore » residue is mechanochemically treated, followed by oxidative annealing and finally re-leached. In the second process, the MOCVD waste dust is mechanochemically treated, followed by oxidative annealing and finally leached. Both of these treatment processes are competitive with each other, appropriate for gallium leaching and treatment of the waste MOCVD dust. Without mechanochemical oxidation, 40.11 and 1.86 w/w% of gallium and Indium are leached using 4 M HCl, 100 °C and pulp density of 100 kg/m{sup 3,} respectively. After mechanochemical oxidation, both these processes achieved 90 w/w% of gallium and 1.86 w/w% of indium leaching at their optimum condition. - Highlights: • Waste MOCVD dust is treated through mechanochemical leaching. • GaN is hardly leached, and converted to NaGaO{sub 2} through ball milling and annealing. • Process for gallium recovery from waste MOCVD dust has been developed. • Thermal analysis and phase properties of GaN to Ga{sub 2}O{sub 3} and GaN to NaGaO{sub 2} is revealed. • Solid-state chemistry involved in this process is reported.« less

Characteristics of Superjunction Lateral-Double-Diffusion Metal Oxide Semiconductor Field Effect Transistor and Degradation after Electrical Stress

NASA Astrophysics Data System (ADS)

Lin, Jyh‑Ling; Lin, Ming‑Jang; Lin, Li‑Jheng

2006-04-01

The superjunction lateral double diffusion metal oxide semiconductor field effect has recently received considerable attention. Introducing heavily doped p-type strips to the n-type drift region increases the horizontal depletion capability. Consequently, the doping concentration of the drift region is higher and the conduction resistance is lower than those of conventional lateral-double-diffusion metal oxide semiconductor field effect transistors (LDMOSFETs). These characteristics may increase breakdown voltage (\\mathit{BV}) and reduce specific on-resistance (Ron,sp). In this study, we focus on the electrical characteristics of conventional LDMOSFETs on silicon bulk, silicon-on-insulator (SOI) LDMOSFETs and superjunction LDMOSFETs after bias stress. Additionally, the \\mathit{BV} and Ron,sp of superjunction LDMOSFETs with different N/P drift region widths and different dosages are discussed. Simulation tools, including two-dimensional (2-D) TSPREM-4/MEDICI and three-dimensional (3-D) DAVINCI, were employed to determine the device characteristics.

Blue/pink/purple electroluminescence from metal-oxide-semiconductor devices fabricated by spin-coating of [tantalum:(gadolinium/praseodymium)] and (praseodymium:cerium) organic compounds on silicon

NASA Astrophysics Data System (ADS)

Ohzone, Takashi; Matsuda, Toshihiro; Fukuoka, Ryouhei; Hattori, Fumihiro; Iwata, Hideyuki

2016-08-01

Blue/pink/purple electroluminescence (EL) from metal-oxide-semiconductor (MOS) devices with an indium tin oxide (ITO)/[Gd/(Ta + Gd/Pr)/(Pr + Ce)-Si-O] insulator layer/n+-Si substrate surface is reported. The insulator layers were fabricated from organic liquid sources of Gd or (Ta + Gd/Pr)/(Pr + Ce) mixtures, which were spin-coated on the n+-Si substrate and annealed at 950 °C for 30 min in air. The EL emission could be observed by the naked eye in the dark in the Fowler-Nordheim (FN) tunnel current regions. Peak wavelengths in the measured EL spectra were independent of the positive current. The EL intensity ratio of ultraviolet (UV) to the visible range varied with the composition ratio of the (Ta + Gd) liquids, and an optimum Ta to Gd ratio existed for the strongest blue emission, which could be attributed to the Ta-related oxide/silicate. The pink EL of the device fabricated with the (\\text{Ta}:\\text{Pr} = 6:4) mixture ratio can be explained by EL emission peaks related to the Pr3+ ions. The purple EL observed from the (\\text{Pr}:\\text{Ce} = 6:4) device corresponds to the strong and broad emission profile near the 357 nm peak, which cannot be assigned to Ce3+ ions. The results suggest that the EL can be attributed to the double-layer oxides with different compositions in the MOS devices. The upper layer consists of various Ta-, Gd-, Pr-, and Ce-related oxides and their silicates, while the lower SiO x -rich layer contributes to the FN current due to the high electric field, and thus the various EL colors.

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

Restorative effect of oxygen annealing on device performance in HfIZO thin-film transistors

NASA Astrophysics Data System (ADS)

Ha, Tae-Jun

2015-03-01

Metal-oxide based thin-film transistors (oxide-TFTs) are very promising for use in next generation electronics such as transparent displays requiring high switching and driving performance. In this study, we demonstrate an optimized process to secure excellent device performance with a favorable shift of the threshold voltage toward 0V in amorphous hafnium-indium-zinc-oxide (a-HfIZO) TFTs by using post-treatment with oxygen annealing. This enhancement results from the improved interfacial characteristics between gate dielectric and semiconductor layers due to the reduction in the density of interfacial states related to oxygen vacancies afforded by oxygen annealing. The device statistics confirm the improvement in the device-to-device and run-to-run uniformity. We also report on the photo-induced stability in such oxide-TFTs against long-term UV irradiation, which is significant for transparent displays.

Three fundamental devices in one: a reconfigurable multifunctional device in two-dimensional WSe2

NASA Astrophysics Data System (ADS)

Dhakras, Prathamesh; Agnihotri, Pratik; Lee, Ji Ung

2017-06-01

The three pillars of semiconductor device technologies are (1) the p-n diode, (2) the metal-oxide-semiconductor field-effect transistor and (3) the bipolar junction transistor. They have enabled the unprecedented growth in the field of information technology that we see today. Until recently, the technological revolution for better, faster and more efficient devices has been governed by scaling down the device dimensions following Moore’s Law. With the slowing of Moore’s law, there is a need for alternative materials and computing technologies that can continue the advancement in functionality. Here, we describe a single, dynamically reconfigurable device that implements these three fundamental device functions. The device uses buried gates to achieve n- and p-channels and fits into a larger effort to develop devices with enhanced functionalities, including logic functions, over device scaling. As they are all surface conducting devices, we use one material parameter, the interface trap density of states, to describe the key figure-of-merit of each device.

An Ultrasensitive Organic Semiconductor NO2 Sensor Based on Crystalline TIPS-Pentacene Films.

PubMed

Wang, Zi; Huang, Lizhen; Zhu, Xiaofei; Zhou, Xu; Chi, Lifeng

2017-10-01

Organic semiconductor gas sensor is one of the promising candidates of room temperature operated gas sensors with high selectivity. However, for a long time the performance of organic semiconductor sensors, especially for the detection of oxidizing gases, is far behind that of the traditional metal oxide gas sensors. Although intensive attempts have been made to address the problem, the performance and the understanding of the sensing mechanism are still far from sufficient. Herein, an ultrasensitive organic semiconductor NO 2 sensor based on 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPS-petacene) is reported. The device achieves a sensitivity over 1000%/ppm and fast response/recovery, together with a low limit of detection (LOD) of 20 ppb, all of which reach the level of metal oxide sensors. After a comprehensive analysis on the morphology and electrical properties of the organic films, it is revealed that the ultrahigh performance is largely related to the film charge transport ability, which was less concerned in the studies previously. And the combination of efficient charge transport and low original charge carrier concentration is demonstrated to be an effective access to obtain high performance organic semiconductor gas sensors. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Development of silicon carbide semiconductor devices for high temperature applications

NASA Technical Reports Server (NTRS)

Matus, Lawrence G.; Powell, J. Anthony; Petit, Jeremy B.

1991-01-01

The semiconducting properties of electronic grade silicon carbide crystals, such as wide energy bandgap, make it particularly attractive for high temperature applications. Applications for high temperature electronic devices include instrumentation for engines under development, engine control and condition monitoring systems, and power conditioning and control systems for space platforms and satellites. Discrete prototype SiC devices were fabricated and tested at elevated temperatures. Grown p-n junction diodes demonstrated very good rectification characteristics at 870 K. A depletion-mode metal-oxide-semiconductor field-effect transistor was also successfully fabricated and tested at 770 K. While optimization of SiC fabrication processes remain, it is believed that SiC is an enabling high temperature electronic technology.

Training and operation of an integrated neuromorphic network based on metal-oxide memristors.

PubMed

Prezioso, M; Merrikh-Bayat, F; Hoskins, B D; Adam, G C; Likharev, K K; Strukov, D B

2015-05-07

Despite much progress in semiconductor integrated circuit technology, the extreme complexity of the human cerebral cortex, with its approximately 10(14) synapses, makes the hardware implementation of neuromorphic networks with a comparable number of devices exceptionally challenging. To provide comparable complexity while operating much faster and with manageable power dissipation, networks based on circuits combining complementary metal-oxide-semiconductors (CMOSs) and adjustable two-terminal resistive devices (memristors) have been developed. In such circuits, the usual CMOS stack is augmented with one or several crossbar layers, with memristors at each crosspoint. There have recently been notable improvements in the fabrication of such memristive crossbars and their integration with CMOS circuits, including first demonstrations of their vertical integration. Separately, discrete memristors have been used as artificial synapses in neuromorphic networks. Very recently, such experiments have been extended to crossbar arrays of phase-change memristive devices. The adjustment of such devices, however, requires an additional transistor at each crosspoint, and hence these devices are much harder to scale than metal-oxide memristors, whose nonlinear current-voltage curves enable transistor-free operation. Here we report the experimental implementation of transistor-free metal-oxide memristor crossbars, with device variability sufficiently low to allow operation of integrated neural networks, in a simple network: a single-layer perceptron (an algorithm for linear classification). The network can be taught in situ using a coarse-grain variety of the delta rule algorithm to perform the perfect classification of 3 × 3-pixel black/white images into three classes (representing letters). This demonstration is an important step towards much larger and more complex memristive neuromorphic networks.

Design of Contact Electrodes for Semiconductor Nanowire Solar Energy Harvesting Devices.

PubMed

Lin, Tzuging; Ramadurgam, Sarath; Yang, Chen

2017-04-12

Transparent, low-resistive contacts are critical for efficient solar energy harvesting devices. It is important to reconsider the material choices and electrode design as devices move from 2D films to 1D nanostructures. In this paper, we study the effectiveness of indium tin oxide (ITO) and metals, such as Ag and Cu, as contacts in 2D and 1D systems. Although ITO has been studied extensively and developed into an effective transparent contact for 2D devices, our results show that effectiveness does not translate to 1D systems. Particularly with consideration of resistance requirement, nanowires with metal shells as contacts enable better absorption within the semiconductor as compared to ITO. Furthermore, there is a strong dependence of contact performance on the semiconductor band gap and diameter of nanowires. We found that metal contacts outperform ITO for nanowire devices, regardless of the sheet resistance constraint, in the regime of diameters less than 100 nm and band-gaps greater than 1 eV. These metal shells optimized for best absorption are significantly thinner than ITO, which enables for the design of devices with high nanowire number density and consequently higher device efficiencies.

Review of - SiC wide-bandgap heterostructure properties as an alternate semiconductor material

NASA Astrophysics Data System (ADS)

Rajput Priti, J.; Patankar, Udayan S.; Koel, Ants; Nitnaware, V. N.

2018-05-01

Silicon substance (is also known as Quartz) is an abundant in nature and the electrical properties it exhibits, plays a vital role in developing its usage in the field of semiconductor. More than decades we can say that Silicon has shown desirable signs but at the later parts it has shown some research potential for development of alternative material as semiconductor devices. This need has come to light as we started scaling down in size of the Silicon material and up in speed. This semiconductor material started exhibiting several fundamental physical limits that include the minimum gate oxide thickness and the maximum saturation velocity of carriers which determines the operation frequency. Though the alternative semiconductors provide some answers (such as III-V's for high speed devices) for a path to skirt these problems, there also may be some ways to extend the life of silicon itself. Two paths are used as for alternative semiconductors i.e alternative gate dielectrics and silicon-based heterostructures. The SiC material has some strength properties under different conditions and find out the defects available in the material.

SEM evaluation of metallization on semiconductors. [Scanning Electron Microscope

NASA Technical Reports Server (NTRS)

Fresh, D. L.; Adolphsen, J. W.

1974-01-01

A test method for the evaluation of metallization on semiconductors is presented and discussed. The method has been prepared in MIL-STD format for submittal as a proposed addition to MIL-STD-883. It is applicable to discrete devices and to integrated circuits and specifically addresses batch-process oriented defects. Quantitative accept/reject criteria are given for contact windows, other oxide steps, and general interconnecting metallization. Figures are provided that illustrate typical types of defects. Apparatus specifications, sampling plans, and specimen preparation and examination requirements are described. Procedures for glassivated devices and for multi-metal interconnection systems are included.

Submicron Silicon MOSFET

NASA Technical Reports Server (NTRS)

Daud, T.

1986-01-01

Process for making metal-oxide/semiconductor field-effect transistors (MOSFET's) results in gate-channel lengths of only few hundred angstroms about 100 times as small as state-of-the-art devices. Gates must be shortened to develop faster MOSFET's; proposed fabrication process used to study effects of size reduction in MOS devices and eventually to build practical threedimensional structures.

High performance low voltage organic field effect transistors on plastic substrate for amplifier circuits

NASA Astrophysics Data System (ADS)

Houin, G.; Duez, F.; Garcia, L.; Cantatore, E.; Torricelli, F.; Hirsch, L.; Belot, D.; Pellet, C.; Abbas, M.

2016-09-01

The high performance air stable organic semiconductor small molecule dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT) was chosen as active layer for field effect transistors built to realize flexible amplifier circuits. Initial device on rigid Si/SiO2 substrate showed appreciable performance with hysteresis-free characteristics. A number of approaches were applied to simplify the process, improve device performance and decrease the operating voltage: they include an oxide interfacial layer to decrease contact resistance; a polymer passivation layer to optimize semiconductor/dielectric interface and an anodized high-k oxide as dielectric layer for low voltage operation. The devices fabricated on plastic substrate yielded excellent electrical characteristics, showing mobility of 1.6 cm2/Vs, lack of hysteresis, operation below 5 V and on/off current ratio above 105. An OFET model based on variable ranging hopping theory was used to extract the relevant parameters from the transfer and output characteristics, which enabled us to simulate our devices achieving reasonable agreement with the measurements

Ferroelectricity in Covalently functionalized Two-dimensional Materials: Integration of High-mobility Semiconductors and Nonvolatile Memory.

PubMed

Wu, Menghao; Dong, Shuai; Yao, Kailun; Liu, Junming; Zeng, Xiao Cheng

2016-11-09

Realization of ferroelectric semiconductors by conjoining ferroelectricity with semiconductors remains a challenging task because most present-day ferroelectric materials are unsuitable for such a combination due to their wide bandgaps. Herein, we show first-principles evidence toward the realization of a new class of two-dimensional (2D) ferroelectric semiconductors through covalent functionalization of many prevailing 2D materials. Members in this new class of 2D ferroelectric semiconductors include covalently functionalized germanene, and stanene (Nat. Commun. 2014, 5, 3389), as well as MoS 2 monolayer (Nat. Chem. 2015, 7, 45), covalent functionalization of the surface of bulk semiconductors such as silicon (111) (J. Phys. Chem. B 2006, 110 , 23898), and the substrates of oxides such as silica with self-assembly monolayers (Nano Lett. 2014, 14, 1354). The newly predicted 2D ferroelectric semiconductors possess high mobility, modest bandgaps, and distinct ferroelectricity that can be exploited for developing various heterostructural devices with desired functionalities. For example, we propose applications of the 2D materials as 2D ferroelectric field-effect transistors with ultrahigh on/off ratio, topological transistors with Dirac Fermions switchable between holes and electrons, ferroelectric junctions with ultrahigh electro-resistance, and multiferroic junctions for controlling spin by electric fields. All these heterostructural devices take advantage of the combination of high-mobility semiconductors with fast writing and nondestructive reading capability of nonvolatile memory, thereby holding great potential for the development of future multifunctional devices.

Polarographic carbon dioxide transducer amplifier

NASA Technical Reports Server (NTRS)

Stillman, G.

1971-01-01

Electronic amplifier contains matched pair of metal oxide semiconductor field effect transistor devices which have high input impedance and long-term stability. Thermistor in feedback loop provides temperature compensation for large drifts in the sensor.

GaN metal-oxide-semiconductor field-effect transistors on AlGaN/GaN heterostructure with recessed gate

NASA Astrophysics Data System (ADS)

Wang, Qingpeng; Ao, Jin-Ping; Wang, Pangpang; Jiang, Ying; Li, Liuan; Kawaharada, Kazuya; Liu, Yang

2015-04-01

GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure with a recess gate were fabricated and characterized. The device showed good pinch-off characteristics and a maximum field-effect mobility of 145.2 cm2·V-1·s-1. The effects of etching gas of Cl2 and SiCl4 were investigated in the gate recess process. SiCl4-etched devices showed higher channel mobility and lower threshold voltage. Atomic force microscope measurement was done to investigate the etching profile with different etching protection mask. Compared with photoresist, SiO2-masked sample showed lower surface roughness and better profile with stepper sidewall and weaker trenching effect resulting in higher channel mobility in the MOSFET.

Origin of the performances degradation of two-dimensional-based metal-oxide-semiconductor field effect transistors in the sub-10 nm regime: A first-principles study

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Anh Khoa Augustin; IMEC, 75 Kapeldreef, B-3001 Leuven; Pourtois, Geoffrey

2016-01-25

The impact of the scaling of the channel length on the performances of metal-oxide-semiconductor field effect transistors, based on two-dimensional (2D) channel materials, is theoretically investigated, using density functional theory combined with the non-equilibrium Green's function method. It is found that the scaling of the channel length below 10 nm leads to strong device performance degradations. Our simulations reveal that this degradation is essentially due to the tunneling current flowing between the source and the drain in these aggressively scaled devices. It is shown that this electron tunneling process is modulated by the effective mass of the 2D channel material, andmore » sets the limit of the scaling in future transistor designs.« less

Comparative Study of HfTa-based gate-dielectric Ge metal-oxide-semiconductor capacitors with and without AlON interlayer

NASA Astrophysics Data System (ADS)

Xu, J. P.; Zhang, X. F.; Li, C. X.; Chan, C. L.; Lai, P. T.

2010-04-01

The electrical properties and high-field reliability of HfTa-based gate-dielectric metal-oxide-semiconductor (MOS) devices with and without AlON interlayer on Ge substrate are investigated. Experimental results show that the MOS capacitor with HfTaON/AlON stack gate dielectric exhibits low interface-state/oxide-charge densities, low gate leakage, small capacitance equivalent thickness (˜1.1 nm), and high dielectric constant (˜20). All of these should be attributed to the blocking role of the ultrathin AlON interlayer against interdiffusions of Ge, Hf, and Ta and penetration of O into the Ge substrate, with the latter effectively suppressing the unintentional formation of unstable poor-quality low- k GeO x and giving a superior AlON/Ge interface. Moreover, incorporation of N into both the interlayer and high- k dielectric further improves the device reliability under high-field stress through the formation of strong N-related bonds.

Atomic switches: atomic-movement-controlled nanodevices for new types of computing

PubMed Central

Hino, Takami; Hasegawa, Tsuyoshi; Terabe, Kazuya; Tsuruoka, Tohru; Nayak, Alpana; Ohno, Takeo; Aono, Masakazu

2011-01-01

Atomic switches are nanoionic devices that control the diffusion of metal cations and their reduction/oxidation processes in the switching operation to form/annihilate a metal atomic bridge, which is a conductive path between two electrodes in the on-state. In contrast to conventional semiconductor devices, atomic switches can provide a highly conductive channel even if their size is of nanometer order. In addition to their small size and low on-resistance, their nonvolatility has enabled the development of new types of programmable devices, which may achieve all the required functions on a single chip. Three-terminal atomic switches have also been developed, in which the formation and annihilation of a metal atomic bridge between a source electrode and a drain electrode are controlled by a third (gate) electrode. Three-terminal atomic switches are expected to enhance the development of new types of logic circuits, such as nonvolatile logic. The recent development of atomic switches that use a metal oxide as the ionic conductive material has enabled the integration of atomic switches with complementary metal-oxide-semiconductor (CMOS) devices, which will facilitate the commercialization of atomic switches. The novel characteristics of atomic switches, such as their learning and photosensing abilities, are also introduced in the latter part of this review. PMID:27877376

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

NASA Astrophysics Data System (ADS)

Held, Martin; Schießl, Stefan P.; Miehler, Dominik; Gannott, Florentina; Zaumseil, Jana

2015-08-01

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfOx) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states at the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100-300 nF/cm2) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfOx dielectrics.

Interfaces of electrical contacts in organic semiconductor devices

NASA Astrophysics Data System (ADS)

Demirkan, Korhan

Progress in organic semiconductor devices relies on better understanding of interfaces as well as material development. The engineering of interfaces that exhibit low resistance, low operating voltage and long-term stability to minimize device degradation is one of the crucial requirements. Photoelectron spectroscopy is a powerful technique to study the metal-semiconductor interfaces, allowing: (i) elucidation of the energy levels of the semiconductor and the contacts that determine Schottky barrier height, (ii) inspection of electrical interactions (such as charge transfer, dipole formation, formation of induced density of states or formation of polaron/bi-polaron states) that effect the energy level alignment, (iii) determination of interfacial chemistry, and (iv) estimation of interface morphology. In this thesis, we have used photoelectron spectroscopy extensively for detailed analysis of the metal organic semiconductor interfaces. In this study, we demonstrate the use of photoelectron spectroscopy for construction of energy level diagrams and display some results related to chemical tailoring of materials for engineering interfaces with lowered Schottky barriers. Following our work on the energy level alignment of poly(p-phenyene vinylene) based organic semiconductors on various substrates [Au, indium tin oxide, Si (with native oxide) and Al (with native oxide)], we tested controlling the energy level alignment by using polar self assembled molecules (SAMs). Photoelectron spectroscopy showed that, by introducing SAMs on the Au surface, we successfully changed the effective work function of Au surface. We found that in this case, the change in the effective work function of the metal surface was not reflected as a shift in the energy levels of the organic semiconductor, as opposed to the results achieved with different substrate materials. To investigate the chemical interactions at the metal/organic interface, we studied the metallization of poly(2-methoxy-5,2'-ethyl-hexyloxy-phenylene vinylene) (MEH-PPV), polystyrene (PS) and ozone treated polystyrene (PS-O3) surfaces by thermal deposition of aluminum. Photoelectron spectroscopy showed the degree of chemical interaction between Al and each polymer, for MEH-PPV, the chemical interactions were mainly through the C-O present in the side chain of the polymer structure. The chemical interaction of Al with polystyrene was less significant, but it showed a dramatic increase after ozone treatment of the polystyrene surface (due to the formation of exposed oxygen sites). Formation of metal oxide and metal-organic compound is detected during the Al metallization of MEH-PPV and ozone-treated PS surfaces. Our results showed that the condensation of Al on polymer surfaces is highly dependent on surface reactivity. Enormous differences were observed for the condensation coefficient of Al on PS and PS-O3 surfaces. For the inert PS surface, results showed that Al atoms poorly wet the polymer surface and form distributed clusters at the surface. Results on reactive polymer surfaces suggest morphology reminiscent of a Stranski-Krastanov-type growth and high contact area. Many studies have shown that the insertion of a thin interlayer of the oxide or fluoride of alkali or alkaline metals between the low work function electrode and the organic semiconductor layers dramatically lowers the onset voltage and increases the efficiency compared to identical devices without the insulating layer. Various modes have been suggested for the mechanism of device performance enhancement. We have investigated the chemical and electrical interaction of (i) LiF with MEH-PPV, (ii) Al with MEH-PPV in the presence of a thin LiF layer at the interface, and finally (iii) the interaction of Al with LiF. AFM and XPS data showed that LiF forms island on the surface. Our data in agreement with various existing models suggested the (i) alteration in the electronic properties under applied bias, (ii) doping of the organic semiconductor, (iii) formation of metal alloy (Au-Li). In addition to the possible electrical modifications at the interface suggested previously, our data also suggest a change in the film growth on LiF modified surfaces.

An integrated semiconductor device enabling non-optical genome sequencing.

PubMed

Rothberg, Jonathan M; Hinz, Wolfgang; Rearick, Todd M; Schultz, Jonathan; Mileski, William; Davey, Mel; Leamon, John H; Johnson, Kim; Milgrew, Mark J; Edwards, Matthew; Hoon, Jeremy; Simons, Jan F; Marran, David; Myers, Jason W; Davidson, John F; Branting, Annika; Nobile, John R; Puc, Bernard P; Light, David; Clark, Travis A; Huber, Martin; Branciforte, Jeffrey T; Stoner, Isaac B; Cawley, Simon E; Lyons, Michael; Fu, Yutao; Homer, Nils; Sedova, Marina; Miao, Xin; Reed, Brian; Sabina, Jeffrey; Feierstein, Erika; Schorn, Michelle; Alanjary, Mohammad; Dimalanta, Eileen; Dressman, Devin; Kasinskas, Rachel; Sokolsky, Tanya; Fidanza, Jacqueline A; Namsaraev, Eugeni; McKernan, Kevin J; Williams, Alan; Roth, G Thomas; Bustillo, James

2011-07-20

The seminal importance of DNA sequencing to the life sciences, biotechnology and medicine has driven the search for more scalable and lower-cost solutions. Here we describe a DNA sequencing technology in which scalable, low-cost semiconductor manufacturing techniques are used to make an integrated circuit able to directly perform non-optical DNA sequencing of genomes. Sequence data are obtained by directly sensing the ions produced by template-directed DNA polymerase synthesis using all-natural nucleotides on this massively parallel semiconductor-sensing device or ion chip. The ion chip contains ion-sensitive, field-effect transistor-based sensors in perfect register with 1.2 million wells, which provide confinement and allow parallel, simultaneous detection of independent sequencing reactions. Use of the most widely used technology for constructing integrated circuits, the complementary metal-oxide semiconductor (CMOS) process, allows for low-cost, large-scale production and scaling of the device to higher densities and larger array sizes. We show the performance of the system by sequencing three bacterial genomes, its robustness and scalability by producing ion chips with up to 10 times as many sensors and sequencing a human genome.

Thin film photovoltaic device

DOEpatents

Catalano, Anthony W.; Bhushan, Manjul

1982-01-01

A thin film photovoltaic solar cell which utilizes a zinc phosphide semiconductor is of the homojunction type comprising an n-type conductivity region forming an electrical junction with a p-type region, both regions consisting essentially of the same semiconductor material. The n-type region is formed by treating zinc phosphide with an extrinsic dopant such as magnesium. The semiconductor is formed on a multilayer substrate which acts as an opaque contact. Various transparent contacts may be used, including a thin metal film of the same chemical composition as the n-type dopant or conductive oxides or metal grids.

Prediction of the thermal annealing of thick oxide metal-oxide-semiconductor dosimeters irradiated in a harsh radiation environment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ravotti, F.; Glaser, M.; Saigne, F.

Radiation-sensing metal-oxide-semiconductor field-effect transistors produced by the laboratory LAAS-CNRS were exposed to a harsh hadron field that represents the real radiation environment expected at the CERN Large Hadron Collider experiments. The long-term stability of the transistor's I{sub ds}-V{sub gs} characteristic was investigated using the isochronal annealing technique. In this work, devices exposed to high intensity hadron levels ({phi}{>=}10{sup 12} neutrons/cm{sup 2}) show evidences of displacement damages in the I{sub ds}-V{sub gs} annealing behavior. By comparing experimental and simulated results over 14 months, the isochronal annealing method, originally devoted to oxide trapped charge, is shown to enable prediction of the recoverymore » of silicon bulk defects.« less

Nanoscale patterning of electronic devices at the amorphous LaAlO3/SrTiO3 oxide interface using an electron sensitive polymer mask

NASA Astrophysics Data System (ADS)

Bjørlig, Anders V.; von Soosten, Merlin; Erlandsen, Ricci; Dahm, Rasmus Tindal; Zhang, Yu; Gan, Yulin; Chen, Yunzhong; Pryds, Nini; Jespersen, Thomas S.

2018-04-01

A simple approach is presented for designing complex oxide mesoscopic electronic devices based on the conducting interfaces of room temperature grown LaAlO3/SrTiO3 heterostructures. The technique is based entirely on methods known from conventional semiconductor processing technology, and we demonstrate a lateral resolution of ˜100 nm. We study the low temperature transport properties of nanoscale wires and demonstrate the feasibility of the technique for defining in-plane gates allowing local control of the electrostatic environment in mesoscopic devices.

Active pixel sensor array with multiresolution readout

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Kemeny, Sabrina E. (Inventor); Pain, Bedabrata (Inventor)

1999-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. The imaging device can also include an electronic shutter formed on the substrate adjacent the photogate, and/or a storage section to allow for simultaneous integration. In addition, the imaging device can include a multiresolution imaging circuit to provide images of varying resolution. The multiresolution circuit could also be employed in an array where the photosensitive portion of each pixel cell is a photodiode. This latter embodiment could further be modified to facilitate low light imaging.

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices

PubMed Central

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines. PMID:25763152

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices.

PubMed

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.

Metal Contacts in Semiconductors.

DTIC Science & Technology

1983-11-01

greater understanding of the role that imperfec- tions, defects etc. play in the formation of Schottk~y barriers and related devices. In section 1 of...these effects. In Section 2 of this report we consider the role of surface defects in the pinning of the Fermi level at free semiconductor surfaces and...in the adsorption and oxidation processes involved when these surfaces interact with gases and metals. The role of imperfections at metal

Screening-Engineered Field-Effect Solar Cells

DTIC Science & Technology

2012-01-01

virtually any semiconductor, including the promising but hard-to- dope metal oxides, sulfides, and phosphides.3 Prototype SFPV devices have been...MIS interface. Unfortu- nately, MIS cells, though sporting impressive efficiencies,4−6 typically have short operating lifetimes due to surface state...instability at the MIS interface.7 Methods aimed at direct field- effect “ doping ” of semiconductors, in which the voltage is externally applied to a gate

Large current modulation and tunneling magnetoresistance change by a side-gate electric field in a GaMnAs-based vertical spin metal-oxide-semiconductor field-effect transistor.

PubMed

Kanaki, Toshiki; Yamasaki, Hiroki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2018-05-08

A vertical spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) is a promising low-power device for the post scaling era. Here, using a ferromagnetic-semiconductor GaMnAs-based vertical spin MOSFET with a GaAs channel layer, we demonstrate a large drain-source current I DS modulation by a gate-source voltage V GS with a modulation ratio up to 130%, which is the largest value that has ever been reported for vertical spin field-effect transistors thus far. We find that the electric field effect on indirect tunneling via defect states in the GaAs channel layer is responsible for the large I DS modulation. This device shows a tunneling magnetoresistance (TMR) ratio up to ~7%, which is larger than that of the planar-type spin MOSFETs, indicating that I DS can be controlled by the magnetization configuration. Furthermore, we find that the TMR ratio can be modulated by V GS . This result mainly originates from the electric field modulation of the magnetic anisotropy of the GaMnAs ferromagnetic electrodes as well as the potential modulation of the nonmagnetic semiconductor GaAs channel layer. Our findings provide important progress towards high-performance vertical spin MOSFETs.

Optical investigations of nanostructured oxides and semiconductors

NASA Astrophysics Data System (ADS)

Irvin, Patrick Richard

This work is motivated by the prospect of building a quantum computer: a device that would allow physicists to explore quantum mechanics more deeply, and allow everyone else to keep their credit card numbers safe on the Internet. In this thesis we explore two classes of materials that are relevant to a proposed quantum computer architecture: oxides and semiconductors. Systems with a ferroelectric to paraelectric transition in the vicinity of room temperature are useful for devices. We investigate strained-SrTiO 3, which is ferroelectric at room-temperature, and a composite material of (Ba,Sr)TiO3 and MgO. We present optical techniques to measure electron spin dynamics with GHz dynamical bandwidth, transform-limited spectral selectivity, and phase-sensitive detection. We demonstrate this technique by measuring GHz-spin precession in n-GaAs. We also describe our efforts to optically probe InAs/GaAs and GaAs/AlGaAs quantum dots. Nanoscale devices with photonic properties have been the subject of intense research over the past decade. Potential nanophotonic applications include communications, polarization-sensitive detectors, and solar power generation. Here we show photosensitivity of a nanoscale detector written at the interface between two oxides.

Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications.

PubMed

Jeon, Sanghun; Park, Sungho; Song, Ihun; Hur, Ji-Hyun; Park, Jaechul; Kim, Hojung; Kim, Sunil; Kim, Sangwook; Yin, Huaxiang; Chung, U-In; Lee, Eunha; Kim, Changjung

2011-01-01

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

Review on analog/radio frequency performance of advanced silicon MOSFETs

NASA Astrophysics Data System (ADS)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

Comprehensive review on the development of high mobility in oxide thin film transistors

NASA Astrophysics Data System (ADS)

Choi, Jun Young; Lee, Sang Yeol

2017-11-01

Oxide materials are one of the most advanced key technology in the thin film transistors (TFTs) for the high-end of device applications. Amorphous oxide semiconductors (AOSs) have leading technique for flat panel display (FPD), active matrix organic light emitting display (AMOLED) and active matrix liquid crystal display (AMLCD) due to their excellent electrical characteristics, such as field effect mobility ( μ FE ), subthreshold swing (S.S) and threshold voltage ( V th ). Covalent semiconductor like amorphous silicon (a-Si) is attributed to the anti-bonding and bonding states of Si hybridized orbitals. However, AOSs have not grain boundary and excellent performances originated from the unique characteristics of AOS which is the direct orbital overlap between s orbitals of neighboring metal cations. High mobility oxide TFTs have gained attractive attention during the last few years and today in display industries. It is progressively developed to increase the mobility either by exploring various oxide semiconductors or by adopting new TFT structures. Mobility of oxide thin film transistor has been rapidly increased from single digit to higher than 100 cm2/V·s in a decade. In this review, we discuss on the comprehensive review on the mobility of oxide TFTs in a decade and propose bandgap engineering and novel structure to enhance the electrical characteristics of oxide TFTs.

Upper-Bound Estimates Of SEU in CMOS

NASA Technical Reports Server (NTRS)

Edmonds, Larry D.

1990-01-01

Theory of single-event upsets (SEU) (changes in logic state caused by energetic charged subatomic particles) in complementary metal oxide/semiconductor (CMOS) logic devices extended to provide upper-bound estimates of rates of SEU when limited experimental information available and configuration and dimensions of SEU-sensitive regions of devices unknown. Based partly on chord-length-distribution method.

Economic analysis of crystal growth in space

NASA Technical Reports Server (NTRS)

Ulrich, D. R.; Chung, A. M.; Yan, C. S.; Mccreight, L. R.

1972-01-01

Many advanced electronic technologies and devices for the 1980's are based on sophisticated compound single crystals, i.e. ceramic oxides and compound semiconductors. Space processing of these electronic crystals with maximum perfection, purity, and size is suggested. No ecomonic or technical justification was found for the growth of silicon single crystals for solid state electronic devices in space.

Study on the photoresponse of amorphous In-Ga-Zn-O and zinc oxynitride semiconductor devices by the extraction of sub-gap-state distribution and device simulation.

PubMed

Jang, Jun Tae; Park, Jozeph; Ahn, Byung Du; Kim, Dong Myong; Choi, Sung-Jin; Kim, Hyun-Suk; Kim, Dae Hwan

2015-07-22

Persistent photoconduction (PPC) is a phenomenon that limits the application of oxide semiconductor thin-film transistors (TFTs) in optical sensor-embedded displays. In the present work, a study on zinc oxynitride (ZnON) semiconductor TFTs based on the combination of experimental results and device simulation is presented. Devices incorporating ZnON semiconductors exhibit negligible PPC effects compared with amorphous In-Ga-Zn-O (a-IGZO) TFTs, and the difference between the two types of materials are examined by monochromatic photonic C-V spectroscopy (MPCVS). The latter method allows the estimation of the density of subgap states in the semiconductor, which may account for the different behavior of ZnON and IGZO materials with respect to illumination and the associated PPC. In the case of a-IGZO TFTs, the oxygen flow rate during the sputter deposition of a-IGZO is found to influence the amount of PPC. Small oxygen flow rates result in pronounced PPC, and large densities of valence band tail (VBT) states are observed in the corresponding devices. This implies a dependence of PPC on the amount of oxygen vacancies (VO). On the other hand, ZnON has a smaller bandgap than a-IGZO and contains a smaller density of VBT states over the entire range of its bandgap energy. Here, the concept of activation energy window (AEW) is introduced to explain the occurrence of PPC effects by photoinduced electron doping, which is likely to be associated with the formation of peroxides in the semiconductor. The analytical methodology presented in this report accounts well for the reduction of PPC in ZnON TFTs, and provides a quantitative tool for the systematic development of phototransistors for optical sensor-embedded interactive displays.

Nitride passivation reduces interfacial traps in atomic-layer-deposited Al2O3/GaAs (001) metal-oxide-semiconductor capacitors using atmospheric metal-organic chemical vapor deposition

NASA Astrophysics Data System (ADS)

Aoki, T.; Fukuhara, N.; Osada, T.; Sazawa, H.; Hata, M.; Inoue, T.

2014-07-01

Using an atmospheric metal-organic chemical vapor deposition system, we passivated GaAs with AlN prior to atomic layer deposition of Al2O3. This AlN passivation incorporated nitrogen at the Al2O3/GaAs interface, improving the capacitance-voltage (C-V) characteristics of the resultant metal-oxide-semiconductor capacitors (MOSCAPs). The C-V curves of these devices showed a remarkable reduction in the frequency dispersion of the accumulation capacitance. Using the conductance method at various temperatures, we extracted the interfacial density of states (Dit). The Dit was reduced over the entire GaAs band gap. In particular, these devices exhibited Dit around the midgap of less than 4 × 1012 cm-2eV-1, showing that AlN passivation effectively reduced interfacial traps in the MOS structure.

A Self-Aligned InGaAs Quantum-Well Metal-Oxide-Semiconductor Field-Effect Transistor Fabricated through a Lift-Off-Free Front-End Process

NASA Astrophysics Data System (ADS)

Lin, Jianqiang; Kim, Tae-Woo; Antoniadis, Dimitri A.; del Alamo, Jesús A.

2012-06-01

We present a novel n-type InGaAs quantum-well metal-oxide-semiconductor field-effect transistor (QW-MOSFET) fabricated by a self-aligned gate-last process and investigate relevant Si-like manufacturing issues in future III-V MOSFETs. The device structure features a composite InP/Al2O3 gate barrier with a capacitance equivalent thickness (CET) of 3 nm and non alloyed Mo ohmic contacts. We have found that RIE introduces significant damage to the intrinsic device resulting in poor current drive and subthreshold swing. The effect is largely removed through a thermal annealing step. Thermally annealed QW-MOSFETs exhibit a subthreshold swing of 95 mV/dec, indicative of excellent interfacial characteristics. The peak mobility of the MOSFET is 2780 cm2 V-1 s-1.

Multifunctional Hybrid Multilayer Gate Dielectrics with Tunable Surface Energy for Ultralow-Power Organic and Amorphous Oxide Thin-Film Transistors.

PubMed

Byun, Hye-Ran; You, Eun-Ah; Ha, Young-Geun

2017-03-01

For large-area, printable, and flexible electronic applications using advanced semiconductors, novel dielectric materials with excellent capacitance, insulating property, thermal stability, and mechanical flexibility need to be developed to achieve high-performance, ultralow-voltage operation of thin-film transistors (TFTs). In this work, we first report on the facile fabrication of multifunctional hybrid multilayer gate dielectrics with tunable surface energy via a low-temperature solution-process to produce ultralow-voltage organic and amorphous oxide TFTs. The hybrid multilayer dielectric materials are constructed by iteratively stacking bifunctional phosphonic acid-based self-assembled monolayers combined with ultrathin high-k oxide layers. The nanoscopic thickness-controllable hybrid dielectrics exhibit the superior capacitance (up to 970 nF/cm 2 ), insulating property (leakage current densities <10 -7 A/cm 2 ), and thermal stability (up to 300 °C) as well as smooth surfaces (root-mean-square roughness <0.35 nm). In addition, the surface energy of the hybrid multilayer dielectrics are easily changed by switching between mono- and bifunctional phosphonic acid-based self-assembled monolayers for compatible fabrication with both organic and amorphous oxide semiconductors. Consequently, the hybrid multilayer dielectrics integrated into TFTs reveal their excellent dielectric functions to achieve high-performance, ultralow-voltage operation (< ± 2 V) for both organic and amorphous oxide TFTs. Because of the easily tunable surface energy, the multifunctional hybrid multilayer dielectrics can also be adapted for various organic and inorganic semiconductors, and metal gates in other device configurations, thus allowing diverse advanced electronic applications including ultralow-power and large-area electronic devices.

Cadmium-free junction fabrication process for CuInSe.sub.2 thin film solar cells

DOEpatents

Ramanathan, Kannan V.; Contreras, Miguel A.; Bhattacharya, Raghu N.; Keane, James; Noufi, Rommel

1999-01-01

The present invention provides an economical, simple, dry and controllable semiconductor layer junction forming process to make cadmium free high efficiency photovoltaic cells having a first layer comprised primarily of copper indium diselenide having a thin doped copper indium diselenide n-type region, generated by thermal diffusion with a group II(b) element such as zinc, and a halide, such as chlorine, and a second layer comprised of a conventional zinc oxide bilayer. A photovoltaic device according the present invention includes a first thin film layer of semiconductor material formed primarily from copper indium diselenide. Doping of the copper indium diselenide with zinc chloride is accomplished using either a zinc chloride solution or a solid zinc chloride material. Thermal diffusion of zinc chloride into the copper indium diselenide upper region creates the thin n-type copper indium diselenide surface. A second thin film layer of semiconductor material comprising zinc oxide is then applied in two layers. The first layer comprises a thin layer of high resistivity zinc oxide. The second relatively thick layer of zinc oxide is doped to exhibit low resistivity.

Models of second-order effects in metal-oxide-semiconductor field-effect transistors for computer applications

NASA Technical Reports Server (NTRS)

Benumof, Reuben; Zoutendyk, John; Coss, James

1988-01-01

Second-order effects in metal-oxide-semiconductor field-effect transistors (MOSFETs) are important for devices with dimensions of 2 microns or less. The short and narrow channel effects and drain-induced barrier lowering primarily affect threshold voltage, but formulas for drain current must also take these effects into account. In addition, the drain current is sensitive to channel length modulation due to pinch-off or velocity saturation and is diminished by electron mobility degradation due to normal and lateral electric fields in the channel. A model of a MOSFET including these considerations and emphasizing charge conservation is discussed.

H+-type and OH--type biological protonic semiconductors and complementary devices

NASA Astrophysics Data System (ADS)

Deng, Yingxin; Josberger, Erik; Jin, Jungho; Rousdari, Anita Fadavi; Helms, Brett A.; Zhong, Chao; Anantram, M. P.; Rolandi, Marco

2013-10-01

Proton conduction is essential in biological systems. Oxidative phosphorylation in mitochondria, proton pumping in bacteriorhodopsin, and uncoupling membrane potentials by the antibiotic Gramicidin are examples. In these systems, H+ hop along chains of hydrogen bonds between water molecules and hydrophilic residues - proton wires. These wires also support the transport of OH- as proton holes. Discriminating between H+ and OH- transport has been elusive. Here, H+ and OH- transport is achieved in polysaccharide- based proton wires and devices. A H+- OH- junction with rectifying behaviour and H+-type and OH--type complementary field effect transistors are demonstrated. We describe these devices with a model that relates H+ and OH- to electron and hole transport in semiconductors. In turn, the model developed for these devices may provide additional insights into proton conduction in biological systems.

H+-type and OH−-type biological protonic semiconductors and complementary devices

PubMed Central

Deng, Yingxin; Josberger, Erik; Jin, Jungho; Rousdari, Anita Fadavi; Helms, Brett A.; Zhong, Chao; Anantram, M. P.; Rolandi, Marco

2013-01-01

Proton conduction is essential in biological systems. Oxidative phosphorylation in mitochondria, proton pumping in bacteriorhodopsin, and uncoupling membrane potentials by the antibiotic Gramicidin are examples. In these systems, H+ hop along chains of hydrogen bonds between water molecules and hydrophilic residues – proton wires. These wires also support the transport of OH− as proton holes. Discriminating between H+ and OH− transport has been elusive. Here, H+ and OH− transport is achieved in polysaccharide- based proton wires and devices. A H+- OH− junction with rectifying behaviour and H+-type and OH−-type complementary field effect transistors are demonstrated. We describe these devices with a model that relates H+ and OH− to electron and hole transport in semiconductors. In turn, the model developed for these devices may provide additional insights into proton conduction in biological systems. PMID:24089083

Self-activated ultrahigh chemosensitivity of oxide thin film nanostructures for transparent sensors

PubMed Central

Moon, Hi Gyu; Shim, Young-Soek; Kim, Do Hong; Jeong, Hu Young; Jeong, Myoungho; Jung, Joo Young; Han, Seung Min; Kim, Jong Kyu; Kim, Jin-Sang; Park, Hyung-Ho; Lee, Jong-Heun; Tuller, Harry L.; Yoon, Seok-Jin; Jang, Ho Won

2012-01-01

One of the top design priorities for semiconductor chemical sensors is developing simple, low-cost, sensitive and reliable sensors to be built in handheld devices. However, the need to implement heating elements in sensor devices, and the resulting high power consumption, remains a major obstacle for the realization of miniaturized and integrated chemoresistive thin film sensors based on metal oxides. Here we demonstrate structurally simple but extremely efficient all oxide chemoresistive sensors with ~90% transmittance at visible wavelengths. Highly effective self-activation in anisotropically self-assembled nanocolumnar tungsten oxide thin films on glass substrate with indium-tin oxide electrodes enables ultrahigh response to nitrogen dioxide and volatile organic compounds with detection limits down to parts per trillion levels and power consumption less than 0.2 microwatts. Beyond the sensing performance, high transparency at visible wavelengths creates opportunities for their use in transparent electronic circuitry and optoelectronic devices with avenues for further functional convergence. PMID:22905319

Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

NASA Astrophysics Data System (ADS)

Tu, Hongen

This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high-performance MEMS devices and electronics can be integrated into flexible substrates. The potential of our technology is enormous. Many wearable and implantable devices can be developed based on this technology.

Thin film photovoltaic device

DOEpatents

Catalano, A.W.; Bhushan, M.

1982-08-03

A thin film photovoltaic solar cell which utilizes a zinc phosphide semiconductor is of the homojunction type comprising an n-type conductivity region forming an electrical junction with a p-type region, both regions consisting essentially of the same semiconductor material. The n-type region is formed by treating zinc phosphide with an extrinsic dopant such as magnesium. The semiconductor is formed on a multilayer substrate which acts as an opaque contact. Various transparent contacts may be used, including a thin metal film of the same chemical composition as the n-type dopant or conductive oxides or metal grids. 5 figs.

Latest progress in gallium-oxide electronic devices

NASA Astrophysics Data System (ADS)

Higashiwaki, Masataka; Wong, Man Hoi; Konishi, Keita; Nakata, Yoshiaki; Lin, Chia-Hung; Kamimura, Takafumi; Ravikiran, Lingaparthi; Sasaki, Kohei; Goto, Ken; Takeyama, Akinori; Makino, Takahiro; Ohshima, Takeshi; Kuramata, Akito; Yamakoshi, Shigenobu; Murakami, Hisashi; Kumagai, Yoshinao

2018-02-01

Gallium oxide (Ga2O3) has emerged as a new competitor to SiC and GaN in the race toward next-generation power switching and harsh environment electronics by virtue of the excellent material properties and the relative ease of mass wafer production. In this proceedings paper, an overview of our recent development progress of Ga2O3 metal-oxide-semiconductor field-effect transistors and Schottky barrier diodes will be reported.

A room-temperature magnetic semiconductor from a ferromagnetic metallic glass

NASA Astrophysics Data System (ADS)

Liu, Wenjian; Zhang, Hongxia; Shi, Jin-An; Wang, Zhongchang; Song, Cheng; Wang, Xiangrong; Lu, Siyuan; Zhou, Xiangjun; Gu, Lin; Louzguine-Luzgin, Dmitri V.; Chen, Mingwei; Yao, Kefu; Chen, Na

2016-12-01

Emerging for future spintronic/electronic applications, magnetic semiconductors have stimulated intense interest due to their promises for new functionalities and device concepts. So far, the so-called diluted magnetic semiconductors attract many attentions, yet it remains challenging to increase their Curie temperatures above room temperature, particularly those based on III-V semiconductors. In contrast to the concept of doping magnetic elements into conventional semiconductors to make diluted magnetic semiconductors, here we propose to oxidize originally ferromagnetic metals/alloys to form new species of magnetic semiconductors. We introduce oxygen into a ferromagnetic metallic glass to form a Co28.6Fe12.4Ta4.3B8.7O46 magnetic semiconductor with a Curie temperature above 600 K. The demonstration of p-n heterojunctions and electric field control of the room-temperature ferromagnetism in this material reflects its p-type semiconducting character, with a mobility of 0.1 cm2 V-1 s-1. Our findings may pave a new way to realize high Curie temperature magnetic semiconductors with unusual multifunctionalities.

SNS Heterojunctions With New Combinations Of Materials

NASA Technical Reports Server (NTRS)

Vasquez, Richard P.; Hunt, Brian D.; Foote, Marc C.

1992-01-01

New combinations of materials proposed for superconductor/normal-metal/superconductor (SNS) heterojunctions in low-temperature electronic devices such as fast switches, magnetometers, and mixers. Epitaxial heterojunctions formed between high-temperature superconductors and either oxide semiconductors or metals. Concept offers alternative to other three-layer heterojunction concepts; physical principles of operation permit SNS devices to have thicker barrier layers and fabricated more easily.

Electroluminescence from metal-oxide-semiconductor devices with erbium-doped CeO{sub 2} films on silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lv, Chunyan; Department of Chemistry, Huzhou University, Zhejiang, Huzhou 313000; Zhu, Chen

2015-04-06

We report on erbium (Er)-related electroluminescence (EL) in the visible and near-infrared (NIR) from metal-oxide-semiconductor (MOS) devices with Er-doped CeO{sub 2} (CeO{sub 2}:Er) films on silicon. The onset voltage of such EL under either forward or reverse bias is smaller than 10 V. Moreover, the EL quenching can be avoidable for the CeO{sub 2}:Er-based MOS devices. Analysis on the current-voltage characteristic of the device indicates that the electron transportation at the EL-enabling voltages under either forward or reverse bias is dominated by trap-assisted tunneling mechanism. Namely, electrons in n{sup +}-Si/ITO can tunnel into the conduction band of CeO{sub 2} host viamore » defect states at sufficiently high forward/reverse bias voltages. Then, a fraction of such electrons are accelerated by electric field to become hot electrons, which impact-excite the Er{sup 3+} ions, thus leading to characteristic emissions. It is believed that this work has laid the foundation for developing viable silicon-based emitters using CeO{sub 2}:Er films.« less

Mechanistic analysis of temperature-dependent current conduction through thin tunnel oxide in n+-polySi/SiO2/n+-Si structures

NASA Astrophysics Data System (ADS)

Samanta, Piyas

2017-09-01

We present a detailed investigation on temperature-dependent current conduction through thin tunnel oxides grown on degenerately doped n-type silicon (n+-Si) under positive bias ( VG ) on heavily doped n-type polycrystalline silicon (n+-polySi) gate in metal-oxide-semiconductor devices. The leakage current measured between 298 and 573 K and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole-Frenkel (PF) emission of trapped electrons from the neutral electron traps located in the silicon dioxide (SiO2) band gap in addition to Fowler-Nordheim (FN) tunneling of electrons from n+-Si acting as the drain node in FLOating gate Tunnel OXide Electrically Erasable Programmable Read-Only Memory devices. Process-induced neutral electron traps are located at 0.18 eV and 0.9 eV below the SiO2 conduction band. Throughout the temperature range studied here, PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm. A physics based new analytical formula has been developed for FN tunneling of electrons from the accumulation layer of degenerate semiconductors at a wide range of temperatures incorporating the image force barrier rounding effect. FN tunneling has been formulated in the framework of Wentzel-Kramers-Brilloiun taking into account the correction factor due to abrupt variation of the energy barrier at the cathode/oxide interface. The effect of interfacial and near-interfacial trapped-oxide charges on FN tunneling has also been investigated in detail at positive VG . The mechanism of leakage current conduction through SiO2 films plays a crucial role in simulation of time-dependent dielectric breakdown of the memory devices and to precisely predict the normal operating field or applied floating gate (FG) voltage for lifetime projection of the devices. In addition, we present theoretical results showing the effect of drain doping concentration on the FG leakage current.

Polymer/metal oxide hybrid dielectrics for low voltage field-effect transistors with solution-processed, high-mobility semiconductors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Held, Martin; Schießl, Stefan P.; Gannott, Florentina

Transistors for future flexible organic light-emitting diode (OLED) display backplanes should operate at low voltages and be able to sustain high currents over long times without degradation. Hence, high capacitance dielectrics with low surface trap densities are required that are compatible with solution-processable high-mobility semiconductors. Here, we combine poly(methyl methacrylate) (PMMA) and atomic layer deposition hafnium oxide (HfO{sub x}) into a bilayer hybrid dielectric for field-effect transistors with a donor-acceptor polymer (DPPT-TT) or single-walled carbon nanotubes (SWNTs) as the semiconductor and demonstrate substantially improved device performances for both. The ultra-thin PMMA layer ensures a low density of trap states atmore » the semiconductor-dielectric interface while the metal oxide layer provides high capacitance, low gate leakage and superior barrier properties. Transistors with these thin (≤70 nm), high capacitance (100–300 nF/cm{sup 2}) hybrid dielectrics enable low operating voltages (<5 V), balanced charge carrier mobilities and low threshold voltages. Moreover, the hybrid layers substantially improve the bias stress stability of the transistors compared to those with pure PMMA and HfO{sub x} dielectrics.« less

Rapid Transition of the Hole Rashba Effect from Strong Field Dependence to Saturation in Semiconductor Nanowires

NASA Astrophysics Data System (ADS)

Luo, Jun-Wei; Li, Shu-Shen; Zunger, Alex

2017-09-01

The electric field manipulation of the Rashba spin-orbit coupling effects provides a route to electrically control spins, constituting the foundation of the field of semiconductor spintronics. In general, the strength of the Rashba effects depends linearly on the applied electric field and is significant only for heavy-atom materials with large intrinsic spin-orbit interaction under high electric fields. Here, we illustrate in 1D semiconductor nanowires an anomalous field dependence of the hole (but not electron) Rashba effect (HRE). (i) At low fields, the strength of the HRE exhibits a steep increase with the field so that even low fields can be used for device switching. (ii) At higher fields, the HRE undergoes a rapid transition to saturation with a giant strength even for light-atom materials such as Si (exceeding 100 meV Å). (iii) The nanowire-size dependence of the saturation HRE is rather weak for light-atom Si, so size fluctuations would have a limited effect; this is a key requirement for scalability of Rashba-field-based spintronic devices. These three features offer Si nanowires as a promising platform for the realization of scalable complementary metal-oxide-semiconductor compatible spintronic devices.

Abatement of waste gases and water during the processes of semiconductor fabrication.

PubMed

Wen, Rui-mei; Liang, Jun-wu

2002-10-01

The purpose of this article is to examine the methods and equipment for abating waste gases and water produced during the manufacture of semiconductor materials and devices. Three separating methods and equipment are used to control three different groups of electronic wastes. The first group includes arsine and phosphine emitted during the processes of semiconductor materials manufacture. The abatement procedure for this group of pollutants consists of adding iodates, cupric and manganese salts to a multiple shower tower (MST) structure. The second group includes pollutants containing arsenic, phosphorus, HF, HCl, NO2, and SO3 emitted during the manufacture of semiconductor materials and devices. The abatement procedure involves mixing oxidants and bases in an oval column with a separator in the middle. The third group consists of the ions of As, P and heavy metals contained in the waste water. The abatement procedure includes adding CaCO3 and ferric salts in a flocculation-sedimentation compact device equipment. Test results showed that all waste gases and water after the abatement procedures presented in this article passed the discharge standards set by the State Environmental Protection Administration of China.

Reduction of Charge Traps and Stability Enhancement in Solution-Processed Organic Field-Effect Transistors Based on a Blended n-Type Semiconductor.

PubMed

Campos, Antonio; Riera-Galindo, Sergi; Puigdollers, Joaquim; Mas-Torrent, Marta

2018-05-09

Solution-processed n-type organic field-effect transistors (OFETs) are essential elements for developing large-area, low-cost, and all organic logic/complementary circuits. Nonetheless, the development of air-stable n-type organic semiconductors (OSCs) lags behind their p-type counterparts. The trapping of electrons at the semiconductor-dielectric interface leads to a lower performance and operational stability. Herein, we report printed small-molecule n-type OFETs based on a blend with a binder polymer, which enhances the device stability due to the improvement of the semiconductor-dielectric interface quality and a self-encapsulation. Both combined effects prevent the fast deterioration of the OSC. Additionally, a complementary metal-oxide semiconductor-like inverter is fabricated depositing p-type and n-type OSCs simultaneously.

Transparent amorphous oxide semiconductors for organic electronics: Application to inverted OLEDs

PubMed Central

Hosono, Hideo; Toda, Yoshitake; Kamiya, Toshio; Watanabe, Satoru

2017-01-01

Efficient electron transfer between a cathode and an active organic layer is one key to realizing high-performance organic devices, which require electron injection/transport materials with very low work functions. We developed two wide-bandgap amorphous (a-) oxide semiconductors, a-calcium aluminate electride (a-C12A7:e) and a-zinc silicate (a-ZSO). A-ZSO exhibits a low work function of 3.5 eV and high electron mobility of 1 cm2/(V · s); furthermore, it also forms an ohmic contact with not only conventional cathode materials but also anode materials. A-C12A7:e has an exceptionally low work function of 3.0 eV and is used to enhance the electron injection property from a-ZSO to an emission layer. The inverted electron-only and organic light-emitting diode (OLED) devices fabricated with these two materials exhibit excellent performance compared with the normal type with LiF/Al. This approach provides a solution to the problem of fabricating oxide thin-film transistor-driven OLEDs with both large size and high stability. PMID:28028243

Carrier mobility enhancement of nano-crystalline semiconductor films: Incorporation of redox -relay species into the grain boundary interface

NASA Astrophysics Data System (ADS)

Desilva, L. A.; Bandara, T. M. W. J.; Hettiarachchi, B. H.; Kumara, G. R. A.; Perera, A. G. U.; Rajapaksa, R. M. G.; Tennakone, K.

Dye-sensitized and perovskite solar cells and other nanostructured heterojunction electronic devices require securing intimate electronic contact between nanostructured surfaces. Generally, the strategy is solution phase coating of a hole -collector over a nano-crystalline high-band gap n-type oxide semiconductor film painted with a thin layer of the light harvesting material. The nano-crystallites of the hole - collector fills the pores of the painted oxide surface. Most ills of these devices are associated with imperfect contact and high resistance of the hole conducting layer constituted of nano-crystallites. Denaturing of the delicate light harvesting material forbid sintering at elevated temperatures to reduce the grain boundary resistance. It is found that the interfacial and grain boundary resistance can be significantly reduced via incorporation of redox species into the interfaces to form ultra-thin layers. Suitable redox moieties, preferably bonded to the surface, act as electron transfer relays greatly reducing the film resistance offerring a promising method of enhancing the effective hole mobility of nano-crystalline hole-collectors and developing hole conductor paints for application in nanostructured devices.

Amorphous oxide alloys as interfacial layers with broadly tunable electronic structures for organic photovoltaic cells.

PubMed

Zhou, Nanjia; Kim, Myung-Gil; Loser, Stephen; Smith, Jeremy; Yoshida, Hiroyuki; Guo, Xugang; Song, Charles; Jin, Hosub; Chen, Zhihua; Yoon, Seok Min; Freeman, Arthur J; Chang, Robert P H; Facchetti, Antonio; Marks, Tobin J

2015-06-30

In diverse classes of organic optoelectronic devices, controlling charge injection, extraction, and blocking across organic semiconductor-inorganic electrode interfaces is crucial for enhancing quantum efficiency and output voltage. To this end, the strategy of inserting engineered interfacial layers (IFLs) between electrical contacts and organic semiconductors has significantly advanced organic light-emitting diode and organic thin film transistor performance. For organic photovoltaic (OPV) devices, an electronically flexible IFL design strategy to incrementally tune energy level matching between the inorganic electrode system and the organic photoactive components without varying the surface chemistry would permit OPV cells to adapt to ever-changing generations of photoactive materials. Here we report the implementation of chemically/environmentally robust, low-temperature solution-processed amorphous transparent semiconducting oxide alloys, In-Ga-O and Ga-Zn-Sn-O, as IFLs for inverted OPVs. Continuous variation of the IFL compositions tunes the conduction band minima over a broad range, affording optimized OPV power conversion efficiencies for multiple classes of organic active layer materials and establishing clear correlations between IFL/photoactive layer energetics and device performance.

Growth of Bulk Wide Bandgap Semiconductor Crystals and Their Potential Applications

NASA Technical Reports Server (NTRS)

Chen, Kuo-Tong; Shi, Detang; Morgan, S. H.; Collins, W. Eugene; Burger, Arnold

1997-01-01

Developments in bulk crystal growth research for electro-optical devices in the Center for Photonic Materials and Devices since its establishment have been reviewed. Purification processes and single crystal growth systems employing physical vapor transport and Bridgman methods were assembled and used to produce high purity and superior quality wide bandgap materials such as heavy metal halides and II-VI compound semiconductors. Comprehensive material characterization techniques have been employed to reveal the optical, electrical and thermodynamic properties of crystals, and the results were used to establish improved material processing procedures. Postgrowth treatments such as passivation, oxidation, chemical etching and metal contacting during the X-ray and gamma-ray device fabrication process have also been investigated and low noise threshold with improved energy resolution has been achieved.

Resistance change effect in SrTiO3/Si (001) isotype heterojunction

NASA Astrophysics Data System (ADS)

Huang, Xiushi; Gao, Zhaomeng; Li, Pei; Wang, Longfei; Liu, Xiansheng; Zhang, Weifeng; Guo, Haizhong

2018-02-01

Resistance switching has been observed in double and multi-layer structures of ferroelectric films. The higher switching ratio opens up a vast path for emerging ferroelectric semiconductor devices. An n-n+ isotype heterojunction has been fabricated by depositing an oxide SrTiO3 layer on a conventional n-type Si (001) substrate (SrTiO3/Si) by pulsed laser disposition. Rectification and resistive switching behaviors in the n-n+ SrTiO3/Si heterojunction were observed by a conductive atomic force microscopy, and the n-n+ SrTiO3/Si heterojunction exhibits excellent endurance and retention characteristics. The possible mechanism was proposed based on the band structure of the n-n+ SrTiO3/Si heterojunction, and the observed electrical behaviors could be attributed to the modulation effect of the electric field reversal on the width of accumulation and the depletion region, as well as the height of potential of the n-n+ junction formed at the STO/Si interface. Moreover, oxygen vacancies are also indicated to play a crucial role in causing insulator to semiconductor transition. These results open the way to potential application in future microelectronic devices based on perovskite oxide layers on conventional semiconductors.

Role of point defects and HfO2/TiN interface stoichiometry on effective work function modulation in ultra-scaled complementary metal-oxide-semiconductor devices

NASA Astrophysics Data System (ADS)

Pandey, R. K.; Sathiyanarayanan, Rajesh; Kwon, Unoh; Narayanan, Vijay; Murali, K. V. R. M.

2013-07-01

We investigate the physical properties of a portion of the gate stack of an ultra-scaled complementary metal-oxide-semiconductor (CMOS) device. The effects of point defects, such as oxygen vacancy, oxygen, and aluminum interstitials at the HfO2/TiN interface, on the effective work function of TiN are explored using density functional theory. We compute the diffusion barriers of such point defects in the bulk TiN and across the HfO2/TiN interface. Diffusion of these point defects across the HfO2/TiN interface occurs during the device integration process. This results in variation of the effective work function and hence in the threshold voltage variation in the devices. Further, we simulate the effects of varying the HfO2/TiN interface stoichiometry on the effective work function modulation in these extremely-scaled CMOS devices. Our results show that the interface rich in nitrogen gives higher effective work function, whereas the interface rich in titanium gives lower effective work function, compared to a stoichiometric HfO2/TiN interface. This theoretical prediction is confirmed by the experiment, demonstrating over 700 meV modulation in the effective work function.

Pronounced photogating effect in atomically thin WSe2 with a self-limiting surface oxide layer

NASA Astrophysics Data System (ADS)

Yamamoto, Mahito; Ueno, Keiji; Tsukagoshi, Kazuhito

2018-04-01

The photogating effect is a photocurrent generation mechanism that leads to marked responsivity in two-dimensional (2D) semiconductor-based devices. A key step to promote the photogating effect in a 2D semiconductor is to integrate it with a high density of charge traps. Here, we show that self-limiting surface oxides on atomically thin WSe2 can serve as effective electron traps to facilitate p-type photogating. By examining the gate-bias-induced threshold voltage shift of a p-type transistor based on single-layer WSe2 with surface oxide, the electron trap density and the trap rate of the oxide are determined to be >1012 cm-2 and >1010 cm-2 s-1, respectively. White-light illumination on an oxide-covered 4-layer WSe2 transistor leads to the generation of photocurrent, the magnitude of which increases with the hole mobility. During illumination, the photocurrent evolves on a timescale of seconds, and a portion of the current persists even after illumination. These observations indicate that the photogenerated electrons are trapped deeply in the surface oxide and effectively gate the underlying WSe2. Owing to the pronounced photogating effect, the responsivity of the oxide-covered WSe2 transistor is observed to exceed 3000 A/W at an incident optical power of 1.1 nW, suggesting the effectiveness of surface oxidation in facilitating the photogating effect in 2D semiconductors.

The controlled growth of perovskite thin films: Opportunities, challenges, and synthesis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schlom, D.G.; Theis, C.D.; Hawley, M.E.

1997-10-01

The broad spectrum of electronic and optical properties exhibited by perovskites offers tremendous opportunities for microelectronic devices, especially when a combination of properties in a single device is desired. Molecular beam epitaxy (MBE) has achieved unparalleled control in the integration of semiconductors at the monolayer-level; its use for the integration of perovskites with similar nanoscale customization appears promising. Composition control and oxidation are often significant challenges to the growth of perovskites by MBE, but we show that these can be met through the use of purified ozone as an oxidant and real-time atomic absorption composition control. The opportunities, challenges, andmore » synthesis of oxide heterostructures by reactive MBE are described, with examples taken from the growth of oxide superconductors and oxide ferroelectrics.« less

The photoirradiation induced p-n junction in naphthylamine-based organic photovoltaic cells

NASA Astrophysics Data System (ADS)

Bai, Linyi; Gao, Qiang; Xia, Youyi; Ang, Chung Yen; Bose, Purnandhu; Tan, Si Yu; Zhao, Yanli

2015-08-01

The bulk heterojunction (BHJ) plays an indispensable role in organic photovoltaics, and thus has been investigated extensively in recent years. While a p-n heterojunction is usually fabricated using two different donor and acceptor materials such as poly(3-hexylthiophene-2,5-diyl) (P3HT) and phenyl-C61-butyric acid methyl ester (PCBM), it is really rare that such a BHJ is constructed by a single entity. Here, we presented a photoirradiation-induced p-n heterojunction in naphthylamine-based organic photovoltaic cells, where naphthylamine as a typical p-type semiconductor could be oxidized under photoirradiation and transformed into a new semiconductor with the n-type character. The p-n heterojunction was realized using both the remaining naphthylamine and its oxidative product, giving rise to the performance improvement in organic photovoltaic devices. The experimental results show that the power conversion efficiency (PCE) of the devices could be achieved up to 1.79% and 0.43% in solution and thin film processes, respectively. Importantly, this technology using naphthylamine does not require classic P3HT and PCBM to realize the p-n heterojunction, thereby simplifying the device fabrication process. The present approach opens up a promising route for the development of novel materials applicable to the p-n heterojunction.The bulk heterojunction (BHJ) plays an indispensable role in organic photovoltaics, and thus has been investigated extensively in recent years. While a p-n heterojunction is usually fabricated using two different donor and acceptor materials such as poly(3-hexylthiophene-2,5-diyl) (P3HT) and phenyl-C61-butyric acid methyl ester (PCBM), it is really rare that such a BHJ is constructed by a single entity. Here, we presented a photoirradiation-induced p-n heterojunction in naphthylamine-based organic photovoltaic cells, where naphthylamine as a typical p-type semiconductor could be oxidized under photoirradiation and transformed into a new semiconductor with the n-type character. The p-n heterojunction was realized using both the remaining naphthylamine and its oxidative product, giving rise to the performance improvement in organic photovoltaic devices. The experimental results show that the power conversion efficiency (PCE) of the devices could be achieved up to 1.79% and 0.43% in solution and thin film processes, respectively. Importantly, this technology using naphthylamine does not require classic P3HT and PCBM to realize the p-n heterojunction, thereby simplifying the device fabrication process. The present approach opens up a promising route for the development of novel materials applicable to the p-n heterojunction. Electronic supplementary information (ESI) available: Additional synthesis and characterization details. See DOI: 10.1039/c5nr04471e

Physicochemical and Electrophysical Properties of Metal/Semiconductor Containing Nanostructured Composites

NASA Astrophysics Data System (ADS)

Gerasimov, G. N.; Gromov, V. F.; Trakhtenberg, L. I.

2018-06-01

The properties of nanostructured composites based on metal oxides and metal-polymer materials are analyzed, along with ways of preparing them. The effect the interaction between metal and semiconductor nanoparticles has on the conductivity, photoconductivity, catalytic activity, and magnetic, dielectric, and sensor properties of nanocomposites is discussed. It is shown that as a result of this interaction, a material can acquire properties that do not exist in systems of isolated particles. The transfer of electrons between metal particles of different sizes in polymeric matrices leads to specific dielectric losses, and to an increase in the rate and a change in the direction of chemical reactions catalyzed by these particles. The interaction between metal-oxide semiconductor particles results in the electronic and chemical sensitization of sensor effects in nanostructured composite materials. Studies on creating molecular machines (Brownian motors), devices for magnetic recording of information, and high-temperature superconductors based on nanostructured systems are reviewed.

Conductors and semiconductors for advanced organic electronics

NASA Astrophysics Data System (ADS)

Meyer-Friedrichsen, Timo; Elschner, Andreas; Keohan, Frank; Lövenich, Wilfried; Ponomarenko, Sergei A.

2009-08-01

The development of suitable materials for organic electronics is still one of the key points to access new application areas with this promising technology. Semiconductors based on thiophene chemistry show very high charge carrier mobilities. The functionalization with linker groups provided materials that built monomolecular layers of the semiconductors on the hydrolyzed oxide surface of a silicon-wafer. This approach lead to self-assembled mono-layer field-effect transistors (SAM-FETs) with mobilities of up to 0.04 cm2/Vs, which is comparable to the values of the respective bulk thin film. Transparent inorganic conductors like ITO are highly conductive but the costly processing and the brittleness hamper their use in cost-sensitive and/or flexible devices. Highly conductive PEDOT-grades have been developed with conductivities of up to 1000 S/cm which are easily applicable by printing techniques and can be used as ITO replacement in devices such as touch panels or organic photovoltaics.

Universal strategy for Ohmic hole injection into organic semiconductors with high ionization energies

NASA Astrophysics Data System (ADS)

Kotadiya, Naresh B.; Lu, Hao; Mondal, Anirban; Ie, Yutaka; Andrienko, Denis; Blom, Paul W. M.; Wetzelaer, Gert-Jan A. H.

2018-02-01

Barrier-free (Ohmic) contacts are a key requirement for efficient organic optoelectronic devices, such as organic light-emitting diodes, solar cells, and field-effect transistors. Here, we propose a simple and robust way of forming an Ohmic hole contact on organic semiconductors with a high ionization energy (IE). The injected hole current from high-work-function metal-oxide electrodes is improved by more than an order of magnitude by using an interlayer for which the sole requirement is that it has a higher IE than the organic semiconductor. Insertion of the interlayer results in electrostatic decoupling of the electrode from the semiconductor and realignment of the Fermi level with the IE of the organic semiconductor. The Ohmic-contact formation is illustrated for a number of material combinations and solves the problem of hole injection into organic semiconductors with a high IE of up to 6 eV.

Universal strategy for Ohmic hole injection into organic semiconductors with high ionization energies.

PubMed

Kotadiya, Naresh B; Lu, Hao; Mondal, Anirban; Ie, Yutaka; Andrienko, Denis; Blom, Paul W M; Wetzelaer, Gert-Jan A H

2018-04-01

Barrier-free (Ohmic) contacts are a key requirement for efficient organic optoelectronic devices, such as organic light-emitting diodes, solar cells, and field-effect transistors. Here, we propose a simple and robust way of forming an Ohmic hole contact on organic semiconductors with a high ionization energy (IE). The injected hole current from high-work-function metal-oxide electrodes is improved by more than an order of magnitude by using an interlayer for which the sole requirement is that it has a higher IE than the organic semiconductor. Insertion of the interlayer results in electrostatic decoupling of the electrode from the semiconductor and realignment of the Fermi level with the IE of the organic semiconductor. The Ohmic-contact formation is illustrated for a number of material combinations and solves the problem of hole injection into organic semiconductors with a high IE of up to 6 eV.

III-V compound semiconductor growth on silicon via germanium buffer and surface passivation for CMOS technology

NASA Astrophysics Data System (ADS)

Choi, Donghun

Integration of III-V compound semiconductors on silicon substrates has recently received much attention for the development of optoelectronic and high speed electronic devices. However, it is well known that there are some key challenges for the realization of III-V device fabrication on Si substrates: (i) the large lattice mismatch (in case of GaAs: 4.1%), and (ii) the formation of antiphase domain (APD) due to the polar compound semiconductor growth on non-polar elemental structure. Besides these growth issues, the lack of a useful surface passivation technology for compound semiconductors has precluded development of metal-oxide-semiconductor (MOS) devices and causes high surface recombination parasitics in scaled devices. This work demonstrates the growth of high quality III-V materials on Si via an intermediate Ge buffer layer and some surface passivation methods to reduce interface defect density for the fabrication of MOS devices. The initial goal was to achieve both low threading dislocation density (TDD) and low surface roughness on Ge-on-Si heterostructure growth. This was achieved by repeating a deposition-annealing cycle consisting of low temperature deposition + high temperature-high rate deposition + high temperature hydrogen annealing, using reduced-pressure chemical-vapor deposition (CVD). We then grew III-V materials on the Ge/Si virtual substrates using molecular-beam epitaxy (MBE). The relationship between initial Ge surface configuration and antiphase boundary formation was investigated using surface reflection high-energy electron diffraction (RHEED) patterns and atomic force microscopy (AFM) image analysis. In addition, some MBE growth techniques, such as migration enhanced epitaxy (MEE) and low temperature GaAs growth, were adopted to improve surface roughness and solve the Ge self-doping problem. Finally, an Al2O3 gate oxide layer was deposited using atomic-layer-deposition (ALD) system after HCl native oxide etching and ALD in-situ pre-annealing at 400 °C. A 100 nm thick aluminum layer was deposited to form the gate contact for a MOS device fabrication. C-V measurement results show very small frequency dispersion and 200-300 mV hysteresis, comparable to our best results for InGaAs/GaAs MOS structures on GaAs substrate. Most notably, the quasi-static C-V curve demonstrates clear inversion layer formation. I-V curves show a reasonable leakage current level. The inferred midgap interface state density, Dit, of 2.4 x 1012 eV-1cm-2 was calculated by combined high-low frequency capacitance method. In addition, we investigated the interface properties of amorphous LaAlO 3/GaAs MOS capacitors fabricated on GaAs substrate. The surface was protected during sample transfer between III-V and oxide molecular beam deposition (MBD) chambers by a thick arsenic-capping layer. An annealing method, a low temperature-short time RTA followed by a high temperature RTA, was developed, yielding extremely small hysteresis (˜ 30 mV), frequency dispersion (˜ 60 mV), and interface trap density (mid 1010 eV-1cm -2). We used capacitance-voltage (C-V) and current-voltage (I-V) measurements for electrical characterization of MOS devices, tapping-mode AFM for surface morphology analysis, X-ray photoelectron spectroscopy (XPS) for chemical elements analysis of interface, cross section transmission-electron microscopy (TEM), X-ray diffraction (XRD), secondary ion mass spectrometry (SIMS), and photoluminescence (PL) measurement for film quality characterization. This successful growth and appropriate surface treatments of III-V materials provides a first step for the fabrication of III-V optical and electrical devices on the same Si-based electronic circuits.

A silicon-on-insulator complementary-metal-oxide-semiconductor compatible flexible electronics technology

NASA Astrophysics Data System (ADS)

Tu, Hongen; Xu, Yong

2012-07-01

This paper reports a simple flexible electronics technology that is compatible with silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) processes. Compared with existing technologies such as direct fabrication on flexible substrates and transfer printing, the main advantage of this technology is its post-SOI-CMOS compatibility. Consequently, high-performance and high-density CMOS circuits can be first fabricated on SOI wafers using commercial foundry and then be integrated into flexible substrates. The yield is also improved by eliminating the transfer printing step. Furthermore, this technology allows the integration of various sensors and microfluidic devices. To prove the concept of this technology, flexible MOSFETs have been demonstrated.

Radiation tolerant 1 micron CMOS technology

NASA Astrophysics Data System (ADS)

Crevel, P.; Rodde, K.

1991-03-01

Starting from a standard one micron Complementary Metal Oxide Semiconductor (CMOS) for high density, low power memory applications, the degree of radiation tolerance of the baseline process is evaluated. Implemented process modifications to improve latchup sensitivity under heavy ion irradiation as well as total dose effects without changing layout rules are described. By changing doping profiles in Metal Nitride Oxide Semiconductors (MNOS) and P-channel MOS (PMOS) device regions, it is possible to guarantee data sheet specification of a 64 K low power static RAM for total gamma dose up to 35 krad (Si) (and even higher values for the gate array family) without latch up for Linear Energy Transfer LET up to 115 MeV/(mg/cm squared).

Silicon carbide, a semiconductor for space power electronics

NASA Technical Reports Server (NTRS)

Powell, J. Anthony; Matus, Lawrence G.

1991-01-01

After many years of promise as a high temperature semiconductor, silicon carbide (SiC) is finally emerging as a useful electronic material. Recent significant progress that has led to this emergence has been in the areas of crystal growth and device fabrication technology. High quality single-crystal SiC wafers, up to 25 mm in diameter, can now be produced routinely from boules grown by a high temperature (2700 K) sublimation process. Device fabrication processes, including chemical vapor deposition (CVD), in situ doping during CVD, reactive ion etching, oxidation, metallization, etc. have been used to fabricate p-n junction diodes and MOSFETs. The diode was operated to 870 K and the MOSFET to 770 K.

Electra-optical device including a nitrogen containing electrolyte

DOEpatents

Bates, J.B.; Dudney, N.J.; Gruzalski, G.R.; Luck, C.F.

1995-10-03

Described is a thin-film battery, especially a thin-film microbattery, and a method for making same having application as a backup or primary integrated power source for electronic devices. The battery includes a novel electrolyte which is electrochemically stable and does not react with the lithium anode and a novel vanadium oxide cathode. Configured as a microbattery, the battery can be fabricated directly onto a semiconductor chip, onto the semiconductor die or onto any portion of the chip carrier. The battery can be fabricated to any specified size or shape to meet the requirements of a particular application. The battery is fabricated of solid state materials and is capable of operation between {minus}15 C and 150 C.

Neutron, gamma ray and post-irradiation thermal annealing effects on power semiconductor switches

NASA Technical Reports Server (NTRS)

Schwarze, G. E.; Frasca, A. J.

1991-01-01

Experimental data showing the effects of neutrons and gamma rays on the performance characteristics of power-type NPN bipolar junction transistors (BJTs), metal-oxide-semiconductor field effect transistors (MOSFETs), and static induction transistors (SITs) are given. These three types of devices were tested at radiation levels which met or exceeded the SP-100 requirements. For the SP-100 radiation requirements, the BJTs were found to be most sensitive to neutrons, the MOSFETs were most sensitive to gamma rays, and the SITs were only slightly sensitive to neutrons. Postirradiation thermal anneals at 300 K and up to 425 K were done on these devices and the effectiveness of these anneals are also discussed.

Electrical instability of InGaZnO thin-film transistors with and without titanium sub-oxide layer under light illumination

NASA Astrophysics Data System (ADS)

Chiu, Y. C.; Zheng, Z. W.; Cheng, C. H.; Chen, P. C.; Yen, S. S.; Fan, C. C.; Hsu, H. H.; Kao, H. L.; Chang, C. Y.

2017-03-01

The electrical instability behaviors of amorphous indium-gallium-zinc oxide thin-film transistors with and without titanium sub-oxide passivation layer were investigated under light illumination in this study. For the unpassivated IGZO TFT device, in contrast with the dark case, a noticeable increase of the sub-threshold swing was observed when under the illumination environment, which can be attributed to the generation of ionized oxygen vacancies within the α-IGZO active layer by high energy photons. For the passivated TFT device, the much smaller SS of 70 mV/dec and high device mobility of >100 cm2/Vs at a drive voltage of 3 V with negligible degradation under light illumination are achieved due to the passivation effect of n-type titanium sub-oxide semiconductor, which may create potential application for high-performance display.

In Situ Chemical Modification of Schottky Barrier in Solution-Processed Zinc Tin Oxide Diode.

PubMed

Son, Youngbae; Li, Jiabo; Peterson, Rebecca L

2016-09-14

Here we present a novel in situ chemical modification process to form vertical Schottky diodes using palladium (Pd) rectifying bottom contacts, amorphous zinc tin oxide (Zn-Sn-O) semiconductor made via acetate-based solution process, and molybdenum top ohmic contacts. Using X-ray photoelectron spectroscopy depth profiling, we show that oxygen plasma treatment of Pd creates a PdOx interface layer, which is then reduced back to metallic Pd by in situ reactions during Zn-Sn-O film annealing. The plasma treatment ensures an oxygen-rich environment in the semiconductor near the Schottky barrier, reducing the level of oxygen-deficiency-related defects and improving the rectifying contact. Using this process, we achieve diodes with high forward current density exceeding 10(3)A cm(-2) at 1 V, rectification ratios of >10(2), and ideality factors of around 1.9. The measured diode current-voltage characteristics are compared to numerical simulations of thermionic field emission with sub-bandgap states in the semiconductor, which we attribute to spatial variations in metal stoichiometry of amorphous Zn-Sn-O. To the best of our knowledge, this is the first demonstration of vertical Schottky diodes using solution-processed amorphous metal oxide semiconductor. Furthermore, the in situ chemical modification method developed here can be adapted to tune interface properties in many other oxide devices.

Integration of ZnO and CuO nanowires into a thermoelectric module

PubMed Central

Dalola, Simone; Faglia, Guido; Comini, Elisabetta; Ferroni, Matteo; Soldano, Caterina; Ferrari, Vittorio; Sberveglieri, Giorgio

2014-01-01

Summary Zinc oxide (ZnO, n-type) and copper oxide (CuO, p-type) nanowires have been synthesized and preliminarily investigated as innovative materials for the fabrication of a proof-of-concept thermoelectric device. The Seebeck coefficients, electrical conductivity and thermoelectric power factors (TPF) of both semiconductor materials have been determined independently using a custom experimental set-up, leading to results in agreement with available literature with potential improvement. Combining bundles of ZnO and CuO nanowires in a series of five thermocouples on alumina leads to a macroscopic prototype of a planar thermoelectric generator (TEG) unit. This demonstrates the possibility of further integration of metal oxide nanostructures into efficient thermoelectric devices. PMID:24991531

Integration of ZnO and CuO nanowires into a thermoelectric module.

PubMed

Zappa, Dario; Dalola, Simone; Faglia, Guido; Comini, Elisabetta; Ferroni, Matteo; Soldano, Caterina; Ferrari, Vittorio; Sberveglieri, Giorgio

2014-01-01

Zinc oxide (ZnO, n-type) and copper oxide (CuO, p-type) nanowires have been synthesized and preliminarily investigated as innovative materials for the fabrication of a proof-of-concept thermoelectric device. The Seebeck coefficients, electrical conductivity and thermoelectric power factors (TPF) of both semiconductor materials have been determined independently using a custom experimental set-up, leading to results in agreement with available literature with potential improvement. Combining bundles of ZnO and CuO nanowires in a series of five thermocouples on alumina leads to a macroscopic prototype of a planar thermoelectric generator (TEG) unit. This demonstrates the possibility of further integration of metal oxide nanostructures into efficient thermoelectric devices.

Engineering of band gap states of amorphous SiZnSnO semiconductor as a function of Si doping concentration.

PubMed

Choi, Jun Young; Heo, Keun; Cho, Kyung-Sang; Hwang, Sung Woo; Kim, Sangsig; Lee, Sang Yeol

2016-11-04

We investigated the band gap of SiZnSnO (SZTO) with different Si contents. Band gap engineering of SZTO is explained by the evolution of the electronic structure, such as changes in the band edge states and band gap. Using ultraviolet photoelectron spectroscopy (UPS), it was verified that Si atoms can modify the band gap of SZTO thin films. Carrier generation originating from oxygen vacancies can modify the band-gap states of oxide films with the addition of Si. Since it is not easy to directly derive changes in the band gap states of amorphous oxide semiconductors, no reports of the relationship between the Fermi energy level of oxide semiconductor and the device stability of oxide thin film transistors (TFTs) have been presented. The addition of Si can reduce the total density of trap states and change the band-gap properties. When 0.5 wt% Si was used to fabricate SZTO TFTs, they showed superior stability under negative bias temperature stress. We derived the band gap and Fermi energy level directly using data from UPS, Kelvin probe, and high-resolution electron energy loss spectroscopy analyses.

Engineering of band gap states of amorphous SiZnSnO semiconductor as a function of Si doping concentration

PubMed Central

Choi, Jun Young; Heo, Keun; Cho, Kyung-Sang; Hwang, Sung Woo; Kim, Sangsig; Lee, Sang Yeol

2016-01-01

We investigated the band gap of SiZnSnO (SZTO) with different Si contents. Band gap engineering of SZTO is explained by the evolution of the electronic structure, such as changes in the band edge states and band gap. Using ultraviolet photoelectron spectroscopy (UPS), it was verified that Si atoms can modify the band gap of SZTO thin films. Carrier generation originating from oxygen vacancies can modify the band-gap states of oxide films with the addition of Si. Since it is not easy to directly derive changes in the band gap states of amorphous oxide semiconductors, no reports of the relationship between the Fermi energy level of oxide semiconductor and the device stability of oxide thin film transistors (TFTs) have been presented. The addition of Si can reduce the total density of trap states and change the band-gap properties. When 0.5 wt% Si was used to fabricate SZTO TFTs, they showed superior stability under negative bias temperature stress. We derived the band gap and Fermi energy level directly using data from UPS, Kelvin probe, and high-resolution electron energy loss spectroscopy analyses. PMID:27812035

Efficient p-n junction-based thermoelectric generator that can operate at extreme temperature conditions

NASA Astrophysics Data System (ADS)

Chavez, Ruben; Angst, Sebastian; Hall, Joseph; Maculewicz, Franziska; Stoetzel, Julia; Wiggers, Hartmut; Thanh Hung, Le; Van Nong, Ngo; Pryds, Nini; Span, Gerhard; Wolf, Dietrich E.; Schmechel, Roland; Schierning, Gabi

2018-01-01

In many industrial processes, a large proportion of energy is lost in the form of heat. Thermoelectric generators can convert this waste heat into electricity by means of the Seebeck effect. However, the use of thermoelectric generators in practical applications on an industrial scale is limited in part because electrical, thermal, and mechanical bonding contacts between the semiconductor materials and the metal electrodes in current designs are not capable of withstanding thermal-mechanical stress and alloying of the metal-semiconductor interface when exposed to the high temperatures occurring in many real-world applications. Here we demonstrate a concept for thermoelectric generators that can address this issue by replacing the metallization and electrode bonding on the hot side of the device by a p-n junction between the two semiconductor materials, making the device robust against temperature induced failure. In our proof-of-principle demonstration, a p-n junction device made from nanocrystalline silicon is at least comparable in its efficiency and power output to conventional devices of the same material and fabrication process, but with the advantage of sustaining high hot side temperatures and oxidative atmosphere.

A new era of semiconductor genetics using ion-sensitive field-effect transistors: the gene-sensitive integrated cell.

PubMed

Toumazou, Christofer; Thay, Tan Sri Lim Kok; Georgiou, Pantelis

2014-03-28

Semiconductor genetics is now disrupting the field of healthcare owing to the rapid parallelization and scaling of DNA sensing using ion-sensitive field-effect transistors (ISFETs) fabricated using commercial complementary metal -oxide semiconductor technology. The enabling concept of DNA reaction monitoring introduced by Toumazou has made this a reality and we are now seeing relentless scaling with Moore's law ultimately achieving the $100 genome. In this paper, we present the next evolution of this technology through the creation of the gene-sensitive integrated cell (GSIC) for label-free real-time analysis based on ISFETs. This device is derived from the traditional metal-oxide semiconductor field-effect transistor (MOSFET) and has electrical performance identical to that of a MOSFET in a standard semiconductor process, yet is capable of incorporating DNA reaction chemistries for applications in single nucleotide polymorphism microarrays and DNA sequencing. Just as application-specific integrated circuits, which are developed in much the same way, have shaped our consumer electronics industry and modern communications and memory technology, so, too, do GSICs based on a single underlying technology principle have the capacity to transform the life science and healthcare industries.

Heterojunction PbS nanocrystal solar cells with oxide charge-transport layers.

PubMed

Hyun, Byung-Ryool; Choi, Joshua J; Seyler, Kyle L; Hanrath, Tobias; Wise, Frank W

2013-12-23

Oxides are commonly employed as electron-transport layers in optoelectronic devices based on semiconductor nanocrystals, but are relatively rare as hole-transport layers. We report studies of NiO hole-transport layers in PbS nanocrystal photovoltaic structures. Transient fluorescence experiments are used to verify the relevant energy levels for hole transfer. On the basis of these results, planar heterojunction devices with ZnO as the photoanode and NiO as the photocathode were fabricated and characterized. Solution-processed devices were used to systematically study the dependence on nanocrystal size and achieve conversion efficiency as high as 2.5%. Optical modeling indicates that optimum performance should be obtained with thinner oxide layers than can be produced reliably by solution casting. Room-temperature sputtering allows deposition of oxide layers as thin as 10 nm, which enables optimization of device performance with respect to the thickness of the charge-transport layers. The best devices achieve an open-circuit voltage of 0.72 V and efficiency of 5.3% while eliminating most organic material from the structure and being compatible with tandem structures.

Verification of Fowler-Nordheim electron tunneling mechanism in Ni/SiO2/n-4H SiC and n+ poly-Si/SiO2/n-4H SiC MOS devices by different models

NASA Astrophysics Data System (ADS)

Kodigala, Subba Ramaiah

2016-11-01

This article emphasizes verification of Fowler-Nordheim electron tunneling mechanism in the Ni/SiO2/n-4H SiC MOS devices by developing three different kinds of models. The standard semiconductor equations are categorically solved to obtain the change in Fermi energy level of semiconductor with effect of temperature and field that extend support to determine sustainable and accurate tunneling current through the oxide layer. The forward and reverse bias currents with variation of electric field are simulated with help of different models developed by us for MOS devices by applying adequate conditions. The latter is quite different from former in terms of tunneling mechanism in the MOS devices. The variation of barrier height with effect of quantum mechanical, temperature, and fields is considered as effective barrier height for the generation of current-field (J-F) curves under forward and reverse biases but quantum mechanical effect is void in the latter. In addition, the J-F curves are also simulated with variation of carrier concentration in the n-type 4H SiC semiconductor of MOS devices and the relation between them is established.

Atomic layer deposition: an enabling technology for the growth of functional nanoscale semiconductors

NASA Astrophysics Data System (ADS)

Biyikli, Necmi; Haider, Ali

2017-09-01

In this paper, we present the progress in the growth of nanoscale semiconductors grown via atomic layer deposition (ALD). After the adoption by semiconductor chip industry, ALD became a widespread tool to grow functional films and conformal ultra-thin coatings for various applications. Based on self-limiting and ligand-exchange-based surface reactions, ALD enabled the low-temperature growth of nanoscale dielectric, metal, and semiconductor materials. Being able to deposit wafer-scale uniform semiconductor films at relatively low-temperatures, with sub-monolayer thickness control and ultimate conformality, makes ALD attractive for semiconductor device applications. Towards this end, precursors and low-temperature growth recipes are developed to deposit crystalline thin films for compound and elemental semiconductors. Conventional thermal ALD as well as plasma-assisted and radical-enhanced techniques have been exploited to achieve device-compatible film quality. Metal-oxides, III-nitrides, sulfides, and selenides are among the most popular semiconductor material families studied via ALD technology. Besides thin films, ALD can grow nanostructured semiconductors as well using either template-assisted growth methods or bottom-up controlled nucleation mechanisms. Among the demonstrated semiconductor nanostructures are nanoparticles, nano/quantum-dots, nanowires, nanotubes, nanofibers, nanopillars, hollow and core-shell versions of the afore-mentioned nanostructures, and 2D materials including transition metal dichalcogenides and graphene. ALD-grown nanoscale semiconductor materials find applications in a vast amount of applications including functional coatings, catalysis and photocatalysis, renewable energy conversion and storage, chemical sensing, opto-electronics, and flexible electronics. In this review, we give an overview of the current state-of-the-art in ALD-based nanoscale semiconductor research including the already demonstrated and future applications.

Sub-ppb Oxygen Contaminant Detection in Semi-Conductor Processing

NASA Technical Reports Server (NTRS)

Man, K. F.

1995-01-01

Gaseous contaminants such as oxygen, water vapor, nitrogen and hydrocarbons are often present in the processing environment in semiconductor device fabrication and in containerless materials processing. The contaminants arise as a result of outgassing from hot surfaces or they may be part of the impurities in commercial ultra-high purity gases. Among these gaseous contaminants, oxygen is the most reactive and, therefore, has the most adverse effects on the end product. There has been an intense effort at the Jet Propulsion Laboratory to develop different types of oxygen sorbents to reduce oxygen concentration in a microgravity processing environment to sub-ppb (parts-per-billion) levels. Higher concentrations can lead to rapid surface oxide formation, hence reducing the quality of semiconductor devices. If the concentration of oxygen in a processing chamber at 1000oC is in the ppb level, it will only take approximately 10 seconds for an oxide layer to form on the surface of a sample. The interaction of oxygen with the water surface can lead to the formation of localized defects in semi-conductor devices, hence decreasing the manufacturing yield. For example, efficient production of 64 Mb RAM chips requires contaminations below ppb levels. This paper describes a technique for measuring trace quantities of oxygen contaminants by recording the monoatomic negative ions, O-, using mass spectrometry. The O- formation from the e--O2 interaction utilizes the electron dissociative attachment method that is greatly enhanced at the resonant energy (6.8 eV). The device combines a small gridded electron ionizer with a compact mass spectrometer. The concentrations of oxygen have been measured using the method of standard additions by diluting O2 in N2. The lowest detection limit obtained was 1.2 kHz (O- count rate) at a concentration of 10-10, corresponding to 0.1 ppb.

In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory.

PubMed

Hwang, Eun Suk; Kim, Jun Shik; Jeon, Seok Min; Lee, Seung Jun; Jang, Younjin; Cho, Deok-Yong; Hwang, Cheol Seong

2018-04-01

The programming characteristics of charge trap flash memory device adopting amorphous In 2 Ga 2 ZnO 7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO 2 (blocking oxide)/p ++ -Si (control gate) substrate, where 3 nm thick atomic layer deposited Al 2 O 3 (tunneling oxide) and 5 nm thick low-pressure CVD Si 3 N 4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (E F ) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher E F of MOCVD a-IGZO.

In2Ga2ZnO7 oxide semiconductor based charge trap device for NAND flash memory

NASA Astrophysics Data System (ADS)

Hwang, Eun Suk; Kim, Jun Shik; Jeon, Seok Min; Lee, Seung Jun; Jang, Younjin; Cho, Deok-Yong; Hwang, Cheol Seong

2018-04-01

The programming characteristics of charge trap flash memory device adopting amorphous In2Ga2ZnO7 (a-IGZO) oxide semiconductors as channel layer were evaluated. Metal-organic chemical vapor deposition (MOCVD) and RF-sputtering processes were used to grow a 45 nm thick a-IGZO layer on a 20 nm thick SiO2 (blocking oxide)/p++-Si (control gate) substrate, where 3 nm thick atomic layer deposited Al2O3 (tunneling oxide) and 5 nm thick low-pressure CVD Si3N4 (charge trap) layers were intervened between the a-IGZO and substrate. Despite the identical stoichiometry and other physicochemical properties of the MOCVD and sputtered a-IGZO, a much faster programming speed of MOCVD a-IGZO was observed. A comparable amount of oxygen vacancies was found in both MOCVD and sputtered a-IGZO, confirmed by x-ray photoelectron spectroscopy and bias-illumination-instability test measurements. Ultraviolet photoelectron spectroscopy analysis revealed a higher Fermi level (E F) of the MOCVD a-IGZO (∼0.3 eV) film than that of the sputtered a-IGZO, which could be ascribed to the higher hydrogen concentration in the MOCVD a-IGZO film. Since the programming in a flash memory device is governed by the tunneling of electrons from the channel to charge trapping layer, the faster programming performance could be the result of a higher E F of MOCVD a-IGZO.

Innovations in microelectronics and solid state at North Carolina Agricultural and Technical State University

NASA Technical Reports Server (NTRS)

Williams, L., Jr.

1977-01-01

Research in the following areas is described: (1) Characterization and applications of metallic oxide devices; (2) Electronic properties and energy conversion in organic amorphous semiconductors; (3) Material growth and characterization directed toward improving 3-5 heterojunction solar cells.

Separating semiconductor devices from substrate by etching graded composition release layer disposed between semiconductor devices and substrate including forming protuberances that reduce stiction

DOEpatents

Tauke-Pedretti, Anna; Nielson, Gregory N; Cederberg, Jeffrey G; Cruz-Campa, Jose Luis

2015-05-12

A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between each of the semiconductor devices and the substrate. The etch is stopped while the protuberances remain between each of the semiconductor devices and the substrate. The method also includes separating the semiconductor devices from the substrate. Other methods and apparatus are also disclosed.

Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics

PubMed Central

Park, Sungjun; Lee, SeYeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

2015-01-01

Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 107, and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo. PMID:26271456

Proceedings of the Workshop on Compound Semiconductor Devices and Integrated Circuits (13th) Held in Cabourg, France on 10-12 May 1989

DTIC Science & Technology

1989-05-12

USA Resonant tunneling transistors and New III-V memory devices for new circuit architectures with reduced complexity F. Capasso, Bell. Murray Hill...the evaporation, or by selective oxidation of As, leaving metallic Ga clusters and b) the interdiffusive deterioration of metal contacts on GaAs...VEB (My) Resonant Tunneling Transistors and New III-V Memory Devices for New Circuit Architectures with Reduced Complexity . Invited: F. Capasso

A room-temperature magnetic semiconductor from a ferromagnetic metallic glass.

PubMed

Liu, Wenjian; Zhang, Hongxia; Shi, Jin-An; Wang, Zhongchang; Song, Cheng; Wang, Xiangrong; Lu, Siyuan; Zhou, Xiangjun; Gu, Lin; Louzguine-Luzgin, Dmitri V; Chen, Mingwei; Yao, Kefu; Chen, Na

2016-12-08

Emerging for future spintronic/electronic applications, magnetic semiconductors have stimulated intense interest due to their promises for new functionalities and device concepts. So far, the so-called diluted magnetic semiconductors attract many attentions, yet it remains challenging to increase their Curie temperatures above room temperature, particularly those based on III-V semiconductors. In contrast to the concept of doping magnetic elements into conventional semiconductors to make diluted magnetic semiconductors, here we propose to oxidize originally ferromagnetic metals/alloys to form new species of magnetic semiconductors. We introduce oxygen into a ferromagnetic metallic glass to form a Co 28.6 Fe 12.4 Ta 4.3 B 8.7 O 46 magnetic semiconductor with a Curie temperature above 600 K. The demonstration of p-n heterojunctions and electric field control of the room-temperature ferromagnetism in this material reflects its p-type semiconducting character, with a mobility of 0.1 cm 2  V -1  s -1 . Our findings may pave a new way to realize high Curie temperature magnetic semiconductors with unusual multifunctionalities.

A room-temperature magnetic semiconductor from a ferromagnetic metallic glass

PubMed Central

Liu, Wenjian; Zhang, Hongxia; Shi, Jin-an; Wang, Zhongchang; Song, Cheng; Wang, Xiangrong; Lu, Siyuan; Zhou, Xiangjun; Gu, Lin; Louzguine-Luzgin, Dmitri V.; Chen, Mingwei; Yao, Kefu; Chen, Na

2016-01-01

Emerging for future spintronic/electronic applications, magnetic semiconductors have stimulated intense interest due to their promises for new functionalities and device concepts. So far, the so-called diluted magnetic semiconductors attract many attentions, yet it remains challenging to increase their Curie temperatures above room temperature, particularly those based on III–V semiconductors. In contrast to the concept of doping magnetic elements into conventional semiconductors to make diluted magnetic semiconductors, here we propose to oxidize originally ferromagnetic metals/alloys to form new species of magnetic semiconductors. We introduce oxygen into a ferromagnetic metallic glass to form a Co28.6Fe12.4Ta4.3B8.7O46 magnetic semiconductor with a Curie temperature above 600 K. The demonstration of p–n heterojunctions and electric field control of the room-temperature ferromagnetism in this material reflects its p-type semiconducting character, with a mobility of 0.1 cm2 V−1 s−1. Our findings may pave a new way to realize high Curie temperature magnetic semiconductors with unusual multifunctionalities. PMID:27929059

Combinatorial study of zinc tin oxide thin-film transistors

NASA Astrophysics Data System (ADS)

McDowell, M. G.; Sanderson, R. J.; Hill, I. G.

2008-01-01

Groups of thin-film transistors using a zinc tin oxide semiconductor layer have been fabricated via a combinatorial rf sputtering technique. The ZnO :SnO2 ratio of the film varies as a function of position on the sample, from pure ZnO to SnO2, allowing for a study of zinc tin oxide transistor performance as a function of channel stoichiometry. The devices were found to have mobilities ranging from 2to12cm2/Vs, with two peaks in mobility in devices at ZnO fractions of 0.80±0.03 and 0.25±0.05, and on/off ratios as high as 107. Transistors composed predominantly of SnO2 were found to exhibit light sensitivity which affected both the on/off ratios and threshold voltages of these devices.

Compact modeling of total ionizing dose and aging effects in MOS technologies

DOE PAGES

Esqueda, Ivan S.; Barnaby, Hugh J.; King, Michael Patrick

2015-06-18

This paper presents a physics-based compact modeling approach that incorporates the impact of total ionizing dose (TID) and stress-induced defects into simulations of metal-oxide-semiconductor (MOS) devices and integrated circuits (ICs). This approach utilizes calculations of surface potential (ψs) to capture the charge contribution from oxide trapped charge and interface traps and to describe their impact on MOS electrostatics and device operating characteristics as a function of ionizing radiation exposure and aging effects. The modeling approach is demonstrated for bulk and silicon-on-insulator (SOI) MOS device. The formulation is verified using TCAD simulations and through the comparison of model calculations and experimentalmore » I-V characteristics from irradiated devices. The presented approach is suitable for modeling TID and aging effects in advanced MOS devices and ICs.« less

Rapid Transition of the Hole Rashba Effect from Strong Field Dependence to Saturation in Semiconductor Nanowires.

PubMed

Luo, Jun-Wei; Li, Shu-Shen; Zunger, Alex

2017-09-22

The electric field manipulation of the Rashba spin-orbit coupling effects provides a route to electrically control spins, constituting the foundation of the field of semiconductor spintronics. In general, the strength of the Rashba effects depends linearly on the applied electric field and is significant only for heavy-atom materials with large intrinsic spin-orbit interaction under high electric fields. Here, we illustrate in 1D semiconductor nanowires an anomalous field dependence of the hole (but not electron) Rashba effect (HRE). (i) At low fields, the strength of the HRE exhibits a steep increase with the field so that even low fields can be used for device switching. (ii) At higher fields, the HRE undergoes a rapid transition to saturation with a giant strength even for light-atom materials such as Si (exceeding 100 meV Å). (iii) The nanowire-size dependence of the saturation HRE is rather weak for light-atom Si, so size fluctuations would have a limited effect; this is a key requirement for scalability of Rashba-field-based spintronic devices. These three features offer Si nanowires as a promising platform for the realization of scalable complementary metal-oxide-semiconductor compatible spintronic devices.

Real-time two-dimensional imaging of potassium ion distribution using an ion semiconductor sensor with charged coupled device technology.

PubMed

Hattori, Toshiaki; Masaki, Yoshitomo; Atsumi, Kazuya; Kato, Ryo; Sawada, Kazuaki

2010-01-01

Two-dimensional real-time observation of potassium ion distributions was achieved using an ion imaging device based on charge-coupled device (CCD) and metal-oxide semiconductor technologies, and an ion selective membrane. The CCD potassium ion image sensor was equipped with an array of 32 × 32 pixels (1024 pixels). It could record five frames per second with an area of 4.16 × 4.16 mm(2). Potassium ion images were produced instantly. The leaching of potassium ion from a 3.3 M KCl Ag/AgCl reference electrode was dynamically monitored in aqueous solution. The potassium ion selective membrane on the semiconductor consisted of plasticized poly(vinyl chloride) (PVC) with bis(benzo-15-crown-5). The addition of a polyhedral oligomeric silsesquioxane to the plasticized PVC membrane greatly improved adhesion of the membrane onto Si(3)N(4) of the semiconductor surface, and the potential response was stabilized. The potential response was linear from 10(-2) to 10(-5) M logarithmic concentration of potassium ion. The selectivity coefficients were K(K(+),Li(+))(pot) = 10(-2.85), K(K(+),Na(+))(pot) = 10(-2.30), K(K(+),Rb(+))(pot) =10(-1.16), and K(K(+),Cs(+))(pot) = 10(-2.05).

Bulk ZnO: Current Status, Challenges, and Prospects

DTIC Science & Technology

2009-04-01

von Wenckstern, H. Schmidt, M. Lorenz, and M. Grundmann, “Defects in virgin and N+-implanted ZnO single crystals studied by positron annihilation...characterization, and device applications of semiconductor and complex oxide thin films. He is a co-author of more than 50 papers in referred...REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < 1 Abstract— Rediscovered in the last decade, zinc oxide

Microwave assisted synthesis and characterisation of a zinc oxide/tobacco mosaic virus hybrid material. An active hybrid semiconductor in a field-effect transistor device.

PubMed

Sanctis, Shawn; Hoffmann, Rudolf C; Eiben, Sabine; Schneider, Jörg J

2015-01-01

Tobacco mosaic virus (TMV) has been employed as a robust functional template for the fabrication of a TMV/zinc oxide field effect transistor (FET). A microwave based approach, under mild conditions was employed to synthesize stable zinc oxide (ZnO) nanoparticles, employing a molecular precursor. Insightful studies of the decomposition of the precursor were done using NMR spectroscopy and material characterization of the hybrid material derived from the decomposition was achieved using dynamic light scattering (DLS), transmission electron microscopy (TEM), grazing incidence X-ray diffractometry (GI-XRD) and atomic force microscopy (AFM). TEM and DLS data confirm the formation of crystalline ZnO nanoparticles tethered on top of the virus template. GI-XRD investigations exhibit an orientated nature of the deposited ZnO film along the c-axis. FET devices fabricated using the zinc oxide mineralized virus template material demonstrates an operational transistor performance which was achieved without any high-temperature post-processing steps. Moreover, a further improvement in FET performance was observed by adjusting an optimal layer thickness of the deposited ZnO on top of the TMV. Such a bio-inorganic nanocomposite semiconductor material accessible using a mild and straightforward microwave processing technique could open up new future avenues within the field of bio-electronics.

Real time in vivo imaging and measurement of serine protease activity in the mouse hippocampus using a dedicated complementary metal-oxide semiconductor imaging device.

PubMed

Ng, David C; Tamura, Hideki; Tokuda, Takashi; Yamamoto, Akio; Matsuo, Masamichi; Nunoshita, Masahiro; Ishikawa, Yasuyuki; Shiosaka, Sadao; Ohta, Jun

2006-09-30

The aim of the present study is to demonstrate the application of complementary metal-oxide semiconductor (CMOS) imaging technology for studying the mouse brain. By using a dedicated CMOS image sensor, we have successfully imaged and measured brain serine protease activity in vivo, in real-time, and for an extended period of time. We have developed a biofluorescence imaging device by packaging the CMOS image sensor which enabled on-chip imaging configuration. In this configuration, no optics are required whereby an excitation filter is applied onto the sensor to replace the filter cube block found in conventional fluorescence microscopes. The fully packaged device measures 350 microm thick x 2.7 mm wide, consists of an array of 176 x 144 pixels, and is small enough for measurement inside a single hemisphere of the mouse brain, while still providing sufficient imaging resolution. In the experiment, intraperitoneally injected kainic acid induced upregulation of serine protease activity in the brain. These events were captured in real time by imaging and measuring the fluorescence from a fluorogenic substrate that detected this activity. The entire device, which weighs less than 1% of the body weight of the mouse, holds promise for studying freely moving animals.

Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks.

PubMed

Zhao, Yudan; Li, Qunqing; Xiao, Xiaoyang; Li, Guanhong; Jin, Yuanhao; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan

2016-02-23

We have proposed and fabricated stable and repeatable, flexible, single-walled carbon nanotube (SWCNT) thin film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) integrated circuits based on a three-dimensional (3D) structure. Two layers of SWCNT-TFT devices were stacked, where one layer served as n-type devices and the other one served as p-type devices. On the basis of this method, it is able to save at least half of the area required to construct an inverter and make large-scale and high-density integrated CMOS circuits easier to design and manufacture. The 3D flexible CMOS inverter gain can be as high as 40, and the total noise margin is more than 95%. Moreover, the input and output voltage of the inverter are exactly matched for cascading. 3D flexible CMOS NOR, NAND logic gates, and 15-stage ring oscillators were fabricated on PI substrates with high performance as well. Stable electrical properties of these circuits can be obtained with bending radii as small as 3.16 mm, which shows that such a 3D structure is a reliable architecture and suitable for carbon nanotube electrical applications in complex flexible and wearable electronic devices.

Synthesis of chemicals using solar energy with stable photoelectrochemically active heterostructures.

PubMed

Mubeen, Syed; Singh, Nirala; Lee, Joun; Stucky, Galen D; Moskovits, Martin; McFarland, Eric W

2013-05-08

Efficient and cost-effective conversion of solar energy to useful chemicals and fuels could lead to a significant reduction in fossil hydrocarbon use. Artificial systems that use solar energy to produce chemicals have been reported for more than a century. However the most efficient devices demonstrated, based on traditionally fabricated compound semiconductors, have extremely short working lifetimes due to photocorrosion by the electrolyte. Here we report a stable, scalable design and molecular level fabrication strategy to create photoelectrochemically active heterostructure (PAH) units consisting of an efficient semiconductor light absorber in contact with oxidation and reduction electrocatalysts and otherwise protected by alumina. The functional heterostructures are fabricated by layer-by-layer, template-directed, electrochemical synthesis in porous anodic aluminum oxide membranes to produce high density arrays of electronically autonomous, nanostructured, corrosion resistant, photoactive units (~10(9)-10(10) PAHs per cm(2)). Each PAH unit is isolated from its neighbor by the transparent electrically insulating oxide cellular enclosure that makes the overall assembly fault tolerant. When illuminated with visible light, the free floating devices have been demonstrated to produce hydrogen at a stable rate for over 24 h in corrosive hydroiodic acid electrolyte with light as the only input. The quantum efficiency (averaged over the solar spectrum) for absorbed photons-to-hydrogen conversion was 7.4% and solar-to-hydrogen energy efficiency of incident light was 0.9%. The fabrication approach is scalable for commercial manufacturing and readily adaptable to a variety of earth abundant semiconductors which might otherwise be unstable as photoelectrocatalysts.

Additional compound semiconductor nanowires for photonics

NASA Astrophysics Data System (ADS)

Ishikawa, F.

2016-02-01

GaAs related compound semiconductor heterostructures are one of the most developed materials for photonics. Those have realized various photonic devices with high efficiency, e. g., lasers, electro-optical modulators, and solar cells. To extend the functions of the materials system, diluted nitride and bismide has been paid attention over the past decade. They can largely decrease the band gap of the alloys, providing the greater tunability of band gap and strain status, eventually suppressing the non-radiative Auger recombinations. On the other hand, selective oxidation for AlGaAs is a vital technique for vertical surface emitting lasers. That enables precisely controlled oxides in the system, enabling the optical and electrical confinement, heat transfer, and mechanical robustness. We introduce the above functions into GaAs nanowires. GaAs/GaAsN core-shell nanowires showed clear redshift of the emitting wavelength toward infrared regime. Further, the introduction of N elongated the carrier lifetime at room temperature indicating the passivation of non-radiative surface recombinations. GaAs/GaAsBi nanowire shows the redshift with metamorphic surface morphology. Selective and whole oxidations of GaAs/AlGaAs core-shell nanowires produce semiconductor/oxide composite GaAs/AlGaOx and oxide GaOx/AlGaOx core-shell nanowires, respectively. Possibly sourced from nano-particle species, the oxide shell shows white luminescence. Those property should extend the functions of the nanowires for their application to photonics.

Enhanced electrical properties of oxide semiconductor thin-film transistors with high conductivity thin layer insertion for the channel region

NASA Astrophysics Data System (ADS)

Nguyen, Cam Phu Thi; Raja, Jayapal; Kim, Sunbo; Jang, Kyungsoo; Le, Anh Huy Tuan; Lee, Youn-Jung; Yi, Junsin

2017-02-01

This study examined the performance and the stability of indium tin zinc oxide (ITZO) thin film transistors (TFTs) by inserting an ultra-thin indium tin oxide (ITO) layer at the active/insulator interface. The electrical properties of the double channel device (ITO thickness of 5 nm) were improved in comparison with the single channel ITZO or ITO devices. The TFT characteristics of the device with an ITO thickness of less than 5 nm were degraded due to the formation of an island-like morphology and the carriers scattering at the active/insulator interface. The 5 nm-thick ITO inserted ITZO TFTs (optimal condition) exhibited a superior field effect mobility (∼95 cm2/V·s) compared with the ITZO-only TFTs (∼34 cm2/V·s). The best characteristics of the TFT devices with double channel layer are due to the lowest surface roughness (0.14 nm) and contact angle (50.1°) that result in the highest hydrophicility, and the most effective adhesion at the surface. Furthermore, the threshold voltage shifts for the ITO/ITZO double layer device decreased to 0.80 and -2.39 V compared with 6.10 and -6.79 V (for the ITZO only device) under positive and negative bias stress, respectively. The falling rates of EA were 0.38 eV/V and 0.54 eV/V for the ITZO and ITO/ITZO bi-layer devices, respectively. The faster falling rate of the double channel devices suggests that the trap density, including interface trap and semiconductor bulk trap, can be decreased by the ion insertion of a very thin ITO film into the ITZO/SiO2 reference device. These results demonstrate that the double active layer TFT can potentially be applied to the flat panel display.

Unitary lens semiconductor device

DOEpatents

Lear, Kevin L.

1997-01-01

A unitary lens semiconductor device and method. The unitary lens semiconductor device is provided with at least one semiconductor layer having a composition varying in the growth direction for unitarily forming one or more lenses in the semiconductor layer. Unitary lens semiconductor devices may be formed as light-processing devices such as microlenses, and as light-active devices such as light-emitting diodes, photodetectors, resonant-cavity light-emitting diodes, vertical-cavity surface-emitting lasers, and resonant cavity photodetectors.

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

NASA Astrophysics Data System (ADS)

Hong, Augustin Jinwoo

Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

Method of producing strained-layer semiconductor devices via subsurface-patterning

DOEpatents

Dodson, Brian W.

1993-01-01

A method is described for patterning subsurface features in a semiconductor device, wherein the semiconductor device includes an internal strained layer. The method comprises creating a pattern of semiconductor material over the semiconductor device, the semiconductor material having a predetermined thickness which stabilizes areas of the strained semiconductor layer that lie beneath the pattern. Subsequently, a heating step is applied to the semiconductor device to cause a relaxation in areas of the strained layer which do not lie beneath the semiconductor material pattern, whereby dislocations result in the relaxed areas and impair electrical transport therethrough.

Measuring charge nonuniformity in MOS devices

NASA Technical Reports Server (NTRS)

Maserjian, J.; Zamani, N.

1980-01-01

Convenient method of determining inherent lateral charge non-uniformities along silicon dioxide/silicon interface of metal-oxide-semiconductor (MOS) employs rapid measurement of capacitance of interface as function of voltage at liquid nitrogen temperature. Charge distribution is extracted by fast-Fourier-transform analysis of capacitance voltage (C-V) measurement.

Analyzing Single-Event Gate Ruptures In Power MOSFET's

NASA Technical Reports Server (NTRS)

Zoutendyk, John A.

1993-01-01

Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.

Radiation hardness of β-Ga2O3 metal-oxide-semiconductor field-effect transistors against gamma-ray irradiation

NASA Astrophysics Data System (ADS)

Wong, Man Hoi; Takeyama, Akinori; Makino, Takahiro; Ohshima, Takeshi; Sasaki, Kohei; Kuramata, Akito; Yamakoshi, Shigenobu; Higashiwaki, Masataka

2018-01-01

The effects of ionizing radiation on β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated. A gamma-ray tolerance as high as 1.6 MGy(SiO2) was demonstrated for the bulk Ga2O3 channel by virtue of weak radiation effects on the MOSFETs' output current and threshold voltage. The MOSFETs remained functional with insignificant hysteresis in their transfer characteristics after exposure to the maximum cumulative dose. Despite the intrinsic radiation hardness of Ga2O3, radiation-induced gate leakage and drain current dispersion ascribed respectively to dielectric damage and interface charge trapping were found to limit the overall radiation hardness of these devices.

Miniaturized Metal (Metal Alloy)/PdO(x)/SiC Hydrogen and Hydrocarbon Gas Sensors

NASA Technical Reports Server (NTRS)

Hunter, Gary W. (Inventor); Xu, Jennifer C. (Inventor); Lukco, Dorothy (Inventor)

2008-01-01

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO(x)). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600 C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sided sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Band-to-band tunneling in a carbon nanotube metal-oxide-semiconductor field-effect transistor is dominated by phonon-assisted tunneling.

PubMed

Koswatta, Siyuranga O; Lundstrom, Mark S; Nikonov, Dmitri E

2007-05-01

Band-to-band tunneling (BTBT) devices have recently gained a lot of interest due to their potential for reducing power dissipation in integrated circuits. We have performed extensive simulations for the BTBT operation of carbon nanotube metal-oxide-semiconductor field-effect transistors (CNT-MOSFETs) using the nonequilibrium Green's function formalism for both ballistic and dissipative quantum transport. In comparison with recently reported experimental data (J. Am. Chem. Soc. 2006, 128, 3518-3519), we have obtained strong evidence that BTBT in CNT-MOSFETs is dominated by optical phonon assisted inelastic transport, which can have important implications on the transistor characteristics. It is shown that, under large biasing conditions, two-phonon scattering may also become important.

Limits on silicon nanoelectronics for terascale integration.

PubMed

Meindl, J D; Chen, Q; Davis, J A

2001-09-14

Throughout the past four decades, silicon semiconductor technology has advanced at exponential rates in both performance and productivity. Concerns have been raised, however, that the limits of silicon technology may soon be reached. Analysis of fundamental, material, device, circuit, and system limits reveals that silicon technology has an enormous remaining potential to achieve terascale integration (TSI) of more than 1 trillion transistors per chip. Such massive-scale integration is feasible assuming the development and economical mass production of double-gate metal-oxide-semiconductor field effect transistors with gate oxide thickness of about 1 nanometer, silicon channel thickness of about 3 nanometers, and channel length of about 10 nanometers. The development of interconnecting wires for these transistors presents a major challenge to the achievement of nanoelectronics for TSI.

Electra-optical device including a nitrogen containing electrolyte

DOEpatents

Bates, John B.; Dudney, Nancy J.; Gruzalski, Greg R.; Luck, Christopher F.

1995-01-01

Described is a thin-film battery, especially a thin-film microbattery, and a method for making same having application as a backup or primary integrated power source for electronic devices. The battery includes a novel electrolyte which is electrochemically stable and does not react with the lithium anode and a novel vanadium oxide cathode Configured as a microbattery, the battery can be fabricated directly onto a semiconductor chip, onto the semiconductor die or onto any portion of the chip carrier. The battery can be fabricated to any specified size or shape to meet the requirements of a particular application. The battery is fabricated of solid state materials and is capable of operation between -15.degree. C. and 150.degree. C.

Unitary lens semiconductor device

DOEpatents

Lear, K.L.

1997-05-27

A unitary lens semiconductor device and method are disclosed. The unitary lens semiconductor device is provided with at least one semiconductor layer having a composition varying in the growth direction for unitarily forming one or more lenses in the semiconductor layer. Unitary lens semiconductor devices may be formed as light-processing devices such as microlenses, and as light-active devices such as light-emitting diodes, photodetectors, resonant-cavity light-emitting diodes, vertical-cavity surface-emitting lasers, and resonant cavity photodetectors. 9 figs.

Charge Behaviors around Oxide Device/Pseudo-Physiological Solution Interface with Molecular Dynamic Simulations

NASA Astrophysics Data System (ADS)

Maekawa, Yuki; Shibuta, Yasushi; Sakata, Toshiya

2013-12-01

In this study, we investigated the charge behaviors of ions and water molecules at the oxide device/pseudo-physiological solution interface by use of molecular dynamics (MD) simulations because the detection principle of semiconductor-based biosensors is based on the detection of charge density changes at the oxide sensing surface in physiological environments. In particular, we designed an alpha-quartz (100) surface with some charges corresponding to pH=5.5 so that the ionic behaviors for 500 mM each of Na+ and Cl- around the interface were calculated under the surface condition with charges, considering a real system. As a result of the simulation, we defined the region of Debye length from the calculated potential distribution, in which some parameters such as diffusion coefficient and the vibration of water molecules around the interface differed from those of the bulk solution. The elucidation of the solid/liquid interfacial behaviors by the simulation technique should deepen our understanding of the detection principle of semiconductor-based biosensors and will give guidelines for the design of a bio-interface in the field of biosensing technology, because they cannot be demonstrated experimentally.

Potentiometric Dye Imaging for Pheochromocytoma and Cortical Neurons with a Novel Measurement System Using an Integrated Complementary Metal-Oxide-Semiconductor Imaging Device

NASA Astrophysics Data System (ADS)

Kobayashi, Takuma; Tagawa, Ayato; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Hatanaka, Yumiko; Tamura, Hideki; Ishikawa, Yasuyuki; Shiosaka, Sadao; Ohta, Jun

2010-11-01

The combination of optical imaging with voltage-sensitive dyes is a powerful tool for studying the spatiotemporal patterns of neural activity and understanding the neural networks of the brain. To visualize the potential status of multiple neurons simultaneously using a compact instrument with high density and a wide range, we present a novel measurement system using an implantable biomedical photonic LSI device with a red absorptive light filter for voltage-sensitive dye imaging (BpLSI-red). The BpLSI-red was developed for sensing fluorescence by the on-chip LSI, which was designed by using complementary metal-oxide-semiconductor (CMOS) technology. A micro-electro-mechanical system (MEMS) microfabrication technique was used to postprocess the CMOS sensor chip; light-emitting diodes (LEDs) were integrated for illumination and to enable long-term cell culture. Using the device, we succeeded in visualizing the membrane potential of 2000-3000 cells and the process of depolarization of pheochromocytoma cells (PC12 cells) and mouse cerebral cortical neurons in a primary culture with cellular resolution. Therefore, our measurement application enables the detection of multiple neural activities simultaneously.

Probing and Manipulating the Interfacial Defects of InGaAs Dual-Layer Metal Oxides at the Atomic Scale.

PubMed

Wu, Xing; Luo, Chen; Hao, Peng; Sun, Tao; Wang, Runsheng; Wang, Chaolun; Hu, Zhigao; Li, Yawei; Zhang, Jian; Bersuker, Gennadi; Sun, Litao; Pey, Kinleong

2018-01-01

The interface between III-V and metal-oxide-semiconductor materials plays a central role in the operation of high-speed electronic devices, such as transistors and light-emitting diodes. The high-speed property gives the light-emitting diodes a high response speed and low dark current, and they are widely used in communications, infrared remote sensing, optical detection, and other fields. The rational design of high-performance devices requires a detailed understanding of the electronic structure at this interface; however, this understanding remains a challenge, given the complex nature of surface interactions and the dynamic relationship between the morphology evolution and electronic structures. Herein, in situ transmission electron microscopy is used to probe and manipulate the structural and electrical properties of ZrO 2 films on Al 2 O 3 and InGaAs substrate at the atomic scale. Interfacial defects resulting from the spillover of the oxygen-atom conduction-band wavefunctions are resolved. This study unearths the fundamental defect-driven interfacial electric structure of III-V semiconductor materials and paves the way to future high-speed and high-reliability devices. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Development of a physical and electronic model for RuO 2 nanorod rectenna devices

NASA Astrophysics Data System (ADS)

Dao, Justin

Ruthenium oxide (RuO2) nanorods are an emergent technology in nanostructure devices. As the physical size of electronics approaches a critical lower limit, alternative solutions to further device miniaturization are currently under investigation. Thin-film nanorod growth is an interesting technology, being investigated for use in wireless communications, sensor systems, and alternative energy applications. In this investigation, self-assembled RuO2 nanorods are grown on a variety of substrates via a high density plasma, reactive sputtering process. Nanorods have been found to grow on substrates that form native oxide layers when exposed to air, namely silicon, aluminum, and titanium. Samples were analyzed with Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM) techniques. Conductive Atomic Force Microscopy (C-AFM) measurements were performed on single nanorods to characterize structure and electrical conductivity. The C-AFM probe tip is placed on a single nanorod and I-V characteristics are measured, potentially exhibiting rectifying capabilities. An analysis of these results using fundamental semiconductor physics principles is presented. Experimental data for silicon substrates was most closely approximated by the Simmons model for direct electron tunneling, whereas that of aluminum substrates was well approximated by Fowler-Nordheim tunneling. The native oxide of titanium is regarded as a semiconductor rather than an insulator and its ability to function as a rectifier is not strong. An electronic model for these nanorods is described herein.

Ageing and proton irradiation damage of a low voltage EMCCD in a CMOS process

NASA Astrophysics Data System (ADS)

Dunford, A.; Stefanov, K.; Holland, A.

2018-02-01

Electron Multiplying Charge Coupled Devices (EMCCDs) have revolutionised low light level imaging, providing highly sensitive detection capabilities. Implementing Electron Multiplication (EM) in Charge Coupled Devices (CCDs) can increase the Signal to Noise Ratio (SNR) and lead to further developments in low light level applications such as improvements in image contrast and single photon imaging. Demand has grown for EMCCD devices with properties traditionally restricted to Complementary Metal-Oxide-Semiconductor (CMOS) image sensors, such as lower power consumption and higher radiation tolerance. However, EMCCDs are known to experience an ageing effect, such that the gain gradually decreases with time. This paper presents results detailing EM ageing in an Electron Multiplying Complementary Metal-Oxide-Semiconductor (EMCMOS) device and its effect on several device characteristics such as Charge Transfer Inefficiency (CTI) and thermal dark signal. When operated at room temperature an average decrease in gain of over 20% after an operational period of 175 hours was detected. With many image sensors deployed in harsh radiation environments, the radiation hardness of the device following proton irradiation was also tested. This paper presents the results of a proton irradiation completed at the Paul Scherrer Institut (PSI) at a 10 MeV equivalent fluence of 4.15× 1010 protons/cm2. The pre-irradiation characterisation, irradiation methodology and post-irradiation results are detailed, demonstrating an increase in dark current and a decrease in its activation energy. Finally, this paper presents a comparison of the damage caused by EM gain ageing and proton irradiation.

Thin film transistors for flexible electronics: contacts, dielectrics and semiconductors.

PubMed

Quevedo-Lopez, M A; Wondmagegn, W T; Alshareef, H N; Ramirez-Bon, R; Gnade, B E

2011-06-01

The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed.

Computational insights into charge transfer across functionalized semiconductor surfaces

NASA Astrophysics Data System (ADS)

Kearney, Kara; Rockett, Angus; Ertekin, Elif

2017-12-01

Photoelectrochemical water-splitting is a promising carbon-free fuel production method for producing H2 and O2 gas from liquid water. These cells are typically composed of at least one semiconductor photoelectrode which is prone to degradation and/or oxidation. Various surface modifications are known for stabilizing semiconductor photoelectrodes, yet stabilization techniques are often accompanied by a decrease in photoelectrode performance. However, the impact of surface modification on charge transport and its consequence on performance is still lacking, creating a roadblock for further improvements. In this review, we discuss how density functional theory and finite-element device simulations are reliable tools for providing insight into charge transport across modified photoelectrodes.

Silicon-Carbide Power MOSFET Performance in High Efficiency Boost Power Processing Unit for Extreme Environments

NASA Technical Reports Server (NTRS)

Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Del Castillo, Linda Y.; Fitzpatrick, Fred; Chen, Yuan

2016-01-01

Silicon-Carbide device technology has generated much interest in recent years. With superior thermal performance, power ratings and potential switching frequencies over its Silicon counterpart, Silicon-Carbide offers a greater possibility for high powered switching applications in extreme environment. In particular, Silicon-Carbide Metal-Oxide- Semiconductor Field-Effect Transistors' (MOSFETs) maturing process technology has produced a plethora of commercially available power dense, low on-state resistance devices capable of switching at high frequencies. A novel hard-switched power processing unit (PPU) is implemented utilizing Silicon-Carbide power devices. Accelerated life data is captured and assessed in conjunction with a damage accumulation model of gate oxide and drain-source junction lifetime to evaluate potential system performance at high temperature environments.

Thermally Stable Ohmic Contacts on Silicon Carbide Developed for High- Temperature Sensors and Electronics

NASA Technical Reports Server (NTRS)

Okojie, Robert S.

2001-01-01

The NASA aerospace program, in particular, requires breakthrough instrumentation inside the combustion chambers of engines for the purpose of, among other things, improving computational fluid dynamics code validation and active engine behavioral control (combustion, flow, stall, and noise). This environment can be as high as 600 degrees Celsius, which is beyond the capability of silicon and gallium arsenide devices. Silicon-carbide- (SiC-) based devices appear to be the most technologically mature among wide-bandgap semiconductors with the proven capability to function at temperatures above 500 degrees Celsius. However, the contact metalization of SiC degrades severely beyond this temperature because of factors such as the interdiffusion between layers, oxidation of the contact, and compositional and microstructural changes at the metal/semiconductor interface. These mechanisms have been proven to be device killers. Very costly and weight-adding packaging schemes that include vacuum sealing are sometimes adopted as a solution.

Optical devices combining an organic semiconductor crystal with a two-dimensional inorganic diffraction grating

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kitazawa, Takenori; Yamao, Takeshi, E-mail: yamao@kit.ac.jp; Hotta, Shu

2016-02-01

We have fabricated optical devices using an organic semiconductor crystal as an emission layer in combination with a two-dimensional (2D) inorganic diffraction grating used as an optical cavity. We formed the inorganic diffraction grating by wet etching of aluminum-doped zinc oxide (AZO) under a 2D cyclic olefin copolymer (COC) diffraction grating used as a mask. The COC diffraction grating was fabricated by nanoimprint lithography. The AZO diffraction grating was composed of convex prominences arranged in a triangular lattice. The organic crystal placed on the AZO diffraction grating indicated narrowed peaks in its emission spectrum under ultraviolet light excitation. These aremore » detected parallel to the crystal plane. The peaks were shifted by rotating the optical devices around the normal to the crystal plane, which reflected the rotational symmetries of the triangular lattice through 60°.« less

Dc-To-Dc Converter Uses Reverse Conduction Of MOSFET's

NASA Technical Reports Server (NTRS)

Gruber, Robert P.; Gott, Robert W.

1991-01-01

In modified high-power, phase-controlled, full-bridge, pulse-width-modulated dc-to-dc converters, switching devices power metal oxide/semiconductor field-effect transistors (MOSFET's). Decreases dissipation of power during switching by eliminating approximately 0.7-V forward voltage drop in anti-parallel diodes. Energy-conversion efficiency increased.

Integration of Multi-Functional Oxide Thin Film Heterostructures with III-V Semiconductors

NASA Astrophysics Data System (ADS)

Rahman, Md. Shafiqur

Integration of multi-functional oxide thin films with semiconductors has attracted considerable attention in recent years due to their potential applications in sensing and logic functionalities that can be incorporated in future system-on-a-chip devices. III-V semiconductor, for example, GaAs, have higher saturated electron velocity and mobility allowing transistors based on GaAs to operate at a much higher frequency with less noise compared to Si. In addition, because of its direct bandgap a number of efficient optical devices are possible and by oxide integrating with other III-V semiconductors the wavelengths can be made tunable through hetero-engineering of the bandgap. This study, based on the use of SrTiO3 (STO) films grown on GaAs (001) substrates by molecular beam epitaxy (MBE) as an intermediate buffer layer for the hetero-epitaxial growth of ferromagnetic La0.7Sr 0.3MnO3 (LSMO) and room temperature multiferroic BiFeO 3 (BFO) thin films and superlattice structures using pulsed laser deposition (PLD). The properties of the multilayer thin films in terms of growth modes, lattice spacing/strain, interface structures and texture were characterized by the in-situ reflection high energy electron diffraction (RHEED). The crystalline quality and chemical composition of the complex oxide heterostructures were investigated by a combination of X-ray diffraction (XRD) and X-ray photoelectron absorption spectroscopy (XPS). Surface morphology, piezo-response with domain structure, and ferroelectric switching observations were carried out on the thin film samples using a scanning probe microscope operated as a piezoresponse force microscopy (PFM) in the contact mode. The magnetization measurements with field cooling exhibit a surprising increment in magnetic moment with enhanced magnetic hysteresis squareness. This is the effect of exchange interaction between the antiferromagnetic BFO and the ferromagnetic LSMO at the interface. The integration of BFO materials with LSMO on GaAs substrate also facilitated the demonstration of resistive random access memory (ReRAM) devices which can be faster with lower energy consumption compared to present commercial technologies. Ferroelectric switching observations using piezoresponse force microscopy show polarization switching demonstrating its potential for read-write operation in NVM devices. The ferroelectric and electrical characterization exhibit strong resistive switching with low SET/RESET voltages. Furthermore, a prototypical epitaxial field effect transistor based on multiferroic BFO as the gate dielectric and ferromagnetic LSMO as the conducting channel was also demonstrated. The device exhibits a modulation in channel conductance with high ON/OFF ratio. The measured nanostructure and physical-compositional results from the multilayer are correlated with their corresponding dielectric, piezoelectric, and ferroelectric properties. These results provide an understanding of the heteroepitaxial growth of ferroelectric (FE)-antiferromagnetic (AFM) BFO on ferromagnetic LSMO as a simple thin film or superlattice structure, integrated on STO buffered GaAs (001) with full control over the interface structure at the atomic-scale. This work also represents the first step toward the realization of magnetoelectronic devices integrated with GaAs (001).

Forecasting of the performance of MOS device for space applications

NASA Technical Reports Server (NTRS)

Fang, P. H.

1971-01-01

Analysis of radiation damage of MOSFET data from Explorer 34 (IMP-F), and radiation damage characteristics of MOSFET with boron diffused between a silicon semiconductor and silicon oxide are considered. The first subject is an interpretation of the discrepancy between the space data and the laboratory data. The second subject is an attempt to analyze the radiation damage characteristic of MOSFET when there is modification of electrical properties in the gate oxide region.

Determination of intrinsic mobility of a bilayer oxide thin-film transistor by pulsed I-V method

NASA Astrophysics Data System (ADS)

Woo, Hyunsuk; Kim, Taeho; Hur, Jihyun; Jeon, Sanghun

2017-04-01

Amorphous oxide semiconductor thin-film transistors (TFT) have been considered as outstanding switch devices owing to their high mobility. However, because of their amorphous channel material with a certain level of density of states, a fast transient charging effect in an oxide TFT occurs, leading to an underestimation of the mobility value. In this paper, the effects of the fast charging of high-performance bilayer oxide semiconductor TFTs on mobility are examined in order to determine an accurate mobility extraction method. In addition, an approach based on a pulse I D -V G measurement method is proposed to determine the intrinsic mobility value. Even with the short pulse I D -V G measurement, a certain level of fast transient charge trapping cannot be avoided as long as the charge-trap start time is shorter than the pulse rising time. Using a pulse-amplitude-dependent threshold voltage characterization method, we estimated a correction factor for the apparent mobility, thus allowing us to determine the intrinsic mobility.

Semiconductor/dielectric interface engineering and characterization

NASA Astrophysics Data System (ADS)

Lucero, Antonio T.

The focus of this dissertation is the application and characterization of several, novel interface passivation techniques for III-V semiconductors, and the development of an in-situ electrical characterization. Two different interface passivation techniques were evaluated. The first is interface nitridation using a nitrogen radical plasma source. The nitrogen radical plasma generator is a unique system which is capable of producing a large flux of N-radicals free of energetic ions. This was applied to Si and the surface was studied using x-ray photoelectron spectroscopy (XPS). Ultra-thin nitride layers could be formed from 200-400° C. Metal-oxide-semiconductor capacitors (MOSCAPs) were fabricated using this passivation technique. Interface nitridation was able to reduce leakage current and improve the equivalent oxide thickness of the devices. The second passivation technique studied is the atomic layer deposition (ALD) diethylzinc (DEZ)/water treatment of sulfur treated InGaAs and GaSb. On InGaAs this passivation technique is able to chemically reduce higher oxidation states on the surface, and the process results in the deposition of a ZnS/ZnO interface passivation layer, as determined by XPS. Capacitance-voltage (C-V) measurements of MOSCAPs made on p-InGaAs reveal a large reduction in accumulation dispersion and a reduction in the density of interfacial traps. The same technique was applied to GaSb and the process was studied in an in-situ half-cycle XPS experiment. DEZ/H2O is able to remove all Sb-S from the surface, forming a stable ZnS passivation layer. This passivation layer is resistant to further reoxidation during dielectric deposition. The final part of this dissertation is the design and construction of an ultra-high vacuum cluster tool for in-situ electrical characterization. The system consists of three deposition chambers coupled to an electrical probe station. With this setup, devices can be processed and subsequently electrically characterized without exposing the sample to air. This is the first time that such a system has been reported. A special air-gap C-V probe will allow top gated measurements to be made, allowing semiconductor-dielectric interfaces to be studied during device processing.

Method of physical vapor deposition of metal oxides on semiconductors

DOEpatents

Norton, David P.

2001-01-01

A process for growing a metal oxide thin film upon a semiconductor surface with a physical vapor deposition technique in a high-vacuum environment and a structure formed with the process involves the steps of heating the semiconductor surface and introducing hydrogen gas into the high-vacuum environment to develop conditions at the semiconductor surface which are favorable for growing the desired metal oxide upon the semiconductor surface yet is unfavorable for the formation of any native oxides upon the semiconductor. More specifically, the temperature of the semiconductor surface and the ratio of hydrogen partial pressure to water pressure within the vacuum environment are high enough to render the formation of native oxides on the semiconductor surface thermodynamically unstable yet are not so high that the formation of the desired metal oxide on the semiconductor surface is thermodynamically unstable. Having established these conditions, constituent atoms of the metal oxide to be deposited upon the semiconductor surface are directed toward the surface of the semiconductor by a physical vapor deposition technique so that the atoms come to rest upon the semiconductor surface as a thin film of metal oxide with no native oxide at the semiconductor surface/thin film interface. An example of a structure formed by this method includes an epitaxial thin film of (001)-oriented CeO.sub.2 overlying a substrate of (001) Ge.

Static and low frequency noise characterization of ultra-thin body InAs MOSFETs

NASA Astrophysics Data System (ADS)

Karatsori, T. A.; Pastorek, M.; Theodorou, C. G.; Fadjie, A.; Wichmann, N.; Desplanque, L.; Wallart, X.; Bollaert, S.; Dimitriadis, C. A.; Ghibaudo, G.

2018-05-01

A complete static and low frequency noise characterization of ultra-thin body InAs MOSFETs is presented. Characterization techniques, such as the well-known Y-function method established for Si MOSFETs, are applied in order to extract the electrical parameters and study the behavior of these research grade devices. Additionally, the Lambert-W function parameter extraction methodology valid from weak to strong inversion is also used in order to verify its applicability in these experimental level devices. Moreover, a low-frequency noise characterization of the UTB InAs MOSFETs is presented, revealing carrier trapping/detrapping in slow oxide traps and remote Coulomb scattering as origin of 1/f noise, which allowed for the extraction of the oxide trap areal density. Finally, Lorentzian-like noise is also observed in the sub-micron area devices and attributed to both Random Telegraph Noise from oxide individual traps and g-r noise from the semiconductor interface.

Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

NASA Astrophysics Data System (ADS)

Chambonneau, Maxime; Souiki-Figuigui, Sarra; Chiquet, Philippe; Della Marca, Vincenzo; Postel-Pellerin, Jérémy; Canet, Pierre; Portal, Jean-Michel; Grojo, David

2017-04-01

We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables us to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, and defectivity) and for considerable developments in the growing field of ultrafast microelectronics.

Electroluminescence color tuning between green and red from metal-oxide-semiconductor devices fabricated by spin-coating of rare-earth (terbium + europium) organic compounds on silicon

NASA Astrophysics Data System (ADS)

Matsuda, Toshihiro; Hattori, Fumihiro; Iwata, Hideyuki; Ohzone, Takashi

2018-04-01

Color tunable electroluminescence (EL) from metal-oxide-semiconductor devices with the rare-earth elements Tb and Eu is reported. Organic compound liquid sources of (Tb + Ba) and Eu with various Eu/Tb ratios from 0.001 to 0.4 were spin-coated on an n+-Si substrate and annealed to form an oxide insulator layer. The EL spectra had only peaks corresponding to the intrashell Tb3+/Eu3+ transitions in the spectral range from green to red, and the intensity ratio of the peaks was appropriately tuned using the appropriate Eu/Tb ratios in liquid sources. Consequently, the EL emission colors linearly changed from yellowish green to yellowish orange and eventually to reddish orange on the CIE chromaticity diagram. The gate current +I G current also affected the EL colors for the medium-Eu/Tb-ratio device. The structure of the surface insulator films analyzed by cross-sectional transmission electron microscopy (TEM), X-ray diffraction (XRD) analysis, and X-ray photoelectron spectroscopy (XPS) has four layers, namely, (Tb4O7 + Eu2O3), [Tb4O7 + Eu2O3 + (Tb/Eu/Ba)SiO x ], (Tb/Eu/Ba)SiO x , and SiO x -rich oxide. The EL mechanism proposed is that electrons injected from the Si substrate into the SiO x -rich oxide and Tb/Eu/Ba-silicate layers become hot electrons accelerated in a high electric field, and then these hot electrons excite Tb3+ and Eu3+ ions in the Tb4O7/Eu2O3 layers resulting in EL emission from Tb3+ and Eu3+ intrashell transitions.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

PubMed

Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

2012-08-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

PubMed Central

2012-01-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials. PMID:22853458

Robust, functional nanocrystal solids by infilling with atomic layer deposition.

PubMed

Liu, Yao; Gibbs, Markelle; Perkins, Craig L; Tolentino, Jason; Zarghami, Mohammad H; Bustamante, Jorge; Law, Matt

2011-12-14

Thin films of colloidal semiconductor nanocrystals (NCs) are inherently metatstable materials prone to oxidative and photothermal degradation driven by their large surface-to-volume ratios and high surface energies. (1) The fabrication of practical electronic devices based on NC solids hinges on preventing oxidation, surface diffusion, ripening, sintering, and other unwanted physicochemical changes that can plague these materials. Here we use low-temperature atomic layer deposition (ALD) to infill conductive PbSe NC solids with metal oxides to produce inorganic nanocomposites in which the NCs are locked in place and protected against oxidative and photothermal damage. Infilling NC field-effect transistors and solar cells with amorphous alumina yields devices that operate with enhanced and stable performance for at least months in air. Furthermore, ALD infilling with ZnO lowers the height of the inter-NC tunnel barrier for electron transport, yielding PbSe NC films with electron mobilities of 1 cm2 V(-1) s(-1). Our ALD technique is a versatile means to fabricate robust NC solids for optoelectronic devices.

Effect of oxide insertion layer on resistance switching properties of copper phthalocyanine

NASA Astrophysics Data System (ADS)

Joshi, Nikhil G.; Pandya, Nirav C.; Joshi, U. S.

2013-02-01

Organic memory device showing resistance switching properties is a next-generation of the electrical memory unit. We have investigated the bistable resistance switching in current-voltage (I-V) characteristics of organic diode based on copper phthalocyanine (CuPc) film sandwiched between aluminum (Al) electrodes. Pronounced hysteresis in the I-V curves revealed a resistance switching with on-off ratio of the order of 85%. In order to control the charge injection in the CuPc, nanoscale indium oxide buffer layer was inserted to form Al/CuPc/In2O3/Al device. Analysis of I-V measurements revealed space charge limited switching conduction at the Al/CuPc interface. The traps in the organic layer and charge blocking by oxide insertion layer have been used to explain the absence of resistance switching in the oxide buffer layered memory device cell. Present study offer potential applications for CuPc organic semiconductor in low power non volatile resistive switching memory and logic circuits.

Influence of CO annealing in metal-oxide-semiconductor capacitors with SiO2 films thermally grown on Si and on SiC

NASA Astrophysics Data System (ADS)

Pitthan, E.; dos Reis, R.; Corrêa, S. A.; Schmeisser, D.; Boudinov, H. I.; Stedile, F. C.

2016-01-01

Understanding the influence of SiC reaction with CO, a by-product of SiC thermal oxidation, is a key point to elucidate the origin of electrical defects in SiC metal-oxide-semiconductor (MOS) devices. In this work, the effects on electrical, structural, and chemical properties of SiO2/Si and SiO2/SiC structures submitted to CO annealing were investigated. It was observed that long annealing times resulted in the incorporation of carbon from CO in the Si substrate, followed by deterioration of the SiO2/Si interface, and its crystallization as SiC. Besides, this incorporated carbon remained in the Si surface (previous SiO2/Si region) after removal of the silicon dioxide film by HF etching. In the SiC case, an even more defective surface region was observed due to the CO interaction. All MOS capacitors formed using both semiconductor materials presented higher leakage current and generation of positive effective charge after CO annealings. Such results suggest that the negative fixed charge, typically observed in SiO2/SiC structures, is not originated from the interaction of the CO by-product, formed during SiC oxidation, with the SiO2/SiC interfacial region.

Tunable infrared absorption and visible transparency of colloidal aluminum-doped zinc oxide nanocrystals.

PubMed

Buonsanti, Raffaella; Llordes, Anna; Aloni, Shaul; Helms, Brett A; Milliron, Delia J

2011-11-09

Plasmonic nanocrystals have been attracting a lot of attention both for fundamental studies and different applications, from sensing to imaging and optoelectronic devices. Transparent conductive oxides represent an interesting class of plasmonic materials in addition to metals and vacancy-doped semiconductor quantum dots. Herein, we report a rational synthetic strategy of high-quality colloidal aluminum-doped zinc oxide nanocrystals. The presence of substitutional aluminum in the zinc oxide lattice accompanied by the generation of free electrons is proved for the first time by tunable surface plasmon absorption in the infrared region both in solution and in thin films.

Sintered silver joints via controlled topography of electronic packaging subcomponents

DOEpatents

Wereszczak, Andrew A.

2014-09-02

Disclosed are sintered silver bonded electronic package subcomponents and methods for making the same. Embodiments of the sintered silver bonded EPSs include topography modification of one or more metal surfaces of semiconductor devices bonded together by the sintered silver joint. The sintered silver bonded EPSs include a first semiconductor device having a first metal surface, the first metal surface having a modified topography that has been chemically etched, grit blasted, uniaxial ground and/or grid sliced connected to a second semiconductor device which may also include a first metal surface with a modified topography, a silver plating layer on the first metal surface of the first semiconductor device and a silver plating layer on the first metal surface of the second semiconductor device and a sintered silver joint between the silver plating layers of the first and second semiconductor devices which bonds the first semiconductor device to the second semiconductor device.

An Overview of High-k Oxides on Hydrogenated-Diamond for Metal-Oxide-Semiconductor Capacitors and Field-Effect Transistors.

PubMed

Liu, Jiangwei; Koide, Yasuo

2018-06-04

Thanks to its excellent intrinsic properties, diamond is promising for applications of high-power electronic devices, ultraviolet detectors, biosensors, high-temperature tolerant gas sensors, etc. Here, an overview of high- k oxides on hydrogenated-diamond (H-diamond) for metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) is demonstrated. Fabrication routines for the H-diamond MOS capacitors and MOSFETs, band configurations of oxide/H-diamond heterointerfaces, and electrical properties of the MOS and MOSFETs are summarized and discussed. High- k oxide insulators are deposited using atomic layer deposition (ALD) and sputtering deposition (SD) techniques. Electrical properties of the H-diamond MOS capacitors with high- k oxides of ALD-Al₂O₃, ALD-HfO₂, ALD-HfO₂/ALD-Al₂O₃ multilayer, SD-HfO₂/ALD-HfO₂ bilayer, SD-TiO₂/ALD-Al₂O₃ bilayer, and ALD-TiO₂/ALD-Al₂O₃ bilayer are discussed. Analyses for capacitance-voltage characteristics of them show that there are low fixed and trapped charge densities for the ALD-Al₂O₃/H-diamond and SD-HfO₂/ALD-HfO₂/H-diamond MOS capacitors. The k value of 27.2 for the ALD-TiO₂/ALD-Al₂O₃ bilayer is larger than those of the other oxide insulators. Drain-source current versus voltage curves show distinct pitch-off and p -type channel characteristics for the ALD-Al₂O₃/H-diamond, SD-HfO₂/ALD-HfO₂/H-diamond, and ALD-TiO₂/ALD-Al₂O₃/H-diamond MOSFETs. Understanding of fabrication routines and electrical properties for the high- k oxide/H-diamond MOS electronic devices is meaningful for the fabrication of high-performance H-diamond MOS capacitor and MOSFET gas sensors.

Read-noise characterization of focal plane array detectors via mean-variance analysis.

PubMed

Sperline, R P; Knight, A K; Gresham, C A; Koppenaal, D W; Hieftje, G M; Denton, M B

2005-11-01

Mean-variance analysis is described as a method for characterization of the read-noise and gain of focal plane array (FPA) detectors, including charge-coupled devices (CCDs), charge-injection devices (CIDs), and complementary metal-oxide-semiconductor (CMOS) multiplexers (infrared arrays). Practical FPA detector characterization is outlined. The nondestructive readout capability available in some CIDs and FPA devices is discussed as a means for signal-to-noise ratio improvement. Derivations of the equations are fully presented to unify understanding of this method by the spectroscopic community.

Comprehensive capacitance-voltage analysis including quantum effects for high-k interfaces on germanium and other alternative channel materials

NASA Astrophysics Data System (ADS)

Anwar, Sarkar R. M.

High mobility alternative channel materials to silicon are critical to the continued scaling of metal oxide semiconductor (MOS) devices. However, before they can be incorporated into advanced devices, some major issues need to be solved. The high mobility materials suffer from lower allowable thermal budgets compared to Si (before desorption and defect formation becomes an issue) and the absence of a good quality native oxide has further increased the interest in the use of high-k dielectrics. However, the high interface state density and high electric fields at these semiconductor/high-k interfaces can significantly impact the capacitance-voltage (C-V) profile, and current C-V modeling software cannot account for these effects. This in turn affects the parameters extracted from the C-V data of the high mobility semiconductor/high-k interface, which are crucial to fully understand the interface properties and expedite process development. To address this issue, we developed a model which takes into account quantum corrections which can be applied to a number of these alternative channel materials including SixGe1-x, Ge, InGaAs, and GaAs. The C-V simulation using this QM correction model is orders of magnitude faster compared to a full band Schrodinger-Poisson solver. The simulated C-V is directly benchmarked to a self consistent Schrodinger-Poisson solution for each bulk semiconductor material, and from the benchmarking process the QM correction parameters are extracted. The full program, C-V Alternative Channel Extraction (CV ACE), incorporates a quantum mechanical correction model, along with the interface state density model, and can extract device parameters such as equivalent oxide thickness (EOT), doping density and flat band voltage (Vfb) as well as the interface state density profile using multiple measurements performed at different frequencies and temperatures, simultaneously. The program was used to analyze experimentally measured C-V profiles and the extracted device parameters show excellent agreement with the known device structure and previously published results. CV ACE has been applied in the development of a process flow for germanium interface passivation in Ge based MOS devices using a GeOx interlayer. A post atomic layer deposition (ALD) plasma oxidation (PPO) process was developed using radio frequency (RF) plasma in a plasma enhanced chemical vapor deposition (PECVD) chamber and demonstrated significant surface passivation. Various gases were investigated and 1% O2/Ar was found to reduce the growth rate and provide excellent control over the degradation of EOT. A 100 W plasma with 1% O2/Ar was found to provide the best combination of EOT and low Dit and is concluded to be the optimum process for PPO of germanium surfaces. CV ACE and PPO were also utilized to investigate other process development challenges. A study of the impact of low temperature anneals on Ge-based MOS devices was found to result in a degradation of the electrical thickness and a change in fixed charge, indicating that the process window is very narrow and at much lower temperatures than for Si.

Reducing leakage current in semiconductor devices

DOEpatents

Lu, Bin; Matioli, Elison de Nazareth; Palacios, Tomas Apostol

2018-03-06

A semiconductor device includes a first region having a first semiconductor material and a second region having a second semiconductor material. The second region is formed over the first region. The semiconductor device also includes a current blocking structure formed in the first region between first and second terminals of the semiconductor device. The current blocking structure is configured to reduce current flow in the first region between the first and second terminals.

Functionalized organic semiconductor molecules to enhance charge carrier injection in electroluminescent cell

NASA Astrophysics Data System (ADS)

Yalcin, Eyyup; Kara, Duygu Akin; Karakaya, Caner; Yigit, Mesude Zeliha; Havare, Ali Kemal; Can, Mustafa; Tozlu, Cem; Demic, Serafettin; Kus, Mahmut; Aboulouard, Abdelkhalk

2017-07-01

Organic semiconductor (OSC) materials as a charge carrier interface play an important role to improve the device performance of organic electroluminescent cells. In this study, 4,4″-bis(diphenyl amino)-1,1':3‧,1″-terphenyl-5'-carboxylic acid (TPA) and 4,4″-di-9H-carbazol-9-yl-1,1':3‧,1″-terphenyl-5'-carboxylic acid (CAR) has been designed and synthesized to modify indium tin oxide (ITO) layer as interface. Bare ITO and PEDOT:PSS coated on ITO was used as reference anode electrodes for comparison. Furthermore, PEDOT:PSS coated over CAR/ITO and TPA/ITO to observe stability of OSC molecules and to completely cover the ITO surface. Electrical, optical and surface characterizations were performed for each device. Almost all modified devices showed around 36% decrease at the turn on voltage with respect to bare ITO. The current density of bare ITO, ITO/CAR and ITO/TPA were measured as 288, 1525 and 1869 A/m2, respectively. By increasing current density, luminance of modified devices showed much better performance with respect to unmodified devices.

Extraction of carrier mobility and interface trap density in InGaAs metal oxide semiconductor structures using gated Hall method

NASA Astrophysics Data System (ADS)

Chidambaram, Thenappan

III-V semiconductors are potential candidates to replace Si as a channel material in next generation CMOS integrated circuits owing to their superior carrier mobilities. Low density of states (DOS) and typically high interface and border trap densities (Dit) in high mobility group III-V semiconductors provide difficulties in quantification of Dit near the conduction band edge. The trap response above the threshold voltage of a MOSFET can be very fast, and conventional Dit extraction methods, based on capacitance/conductance response (CV methods) of MOS capacitors at frequencies <1MHz, cannot distinguish conducting and trapped carriers. In addition, the CV methods have to deal with high dispersion in the accumulation region that makes it a difficult task to measure the true oxide capacitance, Cox value. Another implication of these properties of III-V interfaces is an ambiguity of determination of electron density in the MOSFET channel. Traditional evaluation of carrier density by integration of the C-V curve, gives incorrect values for D it and mobility. Here we employ gated Hall method to quantify the D it spectrum at the high-K oxide/III-V semiconductor interface for buried and surface channel devices using Hall measurement and capacitance-voltage data. Determination of electron density directly from Hall measurements allows for obtaining true mobility values.

Role of order and disorder on the electronic performances of oxide semiconductor thin film transistors

NASA Astrophysics Data System (ADS)

Martins, R.; Barquinha, P.; Ferreira, I.; Pereira, L.; Gonçalves, G.; Fortunato, E.

2007-02-01

The role of order and disorder on the electronic performances of n-type ionic oxides such as zinc oxide, gallium zinc oxide, and indium zinc oxide used as active (channel) or passive (drain/source) layers in thin film transistors (TFTs) processed at room temperature are discussed, taking as reference the known behavior observed in conventional covalent semiconductors such as silicon. The work performed shows that while in the oxide semiconductors the Fermi level can be pinned up within the conduction band, independent of the state of order, the same does not happen with silicon. Besides, in the oxide semiconductors the carrier mobility is not bandtail limited and so disorder does not affect so strongly the mobility as it happens in covalent semiconductors. The electrical properties of the oxide films (resistivity, carrier concentration, and mobility) are highly dependent on the oxygen vacancies (source of free carriers), which can be controlled by changing the oxygen partial pressure during the deposition process and/or by adding other metal ions to the matrix. In this case, we make the oxide matrix less sensitive to the presence of oxygen, widening the range of oxygen partial pressures that can be used and thus improving the process control of the film resistivity. The results obtained in fully transparent TFT using polycrystalline ZnO or amorphous indium zinc oxide (IZO) as channel layers and highly conductive poly/nanocrystalline ZGO films or amorphous IZO as drain/source layers show that both devices work in the enhancement mode, but the TFT with the highest electronic saturation mobility and on/off ratio 49.9cm2/Vs and 4.3×108, respectively, are the ones in which the active and passive layers are amorphous. The ZnO TFT whose channel is based on polycrystalline ZnO, the mobility and on/off ratio are, respectively, 26cm2/Vs and 3×106. This behavior is attributed to the fact that the electronic transport is governed by the s-like metal cation conduction bands, not significantly affected by any type of angular disorder promoted by the 2p O states related to the valence band, or small amounts of incorporated metal impurities that lead to a better control of vacancies and of the TFT off current.

Charge Carriers Modulate the Bonding of Semiconductor Nanoparticle Dopants As Revealed by Time-Resolved X-ray Spectroscopy

DOE PAGES

Hassan, Asra; Zhang, Xiaoyi; Liu, Xiaohan; ...

2017-08-28

Understanding the electronic structure of doped semiconductors is essential to realize advancements in electronics and in the rational design of nanoscale devices. Here, we report the results of time-resolved X-ray absorption studies on copper-doped cadmium sulfide nanoparticles that provide an explicit description of the electronic dynamics of the dopants. The interaction of a dopant ion and an excess charge carrier is unambiguously observed via monitoring the oxidation state. The experimental data combined with DFT calculations demonstrate that dopant bonding to the host matrix is modulated by its interaction with charge carriers. Additionally, the transient photoluminescence and the kinetics of dopantmore » oxidation reveal the presence of two types of surface-bound ions that create mid-gap states.« less

Charge Carriers Modulate the Bonding of Semiconductor Nanoparticle Dopants As Revealed by Time-Resolved X-ray Spectroscopy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hassan, Asra; Zhang, Xiaoyi; Liu, Xiaohan

Understanding the electronic structure of doped semiconductors is essential to realize advancements in electronics and in the rational design of nanoscale devices. Here, we report the results of time-resolved X-ray absorption studies on copper-doped cadmium sulfide nanoparticles that provide an explicit description of the electronic dynamics of the dopants. The interaction of a dopant ion and an excess charge carrier is unambiguously observed via monitoring the oxidation state. The experimental data combined with DFT calculations demonstrate that dopant bonding to the host matrix is modulated by its interaction with charge carriers. Additionally, the transient photoluminescence and the kinetics of dopantmore » oxidation reveal the presence of two types of surface-bound ions that create mid-gap states.« less

Miniaturized metal (metal alloy)/ PdO.sub.x/SiC hydrogen and hydrocarbon gas sensors

NASA Technical Reports Server (NTRS)

Hunter, Gary W. (Inventor); Xu, Jennifer C. (Inventor); Lukco, Dorothy (Inventor)

2011-01-01

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO.sub.x ). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600.degree. C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sized sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Miniaturized metal (metal alloy)/ PdO.sub.x/SiC hydrogen and hydrocarbon gas sensors

NASA Technical Reports Server (NTRS)

Xu, Jennifer C. (Inventor); Hunter, Gary W. (Inventor); Lukco, Dorothy (Inventor)

2008-01-01

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO.sub.x). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600.degree. C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sized sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Nanocrystalline ZnON; High mobility and low band gap semiconductor material for high performance switch transistor and image sensor application

PubMed Central

Lee, Eunha; Benayad, Anass; Shin, Taeho; Lee, HyungIk; Ko, Dong-Su; Kim, Tae Sang; Son, Kyoung Seok; Ryu, Myungkwan; Jeon, Sanghun; Park, Gyeong-Su

2014-01-01

Interest in oxide semiconductors stems from benefits, primarily their ease of process, relatively high mobility (0.3–10 cm2/vs), and wide-bandgap. However, for practical future electronic devices, the channel mobility should be further increased over 50 cm2/vs and wide-bandgap is not suitable for photo/image sensor applications. The incorporation of nitrogen into ZnO semiconductor can be tailored to increase channel mobility, enhance the optical absorption for whole visible light and form uniform micro-structure, satisfying the desirable attributes essential for high performance transistor and visible light photo-sensors on large area platform. Here, we present electronic, optical and microstructural properties of ZnON, a composite of Zn3N2 and ZnO. Well-optimized ZnON material presents high mobility exceeding 100 cm2V−1s−1, the band-gap of 1.3 eV and nanocrystalline structure with multiphase. We found that mobility, microstructure, electronic structure, band-gap and trap properties of ZnON are varied with nitrogen concentration in ZnO. Accordingly, the performance of ZnON-based device can be adjustable to meet the requisite of both switch device and image-sensor potentials. These results demonstrate how device and material attributes of ZnON can be optimized for new device strategies in display technology and we expect the ZnON will be applicable to a wide range of imaging/display devices. PMID:24824778

Oxidation of SiC

NASA Astrophysics Data System (ADS)

Cooper, James A.

1997-03-01

SiC is a wide band gap hexagonal anisotropic semiconductor which is attractive for use in high voltage, high temperature, or high power applications. SiC is also the only compound semiconductor that can be thermally oxidized to form SiO_2, making it possible to construct many conventional MOS devices in this material. The electrical quality of the SiO_2/SiC interface is far from ideal, however, and considerable research is presently directed to understanding and improving this interface. Electrical characterization of the SiC MOS interface is complicated by the wide band gap, since most interface states are energetically too far removed from the conduction or valence bands to respond to electrical stimulation at room temperature. Moreover, very little information is yet available on the properties of the MOS interface on the 4H polytype of SiC (preferred because of it's higher bulk electron mobility) or on interfaces on crystalline surfaces perpendicular to the basal plane (where an equal number of Si and C atoms are present). Finally, electron mobilities in inversion layers on 4H-SiC reported to date are anomolously low, especially in consideration of the relatively high bulk mobilities in this polytype. In this talk we will discuss MOS characterization techniques for wide band gap semiconductors and review the current understanding of the physics of the MOS interface on thermally oxidized SiC.

A concise way to estimate the average density of interface states in an ITO-SiOx/n-Si heterojunction solar cell

NASA Astrophysics Data System (ADS)

Li, Y.; Han, B. C.; Gao, M.; Wan, Y. Z.; Yang, J.; Du, H. W.; Ma, Z. Q.

2017-09-01

On the basis of a photon-assisted high frequency capacitance-voltage (C-V) method (1 MHz C-V), an effective approach is developed to evaluate the average interface state density (Dit) of an ITO-SiOx/n-Si heterojunction structure. Tin-doped indium oxide (ITO) films with different thicknesses were directly deposited on (100) n-type crystalline silicon by magnetron sputtering to fabricate semiconductor-insulator-semiconductor (SIS) hetero-interface regions where an ultra-thin SiOx passivation layer was naturally created. The morphology of the SiOx layer was confirmed by X-ray photoelectron spectroscopy depth profiling and transmission electron microscope analysis. The thinness of this SiOx layer was the main reason for the SIS interface state density being more difficult to detect than that of a typical metal-oxide-semiconductor structure. A light was used for photon injection while measuring the C-V of the device, thus enabling the photon-assisted C-V measurement of the Dit. By quantifying decreases of the light-induced-voltage as a variation of the capacitance caused by parasitic charge at interface states the passivation quality within the interface of ITO-SiOx/n-Si could be reasonably evaluated. The average interface state density of these SIS devices was measured as 1.2-1.7 × 1011 eV-1 cm-2 and declined as the passivation layer was made thicker. The lifetime of the minority carriers, dark leakage current, and the other photovoltaic parameters of the devices were also used to determine the passivation.

Oxide Structure Dependence of SiO2/SiOx/3C-SiC/n-Type Si Nonvolatile Resistive Memory on Memory Operation Characteristics

NASA Astrophysics Data System (ADS)

Yamaguchi, Yuichiro; Shouji, Masatsugu; Suda, Yoshiyuki

2012-11-01

We have investigated the dependence of the oxide layer structure of our previously proposed metal/SiO2/SiOx/3C-SiC/n-Si/metal metal-insulator-semiconductor (MIS) resistive memory device on the memory operation characteristics. The current-voltage (I-V) measurement and X-ray photoemission spectroscopy results suggest that SiOx defect states mainly caused by the oxidation of 3C-SiC at temperatures below 1000 °C are related to the hysteresis memory behavior in the I-V curve. By restricting the SiOx interface region, the number of switching cycles and the on/off current ratio are more enhanced. Compared with a memory device formed by one-step or two-step oxidation of 3C-SiC, a memory device formed by one-step oxidation of Si/3C-SiC exhibits a more restrictive SiOx interface with a more definitive SiO2 layer and higher memory performances for both the endurance switching cycle and on/off current ratio.

Metal-oxide-metal point contact junction detectors. [detection mechanism and mechanical stability

NASA Technical Reports Server (NTRS)

Baird, J.; Havemann, R. H.; Fults, R. D.

1973-01-01

The detection mechanism(s) and design of a mechanically stable metal-oxide-metal point contact junction detector are considered. A prototype for a mechanically stable device has been constructed and tested. A technique has been developed which accurately predicts microwave video detector and heterodyne mixer SIM (semiconductor-insulator-metal) diode performance from low dc frequency volt-ampere curves. The difference in contact potential between the two metals and geometrically induced rectification constitute the detection mechanisms.

Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors

NASA Astrophysics Data System (ADS)

Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

2016-04-01

In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade-1 and 3.62 × 1011 eV-1 cm-2, respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

Oxide materials for spintronic device applications

NASA Astrophysics Data System (ADS)

Prestgard, Megan Campbell

Spintronic devices are currently being researched as next-generation alternatives to traditional electronics. Electronics, which utilize the charge-carrying capabilities of electrons to store information, are fundamentally limited not only by size constraints, but also by limits on current flow and degradation, due to electro-migration. Spintronics devices are able to overcome these limitations, as their information storage is in the spin of electrons, rather than their charge. By using spin rather than charge, these current-limiting shortcomings can be easily overcome. However, for spintronic devices to be fully implemented into the current technology industry, their capabilities must be improved. Spintronic device operation relies on the movement and manipulation of spin-polarized electrons, in which there are three main processes that must be optimized in order to maximize device efficiencies. These spin-related processes are: the injection of spin-polarized electrons, the transport and manipulation of these carriers, and the detection of spin-polarized currents. In order to enhance the rate of spin-polarized injection, research has been focused on the use of alternative methods to enhance injection beyond that of a simple ferromagnetic metal/semiconductor injector interface. These alternatives include the use of oxide-based tunnel barriers and the modification of semiconductors and insulators for their use as ferromagnetic injector materials. The transport of spin-polarized carriers is heavily reliant on the optimization of materials' properties in order to enhance the carrier mobility and to quench spin-orbit coupling (SOC). However, a certain degree of SOC is necessary in order to allow for the electric-field, gate-controlled manipulation of spin currents. Spin detection can be performed via both optical and electrical techniques. Using electrical methods relies on the conversion between spin and charge currents via SOC and is often the preferred method for device-based applications. This dissertation presents experimental results on the use of oxides for fulfilling the three spintronic device requirements. In the case of spin injection, the study of dilute magnetic dielectrics (DMDs) shows the importance of doping on the magnetic properties of the resulting tunnel barriers. The study of spin transport in ZnO has shown that, even at room temperature, the spin diffusion length is relatively long, on the order of 100 nm. These studies have also probed the spin relaxation mechanics in ZnO and have shown that Dyakonov-Perel spin relaxation, operating according to Fermi-Dirac statistics, is the dominant spin relaxation mechanism in zinc oxide. Finally, spin detection in ZnO has shown that, similar to other semiconductors, by modifying the resistivity of the ZnO thin films, the spin Hall angle (SHA) can be enhanced to nearly that of metals. This is possible by enhancing extrinsic SOC due to skew-scattering from impurities as well as phonons. In addition, thermal spin injection has also been detected using ZnO, which results support the independently measured inverse spin-Hall effect studies. The work represented herein illustrates that oxide materials have the potential to enhance spintronic device potential in all processes pertinent to spintronic applications.

Investigation of Gallium Nitride Transistor Reliability through Accelerated Life Testing and Modeling

DTIC Science & Technology

2011-12-01

Carbon Cd Cadmium CdS Cadmium Sulfide CMOS Complementary Metal Oxide Semiconductor DC Direct Current DoD Department of Defense EBL Electron...Crane Division [NAVSEA Crane], Crane, Indiana ) are Section 4.1and Section 4.3, Condition 2. Eight devices were stressed for over 1000 hours each and

JPL CMOS Active Pixel Sensor Technology

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

Top-down Fabrication and Enhanced Active Area Electronic Characteristics of Amorphous Oxide Nanoribbons for Flexible Electronics.

PubMed

Jang, Hyun-June; Joong Lee, Ki; Jo, Kwang-Won; Katz, Howard E; Cho, Won-Ju; Shin, Yong-Beom

2017-07-18

Inorganic amorphous oxide semiconductor (AOS) materials such as amorphous InGaZnO (a-IGZO) possess mechanical flexibility and outstanding electrical properties, and have generated great interest for use in flexible and transparent electronic devices. In the past, however, AOS devices required higher activation energies, and hence higher processing temperatures, than organic ones to neutralize defects. It is well known that one-dimensional nanowires tend to have better carrier mobility and mechanical strength along with fewer defects than the corresponding two-dimensional films, but until now it has been difficult, costly, and impractical to fabricate such nanowires in proper alignments by either "bottom-up" growth techniques or by "top-down" e-beam lithography. Here we show a top-down, cost-effective, and scalable approach for the fabrication of parallel, laterally oriented AOS nanoribbons based on lift-off and nano-imprinting. High mobility (132 cm 2 /Vs), electrical stability, and transparency are obtained in a-IGZO nanoribbons, compared to the planar films of the same a-IGZO semiconductor.

Improved interface properties of Ge metal-oxide-semiconductor capacitor with TaTiO gate dielectric by using in situ TaON passivation interlayer

NASA Astrophysics Data System (ADS)

Ji, F.; Xu, J. P.; Liu, J. G.; Li, C. X.; Lai, P. T.

2011-05-01

TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N2 to suppress the growth of unstable GeOx at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3×1011 cm-2 eV), small gate leakage current (8.6×10-4 A cm-2 at Vg-Vfb=1 V), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet-N2 anneal can significantly suppress the growth of unstable low-k GeOx.

Nitride passivation reduces interfacial traps in atomic-layer-deposited Al{sub 2}O{sub 3}/GaAs (001) metal-oxide-semiconductor capacitors using atmospheric metal-organic chemical vapor deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aoki, T., E-mail: aokit@sc.sumitomo-chem.co.jp; Fukuhara, N.; Osada, T.

2014-07-21

Using an atmospheric metal-organic chemical vapor deposition system, we passivated GaAs with AlN prior to atomic layer deposition of Al{sub 2}O{sub 3}. This AlN passivation incorporated nitrogen at the Al{sub 2}O{sub 3}/GaAs interface, improving the capacitance-voltage (C–V) characteristics of the resultant metal-oxide-semiconductor capacitors (MOSCAPs). The C–V curves of these devices showed a remarkable reduction in the frequency dispersion of the accumulation capacitance. Using the conductance method at various temperatures, we extracted the interfacial density of states (D{sub it}). The D{sub it} was reduced over the entire GaAs band gap. In particular, these devices exhibited D{sub it} around the midgap ofmore » less than 4 × 10{sup 12} cm{sup −2}eV{sup −1}, showing that AlN passivation effectively reduced interfacial traps in the MOS structure.« less

Design and development of short- and long-wavelength MQW infrared vertical cavity surface emitting lasers

NASA Astrophysics Data System (ADS)

Iliadis, Agisilaos A.; Christou, Aristos

2003-07-01

The design, fabrication and performance of low threshold selectively oxidized infrared vertical cavity surface emitting lasers (VCSELs) for operation at 0.89μm and 1.55μm wavelengths using optimized graded Bragg mirrors, is reported. The devices are based on III-V ternary (AlGaAs/GaAs) and quaternary (AlInGaAs/GaInAsP/InP) graded semiconductor alloys and quantum wells and are grown by Molecular Beam Epitaxy. The VCSEL arrays are processed using inductively coupled plasma (ICP) etching with BCl3 gas mixtures to achieve vertical walls and small geometries, and the fabrication of the devices proceeds by using conventional Ohmic contacts (Ti-Pt-Au and Ni-Au-Ge-Ni) and indium tin oxide (ITO) transparent contacts. The theoretical investigation of the optical properties of the quaternary compound semiconductor alloys allows us to select the optimum materials for highly reflective Bragg mirrors with less periods. The simulation of the designed VCSEL performance has been carried out by evaluation of the important laser characteristics such as threshold gain, threshold current density and external quantum efficiency.

Oxide semiconductors for organic opto-electronic devices

NASA Astrophysics Data System (ADS)

Sigdel, Ajaya K.

In this dissertation, I have introduced various concepts on the modulations of various surface, interface and bulk opto-electronic properties of ZnO based semiconductor for charge transport, charge selectivity and optimal device performance. I have categorized transparent semiconductors into two sub groups depending upon their role in a device. Electrodes, usually 200 to 500 nm thick, optimized for good transparency and transporting the charges to the external circuit. Here, the electrical conductivity in parallel direction to thin film, i.e bulk conductivity is important. And contacts, usually 5 to 50 nm thick, are optimized in case of solar cells for providing charge selectivity and asymmetry to manipulate the built in field inside the device for charge separation and collection. Whereas in Organic LEDs (OLEDs), contacts provide optimum energy level alignment at organic oxide interface for improved charge injections. For an optimal solar cell performance, transparent electrodes are designed with maximum transparency in the region of interest to maximize the light to pass through to the absorber layer for photo-generation, plus they are designed for minimum sheet resistance for efficient charge collection and transport. As such there is need for material with high conductivity and transparency. Doping ZnO with some common elements such as B, Al, Ga, In, Ge, Si, and F result in n-type doping with increase in carriers resulting in high conductivity electrode, with better or comparable opto-electronic properties compared to current industry-standard indium tin oxide (ITO). Furthermore, improvement in mobility due to improvement on crystallographic structure also provide alternative path for high conductivity ZnO TCOs. Implementing these two aspects, various studies were done on gallium doped zinc oxide (GZO) transparent electrode, a very promising indium free electrode. The dynamics of the superimposed RF and DC power sputtering was utilized to improve the microstructure during the thin films growth, resulting in GZO electrode with conductivity greater than 4000 S/cm and transparency greater than ˜ 90%. Similarly, various studies on research and development of Indium Zinc Tin Oxide and Indium Zinc Oxide thin films which can be applied to flexible substrates for next generation solar cells application is presented. In these new TCO systems, understanding the role of crystallographic structure ranging from poly-crystalline to amorphous phase and the influence on the charge transport and optical transparency as well as important surface passivation and surface charge transport properties. Implementation of these electrode based on ZnO on opto-electronics devices such as OLED and OPV is complicated due to chemical interaction over time with the organic layer or with ambient. The problem of inefficient charge collection/injection due to poor understanding of interface and/or bulk property of oxide electrode exists at several oxide-organic interfaces. The surface conductivity, the work function, the formation of dipoles and the band-bending at the interfacial sites can positively or negatively impact the device performance. Detailed characterization of the surface composition both before and after various chemicals treatment of various oxide electrode can therefore provide insight into optimization of device performance. Some of the work related to controlling the interfacial chemistry associated with charge transport of transparent electrodes are discussed. Thus, the role of various pre-treatment on poly-crystalline GZO electrode and amorphous indium zinc oxide (IZO) electrode is compared and contrasted. From the study, we have found that removal of defects and self passivating defects caused by accumulation of hydroxides in the surface of both poly-crystalline GZO and amorphous IZO, are critical for improving the surface conductivity and charge transport. Further insight on how these insulating and self-passivating defects cause charge accumulation and recombination in an device is discussed. (Abstract shortened by UMI.)

Nonvolatile gate effect in a ferroelectric-semiconductor quantum well.

PubMed

Stolichnov, Igor; Colla, Enrico; Setter, Nava; Wojciechowski, Tomasz; Janik, Elzbieta; Karczewski, Grzegorz

2006-12-15

Field effect transistors with ferroelectric gates would make ideal rewritable nonvolatile memories were it not for the severe problems in integrating the ferroelectric oxide directly on the semiconductor channel. We propose a powerful way to avoid these problems using a gate material that is ferroelectric and semiconducting simultaneously. First, ferroelectricity in semiconductor (Cd,Zn)Te films is proven and studied using modified piezoforce scanning probe microscopy. Then, a rewritable field effect device is demonstrated by local poling of the (Cd,Zn)Te layer of a (Cd,Zn)Te/CdTe quantum well, provoking a reversible, nonvolatile change in the resistance of the 2D electron gas. The results point to a potential new family of nanoscale one-transistor memories.

Methods and devices for fabricating and assembling printable semiconductor elements

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nuzzo, Ralph G.; Rogers, John A.; Menard, Etienne

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Methods and devices for fabricating and assembling printable semiconductor elements

DOEpatents

Nuzzo, Ralph G; Rogers, John A; Menard, Etienne; Lee, Keon Jae; Khang, Dahl-Young; Sun, Yugang; Meitl, Matthew; Zhu, Zhengtao

2014-03-04

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Holmium hafnate: An emerging electronic device material

NASA Astrophysics Data System (ADS)

Pavunny, Shojan P.; Sharma, Yogesh; Kooriyattil, Sudheendran; Dugu, Sita; Katiyar, Rajesh K.; Scott, James F.; Katiyar, Ram S.

2015-03-01

We report structural, optical, charge transport, and temperature properties as well as the frequency dependence of the dielectric constant of Ho2Hf2O7 (HHO) which make this material desirable as an alternative high-k dielectric for future silicon technology devices. A high dielectric constant of ˜20 and very low dielectric loss of ˜0.1% are temperature and voltage independent at 100 kHz near ambient conditions. The Pt/HHO/Pt capacitor exhibits exceptionally low Schottky emission-based leakage currents. In combination with the large observed bandgap Eg of 5.6 eV, determined by diffuse reflectance spectroscopy, our results reveal fundamental physics and materials science of the HHO metal oxide and its potential application as a high-k dielectric for the next generation of complementary metal-oxide-semiconductor devices.

Oxygen-ion-migration-modulated bipolar resistive switching and complementary resistive switching in tungsten/indium tin oxide/gold memory device

NASA Astrophysics Data System (ADS)

Wu, Xinghui; Zhang, Qiuhui; Cui, Nana; Xu, Weiwei; Wang, Kefu; Jiang, Wei; Xu, Qixing

2018-06-01

In this paper, we report our investigation of room-temperature-fabricated tungsten/indium tin oxide/gold (W/ITO/Au) resistive random access memory (RRAM), which exhibits asymmetric bipolar resistive switching (BRS) behavior. The device displays good write/erase endurance and data retention properties. The device shows complementary resistive switching (CRS) characteristics after controlling the compliance current. A WO x layer electrically formed at the W/ITO in the forming process. Mobile oxygen ions within ITO migrate toward the electrode/ITO interface and produce a semiconductor-like layer that acts as a free-carrier barrier. The CRS characteristic here can be elucidated in light of the evolution of an asymmetric free-carrier blocking layer at the electrode/ITO interface.

Novel failure mechanism and improvement for split-gate trench MOSFET with large current under unclamped inductive switch stress

NASA Astrophysics Data System (ADS)

Tian, Ye; Yang, Zhuo; Xu, Zhiyuan; Liu, Siyang; Sun, Weifeng; Shi, Longxing; Zhu, Yuanzheng; Ye, Peng; Zhou, Jincheng

2018-04-01

In this paper, a novel failure mechanism under unclamped inductive switch (UIS) for Split-Gate Trench Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with large current is investigated. The device sample is tested and analyzed in detail. The simulation results demonstrate that the nonuniform potential distribution of the source poly should be responsible for the failure. Three structures are proposed and verified available to improve the device UIS ruggedness by TCAD simulation. The best one of the structures the device with source metal inserting into source poly through contacts in the field oxide is carried out and measured. The results demonstrate that the optimized structure can balance the trade-off between the UIS ruggedness and the static characteristics.

Engineering of Metal Oxide Nanoparticles for Application in Electrochemical Devices

NASA Astrophysics Data System (ADS)

Santos, Lidia Sofia Leitao

The growing demand for materials and devices with new functionalities led to the increased interest in the field of nanomaterials and nanotechnologies. Nanoparticles, not only present a reduced size as well as high reactivity, which allows the development of electronic and electrochemical devices with exclusive properties, when compared with thin films. This dissertation aims to explore the development of several nanostructured metal oxides by solvothermal synthesis and its application in different electrochemical devices. Within this broad theme, this study has a specific number of objectives: a) research of the influence of the synthesis parameters to the structure and morphology of the nanoparticles; b) improvement of the performance of the electrochromic devices with the application of the nanoparticles as electrode; c) application of the nanoparticles as probes to sensing devices; and d) production of solution-pro-cessed transistors with a nanostructured metal oxide semiconductor. Regarding the results, several conclusions can be exposed. Solvothermal synthesis shows to be a very versatile method to control the growth and morphology of the nanoparticles. The electrochromic device performance is influenced by the different structures and morphologies of WO3 nanoparticles, mainly due to the surface area and conductivity of the materials. The deposition of the electrochromic layer by inkjet printing allows the patterning of the electrodes without wasting material and without any additional steps. Nanostructured WO3 probes were produced by electrodeposition and drop casting and applied as pH sensor and biosensor, respectively. The good performance and sensitivity of the devices is explained by the high number of electrochemical reactions occurring at the surface of the na-noparticles. GIZO nanoparticles were deposited by spin coating and used in electrolyte-gated transistors, which promotes a good interface between the semiconductor and the dielectric. The produced transistors work at low potential and with improved ON-OFF current ratio, up to 6 orders of mag-nitude. To summarize, the low temperatures used in the production of the devices are compatible with flexible substrates and additionally, the low cost of the techniques involved can be adapted for disposable devices.

Methods of producing free-standing semiconductors using sacrificial buffer layers and recyclable substrates

DOEpatents

Ptak, Aaron Joseph; Lin, Yong; Norman, Andrew; Alberi, Kirstin

2015-05-26

A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a spinel substrate using a sacrificial buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The sacrificial buffer material and semiconductor materials may be deposited using lattice-matching epitaxy or coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The sacrificial buffer layer may be dissolved using an epitaxial liftoff technique in order to separate the semiconductor device from the spinel substrate, and the spinel substrate may be reused in the subsequent fabrication of other semiconductor devices. The low-defect density semiconductor materials produced using this method result in the enhanced performance of the semiconductor devices that incorporate the semiconductor materials.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Ao; Liu, Guoxia, E-mail: gxliu@qdu.edu.cn, E-mail: fukaishan@yahoo.com; Zhu, Huihui

Solution-processed p-type oxide semiconductors have recently attracted increasing interests for the applications in low-cost optoelectronic devices and low-power consumption complementary metal-oxide-semiconductor circuits. In this work, p-type nickel oxide (NiO{sub x}) thin films were prepared using low-temperature solution process and integrated as the channel layer in thin-film transistors (TFTs). The electrical properties of NiO{sub x} TFTs, together with the characteristics of NiO{sub x} thin films, were systematically investigated as a function of annealing temperature. By introducing aqueous high-k aluminum oxide (Al{sub 2}O{sub 3}) gate dielectric, the electrical performance of NiO{sub x} TFT was improved significantly compared with those based on SiO{submore » 2} dielectric. Particularly, the hole mobility was found to be 60 times enhancement, quantitatively from 0.07 to 4.4 cm{sup 2}/V s, which is mainly beneficial from the high areal capacitance of the Al{sub 2}O{sub 3} dielectric and high-quality NiO{sub x}/Al{sub 2}O{sub 3} interface. This simple solution-based method for producing p-type oxide TFTs is promising for next-generation oxide-based electronic applications.« less

Study of SiO{sub 2}/4H-SiC interface nitridation by post-oxidation annealing in pure nitrogen gas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chanthaphan, Atthawut, E-mail: chanthaphan@asf.mls.eng.osaka-u.ac.jp; Hosoi, Takuji, E-mail: hosoi@mls.eng.osaka-u.ac.jp; Shimura, Takayoshi

An alternative and effective method to perform interface nitridation for 4H-SiC metal-oxide-semiconductor (MOS) devices was developed. We found that the high-temperature post-oxidation annealing (POA) in N{sub 2} ambient was beneficial to incorporate a sufficient amount of nitrogen atoms directly into thermal SiO{sub 2}/SiC interfaces. Although N{sub 2}-POA was ineffective for samples with thick thermal oxide layers, interface nitridation using N{sub 2}-POA was achieved under certain conditions, i.e., thin SiO{sub 2} layers (< 15 nm) and high annealing temperatures (>1350°C). Electrical characterizations of SiC-MOS capacitors treated with high-temperature N{sub 2}-POA revealed the same evidence of slow trap passivation and fast trapmore » generation that occurred in NO-treated devices fabricated with the optimized nitridation conditions.« less

Resistive switching characteristics and mechanisms in silicon oxide memory devices

NASA Astrophysics Data System (ADS)

Chang, Yao-Feng; Fowler, Burt; Chen, Ying-Chen; Zhou, Fei; Wu, Xiaohan; Chen, Yen-Ting; Wang, Yanzhen; Xue, Fei; Lee, Jack C.

2016-05-01

Intrinsic unipolar SiOx-based resistance random access memories (ReRAM) characterization, switching mechanisms, and applications have been investigated. Device structures, material compositions, and electrical characteristics are identified that enable ReRAM cells with high ON/OFF ratio, low static power consumption, low switching power, and high readout-margin using complementary metal-oxide semiconductor transistor (CMOS)-compatible SiOx-based materials. These ideas are combined with the use of horizontal and vertical device structure designs, composition optimization, electrical control, and external factors to help understand resistive switching (RS) mechanisms. Measured temperature effects, pulse response, and carrier transport behaviors lead to compact models of RS mechanisms and energy band diagrams in order to aid the development of computer-aided design for ultralarge-v scale integration. This chapter presents a comprehensive investigation of SiOx-based RS characteristics and mechanisms for the post-CMOS device era.

Reusable fast opening switch

DOEpatents

Van Devender, J.P.; Emin, D.

1983-12-21

A reusable fast opening switch for transferring energy, in the form of a high power pulse, from an electromagnetic storage device such as an inductor into a load. The switch is efficient, compact, fast and reusable. The switch comprises a ferromagnetic semiconductor which undergoes a fast transition between conductive and metallic states at a critical temperature and which undergoes the transition without a phase change in its crystal structure. A semiconductor such as europium rich europhous oxide, which undergoes a conductor to insulator transition when it is joule heated from its conductor state, can be used to form the switch.

Reusable fast opening switch

DOEpatents

Van Devender, John P.; Emin, David

1986-01-01

A reusable fast opening switch for transferring energy, in the form of a high power pulse, from an electromagnetic storage device such as an inductor into a load. The switch is efficient, compact, fast and reusable. The switch comprises a ferromagnetic semiconductor which undergoes a fast transition between conductive and insulating states at a critical temperature and which undergoes the transition without a phase change in its crystal structure. A semiconductor such as europium rich europhous oxide, which undergoes a conductor to insulator transition when it is joule heated from its conductor state, can be used to form the switch.

Materials sciences research. [research facilities, research projects, and technical reports of materials tests

NASA Technical Reports Server (NTRS)

1973-01-01

Research projects involving materials research conducted by various international test facilities are reported. Much of the materials research is classified in the following areas: (1) acousto-optic, acousto-electric, and ultrasonic research, (2) research for elucidating transport phenomena in well characterized oxides, (3) research in semiconductor materials and semiconductor devices, (4) the study of interfaces and interfacial phenomena, and (5) materials research relevant to natural resources. Descriptions of the individual research programs are listed alphabetically by the name of the author and show all personnel involved, resulting publications, and associated meeting speeches.

In-situ integrated processing and characterization of thin films of high temperature superconductors, dielectrics and semiconductors by MOCVD

NASA Technical Reports Server (NTRS)

Singh, R.; Sinha, S.; Hsu, N. J.; Thakur, R. P. S.; Chou, P.; Kumar, A.; Narayan, J.

1990-01-01

In this strategy of depositing the basic building blocks of superconductors, semiconductors, and dielectric having common elements, researchers deposited superconducting films of Y-Ba-Cu-O, semiconductor films of Cu2O, and dielectric films of BaF2 and Y2O3 by metal oxide chemical vapor deposition (MOCVD). By switching source materials entering the chamber, and by using direct writting capability, complex device structures like three-terminal hybrid semiconductors/superconductors transistors can be fabricated. The Y-Ba-Cu-O superconducting thin films on BaF2/YSZ substrates show a T(sub c) of 80 K and are textured with most of the grains having their c-axis or a-axis perpendicular to the substrate. Electrical characteristics as well as structural characteristics of superconductors and related materials obtained by x-ray defraction, electron microscopy, and energy dispersive x-ray analysis are discussed.

In-situ integrated processing and characterization of thin films of high temperature superconductors, dielectrics and semiconductors by MOCVD

NASA Technical Reports Server (NTRS)

Singh, R.; Sinha, S.; Hsu, N. J.; Thakur, R. P. S.; Chou, P.; Kumar, A.; Narayan, J.

1991-01-01

In this strategy of depositing the basic building blocks of superconductors, semiconductors, and dielectrics having common elements, researchers deposited superconducting films of Y-Ba-Cu-O, semiconductor films of Cu2O, and dielectric films of BaF2 and Y2O3 by metal oxide chemical vapor deposition (MOCVD). By switching source materials entering the chamber, and by using direct writing capability, complex device structures like three terminal hybrid semiconductor/superconductor transistors can be fabricated. The Y-Ba-Cu-O superconducting thin films on BaF2/YSZ substrates show a T(sub c) of 80 K and are textured with most of the grains having their c-axis or a-axis perpendicular to the substrate. Electrical characteristics as well as structural characteristics of superconductors and related materials obtained by x-ray deffraction, electron microscopy, and energy dispersive x-ray analysis are discussed.

Metal oxide electrocatalysts for alternative energy technologies

NASA Astrophysics Data System (ADS)

Pacquette, Adele Lawren

This dissertation focuses on the development of metal oxide electrocatalysts with varying applications for alternative energy technologies. Interest in utilizing clean, renewable and sustainable sources of energy for powering the planet in the future has received much attention. This will address the growing concern of the need to reduce our dependence on fossil fuels. The facile synthesis of metal oxides from earth abundant metals was explored in this work. The electrocatalysts can be incorporated into photoelectrochemical devices, fuel cells, and other energy storage devices. The first section addresses the utilization of semiconductors that can harness solar energy for water splitting to generate hydrogen. An oxysulfide was studied in order to combine the advantageous properties of the stability of metal oxides and the visible light absorbance of metal chalcogenides. Bi 2O2S was synthesized under facile hydrothermal conditions. The band gap of Bi2O2S was smaller than that of its oxide counterpart, Bi2O3. Light absorption by Bi 2O2S was extended to the visible region (>600 nm) in comparison to Bi2O3. The formation of a composite with In 2O3 was formed in order to create a UV irradiation protective coating of the Bi2O2S. The Bi2O2S/In 2O3 composite coupled with a dye CrTPP(Cl) and cocatalysts Pt and Co3O4 was utilized for water splitting under light irradiation to generate hydrogen and oxygen. The second section focuses on improving the stability and light absorption of semiconductors by changing the shapes and morphologies. One of the limitations of semiconductor materials is that recombination of electron-hole pairs occur within the bulk of the materials instead of migration to the surface. Three-dimensional shapes, such as nanorods, can prevent this recombination in comparison to spherical particles. Hierarchical structures, such as dendrites, cubes, and multipods, were synthesized under hydrothermal conditions, in order to reduce recombination and improve photocatalytic activity. Another disadvantageous property of semiconductors is that photocorrosion of metal chalcogenides such as CdS occurs. In an attempt to prevent this, these materials were coated with more stable oxides such as Cu2O and TiO2. The photocatalytic activity of these CdS multipods protected by the stable oxides was enhanced in comparison to CdS particles. The third section describes the synthesis and the use of mixed metal oxides for alcohol oxidation. Presently, Pt is the most active and efficient metal catalyst for alcohol oxidation in fuel cells. It is necessary to develop cheaper, earth abundant metals that can replace Pt. Mixed metal oxides based on Mo-V-(Te,Nb)-O were synthesized under hydrothermal conditions. These materials were incorporated into an electrochemical cell and used to oxidize cyclohexanol. At low temperatures of 60°C, cyclohexanol was converted to cyclohexanone, cyclohexene, and adipic acid on Mo-V-O, Mo-V-Te-O, and Mo-V-Te-Nb-O respectively. The present work showed that these interesting materials might potentially be utilized as a catalyst in complex alcohol fuel cell technologies. In the final section, the electrochemical actuation in conducting polymers is studied. Conducting polymers, such as polypyrrole (PPy), and polythiophene (PTh), are often incorporated into actuators, sensors, and energy storage devices such as supercapacitors. The mechanism of the actuation in these polymers due to the insertion/removal of ions was studied. Electrochemical quartz crystal microbalance (EQCM) studies and in situ electrochemical stress measurements were the techniques used to study and to understand the observed actuation mechanism. The bilayer polypyrrole/polythiophene (PPy PTh) polymer film showed potential for enhancing the actuation and capacitance in energy storage devices.

Band alignments in Fe/graphene/Si(001) junctions studied by x-ray photoemission spectroscopy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Le Breton, J.-C., E-mail: jean-christophe.lebreton@univ-rennes1.fr; Tricot, S.; Delhaye, G.

2016-08-01

The control of tunnel contact resistance is of primary importance for semiconductor-based spintronic devices. This control is hardly achieved with conventional oxide-based tunnel barriers due to deposition-induced interface states. Manipulation of single 2D atomic crystals (such as graphene sheets) weakly interacting with their substrate might represent an alternative and efficient way to design new heterostructures for a variety of different purposes including spin injection into semiconductors. In the present paper, we study by x-ray photoemission spectroscopy the band alignments and interface chemistry of iron–graphene-hydrogenated passivated silicon (001) surfaces for a low and a high n-doping concentration. We find that themore » hydrogen passivation of the Si(001) surface remains efficient even with a graphene sheet on the Si(001) surface. For both doping concentrations, the semiconductor is close to flat-band conditions which indicates that the Fermi level is unpinned on the semiconductor side of the Graphene/Si(001):H interface. When iron is deposited on the graphene/Si(001):H structures, the Schottky barrier height remains mainly unaffected by the metallic overlayer with a very low barrier height for electrons, a sought-after property in semiconductor based spintronic devices. Finally, we demonstrate that the graphene layer intercalated between the metal and semiconductor also serves as a protection against iron-silicide formation even at elevated temperatures preventing from the formation of a Si-based magnetic dead layer.« less

Band alignments in Fe/graphene/Si(001) junctions studied by x-ray photoemission spectroscopy

NASA Astrophysics Data System (ADS)

Le Breton, J.-C.; Tricot, S.; Delhaye, G.; Lépine, B.; Turban, P.; Schieffer, P.

2016-08-01

The control of tunnel contact resistance is of primary importance for semiconductor-based spintronic devices. This control is hardly achieved with conventional oxide-based tunnel barriers due to deposition-induced interface states. Manipulation of single 2D atomic crystals (such as graphene sheets) weakly interacting with their substrate might represent an alternative and efficient way to design new heterostructures for a variety of different purposes including spin injection into semiconductors. In the present paper, we study by x-ray photoemission spectroscopy the band alignments and interface chemistry of iron-graphene-hydrogenated passivated silicon (001) surfaces for a low and a high n-doping concentration. We find that the hydrogen passivation of the Si(001) surface remains efficient even with a graphene sheet on the Si(001) surface. For both doping concentrations, the semiconductor is close to flat-band conditions which indicates that the Fermi level is unpinned on the semiconductor side of the Graphene/Si(001):H interface. When iron is deposited on the graphene/Si(001):H structures, the Schottky barrier height remains mainly unaffected by the metallic overlayer with a very low barrier height for electrons, a sought-after property in semiconductor based spintronic devices. Finally, we demonstrate that the graphene layer intercalated between the metal and semiconductor also serves as a protection against iron-silicide formation even at elevated temperatures preventing from the formation of a Si-based magnetic dead layer.

Graphene field-effect devices

NASA Astrophysics Data System (ADS)

Echtermeyer, T. J.; Lemme, M. C.; Bolten, J.; Baus, M.; Ramsteiner, M.; Kurz, H.

2007-09-01

In this article, graphene is investigated with respect to its electronic properties when introduced into field effect devices (FED). With the exception of manual graphene deposition, conventional top-down CMOS-compatible processes are applied. Few and monolayer graphene sheets are characterized by scanning electron microscopy, atomic force microscopy and Raman spectroscopy. The electrical properties of monolayer graphene sandwiched between two silicon dioxide films are studied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from double-gated Graphene-FEDs and silicon metal-oxide-semiconductor field-effect-transistors (MOSFETs).

Study of the Physics of Insulating Films as Related to the Reliability of Metal-Oxide-Semiconductor (MOS) Devices

DTIC Science & Technology

1982-09-01

the critical reading of this manuscript by D.R. Young and M.H. Brodsky, the technical assistance of F.L. Pesavento , and the device fabrication by the...of F. L. Pesavento and J. A. Tornello IBM - Thomas J. Watson Research Center Yorktown Heights, New York ABSTRACT Both photon-assisted-tunneling and...to acknowledge J. A. Tornello for help with the sample preparation, and S. K. Lai and F. L. Pesavento for help with the internal photoemission

Study of the Physics of Insulating Films as Related to the Reliability of Metal-Oxide Semiconductor Devices

DTIC Science & Technology

1980-11-01

materials work and sample preparation of D.W. Dong; the technical assistance of F.L. Pesavento and J.A. Calise; the assistance in device fabrication...FILMS D.J. DiMaria R. Ghez D.W. Dong I.B.M. Thomas J. Watson Research Center Yorktown Heights, New York 10598 Technical Assistance of F.L. Pesavento and... Pesavento and J.A. Calise; the assistance with gate metallizations by the Silicon Facility and Central Scientific Services at the T.J. Watson

InxGa1-xSb Channel p-Metal-Oxide-Semiconductor Field Effect Transistors: Effect of Strain and Heterostructure Design

DTIC Science & Technology

2011-07-06

biaxial compressive strain is known to split the light- and heavy-hole bands, reducing the interband scattering and causing the light hole band to move up...and heterostructure design are presented. In Section V, we use temperature- dependent measurements and pulsed I-V measurements to analyze the results...minimal in our devices. The temperature dependence of hole mobility was stud- ied for both the surface and buried channel devices, as plot- ted in Fig

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

NASA Technical Reports Server (NTRS)

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

Facet-Selective Epitaxy of Compound Semiconductors on Faceted Silicon Nanowires.

PubMed

Mankin, Max N; Day, Robert W; Gao, Ruixuan; No, You-Shin; Kim, Sun-Kyung; McClelland, Arthur A; Bell, David C; Park, Hong-Gyu; Lieber, Charles M

2015-07-08

Integration of compound semiconductors with silicon (Si) has been a long-standing goal for the semiconductor industry, as direct band gap compound semiconductors offer, for example, attractive photonic properties not possible with Si devices. However, mismatches in lattice constant, thermal expansion coefficient, and polarity between Si and compound semiconductors render growth of epitaxial heterostructures challenging. Nanowires (NWs) are a promising platform for the integration of Si and compound semiconductors since their limited surface area can alleviate such material mismatch issues. Here, we demonstrate facet-selective growth of cadmium sulfide (CdS) on Si NWs. Aberration-corrected transmission electron microscopy analysis shows that crystalline CdS is grown epitaxially on the {111} and {110} surface facets of the Si NWs but that the Si{113} facets remain bare. Further analysis of CdS on Si NWs grown at higher deposition rates to yield a conformal shell reveals a thin oxide layer on the Si{113} facet. This observation and control experiments suggest that facet-selective growth is enabled by the formation of an oxide, which prevents subsequent shell growth on the Si{113} NW facets. Further studies of facet-selective epitaxial growth of CdS shells on micro-to-mesoscale wires, which allows tuning of the lateral width of the compound semiconductor layer without lithographic patterning, and InP shell growth on Si NWs demonstrate the generality of our growth technique. In addition, photoluminescence imaging and spectroscopy show that the epitaxial shells display strong and clean band edge emission, confirming their high photonic quality, and thus suggesting that facet-selective epitaxy on NW substrates represents a promising route to integration of compound semiconductors on Si.

Generic process for preparing a crystalline oxide upon a group IV semiconductor substrate

DOEpatents

McKee, Rodney A.; Walker, Frederick J.; Chisholm, Matthew F.

2000-01-01

A process for growing a crystalline oxide epitaxially upon the surface of a Group IV semiconductor, as well as a structure constructed by the process, is described. The semiconductor can be germanium or silicon, and the crystalline oxide can generally be represented by the formula (AO).sub.n (A'BO.sub.3).sub.m in which "n" and "m" are non-negative integer repeats of planes of the alkaline earth oxides or the alkaline earth-containing perovskite oxides. With atomic level control of interfacial thermodynamics in a multicomponent semiconductor/oxide system, a highly perfect interface between a semiconductor and a crystalline oxide can be obtained.

Hole injection and dielectric breakdown in 6H-SiC and 4H-SiC metal-oxide-semiconductor structures during substrate electron injection via Fowler-Nordheim tunneling

NASA Astrophysics Data System (ADS)

Samanta, Piyas; Mandal, Krishna C.

2015-12-01

Hole injection into silicon dioxide (SiO2) films (8-40 nm thick) is investigated for the first time during substrate electron injection via Fowler-Nordheim (FN) tunneling in n-type 4H- and 6H-SiC (silicon carbide) based metal-oxide-semiconductor (MOS) structures at a wide range of temperatures (T) between 298 and 598 K and oxide electric fields Eox from 6 to 10 MV/cm. Holes are generated in heavily doped n-type polycrystalline silicon (n+ -polySi) gate serving as the anode as well as in the bulk silicon dioxide (SiO2) film via hot-electron initiated band-to-band ionization (BTBI). In absence of oxide trapped charges, it is shown that at a given temperature, the hole injection rates from either of the above two mechanisms are higher in n-4H-SiC MOS devices than those in n-6H-SiC MOS structures when compared at a given Eox and SiO2 thickness (tox). On the other hand, relative to n-4H-SiC devices, n-6H-SiC structures exhibit higher hole injection rates for a given tox during substrate electron injection at a given FN current density je,FN throughout the temperature range studied here. These two observations clearly reveal that the substrate material (n-6H-SiC and n-4H-SiC) dependencies on time-to-breakdown (tBD) or injected charge (electron) to breakdown (QBD) of the SiO2 film depend on the mode of FN injections (constant field/voltage and current) from the substrate which is further verified from the rigorous device simulation as well.

Simulation study of ballistic spin-MOSFET devices with ferromagnetic channels based on some Heusler and oxide compounds

NASA Astrophysics Data System (ADS)

Graziosi, Patrizio; Neophytou, Neophytos

2018-02-01

Newly emerged materials from the family of Heuslers and complex oxides exhibit finite bandgaps and ferromagnetic behavior with Curie temperatures much higher than even room temperature. In this work, using the semiclassical top-of-the-barrier FET model, we explore the operation of a spin-MOSFET that utilizes such ferromagnetic semiconductors as channel materials, in addition to ferromagnetic source/drain contacts. Such a device could retain the spin polarization of injected electrons in the channel, the loss of which limits the operation of traditional spin transistors with non-ferromagnetic channels. We examine the operation of four material systems that are currently considered some of the most prominent known ferromagnetic semiconductors: three Heusler-type alloys (Mn2CoAl, CrVZrAl, and CoVZrAl) and one from the oxide family (NiFe2O4). We describe their band structures by using data from DFT (Density Functional Theory) calculations. We investigate under which conditions high spin polarization and significant ION/IOFF ratio, two essential requirements for the spin-MOSFET operation, are both achieved. We show that these particular Heusler channels, in their bulk form, do not have adequate bandgap to provide high ION/IOFF ratios and have small magnetoconductance compared to state-of-the-art devices. However, with confinement into ultra-narrow sizes down to a few nanometers, and by engineering their spin dependent contact resistances, they could prove promising channel materials for the realization of spin-MOSFET transistor devices that offer combined logic and memory functionalities. Although the main compounds of interest in this paper are Mn2CoAl, CrVZrAl, CoVZrAl, and NiFe2O4 alone, we expect that the insight we provide is relevant to other classes of such materials as well.

Multi-Dimensional Quantum Tunneling and Transport Using the Density-Gradient Model

NASA Technical Reports Server (NTRS)

Biegel, Bryan A.; Yu, Zhi-Ping; Ancona, Mario; Rafferty, Conor; Saini, Subhash (Technical Monitor)

1999-01-01

We show that quantum effects are likely to significantly degrade the performance of MOSFETs (metal oxide semiconductor field effect transistor) as these devices are scaled below 100 nm channel length and 2 nm oxide thickness over the next decade. A general and computationally efficient electronic device model including quantum effects would allow us to monitor and mitigate these effects. Full quantum models are too expensive in multi-dimensions. Using a general but efficient PDE solver called PROPHET, we implemented the density-gradient (DG) quantum correction to the industry-dominant classical drift-diffusion (DD) model. The DG model efficiently includes quantum carrier profile smoothing and tunneling in multi-dimensions and for any electronic device structure. We show that the DG model reduces DD model error from as much as 50% down to a few percent in comparison to thin oxide MOS capacitance measurements. We also show the first DG simulations of gate oxide tunneling and transverse current flow in ultra-scaled MOSFETs. The advantages of rapid model implementation using the PDE solver approach will be demonstrated, as well as the applicability of the DG model to any electronic device structure.

Trap densities and transport properties of pentacene metal-oxide-semiconductor transistors: II—Numerical modeling of dc characteristics

NASA Astrophysics Data System (ADS)

Basile, A. F.; Kyndiah, A.; Biscarini, F.; Fraboni, B.

2014-06-01

A numerical procedure to calculate the drain-current (ID) vs. gate-voltage (VG) characteristics from numerical solutions of the Poisson equation for organic Thin-Film Transistors (TFTs) is presented. Polaron transport is modeled as two-dimensional charge transport in a semiconductor having free-carrier density of states proportional to the density of molecules and traps with energy equal to the polaron-hopping barrier. The simulated ID-VG curves are proportional to the product of the density of free carriers, calculated as a function of VG, and the intrinsic mobility, assumed to be a constant independent of temperature. The presence of traps in the oxide was also taken into account in the model, which was applied to a TFT made with six monolayers of pentacene grown on an oxide substrate. The polaron-hopping barrier determines the temperature dependence of the simulated ID-VG curves, trapping in the oxide is responsible for current reduction at high bias and the slope of the characteristics near threshold is related to the metal-semiconductor work-function difference. The values of the model parameters yielding the best match between calculations and experiments are consistent with previous experimental results and theoretical predictions. Therefore, this model enables to extract both physical and technological properties of thin-film devices from the temperature-dependent dc characteristics.

Charge-flow structures as polymeric early-warning fire alarm devices. M.S. Thesis; [metal oxide semiconductors

NASA Technical Reports Server (NTRS)

Sechen, C. M.; Senturia, S. D.

1977-01-01

The charge-flow transistor (CFT) and its applications for fire detection and gas sensing were investigated. The utility of various thin film polymers as possible sensing materials was determined. One polymer, PAPA, showed promise as a relative humidity sensor; two others, PFI and PSB, were found to be particularly suitable for fire detection. The behavior of the charge-flow capacitor, which is basically a parallel-plate capacitor with a polymer-filled gap in the metallic tip electrode, was successfully modeled as an RC transmission line. Prototype charge-flow transistors were fabricated and tested. The effective threshold voltage of this metal oxide semiconductor was found to be dependent on whether surface or bulk conduction in the thin film was dominant. Fire tests with a PFI-coated CFT indicate good sensitivity to smouldering fires.

Improved Hot Carrier Reliability Characteristics of Metal Oxide Semiconductor Field Effect Transistors with High-k Gate Dielectric by Using High Pressure Deuterium Post Metallization Annealing

NASA Astrophysics Data System (ADS)

Park, Hokyung; Choi, Rino; Lee, Byoung Hun; Hwang, Hyunsang

2007-09-01

High pressure deuterium annealing on the hot carrier reliability characteristics of HfSiO metal oxide semiconductor field effect transistor (MOSFET) was investigated. Comparing with the conventional forming gas (H2/Ar=10%/96%, 480 °C, 30 min) annealed sample, MOSFET annealed in 5 atm pure deuterium ambient at 400 °C showed the improvement of linear drain current, reduction of interface trap density, and improvement of the hot carrier reliability characteristics. These improvements can be attributed to the effective passivation of the interface trap site after high pressure annealing and heavy mass effect of deuterium. These results indicate that high pressure pure deuterium annealing can be a promising process for improving device performance as well as hot carrier reliability, together.

Single InAs/GaSb nanowire low-power CMOS inverter.

PubMed

Dey, Anil W; Svensson, Johannes; Borg, B Mattias; Ek, Martin; Wernersson, Lars-Erik

2012-11-14

III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

Biodegradable elastomers and silicon nanomembranes/nanoribbons for stretchable, transient electronics, and biosensors.

PubMed

Hwang, Suk-Won; Lee, Chi Hwan; Cheng, Huanyu; Jeong, Jae-Woong; Kang, Seung-Kyun; Kim, Jae-Hwan; Shin, Jiho; Yang, Jian; Liu, Zhuangjian; Ameer, Guillermo A; Huang, Yonggang; Rogers, John A

2015-05-13

Transient electronics represents an emerging class of technology that exploits materials and/or device constructs that are capable of physically disappearing or disintegrating in a controlled manner at programmed rates or times. Inorganic semiconductor nanomaterials such as silicon nanomembranes/nanoribbons provide attractive choices for active elements in transistors, diodes and other essential components of overall systems that dissolve completely by hydrolysis in biofluids or groundwater. We describe here materials, mechanics, and design layouts to achieve this type of technology in stretchable configurations with biodegradable elastomers for substrate/encapsulation layers. Experimental and theoretical results illuminate the mechanical properties under large strain deformation. Circuit characterization of complementary metal-oxide-semiconductor inverters and individual transistors under various levels of applied loads validates the design strategies. Examples of biosensors demonstrate possibilities for stretchable, transient devices in biomedical applications.

Electronic Properties and Device Applications of III-V Compound Semiconductor Native Oxides

DTIC Science & Technology

2006-03-02

MRD X-ray diffractometer with CuKa as the radiation source. The doping level in GaAs was meassured by electrochemical voltage (ECV) using an Accent... hard to prevent the gate metal from overlapping the mesa edge thus creating a parasitic leakage path to the channel42. To reduce the gate leakage

Study of digital charge coupled devices

NASA Technical Reports Server (NTRS)

Wilson, D. D.; Young, V. F.

1980-01-01

Charge coupled devices represent unique usage of the metal oxide semiconductor concept. These devices can sample an AC signal at the input, transfer charge proportional to this signal through the CCD shift register and then provide an output of the same frequency and shape as the input. The delay time between input and output is controlled by the CCD operating frequency and the number of stages in the shift resistor. This work is a reliability evaluation of the buried channel and surface channel CCD technologies. The constructions are analyzed, failure modes are described, and test results are reported.

Computer-aided engineering of semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

Meindl, J. D.; Dutton, R. W.; Gibbons, J. F.; Helms, C. R.; Plummer, J. D.; Tiller, W. A.; Ho, C. P.; Saraswat, K. C.; Deal, B. E.; Kamins, T. I.

1980-07-01

Economical procurement of small quantities of high performance custom integrated circuits for military systems is impeded by inadequate process, device and circuit models that handicap low cost computer aided design. The principal objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer-aided design of custom large-scale integrated circuits. The basic areas under investigation are (1) thermal oxidation, (2) ion implantation and diffusion, (3) chemical vapor deposition of silicon and refractory metal silicides, (4) device simulation and analytic measurements. This report discusses the fourth year of the program.

Heterojunction oxide thin-film transistors with unprecedented electron mobility grown from solution.

PubMed

Faber, Hendrik; Das, Satyajit; Lin, Yen-Hung; Pliatsikas, Nikos; Zhao, Kui; Kehagias, Thomas; Dimitrakopulos, George; Amassian, Aram; Patsalas, Panos A; Anthopoulos, Thomas D

2017-03-01

Thin-film transistors made of solution-processed metal oxide semiconductors hold great promise for application in the emerging sector of large-area electronics. However, further advancement of the technology is hindered by limitations associated with the extrinsic electron transport properties of the often defect-prone oxides. We overcome this limitation by replacing the single-layer semiconductor channel with a low-dimensional, solution-grown In 2 O 3 /ZnO heterojunction. We find that In 2 O 3 /ZnO transistors exhibit band-like electron transport, with mobility values significantly higher than single-layer In 2 O 3 and ZnO devices by a factor of 2 to 100. This marked improvement is shown to originate from the presence of free electrons confined on the plane of the atomically sharp heterointerface induced by the large conduction band offset between In 2 O 3 and ZnO. Our finding underscores engineering of solution-grown metal oxide heterointerfaces as an alternative strategy to thin-film transistor development and has the potential for widespread technological applications.

Heterojunction oxide thin-film transistors with unprecedented electron mobility grown from solution

PubMed Central

Faber, Hendrik; Das, Satyajit; Lin, Yen-Hung; Pliatsikas, Nikos; Zhao, Kui; Kehagias, Thomas; Dimitrakopulos, George; Amassian, Aram; Patsalas, Panos A.; Anthopoulos, Thomas D.

2017-01-01

Thin-film transistors made of solution-processed metal oxide semiconductors hold great promise for application in the emerging sector of large-area electronics. However, further advancement of the technology is hindered by limitations associated with the extrinsic electron transport properties of the often defect-prone oxides. We overcome this limitation by replacing the single-layer semiconductor channel with a low-dimensional, solution-grown In2O3/ZnO heterojunction. We find that In2O3/ZnO transistors exhibit band-like electron transport, with mobility values significantly higher than single-layer In2O3 and ZnO devices by a factor of 2 to 100. This marked improvement is shown to originate from the presence of free electrons confined on the plane of the atomically sharp heterointerface induced by the large conduction band offset between In2O3 and ZnO. Our finding underscores engineering of solution-grown metal oxide heterointerfaces as an alternative strategy to thin-film transistor development and has the potential for widespread technological applications. PMID:28435867

AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors using Sc2O3 as the gate oxide and surface passivation

NASA Astrophysics Data System (ADS)

Mehandru, R.; Luo, B.; Kim, J.; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R.; Gillespie, J.; Jenkins, T.; Sewell, J.; Via, D.; Crespo, A.

2003-04-01

We demonstrated that Sc2O3 thin films deposited by plasma-assisted molecular-beam epitaxy can be used simultaneously as a gate oxide and as a surface passivation layer on AlGaN/GaN high electron mobility transistors (HEMTs). The maximum drain source current, IDS, reaches a value of over 0.8 A/mm and is ˜40% higher on Sc2O3/AlGaN/GaN transistors relative to conventional HEMTs fabricated on the same wafer. The metal-oxide-semiconductor HEMTs (MOS-HEMTs) threshold voltage is in good agreement with the theoretical value, indicating that Sc2O3 retains a low surface state density on the AlGaN/GaN structures and effectively eliminates the collapse in drain current seen in unpassivated devices. The MOS-HEMTs can be modulated to +6 V of gate voltage. In particular, Sc2O3 is a very promising candidate as a gate dielectric and surface passivant because it is more stable on GaN than is MgO.

Improved interfacial and electrical properties of GaAs metal-oxide-semiconductor capacitors with HfTiON as gate dielectric and TaON as passivation interlayer

NASA Astrophysics Data System (ADS)

Wang, L. S.; Xu, J. P.; Zhu, S. Y.; Huang, Y.; Lai, P. T.

2013-08-01

The interfacial and electrical properties of sputtered HfTiON on sulfur-passivated GaAs with or without TaON as interfacial passivation layer (IPL) are investigated. Experimental results show that the GaAs metal-oxide-semiconductor capacitor with HfTiON/TaON stacked gate dielectric annealed at 600 °C exhibits low interface-state density (1.0 × 1012 cm-2 eV-1), small gate leakage current (7.3 × 10-5 A cm-2 at Vg = Vfb + 1 V), small capacitance equivalent thickness (1.65 nm), and large equivalent dielectric constant (26.2). The involved mechanisms lie in the fact that the TaON IPL can effectively block the diffusions of Hf, Ti, and O towards GaAs surface and suppress the formation of interfacial As-As bonds, Ga-/As-oxides, thus unpinning the Femi level at the TaON/GaAs interface and improving the interface quality and electrical properties of the device.

Quasi-Two-Dimensional h-BN/β-Ga2O3 Heterostructure Metal-Insulator-Semiconductor Field-Effect Transistor.

PubMed

Kim, Janghyuk; Mastro, Michael A; Tadjer, Marko J; Kim, Jihyun

2017-06-28

β-gallium oxide (β-Ga 2 O 3 ) and hexagonal boron nitride (h-BN) heterostructure-based quasi-two-dimensional metal-insulator-semiconductor field-effect transistors (MISFETs) were demonstrated by integrating mechanical exfoliation of (quasi)-two-dimensional materials with a dry transfer process, wherein nanothin flakes of β-Ga 2 O 3 and h-BN were utilized as the channel and gate dielectric, respectively, of the MISFET. The h-BN dielectric, which has an extraordinarily flat and clean surface, provides a minimal density of charged impurities on the interface between β-Ga 2 O 3 and h-BN, resulting in superior device performances (maximum transconductance, on/off ratio, subthreshold swing, and threshold voltage) compared to those of the conventional back-gated configurations. Also, double-gating of the fabricated device was demonstrated by biasing both top and bottom gates, achieving the modulation of the threshold voltage. This heterostructured wide-band-gap nanodevice shows a new route toward stable and high-power nanoelectronic devices.

A self-assembled microbonded germanium/silicon heterojunction photodiode for 25 Gb/s high-speed optical interconnects

PubMed Central

Tseng, Chih-Kuo; Chen, Wei-Ting; Chen, Ku-Hung; Liu, Han-Din; Kang, Yimin; Na, Neil; Lee, Ming-Chang M.

2013-01-01

A novel technique using surface tension to locally bond germanium (Ge) on silicon (Si) is presented for fabricating high performance Ge/Si photodiodes. Surface tension is a cohesive force among liquid molecules that tends to bring contiguous objects in contact to maintain a minimum surface energy. We take advantage of this phenomenon to fabricate a heterojunction optoelectronic device where the lattice constants of joined semiconductors are different. A high-speed Ge/Si heterojunction waveguide photodiode is presented by microbonding a beam-shaped Ge, first grown by rapid-melt-growth (RMG) method, on top of a Si waveguide via surface tension. Excellent device performances such as an operating bandwidth of 17 GHz and a responsivity of 0.66 and 0.70 A/W at the reverse bias of −4 and −6 V, respectively, are demonstrated. This technique can be simply implemented via modern complementary metal-oxide-semiconductor (CMOS) fabrication technologies for integrating Ge on Si devices. PMID:24232956

Silicon and germanium nanowire electronics: physics of conventional and unconventional transistors

NASA Astrophysics Data System (ADS)

Weber, Walter M.; Mikolajick, Thomas

2017-06-01

Research in the field of electronics of 1D group-IV semiconductor structures has attracted increasing attention over the past 15 years. The exceptional combination of the unique 1D electronic transport properties with the mature material know-how of highly integrated silicon and germanium technology holds the promise of enhancing state-of-the-art electronics. In addition of providing conduction channels that can bring conventional field effect transistors to the uttermost scaling limits, the physics of 1D group IV nanowires endows new device principles. Such unconventional silicon and germanium nanowire devices are contenders for beyond complementary metal oxide semiconductor (CMOS) computing by virtue of their distinct switching behavior and higher expressive value. This review conveys to the reader a systematic recapitulation and analysis of the physics of silicon and germanium nanowires and the most relevant CMOS and CMOS-like devices built from silicon and germanium nanowires, including inversion mode, junctionless, steep-slope, quantum well and reconfigurable transistors.

Robust, functional nanocrystal solids by infilling with atomic layer deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Yao; Gibbs, Markelle; Perkins, Craig L.

2011-12-14

Thin films of colloidal semiconductor nanocrystals (NCs) are inherently metatstable materials prone to oxidative and photothermal degradation driven by their large surface-to-volume ratios and high surface energies. The fabrication of practical electronic devices based on NC solids hinges on preventing oxidation, surface diffusion, ripening, sintering, and other unwanted physicochemical changes that can plague these materials. Here we use low-temperature atomic layer deposition (ALD) to infill conductive PbSe NC solids with metal oxides to produce inorganic nanocomposites in which the NCs are locked in place and protected against oxidative and photothermal damage. Infilling NC field-effect transistors and solar cells with amorphousmore » alumina yields devices that operate with enhanced and stable performance for at least months in air. Furthermore, ALD infilling with ZnO lowers the height of the inter-NC tunnel barrier for electron transport, yielding PbSe NC films with electron mobilities of 1 cm² V -1 s -1. Our ALD technique is a versatile means to fabricate robust NC solids for optoelectronic devices.« less

Nanotechnology Based Green Energy Conversion Devices with Multifunctional Materials at Low Temperatures.

PubMed

Lu, Yuzheng; Afzal, Muhammad; Zhu, Bin; Wang, Baoyuan; Wang, Jun; Xia, Chen

2017-07-10

Nanocomposites (integrating the nano and composite technologies) for advanced fuel cells (NANOCOFC) demonstrate the great potential to reduce the operational temperature of solid oxide fuel cell (SOFC) significantly in the low temperature (LT) range 300-600ºC. NANOCOFC has offered the development of multi-functional materials composed of semiconductor and ionic materials to meet the requirements of low temperature solid oxide fuel cell (LTSOFC) and green energy conversion devices with their unique mechanisms. This work reviews the recent developments relevant to the devices and the patents in LTSOFCs from nanotechnology perspectives that reports advances including fabrication methods, material compositions, characterization techniques and cell performances. Finally, the future scope of LTSOFC with nanotechnology and the practical applications are also discussed. Copyright© Bentham Science Publishers; For any queries, please email at epub@benthamscience.org.

Gas-phase synthesis of semiconductor nanocrystals and its applications

NASA Astrophysics Data System (ADS)

Mandal, Rajib

Luminescent nanomaterials is a newly emerging field that provides challenges not only to fundamental research but also to innovative technology in several areas such as electronics, photonics, nanotechnology, display, lighting, biomedical engineering and environmental control. These nanomaterials come in various forms, shapes and comprises of semiconductors, metals, oxides, and inorganic and organic polymers. Most importantly, these luminescent nanomaterials can have different properties owing to their size as compared to their bulk counterparts. Here we describe the use of plasmas in synthesis, modification, and deposition of semiconductor nanomaterials for luminescence applications. Nanocrystalline silicon is widely known as an efficient and tunable optical emitter and is attracting great interest for applications in several areas. To date, however, luminescent silicon nanocrystals (NCs) have been used exclusively in traditional rigid devices. For the field to advance towards new and versatile applications for nanocrystal-based devices, there is a need to investigate whether these NCs can be used in flexible and stretchable devices. We show how the optical and structural/morphological properties of plasma-synthesized silicon nanocrystals (Si NCs) change when they are deposited on stretchable substrates made of polydimethylsiloxane (PDMS). Synthesis of these NCs was performed in a nonthermal, low-pressure gas phase plasma reactor. To our knowledge, this is the first demonstration of direct deposition of NCs onto stretchable substrates. Additionally, in order to prevent oxidation and enhance the luminescence properties, a silicon nitride shell was grown around Si NCs. We have demonstrated surface nitridation of Si NCs in a single step process using non?thermal plasma in several schemes including a novel dual-plasma synthesis/shell growth process. These coated NCs exhibit SiNx shells with composition depending on process parameters. While measurements including photoluminescence (PL), surface analysis, and defect identification indicate the shell is protective against oxidation compared to Si NCs without any shell growth. Gallium Nitride (GaN) is one of the most well-known semiconductor material and the industry standard for fabricating LEDs. The problem is that epitaxial growth of high-quality GaN requires costly substrates (e.g. sapphire), high temperatures, and long processing times. Synthesizing freestanding NCs of GaN, on the other hand, could enable these novel device morphologies, as the NCs could be incorporated into devices without the requirements imposed by epitaxial GaN growth. Synthesis of GaN NCs was performed using a fully gas-phase process. Different sizes of crystalline GaN nanoparticles were produced indicating versatility of this gas-phase process. Elemental analysis using X-ray photoelectron spectroscopy (XPS) indicated a possible nitrogen deficiency in the NCs; addition of secondary plasma for surface treatment indicates improving stoichiometric ratio and points towards a unique method for creating high-quality GaN NCs with ultimate alloying and doping for full-spectrum luminescence.

Locally oxidized silicon surface-plasmon Schottky detector for telecom regime.

PubMed

Goykhman, Ilya; Desiatov, Boris; Khurgin, Jacob; Shappir, Joseph; Levy, Uriel

2011-06-08

We experimentally demonstrate an on-chip nanoscale silicon surface-plasmon Schottky photodetector based on internal photoemission process and operating at telecom wavelengths. The device is fabricated using a self-aligned approach of local-oxidation of silicon (LOCOS) on silicon on insulator substrate, which provides compatibility with standard complementary metal-oxide semiconductor technology and enables the realization of the photodetector and low-loss bus photonic waveguide at the same fabrication step. Additionally, LOCOS technique allows avoiding lateral misalignment between the silicon surface and the metal layer to form a nanoscale Schottky contact. The fabricated devices showed enhanced detection capability for shorter wavelengths that is attributed to increased probability of the internal photoemission process. We found the responsivity of the nanodetector to be 0.25 and 13.3 mA/W for incident optical wavelengths of 1.55 and 1.31 μm, respectively. The presented device can be integrated with other nanophotonic and nanoplasmonic structures for the realization of monolithic opto-electronic circuitry on-chip.

Fabrication of smooth patterned structures of refractory metals, semiconductors, and oxides via template stripping.

PubMed

Park, Jong Hyuk; Nagpal, Prashant; McPeak, Kevin M; Lindquist, Nathan C; Oh, Sang-Hyun; Norris, David J

2013-10-09

The template-stripping method can yield smooth patterned films without surface contamination. However, the process is typically limited to coinage metals such as silver and gold because other materials cannot be readily stripped from silicon templates due to strong adhesion. Herein, we report a more general template-stripping method that is applicable to a larger variety of materials, including refractory metals, semiconductors, and oxides. To address the adhesion issue, we introduce a thin gold layer between the template and the deposited materials. After peeling off the combined film from the template, the gold layer can be selectively removed via wet etching to reveal a smooth patterned structure of the desired material. Further, we demonstrate template-stripped multilayer structures that have potential applications for photovoltaics and solar absorbers. An entire patterned device, which can include a transparent conductor, semiconductor absorber, and back contact, can be fabricated. Since our approach can also produce many copies of the patterned structure with high fidelity by reusing the template, a low-cost and high-throughput process in micro- and nanofabrication is provided that is useful for electronics, plasmonics, and nanophotonics.

pn junctions based on a single transparent perovskite semiconductor BaSnO3

NASA Astrophysics Data System (ADS)

Kim, Hoon Min; Kim, Useong; Park, Chulkwon; Kwon, Hyukwoo; Lee, Woongjae; Kim, Tai Hoon; Kim, Kee Hoon; Char, Kookrin; Mdpl, Department Of Physics; Astronomy Team; Censcmr, Department Of Physics; Astronomy Team

2014-03-01

Successful p doping of transparent oxide semiconductor will further increase its potential, especially in the area of optoelectronic applications. We will report our efforts to dope the BaSnO3 (BSO) with K by pulsed laser deposition. Although the K doped BSO exhibits rather high resistivity at room temperature, its conductivity increases dramatically at higher temperatures. Furthermore, the conductivity decreases when a small amount of oxygen was removed from the film, consistent with the behavior of p type doped oxides. We have fabricated pn junctions by using K doped BSO as a p type and La doped BSO as an n type material. I_V characteristics of these devices show the typical rectifying behavior of pn junctions. We will present the analysis of the junction properties from the temperature dependent measurement of their electrical properties, which shows that the I_V characteristics are consistent with the material parameters such as the carrier concentration, the mobility, and the bandgap. Our demonstration of pn junctions based on a single transparent perovskite semiconductor further enhances the potential of BSO system with high mobility and stability.

In-situ thermal annealing of on-membrane silicon-on-insulator semiconductor-based devices after high gamma dose irradiation.

PubMed

Amor, S; André, N; Kilchytska, V; Tounsi, F; Mezghani, B; Gérard, P; Ali, Z; Udrea, F; Flandre, D; Francis, L A

2017-05-05

In this paper, we investigate the recovery of some semiconductor-based components, such as N/P-type field-effect transistors (FETs) and a complementary metal-oxide-semiconductor (CMOS) inverter, after being exposed to a high total dose of gamma ray radiation. The employed method consists mainly of a rapid, low power and in situ annealing mitigation technique by silicon-on-insulator micro-hotplates. Due to the ionizing effect of the gamma irradiation, the threshold voltages showed an average shift of -580 mV for N-channel transistors, and -360 mV for P-MOSFETs. A 4 min double-cycle annealing of components with a heater temperature up to 465 °C, corresponding to a maximum power of 38 mW, ensured partial recovery but was not sufficient for full recovery. The degradation was completely recovered after the use of a built-in high temperature annealing process, up to 975 °C for 8 min corresponding to a maximum power of 112 mW, which restored the normal operating characteristics for all devices after their irradiation.

Solution-based electrical doping of semiconducting polymer films over a limited depth

NASA Astrophysics Data System (ADS)

Kolesov, Vladimir A.; Fuentes-Hernandez, Canek; Chou, Wen-Fang; Aizawa, Naoya; Larrain, Felipe A.; Wang, Ming; Perrotta, Alberto; Choi, Sangmoo; Graham, Samuel; Bazan, Guillermo C.; Nguyen, Thuc-Quyen; Marder, Seth R.; Kippelen, Bernard

2017-04-01

Solution-based electrical doping protocols may allow more versatility in the design of organic electronic devices; yet, controlling the diffusion of dopants in organic semiconductors and their stability has proven challenging. Here we present a solution-based approach for electrical p-doping of films of donor conjugated organic semiconductors and their blends with acceptors over a limited depth with a decay constant of 10-20 nm by post-process immersion into a polyoxometalate solution (phosphomolybdic acid, PMA) in nitromethane. PMA-doped films show increased electrical conductivity and work function, reduced solubility in the processing solvent, and improved photo-oxidative stability in air. This approach is applicable to a variety of organic semiconductors used in photovoltaics and field-effect transistors. PMA doping over a limited depth of bulk heterojunction polymeric films, in which amine-containing polymers were mixed in the solution used for film formation, enables single-layer organic photovoltaic devices, processed at room temperature, with power conversion efficiencies up to 5.9 +/- 0.2% and stable performance on shelf-lifetime studies at 60 °C for at least 280 h.

In-situ thermal annealing of on-membrane silicon-on-insulator semiconductor-based devices after high gamma dose irradiation

NASA Astrophysics Data System (ADS)

Amor, S.; André, N.; Kilchytska, V.; Tounsi, F.; Mezghani, B.; Gérard, P.; Ali, Z.; Udrea, F.; Flandre, D.; Francis, L. A.

2017-05-01

In this paper, we investigate the recovery of some semiconductor-based components, such as N/P-type field-effect transistors (FETs) and a complementary metal-oxide-semiconductor (CMOS) inverter, after being exposed to a high total dose of gamma ray radiation. The employed method consists mainly of a rapid, low power and in situ annealing mitigation technique by silicon-on-insulator micro-hotplates. Due to the ionizing effect of the gamma irradiation, the threshold voltages showed an average shift of -580 mV for N-channel transistors, and -360 mV for P-MOSFETs. A 4 min double-cycle annealing of components with a heater temperature up to 465 °C, corresponding to a maximum power of 38 mW, ensured partial recovery but was not sufficient for full recovery. The degradation was completely recovered after the use of a built-in high temperature annealing process, up to 975 °C for 8 min corresponding to a maximum power of 112 mW, which restored the normal operating characteristics for all devices after their irradiation.

Neutron, gamma ray and post-irradiation thermal annealing effects on power semiconductor switches

NASA Technical Reports Server (NTRS)

Schwarze, G. E.; Frasca, A. J.

1991-01-01

The effects of neutron and gamma rays on the electrical and switching characteristics of power semiconductor switches must be known and understood by the designer of the power conditioning, control, and transmission subsystem of space nuclear power systems. The SP-100 radiation requirements at 25 m from the nuclear source are a neutron fluence of 10(exp 13) n/sq cm and a gamma dose of 0.5 Mrads. Experimental data showing the effects of neutrons and gamma rays on the performance characteristics of power-type NPN Bipolar Junction Transistors (BJTs), Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), and Static Induction Transistors (SITs) are presented. These three types of devices were tested at radiation levels which met or exceeded the SP-100 requirements. For the SP-100 radiation requirements, the BJTs were found to be most sensitive to neutrons, the MOSFETs were most sensitive to gamma rays, and the SITs were only slightly sensitive to neutrons. Post-irradiation thermal anneals at 300 K and up to 425 K were done on these devices and the effectiveness of these anneals are also discussed.

Thin-film encapsulation of organic electronic devices based on vacuum evaporated lithium fluoride as protective buffer layer

NASA Astrophysics Data System (ADS)

Peng, Yingquan; Ding, Sihan; Wen, Zhanwei; Xu, Sunan; Lv, Wenli; Xu, Ziqiang; Yang, Yuhuan; Wang, Ying; Wei, Yi; Tang, Ying

2017-03-01

Encapsulation is indispensable for organic thin-film electronic devices to ensure reliable operation and long-term stability. For thin-film encapsulating organic electronic devices, insulating polymers and inorganic metal oxides thin films are widely used. However, spin-coating of insulating polymers directly on organic electronic devices may destroy or introduce unwanted impurities in the underlying organic active layers. And also, sputtering of inorganic metal oxides may damage the underlying organic semiconductors. Here, we demonstrated that by utilizing vacuum evaporated lithium fluoride (LiF) as protective buffer layer, spin-coated insulating polymer polyvinyl alcohol (PVA), and sputtered inorganic material Er2O3, can be successfully applied for thin film encapsulation of copper phthalocyanine (CuPc)-based organic diodes. By encapsulating with LiF/PVA/LiF trilayer and LiF/Er2O3 bilayer films, the device lifetime improvements of 10 and 15 times can be achieved. These methods should be applicable for thin-film encapsulation of all kinds of organic electronic devices. Moisture-induced hole trapping, and Al top electrode oxidation are suggest to be the origins of current decay for the LiF/PVA/LiF trilayer and LiF/Er2O3 bilayer films encapsulated devices, respectively.

Light-activated resistance switching in SiOx RRAM devices

NASA Astrophysics Data System (ADS)

Mehonic, A.; Gerard, T.; Kenyon, A. J.

2017-12-01

We report a study of light-activated resistance switching in silicon oxide (SiOx) resistive random access memory (RRAM) devices. Our devices had an indium tin oxide/SiOx/p-Si Metal/Oxide/Semiconductor structure, with resistance switching taking place in a 35 nm thick SiOx layer. The optical activity of the devices was investigated by characterising them in a range of voltage and light conditions. Devices respond to illumination at wavelengths in the range of 410-650 nm but are unresponsive at 1152 nm, suggesting that photons are absorbed by the bottom p-type silicon electrode and that generation of free carriers underpins optical activity. Applied light causes charging of devices in the high resistance state (HRS), photocurrent in the low resistance state (LRS), and lowering of the set voltage (required to go from the HRS to LRS) and can be used in conjunction with a voltage bias to trigger switching from the HRS to the LRS. We demonstrate negative correlation between set voltage and applied laser power using a 632.8 nm laser source. We propose that, under illumination, increased electron injection and hence a higher rate of creation of Frenkel pairs in the oxide—precursors for the formation of conductive oxygen vacancy filaments—reduce switching voltages. Our results open up the possibility of light-triggered RRAM devices.

Oxide-based thin film transistors for flexible electronics

NASA Astrophysics Data System (ADS)

He, Yongli; Wang, Xiangyu; Gao, Ya; Hou, Yahui; Wan, Qing

2018-01-01

The continuous progress in thin film materials and devices has greatly promoted the development in the field of flexible electronics. As one of the most common thin film devices, thin film transistors (TFTs) are significant building blocks for flexible platforms. Flexible oxide-based TFTs are well compatible with flexible electronic systems due to low process temperature, high carrier mobility, and good uniformity. The present article is a review of the recent progress and major trends in the field of flexible oxide-based thin film transistors. First, an introduction of flexible electronics and flexible oxide-based thin film transistors is given. Next, we introduce oxide semiconductor materials and various flexible oxide-based TFTs classified by substrate materials including polymer plastics, paper sheets, metal foils, and flexible thin glass. Afterwards, applications of flexible oxide-based TFTs including bendable sensors, memories, circuits, and displays are presented. Finally, we give conclusions and a prospect for possible development trends. Project supported in part by the National Science Foundation for Distinguished Young Scholars of China (No. 61425020), in part by the National Natural Science Foundation of China (No. 11674162).

Inversion channel diamond metal-oxide-semiconductor field-effect transistor with normally off characteristics.

PubMed

Matsumoto, Tsubasa; Kato, Hiromitsu; Oyama, Kazuhiro; Makino, Toshiharu; Ogura, Masahiko; Takeuchi, Daisuke; Inokuma, Takao; Tokuda, Norio; Yamasaki, Satoshi

2016-08-22

We fabricated inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off characteristics. At present, Si MOSFETs and insulated gate bipolar transistors (IGBTs) with inversion channels are widely used because of their high controllability of electric power and high tolerance. Although a diamond semiconductor is considered to be a material with a strong potential for application in next-generation power devices, diamond MOSFETs with an inversion channel have not yet been reported. We precisely controlled the MOS interface for diamond by wet annealing and fabricated p-channel and planar-type MOSFETs with phosphorus-doped n-type body on diamond (111) substrate. The gate oxide of Al2O3 was deposited onto the n-type diamond body by atomic layer deposition at 300 °C. The drain current was controlled by the negative gate voltage, indicating that an inversion channel with a p-type character was formed at a high-quality n-type diamond body/Al2O3 interface. The maximum drain current density and the field-effect mobility of a diamond MOSFET with a gate electrode length of 5 μm were 1.6 mA/mm and 8.0 cm(2)/Vs, respectively, at room temperature.

Multiferroic Double Perovskites ScFe1-xCrxO3 (1 /6 ≤x ≤5 /6 ) for Highly Efficient Photovoltaics and Spintronics

NASA Astrophysics Data System (ADS)

Cai, Tian-Yi; Liu, Shi-Chen; Ju, Sheng; Liu, Cheng-You; Guo, Guang-Yu

2017-09-01

Ferroelectric oxides are attractive materials for constructing efficient solar cells. Nevertheless, a wide band gap of nearly 3.0 eV in these ferroelectric oxides would result in poor overall sunlight absorption and, hence, low energy conversion efficiency. Here, by systematic first-principles density-functional calculations, we demonstrate that double-perovskite semiconductors ScFe1-xCrxO3 (1 /6 ≤x ≤5 /6 ) with a narrow band gap of approximately 1.8 eV would simultaneously exhibit large ferroelectric polarization (100 μ C /cm2 ) and ferrimagnetic magnetization (170 emu/cm3 ). Within a Schottky-based model for a typical sandwich solar-cell structure, a power-conversion efficiency of 9.0% can be reached by neglecting all other sources of photovoltaicity in ferroelectric materials. This value is larger than the largest value of 8.1% observed in ferroelectric oxides. Furthermore, these double perovskites are found to be single-spin semiconductors, and the obtained photocurrent is fully spin polarized over almost the entire Sun spectrum. These fascinating advantages would make ScFex Cr1 -xO3 (1 /6 ≤x ≤5 /6 ) semiconductors promising candidates for highly efficient solar cells and spin photovoltaic devices.

Enhancement of ZnO-based flexible nano generators via a sol-gel technique for sensing and energy harvesting applications

NASA Astrophysics Data System (ADS)

Rajagopalan, P.; Singh, Vipul; Palani, I. A.

2018-03-01

Zinc oxide (ZnO) is a remarkable inorganic semiconductor with exceptional piezoelectric properties compared to other semiconductors. However, in comparison to lead-based hazardous piezoelectric materials, its properties have undesired limitations. Here we report a 5˜6 fold enhancement in piezoelectric features via chemical doping of copper matched to intrinsic ZnO. A flexible piezoelectric nanogenerator (F-PENG) device was fabricated using an unpretentious solution process of spin coating, with other advantages such as robustness, low-weight, improved adhesion, and low cost. The device was used to demonstrate energy harvesting from a standard weight as low as 4 gm and can work as a self-powered mass sensor in a broad range of 4 to 100 gm. The device exhibited a novel energy harvesting technique from a wind source due to its inherent flexibility. At three different velocities (10˜30 m s-1) and five different angles of attack (0˜180 degrees), the device validated the ability to discern different velocities and directions of flow. The device will be useful for mapping the flow of air apart from harvesting the energy. The simulation was done to verify the underlining mechanism of aerodynamics involved.

Enhancement of ZnO-based flexible nano generators via a sol-gel technique for sensing and energy harvesting applications.

PubMed

Rajagopalan, P; Singh, Vipul; Palani, I A

2018-02-01

Zinc oxide (ZnO) is a remarkable inorganic semiconductor with exceptional piezoelectric properties compared to other semiconductors. However, in comparison to lead-based hazardous piezoelectric materials, its properties have undesired limitations. Here we report a 5∼6 fold enhancement in piezoelectric features via chemical doping of copper matched to intrinsic ZnO. A flexible piezoelectric nanogenerator (F-PENG) device was fabricated using an unpretentious solution process of spin coating, with other advantages such as robustness, low-weight, improved adhesion, and low cost. The device was used to demonstrate energy harvesting from a standard weight as low as 4 gm and can work as a self-powered mass sensor in a broad range of 4 to 100 gm. The device exhibited a novel energy harvesting technique from a wind source due to its inherent flexibility. At three different velocities (10∼30 m s -1 ) and five different angles of attack (0∼180 degrees), the device validated the ability to discern different velocities and directions of flow. The device will be useful for mapping the flow of air apart from harvesting the energy. The simulation was done to verify the underlining mechanism of aerodynamics involved.

Surface chemistry relevant to material processing for semiconductor devices

NASA Astrophysics Data System (ADS)

Okada, Lynne Aiko

Metal-oxide-semiconductor (MOS) structures are the core of many modern integrated circuit (IC) devices. Each material utilized in the different regions of the device has its own unique chemistry. Silicon is the base semiconductor material used in the majority of these devices. With IC device complexity increasing and device dimensions decreasing, understanding material interactions and processing becomes increasingly critical. Hsb2 desorption is the rate-limiting step in silicon growth using silane under low temperature conditions. Activation energies for Hsb2 desorption measured during Si chemical vapor deposition (CVD) versus single-crystal studies are found to be significantly lower. It has been proposed that defect sites on the silicon surface could explain the observed differences. Isothermal Hsb2 desorption studies using laser induced thermal desorption (LITD) techniques have addressed this issue. The growth of low temperature oxides is another relevant issue for fabrication of IC devices. Recent studies using 1,4-disilabutane (DSB) (SiHsb3CHsb2CHsb2SiHsb3) at 100sp°C in ambient Osb2 displayed the successful low temperature growth of silicon dioxide (SiOsb2). However, these studies provided no information about the deposition mechanism. We performed LITD and Fourier transform infrared (FTIR) studies on single-crystal and porous silicon surfaces to examine the adsorption, decomposition, and desorption processes to determine the deposition mechanism. Titanium nitride (TiN) diffusion barriers are necessary in modern metallization structures. Controlled deposition using titanium tetrachloride (TiClsb4) and ammonia (NHsb3) has been demonstrated using atomic layered processing (ALP) techniques. We intended to study the sequential deposition method by monitoring the surface intermediates using LITD techniques. However, formation of a Cl impurity source, ammonium chloride (NHsb4sp+Clsp-), was observed, thereby, limiting our ability for effective studies. Tetrakis(dimethylamino)titanium (Tilbrack N\\{CHsb3\\}sb2rbracksb4) (TDMAT) is another precursor used in the CVD deposition of TiN films in IC devices. Thermal decomposition studies have demonstrated deviations from conformal deposition. Successful conformal deposition may be affected by readsorption of the reaction product, dimethylamine (HNlbrack CHsb3rbracksb2). Detailed studies were performed using LITD techniques in order to understand the adsorption and desorption kinetics of TDMAT and dimethylamine to gain insights about the conformal deposition of TiN.

The Morphologies of the Semiconductor Oxides and Their Gas-Sensing Properties

PubMed Central

Lv, Xin; Li, Shuang; Wang, Qingji

2017-01-01

Semiconductor oxide chemoresistive gas sensors are widely used for detecting deleterious gases due to low cost, simple preparation, rapid response and high sensitivity. The performance of gas sensor is greatly affected by the morphology of the semiconductor oxide. There are many semiconductor oxide morphologies, including zero-dimensional, one-dimensional, two-dimensional and three-dimensional ones. The semiconductor oxides with different morphologies significantly enhance the gas-sensing performance. Among the various morphologies, hollow nanostructures and core-shell nanostructures are always the focus of research in the field of gas sensors due to their distinctive structural characteristics and superior performance. Herein the morphologies of semiconductor oxides and their gas-sensing properties are reviewed. This review also proposes a potential strategy for the enhancement of gas-sensing performance in the future. PMID:29189714

Interface Energetics and Chemical Doping of Organic Electronic Materials

NASA Astrophysics Data System (ADS)

Kahn, Antoine

2014-03-01

The energetics of organic semiconductors and their interfaces are central to the performance of organic thin film devices. The relative positions of charge transport states across the many interfaces of multi-layer OLEDs, OPV cells and OFETs determine in great part the efficiency and lifetime of these devices. New experiments are presented here, that look in detail at the position of these transport states and associated gap states and electronic traps that tail into the energy gap of organic molecular (e.g. pentacene) or polymer (P3HT, PBDTTT-C) semiconductors, and which directly affect carrier mobility in these materials. Disorder, sometime caused by simple exposure to an inert gas, impurities and defects are at the origin of these electronic gap states. Recent efforts in chemical doping in organic semiconductors aimed at mitigating the impact of electronic gap states are described. An overview of the reducing or oxidizing power of several n- and p-type dopants for vacuum- or solution-processed films, and their effect on the electronic structure and conductivity of both vacuum- and solution-processed organic semiconductor films is given. Finally, the filling (compensation) of active gap states via doping is investigated on the electron-transport materials C60 and P(NDI2OD-T2) , and the hole-transport polymer PBDTTT-C.

Initial stage oxidation on nano-trenched Si(1 0 0) surface

NASA Astrophysics Data System (ADS)

Sun, Yu; Liu, Yi-Lun; Izumi, Satoshi; Chen, Xue-Feng; Zhai, Zhi; Tian, Shao-Hua

2018-01-01

As the size of an electronic element shrinks to nanoscale, trench design of Si strongly influences the performance of related semiconductor devices. By reactive force field molecular dynamics (ReaxFF MD) simulation, the initial stage oxidation on nano-trenched Si(1 0 0) angled 60°, 90°, 120°, 150° under temperatures from 300 K to 1200 K has been studied. Inhomogeneous oxidation at the convex-concave corners of the Si surface was observed. In general, the initial oxidation process on the Si surface was that, firstly, the O atoms ballistically transported into surface, then a high O concentration induced compressive stress at the surface layers, which prevented further oxidation. Compared to the concave corner, the convex one contacted a larger volume of oxygen at the very beginning stage, leading an anisotropic absorption of O atoms. Afterwards, a critical compression was produced at both the convex and concave corners to limit the oxidation. As a result, an inhomogeneous oxide film grew on nano-trenched Si. Meanwhile, due to enhanced O transport and compression relaxation by increasing temperature, the inhomogeneous oxidation was more obvious under 1200 K. These present results explained the observed experimental phenomena on the oxidation of non-planar Si and provided an aspect on the design of nano-trenched electronic components in the semiconductor field.

Solution Processed Metal Oxide High-κ Dielectrics for Emerging Transistors and Circuits.

PubMed

Liu, Ao; Zhu, Huihui; Sun, Huabin; Xu, Yong; Noh, Yong-Young

2018-06-14

The electronic functionalities of metal oxides comprise conductors, semiconductors, and insulators. Metal oxides have attracted great interest for construction of large-area electronics, particularly thin-film transistors (TFTs), for their high optical transparency, excellent chemical and thermal stability, and mechanical tolerance. High-permittivity (κ) oxide dielectrics are a key component for achieving low-voltage and high-performance TFTs. With the expanding integration of complementary metal oxide semiconductor transistors, the replacement of SiO 2 with high-κ oxide dielectrics has become urgently required, because their provided thicker layers suppress quantum mechanical tunneling. Toward low-cost devices, tremendous efforts have been devoted to vacuum-free, solution processable fabrication, such as spin coating, spray pyrolysis, and printing techniques. This review focuses on recent progress in solution processed high-κ oxide dielectrics and their applications to emerging TFTs. First, the history, basics, theories, and leakage current mechanisms of high-κ oxide dielectrics are presented, and the underlying mechanism for mobility enhancement over conventional SiO 2 is outlined. Recent achievements of solution-processed high-κ oxide materials and their applications in TFTs are summarized and traditional coating methods and emerging printing techniques are introduced. Finally, low temperature approaches, e.g., ecofriendly water-induced, self-combustion reaction, and energy-assisted post treatments, for the realization of flexible electronics and circuits are discussed. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Integration of functional oxides and semiconductors

NASA Astrophysics Data System (ADS)

Demkov, Alex

2012-10-01

The astounding progress of recent years in the area of oxide deposition has made possible the creation of oxide heterostructures with atomically abrupt interfaces. The ability to control the length scale, strain, and orbital order in these materials structures offers a uniquely rich toolbox for condensed matter physicists. Because the oxide layers are very thin, the physics is often controlled by the interface. The electronic properties of oxide interfaces are governed by a subtle interplay of many competing interactions such as strain, polar catastrophe, electron correlation, and Jahn-Teller coupling, as well as by defects and phase stability. It is not clear which, if any, of these newly discovered systems will find applications in future high-tech devices. However, they undoubtedly hold tremendous promise, particularly when integrated with conventional semiconductors such as Si. In this talk I will review our recent results in theoretical modeling and experimental realization of several epitaxial oxide heterostructures. I will set the stage with a brief discussion of extrinsic magnetoelectric coupling at the interface of a perovskite ferroelectric and conventional ferromagnet. I will then describe our recent successful attempt to integrate anatase, a photo-catalytic polymorph of TiO2, with Si (001) using molecular beam epitaxy. In conclusion, I will talk about strain stabilized ferromagnetism in correlated LaCoO3 (LCO) and monolithic integration of LCO and silicon for possible applications in spintronics. The integration is achieved via the single crystal SrTiO3 (STO) buffer epitaxially grown on Si. Superconducting quantum interference device magnetization measurements show that, unlike the bulk material, the ground state of the strained LaCoO3 on silicon is ferromagnetic with a TC of 85 K.

Operation and biasing for single device equivalent to CMOS

DOEpatents

Welch, James D.

2001-01-01

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Demonstration of Al:ZnO as a plasmonic component for near-infrared metamaterials

PubMed Central

Naik, Gururaj V.; Liu, Jingjing; Kildishev, Alexander V.; Shalaev, Vladimir M.; Boltasseva, Alexandra

2012-01-01

Noble metals such as gold and silver are conventionally used as the primary plasmonic building blocks of optical metamaterials. Making subwavelength-scale structural elements from these metals not only seriously limits the optical performance of a device due to high absorption, it also substantially complicates the manufacturing process of nearly all metamaterial devices in the optical wavelength range. As an alternative to noble metals, we propose to use heavily doped oxide semiconductors that offer both functional and fabrication advantages in the near-infrared wavelength range. In this letter, we replace a metal with aluminum-doped zinc oxide as a new plasmonic material and experimentally demonstrate negative refraction in an Al:ZnO/ZnO metamaterial in the near-infrared range. PMID:22611188

Recent progress in magnetic iron oxide-semiconductor composite nanomaterials as promising photocatalysts

NASA Astrophysics Data System (ADS)

Wu, Wei; Changzhong Jiang, Affc; Roy, Vellaisamy A. L.

2014-11-01

Photocatalytic degradation of toxic organic pollutants is a challenging tasks in ecological and environmental protection. Recent research shows that the magnetic iron oxide-semiconductor composite photocatalytic system can effectively break through the bottleneck of single-component semiconductor oxides with low activity under visible light and the challenging recycling of the photocatalyst from the final products. With high reactivity in visible light, magnetic iron oxide-semiconductors can be exploited as an important magnetic recovery photocatalyst (MRP) with a bright future. On this regard, various composite structures, the charge-transfer mechanism and outstanding properties of magnetic iron oxide-semiconductor composite nanomaterials are sketched. The latest synthesis methods and recent progress in the photocatalytic applications of magnetic iron oxide-semiconductor composite nanomaterials are reviewed. The problems and challenges still need to be resolved and development strategies are discussed.

Novel Approach to Front Contact Passivation for CdTe Photovoltaics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kephart, Jason M.

2018-02-18

The goal of this project was to study the use of sputter-deposited oxide materials for interface passivation of CdTe-based photovoltaics. Several candidate materials were chosen based on their promise in passivating the CdTe and CdSeTe semiconductor interface, chemical and thermal stability to device processing, and ability to be deposited by sputter deposition.

Comparative Study on Graded-Barrier AlxGa1‑xN/AlN/GaN/Si Metal-Oxide-Semiconductor Heterostructure Field-Effect Transistor by Using Ultrasonic Spray Pyrolysis Deposition Technique

NASA Astrophysics Data System (ADS)

Lee, Ching-Sung; Hsu, Wei-Chou; Huang, Yi-Ping; Liu, Han-Yin; Yang, Wen-Luh; Yang, Shen-Tin

2018-06-01

Comparative study on a novel Al2O3-dielectric graded-barrier (GB) AlxGa1‑xN/AlN/GaN/Si (x = 0.22 ∼ 0.3) metal-oxide-semiconductor heterostructure field-effect transistor (MOS-HFET) formed by using the ultrasonic spray pyrolysis deposition (USPD) technique has been made with respect to a conventional-barrier (CB) Al0.26Ga0.74N/AlN/GaN/Si MOS-HFET and the reference Schottky-gate HFET devices. The GB AlxGa1‑xN was devised to improve the interfacial quality and enhance the Schottky barrier height at the same time. A cost-effective ultrasonic spray pyrolysis deposition (USPD) method was used to form the high-k Al2O3 gate dielectric and surface passivation on the AlGaN barrier of the present MOS-HFETs. Comprehensive device performances, including maximum extrinsic transconductance (g m,max), maximum drain-source current density (I DS,max), gate-voltage swing (GVS) linearity, breakdown voltages, subthreshold swing (SS), on/off current ratio (I on /I off ), high frequencies, and power performance are investigated.

Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes.

PubMed

Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Zhang, Jialu; Zhou, Chongwu

2011-02-22

Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

Thin film three-dimensional topological insulator metal-oxide-semiconductor field-effect-transistors: A candidate for sub-10 nm devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Akhavan, N. D., E-mail: nima.dehdashti@uwa.edu.au; Jolley, G.; Umana-Membreno, G. A.

2014-08-28

Three-dimensional (3D) topological insulators (TI) are a new state of quantum matter in which surface states reside in the bulk insulating energy bandgap and are protected by time-reversal symmetry. It is possible to create an energy bandgap as a consequence of the interaction between the conduction band and valence band surface states from the opposite surfaces of a TI thin film, and the width of the bandgap can be controlled by the thin film thickness. The formation of an energy bandgap raises the possibility of thin-film TI-based metal-oxide-semiconductor field-effect-transistors (MOSFETs). In this paper, we explore the performance of MOSFETs basedmore » on thin film 3D-TI structures by employing quantum ballistic transport simulations using the effective continuous Hamiltonian with fitting parameters extracted from ab-initio calculations. We demonstrate that thin film transistors based on a 3D-TI structure provide similar electrical characteristics compared to a Si-MOSFET for gate lengths down to 10 nm. Thus, such a device can be a potential candidate to replace Si-based MOSFETs in the sub-10 nm regime.« less

Silicon Metal-oxide-semiconductor Quantum Dots for Single-electron Pumping

PubMed Central

Rossi, Alessandro; Tanttu, Tuomo; Hudson, Fay E.; Sun, Yuxin; Möttönen, Mikko; Dzurak, Andrew S.

2015-01-01

As mass-produced silicon transistors have reached the nano-scale, their behavior and performances are increasingly affected, and often deteriorated, by quantum mechanical effects such as tunneling through single dopants, scattering via interface defects, and discrete trap charge states. However, progress in silicon technology has shown that these phenomena can be harnessed and exploited for a new class of quantum-based electronics. Among others, multi-layer-gated silicon metal-oxide-semiconductor (MOS) technology can be used to control single charge or spin confined in electrostatically-defined quantum dots (QD). These QD-based devices are an excellent platform for quantum computing applications and, recently, it has been demonstrated that they can also be used as single-electron pumps, which are accurate sources of quantized current for metrological purposes. Here, we discuss in detail the fabrication protocol for silicon MOS QDs which is relevant to both quantum computing and quantum metrology applications. Moreover, we describe characterization methods to test the integrity of the devices after fabrication. Finally, we give a brief description of the measurement set-up used for charge pumping experiments and show representative results of electric current quantization. PMID:26067215

Characteristics and reliability of metal-oxide-semiconductor transistors with various depths of plasma-induced Si recess structure

NASA Astrophysics Data System (ADS)

Chen, Jone F.; Tsai, Yen-Lin; Chen, Chun-Yen; Hsu, Hao-Tang; Kao, Chia-Yu; Hwang, Hann-Ping

2018-04-01

Device characteristics and hot-carrier-induced device degradation of n-channel MOS transistors with an off-state breakdown voltage of approximately 25 V and various Si recess depths introduced by sidewall spacer overetching are investigated. Experimental data show that the depth of the Si recess has small effects on device characteristics. A device with a deeper Si recess has lower substrate current and channel electric field, whereas a greater hot-carrier-induced device degradation and a shorter hot-carrier lifetime are observed. Results of technology computer-aided design simulations suggest that these unexpected observations are related to the severity of plasma damage caused by the sidewall spacer overetching and the difference in topology.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nuzzo, Ralph G.; Rogers, John A.; Menard, Etienne

The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Near-thermal limit gating in heavily doped III-V semiconductor nanowires using polymer electrolytes

NASA Astrophysics Data System (ADS)

Ullah, A. R.; Carrad, D. J.; Krogstrup, P.; Nygârd, J.; Micolich, A. P.

2018-02-01

Doping is a common route to reducing nanowire transistor on-resistance but it has limits. A high doping level gives significant loss in gate performance and ultimately complete gate failure. We show that electrolyte gating remains effective even when the Be doping in our GaAs nanowires is so high that traditional metal-oxide gates fail. In this regime we obtain a combination of subthreshold swing and contact resistance that surpasses the best existing p -type nanowire metal-oxide semiconductor field-effect transistors (MOSFETs). Our subthreshold swing of 75 mV/dec is within 25 % of the room-temperature thermal limit and comparable with n -InP and n -GaAs nanowire MOSFETs. Our results open a new path to extending the performance and application of nanowire transistors, and motivate further work on improved solid electrolytes for nanoscale device applications.

Transition metal oxide as anode interface buffer for impedance spectroscopy

NASA Astrophysics Data System (ADS)

Xu, Hui; Tang, Chao; Wang, Xu-Liang; Zhai, Wen-Juan; Liu, Rui-Lan; Rong, Zhou; Pang, Zong-Qiang; Jiang, Bing; Fan, Qu-Li; Huang, Wei

2015-12-01

Impedance spectroscopy is a strong method in electric measurement, which also shows powerful function in research of carrier dynamics in organic semiconductors when suitable mathematical physical models are used. Apart from this, another requirement is that the contact interface between the electrode and materials should at least be quasi-ohmic contact. So in this report, three different transitional metal oxides, V2O5, MoO3 and WO3 were used as hole injection buffer for interface of ITO/NPB. Through the impedance spectroscopy and PSO algorithm, the carrier mobilities and I-V characteristics of the NPB in different devices were measured. Then the data curves were compared with the single layer device without the interface layer in order to investigate the influence of transitional metal oxides on the carrier mobility. The careful research showed that when the work function (WF) of the buffer material was just between the work function of anode and the HOMO of the organic material, such interface material could work as a good bridge for carrier injection. Under such condition, the carrier mobility measured through impedance spectroscopy should be close to the intrinsic value. Considering that the HOMO (or LUMO) of most organic semiconductors did not match with the work function of the electrode, this report also provides a method for wide application of impedance spectroscopy to the research of carrier dynamics.

A new coupling mechanism between two graphene electron waveguides for ultrafast switching

NASA Astrophysics Data System (ADS)

Huang, Wei; Liang, Shi-Jun; Kyoseva, Elica; Ang, Lay Kee

2018-03-01

In this paper, we report a novel coupling between two graphene electron waveguides, in analogy the optical waveguides. The design is based on the coherent quantum mechanical tunneling of Rabi oscillation between the two graphene electron waveguides. Based on this coupling mechanism, we propose that it can be used as an ultrafast electronic switching device. Based on a modified coupled mode theory, we construct a theoretical model to analyze the device characteristics, and predict that the switching speed is faster than 1 ps and the on-off ratio exceeds 106. Due to the long mean free path of electrons in graphene at room temperature, the proposed design avoids the limitation of low temperature operation required in the traditional design by using semiconductor quantum-well structure. The layout of our design is similar to that of a standard complementary metal-oxide-semiconductor transistor that should be readily fabricated with current state-of-art nanotechnology.

Shockwave generation by a semiconductor bridge operation in water

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zvulun, E.; Toker, G.; Gurovich, V. Tz.

2014-05-28

A semiconductor bridge (SCB) is a silicon device, used in explosive systems as the electrical initiator element. In recent years, SCB plasma has been extensively studied, both electrically and using fast photography and spectroscopic imaging. However, the value of the pressure buildup at the bridge remains unknown. In this study, we operated SCB devices in water and, using shadow imaging and reference beam interferometry, obtained the velocity of the shock wave propagation and distribution of the density of water. These results, together with a self-similar hydrodynamic model, were used to calculate the pressure generated by the exploding SCB. In addition,more » the results obtained showed that the energy of the water flow exceeds significantly the energy deposited into the exploded SCB. The latter can be explained by the combustion of the aluminum and silicon atoms released in water, which acts as an oxidizing medium.« less

Hybrid permeable metal-base transistor with large common-emitter current gain and low operational voltage.

PubMed

Feng, Chengang; Yi, Mingdong; Yu, Shunyang; Hümmelgen, Ivo A; Zhang, Tong; Ma, Dongge

2008-04-01

We demonstrate the suitability of N,N'-diphenyl-N,N'-bis(1-naphthylphenyl)-1,1'-biphenyl-4,4'-diamine (NPB), an organic semiconductor widely used in organic light-emitting diodes (OLEDs), for high-gain, low operational voltage nanostructured vertical-architecture transistors, which operate as permeable-base transistors. By introducing vanadium oxide (V2O5) between the injecting metal and NPB layer at the transistor emitter, we reduced the emitter operational voltage. The addition of two Ca layers, leading to a Ca/Ag/Ca base, allowed to obtain a large value of common-emitter current gain, but still retaining the permeable-base transistor character. This kind of vertical devices produced by simple technologies offer attractive new possibilities due to the large variety of available molecular semiconductors, opening the possibility of incorporating new functionalities in silicon-based devices.

Photo-induced persistent inversion of germanium in a 200-nm-deep surface region.

PubMed

Prokscha, T; Chow, K H; Stilp, E; Suter, A; Luetkens, H; Morenzoni, E; Nieuwenhuys, G J; Salman, Z; Scheuermann, R

2013-01-01

The controlled manipulation of the charge carrier concentration in nanometer thin layers is the basis of current semiconductor technology and of fundamental importance for device applications. Here we show that it is possible to induce a persistent inversion from n- to p-type in a 200-nm-thick surface layer of a germanium wafer by illumination with white and blue light. We induce the inversion with a half-life of ~12 hours at a temperature of 220 K which disappears above 280 K. The photo-induced inversion is absent for a sample with a 20-nm-thick gold capping layer providing a Schottky barrier at the interface. This indicates that charge accumulation at the surface is essential to explain the observed inversion. The contactless change of carrier concentration is potentially interesting for device applications in opto-electronics where the gate electrode and gate oxide could be replaced by the semiconductor surface.

Power Electronic Semiconductor Materials for Automotive and Energy Saving Applications - SiC, GaN, Ga2O3, and Diamond.

PubMed

Wellmann, Peter J

2017-11-17

Power electronics belongs to the future key technologies in order to increase system efficiency as well as performance in automotive and energy saving applications. Silicon is the major material for electronic switches since decades. Advanced fabrication processes and sophisticated electronic device designs have optimized the silicon electronic device performance almost to their theoretical limit. Therefore, to increase the system performance, new materials that exhibit physical and chemical properties beyond silicon need to be explored. A number of wide bandgap semiconductors like silicon carbide, gallium nitride, gallium oxide, and diamond exhibit outstanding characteristics that may pave the way to new performance levels. The review will introduce these materials by (i) highlighting their properties, (ii) introducing the challenges in materials growth, and (iii) outlining limits that need innovation steps in materials processing to outperform current technologies.

Power Electronic Semiconductor Materials for Automotive and Energy Saving Applications – SiC, GaN, Ga2O3, and Diamond

PubMed Central

2017-01-01

Power electronics belongs to the future key technologies in order to increase system efficiency as well as performance in automotive and energy saving applications. Silicon is the major material for electronic switches since decades. Advanced fabrication processes and sophisticated electronic device designs have optimized the silicon electronic device performance almost to their theoretical limit. Therefore, to increase the system performance, new materials that exhibit physical and chemical properties beyond silicon need to be explored. A number of wide bandgap semiconductors like silicon carbide, gallium nitride, gallium oxide, and diamond exhibit outstanding characteristics that may pave the way to new performance levels. The review will introduce these materials by (i) highlighting their properties, (ii) introducing the challenges in materials growth, and (iii) outlining limits that need innovation steps in materials processing to outperform current technologies. PMID:29200530

Optically switched graphene/4H-SiC junction bipolar transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chandrashekhar, MVS; Sudarshan, Tangali S.; Omar, Sabih U.

A bi-polar device is provided, along with methods of making the same. The bi-polar device can include a semiconductor substrate doped with a first dopant, a semiconductor layer on the first surface of the semiconductor substrate, and a Schottky barrier layer on the semiconductor layer. The method of forming a bi-polar device can include: forming a semiconductor layer on a first surface of a semiconductor substrate, where the semiconductor substrate comprises a first dopant and where the semiconductor layer comprises a second dopant that has an opposite polarity than the first dopant; and forming a Schottky barrier layer on amore » first portion of the semiconductor layer while leaving a second portion of the semiconductor layer exposed.« less

Semiconductor devices having a recessed electrode structure

DOEpatents

Palacios, Tomas Apostol; Lu, Bin; Matioli, Elison de Nazareth

2015-05-26

An electrode structure is described in which conductive regions are recessed into a semiconductor region. Trenches may be formed in a semiconductor region, such that conductive regions can be formed in the trenches. The electrode structure may be used in semiconductor devices such as field effect transistors or diodes. Nitride-based power semiconductor devices are described including such an electrode structure, which can reduce leakage current and otherwise improve performance.

Determination of Insulator-to-Semiconductor Transition in Sol-Gel Oxide Semiconductors Using Derivative Spectroscopy.

PubMed

Lee, Woobin; Choi, Seungbeom; Kim, Kyung Tae; Kang, Jingu; Park, Sung Kyu; Kim, Yong-Hoon

2015-12-23

We report a derivative spectroscopic method for determining insulator-to-semiconductor transition during sol-gel metal-oxide semiconductor formation. When an as-spun sol-gel precursor film is photochemically activated and changes to semiconducting state, the light absorption characteristics of the metal-oxide film is considerable changed particularly in the ultraviolet region. As a result, a peak is generated in the first-order derivatives of light absorption ( A' ) vs. wavelength (λ) plots, and by tracing the peak center shift and peak intensity, transition from insulating-to-semiconducting state of the film can be monitored. The peak generation and peak center shift are described based on photon-energy-dependent absorption coefficient of metal-oxide films. We discuss detailed analysis method for metal-oxide semiconductor films and its application in thin-film transistor fabrication. We believe this derivative spectroscopy based determination can be beneficial for a non-destructive and a rapid monitoring of the insulator-to-semiconductor transition in sol-gel oxide semiconductor formation.

Deformable devices with integrated functional nanomaterials for wearable electronics.

PubMed

Kim, Jaemin; Lee, Jongsu; Son, Donghee; Choi, Moon Kee; Kim, Dae-Hyeong

2016-01-01

As the market and related industry for wearable electronics dramatically expands, there are continuous and strong demands for flexible and stretchable devices to be seamlessly integrated with soft and curvilinear human skin or clothes. However, the mechanical mismatch between the rigid conventional electronics and the soft human body causes many problems. Therefore, various prospective nanomaterials that possess a much lower flexural rigidity than their bulk counterparts have rapidly established themselves as promising electronic materials replacing rigid silicon and/or compound semiconductors in next-generation wearable devices. Many hybrid structures of multiple nanomaterials have been also developed to pursue both high performance and multifunctionality. Here, we provide an overview of state-of-the-art wearable devices based on one- or two-dimensional nanomaterials (e.g., carbon nanotubes, graphene, single-crystal silicon and oxide nanomembranes, organic nanomaterials and their hybrids) in combination with zero-dimensional functional nanomaterials (e.g., metal/oxide nanoparticles and quantum dots). Starting from an introduction of materials strategies, we describe device designs and the roles of individual ones in integrated systems. Detailed application examples of wearable sensors/actuators, memories, energy devices, and displays are also presented.

Total Ionizing Dose Effects in MOS Oxides and Devices

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; McLean, F. B.

2003-01-01

The development of military and space electronics technology has traditionally been heavily influenced by the commercial semiconductor industry. The development of MOS technology, and particularly CMOS technology, as dominant commercial technologies has occurred entirely within the lifetime of the NSREC. For this reason, it is not surprising that the study of radiation interactions with MOS materials, devices and circuits has been a major theme of this conference for most of its history. The basic radiation problem in a MOS transistor is illustrated. The application of an appropriate gate voltage causes a conducting channel to form between the source and drain, so that current flows when the device is turned on. In Fig. lb, the effect of ionizing radiation is illustrated. Radiation-induced trapped charge has built up in the gate oxide, which causes a shift in the threshold voltage (that is, a change in the voltage which must be applied to turn the device on). If this shift is large enough, the device cannot be turned off, even at zero volts applied, and the device is said to have failed by going depletion mode.

Effects of consecutive irradiation and bias temperature stress in p-channel power vertical double-diffused metal oxide semiconductor transistors

NASA Astrophysics Data System (ADS)

Davidović, Vojkan; Danković, Danijel; Ilić, Aleksandar; Manić, Ivica; Golubović, Snežana; Djorić-Veljković, Snežana; Prijić, Zoran; Prijić, Aneta; Stojadinović, Ninoslav

2018-04-01

The mechanisms responsible for the effects of consecutive irradiation and negative bias temperature (NBT) stress in p-channel power vertical double-diffused MOS (VDMOS) transistors are presented in this paper. The investigation was performed in order to clarify the mechanisms responsible for the effects of specific kind of stress in devices previously subjected to the other kind of stress. In addition, it may help in assessing the behaviour of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to additional build-up of oxide trapped charge and interface traps, while NBT stress effects in previously irradiated devices depend on gate bias applied during irradiation and on the total dose received. In the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress leads to slight further device degradation. On the other hand, in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress may have a positive role, as it actually anneals a part of radiation-induced degradation.

Deformable devices with integrated functional nanomaterials for wearable electronics

NASA Astrophysics Data System (ADS)

Kim, Jaemin; Lee, Jongsu; Son, Donghee; Choi, Moon Kee; Kim, Dae-Hyeong

2016-03-01

As the market and related industry for wearable electronics dramatically expands, there are continuous and strong demands for flexible and stretchable devices to be seamlessly integrated with soft and curvilinear human skin or clothes. However, the mechanical mismatch between the rigid conventional electronics and the soft human body causes many problems. Therefore, various prospective nanomaterials that possess a much lower flexural rigidity than their bulk counterparts have rapidly established themselves as promising electronic materials replacing rigid silicon and/or compound semiconductors in next-generation wearable devices. Many hybrid structures of multiple nanomaterials have been also developed to pursue both high performance and multifunctionality. Here, we provide an overview of state-of-the-art wearable devices based on one- or two-dimensional nanomaterials (e.g., carbon nanotubes, graphene, single-crystal silicon and oxide nanomembranes, organic nanomaterials and their hybrids) in combination with zero-dimensional functional nanomaterials (e.g., metal/oxide nanoparticles and quantum dots). Starting from an introduction of materials strategies, we describe device designs and the roles of individual ones in integrated systems. Detailed application examples of wearable sensors/actuators, memories, energy devices, and displays are also presented.

High performance flexible electronics for biomedical devices.

PubMed

Salvatore, Giovanni A; Munzenrieder, Niko; Zysset, Christoph; Kinkeldei, Thomas; Petti, Luisa; Troster, Gerhard

2014-01-01

Plastic electronics is soft, deformable and lightweight and it is suitable for the realization of devices which can form an intimate interface with the body, be implanted or integrated into textile for wearable and biomedical applications. Here, we present flexible electronics based on amorphous oxide semiconductors (a-IGZO) whose performance can achieve MHz frequency even when bent around hair. We developed an assembly technique to integrate complex electronic functionalities into textile while preserving the softness of the garment. All this and further developments can open up new opportunities in health monitoring, biotechnology and telemedicine.

Cryogenic transimpedance amplifier for micromechanical capacitive sensors.

PubMed

Antonio, D; Pastoriza, H; Julián, P; Mandolesi, P

2008-08-01

We developed a cryogenic transimpedance amplifier that works at a broad range of temperatures, from room temperature down to 4 K. The device was realized with a standard complementary metal oxide semiconductor 1.5 mum process. Measurements of current-voltage characteristics, open-loop gain, input referred noise current, and power consumption are presented as a function of temperature. The transimpedance amplifier has been successfully applied to sense the motion of a polysilicon micromechanical oscillator at low temperatures. The whole device is intended to serve as a magnetometer for microscopic superconducting samples.

Study of the Physics of Insulating Films as Related to the Reliability of Metal-Oxide-Semiconductor (MOS) Devices

DTIC Science & Technology

1981-06-01

believed to be due to irregularities in the field at the cathode) from occurring. These DEIS EAROMs operate at lower power due to the small injected SiO...memory devices which can store information without an external power supply for long periods of time are currently an area of much interest [1-5]. Current...oppose each other. These require- ments are to get charge into and out of a charge storage layer at low voltages and powers in times on the order of

Silicon device performance measurements to support temperature range enhancement

NASA Technical Reports Server (NTRS)

Johnson, R. Wayne; Askew, Ray; Bromstead, James; Weir, Bennett

1991-01-01

The results of the NPN bipolar transistor (BJT) (2N6023) breakdown voltage measurements were analyzed. Switching measurements were made on the NPN BJT, the insulated gate bipolar transistor (IGBT) (TA9796) and the N-channel metal oxide semiconductor field effect transistor (MOSFET) (RFH75N05E). Efforts were also made to build a H-bridge inverter. Also discussed are the plans that have been made to do life testing on the devices, to build an inductive switching test circuit and to build a dc/dc switched mode converter.

Vertical power MOS transistor as a thermoelectric quasi-nanowire device

NASA Astrophysics Data System (ADS)

Roizin, Gregory; Beeri, Ofer; Peretz, Mor Mordechai; Gelbstein, Yaniv

2016-12-01

Nano-materials exhibit superior performance over bulk materials in a variety of applications such as direct heat to electricity thermoelectric generators (TEGs) and many more. However, a gap still exists for the integration of these nano-materials into practical applications. This study explores the feasibility of utilizing the advantages of nano-materials' thermo-electric properties, using regular bulk technology. Present-day TEGs are often applied by dedicated thermoelectric materials such as semiconductor alloys (e.g., PbTe, BiTe) whereas the standard semiconductor materials such as the doped silicon have not been widely addressed, with limited exceptions of nanowires. This study attempts to close the gap between the nano-materials' properties and the well-established bulk devices, approached for the first time by exploiting the nano-metric dimensions of the conductive channel in metal-oxide-semiconductor (MOS) structures. A significantly higher electrical current than expected from a bulk silicon device has been experimentally measured as a result of the application of a positive gate voltage and a temperature gradient between the "source" and the "drain" terminals of a commercial NMOS transistor. This finding implies on a "quasi-nanowire" behaviour of the transistor channel, which can be easily controlled by the transistor's gate voltage that is applied. This phenomenon enables a considerable improvement of silicon based TEGs, fabricated by traditional silicon technology. Four times higher ZT values (TEG quality factor) compared to conventional bulk silicon have been observed for an off-the-shelf silicon device. By optimizing the device, it is believed that even higher ZT values can be achieved.

Heterogeneous integration of low-temperature metal-oxide TFTs

NASA Astrophysics Data System (ADS)

Schuette, Michael L.; Green, Andrew J.; Leedy, Kevin D.; McCandless, Jonathan P.; Jessen, Gregg H.

2017-02-01

The breadth of circuit fabrication opportunities enabled by metal-oxide thin-film transistors (MO-TFTs) is unprecedented. Large-area deposition techniques and high electron mobility are behind their adoption in the display industry, and substrate agnosticism and low process temperatures enabled the present wave of flexible electronics research. Reports of circuits involving complementaryMO-TFTs, oxide-organic hybrid combinations, and even MO-TFTs integrated onto Si LSI back end of line interconnects demonstrate this technology's utility in 2D and 3D monolithic heterogeneous integration (HI). In addition to a brief literature review focused on functional HI between MO-TFTs and a variety of dissimilar active devices, we share progress toward integrating MO-TFTs with compound semiconductor devices, namely GaN HEMTs. A monolithically integrated cascode topology was used to couple a HEMT's >200 V breakdown characteristic with the gate driving characteristic of an IGZO TFT, effectively shifting the HEMT threshold voltage from -3 V to +1 V.

Fabricating Ohmic contact on Nb-doped SrTiO{sub 3} surface in nanoscale

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Yuhang; National Key Laboratory of Shock Wave and Detonation Physics, Institute of Fluid Physics, Chinese Academy of Engineering Physics, Mianyang, Sichuan 621999; Shi, Xiaolan

2016-05-09

Fabricating reliable nano-Ohmic contact on wide gap semiconductors is an important yet difficult step in oxide nanoelectronics. We fabricated Ohmic contact on the n-type wide gap oxide Nb-doped SrTiO{sub 3} in nanoscale by mechanically scratching the surface using an atomic force microscopy tip. Although contacted to high work function metal, the scratched area exhibits nearly linear IV behavior with low contact resistance, which maintains for hours in vacuum. In contrast, the unscratched area shows Fowler–Nordheim tunneling dominated Schottky rectifying behavior with high contact resistance. It was found that the Ohmic conductivity in the scratched area was drastically suppressed by oxygenmore » gas indicating the oxygen vacancy origin of the Ohmic behavior. The surface oxygen vacancy induced barrier width reduction was proposed to explain the phenomena. The nanoscale approach is also applicable to macroscopic devices and has potential application in all-oxide devices.« less

Extraction method of interfacial injected charges for SiC power MOSFETs

NASA Astrophysics Data System (ADS)

Wei, Jiaxing; Liu, Siyang; Li, Sheng; Song, Haiyang; Chen, Xin; Li, Ting; Fang, Jiong; Sun, Weifeng

2018-01-01

An improved novel extraction method which can characterize the injected charges along the gate oxide interface for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. According to the different interface situations of the channel region and the junction FET (JFET) region, the gate capacitance versus gate voltage (Cg-Vg) curve of the device can be divided into three relatively independent parts, through which the locations and the types of the charges injected in to the oxide above the interface can be distinguished. Moreover, the densities of these charges can also be calculated by the amplitudes of the shifts in the Cg-Vg curve. The correctness of this method is proved by TCAD simulations. Moreover, experiments on devices stressed by unclamped-inductive-switching (UIS) stress and negative bias temperature stress (NBTS) are performed to verify the validity of this method.

Synthesis Methods, Microscopy Characterization and Device Integration of Nanoscale Metal Oxide Semiconductors for Gas Sensing

PubMed Central

Vander Wal, Randy L.; Berger, Gordon M.; Kulis, Michael J.; Hunter, Gary W.; Xu, Jennifer C.; Evans, Laura

2009-01-01

A comparison is made between SnO2, ZnO, and TiO2 single-crystal nanowires and SnO2 polycrystalline nanofibers for gas sensing. Both nanostructures possess a one-dimensional morphology. Different synthesis methods are used to produce these materials: thermal evaporation-condensation (TEC), controlled oxidation, and electrospinning. Advantages and limitations of each technique are listed. Practical issues associated with harvesting, purification, and integration of these materials into sensing devices are detailed. For comparison to the nascent form, these sensing materials are surface coated with Pd and Pt nanoparticles. Gas sensing tests, with respect to H2, are conducted at ambient and elevated temperatures. Comparative normalized responses and time constants for the catalyst and noncatalyst systems provide a basis for identification of the superior metal-oxide nanostructure and catalyst combination. With temperature-dependent data, Arrhenius analyses are made to determine activation energies for the catalyst-assisted systems. PMID:22408484

Large bandgap reduced graphene oxide (rGO) based n-p + heterojunction photodetector with improved NIR performance

NASA Astrophysics Data System (ADS)

Singh, Manjri; Kumar, Gaurav; Prakash, Nisha; Khanna, Suraj P.; Pal, Prabir; Singh, Surinder P.

2018-04-01

Integration of two-dimensional reduced graphene oxide (rGO) with conventional Si semiconductor offers novel strategies for realizing broadband photodiode with enhanced device performance. In this quest, we have synthesized large bandgap rGO and fabricated metal-free broadband (300–1100 nm) back-to-back connected np-pn hybrid photodetector utilizing drop casted n-rGO/p +-Si heterojunctions with high performance in NIR region (830 nm). With controlled illumination, the device exhibited a peak responsivity of 16.7 A W‑1 and peak detectivity of 2.56 × 1012 Jones under 830 nm illumination (11 μW cm‑2) at 1 V applied bias with fast response (∼460 μs) and recovery time (∼446 μs). The fabricated device demonstrated excellent repeatability, durability and photoswitching behavior with high external quantum efficiency (∼2.5 × 103%), along with ultrasensitive behavior at low light conditions.

Self Assembly and Interface Engineering of Organic Functional Materials for High Performance Polymer Solar Cells

NASA Astrophysics Data System (ADS)

Jen, Alex

2010-03-01

The performance of polymer solar cells are strongly dependent on the efficiency of light harvesting, exciton dissociation, charge transport, and charge collection at the metal/organic, metal/metal oxide, and organic/metal oxide interfaces. To improve the device performance, two parallel approaches were used: 1) developing novel low band gap conjugated polymers with good charge-transporting properties and 2) modifying the interfaces between the organic/metal oxide and organic/metal layers with functional self-assembling monolayers to tune their energy barriers. Moreover, the molecule engineering approach was also used to tune the energy level, charge mobility, and morphology of organic semiconductors.

Microgravity

NASA Image and Video Library

1999-11-10

Space Vacuum Epitaxy Center works with industry and government laboratories to develop advanced thin film materials and devices by utilizing the most abundant free resource in orbit: the vacuum of space. SVEC, along with its affiliates, is developing semiconductor mid-IR lasers for environmental sensing and defense applications, high efficiency solar cells for space satellite applications, oxide thin films for computer memory applications, and ultra-hard thin film coatings for wear resistance in micro devices. Performance of these vacuum deposited thin film materials and devices can be enhanced by using the ultra-vacuum of space for which SVEC has developed the Wake Shield Facility---a free flying research platform dedicated to thin film materials development in space.

Microgravity

NASA Image and Video Library

2000-11-10

Space Vacuum Epitaxy Center works with industry and government laboratories to develop advanced thin film materials and devices by utilizing the most abundant free resource in orbit: the vacuum of space. SVEC, along with its affiliates, is developing semiconductor mid-IR lasers for environmental sensing and defense applications, high efficiency solar cells for space satellite applications, oxide thin films for computer memory applications, and ultra-hard thin film coatings for wear resistance in micro devices. Performance of these vacuum deposited thin film materials and devices can be enhanced by using the ultra-vacuum of space for which SVEC has developed the Wake Shield Facility---a free flying research platform dedicated to thin film materials development in space.

Impact of Air Filter Material on Metal Oxide Semiconductor (MOS) Device Characteristics in HF Vapor Environment

NASA Astrophysics Data System (ADS)

Hsiao, Chih-Wen; Lou, Jen-Chung; Yeh, Ching-Fa; Hsieh, Chih-Ming; Lin, Shiuan-Jeng; Kusumi, Toshio

2004-05-01

Airborne molecular contamination (AMC) is becoming increasingly important as devices are scaled down to the nanometer generation. Optimum ultra low penetration air (ULPA) filter technology can eliminate AMC. In a cleanroom, however, the acid vapor generated from the cleaning process may degrade the ULPA filter, releasing AMC to the air and the surface of wafers, degrading the electrical characteristics of devices. This work proposes the new PTFE ULPA filter, which is resistant to acid vapor corrosion, to solve this problem. Experimental results demonstrate that the PTFE ULPA filter can effectively eliminate the AMC and provide a very clean cleanroom environment.

Electrode-stress-induced nanoscale disorder in Si quantum electronic devices

DOE PAGES

Park, J.; Ahn, Y.; Tilka, J. A.; ...

2016-06-20

Disorder in the potential-energy landscape presents a major obstacle to the more rapid development of semiconductor quantum device technologies. We report a large-magnitude source of disorder, beyond commonly considered unintentional background doping or fixed charge in oxide layers: nanoscale strain fields induced by residual stresses in nanopatterned metal gates. Quantitative analysis of synchrotron coherent hard x-ray nanobeam diffraction patterns reveals gate-induced curvature and strains up to 0.03% in a buried Si quantum well within a Si/SiGe heterostructure. Furthermore, electrode stress presents both challenges to the design of devices and opportunities associated with the lateral manipulation of electronic energy levels.

Multifunctional Self-Assembled Monolayers for Organic Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Cernetic, Nathan

Organic field effect transistors (OFETs) have the potential to reach commercialization for a wide variety of applications such as active matrix display circuitry, chemical and biological sensing, radio-frequency identification devices and flexible electronics. In order to be commercially competitive with already at-market amorphous silicon devices, OFETs need to approach similar performance levels. Significant progress has been made in developing high performance organic semiconductors and dielectric materials. Additionally, a common route to improve the performance metric of OFETs is via interface modification at the critical dielectric/semiconductor and electrode/semiconductor interface which often play a significant role in charge transport properties. These metal oxide interfaces are typically modified with rationally designed multifunctional self-assembled monolayers. As means toward improving the performance metrics of OFETs, rationally designed multifunctional self-assembled monolayers are used to explore the relationship between surface energy, SAM order, and SAM dipole on OFET performance. The studies presented within are (1) development of a multifunctional SAM capable of simultaneously modifying dielectric and metal surface while maintaining compatibility with solution processed techniques (2) exploration of the relationship between SAM dipole and anchor group on graphene transistors, and (3) development of self-assembled monolayer field-effect transistor in which the traditional thick organic semiconductor is replaced by a rationally designed self-assembled monolayer semiconductor. The findings presented within represent advancement in the understanding of the influence of self-assembled monolayers on OFETs as well as progress towards rationally designed monolayer transistors.

Strain-based control of crystal anisotropy for perovskite oxides on semiconductor-based material

DOEpatents

McKee, Rodney Allen; Walker, Frederick Joseph

2000-01-01

A crystalline structure and a semiconductor device includes a substrate of a semiconductor-based material and a thin film of an anisotropic crystalline material epitaxially arranged upon the surface of the substrate so that the thin film couples to the underlying substrate and so that the geometries of substantially all of the unit cells of the thin film are arranged in a predisposed orientation relative to the substrate surface. The predisposition of the geometries of the unit cells of the thin film is responsible for a predisposed orientation of a directional-dependent quality, such as the dipole moment, of the unit cells. The predisposed orientation of the unit cell geometries are influenced by either a stressed or strained condition of the lattice at the interface between the thin film material and the substrate surface.

The fabrication of carbon nanotube field-effect transistors with semiconductors as the source and drain contact materials.

PubMed

Xiao, Z; Camino, F E

2009-04-01

Sb(2)Te(3) and Bi(2)Te(2)Se semiconductor materials were used as the source and drain contact materials in the fabrication of carbon nanotube field-effect transistors (CNTFETs). Ultra-purified single-walled carbon nanotubes (SWCNTs) were ultrasonically dispersed in N-methyl pyrrolidone solvent. Dielectrophoresis was used to deposit and align SWCNTs for fabrication of CNTFETs. The Sb(2)Te(3)- and Bi(2)Te(2)Se-based CNTFETs demonstrate p-type metal-oxide-silicon-like I-V curves with high on/off drain-source current ratio at large drain-source voltages and good saturation of drain-source current with increasing drain-source voltage. The fabrication process developed is novel and has general meaning, and could be used for the fabrication of SWCNT-based integrated devices and systems with semiconductor contact materials.

Plasma Properties of an Exploding Semiconductor Igniter

NASA Astrophysics Data System (ADS)

McGuirk, J. S.; Thomas, K. A.; Shaffer, E.; Malone, A. L.; Baginski, T.; Baginski, M. E.

1997-11-01

Requirements by the automotive industry for low-cost, pyrotechnic igniters for automotive airbags have led to the development of several semiconductor devices. The properties of the plasma produced by the vaporization of an exploding semiconductor are necessary in order to minimize the electrical energy requirements. This work considers two silicon-based semiconductor devices: the semiconductor bridge (SCB) and the semiconductor junction igniter both consisting of etched silicon with vapor deposited aluminum structures. Electrical current passing through the device heats a narrow junction region to the point of vaporization creating an aluminum and silicon low-temperature plasma. This work will investigate the electrical characteristics of both devices and infer the plasma properties. Furthermore optical spectral measurements will be taken of the exploding devices to estimate the temperature and density of the plasma.

Extremely long nonradiative relaxation of photoexcited graphane is greatly accelerated by oxidation: time-domain ab initio study.

PubMed

Nelson, Tammie R; Prezhdo, Oleg V

2013-03-06

Graphane and its derivatives are stable and extremely thin, wide band gap semiconductors that promise to replace conventional semiconductors in electronics, catalysis, and energy applications, greatly reducing device size and power consumption. In order to be useful, band-gap excitations in these materials should be long lived and nonradiative energy losses to heat should be slow. We use state-of-the-art nonadiabatic molecular dynamics combined with time-dependent density functional theory in order to determine the nonradiative lifetime and radiative line width of the lowest energy singlet excitations in pure and oxidized graphanes. We predict that pure graphane has a very long nonradiative decay time, on the order of 100 ns, while epoxy- and hydroxy-graphanes lose electronic excitation energy to heat 10-20 times faster. The luminescence line width is 1.5 times larger in pristine graphane compared to its oxidized forms, and at room temperature, it is on the order of 50 meV. Hydroxylation lowers graphane's band gap, while epoxidation increases the gap. The nonradiative decay and luminescence line width of pure graphane are governed by electron coupling to the 1200 cm(-1) vibrational mode. In the oxidized forms of graphane, the electronic excitations couple to a broad range of vibrational modes, rationalizing the more rapid nonradiative decay in these systems. The slow electron-phonon energy losses in graphane compared to other graphene derivatives, such as carbon nanotubes and nanoribbons, indicate that graphanes are excellent candidates for semiconductor applications.

Photochemical Hydrogen Doping Induced Embedded Two-Dimensional Metallic Channel Formation in InGaZnO at Room Temperature.

PubMed

Kim, Myeong-Ho; Lee, Young-Ahn; Kim, Jinseo; Park, Jucheol; Ahn, Seungbae; Jeon, Ki-Joon; Kim, Jeong Won; Choi, Duck-Kyun; Seo, Hyungtak

2015-10-27

The photochemical tunability of the charge-transport mechanism in metal-oxide semiconductors is of great interest since it may offer a facile but effective semiconductor-to-metal transition, which results from photochemically modified electronic structures for various oxide-based device applications. This might provide a feasible hydrogen (H)-radical doping to realize the effectively H-doped metal oxides, which has not been achieved by thermal and ion-implantation technique in a reliable and controllable way. In this study, we report a photochemical conversion of InGaZnO (IGZO) semiconductor to a transparent conductor via hydrogen doping to the local nanocrystallites formed at the IGZO/glass interface at room temperature. In contrast to thermal or ionic hydrogen doping, ultraviolet exposure of the IGZO surface promotes a photochemical reaction with H radical incorporation to surface metal-OH layer formation and bulk H-doping which acts as a tunable and stable highly doped n-type doping channel and turns IGZO to a transparent conductor. This results in the total conversion of carrier conduction property to the level of metallic conduction with sheet resistance of ∼16 Ω/□, room temperature Hall mobility of 11.8 cm(2) V(-1) sec(-1), the carrier concentration at ∼10(20) cm(-3) without any loss of optical transparency. We demonstrated successful applications of photochemically highly n-doped metal oxide via optical dose control to transparent conductor with excellent chemical and optical doping stability.

Outlook and emerging semiconducting materials for ambipolar transistors.

PubMed

Bisri, Satria Zulkarnaen; Piliego, Claudia; Gao, Jia; Loi, Maria Antonietta

2014-02-26

Ambipolar or bipolar transistors are transistors in which both holes and electrons are mobile inside the conducting channel. This device allows switching among several states: the hole-dominated on-state, the off-state, and the electron-dominated on-state. In the past year, it has attracted great interest in exotic semiconductors, such as organic semiconductors, nanostructured materials, and carbon nanotubes. The ability to utilize both holes and electrons inside one device opens new possibilities for the development of more compact complementary metal-oxide semiconductor (CMOS) circuits, and new kinds of optoelectronic device, namely, ambipolar light-emitting transistors. This progress report highlights the recent progresses in the field of ambipolar transistors, both from the fundamental physics and application viewpoints. Attention is devoted to the challenges that should be faced for the realization of ambipolar transistors with different material systems, beginning with the understanding of the importance of interface modification, which heavily affects injections and trapping of both holes and electrons. The recent development of advanced gating applications, including ionic liquid gating, that open up more possibility to realize ambipolar transport in materials in which one type of charge carrier is highly dominant is highlighted. Between the possible applications of ambipolar field-effect transistors, we focus on ambipolar light-emitting transistors. We put this new device in the framework of its prospective for general lightings, embedded displays, current-driven laser, as well as for photonics-electronics interconnection. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

PubMed

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Temperature Dependence of the Seebeck Coefficient in Zinc Oxide Thin Films

NASA Astrophysics Data System (ADS)

Noori, Amirreza; Masoumi, Saeed; Hashemi, Najmeh

2017-12-01

Thermoelectric devices are reliable tools for converting waste heat into electricity as they last long, produce no noise or vibration, have no moving elements, and their light weight makes them suitable for the outer space usage. Materials with high thermoelectric figure of merit (zT) have the most important role in the fabrication of efficient thermoelectric devices. Metal oxide semiconductors, specially zinc oxide has recently received attention as a material suitable for sensor, optoelectronic and thermoelectric device applications because of their wide direct bandgap, chemical stability, high-energy radiation endurance, transparency and acceptable zT. Understanding the thermoelectric properties of the undoped ZnO thin films can help design better ZnO-based devices. Here, we report the results of our experimental work on the thermoelectric properties of the undoped polycrystalline ZnO thin films. These films are deposited on alumina substrates by thermal evaporation of zinc in vacuum followed by a controlled oxidation process in air carried out at the 350-500 °C temperature range. The experimental setup including gradient heaters, thermometry system and Seebeck voltage measurement equipment for high resistance samples is described. Seebeck voltage and electrical resistivity of the samples are measured at different conditions. The observed temperature dependence of the Seebeck coefficient is discussed.

Controlling band alignments by artificial interface dipoles at perovskite heterointerfaces

DOE PAGES

Yajima, Takeaki; Hikita, Yasuyuki; Minohara, Makoto; ...

2015-04-07

The concept ‘the interface is the device' is embodied in a wide variety of interfacial electronic phenomena and associated applications in oxide materials, ranging from catalysts and clean energy systems to emerging multifunctional devices. Many device properties are defined by the band alignment, which is often influenced by interface dipoles. On the other hand, the ability to purposefully create and control interface dipoles is a relatively unexplored degree of freedom for perovskite oxides, which should be particularly effective for such ionic materials. Here we demonstrate tuning the band alignment in perovskite metal-semiconductor heterojunctions over a broad range of 1.7 eV.more » This is achieved by the insertion of positive or negative charges at the interface, and the resultant dipole formed by the induced screening charge. This approach can be broadly used in applications where decoupling the band alignment from the constituent work functions and electron affinities can enhance device functionality.« less

Photoelectrochemical processes in organic semiconductor: Ambipolar perylene diimide thin film

NASA Astrophysics Data System (ADS)

Kim, Jung Yong; Chung, In Jae

2018-03-01

A thin film of N,N‧-dioctadecyl-3,4,9,10-perylene tetracarboxylic diimide (PTCDI-C18) is spin-coated on indium tin oxide (ITO) glass. Using the PTCDI-C18/ITO electrode, we fabricate a photoelectrochemical cell with the ITO/PTCDI-C18/Redox Electrolyte/Pt configuration. The electrochemical properties of this device are investigated as a function of hydroquinone (HQ) concentration, bias voltage, and wavelength of light. Anodic photocurrent is observed at V ≥ -0.2 V vs. Ag/AgCl, indicating that the PTCDI-C18 film acts as an n-type semiconductor as usual. However, when benzoquinone (BQ) is inserted into the electrolyte system instead of HQ, cathodic photocurrent is observed at V ≤ 0.0 V, displaying that PTCDI-C18 abnormally serves as a p-type semiconductor. Hence the overall results reveal that the PTCDI-C18 film can be an ambipolar functional semiconductor depending on the redox couple in the appropriate voltage.

Synthesis and characterization of metal oxide semiconductors by a facile co-electroplating-annealing method and formation of ZnO/CuO pn heterojunctions with rectifying behavior

NASA Astrophysics Data System (ADS)

Turkdogan, Sunay; Kilic, Bayram

2018-01-01

We have developed a unique growth method and demonstrated the growth of CuO and ZnO semiconductor materials and the fabrication of their pn heterojunctions in ambient atmosphere. The pn heterojunctions were constructed using inherently p-type CuO and inherently n-type ZnO materials. Both p- and n-type semiconductors and pn heterojunctions were prepared using a simple but versatile growth method that relies on the transformation of electroplated Cu and Zn metals into CuO and ZnO semiconductors, respectively and is capable of a large-scale production desired in most of the applications. The structural, chemical, optical and electrical properties of the materials and junctions were investigated using various characterization methods and the results show that our growth method, materials and devices are quite promising to be utilized for various applications including but not limited to solar cells, gas/humidity sensors and photodetectors.

Electronic materials with a wide band gap: recent developments

PubMed Central

Klimm, Detlef

2014-01-01

The development of semiconductor electronics is reviewed briefly, beginning with the development of germanium devices (band gap E g = 0.66 eV) after World War II. A tendency towards alternative materials with wider band gaps quickly became apparent, starting with silicon (E g = 1.12 eV). This improved the signal-to-noise ratio for classical electronic applications. Both semiconductors have a tetrahedral coordination, and by isoelectronic alternative replacement of Ge or Si with carbon or various anions and cations, other semiconductors with wider E g were obtained. These are transparent to visible light and belong to the group of wide band gap semiconductors. Nowadays, some nitrides, especially GaN and AlN, are the most important materials for optical emission in the ultraviolet and blue regions. Oxide crystals, such as ZnO and β-Ga2O3, offer similarly good electronic properties but still suffer from significant difficulties in obtaining stable and technologically adequate p-type conductivity. PMID:25295170

Electrical Properties of Reactive Liquid Crystal Semiconductors

NASA Astrophysics Data System (ADS)

McCulloch, Iain; Coelle, Michael; Genevicius, Kristijonas; Hamilton, Rick; Heckmeier, Michael; Heeney, Martin; Kreouzis, Theo; Shkunov, Maxim; Zhang, Weimin

2008-01-01

Fabrication of display products by low cost printing technologies such as ink jet, gravure offset lithography and flexography requires solution processable semiconductors for the backplane electronics. The products will typically be of lower performance than polysilicon transistors, but comparable to amorphous silicon. A range of prototypes are under development, including rollable electrophoretic displays, active matrix liquid crystal displays (AMLCD's), and flexible organic light-emitting diode (OLED) displays. Organic semiconductors that offer both electrical performance and stability with respect to storage and operation under ambient conditions are required. This work describes the initial evaluation of reactive mesogen semiconductors, which can polymerise within mesophase temperatures, “freezing in” the order in crosslinked domains. These crosslinked domains offer mechanical stability and are inert to solvent exposure in further processing steps. Reactive mesogens containing conjugated aromatic cores, designed to facilitate charge transport and provide good oxidative stability, were prepared and their liquid crystalline properties evaluated. Both time-of-flight and field effect transistor devices were prepared and their electrical characterisation reported.

Lithography for enabling advances in integrated circuits and devices.

PubMed

Garner, C Michael

2012-08-28

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

Contact formation and gettering of precipitated impurities by multiple firing during semiconductor device fabrication

DOEpatents

Sopori, Bhushan

2014-05-27

Methods for contact formation and gettering of precipitated impurities by multiple firing during semiconductor device fabrication are provided. In one embodiment, a method for fabricating an electrical semiconductor device comprises: a first step that includes gettering of impurities from a semiconductor wafer and forming a backsurface field; and a second step that includes forming a front contact for the semiconductor wafer, wherein the second step is performed after completion of the first step.

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Lin, H. C.; Yang, T.; Sharifi, H.; Kim, S. K.; Xuan, Y.; Shen, T.; Mohammadi, S.; Ye, P. D.

2007-11-01

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with ex situ atomic-layer-deposited Al2O3 as gate dielectrics are studied. Maximum drain currents of 211 and 263mA/mm are obtained for 1μm gate-length Al2O3 MOS-HEMTs with 3 and 6nm thick gate oxide, respectively. C-V characteristic shows negligible hysteresis and frequency dispersion. The gate leakage current density of the MOS-HEMTs is 3-5 orders of magnitude lower than the conventional HEMTs under similar bias conditions. The drain current on-off ratio of MOS-HEMTs is ˜3×103 with a subthreshold swing of 90mV/decade. A maximum cutoff frequency (fT) of 27.3GHz and maximum oscillation frequency (fmax) of 39.9GHz and an effective channel mobility of 4250cm2/Vs are measured for the 1μm gate-length Al2O3 MOS-HEMT with 6nm gate oxide. Hooge's constant measured by low frequency noise spectral density characterization is 3.7×10-5 for the same device.

The Use of Ion Implantation for Materials Processing.

DTIC Science & Technology

1980-10-06

consists of a series of sections, each section being an annular insulator (glass) and a shaped metal electrode (polished aluminum ) cemented together. A...depending on the ion species, semiconductor material, attached materials (such as aluminum leads), implantation energy, and dose; but some devices are...concentration of subsurface carbon. Appearing directly beneath the oxide layer, the C concentration first reaches a maximum of about five times the bulk

Automatic illumination compensation device based on a photoelectrochemical biofuel cell driven by visible light

NASA Astrophysics Data System (ADS)

Yu, You; Han, Yanchao; Xu, Miao; Zhang, Lingling; Dong, Shaojun

2016-04-01

Inverted illumination compensation is important in energy-saving projects, artificial photosynthesis and some forms of agriculture, such as hydroponics. However, only a few illumination adjustments based on self-powered biodetectors that quantitatively detect the intensity of visible light have been reported. We constructed an automatic illumination compensation device based on a photoelectrochemical biofuel cell (PBFC) driven by visible light. The PBFC consisted of a glucose dehydrogenase modified bioanode and a p-type semiconductor cuprous oxide photocathode. The PBFC had a high power output of 161.4 μW cm-2 and an open circuit potential that responded rapidly to visible light. It adjusted the amount of illumination inversely irrespective of how the external illumination was changed. This rational design of utilizing PBFCs provides new insights into automatic light adjustable devices and may be of benefit to intelligent applications.Inverted illumination compensation is important in energy-saving projects, artificial photosynthesis and some forms of agriculture, such as hydroponics. However, only a few illumination adjustments based on self-powered biodetectors that quantitatively detect the intensity of visible light have been reported. We constructed an automatic illumination compensation device based on a photoelectrochemical biofuel cell (PBFC) driven by visible light. The PBFC consisted of a glucose dehydrogenase modified bioanode and a p-type semiconductor cuprous oxide photocathode. The PBFC had a high power output of 161.4 μW cm-2 and an open circuit potential that responded rapidly to visible light. It adjusted the amount of illumination inversely irrespective of how the external illumination was changed. This rational design of utilizing PBFCs provides new insights into automatic light adjustable devices and may be of benefit to intelligent applications. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr00759g

Nanoscale characterization of the electrical properties of oxide electrodes at the organic semiconductor-oxide electrode interface in organic solar cells

NASA Astrophysics Data System (ADS)

MacDonald, Gordon Alex

This dissertation focuses on characterizing the nanoscale and surface averaged electrical properties of transparent conducting oxide electrodes such as indium tin oxide (ITO) and transparent metal-oxide (MO) electron selective interlayers (ESLs), such as zinc oxide (ZnO), the ability of these materials to rapidly extract photogenerated charges from organic semiconductors (OSCs) used in organic photovoltaic (OPV) cells, and evaluating their impact on the power conversion efficiency (PCE) of OPV devices. In Chapter 1, we will introduce the fundamental principles, benefits, and the key innovations that have advanced this technology. In Chapter 2 of this dissertation, we demonstrate an innovative application of conductive probe atomic force microscopy (CAFM) to map the nanoscale electrical heterogeneity at the interface between ITO, and a well-studied OSC, copper phthalocyanine (CuPc).(MacDonald et al. (2012) ACS Nano, 6, p. 9623) In this work we collected arrays of current-voltage (J-V) curves, using a CAFM probe as the top contact of CuPc/ITO systems, to map the local J-V responses. By comparing J-V responses to known models for charge transport, we were able to determine if the local rate-limiting-step for charge transport is through the OSC (ohmic) or the CuPc/ITO interface (non-ohmic). Chapter 3 focus on the electrical property characterization of RF-magnetron sputtered ZnO (sp-ZnO) ESL films on ITO substrates. We have shown that the energetic alignment of ESLs and the OSC active materials plays a critical role in determining the PCE of OPV devices and UV light soaking sensitivity. We have used a combination of device testing, modeling, and impedance spectroscopy to characterize the effects that energetic alignment has on the charge carrier transport and distribution within the OPV device. In Chapter 4 we demonstrate that the local properties of sp-ZnO films varies as a function of the underlying ITO crystal face. We show that the local ITO crystal face determines the local nucleation and growth of the sp-ZnO films and, in turn, affects the nanoscale distribution of electrical and chemical properties. These studies have contributed to a detailed understanding of the role that electrical heterogeneity, insulating barriers and energetic alignment at MO/OSC interfaces play in OPV PCE.

Organic-Inorganic Hybrid Halide Perovskites for Memories, Transistors, and Artificial Synapses.

PubMed

Choi, Jaeho; Han, Ji Su; Hong, Kootak; Kim, Soo Young; Jang, Ho Won

2018-05-30

Fascinating characteristics of halide perovskites (HPs), which cannot be seen in conventional semiconductors and metal oxides, have boosted the application of HPs in electronic devices beyond optoelectronics such as solar cells, photodetectors, and light-emitting diodes. Here, recent advances in HP-based memory and logic devices such as resistive-switching memories (i.e., resistive random access memory (RRAM) or memristors), transistors, and artificial synapses are reviewed, focusing on inherently exotic properties of HPs: i) tunable bandgap, ii) facile majority carrier control, iii) fast ion migration, and iv) superflexibility. Various fabrication techniques of HP thin films from solution-based methods to vacuum processes are introduced. Up-to-date work in the field, emphasizing the compositional flexibility of HPs, suggest that HPs are promising candidates for next-generation electronic devices. Taking advantages of their unique electrical properties, low-cost and low-temperature synthesis, and compositional and mechanical flexibility, HPs have enormous potential to provide a new platform for future electronic devices and explosively intensive studies will pave the way in finding new HP materials beyond conventional silicon-based semiconductors to keep up with "More-than-Moore" times. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Ge/IIIV fin field-effect transistor common gate process and numerical simulations

NASA Astrophysics Data System (ADS)

Chen, Bo-Yuan; Chen, Jiann-Lin; Chu, Chun-Lin; Luo, Guang-Li; Lee, Shyong; Chang, Edward Yi

2017-04-01

This study investigates the manufacturing process of thermal atomic layer deposition (ALD) and analyzes its thermal and physical mechanisms. Moreover, experimental observations and computational fluid dynamics (CFD) are both used to investigate the formation and deposition rate of a film for precisely controlling the thickness and structure of the deposited material. First, the design of the TALD system model is analyzed, and then CFD is used to simulate the optimal parameters, such as gas flow and the thermal, pressure, and concentration fields, in the manufacturing process to assist the fabrication of oxide-semiconductors and devices based on them, and to improve their characteristics. In addition, the experiment applies ALD to grow films on Ge and GaAs substrates with three-dimensional (3-D) transistors having high electric performance. The electrical analysis of dielectric properties, leakage current density, and trapped charges for the transistors is conducted by high- and low-frequency measurement instruments to determine the optimal conditions for 3-D device fabrication. It is anticipated that the competitive strength of such devices in the semiconductor industry will be enhanced by the reduction of cost and improvement of device performance through these optimizations.

Study of thickness and uniformity of oxide passivation with DI-O3 on silicon substrate for electronic and photonic applications

NASA Astrophysics Data System (ADS)

Sharma, Mamta; Hazra, Purnima; Singh, Satyendra Kumar

2018-05-01

Since the beginning of semiconductor fabrication technology evolution, clean and passivated substrate surface is one of the prime requirements for fabrication of Electronic and optoelectronic device fabrication. However, as the scale of silicon circuits and device architectures are continuously decreased from micrometer to nanometer (from VLSI to ULSI technology), the cleaning methods to achieve better wafer surface qualities has raised research interests. The development of controlled and uniform silicon dioxide is the most effective and reliable way to achieve better wafer surface quality for fabrication of electronic devices. On the other hand, in order to meet the requirement of high environment safety/regulatory standards, the innovation of cleaning technology is also in demand. The controlled silicon dioxide layer formed by oxidant de-ionized ozonated water has better uniformity. As the uniformity of the controlled silicon dioxide layer is improved on the substrate, it enhances the performance of the devices. We can increase the thickness of oxide layer, by increasing the ozone time treatment. We reported first time to measurement of thickness of controlled silicon dioxide layer and obtained the uniform layer for same ozone time.

Tuning the Seebeck effect in C60-based hybrid thermoelectric devices through temperature-dependent surface polarization and thermally-modulated interface dipoles.

PubMed

Liu, Yuchun; Xu, Ling; Zhao, Chen; Shao, Ming; Hu, Bin

2017-06-07

Fullerene (C 60 ) is an important n-type organic semiconductor with high electron mobility and low thermal conductivity. In this work, we report the experimental results on the tunable Seebeck effect of C 60 hybrid thin-film devices by adopting different oxide layers. After inserting n-type high-dielectric constant titanium oxide (TiO x ) and zinc oxide (ZnO) layers, we observed a significantly enhanced n-type Seebeck effect in oxide/C 60 hybrid devices with Seebeck coefficients of -5.8 mV K -1 for TiO x /C 60 and -2.08 mV K -1 for ZnO/C 60 devices at 100 °C, compared with the value of -400 μV K -1 for the pristine C 60 device. However, when a p-type nickel oxide (NiO) layer is inserted, the C 60 hybrid devices show a p-type to n-type Seebeck effect transition when the temperature increases. The remarkable Seebeck effect and change in Seebeck coefficient in different oxide/C 60 hybrid devices can be attributed to two reasons: the temperature-dependent surface polarization difference and thermally-dependent interface dipoles. Firstly, the surface polarization difference due to temperature-dependent electron-phonon coupling can be enhanced by inserting an oxide layer and functions as an additional driving force for the Seebeck effect development. Secondly, thermally-dependent interface dipoles formed at the electrode/oxide interface play an important role in modifying the density of interface states and affecting the charge diffusion in hybrid devices. The surface polarization difference and interface dipoles function in the same direction in hybrid devices with TiO x and ZnO dielectric layers, leading to enhanced n-type Seebeck effect, while the surface polarization difference and interface dipoles generate the opposite impact on electron diffusion in ITO/NiO/C 60 /Al, leading to a p-type to n-type transition in the Seebeck effect. Therefore, inserting different oxide layers could effectively modulate the Seebeck effect of C 60 -based hybrid devices through the surface polarization difference and thermally-dependent interface dipoles, which represents an effective approach to tune the vertical Seebeck effect in organic functional devices.

Technique for producing highly planar Si/SiO0.64Ge0.36/Si metal-oxide-semiconductor field effect transistor channels

NASA Astrophysics Data System (ADS)

Grasby, T. J.; Parry, C. P.; Phillips, P. J.; McGregor, B. M.; Morris, , R. J. H.; Braithwaite, G.; Whall, T. E.; Parker, E. H. C.; Hammond, R.; Knights, A. P.; Coleman, P. G.

1999-03-01

Si/Si0.64Ge0.36/Si heterostructures have been grown at low temperature (450 °C) to avoid the strain-induced roughening observed for growth temperatures of 550 °C and above. The electrical properties of these structures are poor, and thought to be associated with grown-in point defects as indicated in positron annihilation spectroscopy. However, after an in situ annealing procedure (800 °C for 30 min) the electrical properties dramatically improve, giving an optimum 4 K mobility of 2500 cm2 V-1 s-1 for a sheet density of 6.2×1011 cm-2. The low temperature growth yields highly planar interfaces, which are maintained after anneal as evidenced from transmission electron microscopy. This and secondary ion mass spectroscopy measurements demonstrate that the metastably strained alloy layer can endure the in situ anneal procedure necessary for enhanced electrical properties. Further studies have shown that the layers can also withstand a 120 min thermal oxidation at 800 °C, commensurate with metal-oxide-semiconductor device fabrication.

Questing and the application for silicon based ternary compound within ultra-thin layer of SIS intermediate region

NASA Astrophysics Data System (ADS)

Chen, Shumin; Gao, Ming; Wan, Yazhou; Du, Huiwei; Li, Yong; Ma, Zhongquan

2016-12-01

A silicon based ternary compound was supposed to be solid synthesized with In, Si and O elements by magnetron sputtering of indium tin oxide target (ITO) onto crystal silicon substrate at 250 °C. To make clear the configuration of the intermediate region, a potential method to obtain the chemical bonding of Si with other existing elements was exploited by X-ray photoelectron spectroscopy (XPS) instrument combined with other assisted techniques. The phase composition and solid structure of the interfacial region between ITO and Si substrate were investigated by X-ray diffraction (XRD) and high resolution cross sectional transmission electron microscope (HR-TEM). A photovoltaic device with structure of Al/Ag/ITO/SiOx/p-Si/Al was assembled by depositing ITO films onto the p-Si substrate by using magnetron sputtering. The new matter has been assumed to be a buffer layer for semiconductor-insulator-semiconductor (SIS) photovoltaic device and plays critical role for the promotion of optoelectronic conversion performance from the view point of device physics.

Effective enhancement of hydrophilicity of solution indium zinc oxide-based thin-film transistors by oxygen plasma treatment of deposition layer surface

NASA Astrophysics Data System (ADS)

You, Hsin-Chiang; Wang, Yu-Chih

2016-06-01

In this paper, we describe the use of a simple and efficient sol-gel solution method for synthesizing indium zinc oxide (IZO) films for use as semiconductor channel layers in thin-film transistors (TFTs) on p-type silicon substrates. The performance of IZO-based TFTs was investigated, and the effect of oxygen plasma treatment on the surface of dielectric SiN x was observed. Oxygen plasma treatment effectively enhanced the electron mobility in IZO-based TFT devices from 0.005 to 1.56 cm2 V-1 s-1, an increase of more than 312 times, and effectively enhanced device performance. X-ray photoelectron spectroscopy analysis of the IZO film was performed to clarify element bonding.

Fabrication of Smooth Patterned Structures of Refractory Metals, Semiconductors, and Oxides via Template Stripping

PubMed Central

2013-01-01

The template-stripping method can yield smooth patterned films without surface contamination. However, the process is typically limited to coinage metals such as silver and gold because other materials cannot be readily stripped from silicon templates due to strong adhesion. Herein, we report a more general template-stripping method that is applicable to a larger variety of materials, including refractory metals, semiconductors, and oxides. To address the adhesion issue, we introduce a thin gold layer between the template and the deposited materials. After peeling off the combined film from the template, the gold layer can be selectively removed via wet etching to reveal a smooth patterned structure of the desired material. Further, we demonstrate template-stripped multilayer structures that have potential applications for photovoltaics and solar absorbers. An entire patterned device, which can include a transparent conductor, semiconductor absorber, and back contact, can be fabricated. Since our approach can also produce many copies of the patterned structure with high fidelity by reusing the template, a low-cost and high-throughput process in micro- and nanofabrication is provided that is useful for electronics, plasmonics, and nanophotonics. PMID:24001174

Direct observation of oxygen-vacancy-enhanced polarization in a SrTiO 3-buffered ferroelectric BaTiO 3 film on GaAs

DOE PAGES

Qiao, Q.; Zhang, Y.; Contreras-Guerrero, Rocio; ...

2015-11-16

The integration of functional oxide thin-films on compound semiconductors can lead to a class of reconfigurable spin-based optoelectronic devices if defect-free, fully reversible active layers are stabilized. However, previous first-principles calculations predicted that SrTiO 3 thin filmsgrown on Si exhibit pinned ferroelectric behavior that is not switchable, due to the presence of interfacial vacancies. Meanwhile, piezoresponse force microscopy measurements have demonstrated ferroelectricity in BaTiO 3 grown on semiconductor substrates. The presence of interfacial oxygen vacancies in such complex-oxide/semiconductor systems remains unexplored, and their effect on ferroelectricity is controversial. We also use a combination of aberration-corrected scanning transmission electron microscopy andmore » first-principles density functional theory modeling to examine the role of interfacial oxygen vacancies on the ferroelectricpolarization of a BaTiO 3 thin filmgrown on GaAs. Moreover, we demonstrate that interfacial oxygen vacancies enhance the polar discontinuity (and thus the single domain, out-of-plane polarization pinning in BaTiO 3), and propose that the presence of surface charge screening allows the formation of switchable domains.« less

Spontaneously formed high-performance charge-transport layers of organic single-crystal semiconductors on precisely synthesized insulating polymers

NASA Astrophysics Data System (ADS)

Makita, Tatsuyuki; Sasaki, Masayuki; Annaka, Tatsuro; Sasaki, Mari; Matsui, Hiroyuki; Mitsui, Chikahiko; Kumagai, Shohei; Watanabe, Shun; Hayakawa, Teruaki; Okamoto, Toshihiro; Takeya, Jun

2017-04-01

Charge-transporting semiconductor layers with high carrier mobility and low trap-density, desired for high-performance organic transistors, are spontaneously formed as a result of thermodynamic phase separation from a blend of π-conjugated small molecules and precisely synthesized insulating polymers dissolved in an aromatic solvent. A crystal film grows continuously to the size of centimeters, with the critical conditions of temperature, concentrations, and atmosphere. It turns out that the molecular weight of the insulating polymers plays an essential role in stable film growth and interfacial homogeneity at the phase separation boundary. Fabricating the transistor devices directly at the semiconductor-insulator boundaries, we demonstrate that the mixture of 3,11-didecyldinaphtho[2,3-d:2',3'-d']benzo[1,2-b:4,5-b']dithiophene and poly(methyl methacrylate) with the optimized weight-average molecular weight shows excellent device performances. The spontaneous phase separation with a one-step fabrication process leads to a high mobility up to 10 cm2 V-1 s-1 and a low subthreshold swing of 0.25 V dec-1 even without any surface treatment such as self-assembled monolayer modifications on oxide gate insulators.

Enhancement of ZnO based flexible nano generators via sol gel technique for sensing and energy harvesting applications.

PubMed

Rajagopalan, Pandey; Singh, Vipul; I A, Palani

2018-01-10

Zinc oxide (ZnO) is a remarkable inorganic semiconductor with exceptional piezoelectric properties compared to other semiconductors. However, in comparison to lead-based hazardous piezoelectric materials, its features have undesired limitations. Here we report the 5~6 folds enhancement in the piezoelectric properties via chemical doping of copper matched to intrinsic ZnO. The flexible piezoelectric nanogenerator (F-PENG) device was fabricated using an unpretentious solution process of spin coating with other advantages like robust, low weight, improved adhesion, and low cost. The devices were used to demonstrate energy harvesting from a Standard weight as low as 4 gm and can work as a self-powered mass sensor in a broad range of 4 to 100 gm. The device exhibited a novel energy harvesting technique from a wind source due to its inherent flexibility. At three different velocities (10~30 m/s) and five different angles of attack (0~180 degrees), the device validated the ability to discern different velocities and directions of flow. The device will be useful for mapping the flow of air apart from harvesting the energy. The simulation was done to verify the underlining mechanism of aerodynamics involved in it. © 2018 IOP Publishing Ltd.

Electronic excitation induced defect dynamics in HfO2 based MOS devices investigated by in-situ electrical measurements

NASA Astrophysics Data System (ADS)

Manikanthababu, N.; Vajandar, S.; Arun, N.; Pathak, A. P.; Asokan, K.; Osipowicz, T.; Basu, T.; Nageswara Rao, S. V. S.

2018-03-01

In-situ I-V and C-V characterization studies were carried out to determine the device quality of atomic layer deposited HfO2 (2.7 nm)/SiO2 (0.6 nm)/Si-based metal oxide semiconductor devices during 120 MeV Ag ion irradiation. The influence of various tunneling mechanisms has been investigated by analyzing the I-V characteristics as a function of ion fluence. The nature of the defects created is tentatively identified by the determination of the significant tunneling processes. While the ion induced annealing of defects is observed at lower fluences, ion induced intermixing and radiation damage is found to be significant at higher fluences. The C-V characteristics also reveal significant changes at the interface and oxide trap densities: an increase in the oxide layer thickness occurs through the formation of an HfSiO interlayer. The interlayer is due to the swift heavy ion induced intermixing, which has been confirmed by X-TEM and X-ray photoelectron spectroscopy measurements.

Cross-plane electrical and thermal transport in oxide metal/semiconductor superlattices

NASA Astrophysics Data System (ADS)

Jha, Pankaj

Perovskite oxides display a rich variety of electronic properties as metals, ferroelectrics, ferromagnetics, multiferroics, and thermoelectrics. Cross-plane electron filtering transport in metal/semiconductor superlattices provides a potential approach to increase the thermoelectric figure of merit (ZT). La0.67Sr0.33MnO3 (LSMO) and LaMnO3 (LMO) thin-film depositions were optimized using pulsed laser deposition (PLD) to achieve low resistivity constituent materials for LSMO/LMO superlattice heterostructures on (100)-strontium titanate (STO) substrates. X-ray diffraction and high-resolution reciprocal space mapping (RSM) indicate that the superlattices are epitaxial and pseudomorphic. Cross-plane devices were fabricated by etching cylindrical pillar structures in superlattices using inductively-coupled-plasma reactive-ion etching. The cross-plane electrical conductivity data for LSMO/LMO superlattices reveal an effective barrier height of 220 meV. The cross-plane LSMO/LMO superlattices showed a giant Seebeck coefficient of 2560 microV/K at 300K that increases to 16640 microV/K at 360K. The large Seebeck coefficient may arise due to hot electron and spin filtering as LSMO/LMO superlattice constituent materials exhibit spintronic properties where charges and spin current are intertwined and can generate a spin-Seebeck effect. The room temperature thermal conductivity achieved in low resistivity superlattices was 0.92 W/mK, which indicates that cross-plane phonon scattering at interfaces reduces the lattice contribution to the thermal conductivity. The giant contribution of spin-Seebeck, the large temperature dependence of the cross-plane power factor, and the low thermal conductivity in low resistance LSMO/LMO superlattices may offer opportunities to realize spin-magnetic thermoelectric devices, and suggests a direction for further investigations of the potential of LSMO/LMO oxide superlattices for thermoelectric devices.

Micromechanical Structures Fabrication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rajic, S

2001-05-08

Work in materials other than silicon for MEMS applications has typically been restricted to metals and metal oxides instead of more ''exotic'' semiconductors. However, group III-V and II-VI semiconductors form a very important and versatile collection of material and electronic parameters available to the MEMS and MOEMS designer. With these materials, not only are the traditional mechanical material variables (thermal conductivity, thermal expansion, Young's modulus, etc.) available, but also chemical constituents can be varied in ternary and quaternary materials. This flexibility can be extremely important for both friction and chemical compatibility issues for MEMS. In addition, the ability to continuallymore » vary the bandgap energy can be particularly useful for many electronics and infrared detection applications. However, there are two major obstacles associated with alternate semiconductor material MEMS. The first issue is the actual fabrication of non-silicon micro-devices and the second impediment is communicating with these novel devices. We have implemented an essentially material independent fabrication method that is amenable to most group III-V and II-VI semiconductors. This technique uses a combination of non-traditional direct write precision fabrication processes such as diamond turning, ion milling, laser ablation, etc. This type of deterministic fabrication approach lends itself to an almost trivial assembly process. We also implemented a mechanical, electrical, and optical self-aligning hybridization technique for these alternate-material MEMS substrates.« less

Novel Fabrication and Simple Hybridization of Exotic Material MEMS

DOE Office of Scientific and Technical Information (OSTI.GOV)

Datskos, P.G.; Rajic, S.

1999-11-13

Work in materials other than silicon for MEMS applications has typically been restricted to metals and metal oxides instead of more ''exotic'' semiconductors. However, group III-V and II-VI semiconductors form a very important and versatile collection of material and electronic parameters available to the MEMS and MOEMS designer. With these materials, not only are the traditional mechanical material variables (thermal conductivity, thermal expansion, Young's modulus, etc.) available, but also chemical constituents can be varied in ternary and quaternary materials. This flexibility can be extremely important for both friction and chemical compatibility issues for MEMS. In addition, the ability to continuallymore » vary the bandgap energy can be particularly useful for many electronics and infrared detection applications. However, there are two major obstacles associated with alternate semiconductor material MEMS. The first issue is the actual fabrication of non-silicon devices and the second impediment is communicating with these novel devices. We will describe an essentially material independent fabrication method that is amenable to most group III-V and II-VI semiconductors. This technique uses a combination of non-traditional direct write precision fabrication processes such as diamond turning, ion milling, laser ablation, etc. This type of deterministic fabrication approach lends itself to an almost trivial assembly process. We will also describe in detail the mechanical, electrical, and optical self-aligning hybridization technique used for these alternate-material MEMS.« less

Effects of Lightning Injection on Power-MOSFETs

NASA Technical Reports Server (NTRS)

Celaya, Jose; Saha, Sankalita; Wysocki, Phil; Ely, Jay; Nguyen, Truong; Szatkowski, George; Koppen, Sandra; Mielnik, John; Vaughan, Roger; Goebel, Kai

2009-01-01

Lightning induced damage is one of the major concerns in aircraft health monitoring. Such short-duration high voltages can cause significant damage to electronic devices. This paper presents a study on the effects of lightning injection on power metal-oxide semiconductor field effect transistors (MOSFETs). This approach consisted of pin-injecting lightning waveforms into the gate, drain and/or source of MOSFET devices while they were in the OFF-state. Analysis of the characteristic curves of the devices showed that for certain injection modes the devices can accumulate considerable damage rendering them inoperable. Early results demonstrate that a power MOSFET, even in its off-state, can incur considerable damage due to lightning pin injection, leading to significant deviation in its behavior and performance, and to possibly early device failures.

Electroluminescent devices formed using semiconductor nanocrystals as an electron transport media and method of making such electroluminescent devices

DOEpatents

Alivisatos, A. Paul; Colvin, Vickie

1996-01-01

An electroluminescent device is described, as well as a method of making same, wherein the device is characterized by a semiconductor nanocrystal electron transport layer capable of emitting visible light in response to a voltage applied to the device. The wavelength of the light emitted by the device may be changed by changing either the size or the type of semiconductor nanocrystals used in forming the electron transport layer. In a preferred embodiment the device is further characterized by the capability of emitting visible light of varying wavelengths in response to changes in the voltage applied to the device. The device comprises a hole processing structure capable of injecting and transporting holes, and usually comprising a hole injecting layer and a hole transporting layer; an electron transport layer in contact with the hole processing structure and comprising one or more layers of semiconductor nanocrystals; and an electron injecting layer in contact with the electron transport layer for injecting electrons into the electron transport layer. The capability of emitting visible light of various wavelengths is principally based on the variations in voltage applied thereto, but the type of semiconductor nanocrystals used and the size of the semiconductor nanocrystals in the layers of semiconductor nanometer crystals may also play a role in color change, in combination with the change in voltage.

Cathode for an electrochemical cell

DOEpatents

Bates, John B.; Dudney, Nancy J.; Gruzalski, Greg R.; Luck, Christopher F.

2001-01-01

Described is a thin-film battery, especially a thin-film microbattery, and a method for making same having application as a backup or primary integrated power source for electronic devices. The battery includes a novel electrolyte which is electrochemically stable and does not react with the lithium anode and a novel vanadium oxide cathode. Configured as a microbattery, the battery can be fabricated directly onto a semiconductor chip, onto the semiconductor die or onto any portion of the chip carrier. The battery can be fabricated to any specified size or shape to meet the requirements of a particular application. The battery is fabricated of solid state materials and is capable of operation between -15.degree. C. and 150.degree. C.

Method for making an electrochemical cell

DOEpatents

Bates, John B.; Dudney, Nancy J.

1996-01-01

Described is a thin-film battery, especially a thin-film microbattery, and a method for making same having application as a backup or primary integrated power source for electronic devices. The battery includes a novel electrolyte which is electrochemically stable and does not react with the lithium anode and a novel vanadium oxide cathode Configured as a microbattery, the battery can be fabricated directly onto a semiconductor chip, onto the semiconductor die or onto any portion of the chip carrier. The battery can be fabricated to any specified size or shape to meet the requirements of a particular application. The battery is fabricated of solid state materials and is capable of operation between -15.degree. C. and 150.degree. C.

Vertical III-V nanowire device integration on Si(100).

PubMed

Borg, Mattias; Schmid, Heinz; Moselund, Kirsten E; Signorello, Giorgio; Gignac, Lynne; Bruley, John; Breslin, Chris; Das Kanungo, Pratyush; Werner, Peter; Riel, Heike

2014-01-01

We report complementary metal-oxide-semiconductor (CMOS)-compatible integration of compound semiconductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO2 nanotube templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si-InAs heterojunction nanowire tunnel diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process.

Surface modification using low energy ground state ion beams

NASA Technical Reports Server (NTRS)

Chutjian, Ara (Inventor); Hecht, Michael H. (Inventor); Orient, Otto J. (Inventor)

1990-01-01

A method of effecting modifications at the surfaces of materials using low energy ion beams of known quantum state, purity, flux, and energy is presented. The ion beam is obtained by bombarding ion-generating molecules with electrons which are also at low energy. The electrons used to bombard the ion generating molecules are separated from the ions thus obtained and the ion beam is directed at the material surface to be modified. Depending on the type of ion generating molecules used, different ions can be obtained for different types of surface modifications such as oxidation and diamond film formation. One area of application is in the manufacture of semiconductor devices from semiconductor wafers.

Dual passivation of intrinsic defects at the compound semiconductor/oxide interface using an oxidant and a reductant.

PubMed

Kent, Tyler; Chagarov, Evgeniy; Edmonds, Mary; Droopad, Ravi; Kummel, Andrew C

2015-05-26

Studies have shown that metal oxide semiconductor field-effect transistors fabricated utilizing compound semiconductors as the channel are limited in their electrical performance. This is attributed to imperfections at the semiconductor/oxide interface which cause electronic trap states, resulting in inefficient modulation of the Fermi level. The physical origin of these states is still debated mainly because of the difficulty in assigning a particular electronic state to a specific physical defect. To gain insight into the exact source of the electronic trap states, density functional theory was employed to model the intrinsic physical defects on the InGaAs (2 × 4) surface and to model the effective passivation of these defects by utilizing both an oxidant and a reductant to eliminate metallic bonds and dangling-bond-induced strain at the interface. Scanning tunneling microscopy and spectroscopy were employed to experimentally determine the physical and electronic defects and to verify the effectiveness of dual passivation with an oxidant and a reductant. While subsurface chemisorption of oxidants on compound semiconductor substrates can be detrimental, it has been shown theoretically and experimentally that oxidants are critical to removing metallic defects at oxide/compound semiconductor interfaces present in nanoscale channels, oxides, and other nanostructures.

Charge Transport in Low-Temperature Processed Thin-Film Transistors Based on Indium Oxide/Zinc Oxide Heterostructures.

PubMed

Krausmann, Jan; Sanctis, Shawn; Engstler, Jörg; Luysberg, Martina; Bruns, Michael; Schneider, Jörg J

2018-06-20

The influence of the composition within multilayered heterostructure oxide semiconductors has a critical impact on the performance of thin-film transistor (TFT) devices. The heterostructures, comprising alternating polycrystalline indium oxide and zinc oxide layers, are fabricated by a facile atomic layer deposition (ALD) process, enabling the tuning of its electrical properties by precisely controlling the thickness of the individual layers. This subsequently results in enhanced TFT performance for the optimized stacked architecture after mild thermal annealing at temperatures as low as 200 °C. Superior transistor characteristics, resulting in an average field-effect mobility (μ sat. ) of 9.3 cm 2 V -1 s -1 ( W/ L = 500), an on/off ratio ( I on / I off ) of 5.3 × 10 9 , and a subthreshold swing of 162 mV dec -1 , combined with excellent long-term and bias stress stability are thus demonstrated. Moreover, the inherent semiconducting mechanism in such multilayered heterostructures can be conveniently tuned by controlling the thickness of the individual layers. Herein, devices comprising a higher In 2 O 3 /ZnO ratio, based on individual layer thicknesses, are predominantly governed by percolation conduction with temperature-independent charge carrier mobility. Careful adjustment of the individual oxide layer thicknesses in devices composed of stacked layers plays a vital role in the reduction of trap states, both interfacial and bulk, which consequently deteriorates the overall device performance. The findings enable an improved understanding of the correlation between TFT performance and the respective thin-film composition in ALD-based heterostructure oxides.

Bonding Cu to Al2O3 with Bi-B-Zn Oxide Glass Via Oxidation-Reduction Reaction

NASA Astrophysics Data System (ADS)

Chen, Jianqiang; Li, Yufeng; Miao, Weiliang; Mai, Chengle; Li, Mingyu

2018-01-01

Bonding Cu on Al2O3 is a key and difficult technology applied in high-power semiconductor devices. A method proposed in this work investigates bonding with a kind of Bi-B-Zn oxide glass powder paste as a solder. Oxidation-reduction reactions between the Cu plate and the solder took place and generated Bi metal during the joining procedure. With an increase in the joining temperature, the tensile strength increased due to the increase of Bi metal formation. The Bi metal played an important role in joining Cu and Al2O3 because of its much better wettability on Cu than that of the oxides. A compound ZnAl2O4 was observed to form between the Al2O3 ceramic and oxide layer, which strengthened the bond.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shi, Zhemin; Department of Physical Electronics, Tokyo Institute of Technology, 2-12-1 O-okayama, Meguro-ku, Tokyo 152-8552; Taguchi, Dai

The details of turnover process of spontaneous polarization and associated carrier motions in indium-tin oxide/poly-(vinylidene-trifluoroethylene)/pentacene/Au capacitor were analyzed by coupling displacement current measurement (DCM) and electric-field-induced optical second-harmonic generation (EFISHG) measurement. A model was set up from DCM results to depict the relationship between electric field in semiconductor layer and applied external voltage, proving that photo illumination effect on the spontaneous polarization process lied in variation of semiconductor conductivity. The EFISHG measurement directly and selectively probed the electric field distribution in semiconductor layer, modifying the model and revealing detailed carrier behaviors involving photo illumination effect, dipole reversal, and interfacial chargingmore » in the device. A further decrease of DCM current in the low voltage region under illumination was found as the result of illumination effect, and the result was argued based on the changing of the total capacitance of the double-layer capacitors.« less

Effect of top-down nanomachining on electrical conduction properties of TiO2 nanostructure-based chemical sensors.

PubMed

Francioso, L; De Pascali, C; Capone, S; Siciliano, P

2012-03-09

The present research was motivated by the growing interest of the scientific community towards the understanding of basic gas-surface interaction mechanisms in 1D nanostructured metal oxide semiconductors, whose significantly enhanced chemical detection sensitivity is known. In this work, impedance spectroscopy (IS) was used to evaluate how a top-down patterning of the sensitive layer can modulate the electrical properties of a gas sensor based on a fully integrated nanometric array of TiO(2) polycrystalline strips. The aim of the study was supported by comparative experimental activity carried out on different thin film gas sensors based on identical TiO(2) polycrystalline sensitive thin films. The impedance responses of the investigated devices under dry air (as the reference environment) and ethanol vapors (as the target gas) were fitted by a complex nonlinear least-squares method using LEVM software, in order to find an appropriate equivalent circuit describing the main conduction processes involved in the gas/semiconductor interactions. Two different equivalent circuit models were identified as completely representative of the TiO(2) thin film and the TiO(2) nanostructure-based gas sensors, respectively. All the circuit parameters were quantified and the related standard deviations were evaluated. The simulated results well approximated the experimental data as indicated by the small mean errors of the fits (in the range of 10(-4)) and the small standard deviations of the circuit parameters. In addition to the substrate capacitance, three different contributions to the overall conduction mechanism were identified for both equivalent circuits: bulk conductivity, intergrain contact and semiconductor-electrode contact, electrically represented by an ideal resistor R(g), a parallel R(gb)C(gb) block and a parallel R(c)-CPE(c) combination, respectively. In terms of equivalent circuit modeling, the sensitive layer patterning introduced an additional parameter in parallel connection with the whole circuit block. Such a circuit element (an ideal inductor, L) has an average value of about 125 μH and exhibits no direct dependence on the analyte gas concentration. Its presence could be due to complex mutual inductance effects occurring both between all the adjacent nanostrips (10 µm spaced) and between the nanostrips and the n-type-doped silicon substrate underneath the thermal oxide (wire/plate effect), where a two order of magnitude higher magnetic permeability of silicon can give L values comparable with those estimated by the fitting procedure. Slightly modified experimental models confirmed that the theoretical background, regulating thin film devices based on metal oxide semiconductors, is also valid for nanopatterned devices.

Synthesis of visible-light responsive graphene oxide/TiO(2) composites with p/n heterojunction.

PubMed

Chen, Chao; Cai, Weimin; Long, Mingce; Zhou, Baoxue; Wu, Yahui; Wu, Deyong; Feng, Yujie

2010-11-23

Graphene oxide/TiO(2) composites were prepared by using TiCl(3) and graphene oxide as reactants. The concentration of graphene oxide in starting solution played an important role in photoelectronic and photocatalytic performance of graphene oxide/TiO(2) composites. Either a p-type or n-type semiconductor was formed by graphene oxide in graphene oxide/TiO(2) composites. These semiconductors could be excited by visible light with wavelengths longer than 510 nm and acted as sensitizer in graphene oxide/TiO(2) composites. Visible-light driven photocatalytic performance of graphene oxide/TiO(2) composites in degradation of methyl orange was also studied. Crystalline quality and chemical states of carbon elements from graphene oxide in graphene oxide/TiO(2) composites depended on the concentration of graphene oxide in the starting solution. This study shows a possible way to fabricate graphene oxide/semiconductor composites with different properties by using a tunable semiconductor conductivity type of graphene oxide.

Electro-mechanical coupling of semiconductor film grown on stainless steel by oxidation

NASA Astrophysics Data System (ADS)

Lin, M. C.; Wang, G.; Guo, L. Q.; Qiao, L. J.; Volinsky, Alex A.

2013-09-01

Electro-mechanical coupling phenomenon in oxidation film on stainless steel has been discovered by using current-sensing atomic force microscopy, along with the I-V curves measurements. The oxidation films exhibit either ohmic, n-type, or p-type semiconductor properties, according to the obtained I-V curves. This technique allows characterizing oxidation films with high spatial resolution. Semiconductor properties of oxidation films must be considered as additional stress corrosion cracking mechanisms.

1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

NASA Astrophysics Data System (ADS)

Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

Method and apparatus for use of III-nitride wide bandgap semiconductors in optical communications

DOEpatents

Hui, Rongqing [Lenexa, KS; Jiang, Hong-Xing [Manhattan, KS; Lin, Jing-Yu [Manhattan, KS

2008-03-18

The present disclosure relates to the use of III-nitride wide bandgap semiconductor materials for optical communications. In one embodiment, an optical device includes an optical waveguide device fabricated using a III-nitride semiconductor material. The III-nitride semiconductor material provides for an electrically controllable refractive index. The optical waveguide device provides for high speed optical communications in an infrared wavelength region. In one embodiment, an optical amplifier is provided using optical coatings at the facet ends of a waveguide formed of erbium-doped III-nitride semiconductor materials.

Modeling of Sonos Memory Cell Erase Cycle

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memories (NVSMS) have many advantages. These memories are electrically erasable programmable read-only memories (EEPROMs). They utilize low programming voltages, endure extended erase/write cycles, are inherently resistant to radiation, and are compatible with high-density scaled CMOS for low power, portable electronics. The SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. The SONOS floating gate charge and voltage, tunneling current, threshold voltage, and drain current were characterized during an erase cycle. Comparisons were made between the model predictions and experimental device data.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang, Chan-Shan; Chemical Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720; Tang, Tsung-Ta

Indium Tin Oxide (ITO) nanowhiskers (NWhs) obliquely evaporated by electron-beam glancing-angle deposition can serve simultaneously as transparent electrodes and alignment layer for liquid crystal (LC) devices in the terahertz (THz) frequency range. To demonstrate, we constructed a THz LC phase shifter with ITO NWhs. Phase shift exceeding π/2 at 1.0 THz was achieved in a ∼517 μm-thick cell. The phase shifter exhibits high transmittance (∼78%). The driving voltage required for quarter-wave operation is as low as 5.66 V (rms), compatible with complementary metal-oxide-semiconductor (CMOS) and thin-film transistor (TFT) technologies.

Modelling switching-time effects in high-frequency power conditioning networks

NASA Technical Reports Server (NTRS)

Owen, H. A.; Sloane, T. H.; Rimer, B. H.; Wilson, T. G.

1979-01-01

Power transistor networks which switch large currents in highly inductive environments are beginning to find application in the hundred kilohertz switching frequency range. Recent developments in the fabrication of metal-oxide-semiconductor field-effect transistors in the power device category have enhanced the movement toward higher switching frequencies. Models for switching devices and of the circuits in which they are imbedded are required to properly characterize the mechanisms responsible for turning on and turning off effects. Easily interpreted results in the form of oscilloscope-like plots assist in understanding the effects of parametric studies using topology oriented computer-aided analysis methods.

Solar energy conversion in a photoelectrochemical biofuel cell.

PubMed

Hambourger, Michael; Kodis, Gerdenis; Vaughn, Michael D; Moore, Gary F; Gust, Devens; Moore, Ana L; Moore, Thomas A

2009-12-07

A photoelectrochemical biofuel cell has been developed which incorporates aspects of both an enzymatic biofuel cell and a dye-sensitized solar cell. Photon absorption at a porphyrin-sensitized n-type semiconductor electrode gives rise to a charge-separated state. Electrons and holes are shuttled to appropriate cathodic and anodic catalysts, respectively, allowing the production of electricity, or a reduced fuel, via the photochemical oxidation of a biomass-derived substrate. The operation of this device is reviewed. The use of alternate anodic redox mediators provides insight regarding loss mechanisms in the device. Design strategies for enhanced performance are discussed.

A webcam in Bayer-mode as a light beam profiler for the near infra-red

PubMed Central

Langer, Gregor; Hochreiner, Armin; Burgholzer, Peter; Berer, Thomas

2013-01-01

Beam profiles are commonly measured with complementary metal oxide semiconductors (CMOS) or charge coupled devices (CCD). The devices are fast and reliable but expensive. By making use of the fact that the Bayer-filter in commercial webcams is transparent in the near infra-red (>800 nm) and their CCD chips are sensitive up to about 1100 nm, we demonstrate a cheap and simple way to measure laser beam profiles with a resolution down to around ±1 μm, which is close to the resolution of the knife-edge technique. PMID:23645943

A webcam in Bayer-mode as a light beam profiler for the near infra-red.

PubMed

Langer, Gregor; Hochreiner, Armin; Burgholzer, Peter; Berer, Thomas

2013-05-01

Beam profiles are commonly measured with complementary metal oxide semiconductors (CMOS) or charge coupled devices (CCD). The devices are fast and reliable but expensive. By making use of the fact that the Bayer-filter in commercial webcams is transparent in the near infra-red (>800 nm) and their CCD chips are sensitive up to about 1100 nm, we demonstrate a cheap and simple way to measure laser beam profiles with a resolution down to around ±1 μm, which is close to the resolution of the knife-edge technique.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Park, J.; Ahn, Y.; Tilka, J. A.

Disorder in the potential-energy landscape presents a major obstacle to the more rapid development of semiconductor quantum device technologies. We report a large-magnitude source of disorder, beyond commonly considered unintentional background doping or fixed charge in oxide layers: nanoscale strain fields induced by residual stresses in nanopatterned metal gates. Quantitative analysis of synchrotron coherent hard x-ray nanobeam diffraction patterns reveals gate-induced curvature and strains up to 0.03% in a buried Si quantum well within a Si/SiGe heterostructure. Furthermore, electrode stress presents both challenges to the design of devices and opportunities associated with the lateral manipulation of electronic energy levels.

Prediction and measurement of radiation damage to CMOS devices on board spacecraft

NASA Technical Reports Server (NTRS)

Cliff, R. A.; Danchenko, V.; Stassinopoulos, E. G.; Sing, M.; Brucker, G. J.; Ohanian, R. S.

1976-01-01

The initial results obtained from the Complementary Metal Oxide Semiconductors Radiation Effects Measurement experiment are presented. Predictions of radiation damage to C-MOS devices are based on standard environment models and computational techniques. A comparison of the shifts in CMOS threshold potentials, that is, those measured in space to those obtained from the on the ground simulation experiment with Co 60, indicated that the measured space damage is greater than predicted by a factor of two for shields thicker than 100 mils (2.54 mm), but agrees well with predictions for the thinner shields.

Modeling of Nano-Scale Transistors and Memory Devices for Low Power Applications

NASA Astrophysics Data System (ADS)

Cao, Xi

As the featuring size of transistors scaled down to sub-20 nm, the continuous scaling of power has become one of the main challenges of the semiconductor industry. The power issue is raised by the barely scalable supply voltage and a limitation on the subthreshold swing (SS) of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, self-consistent quantum transport device simulators are developed to examine the nanoscale transistors based on black phosphorus (BP) materials. The scaling limit of double-gated BP MOSFETs is assessed. To reduce the SS below the thermionic limit for ultra-steep switching, tunnel FETs (TFETs) and vertical ballistic impact ionization FETs based on BP and its heterojunctions are investigated. Furthermore, the ferroelectric tunneling junction (FTJ) is modeled and examined for potential low power memory applications. For BP MOSFETs, the device physics at the ultimate scaling limit are examined. The performance of monolayer BP MOSFETs is projected to sub-10 nm and compared with the International Technology Roadmap for Semiconductors (ITRS) requirements. And the interplay of quantum mechanical effects and the highly anisotropic bandstructure of BP at this scale is investigated. By choice of layer number and crystalline direction, BP materials can offer a range of bandgap and effective mass values, which is attractive for TFET applications. Therefore, scaling behaviors of BP TFETs near and below the 10 nm scale are studied. The gate oxide thickness scaling and the effect of high-k dielectric are compared between the TFETs and the MOSFETs. For the TFETs with the gate lengths beyond 10 nm and at the sub-10 nm scale, the direct-source-to-drain tunneling issues are evaluated, and different strategies to achieve ultra-steep switching are specified. In a sub-10 nm graphene-BP-graphene heterojunction transistor, the sharp turnon behavior was observed, under a small source-drain bias of 0.1 V. The fast switch is attributed to a ballistic energy-dependent impact ionization mechanism. A device model is developed, which shows agreement with experiment results. The model is applied to explore the gate oxide scaling behavior and the effect of graphene doping, and to optimize the device for low power applications. Finally, to keep the integrity of the computing system, the FTJ is studied for its possible use as a low power memory device. A compact model for FTJ, dealing with both static and dynamic behaviors, is developed and compared with experimental data. The write energy consumed by the memory cell, comprising one transistor and one FTJ, is estimated by applying the compact model to circuit simulation. And a way to reduce the write energy is suggested.

An Autonomous Circuit for the Measurement of Photovoltaic Devices Parameters.

DTIC Science & Technology

1986-09-01

Comparison Data, Gallium Arsenide ................ 80 A 7 A,. TABLE OF SYMBOLS A Curve Fitting Constant ADC Analog to Digital Converter AMO Air-Mass-Zero...in Radiation Fluence in the Logarithmic Region CMOS Complementary Metal-Oxide Semiconductor DAC Digital to Analog Converter DC Direct Current Dp Hole...characteristics of individual solar cells. A novel circuit is developed that uses a microprocessor controlled Digital to Analog Converter (DAC) to obtain

Functional integrity of flexible n-channel metal-oxide-semiconductor field-effect transistors on a reversibly bistable platform

NASA Astrophysics Data System (ADS)

Alfaraj, Nasir; Hussain, Aftab M.; Torres Sevilla, Galo A.; Ghoneim, Mohamed T.; Rojas, Jhonathan P.; Aljedaani, Abdulrahman B.; Hussain, Muhammad M.

2015-10-01

Flexibility can bring a new dimension to state-of-the-art electronics, such as rollable displays and integrated circuit systems being transformed into more powerful resources. Flexible electronics are typically hosted on polymeric substrates. Such substrates can be bent and rolled up, but cannot be independently fixed at the rigid perpendicular position necessary to realize rollable display-integrated gadgets and electronics. A reversibly bistable material can assume two stable states in a reversible way: flexibly rolled state and independently unbent state. Such materials are used in cycling and biking safety wristbands and a variety of ankle bracelets for orthopedic healthcare. They are often wrapped around an object with high impulsive force loading. Here, we study the effects of cumulative impulsive force loading on thinned (25 μm) flexible silicon-based n-channel metal-oxide-semiconductor field-effect transistor devices housed on a reversibly bistable flexible platform. We found that the transistors have maintained their high performance level up to an accumulated 180 kN of impact force loading. The gate dielectric layers have maintained their reliability, which is evidenced by the low leakage current densities. Also, we observed low variation in the effective electron mobility values, which manifests that the device channels have maintained their carrier transport properties.

A Distance Detector with a Strip Magnetic MOSFET and Readout Circuit.

PubMed

Sung, Guo-Ming; Lin, Wen-Sheng; Wang, Hsing-Kuang

2017-01-10

This paper presents a distance detector composed of two separated metal-oxide semiconductor field-effect transistors (MOSFETs), a differential polysilicon cross-shaped Hall plate (CSHP), and a readout circuit. The distance detector was fabricated using 0.18 μm 1P6M Complementary Metal-Oxide Semiconductor (CMOS) technology to sense the magnetic induction perpendicular to the chip surface. The differential polysilicon CSHP enabled the magnetic device to not only increase the magnetosensitivity but also eliminate the offset voltage generated because of device mismatch and Lorentz force. Two MOSFETs generated two drain currents with a quadratic function of the differential Hall voltages at CSHP. A readout circuit-composed of a current-to-voltage converter, a low-pass filter, and a difference amplifier-was designed to amplify the current difference between two drains of MOSFETs. Measurements revealed that the electrostatic discharge (ESD) could be eliminated from the distance sensor by grounding it to earth; however, the sensor could be desensitized by ESD in the absence of grounding. The magnetic influence can be ignored if the magnetic body (human) stays far from the magnetic sensor, and the measuring system is grounded to earth by using the ESD wrist strap (Strap E-GND). Both 'no grounding' and 'grounding to power supply' conditions were unsuitable for measuring the induced Hall voltage.

Methods of forming semiconductor devices and devices formed using such methods

DOEpatents

Fox, Robert V; Rodriguez, Rene G; Pak, Joshua

2013-05-21

Single source precursors are subjected to carbon dioxide to form particles of material. The carbon dioxide may be in a supercritical state. Single source precursors also may be subjected to supercritical fluids other than supercritical carbon dioxide to form particles of material. The methods may be used to form nanoparticles. In some embodiments, the methods are used to form chalcopyrite materials. Devices such as, for example, semiconductor devices may be fabricated that include such particles. Methods of forming semiconductor devices include subjecting single source precursors to carbon dioxide to form particles of semiconductor material, and establishing electrical contact between the particles and an electrode.

Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

NASA Astrophysics Data System (ADS)

Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

2003-05-01

Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

Potentials and challenges of integration for complex metal oxides in CMOS devices and beyond

NASA Astrophysics Data System (ADS)

Kim, Y.; Pham, C.; Chang, J. P.

2015-02-01

This review focuses on recent accomplishments on complex metal oxide based multifunctional materials and the potential they hold in advancing integrated circuits. It begins with metal oxide based high-κ materials to highlight the success of their integration since 45 nm complementary metal-oxide-semiconductor (CMOS) devices. By simultaneously offering a higher dielectric constant for improved capacitance as well as providing a thicker physical layer to prevent the quantum mechanical tunnelling of electrons, high-κ materials have enabled the continued down-scaling of CMOS based devices. The most recent technology driver has been the demand to lower device power consumption, which requires the design and synthesis of novel materials, such as complex metal oxides that exhibit remarkable tunability in their ferromagnetic, ferroelectric and multiferroic properties. These properties make them suitable for a wide variety of applications such as magnetoelectric random access memory, radio frequency band pass filters, antennae and magnetic sensors. Single-phase multiferroics, while rare, offer unique functionalities which have motivated much scientific and technological research to ascertain the origins of their multiferroicity and their applicability to potential devices. However, due to the weak magnetoelectric coupling for single-phase multiferroics, engineered multiferroic composites based on magnetostrictive ferromagnets interfacing piezoelectrics or ferroelectrics have shown enhanced multiferroic behaviour from effective strain coupling at the interface. In addition, nanostructuring of the ferroic phases has demonstrated further improvement in the coupling effect. Therefore, single-phase and engineered composite multiferroics consisting of complex metal oxides are reviewed in terms of magnetoelectric coupling effects and voltage controlled ferromagnetic properties, followed by a review on the integration challenges that need to be overcome to realize the materials’ full potential.

Coincident site lattice-matched growth of semiconductors on substrates using compliant buffer layers

DOEpatents

Norman, Andrew

2016-08-23

A method of producing semiconductor materials and devices that incorporate the semiconductor materials are provided. In particular, a method is provided of producing a semiconductor material, such as a III-V semiconductor, on a silicon substrate using a compliant buffer layer, and devices such as photovoltaic cells that incorporate the semiconductor materials. The compliant buffer material and semiconductor materials may be deposited using coincident site lattice-matching epitaxy, resulting in a close degree of lattice matching between the substrate material and deposited material for a wide variety of material compositions. The coincident site lattice matching epitaxial process, as well as the use of a ductile buffer material, reduce the internal stresses and associated crystal defects within the deposited semiconductor materials fabricated using the disclosed method. As a result, the semiconductor devices provided herein possess enhanced performance characteristics due to a relatively low density of crystal defects.

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2012 CFR

2012-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2013 CFR

2013-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2014 CFR

2014-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

Photoemission-based microelectronic devices

PubMed Central

Forati, Ebrahim; Dill, Tyler J.; Tao, Andrea R.; Sievenpiper, Dan

2016-01-01

The vast majority of modern microelectronic devices rely on carriers within semiconductors due to their integrability. Therefore, the performance of these devices is limited due to natural semiconductor properties such as band gap and electron velocity. Replacing the semiconductor channel in conventional microelectronic devices with a gas or vacuum channel may scale their speed, wavelength and power beyond what is available today. However, liberating electrons into gas/vacuum in a practical microelectronic device is quite challenging. It often requires heating, applying high voltages, or using lasers with short wavelengths or high powers. Here, we show that the interaction between an engineered resonant surface and a low-power infrared laser can cause enough photoemission via electron tunnelling to implement feasible microelectronic devices such as transistors, switches and modulators. The proposed photoemission-based devices benefit from the advantages of gas-plasma/vacuum electronic devices while preserving the integrability of semiconductor-based devices. PMID:27811946

A graphene solution to conductivity mismatch: spin injection from ferromagnetic metal/graphene tunnel contacts into silicon

NASA Astrophysics Data System (ADS)

van't Erve, Olaf

2014-03-01

New paradigms for spin-based devices, such as spin-FETs and reconfigurable logic, have been proposed and modeled. These devices rely on electron spin being injected, transported, manipulated and detected in a semiconductor channel. This work is the first demonstration on how a single layer of graphene can be used as a low resistance tunnel barrier solution for electrical spin injection into Silicon at room temperature. We will show that a FM metal / monolayer graphene contact serves as a spin-polarized tunnel barrier which successfully circumvents the classic metal / semiconductor conductivity mismatch issue for electrical spin injection. We demonstrate electrical injection and detection of spin accumulation in Si above room temperature, and show that the corresponding spin lifetimes correlate with the Si carrier concentration, confirming that the spin accumulation measured occurs in the Si and not in interface trap states. An ideal tunnel barrier should exhibit several key material characteristics: a uniform and planar habit with well-controlled thickness, minimal defect / trapped charge density, a low resistance-area product for minimal power consumption, and compatibility with both the FM metal and semiconductor, insuring minimal diffusion to/from the surrounding materials at temperatures required for device processing. Graphene, offers all of the above, while preserving spin injection properties, making it a compelling solution to the conductivity mismatch for spin injection into Si. Although Graphene is very conductive in plane, it exhibits poor conductivity perpendicular to the plane. Its sp2 bonding results in a highly uniform, defect free layer, which is chemically inert, thermally robust, and essentially impervious to diffusion. The use of a single monolayer of graphene at the Si interface provides a much lower RA product than any film of an oxide thick enough to prevent pinholes (1 nm). Our results identify a new route to low resistance-area product spin-polarized contacts, a crucial requirement enabling future semiconductor spintronic devices, which rely upon two-terminal magnetoresistance, including spin-based transistors, logic and memory.

Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, Kurt D.; Bai, Yibin; Ryu, Kevin K.; Gregory, James A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winters, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2015-10-01

We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.

Effect of forming gas annealing on the degradation properties of Ge-based MOS stacks

NASA Astrophysics Data System (ADS)

Aguirre, F.; Pazos, S.; Palumbo, F. R. M.; Fadida, S.; Winter, R.; Eizenberg, M.

2018-04-01

The influence of forming gas annealing on the degradation at a constant stress voltage of multi-layered germanium-based Metal-Oxide-Semiconductor capacitors (p-Ge/GeOx/Al2O3/High-K/Metal Gate) has been analyzed in terms of the C-V hysteresis and flat band voltage as a function of both negative and positive stress fields. Significant differences were found for the case of negative voltage stress between the annealed and non-annealed samples, independently of the stressing time. It was found that the hole trapping effect decreases in the case of the forming gas annealed samples, indicating strong passivation of defects with energies close to the valence band existing in the oxide-semiconductor interface during the forming gas annealing. Finally, a comparison between the degradation dynamics of Germanium and III-V (n-InGaAs) MOS stacks is presented to summarize the main challenges in the integration of reliable Ge-III-V hybrid devices.

Determination of bulk and interface density of states in metal oxide semiconductor thin-film transistors by using capacitance-voltage characteristics

NASA Astrophysics Data System (ADS)

Wei, Xixiong; Deng, Wanling; Fang, Jielin; Ma, Xiaoyu; Huang, Junkai

2017-10-01

A physical-based straightforward extraction technique for interface and bulk density of states in metal oxide semiconductor thin film transistors (TFTs) is proposed by using the capacitance-voltage (C-V) characteristics. The interface trap density distribution with energy has been extracted from the analysis of capacitance-voltage characteristics. Using the obtained interface state distribution, the bulk trap density has been determined. With this method, for the interface trap density, it is found that deep state density nearing the mid-gap is approximately constant and tail states density increases exponentially with energy; for the bulk trap density, it is a superposition of exponential deep states and exponential tail states. The validity of the extraction is verified by comparisons with the measured current-voltage (I-V) characteristics and the simulation results by the technology computer-aided design (TCAD) model. This extraction method uses non-numerical iteration which is simple, fast and accurate. Therefore, it is very useful for TFT device characterization.

Ultralow-power complementary metal-oxide-semiconductor inverters constructed on Schottky barrier modified nanowire metal-oxide-semiconductor field-effect-transistors.

PubMed

Ma, R M; Peng, R M; Wen, X N; Dai, L; Liu, C; Sun, T; Xu, W J; Qin, G G

2010-10-01

We show that the threshold voltages of both n- and p-channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) can be lowered to close to zero by adding extra Schottky contacts on top of nanowires (NWs). Novel complementary metal-oxide-semiconductor (CMOS) inverters are constructed on these Schottky barrier modified n- and p-channel NW MOSFETs. Based on the high performances of the modified n- and p-channel MOSFETs, especially the low threshold voltages, the as-fabricated CMOS inverters have low operating voltage, high voltage gain, and ultra-low static power dissipation.

Towards zero-power ICT.

PubMed

Gammaitoni, Luca; Chiuchiú, D; Madami, M; Carlotti, G

2015-06-05

Is it possible to operate a computing device with zero energy expenditure? This question, once considered just an academic dilemma, has recently become strategic for the future of information and communication technology. In fact, in the last forty years the semiconductor industry has been driven by its ability to scale down the size of the complementary metal-oxide semiconductor-field-effect transistor, the building block of present computing devices, and to increase computing capability density up to a point where the power dissipated in heat during computation has become a serious limitation. To overcome such a limitation, since 2004 the Nanoelectronics Research Initiative has launched a grand challenge to address the fundamental limits of the physics of switches. In Europe, the European Commission has recently funded a set of projects with the aim of minimizing the energy consumption of computing. In this article we briefly review state-of-the-art zero-power computing, with special attention paid to the aspects of energy dissipation at the micro- and nanoscales.

Towards zero-power ICT

NASA Astrophysics Data System (ADS)

Gammaitoni, Luca; Chiuchiú, D.; Madami, M.; Carlotti, G.

2015-06-01

Is it possible to operate a computing device with zero energy expenditure? This question, once considered just an academic dilemma, has recently become strategic for the future of information and communication technology. In fact, in the last forty years the semiconductor industry has been driven by its ability to scale down the size of the complementary metal-oxide semiconductor-field-effect transistor, the building block of present computing devices, and to increase computing capability density up to a point where the power dissipated in heat during computation has become a serious limitation. To overcome such a limitation, since 2004 the Nanoelectronics Research Initiative has launched a grand challenge to address the fundamental limits of the physics of switches. In Europe, the European Commission has recently funded a set of projects with the aim of minimizing the energy consumption of computing. In this article we briefly review state-of-the-art zero-power computing, with special attention paid to the aspects of energy dissipation at the micro- and nanoscales.

Near-infrared light emitting device using semiconductor nanocrystals

DOE Office of Scientific and Technical Information (OSTI.GOV)

Supran, Geoffrey J.S.; Song, Katherine W.; Hwang, Gyuweon

A near-infrared light emitting device can include semiconductor nanocrystals that emit at wavelengths beyond 1 .mu.m. The semiconductor nanocrystals can include a core and an overcoating on a surface of the core.

Introduction to Semiconductor Devices

NASA Astrophysics Data System (ADS)

Brennan, Kevin F.

2005-03-01

This volume offers a solid foundation for understanding the most important devices used in the hottest areas of electronic engineering today, from semiconductor fundamentals to state-of-the-art semiconductor devices in the telecommunications and computing industries. Kevin Brennan describes future approaches to computing hardware and RF power amplifiers, and explains how emerging trends and system demands of computing and telecommunications systems influence the choice, design and operation of semiconductor devices. In addition, he covers MODFETs and MOSFETs, short channel effects, and the challenges faced by continuing miniaturization. His book is both an excellent senior/graduate text and a valuable reference for practicing engineers and researchers.

Interface composition of InAs nanowires with Al2O3 and HfO2 thin films

NASA Astrophysics Data System (ADS)

Timm, R.; Hjort, M.; Fian, A.; Borg, B. M.; Thelander, C.; Andersen, J. N.; Wernersson, L.-E.; Mikkelsen, A.

2011-11-01

Vertical InAs nanowires (NWs) wrapped by a thin high-κ dielectric layer may be a key to the next generation of high-speed metal-oxide-semiconductor devices. Here, we have investigated the structure and chemical composition of the interface between InAs NWs and 2 nm thick Al2O3 and HfO2 films. The native oxide on the NWs is significantly reduced upon high-κ deposition, although less effective than for corresponding planar samples, resulting in a 0.8 nm thick interface layer with an In-/As-oxide composition of about 0.7/0.3. The exact oxide reduction and composition including As-suboxides and the role of the NW geometry are discussed in detail.

Latchup in CMOS devices from heavy ions

NASA Technical Reports Server (NTRS)

Soliman, K.; Nichols, D. K.

1983-01-01

It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

NASA Astrophysics Data System (ADS)

Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

2018-02-01

In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

Synthesis Methods, Microscopy Characterization and Device Integration of Nanoscale Metal Oxide Semiconductors for Gas Sensing in Aerospace Applications

NASA Technical Reports Server (NTRS)

VanderWal, Randy L.; Berger, Gordon M.; Kulis, Michael J.; Hunter, Gary W.; Xu, Jennifer C.; Evans, Laura J.

2009-01-01

A comparison is made between SnO2, ZnO, and TiO2 single-crystal nanowires and SnO2 polycrystalline nanofibers for gas sensing. Both nanostructures possess a one-dimensional morphology. Different synthesis methods are used to produce these materials: thermal evaporation-condensation (TEC), controlled oxidation, and electrospinning. Advantages and limitations of each technique are listed. Practical issues associated with harvesting, purification, and integration of these materials into sensing devices are detailed. For comparison to the nascent form, these sensing materials are surface coated with Pd and Pt nanoparticles. Gas sensing tests, with respect to H2, are conducted at ambient and elevated temperatures. Comparative normalized responses and time constants for the catalyst and noncatalyst systems provide a basis for identification of the superior metal-oxide nanostructure and catalyst combination. With temperature-dependent data, Arrhenius analyses are made to determine an activation energy for the catalyst-assisted systems.

The effect of doping on low temperature growth of high quality GaAs nanowires on polycrystalline films

PubMed Central

DeJarld, Matt; Teran, Alan; Luengo-Kovac, Marta; Yan, Lifan; Moon, Eun Seong; Beck, Sara; Guillen, Cristina; Sih, Vanessa; Phillips, Jamie; Milunchick, Joanna Mirecki

2016-01-01

The increasing demand for miniature autonomous sensors requires low cost integration methods, but to date, material limitations have prevented the direct growth of optically active III-V materials on CMOS devices. We report on the deposition of GaAs nanowires on polycrystalline conductive films to allow for direct integration of optoelectronic devices on dissimilar materials. Undoped, Si-doped, and Be-doped nanowires were grown at Ts=400°C on oxide (indium tin oxide) and metallic (platinum and titanium) films. Be-doping is shown to significantly reduce the nanowire diameter and improve the nanowire aspect ratio to 50:1. Photoluminescence measurements of Be-doped nanowires are 1–2 orders of magnitude stronger than undoped and Si-doped nanowires and have a thermal activation energy of 14meV, which is comparable to nanowires grown on crystalline substrates. Electrical measurements confirm that the metal-semiconductor junction is Ohmic. These results demonstrate the feasibility of integrating nanowire-based optoelectronic devices directly on CMOS chips. PMID:27834310

Applications of the silicon wafer direct-bonding technique to electron devices

NASA Astrophysics Data System (ADS)

Furukawa, K.; Nakagawa, A.

1990-01-01

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Bio-sorbable, liquid electrolyte gated thin-film transistor based on a solution-processed zinc oxide layer.

PubMed

Singh, Mandeep; Palazzo, Gerardo; Romanazzi, Giuseppe; Suranna, Gian Paolo; Ditaranto, Nicoletta; Di Franco, Cinzia; Santacroce, Maria Vittoria; Mulla, Mohammad Yusuf; Magliulo, Maria; Manoli, Kyriaki; Torsi, Luisa

2014-01-01

Among the metal oxide semiconductors, ZnO has been widely investigated as a channel material in thin-film transistors (TFTs) due to its excellent electrical properties, optical transparency and simple fabrication via solution-processed techniques. Herein, we report a solution-processable ZnO-based thin-film transistor gated through a liquid electrolyte with an ionic strength comparable to that of a physiological fluid. The surface morphology and chemical composition of the ZnO films upon exposure to water and phosphate-buffered saline (PBS) are discussed in terms of the operation stability and electrical performance of the ZnO TFT devices. The improved device characteristics upon exposure to PBS are associated with the enhancement of the oxygen vacancies in the ZnO lattice due to Na(+) doping. Moreover, the dissolution kinetics of the ZnO thin film in a liquid electrolyte opens the possible applicability of these devices as an active element in "transient" implantable systems.

Highly ultraviolet transparent textured indium tin oxide thin films and the application in light emitting diodes

NASA Astrophysics Data System (ADS)

Chen, Zimin; Zhuo, Yi; Tu, Wenbin; Ma, Xuejin; Pei, Yanli; Wang, Chengxin; Wang, Gang

2017-06-01

Various kinds of materials have been developed as transparent conductors for applications in semiconductor optoelectronic devices. However, there is a bottleneck that transparent conductive materials lose their transparency at ultraviolet (UV) wavelengths and could not meet the demands for commercial UV device applications. In this work, textured indium tin oxide (ITO) is grown and its potential to be used at UV wavelengths is explored. It is observed that the pronounced Burstein-Moss effect could widen the optical bandgap of the textured ITO to 4.7 eV. The average transmittance in UVA (315 nm-400 nm) and UVB (280 nm-315 nm) ranges is as high as 94% and 74%, respectively. The excellent optical property of textured ITO is attributed to its unique structural property. The compatibility of textured ITO thin films to the device fabrication is demonstrated on 368-nm nitride-based light emitting diodes, and the enhancement of light output power by 14.8% is observed compared to sputtered ITO.

Intrinsic Electron Mobility Exceeding 10³ cm²/(V s) in Multilayer InSe FETs.

PubMed

Sucharitakul, Sukrit; Goble, Nicholas J; Kumar, U Rajesh; Sankar, Raman; Bogorad, Zachary A; Chou, Fang-Cheng; Chen, Yit-Tsong; Gao, Xuan P A

2015-06-10

Graphene-like two-dimensional (2D) materials not only are interesting for their exotic electronic structure and fundamental electronic transport or optical properties but also hold promises for device miniaturization down to atomic thickness. As one material belonging to this category, InSe, a III-VI semiconductor, not only is a promising candidate for optoelectronic devices but also has potential for ultrathin field effect transistor (FET) with high mobility transport. In this work, various substrates such as PMMA, bare silicon oxide, passivated silicon oxide, and silicon nitride were used to fabricate multilayer InSe FET devices. Through back gating and Hall measurement in four-probe configuration, the device's field effect mobility and intrinsic Hall mobility were extracted at various temperatures to study the material's intrinsic transport behavior and the effect of dielectric substrate. The sample's field effect and Hall mobilities over the range of 20-300 K fall in the range of 0.1-2.0 × 10(3) cm(2)/(V s), which are comparable or better than the state of the art FETs made of widely studied 2D transition metal dichalcogenides.