Plasma-deposited fluoropolymer film mask for local porous silicon formation

PubMed Central

2012-01-01

The study of an innovative fluoropolymer masking layer for silicon anodization is proposed. Due to its high chemical resistance to hydrofluoric acid even under anodic bias, this thin film deposited by plasma has allowed the formation of deep porous silicon regions patterned on the silicon wafer. Unlike most of other masks, fluoropolymer removal after electrochemical etching is rapid and does not alter the porous layer. Local porous regions were thus fabricated both in p+-type and low-doped n-type silicon substrates. PMID:22734507

Nanostructured silicon ferromagnet collected by a permanent neodymium magnet.

PubMed

Okuno, Takahisa; Thürmer, Stephan; Kanoh, Hirofumi

2017-11-30

Nanostructured silicon (N-Si) was prepared by anodic electroetching of p-type silicon wafers. The obtained magnetic particles were separated by a permanent neodymium magnet as a magnetic nanostructured silicon (mN-Si). The N-Si and mN-Si exhibited different magnetic properties: the N-Si exhibited ferromagnetic-like behaviour, whereas the mN-Si exhibited superparamagnetic-like behaviour.

Reassessment of the recombination parameters of chromium in n- and p-type crystalline silicon and chromium-boron pairs in p-type crystalline silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sun, Chang, E-mail: chang.sun@anu.edu.au; Rougieux, Fiacre E.; Macdonald, Daniel

2014-06-07

Injection-dependent lifetime spectroscopy of both n- and p-type, Cr-doped silicon wafers with different doping levels is used to determine the defect parameters of Cr{sub i} and CrB pairs, by simultaneously fitting the measured lifetimes with the Shockley-Read-Hall model. A combined analysis of the two defects with the lifetime data measured on both n- and p-type samples enables a significant tightening of the uncertainty ranges of the parameters. The capture cross section ratios k = σ{sub n}/σ{sub p} of Cr{sub i} and CrB are determined as 3.2 (−0.6, +0) and 5.8 (−3.4, +0.6), respectively. Courtesy of a direct experimental comparison of the recombinationmore » activity of chromium in n- and p-type silicon, and as also suggested by modelling results, we conclude that chromium has a greater negative impact on carrier lifetimes in p-type silicon than n-type silicon with similar doping levels.« less

Microhardness of carbon-doped (111) p-type Czochralski silicon

NASA Technical Reports Server (NTRS)

Danyluk, S.; Lim, D. S.; Kalejs, J.

1985-01-01

The effect of carbon on (111) p-type Czochralski silicon is examined. The preparation of the silicon and microhardness test procedures are described, and the equation used to determine microhardness from indentations in the silicon wafers is presented. The results indicate that as the carbon concentration in the silicon increases the microhardness increases. The linear increase in microhardness is the result of carbon hindering dislocation motion, and the effect of temperature on silicon deformation and dislocation mobility is explained. The measured microhardness was compared with an analysis which is based on dislocation pinning by carbon; a good correlation was observed. The Labusch model for the effect of pinning sites on dislocation motion is given.

Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

2016-11-01

The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

Transfer of InP epilayers by wafer bonding

NASA Astrophysics Data System (ADS)

Hjort, Klas

2004-08-01

Wafer bonding increases the freedom of design in the integration of dissimilar materials. For example, it is interesting to combine III-V compounds that have direct band gap and high mobility with silicon (Si) that is extensively used in microelectronic applications. The interest to integrate III-V-based materials with Si arises primarily from two types of applications: smart pixels for optical intra- and inter-chip interconnects in the so-called optoelectronic integrated circuits, and optoelectronic devices using some material advantages of combining III-V with Si. Also, in the III-V industry larger substrates are crucial for higher efficiency in high-volume production, and especially so for monolithic microwave integrated circuits (MMIC). For indium phosphide (InP) the development of large-area substrates has not been able to keep up with market demands. One way to circumvent this problem is to use silicon substrates that are large-area, low-cost, and mechanically strong with high thermal conductivity. In addition, silicon is transparent at the emission wavelengths most often used in InP-based optoelectronics. Unfortunately, the large lattice-mismatch, 8.1%, between silicon and InP, has limited the success of heteroepitaxial growth. Hence, one alternative to be reviewed is InP-to-Si wafer bonding. When a direct semiconductor interface is not needed there are several other means of wafer bonding, e.g. adhesive, eutectic, and solid-state. These processes can be used for direct integration of small islets of epitaxially thin InP microelectronics onto other substrates, e.g. by transferring of InP-based epilayers to a Si-based microwave circuit by pick-and-place, BCB resist adhesive bonding and sacrificing of the InP substrate.

Six Sigma-based approach to optimise the diffusion process of crystalline silicon solar cell manufacturing

NASA Astrophysics Data System (ADS)

Prasad, A. Guru; Saravanan, S.; Gijo, E. V.; Dasari, Sreenivasa Murty; Tatachar, Raghu; Suratkar, Prakash

2016-02-01

Silicon-based photovoltaics (PV) plays the dominant role in the history of PV due to the continuous process and technology improvement in silicon solar cells and its manufacturing flow. In general, silicon solar cell process uses either p-type- or n-type-doped silicon as the starting material. Currently, most of the PV industries use p-type, boron-doped silicon wafer as the starting material. In this work too, the boron-doped wafers were considered as the starting material to create pn junction and phosphorus was used as n-type doping material. Industries use either phosphorous oxy chloride (POCl3) or ortho phosphoric acid (H3PO4) as the precursor for doping phosphorous. While the industries use POCl3 as the precursor, the throughput is lesser than that of the industries' use of H3PO4 due to the manufacturing limitations of the POCl3-based equipments. Hence, in order to achieve the operational excellence in POCl3-based equipments, business strategies such as the Six Sigma methodology have to be adapted. This paper describes the application of Six Sigma Define-Measure-Analyze-Improve-Control methodology for throughput improvement of the phosphorus doping process. The optimised recipe has been implemented in the production and it is running successfully. As a result of this project, an effective gain of 0.9 MW was reported per annum.

Method using laser irradiation for the production of atomically clean crystalline silicon and germanium surfaces

DOEpatents

Ownby, G.W.; White, C.W.; Zehner, D.M.

1979-12-28

This invention relates to a new method for removing surface impurities from crystalline silicon or germanium articles, such as off-the-shelf p- or n-type wafers to be doped for use as junction devices. The principal contaminants on such wafers are oxygen and carbon. The new method comprises laser-irradiating the contaminated surface in a non-reactive atmosphere, using one or more of Q-switched laser pulses whose parameters are selected to effect melting of the surface without substantial vaporization thereof. In a typical application, a plurality of pulses is used to convert a surface region of an off-the-shelf silicon wafer to an atomically clean region. This can be accomplished in a system at a pressure below 10-/sup 8/ Torr, using Q-switched ruber-laser pulses having an energy density in the range of from about 60 to 190 MW/cm/sup 2/.

Method using laser irradiation for the production of atomically clean crystalline silicon and germanium surfaces

DOEpatents

Ownby, Gary W.; White, Clark W.; Zehner, David M.

1981-01-01

This invention relates to a new method for removing surface impurities from crystalline silicon or germanium articles, such as off-the-shelf p- or n-type wafers to be doped for use as junction devices. The principal contaminants on such wafers are oxygen and carbon. The new method comprises laser-irradiating the contaminated surface in a non-reactive atmosphere, using one or more of Q-switched laser pulses whose parameters are selected to effect melting of the surface without substantial vaporization thereof. In a typical application, a plurality of pulses is used to convert a surface region of an off-the-shelf silicon wafer to an automatically clean region. This can be accomplished in a system at a pressure below 10.sup.-8 Torr, using Q-switched ruby-laser pulses having an energy density in the range of from about 60 to 190 MW/cm.sup.2.

The Influence of the Surface Neutralization of Active Impurities on the Field-Electron Emission Properties of p-Type Silicon Crystals

NASA Astrophysics Data System (ADS)

Yafarov, R. K.

2017-12-01

Correlation dependences between variations of the structural-phase composition, morphology characteristics, and field-electron-emission (FEE) properties of surface-structured p-type silicon singlecrystalline (100)-oriented wafers have been studied during their stepwise high-dose carbon-ion-beam irradiation. It is established that the stepwise implantation of carbon decreases the FEE threshold and favors an increase in the maximum FEE-current density by more than two orders of magnitude. Physicochemical mechanisms involved in this modification of the properties of near-surface layers of silicon under carbon-ion implantation are considered.

Recycling of silicon: from industrial waste to biocompatible nanoparticles for nanomedicine

NASA Astrophysics Data System (ADS)

Kozlov, N. K.; Natashina, U. A.; Tamarov, K. P.; Gongalsky, M. B.; Solovyev, V. V.; Kudryavtsev, A. A.; Sivakov, V.; Osminkina, L. A.

2017-09-01

The formation of photoluminescent porous silicon (PSi) nanoparticles (NPs) is usually based on an expensive semiconductor grade wafers technology. Here, we report a low-cost method of PSi NPs synthesis from the industrial silicon waste remained after the wafer production. The proposed method is based on metal-assisted wet-chemical etching (MACE) of the silicon surface of cm-sized metallurgical grade silicon stones which leads to a nanostructuring of the surface due to an anisotropic etching, with subsequent ultrasound fracturing in water. The obtained PSi NPs exhibit bright red room temperature photoluminescence (PL) and demonstrate similar microstructure and physical characteristics in comparison with the nanoparticles synthesized from semiconductor grade Si wafers. PSi NPs prepared from metallurgical grade silicon stones, similar to silicon NPs synthesized from high purity silicon wafer, show low toxicity to biological objects that open the possibility of using such type of NPs in nanomedicine.

Fabrication of an X-Ray Imaging Detector

NASA Technical Reports Server (NTRS)

Alcorn, G. E.; Burgess, A. S.

1986-01-01

X-ray detector array yields mosaic image of object emitting 1- to 30-keV range fabricated from n-doped silicon wafer. In proposed fabrication technique, thin walls of diffused n+ dopant divide wafer into pixels of rectangular cross section, each containing central electrode of thermally migrated p-type metal. This pnn+ arrangement reduces leakage current by preventing transistor action caused by pnp structure of earlier version.

Making Porous Luminescent Regions In Silicon Wafers

NASA Technical Reports Server (NTRS)

Fathauer, Robert W.; Jones, Eric W.

1994-01-01

Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

Deconvoluting the mechanism of microwave annealing of block copolymer thin films.

PubMed

Jin, Cong; Murphy, Jeffrey N; Harris, Kenneth D; Buriak, Jillian M

2014-04-22

The self-assembly of block copolymer (BCP) thin films is a versatile method for producing periodic nanoscale patterns with a variety of shapes. The key to attaining a desired pattern or structure is the annealing step undertaken to facilitate the reorganization of nanoscale phase-segregated domains of the BCP on a surface. Annealing BCPs on silicon substrates using a microwave oven has been shown to be very fast (seconds to minutes), both with and without contributions from solvent vapor. The mechanism of the microwave annealing process remains, however, unclear. This work endeavors to uncover the key steps that take place during microwave annealing, which enable the self-assembly process to proceed. Through the use of in situ temperature monitoring with a fiber optic temperature probe in direct contact with the sample, we have demonstrated that the silicon substrate on which the BCP film is cast is the dominant source of heating if the doping of the silicon wafer is sufficiently low. Surface temperatures as high as 240 °C are reached in under 1 min for lightly doped, high resistivity silicon wafers (n- or p-type). The influence of doping, sample size, and BCP composition was analyzed to rule out other possible mechanisms. In situ temperature monitoring of various polymer samples (PS, P2VP, PMMA, and the BCPs used here) showed that the polymers do not heat to any significant extent on their own with microwave irradiation of this frequency (2.45 GHz) and power (∼600 W). It was demonstrated that BCP annealing can be effectively carried out in 60 s on non-microwave-responsive substrates, such as highly doped silicon, indium tin oxide (ITO)-coated glass, glass, and Kapton, by placing a piece of high resistivity silicon wafer in contact with the sample-in this configuration, the silicon wafer is termed the heating element. Annealing and self-assembly of polystyrene-block-poly(2-vinylpyridine) (PS-b-P2VP) and polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) BCPs into horizontal cylinder structures were shown to take place in under 1 min, using a silicon wafer heating element, in a household microwave oven. Defect densities were calculated and were shown to decrease with higher maximum obtained temperatures. Conflicting results in the literature regarding BCP annealing with microwave are explained in light of the results obtained in this study.

Effect of PECVD SiNx/SiOyNx-Si interface property on surface passivation of silicon wafer

NASA Astrophysics Data System (ADS)

Jia, Xiao-Jie; Zhou, Chun-Lan; Zhu, Jun-Jie; Zhou, Su; Wang, Wen-Jing

2016-12-01

It is studied in this paper that the electrical characteristics of the interface between SiOyNx/SiNx stack and silicon wafer affect silicon surface passivation. The effects of precursor flow ratio and deposition temperature of the SiOyNx layer on interface parameters, such as interface state density Dit and fixed charge Qf, and the surface passivation quality of silicon are observed. Capacitance-voltage measurements reveal that inserting a thin SiOyNx layer between the SiNx and the silicon wafer can suppress Qf in the film and Dit at the interface. The positive Qf and Dit and a high surface recombination velocity in stacks are observed to increase with the introduced oxygen and minimal hydrogen in the SiOyNx film increasing. Prepared by deposition at a low temperature and a low ratio of N2O/SiH4 flow rate, the SiOyNx/SiNx stacks result in a low effective surface recombination velocity (Seff) of 6 cm/s on a p-type 1 Ω·cm-5 Ω·cm FZ silicon wafer. The positive relationship between Seff and Dit suggests that the saturation of the interface defect is the main passivation mechanism although the field-effect passivation provided by the fixed charges also make a contribution to it. Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA050302) and the National Natural Science Foundation of China (Grant No. 61306076).

Texturization of as-cut p-type monocrystalline silicon wafer using different wet chemical solutions

NASA Astrophysics Data System (ADS)

Hashmi, Galib; Hasanuzzaman, Muhammad; Basher, Mohammad Khairul; Hoq, Mahbubul; Rahman, Md. Habibur

2018-06-01

Implementing texturization process on the monocrystalline silicon substrate reduces reflection and enhances light absorption of the substrate. Thus texturization is one of the key elements to increase the efficiency of solar cell. Considering as-cut monocrystalline silicon wafer as base substrate, in this work different concentrations of Na2CO3 and NaHCO3 solution, KOH-IPA (isopropyl alcohol) solution and tetramethylammonium hydroxide solution with different time intervals have been investigated for texturization process. Furthermore, saw damage removal process was conducted with 10% NaOH solution, 20 wt% KOH-13.33 wt% IPA solution and HF/nitric/acetic acid solution. The surface morphology of saw damage, saw damage removed surface and textured wafer were observed using optical microscope and field emission scanning electron microscopy. Texturization causes pyramidal micro structures on the surface of (100) oriented monocrystalline silicon wafer. The height of the pyramid on the silicon surface varies from 1.5 to 3.2 µm and the inclined planes of the pyramids are acute angle. Contact angle value indicates that the textured wafer's surface fall in between near-hydrophobic to hydrophobic range. With respect to base material absolute reflectance 1.049-0.75% within 250-800 nm wavelength region, 0.1-0.026% has been achieved within the same wavelength region when textured with 0.76 wt% KOH-4 wt% IPA solution for 20 min. Furthermore, an alternative route of using 1 wt% Na2CO3-0.2 wt% NaHCO3 solution for 50 min has been exploited in the texturization process.

The Novel Preparation of P-N Junction Mesa Diodes by Silicon-Wafer Direct Bonding (SDB)

NASA Astrophysics Data System (ADS)

Yeh, Ching-Fa; Hwangleu, Shyang

1992-05-01

The key processes of silicon-wafer direct bonding (SDB), including hydrophilic surface formation and optimal two-step heat treatment, have been developed However, H2SO4/H2O2 solution being a strong oxidized acid solution, native oxide is found to have grown on the wafer surface as soon as a wafer is treated in this solution. In the case of a wafer further treated in diluted HF solution after hydrophilic surface formation, it is shown that the wafer surface can not only be cleaned of its native oxide but also remains hydrophilic, and can provide excellent voidless bonding. The N+/P and N/P combination junction mesa diodes fabricated on the wafers prepared by these novel SDB technologies are examined. The ideality factor n of the N/P mesa diode is 2.4˜2.8 for the voltage range 0.2˜0.3 V; hence, the lowering of the ideality factor n is evidently achieved. As for the N+/P mesa diode, the ideality factor n shows a value of 1.10˜1.30 for the voltage range 0.2˜0.6 V; the low value of n is attributed to an autodoping phenomenon which has caused the junction interface to form in the P-silicon bulk. However, the fact that the sustaining voltage of the N/P mesa diode showed a value greater than 520 V reveals the effectiveness of our novel SDB processes.

VLED for Si wafer-level packaging

NASA Astrophysics Data System (ADS)

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-03-01

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Liquid-phase-deposited siloxane-based capping layers for silicon solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Veith-Wolf, Boris; Wang, Jianhui; Hannu-Kuure, Milja

2015-02-02

We apply non-vacuum processing to deposit dielectric capping layers on top of ultrathin atomic-layer-deposited aluminum oxide (AlO{sub x}) films, used for the rear surface passivation of high-efficiency crystalline silicon solar cells. We examine various siloxane-based liquid-phase-deposited (LPD) materials. Our optimized AlO{sub x}/LPD stacks show an excellent thermal and chemical stability against aluminum metal paste, as demonstrated by measured surface recombination velocities below 10 cm/s on 1.3 Ωcm p-type silicon wafers after firing in a belt-line furnace with screen-printed aluminum paste on top. Implementation of the optimized LPD layers into an industrial-type screen-printing solar cell process results in energy conversion efficiencies ofmore » up to 19.8% on p-type Czochralski silicon.« less

Effect of electroless etching parameters on the growth and reflection properties of silicon nanowires.

PubMed

Ozdemir, Baris; Kulakci, Mustafa; Turan, Rasit; Unalan, Husnu Emrah

2011-04-15

Vertically aligned silicon nanowire (Si NW) arrays have been fabricated over large areas using an electroless etching (EE) method, which involves etching of silicon wafers in a silver nitrate and hydrofluoric acid based solution. A detailed parametric study determining the relationship between nanowire morphology and time, temperature, solution concentration and starting wafer characteristics (doping type, resistivity, crystallographic orientation) is presented. The as-fabricated Si NW arrays were analyzed by field emission scanning electron microscope (FE-SEM) and a linear dependency of nanowire length to both temperature and time was obtained and the change in the growth rate of Si NWs at increased etching durations was shown. Furthermore, the effects of EE parameters on the optical reflectivity of the Si NWs were investigated in this study. Reflectivity measurements show that the 42.8% reflectivity of the starting silicon wafer drops to 1.3%, recorded for 10 µm long Si NW arrays. The remarkable decrease in optical reflectivity indicates that Si NWs have a great potential to be utilized in radial or coaxial p-n heterojunction solar cells that could provide orthogonal photon absorption and enhanced carrier collection.

Effect of electroless etching parameters on the growth and reflection properties of silicon nanowires

NASA Astrophysics Data System (ADS)

Ozdemir, Baris; Kulakci, Mustafa; Turan, Rasit; Emrah Unalan, Husnu

2011-04-01

Vertically aligned silicon nanowire (Si NW) arrays have been fabricated over large areas using an electroless etching (EE) method, which involves etching of silicon wafers in a silver nitrate and hydrofluoric acid based solution. A detailed parametric study determining the relationship between nanowire morphology and time, temperature, solution concentration and starting wafer characteristics (doping type, resistivity, crystallographic orientation) is presented. The as-fabricated Si NW arrays were analyzed by field emission scanning electron microscope (FE-SEM) and a linear dependency of nanowire length to both temperature and time was obtained and the change in the growth rate of Si NWs at increased etching durations was shown. Furthermore, the effects of EE parameters on the optical reflectivity of the Si NWs were investigated in this study. Reflectivity measurements show that the 42.8% reflectivity of the starting silicon wafer drops to 1.3%, recorded for 10 µm long Si NW arrays. The remarkable decrease in optical reflectivity indicates that Si NWs have a great potential to be utilized in radial or coaxial p-n heterojunction solar cells that could provide orthogonal photon absorption and enhanced carrier collection.

Laser wafering for silicon solar.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurfacemore » damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.« less

Investigation of Backside Textures for Genesis Solar Wind Silicon Collectors

NASA Technical Reports Server (NTRS)

Gonzalez, C. P.; Burkett, P. J.; Rodriguez, M. C.; Allton, J. H.

2014-01-01

Genesis solar wind collectors were comprised of a suite of 15 types of ultrapure materials. The single crystal, pure silicon collectors were fabricated by two methods: float zone (FZ) and Czochralski (CZ). Because of slight differences in bulk purity and surface cleanliness among the fabrication processes and the specific vendor, it is desirable to know which variety of silicon and identity of vendor, so that appropriate reference materials can be used. The Czochralski method results in a bulk composition with slightly higher oxygen, for example. The CZ silicon array wafers that were Genesis-flown were purchased from MEMC Electronics. Most of the Genesis-flown FZ silicon was purchased from Unisil and cleaned by MEMC, although a few FZ wafers were acquired from International Wafer Service (IWS).

Trench process and structure for backside contact solar cells with polysilicon doped regions

DOEpatents

De Ceuster, Denis; Cousins, Peter John; Smith, David D

2014-03-18

A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. An interrupted trench structure separates the P-type doped region from the N-type doped region in some locations but allows the P-type doped region and the N-type doped region to touch in other locations. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. Among other advantages, the resulting solar cell structure allows for increased efficiency while having a relatively low reverse breakdown voltage.

Trench process and structure for backside contact solar cells with polysilicon doped regions

DOEpatents

De Ceuster, Denis; Cousins, Peter John; Smith, David D

2013-05-28

A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. An interrupted trench structure separates the P-type doped region from the N-type doped region in some locations but allows the P-type doped region and the N-type doped region to touch in other locations. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. Among other advantages, the resulting solar cell structure allows for increased efficiency while having a relatively low reverse breakdown voltage.

Trench process and structure for backside contact solar cells with polysilicon doped regions

DOEpatents

De Ceuster, Denis; Cousins, Peter John; Smith, David D.

2010-12-14

A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. An interrupted trench structure separates the P-type doped region from the N-type doped region in some locations but allows the P-type doped region and the N-type doped region to touch in other locations. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. Among other advantages, the resulting solar cell structure allows for increased efficiency while having a relatively low reverse breakdown voltage.

Improvement of silicon solar cell efficiency by ion beam sputtered deposition of AlOxNy thin films.

PubMed

Chen, Sheng-Hui; Hsu, Chun-Che; Wang, Hsuan-Wen; Yeh, Chi-Li; Tseng, Shao-Ze; Lin, Hung-Ju; Lee, Cheng-Chung; Peng, Cheng-Yu

2011-03-20

Negative charge material, AlOxNy, has been fabricated to passivate the surface of p-type silicon. The fabrication of AlOxNy was possible by using ion beam sputtering deposition to deposit AlN thin film on the surface of a p-type silicon wafer and following annealing in oxygen ambient. Capacitance-voltage analysis shows the fixed charge density has increased from 10(11) cm(-2) to 2.26×10(12) cm(-2) after annealing. The solar cell efficiency increased from 15.9% to 17.3%, which is also equivalent to the reduction of surface recombination velocity from 1×10(5)  to 32 cm/s.

Laboratory and testbeam results for thin and epitaxial planar sensors for HL-LHC

DOE PAGES

Bubna, M.; Bolla, G.; Bortoletto, D.; ...

2015-08-03

The High-Luminosity LHC (HL-LHC) upgrade of the CMS pixel detector will require the development of novel pixel sensors which can withstand the increase in instantaneous luminosity to L = 5 × 10 34 cm –2s –1 and collect ~ 3000fb –1 of data. The innermost layer of the pixel detector will be exposed to doses of about 10 16 n eq/ cm 2. Hence, new pixel sensors with improved radiation hardness need to be investigated. A variety of silicon materials (Float-zone, Magnetic Czochralski and Epitaxially grown silicon), with thicknesses from 50 μm to 320 μm in p-type and n-type substrates have beenmore » fabricated using single-sided processing. The effect of reducing the sensor active thickness to improve radiation hardness by using various techniques (deep diffusion, wafer thinning, or growing epitaxial silicon on a handle wafer) has been studied. Furthermore, the results for electrical characterization, charge collection efficiency, and position resolution of various n-on-p pixel sensors with different substrates and different pixel geometries (different bias dot gaps and pixel implant sizes) will be presented.« less

New insight into the discharge mechanism of silicon-air batteries using electrochemical impedance spectroscopy.

PubMed

Cohn, Gil; Eichel, Rüdiger A; Ein-Eli, Yair

2013-03-07

The mechanism of discharge termination in silicon-air batteries, employing a silicon wafer anode, a room-temperature fluorohydrogenate ionic liquid electrolyte and an air cathode membrane, is investigated using a wide range of tools. EIS studies indicate that the interfacial impedance between the electrolyte and the silicon wafer increases upon continuous discharge. In addition, it is shown that the impedance of the air cathode-electrolyte interface is several orders of magnitude lower than that of the anode. Equivalent circuit fitting parameters indicate the difference in the anode-electrolyte interface characteristics for different types of silicon wafers. Evolution of porous silicon surfaces at the anode and their properties, by means of estimated circuit parameters, is also presented. Moreover, it is found that the silicon anode potential has the highest negative impact on the battery discharge voltage, while the air cathode potential is actually stable and invariable along the whole discharge period. The discharge capacity of the battery can be increased significantly by mechanically replacing the silicon anode.

Applications of the silicon wafer direct-bonding technique to electron devices

NASA Astrophysics Data System (ADS)

Furukawa, K.; Nakagawa, A.

1990-01-01

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

System and Method for Fabricating Super Conducting Circuitry on Both Sides of an Ultra-Thin Layer

NASA Technical Reports Server (NTRS)

Brown, Ari D. (Inventor); Mikula, Vilem (Inventor)

2017-01-01

A method of fabricating circuitry in a wafer includes depositing a superconducting metal on a silicon on insulator wafer having a handle wafer, coating the wafer with a sacrificial layer and bonding the wafer to a thermally oxide silicon wafer with a first epoxy. The method includes flipping the wafer, thinning the flipped wafer by removing a handle wafer, etching a buried oxide layer, depositing a superconducting layer, bonding the wafer to a thermally oxidized silicon wafer having a handle wafer using an epoxy, flipping the wafer again, thinning the flipped wafer, etching a buried oxide layer from the wafer and etching the sacrificial layer from the wafer. The result is a wafer having superconductive circuitry on both sides of an ultra-thin silicon layer.

Dry etch method for texturing silicon and device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gershon, Talia S.; Haight, Richard A.; Kim, Jeehwan

2017-07-25

A method for texturing silicon includes loading a silicon wafer into a vacuum chamber, heating the silicon wafer and thermal cracking a gas to generate cracked sulfur species. The silicon wafer is exposed to the cracked sulfur species for a time duration in accordance with a texture characteristic needed for a surface of the silicon wafer.

Water-assisted pulsed Er:YAG laser interaction with silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Jaehun; Ki, Hyungson, E-mail: hski@unist.ac.kr

2015-07-07

Silicon is virtually transparent to the Er:YAG laser with a wavelength of 2.94 μm. In this study, we report that moderately doped silicon (1–10 Ω cm) can be processed by a pulsed Er:YAG laser with a pulse duration of 350 μs and a peak laser intensity of 1.7 × 10{sup 5} W/cm{sup 2} by applying a thin water layer on top of silicon as a light absorbing medium. In this way, water is heated first by strongly absorbing the laser energy and then heats up the silicon wafer indirectly. As the silicon temperature rises, the free carrier concentration and therefore the absorption coefficient of silicon willmore » increase significantly, which may enable the silicon to get directly processed by the Er:YAG laser when the water is vaporized completely. We also believe that the change in surface morphology after melting could contribute to the increase in the laser beam absorptance. It was observed that 525 nm-thick p-type wafer specimens were fully penetrated after 15 laser pulses were irradiated. Bright yellow flames were observed during the process, which indicates that the silicon surface reached the melting point.« less

Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

2018-04-01

In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

Electrochemical method for defect delineation in silicon-on-insulator wafers

DOEpatents

Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

1991-01-01

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Electrically Conductive and Optically Active Porous Silicon Nanowires

PubMed Central

Qu, Yongquan; Liao, Lei; Li, Yujing; Zhang, Hua; Huang, Yu; Duan, Xiangfeng

2009-01-01

We report the synthesis of vertical silicon nanowire array through a two-step metal-assisted chemical etching of highly doped n-type silicon (100) wafers in a solution of hydrofluoric acid and hydrogen peroxide. The morphology of the as-grown silicon nanowires is tunable from solid nonporous nanowires, nonporous/nanoporous core/shell nanowires, and entirely nanoporous nanowires by controlling the hydrogen peroxide concentration in the etching solution. The porous silicon nanowires retain the single crystalline structure and crystallographic orientation of the starting silicon wafer, and are electrically conductive and optically active with visible photoluminescence. The combination of electronic and optical properties in the porous silicon nanowires may provide a platform for the novel optoelectronic devices for energy harvesting, conversion and biosensing. PMID:19807130

Degradation of bare and silanized silicon wafer surfaces by constituents of biological fluids.

PubMed

Dekeyser, C M; Buron, C C; Derclaye, S R; Jonas, A M; Marchand-Brynaert, J; Rouxhet, P G

2012-07-15

The 24 h stability of bare silicon wafers as such or silanized with CH(3)O-(CH(2)-CH(2)-O)(n)-C(3)H(6)-trichlorosilane (n=6-9) was investigated in water, NaCl, phosphate and carbonate solutions, and in phosphate buffered saline (PBS) at 37 °C (close to biological conditions regarding temperature, high ionic strength, and pH). The resulting surfaces were analyzed using ellipsometry, X-ray Reflectometry (XRR), X-ray Photoelectron Spectroscopy (XPS), and Atomic Force Microscopy (AFM). Incubation of the silanized wafers in phosphate solution and PBS provokes a detachment of the silane layer. This is due to a hydrolysis of Si-O bonds which is favored by the action of phosphate, also responsible for a corrosion of non-silanized wafers. The surface alteration (detachment of silane layer and corrosion of the non-silanized wafer) is also important with carbonate solution, due to a higher pH (8.3). The protection of the silicon oxide layer brought by silane against the action of the salts is noticeable for phosphate but not for carbonate. Copyright © 2012 Elsevier Inc. All rights reserved.

Inversion layer solar cell fabrication and evaluation. [etching on silicon films

NASA Technical Reports Server (NTRS)

Call, R. L.

1974-01-01

Inversion layer solar cells were fabricated by etching through the diffused layer on p-type silicon wafers in a comb-like contact pattern. The charge separation comes from an induced p-n junction at the surface. The inverted surface is caused by a layer of transparent material applied to the surface that either contains free positive ions or that creates donor states at the interface. Cells are increased from 3 ma I sub sc to 100 ma by application of sodium silicate. The action is unstable, however, and decays. Non-mesa contaminated oxide cells were fabricated with short circuit currents of over 100 ma measured in the sun. Cells of this type have demonstrated stability.

RF performances of inductors integrated on localized p+-type porous silicon regions

PubMed Central

2012-01-01

To study the influence of localized porous silicon regions on radiofrequency performances of passive devices, inductors were integrated on localized porous silicon regions, full porous silicon sheet, bulk silicon and glass substrates. In this work, a novel strong, resistant fluoropolymer mask is introduced to localize the porous silicon on the silicon wafer. Then, the quality factors and resonant frequencies obtained with the different substrates are presented. A first comparison is done between the performances of inductors integrated on same-thickness localized and full porous silicon sheet layers. The effect of the silicon regions in the decrease of performances of localized porous silicon is discussed. Then, the study shows that the localized porous silicon substrate significantly reduces losses in comparison with high-resistivity silicon or highly doped silicon bulks. These results are promising for the integration of both passive and active devices on the same silicon/porous silicon hybrid substrate. PMID:23009746

Investigation of MeV-Cu implantation and channeling effects into porous silicon formation

NASA Astrophysics Data System (ADS)

Ahmad, M.; Naddaf, M.

2011-11-01

P-type (1 1 1) silicon wafers were implanted by copper ions (2.5 MeV) in channeling and random directions using ion beam accelerator of the Atomic Energy Commission of Syria (AECS). The effect of implantation direction on formation process of porous silicon (PS) using electrochemical etching method has been investigated using scanning electron microscope (SEM) and photoluminescence (PL) techniques. SEM observations revealed that the size, shape and density of the formed pores are highly affected by the direction of beam implantation. This in turn is seen to influence the PL behavior of the PS.

Electronic transport characterization of silicon wafers by spatially resolved steady-state photocarrier radiometric imaging

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Qian; University of the Chinese Academy of Sciences, Beijing 100039; Li, Bincheng, E-mail: bcli@ioe.ac.cn

2015-09-28

Spatially resolved steady-state photocarrier radiometric (PCR) imaging technique is developed to characterize the electronic transport properties of silicon wafers. Based on a nonlinear PCR theory, simulations are performed to investigate the effects of electronic transport parameters (the carrier lifetime, the carrier diffusion coefficient, and the front surface recombination velocity) on the steady-state PCR intensity profiles. The electronic transport parameters of an n-type silicon wafer are simultaneously determined by fitting the measured steady-state PCR intensity profiles to the three-dimensional nonlinear PCR model. The determined transport parameters are in good agreement with the results obtained by the conventional modulated PCR technique withmore » multiple pump beam radii.« less

Method for synthesis of high quality graphene

DOEpatents

Lanzara, Alessandra [Piedmont, CA; Schmid, Andreas K [Berkeley, CA; Yu, Xiaozhu [Berkeley, CA; Hwang, Choonkyu [Albany, CA; Kohl, Annemarie [Beneditkbeuern, DE; Jozwiak, Chris M [Oakland, CA

2012-03-27

A method is described herein for the providing of high quality graphene layers on silicon carbide wafers in a thermal process. With two wafers facing each other in close proximity, in a first vacuum heating stage, while maintained at a vacuum of around 10.sup.-6 Torr, the wafer temperature is raised to about 1500.degree. C., whereby silicon evaporates from the wafer leaving a carbon rich surface, the evaporated silicon trapped in the gap between the wafers, such that the higher vapor pressure of silicon above each of the wafers suppresses further silicon evaporation. As the temperature of the wafers is raised to about 1530.degree. C. or more, the carbon atoms self assemble themselves into graphene.

Silicon (100)/SiO2 by XPS

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jensen, David S.; Kanyal, Supriya S.; Madaan, Nitesh

2013-09-25

Silicon (100) wafers are ubiquitous in microfabrication and, accordingly, their surface characteristics are important. Herein, we report the analysis of Si (100) via X-ray photoelectron spectroscopy (XPS) using monochromatic Al K radiation. Survey scans show that the material is primarily silicon and oxygen, and the Si 2p region shows two peaks that correspond to elemental silicon and silicon dioxide. Using these peaks the thickness of the native oxide (SiO2) was estimated using the equation of Strohmeier.1 The oxygen peak is symmetric. The material shows small amounts of carbon, fluorine, and nitrogen contamination. These silicon wafers are used as the basemore » material for subsequent growth of templated carbon nanotubes.« less

Development of AC-coupled, poly-silicon biased, p-on-n silicon strip detectors in India for HEP experiments

NASA Astrophysics Data System (ADS)

Jain, Geetika; Dalal, Ranjeet; Bhardwaj, Ashutosh; Ranjan, Kirti; Dierlamm, Alexander; Hartmann, Frank; Eber, Robert; Demarteau, Marcel

2018-02-01

P-on-n silicon strip sensors having multiple guard-ring structures have been developed for High Energy Physics applications. The study constitutes the optimization of the sensor design, and fabrication of AC-coupled, poly-silicon biased sensors of strip width of 30 μm and strip pitch of 55 μm. The silicon wafers used for the fabrication are of 4 inch n-type, having an average resistivity of 2-5 k Ω cm, with a thickness of 300 μm. The electrical characterization of these detectors comprises of: (a) global measurements of total leakage current, and backplane capacitance; (b) strip and voltage scans of strip leakage current, poly-silicon resistance, interstrip capacitance, interstrip resistance, coupling capacitance, and dielectric current; and (c) charge collection measurements using ALiBaVa setup. The results of the same are reported here.

Exceptional gettering response of epitaxially grown kerfless silicon

DOE PAGES

Powell, D. M.; Markevich, V. P.; Hofstetter, J.; ...

2016-02-08

The bulk minority-carrier lifetime in p- and n-type kerfless epitaxial (epi) crystalline silicon wafers is shown to increase >500 during phosphorus gettering. We employ kinetic defect simulations and microstructural characterization techniques to elucidate the root cause of this exceptional gettering response. Simulations and deep-level transient spectroscopy (DLTS) indicate that a high concentra- tion of point defects (likely Pt) is “locked in” during fast (60 C/min) cooling during epi wafer growth. The fine dispersion of moderately fast-diffusing recombination-active point defects limits as-grown lifetime but can also be removed during gettering, confirmed by DLTS measurements. Synchrotron-based X-ray fluorescence microscopy indicates metal agglomeratesmore » at structural defects, yet the structural defect density is sufficiently low to enable high lifetimes. Consequently, after phosphorus diffusion gettering, epi silicon exhibits a higher lifetime than materials with similar bulk impurity contents but higher densities of structural defects, including multicrystalline ingot and ribbon silicon materials. As a result, device simulations suggest a solar-cell efficiency potential of this material >23%.« less

Investigation of Defects Origin in p-Type Si for Solar Applications

NASA Astrophysics Data System (ADS)

Gwóźdź, Katarzyna; Placzek-Popko, Ewa; Mikosza, Maciej; Zielony, Eunika; Pietruszka, Rafal; Kopalko, Krzysztof; Godlewski, Marek

2017-07-01

In order to improve the efficiency of a solar cell based on silicon, one must find a compromise between its price and crystalline quality. That is precisely why the knowledge of defects present in the material is of primary importance. This paper studies the defects in commercially available cheap Schottky titanium/gold silicon wafers. The electrical properties of the diodes were defined by using current-voltage and capacitance-voltage measurements. Low series resistance and ideality factor are proofs of the good quality of the sample. The concentration of the acceptors is in accordance with the manufacturer's specifications. Deep level transient spectroscopy measurements were used to identify the defects. Three hole traps were found with activation energies equal to 0.093 eV, 0.379 eV, and 0.535 eV. Comparing the values with the available literature, the defects were determined as connected to the presence of iron interstitials in the silicon. The quality of the silicon wafer seems good enough to use it as a substrate for the solar cell heterojunctions.

Diffusion lengths in irradiated N/P InP-on-Si solar cells

NASA Technical Reports Server (NTRS)

Wojtczuk, Steven; Colerico, Claudia; Summers, Geoffrey P.; Walters, Robert J.; Burke, Edward A.

1995-01-01

Indium phosphide (InP) solar cells are being made on silicon (Si) wafers (InP/Si) to take advantage of both the radiation-hardness properties of the InP solar cell and the light weight and low cost of Si wafers compared to InP or germanium (Ge) wafers. The InP/Si cell application is for long duration and/or high radiation orbit space missions. InP/Si cells have higher absolute efficiency after a high radiation dose than gallium arsenide (GaAs) or silicon (Si) solar cells. In this work, base electron diffusion lengths in the N/P cell are extracted from measured AM0 short-circuit photocurrent at various irradiation levels out to an equivalent 1 MeV fluence of 1017 1 MeV electrons/sq cm for a 1 sq cm 12% BOL InP/Si cell. These values are then checked for consistency by comparing measured Voc data with a theoretical Voc model that includes a dark current term that depends on the extracted diffusion lengths.

Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene

DTIC Science & Technology

2014-08-01

Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene by Eugene Zakar, Wayne Churaman, Collin Becker, Bernard Rod, Luke...Laboratory Adelphi, MD 20783-1138 ARL-TR-7025 August 2014 Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene...Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6

Evaluation and verification of epitaxial process sequence for silicon solar-cell production

NASA Technical Reports Server (NTRS)

Redfield, D.

1981-01-01

To achieve the program goals, 28 minimodules were fabricated and tested, using 600 cells made from three-inch-diameter wafers processed by the sequence chosen for this purpose. Of these 600 cells, half were made from epitaxially grown layers on potentially low-cost substrates. The other half were made from commercial semiconductor-grade (SG), single-crystal silicon wafers that served as controls. Cell processing was normally performed on mixed lots containing significant numbers of each of these two types of wafers. After evaluation of the performance of all cells, they were separated by types for incorporation into modules that were to be tested for electrical performance and response to environmental stress. A simplified flow chart displaying this scheme, for quantities representing half of the planned total to be processed, is presented.

Silicon sample holder for molecular beam epitaxy on pre-fabricated integrated circuits

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Grunthaner, Paula J. (Inventor); Grunthaner, Frank J. (Inventor)

1994-01-01

The sample holder of the invention is formed of the same semiconductor crystal as the integrated circuit on which the molecular beam expitaxial process is to be performed. In the preferred embodiment, the sample holder comprises three stacked micro-machined silicon wafers: a silicon base wafer having a square micro-machined center opening corresponding in size and shape to the active area of a CCD imager chip, a silicon center wafer micro-machined as an annulus having radially inwardly pointing fingers whose ends abut the edges of and center the CCD imager chip within the annulus, and a silicon top wafer micro-machined as an annulus having cantilevered membranes which extend over the top of the CCD imager chip. The micro-machined silicon wafers are stacked in the order given above with the CCD imager chip centered in the center wafer and sandwiched between the base and top wafers. The thickness of the center wafer is about 20% less than the thickness of the CCD imager chip. Preferably, four titanium wires, each grasping the edges of the top and base wafers, compress all three wafers together, flexing the cantilever fingers of the top wafer to accommodate the thickness of the CCD imager chip, acting as a spring holding the CCD imager chip in place.

Large-aperture focusing of x rays with micropore optics using dry etching of silicon wafers.

PubMed

Ezoe, Yuichiro; Moriyama, Teppei; Ogawa, Tomohiro; Kakiuchi, Takuya; Mitsuishi, Ikuyuki; Mitsuda, Kazuhisa; Aoki, Tatsuhiko; Morishita, Kohei; Nakajima, Kazuo

2012-03-01

Large-aperture focusing of Al K(α) 1.49 keV x-ray photons using micropore optics made from a dry-etched 4 in. (100 mm) silicon wafer is demonstrated. Sidewalls of the micropores are smoothed with high-temperature annealing to work as x-ray mirrors. The wafer is bent to a spherical shape to collect parallel x rays into a focus. Our result supports that this new type of optics allows for the manufacturing of ultralight-weight and high-performance x-ray imaging optics with large apertures at low cost. © 2012 Optical Society of America

Microwave characterization of slotline on high resistivity silicon for antenna feed network

NASA Technical Reports Server (NTRS)

Simons, Rainee N.; Taub, Susan R.; Lee, Richard Q.; Young, Paul G.

1993-01-01

Conventional silicon wafers have low resistivity and consequently unacceptably high value of dielectric attenuation constant. Microwave circuits for phased array antenna systems fabricated on these wafers therefore have low efficiency. By choosing a silicon substrate with sufficiently high resistivity it is possible to make the dielectric attenuation constant of the interconnecting microwave transmission lines approach those of GaAs or InP. In order for this to be possible, the transmission lines must be characterized. In this presentation, the effective dielectric constant (epsilon sub eff) and attenuation constant (alpha) of a slotline on high resistivity (5000 to 10 000 ohm-cm) silicon wafer will be discussed. The epsilon sub eff and alpha are determined from the measured resonant frequencies and the corresponding insertion loss of a slotline ring resonator. The results for slotline will be compared with microstrip line and coplanar waveguide.

Investigation on the structural characterization of pulsed p-type porous silicon

NASA Astrophysics Data System (ADS)

Wahab, N. H. Abd; Rahim, A. F. Abd; Mahmood, A.; Yusof, Y.

2017-08-01

P-type Porous silicon (PS) was sucessfully formed by using an electrochemical pulse etching (PC) and conventional direct current (DC) etching techniques. The PS was etched in the Hydrofluoric (HF) based solution at a current density of J = 10 mA/cm2 for 30 minutes from a crystalline silicon wafer with (100) orientation. For the PC process, the current was supplied through a pulse generator with 14 ms cycle time (T) with 10 ms on time (Ton) and pause time (Toff) of 4 ms respectively. FESEM, EDX, AFM, and XRD have been used to characterize the morphological properties of the PS. FESEM images showed that pulse PS (PPC) sample produces more uniform circular structures with estimated average pore sizes of 42.14 nm compared to DC porous (PDC) sample with estimated average size of 16.37nm respectively. The EDX spectrum for both samples showed higher Si content with minimal presence of oxide.

Porosity and thickness effect of porous silicon layer on photoluminescence spectra

NASA Astrophysics Data System (ADS)

Husairi, F. S.; Eswar, K. A.; Guliling, Muliyadi; Khusaimi, Z.; Rusop, M.; Abdullah, S.

2018-05-01

The porous silicon nanostructures was prepared by electrochemical etching of p-type silicon wafer. Porous silicon prepared by using different current density and fix etching time with assistance of halogen lamp. The physical structure of porous silicon measured by the parameters used which know as experimental factor. In this work, we select one of those factors to correlate which optical properties of porous silicon. We investigated the surface morphology by using Surface Profiler (SP) and photoluminescence using Photoluminescence (PL) spectrometer. Different physical characteristics of porous silicon produced when current density varied. Surface profiler used to measure the thickness of porous and the porosity calculated using mass different of silicon. Photoluminescence characteristics of porous silicon depend on their morphology because the size and distribution of pore its self will effect to their exciton energy level. At J=30 mA/cm2 the shorter wavelength produced and it followed the trend of porosity with current density applied.

Development of n+-in-p large-area silicon microstrip sensors for very high radiation environments - ATLAS12 design and initial results

NASA Astrophysics Data System (ADS)

Unno, Y.; Edwards, S. O.; Pyatt, S.; Thomas, J. P.; Wilson, J. A.; Kierstead, J.; Lynn, D.; Carter, J. R.; Hommels, L. B. A.; Robinson, D.; Bloch, I.; Gregor, I. M.; Tackmann, K.; Betancourt, C.; Jakobs, K.; Kuehn, S.; Mori, R.; Parzefall, U.; Wiik-Fucks, L.; Clark, A.; Ferrere, D.; Gonzalez Sevilla, S.; Ashby, J.; Blue, A.; Bates, R.; Buttar, C.; Doherty, F.; Eklund, L.; McMullen, T.; McEwan, F.; O`Shea, V.; Kamada, S.; Yamamura, K.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Nishimura, R.; Takashima, R.; Chilingarov, A.; Fox, H.; Affolder, A. A.; Allport, P. P.; Casse, G.; Dervan, P.; Forshaw, D.; Greenall, A.; Wonsak, S.; Wormald, M.; Cindro, V.; Kramberger, G.; Mandic, I.; Mikuz, M.; Gorelov, I.; Hoeferkamp, M.; Palni, P.; Seidel, S.; Taylor, A.; Toms, K.; Wang, R.; Hessey, N. P.; Valencic, N.; Arai, Y.; Hanagaki, K.; Dolezal, Z.; Kodys, P.; Bohm, J.; Mikestikova, M.; Bevan, A.; Beck, G.; Ely, S.; Fadeyev, V.; Galloway, Z.; Grillo, A. A.; Martinez-McKinney, F.; Ngo, J.; Parker, C.; Sadrozinski, H. F.-W.; Schumacher, D.; Seiden, A.; French, R.; Hodgson, P.; Marin-Reyes, H.; Parker, K.; Paganis, S.; Jinnouchi, O.; Motohashi, K.; Todome, K.; Yamaguchi, D.; Hara, K.; Hagihara, M.; Garcia, C.; Jimenez, J.; Lacasta, C.; Marti i Garcia, S.; Soldevila, U.

2014-11-01

We have been developing a novel radiation-tolerant n+-in-p silicon microstrip sensor for very high radiation environments, aiming for application in the high luminosity large hadron collider. The sensors are fabricated in 6 in., p-type, float-zone wafers, where large-area strip sensor designs are laid out together with a number of miniature sensors. Radiation tolerance has been studied with ATLAS07 sensors and with independent structures. The ATLAS07 design was developed into new ATLAS12 designs. The ATLAS12A large-area sensor is made towards an axial strip sensor and the ATLAS12M towards a stereo strip sensor. New features to the ATLAS12 sensors are two dicing lines: standard edge space of 910 μm and slim edge space of 450 μm, a gated punch-through protection structure, and connection of orphan strips in a triangular corner of stereo strips. We report the design of the ATLAS12 layouts and initial measurements of the leakage current after dicing and the resistivity of the wafers.

Pyroelectric, piezoelectric, and photoeffects in hydroxyapatite thin films on silicon

NASA Astrophysics Data System (ADS)

Lang, S. B.; Tofail, S. A. M.; Gandhi, A. A.; Gregor, M.; Wolf-Brandstetter, C.; Kost, J.; Bauer, S.; Krause, M.

2011-03-01

Hydroxyapatite (HA) is the major component of bone and is used in artificial form in many biomedical applications. It was once believed to have a centrosymmetric crystal structure. In theoretical and experimental studies published in 2005, it was shown to have a monoclinic P21 structure. In the work reported here, 500 nm films of HA were spin-coated on silicon wafers. The materials were not poled. They had a nonuniform polarization distribution and exhibited pyroelectricity, piezoelectricity, and photoeffects. Structures of this type may have a number of technological applications.

Fabrication of Cantilever-Bump Type Si Probe Card

NASA Astrophysics Data System (ADS)

Park, Jeong-Yong; Lee, Dong-Seok; Kim, Dong-Kwon; Lee, Jong-Hyun

2000-12-01

Probe card is most important part in the test system which selects the good or bad chip of integrated circuit (IC) chips. Silicon vertical probe card is able to test multiple semiconductor chips simultaneously. We presented cantilever-bump type vertical probe card. It was fabricated by dry etching using RIE(reactive ion etching) technique and porous silicon micromachining using silicon direct bonded (SDB) wafer. Cantilevers and bumps were fabricated by isotropic etching using RIE@. 3-dimensional structures were formed by porous silicon micromachining technique using SDB wafer. Contact resistance of fabricated probe card was less than 2 Ω and its life time was more than 200,000 turns. The process used in this work is very simple and reproducible, which has good controllability in the tip dimension and spacing. It is expected that the fabricated probe card can reduce testing time, can promote productivity and enables burn-in test.

Influence of fluids on the abrasion of silicon by diamond

NASA Technical Reports Server (NTRS)

Danyluk, S.

1982-01-01

Silicon wafers ((100)-p-type) were abraded at room temperature in acetone, absolute ethanol and water by a pyramid diamond and the resulting groove depth was measured as a function of normal force on the diamond and the absorbed fluids, while all other experimental conditions were held constant. The groove depth rates are in the ratio of 1:2:3 for water, absolute ethanol, and acetone, respectively, for a constant normal force. The groove depth rate is lower when the normal force is decreased. The silicon abraded in the presence of water was chipped as expected for a classical brittle material while the surfaces abraded in the other two fluids showed ductile ploughing as the main mechanism for silicon removal.

Forming n/p Junctions With An Excimer Laser

NASA Technical Reports Server (NTRS)

Alexander, Paul, Jr.; Campbell, Robert B.; Wong, David C.; Bottenberg, William L.; Byron, Stanley

1988-01-01

Compact equipment yields high-quality solar cells. Computer controls pulses of excimer laser and movement of silcon wafer. Mirrors direct laser beam to wafer. Lenses focus beam to small spot on surface. Process suitable for silicon made by dendritic-web-growth process.

Characterization of deliberately nickel-doped silicon wafers and solar cells. [microstructure, electrical properties, and energy conversion efficiency

NASA Technical Reports Server (NTRS)

Salama, A. M.

1980-01-01

Microstructural and electrical evaluation tests were performed on nickel-doped p-type silicon wafers before and after solar cell fabrication. The concentration levels of nickel in silicon were 5 x 10 to the 14th power, 4 x 10 to the 15th power, and 8 x 10 to the 15th power atoms/cu cm. It was found that nickel precipitated out during the growth process in all three ingots. Clumps of precipitates, some of which exhibited star shape, were present at different depths. If the clumps are distributed at depths approximately 20 micron apart and if they are larger than 10 micron in diameter, degradation occurs in solar cell electrical properties and cell conversion efficiency. The larger the size of the precipitate clump, the greater the degradation in solar cell efficiency. A large grain boundary around the cell effective area acted as a gettering center for the precipitates and impurities and caused improvement in solar cell efficiency. Details of the evaluation test results are given.

An experimental investigation of silicon wafer surface roughness and its effect on the full strength of plated metals

NASA Technical Reports Server (NTRS)

Spiers, G. D.

1981-01-01

Plated silicon wafers with surface roughness ranging from 0.4 to 130 microinches were subjected to tensile pull strength tests. Electroless Ni/electroless Cu/electroplated Cu and electroless Ni/electroplated Cu were the two types of plate contacts tested. It was found that smoother surfaces had higher pull strength than rougher, chemically etched surfaces. The presence of the electroless Cu layer was found to be important to adhesion. The mode of fracture of the contact as it left the silicon was studied, and it was found that in almost all cases separation was due to fracture of the bulk silicon phase. The correlation between surface roughness and mode of contact failure is presented and interpreted.

Process Research on Polycrystalline Silicon Material (PROPSM)

NASA Technical Reports Server (NTRS)

Culik, J. S.

1983-01-01

The performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was investigated by measuring the illuminated current voltage (I-V) characteristics of the minicell wafer set. The average short circuit current on different wafers is 3 to 14 percent lower than that of single crystal Czochralski silicon. The scatter was typically less than 3 percent. The average open circuit voltage is 20 to 60 mV less than that of single crystal silicon. The scatter in the open circuit voltage of most of the polycrystalline silicon wafers was 15 to 20 mV, although two wafers had significantly greater scatter than this value. The fill factor of both polycrystalline and single crystal silicon cells was typically in the range of 60 to 70 percent; however several polycrystalline silicon wafers have fill factor averages which are somewhat lower and have a significantly larger degree of scatter.

High Efficiency, Low Cost Solar Cells Manufactured Using 'Silicon Ink' on Thin Crystalline Silicon Wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Antoniadis, H.

Reported are the development and demonstration of a 17% efficient 25mm x 25mm crystalline Silicon solar cell and a 16% efficient 125mm x 125mm crystalline Silicon solar cell, both produced by Ink-jet printing Silicon Ink on a thin crystalline Silicon wafer. To achieve these objectives, processing approaches were developed to print the Silicon Ink in a predetermined pattern to form a high efficiency selective emitter, remove the solvents in the Silicon Ink and fuse the deposited particle Silicon films. Additionally, standard solar cell manufacturing equipment with slightly modified processes were used to complete the fabrication of the Silicon Ink highmore » efficiency solar cells. Also reported are the development and demonstration of a 18.5% efficient 125mm x 125mm monocrystalline Silicon cell, and a 17% efficient 125mm x 125mm multicrystalline Silicon cell, by utilizing high throughput Ink-jet and screen printing technologies. To achieve these objectives, Innovalight developed new high throughput processing tools to print and fuse both p and n type particle Silicon Inks in a predetermined pat-tern applied either on the front or the back of the cell. Additionally, a customized Ink-jet and screen printing systems, coupled with customized substrate handling solution, customized printing algorithms, and a customized ink drying process, in combination with a purchased turn-key line, were used to complete the high efficiency solar cells. This development work delivered a process capable of high volume producing 18.5% efficient crystalline Silicon solar cells and enabled the Innovalight to commercialize its technology by the summer of 2010.« less

Improved Starting Materials for Back-Illuminated Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2009-01-01

An improved type of starting materials for the fabrication of silicon-based imaging integrated circuits that include back-illuminated photodetectors has been conceived, and a process for making these starting materials is undergoing development. These materials are intended to enable reductions in dark currents and increases in quantum efficiencies, relative to those of comparable imagers made from prior silicon-on-insulator (SOI) starting materials. Some background information is prerequisite to a meaningful description of the improved starting materials and process. A prior SOI starting material, depicted in the upper part the figure, includes: a) A device layer on the front side, typically between 2 and 20 m thick, made of p-doped silicon (that is, silicon lightly doped with an electron acceptor, which is typically boron); b) A buried oxide (BOX) layer (that is, a buried layer of oxidized silicon) between 0.2 and 0.5 m thick; and c) A silicon handle layer (also known as a handle wafer) on the back side, between about 600 and 650 m thick. After fabrication of the imager circuitry in and on the device layer, the handle wafer is etched away, the BOX layer acting as an etch stop. In subsequent operation of the imager, light enters from the back, through the BOX layer. The advantages of back illumination over front illumination have been discussed in prior NASA Tech Briefs articles.

Control wafer bow of InGaP on 200 mm Si by strain engineering

NASA Astrophysics Data System (ADS)

Wang, Bing; Bao, Shuyu; Made, Riko I.; Lee, Kwang Hong; Wang, Cong; Eng Kian Lee, Kenneth; Fitzgerald, Eugene A.; Michel, Jurgen

2017-12-01

When epitaxially growing III-V compound semiconductors on Si substrates the mismatch of coefficients of thermal expansion (CTEs) between III-V and Si causes stress and wafer bow. The wafer bow is deleterious for some wafer-scale processing especially when the wafer size is large. Strain engineering was applied in the epitaxy of InGaP films on 200 mm silicon wafers having high quality germanium buffers. By applying compressive strain in the InGaP films to compensate the tensile strain induced by CTE mismatch, wafer bow was decreased from about 100 μm to less than 50 μm. X-ray diffraction studies show a clear trend between the decrease of wafer bow and the compensation of CTE mismatch induced tensile strain in the InGaP layers. In addition, the anisotropic strain relaxation in InGaP films resulted in anisotropic wafer bow along two perpendicular (110) directions. Etch pit density and plane-view transmission electron microscopy characterizations indicate that threading dislocation densities did not change significantly due to the lattice-mismatch applied in the InGaP films. This study shows that strain engineering is an effective method to control wafer bow when growing III-V semiconductors on large size Si substrates.

Slicing of silicon into sheet material. Silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project. Third quarterly report, September 20, 1976--December 19, 1976

DOE Office of Scientific and Technical Information (OSTI.GOV)

Holden, S.C.

1976-12-27

The stability of tensioned blades used in multiblade sawing does not seem to be the limitation in cutting with thin blades. So far, 0.010 cm thick blades have been totally unsuccessful. Recently, 0.015 cm blades have proven successful in wafering, offering an 0.005 cm reduction in the silicon used per slice. The failure of thin blades is characterized as a possible result of blade misalignment or from the inherent uncontrollability of the loose abrasive multiblade process. Corrective procedures will be employed in the assembly of packages to eliminate one type of blade misalignment. Two ingots were sliced with the samemore » batch of standard silicon carbide abrasive slurry to determine the useful lifetime of this expendable material. After 250 slices, the cutting efficiency had not degraded. Further tests will be continued to establish the maximum lifetime of both silicon carbide and boron carbide abrasive. Electron microscopy will be employed to evaluate the wear of abrasive particles in the failure of abrasive slurry. The surface damage of silicon wafers has been characterized as predominantly subsurface fracture. Damage with No. 600 SiC is between 10 and 15 microns into the wafer surface. This agrees well with previous investigations of damage from silicon carbide abrasive papers.« less

Noncontact Measurement of Doping Profile for Bare Silicon

NASA Astrophysics Data System (ADS)

Kohno, Motohiro; Matsubara, Hideaki; Okada, Hiroshi; Hirae, Sadao; Sakai, Takamasa

1998-10-01

In this study, we evaluate the doping concentrations of bare silicon wafers by noncontact capacitance voltage (C V) measurements. The metal-air-insulator-semiconductor (MAIS) method enables the measurement of C V characteristics of silicon wafers without oxidation and electrode preparation. This method has the advantage that a doping profile close to the wafer surface can be obtained. In our experiment, epitaxial silicon wafers were used to compare the MAIS method with the conventional MIS method. The experimental results obtained from the two methods showed good agreement. Then, doping profiles of boron-doped Czochralski (CZ) wafers were measured by the MAIS method. The result indicated a significant reduction of the doping concentration near the wafer surface. This observation is attributed to the well-known deactivation of boron with atomic hydrogen which permeated the silicon bulk during the polishing process. This deactivation was recovered by annealing in air at 180°C for 120 min.

Micro-miniature gas chromatograph column disposed in silicon wafers

DOEpatents

Yu, Conrad M.

2000-01-01

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Polarized Optical Scattering Measurements of Metallic Nanoparticles on a Thin Film Silicon Wafer

NASA Astrophysics Data System (ADS)

Liu, Cheng-Yang; Liu, Tze-An; Fu, Wei-En

2009-09-01

Light scattering has shown its powerful diagnostic capability to characterize optical quality surfaces. In this study, the theory of bidirectional reflectance distribution function (BRDF) was used to analyze the metallic nanoparticles' sizes on wafer surfaces. The BRDF of a surface is defined as the angular distribution of radiance scattered by the surface normalized by the irradiance incident on the surface. A goniometric optical scatter instrument has been developed to perform the BRDF measurements on polarized light scattering on wafer surfaces for the diameter and distribution measurements of metallic nanoparticles. The designed optical scatter instrument is capable of distinguishing various types of optical scattering characteristics, which are corresponding to the diameters of the metallic nanoparticles, near surfaces by using the Mueller matrix calculation. The metallic nanoparticle diameter of measurement is 60 nm on 2 inch thin film wafers. These measurement results demonstrate that the polarization of light scattered by metallic particles can be used to determine the size of metallic nanoparticles on silicon wafers.

Grain-boundary type and distribution in silicon carbide coatings and wafers

NASA Astrophysics Data System (ADS)

Cancino-Trejo, Felix; López-Honorato, Eddie; Walker, Ross C.; Ferrer, Romelia Salomon

2018-03-01

Silicon carbide is the main diffusion barrier against metallic fission products in TRISO (tristructural isotropic) coated fuel particles. The explanation of the accelerated diffusion of silver through SiC has remained a challenge for more than four decades. Although, it is now well accepted that silver diffuse through SiC by grain boundary diffusion, little is known about the characteristics of the grain boundaries in SiC and how these change depending on the type of sample. In this work five different types (coatings and wafers) of SiC produced by chemical vapor deposition were characterized by electron backscatter diffraction (EBSD). The SiC in TRISO particles had a higher concentration of high angle grain boundaries (aprox. 70%) compared to SiC wafers, which ranged between 30 and 60%. Similarly, SiC wafers had a higher concentration of low angle grain boundaries ranging between 15 and 30%, whereas TRISO particles only reached values of around 7%. The same trend remained when comparing the content of coincidence site lattice (CSL) boundaries, since SiC wafers showed a concentration of more than 30%, whilst TRISO particles had contents of around 20%. In all samples the largest fractions of CSL boundaries (3 ≤ Σ ≤ 17) were the Σ3 boundaries. We show that there are important differences between the SiC in TRISO particles and SiC wafers which could explain some of the differences observed in diffusion experiments in the literature.

Emissivity properties of silicon wafers and their application to radiation thermometry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Iuchi, T.; Seo, T.

We studied the spectral and directional emissivities of silicon wafers using an optical polarization technique. Based on the simulation and experimental results, we developed two different radiation thermometry methods for silicon wafers, the first based on a polarized emissivity-invariant condition, and the second based on the relationship between the ratio of the p-to s-polarized radiance and the polarized emissivity. These methods can be performed at temperatures above 600 °C and over a wide wavelength range (0.9∼5 μm), irrespective of dielectric film thickness and substrate resistivity due to the dopant concentrations. Temperature measurements were estimated to have expanded uncertainties (k=2) ofmore » less than 5 °C. A radiometer system with wavelengths above 4.5 μm was successfully developed because the system was not influenced by background noise caused by a high-intensity heating lamp.« less

Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

PubMed

Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

2014-05-13

The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy

NASA Astrophysics Data System (ADS)

Altan, Hakan

All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on transmission and mobility are quantitatively discussed.

Development of a novel precision instrument for high-resolution simultaneous normal and shear force measurements between small planar samples

NASA Astrophysics Data System (ADS)

Lundstrom, Troy; Clark, William; Jalili, Nader

2017-05-01

In the design and development of end effector pads for silicon wafer handling robots, it is imperative that the static friction/adhesion force properties of the pads with respect to a variety of planar surfaces be characterized. In this work, the overall design, calibration, and data acquisition procedure of an instrument developed for performing these measurements on small (<10 mm × 10 mm) planar samples is presented. This device was used to perform adhesion/maximum shear force measurements on polydimethylsiloxane, a silicon wafer, and custom carbon nanotubes forest surfaces. The device was successfully able to measure an effective, mean profile adhesion force of 715 μN between a silicon wafer and a polydimethylsiloxane (2.768 × 10-6 m2) sample. In addition, a nonlinear maximum shear over normal force relationship was also measured between custom carbon nanotubes forest and the silicon wafer surfaces. The maximum shear over a normal force coefficient was found to decrease with increasing initial normal force. Currently, there are numerous devices for measuring normal/shear forces at the nano/micro- and macroscales; however, this device allows for the consistent measurement of these same types of forces on components with surface dimensions ranging from 0.1 mm to 10 mm.

One-step preparation of multiwall carbon nanotube/silicon hybrids for solar energy conversion

NASA Astrophysics Data System (ADS)

Lobiak, Egor V.; Bychanok, Dzmitry S.; Shlyakhova, Elena V.; Kuzhir, Polina P.; Maksimenko, Sergey A.; Bulusheva, Lyubov G.; Okotrub, Alexander V.

2016-03-01

The hybrid material consisting of a thin layer of multiwall carbon nanotubes (MWCNTs) on an n-doped silicon wafer was obtained in one step using an aerosol-assisted catalytic chemical vapor deposition. The MWCNTs were grown from a mixture of acetone and ethanol with ˜0.2 wt.% of iron polyoxomolybdate nanocluster of the keplerate-type structure. The samples produced at 800°C and 1050°C were tested as a solar energy converter. It was shown that photoresponse of the hybrid material significantly depends on the presence of structural defects in MWCNTs, being much higher in the case of more defective nanotubes. This is because defects lead to p-doping of nanotubes, whereas the p-n heterojunction between MWCNTs and silicon provides a high efficiency of the solar cell.

Optimization of Graphene Sensors to Detect Biological Warfare Agents

DTIC Science & Technology

2014-03-27

conductor and a metal at room temperature [53] and in some cases, it acts like a p- type semiconductor [54]. The knowledge of the conductivity ...aptamer functionalized graphene layer interaction was available. Silicon wafers with thermal oxide coats were explored as a next step. The available...picked due to its high electrical conductivity (100,00cm/Vs) and functionalization properties [17]. Figure 1 conceptually represents a graphene-field

Low cost sol-gel derived SiC-SiO2 nanocomposite as anti reflection layer for enhanced performance of crystalline silicon solar cells

NASA Astrophysics Data System (ADS)

Jannat, Azmira; Lee, Woojin; Akhtar, M. Shaheer; Li, Zhen Yu; Yang, O.-Bong

2016-04-01

This paper describes the preparation, characterizations and the antireflection (AR) coating application in crystalline silicon solar cells of sol-gel derived SiC-SiO2 nanocomposite. The prepared SiC-SiO2 nanocomposite was effectively applied as AR layer on p-type Si-wafer via two step processes, where the sol-gel of precursor solution was first coated on p-type Si-wafer using spin coating at 2000 rpm and then subjected to annealing at 450 °C for 1 h. The crystalline, and structural observations revealed the existence of SiC and SiO2 phases, which noticeably confirmed the formation of SiC-SiO2 nanocomposite. The SiC-SiO2 layer on Si solar cells was found to be an excellent AR coating, exhibiting the low reflectance of 7.08% at wavelengths ranging from 400 to 1000 nm. The fabricated crystalline Si solar cell with SiC-SiO2 nanocomposite AR coating showed comparable power conversion efficiency of 16.99% to the conventional SixNx AR coated Si solar cell. New and effective sol-gel derived SiC-SiO2 AR layer would offer a promising technique to produce high performance Si solar cells with low-cost.

High purith low defect FZ silicon

NASA Technical Reports Server (NTRS)

Kimura, H.; Robertson, G.

1985-01-01

The most common intrinsic defects in dislocation-free float zone (FZ) silicon crystals are the A- and B-type swirl defects. The mechanisms of their formation and annihilation have been extensively studied. Another type of defect in dislocation-free FZ crystals is referred to as a D-type defect. Concentrations of these defects can be minimized by optimizing the growth conditions, and the residual swirls can be reduced by the post-growth extrinsic gettering process. Czochralski (Cz) silicon wafers are known to exhibit higher resistance to slip and warpage due to thermal stress than do FZ wafers. The Cz crystals containing dislocations are more resistant to dislocation movement than dislocated FZ crystals because of the locking of dislocations by oxygen atoms present in the Cz crystals. Recently a transverse magnetic field was applied during the FZ growth of extrinsic silicon. Resultant flow patterns, as revealed by striation etching and spreading resistance in Ga-doped silicon crystals, indicate strong effects of the transverse magnetic field on the circulation within the melt. At fields of 5500 gauss, the fluid flow in the melt volume is so altered as to affect the morphology of the growing crystal.

Hybrid single quantum well InP/Si nanobeam lasers for silicon photonics.

PubMed

Fegadolli, William S; Kim, Se-Heon; Postigo, Pablo Aitor; Scherer, Axel

2013-11-15

We report on a hybrid InP/Si photonic crystal nanobeam laser emitting at 1578 nm with a low threshold power of ~14.7 μW. Laser gain is provided from a single InAsP quantum well embedded in a 155 nm InP layer bonded on a standard silicon-on-insulator wafer. This miniaturized nanolaser, with an extremely small modal volume of 0.375(λ/n)(3), is a promising and efficient light source for silicon photonics.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

Tantalum oxide/silicon nitride: A negatively charged surface passivation stack for silicon solar cells

NASA Astrophysics Data System (ADS)

Wan, Yimao; Bullock, James; Cuevas, Andres

2015-05-01

This letter reports effective passivation of crystalline silicon (c-Si) surfaces by thermal atomic layer deposited tantalum oxide (Ta2O5) underneath plasma enhanced chemical vapour deposited silicon nitride (SiNx). Cross-sectional transmission electron microscopy imaging shows an approximately 2 nm thick interfacial layer between Ta2O5 and c-Si. Surface recombination velocities as low as 5.0 cm/s and 3.2 cm/s are attained on p-type 0.8 Ω.cm and n-type 1.0 Ω.cm c-Si wafers, respectively. Recombination current densities of 25 fA/cm2 and 68 fA/cm2 are measured on 150 Ω/sq boron-diffused p+ and 120 Ω/sq phosphorus-diffused n+ c-Si, respectively. Capacitance-voltage measurements reveal a negative fixed insulator charge density of -1.8 × 1012 cm-2 for the Ta2O5 film and -1.0 × 1012 cm-2 for the Ta2O5/SiNx stack. The Ta2O5/SiNx stack is demonstrated to be an excellent candidate for surface passivation of high efficiency silicon solar cells.

Fabrication of close-packed TES microcalorimeter arrays using superconducting molybdenum/gold transition-edge sensors

NASA Astrophysics Data System (ADS)

Finkbeiner, F. M.; Brekosky, R. P.; Chervenak, J. A.; Figueroa-Feliciano, E.; Li, M. J.; Lindeman, M. A.; Stahle, C. K.; Stahle, C. M.; Tralshawala, N.

2002-02-01

We present an overview of our efforts in fabricating Transition-Edge Sensor (TES) microcalorimeter arrays for use in astronomical x-ray spectroscopy. Two distinct types of array schemes are currently pursued: 5×5 single pixel TES array where each pixel is a TES microcalorimeter, and Position-Sensing TES (PoST) array. In the latter, a row of 7 or 15 thermally-linked absorber pixels is read out by two TES at its ends. Both schemes employ superconducting Mo/Au bilayers as the TES. The TES are placed on silicon nitride membranes for thermal isolation from the structural frame. The silicon nitride membranes are prepared by a Deep Reactive Ion Etch (DRIE) process into a silicon wafer. In order to achieve the concept of closely packed arrays without decreasing its structural and functional integrity, we have already developed the technology to fabricate arrays of cantilevered pixel-sized absorbers and slit membranes in silicon nitride films. Furthermore, we have started to investigate ultra-low resistance through-wafer micro-vias to bring the electrical contact out to the back of a wafer. .

Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

NASA Astrophysics Data System (ADS)

Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

2015-04-01

In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on-off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10-13-10-11 µm2/Hz for n-type and 10-12-10-10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

Method for making circular tubular channels with two silicon wafers

DOEpatents

Yu, Conrad M.; Hui, Wing C.

1996-01-01

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Excellent c-Si surface passivation by low-temperature atomic layer deposited titanium oxide

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liao, Baochen, E-mail: liaobaochen@nus.edu.sg; Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117576; A*STAR Institute of Materials Research and Engineering

2014-06-23

In this work, we demonstrate that thermal atomic layer deposited (ALD) titanium oxide (TiO{sub x}) films are able to provide a—up to now unprecedented—level of surface passivation on undiffused low-resistivity crystalline silicon (c-Si). The surface passivation provided by the ALD TiO{sub x} films is activated by a post-deposition anneal and subsequent light soaking treatment. Ultralow effective surface recombination velocities down to 2.8 cm/s and 8.3 cm/s, respectively, are achieved on n-type and p-type float-zone c-Si wafers. Detailed analysis confirms that the TiO{sub x} films are nearly stoichiometric, have no significant level of contaminants, and are of amorphous nature. The passivation is foundmore » to be stable after storage in the dark for eight months. These results demonstrate that TiO{sub x} films are also capable of providing excellent passivation of undiffused c-Si surfaces on a comparable level to thermal silicon oxide, silicon nitride, and aluminum oxide. In addition, it is well known that TiO{sub x} has an optimal refractive index of 2.4 in the visible range for glass encapsulated solar cells, as well as a low extinction coefficient. Thus, the results presented in this work could facilitate the re-emergence of TiO{sub x} in the field of high-efficiency silicon wafer solar cells.« less

Determination of thicknesses and temperatures of crystalline silicon wafers from optical measurements in the far infrared region

NASA Astrophysics Data System (ADS)

Franta, Daniel; Franta, Pavel; Vohánka, Jiří; Čermák, Martin; Ohlídal, Ivan

2018-05-01

Optical measurements of transmittance in the far infrared region performed on crystalline silicon wafers exhibit partially coherent interference effects appropriate for the determination of thicknesses of the wafers. The knowledge of accurate spectral and temperature dependencies of the optical constants of crystalline silicon in this spectral region is crucial for the determination of its thickness and vice versa. The recently published temperature dependent dispersion model of crystalline silicon is suitable for this purpose. Because the linear thermal expansion of crystalline silicon is known, the temperatures of the wafers can be determined with high precision from the evolution of the interference patterns at elevated temperatures.

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

NASA Astrophysics Data System (ADS)

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

The chemo-mechanical effect of cutting fluid on material removal in diamond scribing of silicon

NASA Astrophysics Data System (ADS)

Kumar, Arkadeep; Melkote, Shreyes N.

2017-07-01

The mechanical integrity of silicon wafers cut by diamond wire sawing depends on the damage (e.g., micro-cracks) caused by the cutting process. The damage type and extent depends on the material removal mode, i.e., ductile or brittle. This paper investigates the effect of cutting fluid on the mode of material removal in diamond scribing of single crystal silicon, which simulates the material removal process in diamond wire sawing of silicon wafers. We conducted scribing experiments with a diamond tipped indenter in the absence (dry) and in the presence of a water-based cutting fluid. We found that the cutting mode is more ductile when scribing in the presence of cutting fluid compared to dry scribing. We explain the experimental observations by the chemo-mechanical effect of the cutting fluid on silicon, which lowers its hardness and promotes ductile mode material removal.

Interferometric thickness calibration of 300 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Quandou; Griesmann, Ulf; Polvani, Robert

2005-12-01

The "Improved Infrared Interferometer" (IR 3) at the National Institute of Standards and Technology (NIST) is a phase-measuring interferometer, operating at a wavelength of 1550 nm, which is being developed for measuring the thickness and thickness variation of low-doped silicon wafers with diameters up to 300 mm. The purpose of the interferometer is to produce calibrated silicon wafers, with a certified measurement uncertainty, which can be used as reference wafers by wafer manufacturers and metrology tool manufacturers. We give an overview of the design of the interferometer and discuss its application to wafer thickness measurements. The conversion of optical thickness, as measured by the interferometer, to the wafer thickness requires knowledge of the refractive index of the material of the wafer. We describe a method for measuring the refractive index which is then used to establish absolute thickness and thickness variation maps for the wafer.

1D silicon refractive lenses for surface scattering with high energy x-rays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bertram, F.; Gutowski, O.; Schroer, C.

2016-07-27

At the high energy X-ray beamline P07 at PETRA III, 1D focusing down to 4 micrometer vertical beam height while preserving a horizontal beam width of 0.5 mm was established by refractive lenses etched into a silicon wafer. A single wafer with 8 different lens structures can cover the full energy range between 50 and 120 keV. For surface diffraction on ultrathin films a factor of 4 in intensity can be achieved compared to the already established Al-compound refractive 2D-lenses.

Fabrication of uniform nanoscale cavities via silicon direct wafer bonding.

PubMed

Thomson, Stephen R D; Perron, Justin K; Kimball, Mark O; Mehta, Sarabjit; Gasparini, Francis M

2014-01-09

Measurements of the heat capacity and superfluid fraction of confined (4)He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments(3), bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned(2) in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water(4). The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

Alternate methods of applying diffusants to silicon solar cells. [screen printing of thick-film paste materials and vapor phase transport from solid sources

NASA Technical Reports Server (NTRS)

Brock, T. W.; Field, M. B.

1979-01-01

Low-melting phosphate and borate glasses were screen printed on silicon wafers and heated to form n and p junctions. Data on surface appearance, sheet resistance and junction depth are presented. Similar data are reported for vapor phase transport from sintered aluminum metaphosphate and boron-containing glass-ceramic solid sources. Simultaneous diffusion of an N(+) layer with screen-printed glass and a p(+) layer with screen-printed Al alloy paste was attempted. No p(+) back surface field formation was achieved. Some good cells were produced but the heating in an endless-belt furnace caused a large scatter in sheet resistance and junction depth for three separate lots of wafers.

Criteria for improved open-circuit voltage in a-Si :H(N)/c-Si(P) front heterojunction with intrinsic thin layer solar cells

NASA Astrophysics Data System (ADS)

Nath, Madhumita; Chatterjee, P.; Damon-Lacoste, J.; Roca i Cabarrocas, P.

2008-02-01

Hydrog enated amorphous/crystalline silicon "heterojunction with intrinsic thin layer (HIT)" solar cells have gained popularity after it was demonstrated by Sanyo that they can achieve stable conversion efficiencies, as high as crystalline silicon (c-Si) cells, but where the cost may be reduced with the help of amorphous silicon (a-Si:H) low temperature deposition technology. In this article, we study N-a-Si :H/P-c-Si front HIT structures, where light enters through the N-a-Si :H layer. The aim is to examine ways of improving the open-circuit voltage, using computer modeling in conjunction with experiments. We also assess under which conditions such improvements in Voc actually occur. Modeling indicates that for a density of states Nss⩾1013cm-2 on the surface of the P-c-Si wafer facing the emitter layer, Voc is entirely limited by this parameter and is lower than 0.5V. We also learn that it is possible to increase the Voc to ˜0.73V by reducing this defect density to ˜1010cm-2, by reducing the surface recombination speed of the electrons at the back P-c-Si/aluminum contact (SnL), and by improving the lifetime of the carriers (τ ) in the P-c-Si wafer to ˜5ms. Modeling further indicates that when τ ⩽0.1ms, the sensitivity of Voc to SnL vanishes, as very few back-diffusing electrons can reach the back contact. Improvements in Voc by decreasing both the defect density on the surface of the P-c-Si wafer facing the emitter layer and SnL have been achieved in practice by (a) improved passivation thanks to a thin intrinsic polymorphous silicon layer deposited on the c-Si wafer (instead of a-Si :H) and (b) using localized aluminum and back surface field layers to attain a lower SnL. Experimentally, a Voc of 0.675V has already been attained. Simulations indicate that the lifetime of carriers inside the P-c-Si wafer of these cells is ˜366μs and needs to be improved to achieve a higher Voc.

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

NASA Technical Reports Server (NTRS)

Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

1979-01-01

A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

PubMed

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10more » billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).« less

Synthesis and Characterization of Silicon Nanowires by Electroless Etching

NASA Astrophysics Data System (ADS)

Bhujel, Rabina; Rizal, Umesh; Agarwal, Amit; Swain, Bhabani S.; Swain, Bibhu P.

2018-02-01

Silicon nanowires (SiNWs) were synthesized by two-step electroless etching of p-type Si (100) wafer and characterized by field emission scanning electron microscopy, UV-Vis spectroscopy, x-ray photoelectron spectroscopy, Fourier transform infrared spectroscopy and Raman spectroscopy. The vibrational signature at 1108 and 2087 cm-1 confirmed SiNWs were passivated by both oxygen and hydrogen atoms. Raman peak at 517 cm-1 indicated crystalline SiNWs with tailing toward redshift due to Fano effect. The Si(2p) and Si(2s) core orbital spectra of SiNWs were found at 99.8 and 150.5 eV, respectively. Moreover, the reflection of SiNWs is minimized to 1 to 5% in the 650-nm wavelength.

Performance Evaluations of Ceramic Wafer Seals

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

2006-01-01

Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

Slicing of Silicon into Sheet Material. Silicon Sheet Growth Development for the Large Area Silicon Sheet Task of the Low Cost Solar Array Project

NASA Technical Reports Server (NTRS)

Fleming, J. R.; Holden, S. C.; Wolfson, R. G.

1979-01-01

The use of multiblade slurry sawing to produce silicon wafers from ingots was investigated. The commercially available state of the art process was improved by 20% in terms of area of silicon wafers produced from an ingot. The process was improved 34% on an experimental basis. Economic analyses presented show that further improvements are necessary to approach the desired wafer costs, mostly reduction in expendable materials costs. Tests which indicate that such reduction is possible are included, although demonstration of such reduction was not completed. A new, large capacity saw was designed and tested. Performance comparable with current equipment (in terms of number of wafers/cm) was demonstrated.

Fabrication of a high aspect ratio thick silicon wafer mold and electroplating using flipchip bonding for MEMS applications

NASA Astrophysics Data System (ADS)

Kim, Bong-Hwan; Kim, Jong-Bok

2009-06-01

We have developed a microfabrication process for high aspect ratio thick silicon wafer molds and electroplating using flipchip bonding with THB 151N negative photoresist (JSR micro). This fabrication technique includes large area and high thickness silicon wafer mold electroplating. The process consists of silicon deep reactive ion etching (RIE) of the silicon wafer mold, photoresist bonding between the silicon mold and the substrate, nickel electroplating and a silicon removal process. High thickness silicon wafer molds were made by deep RIE and flipchip bonding. In addition, nickel electroplating was developed. Dry film resist (ORDYL MP112, TOK) and thick negative-tone photoresist (THB 151N, JSR micro) were used as bonding materials. In order to measure the bonding strength, the surface energy was calculated using a blade test. The surface energy of the bonding wafers was found to be 0.36-25.49 J m-2 at 60-180 °C for the dry film resist and 0.4-1.9 J m-2 for THB 151N in the same temperature range. Even though ORDYL MP112 has a better value of surface energy than THB 151N, it has a critical disadvantage when it comes to removing residue after electroplating. The proposed process can be applied to high aspect ratio MEMS structures, such as air gap inductors or vertical MEMS probe tips.

Multi-wire slurry wafering demonstrations. [slicing silicon ingots for solar arrays

NASA Technical Reports Server (NTRS)

Chen, C. P.

1978-01-01

Ten slicing demonstrations on a multi-wire slurry saw, made to evaluate the silicon ingot wafering capabilities, reveal that the present sawing capabilities can provide usable wafer area from an ingot 1.05m/kg (e.g. kerf width 0.135 mm and wafer thickness 0.265 mm). Satisfactory surface qualities and excellent yield of silicon wafers were found. One drawback is that the add-on cost of producing water from this saw, as presently used, is considerably higher than other systems being developed for the low-cost silicon solar array project (LSSA), primarily because the saw uses a large quantity of wire. The add-on cost can be significantly reduced by extending the wire life and/or by rescue of properly plated wire to restore the diameter.

Influence of the doping level on the porosity of silicon nanowires prepared by metal-assisted chemical etching

NASA Astrophysics Data System (ADS)

Geyer, Nadine; Wollschläger, Nicole; Fuhrmann, Bodo; Tonkikh, Alexander; Berger, Andreas; Werner, Peter; Jungmann, Marco; Krause-Rehberg, Reinhard; Leipner, Hartmut S.

2015-06-01

A systematic method to control the porosity of silicon nanowires is presented. This method is based on metal-assisted chemical etching (MACE) and takes advantage of an HF/H2O2 etching solution and a silver catalyst in the form of a thin patterned film deposited on a doped silicon wafer. It is found that the porosity of the etched nanowires can be controlled by the doping level of the wafer. For low doping concentrations, the wires are primarily crystalline and surrounded by only a very thin layer of porous silicon (pSi) layer, while for highly doped silicon, they are porous in their entire volume. We performed a series of controlled experiments to conclude that there exists a well-defined critical doping concentration separating the crystalline and porous regimes. Furthermore, transmission electron microscopy investigations showed that the pSi has also a crystalline morphology on a length scale smaller than the pore size, determined from positron annihilation lifetime spectroscopy to be mesoscopic. Based on the experimental evidence, we devise a theoretical model of the pSi formation during MACE and apply it for better control of the nanowire morphology.

Dip coating process: Silicon sheet growth development for the large-area silicon sheet task of the low-cost silicon solar array project

NASA Technical Reports Server (NTRS)

Heaps, J. D.; Maciolek, R. B.; Harrison, W. B.; Wolner, H. A.; Hendrickson, G.; Nelson, L. D.

1976-01-01

To date, an experimental dip-coating facility was constructed. Using this facility, relatively thin (1 mm) mullite and alumina substrates were successfully dip-coated with 2.5 - 3.0 ohm-cm, p-type silicon with areas of approximately 20 sq cm. The thickness and grain size of these coatings are influenced by the temperature of the melt and the rate at which the substrate is pulled from the melt. One mullite substrate had dendrite-like crystallites of the order of 1 mm wide and 1 to 2 cm long. Their axes were aligned along the direction of pulling. A large variety of substrate materials were purchased or developed enabling the program to commence a substrate definition evaluation. Due to the insulating nature of the substrate, the bottom layer of the p-n junction may have to be made via the top surface. The feasibility of accomplishing this was demonstrated using single crystal wafers.

PDMS spreading morphological patterns on substrates of different hydrophilicity in air vacuum and water.

PubMed

Zbik, Marek S; Frost, Ray L

2010-04-15

In paper has been to investigate the morphological patterns and kinetics of PDMS spreading on silicon wafer using combination of techniques like ellipsometry, atomic force microscope (AFM), scanning electron microscope (SEM) and optical microscopy. A macroscopic silicone oil drops as well as PDMS water based emulsions were studied after deposition on a flat surface of silicon wafer in air, water and vacuum. Our own measurements using an imaging ellipsometer, which also clearly shows the presence of a precursor film. The diffusion constant of this film, measured with a 60,000 cS PDMS sample spreading on a hydrophilic silicon wafer is D(f)=1.4x10(-11) m(2)/s. Regardless of their size, density and method of deposition, droplets on both types of wafer (hydrophilic and hydrophobic) flatten out over a period of many hours, up to 3 days. During this process neighbouring droplets may coalesce, but there is strong evidence that some of the PDMS from the droplets migrates into a thin, continuous film that covers the surface in between droplets. The thin film appears to be ubiquitous if there has been any deposition of PDMS. However, this statement needs further verification. One question is whether the film forms immediately after forced drying, or whether in some or all cases it only forms by spreading from isolated droplets as they slowly flatten out. 2010 Elsevier Inc. All rights reserved.

Method for making circular tubular channels with two silicon wafers

DOEpatents

Yu, C.M.; Hui, W.C.

1996-11-19

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

Robustness up to 400°C of the passivation of c-Si by p-type a-Si:H thanks to ion implantation

NASA Astrophysics Data System (ADS)

Defresne, A.; Plantevin, O.; Roca i Cabarrocas, Pere

2016-12-01

Heterojunction solar cells based on crystalline silicon (c-Si) passivated by hydrogenated amorphous silicon (a-Si:H) thin films are one of the most promising architectures for high energy conversion efficiency. Indeed, a-Si:H thin films can passivate both p-type and n-type wafers and can be deposited at low temperature (<200°C) using PECVD. However, such passivation layers, in particular p-type a-Si:H, show a dramatic degradation in passivation quality above 200°C. Yet, annealing at 300 - 400°C the TCO layer and metallic contacts is highly desirable to reduce the contact resistance as well as the TCO optical absorption. In this work, we show that as expected, ion implantation (5 - 30 keV) introduces defects at the c-Si/a-Si:H interface which strongly degrade the effective lifetime, down to a few micro-seconds. However, the passivation quality can be restored and lifetime values can be improved up to 2 ms over the initial value with annealing. We show here that effective lifetimes above 1 ms can be maintained up to 380°C, opening up the possibility for higher process temperatures in silicon heterojunction device fabrication.

Doping of silicon by carbon during laser ablation process

NASA Astrophysics Data System (ADS)

Raciukaitis, G.; Brikas, M.; Kazlauskiene, V.; Miskinis, J.

2007-04-01

Effect of laser ablation on properties of remaining material was investigated in silicon. It was established that laser cutting of wafers in air induced doping of silicon by carbon. The effect was found to be more distinct by the use of higher laser power or UV radiation. Carbon ions created bonds with silicon in the depth of silicon. Formation of the silicon carbide type bonds was confirmed by SIMS, XPS and AES measurements. Modeling of the carbon diffusion was performed to clarify its depth profile in silicon. Photo-chemical reactions of such type changed the structure of material and could be a reason for the reduced quality of machining. A controlled atmosphere was applied to prevent carbonization of silicon during laser cutting.

Fast Pulling of n-Type Si Ingots for Enhanced Si Solar Cell Production

NASA Astrophysics Data System (ADS)

Kim, Kwanghun; Park, Sanghyun; Park, Jaechang; Pang, Ilsun; Ryu, Sangwoo; Oh, Jihun

2018-07-01

Reducing the manufacturing costs of silicon substrates is an important issue in the silicon-based solar cell industry. In this study, we developed a high-throughput ingot growth method by accelerating the pulling speed in the Czochralski process. By controlling the heat flow of the ingot growth chamber and at the solid-liquid interfaces, the pulling speed of an ingot could be increased by 15% compared to the conventional method, while retaining high quality. The wafer obtained at a high pulling speed showed an enhanced minority carrier lifetime compared with conventional wafers, due to the vacancy passivation effect, and also demonstrated comparable bulk resistivity and impurities. The results in this work are expected to open a new way to enhance the productivity of Si wafers used for Si solar cells, and therefore, to reduce the overall manufacturing cost.

Fast Pulling of n-Type Si Ingots for Enhanced Si Solar Cell Production

NASA Astrophysics Data System (ADS)

Kim, Kwanghun; Park, Sanghyun; Park, Jaechang; Pang, Ilsun; Ryu, Sangwoo; Oh, Jihun

2018-03-01

Reducing the manufacturing costs of silicon substrates is an important issue in the silicon-based solar cell industry. In this study, we developed a high-throughput ingot growth method by accelerating the pulling speed in the Czochralski process. By controlling the heat flow of the ingot growth chamber and at the solid-liquid interfaces, the pulling speed of an ingot could be increased by 15% compared to the conventional method, while retaining high quality. The wafer obtained at a high pulling speed showed an enhanced minority carrier lifetime compared with conventional wafers, due to the vacancy passivation effect, and also demonstrated comparable bulk resistivity and impurities. The results in this work are expected to open a new way to enhance the productivity of Si wafers used for Si solar cells, and therefore, to reduce the overall manufacturing cost.

Lasers in energy device manufacturing

NASA Astrophysics Data System (ADS)

Ostendorf, A.; Schoonderbeek, A.

2008-02-01

Global warming is a current topic all over the world. CO II emissions must be lowered to stop the already started climate change. Developing regenerative energy sources, like photovoltaics and fuel cells contributes to the solution of this problem. Innovative technologies and strategies need to be competitive with conventional energy sources. During the last years, the photovoltaic solar cell industry has experienced enormous growth. However, for solar cells to be competitive on the longer term, both an increase in efficiency as well as reduction in costs is necessary. An effective method to reduce costs of silicon solar cells is reducing the wafer thickness, because silicon makes up a large part of production costs. Consequently, contact free laser processing has a large advantage, because of the decrease in waste materials due to broken wafers as caused by other manufacturing processes. Additionally, many novel high efficiency solar cell concepts are only economically feasible with laser technology, e.g. for scribing silicon thin-film solar cells. This paper describes laser hole drilling, structuring and texturing of silicon wafer based solar cells and describes thin film solar cell scribing. Furthermore, different types of lasers are discussed with respect to processing quality and time.

Crystallographic Orientation Identification in Multicrystalline Silicon Wafers Using NIR Transmission Intensity

NASA Astrophysics Data System (ADS)

Skenes, Kevin; Kumar, Arkadeep; Prasath, R. G. R.; Danyluk, Steven

2018-02-01

Near-infrared (NIR) polariscopy is a technique used for the non-destructive evaluation of the in-plane stresses in photovoltaic silicon wafers. Accurate evaluation of these stresses requires correct identification of the stress-optic coefficient, a material property which relates photoelastic parameters to physical stresses. The material stress-optic coefficient of silicon varies with crystallographic orientation. This variation poses a unique problem when measuring stresses in multicrystalline silicon (mc-Si) wafers. This paper concludes that the crystallographic orientation of silicon can be estimated by measuring the transmission of NIR light through the material. The transmission of NIR light through monocrystalline wafers of known orientation were compared with the transmission of NIR light through various grains in mc-Si wafers. X-ray diffraction was then used to verify the relationship by obtaining the crystallographic orientations of these assorted mc-Si grains. Variation of transmission intensity for different crystallographic orientations is further explained by using planar atomic density. The relationship between transmission intensity and planar atomic density appears to be linear.

The Imaging Properties of a Silicon Wafer X-Ray Telescope

NASA Technical Reports Server (NTRS)

Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

1994-01-01

Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE PAGES

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; ...

2015-10-15

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

NASA Astrophysics Data System (ADS)

Green, Martin A.

2014-03-01

Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Guided ultrasonic wave beam skew in silicon wafers

NASA Astrophysics Data System (ADS)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2018-04-01

In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

Formation and characterization of ZnS/CdS nanocomposite materials into porous silicon

NASA Astrophysics Data System (ADS)

Xue, Tao; Lv, Xiao-yi; Jia, Zhen-hong; Hou, Jun-wei; Jian, Ji-kang

2008-11-01

ZnS/CdS were deposited by chemical vapor deposition (CVD) technique on porous silicon substrates formed by electrochemical anodization of n-type (100) silicon wafer. The optical properties of ZnS/CdS porous silicon composite materials are studied. The results showed that new luminescence characteristics such as strong and stable visible-light emissions with different colors were observed from the ZnS/CdS-PS nanocomposite materials at room temperature.

Laser doping of boron-doped Si paste for high-efficiency silicon solar cells

NASA Astrophysics Data System (ADS)

Tomizawa, Yuka; Imamura, Tetsuya; Soeda, Masaya; Ikeda, Yoshinori; Shiro, Takashi

2015-08-01

Boron laser doping (LD) is a promising technology for high-efficiency solar cells such as p-type passivated locally diffused solar cells and n-type Si-wafer-based solar cells. We produced a printable phosphorus- or boron-doped Si paste (NanoGram® Si paste/ink) for use as a diffuser in the LD process. We used the boron LD process to fabricate high-efficiency passivated emitter and rear locally diffused (PERL) solar cells. PERL solar cells on Czochralski Si (Cz-Si) wafers yielded a maximum efficiency of 19.7%, whereas the efficiency of a reference cell was 18.5%. Fill factors above 79% and open circuit voltages above 655 mV were measured. We found that the boron-doped area effectively performs as a local boron back surface field (BSF). The characteristics of the solar cell formed using NanoGram® Si paste/ink were better than those of the reference cell.

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Investigating reliability attributes of silicon photovoltaic cells - An overview

NASA Technical Reports Server (NTRS)

Royal, E. L.

1982-01-01

Reliability attributes are being developed on a wide variety of advanced single-crystal silicon solar cells. Two separate investigations: cell-contact integrity (metal-to-silicon adherence), and cracked cells identified with fracture-strength-reducing flaws are discussed. In the cell-contact-integrity investigation, analysis of contact pull-strength data shows that cell types made with different metallization technologies, i.e., vacuum, plated, screen-printed and soldered, have appreciably different reliability attributes. In the second investigation, fracture strength was measured using Czochralski wafers and cells taken at various stages of processing and differences were noted. Fracture strength, which is believed to be governed by flaws introduced during wafer sawing, was observed to improve (increase) after chemical polishing and other process steps that tend to remove surface and edge flaws.

Carrier transport and sensitivity issues in heterojunction with intrinsic thin layer solar cells on N-type crystalline silicon: A computer simulation study

NASA Astrophysics Data System (ADS)

Rahmouni, M.; Datta, A.; Chatterjee, P.; Damon-Lacoste, J.; Ballif, C.; Roca i Cabarrocas, P.

2010-03-01

Heterojunction with intrinsic thin layer or "HIT" solar cells are considered favorable for large-scale manufacturing of solar modules, as they combine the high efficiency of crystalline silicon (c-Si) solar cells, with the low cost of amorphous silicon technology. In this article, based on experimental data published by Sanyo, we simulate the performance of a series of HIT cells on N-type crystalline silicon substrates with hydrogenated amorphous silicon (a-Si:H) emitter layers, to gain insight into carrier transport and the general functioning of these devices. Both single and double HIT structures are modeled, beginning with the initial Sanyo cells having low open circuit voltages but high fill factors, right up to double HIT cells exhibiting record values for both parameters. The one-dimensional numerical modeling program "Amorphous Semiconductor Device Modeling Program" has been used for this purpose. We show that the simulations can correctly reproduce the electrical characteristics and temperature dependence for a set of devices with varying I-layer thickness. Under standard AM1.5 illumination, we show that the transport is dominated by the diffusion mechanism, similar to conventional P/N homojunction solar cells, and tunneling is not required to describe the performance of state-of-the art devices. Also modeling has been used to study the sensitivity of N-c-Si HIT solar cell performance to various parameters. We find that the solar cell output is particularly sensitive to the defect states on the surface of the c-Si wafer facing the emitter, to the indium tin oxide/P-a-Si:H front contact barrier height and to the band gap and activation energy of the P-a-Si:H emitter, while the I-a-Si:H layer is necessary to achieve both high Voc and fill factor, as it passivates the defects on the surface of the c-Si wafer. Finally, we describe in detail for most parameters how they affect current transport and cell properties.

A new approach to measure the temperature in rapid thermal processing

NASA Astrophysics Data System (ADS)

Yan, Jiang

This dissertation has presented the research work about a new method to measure the temperatures for the silicon wafer. The new technology is mainly for the rapid thermal processing (RTP) system. RTP is a promising technology in semiconductor manufacturing especially for the devices with minimum feature size less than 0.5 μm. The technique to measure the temperatures of the silicon wafer accurately is the key factor to apply the RTP technology to more critical processes in the manufacturing. Two methods which are mostly used nowadays, thermocouples and pyrometer, all have the limitation to be applied in the RTP. This is the motivation to study the new method using acoustic waves for the temperature measurement. The test system was designed and built up for the study of the acoustic method. The whole system mainly includes the transducer unit, circuit hardware, control software, the computer, and the chamber. The acoustic wave was generated by the PZT-5H transducer. The wave travels through the quartz rod into the silicon wafer. After traveling a certain distances in the wafer, the acoustic waves could be received by other transducers. By measuring the travel time and with the travel distance, the velocity of the acoustic wave traveling in the silicon wafer can be calculated. Because there is a relationship between the velocity and the temperature: the velocities of the acoustic waves traveling in the silicon wafer decrease as the temperatures of the wafer increase, the temperature of the wafer can be finally obtained. The thermocouples were used to check the measurement accuracy of the acoustic method. The temperature mapping across the 8″ silicon wafer was obtained with four transducer sensor unit. The temperatures of the wafer were measured using acoustic method at both static and dynamic status. The main purpose of the tests is to know the measurement accuracy for the new method. The goal of the research work regarding to the accuracy is <=+/-3°C. The measurement was also done under the different wafer conditions in order to clarify that the acoustic method is independent of the wafer conditions.

Slicing of silicon into sheet material: Silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project

NASA Technical Reports Server (NTRS)

Holden, S. C.

1976-01-01

Multiblade slurry sawing is used to slice 10 cm diameter silicon ingots into wafers 0.024 cm thick using 0.050 cm of silicon per slice (0.026 cm kerf loss). Total slicing time is less than twenty hours, and 143 slices are produced simultaneously. Productivity (slice area per hour per blade) is shown as a function or blade load and thickness, and abrasive size. Finer abrasive slurries cause a reduction in slice productivity, and thin blades cause a reduction of wafer accuracy. Sawing induced surface damage is found to extend 18 microns into the wafer.

Doping of silicon with carbon during laser ablation process

NASA Astrophysics Data System (ADS)

Račiukaitis, G.; Brikas, M.; Kazlauskienė, V.; Miškinis, J.

2006-12-01

The effect of laser ablation on properties of remaining material in silicon was investigated. It was found that laser cutting of wafers in the air induced the doping of silicon with carbon. The effect was more distinct when using higher laser power or UV radiation. Carbon ions created bonds with silicon atoms in the depth of the material. Formation of the silicon carbide type bonds was confirmed by SIMS, XPS and AES measurements. Modeling of the carbon diffusion to clarify its depth profile in silicon was performed. Photochemical reactions of such type changed the structure of material and could be the reason of the reduced machining quality. The controlled atmosphere was applied to prevent carbonization of silicon during laser cutting.

Optimization of the Surface Structure on Black Silicon for Surface Passivation

NASA Astrophysics Data System (ADS)

Jia, Xiaojie; Zhou, Chunlan; Wang, Wenjing

2017-03-01

Black silicon shows excellent anti-reflection and thus is extremely useful for photovoltaic applications. However, its high surface recombination velocity limits the efficiency of solar cells. In this paper, the effective minority carrier lifetime of black silicon is improved by optimizing metal-catalyzed chemical etching (MCCE) method, using an Al2O3 thin film deposited by atomic layer deposition (ALD) as a passivation layer. Using the spray method to eliminate the impact on the rear side, single-side black silicon was obtained on n-type solar grade silicon wafers. Post-etch treatment with NH4OH/H2O2/H2O mixed solution not only smoothes the surface but also increases the effective minority lifetime from 161 μs of as-prepared wafer to 333 μs after cleaning. Moreover, adding illumination during the etching process results in an improvement in both the numerical value and the uniformity of the effective minority carrier lifetime.

Optimization of the Surface Structure on Black Silicon for Surface Passivation.

PubMed

Jia, Xiaojie; Zhou, Chunlan; Wang, Wenjing

2017-12-01

Black silicon shows excellent anti-reflection and thus is extremely useful for photovoltaic applications. However, its high surface recombination velocity limits the efficiency of solar cells. In this paper, the effective minority carrier lifetime of black silicon is improved by optimizing metal-catalyzed chemical etching (MCCE) method, using an Al 2 O 3 thin film deposited by atomic layer deposition (ALD) as a passivation layer. Using the spray method to eliminate the impact on the rear side, single-side black silicon was obtained on n-type solar grade silicon wafers. Post-etch treatment with NH 4 OH/H 2 O 2 /H 2 O mixed solution not only smoothes the surface but also increases the effective minority lifetime from 161 μs of as-prepared wafer to 333 μs after cleaning. Moreover, adding illumination during the etching process results in an improvement in both the numerical value and the uniformity of the effective minority carrier lifetime.

Passivation mechanism in silicon heterojunction solar cells with intrinsic hydrogenated amorphous silicon oxide layers

NASA Astrophysics Data System (ADS)

Deligiannis, Dimitrios; van Vliet, Jeroen; Vasudevan, Ravi; van Swaaij, René A. C. M. M.; Zeman, Miro

2017-02-01

In this work, we use intrinsic hydrogenated amorphous silicon oxide layers (a-SiOx:H) with varying oxygen content (cO) but similar hydrogen content to passivate the crystalline silicon wafers. Using our deposition conditions, we obtain an effective lifetime (τeff) above 5 ms for cO ≤ 6 at. % for passivation layers with a thickness of 36 ± 2 nm. We subsequently reduce the thickness of the layers using an accurate wet etching method to ˜7 nm and deposit p- and n-type doped layers fabricating a device structure. After the deposition of the doped layers, τeff appears to be predominantly determined by the doped layers themselves and is less dependent on the cO of the a-SiOx:H layers. The results suggest that τeff is determined by the field-effect rather than by chemical passivation.

Novel ultra-lightweight and high-resolution MEMS x-ray optics

NASA Astrophysics Data System (ADS)

Mitsuishi, Ikuyuki; Ezoe, Yuichiro; Takagi, Utako; Mita, Makoto; Riveros, Raul; Yamaguchi, Hitomi; Kato, Fumiki; Sugiyama, Susumu; Fujiwara, Kouzou; Morishita, Kohei; Nakajima, Kazuo; Fujihira, Shinya; Kanamori, Yoshiaki; Yamasaki, Noriko Y.; Mitsuda, Kazuhisa; Maeda, Ryutaro

2009-05-01

We have been developing ultra light-weight X-ray optics using MEMS (Micro Electro Mechanical Systems) technologies.We utilized crystal planes after anisotropic wet etching of silicon (110) wafers as X-ray mirrors and succeeded in X-ray reflection and imaging. Since we can etch tiny pores in thin wafers, this type of optics can be the lightest X-ray telescope. However, because the crystal planes are alinged in certain directions, we must approximate ideal optical surfaces with flat planes, which limits angular resolution of the optics on the order of arcmin. In order to overcome this issue, we propose novel X-ray optics based on a combination of five recently developed MEMS technologies, namely silicon dry etching, X-ray LIGA, silicon hydrogen anneal, magnetic fluid assisted polishing and hot plastic deformation of silicon. In this paper, we describe this new method and report on our development of X-ray mirrors fabricated by these technologies and X-ray reflection experiments of two types of MEMS X-ray mirrors made of silicon and nickel. For the first time, X-ray reflections on these mirrors were detected in the angular response measurements. Compared to model calculations, surface roughness of the silicon and nickel mirrors were estimated to be 5 nm and 3 nm, respectively.

Oxygen precipitation and bulk microdefects induced by the pre- and postepitaxial annealing in N/N + (100) silicon wafers

NASA Astrophysics Data System (ADS)

Wijaranakula, W.; Matlock, J. H.; Mollenkopf, H.

1987-12-01

Substrate wafers used for fabrication of epitaxial silicon wafers heavily doped with antimony at the concentration of 1020 atoms/cm3 were preannealed at a temperature between 500 and 900 °C prior to epitaxial deposition. Device fabrication thermal simulation was performed by heat treating the preannealed epitaxial wafers at 1050 °C in dry oxygen ambient for 16 h. Postepitaxial nucleation heat treatment at 750 °C for 4 h prior to the 1050 °C heat treament cycle was also applied on some epitaxial wafers for the purpose of enhancing the oxygen precipitation in silicon. It was observed that morphology and density of the bulk defects induced by the thermal treatment are affected by the preannealing temperature. The results also indicate that nucleation and growth kinetics of oxygen precipitates in preannealed n+ degenerate silicon substrate is strongly governed by oxygen and point defect diffusion.

The uses of Man-Made diamond in wafering applications

NASA Technical Reports Server (NTRS)

Fallon, D. B.

1982-01-01

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

NASA Astrophysics Data System (ADS)

Miki, N.; Spearing, S. M.

2003-11-01

Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

CuO-Functionalized Silicon Photoanodes for Photoelectrochemical Water Splitting Devices.

PubMed

Shi, Yuanyuan; Gimbert-Suriñach, Carolina; Han, Tingting; Berardi, Serena; Lanza, Mario; Llobet, Antoni

2016-01-13

One main difficulty for the technological development of photoelectrochemical (PEC) water splitting (WS) devices is the fabrication of active, stable and cost-effective photoelectrodes that ensure high performance. Here, we report the development of a CuO/Silicon based photoanode, which shows an onset potential for the water oxidation of 0.53 V vs SCE at pH 9, that is, an overpotential of 75 mV, and high stability above 10 h. These values account for a photovoltage of 420 mV due to the absorbed photons by silicon, as proven by comparing with analogous CuO/FTO electrodes that are not photoactive. The photoanodes have been fabricated by sputtering a thin film of Cu(0) on commercially available n-type Si wafers, followed by a photoelectrochemical treatment in basic pH conditions. The resulting CuO/Cu layer acts as (1) protective layer to avoid the corrosion of nSi, (2) p-type hole conducting layer for efficient charge separation and transportation, and (3) electrocatalyst to reduce the overpotential of the water oxidation reaction. The low cost, low toxicity, and good performance of CuO-based coatings can be an attractive solution to functionalize unstable materials for solar energy conversion.

Electrical and optical properties of sub-10 nm nickel silicide films for silicon solar cells

NASA Astrophysics Data System (ADS)

Brahmi, Hatem; Ravipati, Srikanth; Yarali, Milad; Shervin, Shahab; Wang, Weijie; Ryou, Jae-Hyun; Mavrokefalos, Anastassios

2017-01-01

Highly conductive and transparent films of ultra-thin p-type nickel silicide films have been prepared by RF magnetron sputtering of nickel on silicon substrates followed by rapid thermal annealing in an inert environment in the temperature range 400-600 °C. The films are uniform throughout the wafer with thicknesses in the range of 3-6 nm. The electrical and optical properties are presented for nickel silicide films with varying thickness. The Drude-Lorentz model and Fresnel equations were used to calculate the dielectric properties, sheet resistance, absorption and transmission of the films. These ultrathin nickel silicide films have excellent optoelectronic properties for p-type contacts with optical transparencies up to 80% and sheet resistance as low as ~0.15 µΩ cm. Furthermore, it was shown that the use of a simple anti-reflection (AR) coating can recover most of the reflected light approaching the values of a standard Si solar cell with the same AR coating. Overall, the combination of ultra-low thickness, high transmittance, low sheet resistance and ability to recover the reflected light by utilizing standard AR coating makes them ideal for utilization in silicon based photovoltaic technologies as a p-type transparent conductor.

Light Enhanced Hydrofluoric Acid Passivation: A Sensitive Technique for Detecting Bulk Silicon Defects

PubMed Central

Grant, Nicholas E.

2016-01-01

A procedure to measure the bulk lifetime (>100 µsec) of silicon wafers by temporarily attaining a very high level of surface passivation when immersing the wafers in hydrofluoric acid (HF) is presented. By this procedure three critical steps are required to attain the bulk lifetime. Firstly, prior to immersing silicon wafers into HF, they are chemically cleaned and subsequently etched in 25% tetramethylammonium hydroxide. Secondly, the chemically treated wafers are then placed into a large plastic container filled with a mixture of HF and hydrochloric acid, and then centered over an inductive coil for photoconductance (PC) measurements. Thirdly, to inhibit surface recombination and measure the bulk lifetime, the wafers are illuminated at 0.2 suns for 1 min using a halogen lamp, the illumination is switched off, and a PC measurement is immediately taken. By this procedure, the characteristics of bulk silicon defects can be accurately determined. Furthermore, it is anticipated that a sensitive RT surface passivation technique will be imperative for examining bulk silicon defects when their concentration is low (<1012 cm-3). PMID:26779939

Investigation of direct current electrical properties of electrochemically etched mesoporous silicon carbide

NASA Astrophysics Data System (ADS)

Gautier, G.; Biscarrat, J.; Defforge, T.; Fèvre, A.; Valente, D.; Gary, A.; Menard, S.

2014-12-01

In this study, we show I-V characterizations of various metal/porous silicon carbide (pSiC)/silicon carbide (SiC) structures. SiC wafers were electrochemically etched from the Si and C faces in the dark or under UV lighting leading to different pSiC morphologies. In the case of low porosity pSiC etched in the dark, the I-V characteristics were found to be almost linear and the extracted resistivities of pSiC were around 1.5 × 104 Ω cm at 30 °C for the Si face. This is around 6 orders of magnitude higher than the resistivity of doped SiC wafers. In the range of 20-200 °C, the activation energy was around 50 meV. pSiC obtained from the C face was less porous and the measured average resistivity was 10 Ω cm. In the case high porosity pSiC etched under UV illumination, the resistivity was found to be much higher, around 1014 Ω cm at room temperature. In this case, the extracted activation energy was estimated to be 290 meV.

Comparison of cross-sectional transmission electron microscope studies of thin germanium epilayers grown on differently oriented silicon wafers.

PubMed

Norris, D J; Myronov, M; Leadley, D R; Walther, T

2017-12-01

We compare transmission electron microscopical analyses of the onset of islanding in the germanium-on-silicon (Ge/Si) system for three different Si substrate orientations: (001), (11¯0) and (11¯1)Si. The Ge was deposited by reduced pressure chemical vapour deposition and forms islands on the surface of all Si wafers; however, the morphology (aspect ratio) of the deposited islands is different for each type of wafer. Moreover, the mechanism for strain relaxation is different for each type of wafer owing to the different orientation of the (111) slip planes with the growth surface. Ge grown on (001)Si is initially pseudomorphically strained, yielding small, almost symmetrical islands of high aspect ratio (clusters or domes) on top interdiffused SiGe pedestals, without any evidence of plastic relaxation by dislocations, which would nucleate later-on when the islands might have coalesced and then the Matthews-Blakeslee limit is reached. For (11¯0)Si, islands are flatter and more asymmetric, and this is correlated with plastic relaxation of some islands by dislocations. In the case of growth on (11¯1)Si wafers, there is evidence of immediate strain relaxation taking place by numerous dislocations and also twinning. In the case of untwined film/substrate interfaces, Burgers circuits drawn around certain (amorphous-like) regions show a nonclosure with an edge-type a/4[1¯12] Burgers vector component visible in projection along [110]. Microtwins of multiples of half unit cells in thickness have been observed which occur at the growth interface between the Si(11¯1) buffer layer and the overlying Ge material. Models of the growth mechanisms to explain the interfacial configurations of each type of wafer are suggested. © 2017 The Authors Journal of Microscopy © 2017 Royal Microscopical Society.

Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

NASA Astrophysics Data System (ADS)

Ostapenko, S.; Tarasov, I.

2000-04-01

A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

Material electronic quality specifications for polycrystalline silicon wafers

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-06-01

As the use of polycrystalline silicon wafers has expanded in the photovoltaic industry, the need grows for monitoring and qualification techniques for as-grown material that can be used to optimize crystal growth and help predict solar cell performance. Particular needs are for obtaining quantitative measures over full wafer areas of the effects of lifetime limiting defects and of the lifetime upgrading taking place during solar cell processing. We review here the approaches being pursued in programs under way to develop material quality specifications for thin Edge-defined Film-fed Growth (EFG) polycrystalline silicon as-grown wafers. These studies involve collaborations between Mobil Solar, and NREL and university-based laboratories.

Model-based correction for local stress-induced overlay errors

NASA Astrophysics Data System (ADS)

Stobert, Ian; Krishnamurthy, Subramanian; Shi, Hongbo; Stiffler, Scott

2018-03-01

Manufacturing embedded DRAM deep trench capacitors can involve etching very deep holes into silicon wafers1. Due to various design constraints, these holes may not be uniformly distributed across the wafer surface. Some wafer processing steps for these trenches results in stress effects which can distort the silicon wafer in a manner that creates localized alignment issues between the trenches and the structures built above them on the wafer. In this paper, we describe a method to model these localized silicon distortions for complex layouts involving billions of deep trench structures. We describe wafer metrology techniques and data which have been used to verify the stress distortion model accuracy. We also provide a description of how this kind of model can be used to manipulate the polygons in the mask tape out flow to compensate for predicted localized misalignments between design shapes from a deep trench mask and subsequent masks.

Intrinsic Gettering in Nitrogen-Doped and Hydrogen-Annealed Czochralski-Grown Silicon Wafers

NASA Astrophysics Data System (ADS)

Goto, Hiroyuki; Pan, Lian-Sheng; Tanaka, Masafumi; Kashima, Kazuhiko

2001-06-01

The properties of nitrogen-doped and hydrogen-annealed Czochralski-grown silicon (NHA-CZ-Si) wafers were investigated in this study. The quality of the subsurface was investigated by monitoring the generation lifetime of minority carriers, as measured by the capacitance-time measurements of a metal oxide silicon capacitor (MOS C-t). The intrinsic gettering (IG) ability was investigated by determining the nickel concentration on the surface and in the subsurface as measured by graphite furnace atomic absorption spectrometry (GFAAS) after the wafer was deliberately contaminated with nickel. From the results obtained, the generation lifetimes of these NHA-CZ-Si wafers were determined to be almost the same as, or a little longer than those of epitaxial wafers, and the IG ability was proportional to the total volume of oxygen precipitates [i.e., bulk micro defects (BMDs)], which was influenced by the oxygen and nitrogen concentrations in the wafers. Therefore, it is suggested that the subsurface of the NHA-CZ-Si wafers is of good quality and the IG capacity is controllable by the nitrogen and oxygen concentrations in the wafers.

Micromachined silicon electrostatic chuck

DOEpatents

Anderson, R.A.; Seager, C.H.

1996-12-10

An electrostatic chuck is faced with a patterned silicon plate, created by micromachining a silicon wafer, which is attached to a metallic base plate. Direct electrical contact between the chuck face (patterned silicon plate`s surface) and the silicon wafer it is intended to hold is prevented by a pattern of flat-topped silicon dioxide islands that protrude less than 5 micrometers from the otherwise flat surface of the chuck face. The islands may be formed in any shape. Islands may be about 10 micrometers in diameter or width and spaced about 100 micrometers apart. One or more concentric rings formed around the periphery of the area between the chuck face and wafer contain a low-pressure helium thermal-contact gas used to assist heat removal during plasma etching of a silicon wafer held by the chuck. The islands are tall enough and close enough together to prevent silicon-to-silicon electrical contact in the space between the islands, and the islands occupy only a small fraction of the total area of the chuck face, typically 0.5 to 5 percent. The pattern of the islands, together with at least one hole bored through the silicon veneer into the base plate, will provide sufficient gas-flow space to allow the distribution of the helium thermal-contact gas. 6 figs.

The Development of High-Density Vertical Silicon Nanowires and Their Application in a Heterojunction Diode.

PubMed

Chang, Wen-Chung; Su, Sheng-Chien; Wu, Chia-Ching

2016-06-30

Vertically aligned p-type silicon nanowire (SiNW) arrays were fabricated through metal-assisted chemical etching (MACE) of Si wafers. An indium tin oxide/indium zinc oxide/silicon nanowire (ITO/IZO/SiNW) heterojunction diode was formed by depositing ITO and IZO thin films on the vertically aligned SiNW arrays. The structural and electrical properties of the resulting ITO/IZO/SiNW heterojunction diode were characterized by field emission scanning electron microscopy (FE-SEM), X-ray diffraction (XRD), and current-voltage (I-V) measurements. Nonlinear and rectifying I-V properties confirmed that a heterojunction diode was successfully formed in the ITO/IZO/SiNW structure. The diode had a well-defined rectifying behavior, with a rectification ratio of 550.7 at 3 V and a turn-on voltage of 2.53 V under dark conditions.

Structural, Optical and Electrical Properties of ZnS/Porous Silicon Heterostructures

NASA Astrophysics Data System (ADS)

Wang, Cai-Feng; Li, Qing-Shan; Lv, Lei; Zhang, Li-Chun; Qi, Hong-Xia; Chen, Hou

2007-03-01

ZnS films are deposited by pulsed laser deposition on porous silicon (PS) substrates formed by electrochemical anodization of p-type (100) silicon wafer. Scanning electron microscope images reveal that the surface of ZnS films is unsmoothed, and there are some cracks in the ZnS films due to the roughness of the PS surface. The x-ray diffraction patterns show that the ZnS films on PS surface are grown in preferring orientation along cubic phase β-ZnS (111) direction. White light emission is obtained by combining the blue-green emission from ZnS films with the orange-red emission from PS layers. Based on the I-V characteristic, the ZnS/PS heterojunction exhibits the rectifying junction behaviour, and an ideality factor n is calculated to be 77 from the I-V plot.

Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).

PubMed

Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

2011-04-21

A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (μTAS), analytical and bio-analytical applications, and MEMS packaging.

Fabrication of Silicon Backshorts with Improved Out-of-Band Rejection for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Fabrication of ultrathin and highly uniform silicon on insulator by numerically controlled plasma chemical vaporization machining.

PubMed

Sano, Yasuhisa; Yamamura, Kazuya; Mimura, Hidekazu; Yamauchi, Kazuto; Mori, Yuzo

2007-08-01

Metal-oxide semiconductor field-effect transistors fabricated on a silicon-on-insulator (SOI) wafer operate faster and at a lower power than those fabricated on a bulk silicon wafer. Scaling down, which improves their performances, demands thinner SOI wafers. In this article, improvement on the thinning of SOI wafers by numerically controlled plasma chemical vaporization machining (PCVM) is described. PCVM is a gas-phase chemical etching method in which reactive species generated in atmospheric-pressure plasma are used. Some factors affecting uniformity are investigated and methods for improvements are presented. As a result of thinning a commercial 8 in. SOI wafer, the initial SOI layer thickness of 97.5+/-4.7 nm was successfully thinned and made uniform at 7.5+/-1.5 nm.

Fabrication Methods for Adaptive Deformable Mirrors

NASA Technical Reports Server (NTRS)

Toda, Risaku; White, Victor E.; Manohara, Harish; Patterson, Keith D.; Yamamoto, Namiko; Gdoutos, Eleftherios; Steeves, John B.; Daraio, Chiara; Pellegrino, Sergio

2013-01-01

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate.

High-efficiency silicon heterojunction solar cells: Status and perspectives

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Wolf, S.

Silicon heterojunction technology (HJT) uses silicon thin-film deposition techniques to fabricate photovoltaic devices from mono-crystalline silicon wafers (c-Si). This enables energy-conversion efficiencies above 21 %, also at industrial-production level. In this presentation we review the present status of this technology and point out recent trends. We first discuss how the properties of thin hydrogenated amorphous silicon (a-Si:H) films can be exploited to fabricate passivating contacts, which is the key to high- efficiency HJT solar cells. Such contacts enable very high operating voltages, approaching the theoretical limits, and yield small temperature coefficients. With this approach, an increasing number of groups aremore » reporting devices with conversion efficiencies well over 20 % on n-type wafers, Panasonic leading the field with 24.7 %. Exciting results have also been obtained on p-type wafers. Despite these high voltages, important efficiency gains can still be made in fill factor and optical design. This requires improved understanding of carrier transport across device interfaces and reduced parasitic absorption in HJT solar cells. For the latter, several strategies can be followed: Short- wavelength losses can be reduced by replacing the front a-Si:H films with wider-bandgap window layers, such as silicon alloys or even metal oxides. Long-wavelength losses are mitigated by introducing new high-mobility TCO’s such as hydrogenated indium oxide, and also by designing new rear reflectors. Optical shadow losses caused by the front metalisation grid are significantly reduced by replacing printed silver electrodes with fine-line plated copper contacts, leading also to possible cost advantages. The ultimate approach to minimize optical losses is the implementation of back-contacted architectures, which are completely devoid of grid shadow losses and parasitic absorption in the front layers can be minimized irrespective of electrical transport requirements. The validity of this approach was convincingly demonstrated by Panasonic, Japan in 2014, reporting on an interdigitated back-contacted HJT cell with an efficiency of 25.6%, setting the new single-junction c-Si record. Finally, given the virtually perfect surface passivation and excellent red response of HJT solar cells, we anticipate these devices will also become the preferred bottom cell in ultra-high efficiency c-Si-based tandem devices, exploiting better the solar spectrum. Such tandem cells have the potential to overcome the fundamental single-junction limit of silicon solar cells (29.4%). Combining HJT cells with perovskite solar cells as top cell appears to be particularly appealing.« less

Zirconium oxide surface passivation of crystalline silicon

NASA Astrophysics Data System (ADS)

Wan, Yimao; Bullock, James; Hettick, Mark; Xu, Zhaoran; Yan, Di; Peng, Jun; Javey, Ali; Cuevas, Andres

2018-05-01

This letter reports effective passivation of crystalline silicon (c-Si) surfaces by thermal atomic layer deposited zirconium oxide (ZrOx). The optimum layer thickness and activation annealing conditions are determined to be 20 nm and 300 °C for 20 min. Cross-sectional transmission electron microscopy imaging shows an approximately 1.6 nm thick SiOx interfacial layer underneath an 18 nm ZrOx layer, consistent with ellipsometry measurements (˜20 nm). Capacitance-voltage measurements show that the annealed ZrOx film features a low interface defect density of 1.0 × 1011 cm-2 eV-1 and a low negative film charge density of -6 × 1010 cm-2. Effective lifetimes of 673 μs and 1.1 ms are achieved on p-type and n-type 1 Ω cm undiffused c-Si wafers, respectively, corresponding to an implied open circuit voltage above 720 mV in both cases. The results demonstrate that surface passivation quality provided by ALD ZrOx is consistent with the requirements of high efficiency silicon solar cells.

Single-order, subwavelength resonant nanograting as a uniformly hot substrate for surface-enhanced Raman spectroscopy.

PubMed

Deng, Xuegong; Braun, Gary B; Liu, Sheng; Sciortino, Paul F; Koefer, Bob; Tombler, Thomas; Moskovits, Martin

2010-05-12

The surface-enhanced Raman spectroscopy (SERS) activity and the optical reflectance of a subwavelength gold nanograting fabricated entirely using top down technologies on silicon wafers are presented. The grating consists of 120 nm gold cladding on top of parallel silica nanowires constituting the grating's lines, with gaps between nanowires <10 nm wide at their narrowest point. The grating produces inordinately intense SERS and shows very strong polarization dependence. Reflectance measurements for the optimized grating indicate that (when p-polarization is used and at least one of the incident electric field components lies across the grating lines) the reflectance drops to <1% at resonance, indicating that essentially all of the radiant energy falling on the surface is coupled into the grating. The SERS intensity and the reflectance at resonance anticorrelate predicatively, suggesting that reflectance measurements can provide a nondestructive, wafer-level test of SERS efficacy. The SERS performance of the gratings is very uniform and reproducible. Extensive measurements on samples cut from both the same wafer and from different wafers, produce a SERS intensity distribution function that is similar to that obtained for ordinary Raman measurements carried out at multiple locations on a polished (100) silicon wafer.

Silicon micro-mold and method for fabrication

DOEpatents

Morales, Alfredo M.

2005-01-11

The present invention describes a method for rapidly fabricating a robust 3-dimensional silicon micro-mold for use in preparing complex metal micro-components. The process begins by depositing a conductive metal layer onto one surface of a silicon wafer. A thin photoresist and a standard lithographic mask are then used to transfer a trace image pattern onto the opposite surface of the wafer by exposing and developing the resist. The exposed portion of the silicon substrate is anisotropically etched through the wafer thickness down to conductive metal layer to provide an etched pattern consisting of a series of rectilinear channels and recesses in the silicon which serve as the silicon micro-mold. Microcomponents are prepared with this mold by first filling the mold channels and recesses with a metal deposit, typically by electroplating, and then removing the silicon micro-mold by chemical etching.

Silicon micro-mold

DOEpatents

Morales, Alfredo M [Livermore, CA

2006-10-24

The present invention describes a method for rapidly fabricating a robust 3-dimensional silicon-mold for use in preparing complex metal micro-components. The process begins by depositing a conductive metal layer onto one surface of a silicon wafer. A thin photoresist and a standard lithographic mask are then used to transfer a trace image pattern onto the opposite surface of the wafer by exposing and developing the resist. The exposed portion of the silicon substrate is anisotropically etched through the wafer thickness down to conductive metal layer to provide an etched pattern consisting of a series of rectilinear channels and recesses in the silicon which serve as the silicon micro-mold. Microcomponents are prepared with this mold by first filling the mold channels and recesses with a metal deposit, typically by electroplating, and then removing the silicon micro-mold by chemical etching.

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

NASA Astrophysics Data System (ADS)

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Two-Dimensional Metal-Free Organic Multiferroic Material for Design of Multifunctional Integrated Circuits.

PubMed

Tu, Zhengyuan; Wu, Menghao; Zeng, Xiao Cheng

2017-05-04

Coexistence of ferromagnetism and ferroelectricity in a single 2D material is highly desirable for integration of multifunctional units in 2D material-based circuits. We report theoretical evidence of C 6 N 8 H organic network as being the first 2D organic multiferroic material with coexisting ferromagnetic and ferroelectric properties. The ferroelectricity stems from multimode proton-transfer within the 2D C 6 N 8 H network, in which a long-range proton-transfer mode is enabled by the facilitation of oxygen molecule when the network is exposed to the air. Such oxygen-assisted ferroelectricity also leads to a high Curie temperature and coupling between ferroelectricity and ferromagnetism. We also find that hydrogenation and carbon doping can transform the 2D g-C 3 N 4 network from an insulator to an n-type/p-type magnetic semiconductor with modest bandgap. Akin to the dopant induced n/p channels in silicon wafer, a variety of dopant created functional units can be integrated into the g-C 3 N 4 wafer by design for nanoelectronic applications.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1991-01-01

This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

1992-01-01

A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

NASA Astrophysics Data System (ADS)

Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

2018-04-01

Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

Formation of silicon carbide by laser ablation in graphene oxide-N-methyl-2-pyrrolidone suspension on silicon surface

NASA Astrophysics Data System (ADS)

Jaleh, Babak; Ghasemi, Samaneh; Torkamany, Mohammad Javad; Salehzadeh, Sadegh; Maleki, Farahnaz

2018-01-01

Laser ablation of a silicon wafer in graphene oxide-N-methyl-2-pyrrolidone (GO-NMP) suspension was carried out with a pulsed Nd:YAG laser (pulse duration = 250 ns, wavelength = 1064 nm). The surface of silicon wafer before and after laser ablation was studied using optical microscopy, scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX). The results showed that the ablation of silicon surface in liquid by pulsed laser was done by the process of melt expulsion under the influence of the confined plasma-induced pressure or shock wave trapped between the silicon wafer and the liquid. The X-ray diffraction‌ (XRD) pattern of Si wafer after laser ablation showed that 4H-SiC layer is formed on its surface. The formation of the above layer was also confirmed by Raman spectroscopy, and X-ray photoelectron spectroscopy‌ (XPS), as well as EDX was utilized. The reflectance of samples decreased with increasing pulse energy. Therefore, the morphological alteration and the formation of SiC layer at high energy increase absorption intensity in the UV‌-vis regions. Theoretical calculations confirm that the formation of silicon carbide from graphene oxide and silicon wafer is considerably endothermic. Development of new methods for increasing the reflectance without causing harmful effects is still an important issue for crystalline Si solar cells. By using the method described in this paper, the optical properties of solar cells can be improved.

Fabrication Characterization of Solar-Cell Silicon Wafers Using a Circular-Rhombus Tool

NASA Astrophysics Data System (ADS)

Pa, Pai-Shan

2010-01-01

A new recycling fabrication method using a custom-built designed circular-rhombus tool for a process combining of micro-electroetching and electrochemical machining for removal of the surface layers from silicon wafers of solar cells is demonstrated. The low yields of epoxy film and Si3N4 thin-film depositions are important factors in semiconductor production. The aim of the proposed recycling fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach for removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. A large diameter cathode of the circular-rhombus tool (with a small gap between the anode and the cathode) corresponds to a high rate of epoxy film removal. A high feed rate of the silicon wafers combined with a high continuous DC electric voltage results in a high removal rate. The high rotational speed of the circular-rhombus tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. A small port radius or large end angle of the rhombus anode provides a large discharge space and good removal effect only a short period of time is required to remove the Si3N4 layer and epoxy film easily and cleanly.

Delta-Doping at Wafer Level for High Throughput, High Yield Fabrication of Silicon Imaging Arrays

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Nikzad, Shoulch (Inventor); Jones, Todd J. (Inventor); Greer, Frank (Inventor); Carver, Alexander G. (Inventor)

2014-01-01

Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3 + NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.

Reducing the Cost of Solar Cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scanlon, B.

2012-04-01

Solar-powered electricity prices could soon approach those of power from coal or natural gas thanks to collaborative research with solar startup Ampulse Corporation at the National Renewable Energy Laboratory. Silicon wafers account for almost half the cost of today's solar photovoltaic panels, so reducing or eliminating wafer costs is essential to bringing prices down. Current crystalline silicon technology converts energy in a highly efficient manner; however, that technology is manufactured with processes that could stand some improvement. The industry needs a method that is less complex, creates less waste and uses less energy. First, half the refined silicon is lostmore » as dust in the wafer-sawing process, driving module costs higher. Wafers are sawn off of large cylindrical ingots, or boules, of silicon. A typical 2-meter boule loses as many as 6,000 potential wafers during sawing. Second, the wafers produced are much thicker than necessary. To efficiently convert sunlight into electricity, the wafers need be only one-tenth the typical thickness. NREL, the Oak Ridge National Laboratory and Ampulse have partnered on an approach to eliminate this waste and dramatically lower the cost of the finished solar panels. By using a chemical vapor deposition process to grow the silicon on inexpensive foil, Ampulse is able to make the solar cells just thick enough to convert most of the solar energy into electricity. No more sawdust - and no more wasting refined silicon materials. NREL developed the technology to grow high-quality silicon and ORNL developed the metal foil that has the correct crystal structure to support that growth. Ampulse is installing a pilot manufacturing line in NREL's Process Development Integration Laboratory, where solar companies can work closely with lab scientists on integrated equipment to answer pressing questions related to their technology development, as well as rapidly overcoming R and D challenges and risk. NREL's program is focused on transformative innovation in the domestic PV industry. With knowledge and expertise acquired from the PDIL pilot production line tools, Ampulse plans to design a full-scale production line to accommodate long rolls of metal foil. The Ampulse process 'goes straight from pure silicon-containing gas to high-quality crystal silicon film,' said Brent Nelson, the operational manager for the Process Development Integration Laboratory. 'The advantage is you can make the wafer just as thin as you need it - 10 microns or less.' Most of today's solar cells are made out of wafer crystalline silicon, though thin-film cells made of more exotic elements such as copper, indium, gallium, arsenic, cadmium, tellurium and others are making a strong push into the market. The advantage of silicon is its abundance, because it is derived from sand. Silicon's disadvantage is that purifying it into wafers suitable for solar cells can be expensive and energy intensive. Manufacturers add carbon and heat to sand to produce metallurgical-grade silicon, which is useful in other industries, but not yet suitable for making solar cells. So this metallurgical-grade silicon is then converted to pure trichlorosilane (SiCl3) or silane (SiH4) gas. Typically, the purified gas is then converted to create a silicon feedstock at 1,000 degrees Celsius. This feedstock is melted at 1,414 C and recrystallized into crystal ingots that are finally sawed into wafers. The Ampulse method differs in that it eliminates the last two steps in the traditional process and works directly with the silane gas growing only the needed silicon right onto a foil substrate. A team of NREL scientists had developed a way to use a process called hot-wire chemical vapor deposition to thicken silicon wafers with near perfect crystal structure. Using a hot tungsten filament much like the one found in an incandescent light bulb, the silane gas molecules are broken apart and deposited onto the wafer using the chemical vapor deposition technique at about 700 C - a much lower temperature than needed to make the wafer. The hot filament decomposes the gas, allowing silicon layers to deposit directly onto the substrate. Armed with this new technique, Branz and Teplin searched for ways to grow the silicon on cheaper materials and still use it for solar cells. They found the ideal synergy when visiting venture capitalists from Battelle Ventures asked them whether they could do anything useful with a breakthrough from Oak Ridge's superconducting wire development group. The new development, called the rolling assisted biaxially textured substrate (RABiTS), was just the opportunity the two scientists had been seeking. If metal foil is to work as a substrate, it must be able to act as a seed crystal so the silicon can grow on it with the correct structure. The RABiTS process forms crystals in the foil that are correctly oriented to receive the silicon atoms and lock them into just the right positions.« less

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto

2006-12-10

To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 {mu}m wide (111) sidewalls was fabricated using a 220 {mu}m thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers.

PubMed

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang, Zhen; Takano, Takayuki; Maeda, Ryutaro

2006-12-10

To develop x-ray mirrors for micropore optics, smooth silicon (111) sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 microm wide (111) sidewalls was fabricated using a 220 microm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time, x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

Development of Mid-infrared GeSn Light Emitting Diodes on a Silicon Substrate

DTIC Science & Technology

2015-04-22

Materials, Heterostrucuture Semiconductor, Light Emitting Devices, Molecular Beam Epitaxy 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF ABSTRACT...LED) structure. Optimization of traditional and hetero- P-i-N structures designed and grown on Ge-buffer Si (001) wafers using molecular beam epitaxy ...designed structures were grown on Ge-buffer Si (001) wafers using molecular beam epitaxy (MBE) with the low-temperature growth technique. (The Ge-buffer

Fabrication of Total-Dose-Radiation-Hardened (TDRH) SOI wafer with embedded silicon nanoclusters

NASA Astrophysics Data System (ADS)

Wu, Aimin; Wang, Xi; Wei, Xing; Chen, Jing; Chen, Ming; Zhang, Zhengxuan

2009-05-01

Si ion-implantation and post annealing of silicon wafers prior to wafer bonding were used to radiation-harden the thermal oxide layer of Silicon on Insulator structures. After grinding and polishing, Total-Dose-Radiation-Hardened SOI (TDRH-SOI) wafers with several-micron-thick device layers were prepared. Electrical characterization before and after X-ray irradiation showed that the flatband voltage shift induced by irradiation was reduced by this preprocessing. Photoluminescence Spectroscopy (PL), Transmission Electron Microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) results indicated that the improvement of the total dose response of the TDRH-SOI wafer was associated with formation of Si nanoclusters in the implanted oxide layer, suggesting that these were the likely candidates for electron and proton trapping centers that reduce the positive charge buildup effect in the buried oxide.

Method for implementation of back-illuminated CMOS or CCD imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor)

2008-01-01

A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

Fabricating a Microcomputer on a Single Silicon Wafer

NASA Technical Reports Server (NTRS)

Evanchuk, V. L.

1983-01-01

Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

Iridium-coated micropore x-ray optics using dry etching of a silicon wafer and atomic layer deposition.

PubMed

Ogawa, Tomohiro; Ezoe, Yuichiro; Moriyama, Teppei; Mitsuishi, Ikuyuki; Kakiuchi, Takuya; Ohashi, Takaya; Mitsuda, Kazuhisa; Putkonen, Matti

2013-08-20

To enhance x-ray reflectivity of silicon micropore optics using dry etching of silicon (111) wafers, iridium coating is tested by use of atomic layer deposition. An iridium layer is successfully formed on sidewalls of tiny micropores with a pore width of 20 μm and depth of 300 μm. The film thickness is ∼20  nm. An enhanced x-ray reflectivity compared to that of silicon is confirmed at Ti K_α 4.51 keV, for what we believe to be the first time, with this type of optics. Some discrepancies from a theoretical reflectivity curve of iridium-coated silicon are noticed at small incident angles <1.3°. When a geometrical shadowing effect due to occultation by a ridge existing on the sidewalls is taken into account, the observed reflectivity becomes well represented by the modified theoretical curve. An estimated surface micro roughness of ∼1  nm rms is consistent with atomic force microscope measurements of the sidewalls.

Surface plasmons based terahertz modulator consisting of silicon-air-metal-dielectric-metal layers

NASA Astrophysics Data System (ADS)

Wang, Wei; Yang, Dongxiao; Qian, Zhenhai

2018-05-01

An optically controlled modulator of the terahertz wave, which is composed of a metal-dielectric-metal structure etched with circular loop arrays on both the metal layers and a photoexcited silicon wafer separated by an air layer, is proposed. Simulation results based on experimentally measured complex permittivities predict that modification of complex permittivity of the silicon wafer through excitation laser leads to a significant tuning of transmission characteristics of the modulator, forming the modulation depths of 59.62% and 96.64% based on localized surface plasmon peak and propagating surface plasmon peak, respectively. The influences of the complex permittivity of the silicon wafer and the thicknesses of both the air layer and the silicon wafer are numerically studied for better understanding the modulation mechanism. This study proposes a feasible methodology to design an optically controlled terahertz modulator with large modulation depth, high speed and suitable insertion loss, which is useful for terahertz applications in the future.

Control of grown-in defects and oxygen precipitates in silicon wafers with DZ-IG structure by ultrahigh-temperature rapid thermal oxidation

NASA Astrophysics Data System (ADS)

Maeda, Susumu; Sudo, Haruo; Okamura, Hideyuki; Nakamura, Kozo; Sueoka, Koji; Izunome, Koji

2018-04-01

A new control technique for achieving compatibility between crystal quality and gettering ability for heavy metal impurities was demonstrated for a nitrogen-doped Czochralski silicon wafer with a diameter of 300 mm via ultra-high temperature rapid thermal oxidation (UHT-RTO) processing. We have found that the DZ-IG structure with surface denuded zone and the wafer bulk with dense oxygen precipitates were formed by the control of vacancies in UHT-RTO process at temperature exceeding 1300 °C. It was also confirmed that most of the void defects were annihilated from the sub-surface of the wafer due to the interstitial Si atoms that were generated at the SiO2/Si interface. These results indicated that vacancies corresponded to dominant species, despite numerous interstitial silicon injections. We have explained these prominent features by the degree of super-saturation for the interstitial silicon due to oxidation and the precise thermal properties of the vacancy and interstitial silicon.

Micromachined silicon electrostatic chuck

DOEpatents

Anderson, Robert A.; Seager, Carleton H.

1996-01-01

An electrostatic chuck is faced with a patterned silicon plate 11, created y micromachining a silicon wafer, which is attached to a metallic base plate 13. Direct electrical contact between the chuck face 15 (patterned silicon plate's surface) and the silicon wafer 17 it is intended to hold is prevented by a pattern of flat-topped silicon dioxide islands 19 that protrude less than 5 micrometers from the otherwise flat surface of the chuck face 15. The islands 19 may be formed in any shape. Islands may be about 10 micrometers in diameter or width and spaced about 100 micrometers apart. One or more concentric rings formed around the periphery of the area between the chuck face 15 and wafer 17 contain a low-pressure helium thermal-contact gas used to assist heat removal during plasma etching of a silicon wafer held by the chuck. The islands 19 are tall enough and close enough together to prevent silicon-to-silicon electrical contact in the space between the islands, and the islands occupy only a small fraction of the total area of the chuck face 15, typically 0.5 to 5 percent. The pattern of the islands 19, together with at least one hole 12 bored through the silicon veneer into the base plate, will provide sufficient gas-flow space to allow the distribution of the helium thermal-contact gas.

Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Zaunbracher, K.

2011-07-01

Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finishedmore » cell performance.« less

Comparison of Photoluminescence Imaging on Starting Multi-Crystalline Silicon Wafers to Finished Cell Performance: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Dorn, D.

2012-06-01

Photoluminescence (PL) imaging techniques can be applied to multicrystalline silicon wafers throughout the manufacturing process. Both band-to-band PL and defect-band emissions, which are longer-wavelength emissions from sub-bandgap transitions, are used to characterize wafer quality and defect content on starting multicrystalline silicon wafers and neighboring wafers processed at each step through completion of finished cells. Both PL imaging techniques spatially highlight defect regions that represent dislocations and defect clusters. The relative intensities of these imaged defect regions change with processing. Band-to-band PL on wafers in the later steps of processing shows good correlation to cell quality and performance. The defect bandmore » images show regions that change relative intensity through processing, and better correlation to cell efficiency and reverse-bias breakdown is more evident at the starting wafer stage as opposed to later process steps. We show that thermal processing in the 200 degrees - 400 degrees C range causes impurities to diffuse to different defect regions, changing their relative defect band emissions.« less

Ultra-Shallow Depth Profiling of Arsenic Implants in Silicon by Hydride Generation-Inductively Coupled Plasma Atomic Emission Spectrometry

NASA Astrophysics Data System (ADS)

Matsubara, Atsuko; Kojima, Hisao; Itoga, Toshihiko; Kanehori, Keiichi

1995-08-01

High resolution depth profiling of arsenic (As) implanted into silicon wafers by a chemical technique is described. Silicon wafers are precisely etched through repeated oxidation by hydrogen peroxide solution and dissolution of the oxide by hydrofluoric acid solution. The etched silicon thickness is determined by inductively-coupled plasma atomic emission spectrometry (ICP-AES). Arsenic concentration is determined by hydride generation ICP-AES (HG-ICP-AES) with prereduction using potassium iodide. The detection limit of As in a 4-inch silicon wafer is 2.4×1018 atoms/cm3. The etched silicon thickness is controlled to less than 4±2 atomic layers. Depth profiling of an ultra-shallow As diffusion layer with the proposed method shows good agreement with profiling using the four-probe method or secondary ion mass spectrometry.

Accurate determination of electronic transport properties of silicon wafers by nonlinear photocarrier radiometry with multiple pump beam sizes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Qian; University of the Chinese Academy of Sciences, Beijing 100039; Li, Bincheng, E-mail: bcli@uestc.ac.cn

2015-12-07

In this paper, photocarrier radiometry (PCR) technique with multiple pump beam sizes is employed to determine simultaneously the electronic transport parameters (the carrier lifetime, the carrier diffusion coefficient, and the front surface recombination velocity) of silicon wafers. By employing the multiple pump beam sizes, the influence of instrumental frequency response on the multi-parameter estimation is totally eliminated. A nonlinear PCR model is developed to interpret the PCR signal. Theoretical simulations are performed to investigate the uncertainties of the estimated parameter values by investigating the dependence of a mean square variance on the corresponding transport parameters and compared to that obtainedmore » by the conventional frequency-scan method, in which only the frequency dependences of the PCR amplitude and phase are recorded at single pump beam size. Simulation results show that the proposed multiple-pump-beam-size method can improve significantly the accuracy of the determination of the electronic transport parameters. Comparative experiments with a p-type silicon wafer with resistivity 0.1–0.2 Ω·cm are performed, and the electronic transport properties are determined simultaneously. The estimated uncertainties of the carrier lifetime, diffusion coefficient, and front surface recombination velocity are approximately ±10.7%, ±8.6%, and ±35.4% by the proposed multiple-pump-beam-size method, which is much improved than ±15.9%, ±29.1%, and >±50% by the conventional frequency-scan method. The transport parameters determined by the proposed multiple-pump-beam-size PCR method are in good agreement with that obtained by a steady-state PCR imaging technique.« less

Passivation of c-Si surfaces by sub-nm amorphous silicon capped with silicon nitride

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wan, Yimao, E-mail: yimao.wan@anu.edu.au; Yan, Di; Bullock, James

2015-12-07

A sub-nm hydrogenated amorphous silicon (a-Si:H) film capped with silicon nitride (SiN{sub x}) is shown to provide a high level passivation to crystalline silicon (c-Si) surfaces. When passivated by a 0.8 nm a-Si:H/75 nm SiN{sub x} stack, recombination current density J{sub 0} values of 9, 11, 47, and 87 fA/cm{sup 2} are obtained on 10 Ω·cm n-type, 0.8 Ω·cm p-type, 160 Ω/sq phosphorus-diffused, and 120 Ω/sq boron-diffused silicon surfaces, respectively. The J{sub 0} on n-type 10 Ω·cm wafers is further reduced to 2.5 ± 0.5 fA/cm{sup 2} when the a-Si:H film thickness exceeds 2.5 nm. The passivation by the sub-nm a-Si:H/SiN{sub x} stack is thermally stable at 400 °C in N{sub 2} formore » 60 min on all four c-Si surfaces. Capacitance–voltage measurements reveal a reduction in interface defect density and film charge density with an increase in a-Si:H thickness. The nearly transparent sub-nm a-Si:H/SiN{sub x} stack is thus demonstrated to be a promising surface passivation and antireflection coating suitable for all types of surfaces encountered in high efficiency c-Si solar cells.« less

Low temperature spalling of silicon: A crack propagation study

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bertoni, Mariana; Uberg Naerland, Tine; Stoddard, Nathan

2017-06-08

Spalling is a promising kerfless method for cutting thin silicon wafers while doubling the yield of a silicon ingot. The main obstacle in this technology is the high total thickness variation of the spalled wafers, often as high as 100% of the wafer thickness. It has been suggested before that a strong correlation exists between low crack velocities and a smooth surface, but this correlation has never been shown during a spalling process in silicon. The reason lies in the challenge associated to measuring such velocities. In this contribution, we present a new approach to assess, in real time, themore » crack velocity as it propagates during a low temperature spalling process. Understanding the relationship between crack velocity and surface roughness during spalling can pave the way to attain full control on the surface quality of the spalled wafer.« less

The Development of High-Density Vertical Silicon Nanowires and Their Application in a Heterojunction Diode

PubMed Central

Chang, Wen-Chung; Su, Sheng-Chien; Wu, Chia-Ching

2016-01-01

Vertically aligned p-type silicon nanowire (SiNW) arrays were fabricated through metal-assisted chemical etching (MACE) of Si wafers. An indium tin oxide/indium zinc oxide/silicon nanowire (ITO/IZO/SiNW) heterojunction diode was formed by depositing ITO and IZO thin films on the vertically aligned SiNW arrays. The structural and electrical properties of the resulting ITO/IZO/SiNW heterojunction diode were characterized by field emission scanning electron microscopy (FE-SEM), X-ray diffraction (XRD), and current−voltage (I−V) measurements. Nonlinear and rectifying I−V properties confirmed that a heterojunction diode was successfully formed in the ITO/IZO/SiNW structure. The diode had a well-defined rectifying behavior, with a rectification ratio of 550.7 at 3 V and a turn-on voltage of 2.53 V under dark conditions. PMID:28773656

Plasma deposition of amorphous silicon carbide thin films irradiated with neutrons

NASA Astrophysics Data System (ADS)

Huran, J.; Bohacek, P.; Kucera, M.; Kleinova, A.; Sasinkova, V.; IEE SAS, Bratislava, Slovakia Team; Polymer Institute, SAS, Bratislava, Slovakia Team; Institute of Chemistry, SAS, Bratislava, Slovakia Team

2015-09-01

Amorphous silicon carbide and N-doped silicon carbide thin films were deposited on P-type Si(100) wafer by plasma enhanced chemical vapor deposition (PECVD) technology using silane, methane, ammonium and argon gases. The concentration of elements in the films was determined by RBS and ERDA method. Chemical compositions were analyzed by FTIR spectroscopy. Photoluminescence properties were studied by photoluminescence spectroscopy (PL). Irradiation of samples with various neutron fluencies was performed at room temperature. The films contain silicon, carbon, hydrogen, nitrogen and small amount of oxygen. From the IR spectra, the films contained Si-C, Si-H, C-H, Si-N, N-H and Si-O bonds. No significance effect on the IR spectra after neutron irradiation was observed. PL spectroscopy results of films showed decreasing PL intensity after neutron irradiation and PL intensity decreased with increased neutron fluencies. The measured current of the prepared structures increased after irradiation with neutrons and rise up with neutron fluencies.

Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

NASA Astrophysics Data System (ADS)

Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

2017-08-01

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

Prediction and Measurement of Temperature Fields in Silicon-on-Insulator Electronic Circuits

DTIC Science & Technology

1995-08-01

common dimensions are given in Table 1. Almost all of the device power is dissipated in the channel. The electri- cally insulating implanted layer...data. Region or Component substrate Material SOI implanted insulating layers single-crystal silicon, 3 x 1015 boron atoms cm -3 Thermal... implanted silicon-dioxide layer in SOI wafers. The data for each device for varying powers fall near a line originating at P = 0 and T0 = 303 K

Aerosol-Assisted Extraction of Silicon Nanoparticles from Wafer Slicing Waste for Lithium Ion Batteries

NASA Astrophysics Data System (ADS)

Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

2015-03-01

A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

Aerosol-Assisted Extraction of Silicon Nanoparticles from Wafer Slicing Waste for Lithium Ion Batteries

PubMed Central

Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

2015-01-01

A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing. PMID:25819285

An all-silicon single-wafer micro-g accelerometer with a combined surface and bulk micromachining process

NASA Technical Reports Server (NTRS)

Yazdi, N.; Najafi, K.

2000-01-01

This paper reports an all-silicon fully symmetrical z-axis micro-g accelerometer that is fabricated on a single-silicon wafer using a combined surface and bulk fabrication process. The microaccelerometer has high device sensitivity, low noise, and low/controllable damping that are the key factors for attaining micro g and sub-micro g resolution in capacitive accelerometers. The microfabrication process produces a large proof mass by using the whole wafer thickness and a large sense capacitance by utilizing a thin sacrificial layer. The sense/feedback electrodes are formed by a deposited 2-3 microns polysilicon film with embedded 25-35 microns-thick vertical stiffeners. These electrodes, while thin, are made very stiff by the thick embedded stiffeners so that force rebalancing of the proof mass becomes possible. The polysilicon electrodes are patterned to create damping holes. The microaccelerometers are batch-fabricated, packaged, and tested successfully. A device with a 2-mm x 1-mm proof mass and a full bridge support has a measured sensitivity of 2 pF/g. The measured sensitivity of a 4-mm x 1-mm accelerometer with a cantilever support is 19.4 pF/g. The calculated noise floor of these devices at atmosphere are 0.23 micro g/sqrt(Hz) and 0.16 micro g/sqrt(Hz), respectively.

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

PubMed

Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

2008-07-30

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

Effect of substrates on Zinc Oxide thin films fabrication using sol-gel method

NASA Astrophysics Data System (ADS)

Kadir, Rosmalini Ab; Taib, Nurmalina Mohd; Ahmad, Wan Rosmaria Wan; Aziz, Anees Abdul; Sabirin Zoolfakar, Ahmad

2018-03-01

The properties of ZnO thin films were deposited on three different substrates via dip coating method was investigated. The films were prepared on glass, ITO and p-type silicon. Characterization of the film revealed that the properties of the dip coated ZnO thin films were influenced by the type of substrates. The grains on ITO and glass were ∼10 nm in size while the grains on wafer agglomerate together to form a denser film. Studies of the optical properties using UV-VIS-NIR of the fabricated films demonstrated that glass has the highest transmittance compared to ITO.

Fabrication of an Absorber-Coupled MKID Detector

NASA Technical Reports Server (NTRS)

Brown, Ari; Hsieh, Wen-Ting; Moseley, Samuel; Stevenson, Thomas; U-Yen, Kongpop; Wollack, Edward

2012-01-01

Absorber-coupled microwave kinetic inductance detector (MKID) arrays were developed for submillimeter and far-infrared astronomy. These sensors comprise arrays of lambda/2 stepped microwave impedance resonators patterned on a 1.5-mm-thick silicon membrane, which is optimized for optical coupling. The detector elements are supported on a 380-mm-thick micro-machined silicon wafer. The resonators consist of parallel plate aluminum transmission lines coupled to low-impedance Nb microstrip traces of variable length, which set the resonant frequency of each resonator. This allows for multiplexed microwave readout and, consequently, good spatial discrimination between pixels in the array. The transmission lines simultaneously act to absorb optical power and employ an appropriate surface impedance and effective filling fraction. The fabrication techniques demonstrate high-fabrication yield of MKID arrays on large, single-crystal membranes and sub-micron front-to-back alignment of the micro strip circuit. An MKID is a detector that operates upon the principle that a superconducting material s kinetic inductance and surface resistance will change in response to being exposed to radiation with a power density sufficient to break its Cooper pairs. When integrated as part of a resonant circuit, the change in surface impedance will result in a shift in its resonance frequency and a decrease of its quality factor. In this approach, incident power creates quasiparticles inside a superconducting resonator, which is configured to match the impedance of free space in order to absorb the radiation being detected. For this reason MKIDs are attractive for use in large-format focal plane arrays, because they are easily multiplexed in the frequency domain and their fabrication is straightforward. The fabrication process can be summarized in seven steps: (1) Alignment marks are lithographically patterned and etched all the way through a silicon on insulator (SOI) wafer, which consists of a thin silicon membrane bonded to a thick silicon handle wafer. (2) The metal microwave circuitry on the front of the membrane is patterned and etched. (3) The wafer is then temporarily bonded with wafer wax to a Pyrex wafer, with the SOI side abutting the Pyrex. (4) The silicon handle component of the SOI wafer is subsequently etched away so as to expose the membrane backside. (5) The wafer is flipped over, and metal microwave circuitry is patterned and etched on the membrane backside. Furthermore, cuts in the membrane are made so as to define the individual detector array chips. (6) Silicon frames are micromachined and glued to the silicon membrane. (7) The membranes, which are now attached to the frames, are released from the Pyrex wafer via dissolution of the wafer wax in acetone.

Support apparatus for semiconductor wafer processing

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

2003-06-10

A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

Silica-sol-based spin-coating barrier layer against phosphorous diffusion for crystalline silicon solar cells

PubMed Central

2014-01-01

The phosphorus barrier layers at the doping procedure of silicon wafers were fabricated using a spin-coating method with a mixture of silica-sol and tetramethylammonium hydroxide, which can be formed at the rear surface prior to the front phosphorus spin-on-demand (SOD) diffusion and directly annealed simultaneously with the front phosphorus layer. The optimization of coating thickness was obtained by changing the applied spin-coating speed; from 2,000 to 8,000 rpm. The CZ-Si p-type silicon solar cells were fabricated with/without using the rear silica-sol layer after taking the sheet resistance measurements, SIMS analysis, and SEM measurements of the silica-sol material evaluations into consideration. For the fabrication of solar cells, a spin-coating phosphorus source was used to form the n+ emitter and was then diffused at 930°C for 35 min. The out-gas diffusion of phosphorus could be completely prevented by spin-coated silica-sol film placed on the rear side of the wafers coated prior to the diffusion process. A roughly 2% improvement in the conversion efficiency was observed when silica-sol was utilized during the phosphorus diffusion step. These results can suggest that the silica-sol material can be an attractive candidate for low-cost and easily applicable spin-coating barrier for any masking purpose involving phosphorus diffusion. PMID:25520602

Silica-sol-based spin-coating barrier layer against phosphorous diffusion for crystalline silicon solar cells.

PubMed

Uzum, Abdullah; Fukatsu, Ken; Kanda, Hiroyuki; Kimura, Yutaka; Tanimoto, Kenji; Yoshinaga, Seiya; Jiang, Yunjian; Ishikawa, Yasuaki; Uraoka, Yukiharu; Ito, Seigo

2014-01-01

The phosphorus barrier layers at the doping procedure of silicon wafers were fabricated using a spin-coating method with a mixture of silica-sol and tetramethylammonium hydroxide, which can be formed at the rear surface prior to the front phosphorus spin-on-demand (SOD) diffusion and directly annealed simultaneously with the front phosphorus layer. The optimization of coating thickness was obtained by changing the applied spin-coating speed; from 2,000 to 8,000 rpm. The CZ-Si p-type silicon solar cells were fabricated with/without using the rear silica-sol layer after taking the sheet resistance measurements, SIMS analysis, and SEM measurements of the silica-sol material evaluations into consideration. For the fabrication of solar cells, a spin-coating phosphorus source was used to form the n(+) emitter and was then diffused at 930°C for 35 min. The out-gas diffusion of phosphorus could be completely prevented by spin-coated silica-sol film placed on the rear side of the wafers coated prior to the diffusion process. A roughly 2% improvement in the conversion efficiency was observed when silica-sol was utilized during the phosphorus diffusion step. These results can suggest that the silica-sol material can be an attractive candidate for low-cost and easily applicable spin-coating barrier for any masking purpose involving phosphorus diffusion.

Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

NASA Astrophysics Data System (ADS)

Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

2018-03-01

A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

Fabrication of a Silicon Backshort Assembly for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

InP on SOI devices for optical communication and optical network on chip

NASA Astrophysics Data System (ADS)

Fedeli, J.-M.; Ben Bakir, B.; Olivier, N.; Grosse, Ph.; Grenouillet, L.; Augendre, E.; Phillippe, P.; Gilbert, K.; Bordel, D.; Harduin, J.

2011-01-01

For about ten years, we have been developing InP on Si devices under different projects focusing first on μlasers then on semicompact lasers. For aiming the integration on a CMOS circuit and for thermal issue, we relied on SiO2 direct bonding of InP unpatterned materials. After the chemical removal of the InP substrate, the heterostructures lie on top of silicon waveguides of an SOI wafer with a separation of about 100nm. Different lasers or photodetectors have been achieved for off-chip optical communication and for intra-chip optical communication within an optical network. For high performance computing with high speed communication between cores, we developed InP microdisk lasers that are coupled to silicon waveguide and produced 100μW of optical power and that can be directly modulated up to 5G at different wavelengths. The optical network is based on wavelength selective circuits with ring resonators. InGaAs photodetectors are evanescently coupled to the silicon waveguide with an efficiency of 0.8A/W. The fabrication has been demonstrated at 200mm wafer scale in a microelectronics clean room for CMOS compatibility. For off-chip communication, silicon on InP evanescent laser have been realized with an innovative design where the cavity is defined in silicon and the gain localized in the QW of bonded InP hererostructure. The investigated devices operate at continuous wave regime with room temperature threshold current below 100 mA, the side mode suppression ratio is as high as 20dB, and the fibercoupled output power is {7mW. Direct modulation can be achieved with already 6G operation.

Smoother Scribing of Silicon Wafers

NASA Technical Reports Server (NTRS)

Danyluk, S.

1986-01-01

Proposed new tool used to scribe silicon wafers into chips more smoothly than before. New scriber produces surface that appears ductile. Scribed groove cuts have relatively smooth walls. Scriber consists of diamond pyramid point on rigid shaft. Ethanol flows through shaft and around point, like ink in ballpoint pen. Ethanol has significantly different effect for scribing silicon than water, used in conventional diamond scribers.

Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

NASA Astrophysics Data System (ADS)

Wang, Shing-Dar; Chen, Ting-Wei

2018-06-01

In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in <1 0 0> direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution

NASA Astrophysics Data System (ADS)

Voorkamp, R.; Verschuuren, M. A.; van Brakel, R.

2016-10-01

Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 - 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and yield. Soft stamps, usually based on silicone rubber, behave fundamentally different compared to rigid stamps on the macro-, micro- and nanometer level. The main limitation of traditional silicones is that they are too soft to support sub-micron features against surface tension based stamp deformation and collapse [4] and handling a soft stamp to achieve accurate feature placement on wafer scales to allow overlay alignment with sub-100nm overlay accuracy.

Carbon mediated reduction of silicon dioxide and growth of copper silicide particles in uniform width channels

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pizzocchero, Filippo; Bøggild, Peter; Booth, Timothy J.

We show that surface arc-discharge deposited carbon plays a critical intermediary role in the breakdown of thermally grown oxide diffusion barriers of 90 nm on a silicon wafer at 1035 °C in an Ar/H{sub 2} atmosphere, resulting in the formation of epitaxial copper silicide particles in ≈ 10 μm wide channels, which are aligned with the intersections of the (100) surface of the wafer and the (110) planes on an oxidized silicon wafer, as well as endotaxial copper silicide nanoparticles within the wafer bulk. We apply energy dispersive x-ray spectroscopy, in combination with scanning and transmission electron microscopy of focusedmore » ion beam fabricated lammelas and trenches in the structure to elucidate the process of their formation.« less

Method for cleaning a solar cell surface opening made with a solar etch paste

DOEpatents

Rohatgi, Ajeet; Meemongkolkiat, Vichai

2010-06-22

A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.

Method for formation of high quality back contact with screen-printed local back surface field

DOEpatents

Rohatgi, Ajeet; Meemongkolkiat, Vichai

2010-11-30

A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.

Technology of silicon charged-particle detectors developed at the Institute of Electron Technology (ITE)

NASA Astrophysics Data System (ADS)

Wegrzecka, Iwona; Panas, Andrzej; Bar, Jan; Budzyński, Tadeusz; Grabiec, Piotr; Kozłowski, Roman; Sarnecki, Jerzy; Słysz, Wojciech; Szmigiel, Dariusz; Wegrzecki, Maciej; Zaborowski, Michał

2013-07-01

The paper discusses the technology of silicon charged-particle detectors developed at the Institute of Electron Technology (ITE). The developed technology enables the fabrication of both planar and epiplanar p+-ν-n+ detector structures with an active area of up to 50 cm2. The starting material for epiplanar structures are silicon wafers with a high-resistivity n-type epitaxial layer ( ν layer - ρ < 3 kΩcm) deposited on a highly doped n+-type substrate (ρ< 0,02Ωcm) developed and fabricated at the Institute of Electronic Materials Technology. Active layer thickness of the epiplanar detectors (νlayer) may range from 10 μm to 150 μm. Imported silicon with min. 5 kΩcm resistivity is used to fabricate planar detectors. Active layer thickness of the planar detectors (ν) layer) may range from 200 μm to 1 mm. This technology enables the fabrication of both discrete and multi-junction detectors (monolithic detector arrays), such as single-sided strip detectors (epiplanar and planar) and double-sided strip detectors (planar). Examples of process diagrams for fabrication of the epiplanar and planar detectors are presented in the paper, and selected technological processes are discussed.

Wet-chemical systems and methods for producing black silicon substrates

DOEpatents

Yost, Vernon; Yuan, Hao-Chih; Page, Matthew

2015-05-19

A wet-chemical method of producing a black silicon substrate. The method comprising soaking single crystalline silicon wafers in a predetermined volume of a diluted inorganic compound solution. The substrate is combined with an etchant solution that forms a uniform noble metal nanoparticle induced Black Etch of the silicon wafer, resulting in a nanoparticle that is kinetically stabilized. The method comprising combining with an etchant solution having equal volumes acetonitrile/acetic acid:hydrofluoric acid:hydrogen peroxide.

Hybrid Integrated Platforms for Silicon Photonics

PubMed Central

Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

2010-01-01

A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

Surface-pattern geometry, topography, and chemical modifications during KrF excimer laser micro-drilling of p-type Si (111) wafers in ambient environment of HCl fumes in air

NASA Astrophysics Data System (ADS)

Zakria Butt, Muhammad; Saher, Sobia; Waqas Khaliq, Muhammad; Siraj, Khurram

2016-11-01

Eight mirror-like polished p-type Si (111) wafers were irradiated with 100, 200, 300, 400, 800, 1200, 1600, and 2000 KrF excimer laser pulses in ambient environment of HCl fumes in air. The laser parameters were: wavelength = 248 nm, pulse width = 20 ns, pulse energy = 20 mJ, and repetition rate = 20 Hz. For each set of laser pulses, characterization of the rectangular etched patterns formed on target surface was done by optical/scanning electron microscopy, XRD, and EDX techniques. The average etched depth increased with the increase in number of laser pulses from 100 to 2000 in accord with Sigmoidal (Boltzmann) function, whereas the average etch rate followed an exponential decay with the increase in number of laser pulses. However, the etched area, maximum etched depth, and maximum etch rate were found to increase linearly with the number of laser pulses, but the rate of increase was faster for 100-400 laser pulses (region I) than that for 800-2000 laser pulses (region II). The elemental composition for each etched-pattern determined by EDX shows that both O and Cl contents increase progressively with the increase in the number of laser shots in region I. However, in region II both O and Cl contents attain saturation values of about 39.33 wt.% and 0.14 wt.%, respectively. Perforation of Si wafers was achieved on irradiation with 1200-2000 laser pulses. XRD analysis confirmed the formation of SiO2, SiCl2 and SiCl4 phases in Si (111) wafers due to chemical reaction of silicon with both HCl fumes and oxygen in air.

Detecting Fermi-level shifts by Auger electron spectroscopy in Si and GaAs

NASA Astrophysics Data System (ADS)

Debehets, J.; Homm, P.; Menghini, M.; Chambers, S. A.; Marchiori, C.; Heyns, M.; Locquet, J. P.; Seo, J. W.

2018-05-01

In this paper, changes in surface Fermi-level of Si and GaAs, caused by doping and cleaning, are investigated by Auger electron spectroscopy. Based on the Auger voltage contrast, we compared the Auger transition peak energy but with higher accuracy by using a more accurate analyzer and an improved peak position determination method. For silicon, a peak shift as large as 0.46 eV was detected when comparing a cleaned p-type and n-type wafer, which corresponds rather well with the theoretical difference in Fermi-levels. If no cleaning was applied, the peak position did not differ significantly for both wafer types, indicating Fermi-level pinning in the band gap. For GaAs, peak shifts were detected after cleaning with HF and (NH4)2S-solutions in an inert atmosphere (N2-gas). Although the (NH4)2S-cleaning in N2 is very efficient in removing the oxygen from the surface, the observed Ga- and As-peak shifts are smaller than those obtained after the HF-cleaning. It is shown that the magnitude of the shift is related to the surface composition. After Si-deposition on the (NH4)2S-cleaned surface, the Fermi-level shifts back to a similar position as observed for an as-received wafer, indicating that this combination is not successful in unpinning the Fermi-level of GaAs.

Direct metallization local Al-back surface field for high efficiency screen printed crystalline silicon solar cells.

PubMed

Lee, Jonghwan; Park, Cheolmin; Dao, Vinh Ai; Lee, Youn-Jung; Ryu, Kyungyul; Choi, Gyuho; Kim, Bonggi; Ju, Minkyu; Jeong, Chaehwan; Yi, Junsin

2013-11-01

In this paper, we present a detailed study on the local back contact (LBC) formation of rear-surface-passivated silicon solar cells, where both the LBC opening and metallization are realized by one-step alloying of a dot of fine pattern screen-printed aluminum paste with the silicon substrate. Based on energy dispersive spectrometer (EDS) and scanning electron microscopy (SEM) characterizations, we suggest that the aluminum distribution and the silicon concentration determine the local-back-surface-field (Al-p+) layer thickness, resistivity of the Al-p+ and hence the quality of the Al-p+ formation. The highest penetration of silicon concentration of 78.17% in aluminum resulted in the formation of a 5 microm-deep Al-p+ layer, and the minimum LBC resistivity of 0.92 x 10-6 omega cm2. The degradation of the rear-surface passivation due to high temperature of the LBC formation process can be fully recovered by forming gas annealing (FGA) at temperature and hydrogen content of 450 degrees C and 15%, respectively. The application of the optimized LBC of rear-surface-passivated by a dot of fine pattern screen(-) printed aluminum paste resulted in efficiency of up to 19.98% for the p-type czochralski (CZ) silicon wafers with 10.24 cm2 cell size at 649 mV open circuit voltage. By FGA for rear-surface passivation recovery, efficiencies up to 20.35% with a V(OC) of 662 mV, FF of 82%, and J(SC) of 37.5 mA/cm2 were demonstrated.

Preparation and Thermal Characterization of Annealed Gold Coated Porous Silicon.

PubMed

Behzad, Kasra; Mat Yunus, Wan Mahmood; Talib, Zainal Abidin; Zakaria, Azmi; Bahrami, Afarin

2012-01-16

Porous silicon (PSi) layers were formed on a p-type Si wafer. Six samples were anodised electrically with a 30 mA/cm² fixed current density for different etching times. The samples were coated with a 50-60 nm gold layer and annealed at different temperatures under Ar flow. The morphology of the layers, before and after annealing, formed by this method was investigated by scanning electron microscopy (SEM). Photoacoustic spectroscopy (PAS) measurements were carried out to measure the thermal diffusivity (TD) of the PSi and Au/PSi samples. For the Au/PSi samples, the thermal diffusivity was measured before and after annealing to study the effect of annealing. Also to study the aging effect, a comparison was made between freshly annealed samples and samples 30 days after annealing.

Study of white light emission from ZnS/PS composite system

NASA Astrophysics Data System (ADS)

Wang, Caifeng; Li, Qingshan; Lu, Lei; Zhang, Lichun; Qi, Hongxia

2007-09-01

ZnS films were deposited by pulsed laser deposition (PLD) on porous silicon (PS) substrates formed by electrochemical anodization of p-type (100) silicon wafer. The photoluminescence (PL) spectra of ZnS/PS composites were measured at room temperature. Under different excitation wavelengths, the relative integrated intensities of the red light emission from PS layers and the blue-green emission from ZnS films had different values. After samples were annealed in vacuum at different temperatures (200, 300, and 400 Celsius degree) for 30 min respectively, a new green emission located at around 550 nm appeared in the PL spectra of all ZnS/PS samples, and all of the ZnS/PS composites had a broad PL band (450-700 nm) in the visible region, exhibiting intensively white light emission.

Tantalum oxide/silicon nitride: A negatively charged surface passivation stack for silicon solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wan, Yimao, E-mail: yimao.wan@anu.edu.au; Bullock, James; Cuevas, Andres

2015-05-18

This letter reports effective passivation of crystalline silicon (c-Si) surfaces by thermal atomic layer deposited tantalum oxide (Ta{sub 2}O{sub 5}) underneath plasma enhanced chemical vapour deposited silicon nitride (SiN{sub x}). Cross-sectional transmission electron microscopy imaging shows an approximately 2 nm thick interfacial layer between Ta{sub 2}O{sub 5} and c-Si. Surface recombination velocities as low as 5.0 cm/s and 3.2 cm/s are attained on p-type 0.8 Ω·cm and n-type 1.0 Ω·cm c-Si wafers, respectively. Recombination current densities of 25 fA/cm{sup 2} and 68 fA/cm{sup 2} are measured on 150 Ω/sq boron-diffused p{sup +} and 120 Ω/sq phosphorus-diffused n{sup +} c-Si, respectively. Capacitance–voltage measurements reveal a negativemore » fixed insulator charge density of −1.8 × 10{sup 12 }cm{sup −2} for the Ta{sub 2}O{sub 5} film and −1.0 × 10{sup 12 }cm{sup −2} for the Ta{sub 2}O{sub 5}/SiN{sub x} stack. The Ta{sub 2}O{sub 5}/SiN{sub x} stack is demonstrated to be an excellent candidate for surface passivation of high efficiency silicon solar cells.« less

Silicon vacancy-related centers in non-irradiated 6H-SiC nanostructure

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bagraev, N. T., E-mail: Impurity.Dipole@mail.ioffe.ru; Danilovskii, E. Yu.; Gets, D. S.

2015-05-15

We present the first findings of the silicon vacancy related centers identified in the non-irradiated 6H-SiC nanostructure using the electron spin resonance (ESR) and electrically-detected (ED) ESR technique. This planar 6H-SiC nanostructure represents the ultra-narrow p-type quantum well confined by the δ-barriers heavily doped with boron on the surface of the n-type 6H-SiC(0001) wafer. The new EDESR technique by measuring the only magnetoresistance of the 6H-SiC nanostructure under the high frequency generation from the δ-barriers appears to allow the identification of the isolated silicon vacancy centers as well as the triplet center with spin state S = 1. The samemore » triplet center that is characterized by the large value of the zero-field splitting constant D and anisotropic g-factor is revealed by the ESR (X-band) method. The hyperfine (HF) lines in the ESR and EDESR spectra originating from the HF interaction with the {sup 14}N nucleus seem to attribute this triplet center to the N-V{sub Si} defect.« less

Predictable quantum efficient detector based on n-type silicon photodiodes

NASA Astrophysics Data System (ADS)

Dönsberg, Timo; Manoocheri, Farshid; Sildoja, Meelis; Juntunen, Mikko; Savin, Hele; Tuovinen, Esa; Ronkainen, Hannu; Prunnila, Mika; Merimaa, Mikko; Tang, Chi Kwong; Gran, Jarle; Müller, Ingmar; Werner, Lutz; Rougié, Bernard; Pons, Alicia; Smîd, Marek; Gál, Péter; Lolli, Lapo; Brida, Giorgio; Rastello, Maria Luisa; Ikonen, Erkki

2017-12-01

The predictable quantum efficient detector (PQED) consists of two custom-made induced junction photodiodes that are mounted in a wedged trap configuration for the reduction of reflectance losses. Until now, all manufactured PQED photodiodes have been based on a structure where a SiO2 layer is thermally grown on top of p-type silicon substrate. In this paper, we present the design, manufacturing, modelling and characterization of a new type of PQED, where the photodiodes have an Al2O3 layer on top of n-type silicon substrate. Atomic layer deposition is used to deposit the layer to the desired thickness. Two sets of photodiodes with varying oxide thicknesses and substrate doping concentrations were fabricated. In order to predict recombination losses of charge carriers, a 3D model of the photodiode was built into Cogenda Genius semiconductor simulation software. It is important to note that a novel experimental method was developed to obtain values for the 3D model parameters. This makes the prediction of the PQED responsivity a completely autonomous process. Detectors were characterized for temperature dependence of dark current, spatial uniformity of responsivity, reflectance, linearity and absolute responsivity at the wavelengths of 488 nm and 532 nm. For both sets of photodiodes, the modelled and measured responsivities were generally in agreement within the measurement and modelling uncertainties of around 100 parts per million (ppm). There is, however, an indication that the modelled internal quantum deficiency may be underestimated by a similar amount. Moreover, the responsivities of the detectors were spatially uniform within 30 ppm peak-to-peak variation. The results obtained in this research indicate that the n-type induced junction photodiode is a very promising alternative to the existing p-type detectors, and thus give additional credibility to the concept of modelled quantum detector serving as a primary standard. Furthermore, the manufacturing of PQEDs is no longer dependent on the availability of a certain type of very lightly doped p-type silicon wafers.

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of +/-500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.

Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-based wafer bonding process.

PubMed

Logan, Andrew; Yeow, John T W

2009-05-01

We report the fabrication and experimental testing of 1-D 23-element capacitive micromachined ultrasonic transducer (CMUT) arrays that have been fabricated using a novel wafer-bonding process whereby the membrane and the insulation layer are both silicon nitride. The membrane and cell cavities are deposited and patterned on separate wafers and fusion-bonded in a vacuum environment to create CMUT cells. A user-grown silicon-nitride membrane layer avoids the need for expensive silicon-on-insulator (SOI) wafers, reduces parasitic capacitance, and reduces dielectric charging. It allows more freedom in selecting the membrane thickness while also providing the benefits of wafer-bonding fabrication such as excellent fill factor, ease of vacuum sealing, and a simplified fabrication process when compared with the more standard sacrificial release process. The devices fabricated have a cell diameter of 22 microm, a membrane thickness of 400 nm, a gap depth of 150 nm, and an insulation thickness of 250 nm. The resonant frequency of the CMUT in air is 17 MHz and has an attenuation compensated center frequency of approximately 9 MHz in immersion with a -6 dB fractional bandwidth of 123%. This paper presents the fabrication process and some characterization results.

High frequency guided wave propagation in monocrystalline silicon wafers

NASA Astrophysics Data System (ADS)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2017-04-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

Thermo-acousto-photonics for noncontact temperature measurement in silicon wafer processing

NASA Astrophysics Data System (ADS)

Suh, Chii-Der S.; Rabroker, G. Andrew; Chona, Ravinder; Burger, Christian P.

1999-10-01

A non-contact thermometry technique has been developed to characterize the thermal state of silicon wafers during rapid thermal processing. Information on thermal variations is obtained from the dispersion relations of the propagating waveguide mode excited in wafers using a non-contact, broadband optical system referred to as Thermal Acousto- Photonics for Non-Destructive Evaluation. Variations of thermo-mechanical properties in silicon wafers are correlated to temperature changes by performing simultaneous time-frequency analyses on Lamb waveforms acquired with a fiber-tip interferometer sensor. Experimental Lamb wave data collected for cases ranging from room temperature to 400 degrees C is presented. The results show that the temporal progressions of all spectral elements found in the fundamental antisymmetric mode are strong functions of temperature. This particular attribute is exploited to achieve a thermal resolution superior to the +/- 5 degrees C attainable through current pyrometric techniques. By analyzing the temperature-dependent group velocity of a specific frequency component over the temperature range considered and then comparing the results to an analytical model developed for silicon wafers undergoing annealing, excellent agreement was obtained. Presented results demonstrate the feasibility of applying laser-induced stress waves as a temperature diagnostic during rapid thermal processing.

CROSS-DISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Excellent Passivation of p-Type Si Surface by Sol-Gel Al2O3 Films

NASA Astrophysics Data System (ADS)

Xiao, Hai-Qing; Zhou, Chun-Lan; Cao, Xiao-Ning; Wang, Wen-Jing; Zhao, Lei; Li, Hai-Ling; Diao, Hong-Wei

2009-08-01

Al2O3 films with a thickness of about 100 nm synthesized by spin coating and thermally treated are applied for field-induced surface passivation of p-type crystalline silicon. The level of surface passivation is determined by techniques based on photoconductance. An effective surface recombination velocity below 100 cm/s is obtained on 10Ω ·cm p-type c-Si wafers (Cz Si). A high density of negative fixed charges in the order of 1012 cm-2 is detected in the Al2O3 films and its impact on the level of surface passivation is demonstrated experimentally. Furthermore, a comparison between the surface passivation achieved for thermal SiO2 and plasma enhanced chemical vapor deposition SiNx:H films on the same c-Si is presented. The high negative fixed charge density explains the excellent passivation of p-type c-Si by Al2O3.

Electroless epitaxial etching for semiconductor applications

DOEpatents

McCarthy, Anthony M.

2002-01-01

A method for fabricating thin-film single-crystal silicon on insulator substrates using electroless etching for achieving efficient etch stopping on epitaxial silicon substrates. Microelectric circuits and devices are prepared on epitaxial silicon wafers in a standard fabrication facility. The wafers are bonded to a holding substrate. The silicon bulk is removed using electroless etching leaving the circuit contained within the epitaxial layer remaining on the holding substrate. A photolithographic operation is then performed to define streets and wire bond pad areas for electrical access to the circuit.

Fabrication and characterization of piezoelectric micromachined ultrasonic transducers with thick composite PZT films.

PubMed

Wang, Zhihong; Zhu, Weiguang; Zhu, Hong; Miao, Jianmin; Chao, Chen; Zhao, Changlei; Tan, Ooi Kiang

2005-12-01

Ferroelectric microelectromechanical systems (MEMS) has been a growing area of research in past decades, in which ferroelectric films are combined with silicon technology for a variety of applications, such as piezo-electric micromachined ultrasonic transducers (pMUTs), which represent a new approach to ultrasound detection and generation. For ultrasound-radiating applications, thicker PZT films are preferred because generative force and response speed of the diaphragm-type transducers increase with increasing film thickness. However, integration of 4- to 20-microm thick PZT films on silicon wafer, either the deposition or the patterning, is still a bottleneck in the micromachining process. This paper reports on a diaphragm-type pMUT. A composite coating technique based on chemical solution deposition and high-energy ball milled powder has been used to fabricate thick PZT films. Micromachining of the pMUTs using such thick films has been investigated. The fabricated pMUT with crack-free PZT films up to 7-microm thick was evaluated as an ultrasonic transmitter. The generated sound pressure level of up to 120 dB indicates that the fabricated pMUT has very good ultrasound-radiating performance and, therefore, can be used to compose pMUT arrays for generating ultrasound beam with high directivity in numerous applications. The pMUT arrays also have been demonstrated.

High-throughput preparation of complex multi-scale patterns from block copolymer/homopolymer blend films

NASA Astrophysics Data System (ADS)

Park, Hyungmin; Kim, Jae-Up; Park, Soojin

2012-02-01

A simple, straightforward process for fabricating multi-scale micro- and nanostructured patterns from polystyrene-block-poly(2-vinylpyridine) (PS-b-P2VP)/poly(methyl methacrylate) (PMMA) homopolymer in a preferential solvent for PS and PMMA is demonstrated. When the PS-b-P2VP/PMMA blend films were spin-coated onto a silicon wafer, PS-b-P2VP micellar arrays consisting of a PS corona and a P2VP core were formed, while the PMMA macrodomains were isolated, due to the macrophase separation caused by the incompatibility between block copolymer micelles and PMMA homopolymer during the spin-coating process. With an increase of PMMA composition, the size of PMMA macrodomains increased. Moreover, the P2VP blocks have a strong interaction with a native oxide of the surface of the silicon wafer, so that the P2VP wetting layer was first formed during spin-coating, and PS nanoclusters were observed on the PMMA macrodomains beneath. Whereas when a silicon surface was modified with a PS brush layer, the PS nanoclusters underlying PMMA domains were not formed. The multi-scale patterns prepared from copolymer micelle/homopolymer blend films are used as templates for the fabrication of gold nanoparticle arrays by incorporating the gold precursor into the P2VP chains. The combination of nanostructures prepared from block copolymer micellar arrays and macrostructures induced by incompatibility between the copolymer and the homopolymer leads to the formation of complex, multi-scale surface patterns by a simple casting process.A simple, straightforward process for fabricating multi-scale micro- and nanostructured patterns from polystyrene-block-poly(2-vinylpyridine) (PS-b-P2VP)/poly(methyl methacrylate) (PMMA) homopolymer in a preferential solvent for PS and PMMA is demonstrated. When the PS-b-P2VP/PMMA blend films were spin-coated onto a silicon wafer, PS-b-P2VP micellar arrays consisting of a PS corona and a P2VP core were formed, while the PMMA macrodomains were isolated, due to the macrophase separation caused by the incompatibility between block copolymer micelles and PMMA homopolymer during the spin-coating process. With an increase of PMMA composition, the size of PMMA macrodomains increased. Moreover, the P2VP blocks have a strong interaction with a native oxide of the surface of the silicon wafer, so that the P2VP wetting layer was first formed during spin-coating, and PS nanoclusters were observed on the PMMA macrodomains beneath. Whereas when a silicon surface was modified with a PS brush layer, the PS nanoclusters underlying PMMA domains were not formed. The multi-scale patterns prepared from copolymer micelle/homopolymer blend films are used as templates for the fabrication of gold nanoparticle arrays by incorporating the gold precursor into the P2VP chains. The combination of nanostructures prepared from block copolymer micellar arrays and macrostructures induced by incompatibility between the copolymer and the homopolymer leads to the formation of complex, multi-scale surface patterns by a simple casting process. Electronic supplementary information (ESI) available: AFM images of PS-b-P2VP/PMMA blend films and cross-sectional line scans. See DOI: 10.1039/c2nr11792d

Solar cell circuit and method for manufacturing solar cells

NASA Technical Reports Server (NTRS)

Mardesich, Nick (Inventor)

2010-01-01

The invention is a novel manufacturing method for making multi-junction solar cell circuits that addresses current problems associated with such circuits by allowing the formation of integral diodes in the cells and allows for a large number of circuits to readily be placed on a single silicon wafer substrate. The standard Ge wafer used as the base for multi-junction solar cells is replaced with a thinner layer of Ge or a II-V semiconductor material on a silicon/silicon dioxide substrate. This allows high-voltage cells with multiple multi-junction circuits to be manufactured on a single wafer, resulting in less array assembly mass and simplified power management.

Chemical method for producing smooth surfaces on silicon wafers

DOEpatents

Yu, Conrad

2003-01-01

An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

Microminiature gas chromatograph

DOEpatents

Yu, Conrad M.

1996-01-01

A microminiature gas chromatograph (.mu.GC) comprising a least one silicon wafer, a gas injector, a column, and a detector. The gas injector has a normally closed valve for introducing a mobile phase including a sample gas in a carrier gas. The valve is fully disposed in the silicon wafer(s). The column is a microcapillary in silicon crystal with a stationary phase and is mechanically connected to receive the mobile phase from the gas injector for the molecular separation of compounds in the sample gas. The detector is mechanically connected to the column for the analysis of the separated compounds of sample gas with electronic means, e.g., ion cell, field emitter and PIN diode.

Comparing the transient response of a resistive-type sensor with a thin film thermocouple during the post-exposure bake process

NASA Astrophysics Data System (ADS)

Kreider, Kenneth G.; DeWitt, David P.; Fowler, Joel B.; Proctor, James E.; Kimes, William A.; Ripple, Dean C.; Tsai, Benjamin K.

2004-04-01

Recent studies on dynamic temperature profiling and lithographic performance modeling of the post-exposure bake (PEB) process have demonstrated that the rate of heating and cooling may have an important influence on resist lithographic response. Measuring the transient surface temperature during the heating or cooling process with such accuracy can only be assured if the sensors embedded in or attached to the test wafer do not affect the temperature distribution in the bare wafer. In this paper we report on an experimental and analytical study to compare the transient response of embedded platinum resistance thermometer (PRT) sensors with surface-deposited, thin-film thermocouples (TFTC). The TFTCs on silicon wafers have been developed at NIST to measure wafer temperatures in other semiconductor thermal processes. Experiments are performed on a test bed built from a commercial, fab-qualified module with hot and chill plates using wafers that have been instrumented with calibrated type-E (NiCr/CuNi) TFTCs and commercial PRTs. Time constants were determined from an energy-balance analysis fitting the temperature-time derivative to the wafer temperature during the heating and cooling processes. The time constants for instrumented wafers ranged from 4.6 s to 5.1 s on heating for both the TFTC and PRT sensors, with an average difference less than 0.1 s between the TFTCs and PRTs and slightly greater differences on cooling.

Hybrid integrated single-wavelength laser with silicon micro-ring reflector

NASA Astrophysics Data System (ADS)

Ren, Min; Pu, Jing; Krishnamurthy, Vivek; Xu, Zhengji; Lee, Chee-Wei; Li, Dongdong; Gonzaga, Leonard; Toh, Yeow T.; Tjiptoharsono, Febi; Wang, Qian

2018-02-01

A hybrid integrated single-wavelength laser with silicon micro-ring reflector is demonstrated theoretically and experimentally. It consists of a heterogeneously integrated III-V section for optical gain, an adiabatic taper for light coupling, and a silicon micro-ring reflector for both wavelength selection and light reflection. Heterogeneous integration processes for multiple III-V chips bonded to an 8-inch Si wafer have been developed, which is promising for massive production of hybrid lasers on Si. The III-V layer is introduced on top of a 220-nm thick SOI layer through low-temperature wafer-boning technology. The optical coupling efficiency of >85% between III-V and Si waveguide has been achieved. The silicon micro-ring reflector, as the key element of the hybrid laser, is studied, with its maximized reflectivity of 85.6% demonstrated experimentally. The compact single-wavelength laser enables fully monolithic integration on silicon wafer for optical communication and optical sensing application.

Uncertainty evaluation of thickness and warp of a silicon wafer measured by a spectrally resolved interferometer

NASA Astrophysics Data System (ADS)

Praba Drijarkara, Agustinus; Gergiso Gebrie, Tadesse; Lee, Jae Yong; Kang, Chu-Shik

2018-06-01

Evaluation of uncertainty of thickness and gravity-compensated warp of a silicon wafer measured by a spectrally resolved interferometer is presented. The evaluation is performed in a rigorous manner, by analysing the propagation of uncertainty from the input quantities through all the steps of measurement functions, in accordance with the ISO Guide to the Expression of Uncertainty in Measurement. In the evaluation, correlation between input quantities as well as uncertainty attributed to thermal effect, which were not included in earlier publications, are taken into account. The temperature dependence of the group refractive index of silicon was found to be nonlinear and varies widely within a wafer and also between different wafers. The uncertainty evaluation described here can be applied to other spectral interferometry applications based on similar principles.

N-type nano-silicon powders with ultra-low electrical resistivity as anode materials in lithium ion batteries

NASA Astrophysics Data System (ADS)

Yue, Zhihao; Zhou, Lang; Jin, Chenxin; Xu, Guojun; Liu, Liekai; Tang, Hao; Li, Xiaomin; Sun, Fugen; Huang, Haibin; Yuan, Jiren

2017-06-01

N-type silicon wafers with electrical resistivity of 0.001 Ω cm were ball-milled to powders and part of them was further mechanically crushed by sand-milling to smaller particles of nano-size. Both the sand-milled and ball-milled silicon powders were, respectively, mixed with graphite powder (silicon:graphite = 5:95, weight ratio) as anode materials for lithium ion batteries. Electrochemical measurements, including cycle and rate tests, present that anode using sand-milled silicon powder performed much better. The first discharge capacity of sand-milled silicon anode is 549.7 mAh/g and it is still up to 420.4 mAh/g after 100 cycles. Besides, the D50 of sand-milled silicon powder shows ten times smaller in particle size than that of ball-milled silicon powder, and they are 276 nm and 2.6 μm, respectively. In addition, there exist some amorphous silicon components in the sand-milled silicon powder excepting the multi-crystalline silicon, which is very different from the ball-milled silicon powder made up of multi-crystalline silicon only.

Surface etching technologies for monocrystalline silicon wafer solar cells

NASA Astrophysics Data System (ADS)

Tang, Muzhi

With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

Three-dimensional crossbar arrays of self-rectifying Si/SiO 2/Si memristors

DOE PAGES

Li, Can; Han, Lili; Jiang, Hao; ...

2017-06-05

Memristors are promising building blocks for the next generation memory, unconventional computing systems and beyond. Currently common materials used to build memristors are not necessarily compatible with the silicon dominant complementary metal-oxide-semiconductor (CMOS) technology. Furthermore, external selector devices or circuits are usually required in order for large memristor arrays to function properly, resulting in increased circuit complexity. Here we demonstrate fully CMOS-compatible, all-silicon based and self-rectifying memristors that negate the need for external selectors in large arrays. It consists of p- and n-type doped single crystalline silicon electrodes and a thin chemically produced silicon oxide switching layer. The device exhibitsmore » repeatable resistance switching behavior with high rectifying ratio (10 5), high ON/OFF conductance ratio (10 4) and attractive retention at 300 °C. We further build a 5-layer 3-dimensional (3D) crossbar array of 100 nm memristors by stacking fluid supported silicon membranes. The CMOS compatibility and self-rectifying behavior open up opportunities for mass production of memristor arrays and 3D hybrid circuits on full-wafer scale silicon and flexible substrates without increasing circuit complexity.« less

Process for Fabrication of Superconducting Vias for Electrical Connection to Groundplane in Cryogenic Detectors

NASA Technical Reports Server (NTRS)

Denis, Kevin L. (Inventor)

2018-01-01

Disclosed are systems, methods, and non-transitory computer-readable storage media for fabrication of silicon on insulator (SOI) wafers with a superconductive via for electrical connection to a groundplane. Fabrication of the SOI wafer with a superconductive via can involve depositing a superconducting groundplane onto a substrate with the superconducting groundplane having an oxidizing layer and a non-oxidizing layer. A layer of monocrystalline silicon can be bonded to the superconducting groundplane and a photoresist layer can be applied to the layer of monocrystalline silicon and the SOI wafer can be etched with the oxygen rich etching plasma, resulting in a monocrystalline silicon top layer with a via that exposes the superconducting groundplane. Then, the fabrication can involve depositing a superconducting surface layer to cover the via.

Novel Bonding Technology for Hermetically Sealed Silicon Micropackage

NASA Astrophysics Data System (ADS)

Lee, Duck-Jung; Ju, Byeong-Kwon; Choi, Woo-Beom; Jeong, Jee-Won; Lee, Yun-Hi; Jang, Jin; Lee, Kwang-Bae; Oh, Myung-Hwan

1999-01-01

We performed glass-to-silicon bonding and fabricated a hermetically sealed silicon wafer using silicon direct bonding followed by anodic bonding (SDAB). The hydrophilized glass and silicon wafers in solution were dried and initially bonded in atmosphere as in the silicon direct bonding (SDB) process, but annealing at high temperature was not performed. Anodic bonding was subsequently carried out for the initially bonded specimens. Then the wafer pairs bonded by the SDAB method were different from those bonded by the anodic bonding process only. The effects of the bonding process on the bonded area and tensile strength were investigated as functions of bonding temperature and voltage. Using scanning electron microscopy (SEM), the cross-sectional view of the bonded interface region was observed. In order to investigate the migration of the sodium ions in the bonding process, the concentration of the bonded glass was compared with that of standard glass. The specimen bonded using the SDAB process had higher efficiency than that using the anodic bonding process only.

Cu gettering by phosphorus-doped emitters in p-type silicon: Effect on light-induced degradation

NASA Astrophysics Data System (ADS)

Inglese, Alessandro; Laine, Hannu S.; Vähänissi, Ville; Savin, Hele

2018-01-01

The presence of copper (Cu) contamination is known to cause relevant light-induced degradation (Cu-LID) effects in p-type silicon. Due to its high diffusivity, Cu is generally regarded as a relatively benign impurity, which can be readily relocated during device fabrication from the wafer bulk, i.e. the region affected by Cu-LID, to the surface phosphorus-doped emitter. This contribution examines in detail the impact of gettering by industrially relevant phosphorus layers on the strength of Cu-LID effects. We find that phosphorus gettering does not always prevent the occurrence of Cu-LID. Specifically, air-cooling after an isothermal anneal at 800°C results in only weak impurity segregation to the phosphorus-doped layer, which turns out to be insufficient for effectively mitigating Cu-LID effects. Furthermore, we show that the gettering efficiency can be enhanced through the addition of a slow cooling ramp (-4°C/min) between 800°C and 600°C, resulting in the nearly complete disappearance of Cu-LID effects.

Silicon micromachined waveguides for millimeter and submillimeter wavelengths

NASA Technical Reports Server (NTRS)

Yap, Markus; Tai, Yu-Chong; Mcgrath, William R.; Walker, Christopher

1992-01-01

The majority of radio receivers, transmitters, and components operating at millimeter and submillimeter wavelengths utilize rectangular waveguides in some form. However, conventional machining techniques for waveguides operating above a few hundred GHz are complicated and costly. This paper reports on the development of silicon micromachining techniques to create silicon-based waveguide circuits which can operate at millimeter and submillimeter wavelengths. As a first step, rectangular WR-10 waveguide structures have been fabricated from (110) silicon wafers using micromachining techniques. The waveguide is split along the broad wall. Each half is formed by first etching a channel completely through a wafer. Potassium hydroxide is used to etch smooth mirror-like vertical walls and LPCVD silicon nitride is used as a masking layer. This wafer is then bonded to another flat wafer using a polyimide bonding technique and diced into the U-shaped half wavelengths. Finally, a gold layer is applied to the waveguide walls. Insertion loss measurements show losses comparable to those of standard metal waveguides. It is suggested that active devices and planar circuits can be integrated with the waveguides, solving the traditional mounting problems. Potential applications in terahertz instrumentation technology are further discussed.

Silicon Nanowires for Solar Thermal Energy Harvesting: an Experimental Evaluation on the Trade-off Effects of the Spectral Optical Properties.

PubMed

Sekone, Abdoul Karim; Chen, Yu-Bin; Lu, Ming-Chang; Chen, Wen-Kai; Liu, Chia-An; Lee, Ming-Tsang

2016-12-01

Silicon nanowire possesses great potential as the material for renewable energy harvesting and conversion. The significantly reduced spectral reflectivity of silicon nanowire to visible light makes it even more attractive in solar energy applications. However, the benefit of its use for solar thermal energy harvesting remains to be investigated and has so far not been clearly reported. The purpose of this study is to provide practical information and insight into the performance of silicon nanowires in solar thermal energy conversion systems. Spectral hemispherical reflectivity and transmissivity of the black silicon nanowire array on silicon wafer substrate were measured. It was observed that the reflectivity is lower in the visible range but higher in the infrared range compared to the plain silicon wafer. A drying experiment and a theoretical calculation were carried out to directly evaluate the effects of the trade-off between scattering properties at different wavelengths. It is clearly seen that silicon nanowires can improve the solar thermal energy harnessing. The results showed that a 17.8 % increase in the harvest and utilization of solar thermal energy could be achieved using a silicon nanowire array on silicon substrate as compared to that obtained with a plain silicon wafer.

Decontamination of Surfaces Exposed to Carbonbased Nanotubes and Nanomaterials

NASA Astrophysics Data System (ADS)

Karimi, Zahra

Contamination of surfaces by nanomaterials can happen due to accidental spillage and release or gradual accumulation during processing or handling. Considering the increasingly wide use of nanomaterials in industry and research labs and also taking into account the diversity of physical and chemical properties of different nanomaterials (such as solubility, aggregation/agglomeration, and surface reactivity), there is a pressing need to define reliable nanomaterial-specific decontamination guidelines. In this project, we propose and investigate a potential method for surface decontamination of carbon-based nanomaterials using solvent cleaning and wipes. The results show that the surfactant-assisted removal efficiencies of multi-walled carbon nanotubes, single walled carbon nantubes and single walled carbon nano-horns from silicon wafers through wiping is greater than 95%, 90% and 78%, respectively. The need for further studies to understand the mechanisms of nanomaterial removal from surfaces and development of standard techniques for surface decontamination of nanomaterials is highlighted. Another phase of experiments were performed to examine the efficiency of surfactants to remove multi-walled carbon nanotubes (MWCNTs) from silicon substrates with nano and microscaled features. In the first set of experiments, nanoscale features were induced on silicon wafers using SF6 and O2 plasma. Atomic force microscopy (AFM) was used to observe the surface topology and roughness. In the second set, well-defined microscale topological features were induced on silicon wafers using photo lithography and plasma etching. The etching time was varied to create semi-ellipsoidal pits with average diameter and height of ~ 7-9 microm, and ~ 1-3 microm, respectively. MWCNTs in the form of liquid solution were deposited on the surface of silicon wafers using the spin coating process. For the cleaning process, the contaminated surfaces were first sprayed with different types of surfactant or water. Then, the MWCNTs were wiped off using a simple wiping mechanism. The areal density of the MWCNTs was quantified prior to and after the removal using scanning electron microscopy (SEM) and post-image processing. For a surface featured with nanoscale asperities, the removal efficiency was measured to be in the range 83-99% based on substrate type and surface roughness. No evident relationship was observed between the etching time and the removal efficiency. For microscale features, increase of the etching time significantly decreases the removal efficiency.

Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

NASA Technical Reports Server (NTRS)

Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.;

Characterization of zinc oxide thin film for pH detector

NASA Astrophysics Data System (ADS)

Hashim, Uda; Fathil, M. F. M.; Arshad, M. K. Md; Gopinath, Subash C. B.; Uda, M. N. A.

2017-03-01

This paper presents the fabrication process of the zinc oxide thin films for using to act as pH detection by using different PH solution. Sol-gel solution technique is used for preparing zinc oxide seed solution, followed by metal oxide deposition process by using spin coater on the silicon dioxide. Silicon dioxide layer is grown on the silicon wafer, then, ZnO seed solution is deposited on the silicon layer, baked, and annealing process carried on to undergo the characterization of its surface morphology, structural and crystalline phase. Electrical characterization is showed by using PH 4, 7, and 10 is dropped on the surface of the die, in addition, APTES solution is used as linker and also as a references of the electrical characterization.

1366 Project Silicon: Reclaiming US Silicon PV Leadership

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling ofmore » 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. SunPath filled the crucial development step between the original research effort in Lexington and the GW factory scheduled to be online before the end of the decade. At the conclusion of the project, it is clear that the Direct Wafer™ technology will have a dramatic impact on the entire silicon photovoltaic supply chain by effectively doubling existing silicon capacity (by reducing silicon usage by 50%) and reducing supply chain capital costs by 35%. The technology, when fully-scaled in the US, will also lead to significant job growth, with the eventual creation of 1,000 jobs in Western New York.« less

Thin edge-defined film-fed growth (EFG) octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1992-03-01

Mobil Solar Energy Corp. investigated manufacturing crystalline silicon wafers using the edge-defined film-fed growth (EFG) technique. This report identifies the following: (1) current capabilities for manufacturing 200-micron-thick crystalline silicon wafers (10 cm x 10 cm) produced by growing octagons using the EFG technique and laser cutting them into wafers; (2) potential manufacturing improvements from decreasing the thickness of the wafers, improving the quality of the laser cut edge, and increasing cutting speed, all of which lead to reduce manufacturing costs, improved performance, and increased production capacities; (3) problems that impede achieving these potentials; and (4) costs and other requirements involved in overcoming the problems.

High-efficiency impurity activation by precise control of cooling rate during atmospheric pressure thermal plasma jet annealing of 4H-SiC wafer

NASA Astrophysics Data System (ADS)

Maruyama, Keisuke; Hanafusa, Hiroaki; Ashihara, Ryuhei; Hayashi, Shohei; Murakami, Hideki; Higashi, Seiichiro

2015-06-01

We have investigated high-temperature and rapid annealing of a silicon carbide (SiC) wafer by atmospheric pressure thermal plasma jet (TPJ) irradiation for impurity activation. To reduce the temperature gradient in the SiC wafer, a DC current preheating system and the lateral back-and-forth motion of the wafer were introduced. A maximum surface temperature of 1835 °C within 2.4 s without sample breakage was achieved, and aluminum (Al), phosphorus (P), and arsenic (As) activations in SiC were demonstrated. We have investigated precise control of heating rate (Rh) and cooling rate (Rc) during rapid annealing of P+-implanted 4H-SiC and its impact on impurity activation. No dependence of resistivity on Rh was observed, while increasing Rc significantly decreased resistivity. A minimum resistivity of 0.0025 Ω·cm and a maximum carrier concentration of 2.9 × 1020 cm-3 were obtained at Rc = 568 °C/s.

A novel approach for betavoltaic devices utilizing nitrogen doped graphene powder as an electrode

NASA Astrophysics Data System (ADS)

Drake, Kyle Joseph

Nitrogen doped graphene was used to create p-n junctions with boron doped silicon wafers. When exposed to beta particle radiation, an electrical current is produced. The betavoltaic cells were fabricated and tested for comparison of power output with that of other types of betavoltaic cells reported in the literature. The electronic properties of graphene allowed it to be a plausible replacement part of the semiconductor used to convert the energy of the beta radiation to usable electrical energy. The research showed that an electric current was produced by the fabricated experimental cells.

MEMS for vibration energy harvesting

NASA Astrophysics Data System (ADS)

Li, Lin; Zhang, Yangjian; San, Haisheng; Guo, Yinbiao; Chen, Xuyuan

2008-03-01

In this paper, a capacitive vibration-to-electrical energy harvester was designed. An integrated process flow for fabricating the designed capacitive harvester is presented. For overcoming the disadvantage of depending on external power source in capacitive energy harvester, two parallel electrodes with different work functions are used as the two electrodes of the capacitor to generate a build-in voltage for initially charging the capacitor. The device is a sandwich structure of silicon layer in two glass layers with area of about 1 cm2. The silicon structure is fabricated by using silicon-on-insulator (SOI) wafer. The glass wafers are anodic bonded on to both sides of the SOI wafer to create a vacuum sealed package.

External self-gettering of nickel in float zone silicon wafers

NASA Astrophysics Data System (ADS)

Gay, N.; Martinuzzi, S.

1997-05-01

During indiffusion of Ni atoms in silicon crystals at 950 °C from a nickel layer source, Ni-Si alloys can be formed close to the surface. Metal solubility in these alloys is higher than in silicon, which induces a marked segregation gettering of the Ni atoms which have diffused in the bulk of the wafers. Consequently, the regions of the wafers covered with the Ni layer are less contaminated than adjacent regions in which Ni atoms have also penetrated, as shown by the absence of precipitates and the higher diffusion length of minority carriers. The results suggest the existence of external self-gettering of Ni atoms by the nickel source.

Microminiature gas chromatograph

DOEpatents

Yu, C.M.

1996-12-10

A microminiature gas chromatograph ({mu}GC) comprising a least one silicon wafer, a gas injector, a column, and a detector. The gas injector has a normally closed valve for introducing a mobile phase including a sample gas in a carrier gas. The valve is fully disposed in the silicon wafer(s). The column is a microcapillary in silicon crystal with a stationary phase and is mechanically connected to receive the mobile phase from the gas injector for the molecular separation of compounds in the sample gas. The detector is mechanically connected to the column for the analysis of the separated compounds of sample gas with electronic means, e.g., ion cell, field emitter and PIN diode. 7 figs.

Silicon wafer temperature monitoring using all-fiber laser ultrasonics

NASA Astrophysics Data System (ADS)

Alcoz, Jorge J.; Duffer, Charles E.

1998-03-01

Laser-ultrasonics is a very attractive technique for in-line process control in the semiconductor industry as it is compatible with the clean room environment and offers the capability to inspect parts at high-temperature. We describe measurements of the velocity of laser-generated Lamb waves in silicon wafers as a function of temperature using fiber- optic laser delivery and all-fiber interferometric sensing. Fundamental anti-symmetric Lamb-wave modes were generated in 5 inches < 111 > silicon wafers using a Nd:YAG laser coupled to a large-core multimode fiber. Generation was also performed using an array of sources created with a diffraction grating. For detection a compact fiber-optic sensor was used which is well suited for industrial environments as it is compact, rugged, stable, and low-cost. The wafers were heated up to 1000 degrees C and the temperature correlated with ultrasonic velocity measurements.

Investigation of Different Colloidal Porous Silicon Solutions and Their Composite Solid Matrix Rods by Optical Techniques

NASA Astrophysics Data System (ADS)

Khan, M. Naziruddin; Aldalbahi, Ali; Almohammedi, Abdullah

2018-03-01

Colloidal porous silicon (PSi) in different solvents was synthesized by simple chemical etching. Colloidal solutions were then prepared using different quantities of silicon wafer pieces (Pcs) and chloroplatinic (Pt) acid in catalyst solution. The effect on the properties of the colloidal solutions and composite rods were investigated using various optical characterization techniques. Absorption and photoluminescence (PL) intensity of the colloidal PSi solutions are observed to depend on the quantity of wafer Pcs, the Pt-solution, and the porosity formation on the wafer surface. The morphological structure of the PSi in a solvent and the solid-rod environments were studied using field-emission scanning electron microscopy (FE-SEM) and were observed to have different structures. A mono-oriented structure of PSi exists in tetrahydrofuran, which has stereo orientation in dioxane and dimethylsulfoxide (approximately 5-8 nm as confirmed using high resolution transmission electron microscopy). Subsequently, some colloidal PSi solutions were directly embedded in three types of sol-gel-based matrices, silica, ormosils (or organically modified silica) and polymer, which easily generated solid rods. Spontaneous emission (SE) of the PSi solutions and their composite rods were examined using a high power picosecond 355 nm laser source. The emitted PL and SE signals of the colloidal PSi solutions were dependent on the Pt volume, nature of the solvent, quantity of Si wafer piece, and pumping energy. The response of SE signals from the PSi composites rods is an interesting phenomenon, and such nanocomposites may be used for future research on light amplification.

Investigation of Different Colloidal Porous Silicon Solutions and Their Composite Solid Matrix Rods by Optical Techniques

NASA Astrophysics Data System (ADS)

Khan, M. Naziruddin; Aldalbahi, Ali; Almohammedi, Abdullah

2018-07-01

Colloidal porous silicon (PSi) in different solvents was synthesized by simple chemical etching. Colloidal solutions were then prepared using different quantities of silicon wafer pieces (Pcs) and chloroplatinic (Pt) acid in catalyst solution. The effect on the properties of the colloidal solutions and composite rods were investigated using various optical characterization techniques. Absorption and photoluminescence (PL) intensity of the colloidal PSi solutions are observed to depend on the quantity of wafer Pcs, the Pt-solution, and the porosity formation on the wafer surface. The morphological structure of the PSi in a solvent and the solid-rod environments were studied using field-emission scanning electron microscopy (FE-SEM) and were observed to have different structures. A mono-oriented structure of PSi exists in tetrahydrofuran, which has stereo orientation in dioxane and dimethylsulfoxide (approximately 5-8 nm as confirmed using high resolution transmission electron microscopy). Subsequently, some colloidal PSi solutions were directly embedded in three types of sol-gel-based matrices, silica, ormosils (or organically modified silica) and polymer, which easily generated solid rods. Spontaneous emission (SE) of the PSi solutions and their composite rods were examined using a high power picosecond 355 nm laser source. The emitted PL and SE signals of the colloidal PSi solutions were dependent on the Pt volume, nature of the solvent, quantity of Si wafer piece, and pumping energy. The response of SE signals from the PSi composites rods is an interesting phenomenon, and such nanocomposites may be used for future research on light amplification.

Transparent electrodes in silicon heterojunction solar cells: Influence on contact passivation

DOE PAGES

Tomasi, Andrea; Sahli, Florent; Seif, Johannes Peter; ...

2015-10-26

Charge carrier collection in silicon heterojunction solar cells occurs via intrinsic/doped hydrogenated amorphous silicon layer stacks deposited on the crystalline silicon wafer surfaces. Usually, both the electron and hole collecting stacks are externally capped by an n-type transparent conductive oxide, which is primarily needed for carrier extraction. Earlier, it has been demonstrated that the mere presence of such oxides can affect the carrier recombination in the crystalline silicon absorber. Here, we present a detailed investigation of the impact of this phenomenon on both the electron and hole collecting sides, including its consequences for the operating voltages of silicon heterojunction solarmore » cells. As a result, we define guiding principles for improved passivating contact design for high-efficiency silicon solar cells.« less

Transparent electrodes in silicon heterojunction solar cells: Influence on contact passivation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tomasi, Andrea; Sahli, Florent; Seif, Johannes Peter

Charge carrier collection in silicon heterojunction solar cells occurs via intrinsic/doped hydrogenated amorphous silicon layer stacks deposited on the crystalline silicon wafer surfaces. Usually, both the electron and hole collecting stacks are externally capped by an n-type transparent conductive oxide, which is primarily needed for carrier extraction. Earlier, it has been demonstrated that the mere presence of such oxides can affect the carrier recombination in the crystalline silicon absorber. Here, we present a detailed investigation of the impact of this phenomenon on both the electron and hole collecting sides, including its consequences for the operating voltages of silicon heterojunction solarmore » cells. As a result, we define guiding principles for improved passivating contact design for high-efficiency silicon solar cells.« less

Annealing optimization of hydrogenated amorphous silicon suboxide film for solar cell application

NASA Astrophysics Data System (ADS)

Guangzhi, Jia; Honggang, Liu; Hudong, Chang

2011-05-01

We investigate a passivation scheme using hydrogenated amorphous silicon suboxide (a-SiOx:H) film for industrial solar cell application. The a-SiOx:H films were deposited using plasma-enhanced chemical vapor deposition (PECVD) by decomposing nitrous oxide, helium and silane at a substrate temperature of around 250 °C. An extensive study has been carried out on the effect of thermal annealing on carrier lifetime and surface recombination velocity, which affect the final output of the solar cell. Minority carrier lifetimes for the deposited a-SiOx:H films without and with the thermal annealing on 4 Ω·cm p-type float-zone silicon wafers are 270 μs and 670 μs, respectively, correlating to surface recombination velocities of 70 cm/s and 30 cm/s. Optical analysis has revealed a distinct decrease of blue light absorption in the a-SiOx:H films compared to the commonly used intrinsic amorphous silicon passivation used in solar cells. This paper also reports that the low cost and high quality passivation fabrication sequences employed in this study are suitable for industrial processes.

Fabrication of optical filters using multilayered porous silicon

NASA Astrophysics Data System (ADS)

Gaber, Noha; Khalil, Diaa; Shaarawi, Amr

2011-02-01

In this work we describe a method for fabricating optical filters using multilayered porous silicon 1D photonic structure. An electrochemical cell is constructed to control the porosity of variable layers in p-type Si wafers. Porous silicon multilayered structures are formed of λ/4 (or multiples) thin films that construct optical interference filters. By changing the anodizing current density of the cell during fabrication, different porosities can be obtained as the optical refractive index is a direct function of the layer porosity. To determine the morphology, the wavelength dependent refractive index n and absorption coefficient α, first, porous silicon free standing mono-layers have been fabricated at different conditions and characterized in the near infrared region (from 1000 to 2500nm). Large difference in refractive index (between 1.6 and 2.6) is obtained. Subsequently, multilayer structures have been fabricated and tested. Their spectral response has been measured and it shows good agreement with numerical simulations. A technique based on inserting etching breaks is adopted to ensure the depth homogeneity. The effect of differing etching/break times on the reproducibility of the filters is studied.

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

NASA Technical Reports Server (NTRS)

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Cohesive zone model for direct silicon wafer bonding

NASA Astrophysics Data System (ADS)

Kubair, D. V.; Spearing, S. M.

2007-05-01

Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

Process Research on Polycrystalline Silicon Material (PROPSM)

NASA Technical Reports Server (NTRS)

Culik, J. S.

1982-01-01

The investigation of the performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was continued by fabricating a set of minicell wafers on a selection of 10 cm x 10 cm wafers. A minicell wafer consists of an array of small (approximately 0.2 sq cm in area) photodiodes which are isolated from one another by a mesa structure. The junction capacitance of each minicell was used to obtain the dopant concentration, and therefore the resistivity, as a function of position across each wafer. The results indicate that there is no significant variation in resistivity with position for any of the polycrystalline wafers, whether Semix or Wacker. However, the resistivity of Semix brick 71-01E did decrease slightly from bottom to top.

Preparation and Thermal Characterization of Annealed Gold Coated Porous Silicon

PubMed Central

Behzad, Kasra; Mat Yunus, Wan Mahmood; Talib, Zainal Abidin; Zakaria, Azmi; Bahrami, Afarin

2012-01-01

Porous silicon (PSi) layers were formed on a p-type Si wafer. Six samples were anodised electrically with a 30 mA/cm2 fixed current density for different etching times. The samples were coated with a 50–60 nm gold layer and annealed at different temperatures under Ar flow. The morphology of the layers, before and after annealing, formed by this method was investigated by scanning electron microscopy (SEM). Photoacoustic spectroscopy (PAS) measurements were carried out to measure the thermal diffusivity (TD) of the PSi and Au/PSi samples. For the Au/PSi samples, the thermal diffusivity was measured before and after annealing to study the effect of annealing. Also to study the aging effect, a comparison was made between freshly annealed samples and samples 30 days after annealing. PMID:28817037

Tracking Efficiency And Charge Sharing of 3D Silicon Sensors at Different Angles in a 1.4T Magnetic Field

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gjersdal, H.; /Oslo U.; Bolle, E.

2012-05-07

A 3D silicon sensor fabricated at Stanford with electrodes penetrating throughout the entire silicon wafer and with active edges was tested in a 1.4 T magnetic field with a 180 GeV/c pion beam at the CERN SPS in May 2009. The device under test was bump-bonded to the ATLAS pixel FE-I3 readout electronics chip. Three readout electrodes were used to cover the 400 {micro}m long pixel side, this resulting in a p-n inter-electrode distance of {approx} 71 {micro}m. Its behavior was confronted with a planar sensor of the type presently installed in the ATLAS inner tracker. Time over threshold, chargemore » sharing and tracking efficiency data were collected at zero and 15{sup o} angles with and without magnetic field. The latest is the angular configuration expected for the modules of the Insertable B-Layer (IBL) currently under study for the LHC phase 1 upgrade expected in 2014.« less

Roll up nanowire battery from silicon chips

PubMed Central

Vlad, Alexandru; Reddy, Arava Leela Mohana; Ajayan, Anakha; Singh, Neelam; Gohy, Jean-François; Melinte, Sorin; Ajayan, Pulickel M.

2012-01-01

Here we report an approach to roll out Li-ion battery components from silicon chips by a continuous and repeatable etch-infiltrate-peel cycle. Vertically aligned silicon nanowires etched from recycled silicon wafers are captured in a polymer matrix that operates as Li+ gel-electrolyte and electrode separator and peeled off to make multiple battery devices out of a single wafer. Porous, electrically interconnected copper nanoshells are conformally deposited around the silicon nanowires to stabilize the electrodes over extended cycles and provide efficient current collection. Using the above developed process we demonstrate an operational full cell 3.4 V lithium-polymer silicon nanowire (LIPOSIL) battery which is mechanically flexible and scalable to large dimensions. PMID:22949696

Fabrication of silicon films from patterned protruded seeds

NASA Astrophysics Data System (ADS)

Zeng, Huang; Zhang, Wei; Li, Jizhou; Wang, Cong; Yang, Hui; Chen, Yigang; Chen, Xiaoyuan; Liu, Dongfang

2017-05-01

Thin, flexible silicon crystals are starting up applications such as light-weighted flexible solar cells, SOI, flexible IC chips, 3D ICs imagers and 3D CMOS imagers on the demand of high performance with low cost. Kerfless wafering technology by direct conversion of source gases into mono-crystalline wafers on reusable substrates is highly cost-effective and feedstock-effective route to cheap wafers with the thickness down to several microns. Here we show a prototype for direct conversion of silicon source gases to wafers by using the substrate with protruded seeds. A reliable and controllable method of wafer-scaled preparation of protruded seed patterns has been developed by filling liquid wax into a rod array as the mask for the selective removal of oxide layer on the rod head. Selectively epitaxial growth is performed on the protruded seeds, and the voidless film is formed by the merging of neighboring seeds through growing. And structured hollows are formed between the grown film and the substrate, which would offer the transferability of the grown film and the reusability of the protruded seeds.

A silicon technology for millimeter-wave monolithic circuits

NASA Astrophysics Data System (ADS)

Stabile, P. J.; Rosen, A.

1984-12-01

A silicon millimeter-wave integrated-circuit (SIMMWIC) technology that includes high-energy ion implantation and pulsed-laser annealing, secondary ion mass spectrometry (SIMS) profile diagnostics, and novel wafer thinning has been developed. This technology has been applied to a SIMMWIC single-pole single-throw (SPST) switch and to IMPATT and p-i-n diode fabrication schemes. Thus, the SIMMWIC technology is a proven base for monolithic millimeter-wave sources and control circuit applications.

Fabrication of spherical microlens array by combining lapping on silicon wafer and rapid surface molding

NASA Astrophysics Data System (ADS)

Liu, Xiaohua; Zhou, Tianfeng; Zhang, Lin; Zhou, Wenchen; Yu, Jianfeng; Lee, L. James; Yi, Allen Y.

2018-07-01

Silicon is a promising mold material for compression molding because of its properties of hardness and abrasion resistance. Silicon wafers with carbide-bonded graphene coating and micro-patterns were evaluated as molds for the fabrication of microlens arrays. This study presents an efficient but flexible manufacturing method for microlens arrays that combines a lapping method and a rapid molding procedure. Unlike conventional processes for microstructures on silicon wafers, such as diamond machining and photolithography, this research demonstrates a unique approach by employing precision steel balls and diamond slurries to create microlenses with accurate geometry. The feasibility of this method was demonstrated by the fabrication of several microlens arrays with different aperture sizes and pitches on silicon molds. The geometrical accuracy and surface roughness of the microlens arrays were measured using an optical profiler. The measurement results indicated good agreement with the optical profile of the design. The silicon molds were then used to copy the microstructures onto polymer substrates. The uniformity and quality of the samples molded through rapid surface molding were also assessed and statistically quantified. To further evaluate the optical functionality of the molded microlens arrays, the focal lengths of the microlens arrays were measured using a simple optical setup. The measurements showed that the microlens arrays molded in this research were compatible with conventional manufacturing methods. This research demonstrated an alternative low-cost and efficient method for microstructure fabrication on silicon wafers, together with the follow-up optical molding processes.

Fabrication and Modification of Nanoporous Silicon Particles

NASA Technical Reports Server (NTRS)

Ferrari, Mauro; Liu, Xuewu

2010-01-01

Silicon-based nanoporous particles as biodegradable drug carriers are advantageous in permeation, controlled release, and targeting. The use of biodegradable nanoporous silicon and silicon dioxide, with proper surface treatments, allows sustained drug release within the target site over a period of days, or even weeks, due to selective surface coating. A variety of surface treatment protocols are available for silicon-based particles to be stabilized, functionalized, or modified as required. Coated polyethylene glycol (PEG) chains showed the effective depression of both plasma protein adsorption and cell attachment to the modified surfaces, as well as the advantage of long circulating. Porous silicon particles are micromachined by lithography. Compared to the synthesis route of the nanomaterials, the advantages include: (1) the capability to make different shapes, not only spherical particles but also square, rectangular, or ellipse cross sections, etc.; (2) the capability for very precise dimension control; (3) the capacity for porosity and pore profile control; and (4) allowance of complex surface modification. The particle patterns as small as 60 nm can be fabricated using the state-of-the-art photolithography. The pores in silicon can be fabricated by exposing the silicon in an HF/ethanol solution and then subjecting the pores to an electrical current. The size and shape of the pores inside silicon can be adjusted by the doping of the silicon, electrical current application, the composition of the electrolyte solution, and etching time. The surface of the silicon particles can be modified by many means to provide targeted delivery and on-site permanence for extended release. Multiple active agents can be co-loaded into the particles. Because the surface modification of particles can be done on wafers before the mechanical release, asymmetrical surface modification is feasible. Starting from silicon wafers, a treatment, such as KOH dipping or reactive ion etching (RIE), may be applied to make the surface rough. This helps remove the nucleation layer. A protective layer is then deposited on the wafer. The protective layer, such as silicon nitride film or photoresist film, protects the wafer from electrochemical etching in an HF-based solution. A lithography technique is applied to pattern the particles onto the protective film. The undesired area of the protective film is removed, and the protective film on the back side of the wafer is also removed. Then the pattern is exposed to HF/surfactant solution, and a larger DC electrical current is applied to the wafers for a selected time. This step removes the nucleation layer. Then a DC current is applied to generate the nanopores. Next, a large electrical current is applied to generate a release layer. The particles are mechanically suspended in the solvent and collected by filtration or centrifuge.

Silicon release coating, method of making same, and method of using same

DOEpatents

Jonczyk, Ralf [Wilmington, DE

2011-11-22

A method of making a release coating includes the following steps: forming a mixture that includes (a) solid components comprising (i) 20-99% silicon by weight and (ii) 1-80% silicon nitride by weight and (b) a solvent; applying the mixture to an inner portion of a crucible or graphite board adapted to form an ingot or wafer comprising silicon; and annealing the mixture in a nitrogen atmosphere at a temperature ranging from 1000 to 2000.degree. C. The invention may also relate to release coatings and methods of making a silicon ingot or wafer including the use of a release coating.

Critical technology limits to silicon material and sheet production

NASA Technical Reports Server (NTRS)

Leipold, M. H.

1982-01-01

Earlier studies have indicated that expenditures related to the preparation of high-purity silicon and its conversion to silicon sheet represent from 40 to 52 percent of the cost of the entire panel. The present investigation is concerned with the elements which were selected for study in connection with the Flat-Plate Solar Array (FSA) Project. The first of two technologies which are being developed within the FSA Project involves the conversion of metallurgical-grade silicon through a silane purification process to silicon particles. The second is concerned with the conversion of trichlorosilane to dichlorosilane, and the subsequent production of silicon using modified rod reactors of the Siemens type. With respect to silicon sheet preparation, efforts have been focused both on the preparation of ingots, followed by wafering, and the direct crystallization of molten silicon into a ribbon or film.

Surface property modification of silicon

NASA Technical Reports Server (NTRS)

Danyluk, S.

1984-01-01

The main emphasis of this work has been to determine the wear rate of silicon in fluid environments and the parameters that influence wear. Three tests were carried out on single crystal Czochralski silicon wafers: circular and linear multiple-scratch tests in fluids by a pyramidal diamond simulated fixed-particle abrasion; microhardness and three-point bend tests were used to determine the hardness and fracture toughness of abraded silicon and the extent of damage induced by abrasion. The wear rate of (100) and (111) n and p-type single crystal Cz silicon abraded by a pyramidal diamond in ethanol, methanol, acetone and de-ionized water was determined by measuring the cross-sectional areas of grooves of the circular and linear multiple-scratch tests. The wear rate depends on the loads on the diamond and is highest for ethanol and lowest for de-ionized water. The surface morphology of the grooves showed lateral and median cracks as well as a plastically deformed region. The hardness and fracture toughness are critical parameters that influence the wear rate. Microhardness tests were conducted to determine the hardness as influenced by fluids. Median cracks and the damage zone surrounding the indentations were also related to the fluid properties.

Slicing of Silicon into Sheet Material: Silicon Sheet Growth Development for the Large Area Silicon Sheet Task of the Low Cost Silicon Solar Array Project

NASA Technical Reports Server (NTRS)

Fleming, J. R.

1979-01-01

Testing of low cost low suspension power slurry vehicles is presented. Cutting oils are unlikely to work, but a mineral oil with additives should be workable. Two different abrasives were tested. A cheaper silicon carbide from Norton gave excellent results except for excessive kerf loss: the particles were too big. An abrasive treated for lubricity showed no lubricity improvement in mineral oil vehicle. The bounce fixture was tested for the first time under constant cut rate conditions (rather than constant force). Although the cut was not completed before the blades broke, the blade lifetime of thin (100 micrometer) blades was 120 times the lifetime without the fixture. The large prototype saw completed a successful run, producing 90% cutting yield (849 wafers) at 20 wafers/cm. Although inexperience with large numbers of wafers caused cleaning breakage to reduce this yield to 74%, the yield was high enough that the concept of the large saw is proven workable.

Detecting Fermi-level shifts by Auger electron spectroscopy in Si and GaAs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Debehets, J.; Homm, P.; Menghini, M.

In this study, changes in surface Fermi-level of Si and GaAs, caused by doping and cleaning, are investigated by Auger electron spectroscopy. Based on the Auger voltage contrast, we compared the Auger transition peak energy but with higher accuracy by using a more accurate analyzer and an improved peak position determination method. For silicon, a peak shift as large as 0.46 eV was detected when comparing a cleaned p-type and n-type wafer, which corresponds rather well with the theoretical difference in Fermi-levels. If no cleaning was applied, the peak position did not differ significantly for both wafer types, indicating Fermi-levelmore » pinning in the band gap. For GaAs, peak shifts were detected after cleaning with HF and (NH 4) 2S-solutions in an inert atmosphere (N 2-gas). Although the (NH 4) 2S-cleaning in N 2 is very efficient in removing the oxygen from the surface, the observed Ga- and As-peak shifts are smaller than those obtained after the HF-cleaning. It is shown that the magnitude of the shift is related to the surface composition. After Si-deposition on the (NH 4) 2S-cleaned surface, the Fermi-level shifts back to a similar position as observed for an as-received wafer, indicating that this combination is not successful in unpinning the Fermi-level of GaAs.« less

Detecting Fermi-level shifts by Auger electron spectroscopy in Si and GaAs

DOE PAGES

Debehets, J.; Homm, P.; Menghini, M.; ...

2018-01-12

In this study, changes in surface Fermi-level of Si and GaAs, caused by doping and cleaning, are investigated by Auger electron spectroscopy. Based on the Auger voltage contrast, we compared the Auger transition peak energy but with higher accuracy by using a more accurate analyzer and an improved peak position determination method. For silicon, a peak shift as large as 0.46 eV was detected when comparing a cleaned p-type and n-type wafer, which corresponds rather well with the theoretical difference in Fermi-levels. If no cleaning was applied, the peak position did not differ significantly for both wafer types, indicating Fermi-levelmore » pinning in the band gap. For GaAs, peak shifts were detected after cleaning with HF and (NH 4) 2S-solutions in an inert atmosphere (N 2-gas). Although the (NH 4) 2S-cleaning in N 2 is very efficient in removing the oxygen from the surface, the observed Ga- and As-peak shifts are smaller than those obtained after the HF-cleaning. It is shown that the magnitude of the shift is related to the surface composition. After Si-deposition on the (NH 4) 2S-cleaned surface, the Fermi-level shifts back to a similar position as observed for an as-received wafer, indicating that this combination is not successful in unpinning the Fermi-level of GaAs.« less

Recent Results on Gridpix Detectors:. AN Integrated Micromegas Grid and a Micromegas Ageing Test

NASA Astrophysics Data System (ADS)

Chefdeville, M.; Aarts, A.; van der Graaf, H.; van der Putten, S.

2006-04-01

A new gas-filled detector combining a Micromegas with a CMOS pixel chip has been recently tested. A procedure to integrate the Micromegas grid onto silicon wafers (‘wafer post processing’) has been developed. We aim to eventually integrate the grid on top of wafers of CMOS pixel chips. The first part of this contribution describes an application in vertex detection (GOSSIP). Then tests of the first detector prototype of a grid integrated on a bare silicon wafer are shown. Finally an ageing test of a Micromegas chamber is presented. After verifying the chambers' proportionality at a very high dose rates, the device was irradiated until ageing became apparent.

Development of microchannel plate x-ray optics

NASA Technical Reports Server (NTRS)

Kaaret, Philip; Chen, Andrew

1994-01-01

The goal of this research program was to develop a novel technique for focusing x-rays based on the optical system of a lobster's eye. A lobster eye employs many closely packed reflecting surfaces arranged within a spherical or cylindrical shell. These optics have two unique properties: they have unlimited fields of view and can be manufactured via replication of identical structures. Because the angular resolution is given by the ratio of the size of the individual optical elements to the focal length, optical elements with sizes on the order of one hundred microns are required to achieve good angular resolution with a compact telescope. We employed anisotropic etching of single crystal silicon wafers for the fabrication of micron-scale optical elements. This technique, commonly referred to as silicon micromachining, is based on silicon fabrication techniques developed by the microelectronics industry. An anisotropic etchant is a chemical which etches certain silicon crystal planes much more rapidly than others. Using wafers in which the slowly etched crystal planes are aligned perpendicularly to the wafer surface, it is possible to etch a pattern completely through a wafer with very little distortion. Our optics consist of rectangular pores etched completely through group of zone axes (110) oriented silicon wafers. The larger surfaces of the pores (the mirror elements) were aligned with the group of zone axes (111) planes of the crystal perpendicular to the wafer surface. We have succeeded in producing silicon lenses with a geometry suitable for 1-d focusing x-ray optics. These lenses have an aspect ratio (40:1) suitable for x-ray reflection and have very good optical surface alignment. We have developed a number of process refinements which improved the quality of the lens geometry and the repeatability of the etch process. A significant progress was made in obtaining good optical surface quality. The RMS roughness was decreased from 110 A for our initial lenses to 30 A in the final lenses. A further factor of three improvement in surface quality is required for the production of efficient x-ray optics. In addition to the silicon fabrication, an x-ray beam line was constructed at Columbia for testing the optics.

A novel ultra-planar, long-stroke and low-voltage piezoelectric micromirror

NASA Astrophysics Data System (ADS)

Bakke, Thor; Vogl, Andreas; Żero, Oleg; Tyholdt, Frode; Johansen, Ib-Rune; Wang, Dag

2010-06-01

A novel piston-type micromirror with a stroke of up to 20 µm at 20 V formed out of a silicon-on-insulator wafer with integrated piezoelectric actuators was designed, fabricated and characterized. The peak-to-valley planarity of a 2 mm diameter mirror was better than 15 nm, and tip-to-tip tilt upon actuation less than 30 nm. A resonance frequency of 9.8 kHz was measured. Analytical and finite element models were developed and compared to measurements. The design is based on a silicon-on-insulator wafer where the circular mirror is formed out of the handle silicon, thus forming a thick, highly rigid and ultra-planar mirror surface. The mirror plate is connected to a supporting frame through a membrane formed out of the device silicon layer. A piezoelectric actuator made of lead-zirconate-titanate (PZT) thin film is structured on top of the membrane, providing mirror deflection by deformation of the membrane. Two actuator designs were tested: one with a single ring and the other with a double ring providing bidirectional movement of the mirror. The fabricated mirrors were characterized by white light interferometry to determine the static and temporal response as well as mirror planarity.

High-aspect ratio micro- and nanostructures enabled by photo-electrochemical etching for sensing and energy harvesting applications

NASA Astrophysics Data System (ADS)

Alhalaili, Badriyah; Dryden, Daniel M.; Vidu, Ruxandra; Ghandiparsi, Soroush; Cansizoglu, Hilal; Gao, Yang; Saif Islam, M.

2018-03-01

Photo-electrochemical (PEC) etching can produce high-aspect ratio features, such as pillars and holes, with high anisotropy and selectivity, while avoiding the surface and sidewall damage caused by traditional deep reactive ion etching (DRIE) or inductively coupled plasma (ICP) RIE. Plasma-based techniques lead to the formation of dangling bonds, surface traps, carrier leakage paths, and recombination centers. In pursuit of effective PEC etching, we demonstrate an optical system using long wavelength (λ = 975 nm) infra-red (IR) illumination from a high-power laser (1-10 W) to control the PEC etching process in n-type silicon. The silicon wafer surface was patterned with notches through a lithography process and KOH etching. Then, PEC etching was introduced by illuminating the backside of the silicon wafer to enhance depth, resulting in high-aspect ratio structures. The effect of the PEC etching process was optimized by varying light intensities and electrolyte concentrations. This work was focused on determining and optimizing this PEC etching technique on silicon, with the goal of expanding the method to a variety of materials including GaN and SiC that are used in designing optoelectronic and electronic devices, sensors and energy harvesting devices.

Stress modeling of microdiaphragm pressure sensors

NASA Technical Reports Server (NTRS)

Tack, P. C.; Busta, H. H.

1986-01-01

A finite element program analysis was used to model the stress distribution of two monocrystalline silicon diaphragm pressure sensors. One configuration consists of an anisotropically backside etched diaphragm into a 250 micron thick, (100) oriented, silicon wafer. The diaphragm and total chip dimensions are given. The device is rigidly clamped on the back to a support substrate. Another configuration consists of a monocrystalline, (100), microdiaphragm which is formed on top of the wafer and whose area is reduced by a factor of 25 over the first configuration. The diaphragm is rigidly clamped to the silicon wafer. The stresses were calculated at a gauge pressure of 300 mm Hg and used to estimate the piezoresistive responses of resistor elements which were placed parallel and perpendicular near the diaphragm edges.

PbS-PbSe IR detector arrays

NASA Technical Reports Server (NTRS)

Barrett, John R. (Inventor)

1986-01-01

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chipping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Two different ways for waveguides and optoelectronics components on top of C-MOS

NASA Astrophysics Data System (ADS)

Fedeli, J. M.; Jeannot, S.; Kostrzewa, M.; Di Cioccio, L.; Jousseaume, V.; Orobtchouk, R.; Maury, P.; Zussy, M.

2006-02-01

While fabrication of photonic components at the wafer level is a long standing goal of integrated optics, new applications such as optical interconnects are introducing new challenges for waveguides and optoelectronic component fabrication. Indeed, global interconnects are expected to face severe limitations in the near future. To face this problem, optical links on top of a CMOS circuits could be an alternative. The critical points to perform an optical link on a chip are firstly the realization of compact passive optical distribution and secondly the report of optoelectronic components for the sources and detectors. This paper presents two different approaches for the integration of both waveguides and optoelectronic components. In a first "total bonding" approach, waveguides have been elaborated using classical "Silicon On Insulators" technology and then reported using molecular bonding on top off Si wafers. The S0I substrate was then chemically etched, after what InP dies were moleculary bonded on top of the waveguides. With this approach, optical components with low loses and a good equilibrium are demonsrated. Using molecular bonding, InP dies were reported with no degradation of the optoelectronic properties of the films. In a second approach, using PECVD silicon nitride or amorphous silicon coupled to PECVD silicon oxide, basic optical components are demonstrated. This low temperature technology is compatible with a microelectronic Back End process, allowing an integration of the waveguides directly on top of CMOS circuits. InP dies can then be bonded on top of the waveguides.

Boron Partitioning Coefficient above Unity in Laser Crystallized Silicon.

PubMed

Lill, Patrick C; Dahlinger, Morris; Köhler, Jürgen R

2017-02-16

Boron pile-up at the maximum melt depth for laser melt annealing of implanted silicon has been reported in numerous papers. The present contribution examines the boron accumulation in a laser doping setting, without dopants initially incorporated in the silicon wafer. Our numerical simulation models laser-induced melting as well as dopant diffusion, and excellently reproduces the secondary ion mass spectroscopy-measured boron profiles. We determine a partitioning coefficient k p above unity with k p = 1 . 25 ± 0 . 05 and thermally-activated diffusivity D B , with a value D B ( 1687 K ) = ( 3 . 53 ± 0 . 44 ) × 10 - 4 cm 2 ·s - 1 of boron in liquid silicon. For similar laser parameters and process conditions, our model predicts the anticipated boron profile of a laser doping experiment.

Method for fabricating an ultra-low expansion mask blank having a crystalline silicon layer

DOEpatents

Cardinale, Gregory F.

2002-01-01

A method for fabricating masks for extreme ultraviolet lithography (EUVL) using Ultra-Low Expansion (ULE) substrates and crystalline silicon. ULE substrates are required for the necessary thermal management in EUVL mask blanks, and defect detection and classification have been obtained using crystalline silicon substrate materials. Thus, this method provides the advantages for both the ULE substrate and the crystalline silicon in an Extreme Ultra-Violet (EUV) mask blank. The method is carried out by bonding a crystalline silicon wafer or member to a ULE wafer or substrate and thinning the silicon to produce a 5-10 .mu.m thick crystalline silicon layer on the surface of the ULE substrate. The thinning of the crystalline silicon may be carried out, for example, by chemical mechanical polishing and if necessary or desired, oxidizing the silicon followed by etching to the desired thickness of the silicon.

Micro/nano electro mechanical systems for practical applications

NASA Astrophysics Data System (ADS)

Esashi, Masayoshi

2009-09-01

Silicon MEMS as electrostatically levitated rotational gyroscope, 2D optical scanner and wafer level packaged devices as integrated capacitive pressure sensor and MEMS switch are described. MEMS which use non-silicon materials as diamond, PZT, conductive polymer, CNT (carbon nano tube), LTCC with electrical feedthrough, SiC (silicon carbide) and LiNbO3 for multi-probe data storage, multi-column electron beam lithography system, probe card for wafer-level burn-in test, mould for glass press moulding and SAW wireless passive sensor respectively are also described.

Etching Selectivity of Cr, Fe and Ni Masks on Si & SiO2 Wafers

NASA Astrophysics Data System (ADS)

Garcia, Jorge; Lowndes, Douglas H.

2000-10-01

During this Summer 2000 I joined the Semiconductors and Thin Films group led by Dr. Douglas H. Lowndes at Oak Ridge National Laboratory’s Solid State Division. Our objective was to evaluate the selectivity that Trifluoromethane (CHF3), and Sulfur Hexafluoride (SF6) plasmas have for Si, SiO2 wafers and the Ni, Cr, and Fe masks; being this etching selectivity the ratio of the etching rates of the plasmas for each of the materials. We made use of Silicon and Silicon Dioxide-coated wafers that have Fe, Cr or Ni masks. In the semiconductor field, metal layers are often used as masks to protect layers underneath during processing steps; when these wafers are taken to the dry etching process, both the wafer and the mask layers’ thickness are reduced.

Spatial distribution of structural defects in Cz-seeded directionally solidified silicon ingots: An etch pit study

NASA Astrophysics Data System (ADS)

Lantreibecq, A.; Legros, M.; Plassat, N.; Monchoux, J. P.; Pihan, E.

2018-02-01

The PV properties of wafers processed from Cz-seeded directionally solidified silicon ingots suffer from variable structural defects. In this study, we draw an overview on the types of structural defects encountered in the specific case of full 〈1 0 0〉 oriented growth. We found micro twins, background dislocations, and subgrains boundaries. We discuss the possible links between thermomechanical stresses and growth processes with spatial evolution of both background dislocation densities and subgrain boundaries length.

Mechanical properties of silicon in subsurface damage layer from nano-grinding studied by atomistic simulation

NASA Astrophysics Data System (ADS)

Zhang, Zhiwei; Chen, Pei; Qin, Fei; An, Tong; Yu, Huiping

2018-05-01

Ultra-thin silicon wafer is highly demanded by semi-conductor industry. During wafer thinning process, the grinding technology will inevitably induce damage to the surface and subsurface of silicon wafer. To understand the mechanism of subsurface damage (SSD) layer formation and mechanical properties of SSD layer, atomistic simulation is the effective tool to perform the study, since the SSD layer is in the scale of nanometer and hardly to be separated from underneath undamaged silicon. This paper is devoted to understand the formation of SSD layer, and the difference between mechanical properties of damaged silicon in SSD layer and ideal silicon. With the atomistic model, the nano-grinding process could be performed between a silicon workpiece and diamond tool under different grinding speed. To reach a thinnest SSD layer, nano-grinding speed will be optimized in the range of 50-400 m/s. Mechanical properties of six damaged silicon workpieces with different depths of cut will be studied. The SSD layer from each workpiece will be isolated, and a quasi-static tensile test is simulated to perform on the isolated SSD layer. The obtained stress-strain curve is an illustration of overall mechanical properties of SSD layer. By comparing the stress-strain curves of damaged silicon and ideal silicon, a degradation of Young's modulus, ultimate tensile strength (UTS), and strain at fracture is observed.

High-alignment-accuracy transfer printing of passive silicon waveguide structures.

PubMed

Ye, Nan; Muliuk, Grigorij; Trindade, Antonio Jose; Bower, Chris; Zhang, Jing; Uvin, Sarah; Van Thourhout, Dries; Roelkens, Gunther

2018-01-22

We demonstrate the transfer printing of passive silicon devices on a silicon-on-insulator target waveguide wafer. Adiabatic taper structures and directional coupler structures were designed for 1310 nm and 1600 nm wavelength coupling tolerant for ± 1 µm misalignment. The release of silicon devices from the silicon substrate was realized by underetching the buried oxide layer while protecting the back-end stack. Devices were successfully picked by a PDMS stamp, by breaking the tethers that kept the silicon coupons in place on the source substrate, and printed with high alignment accuracy on a silicon photonic target wafer. Coupling losses of -1.5 +/- 0.5 dB for the adiabatic taper at 1310 nm wavelength and -0.5 +/- 0.5 dB for the directional coupler at 1600 nm wavelength are obtained.

Porous Silicon Covered with Silver Nanoparticles as Surface-Enhanced Raman Scattering (SERS) Substrate for Ultra-Low Concentration Detection.

PubMed

Kosović, Marin; Balarin, Maja; Ivanda, Mile; Đerek, Vedran; Marciuš, Marijan; Ristić, Mira; Gamulin, Ozren

2015-12-01

Microporous and macro-mesoporous silicon templates for surface-enhanced Raman scattering (SERS) substrates were produced by anodization of low doped p-type silicon wafers. By immersion plating in AgNO3, the templates were covered with silver metallic film consisting of different silver nanostructures. Scanning electron microscopy (SEM) micrographs of these SERS substrates showed diverse morphology with significant difference in an average size and size distribution of silver nanoparticles. Ultraviolet-visible-near-infrared (UV-Vis-NIR) reflection spectroscopy showed plasmonic absorption at 398 and 469 nm, which is in accordance with the SEM findings. The activity of the SERS substrates was tested using rhodamine 6G (R6G) dye molecules and 514.5 nm laser excitation. Contrary to the microporous silicon template, the SERS substrate prepared from macro-mesoporous silicon template showed significantly broader size distribution of irregular silver nanoparticles as well as localized surface plasmon resonance closer to excitation laser wavelength. Such silver morphology has high SERS sensitivity that enables ultralow concentration detection of R6G dye molecules up to 10(-15) M. To our knowledge, this is the lowest concentration detected of R6G dye molecules on porous silicon-based SERS substrates, which might even indicate possible single molecule detection.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Thi, Trinh Cham, E-mail: s1240009@jaist.ac.jp; Koyama, Koichi; Ohdaira, Keisuke

We improve the passivation property of n-type crystalline silicon (c-Si) surface passivated with a catalytic chemical vapor deposited (Cat-CVD) Si nitride (SiN{sub x}) film by inserting a phosphorous (P)-doped layer formed by exposing c-Si surface to P radicals generated by the catalytic cracking of PH{sub 3} molecules (Cat-doping). An extremely low surface recombination velocity (SRV) of 2 cm/s can be achieved for 2.5 Ω cm n-type (100) floating-zone Si wafers passivated with SiN{sub x}/P Cat-doped layers, both prepared in Cat-CVD systems. Compared with the case of only SiN{sub x} passivated layers, SRV decreases from 5 cm/s to 2 cm/s. The decrease in SRVmore » is the result of field effect created by activated P atoms (donors) in a shallow P Cat-doped layer. Annealing process plays an important role in improving the passivation quality of SiN{sub x} films. The outstanding results obtained imply that SiN{sub x}/P Cat-doped layers can be used as promising passivation layers in high-efficiency n-type c-Si solar cells.« less

Bulk lifetime characterization of corona charged silicon wafers with high resistivity by means of microwave detected photoconductivity

NASA Astrophysics Data System (ADS)

Engst, C. R.; Rommel, M.; Bscheid, C.; Eisele, I.; Kutter, C.

2017-12-01

Minority carrier lifetime (lifetime) measurements are performed on corona-charged silicon wafers by means of Microwave Detected Photoconductivity (MDP). The corona charge is deposited on the front and back sides of oxidized wafers in order to adjust accumulation conditions. Once accumulation is established, interface recombination is suppressed and bulk lifetimes are obtained. Neither contacts nor non-CMOS compatible preparation techniques are required in order to achieve accumulation conditions, which makes the method ideally suited for inline characterization. The novel approach, termed ChargedMDP (CMDP), is used to investigate neutron transmutation doped (NTD) float zone silicon with resistivities ranging from 6.0 to 8.2 kΩ cm. The bulk properties of 150 mm NTD wafers are analyzed in detail by performing measurements of the carrier lifetime and the steady-state photoconductivity at various injection levels. The results are compared with MDP measurements of uncharged wafers as well as to the established charged microwave detected Photoconductance Decay (charge-PCD) method. Besides analyzing whole wafers, CMDP measurements are performed on oxide test-structures on a patterned wafer. Finally, the oxide properties are characterized by means of charge-PCD as well as capacitance-voltage measurements. With CMDP, average bulk lifetimes up to 33.1 ms are measured, whereby significant variations are observed among wafers, which are produced out of the same ingot but oxidized in different furnaces. The observed lifetime variations are assumed to be caused by contaminations, which are introduced during the oxidation process. The results obtained by CMDP were neither accessible by means of conventional MDP measurements of uncharged wafers nor with the established charge-PCD method.

Silicon solar cell process development, fabrication and analysis

NASA Technical Reports Server (NTRS)

Yoo, H. I.; Iles, P. A.; Leung, D. C.

1981-01-01

Solar cells were fabricated from EFG ribbons dendritic webs, cast ingots by heat exchanger method, and cast ingots by ubiquitous crystallization process. Baseline and other process variations were applied to fabricate solar cells. EFG ribbons grown in a carbon-containing gas atmosphere showed significant improvement in silicon quality. Baseline solar cells from dendritic webs of various runs indicated that the quality of the webs under investigation was not as good as the conventional CZ silicon, showing an average minority carrier diffusion length of about 60 um versus 120 um of CZ wafers. Detail evaluation of large cast ingots by HEM showed ingot reproducibility problems from run to run and uniformity problems of sheet quality within an ingot. Initial evaluation of the wafers prepared from the cast polycrystalline ingots by UCP suggested that the quality of the wafers from this process is considerably lower than the conventional CZ wafers. Overall performance was relatively uniform, except for a few cells which showed shunting problems caused by inclusions.

Three-dimensional conformal graphene microstructure for flexible and highly sensitive electronic skin

NASA Astrophysics Data System (ADS)

Yang, Jun; Ran, Qincui; Wei, Dapeng; Sun, Tai; Yu, Leyong; Song, Xuefen; Pu, Lichun; Shi, Haofei; Du, Chunlei

2017-03-01

We demonstrate a highly stretchable electronic skin (E-skin) based on the facile combination of microstructured graphene nanowalls (GNWs) and a polydimethylsiloxane (PDMS) substrate. The microstructure of the GNWs was endowed by conformally growing them on the unpolished silicon wafer without the aid of nanofabrication technology. Then a stamping transfer method was used to replicate the micropattern of the unpolished silicon wafer. Due to the large contact interface between the 3D graphene network and the PDMS, this type of E-skin worked under a stretching ratio of nearly 100%, and showed excellent mechanical strength and high sensitivity, with a change in relative resistance of up to 6500% and a gauge factor of 65.9 at 99.64% strain. Furthermore, the E-skin exhibited an obvious highly sensitive response to joint movement, eye movement and sound vibration, demonstrating broad potential applications in healthcare, body monitoring and wearable devices.

Catalyst for microelectromechanical systems microreactors

DOEpatents

Morse, Jeffrey D [Martinez, CA; Sopchak, David A [Livermore, CA; Upadhye, Ravindra S [Pleasanton, CA; Reynolds, John G [San Ramon, CA; Satcher, Joseph H [Patterson, CA; Gash, Alex E [Brentwood, CA

2010-06-29

A microreactor comprising a silicon wafer, a multiplicity of microchannels in the silicon wafer, and a catalyst coating the microchannels. In one embodiment the catalyst coating the microchannels comprises a nanostructured material. In another embodiment the catalyst coating the microchannels comprises an aerogel. In another embodiment the catalyst coating the microchannels comprises a solgel. In another embodiment the catalyst coating the microchannels comprises carbon nanotubes.

Catalyst for microelectromechanical systems microreactors

DOEpatents

Morse, Jeffrey D [Martinez, CA; Sopchak, David A [Livermore, CA; Upadhye, Ravindra S [Pleasanton, CA; Reynolds, John G [San Ramon, CA; Satcher, Joseph H [Patterson, CA; Gash, Alex E [Brentwood, CA

2011-11-15

A microreactor comprising a silicon wafer, a multiplicity of microchannels in the silicon wafer, and a catalyst coating the microchannels. In one embodiment the catalyst coating the microchannels comprises a nanostructured material. In another embodiment the catalyst coating the microchannels comprises an aerogel. In another embodiment the catalyst coating the microchannels comprises a solgel. In another embodiment the catalyst coating the microchannels comprises carbon nanotubes.

Dynamic Chemically Driven Dewetting, Spreading, and Self-Running of Sessile Droplets on Crystalline Silicon.

PubMed

Arscott, Steve

2016-12-06

A chemically driven dewetting effect is demonstrated using sessile droplets of dilute hydrofluoric acid on chemically oxidized silicon wafers. The dewetting occurs as the thin oxide is slowly etched by the droplet and replaced by a hydrogen-terminated surface; the result of this is a gradual increase in the contact angle of the droplet with time. The time-varying work of adhesion is calculated from the time-varying contact angle; this corresponds to the changing chemical nature of the surface during dewetting and can be modeled by the well-known logistic (sigmoid) function often used for the modeling of restricted growth, in this case, the transition from an oxidized surface to a hydrogen-terminated silicon surface. The observation of the time-varying contact angle allows one to both measure the etch rate of the silicon oxide and estimate the hydrogenation rate as a function of HF concentration and wafer type. In addition to this, at a certain HF concentration, a self-running droplet effect is observed. In contrast, on hydrogen-terminated silicon wafers, a chemically induced spreading effect is observed using sessile droplets of nitric acid. The droplet spreading can also be modeled using a logistical function, where the restricted growth is the transition from hydrogen-terminated to a chemically induced oxidized silicon surface. The chemically driven dewetting and spreading observed here add to the methods available to study dynamic wetting (e.g., the moving three-phase contact line) of sessile droplets on surfaces. By slowing down chemical kinetics of the wetting, one is able to record the changing profile of the sessile droplet with time and gather information concerning the time-varying surface chemistry. The data also indicates a chemical interface hysteresis (CIH) that is compared to contact angle hysteresis (CAH). The approach can also be used to study the chemical etching and deposition behavior of thin films using liquids by monitoring the macroscopic droplet profile and relating this to the time-varying physical and chemical interface phenomena.

Alternative Packaging for Back-Illuminated Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2009-01-01

An alternative scheme has been conceived for packaging of silicon-based back-illuminated, back-side-thinned complementary metal oxide/semiconductor (CMOS) and charge-coupled-device image-detector integrated circuits, including an associated fabrication process. This scheme and process are complementary to those described in "Making a Back-Illuminated Imager With Back-Side Connections" (NPO-42839), NASA Tech Briefs, Vol. 32, No. 7 (July 2008), page 38. To avoid misunderstanding, it should be noted that in the terminology of imaging integrated circuits, "front side" or "back side" does not necessarily refer to the side that, during operation, faces toward or away from a source of light or other object to be imaged. Instead, "front side" signifies that side of a semiconductor substrate upon which the pixel pattern and the associated semiconductor devices and metal conductor lines are initially formed during fabrication, and "back side" signifies the opposite side. If the imager is of the type called "back-illuminated," then the back side is the one that faces an object to be imaged. Initially, a back-illuminated, back-side-thinned image-detector is fabricated with its back side bonded to a silicon handle wafer. At a subsequent stage of fabrication, the front side is bonded to a glass wafer (for mechanical support) and the silicon handle wafer is etched away to expose the back side. The frontside integrated circuitry includes metal input/output contact pads, which are rendered inaccessible by the bonding of the front side to the glass wafer. Hence, one of the main problems is to make the input/output contact pads accessible from the back side, which is ultimately to be the side accessible to the external world. The present combination of an alternative packaging scheme and associated fabrication process constitute a solution of the problem.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Investigation of diffusion length distribution on polycrystalline silicon wafers via photoluminescence methods

PubMed Central

Lou, Shishu; Zhu, Huishi; Hu, Shaoxu; Zhao, Chunhua; Han, Peide

2015-01-01

Characterization of the diffusion length of solar cells in space has been widely studied using various methods, but few studies have focused on a fast, simple way to obtain the quantified diffusion length distribution on a silicon wafer. In this work, we present two different facile methods of doing this by fitting photoluminescence images taken in two different wavelength ranges or from different sides. These methods, which are based on measuring the ratio of two photoluminescence images, yield absolute values of the diffusion length and are less sensitive to the inhomogeneity of the incident laser beam. A theoretical simulation and experimental demonstration of this method are presented. The diffusion length distributions on a polycrystalline silicon wafer obtained by the two methods show good agreement. PMID:26364565

Method of fabricating a PbS-PbSe IR detector array

NASA Technical Reports Server (NTRS)

Barrett, John R. (Inventor)

1987-01-01

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chiping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Graphene barristor, a triode device with a gate-controlled Schottky barrier.

PubMed

Yang, Heejun; Heo, Jinseong; Park, Seongjun; Song, Hyun Jae; Seo, David H; Byun, Kyung-Eun; Kim, Philip; Yoo, InKyeong; Chung, Hyun-Jong; Kim, Kinam

2012-06-01

Despite several years of research into graphene electronics, sufficient on/off current ratio I(on)/I(off) in graphene transistors with conventional device structures has been impossible to obtain. We report on a three-terminal active device, a graphene variable-barrier "barristor" (GB), in which the key is an atomically sharp interface between graphene and hydrogenated silicon. Large modulation on the device current (on/off ratio of 10(5)) is achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. The absence of Fermi-level pinning at the interface allows the barrier's height to be tuned to 0.2 electron volt by adjusting graphene's work function, which results in large shifts of diode threshold voltages. Fabricating GBs on respective 150-mm wafers and combining complementary p- and n-type GBs, we demonstrate inverter and half-adder logic circuits.

Germanium photodetectors fabricated on 300 mm silicon wafers for near-infrared focal plane arrays

NASA Astrophysics Data System (ADS)

Zeller, John W.; Rouse, Caitlin; Efstathiadis, Harry; Dhar, Nibir K.; Wijewarnasuriya, Priyalal; Sood, Ashok K.

2017-09-01

SiGe p-i-n photodetectors have been fabricated on 300 mm (12") diameter silicon (Si) wafers utilizing high throughput, large-area complementary metal-oxide semiconductor (CMOS) technologies. These Ge photodetectors are designed to operate in room temperature environments without cooling, and thus have potential size and cost advantages over conventional cooled infrared detectors. The two-step fabrication process for the p-i-n photodetector devices, designed to minimize the formation of defects and threading dislocations, involves low temperature epitaxial growth of a thin p+ (boron) Ge seed/buffer layer, followed by higher temperature deposition of a thicker Ge intrinsic layer. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) demonstrated uniform layer compositions with well defined layer interfaces and reduced dislocation density. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) was likewise employed to analyze the doping levels of the p+ and n+ layers. Current-voltage (I-V) measurements demonstrated that these SiGe photodetectors, when exposed to incident visible-NIR radiation, exhibited dark currents down below 1 μA and significant enhancement in photocurrent at -1 V. The zero-bias photocurrent was also relatively high, showing a minimal drop compared to that at -1 V bias.

Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers

NASA Technical Reports Server (NTRS)

Anthony, Thomas R. (Inventor)

1983-01-01

Alignment-enhancing electrically conductive feed-through paths are provided for the high-speed low-loss transfer of electrical signals between integrated circuits of a plurality of silicon-on-sapphire bodies arrayed in a stack. The alignment-enhancing feed-throughs are made by a process involving the drilling of holes through the body, double-sided sputtering, electroplating, and the filling of the holes with solder by capillary action. The alignment-enhancing feed-throughs are activated by forming a stack of wafers and remelting the solder whereupon the wafers, and the feed-through paths, are pulled into alignment by surface tension forces.

Process for the homoepitaxial growth of single-crystal silicon carbide films on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1993-01-01

The invention is a method for growing homoepitaxial films of SiC on low tilt angle vicinal (0001) SiC wafers. The invention proposes and teaches a new theoretical model for the homoepitaxial growth of SiC films on (0001) SiC substrates. The inventive method consists of preparing the growth surface of SiC wafers slightly off-axis (from less the 0.1 to 6 deg) from the (0001) plane, subjecting the growth surface to a suitable etch, and then growing the homoepitaxial film using conventional SiC growth techniques.

Electron-Beam Deposition of Superconducting Molybdenum Thin Films for the Development of Mo/Au TES X-Ray Microcalorimeter

NASA Technical Reports Server (NTRS)

Finkbeiner, Fred Michael; Adams, Joseph S.; Bandler, Simon R.; Betancour-Martinez, Gabriele L.; Brown, Ari David; Chang, Meng-Ping; Chervenak, James A.; Chiao, Meng P.; Datesman, Aaron; Eckart, Megan E.;

High Temperature Propulsion System Structural Seals for Future Space Launch Vehicles

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H., Jr.; Steinetz, Bruce M.; DeMange, Jeffrey J.

2004-01-01

Durable, flexible sliding seals are required in advanced hypersonic engines to seal the perimeters of movable engine ramps for efficient, safe operation in high heat flux environments at temperatures of 2000 to 2500 F. Current seal designs do not meet the demanding requirements for future engines, so NASA s Glenn Research Center is developing advanced seals and preloading devices to overcome these shortfalls. An advanced ceramic wafer seal design and two types of seal preloading devices were evaluated in a series of compression, scrub, and flow tests. Silicon nitride wafer seals survived 2000 in. 1000 cycles) of scrubbing at 1600 F against an Inconel 625 rub surface with no chips or signs of damage. Flow rates measured for the wafers before and after scrubbing were almost identical and were up to 32 times lower than those recorded for the best braided rope seal flow blockers. Canted coil springs and silicon nitride compression springs showed promise conceptually as potential seal preloading devices to help maintain seal resiliency. A finite element model of the canted coil spring revealed that it should be possible to produce a spring out of high temperature materials for applications at 2000+ F.

High Temperature Propulsion System Structural Seals for Future Space Launch Vehicles

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H., Jr.; Steinetz, Bruce M.; DeMange, Jeffrey J.

2003-01-01

Durable, flexible sliding seals are required in advanced hypersonic engines to seal the perimeters of movable engine ramps for efficient, safe operation in high heat flux environments at temperatures of 2000 to 2500 F. Current seal designs do not meet the demanding requirements for future engines, so NASA's Glenn Research Center is developing advanced seals and preloading devices to overcome these shortfalls. An advanced ceramic wafer seal design and two types of seal preloading devices were evaluated in a series of compression, scrub, and flow tests. Silicon nitride wafer seals survived 2000 in. (1000 cycles) of scrubbing at room temperature against an Inconel 625 rub surface with no chips or signs of damage. Flow rates measured for the wafers before and after scrubbing were almost identical and were much lower than those recorded for the best braided rope seal flow blockers. Canted coil springs and silicon nitride compression springs showed promise conceptually as potential seal preloading devices to help maintain seal resiliency. A finite element model of the canted coil spring revealed that it should be possible to produce a spring out of high temperature materials for applications at 2000+ F.

High-throughput preparation of complex multi-scale patterns from block copolymer/homopolymer blend films.

PubMed

Park, Hyungmin; Kim, Jae-Up; Park, Soojin

2012-02-21

A simple, straightforward process for fabricating multi-scale micro- and nanostructured patterns from polystyrene-block-poly(2-vinylpyridine) (PS-b-P2VP)/poly(methyl methacrylate) (PMMA) homopolymer in a preferential solvent for PS and PMMA is demonstrated. When the PS-b-P2VP/PMMA blend films were spin-coated onto a silicon wafer, PS-b-P2VP micellar arrays consisting of a PS corona and a P2VP core were formed, while the PMMA macrodomains were isolated, due to the macrophase separation caused by the incompatibility between block copolymer micelles and PMMA homopolymer during the spin-coating process. With an increase of PMMA composition, the size of PMMA macrodomains increased. Moreover, the P2VP blocks have a strong interaction with a native oxide of the surface of the silicon wafer, so that the P2VP wetting layer was first formed during spin-coating, and PS nanoclusters were observed on the PMMA macrodomains beneath. Whereas when a silicon surface was modified with a PS brush layer, the PS nanoclusters underlying PMMA domains were not formed. The multi-scale patterns prepared from copolymer micelle/homopolymer blend films are used as templates for the fabrication of gold nanoparticle arrays by incorporating the gold precursor into the P2VP chains. The combination of nanostructures prepared from block copolymer micellar arrays and macrostructures induced by incompatibility between the copolymer and the homopolymer leads to the formation of complex, multi-scale surface patterns by a simple casting process. This journal is © The Royal Society of Chemistry 2012

Slicing of silicon into sheet material. Silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project

NASA Technical Reports Server (NTRS)

Holden, S. C.; Fleming, J. R.

1978-01-01

Fabrication of a prototype large capacity multiple blade slurry saw is considered. Design of the bladehead which will tension up to 1000 blades, and cut a 45 cm long silicon ingot as large as 12 cm in diameter is given. The large blade tensioning force of 270,000 kg is applied through two bolts acting on a pair of scissor toggles, significantly reducing operator set-up time. Tests with an upside-down cutting technique resulted in 100% wafering yields and the highest wafer accuracy yet experienced with MS slicing. Variations in oil and abrasives resulted only in degraded slicing results. A technique of continuous abrasive slurry separation to remove silicon debris is described.

Fine tuning of the dichroic behavior of Bragg reflectors based on anisotropically nanostructured silicon

NASA Astrophysics Data System (ADS)

Diener, J.; Künzner, N.; Kovalev, D.; Gross, E.; Koch, F.; Fujii, M.

2003-05-01

Electro-chemical etching of heavily doped, (110) oriented, p+ (boron) doped silicon wafers results in porous silicon (PSi) layers which exhibit a strong in-plane anisotropy of the refractive index (birefringence). Single- and multiple layers of anisotropically nanostructured silicon (Si) have been fabricated and studied by polarization-resolved reflection and transmission measurements. Dielectric stacks of birefringent PSi acting as distributed Bragg reflectors have two distinct reflection bands depending on the polarization of the incident linearly polarized light. This effect is caused by a three-dimensional (in plane and in-depth) variation of the refraction index. The possibility of fine tuning the two orthogonally polarized reflection bands and their spectral splitting is demonstrated.

MEMS for Practical Applications

NASA Astrophysics Data System (ADS)

Esashi, Masayoshi

Silicon MEMS as electrostatically levitated rotational gyroscopes and 2D optical scanners, and wafer level packaged devices as integrated capacitive pressure sensors and MEMS switches are described. MEMS which use non-silicon materials as LTCC with electrical feedthrough, SiC and LiNbO3 for probe cards for wafer-level burn-in test, molds for glass press molding and SAW wireless passive sensors respectively are also described.

The establishment of a production-ready manufacturing process utilizing thin silicon substrates for solar cells

NASA Technical Reports Server (NTRS)

Pryor, R. A.

1980-01-01

Three inch diameter Czochralski silicon substrates sliced directly to 5 mil, 8 mil, and 27 mil thicknesses with wire saw techniques were procured. Processing sequences incorporating either diffusion or ion implantation technologies were employed to produce n+p or n+pp+ solar cell structures. These cells were evaluated for performance, ease of fabrication, and cost effectiveness. It was determined that the use of 7 mil or even 4 mil wafers would provide near term cost reductions for solar cell manufacturers.

Sensors and Micromachined Devices for the Automotive and New Markets: The Delphi Delco Electronics MEMS Story.

NASA Astrophysics Data System (ADS)

Logsdon, James

2002-03-01

This presentation will provide a brief history of the development of MEMS products and technology, beginning with the manifold absolute pressure sensor in the late seventies through the current variety of Delphi Delco Electronics sensors available today. The technology development of micromachining from uncompensated P plus etch stops to deep reactive ion etching and the technology development of wafer level packaging from electrostatic bonding to glass frit sealing and silicon to silicon direct bonding will be reviewed.

High-Speed Scalable Silicon-MoS2 P-N Heterojunction Photodetectors

PubMed Central

Dhyani, Veerendra; Das, Samaresh

2017-01-01

Two-dimensional molybdenum disulfide (MoS2) is a promising material for ultrasensitive photodetector owing to its favourable band gap and high absorption coefficient. However, their commercial applications are limited by the lack of high quality p-n junction and large wafer scale fabrication process. A high speed Si/MoS2 p-n heterojunction photodetector with simple and CMOS compatible approach has been reported here. The large area MoS2 thin film on silicon platform has been synthesized by sulfurization of RF-sputtered MoO3 films. The fabricated molecular layers of MoS2 on silicon offers high responsivity up to 8.75 A/W (at 580 nm and 3 V bias) with ultra-fast response of 10 μsec (rise time). Transient measurements of Si/MoS2 heterojunction under the modulated light reveal that the devices can function up to 50 kHz. The Si/MoS2 heterojunction is found to be sensitive to broadband wavelengths ranging from visible to near-infrared light with maximum detectivity up to ≈1.4 × 1012 Jones (2 V bias). Reproducible low dark current and high responsivity from over 20 devices in the same wafer has been measured. Additionally, the MoS2/Si photodetectors exhibit excellent stability in ambient atmosphere. PMID:28281652

All silicon electrode photocapacitor for integrated energy storage and conversion.

PubMed

Cohn, Adam P; Erwin, William R; Share, Keith; Oakes, Landon; Westover, Andrew S; Carter, Rachel E; Bardhan, Rizia; Pint, Cary L

2015-04-08

We demonstrate a simple wafer-scale process by which an individual silicon wafer can be processed into a multifunctional platform where one side is adapted to replace platinum and enable triiodide reduction in a dye-sensitized solar cell and the other side provides on-board charge storage as an electrochemical supercapacitor. This builds upon electrochemical fabrication of dual-sided porous silicon and subsequent carbon surface passivation for silicon electrochemical stability. The utilization of this silicon multifunctional platform as a combined energy storage and conversion system yields a total device efficiency of 2.1%, where the high frequency discharge capability of the integrated supercapacitor gives promise for dynamic load-leveling operations to overcome current and voltage fluctuations during solar energy harvesting.

Radiation-tolerant imaging device

DOEpatents

Colella, N.J.; Kimbrough, J.R.

1996-11-19

A barrier at a uniform depth for an entire wafer is used to produce imaging devices less susceptible to noise pulses produced by the passage of ionizing radiation. The barrier prevents charge created in the bulk silicon of a CCD detector or a semiconductor logic or memory device from entering the collection volume of each pixel in the imaging device. The charge barrier is a physical barrier, a potential barrier, or a combination of both. The physical barrier is formed by an SiO{sub 2} insulator. The potential barrier is formed by increasing the concentration of majority carriers (holes) to combine with the electron`s generated by the ionizing radiation. A manufacturer of CCD imaging devices can produce radiation-tolerant devices by merely changing the wafer type fed into his process stream from a standard wafer to one possessing a barrier beneath its surface, thus introducing a very small added cost to his production cost. An effective barrier type is an SiO{sub 2} layer. 7 figs.

Radiation-tolerant imaging device

DOEpatents

Colella, Nicholas J.; Kimbrough, Joseph R.

1996-01-01

A barrier at a uniform depth for an entire wafer is used to produce imaging devices less susceptible to noise pulses produced by the passage of ionizing radiation. The barrier prevents charge created in the bulk silicon of a CCD detector or a semiconductor logic or memory device from entering the collection volume of each pixel in the imaging device. The charge barrier is a physical barrier, a potential barrier, or a combination of both. The physical barrier is formed by an SiO.sub.2 insulator. The potential barrier is formed by increasing the concentration of majority carriers (holes) to combine with the electron's generated by the ionizing radiation. A manufacturer of CCD imaging devices can produce radiation-tolerant devices by merely changing the wafer type fed into his process stream from a standard wafer to one possessing a barrier beneath its surface, thus introducing a very small added cost to his production cost. An effective barrier type is an SiO.sub.2 layer.

Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer

NASA Astrophysics Data System (ADS)

Watanabe, Naoya; Kikuchi, Hidekazu; Yanagisawa, Azusa; Shimamoto, Haruo; Kikuchi, Katsuya; Aoyagi, Masahiro; Nakamura, Akio

2017-07-01

A high-yield via-last through silicon via (TSV) process has been developed using notchless Si etching and wet cleaning of the first metal layer. In this process, the notching was suppressed by optimizing the deep Si etching conditions and wet cleaning was performed using an organic alkaline solution to remove reaction products generated by the etchback step on the first metal layer. By this process, a number of small TSVs (TSV diameter: 6 µm TSV depth: 22 µm number of TSVs: 20,000/chip) could be formed uniformly on an 8-in. wafer. The electrical characteristics of small TSVs formed by this via-last TSV process were investigated. The TSV resistance determined by four-terminal measurements was approximately 24 mΩ. The leakage current between the TSV and the Si substrate was 2.5 pA at 5 V. The TSV capacitance determined using an inductance-capacitance-resistance (LCR) meter was 54 fF, while the TSV yield determined from TSV chain measurements was high (83%) over an 8-in. wafer.

Further Investigations of Hypersonic Engine Seals

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H., Jr.; Steinetz, Bruce M.; DeMange, Jeffrey J.

2004-01-01

Durable, flexible sliding seals are required in advanced hypersonic engines to seal the perimeters of movable engine ramps for efficient, safe operation in high heat flux environments at temperatures of 2000 to 2500 F. Current seal designs do not meet the demanding requirements for future engines, so NASA's Glenn Research Center is developing advanced seals and preloading devices to overcome these shortfalls. An advanced ceramic wafer seal design and two silicon nitride compression spring designs were evaluated in a series of compression, scrub, and flow tests. Silicon nitride wafer seals survived 2000 in. (50.8 m) of scrubbing at 2000 F against a silicon carbide rub surface with no chips or signs of damage. Flow rates measured for the wafers before and after scrubbing were almost identical and were up to 32 times lower than those recorded for the best braided rope seal flow blockers. Silicon nitride compression springs showed promise conceptually as potential seal preload devices to help maintain seal resiliency.

Impurity gettering in silicon using cavities formed by helium implantation and annealing

DOEpatents

Myers, Jr., Samuel M.; Bishop, Dawn M.; Follstaedt, David M.

1998-01-01

Impurity gettering in silicon wafers is achieved by a new process consisting of helium ion implantation followed by annealing. This treatment creates cavities whose internal surfaces are highly chemically reactive due to the presence of numerous silicon dangling bonds. For two representative transition-metal impurities, copper and nickel, the binding energies at cavities were demonstrated to be larger than the binding energies in precipitates of metal silicide, which constitutes the basis of most current impurity gettering. As a result the residual concentration of such impurities after cavity gettering is smaller by several orders of magnitude than after precipitation gettering. Additionally, cavity gettering is effective regardless of the starting impurity concentration in the wafer, whereas precipitation gettering ceases when the impurity concentration reaches a characteristic solubility determined by the equilibrium phase diagram of the silicon-metal system. The strong cavity gettering was shown to induce dissolution of metal-silicide particles from the opposite side of a wafer.

Impurity gettering in silicon using cavities formed by helium implantation and annealing

DOEpatents

Myers, S.M. Jr.; Bishop, D.M.; Follstaedt, D.M.

1998-11-24

Impurity gettering in silicon wafers is achieved by a new process consisting of helium ion implantation followed by annealing. This treatment creates cavities whose internal surfaces are highly chemically reactive due to the presence of numerous silicon dangling bonds. For two representative transition-metal impurities, copper and nickel, the binding energies at cavities were demonstrated to be larger than the binding energies in precipitates of metal silicide, which constitutes the basis of most current impurity gettering. As a result the residual concentration of such impurities after cavity gettering is smaller by several orders of magnitude than after precipitation gettering. Additionally, cavity gettering is effective regardless of the starting impurity concentration in the wafer, whereas precipitation gettering ceases when the impurity concentration reaches a characteristic solubility determined by the equilibrium phase diagram of the silicon-metal system. The strong cavity gettering was shown to induce dissolution of metal-silicide particles from the opposite side of a wafer. 4 figs.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kilpi, Lauri, E-mail: Lauri.Kilpi@vtt.fi; Ylivaara, Oili M. E.; Vaajoki, Antti

The scratch test method is widely used for adhesion evaluation of thin films and coatings. Usual critical load criteria designed for scratch testing of coatings were not applicable to thin atomic layer deposition (ALD) films on silicon wafers. Thus, the bases for critical load evaluation were established and the critical loads suitable for ALD coating adhesion evaluation on silicon wafers were determined in this paper as L{sub CSi1}, L{sub CSi2}, L{sub CALD1}, and L{sub CALD2}, representing the failure points of the silicon substrate and the coating delamination points of the ALD coating. The adhesion performance of the ALD Al{sub 2}O{submore » 3}, TiO{sub 2}, TiN, and TaCN+Ru coatings with a thickness range between 20 and 600 nm and deposition temperature between 30 and 410 °C on silicon wafers was investigated. In addition, the impact of the annealing process after deposition on adhesion was evaluated for selected cases. The tests carried out using scratch and Scotch tape test showed that the coating deposition and annealing temperature, thickness of the coating, and surface pretreatments of the Si wafer had an impact on the adhesion performance of the ALD coatings on the silicon wafer. There was also an improved load carrying capacity due to Al{sub 2}O{sub 3}, the magnitude of which depended on the coating thickness and the deposition temperature. The tape tests were carried out for selected coatings as a comparison. The results show that the scratch test is a useful and applicable tool for adhesion evaluation of ALD coatings, even when carried out for thin (20 nm thick) coatings.« less

Scale-dependent diffusion anisotropy in nanoporous silicon

PubMed Central

Kondrashova, Daria; Lauerer, Alexander; Mehlhorn, Dirk; Jobic, Hervé; Feldhoff, Armin; Thommes, Matthias; Chakraborty, Dipanjan; Gommes, Cedric; Zecevic, Jovana; de Jongh, Petra; Bunde, Armin; Kärger, Jörg; Valiullin, Rustem

2017-01-01

Nanoporous silicon produced by electrochemical etching of highly B-doped p-type silicon wafers can be prepared with tubular pores imbedded in a silicon matrix. Such materials have found many technological applications and provide a useful model system for studying phase transitions under confinement. This paper reports a joint experimental and simulation study of diffusion in such materials, covering displacements from molecular dimensions up to tens of micrometers with carefully selected probe molecules. In addition to mass transfer through the channels, diffusion (at much smaller rates) is also found to occur in directions perpendicular to the channels, thus providing clear evidence of connectivity. With increasing displacements, propagation in both axial and transversal directions is progressively retarded, suggesting a scale-dependent, hierarchical distribution of transport resistances (“constrictions” in the channels) and of shortcuts (connecting “bridges”) between adjacent channels. The experimental evidence from these studies is confirmed by molecular dynamics (MD) simulation in the range of atomistic displacements and rationalized with a simple model of statistically distributed “constrictions” and “bridges” for displacements in the micrometer range via dynamic Monte Carlo (DMC) simulation. Both ranges are demonstrated to be mutually transferrable by DMC simulations based on the pore space topology determined by electron tomography. PMID:28106047

III-V-on-silicon solar cells reaching 33% photoconversion efficiency in two-terminal configuration

NASA Astrophysics Data System (ADS)

Cariou, Romain; Benick, Jan; Feldmann, Frank; Höhn, Oliver; Hauser, Hubert; Beutel, Paul; Razek, Nasser; Wimplinger, Markus; Bläsi, Benedikt; Lackner, David; Hermle, Martin; Siefer, Gerald; Glunz, Stefan W.; Bett, Andreas W.; Dimroth, Frank

2018-04-01

Silicon dominates the photovoltaic industry but the conversion efficiency of silicon single-junction solar cells is intrinsically constrained to 29.4%, and practically limited to around 27%. It is possible to overcome this limit by combining silicon with high-bandgap materials, such as III-V semiconductors, in a multi-junction device. Significant challenges associated with this material combination have hindered the development of highly efficient III-V/Si solar cells. Here, we demonstrate a III-V/Si cell reaching similar performances to standard III-V/Ge triple-junction solar cells. This device is fabricated using wafer bonding to permanently join a GaInP/GaAs top cell with a silicon bottom cell. The key issues of III-V/Si interface recombination and silicon's weak absorption are addressed using poly-silicon/SiOx passivating contacts and a novel rear-side diffraction grating for the silicon bottom cell. With these combined features, we demonstrate a two-terminal GaInP/GaAs//Si solar cell reaching a 1-sun AM1.5G conversion efficiency of 33.3%.

Integration of a UV curable polymer lens and MUMPs structures on a SOI optical bench

NASA Astrophysics Data System (ADS)

Hsieh, Jerwei; Hsiao, Sheng-Yi; Lai, Chun-Feng; Fang, Weileun

2007-08-01

This work presents the design concept of integrating a polymer lens, poly-Si MUMPs and single-crystal-silicon HARM structures on a SOI wafer to form a silicon optical bench. This approach enables the monolithic integration of various optical components on the wafer so as to improve the design flexibility of the silicon optical bench. Fabrication processes, including surface and bulk micromachining on the SOI wafer, have been established to realize bi-convex spherical polymer lenses with in-plane as well as out-of-plane optical axes. In addition, a micro device consisting of an in-plane polymer lens, a thick fiber holder and a mechanical shutter driven by an electrothermal actuator is also demonstrated using the present approach. In summary, this study significantly improves the design flexibility as well as the functions of SiOBs.

Silicon Chemical Vapor Deposition Process Using a Half-Inch Silicon Wafer for Minimal Manufacturing System

NASA Astrophysics Data System (ADS)

Li, Ning; Habuka, Hitoshi; Ikeda, Shin-ichi; Hara, Shiro

A chemical vapor deposition reactor for producing thin silicon films was designed and developed for achieving a new electronic device production system, the Minimal Manufacturing, using a half-inch wafer. This system requires a rapid process by a small footprint reactor. This was designed and verified by employing the technical issues, such as (i) vertical gas flow, (ii) thermal operation using a highly concentrated infrared flux, and (iii) reactor cleaning by chlorine trifluoride gas. The combination of (i) and (ii) could achieve a low heating power and a fast cooling designed by the heat balance of the small wafer placed at a position outside of the reflector. The cleaning process could be rapid by (iii). The heating step could be skipped because chlorine trifluoride gas was reactive at any temperature higher than room temperature.

Investigation of back surface fields effect on bifacial solar cells

NASA Astrophysics Data System (ADS)

Sepeai, Suhaila; Sulaiman, M. Y.; Sopian, Kamaruzzaman; Zaidi, Saleem H.

2012-11-01

A bifacial solar cell, in contrast with a conventional monofacial solar cell, produces photo-generated current from both front and back sides. Bifacial solar cell is an attractive candidate for enhancing photovoltaic (PV) market competitiveness as well as supporting the current efforts to increase efficiency and lower material costs. This paper reports on the fabrication of bifacial solar cells using phosphorus-oxytrichloride (POCl3) emitter formation on p-type, nanotextured silicon (Si) wafer. Backside surface field was formed through Al-diffusion using conventional screen-printing process. Bifacial solar cells with a structure of n+pp+ with and without back surface field (BSF) were fabricated in which silicon nitride (SiN) anti reflection and passivation films were coated on both sides, followed by screen printing of Argentum (Ag) and Argentum/Aluminum (Ag/Al) on front and back contacts, respectively. Bifacial solar cells without BSF exhibited open circuit voltage (VOC) of 535 mV for front and 480 mV for back surface. With Al-alloyed BSF bifacial solar cells, the VOC improved to 580 mV for the front surface and 560 mV for the back surface. Simulation of bifacial solar cells using PC1D and AFORS software demonstrated good agreement with experimental results. Simulations showed that best bifacial solar cells are achieved through a combination of high lifetime wafer, low recombination back surface field, reduced contact resistance, and superior surface passivation.

Simultaneous Detection of Multiple Disease States.

DTIC Science & Technology

1990-02-14

analytes to be assayed in a panel forma And due to its simplicity, OIA has been demonstrated to be generally applicable to a wide range of testing...into two distinct formats on the basis of signal generation: visual and instrumented. In both cases monocrystalline silicon wafers are employed as...Due to the limited surface area available on the monocrystalline silicon wafers, attention must be paid to efficient immobilization to ensure

"Silicon millefeuille": From a silicon wafer to multiple thin crystalline films in a single step

NASA Astrophysics Data System (ADS)

Hernández, David; Trifonov, Trifon; Garín, Moisés; Alcubilla, Ramon

2013-04-01

During the last years, many techniques have been developed to obtain thin crystalline films from commercial silicon ingots. Large market applications are foreseen in the photovoltaic field, where important cost reductions are predicted, and also in advanced microelectronics technologies as three-dimensional integration, system on foil, or silicon interposers [Dross et al., Prog. Photovoltaics 20, 770-784 (2012); R. Brendel, Thin Film Crystalline Silicon Solar Cells (Wiley-VCH, Weinheim, Germany 2003); J. N. Burghartz, Ultra-Thin Chip Technology and Applications (Springer Science + Business Media, NY, USA, 2010)]. Existing methods produce "one at a time" silicon layers, once one thin film is obtained, the complete process is repeated to obtain the next layer. Here, we describe a technology that, from a single crystalline silicon wafer, produces a large number of crystalline films with controlled thickness in a single technological step.

Silicon materials task of the low-cost solar array project. Phase 4: Effects of impurities and processing on silicon solar cells

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Hanes, M. H.; Davis, J. R.; Rohatgi, A.; Raichoudhury, P.; Mollenkopf, H. C.

1981-01-01

The results of the study form a basis for silicon producers, wafer manufacturers, and cell fabricators to develop appropriate cost-benefit relationships for the use of less pure, less costly solar grade silicon. Cr is highly mobile in silicon even at temperatures as low as 600 C. Contrasting with earlier data for Mo, Ti, and V, Cr concentrations vary from place to place in polycrystalline silicon wafers and the electrically-active Cr concentration in the polysilicon is more than an order of magnitude smaller than would be projected from single crystal impurity data. We hypothesize that Cr diffuses during ingot cooldown after growth, preferentially segregates to grain and becomes electrically deactivated. Accelerated aging data from Ni-contaminated silicon imply that no significant impurity-induced cell performance reduction should be expected over a twenty year device lifetime.

Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

NASA Technical Reports Server (NTRS)

Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

1986-01-01

The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

Determination of the p-spray profile for n+ p silicon sensors using a MOSFET

NASA Astrophysics Data System (ADS)

Fretwurst, E.; Garutti, E.; Klanner, R.; Kopsalis, I.; Schwandt, J.; Weberpals, M.

2017-09-01

The standard technique to electrically isolate the n+ implants of segmented silicon sensors fabricated on high-ohmic p-type silicon are p+-implants. Although the knowledge of the p+-implant dose and of the doping profile is highly relevant for the understanding and optimisation of sensors, this information is usually not available from the vendors, and methods to obtain it are highly welcome. The paper presents methods to obtain this information from circular MOSFETs fabricated as test structures on the same wafer as the sensors. Two circular MOSFETs, one with and one without a p+-implant under the gate, are used for this study. They were produced on Magnetic Czochralski silicon doped with ≈ 3 . 5 × 1012cm-2 of boron and 〈 100 〉 crystal orientation. The drain-source current as function of gate voltage for different back-side voltages is measured at a drain-source voltage of 50 mV in the linear MOSFET region, and the values of threshold voltage and mobility extracted using the standard MOSFET formulae. To determine the bulk doping, the implantation dose and profile from the data, two methods are used, which give compatible results. The doping profile, which varies between 3 . 5 × 1012cm-3 and 2 × 1015cm-3 for the MOSFET with p+-implant, is determined down to a distance of a fraction of a μm from the Si-SiO2 interface. The method of extracting the doping profiles is verified using data from a TCAD simulation of the two MOSFETs. The details of the methods and of the problems encountered are discussed.

Optical surface analysis: a new technique for the inspection and metrology of optoelectronic films and wafers

NASA Astrophysics Data System (ADS)

Bechtler, Laurie; Velidandla, Vamsi

2003-04-01

In response to demand for higher volumes and greater product capability, integrated optoelectronic device processing is rapidly increasing in complexity, benefiting from techniques developed for conventional silicon integrated circuit processing. The needs for high product yield and low manufacturing cost are also similar to the silicon wafer processing industry. This paper discusses the design and use of an automated inspection instrument called the Optical Surface Analyzer (OSA) to evaluate two critical production issues in optoelectronic device manufacturing: (1) film thickness uniformity, and (2) defectivity at various process steps. The OSA measurement instrument is better suited to photonics process development than most equipment developed for conventional silicon wafer processing in two important ways: it can handle both transparent and opaque substrates (unlike most inspection and metrology tools), and it is a full-wafer inspection method that captures defects and film variations over the entire substrate surface (unlike most film thickness measurement tools). Measurement examples will be provided in the paper for a variety of films and substrates used for optoelectronics manufacturing.

Progress and challenges for cost effective kerfless Silicon crystal growth for PV application

NASA Astrophysics Data System (ADS)

Serra, J. M.; Alves, J. Maia; Vallera, A. M.

2017-06-01

The major barrier for PV penetration is cost. And the single most important cost factor in silicon technology is the wafer (≈35% of the module cost). Although tremendous progress on cell processing has been reported in recent years, a much smaller evolution is seen on what should be the key point to address - the wafer. The ingot-slicing process is reaching its limits as the wafer thickness is reduced in an effort to lower material costs. Kerf losses of ≈50% and an increase in breakage of a high value added material are putting a lower bound to this approach. New ideas are therefore needed for producing wafers in a way to overcome these limitations. In this paper we present three new concepts being developed in our laboratory that have one thing in common: they all are zero kerf loss processes, aiming at significant reductions in material loss. One explores the concept of exfoliation, the other two aim at the growth of silicon directly into ribbons. These were conceived as continuous processes, based on a floating molten zone concept, to avoid impurity contamination during crystallization.

KEY COMPARISON: CCQM-K32 key comparison and P84 pilot study: Amount of silicon oxide as a thickness of SiO2 on Si

NASA Astrophysics Data System (ADS)

Seah, M. P.

2008-01-01

CCQM-K32 and P84 were conducted following the pilot study P-38 to demonstrate and document the capability of interested National Metrology Institutes to measure the amount of silicon oxide on silicon wafers expressed as a thickness of SiO2 for nominal thicknesses in the range 1.5 nm to 8 nm. 'Amount of substance' may be expressed in many ways and here the measurand is the thickness of the silicon oxide layer on each of a total of 9 samples of nominal thicknesses in the range 1.5 to 8 nm on (100) and (111) Si substrates, expressed as the thickness of SiO2. This report presents the results from K32 and P84. It includes the data received for the measured values and their associated uncertainties, at 95% confidence, for the 9 samples prior to the deadline for receipt of data. The materials are grown by thermal oxidation in very clean furnaces designed for high quality gate oxides on Si wafers in European and US facilities at the same time as those for the pilot study, P-38. Separate samples were provided to each institute in special containers limiting the carbonaceous contamination to below about 0.3 nm. The 9 samples included 5 samples of ultra-thin SiO2 on (100) orientated wafers of Si and 4 samples of ultra-thin SiO2 on (111) orientated wafers of Si. The measurements from the 11 participating laboratories were conducted using ellipsometry, neutron reflectivity (NR), x-ray photoelectron spectroscopy (XPS) or x-ray reflectivity measurements (XRR), guided by the protocol developed in the pilot study P-38 and reproduced in the Appendix. The measurements are given in tables 2 and 3. A very small correction is then made for the different samples that each laboratory received as in table 4. Where appropriate, method offset values deduced from the pilot study P-38 are given in table 5 leading to comparative data in tables 6 and 7. Values for the key comparison reference values (KCRVs) and their associated uncertainties are made from the weighted means and the expanded weighted standard deviations of the means from table 6. This is provided in table 8. Graphical plots of equivalence from tables 6 and 8 are provided in figure 1 and equivalence statements are presented in Annex A. Additional XPS and XRR data from NMIJ for K32 were withdrawn from the KCRV evaluation and are given in Annex B. Main text. To reach the main text of this paper, click on Final Report. Note that this text is that which appears in Appendix B of the BIPM key comparison database kcdb.bipm.org/. The final report has been peer-reviewed and approved for publication by the CCQM, according to the provisions of the CIPM Mutual Recognition Arrangement (MRA).

Advances in photonic MOEMS-MEMS device thinning and polishing

NASA Astrophysics Data System (ADS)

McAneny, James J.; Kennedy, Mark; McGroggan, Tom

2010-02-01

As devices continue to increase in density and complexity, ever more stringent specifications are placed on the wafer scale equipment manufacturers to produce higher quality and higher output. This results in greater investment and more resource being diverted into producing tools and processes which can meet the latest demanding criteria. Substrate materials employed in the fabrication process range from Silicon through InP and include GaAs, InSb and other optical networking or waveguide materials. With this diversity of substrate materials presented, controlling the geometries and surfaces grows progressively more challenging. This article highlights the key parameters which require close monitoring and control in order to produce highly precise wafers as part of the fabrication process. Several as cut and commercially available standard polished wafer materials were used in empirical trials to test tooling options in generating high levels of geometric control over the dimensions while producing high quality surface finishes. Specific attention was given to the measurement and control of: flatness; parallelism/TTV; surface roughness and final target thickness as common specifications required by the industry. By combining the process variables of: plate speed, download pressure, slurry flow rate and concentration, pad type and wafer travel path across the polish pad, the effect of altering these variables was recorded and analysed to realize the optimum process conditions for the materials under test. The results being then used to design improved methods and tooling for the thinning and polishing of photonic materials applied to MOEMS-MEMS device fabrication.

Study and development of non-aqueous silicon-air battery

NASA Astrophysics Data System (ADS)

Cohn, Gil; Ein-Eli, Yair

Silicon-air battery utilizing a single-crystal heavily doped n-type silicon wafer anode and an air cathode is reported in this paper. The battery employs hydrophilic 1-ethyl-3-methylimidazolium oligofluorohydrogenate [EMI·(HF) 2.3F] room temperature ionic liquid electrolyte. Electrochemical studies, including polarization and galvanostatic experiments, performed on various silicon types reveal the predominance performance of heavily doped n-type. Cell discharging at constant current densities of 10, 50, 100 and 300 μA cm -2 in ambient atmosphere, shows working voltages of 1.1-0.8 V. The study shows that as discharge advances, the moist interface of the air electrode is covered by discharge products, which prevent a continuous diffusion of oxygen to the electrode-electrolyte interface. The oxygen suffocation, governed by the settlement of the cell reaction products, is the main factor for an early failure of the cells. Based on the results obtained from scanning electron microscopy, energy-dispersive X-ray spectroscopy and X-ray photoelectron spectroscopy studies, we propose a series of reactions governing the discharge process in silicon-air batteries, as well as a detailed mechanism for silicon oxide deposition on the air electrode porous carbon.

Recombination activity of light-activated copper defects in p-type silicon studied by injection- and temperature-dependent lifetime spectroscopy

NASA Astrophysics Data System (ADS)

Inglese, Alessandro; Lindroos, Jeanette; Vahlman, Henri; Savin, Hele

2016-09-01

The presence of copper contamination is known to cause strong light-induced degradation (Cu-LID) in silicon. In this paper, we parametrize the recombination activity of light-activated copper defects in terms of Shockley—Read—Hall recombination statistics through injection- and temperature dependent lifetime spectroscopy (TDLS) performed on deliberately contaminated float zone silicon wafers. We obtain an accurate fit of the experimental data via two non-interacting energy levels, i.e., a deep recombination center featuring an energy level at Ec-Et=0.48 -0.62 eV with a moderate donor-like capture asymmetry ( k =1.7 -2.6 ) and an additional shallow energy state located at Ec-Et=0.1 -0.2 eV , which mostly affects the carrier lifetime only at high-injection conditions. Besides confirming these defect parameters, TDLS measurements also indicate a power-law temperature dependence of the capture cross sections associated with the deep energy state. Eventually, we compare these results with the available literature data, and we find that the formation of copper precipitates is the probable root cause behind Cu-LID.

Efficiency of silicon solar cells containing chromium

DOEpatents

Frosch, Robert A. Administrator of the National Aeronautics and Space; Salama, Amal M.

1982-01-01

Efficiency of silicon solar cells containing about 10.sup.15 atoms/cm.sup.3 of chromium is improved about 26% by thermal annealing of the silicon wafer at a temperature of 200.degree. C. to form chromium precipitates having a diameter of less than 1 Angstrom. Further improvement in efficiency is achieved by scribing laser lines onto the back surface of the wafer at a spacing of at least 0.5 mm and at a depth of less than 13 micrometers to preferentially precipitate chromium near the back surface and away from the junction region of the device. This provides an economical way to improve the deleterious effects of chromium, one of the impurities present in metallurgical grade silicon material.

Boron diffusion in silicon devices

DOEpatents

Rohatgi, Ajeet; Kim, Dong Seop; Nakayashiki, Kenta; Rounsaville, Brian

2010-09-07

Disclosed are various embodiments that include a process, an arrangement, and an apparatus for boron diffusion in a wafer. In one representative embodiment, a process is provided in which a boric oxide solution is applied to a surface of the wafer. Thereafter, the wafer is subjected to a fast heat ramp-up associated with a first heating cycle that results in a release of an amount of boron for diffusion into the wafer.

High-efficiency silicon heterojunction solar cells: Status and perspectives

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Wolf, S.; Geissbuehler, J.; Loper, P.

Silicon heterojunction technology (HJT) uses silicon thin-film deposition techniques to fabricate photovoltaic devices from mono-crystalline silicon wafers (c-Si). This enables energy-conversion efficiencies above 21 %, also at industrial-production level. In this presentation we review the present status of this technology and point out recent trends. We first discuss how the properties of thin hydrogenated amorphous silicon (a-Si:H) films can be exploited to fabricate passivating contacts, which is the key to high- efficiency HJT solar cells. Such contacts enable very high operating voltages, approaching the theoretical limits, and yield small temperature coefficients. With this approach, an increasing number of groups aremore » reporting devices with conversion efficiencies well over 20 % on both-sides contacted n-type cells, Panasonic leading the field with 24.7 %. Exciting results have also been obtained on p-type wafers. Despite these high voltages, important efficiency gains can still be made in fill factor and optical design. This requires improved understanding of carrier transport across device interfaces and reduced parasitic absorption in HJT solar cells. For the latter, several strategies can be followed: Short-wavelength losses can be reduced by replacing the front a-Si:H films with wider-bandgap window layers, such as silicon alloys or even metal oxides. Long- wavelength losses are mitigated by introducing new high-mobility TCO’s such as hydrogenated indium oxide, and also by designing new rear reflectors. Optical shadow losses caused by the front metallization grid are significantly reduced by replacing printed silver electrodes with fine-line plated copper contacts, leading also to possible cost advantages. The ultimate approach to minimize optical losses is the implementation of back-contacted architectures, which are completely devoid of grid shadow losses and parasitic absorption in the front layers can be minimized irrespective of electrical transport requirements. The validity of this approach was convincingly demonstrated by Panasonic, Japan in 2014, reporting on an interdigitated back-contacted HJT cell with an efficiency of 25.6%, setting the new single-junction c-Si record. Finally, given the virtually perfect surface passivation and excellent red response of HJT solar cells, we anticipate these devices will also become the preferred bottom cell in ultra-high efficiency c-Si-based tandem devices, exploiting better the solar spectrum. Such tandem cells have the potential to overcome the fundamental single-junction limit of silicon solar cells (29.4%). Combining HJT cells with perovskite solar cells as top cell appears to be particularly appealing.« less

Vacancy-type defects in TiO2/SiO2/SiC dielectric stacks

NASA Astrophysics Data System (ADS)

Coleman, P. G.; Burrows, C. P.; Mahapatra, R.; Wright, N. G.

2007-07-01

Open-volume (vacancy-type) point defects have been observed in ˜80-nm-thick titanium dioxide films grown on silicon dioxide/4H silicon carbide substrates as stacks with high dielectric constant for power device applications, using variable-energy positron annihilation spectroscopy. The concentration of vacancies decreases as the titanium dioxide growth temperature is increased in the range from 700to1000°C, whereas grain boundaries form in the polycrystalline material at the highest growth temperatures. It is proposed that the optimal electrical performance for films grown at 800°C reflects a balance between decreasing vacancy concentration and increasing grain boundary formation. The concentration of vacancies at the silicon dioxide/silicon carbide interface appears to saturate after 2.5h oxidation at 1150°C. A supplementary result suggests that the quality of the 10-μm-thick deposited silicon carbide epilayer is compromised at depths of about 2μm and beyond, possibly by the migration of impurities and/or other defects from the standard-grade highly doped 4H silicon carbide wafer beneath the epilayer during oxidation.

Optical Addressing Electronic Tongue Based on Low Selective Photovoltaic Transducer with Nanoporous Silicon Layer

NASA Astrophysics Data System (ADS)

Litvinenko, S. V.; Bielobrov, D. O.; Lysenko, V.; Skryshevsky, V. A.

2016-08-01

The electronic tongue based on the array of low selective photovoltaic (PV) sensors and principal component analysis is proposed for detection of various alcohol solutions. A sensor array is created at the forming of p-n junction on silicon wafer with porous silicon layer on the opposite side. A dynamical set of sensors is formed due to the inhomogeneous distribution of the surface recombination rate at this porous silicon side. The sensitive to molecular adsorption photocurrent is induced at the scanning of this side by laser beam. Water, ethanol, iso-propanol, and their mixtures were selected for testing. It is shown that the use of the random dispersion of surface recombination rates on different spots of the rear side of p-n junction and principal component analysis of PV signals allows identifying mentioned liquid substances and their mixtures.

Design and fabrication of a foldable 3D silicon based package for solid state lighting applications

NASA Astrophysics Data System (ADS)

Sokolovskij, R.; Liu, P.; van Zeijl, H. W.; Mimoun, B.; Zhang, G. Q.

2015-05-01

Miniaturization of solid state lighting (SSL) luminaires as well as reduction of packaging and assembly costs are of prime interest for the SSL lighting industry. A novel silicon based LED package for lighting applications is presented in this paper. The proposed design consists of 5 rigid Si tiles connected by flexible polyimide hinges with embedded interconnects (ICs). Electrical, optical and thermal characteristics were taken into consideration during design. The fabrication process involved polyimide (PI) application and patterning, aluminium interconnect integration in the flexible hinge, LED reflector cavity formation and metalization followed by through wafer DRIE etching for chip formation and release. A method to connect chip front to backside without TSVs was also integrated into the process. Post-fabrication wafer level assembly included LED mounting and wirebond, phosphor-based colour conversion and silicone encapsulation. The package formation was finalized by vacuum assisted wrapping around an assembly structure to form a 3D geometry, which is beneficial for omnidirectional lighting. Bending tests were performed on the flexible ICs and optical performance at different temperatures was evaluated. It is suggested that 3D packages can be expanded to platforms for miniaturized luminaire applications by combining monolithic silicon integration and system-in-package (SiP) technologies.

Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

NASA Astrophysics Data System (ADS)

Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

Microelectromechanical Systems (MEMS) Photoacoustic (PA) Detector of Terahertz (THz) Radiation for Chemical Sensing

DTIC Science & Technology

2014-03-01

26 Feb 2014 Ivan Medvedev, PhD (Member) Date iv AFIT-ENG-14-M-58 Abstract In this research effort, a Microelectromechanical...7. Separation by implantation of oxygen (SIMOX) is a process of creating silicon- on-insulator (SOI) wafers. Oxygen ions are implanted into a silicon...wafer. The depth of the insulating layer is dependent upon the power used during ion implantation [14]. .............................. 16  Figure 8

Determination of the implantation dose in silicon wafers by X-ray fluorescence analysis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Klockenkaemper, R.; Becker, M.; Bubert, H.

1990-08-01

The ion dose implanted in silicon wafers was determined by X-ray fluorescence analysis after the implantation process. As only near-surface layers below 1-{mu}m thickness were considered, the calibration could be carried out with external standards consisting of thin films of doped gelatine spread on pure wafers. Dose values for Cr and Co were determined between 4 {times} 10{sup 15} and 2 {times} 10{sup 17} atoms/cm{sup 2}, the detection limits being about 3 {times} 10{sup 14} atoms/cm{sup 2}. The results are precise and accurate apart from a residual scatter of less than 7%. This was confirmed by flame atomic absorption spectrometrymore » after volatilization of the silicon matrix as SiF{sub 4}. It was found that ion-current measurements carried out during the implantation process can have considerable systematic errors.« less

Large-size, high-uniformity, random silver nanowire networks as transparent electrodes for crystalline silicon wafer solar cells.

PubMed

Xie, Shouyi; Ouyang, Zi; Jia, Baohua; Gu, Min

2013-05-06

Metal nanowire networks are emerging as next generation transparent electrodes for photovoltaic devices. We demonstrate the application of random silver nanowire networks as the top electrode on crystalline silicon wafer solar cells. The dependence of transmittance and sheet resistance on the surface coverage is measured. Superior optical and electrical properties are observed due to the large-size, highly-uniform nature of these networks. When applying the nanowire networks on the solar cells with an optimized two-step annealing process, we achieved as large as 19% enhancement on the energy conversion efficiency. The detailed analysis reveals that the enhancement is mainly caused by the improved electrical properties of the solar cells due to the silver nanowire networks. Our result reveals that this technology is a promising alternative transparent electrode technology for crystalline silicon wafer solar cells.

Noncontacting acoustics-based temperature measurement techniques in rapid thermal processing

NASA Astrophysics Data System (ADS)

Lee, Yong J.; Chou, Ching-Hua; Khuri-Yakub, Butrus T.; Saraswat, Krishna C.

1991-04-01

Temperature measurement of silicon wafers based on the temperature dependence of acoustic waves is studied. The change in the temperature-dependent dispersion relations of the plate modes through the wafer can be exploited to provide a viable temperature monitoring scheme with advantages over both thermocouples and pyrometers. Velocity measurements of acoustic waves through a thin layer of ambient directly above the wafer provides the temperature of the wafer-ambient interface. 1.

Silicon photonics fiber-to-the-home transceiver array based on transfer-printing-based integration of III-V photodetectors.

PubMed

Zhang, Jing; De Groote, Andreas; Abbasi, Amin; Loi, Ruggero; O'Callaghan, James; Corbett, Brian; Trindade, António José; Bower, Christopher A; Roelkens, Gunther

2017-06-26

A 4-channel silicon photonics transceiver array for Point-to-Point (P2P) fiber-to-the-home (FTTH) optical networks at the central office (CO) side is demonstrated. A III-V O-band photodetector array was integrated onto the silicon photonic transmitter through transfer printing technology, showing a polarization-independent responsivity of 0.39 - 0.49 A/W in the O-band. The integrated PDs (30 × 40 μm 2 mesa) have a 3 dB bandwidth of 11.5 GHz at -3 V bias. Together with high-speed C-band silicon ring modulators whose bandwidth is up to 15 GHz, operation of the transceiver array at 10 Gbit/s is demonstrated. The use of transfer printing for the integration of the III-V photodetectors allows for an efficient use of III-V material and enables the scalable integration of III-V devices on silicon photonics wafers, thereby reducing their cost.

Effect of void shape in Czochralski-Si wafers on the intensity of laser-scattering

NASA Astrophysics Data System (ADS)

Takahashi, J.; Kawakami, K.; Nakai, K.

2001-06-01

The shape effect of anisotropic-shaped microvoid defects in Czochralski-grown silicon wafers on the intensity of laser scattering has been investigated. The size and shape of the defects were examined by means of transmission electron microscopy. Octahedral voids in conventional (nitrogen-undoped) wafers showed an almost isotropic scattering property under the incident condition of a p-polarization beam. On the other hand, parallelepiped-plate-shaped voids in nitrogen-doped wafers showed an anisotropic scattering property on both p- and s-polarized components of scattered light, depending strongly on the incident laser direction. The measured results were explained not by scattering calculation using Born approximation but by calculation based on Rayleigh scattering. It was found that the s component is explained by an inclination of a dipole moment induced on a defect from the scattering plane. Furthermore, using numerical electromagnetic analysis it was shown that the asymmetric behavior of the s component on the parallelepiped-plate voids is ascribed to the parallelepiped shape effect. These results suggest that correction of the scattering intensity is necessary to evaluate the size and volume of anisotropic-shaped defects from the scattered intensity.

Proceedings of the Low-Cost Solar Array Wafering Workshop

NASA Technical Reports Server (NTRS)

Morrison, A. D.

1982-01-01

The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Custer, Jonathan S.; Fleming, James G.; Roherty-Osmun, Elizabeth

Refractory ternary nitride films for diffusion barriers in microelectronics have been grown using chemical vapor deposition. Thin films of titanium-silicon-nitride, tungsten-boron-nitride, and tungsten-silicon-nitride of various compositions have been deposited on 150 mm Si wafers. The microstructure of the films are either fully amorphous for the tungsten based films, or nauocrystalline TiN in an amorphous matrix for titanium-silicon-nitride. All films exhibit step coverages suitable for use in future microelectronics generations. Selected films have been tested as diffusion barriers between copper and silicon, and generally perform extremely weH. These fiIms are promising candidates for advanced diffusion barriers for microelectronics applications. The manufacturingmore » of silicon wafers into integrated circuits uses many different process and materials. The manufacturing process is usually divided into two parts: the front end of line (FEOL) and the back end of line (BEOL). In the FEOL the individual transistors that are the heart of an integrated circuit are made on the silicon wafer. The responsibility of the BEOL is to wire all the transistors together to make a complete circuit. The transistors are fabricated in the silicon itself. The wiring is made out of metal, currently aluminum and tungsten, insulated by silicon dioxide, see Figure 1. Unfortunately, silicon will diffuse into aluminum, causing aluminum spiking of junctions, killing transistors. Similarly, during chemical vapor deposition (CVD) of tungsten from ~fj, the reactivity of the fluorine can cause "worn-holes" in the silicon, also destroying transistors. The solution to these problems is a so-called diffusion barrier, which will allow current to pass from the transistors to the wiring, but will prevent reactions between silicon and the metal.« less

From Si wafers to cheap and efficient Si electrodes for Li-ion batteries

NASA Astrophysics Data System (ADS)

Gauthier, Magali; Reyter, David; Mazouzi, Driss; Moreau, Philippe; Guyomard, Dominique; Lestriez, Bernard; Roué, Lionel

2014-06-01

High-energy ball milling is used to recycle Si wafers to produce Si powders for negative electrodes of Li-ion batteries. The resulting Si powder consists in micrometric Si agglomerates made of cold-welded submicrometric nanocrystalline Si particles. Silicon-based composite electrodes prepared with ball-milled Si wafer can achieve more than 900 cycles with a capacity of 1200 mAh g-1 of Si (880 mAh g-1 of electrode) and a coulombic efficiency higher than 99%. This excellent electrochemical performance lies in the use of nanostructured Si produced by ball milling, the electrode formulation in a pH 3 buffer solution with CMC as binder and the use of FEC/VC additives in the electrolyte. This work opens the way to an economically attractive recycling of Si wastes.

A thermal microprobe fabricated with wafer-stage processing

NASA Astrophysics Data System (ADS)

Zhang, Yongxia; Zhang, Yanwei; Blaser, Juliana; Sriram, T. S.; Enver, Ahsan; Marcus, R. B.

1998-05-01

A thermal microprobe has been designed and built for high resolution temperature sensing. The thermal sensor is a thin-film thermocouple junction at the tip of an atomic force microprobe (AFM) silicon probe needle. Only wafer-stage processing steps are used for the fabrication. For high resolution temperature sensing it is essential that the junction be confined to a short distance at the AFM tip. This confinement is achieved by a controlled photoresist coating process. Experiment prototypes have been made with an Au/Pd junction confined to within 0.5 μm of the tip, with the two metals separated elsewhere by a thin insulating oxide layer. Processing begins with double-polished, n-type, 4 in. diameter, 300-μm-thick silicon wafers. Atomically sharp probe tips are formed by a combination of dry and wet chemical etching, and oxidation sharpening. The metal layers are sputtering deposited and the cantilevers are released by a combination of KOH and dry etching. A resistively heated calibration device was made for temperature calibration of the thermal microprobe over the temperature range 25-110 °C. Over this range the thermal outputs of two microprobes are 4.5 and 5.6 μV/K and is linear. Thermal and topographical images are also obtained from a heated tungsten thin film fuse.

Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

NASA Astrophysics Data System (ADS)

Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

2016-02-01

In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

Combination of grazing incidence x-ray fluorescence with x-ray reflectivity in one table-top spectrometer for improved characterization of thin layer and implants on/in silicon wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ingerle, D.; Schiebl, M.; Streli, C.

2014-08-15

As Grazing Incidence X-ray Fluorescence (GIXRF) analysis does not provide unambiguous results for the characterization of nanometre layers as well as nanometre depth profiles of implants in silicon wafers by its own, the approach of providing additional information using the signal from X-ray Reflectivity (XRR) was tested. As GIXRF already uses an X-ray beam impinging under grazing incidence and the variation of the angle of incidence, a GIXRF spectrometer was adapted with an XRR unit to obtain data from the angle dependent fluorescence radiation as well as data from the reflected beam. A θ-2θ goniometer was simulated by combining amore » translation and tilt movement of a Silicon Drift detector, which allows detecting the reflected beam over 5 orders of magnitude. HfO{sub 2} layers as well as As implants in Silicon wafers in the nanometre range were characterized using this new setup. A just recently published combined evaluation approach was used for data evaluation.« less

Using the surface charge profiler for in-line monitoring of doping concentration in silicon epitaxial wafer manufacturing

NASA Astrophysics Data System (ADS)

Tower, Joshua P.; Kamieniecki, Emil; Nguyen, M. C.; Danel, Adrien

1999-08-01

The Surface Charge Profiler (SCP) has been introduced for monitoring and development of silicon epitaxial processes. The SCP measures the near-surface doping concentration and offers advantages that lead to yield enhancement in several ways. First, non-destructive measurement technology enables in-line process monitoring, eliminating the need to sacrifice production wafers for resistivity measurements. Additionally, the full-wafer mapping capability helps in development of improved epitaxial growth processes and early detection of reactor problems. As examples, we present the use of SCP to study the effects of susceptor degradation in barrel reactors and to study autodoping for development of improved dopant uniformity.

Electrostatic bonding of thin (approximately 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (approximately 2 mil) silicon wafers and solar cells

NASA Technical Reports Server (NTRS)

Egelkrout, D. W.; Horne, W. E.

1980-01-01

Electrostatic bonding (ESB) of thin (3 mil) Corning 7070 cover glasses to Ta2O5 AR-coated thin (2 mil) silicon wafers and solar cells is investigated. An experimental program was conducted to establish the effects of variations in pressure, voltage, temperature, time, Ta2O5 thickness, and various prebond glass treatments. Flat wafers without contact grids were used to study the basic effects for bonding to semiconductor surfaces typical of solar cells. Solar cells with three different grid patterns were used to determine additional requirements caused by the raised metallic contacts.

Solid state laser applications in photovoltaics manufacturing

NASA Astrophysics Data System (ADS)

Dunsky, Corey; Colville, Finlay

2008-02-01

Photovoltaic energy conversion devices are on a rapidly accelerating growth path driven by increasing government and societal pressure to use renewable energy as part of an overall strategy to address global warming attributed to greenhouse gas emissions. Initially supported in several countries by generous tax subsidies, solar cell manufacturers are relentlessly pushing the performance/cost ratio of these devices in a quest to reach true cost parity with grid electricity. Clearly this eventual goal will result in further acceleration in the overall market growth. Silicon wafer based solar cells are currently the mainstay of solar end-user installations with a cost up to three times grid electricity. But next-generation technology in the form of thin-film devices promises streamlined, high-volume manufacturing and greatly reduced silicon consumption, resulting in dramatically lower per unit fabrication costs. Notwithstanding the modest conversion efficiency of thin-film devices compared to wafered silicon products (around 6-10% versus 15-20%), this cost reduction is driving existing and start-up solar manufacturers to switch to thin-film production. A key aspect of these devices is patterning large panels to create a monolithic array of series-interconnected cells to form a low current, high voltage module. This patterning is accomplished in three critical scribing processes called P1, P2, and P3. Lasers are the technology of choice for these processes, delivering the desired combination of high throughput and narrow, clean scribes. This paper examines these processes and discusses the optimization of industrial lasers to meet their specific needs.

Wavelength tunable MEMS VCSELs for OCT imaging

NASA Astrophysics Data System (ADS)

Sahoo, Hitesh Kumar; Ansbæk, Thor; Ottaviano, Luisa; Semenova, Elizaveta; Hansen, Ole; Yvind, Kresten

2018-02-01

MEMS VCSELs are one of the most promising swept source (SS) lasers for optical coherence tomography (OCT) and one of the best candidates for future integration with endoscopes, surgical probes and achieving an integrated OCT system. However, the current MEMS-based SS are processed on the III-V wafers, which are small, expensive and challenging to work with. Furthermore, the actuating part, i.e., the MEMS, is on the top of the structure which causes a strong dependence on packaging to decrease its sensitivity to the operating environment. This work addresses these design drawbacks and proposes a novel design framework. The proposed device uses a high contrast grating mirror on a Si MEMS stage as the bottom mirror, all of which is defined in an SOI wafer. The SOI wafer is then bonded to an InP III-V wafer with the desired active layers, thereby sealing the MEMS. Finally, the top mirror, a dielectric DBR (7 pairs of TiO2 - SiO2), is deposited on top. The new device is based on a silicon substrate with MEMS defined on a silicon membrane in an enclosed cavity. Thus the device is much more robust than the existing MEMS VCSELs. This design also enables either a two-way actuation on the MEMS or a smaller optical cavity (pull-away design), i.e., wider FSR (Free Spectral Range) to increase the wavelength sweep. Fabrication of the proposed device is outlined and the results of device characterization are reported.

Electrostatic bonding of thin (cycle sine 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (cycle sine 2 mil) silicon wafers and solar cells

NASA Technical Reports Server (NTRS)

Egelkrout, D. W.

1981-01-01

Electrostatic bonding of thin cover glass to thin solar cells was researched. Silicon solar cells, wafers, and Corning 7070 glass of from about 0.002" to about 0.003" in thickness were used in the investigation to establish optimum parameters for producing mechanically acceptable bonds while minimizing thermal stresses and resultant solar cell electrical parameter degradation.

Cost-effective method of manufacturing a 3D MEMS optical switch

NASA Astrophysics Data System (ADS)

Carr, Emily; Zhang, Ping; Keebaugh, Doug; Chau, Kelvin

2009-02-01

growth of data and video transport networks. All-optical switching eliminates the need for optical-electrical conversion offering the ability to switch optical signals transparently: independent of data rates, formats and wavelength. It also provides network operators much needed automation capabilities to create, monitor and protect optical light paths. To further accelerate the market penetration, it is necessary to identify a path to reduce the manufacturing cost significantly as well as enhance the overall system performance, uniformity and reliability. Currently, most MEMS optical switches are assembled through die level flip-chip bonding with either epoxies or solder bumps. This is due to the alignment accuracy requirements of the switch assembly, defect matching of individual die, and cost of the individual components. In this paper, a wafer level assembly approach is reported based on silicon fusion bonding which aims to reduce the packaging time, defect count and cost through volume production. This approach is successfully demonstrated by the integration of two 6-inch wafers: a mirror array wafer and a "snap-guard" wafer, which provides a mechanical structure on top of the micromirror to prevent electrostatic snap-down. The direct silicon-to-silicon bond eliminates the CTEmismatch and stress issues caused by non-silicon bonding agents. Results from a completed integrated switch assembly will be presented, which demonstrates the reliability and uniformity of some key parameters of this MEMS optical switch.

Hexagon solar power panel

NASA Technical Reports Server (NTRS)

Rubin, I. (Inventor)

1978-01-01

A solar energy panel support is described upon which silicon cells are arrayed. The cells are wafer thin and of two geometrical types, both of the same area and electrical rating, namely hexagon cells and hourglass cells. The hourglass cells are composites of half hexagons. A near perfect nesting relationship of the cells achieves a high density packing whereby optimum energy production per panel area is achieved.

Hexagon solar power panel

DOEpatents

Rubin, Irwin

1978-01-01

A solar energy panel comprises a support upon which silicon cells are arrayed. The cells are wafer thin and of two geometrical types, both of the same area and electrical rating, namely hexagon cells and hourglass cells. The hourglass cells are composites of half hexagons. A near perfect nesting relationship of the cells achieves a high density packing whereby optimum energy production per panel area is achieved.

Dissolution of Oxygen Precipitate Nuclei in n-Type CZ-Si Wafers to Improve Their Material Quality: Experimental Results

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, Bhushan; Basnyat, Prakash; Devayajanam, Srinivas

2017-01-01

We present experimental results which show that oxygen-related precipitate nuclei (OPN) present in p-doped, n-type, Czochralski wafers can be dissolved using a flash-annealing process, yielding very high quality wafers for high-efficiency solar cells. Flash annealing consists of heating a wafer in an optical furnace to temperature between 1150 and 1250 degrees C for a short time. This process produces a large increase in the minority carrier lifetime (MCLT) and homogenizes each wafer. We have tested wafers from different axial locations of two ingots. All wafers reach nearly the same high value of MCLT. The OPN dissolution is confirmed by oxygenmore » analysis using Fourier transform infrared spectra and injection-level dependence of MCLT.« less

Crystal structure of laser-induced subsurface modifications in Si

NASA Astrophysics Data System (ADS)

Verburg, P. C.; Smillie, L. A.; Römer, G. R. B. E.; Haberl, B.; Bradby, J. E.; Williams, J. S.; Huis in't Veld, A. J.

2015-08-01

Laser-induced subsurface modification of dielectric materials is a well-known technology. Applications include the production of optical components and selective etching. In addition to dielectric materials, the subsurface modification technology can be applied to silicon, by employing near to mid-infrared radiation. An application of subsurface modifications in silicon is laser-induced subsurface separation, which is a method to separate wafers into individual dies. Other applications for which proofs of concept exist are the formation of waveguides and resistivity tuning. However, limited knowledge is available about the crystal structure of subsurface modifications in silicon. In this work, we investigate the geometry and crystal structure of laser-induced subsurface modifications in monocrystalline silicon wafers. In addition to the generation of lattice defects, we found that transformations to amorphous silicon and Si -iii/Si -xii occur as a result of the laser irradiation.

Wafer-scale epitaxial graphene on SiC for sensing applications

NASA Astrophysics Data System (ADS)

Karlsson, Mikael; Wang, Qin; Zhao, Yichen; Zhao, Wei; Toprak, Muhammet S.; Iakimov, Tihomir; Ali, Amer; Yakimova, Rositza; Syväjärvi, Mikael; Ivanov, Ivan G.

2015-12-01

The epitaxial graphene-on-silicon carbide (SiC-G) has advantages of high quality and large area coverage owing to a natural interface between graphene and SiC substrate with dimension up to 100 mm. It enables cost effective and reliable solutions for bridging the graphene-based sensors/devices from lab to industrial applications and commercialization. In this work, the structural, optical and electrical properties of wafer-scale graphene grown on 2'' 4H semi-insulating (SI) SiC utilizing sublimation process were systemically investigated with focus on evaluation of the graphene's uniformity across the wafer. As proof of concept, two types of glucose sensors based on SiC-G/Nafion/Glucose-oxidase (GOx) and SiC-G/Nafion/Chitosan/GOx were fabricated and their electrochemical properties were characterized by cyclic voltammetry (CV) measurements. In addition, a few similar glucose sensors based on graphene by chemical synthesis using modified Hummer's method were also fabricated for comparison.

Capillary-Driven Microfluidic Chips for Miniaturized Immunoassays: Efficient Fabrication and Sealing of Chips Using a "Chip-Olate" Process.

PubMed

Temiz, Yuksel; Delamarche, Emmanuel

2017-01-01

The fabrication of silicon-based microfluidic chips is invaluable in supporting the development of many microfluidic concepts for research in the life sciences and in vitro diagnostic applications such as the realization of miniaturized immunoassays using capillary-driven chips. While being extremely abundant, the literature covering microfluidic chip fabrication and assay development might not have addressed properly the challenge of fabricating microfluidic chips on a wafer level or the need for dicing wafers to release chips that need then to be further processed, cleaned, rinsed, and dried one by one. Here, we describe the "chip-olate" process wherein microfluidic structures are formed on a silicon wafer, followed by partial dicing, cleaning, and drying steps. Then, integration of reagents (if any) can be done, followed by lamination of a sealing cover. Breaking by hand the partially diced wafer yields individual chips ready for use.

Resonance ultrasonic vibrations in Cz-Si wafers as a possible diagnostic technique in ion implantation

NASA Astrophysics Data System (ADS)

Zhao, Z. Y.; Ostapenko, S.; Anundson, R.; Tvinnereim, M.; Belyaev, A.; Anthony, M.

2001-07-01

The semiconductor industry does not have effective metrology for well implants. The ability to measure such deep level implants will become increasingly important as we progress along the technology road map. This work explores the possibility of using the acoustic whistle effect on ion implanted silicon wafers. The technique detects the elastic stress and defects in silicon wafers by measuring the sub-harmonic f/2 resonant vibrations on a wafer induced via backside contact to create standing waves, which are measured by a non-contact ultrasonic probe. Preliminary data demonstrates that it is sensitive to implant damage, and there is a direct correlation between this sub-harmonic acoustic mode and some of the implant and anneal conditions. This work presents the results of a feasibility study to assess and quantify the correspondent whistle effect to implant damage, residual damage after annealing and intrinsic defects.

Silicon nanostructure arrays prepared by single step metal assisted chemical etching from single crystal wafer

NASA Astrophysics Data System (ADS)

Sarkar, Kalyan; Das, Debajyoti

2018-04-01

Arrays of silicon nanostructures have been produced by single step Metal Assisted Chemical Etching (MACE) of single crystal Si-wafers at room temp and normal atmospheric condition. By studying optical and structural properties of the silicon nanowire like structures synthesized by Ag catalyst assisted chemical etching, a significant change in the reflectance spectra has been obtained leading to a gross reduction in reflectance from ˜31% to less than 1%. In comparison with bulk c-Si, the surface areas of the nanostructured samples have been increased significantly with the etching time, leading to an efficient absorption of light, favorable for photovoltaic applications.

Low-temperature wafer direct bonding of silicon and quartz glass by a two-step wet chemical surface cleaning

NASA Astrophysics Data System (ADS)

Wang, Chenxi; Xu, Jikai; Zeng, Xiaorun; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

2018-02-01

We demonstrate a facile bonding process for combining silicon and quartz glass wafers by a two-step wet chemical surface cleaning. After a post-annealing at 200 °C, strong bonding interfaces with no defects or microcracks were obtained. On the basis of the detailed surface and bonding interface characterizations, the bonding mechanism was explored and discussed. The amino groups terminated on the cleaned surfaces might contribute to the bonding strength enhancement during the annealing. This cost-effective bonding process has great potentials for silicon- and glass-based heterogeneous integrations without requiring a vacuum system.

Synthesis of ZnS films on Si(100) wafers by using chemical bath deposition assisted by the complexing agent ethylenediamine

NASA Astrophysics Data System (ADS)

Zhu, He-Jie; Wang, Xue-Mei; Gao, Xiao-Yong

2015-07-01

Low-cost synthesis of high-quality ZnS films on silicon wafers is of much importance to the ZnSbased heterojunction blue light-emitting device integrated with silicon. Thus, a series of ZnS films were chemically synthesized at low cost on Si(100) wafers at 353 K under a mixed acidic solution with a pH of 4 with zinc acetate and thioacetamide as precursors and with ethylenediamine and hydrochloric acid as the complexing agent and the pH value modifier, respectively. The effects of the ethylenediamine concentration on the crystallization, surface morphology, and optical properties of the ZnS films were investigated by using X-ray diffractometry, scanning electron microscopy, spectrophotometry, and fluorescence spectroscopy. A mechanism for the formation of ZnS film under an acidic condition was also proposed. All of the ZnS films were polycrystalline in nature, with a dominant cubic phase and a small amounts of hexagonal phases. The crystallization and the surface pattern of the films were clearly improved with increasing ethylenediamine concentration due to its enhanced complexing role. The absorption edge of the films almost underwent a blue shift with increasing ethylenediamine concentration, which was largely attributed to the quantum confinement effects caused by the small particle size of the polycrystalline ZnS films. Defect species and the corresponding strengths of the ZnS films were strongly affected by the ethylenediamine concentration.

Method for forming silicon on a glass substrate

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method by which single-crystal silicon microelectronics may be fabricated on glass substrates at unconventionally low temperatures. This is achieved by fabricating a thin film of silicon on glass and subsequently forming the doped components by a short wavelength (excimer) laser doping procedure and conventional patterning techniques. This method may include introducing a heavily boron doped etch stop layer on a silicon wafer using an excimer laser, which permits good control of the etch stop layer removal process. This method additionally includes dramatically reducing the remaining surface roughness of the silicon thin films after etching in the fabrication of silicon on insulator wafers by scanning an excimer laser across the surface of the silicon thin film causing surface melting, whereby the surface tension of the melt causes smoothing of the surface during recrystallization. Applications for this method include those requiring a transparent or insulating substrate, such as display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard and high temperature electronics.

Method for forming silicon on a glass substrate

DOEpatents

McCarthy, A.M.

1995-03-07

A method by which single-crystal silicon microelectronics may be fabricated on glass substrates at unconventionally low temperatures. This is achieved by fabricating a thin film of silicon on glass and subsequently forming the doped components by a short wavelength (excimer) laser doping procedure and conventional patterning techniques. This method may include introducing a heavily boron doped etch stop layer on a silicon wafer using an excimer laser, which permits good control of the etch stop layer removal process. This method additionally includes dramatically reducing the remaining surface roughness of the silicon thin films after etching in the fabrication of silicon on insulator wafers by scanning an excimer laser across the surface of the silicon thin film causing surface melting, whereby the surface tension of the melt causes smoothing of the surface during recrystallization. Applications for this method include those requiring a transparent or insulating substrate, such as display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard and high temperature electronics. 15 figs.

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Mizubayashi, Wataru; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Masahara, Meishoku

2014-01-01

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (Vt) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal-oxide-nitride-oxide-silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial Vt roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (Lg) is scaled down to 46 nm or less.

Lamb wave propagation in monocrystalline silicon wafers.

PubMed

Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

2018-01-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

Micro-Raman spectroscopy as a tool for the characterization of silicon carbide in power semiconductor material processing

NASA Astrophysics Data System (ADS)

De Biasio, M.; Kraft, M.; Schultz, M.; Goller, B.; Sternig, D.; Esteve, R.; Roesner, M.

2017-05-01

Silicon carbide (SiC) is a wide band-gap semi-conductor material that is used increasingly for high voltage power devices, since it has a higher breakdown field strength and better thermal conductivity than silicon. However, in particular its hardness makes wafer processing difficult and many standard semi-conductor processes have to be specially adapted. We measure the effects of (i) mechanical processing (i.e. grinding of the backside) and (ii) chemical and thermal processing (i.e. doping and annealing), using confocal microscopy to measure the surface roughness of ground wafers and micro-Raman spectroscopy to measure the stresses induced in the wafers by grinding. 4H-SiC wafers with different dopings were studied before and after annealing, using depth-resolved micro-Raman spectroscopy to observe how doping and annealing affect: i.) the damage and stresses induced on the crystalline structure of the samples and ii.) the concentration of free electrical carriers. Our results show that mechanical, chemical and thermal processing techniques have effects on this semiconductor material that can be observed and characterized using confocal microscopy and high resolution micro Raman spectroscopy.

Studying post-etching silicon crystal defects on 300mm wafer by automatic defect review AFM

NASA Astrophysics Data System (ADS)

Zandiatashbar, Ardavan; Taylor, Patrick A.; Kim, Byong; Yoo, Young-kook; Lee, Keibock; Jo, Ahjin; Lee, Ju Suk; Cho, Sang-Joon; Park, Sang-il

2016-03-01

Single crystal silicon wafers are the fundamental elements of semiconductor manufacturing industry. The wafers produced by Czochralski (CZ) process are very high quality single crystalline materials with known defects that are formed during the crystal growth or modified by further processing. While defects can be unfavorable for yield for some manufactured electrical devices, a group of defects like oxide precipitates can have both positive and negative impacts on the final device. The spatial distribution of these defects may be found by scattering techniques. However, due to limitations of scattering (i.e. light wavelength), many crystal defects are either poorly classified or not detected. Therefore a high throughput and accurate characterization of their shape and dimension is essential for reviewing the defects and proper classification. While scanning electron microscopy (SEM) can provide high resolution twodimensional images, atomic force microscopy (AFM) is essential for obtaining three-dimensional information of the defects of interest (DOI) as it is known to provide the highest vertical resolution among all techniques [1]. However AFM's low throughput, limited tip life, and laborious efforts for locating the DOI have been the limitations of this technique for defect review for 300 mm wafers. To address these limitations of AFM, automatic defect review AFM has been introduced recently [2], and is utilized in this work for studying DOI on 300 mm silicon wafer. In this work, we carefully etched a 300 mm silicon wafer with a gaseous acid in a reducing atmosphere at a temperature and for a sufficient duration to decorate and grow the crystal defects to a size capable of being detected as light scattering defects [3]. The etched defects form a shallow structure and their distribution and relative size are inspected by laser light scattering (LLS). However, several groups of defects couldn't be properly sized by the LLS due to the very shallow depth and low light scattering. Likewise, SEM cannot be used effectively for post-inspection defect review and classification of these very shallow types of defects. To verify and obtain accurate shape and three-dimensional information of those defects, automatic defect review AFM (ADR AFM) is utilized for accurate locating and imaging of DOI. In ADR AFM, non-contact mode imaging is used for non-destructive characterization and preserving tip sharpness for data repeatability and reproducibility. Locating DOI and imaging are performed automatically with a throughput of many defects per hour. Topography images of DOI has been collected and compared with SEM images. The ADR AFM has been shown as a non-destructive metrology tool for defect review and obtaining three-dimensional topography information.

Thin EFG octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-01-01

Mobil Solar Energy Corporation currently practices a unique crystal growth technology for producing crystalline silicon sheet, which is then cut with lasers into wafers. The wafers are processed into solar cells and incorporated into modules for photovoltaic applications. The silicon sheet is produced using a method known as Edge-defined Film-fed growth (EFG), in the form of hollow eight-sided polygons (octagons) with 10 cm faces. These are grown to lengths of 5 meters and thickness of 300 microns, with continuous melt replenishment, in compact furnaces designed to operate at a high sheet area production area of 135 sq cm/min. The present Photovoltaic Manufacturing Technology (PVMaT) three-year program seeks to advance the manufacturing line capabilities of the Mobil Solar crystal growth and cutting technologies. If successful, these advancements will provide significant reductions in already low silicon raw material usage, improve process productivity, laser cutting throughput and yield, and so lower both individual wafer cost and the cost of module production. This report summarizes the significant technical improvements in EFG technology achieved in Phase 1 of this program. Technical results are reported for each of the three main program areas: (1) thin octagon growth (crystal growth) -- to reduce the thickness of the octagon to an interim goal of 250 microns during Phase 1, with an ultimate goal of achieving 200 micron thicknesses; (2) laser cutting -- to improve the laser cutting process, so as to produce wafers with decreased laser cutting damage at increased wafer throughput rates; and (3) process control and product specification -- to implement advanced strategies in crystal growth process control and productivity designed to increase wafer yields.

Unveiling the Formation Pathway of Single Crystalline Porous Silicon Nanowires

PubMed Central

Zhong, Xing; Qu, Yongquan; Lin, Yung-Chen; Liao, Lei; Duan, Xiangfeng

2011-01-01

Porous silicon nanowire is emerging as an interesting material system due to its unique combination of structural, chemical, electronic, and optical properties. To fully understand their formation mechanism is of great importance for controlling the fundamental physical properties and enabling potential applications. Here we present a systematic study to elucidate the mechanism responsible for the formation of porous silicon nanowires in a two-step silver-assisted electroless chemical etching method. It is shown that silicon nanowire arrays with various porosities can be prepared by varying multiple experimental parameters such as the resistivity of the starting silicon wafer, the concentration of oxidant (H2O2) and the amount of silver catalyst. Our study shows a consistent trend that the porosity increases with the increasing wafer conductivity (dopant concentration) and oxidant (H2O2) concentration. We further demonstrate that silver ions, formed by the oxidation of silver, can diffuse upwards and re-nucleate on the sidewalls of nanowires to initiate new etching pathways to produce porous structure. The elucidation of this fundamental formation mechanism opens a rational pathway to the production of wafer-scale single crystalline porous silicon nanowires with tunable surface areas ranging from 370 m2·g−1 to 30 m2·g−1, and can enable exciting opportunities in catalysis, energy harvesting, conversion, storage, as well as biomedical imaging and therapy. PMID:21244020

Effects of laser fluence on silicon modification by four-beam laser interference

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhao, Le; Li, Dayou; JR3CN and IRAC, University of Bedfordshire, Luton LU1 3JU

2015-12-21

This paper discusses the effects of laser fluence on silicon modification by four-beam laser interference. In this work, four-beam laser interference was used to pattern single crystal silicon wafers for the fabrication of surface structures, and the number of laser pulses was applied to the process in air. By controlling the parameters of laser irradiation, different shapes of silicon structures were fabricated. The results were obtained with the single laser fluence of 354 mJ/cm{sup 2}, 495 mJ/cm{sup 2}, and 637 mJ/cm{sup 2}, the pulse repetition rate of 10 Hz, the laser exposure pulses of 30, 100, and 300, the laser wavelength of 1064 nm, andmore » the pulse duration of 7–9 ns. The effects of the heat transfer and the radiation of laser interference plasma on silicon wafer surfaces were investigated. The equations of heat flow and radiation effects of laser plasma of interfering patterns in a four-beam laser interference distribution were proposed to describe their impacts on silicon wafer surfaces. The experimental results have shown that the laser fluence has to be properly selected for the fabrication of well-defined surface structures in a four-beam laser interference process. Laser interference patterns can directly fabricate different shape structures for their corresponding applications.« less

Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

NASA Astrophysics Data System (ADS)

Kulshreshtha, Prashant Kumar

This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu-precipitates (upto 50 nm) compresses Si-lattice to facilitate Si-XII/III formations, i.e. high pressure ductile phases. Sweeping voltage measurements at a given load determine that Si lattice has to be stressed beyond 1 mN to complete the Si-I (semiconducting) to Si-II (ohmic) phase changes. Above 1 mN load DSB sample has a varistor-like behavior due to higher grain-boundary resistance from interfacial states. The precipitate defect structure stimulated stresses at the bulk Si lattice or grain boundary modify the rate of elastic energy release at the crack-tip and associated phase change and hardness values in response to external loading. The systematic approach in this thesis elucidates that the interfacial surface area between Si-lattice and precipitate plays pivotal role in defining extent of stresses in the silicon, i.e. smaller precipitates in higher densities are severe than few larger volume precipitates. The finding of high-pressure ductile phase formation during loading of compressed silicon structure has been suggested to PV industry as a prospective candidate for reducing the wafer breakage and allowing larger handling stresses.

Design and fabrication of piezoresistive p-SOI Wheatstone bridges for high-temperature applications

NASA Astrophysics Data System (ADS)

Kähler, Julian; Döring, Lutz; Merzsch, Stephan; Stranz, Andrej; Waag, Andreas; Peiner, Erwin

2011-06-01

For future measurements while depth drilling, commercial sensors are required for a temperature range from -40 up to 300 °C. Conventional piezoresistive silicon sensors cannot be used at higher temperatures due to an exponential increase of leakage currents which results in a drop of the bridge voltage. A well-known procedure to expand the temperature range of silicon sensors and to reduce leakage currents is to employ Silicon-On-Insulator (SOI) instead of standard wafer material. Diffused resistors can be operated up to 200 °C, but show the same problems beyond due to leakage of the p-njunction. Our approach is to use p-SOI where resistors as well as interconnects are defined by etching down to the oxide layer. Leakage is suppressed and the temperature dependence of the bridges is very low (TCR = (2.6 +/- 0.1) μV/K@1 mA up to 400 °C). The design and process flow will be presented in detail. The characteristics of Wheatstone bridges made of silicon, n- SOI, and p-SOI will be shown for temperatures up to 300 °C. Besides, thermal FEM-simulations will be described revealing the effect of stress between silicon and the silicon-oxide layer during temperature cycling.

Uncertainty of a hybrid surface temperature sensor for silicon wafers and comparison with an embedded thermocouple.

PubMed

Iuchi, Tohru; Gogami, Atsushi

2009-12-01

We have developed a user-friendly hybrid surface temperature sensor. The uncertainties of temperature readings associated with this sensor and a thermocouple embedded in a silicon wafer are compared. The expanded uncertainties (k=2) of the hybrid temperature sensor and the embedded thermocouple are 2.11 and 2.37 K, respectively, in the temperature range between 600 and 1000 K. In the present paper, the uncertainty evaluation and the sources of uncertainty are described.

Space optics with silicon wafers and slumped glass

NASA Astrophysics Data System (ADS)

Hudec, R.; Semencova, V.; Inneman, A.; Skulinova, M.; Sveda, L.; Míka, M.; Sik, J.; Lorenc, M.

2017-11-01

The future space X-ray astronomy imaging missions require very large collecting areas at still fine angular resolution and reasonable weight. The novel substrates for X-ray mirrors such as Silicon wafers and thin thermally formed glass enable wide applications of precise and very light weight (volume densities 2.3 to 2.5 gcm-3) optics. The recent status of novel technologies as well as developed test samples with emphasis on precise optical surfaces based on novel materials and their space applications is presented and discussed.

Theoretical analysis of improved efficiency of silicon-wafer solar cells with textured nanotriangular grating structure

NASA Astrophysics Data System (ADS)

Zhang, Yaoju; Zheng, Jun; Zhao, Xuesong; Ruan, Xiukai; Cui, Guihua; Zhu, Haiyong; Dai, Yuxing

2018-03-01

A practical model of crystalline silicon-wafer solar cells is proposed in order to enhance the light absorption and improve the conversion efficiency of silicon solar cells. In the model, the front surface of the silicon photovoltaic film is designed to be a textured-triangular-grating (TTG) structure, and the ITO contact film and the antireflection coating (ARC) of glass are coated on the TTG surface of silicon solar cells. The optical absorption spectrum of solar cells are simulated by applying the finite difference time domain method. Electrical parameters of the solar cells are calculated using two models with and without carrier loss. The effect of structure parameters on the performance of the TTG cell is discussed in detail. It is found that the thickness (tg) of the ARC, period (p) of grating, and base angle (θ) of triangle have a crucial influence on the conversion efficiency. The optimal structure of the TTG cell is designed. The TTG solar cell can produce higher efficiency in a wide range of solar incident angle and the average efficiency of the optimal TTG cell over 7:30-16:30 time of day is 8% higher than that of the optimal plane solar cell. In addition, the study shows that the bulk recombination of carriers has an influence on the conversion efficiency of the cell, the conversion efficiency of the actual solar cell with carrier recombination is reduced by 20.0% of the ideal cell without carrier recombination.

Development of plasma chemical vaporization machining

NASA Astrophysics Data System (ADS)

Mori, Yuzo; Yamauchi, Kazuto; Yamamura, Kazuya; Sano, Yasuhisa

2000-12-01

Conventional machining processes, such as turning, grinding, or lapping are still applied for many materials including functional ones. But those processes are accompanied with the formation of a deformed layer, so that machined surfaces cannot perform their original functions. In order to avoid such points, plasma chemical vaporization machining (CVM) has been developed. Plasma CVM is a chemical machining method using neutral radicals, which are generated by the atmospheric pressure plasma. By using a rotary electrode for generation of plasma, a high density of neutral radicals was formed, and we succeeded in obtaining high removal rate of several microns to several hundred microns per minute for various functional materials such as fused silica, single crystal silicon, molybdenum, tungsten, silicon carbide, and diamond. Especially, a high removal rate equal to lapping in the mechanical machining of fused silica and silicon was realized. 1.4 nm (p-v) was obtained as a surface roughness in the case of machining a silicon wafer. The defect density of a silicon wafer surface polished by various machining method was evaluated by the surface photo voltage spectroscopy. As a result, the defect density of the surface machined by plasma CVM was under 1/100 in comparison with the surface machined by mechanical polishing and argon ion sputtering, and very low defect density which was equivalent to the chemical etched surface was realized. A numerically controlled CVM machine for x-ray mirror fabrication is detailed in the accompanying article in this issue.

Correlation of 150-mm silicon wafer site flatness with stepper performance for deep submicron applications

NASA Astrophysics Data System (ADS)

Huff, Howard R.; Vigil, Joseph C.; Kuyel, Birol; Chan, David Y.; Nguyen, Long P.

1992-06-01

An experimental study was conducted to correlate wafer site flatness SFQD with stepper performance for half-micron lines and spaces. CD measurements were taken on wafers patterned on both GCA pre-production XLS i-line and SVGL Micrascan-90 DUV steppers as well as focus measurements on the Micrascan-90. Wafer site flatness SFQD less than 0.3 micrometers was observed to be a sufficiently small variable in CD non-uniformities for these initial half-micron stepper applications.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, A.M.

1997-10-07

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50 C or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense. 57 figs.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, Anthony M.

1997-01-01

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50.degree. C. or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense.

Structured Antireflective Coating for Silicon at Submillimeter Frequencies

NASA Astrophysics Data System (ADS)

Padilla, Estefania

2018-01-01

Observations at millimeter and submillimeter wavelengths are useful for many astronomical studies, such as the polarization of the cosmic microwave background or the formation and evolution of galaxy clusters. In order to allow observations over a broad spectral bandwidth (approximatively from 70 to 420 GHz), innovative broadband anti-reflective (AR) optics must be utilized in submillimeter telescopes. Due to its low loss and high refractive index, silicon is a fine optical material at these frequencies, but an AR coating with multiple layers is required to maximize its transmission over a wide bandwidth. Structured multilayer AR coatings for silicon are currently being developed at Caltech and JPL. The development process includes the design of the structured layers with commercial electromagnetic simulation software, the fabrication by using deep reactive ion etching, and the test of the transmission and reflection of the patterned wafers. Geometrical 3D patterns have successfully been etched at the surface of the silicon wafers creating up to 2 layers with different effective refractive indices. The transmission and reflection of single AR layer wafers, measured between 75 and 330 GHz, are close to the simulation predictions. These results allow the development of new designs with 5 or 6 AR layers in order to improve the bandwidth and transmission of the silicon AR coatings.

Phosphorus out-diffusion in laser molten silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Köhler, J. R.; Eisele, S. J.

2015-04-14

Laser doping via liquid phase diffusion enables the formation of defect free pn junctions and a tailoring of diffusion profiles by varying the laser pulse energy density and the overlap of laser pulses. We irradiate phosphorus diffused 100 oriented p-type float zone silicon wafers with a 5 μm wide line focused 6.5 ns pulsed frequency doubled Nd:YVO{sub 4} laser beam, using a pulse to pulse overlap of 40%. By varying the number of laser scans N{sub s} = 1, 2, 5, 10, 20, 40 at constant pulse energy density H = 1.3 J/cm{sup 2} and H = 0.79 J/cm{sup 2} we examine the out-diffusion of phosphorus atoms performing secondary ionmore » mass spectroscopy concentration measurements. Phosphorus doping profiles are calculated by using a numerical simulation tool. The tool models laser induced melting and re-solidification of silicon as well as the out-diffusion of phosphorus atoms in liquid silicon during laser irradiation. We investigate the observed out-diffusion process by comparing simulations with experimental concentration measurements. The result is a pulse energy density independent phosphorus out-diffusion velocity v{sub out} = 9 ± 1 cm/s in liquid silicon, a partition coefficient of phosphorus 1 < k{sub p} < 1.1 and a diffusion coefficient D = 1.4(±0.2)cm{sup 2}/s × 10{sup −3 }× exp[−183 meV/(k{sub B}T)].« less

Synthesis and characterization of porous silicon as hydroxyapatite host matrix of biomedical applications.

PubMed

Dussan, A; Bertel, S D; Melo, S F; Mesa, F

2017-01-01

In this work, porous-silicon samples were prepared by electrochemical etching on p-type (B-doped) Silicon (Si) wafers. Hydrofluoric acid (HF)-ethanol (C2H5OH) [HF:Et] and Hydrofluoric acid (HF)-dimethylformamide (DMF-C3H7NO) [HF:DMF] solution concentrations were varied between [1:2]-[1:3] and [1:7]-[1:9], respectively. Effects of synthesis parameters, like current density, solution concentrations, reaction time, on morphological properties were studied by scanning electron microscopy (SEM) and atomic force microscopy (AFM) measurements. Pore sizes varying from 20 nm to micrometers were obtained for long reaction times and [HF:Et] [1:2] concentrations; while pore sizes in the same order were observed for [HF:DMF] [1:7], but for shorter reaction time. Greater surface uniformity and pore distribution was obtained for a current density of around 8 mA/cm2 using solutions with DMF. A correlation between reflectance measurements and pore size is presented. The porous-silicon samples were used as substrate for hydroxyapatite growth by sol-gel method. X-ray diffraction (XRD) and SEM were used to characterize the layers grown. It was found that the layer topography obtained on PS samples was characterized by the evidence of Hydroxyapatite in the inter-pore regions and over the surface.

Synthesis and characterization of porous silicon as hydroxyapatite host matrix of biomedical applications

PubMed Central

Dussan, A.; Bertel, S. D.; Melo, S. F.

2017-01-01

In this work, porous-silicon samples were prepared by electrochemical etching on p-type (B-doped) Silicon (Si) wafers. Hydrofluoric acid (HF)-ethanol (C2H5OH) [HF:Et] and Hydrofluoric acid (HF)-dimethylformamide (DMF-C3H7NO) [HF:DMF] solution concentrations were varied between [1:2]—[1:3] and [1:7]—[1:9], respectively. Effects of synthesis parameters, like current density, solution concentrations, reaction time, on morphological properties were studied by scanning electron microscopy (SEM) and atomic force microscopy (AFM) measurements. Pore sizes varying from 20 nm to micrometers were obtained for long reaction times and [HF:Et] [1:2] concentrations; while pore sizes in the same order were observed for [HF:DMF] [1:7], but for shorter reaction time. Greater surface uniformity and pore distribution was obtained for a current density of around 8 mA/cm2 using solutions with DMF. A correlation between reflectance measurements and pore size is presented. The porous-silicon samples were used as substrate for hydroxyapatite growth by sol-gel method. X-ray diffraction (XRD) and SEM were used to characterize the layers grown. It was found that the layer topography obtained on PS samples was characterized by the evidence of Hydroxyapatite in the inter-pore regions and over the surface. PMID:28291792

Corrosion inhibitors for water-base slurry in multiblade sawing

NASA Technical Reports Server (NTRS)

Chen, C. P.; Odonnell, T. P.

1982-01-01

The use of a water-base slurry instead of the standard PC oil vehicle was proposed for multiblade sawing (MBS) silicon wafering technology. Potential cost savings were considerable; however, significant failures of high-carbon steel blades were observed in limited tests using a water-based slurry during silicon wafering. Failures were attributed to stress corrosion. A specially designed fatigue test of 1095 steel blades in distilled water with various corrosion inhibitor solutions was used to determine the feasibility of using corrosion inhibitors in water-base MBS wafering. Fatigue tests indicate that several corrosion inhibitors have significant potential for use in a water-base MBS operation. Blade samples tested in these specific corrosion-inhibitor solutions exhibited considerably greater lifetime than those blades tested in PC oil.

Contacting graphene in a 200 mm wafer silicon technology environment

NASA Astrophysics Data System (ADS)

Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

2018-06-01

Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

PubMed

Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

2018-08-01

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

Effect of dose and size on defect engineering in carbon cluster implanted silicon wafers

NASA Astrophysics Data System (ADS)

Okuyama, Ryosuke; Masada, Ayumi; Shigematsu, Satoshi; Kadono, Takeshi; Hirose, Ryo; Koga, Yoshihiro; Okuda, Hidehiko; Kurita, Kazunari

2018-01-01

Carbon-cluster-ion-implanted defects were investigated by high-resolution cross-sectional transmission electron microscopy toward achieving high-performance CMOS image sensors. We revealed that implantation damage formation in the silicon wafer bulk significantly differs between carbon-cluster and monomer ions after implantation. After epitaxial growth, small and large defects were observed in the implanted region of carbon clusters. The electron diffraction pattern of both small and large defects exhibits that from bulk crystalline silicon in the implanted region. On the one hand, we assumed that the silicon carbide structure was not formed in the implanted region, and small defects formed because of the complex of carbon and interstitial silicon. On the other hand, large defects were hypothesized to originate from the recrystallization of the amorphous layer formed by high-dose carbon-cluster implantation. These defects are considered to contribute to the powerful gettering capability required for high-performance CMOS image sensors.

Crystal structure of laser-induced subsurface modifications in Si

DOE Office of Scientific and Technical Information (OSTI.GOV)

Verburg, P. C.; Smillie, L. A.; Römer, G. R. B. E.

2015-06-04

Laser-induced subsurface modification of dielectric materials is a well-known technology. Applications include the production of optical components and selective etching. In addition to dielectric materials, the subsurface modification technology can be applied to silicon, by employing near to mid-infrared radiation. An application of subsurface modifications in silicon is laser-induced subsurface separation, which is a method to separate wafers into individual dies. Other applications for which proofs of concept exist are the formation of waveguides and resistivity tuning. However, limited knowledge is available about the crystal structure of subsurface modifications in silicon. In this paper, we investigate the geometry and crystalmore » structure of laser-induced subsurface modifications in monocrystalline silicon wafers. Finally, in addition to the generation of lattice defects, we found that transformations to amorphous silicon and Si-iii/Si-xii occur as a result of the laser irradiation.« less

Fabrication of SOI structures with buried cavities using Si wafer direct bonding and electrochemical etch-stop

NASA Astrophysics Data System (ADS)

Chung, Gwiy-Sang

2003-10-01

This paper describes the fabrication of SOI structures with buried cavities using SDB and electrochemical etch-stop. These methods are suitable for thick membrane fabrication with accurate thickness, uniformity, and flatness. After a feed-through hole for supplied voltage and buried cavities was formed on a handle Si wafer with p-type, the handle wafer was bonded to an active Si wafer consisting of a p-type substrate with an n-type epitaxial layer corresponding to membrane thickness. The bonded pair was then thinned until electrochemical etch-stop occurred at the pn junction during electrochemical etchback. By using the SDB SOI structure with buried cavities, active membranes, which have a free standing structure with a dimension of 900×900 μm2, were fabricated. It is confirmed that the fabrication process of the SDB SOI structure with buried cavities is a powerful and versatile technology for new MEMS applications.

Contactless measurement of electrical conductivity of semiconductor wafers using the reflection of millimeter waves

NASA Astrophysics Data System (ADS)

Ju, Yang; Inoue, Kojiro; Saka, Masumi; Abe, Hiroyuki

2002-11-01

We present a method for quantitative measurement of electrical conductivity of semiconductor wafers in a contactless fashion by using millimeter waves. A focusing sensor was developed to focus a 110 GHz millimeter wave beam on the surface of a silicon wafer. The amplitude and the phase of the reflection coefficient of the millimeter wave signal were measured by which electrical conductivity of the wafer was determined quantitatively, independent of the permittivity and thickness of the wafers. The conductivity obtained by this method agrees well with that measured by the conventional four-point-probe method.

Automated array assembly task development of low-cost polysilicon solar cells

NASA Technical Reports Server (NTRS)

Jones, G. T.

1980-01-01

Development of low cost, large area polysilicon solar cells was conducted in this program. Three types of polysilicon materialk were investigated. A theoretical and experimenal comparison between single crystal silicon and polysilicon solar cell efficiency was performed. Significant electrical performance differences were observed between types of wafer material, i.e. fine grain and coarse grain polysilicon and single crystal silicon. Efficiency degradation due to grain boundaries in fin grain and coarse grain polysilicon was shown to be small. It was demonstrated that 10 percent efficient polysilicon solar cells can be produced with spray on n+ dopants. This result fulfills an important goal of this project, which is the production of batch quantity of 10 percent efficient polysilicon solar cells.

The development of 8 inch roll-to-plate nanoimprint lithography (8-R2P-NIL) system

NASA Astrophysics Data System (ADS)

Lee, Lai Seng; Mohamed, Khairudin; Ooi, Su Guan

2017-07-01

Growth in semiconductor and integrated circuit industry was observed in the past decennium of years for industrial technology which followed Moore's law. The line width of nanostructure to be exposed was influenced by the essential technology of photolithography. Thus, it is crucial to have a low cost and high throughput manufacturing process for nanostructures. Nanoimprint Lithography technique invented by Stephen Y. Chou was considered as major nanolithography process to be used in future integrated circuit and integrated optics. The drawbacks of high imprint pressure, high imprint temperature, air bubbles formation, resist sticking to mold and low throughput of thermal nanoimprint lithography on silicon wafer have yet to be solved. Thus, the objectives of this work is to develop a high throughput, low imprint force, room temperature UV assisted 8 inch roll to plate nanoimprint lithography system capable of imprinting nanostructures on 200 mm silicon wafer using roller imprint with flexible mold. A piece of resist spin coated silicon wafer was placed onto vacuum chuck drives forward by a stepper motor. A quartz roller wrapped with a piece of transparent flexible mold was used as imprint roller. The imprinted nanostructures were cured by 10 W, 365 nm UV LED which situated inside the quartz roller. Heat generated by UV LED was dissipated by micro heat pipe. The flexible mold detaches from imprinted nanostructures in a 'line peeling' pattern and imprint pressure was measured by ultra-thin force sensors. This system has imprinting speed capability ranging from 0.19 mm/s to 5.65 mm/s, equivalent to imprinting capability of 3 to 20 pieces of 8 inch wafers per hour. Speed synchronization between imprint roller and vacuum chuck was achieved by controlling pulse rate supplied to stepper motor which drive the vacuum chuck. The speed different ranging from 2 nm/s to 98 nm/s is achievable. Vacuum chuck height was controlled by stepper motor with displacement of 5 nm/step.

Utilization of Tabula Rasa to Stabilize Bulk Lifetimes in n-Cz Silicon for High-Performance Solar Cell Processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

LaSalvia, Vincenzo; Jensen, Mallory Ann; Youssef, Amanda

2016-11-21

We investigate a high temperature, high cooling-rate anneal Tabula Rasa (TR) and report its implications on n-type Czochralski-grown silicon (n-Cz Si) for photovoltaic fabrication. Tabula Rasa aims at dissolving and homogenizing oxygen precipitate nuclei that can grow during the cell process steps and degrade the cell performance due to their high internal gettering and recombination activity. The Tabula Rasa thermal treatment is performed in a clean tube furnace with cooling rates >100 degrees C/s. We characterize the bulk lifetime by Sinton lifetime and photoluminescence mapping just after Tabula Rasa, and after the subsequent cell processing. After TR, the bulk lifetimemore » surprisingly degrades to <; 0.1ms, only to recover to values equal or higher than the initial non-treated wafer (several ms), after typical high temperature cell process steps. Those include boron diffusion and oxidation; phosphorus diffusion/oxidation; ambient annealing at 850 degrees C; and crystallization annealing of tunneling-passivating contacts (doped polycrystalline silicon on 1.5 nm thermal oxide). The drastic lifetime improvement during high temperature cell processing is attributed to improved external gettering of metal impurities and annealing of intrinsic point defects. Time and injection dependent lifetime spectroscopy further reveals the mechanisms of lifetime improvement after Tabula Rasa treatment. Additionally, we report the efficacy of Tabula Rasa on n-type Cz-Si wafers and its dependence on oxygen concentration, correlated to position within the ingot.« less

Multijunction high-voltage solar cell

NASA Technical Reports Server (NTRS)

Evans, J. C., Jr.; Goradia, C.; Chai, A. T.

1981-01-01

Multijunction cell allows for fabrication of high-voltage solar cell on single semiconductor wafer. Photovoltaic energy source using cell is combined on wafer with circuit it is to power. Cell consists of many voltage-generating regions internally or externally interconnected to give desired voltage and current combination. For computer applications, module is built on silicon wafer with energy for internal information processing and readouts derived from external light source.

Depth profiles of oxygen precipitates in nitride-coated silicon wafers subjected to rapid thermal annealing

NASA Astrophysics Data System (ADS)

Voronkov, V. V.; Falster, R.; Kim, TaeHyeong; Park, SoonSung; Torack, T.

2013-07-01

Silicon wafers, coated with a silicon nitride layer and subjected to high temperature Rapid Thermal Annealing (RTA) in Ar, show—upon a subsequent two-step precipitation anneal cycle (such as 800 °C + 1000 °C)—peculiar depth profiles of oxygen precipitate densities. Some profiles are sharply peaked near the wafer surface, sometimes with a zero bulk density. Other profiles are uniform in depth. The maximum density is always the same. These profiles are well reproduced by simulations assuming that precipitation starts from a uniformly distributed small oxide plates originated from RTA step and composed of oxygen atoms and vacancies ("VO2 plates"). During the first step of the precipitation anneal, an oxide layer propagates around this core plate by a process of oxygen attachment, meaning that an oxygen-only ring-shaped plate emerges around the original plate. These rings, depending on their size, then either dissolve or grow during the second part of the anneal leading to a rich variety of density profiles.

Material removal effect of microchannel processing by femtosecond laser

NASA Astrophysics Data System (ADS)

Zhang, Pan; Chen, Lei; Chen, Jianxiong; Tu, Yiliu

2017-11-01

Material processing using ultra-short-pulse laser is widely used in the field of micromachining, especially for the precision processing of hard and brittle materials. This paper reports a theoretical and experimental study of the ablation characteristics of a silicon wafer under micromachining using a femtosecond laser. The ablation morphology of the silicon wafer surface is surveyed by a detection test with an optical microscope. First, according to the relationship between the diameter of the ablation holes and the incident laser power, the ablation threshold of the silicon wafer is found to be 0.227 J/cm2. Second, the influence of various laser parameters on the size of the ablation microstructure is studied and the ablation morphology is analyzed. Furthermore, a mathematical model is proposed that can calculate the ablation depth per time for a given laser fluence and scanning velocity. Finally, a microchannel milling test is carried out on the micromachining center. The effectiveness and accuracy of the proposed models are verified by comparing the estimated depth to the actual measured results.

Effect of the Ti/Si ratio of spin coating solutions on surface passivation of crystalline silicon by TiO x -SiO x composite films

NASA Astrophysics Data System (ADS)

Yoshiba, Shuhei; Tanitsu, Katsuya; Suda, Yoshiyuki; Kamisako, Koichi

2017-06-01

Passivation films or antireflection coatings are generally prepared using costly vacuum or high-temperature processes. Thus, we report the preparation of TiO x -SiO x composite films by novel spin coatable solutions for the synthesis of low-cost passivation coating materials. The desired films were formed by varying the mixing ratios of TiO x and SiO x , and the resulting films exhibited excellent surface passivation properties. For the p-type wafer, an optimal effective surface recombination velocity (S eff) of 93 cm/s was achieved at \\text{TiO}x:\\text{SiO}x = 6:4, while a surface recombination current density (J 0s) of 195 fA/cm2 was obtained. In contrast, for the n-type wafer, an S eff of 27 cm/s and a J 0s of 38 fA/cm2 were achieved at \\text{TiO}x:\\text{SiO}x = 8:2. This excellent surface passivation effect could be attributed to the low interface state density and high positive fixed charge density. Furthermore, the thickness of the interfacial SiO x layer was determined to be important for obtaining the desired surface passivation effect.

Tuning the polarization-induced free hole density in nanowires graded from GaN to AlN

NASA Astrophysics Data System (ADS)

Golam Sarwar, A. T. M.; Carnevale, Santino D.; Kent, Thomas F.; Yang, Fan; McComb, David W.; Myers, Roberto C.

2015-01-01

We report a systematic study of p-type polarization-induced doping in graded AlGaN nanowire light emitting diodes grown on silicon wafers by plasma-assisted molecular beam epitaxy. The composition gradient in the p-type base is varied in a set of samples from 0.7%Al/nm to 4.95%Al/nm corresponding to negative bound polarization charge densities of 2.2 × 1018 cm-3 to 1.6 × 1019 cm-3. Capacitance measurements and energy band modeling reveal that for gradients greater than or equal to 1.30%Al/nm, the deep donor concentration is negligible and free hole concentrations roughly equal to the bound polarization charge density are achieved up to 1.6 × 1019 cm-3 at a gradient of 4.95%Al/nm. Accurate grading lengths in the p- and n-side of the pn-junction are extracted from scanning transmission electron microscopy images and are used to support energy band calculation and capacitance modeling. These results demonstrate the robust nature of p-type polarization doping in nanowires and put an upper bound on the magnitude of deep donor compensation.

Advanced process control and novel test methods for PVD silicon and elastomeric silicone coatings utilized on ion implant disks, heatsinks and selected platens

DOE Office of Scientific and Technical Information (OSTI.GOV)

Springer, J.; Allen, B.; Wriggins, W.

Coatings play multiple key roles in the proper functioning of mature and current ion implanters. Batch and serial implanters require strategic control of elemental and particulate contamination which often includes scrutiny of the silicon surface coatings encountering direct beam contact. Elastomeric Silicone Coatings must accommodate wafer loading and unloading as well as direct backside contact during implant plus must maintain rigid elemental and particulate specifications. The semiconductor industry has had a significant and continuous effort to obtain ultra-pure silicon coatings with sustained process performance and long life. Low particles and reduced elemental levels for silicon coatings are a major requirementmore » for process engineers, OEM manufacturers, and second source suppliers. Relevant data will be presented. Some emphasis and detail will be placed on the structure and characteristics of a relatively new PVD Silicon Coating process that is very dense and homogeneous. Wear rate under typical ion beam test conditions will be discussed. The PVD Silicon Coating that will be presented here is used on disk shields, wafer handling fingers/fences, exclusion zones of heat sinks, beam dumps and other beamline components. Older, legacy implanters can now provide extended process capability using this new generation PVD silicon - even on implanter systems that were shipped long before the advent of silicon coating for contamination control. Low particles and reduced elemental levels are critical performance criteria for the silicone elastomers used on disk heatsinks and serial implanter platens. Novel evaluation techniques and custom engineered tools are used to investigate the surface interaction characteristics of multiple Elastomeric Silicone Coatings currently in use by the industry - specifically, friction and perpendicular stiction. These parameters are presented as methods to investigate the critical wafer load and unload function. Unique tools and test methods have been developed that deliver accurate and repeatable data, which will be described.« less

Advanced process control and novel test methods for PVD silicon and elastomeric silicone coatings utilized on ion implant disks, heatsinks and selected platens

NASA Astrophysics Data System (ADS)

Springer, J.; Allen, B.; Wriggins, W.; Kuzbyt, R.; Sinclair, R.

2012-11-01

Coatings play multiple key roles in the proper functioning of mature and current ion implanters. Batch and serial implanters require strategic control of elemental and particulate contamination which often includes scrutiny of the silicon surface coatings encountering direct beam contact. Elastomeric Silicone Coatings must accommodate wafer loading and unloading as well as direct backside contact during implant plus must maintain rigid elemental and particulate specifications. The semiconductor industry has had a significant and continuous effort to obtain ultra-pure silicon coatings with sustained process performance and long life. Low particles and reduced elemental levels for silicon coatings are a major requirement for process engineers, OEM manufacturers, and second source suppliers. Relevant data will be presented. Some emphasis and detail will be placed on the structure and characteristics of a relatively new PVD Silicon Coating process that is very dense and homogeneous. Wear rate under typical ion beam test conditions will be discussed. The PVD Silicon Coating that will be presented here is used on disk shields, wafer handling fingers/fences, exclusion zones of heat sinks, beam dumps and other beamline components. Older, legacy implanters can now provide extended process capability using this new generation PVD silicon - even on implanter systems that were shipped long before the advent of silicon coating for contamination control. Low particles and reduced elemental levels are critical performance criteria for the silicone elastomers used on disk heatsinks and serial implanter platens. Novel evaluation techniques and custom engineered tools are used to investigate the surface interaction characteristics of multiple Elastomeric Silicone Coatings currently in use by the industry - specifically, friction and perpendicular stiction. These parameters are presented as methods to investigate the critical wafer load and unload function. Unique tools and test methods have been developed that deliver accurate and repeatable data, which will be described.

Experimental setup for camera-based measurements of electrically and optically stimulated luminescence of silicon solar cells and wafers.

PubMed

Hinken, David; Schinke, Carsten; Herlufsen, Sandra; Schmidt, Arne; Bothe, Karsten; Brendel, Rolf

2011-03-01

We report in detail on the luminescence imaging setup developed within the last years in our laboratory. In this setup, the luminescence emission of silicon solar cells or silicon wafers is analyzed quantitatively. Charge carriers are excited electrically (electroluminescence) using a power supply for carrier injection or optically (photoluminescence) using a laser as illumination source. The luminescence emission arising from the radiative recombination of the stimulated charge carriers is measured spatially resolved using a camera. We give details of the various components including cameras, optical filters for electro- and photo-luminescence, the semiconductor laser and the four-quadrant power supply. We compare a silicon charged-coupled device (CCD) camera with a back-illuminated silicon CCD camera comprising an electron multiplier gain and a complementary metal oxide semiconductor indium gallium arsenide camera. For the detection of the luminescence emission of silicon we analyze the dominant noise sources along with the signal-to-noise ratio of all three cameras at different operation conditions.

Graphene-Based Reversible Nano-Switch/Sensor Schottky Diode

NASA Technical Reports Server (NTRS)

Miranda, Felix A.; Meador, Michael A.; Theofylaktos, Onoufrios; Pinto, Nicholas J.; Mueller, Carl H.; Santos-Perez, Javier

2010-01-01

This proof-of-concept device consists of a thin film of graphene deposited on an electrodized doped silicon wafer. The graphene film acts as a conductive path between a gold electrode deposited on top of a silicon dioxide layer and the reversible side of the silicon wafer, so as to form a Schottky diode. By virtue of the two-dimensional nature of graphene, this device has extreme sensitivity to different gaseous species, thereby serving as a building block for a volatile species sensor, with the attribute of having reversibility properties. That is, the sensor cycles between active and passive sensing states in response to the presence or absence of the gaseous species.

films on silicon at different annealing temperatures

NASA Astrophysics Data System (ADS)

Zhao, Yan; Zhou, Chunlan; Zhang, Xiang; Zhang, Peng; Dou, Yanan; Wang, Wenjing; Cao, Xingzhong; Wang, Baoyi; Tang, Yehua; Zhou, Su

2013-03-01

Thermal atomic layer-deposited (ALD) aluminum oxide (Al2O3) acquires high negative fixed charge density ( Q f) and sufficiently low interface trap density after annealing, which enables excellent surface passivation for crystalline silicon. Q f can be controlled by varying the annealing temperatures. In this study, the effect of the annealing temperature of thermal ALD Al2O3 films on p-type Czochralski silicon wafers was investigated. Corona charging measurements revealed that the Q f obtained at 300°C did not significantly affect passivation. The interface-trapping density markedly increased at high annealing temperature (>600°C) and degraded the surface passivation even at a high Q f. Negatively charged or neutral vacancies were found in the samples annealed at 300°C, 500°C, and 750°C using positron annihilation techniques. The Al defect density in the bulk film and the vacancy density near the SiO x /Si interface region decreased with increased temperature. Measurement results of Q f proved that the Al vacancy of the bulk film may not be related to Q f. The defect density in the SiO x region affected the chemical passivation, but other factors may dominantly influence chemical passivation at 750°C.

The effect of thermal oxidation on the luminescence properties of nanostructured silicon.

PubMed

Liu, Lijia; Sham, Tsun-Kong

2012-08-06

Herein is reported a detailed study of the luminescence properties of nanostructured Si using X-ray excited optical luminescence (XEOL) in combination with X-ray absorption near-edge structures (XANES). P-type Si nanowires synthesized via electroless chemical etching from Si wafers of different doping levels and porous Si synthesized using electrochemical method are examined under X-ray excitation across the Si K-, L(3,2) -, and O K-edges. It is found that while as-prepared Si nanostructures are weak light emitters, intense visible luminescence is observed from thermally oxidized Si nanowires and porous Si. The luminescence mechanism of Si upon oxidation is investigated by oxidizing nanostructured Si at different temperatures. Interestingly, the two luminescence bands observed show different response with the variation of absorption coefficient upon Si and O core-electron excitation in elemental silicon and silicon oxide. A correlation between luminescence properties and electronic structures is thus established. The implications of the finding are discussed in terms of the behavior of the oxygen deficient center (OCD) and non-bridging oxygen hole center (NBOHC). Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Optical/thermal analysis methodology for a space-qualifiable RTP furnace

NASA Technical Reports Server (NTRS)

Bugby, D.; Dardarian, S.; Cole, E.

1993-01-01

A methodology to predict the coupled optical/thermal performance of a reflective cavity heating system was developed and a laboratory test to verify the method was carried out. The procedure was utilized to design a rapid thermal processing (RTP) furnace for the Robot-Operated Material Processing in Space (ROMPS) Program which is a planned STS HH-G canister experiment involving robotics and material processing in microgravity. The laboratory test employed a tungsten-halogen reflector/lamp to heat thin, p-type silicon wafers. Measurements instrumentation consisted of 5-mil Pt/Pt-Rh thermocouples and an optical pyrometer. The predicted results, utilizing an optical ray-tracing program and a lumped-capacitance thermal analyzer, showed good agreement with the measured data for temperatures exceeding 1300 C.

Investigation of dislocation cluster evolution during directional solidification of multicrystalline silicon

NASA Astrophysics Data System (ADS)

Oriwol, Daniel; Trempa, Matthias; Sylla, Lamine; Leipner, Hartmut S.

2017-04-01

Dislocation clusters are the main crystal defects in multicrystalline silicon and are detrimental for solar cell efficiency. They were formed during the silicon ingot casting due to the relaxation of strain energy. The evolution of the dislocation clusters was studied by means of automated analysing tools of the standard wafer and cell production giving information about the cluster development as a function of the ingot height. Due to the observation of the whole wafer surface the point of view is of macroscopic nature. It was found that the dislocations tend to build clusters of high density which usually expand in diameter as a function of ingot height. According to their structure the dislocation clusters can be divided into light and dense clusters. The appearance of both types shows a clear dependence on the orientation of the grain growth direction. Additionally, a process of annihilation of dislocation clusters during the crystallization has been observed. To complement the macroscopic description, the dislocation clusters were also investigates by TEM. It is shown that the dislocations within the subgrain boundaries are closely arranged. Distances of 40-30 nm were found. These results lead to the conclusion that the dislocation density within the cluster structure is impossible to quantify by means of etch pit counting.

Noninvasive, near-field terahertz imaging of hidden objects using a single-pixel detector.

PubMed

Stantchev, Rayko Ivanov; Sun, Baoqing; Hornett, Sam M; Hobson, Peter A; Gibson, Graham M; Padgett, Miles J; Hendry, Euan

2016-06-01

Terahertz (THz) imaging can see through otherwise opaque materials. However, because of the long wavelengths of THz radiation (λ = 400 μm at 0.75 THz), far-field THz imaging techniques suffer from low resolution compared to visible wavelengths. We demonstrate noninvasive, near-field THz imaging with subwavelength resolution. We project a time-varying, intense (>100 μJ/cm(2)) optical pattern onto a silicon wafer, which spatially modulates the transmission of synchronous pulse of THz radiation. An unknown object is placed on the hidden side of the silicon, and the far-field THz transmission corresponding to each mask is recorded by a single-element detector. Knowledge of the patterns and of the corresponding detector signal are combined to give an image of the object. Using this technique, we image a printed circuit board on the underside of a 115-μm-thick silicon wafer with ~100-μm (λ/4) resolution. With subwavelength resolution and the inherent sensitivity to local conductivity, it is possible to detect fissures in the circuitry wiring of a few micrometers in size. THz imaging systems of this type will have other uses too, where noninvasive measurement or imaging of concealed structures is necessary, such as in semiconductor manufacturing or in ex vivo bioimaging.

Making Wide-IF SIS Mixers with Suspended Metal-Beam Leads

NASA Technical Reports Server (NTRS)

Kaul, Anupama; Bumble, Bruce; Lee, Karen; LeDuc, Henry; Rice, Frank; Zmuidzinas, Jonas

2005-01-01

A process that employs silicon-on-insulator (SOI) substrates and silicon (Si) micromachining has been devised for fabricating wide-intermediate-frequency-band (wide-IF) superconductor/insulator/superconductor (SIS) mixer devices that result in suspended gold beam leads used for radio-frequency grounding. The mixers are formed on 25- m-thick silicon membranes. They are designed to operate in the 200 to 300 GHz frequency band, wherein wide-IF receivers for tropospheric- chemistry and astrophysical investigations are necessary. The fabrication process can be divided into three sections: 1. The front-side process, in which SIS devices with beam leads are formed on a SOI wafer; 2. The backside process, in which the SOI wafer is wax-mounted onto a carrier wafer, then thinned, then partitioned into individual devices; and 3. The release process, in which the individual devices are separated using a lithographic dicing technique. The total thickness of the starting 4-in. (10.16-cm)-diameter SOI wafer includes 25 m for the Si device layer, 0.5 m for the buried oxide (BOX) layer, and 350 m the for Si-handle layer. The front-side process begins with deposition of an etch-stop layer of SiO2 or AlN(x), followed by deposition of a Nb/Al- AlN(x) /Nb trilayer in a load-locked DC magnetron sputtering system. The lithography for four of a total of five layers is performed in a commercial wafer-stepping apparatus. Diagnostic test dies are patterned concurrently at certain locations on the wafer, alongside the mixer devices, using a different mask set. The conventional, self-aligned lift-off process is used to pattern the SIS devices up to the wire level.

Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer

PubMed Central

Yu, Yang; Fong, Patrick W. K.; Wang, Shifeng; Surya, Charles

2016-01-01

High quality wafer-scale free-standing WS2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS2, which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm2 at −1 V which shows superior performances compared to the directly grown WS2/GaN heterojunctions. PMID:27897210

Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer.

PubMed

Yu, Yang; Fong, Patrick W K; Wang, Shifeng; Surya, Charles

2016-11-29

High quality wafer-scale free-standing WS 2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS 2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS 2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS 2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS 2 , which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS 2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm 2 at -1 V which shows superior performances compared to the directly grown WS 2 /GaN heterojunctions.

Monitoring of degradation of porous silicon photonic crystals using digital photography

PubMed Central

2014-01-01

We report the monitoring of porous silicon (pSi) degradation in aqueous solutions using a consumer-grade digital camera. To facilitate optical monitoring, the pSi samples were prepared as one-dimensional photonic crystals (rugate filters) by electrochemical etching of highly doped p-type Si wafers using a periodic etch waveform. Two pSi formulations, representing chemistries relevant for self-reporting drug delivery applications, were tested: freshly etched pSi (fpSi) and fpSi coated with the biodegradable polymer chitosan (pSi-ch). Accelerated degradation of the samples in an ethanol-containing pH 10 aqueous basic buffer was monitored in situ by digital imaging with a consumer-grade digital camera with simultaneous optical reflectance spectrophotometric point measurements. As the nanostructured porous silicon matrix dissolved, a hypsochromic shift in the wavelength of the rugate reflectance peak resulted in visible color changes from red to green. While the H coordinate in the hue, saturation, and value (HSV) color space calculated using the as-acquired photographs was a good monitor of degradation at short times (t < 100 min), it was not a useful monitor of sample degradation at longer times since it was influenced by reflections of the broad spectral output of the lamp as well as from the narrow rugate reflectance band. A monotonic relationship was observed between the wavelength of the rugate reflectance peak and an H parameter value calculated from the average red-green-blue (RGB) values of each image by first independently normalizing each channel (R, G, and B) using their maximum and minimum value over the time course of the degradation process. Spectrophotometric measurements and digital image analysis using this H parameter gave consistent relative stabilities of the samples as fpSi > pSi-ch. PMID:25242902

Strain-Compensated InGaAsP Superlattices for Defect Reduction of InP Grown on Exact-Oriented (001) Patterned Si Substrates by Metal Organic Chemical Vapor Deposition.

PubMed

Megalini, Ludovico; Šuran Brunelli, Simone Tommaso; Charles, William O; Taylor, Aidan; Isaac, Brandon; Bowers, John E; Klamkin, Jonathan

2018-02-26

We report on the use of InGaAsP strain-compensated superlattices (SC-SLs) as a technique to reduce the defect density of Indium Phosphide (InP) grown on silicon (InP-on-Si) by Metal Organic Chemical Vapor Deposition (MOCVD). Initially, a 2 μm thick gallium arsenide (GaAs) layer was grown with very high uniformity on exact oriented (001) 300 mm Si wafers; which had been patterned in 90 nm V-grooved trenches separated by silicon dioxide (SiO₂) stripes and oriented along the [110] direction. Undercut at the Si/SiO₂ interface was used to reduce the propagation of defects into the III-V layers. Following wafer dicing; 2.6 μm of indium phosphide (InP) was grown on such GaAs-on-Si templates. InGaAsP SC-SLs and thermal annealing were used to achieve a high-quality and smooth InP pseudo-substrate with a reduced defect density. Both the GaAs-on-Si and the subsequently grown InP layers were characterized using a variety of techniques including X-ray diffraction (XRD); atomic force microscopy (AFM); transmission electron microscopy (TEM); and electron channeling contrast imaging (ECCI); which indicate high-quality of the epitaxial films. The threading dislocation density and RMS surface roughness of the final InP layer were 5 × 10⁸/cm² and 1.2 nm; respectively and 7.8 × 10⁷/cm² and 10.8 nm for the GaAs-on-Si layer.

Strain-Compensated InGaAsP Superlattices for Defect Reduction of InP Grown on Exact-Oriented (001) Patterned Si Substrates by Metal Organic Chemical Vapor Deposition

PubMed Central

Megalini, Ludovico; Šuran Brunelli, Simone Tommaso; Charles, William O.; Taylor, Aidan; Isaac, Brandon; Klamkin, Jonathan

2018-01-01

We report on the use of InGaAsP strain-compensated superlattices (SC-SLs) as a technique to reduce the defect density of Indium Phosphide (InP) grown on silicon (InP-on-Si) by Metal Organic Chemical Vapor Deposition (MOCVD). Initially, a 2 μm thick gallium arsenide (GaAs) layer was grown with very high uniformity on exact oriented (001) 300 mm Si wafers; which had been patterned in 90 nm V-grooved trenches separated by silicon dioxide (SiO2) stripes and oriented along the [110] direction. Undercut at the Si/SiO2 interface was used to reduce the propagation of defects into the III–V layers. Following wafer dicing; 2.6 μm of indium phosphide (InP) was grown on such GaAs-on-Si templates. InGaAsP SC-SLs and thermal annealing were used to achieve a high-quality and smooth InP pseudo-substrate with a reduced defect density. Both the GaAs-on-Si and the subsequently grown InP layers were characterized using a variety of techniques including X-ray diffraction (XRD); atomic force microscopy (AFM); transmission electron microscopy (TEM); and electron channeling contrast imaging (ECCI); which indicate high-quality of the epitaxial films. The threading dislocation density and RMS surface roughness of the final InP layer were 5 × 108/cm2 and 1.2 nm; respectively and 7.8 × 107/cm2 and 10.8 nm for the GaAs-on-Si layer. PMID:29495381

Nanoscale solely amorphous layer in silicon wafers induced by a newly developed diamond wheel

PubMed Central

Zhang, Zhenyu; Guo, Liangchao; Cui, Junfeng; Wang, Bo; Kang, Renke; Guo, Dongming

2016-01-01

Nanoscale solely amorphous layer is achieved in silicon (Si) wafers, using a developed diamond wheel with ceria, which is confirmed by high resolution transmission electron microscopy (HRTEM). This is different from previous reports of ultraprecision grinding, nanoindentation and nanoscratch, in which an amorphous layer at the top, followed by a crystalline damaged layer beneath. The thicknesses of amorphous layer are 43 and 48 nm at infeed rates of 8 and 15 μm/min, respectively, which is verified using HRTEM. Diamond-cubic Si-I phase is verified in Si wafers using selected area electron diffraction patterns, indicating the absence of high pressure phases. Ceria plays an important role in the diamond wheel for achieving ultrasmooth and bright surfaces using ultraprecision grinding. PMID:27734934

A method for determining average damage depth of sawn crystalline silicon wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, B.; Devayajanam, S.; Basnyat, P.

2016-04-01

The depth of surface damage (or simply, damage) in crystalline silicon wafers, caused by wire sawing of ingots, is determined by performing a series of minority carrier lifetime (MCLT) measurements. Samples are sequentially etched to remove thin layers from each surface and MCLT is measured after each etch step. The thickness-removed (..delta..t) at which the lifetime reaches a peak value corresponds to the damage depth. This technique also allows the damage to be quantified in terms of effective surface recombination velocity (Seff). To accomplish this, the MCLT data are converted into an Seff vs ..delta..t plot, which represents a quantitativemore » distribution of the degree of damage within the surface layer. We describe a wafer preparation procedure to attain reproducible etching and MCLT measurement results. We also describe important characteristics of an etchant used for controllably removing thin layers from the wafer surfaces. Some typical results showing changes in the MCLT vs ..delta..t plots for different cutting parameters are given.« less

GaN membrane MSM ultraviolet photodetectors

NASA Astrophysics Data System (ADS)

Muller, A.; Konstantinidis, G.; Kostopoulos, A.; Dragoman, M.; Neculoiu, D.; Androulidaki, M.; Kayambaki, M.; Vasilache, D.; Buiculescu, C.; Petrini, I.

2006-12-01

GaN exhibits unique physical properties, which make this material very attractive for wide range of applications and among them ultraviolet detection. For the first time a MSM type UV photodetector structure was manufactured on a 2.2 μm. thick GaN membrane obtained using micromachining techniques. The low unintentionally doped GaN layer structure was grown by MOCVD on high resistivity (ρ>10kΩcm) <111> oriented silicon wafers, 500μm thick. The epitaxially grown layers include a thin AlN layer in order to reduce the stress in the GaN layer and avoid cracking. Conventional contact lithography, e-gun Ni/Au (10nm /200nm) evaporation and lift-off techniques were used to define the interdigitated Schottky metalization on the top of the wafer. Ten digits with a width of 1μm and a length of 100μm were defined for each electrode. The distance between the digits was also 1μm. After the backside lapping of the wafer to a thickness of approximately 150μm, a 400nm thick Al layer was patterned and deposited on the backside, to be used as mask for the selective reactive ion etching of silicon. The backside mask, for the membrane formation, was patterned using double side alignment techniques and silicon was etched down to the 2.2μm thin GaN layer using SF 6 plasma. A very low dark current (30ρA at 3V) was obtained. Optical responsivity measurements were performed at 1.5V. A maximum responsivity of 18mA/W was obtained at a wavelength of 370nm. This value is very good and can be further improved using transparent contacts for the interdigitated structure.

Development of megasonic cleaning for silicon wafers

NASA Technical Reports Server (NTRS)

Mayer, A.

1980-01-01

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

PubMed

Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

2013-03-25

n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

I-line stepper based overlay evaluation method for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard front side resist in resist experiment. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated and exposed. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 µm SiGe:C BiCMOS technology. The developed technique also allows using significantly smaller alignment marks (i.e. standard FIA alignment marks). Furthermore, the presented method is used, in case of wafer bow related overlay tool problems, for the overlay evaluation of the last two metal layers from production wafers prepared in IHP's standard 0.25/0.13 µm SiGe:C BiCMOS technology. In conclusion, the exposure and measurement job can be done with the same tool, minimizing the back to front side/interface top layer misalignment which leads to a significant device performance improvement of backside/TSV integrated components and technologies.

Low-resistivity photon-transparent window attached to photo-sensitive silicon detector

DOEpatents

Holland, Stephen Edward

2000-02-15

The invention comprises a combination of a low resistivity, or electrically conducting, silicon layer that is transparent to long or short wavelength photons and is attached to the backside of a photon-sensitive layer of silicon, such as a silicon wafer or chip. The window is applied to photon sensitive silicon devices such as photodiodes, charge-coupled devices, active pixel sensors, low-energy x-ray sensors and other radiation detectors. The silicon window is applied to the back side of a photosensitive silicon wafer or chip so that photons can illuminate the device from the backside without interference from the circuit printed on the frontside. A voltage sufficient to fully deplete the high-resistivity photosensitive silicon volume of charge carriers is applied between the low-resistivity back window and the front, patterned, side of the device. This allows photon-induced charge created at the backside to reach the front side of the device and to be processed by any circuitry attached to the front side. Using the inventive combination, the photon sensitive silicon layer does not need to be thinned beyond standard fabrication methods in order to achieve full charge-depletion in the silicon volume. In one embodiment, the inventive backside window is applied to high resistivity silicon to allow backside illumination while maintaining charge isolation in CCD pixels.

Quantum-Well Infrared Photodetector (QWIP) Focal Plane Assembly

NASA Technical Reports Server (NTRS)

Jhabvala, Murzy; Jhabvala, Christine A.; Ewin, Audrey J.; Hess, Larry A.; Hartmann, Thomas M.; La, Anh T.

2012-01-01

A paper describes the Thermal Infrared Sensor (TIRS), a QWIP-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 microns. The focal plane will contain three 640x512 QWIP arrays mounted on a silicon substrate. The silicon substrate is a custom-fabricated carrier board with a single layer of aluminum interconnects. The general fabrication process starts with a 4-in. (approx.10-cm) diameter silicon wafer. The wafer is oxidized, a single substrate contact is etched, and aluminum is deposited, patterned, and alloyed. This technology development is aimed at incorporating three large-format infrared detecting arrays based on GaAs QWIP technology onto a common focal plane with precision alignment of all three arrays. This focal plane must survive the rigors of flight qualification and operate at a temperature of 43 K (-230 C) for five years while orbiting the Earth. The challenges presented include ensuring thermal compatibility among all the components, designing and building a compact, somewhat modular system and ensuring alignment to very tight levels. The multi-array focal plane integrated onto a single silicon substrate is a new application of both QWIP array development and silicon wafer scale integration. The Invar-based assembly has been tested to ensure thermal reliability.

Upgraded metallurgical-grade silicon solar cells with efficiency above 20%

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zheng, P.; Rougieux, F. E.; Samundsett, C.

We present solar cells fabricated with n-type Czochralski–silicon wafers grown with strongly compensated 100% upgraded metallurgical-grade feedstock, with efficiencies above 20%. The cells have a passivated boron-diffused front surface, and a rear locally phosphorus-diffused structure fabricated using an etch-back process. The local heavy phosphorus diffusion on the rear helps to maintain a high bulk lifetime in the substrates via phosphorus gettering, whilst also reducing recombination under the rear-side metal contacts. The independently measured results yield a peak efficiency of 20.9% for the best upgraded metallurgical-grade silicon cell and 21.9% for a control device made with electronic-grade float-zone silicon. The presencemore » of boron-oxygen related defects in the cells is also investigated, and we confirm that these defects can be partially deactivated permanently by annealing under illumination.« less

Reticle variation influence on manufacturing line and wafer device performance

NASA Astrophysics Data System (ADS)

Nistler, John L.; Spurlock, Kyle

1994-01-01

Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

NASA Astrophysics Data System (ADS)

Sun, Q. M.; Melnikov, A.; Mandelis, A.

2015-06-01

Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

Monolithic microchannel heatsink

DOEpatents

Benett, W.J.; Beach, R.J.; Ciarlo, D.R.

1996-08-20

A silicon wafer has slots sawn in it that allow diode laser bars to be mounted in contact with the silicon. Microchannels are etched into the back of the wafer to provide cooling of the diode bars. To facilitate getting the channels close to the diode bars, the channels are rotated from an angle perpendicular to the diode bars which allows increased penetration between the mounted diode bars. This invention enables the fabrication of monolithic silicon microchannel heatsinks for laser diodes. The heatsinks have low thermal resistance because of the close proximity of the microchannels to the laser diode being cooled. This allows high average power operation of two-dimensional laser diode arrays that have a high density of laser diode bars and therefore high optical power density. 9 figs.

Monolithic microchannel heatsink

DOEpatents

Benett, William J.; Beach, Raymond J.; Ciarlo, Dino R.

1996-01-01

A silicon wafer has slots sawn in it that allow diode laser bars to be mounted in contact with the silicon. Microchannels are etched into the back of the wafer to provide cooling of the diode bars. To facilitate getting the channels close to the diode bars, the channels are rotated from an angle perpendicular to the diode bars which allows increased penetration between the mounted diode bars. This invention enables the fabrication of monolithic silicon microchannel heatsinks for laser diodes. The heatsinks have low thermal resistance because of the close proximity of the microchannels to the laser diode being cooled. This allows high average power operation of two-dimensional laser diode arrays that have a high density of laser diode bars and therefore high optical power density.

Chemical multisensors with selective encapsulation of ion-selective membranes

NASA Astrophysics Data System (ADS)

Schwager, Felix J.; Bousse, Luc J.; Bowman, Lyn; Meindl, J. D.

Chemical sensors fabricated with simultaneous wafer scale encapsulation of ion selective electrode mambranes are described. The sensors are miniature ion selective electrodes in chambers located on a silicon substrate. These chambers are made by anodically bonding to the silicon a no. 7740 pyrex glass wafer in which cavities were drilled. Pores with dimensions selectable from 50 microns upwards are opened in the roofs of the chambers by drilling with a CO2 laser. Each sensor die contains four cavities which are filled under reduced pressure with liquid membrane material which is subsequently polymerized. The transducers on the cavity floor are Ag/AgCl electrodes. Interconnects between the sensor chambers on each die and bonding pads are made in the silicon substrate.

Coherent spin transport through a 350 micron thick silicon wafer.

PubMed

Huang, Biqin; Monsma, Douwe J; Appelbaum, Ian

2007-10-26

We use all-electrical methods to inject, transport, and detect spin-polarized electrons vertically through a 350-micron-thick undoped single-crystal silicon wafer. Spin precession measurements in a perpendicular magnetic field at different accelerating electric fields reveal high spin coherence with at least 13pi precession angles. The magnetic-field spacing of precession extrema are used to determine the injector-to-detector electron transit time. These transit time values are associated with output magnetocurrent changes (from in-plane spin-valve measurements), which are proportional to final spin polarization. Fitting the results to a simple exponential spin-decay model yields a conduction electron spin lifetime (T1) lower bound in silicon of over 500 ns at 60 K.

Solid State Research, 1980:3.

DTIC Science & Technology

1980-08-15

wafers. The amount of overgrowth is dependent on the orientation of the silicon substrate and the thick- ness of the SiO 2 layer. V. ANALOG DEVICE...Moulton XI Intl. Quantum Electronics Metal-Doped Lasers A. Mooradian Conference, Boston, Z3-26 June 1980 5Z45 Temperature- Dependent Spectral D.J...High Tempera- C. 0. Bozler 24-27 June 1980 ture Anneal 5327 Growth-Temperature Dependence Z. L. Liau of LPE GaInAsP/lnP Lattice J. J. Hsieh Mismatch

Probing photo-carrier collection efficiencies of individual silicon nanowire diodes on a wafer substrate.

PubMed

Schmitt, S W; Brönstrup, G; Shalev, G; Srivastava, S K; Bashouti, M Y; Döhler, G H; Christiansen, S H

2014-07-21

Vertically aligned silicon nanowire (SiNW) diodes are promising candidates for the integration into various opto-electronic device concepts for e.g. sensing or solar energy conversion. Individual SiNW p-n diodes have intensively been studied, but to date an assessment of their device performance once integrated on a silicon substrate has not been made. We show that using a scanning electron microscope (SEM) equipped with a nano-manipulator and an optical fiber feed-through for tunable (wavelength, power using a tunable laser source) sample illumination, the dark and illuminated current-voltage (I-V) curve of individual SiNW diodes on the substrate wafer can be measured. Surprisingly, the I-V-curve of the serially coupled system composed of SiNW/wafers is accurately described by an equivalent circuit model of a single diode and diode parameters like series and shunting resistivity, diode ideality factor and photocurrent can be retrieved from a fit. We show that the photo-carrier collection efficiency (PCE) of the integrated diode illuminated with variable wavelength and intensity light directly gives insight into the quality of the device design at the nanoscale. We find that the PCE decreases for high light intensities and photocurrent densities, due to the fact that considerable amounts of photo-excited carriers generated within the substrate lead to a decrease in shunting resistivity of the SiNW diode and deteriorate its rectification. The PCE decreases systematically for smaller wavelengths of visible light, showing the possibility of monitoring the effectiveness of the SiNW device surface passivation using the shown measurement technique. The integrated device was pre-characterized using secondary ion mass spectrometry (SIMS), TCAD simulations and electron beam induced current (EBIC) measurements to validate the properties of the characterized material at the single SiNW diode level.

Fine Collimator Grids Using Silicon Metering Structure

NASA Technical Reports Server (NTRS)

Eberhard, Carol

1998-01-01

The project Fine Collimator Grids Using Silicon Metering Structure was managed by Dr. Carol Eberhard of the Electromagnetic Systems & Technology Department (Space & Technology Division) of TRW who also wrote this final report. The KOH chemical etching of the silicon wafers was primarily done by Dr. Simon Prussin of the Electrical Engineering Department of UCLA at the laboratory on campus. Moshe Sergant of the Superconductor Electronics Technology Department (Electronics Systems & Technology Division) of TRW and Dr. Prussin were instrumental in developing the low temperature silicon etching processes. Moshe Sergant and George G. Pinneo of the Microelectronics Production Department (Electronics Systems & Technology Division) of TRW were instrumental in developing the processes for filling the slots etched in the silicon wafers with metal-filled materials. Their work was carried out in the laboratories at the Space Park facility. Moshe Sergant is also responsible for the impressive array of Scanning Electron Microscope images with which the various processes were monitored. Many others also contributed their time and expertise to the project. I wish to thank them all.

Nanoparticle-based etching of silicon surfaces

DOEpatents

Branz, Howard [Boulder, CO; Duda, Anna [Denver, CO; Ginley, David S [Evergreen, CO; Yost, Vernon [Littleton, CO; Meier, Daniel [Atlanta, GA; Ward, James S [Golden, CO

2011-12-13

A method (300) of texturing silicon surfaces (116) such to reduce reflectivity of a silicon wafer (110) for use in solar cells. The method (300) includes filling (330, 340) a vessel (122) with a volume of an etching solution (124) so as to cover the silicon surface 116) of a wafer or substrate (112). The etching solution (124) is made up of a catalytic nanomaterial (140) and an oxidant-etchant solution (146). The catalytic nanomaterial (140) may include gold or silver nanoparticles or noble metal nanoparticles, each of which may be a colloidal solution. The oxidant-etchant solution (146) includes an etching agent (142), such as hydrofluoric acid, and an oxidizing agent (144), such as hydrogen peroxide. Etching (350) is performed for a period of time including agitating or stirring the etching solution (124). The etch time may be selected such that the etched silicon surface (116) has a reflectivity of less than about 15 percent such as 1 to 10 percent in a 350 to 1000 nanometer wavelength range.

GaN-based photon-recycling green light-emitting diodes with vertical-conduction structure.

PubMed

Sheu, Jinn-Kong; Chen, Fu-Bang; Yen, Wei-Yu; Wang, Yen-Chin; Liu, Chun-Nan; Yeh, Yu-Hsiang; Lee, Ming-Lun

2015-04-06

A p-i-n structure with near-UV(n-UV) emitting InGaN/GaN multiple quantum well(MQW) structure stacked on a green unipolar InGaN/GaN MQW was epitaxially grown at the same sapphire substrate. Photon recycling green light-emitting diodes(LEDs) with vertical-conduction feature on silicon substrates were then fabricated by wafer bonding and laser lift-off techniques. The green InGaN/GaN QWs were pumped with n-UV light to reemit low-energy photons when the LEDs were electrically driven with a forward current. Efficiency droop is potentially insignificant compared with the direct green LEDs due to the increase of effective volume of active layer in the optically pumped green LEDs, i.e., light emitting no longer limited in the QWs nearest to the p-type region to cause severe Auger recombination and carrier overflow losses.

Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

PubMed

Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

2015-11-01

Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group. Copyright © 2015 Elsevier B.V. All rights reserved.

Characterization of high-quality kerfless epitaxial silicon for solar cells: Defect sources and impact on minority-carrier lifetime

DOE PAGES

Kivambe, Maulid M.; Powell, Douglas M.; Castellanos, Sergio; ...

2017-11-14

We investigate the types and origins of structural defects in thin (<100 μm) kerfless epitaxial single crystal silicon grown on top of reorganized porous silicon layers. Although the structural defect density is low (has average defect density < 10 4 cm -2), localized areas with a defect density > 10 5 cm -2 are observed. Cross-sectional and systematic plan-view defect etching and microscopy reveals that the majority of stacking faults and dislocations originate at the interface between the porous silicon layer and the epitaxial wafer. Localised dislocation clusters are observed in regions of collapsed/deformed porous silicon and at decorated stackingmore » faults. In localized regions of high extended defect density, increased minority-carrier recombination activity is observed. Evidence for impurity segregation to the extended defects (internal gettering), which is known to exacerbate carrier recombination is demonstrated. In conclusion, the impact of the defects on material performance and substrate re-use is also discussed.« less

Characterization of high-quality kerfless epitaxial silicon for solar cells: Defect sources and impact on minority-carrier lifetime

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kivambe, Maulid M.; Powell, Douglas M.; Castellanos, Sergio

We investigate the types and origins of structural defects in thin (<100 μm) kerfless epitaxial single crystal silicon grown on top of reorganized porous silicon layers. Although the structural defect density is low (has average defect density < 10 4 cm -2), localized areas with a defect density > 10 5 cm -2 are observed. Cross-sectional and systematic plan-view defect etching and microscopy reveals that the majority of stacking faults and dislocations originate at the interface between the porous silicon layer and the epitaxial wafer. Localised dislocation clusters are observed in regions of collapsed/deformed porous silicon and at decorated stackingmore » faults. In localized regions of high extended defect density, increased minority-carrier recombination activity is observed. Evidence for impurity segregation to the extended defects (internal gettering), which is known to exacerbate carrier recombination is demonstrated. In conclusion, the impact of the defects on material performance and substrate re-use is also discussed.« less

Characterization of high-quality kerfless epitaxial silicon for solar cells: Defect sources and impact on minority-carrier lifetime

NASA Astrophysics Data System (ADS)

Kivambe, Maulid M.; Powell, Douglas M.; Castellanos, Sergio; Jensen, Mallory Ann; Morishige, Ashley E.; Lai, Barry; Hao, Ruiying; Ravi, T. S.; Buonassisi, Tonio

2018-02-01

We investigate the types and origins of structural defects in thin (<100 μm) kerfless epitaxial single crystal silicon grown on top of reorganized porous silicon layers. Although the structural defect density is low (has average defect density < 104 cm-2), localized areas with a defect density > 105 cm-2 are observed. Cross-sectional and systematic plan-view defect etching and microscopy reveals that the majority of stacking faults and dislocations originate at the interface between the porous silicon layer and the epitaxial wafer. Localised dislocation clusters are observed in regions of collapsed/deformed porous silicon and at decorated stacking faults. In localized regions of high extended defect density, increased minority-carrier recombination activity is observed. Evidence for impurity segregation to the extended defects (internal gettering), which is known to exacerbate carrier recombination is demonstrated. The impact of the defects on material performance and substrate re-use is also discussed.

Preliminary evaluation of glass resin materials for solar cell cover use. [on spacecraft

NASA Technical Reports Server (NTRS)

Marsik, S. J.; Swartz, C. K.; Baraona, C. R.

1978-01-01

Silicon solar cells and silicon wafers coated with a heat-curable resin consisting of alternating Si-O atoms were subjected to three tests to evaluate the potential utility of this coating in space environments. These included UV irradiation in vacuum at an intensity of 10 air mass zero UV energy-equivalent solar constants for 728 hours followed by a long thermal cycle; 15 thermal shock cycles between 100 C and minus 196 C; and high temperature and humidity (65 C at 90% relative humidity). The UV tests resulted in a 8 to 24% loss in short-circuit current and darkening of the covers. Modification of the resin to provide a better match between the coefficients of expansion of the resin and silicon improved resistance to thermal shock, but also increased the darkening effect under UV irradiation. Silicon wafers coated with the resin were not adversely affected by the temperature/humidity test.

Fluorinion transfer in silver-assisted chemical etching for silicon nanowires arrays

NASA Astrophysics Data System (ADS)

Feng, Tianyu; Xu, Youlong; Zhang, Zhengwei; Mao, Shengchun

2015-08-01

Uniform silicon nanowires arrays (SiNWAs) were fabricated on unpolished rough silicon wafers through KOH pretreatment followed by silver-assisted chemical etching (SACE). Density functional theory (DFT) calculations were used to investigate the function of silver (Ag) at atomic scale in the etching process. Among three adsorption sites of Ag atom on Si(1 0 0) surface, Ag(T4) above the fourth-layer surface Si atoms could transfer fluorinion (F-) to adjacent Si successfully due to its stronger electrostatic attraction force between Ag(T4) and F-, smaller azimuth angle of Fsbnd Ag(T4)sbnd Si, shorter bond length of Fsbnd Si compared with Fsbnd Ag. As F- was transferred to adjacent Si by Ag(T4) one by one, the Si got away from the wafer in the form of SiF4 when it bonded with enough F- while Ag(T4) was still attached onto the Si wafer ready for next transfer. Cyclic voltammetry tests confirmed that Ag can improve the etching rate by transferring F- to Si.

Study of thin film production of ceramic ZrO2 on silicon wafer using second harmonic Nd-Yag laser with pulsed laser deposition technique

NASA Astrophysics Data System (ADS)

Suliyanti, Maria M.; Hidayah, Affi Nur; Kurniawan, K. H.

2012-06-01

Study about thin film production using technique pulsed laser deposition have been done. The Pulsed Laser Deposition (PLD) method has been used for growing thin film of ZrO2 on silicon wafer substrate (111 single crystal, thickness 400μm and diameter 7.5 cm). The target made from Zirconia oxide powder mixing with PVA and press using pressure 100kgN. The laser beam was focused by a lens (f = 100mm) through a quartz window onto the sample surface and the substrate was placed in parallel line with target. The distance between the target and the substrate is about 1 cm. The early results of this synthesis using 75 mJ Nd-YAG second harmonic laser pulse (532 nm Nd-YAG) and low pressure chamber surrounding gas 5 Torr. The irradiation of laser take around 6000 shoots or 10 minutes using frequencies laser 10 Hz. The micro thickness of film can be produced on silicon wafer using this technique. The results of ZrO2 thin film on substrate about 26.92%.

Study on chemical mechanical polishing of silicon wafer with megasonic vibration assisted.

PubMed

Zhai, Ke; He, Qing; Li, Liang; Ren, Yi

2017-09-01

Chemical mechanical polishing (CMP) is the primary method to realize the global planarization of silicon wafer. In order to improve this process, a novel method which combined megasonic vibration to assist chemical mechanical polishing (MA-CMP) is developed in this paper. A matching layer structure of polishing head was calculated and designed. Silicon wafers are polished by megasonic assisted chemical mechanical polishing and traditional chemical mechanical polishing respectively, both coarse polishing and precision polishing experiments were carried out. With the use of megasonic vibration, the surface roughness values Ra reduced from 22.260nm to 17.835nm in coarse polishing, and the material removal rate increased by approximately 15-25% for megasonic assisted chemical mechanical polishing relative to traditional chemical mechanical polishing. Average Surface roughness values Ra reduced from 0.509nm to 0.387nm in precision polishing. The results show that megasonic assisted chemical mechanical polishing is a feasible method to improve polishing efficiency and surface quality. The material removal and finishing mechanisms of megasonic vibration assisted polishing are investigated too. Copyright © 2017 Elsevier B.V. All rights reserved.

Switchable static friction of piezoelectric composite—silicon wafer contacts

NASA Astrophysics Data System (ADS)

van den Ende, D. A.; Fischer, H. R.; Groen, W. A.; van der Zwaag, S.

2013-04-01

The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and a silicon wafer counter surface rests solely on the matrix region of the piezocomposite surface. When actuated, the piezoelectric ceramic fibers protrude from the surface and the wafer rests solely on these protrusions. A threefold decrease in engineering static friction coefficient upon actuation of the piezocomposite was observed: from μ* = 1.65 to μ* = 0.50. These experimental results could be linked to the change in contact surface area and roughness using capillary adhesion theory, which relates the adhesive force to the number and size of the contacting asperities for the different surface states.

Commercial silicon-on-insulator (SOI) wafers as a versatile substrate for laser desorption/ionization mass spectrometry.

PubMed

Kim, Shin Hye; Kim, Jeongkwon; Moon, Dae Won; Han, Sang Yun

2013-01-01

We report here that a commercial silicon-on-insulator (SOI) wafer offers an opportunity for laser desorption/ionization (LDI) of peptide molecules, which occurs directly from its flat surface without requiring special surface preparation. The LDI-on-SOI exhibits intact ionization of peptides with a good detection limit of lower than 20 fmol, of which the mass range is demonstrated up to insulin with citric acid additives. The LDI process most likely arises from laser-induced surface heating promoted by two-dimensional thermal confinement in the thin Si surface layer of the SOI wafer. As a consequence of the thermal process, the LDI-on-SOI method is also capable of creating post-source decay (PSD) of the resulting peptide LDI ions, which is suitable for peptide sequencing using conventional TOF/TOF mass spectrometry.

Bio-inspired Fabrication of Complex Hierarchical Structure in Silicon.

PubMed

Gao, Yang; Peng, Zhengchun; Shi, Tielin; Tan, Xianhua; Zhang, Deqin; Huang, Qiang; Zou, Chuanping; Liao, Guanglan

2015-08-01

In this paper, we developed a top-down method to fabricate complex three dimensional silicon structure, which was inspired by the hierarchical micro/nanostructure of the Morpho butterfly scales. The fabrication procedure includes photolithography, metal masking, and both dry and wet etching techniques. First, microscale photoresist grating pattern was formed on the silicon (111) wafer. Trenches with controllable rippled structures on the sidewalls were etched by inductively coupled plasma reactive ion etching Bosch process. Then, Cr film was angled deposited on the bottom of the ripples by electron beam evaporation, followed by anisotropic wet etching of the silicon. The simple fabrication method results in large scale hierarchical structure on a silicon wafer. The fabricated Si structure has multiple layers with uniform thickness of hundreds nanometers. We conducted both light reflection and heat transfer experiments on this structure. They exhibited excellent antireflection performance for polarized ultraviolet, visible and near infrared wavelengths. And the heat flux of the structure was significantly enhanced. As such, we believe that these bio-inspired hierarchical silicon structure will have promising applications in photovoltaics, sensor technology and photonic crystal devices.

Phosphorus diffusion gettering process of multicrystalline silicon using a sacrificial porous silicon layer

PubMed Central

2012-01-01

The aims of this work are to getter undesirable impurities from low-cost multicrystalline silicon (mc-Si) wafers and then enhance their electronic properties. We used an efficient process which consists of applying phosphorus diffusion into a sacrificial porous silicon (PS) layer in which the gettered impurities have been trapped after the heat treatment. As we have expected, after removing the phosphorus-rich PS layer, the electrical properties of the mc-Si wafers were significantly improved. The PS layers, realized on both sides of the mc-Si substrates, were formed by the stain-etching technique. The phosphorus treatment was achieved using a liquid POCl3-based source on both sides of the mc-Si wafers. The realized phosphorus/PS/Si/PS/phosphorus structures were annealed at a temperature ranging between 700°C and 950°C under a controlled O2 atmosphere, which allows phosphorus to diffuse throughout the PS layers and to getter eventual metal impurities towards the phosphorus-doped PS layer. The effect of this gettering procedure was investigated by means of internal quantum efficiency and the dark current–voltage (I-V) characteristics. The minority carrier lifetime measurements were made using a WTC-120 photoconductance lifetime tester. The serial resistance and the shunt resistance carried out from the dark I-V curves confirm this gettering-related solar cell improvement. It has been shown that the photovoltaic parameters of the gettered silicon solar cells were improved with regard to the ungettered one, which proves the beneficial effect of this gettering process on the conversion efficiency of the multicrystalline silicon solar cells. PMID:22846070

2-dimensional ion velocity distributions measured by laser-induced fluorescence above a radio-frequency biased silicon wafer

NASA Astrophysics Data System (ADS)

Moore, Nathaniel B.; Gekelman, Walter; Pribyl, Patrick; Zhang, Yiting; Kushner, Mark J.

2013-08-01

The dynamics of ions traversing sheaths in low temperature plasmas are important to the formation of the ion energy distribution incident onto surfaces during microelectronics fabrication. Ion dynamics have been measured using laser-induced fluorescence (LIF) in the sheath above a 30 cm diameter, 2.2 MHz-biased silicon wafer in a commercial inductively coupled plasma processing reactor. The velocity distribution of argon ions was measured at thousands of positions above and radially along the surface of the wafer by utilizing a planar laser sheet from a pulsed, tunable dye laser. Velocities were measured both parallel and perpendicular to the wafer over an energy range of 0.4-600 eV. The resulting fluorescence was recorded using a fast CCD camera, which provided resolution of 0.4 mm in space and 30 ns in time. Data were taken at eight different phases during the 2.2 MHz cycle. The ion velocity distributions (IVDs) in the sheath were found to be spatially non-uniform near the edge of the wafer and phase-dependent as a function of height. Several cm above the wafer the IVD is Maxwellian and independent of phase. Experimental results were compared with simulations. The experimental time-averaged ion energy distribution function as a function of height compare favorably with results from the computer model.

Formation of shallow boron emitters in crystalline silicon using flash lamp annealing: Role of excess silicon interstitials

DOE Office of Scientific and Technical Information (OSTI.GOV)

Riise, Heine Nygard, E-mail: h.n.riise@fys.uio.no; Azarov, Alexander; Svensson, Bengt G.

2015-07-13

Shallow, Boron (B)-doped p{sup +} emitters have been realized using spin-on deposition and Flash Lamp Annealing (FLA) to diffuse B into monocrystalline float zone Silicon (Si). The emitters extend between 50 and 140 nm in depth below the surface, have peak concentrations between 9 × 10{sup 19 }cm{sup –3} and 3 × 10{sup 20 }cm{sup –3}, and exhibit sheet resistances between 70 and 3000 Ω/□. An exceptionally large increase in B diffusion occurs for FLA energy densities exceeding ∼93 J/cm{sup 2} irrespective of 10 or 20 ms pulse duration. The effect is attributed to enhanced diffusion of B caused by Si interstitial injection following a thermally activated reaction betweenmore » the spin-on diffusant film and the silicon wafer.« less

Silicon materials task of the low-cost solar array project. Phase 4: Effects of impurities and processing on silicon solar cells

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Hanes, M. H.; Davis, J. R.; Rohatgi, A.; Rai-Choudhury, P.; Mollenkopf, H. C.

1981-01-01

The effects of impurities, various thermochemical processes, and any impurity-process interactions upon the performance of terrestrial solar cells are defined. The results form a basis for silicon producers, wafer manufacturers, and cell fabricators to develop appropriate cost benefit relationships for the use of less pure, less costly solar grade silicon.

Fabrication of high-quality superconductor-insulator-superconductor junctions on thin SiN membranes

NASA Technical Reports Server (NTRS)

Garcia, Edouard; Jacobson, Brian R.; Hu, Qing

1993-01-01

We have successfully fabricated high-quality and high-current density superconductor-insulator-superconductor (SIS) junctions on freestanding thin silicon nitride (SIN) membranes. These devices can be used in a novel millimeter-wave and THz receiver system which is made using micromachining. The SIS junctions with planar antennas were fabricated first on a silicon wafer covered with a SiN membrane, the Si wafer underneath was then etched away using an anisotropic KOH etchant. The current-voltage characteristics of the SIS junctions remained unchanged after the whole process, and the junctions and the membrane survived thermal cycling.

Brewster's angle silicon wafer terahertz linear polarizer.

PubMed

Wojdyla, Antoine; Gallot, Guilhem

2011-07-18

We present a new cost-effective terahertz linear polarizer made from a stack of silicon wafers at Brewster's angle, andevaluate its performances. We show that this polarizer is wide-band, has a high extinction ratio (> 6 × 10(3)) and very small insertion losses (< 1%). We provide measurements of the temporal waveforms after linearly polarizing the THz beam and show that there is no distortion of the pulse. We compare its performances with a commercial wire-grid polarizer, and show that the Brewster's angle polarizer can conveniently be used to control the power of a terahertz beam.

Computational Spectroscopy of Structured Carbon Nanotube Interfaces for Biochemical Sensing

DTIC Science & Technology

2010-04-01

oxidized layer of SiCh served as a diffusion barrier to prevent Pt silicide formation and was shown to aide the formation of well dispersed catalytic nano...Three types of fluorescent mi- crospheres (Fluospheres) from Invitrogen were tested. The fluorescent microspheres were prepared in a 10:1 solution with...spectral channels for a given pixel location. Carbon Nanotube Growth on Pt Sample preparation involved cleaving silicon (100) wafers to desired

Protective Coating For Laser Drilling Of Silicon

NASA Technical Reports Server (NTRS)

Shlichta, Paul J.

1988-01-01

Sodium silicate prevents spattered silicon from fusing with surrounding material. Sodium silicate solution applied to wafer by dipping and draining or by spinning; application by spraying also works. When dried in oven, solution leaves thin coating of sodium silicate glass.

High-performance fused indium gallium arsenide/silicon photodiode

NASA Astrophysics Data System (ADS)

Kang, Yimin

Modern long haul, high bit rate fiber-optic communication systems demand photodetectors with high sensitivity. Avalanche photodiodes (APDs) exhibit superior sensitivity performance than other types of photodetectors by virtual of its internal gain mechanism. This dissertation work further advances the APD performance by applying a novel materials integration technique. It is the first successful demonstration of wafer fused InGaAs/Si APDs with low dark current and low noise. APDs generally adopt separate absorption and multiplication (SAM) structure, which allows independent optimization of materials properties in two distinct regions. While the absorption material needs to have high absorption coefficient in the target wavelength range to achieve high quantum efficiency, it is desirable for the multiplication material to have large discrepancy between its electron and hole ionization coefficients to reduce noise. According to these criteria, InGaAs and Si are the ideal materials combination. Wafer fusion is the enabling technique that makes this theoretical ideal an experimental possibility. APDs fabricated on the fused InGaAs/Si wafer with mesa structure exhibit low dark current and low noise. Special device fabrication techniques and high quality wafer fusion reduce dark current to nano ampere level at unity gain, comparable to state-of-the-art commercial III/V APDs. The small excess noise is attributed to the large difference in ionization coefficients between electrons and holes in silicon. Detailed layer structure designs are developed specifically for fused InGaAs/Si APDs based on principles similar to those used in traditional InGaAs/InP APDs. An accurate yet straightforward technique for device structural parameters extraction is also proposed. The extracted results from the fabricated APDs agree with device design parameters. This agreement also confirms that the fusion interface has negligible effect on electric field distributions for devices fabricated from high quality fusion materials. The feasibility of fused InGaAs/Si APD for analog systems is also explored. Preliminary two-tone measurement shows that a moderately high dynamic range of 70 dBc/Hz1/2 for broadband Spur Free Dynamic Range (SFDR) or 82 dBc/Hz2/3 suboctave SFDR, up to 50 muA of optical current, can be achieved. The theoretical analyses of SNR show that fused InGaAs/Si APD receivers can provide larger Signal-to-Noise Ratio (SNR) than their III/V counterparts.

Characterization of solar-grade silicon produced by the SiF4-Na process

NASA Technical Reports Server (NTRS)

Sanjurjo, A.; Sancier, K. M.; Emerson, R. M.; Leach, S. C.; Minahan, J.

1986-01-01

A process was developed for producing low cost solar grade silicon by the reaction between SiF4 gas and sodium metal. The results of the characterization of the silicon are presented. These results include impurity levels, electronic properties of the silicon after crystal growth, and the performance of solar photovoltaic cells fabricated from wafers of the single crystals. The efficiency of the solar cells fabricated from semiconductor silicon and SiF4-Na silicon was the same.

Silicon Technologies Adjust to RF Applications

NASA Technical Reports Server (NTRS)

Reinecke Taub, Susan; Alterovitz, Samuel A.

1994-01-01

Silicon (Si), although not traditionally the material of choice for RF and microwave applications, has become a serious challenger to other semiconductor technologies for high-frequency applications. Fine-line electron- beam and photolithographic techniques are now capable of fabricating silicon gate sizes as small as 0.1 micron while commonly-available high-resistivity silicon wafers support low-loss microwave transmission lines. These advances, coupled with the recent development of silicon-germanium (SiGe), arm silicon integrated circuits (ICs) with the speed required for increasingly higher-frequency applications.

Influence of interfaces density and thermal processes on mechanical stress of PECVD silicon nitride

NASA Astrophysics Data System (ADS)

Picciotto, A.; Bagolini, A.; Bellutti, P.; Boscardin, M.

2009-10-01

The paper focuses on a particular silicon nitride thin film (SiN x) produced by plasma enahanced chemical vapor deposition (PECVD) technique with high deposition rate (26 nm/min) and low values of mechanical stress (<100 MPa). This was perfomed with mixed frequency procedure varying the modulation of high frequency at 13.56 MHz and low frequency at 308 kHz of RF power supply during the deposition, without changing the ratio of reaction gases. Low stress silicon nitride is commonly obtained by tailoring the thickness ratio of high frequency vs. low frequency silicon nitride layers. The attention of this work was directed to the influence of the number of interfaces per thickness unit on the stress characteristics of the deposited material. Two sets of wafer samples were deposited with low stress silicon nitride, with a thickness of 260 nm and 2 μm, respectively. Thermal annealing processes at 380 and 520 °C in a inert enviroment were also performed on the wafers. The Stoney-Hoffman model was used to estimate the stress values by wafer curvature measurement with a mechanical surface profilometer: the stress was calculated for the as-deposited layer, and after each annealing process. The thickness and the refractive index of the SiN x were also measured and charaterized by variable angle spectra elliposometry (VASE) techinique. The experimental measurements were performed at the MT-LAB, IRST (Istituto per la Ricerca Scientifica e Tecnologica) of Bruno Kessler Foundation for Research in Trento.

Amorphous-diamond electron emitter

DOEpatents

Falabella, Steven

2001-01-01

An electron emitter comprising a textured silicon wafer overcoated with a thin (200 .ANG.) layer of nitrogen-doped, amorphous-diamond (a:D-N), which lowers the field below 20 volts/micrometer have been demonstrated using this emitter compared to uncoated or diamond coated emitters wherein the emission is at fields of nearly 60 volts/micrometer. The silicon/nitrogen-doped, amorphous-diamond (Si/a:D-N) emitter may be produced by overcoating a textured silicon wafer with amorphous-diamond (a:D) in a nitrogen atmosphere using a filtered cathodic-arc system. The enhanced performance of the Si/a:D-N emitter lowers the voltages required to the point where field-emission displays are practical. Thus, this emitter can be used, for example, in flat-panel emission displays (FEDs), and cold-cathode vacuum electronics.

Sensitivity analysis of add-on price estimate for select silicon wafering technologies

NASA Technical Reports Server (NTRS)

Mokashi, A. R.

1982-01-01

The cost of producing wafers from silicon ingots is a major component of the add-on price of silicon sheet. Economic analyses of the add-on price estimates and their sensitivity internal-diameter (ID) sawing, multiblade slurry (MBS) sawing and fixed-abrasive slicing technique (FAST) are presented. Interim price estimation guidelines (IPEG) are used for estimating a process add-on price. Sensitivity analysis of price is performed with respect to cost parameters such as equipment, space, direct labor, materials (blade life) and utilities, and the production parameters such as slicing rate, slices per centimeter and process yield, using a computer program specifically developed to do sensitivity analysis with IPEG. The results aid in identifying the important cost parameters and assist in deciding the direction of technology development efforts.

Methods of Measurement for Semiconductor Materials, Process Control, and Devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1973-01-01

The development of methods of measurement for semiconductor materials, process control, and devices is reported. Significant accomplishments include: (1) Completion of an initial identification of the more important problems in process control for integrated circuit fabrication and assembly; (2) preparations for making silicon bulk resistivity wafer standards available to the industry; and (3) establishment of the relationship between carrier mobility and impurity density in silicon. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers, including gold, in silicon; evaluation of wire bonds and die attachment; study of scanning electron microscopy for wafer inspection and test; measurement of thermal properties of semiconductor devices; determination of S-parameters and delay time in junction devices; and characterization of noise and conversion loss of microwave detector diodes.

A Compact Imaging Detector of Polarization and Spectral Content

NASA Technical Reports Server (NTRS)

Rust, D. M.; Kumar, A.; Thompson, K. E.

1993-01-01

A new type of image detector will simultaneously analyze the polarization of light at all picture elements in a scene. The integrated Dual Imaging Detector (IDID) consists of a polarizing beam splitter bonded to a charge-coupled device (CCD), with signal-analysis circuitry and analog-to-digital converters, all integrated on a silicon chip. The polarizing beam splitter can be either a Ronchi ruling, or an array of cylindrical lenslets, bonded to a birefringent wafer. The wafer, in turn, is bonded to the CCD so that light in the two orthogonal planes of polarization falls on adjacent pairs of pixels. The use of a high-index birefringent material, e.g., rutile, allows the IDID to operate at f-numbers as high as f/3.5. Other aspects of the detector are discussed.

Silicon Hybrid Wafer Scale Integration Interconnect Evaluation

DTIC Science & Technology

1989-12-01

perform Wafer Scale Integration on a routine basis is being vigorously pursued by a number of interests in military, academic , and commercial sectors...A iliciosi rip1 St -110 illic. (;11ptai / W. -a ;,tcd Ihat Ilesc hybhrid futl liods separiltely soI lie llixiiiul’upw~v~ ielts andl ~il (otii’ie thli

Remote Imaging by Nanosecond Terahertz Spectrometer with Standoff Detector

NASA Astrophysics Data System (ADS)

Huang, J.-G.; Huang, Z.-M.; Andreev, Yu. M.; Kokh, K. A.; Lanskii, G. V.; Potekaev, A. I.; Svetlichnyi, V. A.

2018-01-01

Creation and application of the remote imaging spectrometer based on high power nanosecond terahertz source with standoff detector is reported. 2D transmission images of metal objects hided in nonconductive (dielectric) materials were recorded. Reflection images of metal objects mounted on silicon wafers are recorded with simultaneous determination of the wafer parameters (thickness/material).

Charge-carrier relaxation in sonochemically fabricated dendronized CaSiO3-SiO2-Si nanoheterostructures

NASA Astrophysics Data System (ADS)

Savkina, Rada; Smirnov, Aleksey; Kirilova, Svitlana; Shmid, Volodymyr; Podolian, Artem; Nadtochiy, Andriy; Odarych, Volodymyr; Korotchenkov, Oleg

2018-04-01

We present systematic studies of charge-carrier relaxation processes in sonochemically nanostructured silicon wafers. Impedance spectroscopy and transient photovoltage techniques are employed. It is found that interface potential in Si wafers remarkably increases upon their exposure to sonochemical treatments in Ca-rich environments. In contrast, the density of fast interface electron states remains almost unchanged. It is found that the initial photovoltage decay, taken before ultrasonic treatments, exhibits the involvement of shorter- and longer time recombination and trapping centers. The decay speeds up remarkably due to cavitation treatments, which is accompanied by a substantial quenching of the photovoltage magnitude. It is also found that, before the treatments, the photovoltage magnitude is markedly non-uniform over the wafer surface, implying the existence of distributed sites affecting distribution of photoexcited carriers. The treatments cause an overall broadening of the photovoltage distribution. Furthermore, impedance measurements monitor the progress in surface structuring relevant to several relaxation processes. We believe that sonochemical nanostructuring of silicon wafers with dendronized CaSiO3 may enable new promising avenue towards low-cost solar energy efficiency multilayered solar cell device structures.

Nanowire decorated, ultra-thin, single crystalline silicon for photovoltaic devices.

PubMed

Aurang, Pantea; Turan, Rasit; Unalan, Husnu Emrah

2017-10-06

Reducing silicon (Si) wafer thickness in the photovoltaic industry has always been demanded for lowering the overall cost. Further benefits such as short collection lengths and improved open circuit voltages can also be achieved by Si thickness reduction. However, the problem with thin films is poor light absorption. One way to decrease optical losses in photovoltaic devices is to minimize the front side reflection. This approach can be applied to front contacted ultra-thin crystalline Si solar cells to increase the light absorption. In this work, homojunction solar cells were fabricated using ultra-thin and flexible single crystal Si wafers. A metal assisted chemical etching method was used for the nanowire (NW) texturization of ultra-thin Si wafers to compensate weak light absorption. A relative improvement of 56% in the reflectivity was observed for ultra-thin Si wafers with the thickness of 20 ± 0.2 μm upon NW texturization. NW length and top contact optimization resulted in a relative enhancement of 23% ± 5% in photovoltaic conversion efficiency.

SEMICONDUCTOR TECHNOLOGY: Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers

NASA Astrophysics Data System (ADS)

Zhongshan, Zheng; Zhongli, Liu; Ning, Li; Guohua, Li; Enxia, Zhang

2010-02-01

To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density. The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance-voltage (C-V) analysis.

The economic payoff for a state-of-the-art high-efficiency flat-plate crystalline silicon solar cell technology

NASA Technical Reports Server (NTRS)

Bickler, Donald B.; Callaghan, W. T.

1987-01-01

In 1986 during the flat-plate solar array project, silicon solar cells 4.0 sq cm in area were fabricated at the Jet Propulsion Laboratory (JPL) with a conversion efficiency of 20.1 percent (AM1.5-global). Sixteen cells were processed with efficiencies measuring 19.5 percent (AM1.5 global) or better. These cells were produced using refined versions of conventional processing methods, aside from certain advanced techniques that bring about a significant reduction in a major mechanism (surface recombination) that limits cell efficiency. Wacker Siltronic p-type float-zone 0.18-ohm-cm wafers were used. Conversion efficiencies in this range have previously been reported by other researchers, but generally on much smaller (0.5 vs. 4.0 cm) devices which have undergone sophisticated and costly processing steps. An economic analysis is presented of the potential payoffs for this approach, using the Solar Array Manufacturing Industry Costing Standards (SAMICS) methodology. The process sequence used and the assumptions made for capturing the economies of scale are presented.

Dependence of electrical and optical properties of amorphous SiC:H thin films grown by rf plasma enhanced chemical vapor deposition on annealing temperature

NASA Astrophysics Data System (ADS)

Park, M. G.; Choi, W. S.; Hong, B.; Kim, Y. T.; Yoon, D. H.

2002-05-01

In this article, we investigated the dependence of optical and electrical properties of hydrogenated amorphous silicon carbide (a-SiC:H) films on annealing temperature (Ta) and radio frequency (rf) power. The substrate temperature (Ts) was 250 °C, the rf power was varied from 30 to 400 W, and the range of Ta was from 400 to 600 °C. The a-SiC:H films were deposited by using the plasma enhanced chemical vapor deposition system on Corning 7059 glasses and p-type Si (100) wafers with a SiH4+CH4 gas mixture. The experimental results have shown that the optical bandgap energy (Eg) of the a-SiC:H thin films changed little on the annealing temperature while Eg increased with the rf power. The Raman spectrum of the thin films annealed at high temperatures showed that graphitization of carbon clusters and microcrystalline silicon occurs. The current-voltage characteristics have shown good electrical properties in relation to the annealed films.

A MoTe2 based light emitting diode and photodetector for silicon photonic integrated circuits

NASA Astrophysics Data System (ADS)

Bie, Ya-Qing; Heuck, M.; Grosso, G.; Furchi, M.; Cao, Y.; Zheng, J.; Navarro-Moratalla, E.; Zhou, L.; Taniguchi, T.; Watanabe, K.; Kong, J.; Englund, D.; Jarillo-Herrero, P.

A key challenge in photonics today is to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, partly because many components such as waveguides, interferometers and modulators, could be integrated on silicon-based processors. However, light sources and photodetectors present continued challenges. Common approaches for light source include off-chip or wafer-bonded lasers based on III-V materials, but studies show advantages for directly modulated light sources. The most advanced photodetectors in silicon photonics are based on germanium growth which increases system cost. The emerging two dimensional transition metal dichalcogenides (TMDs) offer a path for optical interconnects components that can be integrated with the CMOS processing by back-end-of-the-line processing steps. Here we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with infrared band gap. The state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

Optimized structural designs for stretchable silicon integrated circuits.

PubMed

Kim, Dae-Hyeong; Liu, Zhuangjian; Kim, Yun-Soung; Wu, Jian; Song, Jizhou; Kim, Hoon-Sik; Huang, Yonggang; Hwang, Keh-Chih; Zhang, Yongwei; Rogers, John A

2009-12-01

Materials and design strategies for stretchable silicon integrated circuits that use non-coplanar mesh layouts and elastomeric substrates are presented. Detailed experimental and theoretical studies reveal many of the key underlying aspects of these systems. The results shpw, as an example, optimized mechanics and materials for circuits that exhibit maximum principal strains less than 0.2% even for applied strains of up to approximately 90%. Simple circuits, including complementary metal-oxide-semiconductor inverters and n-type metal-oxide-semiconductor differential amplifiers, validate these designs. The results suggest practical routes to high-performance electronics with linear elastic responses to large strain deformations, suitable for diverse applications that are not readily addressed with conventional wafer-based technologies.

Effect of particle size on the UV pulsed-laser scribing in computational fluid dynamics-based simulations

NASA Astrophysics Data System (ADS)

Park, Kwan-Woo; Na, Suck-Joo

2010-06-01

A computational model for UV pulsed-laser scribing of silicon target is presented and compared with experimental results. The experiments were performed with a high-power Q-switched diode-pumped solid state laser which was operated at 355 nm. They were conducted on n-type 500 μm thick silicon wafers. The scribing width and depth were measured using scanning electron microscopy. The model takes into account major physics, such as heat transfer, evaporation, multiple reflections, and Rayleigh scattering. It also considers the attenuation and redistribution of laser energy due to Rayleigh scattering. Especially, the influence of the average particle sizes in the model is mainly investigated. Finally, it is shown that the computational model describing the laser scribing of silicon is valid at an average particle size of about 10 nm.

Organ-on-a-Chip for Aerospace Physiology and Toxicology

DTIC Science & Technology

2014-12-15

Products (Chicago, IL) supplied the Laboratory Corona Treater. Silicon wafers, 3” with > orientation were obtained from Wafer World Incorporated...was flowed at a process pressure of 500 mT. The plasma was ignited at discharge power of 250 W at 30 kHz and allowed to run for 1 minute. The wafer...slide and PDMS channel surfaces was performed one of two ways. Either using a handheld corona tool operated in a chemical safety hood or the PDMS slabs

Tripodal penta(p-phenylene) for the biofunctionalization of alkynyl-modified silicon surfaces

NASA Astrophysics Data System (ADS)

Sánchez-Molina, María; Díaz, Amelia; Valpuesta, María; Contreras-Cáceres, Rafael; López-Romero, J. Manuel; López-Ramírez, M. Rosa

2018-07-01

Here we report the optimization on the covalent grafting methodology of a tripod-shaped penta(p-phenylene), 1, on alkynyl-terminated silicon surfaces, and the incorporation of an active theophylline derivative, 2, for the specific immobilization of proteins. The tripodal molecule presents azide-terminal groups to be attached onto a silicon surface containing an alkynyl monolayer. Initially, compound 1 has been covalently incorporated on alkynyl-terminated Si wafers, by the copper catalyzed alkyne-azide 1,3-dipolar cycloaddition (CuAAC, a click reaction). The tripod density on the silicon surface is tuned by performing the CuAAC reaction at different concentrations of 1, as well as under different experimental conditions (T, base, copper source, shaking). Then, tripod 1-modified surface has also been biofunctionalized with 2. The effective preparation of this silicon-modified surface allowed us to study the streptavidin immobilization on the surface. Characterization of the different surfaces has been carried out by X-ray Photoelectron Spectroscopy (XPS), Atomic Force Microscopy (AFM) and Bright-Field Optical Transmission Microscopy (Confocal) techniques. We also include density functional theory (DFT) analysis of the organic structures to confirm the height-profile and the tripod-surface relative configuration extracted from AFM images.

Passivation mechanism of thermal atomic layer-deposited Al2O3 films on silicon at different annealing temperatures.

PubMed

Zhao, Yan; Zhou, Chunlan; Zhang, Xiang; Zhang, Peng; Dou, Yanan; Wang, Wenjing; Cao, Xingzhong; Wang, Baoyi; Tang, Yehua; Zhou, Su

2013-03-02

Thermal atomic layer-deposited (ALD) aluminum oxide (Al2O3) acquires high negative fixed charge density (Qf) and sufficiently low interface trap density after annealing, which enables excellent surface passivation for crystalline silicon. Qf can be controlled by varying the annealing temperatures. In this study, the effect of the annealing temperature of thermal ALD Al2O3 films on p-type Czochralski silicon wafers was investigated. Corona charging measurements revealed that the Qf obtained at 300°C did not significantly affect passivation. The interface-trapping density markedly increased at high annealing temperature (>600°C) and degraded the surface passivation even at a high Qf. Negatively charged or neutral vacancies were found in the samples annealed at 300°C, 500°C, and 750°C using positron annihilation techniques. The Al defect density in the bulk film and the vacancy density near the SiOx/Si interface region decreased with increased temperature. Measurement results of Qf proved that the Al vacancy of the bulk film may not be related to Qf. The defect density in the SiOx region affected the chemical passivation, but other factors may dominantly influence chemical passivation at 750°C.

Passivation mechanism of thermal atomic layer-deposited Al2O3 films on silicon at different annealing temperatures

PubMed Central

2013-01-01

Thermal atomic layer-deposited (ALD) aluminum oxide (Al2O3) acquires high negative fixed charge density (Qf) and sufficiently low interface trap density after annealing, which enables excellent surface passivation for crystalline silicon. Qf can be controlled by varying the annealing temperatures. In this study, the effect of the annealing temperature of thermal ALD Al2O3 films on p-type Czochralski silicon wafers was investigated. Corona charging measurements revealed that the Qf obtained at 300°C did not significantly affect passivation. The interface-trapping density markedly increased at high annealing temperature (>600°C) and degraded the surface passivation even at a high Qf. Negatively charged or neutral vacancies were found in the samples annealed at 300°C, 500°C, and 750°C using positron annihilation techniques. The Al defect density in the bulk film and the vacancy density near the SiOx/Si interface region decreased with increased temperature. Measurement results of Qf proved that the Al vacancy of the bulk film may not be related to Qf. The defect density in the SiOx region affected the chemical passivation, but other factors may dominantly influence chemical passivation at 750°C. PMID:23452508

First results of a novel Silicon Drift Detector array designed for low energy X-ray fluorescence spectroscopy

NASA Astrophysics Data System (ADS)

Rachevski, Alexandre; Ahangarianabhari, Mahdi; Bellutti, Pierluigi; Bertuccio, Giuseppe; Brigo, Elena; Bufon, Jernej; Carrato, Sergio; Castoldi, Andrea; Cautero, Giuseppe; Fabiani, Sergio; Giacomini, Gabriele; Gianoncelli, Alessandra; Giuressi, Dario; Guazzoni, Chiara; Kourousias, George; Liu, Chang; Menk, Ralf Hendrik; Montemurro, Giuseppe Vito; Picciotto, Antonino; Piemonte, Claudio; Rashevskaya, Irina; Shi, Yongbiao; Stolfa, Andrea; Vacchi, Andrea; Zampa, Gianluigi; Zampa, Nicola; Zorzi, Nicola

2016-07-01

We developed a trapezoidal shaped matrix with 8 cells of Silicon Drift Detectors (SDD) featuring a very low leakage current (below 180 pA/cm2 at 20 °C) and a shallow uniformly implanted p+ entrance window that enables sensitivity down to few hundreds of eV. The matrix consists of a completely depleted volume of silicon wafer subdivided into 4 square cells and 4 half-size triangular cells. The energy resolution of a single square cell, readout by the ultra-low noise SIRIO charge sensitive preamplifier, is 158 eV FWHM at 5.9 keV and 0 °C. The total sensitive area of the matrix is 231 mm2 and the wafer thickness is 450 μm. The detector was developed in the frame of the INFN R&D project ReDSoX in collaboration with FBK, Trento. Its trapezoidal shape was chosen in order to optimize the detection geometry for the experimental requirements of low energy X-ray fluorescence (LEXRF) spectroscopy, aiming at achieving a large detection angle. We plan to exploit the complete detector at the TwinMic spectromicroscopy beamline at the Elettra Synchrotron (Trieste, Italy). The complete system, composed of 4 matrices, increases the solid angle coverage of the isotropic photoemission hemisphere about 4 times over the present detector configuration. We report on the layout of the SDD matrix and of the experimental set-up, as well as the spectroscopic performance measured both in the laboratory and at the experimental beamline.