Advancements in n-Type Base Crystalline Silicon Solar Cells and Their Emergence in the Photovoltaic Industry

PubMed Central

ur Rehman, Atteq; Lee, Soo Hong

2013-01-01

The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed. PMID:24459433

RF performances of inductors integrated on localized p+-type porous silicon regions

PubMed Central

2012-01-01

To study the influence of localized porous silicon regions on radiofrequency performances of passive devices, inductors were integrated on localized porous silicon regions, full porous silicon sheet, bulk silicon and glass substrates. In this work, a novel strong, resistant fluoropolymer mask is introduced to localize the porous silicon on the silicon wafer. Then, the quality factors and resonant frequencies obtained with the different substrates are presented. A first comparison is done between the performances of inductors integrated on same-thickness localized and full porous silicon sheet layers. The effect of the silicon regions in the decrease of performances of localized porous silicon is discussed. Then, the study shows that the localized porous silicon substrate significantly reduces losses in comparison with high-resistivity silicon or highly doped silicon bulks. These results are promising for the integration of both passive and active devices on the same silicon/porous silicon hybrid substrate. PMID:23009746

Dry etch method for texturing silicon and device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gershon, Talia S.; Haight, Richard A.; Kim, Jeehwan

2017-07-25

A method for texturing silicon includes loading a silicon wafer into a vacuum chamber, heating the silicon wafer and thermal cracking a gas to generate cracked sulfur species. The silicon wafer is exposed to the cracked sulfur species for a time duration in accordance with a texture characteristic needed for a surface of the silicon wafer.

System and Method for Fabricating Super Conducting Circuitry on Both Sides of an Ultra-Thin Layer

NASA Technical Reports Server (NTRS)

Brown, Ari D. (Inventor); Mikula, Vilem (Inventor)

2017-01-01

A method of fabricating circuitry in a wafer includes depositing a superconducting metal on a silicon on insulator wafer having a handle wafer, coating the wafer with a sacrificial layer and bonding the wafer to a thermally oxide silicon wafer with a first epoxy. The method includes flipping the wafer, thinning the flipped wafer by removing a handle wafer, etching a buried oxide layer, depositing a superconducting layer, bonding the wafer to a thermally oxidized silicon wafer having a handle wafer using an epoxy, flipping the wafer again, thinning the flipped wafer, etching a buried oxide layer from the wafer and etching the sacrificial layer from the wafer. The result is a wafer having superconductive circuitry on both sides of an ultra-thin silicon layer.

Effect of electroless etching parameters on the growth and reflection properties of silicon nanowires.

PubMed

Ozdemir, Baris; Kulakci, Mustafa; Turan, Rasit; Unalan, Husnu Emrah

2011-04-15

Vertically aligned silicon nanowire (Si NW) arrays have been fabricated over large areas using an electroless etching (EE) method, which involves etching of silicon wafers in a silver nitrate and hydrofluoric acid based solution. A detailed parametric study determining the relationship between nanowire morphology and time, temperature, solution concentration and starting wafer characteristics (doping type, resistivity, crystallographic orientation) is presented. The as-fabricated Si NW arrays were analyzed by field emission scanning electron microscope (FE-SEM) and a linear dependency of nanowire length to both temperature and time was obtained and the change in the growth rate of Si NWs at increased etching durations was shown. Furthermore, the effects of EE parameters on the optical reflectivity of the Si NWs were investigated in this study. Reflectivity measurements show that the 42.8% reflectivity of the starting silicon wafer drops to 1.3%, recorded for 10 µm long Si NW arrays. The remarkable decrease in optical reflectivity indicates that Si NWs have a great potential to be utilized in radial or coaxial p-n heterojunction solar cells that could provide orthogonal photon absorption and enhanced carrier collection.

Six Sigma-based approach to optimise the diffusion process of crystalline silicon solar cell manufacturing

NASA Astrophysics Data System (ADS)

Prasad, A. Guru; Saravanan, S.; Gijo, E. V.; Dasari, Sreenivasa Murty; Tatachar, Raghu; Suratkar, Prakash

2016-02-01

Silicon-based photovoltaics (PV) plays the dominant role in the history of PV due to the continuous process and technology improvement in silicon solar cells and its manufacturing flow. In general, silicon solar cell process uses either p-type- or n-type-doped silicon as the starting material. Currently, most of the PV industries use p-type, boron-doped silicon wafer as the starting material. In this work too, the boron-doped wafers were considered as the starting material to create pn junction and phosphorus was used as n-type doping material. Industries use either phosphorous oxy chloride (POCl3) or ortho phosphoric acid (H3PO4) as the precursor for doping phosphorous. While the industries use POCl3 as the precursor, the throughput is lesser than that of the industries' use of H3PO4 due to the manufacturing limitations of the POCl3-based equipments. Hence, in order to achieve the operational excellence in POCl3-based equipments, business strategies such as the Six Sigma methodology have to be adapted. This paper describes the application of Six Sigma Define-Measure-Analyze-Improve-Control methodology for throughput improvement of the phosphorus doping process. The optimised recipe has been implemented in the production and it is running successfully. As a result of this project, an effective gain of 0.9 MW was reported per annum.

Effect of electroless etching parameters on the growth and reflection properties of silicon nanowires

NASA Astrophysics Data System (ADS)

Ozdemir, Baris; Kulakci, Mustafa; Turan, Rasit; Emrah Unalan, Husnu

2011-04-01

Vertically aligned silicon nanowire (Si NW) arrays have been fabricated over large areas using an electroless etching (EE) method, which involves etching of silicon wafers in a silver nitrate and hydrofluoric acid based solution. A detailed parametric study determining the relationship between nanowire morphology and time, temperature, solution concentration and starting wafer characteristics (doping type, resistivity, crystallographic orientation) is presented. The as-fabricated Si NW arrays were analyzed by field emission scanning electron microscope (FE-SEM) and a linear dependency of nanowire length to both temperature and time was obtained and the change in the growth rate of Si NWs at increased etching durations was shown. Furthermore, the effects of EE parameters on the optical reflectivity of the Si NWs were investigated in this study. Reflectivity measurements show that the 42.8% reflectivity of the starting silicon wafer drops to 1.3%, recorded for 10 µm long Si NW arrays. The remarkable decrease in optical reflectivity indicates that Si NWs have a great potential to be utilized in radial or coaxial p-n heterojunction solar cells that could provide orthogonal photon absorption and enhanced carrier collection.

Investigation on the structural characterization of pulsed p-type porous silicon

NASA Astrophysics Data System (ADS)

Wahab, N. H. Abd; Rahim, A. F. Abd; Mahmood, A.; Yusof, Y.

2017-08-01

P-type Porous silicon (PS) was sucessfully formed by using an electrochemical pulse etching (PC) and conventional direct current (DC) etching techniques. The PS was etched in the Hydrofluoric (HF) based solution at a current density of J = 10 mA/cm2 for 30 minutes from a crystalline silicon wafer with (100) orientation. For the PC process, the current was supplied through a pulse generator with 14 ms cycle time (T) with 10 ms on time (Ton) and pause time (Toff) of 4 ms respectively. FESEM, EDX, AFM, and XRD have been used to characterize the morphological properties of the PS. FESEM images showed that pulse PS (PPC) sample produces more uniform circular structures with estimated average pore sizes of 42.14 nm compared to DC porous (PDC) sample with estimated average size of 16.37nm respectively. The EDX spectrum for both samples showed higher Si content with minimal presence of oxide.

Low cost sol-gel derived SiC-SiO2 nanocomposite as anti reflection layer for enhanced performance of crystalline silicon solar cells

NASA Astrophysics Data System (ADS)

Jannat, Azmira; Lee, Woojin; Akhtar, M. Shaheer; Li, Zhen Yu; Yang, O.-Bong

2016-04-01

This paper describes the preparation, characterizations and the antireflection (AR) coating application in crystalline silicon solar cells of sol-gel derived SiC-SiO2 nanocomposite. The prepared SiC-SiO2 nanocomposite was effectively applied as AR layer on p-type Si-wafer via two step processes, where the sol-gel of precursor solution was first coated on p-type Si-wafer using spin coating at 2000 rpm and then subjected to annealing at 450 °C for 1 h. The crystalline, and structural observations revealed the existence of SiC and SiO2 phases, which noticeably confirmed the formation of SiC-SiO2 nanocomposite. The SiC-SiO2 layer on Si solar cells was found to be an excellent AR coating, exhibiting the low reflectance of 7.08% at wavelengths ranging from 400 to 1000 nm. The fabricated crystalline Si solar cell with SiC-SiO2 nanocomposite AR coating showed comparable power conversion efficiency of 16.99% to the conventional SixNx AR coated Si solar cell. New and effective sol-gel derived SiC-SiO2 AR layer would offer a promising technique to produce high performance Si solar cells with low-cost.

Porosity and thickness effect of porous silicon layer on photoluminescence spectra

NASA Astrophysics Data System (ADS)

Husairi, F. S.; Eswar, K. A.; Guliling, Muliyadi; Khusaimi, Z.; Rusop, M.; Abdullah, S.

2018-05-01

The porous silicon nanostructures was prepared by electrochemical etching of p-type silicon wafer. Porous silicon prepared by using different current density and fix etching time with assistance of halogen lamp. The physical structure of porous silicon measured by the parameters used which know as experimental factor. In this work, we select one of those factors to correlate which optical properties of porous silicon. We investigated the surface morphology by using Surface Profiler (SP) and photoluminescence using Photoluminescence (PL) spectrometer. Different physical characteristics of porous silicon produced when current density varied. Surface profiler used to measure the thickness of porous and the porosity calculated using mass different of silicon. Photoluminescence characteristics of porous silicon depend on their morphology because the size and distribution of pore its self will effect to their exciton energy level. At J=30 mA/cm2 the shorter wavelength produced and it followed the trend of porosity with current density applied.

Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene

DTIC Science & Technology

2014-08-01

Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene by Eugene Zakar, Wayne Churaman, Collin Becker, Bernard Rod, Luke...Laboratory Adelphi, MD 20783-1138 ARL-TR-7025 August 2014 Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene...Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6

One-step preparation of multiwall carbon nanotube/silicon hybrids for solar energy conversion

NASA Astrophysics Data System (ADS)

Lobiak, Egor V.; Bychanok, Dzmitry S.; Shlyakhova, Elena V.; Kuzhir, Polina P.; Maksimenko, Sergey A.; Bulusheva, Lyubov G.; Okotrub, Alexander V.

2016-03-01

The hybrid material consisting of a thin layer of multiwall carbon nanotubes (MWCNTs) on an n-doped silicon wafer was obtained in one step using an aerosol-assisted catalytic chemical vapor deposition. The MWCNTs were grown from a mixture of acetone and ethanol with ˜0.2 wt.% of iron polyoxomolybdate nanocluster of the keplerate-type structure. The samples produced at 800°C and 1050°C were tested as a solar energy converter. It was shown that photoresponse of the hybrid material significantly depends on the presence of structural defects in MWCNTs, being much higher in the case of more defective nanotubes. This is because defects lead to p-doping of nanotubes, whereas the p-n heterojunction between MWCNTs and silicon provides a high efficiency of the solar cell.

Silicon surface passivation by polystyrenesulfonate thin films

NASA Astrophysics Data System (ADS)

Chen, Jianhui; Shen, Yanjiao; Guo, Jianxin; Chen, Bingbing; Fan, Jiandong; Li, Feng; Liu, Haixu; Xu, Ying; Mai, Yaohua

2017-02-01

The use of polystyrenesulfonate (PSS) thin films in a high-quality passivation scheme involving the suppression of minority carrier recombination at the silicon surface is presented. PSS has been used as a dispersant for aqueous poly-3,4-ethylenedioxythiophene. In this work, PSS is coated as a form of thin film on a Si surface. A millisecond level minority carrier lifetime on a high resistivity Si wafer is obtained. The film thickness, oxygen content, and relative humidity are found to be important factors affecting the passivation quality. While applied to low resistivity silicon wafers, which are widely used for photovoltaic cell fabrication, this scheme yields relatively shorter lifetime, for example, 2.40 ms on n-type and 2.05 ms on p-type wafers with a resistivity of 1-5 Ω.cm. However, these lifetimes are still high enough to obtain high implied open circuit voltages (Voc) of 708 mV and 697 mV for n-type and p-type wafers, respectively. The formation of oxides at the PSS/Si interface is suggested to be responsible for the passivation mechanism.

Forming n/p Junctions With An Excimer Laser

NASA Technical Reports Server (NTRS)

Alexander, Paul, Jr.; Campbell, Robert B.; Wong, David C.; Bottenberg, William L.; Byron, Stanley

1988-01-01

Compact equipment yields high-quality solar cells. Computer controls pulses of excimer laser and movement of silcon wafer. Mirrors direct laser beam to wafer. Lenses focus beam to small spot on surface. Process suitable for silicon made by dendritic-web-growth process.

Fabrication of Cantilever-Bump Type Si Probe Card

NASA Astrophysics Data System (ADS)

Park, Jeong-Yong; Lee, Dong-Seok; Kim, Dong-Kwon; Lee, Jong-Hyun

2000-12-01

Probe card is most important part in the test system which selects the good or bad chip of integrated circuit (IC) chips. Silicon vertical probe card is able to test multiple semiconductor chips simultaneously. We presented cantilever-bump type vertical probe card. It was fabricated by dry etching using RIE(reactive ion etching) technique and porous silicon micromachining using silicon direct bonded (SDB) wafer. Cantilevers and bumps were fabricated by isotropic etching using RIE@. 3-dimensional structures were formed by porous silicon micromachining technique using SDB wafer. Contact resistance of fabricated probe card was less than 2 Ω and its life time was more than 200,000 turns. The process used in this work is very simple and reproducible, which has good controllability in the tip dimension and spacing. It is expected that the fabricated probe card can reduce testing time, can promote productivity and enables burn-in test.

Recycling of silicon: from industrial waste to biocompatible nanoparticles for nanomedicine

NASA Astrophysics Data System (ADS)

Kozlov, N. K.; Natashina, U. A.; Tamarov, K. P.; Gongalsky, M. B.; Solovyev, V. V.; Kudryavtsev, A. A.; Sivakov, V.; Osminkina, L. A.

2017-09-01

The formation of photoluminescent porous silicon (PSi) nanoparticles (NPs) is usually based on an expensive semiconductor grade wafers technology. Here, we report a low-cost method of PSi NPs synthesis from the industrial silicon waste remained after the wafer production. The proposed method is based on metal-assisted wet-chemical etching (MACE) of the silicon surface of cm-sized metallurgical grade silicon stones which leads to a nanostructuring of the surface due to an anisotropic etching, with subsequent ultrasound fracturing in water. The obtained PSi NPs exhibit bright red room temperature photoluminescence (PL) and demonstrate similar microstructure and physical characteristics in comparison with the nanoparticles synthesized from semiconductor grade Si wafers. PSi NPs prepared from metallurgical grade silicon stones, similar to silicon NPs synthesized from high purity silicon wafer, show low toxicity to biological objects that open the possibility of using such type of NPs in nanomedicine.

Carrier transport and sensitivity issues in heterojunction with intrinsic thin layer solar cells on N-type crystalline silicon: A computer simulation study

NASA Astrophysics Data System (ADS)

Rahmouni, M.; Datta, A.; Chatterjee, P.; Damon-Lacoste, J.; Ballif, C.; Roca i Cabarrocas, P.

2010-03-01

Heterojunction with intrinsic thin layer or "HIT" solar cells are considered favorable for large-scale manufacturing of solar modules, as they combine the high efficiency of crystalline silicon (c-Si) solar cells, with the low cost of amorphous silicon technology. In this article, based on experimental data published by Sanyo, we simulate the performance of a series of HIT cells on N-type crystalline silicon substrates with hydrogenated amorphous silicon (a-Si:H) emitter layers, to gain insight into carrier transport and the general functioning of these devices. Both single and double HIT structures are modeled, beginning with the initial Sanyo cells having low open circuit voltages but high fill factors, right up to double HIT cells exhibiting record values for both parameters. The one-dimensional numerical modeling program "Amorphous Semiconductor Device Modeling Program" has been used for this purpose. We show that the simulations can correctly reproduce the electrical characteristics and temperature dependence for a set of devices with varying I-layer thickness. Under standard AM1.5 illumination, we show that the transport is dominated by the diffusion mechanism, similar to conventional P/N homojunction solar cells, and tunneling is not required to describe the performance of state-of-the art devices. Also modeling has been used to study the sensitivity of N-c-Si HIT solar cell performance to various parameters. We find that the solar cell output is particularly sensitive to the defect states on the surface of the c-Si wafer facing the emitter, to the indium tin oxide/P-a-Si:H front contact barrier height and to the band gap and activation energy of the P-a-Si:H emitter, while the I-a-Si:H layer is necessary to achieve both high Voc and fill factor, as it passivates the defects on the surface of the c-Si wafer. Finally, we describe in detail for most parameters how they affect current transport and cell properties.

Criteria for improved open-circuit voltage in a-Si :H(N)/c-Si(P) front heterojunction with intrinsic thin layer solar cells

NASA Astrophysics Data System (ADS)

Nath, Madhumita; Chatterjee, P.; Damon-Lacoste, J.; Roca i Cabarrocas, P.

2008-02-01

Hydrog enated amorphous/crystalline silicon "heterojunction with intrinsic thin layer (HIT)" solar cells have gained popularity after it was demonstrated by Sanyo that they can achieve stable conversion efficiencies, as high as crystalline silicon (c-Si) cells, but where the cost may be reduced with the help of amorphous silicon (a-Si:H) low temperature deposition technology. In this article, we study N-a-Si :H/P-c-Si front HIT structures, where light enters through the N-a-Si :H layer. The aim is to examine ways of improving the open-circuit voltage, using computer modeling in conjunction with experiments. We also assess under which conditions such improvements in Voc actually occur. Modeling indicates that for a density of states Nss⩾1013cm-2 on the surface of the P-c-Si wafer facing the emitter layer, Voc is entirely limited by this parameter and is lower than 0.5V. We also learn that it is possible to increase the Voc to ˜0.73V by reducing this defect density to ˜1010cm-2, by reducing the surface recombination speed of the electrons at the back P-c-Si/aluminum contact (SnL), and by improving the lifetime of the carriers (τ ) in the P-c-Si wafer to ˜5ms. Modeling further indicates that when τ ⩽0.1ms, the sensitivity of Voc to SnL vanishes, as very few back-diffusing electrons can reach the back contact. Improvements in Voc by decreasing both the defect density on the surface of the P-c-Si wafer facing the emitter layer and SnL have been achieved in practice by (a) improved passivation thanks to a thin intrinsic polymorphous silicon layer deposited on the c-Si wafer (instead of a-Si :H) and (b) using localized aluminum and back surface field layers to attain a lower SnL. Experimentally, a Voc of 0.675V has already been attained. Simulations indicate that the lifetime of carriers inside the P-c-Si wafer of these cells is ˜366μs and needs to be improved to achieve a higher Voc.

Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

NASA Astrophysics Data System (ADS)

Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

2017-10-01

Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

Electrical and optical properties of sub-10 nm nickel silicide films for silicon solar cells

NASA Astrophysics Data System (ADS)

Brahmi, Hatem; Ravipati, Srikanth; Yarali, Milad; Shervin, Shahab; Wang, Weijie; Ryou, Jae-Hyun; Mavrokefalos, Anastassios

2017-01-01

Highly conductive and transparent films of ultra-thin p-type nickel silicide films have been prepared by RF magnetron sputtering of nickel on silicon substrates followed by rapid thermal annealing in an inert environment in the temperature range 400-600 °C. The films are uniform throughout the wafer with thicknesses in the range of 3-6 nm. The electrical and optical properties are presented for nickel silicide films with varying thickness. The Drude-Lorentz model and Fresnel equations were used to calculate the dielectric properties, sheet resistance, absorption and transmission of the films. These ultrathin nickel silicide films have excellent optoelectronic properties for p-type contacts with optical transparencies up to 80% and sheet resistance as low as ~0.15 µΩ cm. Furthermore, it was shown that the use of a simple anti-reflection (AR) coating can recover most of the reflected light approaching the values of a standard Si solar cell with the same AR coating. Overall, the combination of ultra-low thickness, high transmittance, low sheet resistance and ability to recover the reflected light by utilizing standard AR coating makes them ideal for utilization in silicon based photovoltaic technologies as a p-type transparent conductor.

Improved Starting Materials for Back-Illuminated Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2009-01-01

An improved type of starting materials for the fabrication of silicon-based imaging integrated circuits that include back-illuminated photodetectors has been conceived, and a process for making these starting materials is undergoing development. These materials are intended to enable reductions in dark currents and increases in quantum efficiencies, relative to those of comparable imagers made from prior silicon-on-insulator (SOI) starting materials. Some background information is prerequisite to a meaningful description of the improved starting materials and process. A prior SOI starting material, depicted in the upper part the figure, includes: a) A device layer on the front side, typically between 2 and 20 m thick, made of p-doped silicon (that is, silicon lightly doped with an electron acceptor, which is typically boron); b) A buried oxide (BOX) layer (that is, a buried layer of oxidized silicon) between 0.2 and 0.5 m thick; and c) A silicon handle layer (also known as a handle wafer) on the back side, between about 600 and 650 m thick. After fabrication of the imager circuitry in and on the device layer, the handle wafer is etched away, the BOX layer acting as an etch stop. In subsequent operation of the imager, light enters from the back, through the BOX layer. The advantages of back illumination over front illumination have been discussed in prior NASA Tech Briefs articles.

Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

NASA Astrophysics Data System (ADS)

Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

2015-04-01

In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on-off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10-13-10-11 µm2/Hz for n-type and 10-12-10-10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

Electrochemical method for defect delineation in silicon-on-insulator wafers

DOEpatents

Guilinger, Terry R.; Jones, Howland D. T.; Kelly, Michael J.; Medernach, John W.; Stevenson, Joel O.; Tsao, Sylvia S.

1991-01-01

An electrochemical method for defect delineation in thin-film SOI or SOS wafers in which a surface of a silicon wafer is electrically connected so as to control the voltage of the surface within a specified range, the silicon wafer is then contacted with an electrolyte, and, after removing the electrolyte, defects and metal contamination in the silicon wafer are identified.

Deconvoluting the mechanism of microwave annealing of block copolymer thin films.

PubMed

Jin, Cong; Murphy, Jeffrey N; Harris, Kenneth D; Buriak, Jillian M

2014-04-22

The self-assembly of block copolymer (BCP) thin films is a versatile method for producing periodic nanoscale patterns with a variety of shapes. The key to attaining a desired pattern or structure is the annealing step undertaken to facilitate the reorganization of nanoscale phase-segregated domains of the BCP on a surface. Annealing BCPs on silicon substrates using a microwave oven has been shown to be very fast (seconds to minutes), both with and without contributions from solvent vapor. The mechanism of the microwave annealing process remains, however, unclear. This work endeavors to uncover the key steps that take place during microwave annealing, which enable the self-assembly process to proceed. Through the use of in situ temperature monitoring with a fiber optic temperature probe in direct contact with the sample, we have demonstrated that the silicon substrate on which the BCP film is cast is the dominant source of heating if the doping of the silicon wafer is sufficiently low. Surface temperatures as high as 240 °C are reached in under 1 min for lightly doped, high resistivity silicon wafers (n- or p-type). The influence of doping, sample size, and BCP composition was analyzed to rule out other possible mechanisms. In situ temperature monitoring of various polymer samples (PS, P2VP, PMMA, and the BCPs used here) showed that the polymers do not heat to any significant extent on their own with microwave irradiation of this frequency (2.45 GHz) and power (∼600 W). It was demonstrated that BCP annealing can be effectively carried out in 60 s on non-microwave-responsive substrates, such as highly doped silicon, indium tin oxide (ITO)-coated glass, glass, and Kapton, by placing a piece of high resistivity silicon wafer in contact with the sample-in this configuration, the silicon wafer is termed the heating element. Annealing and self-assembly of polystyrene-block-poly(2-vinylpyridine) (PS-b-P2VP) and polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) BCPs into horizontal cylinder structures were shown to take place in under 1 min, using a silicon wafer heating element, in a household microwave oven. Defect densities were calculated and were shown to decrease with higher maximum obtained temperatures. Conflicting results in the literature regarding BCP annealing with microwave are explained in light of the results obtained in this study.

Formation and characterization of ZnS/CdS nanocomposite materials into porous silicon

NASA Astrophysics Data System (ADS)

Xue, Tao; Lv, Xiao-yi; Jia, Zhen-hong; Hou, Jun-wei; Jian, Ji-kang

2008-11-01

ZnS/CdS were deposited by chemical vapor deposition (CVD) technique on porous silicon substrates formed by electrochemical anodization of n-type (100) silicon wafer. The optical properties of ZnS/CdS porous silicon composite materials are studied. The results showed that new luminescence characteristics such as strong and stable visible-light emissions with different colors were observed from the ZnS/CdS-PS nanocomposite materials at room temperature.

Synthesis and Characterization of Silicon Nanowires by Electroless Etching

NASA Astrophysics Data System (ADS)

Bhujel, Rabina; Rizal, Umesh; Agarwal, Amit; Swain, Bhabani S.; Swain, Bibhu P.

2018-02-01

Silicon nanowires (SiNWs) were synthesized by two-step electroless etching of p-type Si (100) wafer and characterized by field emission scanning electron microscopy, UV-Vis spectroscopy, x-ray photoelectron spectroscopy, Fourier transform infrared spectroscopy and Raman spectroscopy. The vibrational signature at 1108 and 2087 cm-1 confirmed SiNWs were passivated by both oxygen and hydrogen atoms. Raman peak at 517 cm-1 indicated crystalline SiNWs with tailing toward redshift due to Fano effect. The Si(2p) and Si(2s) core orbital spectra of SiNWs were found at 99.8 and 150.5 eV, respectively. Moreover, the reflection of SiNWs is minimized to 1 to 5% in the 650-nm wavelength.

Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

2018-04-01

In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

PubMed

Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

2014-05-13

The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

Large-aperture focusing of x rays with micropore optics using dry etching of silicon wafers.

PubMed

Ezoe, Yuichiro; Moriyama, Teppei; Ogawa, Tomohiro; Kakiuchi, Takuya; Mitsuishi, Ikuyuki; Mitsuda, Kazuhisa; Aoki, Tatsuhiko; Morishita, Kohei; Nakajima, Kazuo

2012-03-01

Large-aperture focusing of Al K(α) 1.49 keV x-ray photons using micropore optics made from a dry-etched 4 in. (100 mm) silicon wafer is demonstrated. Sidewalls of the micropores are smoothed with high-temperature annealing to work as x-ray mirrors. The wafer is bent to a spherical shape to collect parallel x rays into a focus. Our result supports that this new type of optics allows for the manufacturing of ultralight-weight and high-performance x-ray imaging optics with large apertures at low cost. © 2012 Optical Society of America

Structural, Optical and Electrical Properties of ZnS/Porous Silicon Heterostructures

NASA Astrophysics Data System (ADS)

Wang, Cai-Feng; Li, Qing-Shan; Lv, Lei; Zhang, Li-Chun; Qi, Hong-Xia; Chen, Hou

2007-03-01

ZnS films are deposited by pulsed laser deposition on porous silicon (PS) substrates formed by electrochemical anodization of p-type (100) silicon wafer. Scanning electron microscope images reveal that the surface of ZnS films is unsmoothed, and there are some cracks in the ZnS films due to the roughness of the PS surface. The x-ray diffraction patterns show that the ZnS films on PS surface are grown in preferring orientation along cubic phase β-ZnS (111) direction. White light emission is obtained by combining the blue-green emission from ZnS films with the orange-red emission from PS layers. Based on the I-V characteristic, the ZnS/PS heterojunction exhibits the rectifying junction behaviour, and an ideality factor n is calculated to be 77 from the I-V plot.

Effect of substrates on Zinc Oxide thin films fabrication using sol-gel method

NASA Astrophysics Data System (ADS)

Kadir, Rosmalini Ab; Taib, Nurmalina Mohd; Ahmad, Wan Rosmaria Wan; Aziz, Anees Abdul; Sabirin Zoolfakar, Ahmad

2018-03-01

The properties of ZnO thin films were deposited on three different substrates via dip coating method was investigated. The films were prepared on glass, ITO and p-type silicon. Characterization of the film revealed that the properties of the dip coated ZnO thin films were influenced by the type of substrates. The grains on ITO and glass were ∼10 nm in size while the grains on wafer agglomerate together to form a denser film. Studies of the optical properties using UV-VIS-NIR of the fabricated films demonstrated that glass has the highest transmittance compared to ITO.

Two-Dimensional Metal-Free Organic Multiferroic Material for Design of Multifunctional Integrated Circuits.

PubMed

Tu, Zhengyuan; Wu, Menghao; Zeng, Xiao Cheng

2017-05-04

Coexistence of ferromagnetism and ferroelectricity in a single 2D material is highly desirable for integration of multifunctional units in 2D material-based circuits. We report theoretical evidence of C 6 N 8 H organic network as being the first 2D organic multiferroic material with coexisting ferromagnetic and ferroelectric properties. The ferroelectricity stems from multimode proton-transfer within the 2D C 6 N 8 H network, in which a long-range proton-transfer mode is enabled by the facilitation of oxygen molecule when the network is exposed to the air. Such oxygen-assisted ferroelectricity also leads to a high Curie temperature and coupling between ferroelectricity and ferromagnetism. We also find that hydrogenation and carbon doping can transform the 2D g-C 3 N 4 network from an insulator to an n-type/p-type magnetic semiconductor with modest bandgap. Akin to the dopant induced n/p channels in silicon wafer, a variety of dopant created functional units can be integrated into the g-C 3 N 4 wafer by design for nanoelectronic applications.

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

PubMed

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

NASA Astrophysics Data System (ADS)

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the device silicon layer during micro-fabrication.

Cu gettering by phosphorus-doped emitters in p-type silicon: Effect on light-induced degradation

NASA Astrophysics Data System (ADS)

Inglese, Alessandro; Laine, Hannu S.; Vähänissi, Ville; Savin, Hele

2018-01-01

The presence of copper (Cu) contamination is known to cause relevant light-induced degradation (Cu-LID) effects in p-type silicon. Due to its high diffusivity, Cu is generally regarded as a relatively benign impurity, which can be readily relocated during device fabrication from the wafer bulk, i.e. the region affected by Cu-LID, to the surface phosphorus-doped emitter. This contribution examines in detail the impact of gettering by industrially relevant phosphorus layers on the strength of Cu-LID effects. We find that phosphorus gettering does not always prevent the occurrence of Cu-LID. Specifically, air-cooling after an isothermal anneal at 800°C results in only weak impurity segregation to the phosphorus-doped layer, which turns out to be insufficient for effectively mitigating Cu-LID effects. Furthermore, we show that the gettering efficiency can be enhanced through the addition of a slow cooling ramp (-4°C/min) between 800°C and 600°C, resulting in the nearly complete disappearance of Cu-LID effects.

A new approach to measure the temperature in rapid thermal processing

NASA Astrophysics Data System (ADS)

Yan, Jiang

This dissertation has presented the research work about a new method to measure the temperatures for the silicon wafer. The new technology is mainly for the rapid thermal processing (RTP) system. RTP is a promising technology in semiconductor manufacturing especially for the devices with minimum feature size less than 0.5 μm. The technique to measure the temperatures of the silicon wafer accurately is the key factor to apply the RTP technology to more critical processes in the manufacturing. Two methods which are mostly used nowadays, thermocouples and pyrometer, all have the limitation to be applied in the RTP. This is the motivation to study the new method using acoustic waves for the temperature measurement. The test system was designed and built up for the study of the acoustic method. The whole system mainly includes the transducer unit, circuit hardware, control software, the computer, and the chamber. The acoustic wave was generated by the PZT-5H transducer. The wave travels through the quartz rod into the silicon wafer. After traveling a certain distances in the wafer, the acoustic waves could be received by other transducers. By measuring the travel time and with the travel distance, the velocity of the acoustic wave traveling in the silicon wafer can be calculated. Because there is a relationship between the velocity and the temperature: the velocities of the acoustic waves traveling in the silicon wafer decrease as the temperatures of the wafer increase, the temperature of the wafer can be finally obtained. The thermocouples were used to check the measurement accuracy of the acoustic method. The temperature mapping across the 8″ silicon wafer was obtained with four transducer sensor unit. The temperatures of the wafer were measured using acoustic method at both static and dynamic status. The main purpose of the tests is to know the measurement accuracy for the new method. The goal of the research work regarding to the accuracy is <=+/-3°C. The measurement was also done under the different wafer conditions in order to clarify that the acoustic method is independent of the wafer conditions.

Silicon sample holder for molecular beam epitaxy on pre-fabricated integrated circuits

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Grunthaner, Paula J. (Inventor); Grunthaner, Frank J. (Inventor)

1994-01-01

The sample holder of the invention is formed of the same semiconductor crystal as the integrated circuit on which the molecular beam expitaxial process is to be performed. In the preferred embodiment, the sample holder comprises three stacked micro-machined silicon wafers: a silicon base wafer having a square micro-machined center opening corresponding in size and shape to the active area of a CCD imager chip, a silicon center wafer micro-machined as an annulus having radially inwardly pointing fingers whose ends abut the edges of and center the CCD imager chip within the annulus, and a silicon top wafer micro-machined as an annulus having cantilevered membranes which extend over the top of the CCD imager chip. The micro-machined silicon wafers are stacked in the order given above with the CCD imager chip centered in the center wafer and sandwiched between the base and top wafers. The thickness of the center wafer is about 20% less than the thickness of the CCD imager chip. Preferably, four titanium wires, each grasping the edges of the top and base wafers, compress all three wafers together, flexing the cantilever fingers of the top wafer to accommodate the thickness of the CCD imager chip, acting as a spring holding the CCD imager chip in place.

Applications of the silicon wafer direct-bonding technique to electron devices

NASA Astrophysics Data System (ADS)

Furukawa, K.; Nakagawa, A.

1990-01-01

A silicon wafer direct-bonding (SDB) technique has been developed. A pair of bare silicon wafers, as well as an oxidized wafer pair, are bonded throughout the wafer surfaces without any bonding material. Conventional semiconductor device processes can be used for the bonded wafers, since the bonded interface is stable thermally, chemically, mechanically and electrically. Therefore, the SDB technique is very attractive, and has been applied to several kinds of electron devices. Bare silicon to bare silicon bonding is an alternative for epitaxial growth. A thick, high quality and high resistivity layer on a low resistivity substrate was obtained without autodoping. 1800 V insulated gate bipolar transistors were developed using these SDB wafers. No electrical resistance was observed at the bonded bare silicon interfaces. If oxidized wafers are bonded, the two wafers are electrically isolated, providing silicon on insulator (SOI) wafers. Dielectrically isolated photodiode arrays were fabricated on the SOI wafers and 500 V power IC's are now being developed.

Surface plasmons based terahertz modulator consisting of silicon-air-metal-dielectric-metal layers

NASA Astrophysics Data System (ADS)

Wang, Wei; Yang, Dongxiao; Qian, Zhenhai

2018-05-01

An optically controlled modulator of the terahertz wave, which is composed of a metal-dielectric-metal structure etched with circular loop arrays on both the metal layers and a photoexcited silicon wafer separated by an air layer, is proposed. Simulation results based on experimentally measured complex permittivities predict that modification of complex permittivity of the silicon wafer through excitation laser leads to a significant tuning of transmission characteristics of the modulator, forming the modulation depths of 59.62% and 96.64% based on localized surface plasmon peak and propagating surface plasmon peak, respectively. The influences of the complex permittivity of the silicon wafer and the thicknesses of both the air layer and the silicon wafer are numerically studied for better understanding the modulation mechanism. This study proposes a feasible methodology to design an optically controlled terahertz modulator with large modulation depth, high speed and suitable insertion loss, which is useful for terahertz applications in the future.

Three-dimensional crossbar arrays of self-rectifying Si/SiO 2/Si memristors

DOE PAGES

Li, Can; Han, Lili; Jiang, Hao; ...

2017-06-05

Memristors are promising building blocks for the next generation memory, unconventional computing systems and beyond. Currently common materials used to build memristors are not necessarily compatible with the silicon dominant complementary metal-oxide-semiconductor (CMOS) technology. Furthermore, external selector devices or circuits are usually required in order for large memristor arrays to function properly, resulting in increased circuit complexity. Here we demonstrate fully CMOS-compatible, all-silicon based and self-rectifying memristors that negate the need for external selectors in large arrays. It consists of p- and n-type doped single crystalline silicon electrodes and a thin chemically produced silicon oxide switching layer. The device exhibitsmore » repeatable resistance switching behavior with high rectifying ratio (10 5), high ON/OFF conductance ratio (10 4) and attractive retention at 300 °C. We further build a 5-layer 3-dimensional (3D) crossbar array of 100 nm memristors by stacking fluid supported silicon membranes. The CMOS compatibility and self-rectifying behavior open up opportunities for mass production of memristor arrays and 3D hybrid circuits on full-wafer scale silicon and flexible substrates without increasing circuit complexity.« less

Micromachined silicon electrostatic chuck

DOEpatents

Anderson, R.A.; Seager, C.H.

1996-12-10

An electrostatic chuck is faced with a patterned silicon plate, created by micromachining a silicon wafer, which is attached to a metallic base plate. Direct electrical contact between the chuck face (patterned silicon plate`s surface) and the silicon wafer it is intended to hold is prevented by a pattern of flat-topped silicon dioxide islands that protrude less than 5 micrometers from the otherwise flat surface of the chuck face. The islands may be formed in any shape. Islands may be about 10 micrometers in diameter or width and spaced about 100 micrometers apart. One or more concentric rings formed around the periphery of the area between the chuck face and wafer contain a low-pressure helium thermal-contact gas used to assist heat removal during plasma etching of a silicon wafer held by the chuck. The islands are tall enough and close enough together to prevent silicon-to-silicon electrical contact in the space between the islands, and the islands occupy only a small fraction of the total area of the chuck face, typically 0.5 to 5 percent. The pattern of the islands, together with at least one hole bored through the silicon veneer into the base plate, will provide sufficient gas-flow space to allow the distribution of the helium thermal-contact gas. 6 figs.

Silicon micro-mold

DOEpatents

Morales, Alfredo M [Livermore, CA

2006-10-24

The present invention describes a method for rapidly fabricating a robust 3-dimensional silicon-mold for use in preparing complex metal micro-components. The process begins by depositing a conductive metal layer onto one surface of a silicon wafer. A thin photoresist and a standard lithographic mask are then used to transfer a trace image pattern onto the opposite surface of the wafer by exposing and developing the resist. The exposed portion of the silicon substrate is anisotropically etched through the wafer thickness down to conductive metal layer to provide an etched pattern consisting of a series of rectilinear channels and recesses in the silicon which serve as the silicon micro-mold. Microcomponents are prepared with this mold by first filling the mold channels and recesses with a metal deposit, typically by electroplating, and then removing the silicon micro-mold by chemical etching.

Investigation of Defects Origin in p-Type Si for Solar Applications

NASA Astrophysics Data System (ADS)

Gwóźdź, Katarzyna; Placzek-Popko, Ewa; Mikosza, Maciej; Zielony, Eunika; Pietruszka, Rafal; Kopalko, Krzysztof; Godlewski, Marek

2017-07-01

In order to improve the efficiency of a solar cell based on silicon, one must find a compromise between its price and crystalline quality. That is precisely why the knowledge of defects present in the material is of primary importance. This paper studies the defects in commercially available cheap Schottky titanium/gold silicon wafers. The electrical properties of the diodes were defined by using current-voltage and capacitance-voltage measurements. Low series resistance and ideality factor are proofs of the good quality of the sample. The concentration of the acceptors is in accordance with the manufacturer's specifications. Deep level transient spectroscopy measurements were used to identify the defects. Three hole traps were found with activation energies equal to 0.093 eV, 0.379 eV, and 0.535 eV. Comparing the values with the available literature, the defects were determined as connected to the presence of iron interstitials in the silicon. The quality of the silicon wafer seems good enough to use it as a substrate for the solar cell heterojunctions.

Method using laser irradiation for the production of atomically clean crystalline silicon and germanium surfaces

DOEpatents

Ownby, G.W.; White, C.W.; Zehner, D.M.

1979-12-28

This invention relates to a new method for removing surface impurities from crystalline silicon or germanium articles, such as off-the-shelf p- or n-type wafers to be doped for use as junction devices. The principal contaminants on such wafers are oxygen and carbon. The new method comprises laser-irradiating the contaminated surface in a non-reactive atmosphere, using one or more of Q-switched laser pulses whose parameters are selected to effect melting of the surface without substantial vaporization thereof. In a typical application, a plurality of pulses is used to convert a surface region of an off-the-shelf silicon wafer to an atomically clean region. This can be accomplished in a system at a pressure below 10-/sup 8/ Torr, using Q-switched ruber-laser pulses having an energy density in the range of from about 60 to 190 MW/cm/sup 2/.

Method using laser irradiation for the production of atomically clean crystalline silicon and germanium surfaces

DOEpatents

Ownby, Gary W.; White, Clark W.; Zehner, David M.

1981-01-01

This invention relates to a new method for removing surface impurities from crystalline silicon or germanium articles, such as off-the-shelf p- or n-type wafers to be doped for use as junction devices. The principal contaminants on such wafers are oxygen and carbon. The new method comprises laser-irradiating the contaminated surface in a non-reactive atmosphere, using one or more of Q-switched laser pulses whose parameters are selected to effect melting of the surface without substantial vaporization thereof. In a typical application, a plurality of pulses is used to convert a surface region of an off-the-shelf silicon wafer to an automatically clean region. This can be accomplished in a system at a pressure below 10.sup.-8 Torr, using Q-switched ruby-laser pulses having an energy density in the range of from about 60 to 190 MW/cm.sup.2.

Exceptional gettering response of epitaxially grown kerfless silicon

DOE PAGES

Powell, D. M.; Markevich, V. P.; Hofstetter, J.; ...

2016-02-08

The bulk minority-carrier lifetime in p- and n-type kerfless epitaxial (epi) crystalline silicon wafers is shown to increase >500 during phosphorus gettering. We employ kinetic defect simulations and microstructural characterization techniques to elucidate the root cause of this exceptional gettering response. Simulations and deep-level transient spectroscopy (DLTS) indicate that a high concentra- tion of point defects (likely Pt) is “locked in” during fast (60 C/min) cooling during epi wafer growth. The fine dispersion of moderately fast-diffusing recombination-active point defects limits as-grown lifetime but can also be removed during gettering, confirmed by DLTS measurements. Synchrotron-based X-ray fluorescence microscopy indicates metal agglomeratesmore » at structural defects, yet the structural defect density is sufficiently low to enable high lifetimes. Consequently, after phosphorus diffusion gettering, epi silicon exhibits a higher lifetime than materials with similar bulk impurity contents but higher densities of structural defects, including multicrystalline ingot and ribbon silicon materials. As a result, device simulations suggest a solar-cell efficiency potential of this material >23%.« less

Fabrication of a high aspect ratio thick silicon wafer mold and electroplating using flipchip bonding for MEMS applications

NASA Astrophysics Data System (ADS)

Kim, Bong-Hwan; Kim, Jong-Bok

2009-06-01

We have developed a microfabrication process for high aspect ratio thick silicon wafer molds and electroplating using flipchip bonding with THB 151N negative photoresist (JSR micro). This fabrication technique includes large area and high thickness silicon wafer mold electroplating. The process consists of silicon deep reactive ion etching (RIE) of the silicon wafer mold, photoresist bonding between the silicon mold and the substrate, nickel electroplating and a silicon removal process. High thickness silicon wafer molds were made by deep RIE and flipchip bonding. In addition, nickel electroplating was developed. Dry film resist (ORDYL MP112, TOK) and thick negative-tone photoresist (THB 151N, JSR micro) were used as bonding materials. In order to measure the bonding strength, the surface energy was calculated using a blade test. The surface energy of the bonding wafers was found to be 0.36-25.49 J m-2 at 60-180 °C for the dry film resist and 0.4-1.9 J m-2 for THB 151N in the same temperature range. Even though ORDYL MP112 has a better value of surface energy than THB 151N, it has a critical disadvantage when it comes to removing residue after electroplating. The proposed process can be applied to high aspect ratio MEMS structures, such as air gap inductors or vertical MEMS probe tips.

Plasma deposition of amorphous silicon carbide thin films irradiated with neutrons

NASA Astrophysics Data System (ADS)

Huran, J.; Bohacek, P.; Kucera, M.; Kleinova, A.; Sasinkova, V.; IEE SAS, Bratislava, Slovakia Team; Polymer Institute, SAS, Bratislava, Slovakia Team; Institute of Chemistry, SAS, Bratislava, Slovakia Team

2015-09-01

Amorphous silicon carbide and N-doped silicon carbide thin films were deposited on P-type Si(100) wafer by plasma enhanced chemical vapor deposition (PECVD) technology using silane, methane, ammonium and argon gases. The concentration of elements in the films was determined by RBS and ERDA method. Chemical compositions were analyzed by FTIR spectroscopy. Photoluminescence properties were studied by photoluminescence spectroscopy (PL). Irradiation of samples with various neutron fluencies was performed at room temperature. The films contain silicon, carbon, hydrogen, nitrogen and small amount of oxygen. From the IR spectra, the films contained Si-C, Si-H, C-H, Si-N, N-H and Si-O bonds. No significance effect on the IR spectra after neutron irradiation was observed. PL spectroscopy results of films showed decreasing PL intensity after neutron irradiation and PL intensity decreased with increased neutron fluencies. The measured current of the prepared structures increased after irradiation with neutrons and rise up with neutron fluencies.

Method for implementation of back-illuminated CMOS or CCD imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor)

2008-01-01

A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

Silicon micro-mold and method for fabrication

DOEpatents

Morales, Alfredo M.

2005-01-11

The present invention describes a method for rapidly fabricating a robust 3-dimensional silicon micro-mold for use in preparing complex metal micro-components. The process begins by depositing a conductive metal layer onto one surface of a silicon wafer. A thin photoresist and a standard lithographic mask are then used to transfer a trace image pattern onto the opposite surface of the wafer by exposing and developing the resist. The exposed portion of the silicon substrate is anisotropically etched through the wafer thickness down to conductive metal layer to provide an etched pattern consisting of a series of rectilinear channels and recesses in the silicon which serve as the silicon micro-mold. Microcomponents are prepared with this mold by first filling the mold channels and recesses with a metal deposit, typically by electroplating, and then removing the silicon micro-mold by chemical etching.

Fabricating a Microcomputer on a Single Silicon Wafer

NASA Technical Reports Server (NTRS)

Evanchuk, V. L.

1983-01-01

Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

Silicon vacancy-related centers in non-irradiated 6H-SiC nanostructure

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bagraev, N. T., E-mail: Impurity.Dipole@mail.ioffe.ru; Danilovskii, E. Yu.; Gets, D. S.

2015-05-15

We present the first findings of the silicon vacancy related centers identified in the non-irradiated 6H-SiC nanostructure using the electron spin resonance (ESR) and electrically-detected (ED) ESR technique. This planar 6H-SiC nanostructure represents the ultra-narrow p-type quantum well confined by the δ-barriers heavily doped with boron on the surface of the n-type 6H-SiC(0001) wafer. The new EDESR technique by measuring the only magnetoresistance of the 6H-SiC nanostructure under the high frequency generation from the δ-barriers appears to allow the identification of the isolated silicon vacancy centers as well as the triplet center with spin state S = 1. The samemore » triplet center that is characterized by the large value of the zero-field splitting constant D and anisotropic g-factor is revealed by the ESR (X-band) method. The hyperfine (HF) lines in the ESR and EDESR spectra originating from the HF interaction with the {sup 14}N nucleus seem to attribute this triplet center to the N-V{sub Si} defect.« less

Study of white light emission from ZnS/PS composite system

NASA Astrophysics Data System (ADS)

Wang, Caifeng; Li, Qingshan; Lu, Lei; Zhang, Lichun; Qi, Hongxia

2007-09-01

ZnS films were deposited by pulsed laser deposition (PLD) on porous silicon (PS) substrates formed by electrochemical anodization of p-type (100) silicon wafer. The photoluminescence (PL) spectra of ZnS/PS composites were measured at room temperature. Under different excitation wavelengths, the relative integrated intensities of the red light emission from PS layers and the blue-green emission from ZnS films had different values. After samples were annealed in vacuum at different temperatures (200, 300, and 400 Celsius degree) for 30 min respectively, a new green emission located at around 550 nm appeared in the PL spectra of all ZnS/PS samples, and all of the ZnS/PS composites had a broad PL band (450-700 nm) in the visible region, exhibiting intensively white light emission.

Preparation and Thermal Characterization of Annealed Gold Coated Porous Silicon

PubMed Central

Behzad, Kasra; Mat Yunus, Wan Mahmood; Talib, Zainal Abidin; Zakaria, Azmi; Bahrami, Afarin

2012-01-01

Porous silicon (PSi) layers were formed on a p-type Si wafer. Six samples were anodised electrically with a 30 mA/cm2 fixed current density for different etching times. The samples were coated with a 50–60 nm gold layer and annealed at different temperatures under Ar flow. The morphology of the layers, before and after annealing, formed by this method was investigated by scanning electron microscopy (SEM). Photoacoustic spectroscopy (PAS) measurements were carried out to measure the thermal diffusivity (TD) of the PSi and Au/PSi samples. For the Au/PSi samples, the thermal diffusivity was measured before and after annealing to study the effect of annealing. Also to study the aging effect, a comparison was made between freshly annealed samples and samples 30 days after annealing. PMID:28817037

Detecting Fermi-level shifts by Auger electron spectroscopy in Si and GaAs

NASA Astrophysics Data System (ADS)

Debehets, J.; Homm, P.; Menghini, M.; Chambers, S. A.; Marchiori, C.; Heyns, M.; Locquet, J. P.; Seo, J. W.

2018-05-01

In this paper, changes in surface Fermi-level of Si and GaAs, caused by doping and cleaning, are investigated by Auger electron spectroscopy. Based on the Auger voltage contrast, we compared the Auger transition peak energy but with higher accuracy by using a more accurate analyzer and an improved peak position determination method. For silicon, a peak shift as large as 0.46 eV was detected when comparing a cleaned p-type and n-type wafer, which corresponds rather well with the theoretical difference in Fermi-levels. If no cleaning was applied, the peak position did not differ significantly for both wafer types, indicating Fermi-level pinning in the band gap. For GaAs, peak shifts were detected after cleaning with HF and (NH4)2S-solutions in an inert atmosphere (N2-gas). Although the (NH4)2S-cleaning in N2 is very efficient in removing the oxygen from the surface, the observed Ga- and As-peak shifts are smaller than those obtained after the HF-cleaning. It is shown that the magnitude of the shift is related to the surface composition. After Si-deposition on the (NH4)2S-cleaned surface, the Fermi-level shifts back to a similar position as observed for an as-received wafer, indicating that this combination is not successful in unpinning the Fermi-level of GaAs.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

Preparation and Thermal Characterization of Annealed Gold Coated Porous Silicon.

PubMed

Behzad, Kasra; Mat Yunus, Wan Mahmood; Talib, Zainal Abidin; Zakaria, Azmi; Bahrami, Afarin

2012-01-16

Porous silicon (PSi) layers were formed on a p-type Si wafer. Six samples were anodised electrically with a 30 mA/cm² fixed current density for different etching times. The samples were coated with a 50-60 nm gold layer and annealed at different temperatures under Ar flow. The morphology of the layers, before and after annealing, formed by this method was investigated by scanning electron microscopy (SEM). Photoacoustic spectroscopy (PAS) measurements were carried out to measure the thermal diffusivity (TD) of the PSi and Au/PSi samples. For the Au/PSi samples, the thermal diffusivity was measured before and after annealing to study the effect of annealing. Also to study the aging effect, a comparison was made between freshly annealed samples and samples 30 days after annealing.

Formation of silicon carbide by laser ablation in graphene oxide-N-methyl-2-pyrrolidone suspension on silicon surface

NASA Astrophysics Data System (ADS)

Jaleh, Babak; Ghasemi, Samaneh; Torkamany, Mohammad Javad; Salehzadeh, Sadegh; Maleki, Farahnaz

2018-01-01

Laser ablation of a silicon wafer in graphene oxide-N-methyl-2-pyrrolidone (GO-NMP) suspension was carried out with a pulsed Nd:YAG laser (pulse duration = 250 ns, wavelength = 1064 nm). The surface of silicon wafer before and after laser ablation was studied using optical microscopy, scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX). The results showed that the ablation of silicon surface in liquid by pulsed laser was done by the process of melt expulsion under the influence of the confined plasma-induced pressure or shock wave trapped between the silicon wafer and the liquid. The X-ray diffraction‌ (XRD) pattern of Si wafer after laser ablation showed that 4H-SiC layer is formed on its surface. The formation of the above layer was also confirmed by Raman spectroscopy, and X-ray photoelectron spectroscopy‌ (XPS), as well as EDX was utilized. The reflectance of samples decreased with increasing pulse energy. Therefore, the morphological alteration and the formation of SiC layer at high energy increase absorption intensity in the UV‌-vis regions. Theoretical calculations confirm that the formation of silicon carbide from graphene oxide and silicon wafer is considerably endothermic. Development of new methods for increasing the reflectance without causing harmful effects is still an important issue for crystalline Si solar cells. By using the method described in this paper, the optical properties of solar cells can be improved.

Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

NASA Astrophysics Data System (ADS)

Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

2017-08-01

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

Micromachined silicon electrostatic chuck

DOEpatents

Anderson, Robert A.; Seager, Carleton H.

1996-01-01

An electrostatic chuck is faced with a patterned silicon plate 11, created y micromachining a silicon wafer, which is attached to a metallic base plate 13. Direct electrical contact between the chuck face 15 (patterned silicon plate's surface) and the silicon wafer 17 it is intended to hold is prevented by a pattern of flat-topped silicon dioxide islands 19 that protrude less than 5 micrometers from the otherwise flat surface of the chuck face 15. The islands 19 may be formed in any shape. Islands may be about 10 micrometers in diameter or width and spaced about 100 micrometers apart. One or more concentric rings formed around the periphery of the area between the chuck face 15 and wafer 17 contain a low-pressure helium thermal-contact gas used to assist heat removal during plasma etching of a silicon wafer held by the chuck. The islands 19 are tall enough and close enough together to prevent silicon-to-silicon electrical contact in the space between the islands, and the islands occupy only a small fraction of the total area of the chuck face 15, typically 0.5 to 5 percent. The pattern of the islands 19, together with at least one hole 12 bored through the silicon veneer into the base plate, will provide sufficient gas-flow space to allow the distribution of the helium thermal-contact gas.

Model-based correction for local stress-induced overlay errors

NASA Astrophysics Data System (ADS)

Stobert, Ian; Krishnamurthy, Subramanian; Shi, Hongbo; Stiffler, Scott

2018-03-01

Manufacturing embedded DRAM deep trench capacitors can involve etching very deep holes into silicon wafers1. Due to various design constraints, these holes may not be uniformly distributed across the wafer surface. Some wafer processing steps for these trenches results in stress effects which can distort the silicon wafer in a manner that creates localized alignment issues between the trenches and the structures built above them on the wafer. In this paper, we describe a method to model these localized silicon distortions for complex layouts involving billions of deep trench structures. We describe wafer metrology techniques and data which have been used to verify the stress distortion model accuracy. We also provide a description of how this kind of model can be used to manipulate the polygons in the mask tape out flow to compensate for predicted localized misalignments between design shapes from a deep trench mask and subsequent masks.

Interferometric thickness calibration of 300 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Quandou; Griesmann, Ulf; Polvani, Robert

2005-12-01

The "Improved Infrared Interferometer" (IR 3) at the National Institute of Standards and Technology (NIST) is a phase-measuring interferometer, operating at a wavelength of 1550 nm, which is being developed for measuring the thickness and thickness variation of low-doped silicon wafers with diameters up to 300 mm. The purpose of the interferometer is to produce calibrated silicon wafers, with a certified measurement uncertainty, which can be used as reference wafers by wafer manufacturers and metrology tool manufacturers. We give an overview of the design of the interferometer and discuss its application to wafer thickness measurements. The conversion of optical thickness, as measured by the interferometer, to the wafer thickness requires knowledge of the refractive index of the material of the wafer. We describe a method for measuring the refractive index which is then used to establish absolute thickness and thickness variation maps for the wafer.

High-Speed Scalable Silicon-MoS2 P-N Heterojunction Photodetectors

PubMed Central

Dhyani, Veerendra; Das, Samaresh

2017-01-01

Two-dimensional molybdenum disulfide (MoS2) is a promising material for ultrasensitive photodetector owing to its favourable band gap and high absorption coefficient. However, their commercial applications are limited by the lack of high quality p-n junction and large wafer scale fabrication process. A high speed Si/MoS2 p-n heterojunction photodetector with simple and CMOS compatible approach has been reported here. The large area MoS2 thin film on silicon platform has been synthesized by sulfurization of RF-sputtered MoO3 films. The fabricated molecular layers of MoS2 on silicon offers high responsivity up to 8.75 A/W (at 580 nm and 3 V bias) with ultra-fast response of 10 μsec (rise time). Transient measurements of Si/MoS2 heterojunction under the modulated light reveal that the devices can function up to 50 kHz. The Si/MoS2 heterojunction is found to be sensitive to broadband wavelengths ranging from visible to near-infrared light with maximum detectivity up to ≈1.4 × 1012 Jones (2 V bias). Reproducible low dark current and high responsivity from over 20 devices in the same wafer has been measured. Additionally, the MoS2/Si photodetectors exhibit excellent stability in ambient atmosphere. PMID:28281652

Laser wafering for silicon solar.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

2011-03-01

Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurfacemore » damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.« less

Fabrication Methods for Adaptive Deformable Mirrors

NASA Technical Reports Server (NTRS)

Toda, Risaku; White, Victor E.; Manohara, Harish; Patterson, Keith D.; Yamamoto, Namiko; Gdoutos, Eleftherios; Steeves, John B.; Daraio, Chiara; Pellegrino, Sergio

2013-01-01

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate.

Performance Evaluations of Ceramic Wafer Seals

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

2006-01-01

Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).

PubMed

Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

2011-04-21

A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (μTAS), analytical and bio-analytical applications, and MEMS packaging.

Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

NASA Astrophysics Data System (ADS)

Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

2018-03-01

A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

Transparent electrodes in silicon heterojunction solar cells: Influence on contact passivation

DOE PAGES

Tomasi, Andrea; Sahli, Florent; Seif, Johannes Peter; ...

2015-10-26

Charge carrier collection in silicon heterojunction solar cells occurs via intrinsic/doped hydrogenated amorphous silicon layer stacks deposited on the crystalline silicon wafer surfaces. Usually, both the electron and hole collecting stacks are externally capped by an n-type transparent conductive oxide, which is primarily needed for carrier extraction. Earlier, it has been demonstrated that the mere presence of such oxides can affect the carrier recombination in the crystalline silicon absorber. Here, we present a detailed investigation of the impact of this phenomenon on both the electron and hole collecting sides, including its consequences for the operating voltages of silicon heterojunction solarmore » cells. As a result, we define guiding principles for improved passivating contact design for high-efficiency silicon solar cells.« less

Transparent electrodes in silicon heterojunction solar cells: Influence on contact passivation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tomasi, Andrea; Sahli, Florent; Seif, Johannes Peter

Charge carrier collection in silicon heterojunction solar cells occurs via intrinsic/doped hydrogenated amorphous silicon layer stacks deposited on the crystalline silicon wafer surfaces. Usually, both the electron and hole collecting stacks are externally capped by an n-type transparent conductive oxide, which is primarily needed for carrier extraction. Earlier, it has been demonstrated that the mere presence of such oxides can affect the carrier recombination in the crystalline silicon absorber. Here, we present a detailed investigation of the impact of this phenomenon on both the electron and hole collecting sides, including its consequences for the operating voltages of silicon heterojunction solarmore » cells. As a result, we define guiding principles for improved passivating contact design for high-efficiency silicon solar cells.« less

Method for formation of high quality back contact with screen-printed local back surface field

DOEpatents

Rohatgi, Ajeet; Meemongkolkiat, Vichai

2010-11-30

A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.

Method for cleaning a solar cell surface opening made with a solar etch paste

DOEpatents

Rohatgi, Ajeet; Meemongkolkiat, Vichai

2010-06-22

A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.

Electrically Conductive and Optically Active Porous Silicon Nanowires

PubMed Central

Qu, Yongquan; Liao, Lei; Li, Yujing; Zhang, Hua; Huang, Yu; Duan, Xiangfeng

2009-01-01

We report the synthesis of vertical silicon nanowire array through a two-step metal-assisted chemical etching of highly doped n-type silicon (100) wafers in a solution of hydrofluoric acid and hydrogen peroxide. The morphology of the as-grown silicon nanowires is tunable from solid nonporous nanowires, nonporous/nanoporous core/shell nanowires, and entirely nanoporous nanowires by controlling the hydrogen peroxide concentration in the etching solution. The porous silicon nanowires retain the single crystalline structure and crystallographic orientation of the starting silicon wafer, and are electrically conductive and optically active with visible photoluminescence. The combination of electronic and optical properties in the porous silicon nanowires may provide a platform for the novel optoelectronic devices for energy harvesting, conversion and biosensing. PMID:19807130

Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer

PubMed Central

Yu, Yang; Fong, Patrick W. K.; Wang, Shifeng; Surya, Charles

2016-01-01

High quality wafer-scale free-standing WS2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS2, which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm2 at −1 V which shows superior performances compared to the directly grown WS2/GaN heterojunctions. PMID:27897210

Carbon mediated reduction of silicon dioxide and growth of copper silicide particles in uniform width channels

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pizzocchero, Filippo; Bøggild, Peter; Booth, Timothy J.

We show that surface arc-discharge deposited carbon plays a critical intermediary role in the breakdown of thermally grown oxide diffusion barriers of 90 nm on a silicon wafer at 1035 °C in an Ar/H{sub 2} atmosphere, resulting in the formation of epitaxial copper silicide particles in ≈ 10 μm wide channels, which are aligned with the intersections of the (100) surface of the wafer and the (110) planes on an oxidized silicon wafer, as well as endotaxial copper silicide nanoparticles within the wafer bulk. We apply energy dispersive x-ray spectroscopy, in combination with scanning and transmission electron microscopy of focusedmore » ion beam fabricated lammelas and trenches in the structure to elucidate the process of their formation.« less

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Fabrication of an Absorber-Coupled MKID Detector

NASA Technical Reports Server (NTRS)

Brown, Ari; Hsieh, Wen-Ting; Moseley, Samuel; Stevenson, Thomas; U-Yen, Kongpop; Wollack, Edward

2012-01-01

Absorber-coupled microwave kinetic inductance detector (MKID) arrays were developed for submillimeter and far-infrared astronomy. These sensors comprise arrays of lambda/2 stepped microwave impedance resonators patterned on a 1.5-mm-thick silicon membrane, which is optimized for optical coupling. The detector elements are supported on a 380-mm-thick micro-machined silicon wafer. The resonators consist of parallel plate aluminum transmission lines coupled to low-impedance Nb microstrip traces of variable length, which set the resonant frequency of each resonator. This allows for multiplexed microwave readout and, consequently, good spatial discrimination between pixels in the array. The transmission lines simultaneously act to absorb optical power and employ an appropriate surface impedance and effective filling fraction. The fabrication techniques demonstrate high-fabrication yield of MKID arrays on large, single-crystal membranes and sub-micron front-to-back alignment of the micro strip circuit. An MKID is a detector that operates upon the principle that a superconducting material s kinetic inductance and surface resistance will change in response to being exposed to radiation with a power density sufficient to break its Cooper pairs. When integrated as part of a resonant circuit, the change in surface impedance will result in a shift in its resonance frequency and a decrease of its quality factor. In this approach, incident power creates quasiparticles inside a superconducting resonator, which is configured to match the impedance of free space in order to absorb the radiation being detected. For this reason MKIDs are attractive for use in large-format focal plane arrays, because they are easily multiplexed in the frequency domain and their fabrication is straightforward. The fabrication process can be summarized in seven steps: (1) Alignment marks are lithographically patterned and etched all the way through a silicon on insulator (SOI) wafer, which consists of a thin silicon membrane bonded to a thick silicon handle wafer. (2) The metal microwave circuitry on the front of the membrane is patterned and etched. (3) The wafer is then temporarily bonded with wafer wax to a Pyrex wafer, with the SOI side abutting the Pyrex. (4) The silicon handle component of the SOI wafer is subsequently etched away so as to expose the membrane backside. (5) The wafer is flipped over, and metal microwave circuitry is patterned and etched on the membrane backside. Furthermore, cuts in the membrane are made so as to define the individual detector array chips. (6) Silicon frames are micromachined and glued to the silicon membrane. (7) The membranes, which are now attached to the frames, are released from the Pyrex wafer via dissolution of the wafer wax in acetone.

High-efficiency impurity activation by precise control of cooling rate during atmospheric pressure thermal plasma jet annealing of 4H-SiC wafer

NASA Astrophysics Data System (ADS)

Maruyama, Keisuke; Hanafusa, Hiroaki; Ashihara, Ryuhei; Hayashi, Shohei; Murakami, Hideki; Higashi, Seiichiro

2015-06-01

We have investigated high-temperature and rapid annealing of a silicon carbide (SiC) wafer by atmospheric pressure thermal plasma jet (TPJ) irradiation for impurity activation. To reduce the temperature gradient in the SiC wafer, a DC current preheating system and the lateral back-and-forth motion of the wafer were introduced. A maximum surface temperature of 1835 °C within 2.4 s without sample breakage was achieved, and aluminum (Al), phosphorus (P), and arsenic (As) activations in SiC were demonstrated. We have investigated precise control of heating rate (Rh) and cooling rate (Rc) during rapid annealing of P+-implanted 4H-SiC and its impact on impurity activation. No dependence of resistivity on Rh was observed, while increasing Rc significantly decreased resistivity. A minimum resistivity of 0.0025 Ω·cm and a maximum carrier concentration of 2.9 × 1020 cm-3 were obtained at Rc = 568 °C/s.

Tracking Efficiency And Charge Sharing of 3D Silicon Sensors at Different Angles in a 1.4T Magnetic Field

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gjersdal, H.; /Oslo U.; Bolle, E.

2012-05-07

A 3D silicon sensor fabricated at Stanford with electrodes penetrating throughout the entire silicon wafer and with active edges was tested in a 1.4 T magnetic field with a 180 GeV/c pion beam at the CERN SPS in May 2009. The device under test was bump-bonded to the ATLAS pixel FE-I3 readout electronics chip. Three readout electrodes were used to cover the 400 {micro}m long pixel side, this resulting in a p-n inter-electrode distance of {approx} 71 {micro}m. Its behavior was confronted with a planar sensor of the type presently installed in the ATLAS inner tracker. Time over threshold, chargemore » sharing and tracking efficiency data were collected at zero and 15{sup o} angles with and without magnetic field. The latest is the angular configuration expected for the modules of the Insertable B-Layer (IBL) currently under study for the LHC phase 1 upgrade expected in 2014.« less

Determination of the p-spray profile for n+ p silicon sensors using a MOSFET

NASA Astrophysics Data System (ADS)

Fretwurst, E.; Garutti, E.; Klanner, R.; Kopsalis, I.; Schwandt, J.; Weberpals, M.

2017-09-01

The standard technique to electrically isolate the n+ implants of segmented silicon sensors fabricated on high-ohmic p-type silicon are p+-implants. Although the knowledge of the p+-implant dose and of the doping profile is highly relevant for the understanding and optimisation of sensors, this information is usually not available from the vendors, and methods to obtain it are highly welcome. The paper presents methods to obtain this information from circular MOSFETs fabricated as test structures on the same wafer as the sensors. Two circular MOSFETs, one with and one without a p+-implant under the gate, are used for this study. They were produced on Magnetic Czochralski silicon doped with ≈ 3 . 5 × 1012cm-2 of boron and 〈 100 〉 crystal orientation. The drain-source current as function of gate voltage for different back-side voltages is measured at a drain-source voltage of 50 mV in the linear MOSFET region, and the values of threshold voltage and mobility extracted using the standard MOSFET formulae. To determine the bulk doping, the implantation dose and profile from the data, two methods are used, which give compatible results. The doping profile, which varies between 3 . 5 × 1012cm-3 and 2 × 1015cm-3 for the MOSFET with p+-implant, is determined down to a distance of a fraction of a μm from the Si-SiO2 interface. The method of extracting the doping profiles is verified using data from a TCAD simulation of the two MOSFETs. The details of the methods and of the problems encountered are discussed.

Detecting Fermi-level shifts by Auger electron spectroscopy in Si and GaAs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Debehets, J.; Homm, P.; Menghini, M.

In this study, changes in surface Fermi-level of Si and GaAs, caused by doping and cleaning, are investigated by Auger electron spectroscopy. Based on the Auger voltage contrast, we compared the Auger transition peak energy but with higher accuracy by using a more accurate analyzer and an improved peak position determination method. For silicon, a peak shift as large as 0.46 eV was detected when comparing a cleaned p-type and n-type wafer, which corresponds rather well with the theoretical difference in Fermi-levels. If no cleaning was applied, the peak position did not differ significantly for both wafer types, indicating Fermi-levelmore » pinning in the band gap. For GaAs, peak shifts were detected after cleaning with HF and (NH 4) 2S-solutions in an inert atmosphere (N 2-gas). Although the (NH 4) 2S-cleaning in N 2 is very efficient in removing the oxygen from the surface, the observed Ga- and As-peak shifts are smaller than those obtained after the HF-cleaning. It is shown that the magnitude of the shift is related to the surface composition. After Si-deposition on the (NH 4) 2S-cleaned surface, the Fermi-level shifts back to a similar position as observed for an as-received wafer, indicating that this combination is not successful in unpinning the Fermi-level of GaAs.« less

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE PAGES

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; ...

2015-10-15

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Radiation-tolerant imaging device

DOEpatents

Colella, Nicholas J.; Kimbrough, Joseph R.

1996-01-01

A barrier at a uniform depth for an entire wafer is used to produce imaging devices less susceptible to noise pulses produced by the passage of ionizing radiation. The barrier prevents charge created in the bulk silicon of a CCD detector or a semiconductor logic or memory device from entering the collection volume of each pixel in the imaging device. The charge barrier is a physical barrier, a potential barrier, or a combination of both. The physical barrier is formed by an SiO.sub.2 insulator. The potential barrier is formed by increasing the concentration of majority carriers (holes) to combine with the electron's generated by the ionizing radiation. A manufacturer of CCD imaging devices can produce radiation-tolerant devices by merely changing the wafer type fed into his process stream from a standard wafer to one possessing a barrier beneath its surface, thus introducing a very small added cost to his production cost. An effective barrier type is an SiO.sub.2 layer.

Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

NASA Astrophysics Data System (ADS)

Wang, Shing-Dar; Chen, Ting-Wei

2018-06-01

In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in <1 0 0> direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

A silicon technology for millimeter-wave monolithic circuits

NASA Astrophysics Data System (ADS)

Stabile, P. J.; Rosen, A.

1984-12-01

A silicon millimeter-wave integrated-circuit (SIMMWIC) technology that includes high-energy ion implantation and pulsed-laser annealing, secondary ion mass spectrometry (SIMS) profile diagnostics, and novel wafer thinning has been developed. This technology has been applied to a SIMMWIC single-pole single-throw (SPST) switch and to IMPATT and p-i-n diode fabrication schemes. Thus, the SIMMWIC technology is a proven base for monolithic millimeter-wave sources and control circuit applications.

Detecting Fermi-level shifts by Auger electron spectroscopy in Si and GaAs

DOE PAGES

Debehets, J.; Homm, P.; Menghini, M.; ...

2018-01-12

In this study, changes in surface Fermi-level of Si and GaAs, caused by doping and cleaning, are investigated by Auger electron spectroscopy. Based on the Auger voltage contrast, we compared the Auger transition peak energy but with higher accuracy by using a more accurate analyzer and an improved peak position determination method. For silicon, a peak shift as large as 0.46 eV was detected when comparing a cleaned p-type and n-type wafer, which corresponds rather well with the theoretical difference in Fermi-levels. If no cleaning was applied, the peak position did not differ significantly for both wafer types, indicating Fermi-levelmore » pinning in the band gap. For GaAs, peak shifts were detected after cleaning with HF and (NH 4) 2S-solutions in an inert atmosphere (N 2-gas). Although the (NH 4) 2S-cleaning in N 2 is very efficient in removing the oxygen from the surface, the observed Ga- and As-peak shifts are smaller than those obtained after the HF-cleaning. It is shown that the magnitude of the shift is related to the surface composition. After Si-deposition on the (NH 4) 2S-cleaned surface, the Fermi-level shifts back to a similar position as observed for an as-received wafer, indicating that this combination is not successful in unpinning the Fermi-level of GaAs.« less

Solar cell circuit and method for manufacturing solar cells

NASA Technical Reports Server (NTRS)

Mardesich, Nick (Inventor)

2010-01-01

The invention is a novel manufacturing method for making multi-junction solar cell circuits that addresses current problems associated with such circuits by allowing the formation of integral diodes in the cells and allows for a large number of circuits to readily be placed on a single silicon wafer substrate. The standard Ge wafer used as the base for multi-junction solar cells is replaced with a thinner layer of Ge or a II-V semiconductor material on a silicon/silicon dioxide substrate. This allows high-voltage cells with multiple multi-junction circuits to be manufactured on a single wafer, resulting in less array assembly mass and simplified power management.

Slicing of silicon into sheet material: Silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project

NASA Technical Reports Server (NTRS)

Holden, S. C.

1976-01-01

Multiblade slurry sawing is used to slice 10 cm diameter silicon ingots into wafers 0.024 cm thick using 0.050 cm of silicon per slice (0.026 cm kerf loss). Total slicing time is less than twenty hours, and 143 slices are produced simultaneously. Productivity (slice area per hour per blade) is shown as a function or blade load and thickness, and abrasive size. Finer abrasive slurries cause a reduction in slice productivity, and thin blades cause a reduction of wafer accuracy. Sawing induced surface damage is found to extend 18 microns into the wafer.

Hybrid integrated single-wavelength laser with silicon micro-ring reflector

NASA Astrophysics Data System (ADS)

Ren, Min; Pu, Jing; Krishnamurthy, Vivek; Xu, Zhengji; Lee, Chee-Wei; Li, Dongdong; Gonzaga, Leonard; Toh, Yeow T.; Tjiptoharsono, Febi; Wang, Qian

2018-02-01

A hybrid integrated single-wavelength laser with silicon micro-ring reflector is demonstrated theoretically and experimentally. It consists of a heterogeneously integrated III-V section for optical gain, an adiabatic taper for light coupling, and a silicon micro-ring reflector for both wavelength selection and light reflection. Heterogeneous integration processes for multiple III-V chips bonded to an 8-inch Si wafer have been developed, which is promising for massive production of hybrid lasers on Si. The III-V layer is introduced on top of a 220-nm thick SOI layer through low-temperature wafer-boning technology. The optical coupling efficiency of >85% between III-V and Si waveguide has been achieved. The silicon micro-ring reflector, as the key element of the hybrid laser, is studied, with its maximized reflectivity of 85.6% demonstrated experimentally. The compact single-wavelength laser enables fully monolithic integration on silicon wafer for optical communication and optical sensing application.

Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer.

PubMed

Yu, Yang; Fong, Patrick W K; Wang, Shifeng; Surya, Charles

2016-11-29

High quality wafer-scale free-standing WS 2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS 2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS 2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS 2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS 2 , which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS 2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm 2 at -1 V which shows superior performances compared to the directly grown WS 2 /GaN heterojunctions.

Support apparatus for semiconductor wafer processing

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

2003-06-10

A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

Boron Partitioning Coefficient above Unity in Laser Crystallized Silicon.

PubMed

Lill, Patrick C; Dahlinger, Morris; Köhler, Jürgen R

2017-02-16

Boron pile-up at the maximum melt depth for laser melt annealing of implanted silicon has been reported in numerous papers. The present contribution examines the boron accumulation in a laser doping setting, without dopants initially incorporated in the silicon wafer. Our numerical simulation models laser-induced melting as well as dopant diffusion, and excellently reproduces the secondary ion mass spectroscopy-measured boron profiles. We determine a partitioning coefficient k p above unity with k p = 1 . 25 ± 0 . 05 and thermally-activated diffusivity D B , with a value D B ( 1687 K ) = ( 3 . 53 ± 0 . 44 ) × 10 - 4 cm 2 ·s - 1 of boron in liquid silicon. For similar laser parameters and process conditions, our model predicts the anticipated boron profile of a laser doping experiment.

Vacancy-type defects in TiO2/SiO2/SiC dielectric stacks

NASA Astrophysics Data System (ADS)

Coleman, P. G.; Burrows, C. P.; Mahapatra, R.; Wright, N. G.

2007-07-01

Open-volume (vacancy-type) point defects have been observed in ˜80-nm-thick titanium dioxide films grown on silicon dioxide/4H silicon carbide substrates as stacks with high dielectric constant for power device applications, using variable-energy positron annihilation spectroscopy. The concentration of vacancies decreases as the titanium dioxide growth temperature is increased in the range from 700to1000°C, whereas grain boundaries form in the polycrystalline material at the highest growth temperatures. It is proposed that the optimal electrical performance for films grown at 800°C reflects a balance between decreasing vacancy concentration and increasing grain boundary formation. The concentration of vacancies at the silicon dioxide/silicon carbide interface appears to saturate after 2.5h oxidation at 1150°C. A supplementary result suggests that the quality of the 10-μm-thick deposited silicon carbide epilayer is compromised at depths of about 2μm and beyond, possibly by the migration of impurities and/or other defects from the standard-grade highly doped 4H silicon carbide wafer beneath the epilayer during oxidation.

Silicon Nanowires for Solar Thermal Energy Harvesting: an Experimental Evaluation on the Trade-off Effects of the Spectral Optical Properties.

PubMed

Sekone, Abdoul Karim; Chen, Yu-Bin; Lu, Ming-Chang; Chen, Wen-Kai; Liu, Chia-An; Lee, Ming-Tsang

2016-12-01

Silicon nanowire possesses great potential as the material for renewable energy harvesting and conversion. The significantly reduced spectral reflectivity of silicon nanowire to visible light makes it even more attractive in solar energy applications. However, the benefit of its use for solar thermal energy harvesting remains to be investigated and has so far not been clearly reported. The purpose of this study is to provide practical information and insight into the performance of silicon nanowires in solar thermal energy conversion systems. Spectral hemispherical reflectivity and transmissivity of the black silicon nanowire array on silicon wafer substrate were measured. It was observed that the reflectivity is lower in the visible range but higher in the infrared range compared to the plain silicon wafer. A drying experiment and a theoretical calculation were carried out to directly evaluate the effects of the trade-off between scattering properties at different wavelengths. It is clearly seen that silicon nanowires can improve the solar thermal energy harnessing. The results showed that a 17.8 % increase in the harvest and utilization of solar thermal energy could be achieved using a silicon nanowire array on silicon substrate as compared to that obtained with a plain silicon wafer.

MEMS for Practical Applications

NASA Astrophysics Data System (ADS)

Esashi, Masayoshi

Silicon MEMS as electrostatically levitated rotational gyroscopes and 2D optical scanners, and wafer level packaged devices as integrated capacitive pressure sensors and MEMS switches are described. MEMS which use non-silicon materials as LTCC with electrical feedthrough, SiC and LiNbO3 for probe cards for wafer-level burn-in test, molds for glass press molding and SAW wireless passive sensors respectively are also described.

High-aspect ratio micro- and nanostructures enabled by photo-electrochemical etching for sensing and energy harvesting applications

NASA Astrophysics Data System (ADS)

Alhalaili, Badriyah; Dryden, Daniel M.; Vidu, Ruxandra; Ghandiparsi, Soroush; Cansizoglu, Hilal; Gao, Yang; Saif Islam, M.

2018-03-01

Photo-electrochemical (PEC) etching can produce high-aspect ratio features, such as pillars and holes, with high anisotropy and selectivity, while avoiding the surface and sidewall damage caused by traditional deep reactive ion etching (DRIE) or inductively coupled plasma (ICP) RIE. Plasma-based techniques lead to the formation of dangling bonds, surface traps, carrier leakage paths, and recombination centers. In pursuit of effective PEC etching, we demonstrate an optical system using long wavelength (λ = 975 nm) infra-red (IR) illumination from a high-power laser (1-10 W) to control the PEC etching process in n-type silicon. The silicon wafer surface was patterned with notches through a lithography process and KOH etching. Then, PEC etching was introduced by illuminating the backside of the silicon wafer to enhance depth, resulting in high-aspect ratio structures. The effect of the PEC etching process was optimized by varying light intensities and electrolyte concentrations. This work was focused on determining and optimizing this PEC etching technique on silicon, with the goal of expanding the method to a variety of materials including GaN and SiC that are used in designing optoelectronic and electronic devices, sensors and energy harvesting devices.

High Efficiency, Low Cost Solar Cells Manufactured Using 'Silicon Ink' on Thin Crystalline Silicon Wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Antoniadis, H.

Reported are the development and demonstration of a 17% efficient 25mm x 25mm crystalline Silicon solar cell and a 16% efficient 125mm x 125mm crystalline Silicon solar cell, both produced by Ink-jet printing Silicon Ink on a thin crystalline Silicon wafer. To achieve these objectives, processing approaches were developed to print the Silicon Ink in a predetermined pattern to form a high efficiency selective emitter, remove the solvents in the Silicon Ink and fuse the deposited particle Silicon films. Additionally, standard solar cell manufacturing equipment with slightly modified processes were used to complete the fabrication of the Silicon Ink highmore » efficiency solar cells. Also reported are the development and demonstration of a 18.5% efficient 125mm x 125mm monocrystalline Silicon cell, and a 17% efficient 125mm x 125mm multicrystalline Silicon cell, by utilizing high throughput Ink-jet and screen printing technologies. To achieve these objectives, Innovalight developed new high throughput processing tools to print and fuse both p and n type particle Silicon Inks in a predetermined pat-tern applied either on the front or the back of the cell. Additionally, a customized Ink-jet and screen printing systems, coupled with customized substrate handling solution, customized printing algorithms, and a customized ink drying process, in combination with a purchased turn-key line, were used to complete the high efficiency solar cells. This development work delivered a process capable of high volume producing 18.5% efficient crystalline Silicon solar cells and enabled the Innovalight to commercialize its technology by the summer of 2010.« less

Stress modeling of microdiaphragm pressure sensors

NASA Technical Reports Server (NTRS)

Tack, P. C.; Busta, H. H.

1986-01-01

A finite element program analysis was used to model the stress distribution of two monocrystalline silicon diaphragm pressure sensors. One configuration consists of an anisotropically backside etched diaphragm into a 250 micron thick, (100) oriented, silicon wafer. The diaphragm and total chip dimensions are given. The device is rigidly clamped on the back to a support substrate. Another configuration consists of a monocrystalline, (100), microdiaphragm which is formed on top of the wafer and whose area is reduced by a factor of 25 over the first configuration. The diaphragm is rigidly clamped to the silicon wafer. The stresses were calculated at a gauge pressure of 300 mm Hg and used to estimate the piezoresistive responses of resistor elements which were placed parallel and perpendicular near the diaphragm edges.

A novel ultra-planar, long-stroke and low-voltage piezoelectric micromirror

NASA Astrophysics Data System (ADS)

Bakke, Thor; Vogl, Andreas; Żero, Oleg; Tyholdt, Frode; Johansen, Ib-Rune; Wang, Dag

2010-06-01

A novel piston-type micromirror with a stroke of up to 20 µm at 20 V formed out of a silicon-on-insulator wafer with integrated piezoelectric actuators was designed, fabricated and characterized. The peak-to-valley planarity of a 2 mm diameter mirror was better than 15 nm, and tip-to-tip tilt upon actuation less than 30 nm. A resonance frequency of 9.8 kHz was measured. Analytical and finite element models were developed and compared to measurements. The design is based on a silicon-on-insulator wafer where the circular mirror is formed out of the handle silicon, thus forming a thick, highly rigid and ultra-planar mirror surface. The mirror plate is connected to a supporting frame through a membrane formed out of the device silicon layer. A piezoelectric actuator made of lead-zirconate-titanate (PZT) thin film is structured on top of the membrane, providing mirror deflection by deformation of the membrane. Two actuator designs were tested: one with a single ring and the other with a double ring providing bidirectional movement of the mirror. The fabricated mirrors were characterized by white light interferometry to determine the static and temporal response as well as mirror planarity.

Silicon release coating, method of making same, and method of using same

DOEpatents

Jonczyk, Ralf [Wilmington, DE

2011-11-22

A method of making a release coating includes the following steps: forming a mixture that includes (a) solid components comprising (i) 20-99% silicon by weight and (ii) 1-80% silicon nitride by weight and (b) a solvent; applying the mixture to an inner portion of a crucible or graphite board adapted to form an ingot or wafer comprising silicon; and annealing the mixture in a nitrogen atmosphere at a temperature ranging from 1000 to 2000.degree. C. The invention may also relate to release coatings and methods of making a silicon ingot or wafer including the use of a release coating.

PbS-PbSe IR detector arrays

NASA Technical Reports Server (NTRS)

Barrett, John R. (Inventor)

1986-01-01

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chipping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Three-dimensional conformal graphene microstructure for flexible and highly sensitive electronic skin

NASA Astrophysics Data System (ADS)

Yang, Jun; Ran, Qincui; Wei, Dapeng; Sun, Tai; Yu, Leyong; Song, Xuefen; Pu, Lichun; Shi, Haofei; Du, Chunlei

2017-03-01

We demonstrate a highly stretchable electronic skin (E-skin) based on the facile combination of microstructured graphene nanowalls (GNWs) and a polydimethylsiloxane (PDMS) substrate. The microstructure of the GNWs was endowed by conformally growing them on the unpolished silicon wafer without the aid of nanofabrication technology. Then a stamping transfer method was used to replicate the micropattern of the unpolished silicon wafer. Due to the large contact interface between the 3D graphene network and the PDMS, this type of E-skin worked under a stretching ratio of nearly 100%, and showed excellent mechanical strength and high sensitivity, with a change in relative resistance of up to 6500% and a gauge factor of 65.9 at 99.64% strain. Furthermore, the E-skin exhibited an obvious highly sensitive response to joint movement, eye movement and sound vibration, demonstrating broad potential applications in healthcare, body monitoring and wearable devices.

Method for fabricating an ultra-low expansion mask blank having a crystalline silicon layer

DOEpatents

Cardinale, Gregory F.

2002-01-01

A method for fabricating masks for extreme ultraviolet lithography (EUVL) using Ultra-Low Expansion (ULE) substrates and crystalline silicon. ULE substrates are required for the necessary thermal management in EUVL mask blanks, and defect detection and classification have been obtained using crystalline silicon substrate materials. Thus, this method provides the advantages for both the ULE substrate and the crystalline silicon in an Extreme Ultra-Violet (EUV) mask blank. The method is carried out by bonding a crystalline silicon wafer or member to a ULE wafer or substrate and thinning the silicon to produce a 5-10 .mu.m thick crystalline silicon layer on the surface of the ULE substrate. The thinning of the crystalline silicon may be carried out, for example, by chemical mechanical polishing and if necessary or desired, oxidizing the silicon followed by etching to the desired thickness of the silicon.

Micro/nano electro mechanical systems for practical applications

NASA Astrophysics Data System (ADS)

Esashi, Masayoshi

2009-09-01

Silicon MEMS as electrostatically levitated rotational gyroscope, 2D optical scanner and wafer level packaged devices as integrated capacitive pressure sensor and MEMS switch are described. MEMS which use non-silicon materials as diamond, PZT, conductive polymer, CNT (carbon nano tube), LTCC with electrical feedthrough, SiC (silicon carbide) and LiNbO3 for multi-probe data storage, multi-column electron beam lithography system, probe card for wafer-level burn-in test, mould for glass press moulding and SAW wireless passive sensor respectively are also described.

Control of grown-in defects and oxygen precipitates in silicon wafers with DZ-IG structure by ultrahigh-temperature rapid thermal oxidation

NASA Astrophysics Data System (ADS)

Maeda, Susumu; Sudo, Haruo; Okamura, Hideyuki; Nakamura, Kozo; Sueoka, Koji; Izunome, Koji

2018-04-01

A new control technique for achieving compatibility between crystal quality and gettering ability for heavy metal impurities was demonstrated for a nitrogen-doped Czochralski silicon wafer with a diameter of 300 mm via ultra-high temperature rapid thermal oxidation (UHT-RTO) processing. We have found that the DZ-IG structure with surface denuded zone and the wafer bulk with dense oxygen precipitates were formed by the control of vacancies in UHT-RTO process at temperature exceeding 1300 °C. It was also confirmed that most of the void defects were annihilated from the sub-surface of the wafer due to the interstitial Si atoms that were generated at the SiO2/Si interface. These results indicated that vacancies corresponded to dominant species, despite numerous interstitial silicon injections. We have explained these prominent features by the degree of super-saturation for the interstitial silicon due to oxidation and the precise thermal properties of the vacancy and interstitial silicon.

Effect of the Ti/Si ratio of spin coating solutions on surface passivation of crystalline silicon by TiO x -SiO x composite films

NASA Astrophysics Data System (ADS)

Yoshiba, Shuhei; Tanitsu, Katsuya; Suda, Yoshiyuki; Kamisako, Koichi

2017-06-01

Passivation films or antireflection coatings are generally prepared using costly vacuum or high-temperature processes. Thus, we report the preparation of TiO x -SiO x composite films by novel spin coatable solutions for the synthesis of low-cost passivation coating materials. The desired films were formed by varying the mixing ratios of TiO x and SiO x , and the resulting films exhibited excellent surface passivation properties. For the p-type wafer, an optimal effective surface recombination velocity (S eff) of 93 cm/s was achieved at \\text{TiO}x:\\text{SiO}x = 6:4, while a surface recombination current density (J 0s) of 195 fA/cm2 was obtained. In contrast, for the n-type wafer, an S eff of 27 cm/s and a J 0s of 38 fA/cm2 were achieved at \\text{TiO}x:\\text{SiO}x = 8:2. This excellent surface passivation effect could be attributed to the low interface state density and high positive fixed charge density. Furthermore, the thickness of the interfacial SiO x layer was determined to be important for obtaining the desired surface passivation effect.

Method of fabricating a PbS-PbSe IR detector array

NASA Technical Reports Server (NTRS)

Barrett, John R. (Inventor)

1987-01-01

A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chiping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.

Excellent c-Si surface passivation by low-temperature atomic layer deposited titanium oxide

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liao, Baochen, E-mail: liaobaochen@nus.edu.sg; Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117576; A*STAR Institute of Materials Research and Engineering

2014-06-23

In this work, we demonstrate that thermal atomic layer deposited (ALD) titanium oxide (TiO{sub x}) films are able to provide a—up to now unprecedented—level of surface passivation on undiffused low-resistivity crystalline silicon (c-Si). The surface passivation provided by the ALD TiO{sub x} films is activated by a post-deposition anneal and subsequent light soaking treatment. Ultralow effective surface recombination velocities down to 2.8 cm/s and 8.3 cm/s, respectively, are achieved on n-type and p-type float-zone c-Si wafers. Detailed analysis confirms that the TiO{sub x} films are nearly stoichiometric, have no significant level of contaminants, and are of amorphous nature. The passivation is foundmore » to be stable after storage in the dark for eight months. These results demonstrate that TiO{sub x} films are also capable of providing excellent passivation of undiffused c-Si surfaces on a comparable level to thermal silicon oxide, silicon nitride, and aluminum oxide. In addition, it is well known that TiO{sub x} has an optimal refractive index of 2.4 in the visible range for glass encapsulated solar cells, as well as a low extinction coefficient. Thus, the results presented in this work could facilitate the re-emergence of TiO{sub x} in the field of high-efficiency silicon wafer solar cells.« less

Fabrication of SOI structures with buried cavities using Si wafer direct bonding and electrochemical etch-stop

NASA Astrophysics Data System (ADS)

Chung, Gwiy-Sang

2003-10-01

This paper describes the fabrication of SOI structures with buried cavities using SDB and electrochemical etch-stop. These methods are suitable for thick membrane fabrication with accurate thickness, uniformity, and flatness. After a feed-through hole for supplied voltage and buried cavities was formed on a handle Si wafer with p-type, the handle wafer was bonded to an active Si wafer consisting of a p-type substrate with an n-type epitaxial layer corresponding to membrane thickness. The bonded pair was then thinned until electrochemical etch-stop occurred at the pn junction during electrochemical etchback. By using the SDB SOI structure with buried cavities, active membranes, which have a free standing structure with a dimension of 900×900 μm2, were fabricated. It is confirmed that the fabrication process of the SDB SOI structure with buried cavities is a powerful and versatile technology for new MEMS applications.

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

NASA Technical Reports Server (NTRS)

Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

1979-01-01

A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

Catalyst for microelectromechanical systems microreactors

DOEpatents

Morse, Jeffrey D [Martinez, CA; Sopchak, David A [Livermore, CA; Upadhye, Ravindra S [Pleasanton, CA; Reynolds, John G [San Ramon, CA; Satcher, Joseph H [Patterson, CA; Gash, Alex E [Brentwood, CA

2011-11-15

A microreactor comprising a silicon wafer, a multiplicity of microchannels in the silicon wafer, and a catalyst coating the microchannels. In one embodiment the catalyst coating the microchannels comprises a nanostructured material. In another embodiment the catalyst coating the microchannels comprises an aerogel. In another embodiment the catalyst coating the microchannels comprises a solgel. In another embodiment the catalyst coating the microchannels comprises carbon nanotubes.

Catalyst for microelectromechanical systems microreactors

DOEpatents

Morse, Jeffrey D [Martinez, CA; Sopchak, David A [Livermore, CA; Upadhye, Ravindra S [Pleasanton, CA; Reynolds, John G [San Ramon, CA; Satcher, Joseph H [Patterson, CA; Gash, Alex E [Brentwood, CA

2010-06-29

A microreactor comprising a silicon wafer, a multiplicity of microchannels in the silicon wafer, and a catalyst coating the microchannels. In one embodiment the catalyst coating the microchannels comprises a nanostructured material. In another embodiment the catalyst coating the microchannels comprises an aerogel. In another embodiment the catalyst coating the microchannels comprises a solgel. In another embodiment the catalyst coating the microchannels comprises carbon nanotubes.

High-alignment-accuracy transfer printing of passive silicon waveguide structures.

PubMed

Ye, Nan; Muliuk, Grigorij; Trindade, Antonio Jose; Bower, Chris; Zhang, Jing; Uvin, Sarah; Van Thourhout, Dries; Roelkens, Gunther

2018-01-22

We demonstrate the transfer printing of passive silicon devices on a silicon-on-insulator target waveguide wafer. Adiabatic taper structures and directional coupler structures were designed for 1310 nm and 1600 nm wavelength coupling tolerant for ± 1 µm misalignment. The release of silicon devices from the silicon substrate was realized by underetching the buried oxide layer while protecting the back-end stack. Devices were successfully picked by a PDMS stamp, by breaking the tethers that kept the silicon coupons in place on the source substrate, and printed with high alignment accuracy on a silicon photonic target wafer. Coupling losses of -1.5 +/- 0.5 dB for the adiabatic taper at 1310 nm wavelength and -0.5 +/- 0.5 dB for the directional coupler at 1600 nm wavelength are obtained.

Sensors and Micromachined Devices for the Automotive and New Markets: The Delphi Delco Electronics MEMS Story.

NASA Astrophysics Data System (ADS)

Logsdon, James

2002-03-01

This presentation will provide a brief history of the development of MEMS products and technology, beginning with the manifold absolute pressure sensor in the late seventies through the current variety of Delphi Delco Electronics sensors available today. The technology development of micromachining from uncompensated P plus etch stops to deep reactive ion etching and the technology development of wafer level packaging from electrostatic bonding to glass frit sealing and silicon to silicon direct bonding will be reviewed.

Method for synthesis of high quality graphene

DOEpatents

Lanzara, Alessandra [Piedmont, CA; Schmid, Andreas K [Berkeley, CA; Yu, Xiaozhu [Berkeley, CA; Hwang, Choonkyu [Albany, CA; Kohl, Annemarie [Beneditkbeuern, DE; Jozwiak, Chris M [Oakland, CA

2012-03-27

A method is described herein for the providing of high quality graphene layers on silicon carbide wafers in a thermal process. With two wafers facing each other in close proximity, in a first vacuum heating stage, while maintained at a vacuum of around 10.sup.-6 Torr, the wafer temperature is raised to about 1500.degree. C., whereby silicon evaporates from the wafer leaving a carbon rich surface, the evaporated silicon trapped in the gap between the wafers, such that the higher vapor pressure of silicon above each of the wafers suppresses further silicon evaporation. As the temperature of the wafers is raised to about 1530.degree. C. or more, the carbon atoms self assemble themselves into graphene.

Radiation-tolerant imaging device

DOEpatents

Colella, N.J.; Kimbrough, J.R.

1996-11-19

A barrier at a uniform depth for an entire wafer is used to produce imaging devices less susceptible to noise pulses produced by the passage of ionizing radiation. The barrier prevents charge created in the bulk silicon of a CCD detector or a semiconductor logic or memory device from entering the collection volume of each pixel in the imaging device. The charge barrier is a physical barrier, a potential barrier, or a combination of both. The physical barrier is formed by an SiO{sub 2} insulator. The potential barrier is formed by increasing the concentration of majority carriers (holes) to combine with the electron`s generated by the ionizing radiation. A manufacturer of CCD imaging devices can produce radiation-tolerant devices by merely changing the wafer type fed into his process stream from a standard wafer to one possessing a barrier beneath its surface, thus introducing a very small added cost to his production cost. An effective barrier type is an SiO{sub 2} layer. 7 figs.

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

NASA Technical Reports Server (NTRS)

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Comparison of cross-sectional transmission electron microscope studies of thin germanium epilayers grown on differently oriented silicon wafers.

PubMed

Norris, D J; Myronov, M; Leadley, D R; Walther, T

2017-12-01

We compare transmission electron microscopical analyses of the onset of islanding in the germanium-on-silicon (Ge/Si) system for three different Si substrate orientations: (001), (11¯0) and (11¯1)Si. The Ge was deposited by reduced pressure chemical vapour deposition and forms islands on the surface of all Si wafers; however, the morphology (aspect ratio) of the deposited islands is different for each type of wafer. Moreover, the mechanism for strain relaxation is different for each type of wafer owing to the different orientation of the (111) slip planes with the growth surface. Ge grown on (001)Si is initially pseudomorphically strained, yielding small, almost symmetrical islands of high aspect ratio (clusters or domes) on top interdiffused SiGe pedestals, without any evidence of plastic relaxation by dislocations, which would nucleate later-on when the islands might have coalesced and then the Matthews-Blakeslee limit is reached. For (11¯0)Si, islands are flatter and more asymmetric, and this is correlated with plastic relaxation of some islands by dislocations. In the case of growth on (11¯1)Si wafers, there is evidence of immediate strain relaxation taking place by numerous dislocations and also twinning. In the case of untwined film/substrate interfaces, Burgers circuits drawn around certain (amorphous-like) regions show a nonclosure with an edge-type a/4[1¯12] Burgers vector component visible in projection along [110]. Microtwins of multiples of half unit cells in thickness have been observed which occur at the growth interface between the Si(11¯1) buffer layer and the overlying Ge material. Models of the growth mechanisms to explain the interfacial configurations of each type of wafer are suggested. © 2017 The Authors Journal of Microscopy © 2017 Royal Microscopical Society.

Mechanical properties of silicon in subsurface damage layer from nano-grinding studied by atomistic simulation

NASA Astrophysics Data System (ADS)

Zhang, Zhiwei; Chen, Pei; Qin, Fei; An, Tong; Yu, Huiping

2018-05-01

Ultra-thin silicon wafer is highly demanded by semi-conductor industry. During wafer thinning process, the grinding technology will inevitably induce damage to the surface and subsurface of silicon wafer. To understand the mechanism of subsurface damage (SSD) layer formation and mechanical properties of SSD layer, atomistic simulation is the effective tool to perform the study, since the SSD layer is in the scale of nanometer and hardly to be separated from underneath undamaged silicon. This paper is devoted to understand the formation of SSD layer, and the difference between mechanical properties of damaged silicon in SSD layer and ideal silicon. With the atomistic model, the nano-grinding process could be performed between a silicon workpiece and diamond tool under different grinding speed. To reach a thinnest SSD layer, nano-grinding speed will be optimized in the range of 50-400 m/s. Mechanical properties of six damaged silicon workpieces with different depths of cut will be studied. The SSD layer from each workpiece will be isolated, and a quasi-static tensile test is simulated to perform on the isolated SSD layer. The obtained stress-strain curve is an illustration of overall mechanical properties of SSD layer. By comparing the stress-strain curves of damaged silicon and ideal silicon, a degradation of Young's modulus, ultimate tensile strength (UTS), and strain at fracture is observed.

Investigation of back surface fields effect on bifacial solar cells

NASA Astrophysics Data System (ADS)

Sepeai, Suhaila; Sulaiman, M. Y.; Sopian, Kamaruzzaman; Zaidi, Saleem H.

2012-11-01

A bifacial solar cell, in contrast with a conventional monofacial solar cell, produces photo-generated current from both front and back sides. Bifacial solar cell is an attractive candidate for enhancing photovoltaic (PV) market competitiveness as well as supporting the current efforts to increase efficiency and lower material costs. This paper reports on the fabrication of bifacial solar cells using phosphorus-oxytrichloride (POCl3) emitter formation on p-type, nanotextured silicon (Si) wafer. Backside surface field was formed through Al-diffusion using conventional screen-printing process. Bifacial solar cells with a structure of n+pp+ with and without back surface field (BSF) were fabricated in which silicon nitride (SiN) anti reflection and passivation films were coated on both sides, followed by screen printing of Argentum (Ag) and Argentum/Aluminum (Ag/Al) on front and back contacts, respectively. Bifacial solar cells without BSF exhibited open circuit voltage (VOC) of 535 mV for front and 480 mV for back surface. With Al-alloyed BSF bifacial solar cells, the VOC improved to 580 mV for the front surface and 560 mV for the back surface. Simulation of bifacial solar cells using PC1D and AFORS software demonstrated good agreement with experimental results. Simulations showed that best bifacial solar cells are achieved through a combination of high lifetime wafer, low recombination back surface field, reduced contact resistance, and superior surface passivation.

Alternative Packaging for Back-Illuminated Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2009-01-01

An alternative scheme has been conceived for packaging of silicon-based back-illuminated, back-side-thinned complementary metal oxide/semiconductor (CMOS) and charge-coupled-device image-detector integrated circuits, including an associated fabrication process. This scheme and process are complementary to those described in "Making a Back-Illuminated Imager With Back-Side Connections" (NPO-42839), NASA Tech Briefs, Vol. 32, No. 7 (July 2008), page 38. To avoid misunderstanding, it should be noted that in the terminology of imaging integrated circuits, "front side" or "back side" does not necessarily refer to the side that, during operation, faces toward or away from a source of light or other object to be imaged. Instead, "front side" signifies that side of a semiconductor substrate upon which the pixel pattern and the associated semiconductor devices and metal conductor lines are initially formed during fabrication, and "back side" signifies the opposite side. If the imager is of the type called "back-illuminated," then the back side is the one that faces an object to be imaged. Initially, a back-illuminated, back-side-thinned image-detector is fabricated with its back side bonded to a silicon handle wafer. At a subsequent stage of fabrication, the front side is bonded to a glass wafer (for mechanical support) and the silicon handle wafer is etched away to expose the back side. The frontside integrated circuitry includes metal input/output contact pads, which are rendered inaccessible by the bonding of the front side to the glass wafer. Hence, one of the main problems is to make the input/output contact pads accessible from the back side, which is ultimately to be the side accessible to the external world. The present combination of an alternative packaging scheme and associated fabrication process constitute a solution of the problem.

Fabrication of ultrathin and highly uniform silicon on insulator by numerically controlled plasma chemical vaporization machining.

PubMed

Sano, Yasuhisa; Yamamura, Kazuya; Mimura, Hidekazu; Yamauchi, Kazuto; Mori, Yuzo

2007-08-01

Metal-oxide semiconductor field-effect transistors fabricated on a silicon-on-insulator (SOI) wafer operate faster and at a lower power than those fabricated on a bulk silicon wafer. Scaling down, which improves their performances, demands thinner SOI wafers. In this article, improvement on the thinning of SOI wafers by numerically controlled plasma chemical vaporization machining (PCVM) is described. PCVM is a gas-phase chemical etching method in which reactive species generated in atmospheric-pressure plasma are used. Some factors affecting uniformity are investigated and methods for improvements are presented. As a result of thinning a commercial 8 in. SOI wafer, the initial SOI layer thickness of 97.5+/-4.7 nm was successfully thinned and made uniform at 7.5+/-1.5 nm.

Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

NASA Astrophysics Data System (ADS)

Green, Martin A.

2014-03-01

Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

Optical Addressing Electronic Tongue Based on Low Selective Photovoltaic Transducer with Nanoporous Silicon Layer

NASA Astrophysics Data System (ADS)

Litvinenko, S. V.; Bielobrov, D. O.; Lysenko, V.; Skryshevsky, V. A.

2016-08-01

The electronic tongue based on the array of low selective photovoltaic (PV) sensors and principal component analysis is proposed for detection of various alcohol solutions. A sensor array is created at the forming of p-n junction on silicon wafer with porous silicon layer on the opposite side. A dynamical set of sensors is formed due to the inhomogeneous distribution of the surface recombination rate at this porous silicon side. The sensitive to molecular adsorption photocurrent is induced at the scanning of this side by laser beam. Water, ethanol, iso-propanol, and their mixtures were selected for testing. It is shown that the use of the random dispersion of surface recombination rates on different spots of the rear side of p-n junction and principal component analysis of PV signals allows identifying mentioned liquid substances and their mixtures.

Single-order, subwavelength resonant nanograting as a uniformly hot substrate for surface-enhanced Raman spectroscopy.

PubMed

Deng, Xuegong; Braun, Gary B; Liu, Sheng; Sciortino, Paul F; Koefer, Bob; Tombler, Thomas; Moskovits, Martin

2010-05-12

The surface-enhanced Raman spectroscopy (SERS) activity and the optical reflectance of a subwavelength gold nanograting fabricated entirely using top down technologies on silicon wafers are presented. The grating consists of 120 nm gold cladding on top of parallel silica nanowires constituting the grating's lines, with gaps between nanowires <10 nm wide at their narrowest point. The grating produces inordinately intense SERS and shows very strong polarization dependence. Reflectance measurements for the optimized grating indicate that (when p-polarization is used and at least one of the incident electric field components lies across the grating lines) the reflectance drops to <1% at resonance, indicating that essentially all of the radiant energy falling on the surface is coupled into the grating. The SERS intensity and the reflectance at resonance anticorrelate predicatively, suggesting that reflectance measurements can provide a nondestructive, wafer-level test of SERS efficacy. The SERS performance of the gratings is very uniform and reproducible. Extensive measurements on samples cut from both the same wafer and from different wafers, produce a SERS intensity distribution function that is similar to that obtained for ordinary Raman measurements carried out at multiple locations on a polished (100) silicon wafer.

The Imaging Properties of a Silicon Wafer X-Ray Telescope

NASA Technical Reports Server (NTRS)

Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

1994-01-01

Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

NASA Astrophysics Data System (ADS)

Cunning, Benjamin V.; Ahmed, Mohsin; Mishra, Neeraj; Ranjbar Kermany, Atieh; Wood, Barry; Iacopi, Francesca

2014-08-01

Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices.

Electronic transport characterization of silicon wafers by spatially resolved steady-state photocarrier radiometric imaging

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Qian; University of the Chinese Academy of Sciences, Beijing 100039; Li, Bincheng, E-mail: bcli@ioe.ac.cn

2015-09-28

Spatially resolved steady-state photocarrier radiometric (PCR) imaging technique is developed to characterize the electronic transport properties of silicon wafers. Based on a nonlinear PCR theory, simulations are performed to investigate the effects of electronic transport parameters (the carrier lifetime, the carrier diffusion coefficient, and the front surface recombination velocity) on the steady-state PCR intensity profiles. The electronic transport parameters of an n-type silicon wafer are simultaneously determined by fitting the measured steady-state PCR intensity profiles to the three-dimensional nonlinear PCR model. The determined transport parameters are in good agreement with the results obtained by the conventional modulated PCR technique withmore » multiple pump beam radii.« less

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

1992-01-01

A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Integration of a UV curable polymer lens and MUMPs structures on a SOI optical bench

NASA Astrophysics Data System (ADS)

Hsieh, Jerwei; Hsiao, Sheng-Yi; Lai, Chun-Feng; Fang, Weileun

2007-08-01

This work presents the design concept of integrating a polymer lens, poly-Si MUMPs and single-crystal-silicon HARM structures on a SOI wafer to form a silicon optical bench. This approach enables the monolithic integration of various optical components on the wafer so as to improve the design flexibility of the silicon optical bench. Fabrication processes, including surface and bulk micromachining on the SOI wafer, have been established to realize bi-convex spherical polymer lenses with in-plane as well as out-of-plane optical axes. In addition, a micro device consisting of an in-plane polymer lens, a thick fiber holder and a mechanical shutter driven by an electrothermal actuator is also demonstrated using the present approach. In summary, this study significantly improves the design flexibility as well as the functions of SiOBs.

Surface etching technologies for monocrystalline silicon wafer solar cells

NASA Astrophysics Data System (ADS)

Tang, Muzhi

With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fong, Theodore E.

2013-05-06

The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technologymore » further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.« less

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers.

PubMed

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang, Zhen; Takano, Takayuki; Maeda, Ryutaro

2006-12-10

To develop x-ray mirrors for micropore optics, smooth silicon (111) sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 microm wide (111) sidewalls was fabricated using a 220 microm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time, x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto

2006-12-10

To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 {mu}m wide (111) sidewalls was fabricated using a 220 {mu}m thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

Fabrication of Total-Dose-Radiation-Hardened (TDRH) SOI wafer with embedded silicon nanoclusters

NASA Astrophysics Data System (ADS)

Wu, Aimin; Wang, Xi; Wei, Xing; Chen, Jing; Chen, Ming; Zhang, Zhengxuan

2009-05-01

Si ion-implantation and post annealing of silicon wafers prior to wafer bonding were used to radiation-harden the thermal oxide layer of Silicon on Insulator structures. After grinding and polishing, Total-Dose-Radiation-Hardened SOI (TDRH-SOI) wafers with several-micron-thick device layers were prepared. Electrical characterization before and after X-ray irradiation showed that the flatband voltage shift induced by irradiation was reduced by this preprocessing. Photoluminescence Spectroscopy (PL), Transmission Electron Microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) results indicated that the improvement of the total dose response of the TDRH-SOI wafer was associated with formation of Si nanoclusters in the implanted oxide layer, suggesting that these were the likely candidates for electron and proton trapping centers that reduce the positive charge buildup effect in the buried oxide.

All silicon electrode photocapacitor for integrated energy storage and conversion.

PubMed

Cohn, Adam P; Erwin, William R; Share, Keith; Oakes, Landon; Westover, Andrew S; Carter, Rachel E; Bardhan, Rizia; Pint, Cary L

2015-04-08

We demonstrate a simple wafer-scale process by which an individual silicon wafer can be processed into a multifunctional platform where one side is adapted to replace platinum and enable triiodide reduction in a dye-sensitized solar cell and the other side provides on-board charge storage as an electrochemical supercapacitor. This builds upon electrochemical fabrication of dual-sided porous silicon and subsequent carbon surface passivation for silicon electrochemical stability. The utilization of this silicon multifunctional platform as a combined energy storage and conversion system yields a total device efficiency of 2.1%, where the high frequency discharge capability of the integrated supercapacitor gives promise for dynamic load-leveling operations to overcome current and voltage fluctuations during solar energy harvesting.

Boron diffusion in silicon devices

DOEpatents

Rohatgi, Ajeet; Kim, Dong Seop; Nakayashiki, Kenta; Rounsaville, Brian

2010-09-07

Disclosed are various embodiments that include a process, an arrangement, and an apparatus for boron diffusion in a wafer. In one representative embodiment, a process is provided in which a boric oxide solution is applied to a surface of the wafer. Thereafter, the wafer is subjected to a fast heat ramp-up associated with a first heating cycle that results in a release of an amount of boron for diffusion into the wafer.

"Silicon millefeuille": From a silicon wafer to multiple thin crystalline films in a single step

NASA Astrophysics Data System (ADS)

Hernández, David; Trifonov, Trifon; Garín, Moisés; Alcubilla, Ramon

2013-04-01

During the last years, many techniques have been developed to obtain thin crystalline films from commercial silicon ingots. Large market applications are foreseen in the photovoltaic field, where important cost reductions are predicted, and also in advanced microelectronics technologies as three-dimensional integration, system on foil, or silicon interposers [Dross et al., Prog. Photovoltaics 20, 770-784 (2012); R. Brendel, Thin Film Crystalline Silicon Solar Cells (Wiley-VCH, Weinheim, Germany 2003); J. N. Burghartz, Ultra-Thin Chip Technology and Applications (Springer Science + Business Media, NY, USA, 2010)]. Existing methods produce "one at a time" silicon layers, once one thin film is obtained, the complete process is repeated to obtain the next layer. Here, we describe a technology that, from a single crystalline silicon wafer, produces a large number of crystalline films with controlled thickness in a single technological step.

1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10more » billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).« less

Development of a novel precision instrument for high-resolution simultaneous normal and shear force measurements between small planar samples

NASA Astrophysics Data System (ADS)

Lundstrom, Troy; Clark, William; Jalili, Nader

2017-05-01

In the design and development of end effector pads for silicon wafer handling robots, it is imperative that the static friction/adhesion force properties of the pads with respect to a variety of planar surfaces be characterized. In this work, the overall design, calibration, and data acquisition procedure of an instrument developed for performing these measurements on small (<10 mm × 10 mm) planar samples is presented. This device was used to perform adhesion/maximum shear force measurements on polydimethylsiloxane, a silicon wafer, and custom carbon nanotubes forest surfaces. The device was successfully able to measure an effective, mean profile adhesion force of 715 μN between a silicon wafer and a polydimethylsiloxane (2.768 × 10-6 m2) sample. In addition, a nonlinear maximum shear over normal force relationship was also measured between custom carbon nanotubes forest and the silicon wafer surfaces. The maximum shear over a normal force coefficient was found to decrease with increasing initial normal force. Currently, there are numerous devices for measuring normal/shear forces at the nano/micro- and macroscales; however, this device allows for the consistent measurement of these same types of forces on components with surface dimensions ranging from 0.1 mm to 10 mm.

GaN-based photon-recycling green light-emitting diodes with vertical-conduction structure.

PubMed

Sheu, Jinn-Kong; Chen, Fu-Bang; Yen, Wei-Yu; Wang, Yen-Chin; Liu, Chun-Nan; Yeh, Yu-Hsiang; Lee, Ming-Lun

2015-04-06

A p-i-n structure with near-UV(n-UV) emitting InGaN/GaN multiple quantum well(MQW) structure stacked on a green unipolar InGaN/GaN MQW was epitaxially grown at the same sapphire substrate. Photon recycling green light-emitting diodes(LEDs) with vertical-conduction feature on silicon substrates were then fabricated by wafer bonding and laser lift-off techniques. The green InGaN/GaN QWs were pumped with n-UV light to reemit low-energy photons when the LEDs were electrically driven with a forward current. Efficiency droop is potentially insignificant compared with the direct green LEDs due to the increase of effective volume of active layer in the optically pumped green LEDs, i.e., light emitting no longer limited in the QWs nearest to the p-type region to cause severe Auger recombination and carrier overflow losses.

Efficiency of silicon solar cells containing chromium

DOEpatents

Frosch, Robert A. Administrator of the National Aeronautics and Space; Salama, Amal M.

1982-01-01

Efficiency of silicon solar cells containing about 10.sup.15 atoms/cm.sup.3 of chromium is improved about 26% by thermal annealing of the silicon wafer at a temperature of 200.degree. C. to form chromium precipitates having a diameter of less than 1 Angstrom. Further improvement in efficiency is achieved by scribing laser lines onto the back surface of the wafer at a spacing of at least 0.5 mm and at a depth of less than 13 micrometers to preferentially precipitate chromium near the back surface and away from the junction region of the device. This provides an economical way to improve the deleterious effects of chromium, one of the impurities present in metallurgical grade silicon material.

The uses of Man-Made diamond in wafering applications

NASA Technical Reports Server (NTRS)

Fallon, D. B.

1982-01-01

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

Design and fabrication of piezoresistive p-SOI Wheatstone bridges for high-temperature applications

NASA Astrophysics Data System (ADS)

Kähler, Julian; Döring, Lutz; Merzsch, Stephan; Stranz, Andrej; Waag, Andreas; Peiner, Erwin

2011-06-01

For future measurements while depth drilling, commercial sensors are required for a temperature range from -40 up to 300 °C. Conventional piezoresistive silicon sensors cannot be used at higher temperatures due to an exponential increase of leakage currents which results in a drop of the bridge voltage. A well-known procedure to expand the temperature range of silicon sensors and to reduce leakage currents is to employ Silicon-On-Insulator (SOI) instead of standard wafer material. Diffused resistors can be operated up to 200 °C, but show the same problems beyond due to leakage of the p-njunction. Our approach is to use p-SOI where resistors as well as interconnects are defined by etching down to the oxide layer. Leakage is suppressed and the temperature dependence of the bridges is very low (TCR = (2.6 +/- 0.1) μV/K@1 mA up to 400 °C). The design and process flow will be presented in detail. The characteristics of Wheatstone bridges made of silicon, n- SOI, and p-SOI will be shown for temperatures up to 300 °C. Besides, thermal FEM-simulations will be described revealing the effect of stress between silicon and the silicon-oxide layer during temperature cycling.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1991-01-01

This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Silicon Chemical Vapor Deposition Process Using a Half-Inch Silicon Wafer for Minimal Manufacturing System

NASA Astrophysics Data System (ADS)

Li, Ning; Habuka, Hitoshi; Ikeda, Shin-ichi; Hara, Shiro

A chemical vapor deposition reactor for producing thin silicon films was designed and developed for achieving a new electronic device production system, the Minimal Manufacturing, using a half-inch wafer. This system requires a rapid process by a small footprint reactor. This was designed and verified by employing the technical issues, such as (i) vertical gas flow, (ii) thermal operation using a highly concentrated infrared flux, and (iii) reactor cleaning by chlorine trifluoride gas. The combination of (i) and (ii) could achieve a low heating power and a fast cooling designed by the heat balance of the small wafer placed at a position outside of the reflector. The cleaning process could be rapid by (iii). The heating step could be skipped because chlorine trifluoride gas was reactive at any temperature higher than room temperature.

Uncertainty evaluation of thickness and warp of a silicon wafer measured by a spectrally resolved interferometer

NASA Astrophysics Data System (ADS)

Praba Drijarkara, Agustinus; Gergiso Gebrie, Tadesse; Lee, Jae Yong; Kang, Chu-Shik

2018-06-01

Evaluation of uncertainty of thickness and gravity-compensated warp of a silicon wafer measured by a spectrally resolved interferometer is presented. The evaluation is performed in a rigorous manner, by analysing the propagation of uncertainty from the input quantities through all the steps of measurement functions, in accordance with the ISO Guide to the Expression of Uncertainty in Measurement. In the evaluation, correlation between input quantities as well as uncertainty attributed to thermal effect, which were not included in earlier publications, are taken into account. The temperature dependence of the group refractive index of silicon was found to be nonlinear and varies widely within a wafer and also between different wafers. The uncertainty evaluation described here can be applied to other spectral interferometry applications based on similar principles.

Large-size, high-uniformity, random silver nanowire networks as transparent electrodes for crystalline silicon wafer solar cells.

PubMed

Xie, Shouyi; Ouyang, Zi; Jia, Baohua; Gu, Min

2013-05-06

Metal nanowire networks are emerging as next generation transparent electrodes for photovoltaic devices. We demonstrate the application of random silver nanowire networks as the top electrode on crystalline silicon wafer solar cells. The dependence of transmittance and sheet resistance on the surface coverage is measured. Superior optical and electrical properties are observed due to the large-size, highly-uniform nature of these networks. When applying the nanowire networks on the solar cells with an optimized two-step annealing process, we achieved as large as 19% enhancement on the energy conversion efficiency. The detailed analysis reveals that the enhancement is mainly caused by the improved electrical properties of the solar cells due to the silver nanowire networks. Our result reveals that this technology is a promising alternative transparent electrode technology for crystalline silicon wafer solar cells.

Unveiling the Formation Pathway of Single Crystalline Porous Silicon Nanowires

PubMed Central

Zhong, Xing; Qu, Yongquan; Lin, Yung-Chen; Liao, Lei; Duan, Xiangfeng

2011-01-01

Porous silicon nanowire is emerging as an interesting material system due to its unique combination of structural, chemical, electronic, and optical properties. To fully understand their formation mechanism is of great importance for controlling the fundamental physical properties and enabling potential applications. Here we present a systematic study to elucidate the mechanism responsible for the formation of porous silicon nanowires in a two-step silver-assisted electroless chemical etching method. It is shown that silicon nanowire arrays with various porosities can be prepared by varying multiple experimental parameters such as the resistivity of the starting silicon wafer, the concentration of oxidant (H2O2) and the amount of silver catalyst. Our study shows a consistent trend that the porosity increases with the increasing wafer conductivity (dopant concentration) and oxidant (H2O2) concentration. We further demonstrate that silver ions, formed by the oxidation of silver, can diffuse upwards and re-nucleate on the sidewalls of nanowires to initiate new etching pathways to produce porous structure. The elucidation of this fundamental formation mechanism opens a rational pathway to the production of wafer-scale single crystalline porous silicon nanowires with tunable surface areas ranging from 370 m2·g−1 to 30 m2·g−1, and can enable exciting opportunities in catalysis, energy harvesting, conversion, storage, as well as biomedical imaging and therapy. PMID:21244020

Silicon micromachined waveguides for millimeter and submillimeter wavelengths

NASA Technical Reports Server (NTRS)

Yap, Markus; Tai, Yu-Chong; Mcgrath, William R.; Walker, Christopher

1992-01-01

The majority of radio receivers, transmitters, and components operating at millimeter and submillimeter wavelengths utilize rectangular waveguides in some form. However, conventional machining techniques for waveguides operating above a few hundred GHz are complicated and costly. This paper reports on the development of silicon micromachining techniques to create silicon-based waveguide circuits which can operate at millimeter and submillimeter wavelengths. As a first step, rectangular WR-10 waveguide structures have been fabricated from (110) silicon wafers using micromachining techniques. The waveguide is split along the broad wall. Each half is formed by first etching a channel completely through a wafer. Potassium hydroxide is used to etch smooth mirror-like vertical walls and LPCVD silicon nitride is used as a masking layer. This wafer is then bonded to another flat wafer using a polyimide bonding technique and diced into the U-shaped half wavelengths. Finally, a gold layer is applied to the waveguide walls. Insertion loss measurements show losses comparable to those of standard metal waveguides. It is suggested that active devices and planar circuits can be integrated with the waveguides, solving the traditional mounting problems. Potential applications in terahertz instrumentation technology are further discussed.

Aerosol-Assisted Extraction of Silicon Nanoparticles from Wafer Slicing Waste for Lithium Ion Batteries

PubMed Central

Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

2015-01-01

A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing. PMID:25819285

Aerosol-Assisted Extraction of Silicon Nanoparticles from Wafer Slicing Waste for Lithium Ion Batteries

NASA Astrophysics Data System (ADS)

Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

2015-03-01

A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

Study and development of non-aqueous silicon-air battery

NASA Astrophysics Data System (ADS)

Cohn, Gil; Ein-Eli, Yair

Silicon-air battery utilizing a single-crystal heavily doped n-type silicon wafer anode and an air cathode is reported in this paper. The battery employs hydrophilic 1-ethyl-3-methylimidazolium oligofluorohydrogenate [EMI·(HF) 2.3F] room temperature ionic liquid electrolyte. Electrochemical studies, including polarization and galvanostatic experiments, performed on various silicon types reveal the predominance performance of heavily doped n-type. Cell discharging at constant current densities of 10, 50, 100 and 300 μA cm -2 in ambient atmosphere, shows working voltages of 1.1-0.8 V. The study shows that as discharge advances, the moist interface of the air electrode is covered by discharge products, which prevent a continuous diffusion of oxygen to the electrode-electrolyte interface. The oxygen suffocation, governed by the settlement of the cell reaction products, is the main factor for an early failure of the cells. Based on the results obtained from scanning electron microscopy, energy-dispersive X-ray spectroscopy and X-ray photoelectron spectroscopy studies, we propose a series of reactions governing the discharge process in silicon-air batteries, as well as a detailed mechanism for silicon oxide deposition on the air electrode porous carbon.

Multi-wire slurry wafering demonstrations. [slicing silicon ingots for solar arrays

NASA Technical Reports Server (NTRS)

Chen, C. P.

1978-01-01

Ten slicing demonstrations on a multi-wire slurry saw, made to evaluate the silicon ingot wafering capabilities, reveal that the present sawing capabilities can provide usable wafer area from an ingot 1.05m/kg (e.g. kerf width 0.135 mm and wafer thickness 0.265 mm). Satisfactory surface qualities and excellent yield of silicon wafers were found. One drawback is that the add-on cost of producing water from this saw, as presently used, is considerably higher than other systems being developed for the low-cost silicon solar array project (LSSA), primarily because the saw uses a large quantity of wire. The add-on cost can be significantly reduced by extending the wire life and/or by rescue of properly plated wire to restore the diameter.

Optimization of the Surface Structure on Black Silicon for Surface Passivation

NASA Astrophysics Data System (ADS)

Jia, Xiaojie; Zhou, Chunlan; Wang, Wenjing

2017-03-01

Black silicon shows excellent anti-reflection and thus is extremely useful for photovoltaic applications. However, its high surface recombination velocity limits the efficiency of solar cells. In this paper, the effective minority carrier lifetime of black silicon is improved by optimizing metal-catalyzed chemical etching (MCCE) method, using an Al2O3 thin film deposited by atomic layer deposition (ALD) as a passivation layer. Using the spray method to eliminate the impact on the rear side, single-side black silicon was obtained on n-type solar grade silicon wafers. Post-etch treatment with NH4OH/H2O2/H2O mixed solution not only smoothes the surface but also increases the effective minority lifetime from 161 μs of as-prepared wafer to 333 μs after cleaning. Moreover, adding illumination during the etching process results in an improvement in both the numerical value and the uniformity of the effective minority carrier lifetime.

Laser doping of boron-doped Si paste for high-efficiency silicon solar cells

NASA Astrophysics Data System (ADS)

Tomizawa, Yuka; Imamura, Tetsuya; Soeda, Masaya; Ikeda, Yoshinori; Shiro, Takashi

2015-08-01

Boron laser doping (LD) is a promising technology for high-efficiency solar cells such as p-type passivated locally diffused solar cells and n-type Si-wafer-based solar cells. We produced a printable phosphorus- or boron-doped Si paste (NanoGram® Si paste/ink) for use as a diffuser in the LD process. We used the boron LD process to fabricate high-efficiency passivated emitter and rear locally diffused (PERL) solar cells. PERL solar cells on Czochralski Si (Cz-Si) wafers yielded a maximum efficiency of 19.7%, whereas the efficiency of a reference cell was 18.5%. Fill factors above 79% and open circuit voltages above 655 mV were measured. We found that the boron-doped area effectively performs as a local boron back surface field (BSF). The characteristics of the solar cell formed using NanoGram® Si paste/ink were better than those of the reference cell.

New insight into the discharge mechanism of silicon-air batteries using electrochemical impedance spectroscopy.

PubMed

Cohn, Gil; Eichel, Rüdiger A; Ein-Eli, Yair

2013-03-07

The mechanism of discharge termination in silicon-air batteries, employing a silicon wafer anode, a room-temperature fluorohydrogenate ionic liquid electrolyte and an air cathode membrane, is investigated using a wide range of tools. EIS studies indicate that the interfacial impedance between the electrolyte and the silicon wafer increases upon continuous discharge. In addition, it is shown that the impedance of the air cathode-electrolyte interface is several orders of magnitude lower than that of the anode. Equivalent circuit fitting parameters indicate the difference in the anode-electrolyte interface characteristics for different types of silicon wafers. Evolution of porous silicon surfaces at the anode and their properties, by means of estimated circuit parameters, is also presented. Moreover, it is found that the silicon anode potential has the highest negative impact on the battery discharge voltage, while the air cathode potential is actually stable and invariable along the whole discharge period. The discharge capacity of the battery can be increased significantly by mechanically replacing the silicon anode.

Microminiature gas chromatograph

DOEpatents

Yu, Conrad M.

1996-01-01

A microminiature gas chromatograph (.mu.GC) comprising a least one silicon wafer, a gas injector, a column, and a detector. The gas injector has a normally closed valve for introducing a mobile phase including a sample gas in a carrier gas. The valve is fully disposed in the silicon wafer(s). The column is a microcapillary in silicon crystal with a stationary phase and is mechanically connected to receive the mobile phase from the gas injector for the molecular separation of compounds in the sample gas. The detector is mechanically connected to the column for the analysis of the separated compounds of sample gas with electronic means, e.g., ion cell, field emitter and PIN diode.

Fabrication of close-packed TES microcalorimeter arrays using superconducting molybdenum/gold transition-edge sensors

NASA Astrophysics Data System (ADS)

Finkbeiner, F. M.; Brekosky, R. P.; Chervenak, J. A.; Figueroa-Feliciano, E.; Li, M. J.; Lindeman, M. A.; Stahle, C. K.; Stahle, C. M.; Tralshawala, N.

2002-02-01

We present an overview of our efforts in fabricating Transition-Edge Sensor (TES) microcalorimeter arrays for use in astronomical x-ray spectroscopy. Two distinct types of array schemes are currently pursued: 5×5 single pixel TES array where each pixel is a TES microcalorimeter, and Position-Sensing TES (PoST) array. In the latter, a row of 7 or 15 thermally-linked absorber pixels is read out by two TES at its ends. Both schemes employ superconducting Mo/Au bilayers as the TES. The TES are placed on silicon nitride membranes for thermal isolation from the structural frame. The silicon nitride membranes are prepared by a Deep Reactive Ion Etch (DRIE) process into a silicon wafer. In order to achieve the concept of closely packed arrays without decreasing its structural and functional integrity, we have already developed the technology to fabricate arrays of cantilevered pixel-sized absorbers and slit membranes in silicon nitride films. Furthermore, we have started to investigate ultra-low resistance through-wafer micro-vias to bring the electrical contact out to the back of a wafer. .

1D silicon refractive lenses for surface scattering with high energy x-rays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bertram, F.; Gutowski, O.; Schroer, C.

2016-07-27

At the high energy X-ray beamline P07 at PETRA III, 1D focusing down to 4 micrometer vertical beam height while preserving a horizontal beam width of 0.5 mm was established by refractive lenses etched into a silicon wafer. A single wafer with 8 different lens structures can cover the full energy range between 50 and 120 keV. For surface diffraction on ultrathin films a factor of 4 in intensity can be achieved compared to the already established Al-compound refractive 2D-lenses.

Application of neutron transmutation doping method to initially p-type silicon material.

PubMed

Kim, Myong-Seop; Kang, Ki-Doo; Park, Sang-Jun

2009-01-01

The neutron transmutation doping (NTD) method was applied to the initially p-type silicon in order to extend the NTD applications at HANARO. The relationship between the irradiation neutron fluence and the final resistivity of the initially p-type silicon material was investigated. The proportional constant between the neutron fluence and the resistivity was determined to be 2.3473x10(19)nOmegacm(-1). The deviation of the final resistivity from the target for almost all the irradiation results of the initially p-type silicon ingots was at a range from -5% to 2%. In addition, the burn-up effect of the boron impurities, the residual (32)P activity and the effect of the compensation characteristics for the initially p-type silicon were studied. Conclusively, the practical methodology to perform the neutron transmutation doping of the initially p-type silicon ingot was established.

Development of plasma chemical vaporization machining

NASA Astrophysics Data System (ADS)

Mori, Yuzo; Yamauchi, Kazuto; Yamamura, Kazuya; Sano, Yasuhisa

2000-12-01

Conventional machining processes, such as turning, grinding, or lapping are still applied for many materials including functional ones. But those processes are accompanied with the formation of a deformed layer, so that machined surfaces cannot perform their original functions. In order to avoid such points, plasma chemical vaporization machining (CVM) has been developed. Plasma CVM is a chemical machining method using neutral radicals, which are generated by the atmospheric pressure plasma. By using a rotary electrode for generation of plasma, a high density of neutral radicals was formed, and we succeeded in obtaining high removal rate of several microns to several hundred microns per minute for various functional materials such as fused silica, single crystal silicon, molybdenum, tungsten, silicon carbide, and diamond. Especially, a high removal rate equal to lapping in the mechanical machining of fused silica and silicon was realized. 1.4 nm (p-v) was obtained as a surface roughness in the case of machining a silicon wafer. The defect density of a silicon wafer surface polished by various machining method was evaluated by the surface photo voltage spectroscopy. As a result, the defect density of the surface machined by plasma CVM was under 1/100 in comparison with the surface machined by mechanical polishing and argon ion sputtering, and very low defect density which was equivalent to the chemical etched surface was realized. A numerically controlled CVM machine for x-ray mirror fabrication is detailed in the accompanying article in this issue.

Theoretical analysis of improved efficiency of silicon-wafer solar cells with textured nanotriangular grating structure

NASA Astrophysics Data System (ADS)

Zhang, Yaoju; Zheng, Jun; Zhao, Xuesong; Ruan, Xiukai; Cui, Guihua; Zhu, Haiyong; Dai, Yuxing

2018-03-01

A practical model of crystalline silicon-wafer solar cells is proposed in order to enhance the light absorption and improve the conversion efficiency of silicon solar cells. In the model, the front surface of the silicon photovoltaic film is designed to be a textured-triangular-grating (TTG) structure, and the ITO contact film and the antireflection coating (ARC) of glass are coated on the TTG surface of silicon solar cells. The optical absorption spectrum of solar cells are simulated by applying the finite difference time domain method. Electrical parameters of the solar cells are calculated using two models with and without carrier loss. The effect of structure parameters on the performance of the TTG cell is discussed in detail. It is found that the thickness (tg) of the ARC, period (p) of grating, and base angle (θ) of triangle have a crucial influence on the conversion efficiency. The optimal structure of the TTG cell is designed. The TTG solar cell can produce higher efficiency in a wide range of solar incident angle and the average efficiency of the optimal TTG cell over 7:30-16:30 time of day is 8% higher than that of the optimal plane solar cell. In addition, the study shows that the bulk recombination of carriers has an influence on the conversion efficiency of the cell, the conversion efficiency of the actual solar cell with carrier recombination is reduced by 20.0% of the ideal cell without carrier recombination.

Contacting graphene in a 200 mm wafer silicon technology environment

NASA Astrophysics Data System (ADS)

Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

2018-06-01

Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

On-chip integration of suspended InGaN/GaN multiple-quantum-well devices with versatile functionalities.

PubMed

Cai, Wei; Yang, Yongchao; Gao, Xumin; Yuan, Jialei; Yuan, Wei; Zhu, Hongbo; Wang, Yongjin

2016-03-21

We propose, fabricate and demonstrate on-chip photonic integration of suspended InGaN/GaN multiple quantum wells (MQWs) devices on the GaN-on-silicon platform. Both silicon removal and back wafer etching are conducted to obtain membrane-type devices, and suspended waveguides are used for the connection between p-n junction InGaN/GaN MQWs devices. As an in-plane data transmission system, the middle p-n junction InGaN/GaN MQWs device is used as a light emitting diode (LED) to deliver signals by modulating the intensity of the emitted light, and the other two devices act as photodetectors (PDs) to sense the light guided by the suspended waveguide and convert the photons into electrons, achieving 1 × 2 in-plane information transmission via visible light. Correspondingly, the three devices can function as independent PDs to realize multiple receivers for free space visible light communication. Further, the on-chip photonic platform can be used as an active electro-optical sensing system when the middle device acts as a PD and the other two devices serve as LEDs. The experimental results show that the auxiliary LED sources can enhance the amplitude of the induced photocurrent.

Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

NASA Astrophysics Data System (ADS)

Kulshreshtha, Prashant Kumar

This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu-precipitates (upto 50 nm) compresses Si-lattice to facilitate Si-XII/III formations, i.e. high pressure ductile phases. Sweeping voltage measurements at a given load determine that Si lattice has to be stressed beyond 1 mN to complete the Si-I (semiconducting) to Si-II (ohmic) phase changes. Above 1 mN load DSB sample has a varistor-like behavior due to higher grain-boundary resistance from interfacial states. The precipitate defect structure stimulated stresses at the bulk Si lattice or grain boundary modify the rate of elastic energy release at the crack-tip and associated phase change and hardness values in response to external loading. The systematic approach in this thesis elucidates that the interfacial surface area between Si-lattice and precipitate plays pivotal role in defining extent of stresses in the silicon, i.e. smaller precipitates in higher densities are severe than few larger volume precipitates. The finding of high-pressure ductile phase formation during loading of compressed silicon structure has been suggested to PV industry as a prospective candidate for reducing the wafer breakage and allowing larger handling stresses.

Schottky barrier amorphous silicon solar cell with thin doped region adjacent metal Schottky barrier

DOEpatents

Carlson, David E.; Wronski, Christopher R.

1979-01-01

A Schottky barrier amorphous silicon solar cell incorporating a thin highly doped p-type region of hydrogenated amorphous silicon disposed between a Schottky barrier high work function metal and the intrinsic region of hydrogenated amorphous silicon wherein said high work function metal and said thin highly doped p-type region forms a surface barrier junction with the intrinsic amorphous silicon layer. The thickness and concentration of p-type dopants in said p-type region are selected so that said p-type region is fully ionized by the Schottky barrier high work function metal. The thin highly doped p-type region has been found to increase the open circuit voltage and current of the photovoltaic device.

Reassessment of the recombination parameters of chromium in n- and p-type crystalline silicon and chromium-boron pairs in p-type crystalline silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sun, Chang, E-mail: chang.sun@anu.edu.au; Rougieux, Fiacre E.; Macdonald, Daniel

2014-06-07

Injection-dependent lifetime spectroscopy of both n- and p-type, Cr-doped silicon wafers with different doping levels is used to determine the defect parameters of Cr{sub i} and CrB pairs, by simultaneously fitting the measured lifetimes with the Shockley-Read-Hall model. A combined analysis of the two defects with the lifetime data measured on both n- and p-type samples enables a significant tightening of the uncertainty ranges of the parameters. The capture cross section ratios k = σ{sub n}/σ{sub p} of Cr{sub i} and CrB are determined as 3.2 (−0.6, +0) and 5.8 (−3.4, +0.6), respectively. Courtesy of a direct experimental comparison of the recombinationmore » activity of chromium in n- and p-type silicon, and as also suggested by modelling results, we conclude that chromium has a greater negative impact on carrier lifetimes in p-type silicon than n-type silicon with similar doping levels.« less

Comparing the transient response of a resistive-type sensor with a thin film thermocouple during the post-exposure bake process

NASA Astrophysics Data System (ADS)

Kreider, Kenneth G.; DeWitt, David P.; Fowler, Joel B.; Proctor, James E.; Kimes, William A.; Ripple, Dean C.; Tsai, Benjamin K.

2004-04-01

Recent studies on dynamic temperature profiling and lithographic performance modeling of the post-exposure bake (PEB) process have demonstrated that the rate of heating and cooling may have an important influence on resist lithographic response. Measuring the transient surface temperature during the heating or cooling process with such accuracy can only be assured if the sensors embedded in or attached to the test wafer do not affect the temperature distribution in the bare wafer. In this paper we report on an experimental and analytical study to compare the transient response of embedded platinum resistance thermometer (PRT) sensors with surface-deposited, thin-film thermocouples (TFTC). The TFTCs on silicon wafers have been developed at NIST to measure wafer temperatures in other semiconductor thermal processes. Experiments are performed on a test bed built from a commercial, fab-qualified module with hot and chill plates using wafers that have been instrumented with calibrated type-E (NiCr/CuNi) TFTCs and commercial PRTs. Time constants were determined from an energy-balance analysis fitting the temperature-time derivative to the wafer temperature during the heating and cooling processes. The time constants for instrumented wafers ranged from 4.6 s to 5.1 s on heating for both the TFTC and PRT sensors, with an average difference less than 0.1 s between the TFTCs and PRTs and slightly greater differences on cooling.

Fabrication of Silicon Backshorts with Improved Out-of-Band Rejection for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Method of forming contacts for a back-contact solar cell

DOEpatents

Manning, Jane

2015-10-20

Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions.

Method of forming contacts for a back-contact solar cell

DOEpatents

Manning, Jane

2014-07-15

Methods of forming contacts for solar cells are described. In one embodiment, a method includes forming a silicon layer above a substrate, forming and patterning a solid-state p-type dopant source on the silicon layer, forming an n-type dopant source layer over exposed regions of the silicon layer and over a plurality of regions of the solid-state p-type dopant source, and heating the substrate to provide a plurality of n-type doped silicon regions among a plurality of p-type doped silicon regions.

Material removal effect of microchannel processing by femtosecond laser

NASA Astrophysics Data System (ADS)

Zhang, Pan; Chen, Lei; Chen, Jianxiong; Tu, Yiliu

2017-11-01

Material processing using ultra-short-pulse laser is widely used in the field of micromachining, especially for the precision processing of hard and brittle materials. This paper reports a theoretical and experimental study of the ablation characteristics of a silicon wafer under micromachining using a femtosecond laser. The ablation morphology of the silicon wafer surface is surveyed by a detection test with an optical microscope. First, according to the relationship between the diameter of the ablation holes and the incident laser power, the ablation threshold of the silicon wafer is found to be 0.227 J/cm2. Second, the influence of various laser parameters on the size of the ablation microstructure is studied and the ablation morphology is analyzed. Furthermore, a mathematical model is proposed that can calculate the ablation depth per time for a given laser fluence and scanning velocity. Finally, a microchannel milling test is carried out on the micromachining center. The effectiveness and accuracy of the proposed models are verified by comparing the estimated depth to the actual measured results.

Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

PubMed

Shen, Wen-Wei; Lin, Yu-Min; Wu, Sheng-Tsai; Lee, Chia-Hsin; Huang, Shin-Yi; Chang, Hsiang-Hung; Chang, Tao-Chih; Chen, Kuan-Neng

2018-08-01

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.

Process for Fabrication of Superconducting Vias for Electrical Connection to Groundplane in Cryogenic Detectors

NASA Technical Reports Server (NTRS)

Denis, Kevin L. (Inventor)

2018-01-01

Disclosed are systems, methods, and non-transitory computer-readable storage media for fabrication of silicon on insulator (SOI) wafers with a superconductive via for electrical connection to a groundplane. Fabrication of the SOI wafer with a superconductive via can involve depositing a superconducting groundplane onto a substrate with the superconducting groundplane having an oxidizing layer and a non-oxidizing layer. A layer of monocrystalline silicon can be bonded to the superconducting groundplane and a photoresist layer can be applied to the layer of monocrystalline silicon and the SOI wafer can be etched with the oxygen rich etching plasma, resulting in a monocrystalline silicon top layer with a via that exposes the superconducting groundplane. Then, the fabrication can involve depositing a superconducting surface layer to cover the via.

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay marks. In this work, the non-contact infrared alignment system of the Nikon i-line Stepper NSR-SF150 for both the alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard back to front side application. The overlay was measured and determined using both, the EVG NT40 automated measurement system with special overlay marks and the measurement of the FIA marks of the front and back side layer. A comparison of both results shows mismatches in x and y translations smaller than 200 nm, which is relatively small compared to the overlay tolerances of +/-500 nm for the back to front side process. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated. Due to the super IR light transparency of both doubled side polished wafers, the embedded FIA marks generate a stable and clear signal for accurate x and y wafer coordinate positioning. The FIA marks of the device wafer top layer were measured under standard condition in a developed photoresist mask without IR illumination. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 μm SiGe:C BiCMOS technology. The presented method can be applied for both the standard back to front side process technologies and also new temporary and permanent wafer bonding applications.

1366 Project Silicon: Reclaiming US Silicon PV Leadership

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling ofmore » 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. SunPath filled the crucial development step between the original research effort in Lexington and the GW factory scheduled to be online before the end of the decade. At the conclusion of the project, it is clear that the Direct Wafer™ technology will have a dramatic impact on the entire silicon photovoltaic supply chain by effectively doubling existing silicon capacity (by reducing silicon usage by 50%) and reducing supply chain capital costs by 35%. The technology, when fully-scaled in the US, will also lead to significant job growth, with the eventual creation of 1,000 jobs in Western New York.« less

Noninvasive, near-field terahertz imaging of hidden objects using a single-pixel detector.

PubMed

Stantchev, Rayko Ivanov; Sun, Baoqing; Hornett, Sam M; Hobson, Peter A; Gibson, Graham M; Padgett, Miles J; Hendry, Euan

2016-06-01

Terahertz (THz) imaging can see through otherwise opaque materials. However, because of the long wavelengths of THz radiation (λ = 400 μm at 0.75 THz), far-field THz imaging techniques suffer from low resolution compared to visible wavelengths. We demonstrate noninvasive, near-field THz imaging with subwavelength resolution. We project a time-varying, intense (>100 μJ/cm(2)) optical pattern onto a silicon wafer, which spatially modulates the transmission of synchronous pulse of THz radiation. An unknown object is placed on the hidden side of the silicon, and the far-field THz transmission corresponding to each mask is recorded by a single-element detector. Knowledge of the patterns and of the corresponding detector signal are combined to give an image of the object. Using this technique, we image a printed circuit board on the underside of a 115-μm-thick silicon wafer with ~100-μm (λ/4) resolution. With subwavelength resolution and the inherent sensitivity to local conductivity, it is possible to detect fissures in the circuitry wiring of a few micrometers in size. THz imaging systems of this type will have other uses too, where noninvasive measurement or imaging of concealed structures is necessary, such as in semiconductor manufacturing or in ex vivo bioimaging.

Multijunction high-voltage solar cell

NASA Technical Reports Server (NTRS)

Evans, J. C., Jr.; Goradia, C.; Chai, A. T.

1981-01-01

Multijunction cell allows for fabrication of high-voltage solar cell on single semiconductor wafer. Photovoltaic energy source using cell is combined on wafer with circuit it is to power. Cell consists of many voltage-generating regions internally or externally interconnected to give desired voltage and current combination. For computer applications, module is built on silicon wafer with energy for internal information processing and readouts derived from external light source.

Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-based wafer bonding process.

PubMed

Logan, Andrew; Yeow, John T W

2009-05-01

We report the fabrication and experimental testing of 1-D 23-element capacitive micromachined ultrasonic transducer (CMUT) arrays that have been fabricated using a novel wafer-bonding process whereby the membrane and the insulation layer are both silicon nitride. The membrane and cell cavities are deposited and patterned on separate wafers and fusion-bonded in a vacuum environment to create CMUT cells. A user-grown silicon-nitride membrane layer avoids the need for expensive silicon-on-insulator (SOI) wafers, reduces parasitic capacitance, and reduces dielectric charging. It allows more freedom in selecting the membrane thickness while also providing the benefits of wafer-bonding fabrication such as excellent fill factor, ease of vacuum sealing, and a simplified fabrication process when compared with the more standard sacrificial release process. The devices fabricated have a cell diameter of 22 microm, a membrane thickness of 400 nm, a gap depth of 150 nm, and an insulation thickness of 250 nm. The resonant frequency of the CMUT in air is 17 MHz and has an attenuation compensated center frequency of approximately 9 MHz in immersion with a -6 dB fractional bandwidth of 123%. This paper presents the fabrication process and some characterization results.

MEMS for vibration energy harvesting

NASA Astrophysics Data System (ADS)

Li, Lin; Zhang, Yangjian; San, Haisheng; Guo, Yinbiao; Chen, Xuyuan

2008-03-01

In this paper, a capacitive vibration-to-electrical energy harvester was designed. An integrated process flow for fabricating the designed capacitive harvester is presented. For overcoming the disadvantage of depending on external power source in capacitive energy harvester, two parallel electrodes with different work functions are used as the two electrodes of the capacitor to generate a build-in voltage for initially charging the capacitor. The device is a sandwich structure of silicon layer in two glass layers with area of about 1 cm2. The silicon structure is fabricated by using silicon-on-insulator (SOI) wafer. The glass wafers are anodic bonded on to both sides of the SOI wafer to create a vacuum sealed package.

Microminiature gas chromatograph

DOEpatents

Yu, C.M.

1996-12-10

A microminiature gas chromatograph ({mu}GC) comprising a least one silicon wafer, a gas injector, a column, and a detector. The gas injector has a normally closed valve for introducing a mobile phase including a sample gas in a carrier gas. The valve is fully disposed in the silicon wafer(s). The column is a microcapillary in silicon crystal with a stationary phase and is mechanically connected to receive the mobile phase from the gas injector for the molecular separation of compounds in the sample gas. The detector is mechanically connected to the column for the analysis of the separated compounds of sample gas with electronic means, e.g., ion cell, field emitter and PIN diode. 7 figs.

Novel Bonding Technology for Hermetically Sealed Silicon Micropackage

NASA Astrophysics Data System (ADS)

Lee, Duck-Jung; Ju, Byeong-Kwon; Choi, Woo-Beom; Jeong, Jee-Won; Lee, Yun-Hi; Jang, Jin; Lee, Kwang-Bae; Oh, Myung-Hwan

1999-01-01

We performed glass-to-silicon bonding and fabricated a hermetically sealed silicon wafer using silicon direct bonding followed by anodic bonding (SDAB). The hydrophilized glass and silicon wafers in solution were dried and initially bonded in atmosphere as in the silicon direct bonding (SDB) process, but annealing at high temperature was not performed. Anodic bonding was subsequently carried out for the initially bonded specimens. Then the wafer pairs bonded by the SDAB method were different from those bonded by the anodic bonding process only. The effects of the bonding process on the bonded area and tensile strength were investigated as functions of bonding temperature and voltage. Using scanning electron microscopy (SEM), the cross-sectional view of the bonded interface region was observed. In order to investigate the migration of the sodium ions in the bonding process, the concentration of the bonded glass was compared with that of standard glass. The specimen bonded using the SDAB process had higher efficiency than that using the anodic bonding process only.

a Study of Oxygen Precipitation in Heavily Doped Silicon.

NASA Astrophysics Data System (ADS)

Graupner, Robert Kurt

Gettering of impurities with oxygen precipitates is widely used during the fabrication of semiconductors to improve the performance and yield of the devices. Since the effectiveness of the gettering process is largely dependent on the initial interstitial oxygen concentration, accurate measurements of this parameter are of considerable importance. Measurements of interstitial oxygen following thermal cycles are required for development of semiconductor fabrication processes and for research into the mechanisms of oxygen precipitate nucleation and growth. Efforts by industrial associations have led to the development of standard procedures for the measurement of interstitial oxygen in wafers. However practical oxygen measurements often do not satisfy the requirements of such standard procedures. An additional difficulty arises when the silicon wafer has a low resitivity (high dopant concentration). In such cases the infrared light used for the measurement is severely attenuated by the electrons of holes introduced by the dopant. Since such wafers are the substrates used for the production of widely used epitaxial wafers, this measurement problem is economically important. Alternative methods such as Secondary Ion Mass Spectroscopy or Gas Fusion Analysis have been developed to measure oxygen in these cases. However, neither of these methods is capable of distinguishing interstitial oxygen from precipitated oxygen as required for precipitation studies. In addition to the commercial interest in heavily doped silicon substrates, they are also of interest for research into the role of point defects in nucleation and precipitation processes. Despite considerable research effort, there is still disagreement concerning the type of point defect and its role in semiconductor processes. Studies of changes in the interstitial oxygen concentration of heavily doped and lightly doped silicon wafers could help clarify the role of point defects in oxygen nucleation and precipitation processes. This could lead to more effective control and use of oxygen precipitation for gettering. One of the principal purposes of this thesis is the extension of the infrared interstitial oxygen measurement technique to situations outside the measurement capacities of the standard technique. These situations include silicon slices exhibiting interfering precipitate absorption bands and heavily doped n-type silicon wafers. A new method is presented for correcting for the effect of multiple reflections in silicon wafers with optically rough surfaces. The technique for the measurement of interstitial oxygen in heavily doped n-type wafers is then used to perform a comparative study of oxygen precipitation in heavily antimony doped (.035 ohm-cm) silicon and lightly doped p-type silicon. A model is presented to quantitatively explain the observed suppression of defect formation in heavily doped n-type wafers.

2-dimensional ion velocity distributions measured by laser-induced fluorescence above a radio-frequency biased silicon wafer

NASA Astrophysics Data System (ADS)

Moore, Nathaniel B.; Gekelman, Walter; Pribyl, Patrick; Zhang, Yiting; Kushner, Mark J.

2013-08-01

The dynamics of ions traversing sheaths in low temperature plasmas are important to the formation of the ion energy distribution incident onto surfaces during microelectronics fabrication. Ion dynamics have been measured using laser-induced fluorescence (LIF) in the sheath above a 30 cm diameter, 2.2 MHz-biased silicon wafer in a commercial inductively coupled plasma processing reactor. The velocity distribution of argon ions was measured at thousands of positions above and radially along the surface of the wafer by utilizing a planar laser sheet from a pulsed, tunable dye laser. Velocities were measured both parallel and perpendicular to the wafer over an energy range of 0.4-600 eV. The resulting fluorescence was recorded using a fast CCD camera, which provided resolution of 0.4 mm in space and 30 ns in time. Data were taken at eight different phases during the 2.2 MHz cycle. The ion velocity distributions (IVDs) in the sheath were found to be spatially non-uniform near the edge of the wafer and phase-dependent as a function of height. Several cm above the wafer the IVD is Maxwellian and independent of phase. Experimental results were compared with simulations. The experimental time-averaged ion energy distribution function as a function of height compare favorably with results from the computer model.

Noncontact Measurement of Doping Profile for Bare Silicon

NASA Astrophysics Data System (ADS)

Kohno, Motohiro; Matsubara, Hideaki; Okada, Hiroshi; Hirae, Sadao; Sakai, Takamasa

1998-10-01

In this study, we evaluate the doping concentrations of bare silicon wafers by noncontact capacitance voltage (C V) measurements. The metal-air-insulator-semiconductor (MAIS) method enables the measurement of C V characteristics of silicon wafers without oxidation and electrode preparation. This method has the advantage that a doping profile close to the wafer surface can be obtained. In our experiment, epitaxial silicon wafers were used to compare the MAIS method with the conventional MIS method. The experimental results obtained from the two methods showed good agreement. Then, doping profiles of boron-doped Czochralski (CZ) wafers were measured by the MAIS method. The result indicated a significant reduction of the doping concentration near the wafer surface. This observation is attributed to the well-known deactivation of boron with atomic hydrogen which permeated the silicon bulk during the polishing process. This deactivation was recovered by annealing in air at 180°C for 120 min.

Graphene-Based Reversible Nano-Switch/Sensor Schottky Diode

NASA Technical Reports Server (NTRS)

Miranda, Felix A.; Meador, Michael A.; Theofylaktos, Onoufrios; Pinto, Nicholas J.; Mueller, Carl H.; Santos-Perez, Javier

2010-01-01

This proof-of-concept device consists of a thin film of graphene deposited on an electrodized doped silicon wafer. The graphene film acts as a conductive path between a gold electrode deposited on top of a silicon dioxide layer and the reversible side of the silicon wafer, so as to form a Schottky diode. By virtue of the two-dimensional nature of graphene, this device has extreme sensitivity to different gaseous species, thereby serving as a building block for a volatile species sensor, with the attribute of having reversibility properties. That is, the sensor cycles between active and passive sensing states in response to the presence or absence of the gaseous species.

Cohesive zone model for direct silicon wafer bonding

NASA Astrophysics Data System (ADS)

Kubair, D. V.; Spearing, S. M.

2007-05-01

Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

Reliability Analysis/Assessment of Advanced Technologies

DTIC Science & Technology

1990-05-01

34, Reliability Physics 1980 , IEEE, p. 165. 25. RADC-TR-83-244. 26. Towner, Janet M., et. al., "Aluminum Electromigration Under Pulsed D.C. Conditions...Duvvury, Redwine, Kitagawa, Haas, Chuang, Beydler, Hyslop , "Impact of Hot Carriers On DRAM circuits", 1987 IEEE/IRPS. 58. Cahoon, Thornewell, Tsai...et. a]., "Substrate for Large Silicon Chip and Full Wafer Packaging", Semiconductor International, pp. 149-156, April 1980 . 5. T.E. Lewis and D.L

Simultaneous dual-functioning InGaN/GaN multiple-quantum-well diode for transferrable optoelectronics

NASA Astrophysics Data System (ADS)

Shi, Zheng; Yuan, Jialei; Zhang, Shuai; Liu, Yuhuai; Wang, Yongjin

2017-10-01

We propose a wafer-level procedure for the fabrication of 1.5-mm-diameter dual functioning InGaN/GaN multiple-quantum-well (MQW) diodes on a GaN-on-silicon platform for transferrable optoelectronics. Nitride semiconductor materials are grown on (111) silicon substrates with intermediate Al-composition step-graded buffer layers, and membrane-type MQW-diode architectures are obtained by a combination of silicon removal and III-nitride film backside thinning. Suspended MQW-diodes are directly transferred from silicon to foreign substrates such as metal, glass and polyethylene terephthalate by mechanically breaking the support beams. The transferred MQW-diodes display strong electroluminescence under current injection and photodetection under light irradiation. Interestingly, they demonstrate a simultaneous light-emitting light-detecting function, endowing the 1.5-mm-diameter MQW-diode with the capability of producing transferrable optoelectronics for adjustable displays, wearable optical sensors, multifunctional energy harvesting, flexible light communication and monolithic photonic circuit.

Optimization of the Surface Structure on Black Silicon for Surface Passivation.

PubMed

Jia, Xiaojie; Zhou, Chunlan; Wang, Wenjing

2017-12-01

Black silicon shows excellent anti-reflection and thus is extremely useful for photovoltaic applications. However, its high surface recombination velocity limits the efficiency of solar cells. In this paper, the effective minority carrier lifetime of black silicon is improved by optimizing metal-catalyzed chemical etching (MCCE) method, using an Al 2 O 3 thin film deposited by atomic layer deposition (ALD) as a passivation layer. Using the spray method to eliminate the impact on the rear side, single-side black silicon was obtained on n-type solar grade silicon wafers. Post-etch treatment with NH 4 OH/H 2 O 2 /H 2 O mixed solution not only smoothes the surface but also increases the effective minority lifetime from 161 μs of as-prepared wafer to 333 μs after cleaning. Moreover, adding illumination during the etching process results in an improvement in both the numerical value and the uniformity of the effective minority carrier lifetime.

Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

NASA Technical Reports Server (NTRS)

Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.;

Silicon nanowire-based tunneling field-effect transistors on flexible plastic substrates.

PubMed

Lee, Myeongwon; Koo, Jamin; Chung, Eun-Ae; Jeong, Dong-Young; Koo, Yong-Seo; Kim, Sangsig

2009-11-11

A technique to implement silicon nanowire (SiNW)-based tunneling field-effect transistors (TFETs) on flexible plastic substrates is developed for the first time. The p-i-n configured Si NWs are obtained from an Si wafer using a conventional top-down CMOS-compatible technology, and they are then transferred onto the plastic substrate. Based on gate-controlled band-to-band tunneling (BTBT) as their working principle, the SiNW-based TFETs show normal p-channel switching behavior with a threshold voltage of -1.86 V and a subthreshold swing of 827 mV/dec. In addition, ambipolar conduction is observed due to the presence of the BTBT between the heavily doped p+ drain and n+ channel regions, indicating that our TFETs can operate in the n-channel mode as well. Furthermore, the BTBT generation rates for both the p-channel and n-channel operating modes are nearly independent of the bending state (strain = 0.8%) of the plastic substrate.

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

NASA Astrophysics Data System (ADS)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Coherent spin transport through a 350 micron thick silicon wafer.

PubMed

Huang, Biqin; Monsma, Douwe J; Appelbaum, Ian

2007-10-26

We use all-electrical methods to inject, transport, and detect spin-polarized electrons vertically through a 350-micron-thick undoped single-crystal silicon wafer. Spin precession measurements in a perpendicular magnetic field at different accelerating electric fields reveal high spin coherence with at least 13pi precession angles. The magnetic-field spacing of precession extrema are used to determine the injector-to-detector electron transit time. These transit time values are associated with output magnetocurrent changes (from in-plane spin-valve measurements), which are proportional to final spin polarization. Fitting the results to a simple exponential spin-decay model yields a conduction electron spin lifetime (T1) lower bound in silicon of over 500 ns at 60 K.

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Making Wide-IF SIS Mixers with Suspended Metal-Beam Leads

NASA Technical Reports Server (NTRS)

Kaul, Anupama; Bumble, Bruce; Lee, Karen; LeDuc, Henry; Rice, Frank; Zmuidzinas, Jonas

2005-01-01

A process that employs silicon-on-insulator (SOI) substrates and silicon (Si) micromachining has been devised for fabricating wide-intermediate-frequency-band (wide-IF) superconductor/insulator/superconductor (SIS) mixer devices that result in suspended gold beam leads used for radio-frequency grounding. The mixers are formed on 25- m-thick silicon membranes. They are designed to operate in the 200 to 300 GHz frequency band, wherein wide-IF receivers for tropospheric- chemistry and astrophysical investigations are necessary. The fabrication process can be divided into three sections: 1. The front-side process, in which SIS devices with beam leads are formed on a SOI wafer; 2. The backside process, in which the SOI wafer is wax-mounted onto a carrier wafer, then thinned, then partitioned into individual devices; and 3. The release process, in which the individual devices are separated using a lithographic dicing technique. The total thickness of the starting 4-in. (10.16-cm)-diameter SOI wafer includes 25 m for the Si device layer, 0.5 m for the buried oxide (BOX) layer, and 350 m the for Si-handle layer. The front-side process begins with deposition of an etch-stop layer of SiO2 or AlN(x), followed by deposition of a Nb/Al- AlN(x) /Nb trilayer in a load-locked DC magnetron sputtering system. The lithography for four of a total of five layers is performed in a commercial wafer-stepping apparatus. Diagnostic test dies are patterned concurrently at certain locations on the wafer, alongside the mixer devices, using a different mask set. The conventional, self-aligned lift-off process is used to pattern the SIS devices up to the wire level.

Chromium Trioxide Hole-Selective Heterocontacts for Silicon Solar Cells.

PubMed

Lin, Wenjie; Wu, Weiliang; Liu, Zongtao; Qiu, Kaifu; Cai, Lun; Yao, Zhirong; Ai, Bin; Liang, Zongcun; Shen, Hui

2018-04-25

A high recombination rate and high thermal budget for aluminum (Al) back surface field are found in the industrial p-type silicon solar cells. Direct metallization on lightly doped p-type silicon, however, exhibits a large Schottky barrier for the holes on the silicon surface because of Fermi-level pinning effect. As a result, low-temperature-deposited, dopant-free chromium trioxide (CrO x , x < 3) with high stability and high performance is first applied in a p-type silicon solar cell as a hole-selective contact at the rear surface. By using 4 nm CrO x between the p-type silicon and Ag, we achieve a reduction of the contact resistivity for the contact of Ag directly on p-type silicon. For further improvement, we utilize a CrO x (2 nm)/Ag (30 nm)/CrO x (2 nm) multilayer film on the contact between Ag and p-type crystalline silicon (c-Si) to achieve a lower contact resistance (40 mΩ·cm 2 ). The low-resistivity Ohmic contact is attributed to the high work function of the uniform CrO x film and the depinning of the Fermi level of the SiO x layer at the silicon interface. Implementing the advanced hole-selective contacts with CrO x /Ag/CrO x on the p-type silicon solar cell results in a power conversion efficiency of 20.3%, which is 0.1% higher than that of the cell utilizing 4 nm CrO x . Compared with the commercialized p-type solar cell, the novel CrO x -based hole-selective transport material opens up a new possibility for c-Si solar cells using high-efficiency, low-temperature, and dopant-free deposition techniques.

Silicon Hybrid Wafer Scale Integration Interconnect Evaluation

DTIC Science & Technology

1989-12-01

perform Wafer Scale Integration on a routine basis is being vigorously pursued by a number of interests in military, academic , and commercial sectors...A iliciosi rip1 St -110 illic. (;11ptai / W. -a ;,tcd Ihat Ilesc hybhrid futl liods separiltely soI lie llixiiiul’upw~v~ ielts andl ~il (otii’ie thli

Iridium-coated micropore x-ray optics using dry etching of a silicon wafer and atomic layer deposition.

PubMed

Ogawa, Tomohiro; Ezoe, Yuichiro; Moriyama, Teppei; Mitsuishi, Ikuyuki; Kakiuchi, Takuya; Ohashi, Takaya; Mitsuda, Kazuhisa; Putkonen, Matti

2013-08-20

To enhance x-ray reflectivity of silicon micropore optics using dry etching of silicon (111) wafers, iridium coating is tested by use of atomic layer deposition. An iridium layer is successfully formed on sidewalls of tiny micropores with a pore width of 20 μm and depth of 300 μm. The film thickness is ∼20  nm. An enhanced x-ray reflectivity compared to that of silicon is confirmed at Ti K_α 4.51 keV, for what we believe to be the first time, with this type of optics. Some discrepancies from a theoretical reflectivity curve of iridium-coated silicon are noticed at small incident angles <1.3°. When a geometrical shadowing effect due to occultation by a ridge existing on the sidewalls is taken into account, the observed reflectivity becomes well represented by the modified theoretical curve. An estimated surface micro roughness of ∼1  nm rms is consistent with atomic force microscope measurements of the sidewalls.

A Compact Imaging Detector of Polarization and Spectral Content

NASA Technical Reports Server (NTRS)

Rust, D. M.; Kumar, A.; Thompson, K. E.

1993-01-01

A new type of image detector will simultaneously analyze the polarization of light at all picture elements in a scene. The integrated Dual Imaging Detector (IDID) consists of a polarizing beam splitter bonded to a charge-coupled device (CCD), with signal-analysis circuitry and analog-to-digital converters, all integrated on a silicon chip. The polarizing beam splitter can be either a Ronchi ruling, or an array of cylindrical lenslets, bonded to a birefringent wafer. The wafer, in turn, is bonded to the CCD so that light in the two orthogonal planes of polarization falls on adjacent pairs of pixels. The use of a high-index birefringent material, e.g., rutile, allows the IDID to operate at f-numbers as high as f/3.5. Other aspects of the detector are discussed.

A high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging.

PubMed

Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

2014-12-16

This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in "H" type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than -0.01% F.S/°C in the range of -40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S.

Chemical multisensors with selective encapsulation of ion-selective membranes

NASA Astrophysics Data System (ADS)

Schwager, Felix J.; Bousse, Luc J.; Bowman, Lyn; Meindl, J. D.

Chemical sensors fabricated with simultaneous wafer scale encapsulation of ion selective electrode mambranes are described. The sensors are miniature ion selective electrodes in chambers located on a silicon substrate. These chambers are made by anodically bonding to the silicon a no. 7740 pyrex glass wafer in which cavities were drilled. Pores with dimensions selectable from 50 microns upwards are opened in the roofs of the chambers by drilling with a CO2 laser. Each sensor die contains four cavities which are filled under reduced pressure with liquid membrane material which is subsequently polymerized. The transducers on the cavity floor are Ag/AgCl electrodes. Interconnects between the sensor chambers on each die and bonding pads are made in the silicon substrate.

In(x)Ga(₁-x)As nanowires on silicon: one-dimensional heterogeneous epitaxy, bandgap engineering, and photovoltaics.

PubMed

Shin, Jae Cheol; Kim, Kyou Hyun; Yu, Ki Jun; Hu, Hefei; Yin, Leijun; Ning, Cun-Zheng; Rogers, John A; Zuo, Jian-Min; Li, Xiuling

2011-11-09

We report on the one-dimensional (1D) heteroepitaxial growth of In(x)Ga(1-x)As (x = 0.2-1) nanowires (NWs) on silicon (Si) substrates over almost the entire composition range using metalorganic chemical vapor deposition (MOCVD) without catalysts or masks. The epitaxial growth takes place spontaneously producing uniform, nontapered, high aspect ratio NW arrays with a density exceeding 1 × 10(8)/cm(2). NW diameter (∼30-250 nm) is inversely proportional to the lattice mismatch between In(x)Ga(1-x)As and Si (∼4-11%), and can be further tuned by MOCVD growth condition. Remarkably, no dislocations have been found in all composition In(x)Ga(1-x)As NWs, even though massive stacking faults and twin planes are present. Indium rich NWs show more zinc-blende and Ga-rich NWs exhibit dominantly wurtzite polytype, as confirmed by scanning transmission electron microscopy (STEM) and photoluminescence spectra. Solar cells fabricated using an n-type In(0.3)Ga(0.7)As NW array on a p-type Si(111) substrate with a ∼ 2.2% area coverage, operates at an open circuit voltage, V(oc), and a short circuit current density, J(sc), of 0.37 V and 12.9 mA/cm(2), respectively. This work represents the first systematic report on direct 1D heteroepitaxy of ternary In(x)Ga(1-x)As NWs on silicon substrate in a wide composition/bandgap range that can be used for wafer-scale monolithic heterogeneous integration for high performance photovoltaics.

Transfer of InP epilayers by wafer bonding

NASA Astrophysics Data System (ADS)

Hjort, Klas

2004-08-01

Wafer bonding increases the freedom of design in the integration of dissimilar materials. For example, it is interesting to combine III-V compounds that have direct band gap and high mobility with silicon (Si) that is extensively used in microelectronic applications. The interest to integrate III-V-based materials with Si arises primarily from two types of applications: smart pixels for optical intra- and inter-chip interconnects in the so-called optoelectronic integrated circuits, and optoelectronic devices using some material advantages of combining III-V with Si. Also, in the III-V industry larger substrates are crucial for higher efficiency in high-volume production, and especially so for monolithic microwave integrated circuits (MMIC). For indium phosphide (InP) the development of large-area substrates has not been able to keep up with market demands. One way to circumvent this problem is to use silicon substrates that are large-area, low-cost, and mechanically strong with high thermal conductivity. In addition, silicon is transparent at the emission wavelengths most often used in InP-based optoelectronics. Unfortunately, the large lattice-mismatch, 8.1%, between silicon and InP, has limited the success of heteroepitaxial growth. Hence, one alternative to be reviewed is InP-to-Si wafer bonding. When a direct semiconductor interface is not needed there are several other means of wafer bonding, e.g. adhesive, eutectic, and solid-state. These processes can be used for direct integration of small islets of epitaxially thin InP microelectronics onto other substrates, e.g. by transferring of InP-based epilayers to a Si-based microwave circuit by pick-and-place, BCB resist adhesive bonding and sacrificing of the InP substrate.

Quantum-Well Infrared Photodetector (QWIP) Focal Plane Assembly

NASA Technical Reports Server (NTRS)

Jhabvala, Murzy; Jhabvala, Christine A.; Ewin, Audrey J.; Hess, Larry A.; Hartmann, Thomas M.; La, Anh T.

2012-01-01

A paper describes the Thermal Infrared Sensor (TIRS), a QWIP-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 microns. The focal plane will contain three 640x512 QWIP arrays mounted on a silicon substrate. The silicon substrate is a custom-fabricated carrier board with a single layer of aluminum interconnects. The general fabrication process starts with a 4-in. (approx.10-cm) diameter silicon wafer. The wafer is oxidized, a single substrate contact is etched, and aluminum is deposited, patterned, and alloyed. This technology development is aimed at incorporating three large-format infrared detecting arrays based on GaAs QWIP technology onto a common focal plane with precision alignment of all three arrays. This focal plane must survive the rigors of flight qualification and operate at a temperature of 43 K (-230 C) for five years while orbiting the Earth. The challenges presented include ensuring thermal compatibility among all the components, designing and building a compact, somewhat modular system and ensuring alignment to very tight levels. The multi-array focal plane integrated onto a single silicon substrate is a new application of both QWIP array development and silicon wafer scale integration. The Invar-based assembly has been tested to ensure thermal reliability.

Reticle variation influence on manufacturing line and wafer device performance

NASA Astrophysics Data System (ADS)

Nistler, John L.; Spurlock, Kyle

1994-01-01

Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

Switchable static friction of piezoelectric composite—silicon wafer contacts

NASA Astrophysics Data System (ADS)

van den Ende, D. A.; Fischer, H. R.; Groen, W. A.; van der Zwaag, S.

2013-04-01

The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and a silicon wafer counter surface rests solely on the matrix region of the piezocomposite surface. When actuated, the piezoelectric ceramic fibers protrude from the surface and the wafer rests solely on these protrusions. A threefold decrease in engineering static friction coefficient upon actuation of the piezocomposite was observed: from μ* = 1.65 to μ* = 0.50. These experimental results could be linked to the change in contact surface area and roughness using capillary adhesion theory, which relates the adhesive force to the number and size of the contacting asperities for the different surface states.

Low-resistivity photon-transparent window attached to photo-sensitive silicon detector

DOEpatents

Holland, Stephen Edward

2000-02-15

The invention comprises a combination of a low resistivity, or electrically conducting, silicon layer that is transparent to long or short wavelength photons and is attached to the backside of a photon-sensitive layer of silicon, such as a silicon wafer or chip. The window is applied to photon sensitive silicon devices such as photodiodes, charge-coupled devices, active pixel sensors, low-energy x-ray sensors and other radiation detectors. The silicon window is applied to the back side of a photosensitive silicon wafer or chip so that photons can illuminate the device from the backside without interference from the circuit printed on the frontside. A voltage sufficient to fully deplete the high-resistivity photosensitive silicon volume of charge carriers is applied between the low-resistivity back window and the front, patterned, side of the device. This allows photon-induced charge created at the backside to reach the front side of the device and to be processed by any circuitry attached to the front side. Using the inventive combination, the photon sensitive silicon layer does not need to be thinned beyond standard fabrication methods in order to achieve full charge-depletion in the silicon volume. In one embodiment, the inventive backside window is applied to high resistivity silicon to allow backside illumination while maintaining charge isolation in CCD pixels.

Study of thin film production of ceramic ZrO2 on silicon wafer using second harmonic Nd-Yag laser with pulsed laser deposition technique

NASA Astrophysics Data System (ADS)

Suliyanti, Maria M.; Hidayah, Affi Nur; Kurniawan, K. H.

2012-06-01

Study about thin film production using technique pulsed laser deposition have been done. The Pulsed Laser Deposition (PLD) method has been used for growing thin film of ZrO2 on silicon wafer substrate (111 single crystal, thickness 400μm and diameter 7.5 cm). The target made from Zirconia oxide powder mixing with PVA and press using pressure 100kgN. The laser beam was focused by a lens (f = 100mm) through a quartz window onto the sample surface and the substrate was placed in parallel line with target. The distance between the target and the substrate is about 1 cm. The early results of this synthesis using 75 mJ Nd-YAG second harmonic laser pulse (532 nm Nd-YAG) and low pressure chamber surrounding gas 5 Torr. The irradiation of laser take around 6000 shoots or 10 minutes using frequencies laser 10 Hz. The micro thickness of film can be produced on silicon wafer using this technique. The results of ZrO2 thin film on substrate about 26.92%.

Noncontacting acoustics-based temperature measurement techniques in rapid thermal processing

NASA Astrophysics Data System (ADS)

Lee, Yong J.; Chou, Ching-Hua; Khuri-Yakub, Butrus T.; Saraswat, Krishna C.

1991-04-01

Temperature measurement of silicon wafers based on the temperature dependence of acoustic waves is studied. The change in the temperature-dependent dispersion relations of the plate modes through the wafer can be exploited to provide a viable temperature monitoring scheme with advantages over both thermocouples and pyrometers. Velocity measurements of acoustic waves through a thin layer of ambient directly above the wafer provides the temperature of the wafer-ambient interface. 1.

Monolithic microchannel heatsink

DOEpatents

Benett, W.J.; Beach, R.J.; Ciarlo, D.R.

1996-08-20

A silicon wafer has slots sawn in it that allow diode laser bars to be mounted in contact with the silicon. Microchannels are etched into the back of the wafer to provide cooling of the diode bars. To facilitate getting the channels close to the diode bars, the channels are rotated from an angle perpendicular to the diode bars which allows increased penetration between the mounted diode bars. This invention enables the fabrication of monolithic silicon microchannel heatsinks for laser diodes. The heatsinks have low thermal resistance because of the close proximity of the microchannels to the laser diode being cooled. This allows high average power operation of two-dimensional laser diode arrays that have a high density of laser diode bars and therefore high optical power density. 9 figs.

Monolithic microchannel heatsink

DOEpatents

Benett, William J.; Beach, Raymond J.; Ciarlo, Dino R.

1996-01-01

A silicon wafer has slots sawn in it that allow diode laser bars to be mounted in contact with the silicon. Microchannels are etched into the back of the wafer to provide cooling of the diode bars. To facilitate getting the channels close to the diode bars, the channels are rotated from an angle perpendicular to the diode bars which allows increased penetration between the mounted diode bars. This invention enables the fabrication of monolithic silicon microchannel heatsinks for laser diodes. The heatsinks have low thermal resistance because of the close proximity of the microchannels to the laser diode being cooled. This allows high average power operation of two-dimensional laser diode arrays that have a high density of laser diode bars and therefore high optical power density.

Optimized structural designs for stretchable silicon integrated circuits.

PubMed

Kim, Dae-Hyeong; Liu, Zhuangjian; Kim, Yun-Soung; Wu, Jian; Song, Jizhou; Kim, Hoon-Sik; Huang, Yonggang; Hwang, Keh-Chih; Zhang, Yongwei; Rogers, John A

2009-12-01

Materials and design strategies for stretchable silicon integrated circuits that use non-coplanar mesh layouts and elastomeric substrates are presented. Detailed experimental and theoretical studies reveal many of the key underlying aspects of these systems. The results shpw, as an example, optimized mechanics and materials for circuits that exhibit maximum principal strains less than 0.2% even for applied strains of up to approximately 90%. Simple circuits, including complementary metal-oxide-semiconductor inverters and n-type metal-oxide-semiconductor differential amplifiers, validate these designs. The results suggest practical routes to high-performance electronics with linear elastic responses to large strain deformations, suitable for diverse applications that are not readily addressed with conventional wafer-based technologies.

Protective Coating For Laser Drilling Of Silicon

NASA Technical Reports Server (NTRS)

Shlichta, Paul J.

1988-01-01

Sodium silicate prevents spattered silicon from fusing with surrounding material. Sodium silicate solution applied to wafer by dipping and draining or by spinning; application by spraying also works. When dried in oven, solution leaves thin coating of sodium silicate glass.

Electrical Investigation of Nanostructured Fe2O3/p-Si Heterojunction Diode Fabricated Using the Sol-Gel Technique

NASA Astrophysics Data System (ADS)

Mansour, Shehab A.; Ibrahim, Mervat M.

2017-11-01

Iron oxide (α-Fe2O3) nanocrystals have been synthesized via the sol-gel technique. The structural and morphological features of these nanocrystals were studied using x-ray diffraction, Fourier transform-infrared spectroscopy and transmission electron microscopy. Colloidal solution of synthesized α-Fe2O3 (hematite) was spin-coated onto a single-crystal p-type silicon (p-Si) wafer to fabricate a heterojunction diode with Mansourconfiguration Ag/Fe2O3/p-Si/Al. This diode was electrically characterized at room temperature using current-voltage (I-V) characteristics in the voltage range from -9 V to +9 V. The fabricated diode showed a good rectification behavior with a rectification factor 1.115 × 102 at 6 V. The junction parameters such as ideality factor, barrier height, series resistance and shunt resistance are determined using conventional I-V characteristics. For low forward voltage, the conduction mechanism is dominated by the defect-assisted tunneling process with conventional electron-hole recombination. However, at higher voltage, I-V ohmic and space charge-limited current conduction was became less effective with the contribution of the trapped-charge-limited current at the highest voltage range.

Progress and challenges for cost effective kerfless Silicon crystal growth for PV application

NASA Astrophysics Data System (ADS)

Serra, J. M.; Alves, J. Maia; Vallera, A. M.

2017-06-01

The major barrier for PV penetration is cost. And the single most important cost factor in silicon technology is the wafer (≈35% of the module cost). Although tremendous progress on cell processing has been reported in recent years, a much smaller evolution is seen on what should be the key point to address - the wafer. The ingot-slicing process is reaching its limits as the wafer thickness is reduced in an effort to lower material costs. Kerf losses of ≈50% and an increase in breakage of a high value added material are putting a lower bound to this approach. New ideas are therefore needed for producing wafers in a way to overcome these limitations. In this paper we present three new concepts being developed in our laboratory that have one thing in common: they all are zero kerf loss processes, aiming at significant reductions in material loss. One explores the concept of exfoliation, the other two aim at the growth of silicon directly into ribbons. These were conceived as continuous processes, based on a floating molten zone concept, to avoid impurity contamination during crystallization.

Fabrication of high-quality superconductor-insulator-superconductor junctions on thin SiN membranes

NASA Technical Reports Server (NTRS)

Garcia, Edouard; Jacobson, Brian R.; Hu, Qing

1993-01-01

We have successfully fabricated high-quality and high-current density superconductor-insulator-superconductor (SIS) junctions on freestanding thin silicon nitride (SIN) membranes. These devices can be used in a novel millimeter-wave and THz receiver system which is made using micromachining. The SIS junctions with planar antennas were fabricated first on a silicon wafer covered with a SiN membrane, the Si wafer underneath was then etched away using an anisotropic KOH etchant. The current-voltage characteristics of the SIS junctions remained unchanged after the whole process, and the junctions and the membrane survived thermal cycling.

A MoTe2 based light emitting diode and photodetector for silicon photonic integrated circuits

NASA Astrophysics Data System (ADS)

Bie, Ya-Qing; Heuck, M.; Grosso, G.; Furchi, M.; Cao, Y.; Zheng, J.; Navarro-Moratalla, E.; Zhou, L.; Taniguchi, T.; Watanabe, K.; Kong, J.; Englund, D.; Jarillo-Herrero, P.

A key challenge in photonics today is to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, partly because many components such as waveguides, interferometers and modulators, could be integrated on silicon-based processors. However, light sources and photodetectors present continued challenges. Common approaches for light source include off-chip or wafer-bonded lasers based on III-V materials, but studies show advantages for directly modulated light sources. The most advanced photodetectors in silicon photonics are based on germanium growth which increases system cost. The emerging two dimensional transition metal dichalcogenides (TMDs) offer a path for optical interconnects components that can be integrated with the CMOS processing by back-end-of-the-line processing steps. Here we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with infrared band gap. The state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

Experimental study of optical and electrical properties of ZnO nano composites electrodeposited on n-porous silicon substrate for photovoltaic applications

NASA Astrophysics Data System (ADS)

Selmane, Naceur; Cheknane, Ali; Gabouze, Nourddine; Maloufi, Nabila; Aillerie, Michel

2017-11-01

ZnO films deposited on silicon porous substrates (PS) were prepared by electro-deposition anodization on n type (100) silicon wafer. This ZnO/PS structure combines substrates having specific structural and optical properties (IR emission), with nano-composites of ZnO potentially interesting due to their functional properties (UV emission) to be integrated as constitutive elements of devices in various optoelectronic applications mainly in blue light emitters. With this combined structure, the blue shift in the PL peak is possible and easy to obtain (467nm). The vibration modes of PS and ZnO films on PS substrates (ZnO /PS) were investigated by infrared (FTIR) measurements and their behaviors were analyzed and discussed by considering the structural properties characterized by X-ray diffraction (DRX) and scanning electronic microscopy (MEB).

Silicon materials task of the low-cost solar array project. Phase 4: Effects of impurities and processing on silicon solar cells

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Hanes, M. H.; Davis, J. R.; Rohatgi, A.; Rai-Choudhury, P.; Mollenkopf, H. C.

1981-01-01

The effects of impurities, various thermochemical processes, and any impurity-process interactions upon the performance of terrestrial solar cells are defined. The results form a basis for silicon producers, wafer manufacturers, and cell fabricators to develop appropriate cost benefit relationships for the use of less pure, less costly solar grade silicon.

Amorphous-diamond electron emitter

DOEpatents

Falabella, Steven

2001-01-01

An electron emitter comprising a textured silicon wafer overcoated with a thin (200 .ANG.) layer of nitrogen-doped, amorphous-diamond (a:D-N), which lowers the field below 20 volts/micrometer have been demonstrated using this emitter compared to uncoated or diamond coated emitters wherein the emission is at fields of nearly 60 volts/micrometer. The silicon/nitrogen-doped, amorphous-diamond (Si/a:D-N) emitter may be produced by overcoating a textured silicon wafer with amorphous-diamond (a:D) in a nitrogen atmosphere using a filtered cathodic-arc system. The enhanced performance of the Si/a:D-N emitter lowers the voltages required to the point where field-emission displays are practical. Thus, this emitter can be used, for example, in flat-panel emission displays (FEDs), and cold-cathode vacuum electronics.

Effect of Rapid Thermal Processing on Light-Induced Degradation of Carrier Lifetime in Czochralski p-Type Silicon Bare Wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Y.; Bouhafs, D.; Khelifati, N.; Belhousse, S.; Menari, H.; Guenda, A.; Khelfane, A.

2016-11-01

The electrical properties of Czochralski silicon (Cz-Si) p-type boron-doped bare wafers have been investigated after rapid thermal processing (RTP) with different peak temperatures. Treated wafers were exposed to light for various illumination times, and the effective carrier lifetime ( τ eff) measured using the quasi-steady-state photoconductance (QSSPC) technique. τ eff values dropped after prolonged illumination exposure due to light-induced degradation (LID) related to electrical activation of boron-oxygen (BO) complexes, except in the sample treated with peak temperature of 785°C, for which the τ eff degradation was less pronounced. Also, a reduction was observed when using the 830°C peak temperature, an effect that was enhanced by alteration of the wafer morphology (roughness). Furthermore, the electrical resistivity presented good stability under light exposure as a function of temperature compared with reference wafers. Additionally, the optical absorption edge shifted to higher wavelength, leading to increased free-carrier absorption by treated wafers. Moreover, a theoretical model is used to understand the lifetime degradation and regeneration behavior as a function of illumination time. We conclude that RTP plays an important role in carrier lifetime regeneration for Cz-Si wafers via modification of optoelectronic and structural properties. The balance between an optimized RTP cycle and the rest of the solar cell elaboration process can overcome the negative effect of LID and contribute to achievement of higher solar cell efficiency and module performance.

N-VSi-related center in non-irradiated 6H SiC nanostructure

NASA Astrophysics Data System (ADS)

Bagraev, Nikolay; Danilovskii, Eduard; Gets, Dmitrii; Kalabukhova, Ekaterina; Klyachkin, Leonid; Malyarenko, Anna; Savchenko, Dariya; Shanina, Bella

2014-02-01

We present the first findings of the vacancy-related centers identified by the electron spin resonance (ESR) and electrically-detected (ED) ESR method in the non-irradiated 6H-SiC nanostructure. This planar 6H-SiC nanostructure represents the ultra-narrow p-type quantum well confined by the δ-barriers heavily doped with boron on the surface of the n-type 6H-SiC (0001) wafer. The EDESR method by measuring the only magnetoresistance of the 6H SiC nanostructure under the high frequency generation from the δ-barriers appears to allow the identification of the silicon vacancy centers as well as the triplet center with spin state S=1. The same triplet center that is characterized by the larger value of the zero-field splitting constant D and anisotropic g-factor is revealed by the ESR (X-band) method. The hyperfine (hf) lines in the ESR and EDESR spectra originating from the hf interaction with the 14N nucleus allow us to attribute this triplet center to the N-VSi defect.

Fabrication of a Silicon Backshort Assembly for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Solar cell and I.C. aspects of ingot-to-slice mechanical processing

NASA Astrophysics Data System (ADS)

Dyer, L. D.

1985-08-01

Intensive efforts have been put into the growth of silicon crystals to suit today's solar cell and integrated circuit requirements. Each step of processing the crystal must also receive concentrated attention to preserve the grown-in perfection and to provide a suitable device-ready wafer at reasonable cost. A comparison is made between solar cell and I.C. requirements on the mechanical processing of silicon from ingot to wafer. Specific defects are described that can ruin the slice or can possibly lead to device degradation. These include grinding cracks, saw exit chips, crow's-foot fractures, edge cracks, and handling scratches.

Solar cell and I.C. aspects of ingot-to-slice mechanical processing

NASA Technical Reports Server (NTRS)

Dyer, L. D.

1985-01-01

Intensive efforts have been put into the growth of silicon crystals to suit today's solar cell and integrated circuit requirements. Each step of processing the crystal must also receive concentrated attention to preserve the grown-in perfection and to provide a suitable device-ready wafer at reasonable cost. A comparison is made between solar cell and I.C. requirements on the mechanical processing of silicon from ingot to wafer. Specific defects are described that can ruin the slice or can possibly lead to device degradation. These include grinding cracks, saw exit chips, crow's-foot fractures, edge cracks, and handling scratches.

Electron-Beam Deposition of Superconducting Molybdenum Thin Films for the Development of Mo/Au TES X-Ray Microcalorimeter

NASA Technical Reports Server (NTRS)

Finkbeiner, Fred Michael; Adams, Joseph S.; Bandler, Simon R.; Betancour-Martinez, Gabriele L.; Brown, Ari David; Chang, Meng-Ping; Chervenak, James A.; Chiao, Meng P.; Datesman, Aaron; Eckart, Megan E.;

Optical surface analysis: a new technique for the inspection and metrology of optoelectronic films and wafers

NASA Astrophysics Data System (ADS)

Bechtler, Laurie; Velidandla, Vamsi

2003-04-01

In response to demand for higher volumes and greater product capability, integrated optoelectronic device processing is rapidly increasing in complexity, benefiting from techniques developed for conventional silicon integrated circuit processing. The needs for high product yield and low manufacturing cost are also similar to the silicon wafer processing industry. This paper discusses the design and use of an automated inspection instrument called the Optical Surface Analyzer (OSA) to evaluate two critical production issues in optoelectronic device manufacturing: (1) film thickness uniformity, and (2) defectivity at various process steps. The OSA measurement instrument is better suited to photonics process development than most equipment developed for conventional silicon wafer processing in two important ways: it can handle both transparent and opaque substrates (unlike most inspection and metrology tools), and it is a full-wafer inspection method that captures defects and film variations over the entire substrate surface (unlike most film thickness measurement tools). Measurement examples will be provided in the paper for a variety of films and substrates used for optoelectronics manufacturing.

Delta-Doping at Wafer Level for High Throughput, High Yield Fabrication of Silicon Imaging Arrays

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Nikzad, Shoulch (Inventor); Jones, Todd J. (Inventor); Greer, Frank (Inventor); Carver, Alexander G. (Inventor)

2014-01-01

Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3 + NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.

A cochlear implant fabricated using a bulk silicon-surface micromachining process

NASA Astrophysics Data System (ADS)

Bell, Tracy Elizabeth

1999-11-01

This dissertation presents the design and fabrication of two generations of a silicon microelectrode array for use in a cochlear implant. A cochlear implant is a device that is inserted into the inner ear and uses electrical stimulation to provide sound sensations to the profoundly deaf. The first-generation silicon cochlear implant is a passive device fabricated using silicon microprobe technology developed at the University of Michigan. It contains twenty-two iridium oxide (IrO) stimulating sites that are 250 mum in diameter and spaced at 750 mum intervals. In-vivo recordings were made in guinea pig auditory cortex in response to electrical stimulation with this device, verifying its ability to electrically evoke an auditory response. Auditory thresholds as low as 78 muA were recorded. The second-generation implant is a thirty-two site, four-channel device with on-chip CMOS site-selection circuitry and integrated position sensing. It was fabricated using a novel bulk silicon surface micromachining process which was developed as a part of this dissertation work. While the use of semiconductor technology offers many advantages in fabricating cochlear implants over the methods currently used, it was felt that even further advantages could be gained by developing a new micromachining process which would allow circuitry to be distributed along the full length of the cochlear implant substrate. The new process uses electropolishing of an n+ bulk silicon sacrificial layer to undercut and release n- epitaxial silicon structures from the wafer. An extremely abrupt etch-stop between the n+ and n- silicon is obtained, with no electropolishing taking place in the n-type silicon that is doped lower than 1 x 1017 cm-3 in concentration. Lateral electropolishing rates of up to 50 mum/min were measured using this technique, allowing one millimeter-wide structures to be fully undercut in as little as 10 minutes. The new micromachining process was integrated with a standard p-well CMOS integrated circuit process to fabricate the second-generation active silicon cochlear implants.

Investigation of diffusion length distribution on polycrystalline silicon wafers via photoluminescence methods

PubMed Central

Lou, Shishu; Zhu, Huishi; Hu, Shaoxu; Zhao, Chunhua; Han, Peide

2015-01-01

Characterization of the diffusion length of solar cells in space has been widely studied using various methods, but few studies have focused on a fast, simple way to obtain the quantified diffusion length distribution on a silicon wafer. In this work, we present two different facile methods of doing this by fitting photoluminescence images taken in two different wavelength ranges or from different sides. These methods, which are based on measuring the ratio of two photoluminescence images, yield absolute values of the diffusion length and are less sensitive to the inhomogeneity of the incident laser beam. A theoretical simulation and experimental demonstration of this method are presented. The diffusion length distributions on a polycrystalline silicon wafer obtained by the two methods show good agreement. PMID:26364565

Bio-inspired Fabrication of Complex Hierarchical Structure in Silicon.

PubMed

Gao, Yang; Peng, Zhengchun; Shi, Tielin; Tan, Xianhua; Zhang, Deqin; Huang, Qiang; Zou, Chuanping; Liao, Guanglan

2015-08-01

In this paper, we developed a top-down method to fabricate complex three dimensional silicon structure, which was inspired by the hierarchical micro/nanostructure of the Morpho butterfly scales. The fabrication procedure includes photolithography, metal masking, and both dry and wet etching techniques. First, microscale photoresist grating pattern was formed on the silicon (111) wafer. Trenches with controllable rippled structures on the sidewalls were etched by inductively coupled plasma reactive ion etching Bosch process. Then, Cr film was angled deposited on the bottom of the ripples by electron beam evaporation, followed by anisotropic wet etching of the silicon. The simple fabrication method results in large scale hierarchical structure on a silicon wafer. The fabricated Si structure has multiple layers with uniform thickness of hundreds nanometers. We conducted both light reflection and heat transfer experiments on this structure. They exhibited excellent antireflection performance for polarized ultraviolet, visible and near infrared wavelengths. And the heat flux of the structure was significantly enhanced. As such, we believe that these bio-inspired hierarchical silicon structure will have promising applications in photovoltaics, sensor technology and photonic crystal devices.

Nanoparticle-based etching of silicon surfaces

DOEpatents

Branz, Howard [Boulder, CO; Duda, Anna [Denver, CO; Ginley, David S [Evergreen, CO; Yost, Vernon [Littleton, CO; Meier, Daniel [Atlanta, GA; Ward, James S [Golden, CO

2011-12-13

A method (300) of texturing silicon surfaces (116) such to reduce reflectivity of a silicon wafer (110) for use in solar cells. The method (300) includes filling (330, 340) a vessel (122) with a volume of an etching solution (124) so as to cover the silicon surface 116) of a wafer or substrate (112). The etching solution (124) is made up of a catalytic nanomaterial (140) and an oxidant-etchant solution (146). The catalytic nanomaterial (140) may include gold or silver nanoparticles or noble metal nanoparticles, each of which may be a colloidal solution. The oxidant-etchant solution (146) includes an etching agent (142), such as hydrofluoric acid, and an oxidizing agent (144), such as hydrogen peroxide. Etching (350) is performed for a period of time including agitating or stirring the etching solution (124). The etch time may be selected such that the etched silicon surface (116) has a reflectivity of less than about 15 percent such as 1 to 10 percent in a 350 to 1000 nanometer wavelength range.

Addressable Inverter Matrix Tests Integrated-Circuit Wafer

NASA Technical Reports Server (NTRS)

Buehler, Martin G.

1988-01-01

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Further Investigations of Hypersonic Engine Seals

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H., Jr.; Steinetz, Bruce M.; DeMange, Jeffrey J.

2004-01-01

Durable, flexible sliding seals are required in advanced hypersonic engines to seal the perimeters of movable engine ramps for efficient, safe operation in high heat flux environments at temperatures of 2000 to 2500 F. Current seal designs do not meet the demanding requirements for future engines, so NASA's Glenn Research Center is developing advanced seals and preloading devices to overcome these shortfalls. An advanced ceramic wafer seal design and two silicon nitride compression spring designs were evaluated in a series of compression, scrub, and flow tests. Silicon nitride wafer seals survived 2000 in. (50.8 m) of scrubbing at 2000 F against a silicon carbide rub surface with no chips or signs of damage. Flow rates measured for the wafers before and after scrubbing were almost identical and were up to 32 times lower than those recorded for the best braided rope seal flow blockers. Silicon nitride compression springs showed promise conceptually as potential seal preload devices to help maintain seal resiliency.

A High-Q Resonant Pressure Microsensor with Through-Glass Electrical Interconnections Based on Wafer-Level MEMS Vacuum Packaging

PubMed Central

Luo, Zhenyu; Chen, Deyong; Wang, Junbo; Li, Yinan; Chen, Jian

2014-01-01

This paper presents a high-Q resonant pressure microsensor with through-glass electrical interconnections based on wafer-level MEMS vacuum packaging. An approach to maintaining high-vacuum conditions by integrating the MEMS fabrication process with getter material preparation is presented in this paper. In this device, the pressure under measurement causes a deflection of a pressure-sensitive silicon square diaphragm, which is further translated to stress build up in “H” type doubly-clamped micro resonant beams, leading to a resonance frequency shift. The device geometries were optimized using FEM simulation and a 4-inch SOI wafer was used for device fabrication, which required only three photolithographic steps. In the device fabrication, a non-evaporable metal thin film as the getter material was sputtered on a Pyrex 7740 glass wafer, which was then anodically bonded to the patterned SOI wafer for vacuum packaging. Through-glass via holes predefined in the glass wafer functioned as the electrical interconnections between the patterned SOI wafer and the surrounding electrical components. Experimental results recorded that the Q-factor of the resonant beam was beyond 22,000, with a differential sensitivity of 89.86 Hz/kPa, a device resolution of 10 Pa and a nonlinearity of 0.02% F.S with the pressure varying from 50 kPa to 100 kPa. In addition, the temperature drift coefficient was less than −0.01% F.S/°C in the range of −40 °C to 70 °C, the long-term stability error was quantified as 0.01% F.S over a 5-month period and the accuracy of the microsensor was better than 0.01% F.S. PMID:25521385

Lithium-ion drifting: Application to the study of point defects in floating-zone silicon

NASA Technical Reports Server (NTRS)

Walton, J. T.; Wong, Y. K.; Zulehner, W.

1997-01-01

The use of lithium-ion (Li(+)) drifting to study the properties of point defects in p-type Floating-Zone (FZ) silicon crystals is reported. The Li(+) drift technique is used to detect the presence of vacancy-related defects (D defects) in certain p-type FZ silicon crystals. SUPREM-IV modeling suggests that the silicon point defect diffusivities are considerably higher than those commonly accepted, but are in reasonable agreement with values recently proposed. These results demonstrate the utility of Li(+) drifting in the study of silicon point defect properties in p-type FZ crystals. Finally, a straightforward measurement of the Li(+) compensation depth is shown to yield estimates of the vacancy-related defect concentration in p-type FZ crystals.

Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

NASA Astrophysics Data System (ADS)

Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

Capillary-Driven Microfluidic Chips for Miniaturized Immunoassays: Efficient Fabrication and Sealing of Chips Using a "Chip-Olate" Process.

PubMed

Temiz, Yuksel; Delamarche, Emmanuel

2017-01-01

The fabrication of silicon-based microfluidic chips is invaluable in supporting the development of many microfluidic concepts for research in the life sciences and in vitro diagnostic applications such as the realization of miniaturized immunoassays using capillary-driven chips. While being extremely abundant, the literature covering microfluidic chip fabrication and assay development might not have addressed properly the challenge of fabricating microfluidic chips on a wafer level or the need for dicing wafers to release chips that need then to be further processed, cleaned, rinsed, and dried one by one. Here, we describe the "chip-olate" process wherein microfluidic structures are formed on a silicon wafer, followed by partial dicing, cleaning, and drying steps. Then, integration of reagents (if any) can be done, followed by lamination of a sealing cover. Breaking by hand the partially diced wafer yields individual chips ready for use.

PN-type carrier-induced filter with modulatable extinction ratio.

PubMed

Fang, Qing; Tu, Xiaoguang; Song, Junfeng; Jia, Lianxi; Luo, Xianshu; Yang, Yan; Yu, Mingbin; Lo, Guoqiang

2014-12-01

We demonstrate the first PN-type carrier-induced silicon waveguide Bragg grating filter on a SOI wafer. The optical extinction ratio of this kind of filter can be efficiently modulated under both reverse and forward biases. The carrier-induced Bragg grating based on a PN junction is fabricated on the silicon waveguide using litho compensation technology. The measured optical bandwidth and the extinction ratio of the filter are 0.45 nm and 19 dB, respectively. The optical extinction ratio modulation under the reverse bias is more than 11.5 dB and it is more than 10 dB under the forward bias. Only 1-dB optical transmission loss is realized in this Bragg grating under a reverse bias. The shifting rates of the central wavelength under forward and reverse biases are ~-1.25 nm/V and 0.01 nm/V, respectively. The 3-dB modulation bandwidth of this filter is 5.1 GHz at a bias of -10 V.

Correlation of 150-mm silicon wafer site flatness with stepper performance for deep submicron applications

NASA Astrophysics Data System (ADS)

Huff, Howard R.; Vigil, Joseph C.; Kuyel, Birol; Chan, David Y.; Nguyen, Long P.

1992-06-01

An experimental study was conducted to correlate wafer site flatness SFQD with stepper performance for half-micron lines and spaces. CD measurements were taken on wafers patterned on both GCA pre-production XLS i-line and SVGL Micrascan-90 DUV steppers as well as focus measurements on the Micrascan-90. Wafer site flatness SFQD less than 0.3 micrometers was observed to be a sufficiently small variable in CD non-uniformities for these initial half-micron stepper applications.

Electron-selective contacts via ultra-thin organic interface dipoles for silicon organic heterojunction solar cells

NASA Astrophysics Data System (ADS)

Reichel, Christian; Würfel, Uli; Winkler, Kristina; Schleiermacher, Hans-Frieder; Kohlstädt, Markus; Unmüssig, Moritz; Messmer, Christoph A.; Hermle, Martin; Glunz, Stefan W.

2018-01-01

In the last years, novel materials for the formation of electron-selective contacts on n-type crystalline silicon (c-Si) heterojunction solar cells were explored as an interfacial layer between the metal electrode and the c-Si wafer. Besides inorganic materials like transition metal oxides or alkali metal fluorides, also interfacial layers based on organic molecules with a permanent dipole moment are promising candidates to improve the contact properties. Here, the dipole effect plays an essential role in the modification of the interface and effective work function of the contact. The amino acids L-histidine, L-tryptophan, L-phenylalanine, glycine, and sarcosine, the nucleobase adenine, and the heterocycle 4-hydroxypyridine were investigated as dipole materials for an electron-selective contact on the back of p- and n-type c-Si with a metal electrode based on aluminum (Al). Furthermore, the effect of an added fluorosurfactant on the resulting contact properties was examined. The performance of n-type c-Si solar cells with a boron diffusion on the front was significantly increased when L-histidine and/or the fluorosurfactant was applied as a full-area back surface field. This improvement was attributed to the modification of the interface and the effective work function of the contact by the dipole material which was corroborated by numerical device simulations. For these solar cells, conversion efficiencies of 17.5% were obtained with open-circuit voltages (Voc) of 625 mV and fill factors of 76.3%, showing the potential of organic interface dipoles for silicon organic heterojunction solar cells due to their simple formation by solution processing and their low thermal budget requirements.

Methods of Measurement for Semiconductor Materials, Process Control, and Devices

NASA Technical Reports Server (NTRS)

Bullis, W. M. (Editor)

1973-01-01

The development of methods of measurement for semiconductor materials, process control, and devices is reported. Significant accomplishments include: (1) Completion of an initial identification of the more important problems in process control for integrated circuit fabrication and assembly; (2) preparations for making silicon bulk resistivity wafer standards available to the industry; and (3) establishment of the relationship between carrier mobility and impurity density in silicon. Work is continuing on measurement of resistivity of semiconductor crystals; characterization of generation-recombination-trapping centers, including gold, in silicon; evaluation of wire bonds and die attachment; study of scanning electron microscopy for wafer inspection and test; measurement of thermal properties of semiconductor devices; determination of S-parameters and delay time in junction devices; and characterization of noise and conversion loss of microwave detector diodes.

Post exposure bake unit equipped with wafer-shape compensation technology

NASA Astrophysics Data System (ADS)

Goto, Shigehiro; Morita, Akihiko; Oyama, Kenichi; Hori, Shimpei; Matsuchika, Keiji; Taniguchi, Hideyuki

2007-03-01

In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

Processing of n+/p-/p+ strip detectors with atomic layer deposition (ALD) grown Al2O3 field insulator on magnetic Czochralski silicon (MCz-si) substrates

NASA Astrophysics Data System (ADS)

Härkönen, J.; Tuovinen, E.; Luukka, P.; Gädda, A.; Mäenpää, T.; Tuominen, E.; Arsenovich, T.; Junkes, A.; Wu, X.; Li, Z.

2016-08-01

Detectors manufactured on p-type silicon material are known to have significant advantages in very harsh radiation environment over n-type detectors, traditionally used in High Energy Physics experiments for particle tracking. In p-type (n+ segmentation on p substrate) position-sensitive strip detectors, however, the fixed oxide charge in the silicon dioxide is positive and, thus, causes electron accumulation at the Si/SiO2 interface. As a result, unless appropriate interstrip isolation is applied, the n-type strips are short-circuited. Widely adopted methods to terminate surface electron accumulation are segmented p-stop or p-spray field implantations. A different approach to overcome the near-surface electron accumulation at the interface of silicon dioxide and p-type silicon is to deposit a thin film field insulator with negative oxide charge. We have processed silicon strip detectors on p-type Magnetic Czochralski silicon (MCz-Si) substrates with aluminum oxide (Al2O3) thin film insulator, grown with Atomic Layer Deposition (ALD) method. The electrical characterization by current-voltage and capacitance-voltage measurement shows reliable performance of the aluminum oxide. The final proof of concept was obtained at the test beam with 200 GeV/c muons. For the non-irradiated detector the charge collection efficiency (CCE) was nearly 100% with a signal-to-noise ratio (S/N) of about 40, whereas for the 2×1015 neq/cm2 proton irradiated detector the CCE was 35%, when the sensor was biased at 500 V. These results are comparable with the results from p-type detectors with the p-spray and p-stop interstrip isolation techniques. In addition, interestingly, when the aluminum oxide was irradiated with Co-60 gamma-rays, an accumulation of negative fixed oxide charge in the oxide was observed.

PDMS spreading morphological patterns on substrates of different hydrophilicity in air vacuum and water.

PubMed

Zbik, Marek S; Frost, Ray L

2010-04-15

In paper has been to investigate the morphological patterns and kinetics of PDMS spreading on silicon wafer using combination of techniques like ellipsometry, atomic force microscope (AFM), scanning electron microscope (SEM) and optical microscopy. A macroscopic silicone oil drops as well as PDMS water based emulsions were studied after deposition on a flat surface of silicon wafer in air, water and vacuum. Our own measurements using an imaging ellipsometer, which also clearly shows the presence of a precursor film. The diffusion constant of this film, measured with a 60,000 cS PDMS sample spreading on a hydrophilic silicon wafer is D(f)=1.4x10(-11) m(2)/s. Regardless of their size, density and method of deposition, droplets on both types of wafer (hydrophilic and hydrophobic) flatten out over a period of many hours, up to 3 days. During this process neighbouring droplets may coalesce, but there is strong evidence that some of the PDMS from the droplets migrates into a thin, continuous film that covers the surface in between droplets. The thin film appears to be ubiquitous if there has been any deposition of PDMS. However, this statement needs further verification. One question is whether the film forms immediately after forced drying, or whether in some or all cases it only forms by spreading from isolated droplets as they slowly flatten out. 2010 Elsevier Inc. All rights reserved.

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2010 CFR

2010-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer... where wastewater undergoes treatment (such as pH adjustment) before discharge, and are not used to...

Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

PubMed

Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

2015-11-01

Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group. Copyright © 2015 Elsevier B.V. All rights reserved.

Anomalous Seebeck coefficient observed in silicon nanowire micro thermoelectric generator

NASA Astrophysics Data System (ADS)

Hashimoto, S.; Asada, S.; Xu, T.; Oba, S.; Himeda, Y.; Yamato, R.; Matsukawa, T.; Matsuki, T.; Watanabe, T.

2017-07-01

We have found experimentally an anomalous thermoelectric characteristic of an n-type Si nanowire micro thermoelectric generator (μTEG). The μTEG is fabricated on a silicon-on-insulator wafer by electron beam lithography and dry etching, and its surface is covered with a thermally grown silicon dioxide film. The observed thermoelectric current is opposite to what is expected from the Seebeck coefficient of n-type Si. The result is understandable by considering a potential barrier in the nanowire. Upon the application of the temperature gradient across the nanowire, the potential barrier impedes the diffusion of thermally activated majority carriers into the nanowire, and it rather stimulates the injection of thermally generated minority carriers. The most plausible origin of the potential barrier is negative charges trapped at the interface between the Si nanowire and the oxide film. We practically confirmed that the normal Seebeck coefficient of the n-type Si nanowire is recovered after the hydrogen forming gas annealing. This implies that the interface traps are diminished by the hydrogen termination of bonding defects. The present results show the importance of the surface inactivation treatment of μTEGs to suppress the potential barrier and unfavorable contribution of minority carriers.

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

PubMed

Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

2008-07-30

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2011 CFR

2011-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer... where wastewater undergoes treatment (such as pH adjustment) before discharge, and are not used to...

Advanced process control and novel test methods for PVD silicon and elastomeric silicone coatings utilized on ion implant disks, heatsinks and selected platens

DOE Office of Scientific and Technical Information (OSTI.GOV)

Springer, J.; Allen, B.; Wriggins, W.

Coatings play multiple key roles in the proper functioning of mature and current ion implanters. Batch and serial implanters require strategic control of elemental and particulate contamination which often includes scrutiny of the silicon surface coatings encountering direct beam contact. Elastomeric Silicone Coatings must accommodate wafer loading and unloading as well as direct backside contact during implant plus must maintain rigid elemental and particulate specifications. The semiconductor industry has had a significant and continuous effort to obtain ultra-pure silicon coatings with sustained process performance and long life. Low particles and reduced elemental levels for silicon coatings are a major requirementmore » for process engineers, OEM manufacturers, and second source suppliers. Relevant data will be presented. Some emphasis and detail will be placed on the structure and characteristics of a relatively new PVD Silicon Coating process that is very dense and homogeneous. Wear rate under typical ion beam test conditions will be discussed. The PVD Silicon Coating that will be presented here is used on disk shields, wafer handling fingers/fences, exclusion zones of heat sinks, beam dumps and other beamline components. Older, legacy implanters can now provide extended process capability using this new generation PVD silicon - even on implanter systems that were shipped long before the advent of silicon coating for contamination control. Low particles and reduced elemental levels are critical performance criteria for the silicone elastomers used on disk heatsinks and serial implanter platens. Novel evaluation techniques and custom engineered tools are used to investigate the surface interaction characteristics of multiple Elastomeric Silicone Coatings currently in use by the industry - specifically, friction and perpendicular stiction. These parameters are presented as methods to investigate the critical wafer load and unload function. Unique tools and test methods have been developed that deliver accurate and repeatable data, which will be described.« less

Atomic force microscopy nanomanipulation of silicon nanocrystals for nanodevice fabrication

NASA Astrophysics Data System (ADS)

Decossas, Sébastien; Mazen, Frédéric; Baron, Thierry; Brémond, Georges; Souifi, Abdelkader

2003-12-01

An atomic force microscopy (AFM) tip has been used to manipulate silicon nanocrystals deposited by low-pressure chemical vapour deposition on thermally oxidized p-type Si wafer. Three nanomanipulation methods are presented. The first one catches a nanocrystal with the AFM tip and deposits it elsewhere: the tip is used as an electrostatic 'nano-crane'. The second one simultaneously manipulates a set of nanocrystals in order to draw well-defined unidimensional lines: the tip is used as a 'nano-broom'. The third one manipulates individual nanocrystals with a precision of about 10 nm using both oscillating and contact AFM modes. Switching from strong interaction forces (chemical) to weak ones (van der Waals, electrostatic or capillarity) is the basis of these manipulation methods. We have applied the second method to connect two electrodes drawn by e-beam and lift-off with a 70 nm long silicon nanocrystal chain. Current versus voltage characterization of the nanofabricated device shows that the increase in nanocrystal density gives rise to conduction between the connected electrodes. Resonant tunnelling effects resulting from Si nanocrystal (nc-Si) multiple tunnel junctions have been observed at 300 K. We also show that offset charges directly influence the position of the resonant tunnelling peaks. Finally, the possibility of manipulating nc-Si with a diameter of around 5 nm is shown to be a promising way to fabricate single electron devices operating at room temperature and fully compatible with silicon technology.

Formation and metrology of dual scale nano-morphology on SF(6) plasma etched silicon surfaces.

PubMed

Boulousis, G; Constantoudis, V; Kokkoris, G; Gogolides, E

2008-06-25

Surface roughness and nano-morphology in SF(6) plasma etched silicon substrates are investigated in a helicon type plasma reactor as a function of etching time and process parameters. The plasma etched surfaces are analyzed by atomic force microscopy. It is found that dual scale nano-roughness is formatted on the silicon surface comprising an underlying nano-roughness and superimposed nano-mounds. Detailed metrological quantification is proposed for the characterization of dual scale surface morphology. As etching proceeds, the mounds become higher, fewer and wider, and the underlying nano-roughness also increases. Increase in wafer temperature leads to smoother surfaces with lower, fewer and wider nano-mounds. A mechanism based on the deposition of etch inhibiting particles during the etching process is proposed for the explanation of the experimental behavior. In addition, appropriately designed experiments are conducted, and they confirm the presence of this mechanism.

Silicon trench photodiodes on a wafer for efficient X-ray-to-current signal conversion using side-X-ray-irradiation mode

NASA Astrophysics Data System (ADS)

Ariyoshi, Tetsuya; Takane, Yuta; Iwasa, Jumpei; Sakamoto, Kenji; Baba, Akiyoshi; Arima, Yutaka

2018-04-01

In this paper, we report a direct-conversion-type X-ray sensor composed of trench-structured silicon photodiodes, which achieves a high X-ray-to-current conversion efficiency under side X-ray irradiation. The silicon X-ray sensor with a length of 22.6 mm and a trench depth of 300 µm was fabricated using a single-poly single-metal 0.35 µm process. X-rays with a tube voltage of 80 kV were irradiated along the trench photodiode from the side of the test chip. The theoretical limit of X-ray-to-current conversion efficiency of 83.8% was achieved at a low reverse bias voltage of 25 V. The X-ray-to-electrical signal conversion efficiency of conventional indirect-conversion-type X-ray sensors is about 10%. Therefore, the developed sensor has a conversion efficiency that is about eight times higher than that of conventional sensors. It is expected that the developed X-ray sensor will be able to markedly lower the radiation dose required for X-ray diagnoses.

Cost-effective method of manufacturing a 3D MEMS optical switch

NASA Astrophysics Data System (ADS)

Carr, Emily; Zhang, Ping; Keebaugh, Doug; Chau, Kelvin

2009-02-01

growth of data and video transport networks. All-optical switching eliminates the need for optical-electrical conversion offering the ability to switch optical signals transparently: independent of data rates, formats and wavelength. It also provides network operators much needed automation capabilities to create, monitor and protect optical light paths. To further accelerate the market penetration, it is necessary to identify a path to reduce the manufacturing cost significantly as well as enhance the overall system performance, uniformity and reliability. Currently, most MEMS optical switches are assembled through die level flip-chip bonding with either epoxies or solder bumps. This is due to the alignment accuracy requirements of the switch assembly, defect matching of individual die, and cost of the individual components. In this paper, a wafer level assembly approach is reported based on silicon fusion bonding which aims to reduce the packaging time, defect count and cost through volume production. This approach is successfully demonstrated by the integration of two 6-inch wafers: a mirror array wafer and a "snap-guard" wafer, which provides a mechanical structure on top of the micromirror to prevent electrostatic snap-down. The direct silicon-to-silicon bond eliminates the CTEmismatch and stress issues caused by non-silicon bonding agents. Results from a completed integrated switch assembly will be presented, which demonstrates the reliability and uniformity of some key parameters of this MEMS optical switch.

Studies of Silicon Nanowires with Different Parameters — By PECVD

NASA Astrophysics Data System (ADS)

Leela, S.; Abirami, T.; Bhattacharya, Sekhar; Ahmed, Nafis; Monika, S.; Priya, R. Nivedha

2016-10-01

One-dimensional nanostructures such as nanowires have a wide range of applications. Silicon is the best competitive material for the carbon nanotubes (CNTs). Carbon and silicon have some similar and peculiar properties. Silicon nanowires (SiNWs) were synthesized using plasma enhanced chemical vapor deposition (PECVD) on p-Si (111) wafer. Gold is used as a catalyst for the growth of the SiNWs. Based on our fundamental understanding of vapor-liquid-solid (VLS) nanowire growth mechanism, different levels of growth controls have been achieved. Gold catalyst deposited and annealed at different temperatures with different thicknesses (450∘C, 500∘C and 550∘C, 600∘C, 650∘C for 4min and 8min and 3nm, 5nm, 30nm Au thickness). SiNW grown by PECVD with different carrier gases varies with flow rate. We observed the different dimensions of Si nanowires by FESEM and optimized the growth parameters to get the vertical aligned and singular Si nanowires. Optical phonon of the Si nanowires and crystallinity nature were identified by Raman spectral studies.

SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution

NASA Astrophysics Data System (ADS)

Voorkamp, R.; Verschuuren, M. A.; van Brakel, R.

2016-10-01

Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 - 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and yield. Soft stamps, usually based on silicone rubber, behave fundamentally different compared to rigid stamps on the macro-, micro- and nanometer level. The main limitation of traditional silicones is that they are too soft to support sub-micron features against surface tension based stamp deformation and collapse [4] and handling a soft stamp to achieve accurate feature placement on wafer scales to allow overlay alignment with sub-100nm overlay accuracy.

32-element beta detector developed at the Institute of Electron Technology (ITE)

NASA Astrophysics Data System (ADS)

Wegrzecki, Maciej; Yakushev, Alexander; Bar, Jan; Budzyński, Tadeusz; Grabiec, Piotr; Kłos, Helena; Panas, Andrzej; Słysz, Wojciech; Stolarski, Maciej; Szmigiel, Dariusz; Wegrzecka, Iwona; Zaborowski, Michał

2014-08-01

The paper presents the design, technology and parameters of a new .silicon detector for detection of electrons (below named as beta detector) developed at the Institute of Electron Technology (ITE). The detector will be used for research on transactinide elements at the GSI Helmholtzzentrum für Schwerionenforschung GmbH, Darmstadt (GSI). The detector consists of a monolithic 32-element array with an active area diameter of 90 mm and a thickness of 0.9 mm. The starting material is a high-resistivity ν silicon wafer (5 kΩcm resistivity). 32 planar p+-ν junctions are formed by boron diffusion on the top side of the wafer. On the bottom side, an n+ region, which forms a common cathode, is formed on the entire surface by phosphorus diffusion. The array is mounted on a special epoxy-glass laminate substrate, copper-clad on both sides. Two model detectors have been fabricated and studied. Very good electrical parameters have been achieved. For the first array, with supply voltage VR = 20 V, the minimum dark current was 8 nA, the maximum dark current 97.1 nA, and the average dark current 25.1 nA. For the second array, it was 11.5 nA, 378.8 nA and 40.0 nA respectively.

The effect of light soaking on crystalline silicon surface passivation by atomic layer deposited Al2O3

NASA Astrophysics Data System (ADS)

Liao, Baochen; Stangl, Rolf; Mueller, Thomas; Lin, Fen; Bhatia, Charanjit S.; Hoex, Bram

2013-01-01

The effect of light soaking of crystalline silicon wafer lifetime samples surface passivated by thermal atomic layer deposited (ALD) Al2O3 is investigated in this paper. Contrary to other passivation materials used in solar cell applications (i.e., SiO2, SiNx), using thermal ALD Al2O3, an increase in effective carrier lifetime after light soaking under standard testing conditions is observed for both p-type (˜45%) and n-type (˜60%) FZ c-Si lifetime samples. After light soaking and storing the samples in a dark and dry environment, the effective lifetime decreases again and practically returns to the value before light soaking. The rate of lifetime decrease after light soaking is significantly slower than the rate of lifetime increase by light soaking. To investigate the underlying mechanism, corona charge experiments are carried out on p-type c-Si samples before and after light soaking. The results indicate that the negative fixed charge density Qf present in the Al2O3 films increases due to the light soaking, which results in an improved field-effect passivation. Numerical calculations also confirm that the improved field-effect passivation is the main contributor for the increased effective lifetime after light soaking. To further understand the light soaking phenomenon, a kinetic model—a charge trapping/de-trapping model—is proposed to explain the time dependent behavior of the lifetime increase/decrease observed under/after light soaking. The trap model fits the experimental results very well. The observed light enhanced passivation for ALD Al2O3 passivated c-Si is of technological relevance, because solar cell devices operate under illumination, thus an increase in solar cell efficiency due to light soaking can be expected.

Impurity gettering in silicon using cavities formed by helium implantation and annealing

DOEpatents

Myers, Jr., Samuel M.; Bishop, Dawn M.; Follstaedt, David M.

1998-01-01

Impurity gettering in silicon wafers is achieved by a new process consisting of helium ion implantation followed by annealing. This treatment creates cavities whose internal surfaces are highly chemically reactive due to the presence of numerous silicon dangling bonds. For two representative transition-metal impurities, copper and nickel, the binding energies at cavities were demonstrated to be larger than the binding energies in precipitates of metal silicide, which constitutes the basis of most current impurity gettering. As a result the residual concentration of such impurities after cavity gettering is smaller by several orders of magnitude than after precipitation gettering. Additionally, cavity gettering is effective regardless of the starting impurity concentration in the wafer, whereas precipitation gettering ceases when the impurity concentration reaches a characteristic solubility determined by the equilibrium phase diagram of the silicon-metal system. The strong cavity gettering was shown to induce dissolution of metal-silicide particles from the opposite side of a wafer.

Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy

NASA Astrophysics Data System (ADS)

Altan, Hakan

All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on transmission and mobility are quantitatively discussed.

Stereoregular polyacrylamide and its copolymer brushes: Preparation and surface characters

NASA Astrophysics Data System (ADS)

Jiang, Jianguo; Wang, Xiaoshu; Lu, Xiaoyan; Lu, Yun

2008-12-01

Two kinds of polymer brushes, the single one with stereospecific polyacrylamide (PAAM) chains and the dual-component one with random poly(methyl methacrylate) (PMMA) segments grafting from stereospecific PAAM chains, were prepared on silicon wafer for the first time by combining the immobilization of initiator and the stereospecific living radical in situ polymerization. With the addition of the Lewis acid AlCl 3 into the polymerization system, the PAAM brushes obtained exhibited an increased stereospecificity as well as a decreased hydrophilicity, which might attribute to the reduced thickness of PAAM brushes on the silicon wafer and the handicap of the free rotation of the stereospecific molecular chain. The smoother surface morphology of the stereospecific PAAM brushes shown in AFM images was in good agreement with the experimental data of water contact angle. Also, block amphiphilic copolymer brushes were prepared with the stereospecific PAAM formed first on silicon wafer as the anchored-initiator and revealed a novel surface self-assembly behavior after being treated with different solvent such as toluene or water. The stereospecificity of PAAM chains in the polymer brushes could be modulated by adjusting reaction conditions according to the requirement of applications for surface hydrophilicity.

Influence of the doping type and level on the morphology of porous Si formed by galvanic etching

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pyatilova, O. V., E-mail: 5ilova87@gmail.com; Gavrilov, S. A.; Shilyaeva, Yu. I.

The formation of porous silicon (por-Si) layers by the galvanic etching of single-crystal Si samples (doped with boron or phosphorus) in an HF/C{sub 2}H{sub 5}OH/H{sub 2}O{sub 2} solution is investigated. The por-Si layers are analyzed by the capillary condensation of nitrogen and scanning electron microscopy (SEM). The dependences of the morphological characteristics of por-Si (pore diameter, specific surface area, pore volume, and thickness of the pore walls), which determine the por-Si combustion kinetics, on the dopant type and initial wafer resistivity are established.

Wet-chemical systems and methods for producing black silicon substrates

DOEpatents

Yost, Vernon; Yuan, Hao-Chih; Page, Matthew

2015-05-19

A wet-chemical method of producing a black silicon substrate. The method comprising soaking single crystalline silicon wafers in a predetermined volume of a diluted inorganic compound solution. The substrate is combined with an etchant solution that forms a uniform noble metal nanoparticle induced Black Etch of the silicon wafer, resulting in a nanoparticle that is kinetically stabilized. The method comprising combining with an etchant solution having equal volumes acetonitrile/acetic acid:hydrofluoric acid:hydrogen peroxide.

A repeatable and scalable fabrication method for sharp, hollow silicon microneedles

NASA Astrophysics Data System (ADS)

Kim, H.; Theogarajan, L. S.; Pennathur, S.

2018-03-01

Scalability and manufacturability are impeding the mass commercialization of microneedles in the medical field. Specifically, microneedle geometries need to be sharp, beveled, and completely controllable, difficult to achieve with microelectromechanical fabrication techniques. In this work, we performed a parametric study using silicon etch chemistries to optimize the fabrication of scalable and manufacturable beveled silicon hollow microneedles. We theoretically verified our parametric results with diffusion reaction equations and created a design guideline for a various set of miconeedles (80-160 µm needle base width, 100-1000 µm pitch, 40-50 µm inner bore diameter, and 150-350 µm height) to show the repeatability, scalability, and manufacturability of our process. As a result, hollow silicon microneedles with any dimensions can be fabricated with less than 2% non-uniformity across a wafer and 5% deviation between different processes. The key to achieving such high uniformity and consistency is a non-agitated HF-HNO3 bath, silicon nitride masks, and surrounding silicon filler materials with well-defined dimensions. Our proposed method is non-labor intensive, well defined by theory, and straightforward for wafer scale mass production, opening doors to a plethora of potential medical and biosensing applications.

Study of thickness and uniformity of oxide passivation with DI-O3 on silicon substrate for electronic and photonic applications

NASA Astrophysics Data System (ADS)

Sharma, Mamta; Hazra, Purnima; Singh, Satyendra Kumar

2018-05-01

Since the beginning of semiconductor fabrication technology evolution, clean and passivated substrate surface is one of the prime requirements for fabrication of Electronic and optoelectronic device fabrication. However, as the scale of silicon circuits and device architectures are continuously decreased from micrometer to nanometer (from VLSI to ULSI technology), the cleaning methods to achieve better wafer surface qualities has raised research interests. The development of controlled and uniform silicon dioxide is the most effective and reliable way to achieve better wafer surface quality for fabrication of electronic devices. On the other hand, in order to meet the requirement of high environment safety/regulatory standards, the innovation of cleaning technology is also in demand. The controlled silicon dioxide layer formed by oxidant de-ionized ozonated water has better uniformity. As the uniformity of the controlled silicon dioxide layer is improved on the substrate, it enhances the performance of the devices. We can increase the thickness of oxide layer, by increasing the ozone time treatment. We reported first time to measurement of thickness of controlled silicon dioxide layer and obtained the uniform layer for same ozone time.

Nano-Multiplication-Region Avalanche Photodiodes and Arrays

NASA Technical Reports Server (NTRS)

Zheng, Xinyu; Pain, Bedabrata; Cunningham, Thomas

2008-01-01

Nano-multiplication-region avalanche photodiodes (NAPDs), and imaging arrays of NAPDs integrated with complementary metal oxide/semiconductor (CMOS) active-pixel-sensor integrated circuitry, are being developed for applications in which there are requirements for high-sensitivity (including photoncounting) detection and imaging at wavelengths from about 250 to 950 nm. With respect to sensitivity and to such other characteristics as speed, geometric array format, radiation hardness, power demand of associated circuitry, size, weight, and robustness, NAPDs and arrays thereof are expected to be superior to prior photodetectors and arrays including CMOS active-pixel sensors (APSs), charge-coupled devices (CCDs), traditional APDs, and microchannelplate/ CCD combinations. Figure 1 depicts a conceptual NAPD array, integrated with APS circuitry, fabricated on a thick silicon-on-insulator wafer (SOI). Figure 2 presents selected aspects of the structure of a typical single pixel, which would include a metal oxide/semiconductor field-effect transistor (MOSFET) integrated with the NAPD. The NAPDs would reside in silicon islands formed on the buried oxide (BOX) layer of the SOI wafer. The silicon islands would be surrounded by oxide-filled insulation trenches, which, together with the BOX layer, would constitute an oxide embedding structure. There would be two kinds of silicon islands: NAPD islands for the NAPDs and MOSFET islands for in-pixel and global CMOS circuits. Typically, the silicon islands would be made between 5 and 10 m thick, but, if necessary, the thickness could be chosen outside this range. The side walls of the silicon islands would be heavily doped with electron-acceptor impurities (p+-doped) to form anodes for the photodiodes and guard layers for the MOSFETs. A nanoscale reach-through structure at the front (top in the figures) central position of each NAPD island would contain the APD multiplication region. Typically, the reach-through structure would be about 0.1 microns in diameter and between 0.3 and 0.4 nm high. The top layer in the reach-through structure would be heavily doped with electron-donor impurities (n+-doped) to make it act as a cathode. A layer beneath the cathode, between 0.1 and 0.2 nm thick, would be p-doped to a concentration .10(exp 17)cu cm. A thin n+-doped polysilicon pad would be formed on the top of the cathode to protect the cathode against erosion during a metal-silicon alloying step that would be part of the process of fabricating the array.

Advanced process control and novel test methods for PVD silicon and elastomeric silicone coatings utilized on ion implant disks, heatsinks and selected platens

NASA Astrophysics Data System (ADS)

Springer, J.; Allen, B.; Wriggins, W.; Kuzbyt, R.; Sinclair, R.

2012-11-01

Coatings play multiple key roles in the proper functioning of mature and current ion implanters. Batch and serial implanters require strategic control of elemental and particulate contamination which often includes scrutiny of the silicon surface coatings encountering direct beam contact. Elastomeric Silicone Coatings must accommodate wafer loading and unloading as well as direct backside contact during implant plus must maintain rigid elemental and particulate specifications. The semiconductor industry has had a significant and continuous effort to obtain ultra-pure silicon coatings with sustained process performance and long life. Low particles and reduced elemental levels for silicon coatings are a major requirement for process engineers, OEM manufacturers, and second source suppliers. Relevant data will be presented. Some emphasis and detail will be placed on the structure and characteristics of a relatively new PVD Silicon Coating process that is very dense and homogeneous. Wear rate under typical ion beam test conditions will be discussed. The PVD Silicon Coating that will be presented here is used on disk shields, wafer handling fingers/fences, exclusion zones of heat sinks, beam dumps and other beamline components. Older, legacy implanters can now provide extended process capability using this new generation PVD silicon - even on implanter systems that were shipped long before the advent of silicon coating for contamination control. Low particles and reduced elemental levels are critical performance criteria for the silicone elastomers used on disk heatsinks and serial implanter platens. Novel evaluation techniques and custom engineered tools are used to investigate the surface interaction characteristics of multiple Elastomeric Silicone Coatings currently in use by the industry - specifically, friction and perpendicular stiction. These parameters are presented as methods to investigate the critical wafer load and unload function. Unique tools and test methods have been developed that deliver accurate and repeatable data, which will be described.

3D interconnect metrology in CMS/ITRI

NASA Astrophysics Data System (ADS)

Ku, Y. S.; Shyu, D. M.; Hsu, W. T.; Chang, P. Y.; Chen, Y. C.; Pang, H. L.

2011-05-01

Semiconductor device packaging technology is rapidly advancing, in response to the demand for thinner and smaller electronic devices. Three-dimensional chip/wafer stacking that uses through-silicon vias (TSV) is a key technical focus area, and the continuous development of this novel technology has created a need for non-contact characterization. Many of these challenges are novel to the industry due to the relatively large variety of via sizes and density, and new processes such as wafer thinning and stacked wafer bonding. This paper summarizes the developing metrology that has been used during via-middle & via-last TSV process development at EOL/ITRI. While there is a variety of metrology and inspection applications for 3D interconnect processing, the main topics covered here are via CD/depth measurement, thinned wafer inspection and wafer warpage measurement.

Impurity gettering in silicon using cavities formed by helium implantation and annealing

DOEpatents

Myers, S.M. Jr.; Bishop, D.M.; Follstaedt, D.M.

1998-11-24

Impurity gettering in silicon wafers is achieved by a new process consisting of helium ion implantation followed by annealing. This treatment creates cavities whose internal surfaces are highly chemically reactive due to the presence of numerous silicon dangling bonds. For two representative transition-metal impurities, copper and nickel, the binding energies at cavities were demonstrated to be larger than the binding energies in precipitates of metal silicide, which constitutes the basis of most current impurity gettering. As a result the residual concentration of such impurities after cavity gettering is smaller by several orders of magnitude than after precipitation gettering. Additionally, cavity gettering is effective regardless of the starting impurity concentration in the wafer, whereas precipitation gettering ceases when the impurity concentration reaches a characteristic solubility determined by the equilibrium phase diagram of the silicon-metal system. The strong cavity gettering was shown to induce dissolution of metal-silicide particles from the opposite side of a wafer. 4 figs.

Slicing of silicon into sheet material: Silicon sheet growth development for the large area silicon sheet task of the Low Cost Silicon Solar Array project

NASA Technical Reports Server (NTRS)

Fleming, J. R.

1978-01-01

The limits of blade tolerance were defined. The standard blades are T-2 thickness tolerance. Good results were obtained by using a slurry fluid consisting of mineral oil and a lubricity additive. Adjustments of the formulation and fine tuning of the cutting process with the new fluid are necessary. Test results and consultation indicate that the blade breakage encountered with water based slurries is unavoidable. Two full capacity (974 wafer) runs were made on the large prototype saw. Both runs resulted in extremely low yield. However, the reasons for the low yield were lack of proper technique rather than problems with machine function. The test on the effect of amount of material etched off of an as-sawn wafer on solar cell efficiency were completed. The results agree with previous work at JPL in that the minimum material removed per side that gives maximum efficiency is on the order of 10 microns.

Photovoltaic Device Including A Boron Doping Profile In An I-Type Layer

DOEpatents

Yang, Liyou

1993-10-26

A photovoltaic cell for use in a single junction or multijunction photovoltaic device, which includes a p-type layer of a semiconductor compound including silicon, an i-type layer of an amorphous semiconductor compound including silicon, and an n-type layer of a semiconductor compound including silicon formed on the i-type layer. The i-type layer including an undoped first sublayer formed on the p-type layer, and a boron-doped second sublayer formed on the first sublayer.

Boron Doped Nanocrystalline Film with Improved Work Function as a Buffer Layer in Thin Film Silicon Solar Cells.

PubMed

Park, Jinjoo; Shin, Chonghoon; Park, Hyeongsik; Jung, Junhee; Lee, Youn-Jung; Bong, Sungjae; Dao, Vinh Ai; Balaji, Nagarajan; Yi, Junsin

2015-03-01

We investigated thin film silicon solar cells with boron doped hydrogenated nanocrystalline silicon/ hydrogenated amorphous silicon oxide [p-type nc-Si:H/a-SiOx:H] layer. First, we researched the bandgap engineering of diborane (B2H6) doped wide bandgap hydrogenated nanocryslline silicon (p-type nc-Si:H) films, which have excellent electrical properties of high dark conductivity, and low activation energy. The films prepared with lower doping ratio and higher hydrogen dilution ratio had higher optical gap (Eg), with higher dark conductivity (σ(d)), and lower activation energy (Ea). We controlled Eg from 2.10 eV to 1.75 eV, with σ(d) from 1.1 S/cm to 7.59 x 10(-3) S/cm, and Ea from 0.040 eV to 0.128 eV. Next, we focused on the fabrication of thin film silicon solar cells. By inserting p-type nc-Si:H film into the thin film silicon solar cells, we achieved a remarkable increase in the built-in potential from 0.803 eV to 0.901 eV. By forming p-type nc-Si:H film between SnO2:F/ZnO:Al (30 nm) and p-type a-SiOx:H layer, the solar cell properties of open circuit voltage (Voc), short circuit current density (Jsc), and efficiency (η) were improved by 3.7%, 9.2%, and 9.8%, respectively.

Graphene-Si heterogeneous nanotechnology

NASA Astrophysics Data System (ADS)

Akinwande, Deji; Tao, Li

2013-05-01

It is widely envisioned that graphene, an atomic sheet of carbon that has generated very broad interest has the largest prospects for flexible smart systems and for integrated graphene-silicon (G-Si) heterogeneous very large-scale integrated (VLSI) nanoelectronics. In this work, we focus on the latter and elucidate the research progress that has been achieved for integration of graphene with Si-CMOS including: wafer-scale graphene growth by chemical vapor deposition on Cu/SiO2/Si substrates, wafer-scale graphene transfer that afforded the fabrication of over 10,000 devices, wafer-scalable mitigation strategies to restore graphene's device characteristics via fluoropolymer interaction, and demonstrations of graphene integrated with commercial Si- CMOS chips for hybrid nanoelectronics and sensors. Metrology at the wafer-scale has led to the development of custom Raman processing software (GRISP) now available on the nanohub portal. The metrology reveals that graphene grown on 4-in substrates have monolayer quality comparable to exfoliated flakes. At room temperature, the high-performance passivated graphene devices on SiO2/Si can afford average mobilities 3000cm2/V-s and gate modulation that exceeds an order of magnitude. The latest growth research has yielded graphene with high mobilities greater than 10,000cm2/V-s on oxidized silicon. Further progress requires track compatible graphene-Si integration via wafer bonding in order to translate graphene research from basic to applied research in commercial R and D laboratories to ultimately yield a viable nanotechnology.

Electrochemically deposited cobalt/platinum (Co/Pt) film into porous silicon: Structural investigation and magnetic properties

NASA Astrophysics Data System (ADS)

Harraz, F. A.; Salem, A. M.; Mohamed, B. A.; Kandil, A.; Ibrahim, I. A.

2013-01-01

A nanostructured CoPt magnetic film was deposited from a single electrolyte into porous silicon layer by an electrochemical technique, followed by annealing at 600 °C in Ar atmosphere during which the CoPt alloy was converted to L10 ordered phase. Porous silicon with pore diameter between 5 and 100 nm was firstly fabricated by galvanostatic anodization of n-type silicon wafer in the presence of CrO3 as oxidizing agent and ethanol or sodium lauryl sulfate as surfactants. The role of the surfactant on the produced pore size and morphology was investigated by means of UV-vis spectra. As-formed porous silicon was consequently used as a template for the electrodeposition of magnetic CoPt film. The phase formation, microstructure and the magnetic properties were fully analyzed by XRD, FE-SEM, EDS and VSM measurements. It was found that, upon annealing the coercivity was significantly increased due to the transformation to the L10 ordered structure. The saturation magnetization and remanence ratio were also found to increase, indicating no loss of Co content or oxidation reaction after the annealing. Results of synthesis and characterization of CoPt/porous silicon nanocomposite are addressed and thoroughly discussed.

Highly nonlinear sub-micron silicon nitride trench waveguide coated with gold nanoparticles

NASA Astrophysics Data System (ADS)

Huang, Yuewang; Zhao, Qiancheng; Sharac, Nicholas; Ragan, Regina; Boyraz, Ozdal

2015-05-01

We demonstrate the fabrication of a highly nonlinear sub-micron silicon nitride trench waveguide coated with gold nanoparticles for plasmonic enhancement. The average enhancement effect is evaluated by measuring the spectral broadening effect caused by self-phase-modulation. The nonlinear refractive index n2 was measured to be 7.0917×10-19 m2/W for a waveguide whose Wopen is 5 μm. Several waveguides at different locations on one wafer were measured in order to take the randomness of the nanoparticle distribution into consideration. The largest enhancement is measured to be as high as 10 times. Fabrication of this waveguide started with a MEMS grade photomask. By using conventional optical lithography, the wide linewidth was transferred to a <100> wafer. Then the wafer was etched anisotropically by potassium hydroxide (KOH) to engrave trapezoidal trenches with an angle of 54.7º. Side wall roughness was mitigated by KOH etching and thermal oxidation that was used to generate a buffer layer for silicon nitride waveguide. The guiding material silicon nitride was then deposited by low pressure chemical vapor deposition. The waveguide was then patterned with a chemical template, with 20 nm gold particles being chemically attached to the functionalized poly(methyl methacrylate) domains. Since the particles attached only to the PMMA domains, they were confined to localized regions, therefore forcing the nanoparticles into clusters of various numbers and geometries. Experiments reveal that the waveguide has negligible nonlinear absorption loss, and its nonlinear refractive index can be greatly enhanced by gold nano clusters. The silicon nitride trench waveguide has large nonlinear refractive index, rendering itself promising for nonlinear applications.

Advances in Sensors and Their Integration into Aircraft Guidance and Control Systems,

DTIC Science & Technology

1983-06-01

this function taking account of the limitations of the existing air- craft systems such as:- (a) Cockpit space (b) use of existing controls particularly...electrostatically focused under the influence of high potentials to form an electron image on a thin silicon wafer target upon which a very tightly spaced ...matrix of p-n junctions have been formed. The spacing of the diodes is of the order of n m. A gain mechanism is caused because the photo electrons

Using the surface charge profiler for in-line monitoring of doping concentration in silicon epitaxial wafer manufacturing

NASA Astrophysics Data System (ADS)

Tower, Joshua P.; Kamieniecki, Emil; Nguyen, M. C.; Danel, Adrien

1999-08-01

The Surface Charge Profiler (SCP) has been introduced for monitoring and development of silicon epitaxial processes. The SCP measures the near-surface doping concentration and offers advantages that lead to yield enhancement in several ways. First, non-destructive measurement technology enables in-line process monitoring, eliminating the need to sacrifice production wafers for resistivity measurements. Additionally, the full-wafer mapping capability helps in development of improved epitaxial growth processes and early detection of reactor problems. As examples, we present the use of SCP to study the effects of susceptor degradation in barrel reactors and to study autodoping for development of improved dopant uniformity.

Heterogeneous microring and Mach-Zehnder modulators based on lithium niobate and chalcogenide glasses on silicon

DOE PAGES

Rao, Ashutosh; Patil, Aniket; Chiles, Jeff; ...

2015-08-20

In this study, thin films of lithium niobate are wafer bonded onto silicon substrates and rib-loaded with a chalcogenide glass, Ge 23Sb 7S 70, to demonstrate strongly confined single-mode submicron waveguides, microring modulators, and Mach-Zehnder modulators in the telecom C band. The 200 μm radii microring modulators present 1.2 dB/cm waveguide propagation loss, 1.2 × 10 5 quality factor, 0.4 GHz/V tuning rate, and 13 dB extinction ratio. The 6 mm long Mach-Zehnder modulators have a half-wave voltage-length product of 3.8 V.cm and an extinction ratio of 15 dB. The demonstrated work is a key step towards enabling wafer scalemore » dense on-chip integration of high performance lithium niobate electro-optical devices on silicon for short reach optical interconnects and higher order advanced modulation schemes.« less

Formation of copper precipitates in silicon

NASA Astrophysics Data System (ADS)

Flink, Christoph; Feick, Henning; McHugo, Scott A.; Mohammed, Amna; Seifert, Winfried; Hieslmair, Henry; Heiser, Thomas; Istratov, Andrei A.; Weber, Eicke R.

1999-12-01

The formation of copper precipitates in silicon was studied after high-temperature intentional contamination of p- and n-type FZ and Cz-grown silicon and quench to room temperature. With the Transient Ion Drift (TID) technique on p-type silicon a critical Fermi level position at EC-0.2 eV was found. Only if the Fermi level position, which is determined by the concentrations of the acceptors and the copper donors, surpasses this critical value precipitation takes place. If the Fermi level is below this level the supersaturated interstitial copper diffuses out. An electrostatic precipitation model is introduced that correlates the observed precipitation behavior with the electrical activity of the copper precipitates as detected with Deep Level Transient Spectroscopy (DLTS) on n-type and with Minority Carrier Transient Spectroscopy (MCTS) on p-type silicon.

Rotationally Commensurate Growth of MoS2 on Epitaxial Graphene

DTIC Science & Technology

2015-11-13

at the monolayer MoS2 edges. KEYWORDS: transition metal dichalcogenide, silicon carbide , scanning tunneling microscopy, synchrotron X-ray scattering... silicon from SiC not only offers uniform large-area synthesis of graphene but also provides technological advantages over alternative methods such as...Röhrl, J.; et al. Towards Wafer-Size Graphene Layers by Atmospheric Pressure Graphitization of Silicon Carbide . Nat. Mater. 2009, 8, 203−207. (18) Çelebi

First results of a novel Silicon Drift Detector array designed for low energy X-ray fluorescence spectroscopy

NASA Astrophysics Data System (ADS)

Rachevski, Alexandre; Ahangarianabhari, Mahdi; Bellutti, Pierluigi; Bertuccio, Giuseppe; Brigo, Elena; Bufon, Jernej; Carrato, Sergio; Castoldi, Andrea; Cautero, Giuseppe; Fabiani, Sergio; Giacomini, Gabriele; Gianoncelli, Alessandra; Giuressi, Dario; Guazzoni, Chiara; Kourousias, George; Liu, Chang; Menk, Ralf Hendrik; Montemurro, Giuseppe Vito; Picciotto, Antonino; Piemonte, Claudio; Rashevskaya, Irina; Shi, Yongbiao; Stolfa, Andrea; Vacchi, Andrea; Zampa, Gianluigi; Zampa, Nicola; Zorzi, Nicola

2016-07-01

We developed a trapezoidal shaped matrix with 8 cells of Silicon Drift Detectors (SDD) featuring a very low leakage current (below 180 pA/cm2 at 20 °C) and a shallow uniformly implanted p+ entrance window that enables sensitivity down to few hundreds of eV. The matrix consists of a completely depleted volume of silicon wafer subdivided into 4 square cells and 4 half-size triangular cells. The energy resolution of a single square cell, readout by the ultra-low noise SIRIO charge sensitive preamplifier, is 158 eV FWHM at 5.9 keV and 0 °C. The total sensitive area of the matrix is 231 mm2 and the wafer thickness is 450 μm. The detector was developed in the frame of the INFN R&D project ReDSoX in collaboration with FBK, Trento. Its trapezoidal shape was chosen in order to optimize the detection geometry for the experimental requirements of low energy X-ray fluorescence (LEXRF) spectroscopy, aiming at achieving a large detection angle. We plan to exploit the complete detector at the TwinMic spectromicroscopy beamline at the Elettra Synchrotron (Trieste, Italy). The complete system, composed of 4 matrices, increases the solid angle coverage of the isotropic photoemission hemisphere about 4 times over the present detector configuration. We report on the layout of the SDD matrix and of the experimental set-up, as well as the spectroscopic performance measured both in the laboratory and at the experimental beamline.

Silicon on insulator self-aligned transistors

DOEpatents

McCarthy, Anthony M.

2003-11-18

A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

Polarized Optical Scattering Measurements of Metallic Nanoparticles on a Thin Film Silicon Wafer

NASA Astrophysics Data System (ADS)

Liu, Cheng-Yang; Liu, Tze-An; Fu, Wei-En

2009-09-01

Light scattering has shown its powerful diagnostic capability to characterize optical quality surfaces. In this study, the theory of bidirectional reflectance distribution function (BRDF) was used to analyze the metallic nanoparticles' sizes on wafer surfaces. The BRDF of a surface is defined as the angular distribution of radiance scattered by the surface normalized by the irradiance incident on the surface. A goniometric optical scatter instrument has been developed to perform the BRDF measurements on polarized light scattering on wafer surfaces for the diameter and distribution measurements of metallic nanoparticles. The designed optical scatter instrument is capable of distinguishing various types of optical scattering characteristics, which are corresponding to the diameters of the metallic nanoparticles, near surfaces by using the Mueller matrix calculation. The metallic nanoparticle diameter of measurement is 60 nm on 2 inch thin film wafers. These measurement results demonstrate that the polarization of light scattered by metallic particles can be used to determine the size of metallic nanoparticles on silicon wafers.

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

NASA Astrophysics Data System (ADS)

Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

2017-06-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

Recent Results on Gridpix Detectors:. AN Integrated Micromegas Grid and a Micromegas Ageing Test

NASA Astrophysics Data System (ADS)

Chefdeville, M.; Aarts, A.; van der Graaf, H.; van der Putten, S.

2006-04-01

A new gas-filled detector combining a Micromegas with a CMOS pixel chip has been recently tested. A procedure to integrate the Micromegas grid onto silicon wafers (‘wafer post processing’) has been developed. We aim to eventually integrate the grid on top of wafers of CMOS pixel chips. The first part of this contribution describes an application in vertex detection (GOSSIP). Then tests of the first detector prototype of a grid integrated on a bare silicon wafer are shown. Finally an ageing test of a Micromegas chamber is presented. After verifying the chambers' proportionality at a very high dose rates, the device was irradiated until ageing became apparent.

Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

NASA Astrophysics Data System (ADS)

Sun, Q. M.; Melnikov, A.; Mandelis, A.

2015-06-01

Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

A thermal microprobe fabricated with wafer-stage processing

NASA Astrophysics Data System (ADS)

Zhang, Yongxia; Zhang, Yanwei; Blaser, Juliana; Sriram, T. S.; Enver, Ahsan; Marcus, R. B.

1998-05-01

A thermal microprobe has been designed and built for high resolution temperature sensing. The thermal sensor is a thin-film thermocouple junction at the tip of an atomic force microprobe (AFM) silicon probe needle. Only wafer-stage processing steps are used for the fabrication. For high resolution temperature sensing it is essential that the junction be confined to a short distance at the AFM tip. This confinement is achieved by a controlled photoresist coating process. Experiment prototypes have been made with an Au/Pd junction confined to within 0.5 μm of the tip, with the two metals separated elsewhere by a thin insulating oxide layer. Processing begins with double-polished, n-type, 4 in. diameter, 300-μm-thick silicon wafers. Atomically sharp probe tips are formed by a combination of dry and wet chemical etching, and oxidation sharpening. The metal layers are sputtering deposited and the cantilevers are released by a combination of KOH and dry etching. A resistively heated calibration device was made for temperature calibration of the thermal microprobe over the temperature range 25-110 °C. Over this range the thermal outputs of two microprobes are 4.5 and 5.6 μV/K and is linear. Thermal and topographical images are also obtained from a heated tungsten thin film fuse.

Atmospheric-pressure plasma jet system for silicon etching without fluorocarbon gas feed

NASA Astrophysics Data System (ADS)

Ohtsu, Yasunori; Nagamatsu, Kenta

2018-01-01

We developed an atmospheric-pressure plasma jet (APPJ) system with a tungsten rod electrode coated with C2F4 particles of approximately 0.3 µm diameter for the surface treatment of a silicon wafer. The APPJ was generated by dielectric barrier discharge with a driving frequency of 22 kHz using a He gas flow. The characteristics of the APPJ were examined under various experimental conditions. The plasma jet length increased proportionally to the electric field. It was found that the treatment area of the silicon wafer was approximately 1 mm in diameter. By atomic force microscopy analysis, minute irregularities with a maximum length of about 600 nm and part of a ring-shaped trench were observed. A Si etching rate of approximately 400 nm/min was attained at a low power of 6 W and a He flow rate of 1 L/min without introducing molecular gas including F atoms.

Nonlinear conductivity in silicon nitride

NASA Astrophysics Data System (ADS)

Tuncer, Enis

2017-08-01

To better comprehend electrical silicon-package interaction in high voltage applications requires full characterization of the electrical properties of dielectric materials employed in wafer and package level design. Not only the packaging but wafer level dielectrics, i.e. passivation layers, would experience high electric fields generated by the voltage applied pads. In addition the interface between the passivation layer and a mold compound might develop space charge because of the mismatch in electrical properties of the materials. In this contribution electrical properties of a thin silicon nitride (Si3N4) dielectric is reported as a function of temperature and electric field. The measured values later analyzed using different temperature dependent exponential expressions and found that the Mott variable range hopping conduction model was successful to express the data. A full temperature/electric field dependency of conductivity is generated. It was found that the conduction in Si3N4 could be expressed like a field ionization or Fowler-Nordheim mechanism.

Reducing the Cost of Solar Cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scanlon, B.

2012-04-01

Solar-powered electricity prices could soon approach those of power from coal or natural gas thanks to collaborative research with solar startup Ampulse Corporation at the National Renewable Energy Laboratory. Silicon wafers account for almost half the cost of today's solar photovoltaic panels, so reducing or eliminating wafer costs is essential to bringing prices down. Current crystalline silicon technology converts energy in a highly efficient manner; however, that technology is manufactured with processes that could stand some improvement. The industry needs a method that is less complex, creates less waste and uses less energy. First, half the refined silicon is lostmore » as dust in the wafer-sawing process, driving module costs higher. Wafers are sawn off of large cylindrical ingots, or boules, of silicon. A typical 2-meter boule loses as many as 6,000 potential wafers during sawing. Second, the wafers produced are much thicker than necessary. To efficiently convert sunlight into electricity, the wafers need be only one-tenth the typical thickness. NREL, the Oak Ridge National Laboratory and Ampulse have partnered on an approach to eliminate this waste and dramatically lower the cost of the finished solar panels. By using a chemical vapor deposition process to grow the silicon on inexpensive foil, Ampulse is able to make the solar cells just thick enough to convert most of the solar energy into electricity. No more sawdust - and no more wasting refined silicon materials. NREL developed the technology to grow high-quality silicon and ORNL developed the metal foil that has the correct crystal structure to support that growth. Ampulse is installing a pilot manufacturing line in NREL's Process Development Integration Laboratory, where solar companies can work closely with lab scientists on integrated equipment to answer pressing questions related to their technology development, as well as rapidly overcoming R and D challenges and risk. NREL's program is focused on transformative innovation in the domestic PV industry. With knowledge and expertise acquired from the PDIL pilot production line tools, Ampulse plans to design a full-scale production line to accommodate long rolls of metal foil. The Ampulse process 'goes straight from pure silicon-containing gas to high-quality crystal silicon film,' said Brent Nelson, the operational manager for the Process Development Integration Laboratory. 'The advantage is you can make the wafer just as thin as you need it - 10 microns or less.' Most of today's solar cells are made out of wafer crystalline silicon, though thin-film cells made of more exotic elements such as copper, indium, gallium, arsenic, cadmium, tellurium and others are making a strong push into the market. The advantage of silicon is its abundance, because it is derived from sand. Silicon's disadvantage is that purifying it into wafers suitable for solar cells can be expensive and energy intensive. Manufacturers add carbon and heat to sand to produce metallurgical-grade silicon, which is useful in other industries, but not yet suitable for making solar cells. So this metallurgical-grade silicon is then converted to pure trichlorosilane (SiCl3) or silane (SiH4) gas. Typically, the purified gas is then converted to create a silicon feedstock at 1,000 degrees Celsius. This feedstock is melted at 1,414 C and recrystallized into crystal ingots that are finally sawed into wafers. The Ampulse method differs in that it eliminates the last two steps in the traditional process and works directly with the silane gas growing only the needed silicon right onto a foil substrate. A team of NREL scientists had developed a way to use a process called hot-wire chemical vapor deposition to thicken silicon wafers with near perfect crystal structure. Using a hot tungsten filament much like the one found in an incandescent light bulb, the silane gas molecules are broken apart and deposited onto the wafer using the chemical vapor deposition technique at about 700 C - a much lower temperature than needed to make the wafer. The hot filament decomposes the gas, allowing silicon layers to deposit directly onto the substrate. Armed with this new technique, Branz and Teplin searched for ways to grow the silicon on cheaper materials and still use it for solar cells. They found the ideal synergy when visiting venture capitalists from Battelle Ventures asked them whether they could do anything useful with a breakthrough from Oak Ridge's superconducting wire development group. The new development, called the rolling assisted biaxially textured substrate (RABiTS), was just the opportunity the two scientists had been seeking. If metal foil is to work as a substrate, it must be able to act as a seed crystal so the silicon can grow on it with the correct structure. The RABiTS process forms crystals in the foil that are correctly oriented to receive the silicon atoms and lock them into just the right positions.« less

Hybrid Integrated Platforms for Silicon Photonics

PubMed Central

Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

2010-01-01

A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

Studies of SERS efficiency of gold coated porous silicon formed on rough silicon backside

NASA Astrophysics Data System (ADS)

Dridi, H.; Haji, L.; Moadhen, A.

2017-12-01

Starting from a rough backside of silicon wafer, we have formed a porous layer by electrochemical anodization and then coated by a thin film of gold. The morphological characteristics of the porous silicon and in turn the metal film are governed by the anodization process and also by the starting surface. So, in order to investigate the Plasmonic aspect of such rough surface which combines roughness inherent to the porous nature and that due to rough starting surface, we have used a dye target molecule to study its SERS signal using a porous silicon layer obtained on the rough backside surface. The use of unusual backside of silicon wafer could be, beside the others, an interesting way to made SERS effective substrate thanks to reproducible rough porous gold on porous layer from this starting face. The morphological results correspond to the silicon rough surface as a function of the crystallographic orientation showed the presence of two different substrate structure. The optical reflectivity results obtained of gold deposited on oxidized porous silicon showed a dependence of its Localized Surface Plasmon band frequency of the deposit time. SERS results, obtained for a dye target molecule (Rhodamine 6G), show a higher intensities in the case of the 〈110〉 orientation, which characterized by the higher roughness surface. Voici "the most relevant and important aspects of our work".

Influence of the doping level on the porosity of silicon nanowires prepared by metal-assisted chemical etching

NASA Astrophysics Data System (ADS)

Geyer, Nadine; Wollschläger, Nicole; Fuhrmann, Bodo; Tonkikh, Alexander; Berger, Andreas; Werner, Peter; Jungmann, Marco; Krause-Rehberg, Reinhard; Leipner, Hartmut S.

2015-06-01

A systematic method to control the porosity of silicon nanowires is presented. This method is based on metal-assisted chemical etching (MACE) and takes advantage of an HF/H2O2 etching solution and a silver catalyst in the form of a thin patterned film deposited on a doped silicon wafer. It is found that the porosity of the etched nanowires can be controlled by the doping level of the wafer. For low doping concentrations, the wires are primarily crystalline and surrounded by only a very thin layer of porous silicon (pSi) layer, while for highly doped silicon, they are porous in their entire volume. We performed a series of controlled experiments to conclude that there exists a well-defined critical doping concentration separating the crystalline and porous regimes. Furthermore, transmission electron microscopy investigations showed that the pSi has also a crystalline morphology on a length scale smaller than the pore size, determined from positron annihilation lifetime spectroscopy to be mesoscopic. Based on the experimental evidence, we devise a theoretical model of the pSi formation during MACE and apply it for better control of the nanowire morphology.

Effects of laser fluence on silicon modification by four-beam laser interference

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhao, Le; Li, Dayou; JR3CN and IRAC, University of Bedfordshire, Luton LU1 3JU

2015-12-21

This paper discusses the effects of laser fluence on silicon modification by four-beam laser interference. In this work, four-beam laser interference was used to pattern single crystal silicon wafers for the fabrication of surface structures, and the number of laser pulses was applied to the process in air. By controlling the parameters of laser irradiation, different shapes of silicon structures were fabricated. The results were obtained with the single laser fluence of 354 mJ/cm{sup 2}, 495 mJ/cm{sup 2}, and 637 mJ/cm{sup 2}, the pulse repetition rate of 10 Hz, the laser exposure pulses of 30, 100, and 300, the laser wavelength of 1064 nm, andmore » the pulse duration of 7–9 ns. The effects of the heat transfer and the radiation of laser interference plasma on silicon wafer surfaces were investigated. The equations of heat flow and radiation effects of laser plasma of interfering patterns in a four-beam laser interference distribution were proposed to describe their impacts on silicon wafer surfaces. The experimental results have shown that the laser fluence has to be properly selected for the fabrication of well-defined surface structures in a four-beam laser interference process. Laser interference patterns can directly fabricate different shape structures for their corresponding applications.« less

Slicing of silicon into sheet material. Silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project. Third quarterly report, September 20, 1976--December 19, 1976

DOE Office of Scientific and Technical Information (OSTI.GOV)

Holden, S.C.

1976-12-27

The stability of tensioned blades used in multiblade sawing does not seem to be the limitation in cutting with thin blades. So far, 0.010 cm thick blades have been totally unsuccessful. Recently, 0.015 cm blades have proven successful in wafering, offering an 0.005 cm reduction in the silicon used per slice. The failure of thin blades is characterized as a possible result of blade misalignment or from the inherent uncontrollability of the loose abrasive multiblade process. Corrective procedures will be employed in the assembly of packages to eliminate one type of blade misalignment. Two ingots were sliced with the samemore » batch of standard silicon carbide abrasive slurry to determine the useful lifetime of this expendable material. After 250 slices, the cutting efficiency had not degraded. Further tests will be continued to establish the maximum lifetime of both silicon carbide and boron carbide abrasive. Electron microscopy will be employed to evaluate the wear of abrasive particles in the failure of abrasive slurry. The surface damage of silicon wafers has been characterized as predominantly subsurface fracture. Damage with No. 600 SiC is between 10 and 15 microns into the wafer surface. This agrees well with previous investigations of damage from silicon carbide abrasive papers.« less

Disposable attenuated total reflection-infrared crystals from silicon wafer: a versatile approach to surface infrared spectroscopy.

PubMed

Karabudak, Engin; Kas, Recep; Ogieglo, Wojciech; Rafieian, Damon; Schlautmann, Stefan; Lammertink, R G H; Gardeniers, Han J G E; Mul, Guido

2013-01-02

Attenuated total reflection-infrared (ATR-IR) spectroscopy is increasingly used to characterize solids and liquids as well as (catalytic) chemical conversion. Here we demonstrate that a piece of silicon wafer cut by a dicing machine or cleaved manually can be used as disposable internal reflection element (IRE) without the need for polishing and laborious edge preparation. Technical aspects, fundamental differences, and pros and cons of these novel disposable IREs and commercial IREs are discussed. The use of a crystal (the Si wafer) in a disposable manner enables simultaneous preparation and analysis of substrates and application of ATR spectroscopy in high temperature processes that may lead to irreversible interaction between the crystal and the substrate. As representative application examples, the disposable IREs were used to study high temperature thermal decomposition and chemical changes of polyvinyl alcohol (PVA) in a titania (TiO(2)) matrix and assemblies of 65-450 nm thick polystyrene (PS) films.

Heterogeneous microring and Mach-Zehnder modulators based on lithium niobate and chalcogenide glasses on silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rao, Ashutosh; Patil, Aniket; Chiles, Jeff

In this study, thin films of lithium niobate are wafer bonded onto silicon substrates and rib-loaded with a chalcogenide glass, Ge 23Sb 7S 70, to demonstrate strongly confined single-mode submicron waveguides, microring modulators, and Mach-Zehnder modulators in the telecom C band. The 200 μm radii microring modulators present 1.2 dB/cm waveguide propagation loss, 1.2 × 10 5 quality factor, 0.4 GHz/V tuning rate, and 13 dB extinction ratio. The 6 mm long Mach-Zehnder modulators have a half-wave voltage-length product of 3.8 V.cm and an extinction ratio of 15 dB. The demonstrated work is a key step towards enabling wafer scalemore » dense on-chip integration of high performance lithium niobate electro-optical devices on silicon for short reach optical interconnects and higher order advanced modulation schemes.« less

An all-silicon single-wafer micro-g accelerometer with a combined surface and bulk micromachining process

NASA Technical Reports Server (NTRS)

Yazdi, N.; Najafi, K.

2000-01-01

This paper reports an all-silicon fully symmetrical z-axis micro-g accelerometer that is fabricated on a single-silicon wafer using a combined surface and bulk fabrication process. The microaccelerometer has high device sensitivity, low noise, and low/controllable damping that are the key factors for attaining micro g and sub-micro g resolution in capacitive accelerometers. The microfabrication process produces a large proof mass by using the whole wafer thickness and a large sense capacitance by utilizing a thin sacrificial layer. The sense/feedback electrodes are formed by a deposited 2-3 microns polysilicon film with embedded 25-35 microns-thick vertical stiffeners. These electrodes, while thin, are made very stiff by the thick embedded stiffeners so that force rebalancing of the proof mass becomes possible. The polysilicon electrodes are patterned to create damping holes. The microaccelerometers are batch-fabricated, packaged, and tested successfully. A device with a 2-mm x 1-mm proof mass and a full bridge support has a measured sensitivity of 2 pF/g. The measured sensitivity of a 4-mm x 1-mm accelerometer with a cantilever support is 19.4 pF/g. The calculated noise floor of these devices at atmosphere are 0.23 micro g/sqrt(Hz) and 0.16 micro g/sqrt(Hz), respectively.

Improved amorphous/crystalline silicon interface passivation for heterojunction solar cells by low-temperature chemical vapor deposition and post-annealing treatment.

PubMed

Wang, Fengyou; Zhang, Xiaodan; Wang, Liguo; Jiang, Yuanjian; Wei, Changchun; Xu, Shengzhi; Zhao, Ying

2014-10-07

In this study, hydrogenated amorphous silicon (a-Si:H) thin films are deposited using a radio-frequency plasma-enhanced chemical vapor deposition (RF-PECVD) system. The Si-H configuration of the a-Si:H/c-Si interface is regulated by optimizing the deposition temperature and post-annealing duration to improve the minority carrier lifetime (τeff) of a commercial Czochralski (Cz) silicon wafer. The mechanism of this improvement involves saturation of the microstructural defects with hydrogen evolved within the a-Si:H films due to the transformation from SiH2 into SiH during the annealing process. The post-annealing temperature is controlled to ∼180 °C so that silicon heterojunction solar cells (SHJ) could be prepared without an additional annealing step. To achieve better performance of the SHJ solar cells, we also optimize the thickness of the a-Si:H passivation layer. Finally, complete SHJ solar cells are fabricated using different temperatures for the a-Si:H film deposition to study the influence of the deposition temperature on the solar cell parameters. For the optimized a-Si:H deposition conditions, an efficiency of 18.41% is achieved on a textured Cz silicon wafer.

Method for rapid, controllable growth and thickness, of epitaxial silicon films

DOEpatents

Wang, Qi [Littleton, CO; Stradins, Paul [Golden, CO; Teplin, Charles [Boulder, CO; Branz, Howard M [Boulder, CO

2009-10-13

A method of producing epitaxial silicon films on a c-Si wafer substrate using hot wire chemical vapor deposition by controlling the rate of silicon deposition in a temperature range that spans the transition from a monohydride to a hydrogen free silicon surface in a vacuum, to obtain phase-pure epitaxial silicon film of increased thickness is disclosed. The method includes placing a c-Si substrate in a HWCVD reactor chamber. The method also includes supplying a gas containing silicon at a sufficient rate into the reaction chamber to interact with the substrate to deposit a layer containing silicon thereon at a predefined growth rate to obtain phase-pure epitaxial silicon film of increased thickness.

Control wafer bow of InGaP on 200 mm Si by strain engineering

NASA Astrophysics Data System (ADS)

Wang, Bing; Bao, Shuyu; Made, Riko I.; Lee, Kwang Hong; Wang, Cong; Eng Kian Lee, Kenneth; Fitzgerald, Eugene A.; Michel, Jurgen

2017-12-01

When epitaxially growing III-V compound semiconductors on Si substrates the mismatch of coefficients of thermal expansion (CTEs) between III-V and Si causes stress and wafer bow. The wafer bow is deleterious for some wafer-scale processing especially when the wafer size is large. Strain engineering was applied in the epitaxy of InGaP films on 200 mm silicon wafers having high quality germanium buffers. By applying compressive strain in the InGaP films to compensate the tensile strain induced by CTE mismatch, wafer bow was decreased from about 100 μm to less than 50 μm. X-ray diffraction studies show a clear trend between the decrease of wafer bow and the compensation of CTE mismatch induced tensile strain in the InGaP layers. In addition, the anisotropic strain relaxation in InGaP films resulted in anisotropic wafer bow along two perpendicular (110) directions. Etch pit density and plane-view transmission electron microscopy characterizations indicate that threading dislocation densities did not change significantly due to the lattice-mismatch applied in the InGaP films. This study shows that strain engineering is an effective method to control wafer bow when growing III-V semiconductors on large size Si substrates.

Multi-Step Deep Reactive Ion Etching Fabrication Process for Silicon-Based Terahertz Components

NASA Technical Reports Server (NTRS)

Reck, Theodore (Inventor); Perez, Jose Vicente Siles (Inventor); Lee, Choonsup (Inventor); Cooper, Ken B. (Inventor); Jung-Kubiak, Cecile (Inventor); Mehdi, Imran (Inventor); Chattopadhyay, Goutam (Inventor); Lin, Robert H. (Inventor); Peralta, Alejandro (Inventor)

2016-01-01

A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

High-efficiency fiber-to-chip grating couplers realized using an advanced CMOS-compatible silicon-on-insulator platform.

PubMed

Vermeulen, D; Selvaraja, S; Verheyen, P; Lepage, G; Bogaerts, W; Absil, P; Van Thourhout, D; Roelkens, G

2010-08-16

A new generation of Silicon-on-Insulator fiber-to-chip grating couplers which use a silicon overlay to enhance the directionality and thereby the coupling efficiency is presented. Devices are realized on a 200 mm wafer in a CMOS pilot line. The fabricated fiber couplers show a coupling efficiency of -1.6 dB and a 3 dB bandwidth of 80 nm.

The reverse laser drilling of transparent materials

NASA Technical Reports Server (NTRS)

Anthony, T. R.; Lindner, P. A.

1980-01-01

Within a limited range of incident laser-beam intensities, laser drilling of a sapphire wafer initiates on the surface of the wafer where the laser beam exits and proceeds upstream in the laser beam to the surface where the laser beam enters the wafer. This reverse laser drilling is the result of the constructive interference between the laser beam and its reflected component on the exit face of the wafer. Constructive interference occurs only at the exit face of the sapphire wafer because the internally reflected laser beam suffers no phase change there. A model describing reverse laser drilling predicts the ranges of incident laser-beam intensity where no drilling, reverse laser drilling, and forward laser drilling can be expected in various materials. The application of reverse laser drilling in fabricating feed-through conductors in silicon-on-sapphire wafers for a massively parallel processer is described.

Characterization of wafer-level bonded hermetic packages using optical leak detection

NASA Astrophysics Data System (ADS)

Duan, Ani; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

2009-07-01

For MEMS devices required to be operated in a hermetic environment, one of the main reliability issues is related to the packaging methods applied. In this paper, an optical method for testing low volume hermetic cavities formed by anodic bonding between glass and SOI (silicon on insulator) wafer is presented. Several different cavity-geometry structures have been designed, fabricated and applied to monitor the hermeticity of wafer level anodic bonding. SOI wafer was used as the cap wafer on which the different-geometry structures were fabricated using standard MEMS technology. The test cavities were bonded using SOI wafers to glass wafers at 400C and 1000mbar pressure inside a vacuum bonding chamber. The bonding voltage varies from 200V to 600V. The bonding strength between glass and SOI wafer was mechanically tested using shear tester. The deformation amplitudes of the cavity cap surface were monitored by using an optical interferometer. The hermeticity of the glass-to-SOI wafer level bonding was characterized through observing the surface deformation in a 6 months period in atmospheric environment. We have observed a relatively stable micro vacuum-cavity.

Investigation of Different Colloidal Porous Silicon Solutions and Their Composite Solid Matrix Rods by Optical Techniques

NASA Astrophysics Data System (ADS)

Khan, M. Naziruddin; Aldalbahi, Ali; Almohammedi, Abdullah

2018-03-01

Colloidal porous silicon (PSi) in different solvents was synthesized by simple chemical etching. Colloidal solutions were then prepared using different quantities of silicon wafer pieces (Pcs) and chloroplatinic (Pt) acid in catalyst solution. The effect on the properties of the colloidal solutions and composite rods were investigated using various optical characterization techniques. Absorption and photoluminescence (PL) intensity of the colloidal PSi solutions are observed to depend on the quantity of wafer Pcs, the Pt-solution, and the porosity formation on the wafer surface. The morphological structure of the PSi in a solvent and the solid-rod environments were studied using field-emission scanning electron microscopy (FE-SEM) and were observed to have different structures. A mono-oriented structure of PSi exists in tetrahydrofuran, which has stereo orientation in dioxane and dimethylsulfoxide (approximately 5-8 nm as confirmed using high resolution transmission electron microscopy). Subsequently, some colloidal PSi solutions were directly embedded in three types of sol-gel-based matrices, silica, ormosils (or organically modified silica) and polymer, which easily generated solid rods. Spontaneous emission (SE) of the PSi solutions and their composite rods were examined using a high power picosecond 355 nm laser source. The emitted PL and SE signals of the colloidal PSi solutions were dependent on the Pt volume, nature of the solvent, quantity of Si wafer piece, and pumping energy. The response of SE signals from the PSi composites rods is an interesting phenomenon, and such nanocomposites may be used for future research on light amplification.

Low loss poly-silicon for high performance capacitive silicon modulators.

PubMed

Douix, Maurin; Baudot, Charles; Marris-Morini, Delphine; Valéry, Alexia; Fowler, Daivid; Acosta-Alba, Pablo; Kerdilès, Sébastien; Euvrard, Catherine; Blanc, Romuald; Beneyton, Rémi; Souhaité, Aurélie; Crémer, Sébastien; Vulliet, Nathalie; Vivien, Laurent; Boeuf, Frédéric

2018-03-05

Optical properties of poly-silicon material are investigated to be integrated in new silicon photonics devices, such as capacitive modulators. Test structure fabrication is done on 300 mm wafer using LPCVD deposition: 300 nm thick amorphous silicon layers are deposited on thermal oxide, followed by solid phase crystallization anneal. Rib waveguides are fabricated and optical propagation losses measured at 1.31 µm. Physical analysis (TEM ASTAR, AFM and SIMS) are used to assess the origin of losses. Optimal deposition and annealing conditions have been defined, resulting in 400 nm-wide rib waveguides with only 9.2-10 dB/cm losses.

Microdistribution of oxygen in silicon

NASA Technical Reports Server (NTRS)

Murgai, A.; Chi, J. Y.; Gatos, H. C.

1980-01-01

The microdistribution of oxygen in Czochralskii-grown, p-type silicon crystals was determined by using the SEM in the EBIC mode in conjunction with spreading resistance measurements. When the conductivity remained p-type, bands of contrast were observed in the EBIC image which corresponded to maxima in resistivity. When at the oxygen concentration maxima the oxygen donor concentration exceeded the p-type dopant concentration, an inversion of the conductivity occurred. It resulted in the formation of p-n junctions in a striated configuration and the local inversion of the EBIC image contrast. By heat-treating silicon at 1000 C prior to the activation of oxygen donors, some silicon-oxygen micro-precipitates were observed in the EBIC image within the striated oxygen concentration maxima.

Investigation of Different Colloidal Porous Silicon Solutions and Their Composite Solid Matrix Rods by Optical Techniques

NASA Astrophysics Data System (ADS)

Khan, M. Naziruddin; Aldalbahi, Ali; Almohammedi, Abdullah

2018-07-01

Colloidal porous silicon (PSi) in different solvents was synthesized by simple chemical etching. Colloidal solutions were then prepared using different quantities of silicon wafer pieces (Pcs) and chloroplatinic (Pt) acid in catalyst solution. The effect on the properties of the colloidal solutions and composite rods were investigated using various optical characterization techniques. Absorption and photoluminescence (PL) intensity of the colloidal PSi solutions are observed to depend on the quantity of wafer Pcs, the Pt-solution, and the porosity formation on the wafer surface. The morphological structure of the PSi in a solvent and the solid-rod environments were studied using field-emission scanning electron microscopy (FE-SEM) and were observed to have different structures. A mono-oriented structure of PSi exists in tetrahydrofuran, which has stereo orientation in dioxane and dimethylsulfoxide (approximately 5-8 nm as confirmed using high resolution transmission electron microscopy). Subsequently, some colloidal PSi solutions were directly embedded in three types of sol-gel-based matrices, silica, ormosils (or organically modified silica) and polymer, which easily generated solid rods. Spontaneous emission (SE) of the PSi solutions and their composite rods were examined using a high power picosecond 355 nm laser source. The emitted PL and SE signals of the colloidal PSi solutions were dependent on the Pt volume, nature of the solvent, quantity of Si wafer piece, and pumping energy. The response of SE signals from the PSi composites rods is an interesting phenomenon, and such nanocomposites may be used for future research on light amplification.

Characterization and modelling of the boron-oxygen defect activation in compensated n-type silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schön, J.; Niewelt, T.; Broisch, J.

2015-12-28

A study of the activation of the light-induced degradation in compensated n-type Czochralski grown silicon is presented. A kinetic model is established that verifies the existence of both the fast and the slow components known from p-type and proves the quadratic dependence of the defect generation rates of both defects on the hole concentration. The model allows for the description of lifetime degradation kinetics in compensated n-type silicon under various intensities and is in accordance with the findings for p-type silicon. We found that the final concentrations of the slow defect component in compensated n-type silicon only depend on themore » interstitial oxygen concentration and on neither the boron concentration nor the equilibrium electron concentration n{sub 0}. The final concentrations of the fast defect component slightly increase with increasing boron concentration. The results on n-type silicon give new insight to the origin of the BO defect and question the existing models for the defect composition.« less

Molecular transport through nanoporous silicon nitride membranes produced from self-assembling block copolymers.

PubMed

Montagne, Franck; Blondiaux, Nicolas; Bojko, Alexandre; Pugin, Raphaël

2012-09-28

To achieve fast and selective molecular filtration, membrane materials must ideally exhibit a thin porous skin and a high density of pores with a narrow size distribution. Here, we report the fabrication of nanoporous silicon nitride membranes (NSiMs) at the full wafer scale using a versatile process combining block copolymer (BCP) self-assembly and conventional photolithography/etching techniques. In our method, self-assembled BCP micelles are used as templates for creating sub-100 nm nanopores in a thin low-stress silicon nitride layer, which is then released from the underlying silicon wafer by etching. The process yields 100 nm thick free-standing NSiMs of various lateral dimensions (up to a few mm(2)). We show that the membranes exhibit a high pore density, while still retaining excellent mechanical strength. Permeation experiments reveal that the molecular transport rate across NSiMs is up to 16-fold faster than that of commercial polymeric membranes. Moreover, using dextran molecules of various molecular weights, we also demonstrate that size-based separation can be achieved with a very good selectivity. These new silicon nanosieves offer a relevant technological alternative to commercially available ultra- and microfiltration membranes for conducting high resolution biomolecular separations at small scales.

Nano-Photonic Structures for Light Trapping in Ultra-Thin Crystalline Silicon Solar Cells.

PubMed

Pathi, Prathap; Peer, Akshit; Biswas, Rana

2017-01-13

Thick wafer-silicon is the dominant solar cell technology. It is of great interest to develop ultra-thin solar cells that can reduce materials usage, but still achieve acceptable performance and high solar absorption. Accordingly, we developed a highly absorbing ultra-thin crystalline Si based solar cell architecture using periodically patterned front and rear dielectric nanocone arrays which provide enhanced light trapping. The rear nanocones are embedded in a silver back reflector. In contrast to previous approaches, we utilize dielectric photonic crystals with a completely flat silicon absorber layer, providing expected high electronic quality and low carrier recombination. This architecture creates a dense mesh of wave-guided modes at near-infrared wavelengths in the absorber layer, generating enhanced absorption. For thin silicon (<2 μm) and 750 nm pitch arrays, scattering matrix simulations predict enhancements exceeding 90%. Absorption approaches the Lambertian limit at small thicknesses (<10 μm) and is slightly lower (by ~5%) at wafer-scale thicknesses. Parasitic losses are ~25% for ultra-thin (2 μm) silicon and just 1%-2% for thicker (>100 μm) cells. There is potential for 20 μm thick cells to provide 30 mA/cm² photo-current and >20% efficiency. This architecture has great promise for ultra-thin silicon solar panels with reduced material utilization and enhanced light-trapping.

SERS Engineering Collaboration

DTIC Science & Technology

2012-06-01

laser beam. In the second approach, a pulsed laser was used to texture a silicon wafer to form sharp features. Silver was evaporated onto the wafer...orders of magnitude larger than that measured on a gold nanoparticle array on a glass substrate. The largest SERS enhancement for a silver device was...surface plasmons," Yizhuo Chu and Kenneth B. Crozier, Optics Letters vol. 34, 244 (2009) K3. "Gold nanorings as substrates for surface-enhanced Raman

Field induced decrystallization of silicon: Evidence of a microwave non-thermal effect

NASA Astrophysics Data System (ADS)

Nozariasbmarz, Amin; Dsouza, Kelvin; Vashaee, Daryoosh

2018-02-01

It is rather strange and not fully understood that some materials decrystallize when exposed to microwave radiation, and it is still debatable if such a transformation is a thermal or non-thermal effect. We hereby report experimental evidences that weight the latter effect. First, a single crystal silicon wafer exposed to microwaves showed strong decrystallization at high temperature. Second, when some areas of the wafer were masked with metal coating, only the exposed areas underwent decrystallization. Transmission electron microscopy analysis, x-ray diffraction data, and thermal conductivity measurements all indicated strong decrystallization, which occurred in the bulk of the material and was not a surface effect. These observations favor the existence of a non-thermal microwave effect.

GaN membrane MSM ultraviolet photodetectors

NASA Astrophysics Data System (ADS)

Muller, A.; Konstantinidis, G.; Kostopoulos, A.; Dragoman, M.; Neculoiu, D.; Androulidaki, M.; Kayambaki, M.; Vasilache, D.; Buiculescu, C.; Petrini, I.

2006-12-01

GaN exhibits unique physical properties, which make this material very attractive for wide range of applications and among them ultraviolet detection. For the first time a MSM type UV photodetector structure was manufactured on a 2.2 μm. thick GaN membrane obtained using micromachining techniques. The low unintentionally doped GaN layer structure was grown by MOCVD on high resistivity (ρ>10kΩcm) <111> oriented silicon wafers, 500μm thick. The epitaxially grown layers include a thin AlN layer in order to reduce the stress in the GaN layer and avoid cracking. Conventional contact lithography, e-gun Ni/Au (10nm /200nm) evaporation and lift-off techniques were used to define the interdigitated Schottky metalization on the top of the wafer. Ten digits with a width of 1μm and a length of 100μm were defined for each electrode. The distance between the digits was also 1μm. After the backside lapping of the wafer to a thickness of approximately 150μm, a 400nm thick Al layer was patterned and deposited on the backside, to be used as mask for the selective reactive ion etching of silicon. The backside mask, for the membrane formation, was patterned using double side alignment techniques and silicon was etched down to the 2.2μm thin GaN layer using SF 6 plasma. A very low dark current (30ρA at 3V) was obtained. Optical responsivity measurements were performed at 1.5V. A maximum responsivity of 18mA/W was obtained at a wavelength of 370nm. This value is very good and can be further improved using transparent contacts for the interdigitated structure.

Morphology and FT IR spectra of porous silicon

NASA Astrophysics Data System (ADS)

Kopani, Martin; Mikula, Milan; Kosnac, Daniel; Gregus, Jan; Pincik, Emil

2017-12-01

The morphology and chemical bods of p-type and n-type porous Si was compared. The surface of n-type sample is smooth, homogenous without any features. The surface of p-type sample reveals micrometer-sized islands. FTIR investigation reveals various distribution of SiOxHy complexes in both p-and n-type samples. From the conditions leading to porous silicon layer formation (the presence of holes) we suggest both SiOxHy and SiFxHy complexes in the layer.

The silane depletion fraction as an indicator for the amorphous/crystalline silicon interface passivation quality

NASA Astrophysics Data System (ADS)

Descoeudres, A.; Barraud, L.; Bartlome, R.; Choong, G.; De Wolf, Stefaan; Zicarelli, F.; Ballif, C.

2010-11-01

In silicon heterojunction solar cells, thin amorphous silicon layers passivate the crystalline silicon wafer surfaces. By using in situ diagnostics during plasma-enhanced chemical vapor deposition (PECVD), the authors report how the passivation quality of such layers directly relate to the plasma conditions. Good interface passivation is obtained from highly depleted silane plasmas. Based upon this finding, layers deposited in a large-area very high frequency (40.68 MHz) PECVD reactor were optimized for heterojunction solar cells, yielding aperture efficiencies up to 20.3% on 4 cm2 cells.

Process Research on Polycrystalline Silicon Material (PROPSM)

NASA Technical Reports Server (NTRS)

Culik, J. S.

1982-01-01

The investigation of the performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was continued by fabricating a set of minicell wafers on a selection of 10 cm x 10 cm wafers. A minicell wafer consists of an array of small (approximately 0.2 sq cm in area) photodiodes which are isolated from one another by a mesa structure. The junction capacitance of each minicell was used to obtain the dopant concentration, and therefore the resistivity, as a function of position across each wafer. The results indicate that there is no significant variation in resistivity with position for any of the polycrystalline wafers, whether Semix or Wacker. However, the resistivity of Semix brick 71-01E did decrease slightly from bottom to top.

Hot embossed polyethylene through-hole chips for bead-based microfluidic devices

PubMed Central

Chou, Jie; Du, Nan; Ou, Tina; Floriano, Pierre N.; Christodoulides, Nicolaos; McDevitt, John T.

2013-01-01

Over the past decade, there has been a growth of interest in the translation of microfluidic systems into real-world clinical practice, especially for use in point-of-care or near patient settings. While initial fabrication advances in microfluidics involved mainly the etching of silicon and glass, the economics of scaling of these materials is not amendable for point-of-care usage where single-test applications forces cost considerations to be kept low and throughput high. As such, a materials base more consistent with point-of-care needs is required. In this manuscript, the fabrication of a hot embossed, through-hole low-density polyethylene ensembles derived from an anisotropically etched silicon wafer is discussed. This semi-opaque polymer that can be easily sterilized and recycled provides low background noise for fluorescence measurements and yields more affordable cost than other thermoplastics commonly used for microfluidic applications such as cyclic olefin copolymer (COC). To fabrication through-hole microchips from this alternative material for microfluidics, a fabrication technique that uses a high-temperature, high-pressure resistant mold is described. This aluminum-based epoxy mold, serving as the positive master mold for embossing, is casted over etched arrays of pyramidal pits in a silicon wafer. Methods of surface treatment of the wafer prior to casting and PDMS casting of the epoxy are discussed to preserve the silicon wafer for future use. Changes in the thickness of polyethylene are observed for varying embossing temperatures. The methodology described herein can quickly fabricate 20 disposable, single use chips in less than 30 minutes with the ability to scale up 4x by using multiple molds simultaneously. When coupled as a platform supporting porous bead sensors, as in the recently developed Programmable Bio-Nano-Chip, this bead chip system can achieve limits of detection, for the cardiac biomarker C-reactive protein, of 0.3 ng/mL, thereby demonstrating the approach is compatible with high performance, real-world clinical measurements in the context of point-of-care testing. PMID:23183187

Method for processing silicon solar cells

DOEpatents

Tsuo, Y.S.; Landry, M.D.; Pitts, J.R.

1997-05-06

The instant invention teaches a novel method for fabricating silicon solar cells utilizing concentrated solar radiation. The solar radiation is concentrated by use of a solar furnace which is used to form a front surface junction and back-surface field in one processing step. The present invention also provides a method of making multicrystalline silicon from amorphous silicon. The invention also teaches a method of texturing the surface of a wafer by forming a porous silicon layer on the surface of a silicon substrate and a method of gettering impurities. Also contemplated by the invention are methods of surface passivation, forming novel solar cell structures, and hydrogen passivation. 2 figs.

Modeling and Optimization for Epitaxial Growth: Transport and Growth Studies

DTIC Science & Technology

1999-01-01

effect . It is expressed as the sum of these two components j i jC i jT i where jC i and jT i denote the concentration driven and thermally driven...improve manufacturing effectiveness for epitaxial growth of silicon and silicon-germanium (Si-Ge) thin films on a silicon wafer. Growth takes place in the...non-uniformity to compensate for the effects of other phenomena such as reactant depletion, gas heating and gas phase reactions, thermal diffusion of

Fast Pulling of n-Type Si Ingots for Enhanced Si Solar Cell Production

NASA Astrophysics Data System (ADS)

Kim, Kwanghun; Park, Sanghyun; Park, Jaechang; Pang, Ilsun; Ryu, Sangwoo; Oh, Jihun

2018-03-01

Reducing the manufacturing costs of silicon substrates is an important issue in the silicon-based solar cell industry. In this study, we developed a high-throughput ingot growth method by accelerating the pulling speed in the Czochralski process. By controlling the heat flow of the ingot growth chamber and at the solid-liquid interfaces, the pulling speed of an ingot could be increased by 15% compared to the conventional method, while retaining high quality. The wafer obtained at a high pulling speed showed an enhanced minority carrier lifetime compared with conventional wafers, due to the vacancy passivation effect, and also demonstrated comparable bulk resistivity and impurities. The results in this work are expected to open a new way to enhance the productivity of Si wafers used for Si solar cells, and therefore, to reduce the overall manufacturing cost.

Fast Pulling of n-Type Si Ingots for Enhanced Si Solar Cell Production

NASA Astrophysics Data System (ADS)

Kim, Kwanghun; Park, Sanghyun; Park, Jaechang; Pang, Ilsun; Ryu, Sangwoo; Oh, Jihun

2018-07-01

Reducing the manufacturing costs of silicon substrates is an important issue in the silicon-based solar cell industry. In this study, we developed a high-throughput ingot growth method by accelerating the pulling speed in the Czochralski process. By controlling the heat flow of the ingot growth chamber and at the solid-liquid interfaces, the pulling speed of an ingot could be increased by 15% compared to the conventional method, while retaining high quality. The wafer obtained at a high pulling speed showed an enhanced minority carrier lifetime compared with conventional wafers, due to the vacancy passivation effect, and also demonstrated comparable bulk resistivity and impurities. The results in this work are expected to open a new way to enhance the productivity of Si wafers used for Si solar cells, and therefore, to reduce the overall manufacturing cost.

High-Q Wafer Level Package Based on Modified Tri-Layer Anodic Bonding and High Performance Getter and Its Evaluation for Micro Resonant Pressure Sensor.

PubMed

Wang, Liying; Du, Xiaohui; Wang, Lingyun; Xu, Zhanhao; Zhang, Chenying; Gu, Dandan

2017-03-16

In order to achieve and maintain a high quality factor (high-Q) for the micro resonant pressure sensor, this paper presents a new wafer level package by adopting cross-layer anodic bonding technique of the glass/silicon/silica (GSS) stackable structure and integrated Ti getter. A double-layer structure similar to a silicon-on-insulator (SOI) wafer is formed after the resonant layer and the pressure-sensitive layer are bonded by silicon direct bonding (SDB). In order to form good bonding quality between the pressure-sensitive layer and the glass cap layer, the cross-layer anodic bonding technique is proposed for vacuum package by sputtering Aluminum (Al) on the combination wafer of the pressure-sensitive layer and the resonant layer to achieve electrical interconnection. The model and the bonding effect of this technique are discussed. In addition, in order to enhance the performance of titanium (Ti) getter, the prepared and activation parameters of Ti getter under different sputtering conditions are optimized and discussed. Based on the optimized results, the Ti getter (thickness of 300 nm to 500 nm) is also deposited on the inside of the glass groove by magnetron sputtering to maintain stable quality factor (Q). The Q test of the built testing system shows that the number of resonators with a Q value of more than 10,000 accounts for more than 73% of the total. With an interval of 1.5 years, the Q value of the samples remains almost constant. It proves the proposed cross-layer anodic bonding and getter technique can realize high-Q resonant structure for long-term stable operation.

The dual role of silver during silicon etching in HF solution.

PubMed

Abouda-Lachiheb, Manel; Nafie, Nesma; Bouaicha, Mongi

2012-08-13

It was reported that during silicon etching, silver was subjected to have a controversial role. Some researchers debate that silver protects silicon, and, at the same time, other ones confirm that silver catalyzes silicon underneath. In this paper, we give experimental results arguing the dual role that silver has during the formation of silicon nanostructures. We give a proof that the role of silver depends on the experimental details and the intrinsic properties of silver during its deposition on the silicon wafer. Through our investigations, we tracked the silver particles that indicated which mechanism is involved. Characterizations of the prepared samples were made using a scanning electron microscope.

Method for processing silicon solar cells

DOEpatents

Tsuo, Y. Simon; Landry, Marc D.; Pitts, John R.

1997-01-01

The instant invention teaches a novel method for fabricating silicon solar cells utilizing concentrated solar radiation. The solar radiation is concentrated by use of a solar furnace which is used to form a front surface junction and back-surface field in one processing step. The present invention also provides a method of making multicrystallline silicon from amorphous silicon. The invention also teaches a method of texturing the surface of a wafer by forming a porous silicon layer on the surface of a silicon substrate and a method of gettering impurities. Also contemplated by the invention are methods of surface passivation, forming novel solar cell structures, and hydrogen passivation.

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2014 CFR

2014-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

Fluorinion transfer in silver-assisted chemical etching for silicon nanowires arrays

NASA Astrophysics Data System (ADS)

Feng, Tianyu; Xu, Youlong; Zhang, Zhengwei; Mao, Shengchun

2015-08-01

Uniform silicon nanowires arrays (SiNWAs) were fabricated on unpolished rough silicon wafers through KOH pretreatment followed by silver-assisted chemical etching (SACE). Density functional theory (DFT) calculations were used to investigate the function of silver (Ag) at atomic scale in the etching process. Among three adsorption sites of Ag atom on Si(1 0 0) surface, Ag(T4) above the fourth-layer surface Si atoms could transfer fluorinion (F-) to adjacent Si successfully due to its stronger electrostatic attraction force between Ag(T4) and F-, smaller azimuth angle of Fsbnd Ag(T4)sbnd Si, shorter bond length of Fsbnd Si compared with Fsbnd Ag. As F- was transferred to adjacent Si by Ag(T4) one by one, the Si got away from the wafer in the form of SiF4 when it bonded with enough F- while Ag(T4) was still attached onto the Si wafer ready for next transfer. Cyclic voltammetry tests confirmed that Ag can improve the etching rate by transferring F- to Si.

Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

PubMed

Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

2012-07-17

Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

Cobalt related defect levels in silicon analyzed by temperature- and injection-dependent lifetime spectroscopy

NASA Astrophysics Data System (ADS)

Diez, S.; Rein, S.; Roth, T.; Glunz, S. W.

2007-02-01

Temperature- and injection-dependent lifetime spectroscopy (TIDLS) as a method to characterize point defects in silicon with several energy levels is demonstrated. An intentionally cobalt-contaminated p-type wafer was investigated by means of lifetime measurements performed at different temperatures up to 151°C. Two defect energy levels were required to model the lifetime curves on basis of the Shockley-Read-Hall statistics. The detailed analysis is based on the determination of the recently introduced defect parameter solution surface (DPSS) in order to extract the underlying defect parameters. A unique solution has been found for a deep defect level located in the upper band gap half with an energy depth of EC-Et=0.38±0.01eV, with a corresponding ratio of capture cross sections k =σn/σp=0.16 within the interval of uncertainty of 0.06-0.69. Additionally, a deep donor level in the lower band gap half known from the literature could be assigned to a second energy level within the DPSS analysis at Et-EV=0.41±0.02eV with a corresponding ratio of capture cross sections k =σn/σp=16±3. An investigation of the temperature dependence of the capture cross section for electrons suggests that the underlying recombination process of the defect in the lower band gap half is driven by a two stage cascade capture with an activation energy of ΔE =52±2meV. These results show that TIDLS in combination with DPSS analysis is a powerful method to characterize even multiple defect levels that are affecting carrier recombination lifetime in parallel.

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits.

PubMed

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe 2 , a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

Improved broadband and quasi-omnidirectional anti-reflection properties with biomimetic silicon nanostructures.

PubMed

Huang, Yi-Fan; Chattopadhyay, Surojit; Jen, Yi-Jun; Peng, Cheng-Yu; Liu, Tze-An; Hsu, Yu-Kuei; Pan, Ci-Ling; Lo, Hung-Chun; Hsu, Chih-Hsun; Chang, Yuan-Huei; Lee, Chih-Shan; Chen, Kuei-Hsien; Chen, Li-Chyong

2007-12-01

Nature routinely produces nanostructured surfaces with useful properties, such as the self-cleaning lotus leaf, the colour of the butterfly wing, the photoreceptor in brittlestar and the anti-reflection observed in the moth eye. Scientists and engineers have been able to mimic some of these natural structures in the laboratory and in real-world applications. Here, we report a simple aperiodic array of silicon nanotips on a 6-inch wafer with a sub-wavelength structure that can suppress the reflection of light at a range of wavelengths from the ultraviolet, through the visible part of the spectrum, to the terahertz region. Reflection is suppressed for a wide range of angles of incidence and for both s- and p-polarized light. The antireflection properties of the silicon result from changes in the refractive index caused by variations in the height of the silicon nanotips, and can be simulated with models that have been used to explain the low reflection from moth eyes. The improved anti-reflection properties of the surfaces could have applications in renewable energy and electro-optical devices for the military.

Monolithic photonic integrated circuit with a GaN-based bent waveguide

NASA Astrophysics Data System (ADS)

Cai, Wei; Qin, Chuan; Zhang, Shuai; Yuan, Jialei; Zhang, Fenghua; Wang, Yongjin

2018-06-01

Integration of a transmitter, waveguide and receiver into a single chip can generate a multicomponent system with multiple functionalities. Here, we fabricate and characterize a GaN-based photonic integrated circuit (PIC) on a GaN-on-silicon platform. With removal of the silicon and back wafer thinning of the epitaxial film, ultrathin membrane-type devices and highly confined suspended GaN waveguides were formed. Two suspended-membrane InGaN/GaN multiple-quantum-well diodes (MQW-diodes) served as an MQW light-emitting diode (MQW-LED) to emit light and an MQW photodiode (MQW-PD) to sense light. The optical interconnects between the MQW-LED and MQW-PD were achieved using the GaN bent waveguide. The GaN-based PIC consisting of an MQW-LED, waveguides and an MQW-PD forms an in-plane light communication system with a data transmission rate of 70 Mbps.

Hydrogen ion microlithography

DOEpatents

Tsuo, Y. Simon; Deb, Satyen K.

1990-01-01

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing.

Printable nanostructured silicon solar cells for high-performance, large-area flexible photovoltaics.

PubMed

Lee, Sung-Min; Biswas, Roshni; Li, Weigu; Kang, Dongseok; Chan, Lesley; Yoon, Jongseung

2014-10-28

Nanostructured forms of crystalline silicon represent an attractive materials building block for photovoltaics due to their potential benefits to significantly reduce the consumption of active materials, relax the requirement of materials purity for high performance, and hence achieve greatly improved levelized cost of energy. Despite successful demonstrations for their concepts over the past decade, however, the practical application of nanostructured silicon solar cells for large-scale implementation has been hampered by many existing challenges associated with the consumption of the entire wafer or expensive source materials, difficulties to precisely control materials properties and doping characteristics, or restrictions on substrate materials and scalability. Here we present a highly integrable materials platform of nanostructured silicon solar cells that can overcome these limitations. Ultrathin silicon solar microcells integrated with engineered photonic nanostructures are fabricated directly from wafer-based source materials in configurations that can lower the materials cost and can be compatible with deterministic assembly procedures to allow programmable, large-scale distribution, unlimited choices of module substrates, as well as lightweight, mechanically compliant constructions. Systematic studies on optical and electrical properties, photovoltaic performance in experiments, as well as numerical modeling elucidate important design rules for nanoscale photon management with ultrathin, nanostructured silicon solar cells and their interconnected, mechanically flexible modules, where we demonstrate 12.4% solar-to-electric energy conversion efficiency for printed ultrathin (∼ 8 μm) nanostructured silicon solar cells when configured with near-optimal designs of rear-surface nanoposts, antireflection coating, and back-surface reflector.

Thinning of PLZT ceramic wafers for sensor integration

NASA Astrophysics Data System (ADS)

Jin, Na; Liu, Weiguo

2010-08-01

Characteristics of transparent PLZT ceramics can be tailored by controlling the component of them, and therefore showed excellent dielectric, piezoelectric, pyroelectric and ferroelectric properties. To integrate the ceramics with microelectronic circuit to realize integrated applications, the ceramic wafers have to be thinned down to micrometer scale in thickness. A7/65/35 PLZT ceramic wafer was selected in this study for the thinning process. Size of the wafer was 10×10mm with an initial thickness of 300μm. A novel membrane transfer process (MTP) was developed for the thinning and integration of the ceramic wafers. In the MTP process, the ceramic wafer was bonded to silicon wafer using a polymer bonding method. Mechanical grinding method was applied to reduce the thickness of the ceramic. To minimize the surface damage in the ceramic wafer caused by the mechanical grinding, magnetorheological finishing (MRF) method was utilized to polish the wafer. White light interference (WLI) apparatus was used to monitor the surface qualities of the grinded and ploished ceramic wafers. For the PLZT membrane obtained from the MTP process, the final thickness of the thinned and polished wafer was 10μm, the surface roughness was below 1nm in rms, and the flatness was better than λ/5.

Ultrafast carrier dynamics in a p-type GaN wafer under different carrier distributions

NASA Astrophysics Data System (ADS)

Fang, Yu; Yang, Junyi; Yang, Yong; Wu, Xingzhi; Xiao, Zhengguo; Zhou, Feng; Song, Yinglin

2016-02-01

The dependence of the carrier distribution on photoexcited carrier dynamics in a p-type Mg-doped GaN (GaN:Mg) wafer were systematically measured by femtosecond transient absorption (TA) spectroscopy. The homogeneity of the carrier distribution was modified by tuning the wavelength of the UV pulse excitation around the band gap of GaN:Mg. The TA kinetics appeared to be biexponential for all carrier distributions, and only the slower component decayed faster as the inhomogeneity of the carrier distribution increased. It was concluded that the faster component (50-70 ps) corresponded to the trap process of holes by the Mg acceptors, and the slower component (150-600 ps) corresponded to the combination of non-radiative surface recombination and intrinsic carrier recombination via dislocations. Moreover, the slower component increased gradually with the incident fluence due to the saturation of surface states.

Development of Hybrid Sensor Arrays for Sensor Arrays for Simultaneous Measurement of Pressure and Shear Stress Distribution

NASA Technical Reports Server (NTRS)

2000-01-01

This document reports on the progress in developing hybrid sensors for the simultaneous measurement of pressure and shear stress. The key feature for the success of the proposed hybrid sensor array is the ability to deposit Cu-Ni alloy with proper composition (55 - 45) on a silicon wafer to form a strain gage. This alloy strain gage replaces the normally used Si strain gages in MEMS, which are highly nonlinear and temperature dependent. The copper nickel, with proper composition (55 - 45), was successfully deposited on a silicon wafer with a few trials during this period of the project. Pictures of the Cu-Ni alloy strain gage and the x-ray spectra indicating the composition are shown. The planned tests are also reviewed.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xu, Jia; Zhang, Ziang; Weng, Zhankun

This paper presents a new method for the generation of cross-scale laser interference patterns and the fabrication of moth-eye structures on silicon. In the method, moth-eye structures were produced on a surface of silicon wafer using direct six-beam laser interference lithography to improve the antireflection performance of the material surface. The periodic dot arrays of the moth-eye structures were formed due to the ablation of the irradiance distribution of interference patterns on the wafer surface. The shape, size, and distribution of the moth-eye structures can be adjusted by controlling the wavelength, incidence angles, and exposure doses in a direct six-beammore » laser interference lithography setup. The theoretical and experimental results have shown that direct six-beam laser interference lithography can provide a way to fabricate cross-scale moth-eye structures for antireflection applications.« less

Porous silicon technology for integrated microsystems

NASA Astrophysics Data System (ADS)

Wallner, Jin Zheng

With the development of micro systems, there is an increasing demand for integrable porous materials. In addition to those conventional applications, such as filtration, wicking, and insulating, many new micro devices, including micro reactors, sensors, actuators, and optical components, can benefit from porous materials. Conventional porous materials, such as ceramics and polymers, however, cannot meet the challenges posed by micro systems, due to their incompatibility with standard micro-fabrication processes. In an effort to produce porous materials that can be used in micro systems, porous silicon (PS) generated by anodization of single crystalline silicon has been investigated. In this work, the PS formation process has been extensively studied and characterized as a function of substrate type, crystal orientation, doping concentration, current density and surfactant concentration and type. Anodization conditions have been optimized for producing very thick porous silicon layers with uniform pore size, and for obtaining ideal pore morphologies. Three different types of porous silicon materials: meso porous silicon, macro porous silicon with straight pores, and macro porous silicon with tortuous pores, have been successfully produced. Regular pore arrays with controllable pore size in the range of 2mum to 6mum have been demonstrated as well. Localized PS formation has been achieved by using oxide/nitride/polysilicon stack as masking materials, which can withstand anodization in hydrofluoric acid up to twenty hours. A special etching cell with electrolytic liquid backside contact along with two process flows has been developed to enable the fabrication of thick macro porous silicon membranes with though wafer pores. For device assembly, Si-Au and In-Au bonding technologies have been developed. Very low bonding temperature (˜200°C) and thick/soft bonding layers (˜6mum) have been achieved by In-Au bonding technology, which is able to compensate the potentially rough surface on the porous silicon sample without introducing significant thermal stress. (Abstract shortened by UMI.)

Hybrid single quantum well InP/Si nanobeam lasers for silicon photonics.

PubMed

Fegadolli, William S; Kim, Se-Heon; Postigo, Pablo Aitor; Scherer, Axel

2013-11-15

We report on a hybrid InP/Si photonic crystal nanobeam laser emitting at 1578 nm with a low threshold power of ~14.7 μW. Laser gain is provided from a single InAsP quantum well embedded in a 155 nm InP layer bonded on a standard silicon-on-insulator wafer. This miniaturized nanolaser, with an extremely small modal volume of 0.375(λ/n)(3), is a promising and efficient light source for silicon photonics.

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2012 CFR

2012-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

40 CFR 63.7195 - What definitions apply to this subpart?

Code of Federal Regulations, 2013 CFR

2013-07-01

... units used to manufacture p-type and n-type semiconductors or active solid state devices from a wafer.... Examples of semiconductor or related solid state devices include semiconductor diodes, semiconductor stacks... permanently attached to motor vehicles such as trucks, railcars, barges, or ships; (2) Flow-through tanks...

Nano-photonic structures for light trapping in ultra-thin crystalline silicon solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pathi, Prathap; Peer, Akshit; Biswas, Rana

Thick wafer-silicon is the dominant solar cell technology. It is of great interest to develop ultra-thin solar cells that can reduce materials usage, but still achieve acceptable performance and high solar absorption. Accordingly, we developed a highly absorbing ultra-thin crystalline Si based solar cell architecture using periodically patterned front and rear dielectric nanocone arrays which provide enhanced light trapping. The rear nanocones are embedded in a silver back reflector. In contrast to previous approaches, we utilize dielectric photonic crystals with a completely flat silicon absorber layer, providing expected high electronic quality and low carrier recombination. This architecture creates a densemore » mesh of wave-guided modes at near-infrared wavelengths in the absorber layer, generating enhanced absorption. For thin silicon (<2 μm) and 750 nm pitch arrays, scattering matrix simulations predict enhancements exceeding 90%. Absorption approaches the Lambertian limit at small thicknesses (<10 μm) and is slightly lower (by ~5%) at wafer-scale thicknesses. Parasitic losses are ~25% for ultra-thin (2 μm) silicon and just 1%–2% for thicker (>100 μm) cells. There is potential for 20 μm thick cells to provide 30 mA/cm2 photo-current and >20% efficiency. Furthermore, this architecture has great promise for ultra-thin silicon solar panels with reduced material utilization and enhanced light-trapping.« less

Nano-photonic structures for light trapping in ultra-thin crystalline silicon solar cells

DOE PAGES

Pathi, Prathap; Peer, Akshit; Biswas, Rana

2017-01-13

Thick wafer-silicon is the dominant solar cell technology. It is of great interest to develop ultra-thin solar cells that can reduce materials usage, but still achieve acceptable performance and high solar absorption. Accordingly, we developed a highly absorbing ultra-thin crystalline Si based solar cell architecture using periodically patterned front and rear dielectric nanocone arrays which provide enhanced light trapping. The rear nanocones are embedded in a silver back reflector. In contrast to previous approaches, we utilize dielectric photonic crystals with a completely flat silicon absorber layer, providing expected high electronic quality and low carrier recombination. This architecture creates a densemore » mesh of wave-guided modes at near-infrared wavelengths in the absorber layer, generating enhanced absorption. For thin silicon (<2 μm) and 750 nm pitch arrays, scattering matrix simulations predict enhancements exceeding 90%. Absorption approaches the Lambertian limit at small thicknesses (<10 μm) and is slightly lower (by ~5%) at wafer-scale thicknesses. Parasitic losses are ~25% for ultra-thin (2 μm) silicon and just 1%–2% for thicker (>100 μm) cells. There is potential for 20 μm thick cells to provide 30 mA/cm2 photo-current and >20% efficiency. Furthermore, this architecture has great promise for ultra-thin silicon solar panels with reduced material utilization and enhanced light-trapping.« less

A Novel High-Efficiency Rear-Contact Solar Cell with Bifacial Sensitivity

NASA Astrophysics Data System (ADS)

Hezel, R.

At present, wafer-based silicon solar cells have a share of more than 90% of the photovoltaic market. Despite rapid growth in the manufacturing volume, accompanied by a significant drop in the module selling price, the high costs currently associated with photovoltaic power generation are one of the most important obstacles to widespread global use of solar electricity. Up to a certain level, a higher production volume is a key driver in cost reduction. However, apart from a drastic reduction of the silicon wafer thickness in conjunction with improved light-trapping schemes, innovative processing sequences combining very high solar cell efficiencies with simple and cost-effective fabrication techniques are needed to become competitive with conventional energy sources and thus to move solar energy from niche to mainstream.

A Wafer Transfer Technology for MEMS Adaptive Optics

NASA Technical Reports Server (NTRS)

Yang, Eui-Hyeok; Wiberg, Dean V.

2001-01-01

Adaptive optics systems require the combination of several advanced technologies such as precision optics, wavefront sensors, deformable mirrors, and lasers with high-speed control systems. The deformable mirror with a continuous membrane is a key component of these systems. This paper describes a new technique for transferring an entire wafer-level silicon membrane from one substrate to another. This technology is developed for the fabrication of a compact deformable mirror with a continuous facet. A 1 (mu)m thick silicon membrane, 100 mm in diameter, has been successfully transferred without using adhesives or polymers (i.e. wax, epoxy, or photoresist). Smaller or larger diameter membranes can also be transferred using this technique. The fabricated actuator membrane with an electrode gap of 1.5 (mu)m shows a vertical deflection of 0.37 (mu)m at 55 V.

Porous silicon carbide (SiC) semiconductor device

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1994-01-01

A semiconductor device employs at least one layer of semiconducting porous silicon carbide (SiC). The porous SiC layer has a monocrystalline structure wherein the pore sizes, shapes, and spacing are determined by the processing conditions. In one embodiment, the semiconductor device is a p-n junction diode in which a layer of n-type SiC is positioned on a p-type layer of SiC, with the p-type layer positioned on a layer of silicon dioxide. Because of the UV luminescent properties of the semiconducting porous SiC layer, it may also be utilized for other devices such as LEDs and optoelectronic devices.

One Step Synthesis of a PerchlorinatedCyclohexasilane from Trichlorosilane: A Route to New Materials for Flexible Electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Philip Boudjouk

2010-03-27

The serendipitous discovery of tetradecachlorocyclohexasilane dianion 1 was recently reported by our group at NDSU. The dianion is isolated from a mixture of an amine template (pentaethyldiethylenetriamine, pedeta) and HSiCl{sub 3} as insoluble colorless crystals that are easily reduced to give cyclohexasilane (Si{sub 6}H{sub 12}) in high yields and purity. While the product Si{sub 6}H{sub 12} has been shown to be useful as a liquid silane precursor to a-Si:H rectifying diodes and field effect transistors, these initial studies show a non-uniform dopant distributions. The need for a homogeneous dopant has led our group to further develop the chemistry of cyclohexasilane.more » Toward that end, we have focused on the design of molecules that contain a single dopant moiety bound to one or more Si{sub 6} ring(s). New Si{sub 6}H{sub 11}E compounds (where E is an n-type or p-type dopant) are being investigated (eqs. 2, 3) and initial results will be reported including the isolation of chlorocyclohexasilane, Si{sub 6}H{sub 11}Cl. In addition, several different triamine ligand templates to for Si{sub 6}Cl{sub 14}{sup 2-} salts were investigated toward optimizing the yield and ease of isolation for both the salt and the product liquid silane. Cyclohexasilane (Si{sub 6}H{sub 12})-based inks have been used as liquid precursor to silicon-containing electronic materials. Spin-coating of Si{sub 6}H{sub 12}-based inks with subsequent UV light and/or thermal treatment yielded amorphous silicon (a-Si:H) films. Initial results demonstrated the formation of n-type and p-type a-Si that were used in heterojunction structures (i.e., thin a-Si films on heavily-doped Si wafer substrates). While present ink chemistries produce a-Si:H with a high resistivity (i.e., > 10{sup 6} {Omega}.cm), efforts are under development to address this limitation. Additionally, a new printing approach (i.e., collimated aerosol beam direct write, CAB-DW) was developed that allows the deposition of silane-based features with linewidths <10 {micro}m. Assuming silicon-based materials with good electrical properties will be developed, there may be significant cost advantages associated with the ability to controllably deposit the semiconductor in a metered fashion.« less

Development of microchannel plate x-ray optics

NASA Technical Reports Server (NTRS)

Kaaret, Philip; Chen, Andrew

1994-01-01

The goal of this research program was to develop a novel technique for focusing x-rays based on the optical system of a lobster's eye. A lobster eye employs many closely packed reflecting surfaces arranged within a spherical or cylindrical shell. These optics have two unique properties: they have unlimited fields of view and can be manufactured via replication of identical structures. Because the angular resolution is given by the ratio of the size of the individual optical elements to the focal length, optical elements with sizes on the order of one hundred microns are required to achieve good angular resolution with a compact telescope. We employed anisotropic etching of single crystal silicon wafers for the fabrication of micron-scale optical elements. This technique, commonly referred to as silicon micromachining, is based on silicon fabrication techniques developed by the microelectronics industry. An anisotropic etchant is a chemical which etches certain silicon crystal planes much more rapidly than others. Using wafers in which the slowly etched crystal planes are aligned perpendicularly to the wafer surface, it is possible to etch a pattern completely through a wafer with very little distortion. Our optics consist of rectangular pores etched completely through group of zone axes (110) oriented silicon wafers. The larger surfaces of the pores (the mirror elements) were aligned with the group of zone axes (111) planes of the crystal perpendicular to the wafer surface. We have succeeded in producing silicon lenses with a geometry suitable for 1-d focusing x-ray optics. These lenses have an aspect ratio (40:1) suitable for x-ray reflection and have very good optical surface alignment. We have developed a number of process refinements which improved the quality of the lens geometry and the repeatability of the etch process. A significant progress was made in obtaining good optical surface quality. The RMS roughness was decreased from 110 A for our initial lenses to 30 A in the final lenses. A further factor of three improvement in surface quality is required for the production of efficient x-ray optics. In addition to the silicon fabrication, an x-ray beam line was constructed at Columbia for testing the optics.

Roll up nanowire battery from silicon chips

PubMed Central

Vlad, Alexandru; Reddy, Arava Leela Mohana; Ajayan, Anakha; Singh, Neelam; Gohy, Jean-François; Melinte, Sorin; Ajayan, Pulickel M.

2012-01-01

Here we report an approach to roll out Li-ion battery components from silicon chips by a continuous and repeatable etch-infiltrate-peel cycle. Vertically aligned silicon nanowires etched from recycled silicon wafers are captured in a polymer matrix that operates as Li+ gel-electrolyte and electrode separator and peeled off to make multiple battery devices out of a single wafer. Porous, electrically interconnected copper nanoshells are conformally deposited around the silicon nanowires to stabilize the electrodes over extended cycles and provide efficient current collection. Using the above developed process we demonstrate an operational full cell 3.4 V lithium-polymer silicon nanowire (LIPOSIL) battery which is mechanically flexible and scalable to large dimensions. PMID:22949696

Dual-Mode Nuclear Radiation Particle Detector

NASA Astrophysics Data System (ADS)

Zhang, Yali

The design and fabrication of a "dual-mode" nuclear radiation detector using planar silicon technology is described. The device operates at 0.3 K and detects simultaneously the ionization and the phonons produced by nuclear radiation interacting in the substrate. The intended purpose of the device is to detect atomic silicon recoils from the scattering of massive neutral particles that are hypothesized to compose the dark matter halo of our galaxy. The "dual mode" functionality was designed to permit atomic recoils to be distinguished event-by-event from the background due to unavoidable low-level radioactivity in the detector and its surroundings. The device consists of a back contact biased negatively relative to a comb-shaped electrode structure on the opposite face of a high purity wafer. The spacing of the comb teeth is less than the wafer thickness, providing a uniform charge collection electric field throughout most of the wafer volume. Between the teeth of the comb are superconducting transition edge devices consisting of serpentines of 400 A thick, 2 μm wide Ti lines separated by 3 μm spaces. Investigations of ionization-detecting metal-on -silicon contacts at low temperatures are described, including diffused junctions, Au on Si, Au on oxidized Si, and Ti on Si. Diode characteristics continue to change qualitatively at temperatures below 4 K. The destruction of superconductivity in Ti by Au contamination during microfabrication procedures is also reported.

A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits

NASA Astrophysics Data System (ADS)

Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M.; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K.; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

2017-12-01

One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

Fabrication and Modification of Nanoporous Silicon Particles

NASA Technical Reports Server (NTRS)

Ferrari, Mauro; Liu, Xuewu

2010-01-01

Silicon-based nanoporous particles as biodegradable drug carriers are advantageous in permeation, controlled release, and targeting. The use of biodegradable nanoporous silicon and silicon dioxide, with proper surface treatments, allows sustained drug release within the target site over a period of days, or even weeks, due to selective surface coating. A variety of surface treatment protocols are available for silicon-based particles to be stabilized, functionalized, or modified as required. Coated polyethylene glycol (PEG) chains showed the effective depression of both plasma protein adsorption and cell attachment to the modified surfaces, as well as the advantage of long circulating. Porous silicon particles are micromachined by lithography. Compared to the synthesis route of the nanomaterials, the advantages include: (1) the capability to make different shapes, not only spherical particles but also square, rectangular, or ellipse cross sections, etc.; (2) the capability for very precise dimension control; (3) the capacity for porosity and pore profile control; and (4) allowance of complex surface modification. The particle patterns as small as 60 nm can be fabricated using the state-of-the-art photolithography. The pores in silicon can be fabricated by exposing the silicon in an HF/ethanol solution and then subjecting the pores to an electrical current. The size and shape of the pores inside silicon can be adjusted by the doping of the silicon, electrical current application, the composition of the electrolyte solution, and etching time. The surface of the silicon particles can be modified by many means to provide targeted delivery and on-site permanence for extended release. Multiple active agents can be co-loaded into the particles. Because the surface modification of particles can be done on wafers before the mechanical release, asymmetrical surface modification is feasible. Starting from silicon wafers, a treatment, such as KOH dipping or reactive ion etching (RIE), may be applied to make the surface rough. This helps remove the nucleation layer. A protective layer is then deposited on the wafer. The protective layer, such as silicon nitride film or photoresist film, protects the wafer from electrochemical etching in an HF-based solution. A lithography technique is applied to pattern the particles onto the protective film. The undesired area of the protective film is removed, and the protective film on the back side of the wafer is also removed. Then the pattern is exposed to HF/surfactant solution, and a larger DC electrical current is applied to the wafers for a selected time. This step removes the nucleation layer. Then a DC current is applied to generate the nanopores. Next, a large electrical current is applied to generate a release layer. The particles are mechanically suspended in the solvent and collected by filtration or centrifuge.

Sol-Gel Deposited Double Layer TiO₂ and Al₂O₃ Anti-Reflection Coating for Silicon Solar Cell.

PubMed

Jung, Jinsu; Jannat, Azmira; Akhtar, M Shaheer; Yang, O-Bong

2018-02-01

In this work, the deposition of double layer ARC on p-type Si solar cells was carried out by simple spin coating using sol-gel derived Al2O3 and TiO2 precursors for the fabrication of crystalline Si solar cells. The first ARC layer was created by freshly prepared sol-gel derived Al2O3 precursor using spin coating technique and then second ARC layer of TiO2 was deposited with sol-gel derived TiO2 precursor, which was finally annealed at 400 °C. The double layer Al2O3/TiO2 ARC on Si wafer exhibited the low average reflectance of 4.74% in the wavelength range of 400 and 1000 nm. The fabricated solar cells based on double TiO2/Al2O3 ARC attained the conversion efficiency of ~13.95% with short circuit current (JSC) of 35.27 mA/cm2, open circuit voltage (VOC) of 593.35 mV and fill factor (FF) of 66.67%. Moreover, the fabricated solar cells presented relatively low series resistance (Rs) as compared to single layer ARCs, resulting in the high VOC and FF.

Nano-Photonic Structures for Light Trapping in Ultra-Thin Crystalline Silicon Solar Cells

PubMed Central

Pathi, Prathap; Peer, Akshit; Biswas, Rana

2017-01-01

Thick wafer-silicon is the dominant solar cell technology. It is of great interest to develop ultra-thin solar cells that can reduce materials usage, but still achieve acceptable performance and high solar absorption. Accordingly, we developed a highly absorbing ultra-thin crystalline Si based solar cell architecture using periodically patterned front and rear dielectric nanocone arrays which provide enhanced light trapping. The rear nanocones are embedded in a silver back reflector. In contrast to previous approaches, we utilize dielectric photonic crystals with a completely flat silicon absorber layer, providing expected high electronic quality and low carrier recombination. This architecture creates a dense mesh of wave-guided modes at near-infrared wavelengths in the absorber layer, generating enhanced absorption. For thin silicon (<2 μm) and 750 nm pitch arrays, scattering matrix simulations predict enhancements exceeding 90%. Absorption approaches the Lambertian limit at small thicknesses (<10 μm) and is slightly lower (by ~5%) at wafer-scale thicknesses. Parasitic losses are ~25% for ultra-thin (2 μm) silicon and just 1%–2% for thicker (>100 μm) cells. There is potential for 20 μm thick cells to provide 30 mA/cm2 photo-current and >20% efficiency. This architecture has great promise for ultra-thin silicon solar panels with reduced material utilization and enhanced light-trapping. PMID:28336851

The dual role of silver during silicon etching in HF solution

PubMed Central

2012-01-01

It was reported that during silicon etching, silver was subjected to have a controversial role. Some researchers debate that silver protects silicon, and, at the same time, other ones confirm that silver catalyzes silicon underneath. In this paper, we give experimental results arguing the dual role that silver has during the formation of silicon nanostructures. We give a proof that the role of silver depends on the experimental details and the intrinsic properties of silver during its deposition on the silicon wafer. Through our investigations, we tracked the silver particles that indicated which mechanism is involved. Characterizations of the prepared samples were made using a scanning electron microscope. PMID:22888998

Hydrogen ion microlithography

DOEpatents

Tsuo, Y.S.; Deb, S.K.

1990-10-02

Disclosed is a hydrogen ion microlithography process for use in microelectronic fabrication and semiconductor device processing. The process comprises the steps of providing a single layer of either an amorphous silicon or hydrogenated amorphous silicon material. A pattern is recorded in a selected layer of amorphous silicon or hydrogenated amorphous silicon materials by preferentially implanting hydrogen ions therein so as to permit the selected layer to serve as a mask-resist wafer suitable for subsequent development and device fabrication. The layer is developed to provide a surface pattern therein adaptable for subsequent use in microelectronic fabrication and semiconductor device processing. 6 figs.

Oxidation of silicon with a 5 eV O(-) beam

NASA Technical Reports Server (NTRS)

Hecht, M. H.; Orient, O. J.; Chutjian, A.; Vasquez, R. P.

1989-01-01

A silicon wafer has been oxidized at room temperature in vacuum using a pure, ground-state beam of O(-) ions. The beam was of sufficiently low energy that no displacement damage or implantation was energetically possible. The resulting SiO2 films were analyzed with X-ray photoelectron spectroscopy. A logarithmic dependence of oxide thickness on dose was observed, with an extrapolated oxidation efficiency of unity for the clean silicon surface. A distinct initial oxidation phase was observed, with an anomalously high level of silicon suboxides. In addition, the valence-band offset between the silicon and the oxide was unusually small, suggesting a large interfacial dipole.

Fabrication and characterization of physically defined quantum dots on a boron-doped silicon-on-insulator substrate

NASA Astrophysics Data System (ADS)

Mizoguchi, Seiya; Shimatani, Naoki; Kobayashi, Mizuki; Makino, Takaomi; Yamaoka, Yu; Kodera, Tetsuo

2018-04-01

We study hole transport properties in physically defined p-type silicon quantum dots (QDs) on a heavily doped silicon-on-insulator (SOI) substrate. We observe Coulomb diamonds using single QDs and estimate the charging energy as ∼1.6 meV. We obtain the charge stability diagram of double QDs using single QDs as a charge sensor. This is the first demonstration of charge sensing in p-type heavily doped silicon QDs. For future time-resolved measurements, we apply radio-frequency reflectometry using impedance matching of LC circuits to the device. We observe the resonance and estimate the capacitance as ∼0.12 pF from the resonant frequency. This value is smaller than that of the devices with top gates on nondoped SOI substrate. This indicates that high-frequency signals can be applied efficiently to p-type silicon QDs without top gates.

Organ-on-a-Chip for Aerospace Physiology and Toxicology

DTIC Science & Technology

2014-12-15

Products (Chicago, IL) supplied the Laboratory Corona Treater. Silicon wafers, 3” with > orientation were obtained from Wafer World Incorporated...was flowed at a process pressure of 500 mT. The plasma was ignited at discharge power of 250 W at 30 kHz and allowed to run for 1 minute. The wafer...slide and PDMS channel surfaces was performed one of two ways. Either using a handheld corona tool operated in a chemical safety hood or the PDMS slabs

Guided ultrasonic wave beam skew in silicon wafers

NASA Astrophysics Data System (ADS)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2018-04-01

In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

P-Type Silicon Strip Sensors for the new CMS Tracker at HL-LHC

NASA Astrophysics Data System (ADS)

Adam, W.; Bergauer, T.; Brondolin, E.; Dragicevic, M.; Friedl, M.; Frühwirth, R.; Hoch, M.; Hrubec, J.; König, A.; Steininger, H.; Waltenberger, W.; Alderweireldt, S.; Beaumont, W.; Janssen, X.; Lauwers, J.; Van Mechelen, P.; Van Remortel, N.; Van Spilbeeck, A.; Beghin, D.; Brun, H.; Clerbaux, B.; Delannoy, H.; De Lentdecker, G.; Fasanella, G.; Favart, L.; Goldouzian, R.; Grebenyuk, A.; Karapostoli, G.; Lenzi, Th.; Léonard, A.; Luetic, J.; Postiau, N.; Seva, T.; Vanlaer, P.; Vannerom, D.; Wang, Q.; Zhang, F.; Abu Zeid, S.; Blekman, F.; De Bruyn, I.; De Clercq, J.; D'Hondt, J.; Deroover, K.; Lowette, S.; Moortgat, S.; Moreels, L.; Python, Q.; Skovpen, K.; Van Mulders, P.; Van Parijs, I.; Bakhshiansohi, H.; Bondu, O.; Brochet, S.; Bruno, G.; Caudron, A.; Delaere, C.; Delcourt, M.; De Visscher, S.; Francois, B.; Giammanco, A.; Jafari, A.; Komm, M.; Krintiras, G.; Lemaitre, V.; Magitteri, A.; Mertens, A.; Michotte, D.; Musich, M.; Piotrzkowski, K.; Quertenmont, L.; Szilasi, N.; Vidal Marono, M.; Wertz, S.; Beliy, N.; Caebergs, T.; Daubie, E.; Hammad, G. H.; Härkönen, J.; Lampén, T.; Luukka, P.; Peltola, T.; Tuominen, E.; Tuovinen, E.; Eerola, P.; Tuuva, T.; Baulieu, G.; Boudoul, G.; Caponetto, L.; Combaret, C.; Contardo, D.; Dupasquier, T.; Gallbit, G.; Lumb, N.; Mirabito, L.; Perries, S.; Vander Donckt, M.; Viret, S.; Agram, J.-L.; Andrea, J.; Bloch, D.; Bonnin, C.; Brom, J.-M.; Chabert, E.; Chanon, N.; Charles, L.; Conte, E.; Fontaine, J.-Ch.; Gross, L.; Hosselet, J.; Jansova, M.; Tromson, D.; Autermann, C.; Feld, L.; Karpinski, W.; Kiesel, K. M.; Klein, K.; Lipinski, M.; Ostapchuk, A.; Pierschel, G.; Preuten, M.; Rauch, M.; Schael, S.; Schomakers, C.; Schulz, J.; Schwering, G.; Wlochal, M.; Zhukov, V.; Pistone, C.; Fluegge, G.; Kuensken, A.; Pooth, O.; Stahl, A.; Aldaya, M.; Asawatangtrakuldee, C.; Beernaert, K.; Bertsche, D.; Contreras-Campana, C.; Eckerlin, G.; Eckstein, D.; Eichhorn, T.; Gallo, E.; Garay Garcia, J.; Hansen, K.; Haranko, M.; Harb, A.; Hauk, J.; Keaveney, J.; Kalogeropoulos, A.; Kleinwort, C.; Lohmann, W.; Mankel, R.; Maser, H.; Mittag, G.; Muhl, C.; Mussgiller, A.; Pitzl, D.; Reichelt, O.; Savitskyi, M.; Schuetze, P.; Walsh, R.; Zuber, A.; Biskop, H.; Buhmann, P.; Centis-Vignali, M.; Garutti, E.; Haller, J.; Hoffmann, M.; Lapsien, T.; Matysek, M.; Perieanu, A.; Scharf, Ch.; Schleper, P.; Schmidt, A.; Schwandt, J.; Sonneveld, J.; Steinbrück, G.; Vormwald, B.; Wellhausen, J.; Abbas, M.; Amstutz, C.; Barvich, T.; Barth, Ch.; Boegelspacher, F.; De Boer, W.; Butz, E.; Caselle, M.; Colombo, F.; Dierlamm, A.; Freund, B.; Hartmann, F.; Heindl, S.; Husemann, U.; Kornmayer, A.; Kudella, S.; Muller, Th.; Simonis, H. J.; Steck, P.; Weber, M.; Weiler, Th.; Anagnostou, G.; Asenov, P.; Assiouras, P.; Daskalakis, G.; Kyriakis, A.; Loukas, D.; Paspalaki, L.; Siklér, F.; Veszprémi, V.; Bhardwaj, A.; Dalal, R.; Jain, G.; Ranjan, K.; Bakhshiansohl, H.; Behnamian, H.; Khakzad, M.; Naseri, M.; Cariola, P.; Creanza, D.; De Palma, M.; De Robertis, G.; Fiore, L.; Franco, M.; Loddo, F.; Silvestris, L.; Maggi, G.; Martiradonna, S.; My, S.; Selvaggi, G.; Albergo, S.; Cappello, G.; Chiorboli, M.; Costa, S.; Di Mattia, A.; Giordano, F.; Potenza, R.; Saizu, M. A.; Tricomi, A.; Tuve, C.; Barbagli, G.; Brianzi, M.; Ciaranfi, R.; Ciulli, V.; Civinini, C.; D'Alessandro, R.; Focardi, E.; Latino, G.; Lenzi, P.; Meschini, M.; Paoletti, S.; Russo, L.; Scarlini, E.; Sguazzoni, G.; Strom, D.; Viliani, L.; Ferro, F.; Lo Vetere, M.; Robutti, E.; Dinardo, M. E.; Fiorendi, S.; Gennai, S.; Malvezzi, S.; Manzoni, R. A.; Menasce, D.; Moroni, L.; Pedrini, D.; Azzi, P.; Bacchetta, N.; Bisello, D.; Dall'Osso, M.; Pozzobon, N.; Tosi, M.; De Canio, F.; Gaioni, L.; Manghisoni, M.; Nodari, B.; Riceputi, E.; Re, V.; Traversi, G.; Comotti, D.; Ratti, L.; Alunni Solestizi, L.; Biasini, M.; Bilei, G. M.; Cecchi, C.; Checcucci, B.; Ciangottini, D.; Fanò, L.; Gentsos, C.; Ionica, M.; Leonardi, R.; Manoni, E.; Mantovani, G.; Marconi, S.; Mariani, V.; Menichelli, M.; Modak, A.; Morozzi, A.; Moscatelli, F.; Passeri, D.; Placidi, P.; Postolache, V.; Rossi, A.; Saha, A.; Santocchia, A.; Storchi, L.; Spiga, D.; Androsov, K.; Azzurri, P.; Arezzini, S.; Bagliesi, G.; Basti, A.; Boccali, T.; Borrello, L.; Bosi, F.; Castaldi, R.; Ciampa, A.; Ciocci, M. A.; Dell'Orso, R.; Donato, S.; Fedi, G.; Giassi, A.; Grippo, M. T.; Ligabue, F.; Lomtadze, T.; Magazzu, G.; Martini, L.; Mazzoni, E.; Messineo, A.; Moggi, A.; Morsani, F.; Palla, F.; Palmonari, F.; Raffaelli, F.; Rizzi, A.; Savoy-Navarro, A.; Spagnolo, P.; Tenchini, R.; Tonelli, G.; Venturi, A.; Verdini, P. G.; Bellan, R.; Costa, M.; Covarelli, R.; Da Rocha Rolo, M.; Demaria, N.; Rivetti, A.; Dellacasa, G.; Mazza, G.; Migliore, E.; Monteil, E.; Pacher, L.; Ravera, F.; Solano, A.; Fernandez, M.; Gomez, G.; Jaramillo Echeverria, R.; Moya, D.; Gonzalez Sanchez, F. J.; Vila, I.; Virto, A. L.; Abbaneo, D.; Ahmed, I.; Albert, E.; Auzinger, G.; Berruti, G.; Bianchi, G.; Blanchot, G.; Bonnaud, J.; Caratelli, A.; Ceresa, D.; Christiansen, J.; Cichy, K.; Daguin, J.; D'Auria, A.; Detraz, S.; Deyrail, D.; Dondelewski, O.; Faccio, F.; Frank, N.; Gadek, T.; Gill, K.; Honma, A.; Hugo, G.; Jara Casas, L. M.; Kaplon, J.; Kornmayer, A.; Kottelat, L.; Kovacs, M.; Krammer, M.; Lenoir, P.; Mannelli, M.; Marchioro, A.; Marconi, S.; Mersi, S.; Martina, S.; Michelis, S.; Moll, M.; Onnela, A.; Orfanelli, S.; Pavis, S.; Peisert, A.; Pernot, J.-F.; Petagna, P.; Petrucciani, G.; Postema, H.; Rose, P.; Tropea, P.; Troska, J.; Tsirou, A.; Vasey, F.; Vichoudis, P.; Verlaat, B.; Zwalinski, L.; Bachmair, F.; Becker, R.; di Calafiori, D.; Casal, B.; Berger, P.; Djambazov, L.; Donega, M.; Grab, C.; Hits, D.; Hoss, J.; Kasieczka, G.; Lustermann, W.; Mangano, B.; Marionneau, M.; Martinez Ruiz del Arbol, P.; Masciovecchio, M.; Meinhard, M.; Perozzi, L.; Roeser, U.; Starodumov, A.; Tavolaro, V.; Wallny, R.; Zhu, D.; Amsler, C.; Bösiger, K.; Caminada, L.; Canelli, F.; Chiochia, V.; de Cosa, A.; Galloni, C.; Hreus, T.; Kilminster, B.; Lange, C.; Maier, R.; Ngadiuba, J.; Pinna, D.; Robmann, P.; Taroni, S.; Yang, Y.; Bertl, W.; Deiters, K.; Erdmann, W.; Horisberger, R.; Kaestli, H.-C.; Kotlinski, D.; Langenegger, U.; Meier, B.; Rohe, T.; Streuli, S.; Cussans, D.; Flacher, H.; Goldstein, J.; Grimes, M.; Jacob, J.; Seif El Nasr-Storey, S.; Cole, J.; Hoad, C.; Hobson, P.; Morton, A.; Reid, I. D.; Auzinger, G.; Bainbridge, R.; Dauncey, P.; Hall, G.; James, T.; Magnan, A.-M.; Pesaresi, M.; Raymond, D. M.; Uchida, K.; Garabedian, A.; Heintz, U.; Narain, M.; Nelson, J.; Sagir, S.; Speer, T.; Swanson, J.; Tersegno, D.; Watson-Daniels, J.; Chertok, M.; Conway, J.; Conway, R.; Flores, C.; Lander, R.; Pellett, D.; Ricci-Tam, F.; Squires, M.; Thomson, J.; Yohay, R.; Burt, K.; Ellison, J.; Hanson, G.; Olmedo, M.; Si, W.; Yates, B. R.; Gerosa, R.; Sharma, V.; Vartak, A.; Yagil, A.; Zevi Della Porta, G.; Dutta, V.; Gouskos, L.; Incandela, J.; Kyre, S.; Mullin, S.; Patterson, A.; Qu, H.; White, D.; Dominguez, A.; Bartek, R.; Cumalat, J. P.; Ford, W. T.; Jensen, F.; Johnson, A.; Krohn, M.; Leontsinis, S.; Mulholland, T.; Stenson, K.; Wagner, S. R.; Apresyan, A.; Bolla, G.; Burkett, K.; Butler, J. N.; Canepa, A.; Cheung, H. W. K.; Chramowicz, J.; Christian, D.; Cooper, W. E.; Deptuch, G.; Derylo, G.; Gingu, C.; Grünendahl, S.; Hasegawa, S.; Hoff, J.; Howell, J.; Hrycyk, M.; Jindariani, S.; Johnson, M.; Kahlid, F.; Lei, C. M.; Lipton, R.; Lopes De Sá, R.; Liu, T.; Los, S.; Matulik, M.; Merkel, P.; Nahn, S.; Prosser, A.; Rivera, R.; Schneider, B.; Sellberg, G.; Shenai, A.; Spiegel, L.; Tran, N.; Uplegger, L.; Voirin, E.; Berry, D. R.; Chen, X.; Ennesser, L.; Evdokimov, A.; Evdokimov, O.; Gerber, C. E.; Hofman, D. J.; Makauda, S.; Mills, C.; Sandoval Gonzalez, I. D.; Alimena, J.; Antonelli, L. J.; Francis, B.; Hart, A.; Hill, C. S.; Parashar, N.; Stupak, J.; Bortoletto, D.; Bubna, M.; Hinton, N.; Jones, M.; Miller, D. H.; Shi, X.; Tan, P.; Baringer, P.; Bean, A.; Khalil, S.; Kropivnitskaya, A.; Majumder, D.; Wilson, G.; Ivanov, A.; Mendis, R.; Mitchell, T.; Skhirtladze, N.; Taylor, R.; Anderson, I.; Fehling, D.; Gritsan, A.; Maksimovic, P.; Martin, C.; Nash, K.; Osherson, M.; Swartz, M.; Xiao, M.; Bloom, K.; Claes, D. R.; Fangmeier, C.; Gonzalez Suarez, R.; Monroy, J.; Siado, J.; Hahn, K.; Sevova, S.; Sung, K.; Trovato, M.; Bartz, E.; Gershtein, Y.; Halkiadakis, E.; Kyriacou, S.; Lath, A.; Nash, K.; Osherson, M.; Schnetzer, S.; Stone, R.; Walker, M.; Malik, S.; Norberg, S.; Ramirez Vargas, J. E.; Alyari, M.; Dolen, J.; Godshalk, A.; Harrington, C.; Iashvili, I.; Kharchilava, A.; Nguyen, D.; Parker, A.; Rappoccio, S.; Roozbahani, B.; Alexander, J.; Chaves, J.; Chu, J.; Dittmer, S.; McDermott, K.; Mirman, N.; Rinkevicius, A.; Ryd, A.; Salvati, E.; Skinnari, L.; Soffi, L.; Tao, Z.; Thom, J.; Tucker, J.; Zientek, M.; Akgün, B.; Ecklund, K. M.; Kilpatrick, M.; Nussbaum, T.; Zabel, J.; Betchart, B.; Covarelli, R.; Demina, R.; Hindrichs, O.; Petrillo, G.; Eusebi, R.; Osipenkov, I.; Perloff, A.; Ulmer, K. A.

2017-06-01

The upgrade of the LHC to the High-Luminosity LHC (HL-LHC) is expected to increase the LHC design luminosity by an order of magnitude. This will require silicon tracking detectors with a significantly higher radiation hardness. The CMS Tracker Collaboration has conducted an irradiation and measurement campaign to identify suitable silicon sensor materials and strip designs for the future outer tracker at the CMS experiment. Based on these results, the collaboration has chosen to use n-in-p type silicon sensors and focus further investigations on the optimization of that sensor type. This paper describes the main measurement results and conclusions that motivated this decision.

A CWDM photoreceiver module for 10 Gb/s x 4ch interconnection based on a vertical-illumination-type Ge-on-Si photodetectors and a silica-based AWG

NASA Astrophysics Data System (ADS)

Jang, Ki-Seok; Joo, Jiho; Kim, Taeyong; Kim, Sanghoon; Oh, Jin Hyuk; Kim, In Gyoo; Kim, Sun Ae; Kim, Gyungock

2015-03-01

We report a 40 Gb/s photoreceiver based on vertical-illumination type Ge-on-Si photodetectors and a silica-based AWG demultiplexer by employing 4-channel CWDM. The 60um-diameter Ge-on-Si photodetector arrays, grown on a bulk silicon wafer by RPCVD and fabricated with CMOS-compatible process, have ~0.9 A/W responsivity with 13 GHz bandwidth at λ ~ 1330nm. Ge-on-Si photodetector arrays are hybrid-integrated with TIA/LAs and directly-coupled to the AWG. The low-cost FPCB-package based photoreceiver module shows 10.3 Gb/s × 4-channel interconnection with -11 ~ -12.2 dBm sensitivity at a BER = 10-12.

Performance study of double SOI image sensors

NASA Astrophysics Data System (ADS)

Miyoshi, T.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Hara, K.; Ikegami, Y.; Kurachi, I.; Nishimura, R.; Ono, S.; Tauchi, K.; Tsuboyama, T.; Yamada, M.

2018-02-01

Double silicon-on-insulator (DSOI) sensors composed of two thin silicon layers and one thick silicon layer have been developed since 2011. The thick substrate consists of high resistivity silicon with p-n junctions while the thin layers are used as SOI-CMOS circuitry and as shielding to reduce the back-gate effect and crosstalk between the sensor and the circuitry. In 2014, a high-resolution integration-type pixel sensor, INTPIX8, was developed based on the DSOI concept. This device is fabricated using a Czochralski p-type (Cz-p) substrate in contrast to a single SOI (SSOI) device having a single thin silicon layer and a Float Zone p-type (FZ-p) substrate. In the present work, X-ray spectra of both DSOI and SSOI sensors were obtained using an Am-241 radiation source at four gain settings. The gain of the DSOI sensor was found to be approximately three times that of the SSOI device because the coupling capacitance is reduced by the DSOI structure. An X-ray imaging demonstration was also performed and high spatial resolution X-ray images were obtained.

Sidewall patterning—a new wafer-scale method for accurate patterning of vertical silicon structures

NASA Astrophysics Data System (ADS)

Westerik, P. J.; Vijselaar, W. J. C.; Berenschot, J. W.; Tas, N. R.; Huskens, J.; Gardeniers, J. G. E.

2018-01-01

For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that allows for reproducible sub-micrometer resolution local modification along vertical silicon sidewalls. Instead of optical lithography, this method makes smart use of inclined ion beam etching to selectively etch the top parts of structures, and controlled retraction of a conformal layer to define a hard mask in the vertical direction. The top, bottom or middle part of a structure could be selectively exposed, and it was shown that these exposed regions can, for example, be selectively covered with a catalyst, doped, or structured further.

Characterization of silicon heterojunctions for solar cells

PubMed Central

2011-01-01

Conductive-probe atomic force microscopy (CP-AFM) measurements reveal the existence of a conductive channel at the interface between p-type hydrogenated amorphous silicon (a-Si:H) and n-type crystalline silicon (c-Si) as well as at the interface between n-type a-Si:H and p-type c-Si. This is in good agreement with planar conductance measurements that show a large interface conductance. It is demonstrated that these features are related to the existence of a strong inversion layer of holes at the c-Si surface of (p) a-Si:H/(n) c-Si structures, and to a strong inversion layer of electrons at the c-Si surface of (n) a-Si:H/(p) c-Si heterojunctions. These are intimately related to the band offsets, which allows us to determine these parameters with good precision. PMID:21711658

Lasers in energy device manufacturing

NASA Astrophysics Data System (ADS)

Ostendorf, A.; Schoonderbeek, A.

2008-02-01

Global warming is a current topic all over the world. CO II emissions must be lowered to stop the already started climate change. Developing regenerative energy sources, like photovoltaics and fuel cells contributes to the solution of this problem. Innovative technologies and strategies need to be competitive with conventional energy sources. During the last years, the photovoltaic solar cell industry has experienced enormous growth. However, for solar cells to be competitive on the longer term, both an increase in efficiency as well as reduction in costs is necessary. An effective method to reduce costs of silicon solar cells is reducing the wafer thickness, because silicon makes up a large part of production costs. Consequently, contact free laser processing has a large advantage, because of the decrease in waste materials due to broken wafers as caused by other manufacturing processes. Additionally, many novel high efficiency solar cell concepts are only economically feasible with laser technology, e.g. for scribing silicon thin-film solar cells. This paper describes laser hole drilling, structuring and texturing of silicon wafer based solar cells and describes thin film solar cell scribing. Furthermore, different types of lasers are discussed with respect to processing quality and time.

Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

NASA Astrophysics Data System (ADS)

Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

2018-03-01

It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up to 7KW. The wafer surface is coated with Yttrium oxide film which allows Silicon Etch chemistry. At Fab-8, we carried investigations in 14 nm FEOL critical etch process which has direct impact on yield, using SensorArray EtchTemp-SE wafer, we measured ESC temperature profile across multiple chambers, for both plasma on and plasma off, promising results achieved on chamber temperature signature identification, guideline for chamber to chamber matching improvement. Correlation between wafer mean temperature and determining criticality-process parameters of recess depth and CD is observed. Furthermore, detail zonal temperature/profile correlation is investigated to identify individual correlation in each chuck zone, and provided unique process knobs corresponding to each chunk. Meanwhile, passive ESC Chuck DOE was done to modulate wafer temperature at different zones, and Sensor Array wafer measurements verified temperature responding well with the ESC set point. Correlation R2 = 0.9979 for outer ring and R2 = 0.9981 for Mid Outer ring is observed, as shown in . Experiments planning to modulate edge zone ESC temperature to tune profile within-wafer uniformity and prove gain in edge yield enhancement and to improve edge yield is underway.

Microhardness of carbon-doped (111) p-type Czochralski silicon

NASA Technical Reports Server (NTRS)

Danyluk, S.; Lim, D. S.; Kalejs, J.

1985-01-01

The effect of carbon on (111) p-type Czochralski silicon is examined. The preparation of the silicon and microhardness test procedures are described, and the equation used to determine microhardness from indentations in the silicon wafers is presented. The results indicate that as the carbon concentration in the silicon increases the microhardness increases. The linear increase in microhardness is the result of carbon hindering dislocation motion, and the effect of temperature on silicon deformation and dislocation mobility is explained. The measured microhardness was compared with an analysis which is based on dislocation pinning by carbon; a good correlation was observed. The Labusch model for the effect of pinning sites on dislocation motion is given.

Dual ohmic contact to N- and P-type silicon carbide

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2013-01-01

Simultaneous formation of electrical ohmic contacts to silicon carbide (SiC) semiconductor having donor and acceptor impurities (n- and p-type doping, respectively) is disclosed. The innovation provides for ohmic contacts formed on SiC layers having n- and p-doping at one process step during the fabrication of the semiconductor device. Further, the innovation provides a non-discriminatory, universal ohmic contact to both n- and p-type SiC, enhancing reliability of the specific contact resistivity when operated at temperatures in excess of 600.degree. C.

A micro-scale plasma spectrometer for space and plasma edge applications (invited)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Scime, E. E., E-mail: escime@wvu.edu; Keesee, A. M.; Elliott, D.

2016-11-15

A plasma spectrometer design based on advances in lithography and microchip stacking technologies is described. A series of curved plate energy analyzers, with an integrated collimator, is etched into a silicon wafer. Tests of spectrometer elements, the energy analyzer and collimator, were performed with a 5 keV electron beam. The measured collimator transmission and energy selectivity were in good agreement with design targets. A single wafer element could be used as a plasma processing or fusion first wall diagnostic.

Porous silicon carbide (SIC) semiconductor device

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1996-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Hot embossed polyethylene through-hole chips for bead-based microfluidic devices.

PubMed

Chou, Jie; Du, Nan; Ou, Tina; Floriano, Pierre N; Christodoulides, Nicolaos; McDevitt, John T

2013-04-15

Over the past decade, there has been a growth of interest in the translation of microfluidic systems into real-world clinical practice, especially for use in point-of-care or near patient settings. While initial fabrication advances in microfluidics involved mainly the etching of silicon and glass, the economics of scaling of these materials is not amendable for point-of-care usage where single-test applications force cost considerations to be kept low and throughput high. As such, materials base more consistent with point-of-care needs is required. In this manuscript, the fabrication of a hot embossed, through-hole low-density polyethylene ensembles derived from an anisotropically etched silicon wafer is discussed. This semi-opaque polymer that can be easily sterilized and recycled provides low background noise for fluorescence measurements and yields more affordable cost than other thermoplastics commonly used for microfluidic applications such as cyclic olefin copolymer (COC). To fabrication through-hole microchips from this alternative material for microfluidics, a fabrication technique that uses a high-temperature, high-pressure resistant mold is described. This aluminum-based epoxy mold, serving as the positive master mold for embossing, is casted over etched arrays of pyramidal pits in a silicon wafer. Methods of surface treatment of the wafer prior to casting and PDMS casting of the epoxy are discussed to preserve the silicon wafer for future use. Changes in the thickness of polyethylene are observed for varying embossing temperatures. The methodology described herein can quickly fabricate 20 disposable, single use chips in less than 30 min with the ability to scale up 4 times by using multiple molds simultaneously. When coupled as a platform supporting porous bead sensors, as in the recently developed Programmable Bio-Nano-Chip, this bead chip system can achieve limits of detection, for the cardiac biomarker C-reactive protein, of 0.3 ng/mL, thereby demonstrating that the approach is compatible with high performance, real-world clinical measurements in the context of point-of-care testing. Copyright © 2012 Elsevier B.V. All rights reserved.

Glass-silicon column

DOEpatents

Yu, Conrad M.

2003-12-30

A glass-silicon column that can operate in temperature variations between room temperature and about 450.degree. C. The glass-silicon column includes large area glass, such as a thin Corning 7740 boron-silicate glass bonded to a silicon wafer, with an electrode embedded in or mounted on glass of the column, and with a self alignment silicon post/glass hole structure. The glass/silicon components are bonded, for example be anodic bonding. In one embodiment, the column includes two outer layers of silicon each bonded to an inner layer of glass, with an electrode imbedded between the layers of glass, and with at least one self alignment hole and post arrangement. The electrode functions as a column heater, and one glass/silicon component is provided with a number of flow channels adjacent the bonded surfaces.

Commercial silicon-on-insulator (SOI) wafers as a versatile substrate for laser desorption/ionization mass spectrometry.

PubMed

Kim, Shin Hye; Kim, Jeongkwon; Moon, Dae Won; Han, Sang Yun

2013-01-01

We report here that a commercial silicon-on-insulator (SOI) wafer offers an opportunity for laser desorption/ionization (LDI) of peptide molecules, which occurs directly from its flat surface without requiring special surface preparation. The LDI-on-SOI exhibits intact ionization of peptides with a good detection limit of lower than 20 fmol, of which the mass range is demonstrated up to insulin with citric acid additives. The LDI process most likely arises from laser-induced surface heating promoted by two-dimensional thermal confinement in the thin Si surface layer of the SOI wafer. As a consequence of the thermal process, the LDI-on-SOI method is also capable of creating post-source decay (PSD) of the resulting peptide LDI ions, which is suitable for peptide sequencing using conventional TOF/TOF mass spectrometry.

Silicon photonics: some remaining challenges

NASA Astrophysics Data System (ADS)

Reed, G. T.; Topley, R.; Khokhar, A. Z.; Thompson, D. J.; Stanković, S.; Reynolds, S.; Chen, X.; Soper, N.; Mitchell, C. J.; Hu, Y.; Shen, L.; Martinez-Jimenez, G.; Healy, N.; Mailis, S.; Peacock, A. C.; Nedeljkovic, M.; Gardes, F. Y.; Soler Penades, J.; Alonso-Ramos, C.; Ortega-Monux, A.; Wanguemert-Perez, G.; Molina-Fernandez, I.; Cheben, P.; Mashanovich, G. Z.

2016-03-01

This paper discusses some of the remaining challenges for silicon photonics, and how we at Southampton University have approached some of them. Despite phenomenal advances in the field of Silicon Photonics, there are a number of areas that still require development. For short to medium reach applications, there is a need to improve the power consumption of photonic circuits such that inter-chip, and perhaps intra-chip applications are viable. This means that yet smaller devices are required as well as thermally stable devices, and multiple wavelength channels. In turn this demands smaller, more efficient modulators, athermal circuits, and improved wavelength division multiplexers. The debate continues as to whether on-chip lasers are necessary for all applications, but an efficient low cost laser would benefit many applications. Multi-layer photonics offers the possibility of increasing the complexity and effectiveness of a given area of chip real estate, but it is a demanding challenge. Low cost packaging (in particular, passive alignment of fibre to waveguide), and effective wafer scale testing strategies, are also essential for mass market applications. Whilst solutions to these challenges would enhance most applications, a derivative technology is emerging, that of Mid Infra-Red (MIR) silicon photonics. This field will build on existing developments, but will require key enhancements to facilitate functionality at longer wavelengths. In common with mainstream silicon photonics, significant developments have been made, but there is still much left to do. Here we summarise some of our recent work towards wafer scale testing, passive alignment, multiplexing, and MIR silicon photonics technology.

Method for passivating crystal silicon surfaces

DOEpatents

Wang, Qi [Littleton, CO; Wang, Tihu [Littleton, CO; Page, Matthew R [Littleton, CO; Yan, Yanfa [Littleton, CO

2009-12-08

In a method of making a c-Si-based cell or a .mu.c-Si-based cell, the improvement of increasing the minority charge carrier's lifetime, comprising: a) placing a c-Si or polysilicon wafer into CVD reaction chamber under a low vacuum condition and subjecting the substrate of the wafer to heating; and b) passing mixing gases comprising NH.sub.3/H.sub.2 through the reaction chamber at a low vacuum pressure for a sufficient time and at a sufficient flow rate to enable growth of an a-Si:H layer sufficient to increase the lifetime of the c-Si or polysilicon cell beyond that of the growth of an a-Si:H layer without treatment of the wafer with NH.sub.3/H.sub.2.

Disc resonator gyroscope fabrication process requiring no bonding alignment

NASA Technical Reports Server (NTRS)

Shcheglov, Kirill V. (Inventor)

2010-01-01

A method of fabricating a resonant vibratory sensor, such as a disc resonator gyro. A silicon baseplate wafer for a disc resonator gyro is provided with one or more locating marks. The disc resonator gyro is fabricated by bonding a blank resonator wafer, such as an SOI wafer, to the fabricated baseplate, and fabricating the resonator structure according to a pattern based at least in part upon the location of the at least one locating mark of the fabricated baseplate. MEMS-based processing is used for the fabrication processing. In some embodiments, the locating mark is visualized using optical and/or infrared viewing methods. A disc resonator gyroscope manufactured according to these methods is described.

Carrier Selective, Passivated Contacts for High Efficiency Silicon Solar Cells based on Transparent Conducting Oxides

DOE PAGES

Young, David L.; Nemeth, William; Grover, Sachit; ...

2014-01-01

We describe the design, fabrication and results of passivated contacts to n-type silicon utilizing thin SiO 2 and transparent conducting oxide layers. High temperature silicon dioxide is grown on both surfaces of an n-type wafer to a thickness <50 Å, followed by deposition of tin-doped indium oxide (ITO) and a patterned metal contacting layer. As deposited, the thin-film stack has a very high J0, contact, and a non-ohmic, high contact resistance. However, after a forming gas anneal, the passivation quality and the contact resistivity improve significantly. The contacts are characterized by measuring the recombination parameter of the contact (J0, contact)more » and the specific contact resistivity (ρ contact) using a TLM pattern. The best ITO/SiO 2 passivated contact in this study has J 0,contact = 92.5 fA/cm 2 and ρ contact = 11.5 mOhm-cm 2. These values are placed in context with other passivating contacts using an analysis that determines the ultimate efficiency and the optimal area fraction for contacts for a given set of (J0, contact, ρ contact) values. The ITO/SiO 2 contacts are found to have a higher J0, contact, but a similar ρ contact compared to the best reported passivated contacts.« less

Investigation of the Electrical Characteristics of Al/p-Si/Al Schottky Diode

NASA Astrophysics Data System (ADS)

Şenarslan, Elvan; Güzeldir, Betül; Sağlam, Mustafa

2016-04-01

In this study, p-type Si semiconductor wafer with (100) orientation, 400 μm thickness and 1-10 Ω cm resistivity was used. The Si wafer before making contacts were chemically cleaned with the Si cleaning procedure which for remove organic contaminations were ultrasonically cleaned at acetone and methanol for 10 min respectively and then rinsed in deionized water of 18 MΩ and dried with high purity N2. Then respectively RCA1(i.e., boiling in NH3+H2O2+6H2O for 10 min at 60°C ), RCA2 (i.e., boiling in HCl+H2O2+6H2O for 10 min at 60°C ) cleaning procedures were applied and rinsed in deionized water followed by drying with a stream of N2. After the cleaning process, the wafer is immediately inserted in to the coating unit. Ohmic contact was made by evaporating of Al on the non-polished side of the p-Si wafer pieces under ~ 4,2 10-6 Torr pressure. After process evaporation, p-Si with omic contac thermally annealed 580°C for 3 min in a quartz tube furnace in N2. Then, the rectifier contact is made by evaporation Al metal diameter of about 1.0 mm on the polished surface of p-Si in turbo molecular pump at about ~ 1 10-6 Torr. Consequently, Al/p-Si/Al Schottky diode was obtained. The I-V measurements of this diode performed by the use of a KEITLEY 487 Picoammeter/Voltage Source and the C-V measurements were performed with HP 4192A (50-13 MHz) LF Impedance Analyzer at room temperature and in dark.

Structural and electrical investigations of a-Si:H(i) and a-Si:H(n+) stacked layers for improving the interface and passivation qualities

NASA Astrophysics Data System (ADS)

Hsieh, Yu-Lin; Lee, Chien-Chieh; Lu, Chia-Cheng; Fuh, Yiin-Kuen; Chang, Jenq-Yang; Lee, Ju-Yi; Li, Tomi T.

2017-07-01

A symmetrically stacked structure [(a-Si:H(n+)/a-Si:H(i)/CZ wafer (n)/a-Si:H(i)/a-Si:H(n+)] was used to optimize the growth process conditions of the n-type hydrogenated amorphous silicon [a-Si:H(n+)] thin films. Here a-Si:H(n+) film was used as back surface field (BSF) layer for the silicon heterojunction solar cell and all stacked films were prepared by conventional radio-frequency plasma-enhanced chemical vapor deposition. The characterizations of the effective carrier lifetime (τeff), electrical and structural properties, as well as correlation with the hydrogen dilution ratio (R=H2/SiH4) were systematically discussed with the emphasis on the effectiveness of the passivation layer using the lifetime tester, spectroscopic ellipsometry, and hall measurement. High quality of a stacked BSF layer (intrinsic/n-type a-Si:H layer) with effective carrier lifetime of 1.8 ms can be consistently obtained. This improved passivation layer can be primarily attributed to the synergy of chemical and field effect to significantly reduce the surface recombination.

P-Type Silicon Strip Sensors for the new CMS Tracker at HL-LHC

DOE PAGES

Adam, W.; Bergauer, T.; Brondolin, E.; ...

2017-06-27

The upgrade of the LHC to the High-Luminosity LHC (HL-LHC) is expected to increase the LHC design luminosity by an order of magnitude. This will require silicon tracking detectors with a significantly higher radiation hardness. The CMS Tracker Collaboration has conducted an irradiation and measurement campaign to identify suitable silicon sensor materials and strip designs for the future outer tracker at the CMS experiment. Based on these results, the collaboration has chosen to use n-in-p type silicon sensors and focus further investigations on the optimization of that sensor type. Furthermore, this paper describes the main measurement results and conclusions thatmore » motivated this decision.« less

Capillary liquid chromatography-microchip atmospheric pressure chemical ionization-mass spectrometry.

PubMed

Ostman, Pekka; Jäntti, Sirkku; Grigoras, Kestas; Saarela, Ville; Ketola, Raimo A; Franssila, Sami; Kotiaho, Tapio; Kostiainen, Risto

2006-07-01

A miniaturized nebulizer chip for capillary liquid chromatography-atmospheric pressure chemical ionization-mass spectrometry (capillary LC-microchip APCI-MS) is presented. The APCI chip consists of two wafers, a silicon wafer and a Pyrex glass wafer. The silicon wafer has a DRIE etched through-wafer nebulizer gas inlet, an edge capillary insertion channel, a stopper, a vaporizer channel and a nozzle. The platinum heater electrode and pads for electrical connection were patterned on to the Pyrex glass wafer. The two wafers were joined by anodic bonding, creating a microchip version of an APCI-source. The sample inlet capillary from an LC column is directly connected to the vaporizer channel of the APCI chip. The etched nozzle in the microchip forms a narrow sample plume, which is ionized by an external corona needle, and the formed ions are analyzed by a mass spectrometer. The nebulizer chip enables for the first time the use of low flow rate separation techniques with APCI-MS. The performance of capillary LC-microchip APCI-MS was tested with selected neurosteroids. The capillary LC-microchip APCI-MS provides quantitative repeatability and good linearity. The limits of detection (LOD) with a signal-to-noise ratio (S/N) of 3 in MS/MS mode for the selected neurosteroids were 20-1000 fmol (10-500 nmol l(-1)). LODs (S/N = 3) with commercial macro APCI with the same compounds using the same MS were about 10 times higher. Fast heat transfer allows the use of the optimized temperature for each compound during an LC run. The microchip APCI-source provides a convenient and easy method to combine capillary LC to any API-MS equipped with an APCI source. The advantages and potentials of the microchip APCI also make it a very attractive interface in microfluidic APCI-MS.

Method of fabricating porous silicon carbide (SiC)

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1995-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

P-Type Silicon Strip Sensors for the new CMS Tracker at HL-LHC

DOE Office of Scientific and Technical Information (OSTI.GOV)

Adam, W.; Bergauer, T.; Brondolin, E.

The upgrade of the LHC to the High-Luminosity LHC (HL-LHC) is expected to increase the LHC design luminosity by an order of magnitude. This will require silicon tracking detectors with a significantly higher radiation hardness. The CMS Tracker Collaboration has conducted an irradiation and measurement campaign to identify suitable silicon sensor materials and strip designs for the future outer tracker at the CMS experiment. Based on these results, the collaboration has chosen to use n-in-p type silicon sensors and focus further investigations on the optimization of that sensor type. Furthermore, this paper describes the main measurement results and conclusions thatmore » motivated this decision.« less

CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1980-01-01

Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

Sub-Micrometer Zeolite Films on Gold-Coated Silicon Wafers with Single-Crystal-Like Dielectric Constant and Elastic Modulus

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tiriolo, Raffaele; Rangnekar, Neel; Zhang, Han

A low-temperature synthesis coupled with mild activation produces zeolite films exhibiting low dielectric constant (low-k) matching the theoretically predicted and experimentally measured values for single crystals. This synthesis and activation method allows for the fabrication of a device consisting of a b-oriented film of the pure-silica zeolite MFI (silicalite-1) supported on a gold-coated silicon wafer. The zeolite seeds are assembled by a manual assembly process and subjected to optimized secondary growth conditions that do not cause corrosion of the gold underlayer, while strongly promoting in-plane growth. The traditional calcination process is replaced with a non-thermal photochemical activation to ensure preservationmore » of an intact gold layer. The dielectric constant (k), obtained through measurement of electrical capacitance in a metal-insulator-metal configuration, highlights the ultralow k approximate to 1.7 of the synthetized films, which is among the lowest values reported for an MFI film. There is large improvement in elastic modulus of the film (E approximate to 54 GPa) over previous reports, potentially allowing for integration into silicon wafer processing technology.« less

Fabrication of terahertz metamaterials using electrohydrodynamic jet printing for sensitive detection of yeast

NASA Astrophysics Data System (ADS)

Pradhipta Tenggara, Ayodya; Park, S. J.; Teguh Yudistira, Hadi; Ahn, Y. H.; Byun, Doyoung

2017-03-01

We demonstrated the fabrication of terahertz metamaterial sensor for the accurate and on-site detection of yeast using electrohydrodynamic jet printing, which is inexpensive, simple, and environmentally friendly. The very small sized pattern up to 5 µm-width of electrical split ring resonator unit structures could be printed on a large area on both a rigid substrate and flexible substrate, i.e. silicon wafer and polyimide film using the drop on demand technique to eject liquid ink containing silver nanoparticles. Experimental characterization and simulation were performed to study their performances in detecting yeast of different weights. It was shown that the metamaterial sensor fabricated on a flexible polyimide film had higher sensitivity by more than six times than the metamaterial sensor fabricated on a silicon wafer, due to the low refractive index of the PI substrate and due to the extremely thin substrate thickness which lowers the effective index further. The resonance frequency shift saturated when the yeast weights were 145 µg and 215 µg for metamaterial structures with gap size 6.5 µm fabricated on the silicon substrate and on the polyimide substrate, respectively.

Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer

NASA Astrophysics Data System (ADS)

Watanabe, Naoya; Kikuchi, Hidekazu; Yanagisawa, Azusa; Shimamoto, Haruo; Kikuchi, Katsuya; Aoyagi, Masahiro; Nakamura, Akio

2017-07-01

A high-yield via-last through silicon via (TSV) process has been developed using notchless Si etching and wet cleaning of the first metal layer. In this process, the notching was suppressed by optimizing the deep Si etching conditions and wet cleaning was performed using an organic alkaline solution to remove reaction products generated by the etchback step on the first metal layer. By this process, a number of small TSVs (TSV diameter: 6 µm TSV depth: 22 µm number of TSVs: 20,000/chip) could be formed uniformly on an 8-in. wafer. The electrical characteristics of small TSVs formed by this via-last TSV process were investigated. The TSV resistance determined by four-terminal measurements was approximately 24 mΩ. The leakage current between the TSV and the Si substrate was 2.5 pA at 5 V. The TSV capacitance determined using an inductance-capacitance-resistance (LCR) meter was 54 fF, while the TSV yield determined from TSV chain measurements was high (83%) over an 8-in. wafer.

Comparison of Photoluminescence Imaging on Starting Multi-Crystalline Silicon Wafers to Finished Cell Performance: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Dorn, D.

2012-06-01

Photoluminescence (PL) imaging techniques can be applied to multicrystalline silicon wafers throughout the manufacturing process. Both band-to-band PL and defect-band emissions, which are longer-wavelength emissions from sub-bandgap transitions, are used to characterize wafer quality and defect content on starting multicrystalline silicon wafers and neighboring wafers processed at each step through completion of finished cells. Both PL imaging techniques spatially highlight defect regions that represent dislocations and defect clusters. The relative intensities of these imaged defect regions change with processing. Band-to-band PL on wafers in the later steps of processing shows good correlation to cell quality and performance. The defect bandmore » images show regions that change relative intensity through processing, and better correlation to cell efficiency and reverse-bias breakdown is more evident at the starting wafer stage as opposed to later process steps. We show that thermal processing in the 200 degrees - 400 degrees C range causes impurities to diffuse to different defect regions, changing their relative defect band emissions.« less

Degradation of bare and silanized silicon wafer surfaces by constituents of biological fluids.

PubMed

Dekeyser, C M; Buron, C C; Derclaye, S R; Jonas, A M; Marchand-Brynaert, J; Rouxhet, P G

2012-07-15

The 24 h stability of bare silicon wafers as such or silanized with CH(3)O-(CH(2)-CH(2)-O)(n)-C(3)H(6)-trichlorosilane (n=6-9) was investigated in water, NaCl, phosphate and carbonate solutions, and in phosphate buffered saline (PBS) at 37 °C (close to biological conditions regarding temperature, high ionic strength, and pH). The resulting surfaces were analyzed using ellipsometry, X-ray Reflectometry (XRR), X-ray Photoelectron Spectroscopy (XPS), and Atomic Force Microscopy (AFM). Incubation of the silanized wafers in phosphate solution and PBS provokes a detachment of the silane layer. This is due to a hydrolysis of Si-O bonds which is favored by the action of phosphate, also responsible for a corrosion of non-silanized wafers. The surface alteration (detachment of silane layer and corrosion of the non-silanized wafer) is also important with carbonate solution, due to a higher pH (8.3). The protection of the silicon oxide layer brought by silane against the action of the salts is noticeable for phosphate but not for carbonate. Copyright © 2012 Elsevier Inc. All rights reserved.

Dominant Overall Chemical Reaction in a Chlorine Trifluoride Silicon Nitrogen System at Atmospheric Pressure

NASA Astrophysics Data System (ADS)

Habuka, Hitoshi; Otsuka, Toru; Qu, Wei-Feng

1999-11-01

This study evaluates the overall chemical reaction in a chlorine trifluoride silicon nitrogen system at atmospheric pressure, based on the observation of the dominant chemical species in the gas phase using a quadrupole mass spectra analyzer coupled with a horizontal cold-wall single-wafer epitaxial reactor. Chlorine trifluoride gas etches the silicon surface, producing two major products, silicon tetrafluoride gas and chlorine gas, at room temperature and 530 K. The production of chlorosilanes was not observed in this study. The results obtained in this study indicate that the dominant overall chemical reaction in a chlorine trifluoride silicon nitrogen system is 3Si + 4ClF3 →3SiF4 ↑+ 2Cl2 ↑.

Silicon vertical microstructure fabrication by catalytic etching

NASA Astrophysics Data System (ADS)

Huang, Mao-Jung; Yang, Chii-Rong; Chang, Chun-Ming; Chu, Nien-Nan; Shiao, Ming-Hua

2012-08-01

This study presents an effective, simple and inexpensive process for forming micro-scale vertical structures on a (1 0 0) silicon wafer. Several modified etchants and micro-patterns including rectangular, snake-like, circular and comb patterns were employed to determine the optimum etching process. We found that an etchant solution consisting of 4.6 M hydrofluoric acid, 0.44 M hydrogen peroxide and isopropyl alcohol produces microstructures at an etching rate of 0.47 µm min-1 and surface roughness of 17.4 nm. All the patterns were transferred faithfully to the silicon substrate.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Micro benchtop optics by bulk silicon micromachining

DOEpatents

Lee, Abraham P.; Pocha, Michael D.; McConaghy, Charles F.; Deri, Robert J.

2000-01-01

Micromachining of bulk silicon utilizing the parallel etching characteristics of bulk silicon and integrating the parallel etch planes of silicon with silicon wafer bonding and impurity doping, enables the fabrication of on-chip optics with in situ aligned etched grooves for optical fibers, micro-lenses, photodiodes, and laser diodes. Other optical components that can be microfabricated and integrated include semi-transparent beam splitters, micro-optical scanners, pinholes, optical gratings, micro-optical filters, etc. Micromachining of bulk silicon utilizing the parallel etching characteristics thereof can be utilized to develop miniaturization of bio-instrumentation such as wavelength monitoring by fluorescence spectrometers, and other miniaturized optical systems such as Fabry-Perot interferometry for filtering of wavelengths, tunable cavity lasers, micro-holography modules, and wavelength splitters for optical communication systems.

Preparation and atomic force microscopy of CTAB stabilized polythiophene nanoparticles thin film

DOE Office of Scientific and Technical Information (OSTI.GOV)

Graak, Pinki; Devi, Ranjna; Kumar, Dinesh

2016-05-06

Polythiophene nanoparticles were synthesized by iron catalyzed oxidative polymerization method. Polythiophene formation was detected by UV-Visible spectroscopy with λmax 375nm. Thin films of CTAB stabilized polythiophene nanoparticles was deposited on n-type silicon wafer by spin coating technique at 3000rpm in three cycles. Thickness of the thin films was computed as 300-350nm by ellipsometry. Atomic force micrscopyrevealws the particle size of polymeric nanoparticles in the range of 30nm to 100nm. Roughness of thinfilm was also analyzed from the atomic force microscopy data by Picoimage software. The observed RMS value lies in the range of 6 nm to 12 nm.

Improved method of preparing p-i-n junctions in amorphous silicon semiconductors

DOEpatents

Madan, A.

1984-12-10

A method of preparing p/sup +/-i-n/sup +/ junctions for amorphous silicon semiconductors includes depositing amorphous silicon on a thin layer of trivalent material, such as aluminum, indium, or gallium at a temperature in the range of 200/sup 0/C to 250/sup 0/C. At this temperature, the layer of trivalent material diffuses into the amorphous silicon to form a graded p/sup +/-i junction. A layer of n-type doped material is then deposited onto the intrinsic amorphous silicon layer in a conventional manner to finish forming the p/sup +/-i-n/sup +/ junction.

CdO thin films based on the annealing temperature differences prepared by sol-gel method and their heterojunction devices

NASA Astrophysics Data System (ADS)

Soylu, M.; Yazici, T.

2017-12-01

Undoped CdO films were prepared on glass substrate and p-type silicon wafer using sol-gel spin coating method. The structural and optical properties of the films were investigated as a function of the annealing temperature. X-ray diffraction (XRD) patterns reveal that the films are formed from CdO with cubic crystal structure and (1 1 1) preferred orientation. It is seen that good crystallinity is due to the high annealing temperature. The surface morphology of the CdO films was found to be depending on the annealing temperature, showing cauliflower like structure. Optical band gaps for annealing temperature of 250 °C and 450 °C were found to be 2.49 eV and 2.27 eV, respectively, showing a decrease with raising temperature. Optics parameters such as extinction coefficient, refractive index, and surface-volume energy loss were determined with spectrophotometric analysis as a function of annealing temperature. CdO/p-Si heterojunction structure showed weak rectifying behavior. The diode parameters were found to be depending on annealing temperature. The results are encouraging to get better conjunction with CdO thin film component at optimize annealing temperature.

Local residual stress monitoring of aluminum nitride MEMS using UV micro-Raman spectroscopy

DOE PAGES

Choi, Sukwon; Griffin, Benjamin A.

2016-01-06

Localized stress variation in aluminum nitride (AlN) sputtered on patterned metallization has been monitored through the use of UV micro-Raman spectroscopy. This technique utilizing 325 nm laser excitation allows detection of the AlN E2(high) phonon mode in the presence of metal electrodes beneath the AlN layer with a high spatial resolution of less than 400 nm. The AlN film stress shifted 400 MPa from regions where AlN was deposited over a bottom metal electrode versus silicon dioxide. Thus, across wafer stress variations were also investigated showing that wafer level stress metrology, for example using wafer curvature measurements, introduces large uncertaintiesmore » for predicting the impact of AlN residual stress on the device performance.« less

Method for enhancing the solubility of dopants in silicon

DOEpatents

Sadigh, Babak; Lenosky, Thomas J.; De La Rubia, Tomas Diaz

2003-09-30

A method for enhancing the equilibrium solid solubility of dopants in silicon, germanium and silicon-germanium alloys. The method involves subjecting silicon-based substrate to biaxial or compression strain. It has been determined that boron solubility was largely enhanced (more than 100%) by a compressive bi-axial strain, based on a size-mismatch theory since the boron atoms are smaller than the silicon atoms. It has been found that the large enhancement or mixing properties of dopants in silicon and germanium substrates is primarily governed by their, and to second order by their size-mismatch with the substrate. Further, it has been determined that the dopant solubility enhancement with strain is most effective when the charge and the size-mismatch of the impurity favor the same type of strain. Thus, the solid solubility of small p-type (e.g., boron) as well as large n-type (e.g., arsenic) dopants can be raised most dramatically by appropriate bi-axial (compressive) strain, and that solubility of a large p-type dopant (e.g, indium) in silicon will be raised due to size-mismatch with silicon, which favors tensile strain, while its negative charge prefers compressive strain, and thus the two effects counteract each other.

Accurate determination of electronic transport properties of silicon wafers by nonlinear photocarrier radiometry with multiple pump beam sizes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Qian; University of the Chinese Academy of Sciences, Beijing 100039; Li, Bincheng, E-mail: bcli@uestc.ac.cn

2015-12-07

In this paper, photocarrier radiometry (PCR) technique with multiple pump beam sizes is employed to determine simultaneously the electronic transport parameters (the carrier lifetime, the carrier diffusion coefficient, and the front surface recombination velocity) of silicon wafers. By employing the multiple pump beam sizes, the influence of instrumental frequency response on the multi-parameter estimation is totally eliminated. A nonlinear PCR model is developed to interpret the PCR signal. Theoretical simulations are performed to investigate the uncertainties of the estimated parameter values by investigating the dependence of a mean square variance on the corresponding transport parameters and compared to that obtainedmore » by the conventional frequency-scan method, in which only the frequency dependences of the PCR amplitude and phase are recorded at single pump beam size. Simulation results show that the proposed multiple-pump-beam-size method can improve significantly the accuracy of the determination of the electronic transport parameters. Comparative experiments with a p-type silicon wafer with resistivity 0.1–0.2 Ω·cm are performed, and the electronic transport properties are determined simultaneously. The estimated uncertainties of the carrier lifetime, diffusion coefficient, and front surface recombination velocity are approximately ±10.7%, ±8.6%, and ±35.4% by the proposed multiple-pump-beam-size method, which is much improved than ±15.9%, ±29.1%, and >±50% by the conventional frequency-scan method. The transport parameters determined by the proposed multiple-pump-beam-size PCR method are in good agreement with that obtained by a steady-state PCR imaging technique.« less

Superacid Passivation of Crystalline Silicon Surfaces.

PubMed

Bullock, James; Kiriya, Daisuke; Grant, Nicholas; Azcatl, Angelica; Hettick, Mark; Kho, Teng; Phang, Pheng; Sio, Hang C; Yan, Di; Macdonald, Daniel; Quevedo-Lopez, Manuel A; Wallace, Robert M; Cuevas, Andres; Javey, Ali

2016-09-14

The reduction of parasitic recombination processes commonly occurring within the silicon crystal and at its surfaces is of primary importance in crystalline silicon devices, particularly in photovoltaics. Here we explore a simple, room temperature treatment, involving a nonaqueous solution of the superacid bis(trifluoromethane)sulfonimide, to temporarily deactivate recombination centers at the surface. We show that this treatment leads to a significant enhancement in optoelectronic properties of the silicon wafer, attaining a level of surface passivation in line with state-of-the-art dielectric passivation films. Finally, we demonstrate its advantage as a bulk lifetime and process cleanliness monitor, establishing its compatibility with large area photoluminescence imaging in the process.

Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

NASA Astrophysics Data System (ADS)

Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

2018-05-01

A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

Impact of crystal orientation on ohmic contact resistance of enhancement-mode p-GaN gate high electron mobility transistors on 200 mm silicon substrates

NASA Astrophysics Data System (ADS)

Van Hove, Marleen; Posthuma, Niels; Geens, Karen; Wellekens, Dirk; Li, Xiangdong; Decoutere, Stefaan

2018-04-01

p-GaN gate enhancement mode power transistors were processed in a Si CMOS processing line on 200 mm Si(111) substrates using Au-free metallization schemes. Si/Ti/Al/Ti/TiN ohmic contacts were formed after full recessing of the AlGaN barrier, followed by a HCl-based wet cleaning step. The electrical performance of devices aligned to the [11\\bar{2}0] and the perpendicular [1\\bar{1}00] directions was compared. The ohmic contact resistance was decreased from 1 Ω·mm for the [11\\bar{2}0] direction to 0.35 Ω·mm for the [1\\bar{1}00] direction, resulting in an increase of the drain saturation current from 0.5 to 0.6 A/mm, and a reduction of the on-resistance from 6.4 to 5.1 Ω·mm. Moreover, wafer mapping of the device characteristics over the 200 mm wafer showed a tighter statistical distribution for the [1\\bar{1}00] direction. However, by using an optimized sulfuric/ammonia peroxide (SPM/APM) cleaning step, the ohmic contact resistance could be lowered to 0.3 Ω·mm for both perpendicular directions.

FABRICATION OF A RETINAL PROSTHETIC TEST DEVICE USING ELECTRODEPOSITED SILICON OVER POLYPYRROLE PATTERNED WITH SU-8 PHOTORESIST

PubMed Central

Miller, Eric; Ellis, Daniel; Charles, Duran; McKenzie, Jason

2016-01-01

A materials fabrication study of a photodiode array for possible application of retina prosthesis was undertaken. A test device was fabricated using a glassy carbon electrode patterned with SU-8 photoresist. In the openings, p-type polypyrrole was first electrodeposited using 1-butyl-1-methylpyridinium bis(trifluoromethylsulfonyl)imide ionic liquid. The polypyrrole was self-doped with imide ion at ~1.5 mole %, was verified as p-type, and had a resistivity of ~20 Ωcm. N-type Silicon was then electrodeposited over this layer using silicon tetrachloride / phosphorus trichloride in acetonitrile and passivated in a second electrodeposition using trimethylchlorosilane. Electron microscopy revealed the successful electrodeposition of silicon over patterned polypyrrole. Rudimentary photodiode behavior was observed. The passivation improved but did not completely protect the electrodeposited silicon from oxidation by air. PMID:27616940

Thin film transistors on plastic substrates with reflective coatings for radiation protection

DOEpatents

Wolfe, Jesse D.; Theiss, Steven D.; Carey, Paul G.; Smith, Patrick M.; Wickboldt, Paul

2003-11-04

Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

Microelectromechanical Systems (MEMS) Photoacoustic (PA) Detector of Terahertz (THz) Radiation for Chemical Sensing

DTIC Science & Technology

2014-03-01

26 Feb 2014 Ivan Medvedev, PhD (Member) Date iv AFIT-ENG-14-M-58 Abstract In this research effort, a Microelectromechanical...7. Separation by implantation of oxygen (SIMOX) is a process of creating silicon- on-insulator (SOI) wafers. Oxygen ions are implanted into a silicon...wafer. The depth of the insulating layer is dependent upon the power used during ion implantation [14]. .............................. 16  Figure 8

Integrated Optical Interferometers with Micromachined Diaphragms for Pressure Sensing

NASA Technical Reports Server (NTRS)

DeBrabander, Gregory N.; Boyd, Joseph T.

1996-01-01

Optical pressure sensors have been fabricated which use an integrated optical channel waveguide that is part of an interferometer to measure the pressure-induced strain in a micromachined silicon diaphragm. A silicon substrate is etched from the back of the wafer leaving a rectangular diaphragm. On the opposite side of the wafer, ring resonator and Mach-Zehnder interferometers are formed with optical channel waveguides made from a low pressure chemical vapor deposited film of silicon oxynitride. The interferometer's phase is altered by pressure-induced stress in a channel segment positioned over the long edge of the diaphragm. The phase change in the ring resonator is monitored using a link-insensitive swept frequency laser diode, while in the Mach-Zehnder it is determined using a broad band super luminescent diode with subsequent wavelength separation. The ring resonator was found to be highly temperature sensitive, while the Mach-Zehnder, which had a smaller optical path length difference, was proportionally less so. The quasi-TM mode was more sensitive to pressure, in accord with calculations. Waveguide and sensor theory, sensitivity calculations, a fabrication sequence, and experimental results are presented.

Study on chemical mechanical polishing of silicon wafer with megasonic vibration assisted.

PubMed

Zhai, Ke; He, Qing; Li, Liang; Ren, Yi

2017-09-01

Chemical mechanical polishing (CMP) is the primary method to realize the global planarization of silicon wafer. In order to improve this process, a novel method which combined megasonic vibration to assist chemical mechanical polishing (MA-CMP) is developed in this paper. A matching layer structure of polishing head was calculated and designed. Silicon wafers are polished by megasonic assisted chemical mechanical polishing and traditional chemical mechanical polishing respectively, both coarse polishing and precision polishing experiments were carried out. With the use of megasonic vibration, the surface roughness values Ra reduced from 22.260nm to 17.835nm in coarse polishing, and the material removal rate increased by approximately 15-25% for megasonic assisted chemical mechanical polishing relative to traditional chemical mechanical polishing. Average Surface roughness values Ra reduced from 0.509nm to 0.387nm in precision polishing. The results show that megasonic assisted chemical mechanical polishing is a feasible method to improve polishing efficiency and surface quality. The material removal and finishing mechanisms of megasonic vibration assisted polishing are investigated too. Copyright © 2017 Elsevier B.V. All rights reserved.

MEMS fiber-optic Fabry-Perot pressure sensor for high temperature application

NASA Astrophysics Data System (ADS)

Fang, G. C.; Jia, P. G.; Cao, Q.; Xiong, J. J.

2016-10-01

We design and demonstrate a fiber-optic Fabry-Perot pressure sensor (FOFPPS) for high-temperature sensing by employing micro-electro-mechanical system (MEMS) technology. The FOFPPS is fabricated by anodically bonding the silicon wafer and the Pyrex glass together and fixing the facet of the optical fiber in parallel with the silicon surface by glass frit and organic adhesive. The silicon wafer can be reduced through dry etching technology to construct the sensitive diaphragm. The length of the cavity changes with the deformation of the diaphragm due to the loaded pressure, which leads to a wavelength shift of the interference spectrum. The pressure can be gauged by measuring the wavelength shift. The pressure experimental results show that the sensor has linear pressure sensitivities ranging from 0 kPa to 600 kPa at temperature range between 20°C to 300°C. The pressure sensitivity at 300°C is approximately 27.63 pm/kPa. The pressure sensitivities gradually decrease with increasing the temperature. The sensor also has a linear thermal drift when temperature changes from 20°C - 300°C.

New optoelectronic methodology for nondestructive evaluation of MEMS at the wafer level

NASA Astrophysics Data System (ADS)

Furlong, Cosme; Ferguson, Curtis F.; Melson, Michael J.

2004-02-01

One of the approaches to fabrication of MEMS involves surface micromachining to define dies on single crystal silicon wafers, dicing of the wafers to separate the dies, and electronic packaging of the individual dies. Dicing and packaging of MEMS accounts for a large fraction of the fabrication costs, therefore, nondestructive evaluation at the wafer level, before dicing, can have significant implications on improving production yield and costs. In this paper, advances in development of optoelectronic holography (OEH) techniques for nondestructive, noninvasive, full-field of view evaluation of MEMS at the wafer level are described. With OEH techniques, quantitative measurements of shape and deformation of MEMS, as related to their performance and integrity, are obtained with sub-micrometer spatial resolution and nanometer measuring accuracy. To inspect an entire wafer with OEH methodologies, measurements of overlapping regions of interest (ROI) on a wafer are recorded and adjacent ROIs are stitched together through efficient 3D correlation analysis algorithms. Capabilities of the OEH techniques are illustrated with representative applications, including determination of optimal inspection conditions to minimize inspection time while achieving sufficient levels of accuracy and resolution.

Low temperature coefficient of resistance and high gage factor in beryllium-doped silicon

NASA Technical Reports Server (NTRS)

Robertson, J. B.; Littlejohn, M. A.

1974-01-01

The gage factor and resistivity of p-type silicon doped with beryllium was studied as a function of temperature, crystal orientation, and beryllium doping concentration. It was shown that the temperature coefficient of resistance can be varied and reduced to zero near room temperature by varying the beryllium doping level. Similarly, the magnitude of the piezoresistance gage factor for beryllium-doped silicon is slightly larger than for silicon doped with a shallow acceptor impurity such as boron, whereas the temperature coefficient of piezoresistance is about the same for material containing these two dopants. These results are discussed in terms of a model for the piezoresistance of compensated p-type silicon.

Probing photo-carrier collection efficiencies of individual silicon nanowire diodes on a wafer substrate.

PubMed

Schmitt, S W; Brönstrup, G; Shalev, G; Srivastava, S K; Bashouti, M Y; Döhler, G H; Christiansen, S H

2014-07-21

Vertically aligned silicon nanowire (SiNW) diodes are promising candidates for the integration into various opto-electronic device concepts for e.g. sensing or solar energy conversion. Individual SiNW p-n diodes have intensively been studied, but to date an assessment of their device performance once integrated on a silicon substrate has not been made. We show that using a scanning electron microscope (SEM) equipped with a nano-manipulator and an optical fiber feed-through for tunable (wavelength, power using a tunable laser source) sample illumination, the dark and illuminated current-voltage (I-V) curve of individual SiNW diodes on the substrate wafer can be measured. Surprisingly, the I-V-curve of the serially coupled system composed of SiNW/wafers is accurately described by an equivalent circuit model of a single diode and diode parameters like series and shunting resistivity, diode ideality factor and photocurrent can be retrieved from a fit. We show that the photo-carrier collection efficiency (PCE) of the integrated diode illuminated with variable wavelength and intensity light directly gives insight into the quality of the device design at the nanoscale. We find that the PCE decreases for high light intensities and photocurrent densities, due to the fact that considerable amounts of photo-excited carriers generated within the substrate lead to a decrease in shunting resistivity of the SiNW diode and deteriorate its rectification. The PCE decreases systematically for smaller wavelengths of visible light, showing the possibility of monitoring the effectiveness of the SiNW device surface passivation using the shown measurement technique. The integrated device was pre-characterized using secondary ion mass spectrometry (SIMS), TCAD simulations and electron beam induced current (EBIC) measurements to validate the properties of the characterized material at the single SiNW diode level.

Programmable 2-D Addressable Cryogenic Aperture Masks

NASA Technical Reports Server (NTRS)

Kutyrev, A. S.; Moseley, S. H.; Jhabvala, M.; Li, M.; Schwinger, D. S.; Silverberg, R. F.; Wesenberg, R. P.

2004-01-01

We are developing a two-dimensional array of square microshutters (programmable aperture mask) for a multi-object spectrometer for the James Webb Space Telescope (JWST). This device will provide random access selection of the areas in the field to be studied. The device is in essence a close packed array of square slits, each of which can be opened independently to select areas of the sky for detailed study.The device is produced using a 100-micron thick silicon wafer as a substrate with 0.5-micron thick silicon nitride shutters on top of it. Silicon nitride has been selected as the blade and flexure material because its stiffness allows thinner and lighter structures than single crystal Si, the chief alternative, and because of its ease of manufacture. The 100 micron silicon wafer is backetched in a high aspect ratio Deep Reactive Ion Etching (Deep RIE) to leave only a support grid for the shutters and the address electronics. The shutter actuation is done magnetically whereas addressing is electrostatic. 128x128 format microshutter arrays have been produced. Their operation has been demostarted on 32x32 subarrays. Good reliability of the fabrication process and good quality of the microshutters has been achieved. The mechanical behavior and optical performance of the fabricated arrays at cryogenic temperature are being studied.

Heteroepitaxial growth of In{sub 0.30}Ga{sub 0.70}As high-electron mobility transistor on 200 mm silicon substrate using metamorphic graded buffer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kohen, David, E-mail: david.kohen@asm.com; Nguyen, Xuan Sang; Made, Riko I

We report on the growth of an In{sub 0.30}Ga{sub 0.70}As channel high-electron mobility transistor (HEMT) on a 200 mm silicon wafer by metal organic vapor phase epitaxy. By using a 3 μm thick buffer comprising a Ge layer, a GaAs layer and an InAlAs compositionally graded strain relaxing buffer, we achieve threading dislocation density of (1.0 ± 0.3) × 10{sup 7} cm{sup −2} with a surface roughness of 10 nm RMS. No phase separation was observed during the InAlAs compositionally graded buffer layer growth. 1.4 μm long channel length transistors are fabricated from the wafer with I{sub DS} of 70more » μA/μm and g{sub m} of above 60 μS/μm, demonstrating the high quality of the grown materials.« less

Thin film transistors on plastic substrates with reflective coatings for radiation protection

DOEpatents

Wolfe, Jesse D [Fairfield, CA; Theiss, Steven D [Woodbury, MN; Carey, Paul G [Mountain View, CA; Smith, Patrick M [San Ramon, CA; Wickbold, Paul [Walnut Creek, CA

2006-09-26

Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

I-line stepper based overlay evaluation method for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the offsets between all different FIA's into account, after correcting the wafer rotation induced FIA position errors, hence an overlay for the stacked wafers can be determined. The developed approach has been validated by a standard front side resist in resist experiment. After the successful validation of the developed technique, special wafer stacks with FIA alignment marks in the bonding interface are fabricated and exposed. Following overlay calculation shows an overlay of less than 200 nm, which enables very accurate process condition for highly scaled TSV integration and advanced substrate integration into IHP's 0.25/0.13 µm SiGe:C BiCMOS technology. The developed technique also allows using significantly smaller alignment marks (i.e. standard FIA alignment marks). Furthermore, the presented method is used, in case of wafer bow related overlay tool problems, for the overlay evaluation of the last two metal layers from production wafers prepared in IHP's standard 0.25/0.13 µm SiGe:C BiCMOS technology. In conclusion, the exposure and measurement job can be done with the same tool, minimizing the back to front side/interface top layer misalignment which leads to a significant device performance improvement of backside/TSV integrated components and technologies.

Thin Film Transistors On Plastic Substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

2004-01-20

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

Method for making circular tubular channels with two silicon wafers

DOEpatents

Yu, Conrad M.; Hui, Wing C.

1996-01-01

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

Slicing of silicon into sheet material. Silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project

NASA Technical Reports Server (NTRS)

Holden, S. C.; Fleming, J. R.

1978-01-01

Fabrication of a prototype large capacity multiple blade slurry saw is considered. Design of the bladehead which will tension up to 1000 blades, and cut a 45 cm long silicon ingot as large as 12 cm in diameter is given. The large blade tensioning force of 270,000 kg is applied through two bolts acting on a pair of scissor toggles, significantly reducing operator set-up time. Tests with an upside-down cutting technique resulted in 100% wafering yields and the highest wafer accuracy yet experienced with MS slicing. Variations in oil and abrasives resulted only in degraded slicing results. A technique of continuous abrasive slurry separation to remove silicon debris is described.

Printed Large-Area Single-Mode Photonic Crystal Bandedge Surface-Emitting Lasers on Silicon (Open Access Publisher’s Version)

DTIC Science & Technology

2016-01-04

Mode Photonic Crystal Bandedge Surface-Emitting Lasers on Silicon Article in Scientific Reports · January 2016 DOI : 10.1038/srep18860 CITATIONS 5 READS...1Scientific RepoRts | 6:18860 | DOI : 10.1038/srep18860 www.nature.com/scientificreports Printed Large-Area Single-Mode Photonic Crystal Bandedge...bandgap group III-V materials on Si1,4–11 through wafer bonding, printing, and direct-growth. Most lasers demonstrated so far are edge-emitting

Semiconductor P-I-N detector

DOEpatents

Sudharsanan, Rengarajan; Karam, Nasser H.

2001-01-01

A semiconductor P-I-N detector including an intrinsic wafer, a P-doped layer, an N-doped layer, and a boundary layer for reducing the diffusion of dopants into the intrinsic wafer. The boundary layer is positioned between one of the doped regions and the intrinsic wafer. The intrinsic wafer can be composed of CdZnTe or CdTe, the P-doped layer can be composed of ZnTe doped with copper, and the N-doped layer can be composed of CdS doped with indium. The boundary layers is formed of an undoped semiconductor material. The boundary layer can be deposited onto the underlying intrinsic wafer. The doped regions are then typically formed by a deposition process or by doping a section of the deposited boundary layer.

Al+Si Interface Optical Properties Obtained in the Si Solar Cell Configuration

DOE PAGES

Subedi, Indra; Silverman, Timothy J.; Deceglie, Michael G.; ...

2017-10-18

Al is a commonly used material for rear side metallization in commercial silicon (Si) wafer solar cells. In this study, through-the-silicon spectroscopic ellipsometry is used in a test sample to measure Al+Si interface optical properties like those in Si wafer solar cells. Two different spectroscopic ellipsometers are used for measurement of Al+Si interface optical properties over the 1128-2500 nm wavelength range. For validation, the measured interface optical properties are used in a ray tracing simulation over the 300-2500 nm wavelength range for an encapsulated Si solar cell having random pyramidal texture. The ray tracing model matches well with the measuredmore » total reflectance at normal incidence of a commercially available Si module. The Al+Si optical properties presented here enable quantitative assessment of major irradiance/current flux losses arising from reflection and parasitic absorption in encapsulated Si solar cells.« less

Berkeley Lab Sheds Light on Improving Solar Cell Efficiency

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lawrence Berkeley National Laboratory

2007-07-20

Typical manufacturing methods produce solar cells with an efficiency of 12-15%; and 14% efficiency is the bare minimum for achieving a profit. In work performed at the Ernest Orlando Lawrence Berkeley National Laboratory (Berkeley, CA, 5 10-486-577 1)--a US Department of Energy national laboratory that conducts unclassified scientific research and is managed by the University of California--scientist Scott McHugo has obtained keen insights into the impaired performance of solar cells manufactured from polycrystalline silicon. The solar cell market is potentially vast, according to Berkeley Lab. Lightweight solar panels are highly beneficial for providing electrical power to remote locations in developingmore » nations, since there is no need to build transmission lines or truck-in generator fuel. Moreover, industrial nations confronted with diminishing resources have active programs aimed at producing improved, less expensive solar cells. 'In a solar cell, there is a junction between p-type silicon and an n-type layer, such as diffused-in phosphorous', explained McHugo, who is now with Berkeley Lab's Accelerator and Fusion Research Division. 'When sunlight is absorbed, it frees electrons, which start migrating in a random-walk fashion toward that junction. If the electrons make it to the junction; they contribute to the cell's output of electric current. Often, however, before they reach the junction, they recombine at specific sites in the crystal' (and, therefore, cannot contribute to current output). McHugo scrutinized a map of a silicon wafer in which sites of high recombination appeared as dark regions. Previously, researchers had shown that such phenomena occurred not primarily at grain boundaries in the polycrystalline material, as might be expected, but more often at dislocations in the crystal. However, the dislocations themselves were not the problem. Using a unique heat treatment technique, McHugo performed electrical measurements to investigate the material at the dislocations. He was purportedly the first to show that they were 'decorated' with iron.« less

Laser ablation of single-crystalline silicon by radiation of pulsed frequency-selective fiber laser

NASA Astrophysics Data System (ADS)

Veiko, V. P.; Skvortsov, A. M.; Huynh, C. T.; Petrov, A. A.

2015-07-01

We have studied the process of destruction of the surface of a single-crystalline silicon wafer scanned by the beam of a pulsed ytterbium-doped fiber laser radiation with a wavelength of λ = 1062 nm. It is established that the laser ablation can proceed without melting of silicon and the formation of a plasma plume. Under certain parameters of the process (radiation power, beam scan velocity, and beam overlap density), pronounced oxidation of silicon microparticles with the formation of a characteristic loose layer of fine powdered silicon dioxide has been observed for the first time. The range of lasing and beam scanning regimes in which the growth of SiO2 layer takes place is determined.

Slicing of Silicon into Sheet Material. Silicon Sheet Growth Development for the Large Area Silicon Sheet Task of the Low Cost Solar Array Project

NASA Technical Reports Server (NTRS)

Fleming, J. R.; Holden, S. C.; Wolfson, R. G.

1979-01-01

The use of multiblade slurry sawing to produce silicon wafers from ingots was investigated. The commercially available state of the art process was improved by 20% in terms of area of silicon wafers produced from an ingot. The process was improved 34% on an experimental basis. Economic analyses presented show that further improvements are necessary to approach the desired wafer costs, mostly reduction in expendable materials costs. Tests which indicate that such reduction is possible are included, although demonstration of such reduction was not completed. A new, large capacity saw was designed and tested. Performance comparable with current equipment (in terms of number of wafers/cm) was demonstrated.

Forming high-efficiency silicon solar cells using density-graded anti-reflection surfaces

DOEpatents

Yuan, Hao-Chih; Branz, Howard M.; Page, Matthew R.

2015-07-07

A method (50) is provided for processing a graded-density AR silicon surface (14) to provide effective surface passivation. The method (50) includes positioning a substrate or wafer (12) with a silicon surface (14) in a reaction or processing chamber (42). The silicon surface (14) has been processed (52) to be an AR surface with a density gradient or region of black silicon. The method (50) continues with heating (54) the chamber (42) to a high temperature for both doping and surface passivation. The method (50) includes forming (58), with a dopant-containing precursor in contact with the silicon surface (14) of the substrate (12), an emitter junction (16) proximate to the silicon surface (14) by doping the substrate (12). The method (50) further includes, while the chamber is maintained at the high or raised temperature, forming (62) a passivation layer (19) on the graded-density silicon anti-reflection surface (14).

Synergistically Enhanced Performance of Ultrathin Nanostructured Silicon Solar Cells Embedded in Plasmonically Assisted, Multispectral Luminescent Waveguides

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Sung-Min; Dhar, Purnim; Chen, Huandong

Ultrathin silicon solar cells fabricated by anisotropic wet chemical etching of single-crystalline wafer materials represent an attractive materials platform that could provide many advantages for realizing high-performance, low-cost photovoltaics. However, their intrinsically limited photovoltaic performance arising from insufficient absorption of low-energy photons demands careful design of light management to maximize the efficiency and preserve the cost-effectiveness of solar cells. Herein we present an integrated flexible solar module of ultrathin, nanostructured silicon solar cells capable of simultaneously exploiting spectral upconversion and downshifting in conjunction with multispectral luminescent waveguides and a nanostructured plasmonic reflector to compensate for their weak optical absorption andmore » enhance their performance. The 8 μm-thick silicon solar cells incorporating a hexagonally periodic nanostructured surface relief are surface-embedded in layered multispectral luminescent media containing organic dyes and NaYF4:Yb3+,Er3+ nanocrystals as downshifting and upconverting luminophores, respectively, via printing-enabled deterministic materials assembly. The ultrathin nanostructured silicon microcells in the composite luminescent waveguide exhibit strongly augmented photocurrent (~40.1 mA/cm2) and energy conversion efficiency (~12.8%) than devices with only a single type of luminescent species, owing to the synergistic contributions from optical downshifting, plasmonically enhanced upconversion, and waveguided photon flux for optical concentration, where the short-circuit current density increased by ~13.6 mA/cm2 compared with microcells in a nonluminescent medium on a plain silver reflector under a confined illumination.« less

Opportunities of CMOS-MEMS integration through LSI foundry and open facility

NASA Astrophysics Data System (ADS)

Mita, Yoshio; Lebrasseur, Eric; Okamoto, Yuki; Marty, Frédéfic; Setoguchi, Ryota; Yamada, Kentaro; Mori, Isao; Morishita, Satoshi; Imai, Yoshiaki; Hosaka, Kota; Hirakawa, Atsushi; Inoue, Shu; Kubota, Masanori; Denoual, Matthieu

2017-06-01

Since the 2000s, several countries have established micro- and nanofabrication platforms for the research and education community as national projects. By combining such platforms with VLSI multichip foundry services, various integrated devices, referred to as “CMOS-MEMS”, can be realized without constructing an entire cleanroom. In this paper, we summarize MEMS-last postprocess schemes for CMOS devices on a bulk silicon wafer as well as on a silicon-on-insulator (SOI) wafer using an open-access cleanroom of the Nanotechnology Platform of MEXT Japan. The integration devices presented in this article are free-standing structures and postprocess isolated LSI devices. Postprocess issues are identified with their solutions, such as the reactive ion etching (RIE) lag for dry release and the impact of the deep RIE (DRIE) postprocess on transistor characteristics. Integration with nonsilicon materials is proposed as one of the future directions.

Enabling Large Focal Plane Arrays through Mosaic Hybridization

NASA Technical Reports Server (NTRS)

Miller, Timothy M.; Jhabvala, Christine A.; Costen, Nick; Benford, Dominic J.

2012-01-01

We have demonstrated the hybridization of large mosaics of far-infrared detectors, joining separately fabricated sub-units into a single unit on a single, large substrate. We produced a single detector mockup on a 100mm diameter wafer and four mockup readout quadrant chips from a separate 100mm wafer. The individually fabricated parts were hybridized using a Suss FC150 flip chip bonder to assemble the detector-readout stack. Once all of the hybridized readouts were in place, a single, large and thick silicon substrate was placed on the stack and attached with permanent epoxy to provide strength and a Coefficient of Thermal Expansion (CTE) match to the silicon components underneath. Wirebond pads on the readout chips connect circuits to warm readout electronics; and were used to validate the successful superconducting electrical interconnection of the mockup mosaic-hybridized detector. This demonstration is directly scalable to 150 mm diameter wafers, enabling pixel areas over ten times the area currently demonstrated.

Role of Cellulose Nanocrystals on the Microstructure of Maleic Anhydride Plasma Polymer Thin Films.

PubMed

Brioude, Michel M; Roucoules, Vincent; Haidara, Hamidou; Vonna, Laurent; Laborie, Marie-Pierre

2015-07-01

Recently, it was shown that the microstructure of a maleic anhydride plasma polymer (MAPP) could be tailored ab initio by adjusting the plasma process parameters. In this work, we aim to investigate the ability of cellulose nanocrystals (CNCs) to induce topographical structuration. Thus, a new approach was designed based on the deposition of MAPP on CNCs model surfaces. The nanocellulosic surfaces were produced by spin-coating the CNC suspension on a silicon wafer substrate and on a hydrophobic silicon wafer substrate patterned with circular hydrophilic microsized domains (diameter of 86.9 ± 4.9 μm), resulting in different degrees of CNC aggregation. By depositing the MAPP over these surfaces, it was possible to observe that the surface fraction of nanostructures increased from 20% to 35%. This observation suggests that CNCs can act as nucleation points resulting in more structures, although a critical density of the CNCs is required.

The Selective Epitaxy of Silicon at Low Temperatures.

NASA Astrophysics Data System (ADS)

Lou, Jen-Chung

1991-01-01

This dissertation has developed a process for the selective epitaxial growth (SEG) of silicon at low temperatures using a dichlorosilane-hydrogen mixture in a hot-wall low pressure chemical vapor deposition (LPCVD) reactor. Some basic issues concerning the quality of epilayers --substrate preparation, ex-situ and in-situ cleaning, and deposition cycle, have been studied. We find it necessary to use a plasma etch to open epitaxial windows for the SEG of Si. A cycled plasma etch, a thin sacrificial oxide growth, and an oxide etching step can completely remove plasma-etch-induced surface damage and contaminants, which result in high quality epilayers. A practical wafer cleaning step is developed for low temperature Si epitaxial growth. An ex-situ HF vapor treatment can completely remove chemical oxide from the silicon surface and retard the reoxidation of the silicon surface. An in-situ low-concentration DCS cycle can aid in decomposition of surface oxide during a 900 ^circC H_2 prebake step. An HF vapor treatment combined with a low-concentration of DCS cycle consistently achieves defect-free epilayers at 850^circC and lower temperatures. We also show that a BF_sp{2}{+ } or F^+ ion implantation is a potential ex-situ wafer cleaning process for SEG of Si at low temperatures. The mechanism for the formation of surface features on Si epilayers is also discussed. Based on O ^+ ion implantation, we showed that the oxygen incorporation in silicon epilayers suppresses the Si growth rate. Therefore, we attribute the formation of surface features to the local reduction of the Si growth rate due to the dissolution of oxide islands at the epi/substrate interface. Finally, with this developed process for the SEG of silicon, defect-free overgrown epilayers are also obtained. This achievement demonstrates the feasibility for the future silicon-on-oxide (SOI) manufacturing technology.

Hybrid Silicon Photonic Integration using Quantum Well Intermixing

NASA Astrophysics Data System (ADS)

Jain, Siddharth R.

With the push for faster data transfer across all domains of telecommunication, optical interconnects are transitioning into shorter range applications such as in data centers and personal computing. Silicon photonics, with its economic advantages of leveraging well-established silicon manufacturing facilities, is considered the most promising approach to further scale down the cost and size of optical interconnects for chip-to-chip communication. Intrinsic properties of silicon however limit its ability to generate and modulate light, both of which are key to realizing on-chip optical data transfer. The hybrid silicon approach directly addresses this problem by using molecularly bonded III-V epitaxial layers on silicon for optical gain and absorption. This technology includes direct transfer of III-V wafer to a pre-patterned silicon-on-insulator wafer. Several discrete devices for light generation, modulation, amplification and detection have already been demonstrated on this platform. As in the case of electronics, multiple photonic elements can be integrated on a single chip to improve performance and functionality. However, scalable photonic integration requires the ability to control the bandgap for individual devices along with design changes to simplify fabrication. In the research presented here, quantum well intermixing is used as a technique to define multiple bandgaps for integration on the hybrid silicon platform. Implantation enhanced disordering is used to generate four bandgaps spread over 120+ nm. By combining these selectively intermixed III-V layers with pre-defined gratings and waveguides on silicon, we fabricate distributed feedback, distributed Bragg reflector, Fabry-Perot and mode-locked lasers along with photodetectors, electro-absorption modulators and other test structures, all on a single chip. We demonstrate a broadband laser source with continuous-wave operational lasers over a 200 nm bandwidth. Some of these lasers are integrated with modulators with a 3-dB bandwidth above 25 GHz, thus demonstrating coarse wavelength division multiplexing transmitter on silicon.

Decontaminating Solar Wind Samples with the Genesis Ultra-Pure Water Megasonic Wafer Spin Cleaner

NASA Technical Reports Server (NTRS)

Calaway, Michael J.; Rodriquez, M. C.; Allton, J. H.; Stansbery, E. K.

2009-01-01

The Genesis sample return capsule, though broken during the landing impact, contained most of the shattered ultra-pure solar wind collectors comprised of silicon and other semiconductor wafers materials. Post-flight analysis revealed that all wafer fragments were littered with surface particle contamination from spacecraft debris as well as soil from the impact site. This particulate contamination interferes with some analyses of solar wind. In early 2005, the Genesis science team decided to investigate methods for removing the surface particle contamination prior to solar wind analysis.

Influence of interfaces density and thermal processes on mechanical stress of PECVD silicon nitride

NASA Astrophysics Data System (ADS)

Picciotto, A.; Bagolini, A.; Bellutti, P.; Boscardin, M.

2009-10-01

The paper focuses on a particular silicon nitride thin film (SiN x) produced by plasma enahanced chemical vapor deposition (PECVD) technique with high deposition rate (26 nm/min) and low values of mechanical stress (<100 MPa). This was perfomed with mixed frequency procedure varying the modulation of high frequency at 13.56 MHz and low frequency at 308 kHz of RF power supply during the deposition, without changing the ratio of reaction gases. Low stress silicon nitride is commonly obtained by tailoring the thickness ratio of high frequency vs. low frequency silicon nitride layers. The attention of this work was directed to the influence of the number of interfaces per thickness unit on the stress characteristics of the deposited material. Two sets of wafer samples were deposited with low stress silicon nitride, with a thickness of 260 nm and 2 μm, respectively. Thermal annealing processes at 380 and 520 °C in a inert enviroment were also performed on the wafers. The Stoney-Hoffman model was used to estimate the stress values by wafer curvature measurement with a mechanical surface profilometer: the stress was calculated for the as-deposited layer, and after each annealing process. The thickness and the refractive index of the SiN x were also measured and charaterized by variable angle spectra elliposometry (VASE) techinique. The experimental measurements were performed at the MT-LAB, IRST (Istituto per la Ricerca Scientifica e Tecnologica) of Bruno Kessler Foundation for Research in Trento.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1997-09-02

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

New electron trap in p-type Czochralski silicon

NASA Technical Reports Server (NTRS)

Mao, B.-Y.; Lagowski, J.; Gatos, H. C.

1984-01-01

A new electron trap (acceptor level) was discovered in p-type Czochralski (CZ) silicon by current transient spectroscopy. The behavior of this trap was found to be similar to that of the oxygen thermal donors; thus, 450 C annealing increases the trap concentration while high-temperature annealing (1100-1200 C) leads to the virtual elimination of the trap. The new trap is not observed in either float-zone or n-type CZ silicon. Its energy level depends on the group III doping element in the sample. These findings suggest that the trap is related to oxygen, and probably to the acceptor impurity as well.

Resistivity Distribution of Multicrystalline Silicon Ingot Grown by Directional Solidification

NASA Astrophysics Data System (ADS)

Sun, S. H.; Tan, Y.; Dong, W.; Zhang, H. X.; Zhang, J. S.

2012-06-01

The effects of impurities on the resistivity distribution and polarity of multicrystalline silicon ingot prepared by directional solidification were investigated in this article. The shape of the equivalence line of the resistivity in the vertical and cross sections was determined by the solid-liquid interface. Along the solidification height of silicon ingot, the conductive type changed from p-type in the lower part of the silicon ingot to n-type in the upper part of the silicon ingot. The resistivity in the vertical section of the silicon ingot initially increased along the height of the solidified part, and reached its maximum at the polarity transition position, then decreased rapidly along the height of solidified part and approached zero on the top of the ingot because of the accumulation of impurities. The variation of resistivity in the vertical section of the ingot has been proven to be deeply relevant to the distribution of Al, B, and P in the growth direction of solidification.

Al+Si Interface Optical Properties Obtained in the Si Solar Cell Configuration

DOE Office of Scientific and Technical Information (OSTI.GOV)

Subedi, Indra; Silverman, Timothy J.; Deceglie, Michael G.

Al is a commonly used material for rear side metallization in commercial silicon (Si) wafer solar cells. In this study, through-the-silicon spectroscopic ellipsometry is used in a test sample to measure Al+Si interface optical properties like those in Si wafer solar cells. Two different spectroscopic ellipsometers are used for measurement of Al+Si interface optical properties over the 1128-2500 nm wavelength range. For validation, the measured interface optical properties are used in a ray tracing simulation over the 300-2500 nm wavelength range for an encapsulated Si solar cell having random pyramidal texture. The ray tracing model matches well with the measuredmore » total reflectance at normal incidence of a commercially available Si module. The Al+Si optical properties presented here enable quantitative assessment of major irradiance/current flux losses arising from reflection and parasitic absorption in encapsulated Si solar cells.« less

Silicon Alignment Pins: An Easy Way to Realize a Wafer-To-Wafer Alignment

NASA Technical Reports Server (NTRS)

Peralta, Alejandro (Inventor); Gill, John J. (Inventor); Toda, Risaku (Inventor); Lin, Robert H. (Inventor); Jung-Kubiak, Cecile (Inventor); Reck, Theodore (Inventor); Thomas, Bertrand (Inventor); Siles, Jose V. (Inventor); Lee, Choonsup (Inventor); Chattopadhyay, Goutam (Inventor)

2016-01-01

A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

Locally-enhanced light scattering by a monocrystalline silicon wafer

NASA Astrophysics Data System (ADS)

Ma, Li; Zhang, Pan; Li, Zhen-Hua; Liu, Chun-Xiang; Li, Xing; Zhan, Zi-Jun; Ren, Xiao-Rong; He, Chang-Wei; Chen, Chao; Cheng, Chuan-Fu

2018-03-01

We study the optical properties of light scattering by a monocrystalline silicon wafer, by using transparent material to replicate its surface structure and illuminating a fabricated sample with a laser source. The experimental results show that the scattering field contains four spots of concentrated intensity with high local energy, and these spots are distributed at the four vertices of a square with lines of intensity linking adjacent spots. After discussing simulations of and theory about the formation of this light scattering, we conclude that the scattering field is formed by the effects of both geometrical optics and physical optics. Moreover, we calculate the central angle of the spots in the light field, and the result indicates that the locally-enhanced intensity spots have a definite scattering angle. These results may possibly provide a method for improving energy efficiency within mono-Si based solar cells.

Forming high efficiency silicon solar cells using density-graded anti-reflection surfaces

DOEpatents

Yuan, Hao-Chih; Branz, Howard M.; Page, Matthew R.

2014-09-09

A method (50) is provided for processing a graded-density AR silicon surface (14) to provide effective surface passivation. The method (50) includes positioning a substrate or wafer (12) with a silicon surface (14) in a reaction or processing chamber (42). The silicon surface (14) has been processed (52) to be an AR surface with a density gradient or region of black silicon. The method (50) continues with heating (54) the chamber (42) to a high temperature for both doping and surface passivation. The method (50) includes forming (58), with a dopant-containing precursor in contact with the silicon surface (14) of the substrate (12), an emitter junction (16) proximate to the silicon surface (14) by doping the substrate (12). The method (50) further includes, while the chamber is maintained at the high or raised temperature, forming (62) a passivation layer (19) on the graded-density silicon anti-reflection surface (14).

Method for making circular tubular channels with two silicon wafers

DOEpatents

Yu, C.M.; Hui, W.C.

1996-11-19

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

MEMS based Low Cost Piezoresistive Microcantilever Force Sensor and Sensor Module.

PubMed

Pandya, H J; Kim, Hyun Tae; Roy, Rajarshi; Desai, Jaydev P

2014-03-01

In the present work, we report fabrication and characterization of a low-cost MEMS based piezoresistive micro-force sensor with SU-8 tip using laboratory made silicon-on-insulator (SOI) substrate. To prepare SOI wafer, silicon film (0.8 µm thick) was deposited on an oxidized silicon wafer using RF magnetron sputtering technique. The films were deposited in Argon (Ar) ambient without external substrate heating. The material characteristics of the sputtered deposited silicon film and silicon film annealed at different temperatures (400-1050°C) were studied using atomic force microscopy (AFM) and X-ray diffraction (XRD) techniques. The residual stress of the films was measured as a function of annealing temperature. The stress of the as-deposited films was observed to be compressive and annealing the film above 1050°C resulted in a tensile stress. The stress of the film decreased gradually with increase in annealing temperature. The fabricated cantilevers were 130 µm in length, 40 µm wide and 1.0 µm thick. A series of force-displacement curves were obtained using fabricated microcantilever with commercial AFM setup and the data were analyzed to get the spring constant and the sensitivity of the fabricated microcantilever. The measured spring constant and sensitivity of the sensor was 0.1488N/m and 2.7mV/N. The microcantilever force sensor was integrated with an electronic module that detects the change in resistance of the sensor with respect to the applied force and displays it on the computer screen.

MEMS based Low Cost Piezoresistive Microcantilever Force Sensor and Sensor Module

PubMed Central

Pandya, H. J.; Kim, Hyun Tae; Roy, Rajarshi; Desai, Jaydev P.

2014-01-01

In the present work, we report fabrication and characterization of a low-cost MEMS based piezoresistive micro-force sensor with SU-8 tip using laboratory made silicon-on-insulator (SOI) substrate. To prepare SOI wafer, silicon film (0.8 µm thick) was deposited on an oxidized silicon wafer using RF magnetron sputtering technique. The films were deposited in Argon (Ar) ambient without external substrate heating. The material characteristics of the sputtered deposited silicon film and silicon film annealed at different temperatures (400–1050°C) were studied using atomic force microscopy (AFM) and X-ray diffraction (XRD) techniques. The residual stress of the films was measured as a function of annealing temperature. The stress of the as-deposited films was observed to be compressive and annealing the film above 1050°C resulted in a tensile stress. The stress of the film decreased gradually with increase in annealing temperature. The fabricated cantilevers were 130 µm in length, 40 µm wide and 1.0 µm thick. A series of force-displacement curves were obtained using fabricated microcantilever with commercial AFM setup and the data were analyzed to get the spring constant and the sensitivity of the fabricated microcantilever. The measured spring constant and sensitivity of the sensor was 0.1488N/m and 2.7mV/N. The microcantilever force sensor was integrated with an electronic module that detects the change in resistance of the sensor with respect to the applied force and displays it on the computer screen. PMID:24855449

Fundamental Studies of the Mechanical Behavior of Microelectronic Thin Film Materials

DTIC Science & Technology

1991-01-01

scanning, wafer curvature technique to study the kinetics of crystallization of amorphous silicon. When a thin film of amorphous silicon crystallizes...the film and the kinetics of the crystallization process. We find the tensile stress in the film to increase by about 500 MPa when crystallization...occurs. This is a very large stress that could have significance for device processing and applications. By measuring the kinetics of this stress change

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1997-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Process Research on Polycrystalline Silicon Material (PROPSM)

NASA Technical Reports Server (NTRS)

Culik, J. S.

1983-01-01

The performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was investigated by measuring the illuminated current voltage (I-V) characteristics of the minicell wafer set. The average short circuit current on different wafers is 3 to 14 percent lower than that of single crystal Czochralski silicon. The scatter was typically less than 3 percent. The average open circuit voltage is 20 to 60 mV less than that of single crystal silicon. The scatter in the open circuit voltage of most of the polycrystalline silicon wafers was 15 to 20 mV, although two wafers had significantly greater scatter than this value. The fill factor of both polycrystalline and single crystal silicon cells was typically in the range of 60 to 70 percent; however several polycrystalline silicon wafers have fill factor averages which are somewhat lower and have a significantly larger degree of scatter.

High fill-factor micromirror array using a self-aligned vertical comb drive actuator with two rotational axes

NASA Astrophysics Data System (ADS)

Kim, Minsoo; Park, Jae-Hyoung; Jeon, Jin-A.; Yoo, Byung-Wook; Park, I. H.; Kim, Yong-Kweon

2009-03-01

We present a two-axis micromirror array with high fill-factor, using a new fabrication procedure on the full wafer scale. The micromirror comprises a self-aligned vertical comb drive actuator with a mirror plate mounted on it and electrical lines on a bottom substrate. A high-aspect-ratio vertical comb drive was built using a bulk micromachining technique on a silicon-on-insulator (SOI) wafer. The thickness of the torsion spring was adjusted using multiple silicon etching steps to enhance the static angular deflection of the mirrors. To address the array, electrical lines were fabricated on a glass substrate and combined with the comb actuators using an anodic bonding process. The silicon mirror plate was fabricated together with the actuator using a wafer bonding process and segmented at the final release step. The actuator and addressing lines were hidden behind the mirror plate, resulting in a high fill-factor of 84% in an 8 × 8 array of micromirrors, each 340 µm × 340 µm. The fabricated mirror plate has a high-quality optical surface with an average surface roughness (Ra) of 4 nm and a curvature radius of 0.9 m. The static and dynamic responses of the micromirror were characterized by comparing the measured results with the calculated values. The maximum static optical deflection for the outer axis is 4.32° at 60 V, and the maximum inner axis tilting angle is 2.82° at 96 V bias. The torsion resonance frequencies along the outer and inner axes were 1.94 kHz and 0.95 kHz, respectively.

Laser Beam Shaping

NASA Astrophysics Data System (ADS)

Aït-Ameur, Kamel; Passilly, Nicolas; de Saint Denis, R.; Fromager, Michaël

2008-09-01

We consider the promising properties of very simple Diffractive Optical Elements (DOE) for reshaping the intensity profile of a laser beam. The first type of DOE that we have considered is a phase aperture which consists in a transparent plate with a circular relief introducing a π phase shift in the central region of the incident beam. The phase aperture is able to convert a Gaussian beam into a super-Gaussian, a ring-shaped or a doughnut profile. The second DOE that has been considered is an adjustable axicon able to transform a Gaussian laser beam into a dark hollow beam or a Bessel-Gauss beam. The desired conical geometry is obtained from a deformable mirror formed by a 2 inches, 0.25mm thick silicon wafer supported by a standard 2 inches optical mount. To achieve the adequate deformation a small metallic ball pushes the back of the mirror wafer. The realized shape is monitored with a Shack-Hartmann wave-front sensor and it is shown that conical shape cannot be achieved. Nevertheless, recorded wave fronts exhibit important third order spherical aberration able to achieve beam profile transformation as conical lenses.

Pinch-off mechanism in double-lateral-gate junctionless transistors fabricated by scanning probe microscope based lithography

PubMed Central

Dehzangi, Arash; Abedini, Alam; Abdullah, Ahmad Makarimi; Saion, Elias; Hutagalung, Sabar D; Hamidon, Mohd N; Hassan, Jumiah

2012-01-01

Summary A double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (1015) silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with the numerical characteristics of the device. The simulation results are used to investigate the pinch-off mechanism, from the flat band to the off state. The study is based on the variation of the carrier density and the electric-field components. The device is a pinch-off transistor, which is normally in the on state and is driven into the off state by the application of a positive gate voltage. We demonstrate that the depletion starts from the bottom corner of the channel facing the gates and expands toward the center and top of the channel. Redistribution of the carriers due to the electric field emanating from the gates creates an electric field perpendicular to the current, toward the bottom of the channel, which provides the electrostatic squeezing of the current. PMID:23365794

Micro-miniature gas chromatograph column disposed in silicon wafers

DOEpatents

Yu, Conrad M.

2000-01-01

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Dissolution of Oxygen Precipitate Nuclei in n-Type CZ-Si Wafers to Improve Their Material Quality: Experimental Results

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, Bhushan; Basnyat, Prakash; Devayajanam, Srinivas

2017-01-01

We present experimental results which show that oxygen-related precipitate nuclei (OPN) present in p-doped, n-type, Czochralski wafers can be dissolved using a flash-annealing process, yielding very high quality wafers for high-efficiency solar cells. Flash annealing consists of heating a wafer in an optical furnace to temperature between 1150 and 1250 degrees C for a short time. This process produces a large increase in the minority carrier lifetime (MCLT) and homogenizes each wafer. We have tested wafers from different axial locations of two ingots. All wafers reach nearly the same high value of MCLT. The OPN dissolution is confirmed by oxygenmore » analysis using Fourier transform infrared spectra and injection-level dependence of MCLT.« less

Dislocation-free strained silicon-on-silicon by in-place bonding

NASA Astrophysics Data System (ADS)

Cohen, G. M.; Mooney, P. M.; Paruchuri, V. K.; Hovel, H. J.

2005-06-01

In-place bonding is a technique where silicon-on-insulator (SOI) slabs are bonded by hydrophobic attraction to the underlying silicon substrate when the buried oxide is undercut in dilute HF. The bonding between the exposed surfaces of the SOI slab and the substrate propagates simultaneously with the buried oxide etching. As a result, the slabs maintain their registration and are referred to as "bonded in-place". We report the fabrication of dislocation-free strained silicon slabs from pseudomorphic trilayer Si/SiGe/SOI by in-place bonding. Removal of the buried oxide allows the compressively strained SiGe film to relax elastically and induce tensile strain in the top and bottom silicon films. The slabs remain bonded to the substrate by van der Waals forces when the wafer is dried. Subsequent annealing forms a covalent bond such that when the upper Si and the SiGe layer are removed, the bonded silicon slab remains strained.

Silicon materials task of the low-cost solar array project. Phase 4: Effects of impurities and processing on silicon solar cells

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Hanes, M. H.; Davis, J. R.; Rohatgi, A.; Raichoudhury, P.; Mollenkopf, H. C.

1981-01-01

The results of the study form a basis for silicon producers, wafer manufacturers, and cell fabricators to develop appropriate cost-benefit relationships for the use of less pure, less costly solar grade silicon. Cr is highly mobile in silicon even at temperatures as low as 600 C. Contrasting with earlier data for Mo, Ti, and V, Cr concentrations vary from place to place in polycrystalline silicon wafers and the electrically-active Cr concentration in the polysilicon is more than an order of magnitude smaller than would be projected from single crystal impurity data. We hypothesize that Cr diffuses during ingot cooldown after growth, preferentially segregates to grain and becomes electrically deactivated. Accelerated aging data from Ni-contaminated silicon imply that no significant impurity-induced cell performance reduction should be expected over a twenty year device lifetime.

High-performance field emission device utilizing vertically aligned carbon nanotubes-based pillar architectures

NASA Astrophysics Data System (ADS)

Gupta, Bipin Kumar; Kedawat, Garima; Gangwar, Amit Kumar; Nagpal, Kanika; Kashyap, Pradeep Kumar; Srivastava, Shubhda; Singh, Satbir; Kumar, Pawan; Suryawanshi, Sachin R.; Seo, Deok Min; Tripathi, Prashant; More, Mahendra A.; Srivastava, O. N.; Hahm, Myung Gwan; Late, Dattatray J.

2018-01-01

The vertical aligned carbon nanotubes (CNTs)-based pillar architectures were created on laminated silicon oxide/silicon (SiO2/Si) wafer substrate at 775 °C by using water-assisted chemical vapor deposition under low pressure process condition. The lamination was carried out by aluminum (Al, 10.0 nm thickness) as a barrier layer and iron (Fe, 1.5 nm thickness) as a catalyst precursor layer sequentially on a silicon wafer substrate. Scanning electron microscope (SEM) images show that synthesized CNTs are vertically aligned and uniformly distributed with a high density. The CNTs have approximately 2-30 walls with an inner diameter of 3-8 nm. Raman spectrum analysis shows G-band at 1580 cm-1 and D-band at 1340 cm-1. The G-band is higher than D-band, which indicates that CNTs are highly graphitized. The field emission analysis of the CNTs revealed high field emission current density (4mA/cm2 at 1.2V/μm), low turn-on field (0.6 V/μm) and field enhancement factor (6917) with better stability and longer lifetime. Emitter morphology resulting in improved promising field emission performances, which is a crucial factor for the fabrication of pillared shaped vertical aligned CNTs bundles as practical electron sources.

Hall mobility in multicrystalline silicon

NASA Astrophysics Data System (ADS)

Schindler, F.; Geilker, J.; Kwapil, W.; Warta, W.; Schubert, M. C.

2011-08-01

Knowledge of the carrier mobility in silicon is of utmost importance for photovoltaic applications, as it directly influences the diffusion length and thereby the cell efficiency. Moreover, its value is needed for a correct quantitative evaluation of a variety of lifetime measurements. However, models that describe the carrier mobility in silicon are based on theoretical calculations or fits to experimental data in monocrystalline silicon. Multicrystalline (mc) silicon features crystal defects such as dislocations and grain boundaries, with the latter possibly leading to potential barriers through the trapping of charge carriers and thereby influencing the mobility, as shown, for example, by Maruska et al. [Appl. Phys. Lett. 36, 381 (1980)]. To quantify the mobilities in multicrystalline silicon, we performed Hall measurements in p-type mc-Si samples of various resistivities and different crystal structures and compared the data to majority carrier Hall mobilities in p-type monocrystalline floatzone (FZ) silicon. For lack of a model that provides reliable values of the Hall mobility in silicon, an empirical fit similar to existing models for conductivity mobilities is proposed based on Hall measurements of monocrystalline p-type FZ silicon. By comparing the measured Hall mobilities obtained from mc silicon with the corresponding Hall mobilities in monocrystalline silicon of the same resistivity, we found that the mobility reduction due to the presence of crystal defects in mc-Si ranges between 0% and 5% only. Mobility decreases of up to 30% as reported by Peter et al. [Proceedings of the 23rd European Photovoltaic Solar Energy Conference, Valencia, Spain, 1-5 September 2008], or even of a factor of 2 to 3 as detected by Palais et al. [Mater. Sci. Eng. B 102, 184 (2003)], in multicrystalline silicon were not observed.

Thin EFG octagons

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-01-01

Mobil Solar Energy Corporation currently practices a unique crystal growth technology for producing crystalline silicon sheet, which is then cut with lasers into wafers. The wafers are processed into solar cells and incorporated into modules for photovoltaic applications. The silicon sheet is produced using a method known as Edge-defined Film-fed growth (EFG), in the form of hollow eight-sided polygons (octagons) with 10 cm faces. These are grown to lengths of 5 meters and thickness of 300 microns, with continuous melt replenishment, in compact furnaces designed to operate at a high sheet area production area of 135 sq cm/min. The present Photovoltaic Manufacturing Technology (PVMaT) three-year program seeks to advance the manufacturing line capabilities of the Mobil Solar crystal growth and cutting technologies. If successful, these advancements will provide significant reductions in already low silicon raw material usage, improve process productivity, laser cutting throughput and yield, and so lower both individual wafer cost and the cost of module production. This report summarizes the significant technical improvements in EFG technology achieved in Phase 1 of this program. Technical results are reported for each of the three main program areas: (1) thin octagon growth (crystal growth) -- to reduce the thickness of the octagon to an interim goal of 250 microns during Phase 1, with an ultimate goal of achieving 200 micron thicknesses; (2) laser cutting -- to improve the laser cutting process, so as to produce wafers with decreased laser cutting damage at increased wafer throughput rates; and (3) process control and product specification -- to implement advanced strategies in crystal growth process control and productivity designed to increase wafer yields.

Chemical shift and surface characteristics of Al-doped ZnO thin film on SiOC dielectrics.

PubMed

Oh, Teresa; Lee, Sang Yeol

2013-10-01

Aluminum doped zinc oxide (AZO) films were fabricated on SiOC/p-Si wafer and SiOC film was prepared on a p-type Si substrate with the SiC target at oxygen ambient with the gas flow rate of 5-30 sccm by a RF magnetron sputter. C-V curve of SiOC/Si wafer was measured to observe the relationship between the polarity of SiOC dielectrics and the change of capacitance depending on oxygen gas flow rate. The SiOC film could be controlled to be polar or nonpolar, and their surface energy was changed depending on the polarity. Smooth surface is essential to improve the TFT performance. AZO-TFTs used smooth SiOC film with low polarity as a gate insulator was observed to show low leakage current (IL) and low subthreshold voltage swing. It is proposed that SiOC film with high degree amorphous structure as a gate insulator between AZO and Si wafer could solve problems of the mismatched interfaces, which was originated from the electron scattering due to the grain boundary.

NIR spectrometer using a Schottky photodetector enhanced by grating-based SPR.

PubMed

Chen, Wenjing; Kan, Tetsuo; Ajiki, Yoshiharu; Matsumoto, Kiyoshi; Shimoyama, Isao

2016-10-31

We present a near-infrared (NIR) spectrum measurement method using a Schottky photodetector enhanced by surface plasmon resonance (SPR). An Au grating was fabricated on an n-type silicon wafer to form a Schottky barrier and act as an SPR coupler. The resulting photodetector provides wavelength-selective photodetection depending on the SPR coupling angle. A matrix was pre-calculated to describe this characteristic. The spectrum was obtained from this matrix and the measured photocurrents at various SPR coupling angles. Light with single and multiple wavelengths was tested. Comparative measurements showed that our method is able to detect spectra with a wavelength resolution comparable to that of a commercial spectrometer.

Ultra-Shallow Depth Profiling of Arsenic Implants in Silicon by Hydride Generation-Inductively Coupled Plasma Atomic Emission Spectrometry

NASA Astrophysics Data System (ADS)

Matsubara, Atsuko; Kojima, Hisao; Itoga, Toshihiko; Kanehori, Keiichi

1995-08-01

High resolution depth profiling of arsenic (As) implanted into silicon wafers by a chemical technique is described. Silicon wafers are precisely etched through repeated oxidation by hydrogen peroxide solution and dissolution of the oxide by hydrofluoric acid solution. The etched silicon thickness is determined by inductively-coupled plasma atomic emission spectrometry (ICP-AES). Arsenic concentration is determined by hydride generation ICP-AES (HG-ICP-AES) with prereduction using potassium iodide. The detection limit of As in a 4-inch silicon wafer is 2.4×1018 atoms/cm3. The etched silicon thickness is controlled to less than 4±2 atomic layers. Depth profiling of an ultra-shallow As diffusion layer with the proposed method shows good agreement with profiling using the four-probe method or secondary ion mass spectrometry.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1995-05-09

A method is disclosed for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Nanowires from dirty multi-crystalline Si for hydrogen generation

NASA Astrophysics Data System (ADS)

Li, Xiaopeng; Schweizer, Stefan L.; Sprafke, Alexander; Wehrspohn, Ralf B.

2013-09-01

Silicon nanowires are considered as a promising architecture for solar energy conversion systems. By metal assisted chemical etching of multi-crystalline upgraded metallurgical silicon (UMG-Si), large areas of silicon nanowires (SiNWs) with high quality can be produced on the mother substrates. These areas show a low reflectance comparable to black silicon. More interestingly, we find that various metal impurities inside UMG-Si are removed due to the etching through element analysis. A prototype cell was built to test the photoelectrochemical (PEC) properties of UMG-SiNWs for water splitting. The on-set potential for hydrogen evolution was much reduced, and the photocurrent density showed an increment of 35% in comparison with a `dirty' UMG-Si wafer.

Boron doping a semiconductor particle

DOEpatents

Stevens, Gary Don; Reynolds, Jeffrey Scott; Brown, Louanne Kay

1998-06-09

A method (10,30) of boron doping a semiconductor particle using boric acid to obtain a p-type doped particle. Either silicon spheres or silicon powder is mixed with a diluted solution of boric acid having a predetermined concentration. The spheres are dried (16), with the boron film then being driven (18) into the sphere. A melt procedure mixes the driven boron uniformly throughout the sphere. In the case of silicon powder, the powder is metered out (38) into piles and melted/fused (40) with an optical furnace. Both processes obtain a p-type doped silicon sphere with desired resistivity. Boric acid is not a restricted chemical, is inexpensive, and does not pose any special shipping, handling, or disposal requirements.

High-Efficiency Silicon/Organic Heterojunction Solar Cells with Improved Junction Quality and Interface Passivation.

PubMed

He, Jian; Gao, Pingqi; Ling, Zhaoheng; Ding, Li; Yang, Zhenhai; Ye, Jichun; Cui, Yi

2016-12-27

Silicon/organic heterojunction solar cells (HSCs) based on conjugated polymers, poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS), and n-type silicon (n-Si) have attracted wide attention due to their potential advantages of high efficiency and low cost. However, the state-of-the-art efficiencies are still far from satisfactory due to the inferior junction quality. Here, facile treatments were applied by pretreating the n-Si wafer in tetramethylammonium hydroxide (TMAH) solution and using a capping copper iodide (CuI) layer on the PEDOT:PSS layer to achieve a high-quality Schottky junction. Detailed photoelectric characteristics indicated that the surface recombination was greatly suppressed after TMAH pretreatment, which increased the thickness of the interfacial oxide layer. Furthermore, the CuI capping layer induced a strong inversion layer near the n-Si surface, resulting in an excellent field effect passivation. With the collaborative improvements in the interface chemical and electrical passivation, a competitive open-circuit voltage of 0.656 V and a high fill factor of 78.1% were achieved, leading to a stable efficiency of over 14.3% for the planar n-Si/PEDOT:PSS HSCs. Our findings suggest promising strategies to further exploit the full voltage as well as efficiency potentials for Si/organic solar cells.

Trimming of silicon ring resonator by electron beam induced compaction and strain.

PubMed

Schrauwen, J; Van Thourhout, D; Baets, R

2008-03-17

Silicon is becoming the preferable platform for future integrated components, mostly due to the mature and reliable fabrication capabilities of electronics industry. Nevertheless, even the most advanced fabrication technologies suffer from non-uniformity on wafer scale and on chip scale, causing variations in the critical dimensions of fabricated components. This is an important issue since photonic circuits, and especially cavities such as ring resonators, are extremely sensitive to these variations. In this paper we present a way to circumvent these problems by trimming using electron beam induced compaction of oxide in silicon on insulator. Volume compaction of the oxide cladding causes both changes in the refractive index and creates strain in the silicon lattice. We demonstrate a resonance wavelength red shift 4.91 nm in a silicon ring resonator.

Investigation of Backside Textures for Genesis Solar Wind Silicon Collectors

NASA Technical Reports Server (NTRS)

Gonzalez, C. P.; Burkett, P. J.; Rodriguez, M. C.; Allton, J. H.

2014-01-01

Genesis solar wind collectors were comprised of a suite of 15 types of ultrapure materials. The single crystal, pure silicon collectors were fabricated by two methods: float zone (FZ) and Czochralski (CZ). Because of slight differences in bulk purity and surface cleanliness among the fabrication processes and the specific vendor, it is desirable to know which variety of silicon and identity of vendor, so that appropriate reference materials can be used. The Czochralski method results in a bulk composition with slightly higher oxygen, for example. The CZ silicon array wafers that were Genesis-flown were purchased from MEMC Electronics. Most of the Genesis-flown FZ silicon was purchased from Unisil and cleaned by MEMC, although a few FZ wafers were acquired from International Wafer Service (IWS).

Silicon Carbide High-Temperature Power Rectifiers Fabricated and Characterized

NASA Technical Reports Server (NTRS)

1996-01-01

The High Temperature Integrated Electronics and Sensors (HTIES) team at the NASA Lewis Research Center is developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. Silicon carbide's demonstrated ability to function under extreme high-temperature, high power, and/or high-radiation conditions will enable significant improvements to a far ranging variety of applications and systems. These improvements range from improved high-voltage switching for energy savings in public electric power distribution and electric vehicles, to more powerful microwave electronics for radar and cellular communications, to sensors and controls for cleaner-burning, more fuel-efficient jet aircraft and automobile engines. In the case of jet engines, uncooled operation of 300 to 600 C SiC power actuator electronics mounted in key high-temperature areas would greatly enhance system performance and reliability. Because silicon cannot function at these elevated temperatures, the semiconductor device circuit components must be made of SiC. Lewis' HTIES group recently fabricated and characterized high-temperature SiC rectifier diodes whose record-breaking characteristics represent significant progress toward the realization of advanced high-temperature actuator control circuits. The first figure illustrates the 600 C probe-testing of a Lewis SiC pn-junction rectifier diode sitting on top of a glowing red-hot heating element. The second figure shows the current-versus voltage rectifying characteristics recorded at 600 C. At this high temperature, the diodes were able to "turn-on" to conduct 4 A of current when forward biased, and yet block the flow of current ($quot;turn-off") when reverse biases as high as 150 V were applied. This device represents a new record for semiconductor device operation, in that no previous semiconductor electronic device has ever simultaneously demonstrated 600 C functionality, and 4-A turn-on and 150-V rectification. The high operating current was achieved despite severe device size limitations imposed by present-day SiC wafer defect densities. Further substantial increases in device performance can be expected when SiC wafer defect densities decrease as SiC wafer production technology matures.

CMUT Fabrication Based On A Thick Buried Oxide Layer

PubMed Central

Kupnik, Mario; Vaithilingam, Srikant; Torashima, Kazutoshi; Wygant, Ira O.; Khuri-Yakub, Butrus T.

2010-01-01

We introduce a versatile fabrication process for direct wafer-bonded CMUTs. The objective is a flexible fabrication platform for single element transducers, 1D and 2D arrays, and reconfigurable arrays. The main process features are: A low number of litho masks (five for a fully populated 2D array); a simple fabrication sequence on standard MEMS tools without complicated wafer handling (carrier wafers); an improved device reliability; a wide design space in terms of operation frequency and geometric parameters (cell diameter, gap height, effective insulation layer thickness); and a continuous front face of the transducer (CMUT plate) that is connected to ground (shielding for good SNR and human safety in medical applications). All of this is achieved by connecting the hot electrodes individually through a thick buried oxide layer, i.e. from the handle layer of an SOI substrate to silicon electrodes located in each CMUT cell built in the device layer. Vertical insulation trenches are used to isolate these silicon electrodes from the rest of the substrate. Thus, the high electric field is only present where required – in the evacuated gap region of the device and not in the insulation layer of the post region. Array elements (1D and 2D) are simply defined be etching insulation trenches into the handle wafer of the SOI substrate. PMID:22685377

Development of Silver-Free Silicon Photovoltaic Solar Cells with All-Aluminum Electrodes

NASA Astrophysics Data System (ADS)

Sun, Wen-Cheng

To date, the most popular and dominant material for commercial solar cells is crystalline silicon (or wafer-Si). It has the highest cell efficiency and cell lifetime out of all commercial solar cells. Although the potential of crystalline-Si solar cells in supplying energy demands is enormous, their future growth will likely be constrained by two major bottlenecks. The first is the high electricity input to produce crystalline-Si solar cells and modules, and the second is the limited supply of silver (Ag) reserves. These bottlenecks prevent crystalline-Si solar cells from reaching terawatt-scale deployment, which means the electricity produced by crystalline-Si solar cells would never fulfill a noticeable portion of our energy demands in the future. In order to solve the issue of Ag limitation for the front metal grid, aluminum (Al) electroplating has been developed as an alternative metallization technique in the fabrication of crystalline-Si solar cells. The plating is carried out in a near-room-temperature ionic liquid by means of galvanostatic electrolysis. It has been found that dense, adherent Al deposits with resistivity in the high 10--6 Ω-cm range can be reproducibly obtained directly on Si substrates and nickel seed layers. An all-Al Si solar cell, with an electroplated Al front electrode and a screen-printed Al back electrode, has been successfully demonstrated based on commercial p-type monocrystalline-Si solar cells, and its efficiency is approaching 15%. Further optimization of the cell fabrication process, in particular a suitable patterning technique for the front silicon nitride layer, is expected to increase the efficiency of the cell to ~18%. This shows the potential of Al electroplating in cell metallization is promising and replacing Ag with Al as the front finger electrode is feasible.

High performance InAs quantum dot lasers on silicon substrates by low temperature Pd-GaAs wafer bonding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Zihao; Preble, Stefan F.; Yao, Ruizhe

2015-12-28

InAs quantum dot (QD) laser heterostructures have been grown by molecular beam epitaxy system on GaAs substrates, and then transferred to silicon substrates by a low temperature (250 °C) Pd-mediated wafer bonding process. A low interfacial resistivity of only 0.2 Ω cm{sup 2} formed during the bonding process is characterized by the current-voltage measurements. The InAs QD lasers on Si exhibit comparable characteristics to state-of-the-art QD lasers on silicon substrates, where the threshold current density J{sub th} and differential quantum efficiency η{sub d} of 240 A/cm{sup 2} and 23.9%, respectively, at room temperature are obtained with laser bars of cavity length and waveguide ridgemore » of 1.5 mm and 5 μm, respectively. The InAs QD lasers also show operation up to 100 °C with a threshold current density J{sub th} and differential quantum efficiency η{sub d} of 950 A/cm{sup 2} and 9.3%, respectively. The temperature coefficient T{sub 0} of 69 K from 60 to 100 °C is characterized from the temperature dependent J{sub th} measurements.« less

Design and fabrication of a foldable 3D silicon based package for solid state lighting applications

NASA Astrophysics Data System (ADS)

Sokolovskij, R.; Liu, P.; van Zeijl, H. W.; Mimoun, B.; Zhang, G. Q.

2015-05-01

Miniaturization of solid state lighting (SSL) luminaires as well as reduction of packaging and assembly costs are of prime interest for the SSL lighting industry. A novel silicon based LED package for lighting applications is presented in this paper. The proposed design consists of 5 rigid Si tiles connected by flexible polyimide hinges with embedded interconnects (ICs). Electrical, optical and thermal characteristics were taken into consideration during design. The fabrication process involved polyimide (PI) application and patterning, aluminium interconnect integration in the flexible hinge, LED reflector cavity formation and metalization followed by through wafer DRIE etching for chip formation and release. A method to connect chip front to backside without TSVs was also integrated into the process. Post-fabrication wafer level assembly included LED mounting and wirebond, phosphor-based colour conversion and silicone encapsulation. The package formation was finalized by vacuum assisted wrapping around an assembly structure to form a 3D geometry, which is beneficial for omnidirectional lighting. Bending tests were performed on the flexible ICs and optical performance at different temperatures was evaluated. It is suggested that 3D packages can be expanded to platforms for miniaturized luminaire applications by combining monolithic silicon integration and system-in-package (SiP) technologies.

Boron doping a semiconductor particle

DOEpatents

Stevens, G.D.; Reynolds, J.S.; Brown, L.K.

1998-06-09

A method of boron doping a semiconductor particle using boric acid to obtain a p-type doped particle. Either silicon spheres or silicon powder is mixed with a diluted solution of boric acid having a predetermined concentration. The spheres are dried, with the boron film then being driven into the sphere. A melt procedure mixes the driven boron uniformly throughout the sphere. In the case of silicon powder, the powder is metered out into piles and melted/fused with an optical furnace. Both processes obtain a p-type doped silicon sphere with desired resistivity. Boric acid is not a restricted chemical, is inexpensive, and does not pose any special shipping, handling, or disposal requirements. 2 figs.

Detecting Fermi-level shifts by Auger electron spectroscopy in Si and GaAs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Debehets, J.; Homm, P.; Menghini, M.

In this paper, changes in surface Fermi-level of Si and GaAs, caused by doping and cleaning, are investigated by Auger electron spectroscopy. Based on the Auger voltage contrast, we compared the Auger transition peak energy but with higher accuracy by using a more accurate detector and an improved peak position determination method. For silicon, a peak shift as large as 0.46 eV was detected when comparing a cleaned p-type and n-type wafer, which corresponds rather well with the theoretical difference in Fermi-level. If no cleaning was applied, the peak position did not differ significantly for both wafer types, indicating Fermi-levelmore » pinning in the band gap. For GaAs, peak shifts were detected after cleaning with HF and (NH4)2S-solutions in an inert atmosphere (N2-gas). Although the (NH4)2S-cleaning in N2 is very efficient in removing the oxygen from the surface, the observed Ga- and As-peak shifts are smaller than those obtained after the HF-cleaning. It is shown that the magnitude of the shift is related to the surface composition. After Si-deposition on the (NH4)2S-cleaned surface, the Fermi-level shifts back to a similar position as observed for an as-received wafer, indicating that this combination is not successful in unpinning the Fermi-level of GaAs. This work has been funded by J.D.'s PhD fellowship of the Fund of Scientific Research-Flanders (FWO-V) (Dossier No. 11U4516N). P.H. acknowledges support from Becas Chile-CONICYT. This research was also supported by the FWO Odysseus Program, the Belgian Hercules Stichting with the Project No. Her/08/25 and AKUL/13/19 and the KU Leuven project GOA "Fundamental challenges in Semiconductor Research". The authors would also like to thank Bastiaan Opperdoes and Ludwig Henderix for technical support. The work was supported by the U.S. Department of Energy (USDOE), Office of Science, Office of Basic Energy Sciences, Division of Materials Sciences and Engineering, and performed in the Environmental Molecular Sciences Laboratory, a national scientific user facility sponsored by the Department of Energy's Office of Biological and Environmental Research and located at Pacific Northwest National Laboratory (PNNL). Battelle operates PNNL for the USDOE under contract DE-AC05-76RL01830.« less

Contactless measurement of electrical conductivity of semiconductor wafers using the reflection of millimeter waves

NASA Astrophysics Data System (ADS)

Ju, Yang; Inoue, Kojiro; Saka, Masumi; Abe, Hiroyuki

2002-11-01

We present a method for quantitative measurement of electrical conductivity of semiconductor wafers in a contactless fashion by using millimeter waves. A focusing sensor was developed to focus a 110 GHz millimeter wave beam on the surface of a silicon wafer. The amplitude and the phase of the reflection coefficient of the millimeter wave signal were measured by which electrical conductivity of the wafer was determined quantitatively, independent of the permittivity and thickness of the wafers. The conductivity obtained by this method agrees well with that measured by the conventional four-point-probe method.