Interferometric thickness calibration of 300 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Quandou; Griesmann, Ulf; Polvani, Robert

2005-12-01

The "Improved Infrared Interferometer" (IR 3) at the National Institute of Standards and Technology (NIST) is a phase-measuring interferometer, operating at a wavelength of 1550 nm, which is being developed for measuring the thickness and thickness variation of low-doped silicon wafers with diameters up to 300 mm. The purpose of the interferometer is to produce calibrated silicon wafers, with a certified measurement uncertainty, which can be used as reference wafers by wafer manufacturers and metrology tool manufacturers. We give an overview of the design of the interferometer and discuss its application to wafer thickness measurements. The conversion of optical thickness, as measured by the interferometer, to the wafer thickness requires knowledge of the refractive index of the material of the wafer. We describe a method for measuring the refractive index which is then used to establish absolute thickness and thickness variation maps for the wafer.

Micro-miniature gas chromatograph column disposed in silicon wafers

DOEpatents

Yu, Conrad M.

2000-01-01

A micro-miniature gas chromatograph column is fabricated by forming matching halves of a circular cross-section spiral microcapillary in two silicon wafers and then bonding the two wafers together using visual or physical alignment methods. Heating wires are deposited on the outside surfaces of each wafer in a spiral or serpentine pattern large enough in area to cover the whole microcapillary area inside the joined wafers. The visual alignment method includes etching through an alignment window in one wafer and a precision-matching alignment target in the other wafer. The two wafers are then bonded together using the window and target. The physical alignment methods include etching through vertical alignment holes in both wafers and then using pins or posts through corresponding vertical alignment holes to force precision alignment during bonding. The pins or posts may be withdrawn after curing of the bond. Once the wafers are bonded together, a solid phase of very pure silicone is injected in a solution of very pure chloroform into one end of the microcapillary. The chloroform lowers the viscosity of the silicone enough that a high pressure hypodermic needle with a thumbscrew plunger can force the solution into the whole length of the spiral microcapillary. The chloroform is then evaporated out slowly to leave the silicone behind in a deposit.

Guided ultrasonic wave beam skew in silicon wafers

NASA Astrophysics Data System (ADS)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2018-04-01

In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

Silicon wafer-based tandem cells: The ultimate photovoltaic solution?

NASA Astrophysics Data System (ADS)

Green, Martin A.

2014-03-01

Recent large price reductions with wafer-based cells have increased the difficulty of dislodging silicon solar cell technology from its dominant market position. With market leaders expected to be manufacturing modules above 16% efficiency at 0.36/Watt by 2017, even the cost per unit area (60-70/m2) will be difficult for any thin-film photovoltaic technology to significantly undercut. This may make dislodgement likely only by appreciably higher energy conversion efficiency approaches. A silicon wafer-based cell able to capitalize on on-going cost reductions within the mainstream industry, but with an appreciably higher than present efficiency, might therefore provide the ultimate PV solution. With average selling prices of 156 mm quasi-square monocrystalline Si photovoltaic wafers recently approaching 1 (per wafer), wafers now provide clean, low cost templates for overgrowth of thin, wider bandgap high performance cells, nearly doubling silicon's ultimate efficiency potential. The range of possible Si-based tandem approaches is reviewed together with recent results and ultimate prospects.

Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

NASA Astrophysics Data System (ADS)

Ostapenko, S.; Tarasov, I.

2000-04-01

A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

Smoother Scribing of Silicon Wafers

NASA Technical Reports Server (NTRS)

Danyluk, S.

1986-01-01

Proposed new tool used to scribe silicon wafers into chips more smoothly than before. New scriber produces surface that appears ductile. Scribed groove cuts have relatively smooth walls. Scriber consists of diamond pyramid point on rigid shaft. Ethanol flows through shaft and around point, like ink in ballpoint pen. Ethanol has significantly different effect for scribing silicon than water, used in conventional diamond scribers.

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

PubMed

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

Material electronic quality specifications for polycrystalline silicon wafers

NASA Astrophysics Data System (ADS)

Kalejs, J. P.

1994-06-01

As the use of polycrystalline silicon wafers has expanded in the photovoltaic industry, the need grows for monitoring and qualification techniques for as-grown material that can be used to optimize crystal growth and help predict solar cell performance. Particular needs are for obtaining quantitative measures over full wafer areas of the effects of lifetime limiting defects and of the lifetime upgrading taking place during solar cell processing. We review here the approaches being pursued in programs under way to develop material quality specifications for thin Edge-defined Film-fed Growth (EFG) polycrystalline silicon as-grown wafers. These studies involve collaborations between Mobil Solar, and NREL and university-based laboratories.

Method for making circular tubular channels with two silicon wafers

DOEpatents

Yu, C.M.; Hui, W.C.

1996-11-19

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si{sub 3}N{sub 4}) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO{sub 3}/CH{sub 3}COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary. 11 figs.

Method for making circular tubular channels with two silicon wafers

DOEpatents

Yu, Conrad M.; Hui, Wing C.

1996-01-01

A two-wafer microcapillary structure is fabricated by depositing boron nitride (BN) or silicon nitride (Si.sub.3 N.sub.4) on two separate silicon wafers (e.g., crystal-plane silicon with [100] or [110] crystal orientation). Photolithography is used with a photoresist to create exposed areas in the deposition for plasma etching. A slit entry through to the silicon is created along the path desired for the ultimate microcapillary. Acetone is used to remove the photoresist. An isotropic etch, e.g., such as HF/HNO.sub.3 /CH.sub.3 COOH, then erodes away the silicon through the trench opening in the deposition layer. A channel with a half-circular cross section is then formed in the silicon along the line of the trench in the deposition layer. Wet etching is then used to remove the deposition layer. The two silicon wafers are aligned and then bonded together face-to-face to complete the microcapillary.

The Imaging Properties of a Silicon Wafer X-Ray Telescope

NASA Technical Reports Server (NTRS)

Joy, M. K.; Kolodziejczak, J. J.; Weisskopf, M. C.; Fair, S.; Ramsey, B. D.

1994-01-01

Silicon wafers have excellent optical properties --- low microroughness and good medium-scale flatness --- which Make them suitable candidates for inexpensive flat-plate grazing-incidence x-ray mirrors. On short spatial scales (less than 3 mm) the surface quality of silicon wafers rivals that expected of the Advanced X-Ray Astrophysics Facility (AXAF) high-resolution optics. On larger spatial scales, however, performance may be degraded by the departure from flatness of the wafer and by distortions induced by the mounting scheme. In order to investigate such effects, we designed and constructed a prototype silicon-wafer x-ray telescope. The device was then tested in both visible light and x rays. The telescope module consists of 94 150-mm-diameter wafers, densely packed into the first stage of a Kirkpatrick-Baez configuration. X-ray tests at three energies (4.5, 6.4, and 8.0 keV) showed an energy-independent line spread function with full width at half maximum (FWHM) of 150 arcseconds, dominated by deviations from large-scale flatness.

Advancements in n-Type Base Crystalline Silicon Solar Cells and Their Emergence in the Photovoltaic Industry

PubMed Central

ur Rehman, Atteq; Lee, Soo Hong

2013-01-01

The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed. PMID:24459433

Advancements in n-type base crystalline silicon solar cells and their emergence in the photovoltaic industry.

PubMed

ur Rehman, Atteq; Lee, Soo Hong

2013-01-01

The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed.

Towards ultra-thin plasmonic silicon wafer solar cells with minimized efficiency loss.

PubMed

Zhang, Yinan; Stokes, Nicholas; Jia, Baohua; Fan, Shanhui; Gu, Min

2014-05-13

The cost-effectiveness of market-dominating silicon wafer solar cells plays a key role in determining the competiveness of solar energy with other exhaustible energy sources. Reducing the silicon wafer thickness at a minimized efficiency loss represents a mainstream trend in increasing the cost-effectiveness of wafer-based solar cells. In this paper we demonstrate that, using the advanced light trapping strategy with a properly designed nanoparticle architecture, the wafer thickness can be dramatically reduced to only around 1/10 of the current thickness (180 μm) without any solar cell efficiency loss at 18.2%. Nanoparticle integrated ultra-thin solar cells with only 3% of the current wafer thickness can potentially achieve 15.3% efficiency combining the absorption enhancement with the benefit of thinner wafer induced open circuit voltage increase. This represents a 97% material saving with only 15% relative efficiency loss. These results demonstrate the feasibility and prospect of achieving high-efficiency ultra-thin silicon wafer cells with plasmonic light trapping.

Multi-wire slurry wafering demonstrations. [slicing silicon ingots for solar arrays

NASA Technical Reports Server (NTRS)

Chen, C. P.

1978-01-01

Ten slicing demonstrations on a multi-wire slurry saw, made to evaluate the silicon ingot wafering capabilities, reveal that the present sawing capabilities can provide usable wafer area from an ingot 1.05m/kg (e.g. kerf width 0.135 mm and wafer thickness 0.265 mm). Satisfactory surface qualities and excellent yield of silicon wafers were found. One drawback is that the add-on cost of producing water from this saw, as presently used, is considerably higher than other systems being developed for the low-cost silicon solar array project (LSSA), primarily because the saw uses a large quantity of wire. The add-on cost can be significantly reduced by extending the wire life and/or by rescue of properly plated wire to restore the diameter.

Surface etching technologies for monocrystalline silicon wafer solar cells

NASA Astrophysics Data System (ADS)

Tang, Muzhi

With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

High frequency guided wave propagation in monocrystalline silicon wafers

NASA Astrophysics Data System (ADS)

Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

2017-04-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

Degradation of bare and silanized silicon wafer surfaces by constituents of biological fluids.

PubMed

Dekeyser, C M; Buron, C C; Derclaye, S R; Jonas, A M; Marchand-Brynaert, J; Rouxhet, P G

2012-07-15

The 24 h stability of bare silicon wafers as such or silanized with CH(3)O-(CH(2)-CH(2)-O)(n)-C(3)H(6)-trichlorosilane (n=6-9) was investigated in water, NaCl, phosphate and carbonate solutions, and in phosphate buffered saline (PBS) at 37 °C (close to biological conditions regarding temperature, high ionic strength, and pH). The resulting surfaces were analyzed using ellipsometry, X-ray Reflectometry (XRR), X-ray Photoelectron Spectroscopy (XPS), and Atomic Force Microscopy (AFM). Incubation of the silanized wafers in phosphate solution and PBS provokes a detachment of the silane layer. This is due to a hydrolysis of Si-O bonds which is favored by the action of phosphate, also responsible for a corrosion of non-silanized wafers. The surface alteration (detachment of silane layer and corrosion of the non-silanized wafer) is also important with carbonate solution, due to a higher pH (8.3). The protection of the silicon oxide layer brought by silane against the action of the salts is noticeable for phosphate but not for carbonate. Copyright © 2012 Elsevier Inc. All rights reserved.

Summary of theoretical and experimental investigation of grating type, silicon photovoltaic cells. [using p-n junctions on light receiving surface of base crystal

NASA Technical Reports Server (NTRS)

Chen, L. Y.; Loferski, J. J.

1975-01-01

Theoretical and experimental aspects are summarized for single crystal, silicon photovoltaic devices made by forming a grating pattern of p/n junctions on the light receiving surface of the base crystal. Based on the general semiconductor equations, a mathematical description is presented for the photovoltaic properties of such grating-like structures in a two dimensional form. The resulting second order elliptical equation is solved by computer modeling to give solutions for various, reasonable, initial values of bulk resistivity, excess carrier concentration, and surface recombination velocity. The validity of the computer model is established by comparison with p/n devices produced by alloying an aluminum grating pattern into the surface of n-type silicon wafers. Current voltage characteristics and spectral response curves are presented for cells of this type constructed on wafers of different resistivities and orientations.

Crystallographic Orientation Identification in Multicrystalline Silicon Wafers Using NIR Transmission Intensity

NASA Astrophysics Data System (ADS)

Skenes, Kevin; Kumar, Arkadeep; Prasath, R. G. R.; Danyluk, Steven

2018-02-01

Near-infrared (NIR) polariscopy is a technique used for the non-destructive evaluation of the in-plane stresses in photovoltaic silicon wafers. Accurate evaluation of these stresses requires correct identification of the stress-optic coefficient, a material property which relates photoelastic parameters to physical stresses. The material stress-optic coefficient of silicon varies with crystallographic orientation. This variation poses a unique problem when measuring stresses in multicrystalline silicon (mc-Si) wafers. This paper concludes that the crystallographic orientation of silicon can be estimated by measuring the transmission of NIR light through the material. The transmission of NIR light through monocrystalline wafers of known orientation were compared with the transmission of NIR light through various grains in mc-Si wafers. X-ray diffraction was then used to verify the relationship by obtaining the crystallographic orientations of these assorted mc-Si grains. Variation of transmission intensity for different crystallographic orientations is further explained by using planar atomic density. The relationship between transmission intensity and planar atomic density appears to be linear.

Fabrication of uniform nanoscale cavities via silicon direct wafer bonding.

PubMed

Thomson, Stephen R D; Perron, Justin K; Kimball, Mark O; Mehta, Sarabjit; Gasparini, Francis M

2014-01-09

Measurements of the heat capacity and superfluid fraction of confined (4)He have been performed near the lambda transition using lithographically patterned and bonded silicon wafers. Unlike confinements in porous materials often used for these types of experiments(3), bonded wafers provide predesigned uniform spaces for confinement. The geometry of each cell is well known, which removes a large source of ambiguity in the interpretation of data. Exceptionally flat, 5 cm diameter, 375 µm thick Si wafers with about 1 µm variation over the entire wafer can be obtained commercially (from Semiconductor Processing Company, for example). Thermal oxide is grown on the wafers to define the confinement dimension in the z-direction. A pattern is then etched in the oxide using lithographic techniques so as to create a desired enclosure upon bonding. A hole is drilled in one of the wafers (the top) to allow for the introduction of the liquid to be measured. The wafers are cleaned(2) in RCA solutions and then put in a microclean chamber where they are rinsed with deionized water(4). The wafers are bonded at RT and then annealed at ~1,100 °C. This forms a strong and permanent bond. This process can be used to make uniform enclosures for measuring thermal and hydrodynamic properties of confined liquids from the nanometer to the micrometer scale.

Effect of PECVD SiNx/SiOyNx-Si interface property on surface passivation of silicon wafer

NASA Astrophysics Data System (ADS)

Jia, Xiao-Jie; Zhou, Chun-Lan; Zhu, Jun-Jie; Zhou, Su; Wang, Wen-Jing

2016-12-01

It is studied in this paper that the electrical characteristics of the interface between SiOyNx/SiNx stack and silicon wafer affect silicon surface passivation. The effects of precursor flow ratio and deposition temperature of the SiOyNx layer on interface parameters, such as interface state density Dit and fixed charge Qf, and the surface passivation quality of silicon are observed. Capacitance-voltage measurements reveal that inserting a thin SiOyNx layer between the SiNx and the silicon wafer can suppress Qf in the film and Dit at the interface. The positive Qf and Dit and a high surface recombination velocity in stacks are observed to increase with the introduced oxygen and minimal hydrogen in the SiOyNx film increasing. Prepared by deposition at a low temperature and a low ratio of N2O/SiH4 flow rate, the SiOyNx/SiNx stacks result in a low effective surface recombination velocity (Seff) of 6 cm/s on a p-type 1 Ω·cm-5 Ω·cm FZ silicon wafer. The positive relationship between Seff and Dit suggests that the saturation of the interface defect is the main passivation mechanism although the field-effect passivation provided by the fixed charges also make a contribution to it. Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA050302) and the National Natural Science Foundation of China (Grant No. 61306076).

Investigation on the structural characterization of pulsed p-type porous silicon

NASA Astrophysics Data System (ADS)

Wahab, N. H. Abd; Rahim, A. F. Abd; Mahmood, A.; Yusof, Y.

2017-08-01

P-type Porous silicon (PS) was sucessfully formed by using an electrochemical pulse etching (PC) and conventional direct current (DC) etching techniques. The PS was etched in the Hydrofluoric (HF) based solution at a current density of J = 10 mA/cm2 for 30 minutes from a crystalline silicon wafer with (100) orientation. For the PC process, the current was supplied through a pulse generator with 14 ms cycle time (T) with 10 ms on time (Ton) and pause time (Toff) of 4 ms respectively. FESEM, EDX, AFM, and XRD have been used to characterize the morphological properties of the PS. FESEM images showed that pulse PS (PPC) sample produces more uniform circular structures with estimated average pore sizes of 42.14 nm compared to DC porous (PDC) sample with estimated average size of 16.37nm respectively. The EDX spectrum for both samples showed higher Si content with minimal presence of oxide.

Automated Array Assembly Task In-depth Study of Silicon Wafer Surface Texturizing

NASA Technical Reports Server (NTRS)

Jones, G. T.; Chitre, S.; Rhee, S. S.; Allison, K. L.

1979-01-01

A low cost wafer surface texturizing process was studied. An investigation of low cost cleaning operations to clean residual wax and organics from the surface of silicon wafers was made. The feasibility of replacing dry nitrogen with clean dry air for drying silicon wafers was examined. The two stage texturizing process was studied for the purpose of characterizing relevant parameters in large volume applications. The effect of gettering solar cells on photovoltaic energy conversion efficiency is described.

Fabricating a Microcomputer on a Single Silicon Wafer

NASA Technical Reports Server (NTRS)

Evanchuk, V. L.

1983-01-01

Concept for "microcomputer on a slice" reduces microcomputer costs by eliminating scribing, wiring, and packaging of individual circuit chips. Low-cost microcomputer on silicon slice contains redundant components. All components-central processing unit, input/output circuitry, read-only memory, and random-access memory (CPU, I/O, ROM, and RAM) on placed on single silicon wafer.

Lamb wave propagation in monocrystalline silicon wafers.

PubMed

Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

2018-01-01

Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

High Efficiency, Low Cost Solar Cells Manufactured Using 'Silicon Ink' on Thin Crystalline Silicon Wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Antoniadis, H.

Reported are the development and demonstration of a 17% efficient 25mm x 25mm crystalline Silicon solar cell and a 16% efficient 125mm x 125mm crystalline Silicon solar cell, both produced by Ink-jet printing Silicon Ink on a thin crystalline Silicon wafer. To achieve these objectives, processing approaches were developed to print the Silicon Ink in a predetermined pattern to form a high efficiency selective emitter, remove the solvents in the Silicon Ink and fuse the deposited particle Silicon films. Additionally, standard solar cell manufacturing equipment with slightly modified processes were used to complete the fabrication of the Silicon Ink highmore » efficiency solar cells. Also reported are the development and demonstration of a 18.5% efficient 125mm x 125mm monocrystalline Silicon cell, and a 17% efficient 125mm x 125mm multicrystalline Silicon cell, by utilizing high throughput Ink-jet and screen printing technologies. To achieve these objectives, Innovalight developed new high throughput processing tools to print and fuse both p and n type particle Silicon Inks in a predetermined pat-tern applied either on the front or the back of the cell. Additionally, a customized Ink-jet and screen printing systems, coupled with customized substrate handling solution, customized printing algorithms, and a customized ink drying process, in combination with a purchased turn-key line, were used to complete the high efficiency solar cells. This development work delivered a process capable of high volume producing 18.5% efficient crystalline Silicon solar cells and enabled the Innovalight to commercialize its technology by the summer of 2010.« less

Emissivity properties of silicon wafers and their application to radiation thermometry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Iuchi, T.; Seo, T.

We studied the spectral and directional emissivities of silicon wafers using an optical polarization technique. Based on the simulation and experimental results, we developed two different radiation thermometry methods for silicon wafers, the first based on a polarized emissivity-invariant condition, and the second based on the relationship between the ratio of the p-to s-polarized radiance and the polarized emissivity. These methods can be performed at temperatures above 600 °C and over a wide wavelength range (0.9∼5 μm), irrespective of dielectric film thickness and substrate resistivity due to the dopant concentrations. Temperature measurements were estimated to have expanded uncertainties (k=2) ofmore » less than 5 °C. A radiometer system with wavelengths above 4.5 μm was successfully developed because the system was not influenced by background noise caused by a high-intensity heating lamp.« less

Electronic transport characterization of silicon wafers by spatially resolved steady-state photocarrier radiometric imaging

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Qian; University of the Chinese Academy of Sciences, Beijing 100039; Li, Bincheng, E-mail: bcli@ioe.ac.cn

2015-09-28

Spatially resolved steady-state photocarrier radiometric (PCR) imaging technique is developed to characterize the electronic transport properties of silicon wafers. Based on a nonlinear PCR theory, simulations are performed to investigate the effects of electronic transport parameters (the carrier lifetime, the carrier diffusion coefficient, and the front surface recombination velocity) on the steady-state PCR intensity profiles. The electronic transport parameters of an n-type silicon wafer are simultaneously determined by fitting the measured steady-state PCR intensity profiles to the three-dimensional nonlinear PCR model. The determined transport parameters are in good agreement with the results obtained by the conventional modulated PCR technique withmore » multiple pump beam radii.« less

Silicon wafer temperature monitoring using all-fiber laser ultrasonics

NASA Astrophysics Data System (ADS)

Alcoz, Jorge J.; Duffer, Charles E.

1998-03-01

Laser-ultrasonics is a very attractive technique for in-line process control in the semiconductor industry as it is compatible with the clean room environment and offers the capability to inspect parts at high-temperature. We describe measurements of the velocity of laser-generated Lamb waves in silicon wafers as a function of temperature using fiber- optic laser delivery and all-fiber interferometric sensing. Fundamental anti-symmetric Lamb-wave modes were generated in 5 inches < 111 > silicon wafers using a Nd:YAG laser coupled to a large-core multimode fiber. Generation was also performed using an array of sources created with a diffraction grating. For detection a compact fiber-optic sensor was used which is well suited for industrial environments as it is compact, rugged, stable, and low-cost. The wafers were heated up to 1000 degrees C and the temperature correlated with ultrasonic velocity measurements.

Chemical method for producing smooth surfaces on silicon wafers

DOEpatents

Yu, Conrad

2003-01-01

An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

Cohesive zone model for direct silicon wafer bonding

NASA Astrophysics Data System (ADS)

Kubair, D. V.; Spearing, S. M.

2007-05-01

Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

Intrinsic Gettering in Nitrogen-Doped and Hydrogen-Annealed Czochralski-Grown Silicon Wafers

NASA Astrophysics Data System (ADS)

Goto, Hiroyuki; Pan, Lian-Sheng; Tanaka, Masafumi; Kashima, Kazuhiko

2001-06-01

The properties of nitrogen-doped and hydrogen-annealed Czochralski-grown silicon (NHA-CZ-Si) wafers were investigated in this study. The quality of the subsurface was investigated by monitoring the generation lifetime of minority carriers, as measured by the capacitance-time measurements of a metal oxide silicon capacitor (MOS C-t). The intrinsic gettering (IG) ability was investigated by determining the nickel concentration on the surface and in the subsurface as measured by graphite furnace atomic absorption spectrometry (GFAAS) after the wafer was deliberately contaminated with nickel. From the results obtained, the generation lifetimes of these NHA-CZ-Si wafers were determined to be almost the same as, or a little longer than those of epitaxial wafers, and the IG ability was proportional to the total volume of oxygen precipitates [i.e., bulk micro defects (BMDs)], which was influenced by the oxygen and nitrogen concentrations in the wafers. Therefore, it is suggested that the subsurface of the NHA-CZ-Si wafers is of good quality and the IG capacity is controllable by the nitrogen and oxygen concentrations in the wafers.

The Influence of the Surface Neutralization of Active Impurities on the Field-Electron Emission Properties of p-Type Silicon Crystals

NASA Astrophysics Data System (ADS)

Yafarov, R. K.

2017-12-01

Correlation dependences between variations of the structural-phase composition, morphology characteristics, and field-electron-emission (FEE) properties of surface-structured p-type silicon singlecrystalline (100)-oriented wafers have been studied during their stepwise high-dose carbon-ion-beam irradiation. It is established that the stepwise implantation of carbon decreases the FEE threshold and favors an increase in the maximum FEE-current density by more than two orders of magnitude. Physicochemical mechanisms involved in this modification of the properties of near-surface layers of silicon under carbon-ion implantation are considered.

Fabrication Characterization of Solar-Cell Silicon Wafers Using a Circular-Rhombus Tool

NASA Astrophysics Data System (ADS)

Pa, Pai-Shan

2010-01-01

A new recycling fabrication method using a custom-built designed circular-rhombus tool for a process combining of micro-electroetching and electrochemical machining for removal of the surface layers from silicon wafers of solar cells is demonstrated. The low yields of epoxy film and Si3N4 thin-film depositions are important factors in semiconductor production. The aim of the proposed recycling fabrication method is to replace the current approach, which uses strong acid and grinding and may damage the physical structure of silicon wafers and pollute to the environment. A precisely engineered clean production approach for removal of surface microstructure layers from silicon wafers is to develop a mass production system for recycling defective or discarded silicon wafers of solar cells that can reduce pollution and cost. A large diameter cathode of the circular-rhombus tool (with a small gap between the anode and the cathode) corresponds to a high rate of epoxy film removal. A high feed rate of the silicon wafers combined with a high continuous DC electric voltage results in a high removal rate. The high rotational speed of the circular-rhombus tool increases the discharge mobility and improves the removal effect associated with the high feed rate of the workpiece. A small port radius or large end angle of the rhombus anode provides a large discharge space and good removal effect only a short period of time is required to remove the Si3N4 layer and epoxy film easily and cleanly.

Thermo-acousto-photonics for noncontact temperature measurement in silicon wafer processing

NASA Astrophysics Data System (ADS)

Suh, Chii-Der S.; Rabroker, G. Andrew; Chona, Ravinder; Burger, Christian P.

1999-10-01

A non-contact thermometry technique has been developed to characterize the thermal state of silicon wafers during rapid thermal processing. Information on thermal variations is obtained from the dispersion relations of the propagating waveguide mode excited in wafers using a non-contact, broadband optical system referred to as Thermal Acousto- Photonics for Non-Destructive Evaluation. Variations of thermo-mechanical properties in silicon wafers are correlated to temperature changes by performing simultaneous time-frequency analyses on Lamb waveforms acquired with a fiber-tip interferometer sensor. Experimental Lamb wave data collected for cases ranging from room temperature to 400 degrees C is presented. The results show that the temporal progressions of all spectral elements found in the fundamental antisymmetric mode are strong functions of temperature. This particular attribute is exploited to achieve a thermal resolution superior to the +/- 5 degrees C attainable through current pyrometric techniques. By analyzing the temperature-dependent group velocity of a specific frequency component over the temperature range considered and then comparing the results to an analytical model developed for silicon wafers undergoing annealing, excellent agreement was obtained. Presented results demonstrate the feasibility of applying laser-induced stress waves as a temperature diagnostic during rapid thermal processing.

Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

NASA Astrophysics Data System (ADS)

Kulshreshtha, Prashant Kumar

the surface/edge micro-cracks (i.e. sources of crack initiation). The low load (<10mN) nanoindentations using Hysitron Triboindenter RTM have been applied to estimate the zone of crack-propagation related plastic deformation and amorphization around the radial or the lateral cracks. The gradual reduction in hardness due to local stress field and phase change around the crack has been established using electron back scattered diffraction (EBSD), atomic force microscopy (AFM) and Raman spectroscopy, respectively, at nano- and micro-scale. The load (P) vs. displacement (h) curves depict characteristic phase transformation events (eg. elbow or pop-out) depending on the sign of residual stress in the silicon lattice. The formation of Si-XII/III phases (elastic phases) in large volumes during indentation of compressed Si lattice have been discussed as an option to eliminate the edge micro-cracks formed during wafer sawing by ductile flow. The stress gradient at an interface, which can be a grain-boundary (GB), twin or a interface between silicon and precipitate, has been evaluated for crack path modification. An direct-silicon-bonded (DSB) based ideal [110]/[100] interface has been examined to study the effect of crystallographic orientation variation across a planar silicon 2D boundary. Using constant source diffusion/annealing process, Fe and Cu impurities have been incorporated in model [110]/[100]GB to provide equivalence to a real decorated multi-crystalline grain boundary. We found that Fe precipitates harden the undecorated GB structure, whereas Cu precipitates introduce dislocation-induced plasticity to soften it. Aluminum Schottky diodes have been evaporated on the DSB samples to sensitively detect the instantaneous current response from the phase-transformed Si under nanoindenter tip. The impact of metallic impurity and their precipitates on characteristic phase transformations (i.e. pop-in or pop-out) demonstrate that scattered distribution of large Cu

Control wafer bow of InGaP on 200 mm Si by strain engineering

NASA Astrophysics Data System (ADS)

Wang, Bing; Bao, Shuyu; Made, Riko I.; Lee, Kwang Hong; Wang, Cong; Eng Kian Lee, Kenneth; Fitzgerald, Eugene A.; Michel, Jurgen

2017-12-01

When epitaxially growing III-V compound semiconductors on Si substrates the mismatch of coefficients of thermal expansion (CTEs) between III-V and Si causes stress and wafer bow. The wafer bow is deleterious for some wafer-scale processing especially when the wafer size is large. Strain engineering was applied in the epitaxy of InGaP films on 200 mm silicon wafers having high quality germanium buffers. By applying compressive strain in the InGaP films to compensate the tensile strain induced by CTE mismatch, wafer bow was decreased from about 100 μm to less than 50 μm. X-ray diffraction studies show a clear trend between the decrease of wafer bow and the compensation of CTE mismatch induced tensile strain in the InGaP layers. In addition, the anisotropic strain relaxation in InGaP films resulted in anisotropic wafer bow along two perpendicular (110) directions. Etch pit density and plane-view transmission electron microscopy characterizations indicate that threading dislocation densities did not change significantly due to the lattice-mismatch applied in the InGaP films. This study shows that strain engineering is an effective method to control wafer bow when growing III-V semiconductors on large size Si substrates.

Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

NASA Astrophysics Data System (ADS)

Miki, N.; Spearing, S. M.

2003-11-01

Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto

2006-12-10

To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 {mu}m wide (111) sidewalls was fabricated using a 220 {mu}m thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers.

PubMed

Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang, Zhen; Takano, Takayuki; Maeda, Ryutaro

2006-12-10

To develop x-ray mirrors for micropore optics, smooth silicon (111) sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 microm wide (111) sidewalls was fabricated using a 220 microm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time, x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements.

External self-gettering of nickel in float zone silicon wafers

NASA Astrophysics Data System (ADS)

Gay, N.; Martinuzzi, S.

1997-05-01

During indiffusion of Ni atoms in silicon crystals at 950 °C from a nickel layer source, Ni-Si alloys can be formed close to the surface. Metal solubility in these alloys is higher than in silicon, which induces a marked segregation gettering of the Ni atoms which have diffused in the bulk of the wafers. Consequently, the regions of the wafers covered with the Ni layer are less contaminated than adjacent regions in which Ni atoms have also penetrated, as shown by the absence of precipitates and the higher diffusion length of minority carriers. The results suggest the existence of external self-gettering of Ni atoms by the nickel source.

Recovery Act: Novel Kerf-Free PV Wafering that provides a low-cost approach to generate wafers from 150um to 50um in thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fong, Theodore E.

2013-05-06

The technical paper summarizes the project work conducted in the development of Kerf-Free silicon wafering equipment for silicon solar wafering. This new PolyMax technology uses a two step process of implantation and cleaving to exfoliate 50um to 120um wafers with thicknesses ranging from 50um to 120um from a 125mm or 156mm pseudo-squared silicon ingot. No kerf is generated using this method of wafering. This method of wafering contrasts with the current method of making silicon solar wafers using the industry standard wire saw equipment. The report summarizes the activity conducted by Silicon Genesis Corporation in working to develop this technologymore » further and to define the roadmap specifications for the first commercial proto-type equipment for high volume solar wafer manufacturing using the PolyMax technology.« less

Polarized Optical Scattering Measurements of Metallic Nanoparticles on a Thin Film Silicon Wafer

NASA Astrophysics Data System (ADS)

Liu, Cheng-Yang; Liu, Tze-An; Fu, Wei-En

2009-09-01

Light scattering has shown its powerful diagnostic capability to characterize optical quality surfaces. In this study, the theory of bidirectional reflectance distribution function (BRDF) was used to analyze the metallic nanoparticles' sizes on wafer surfaces. The BRDF of a surface is defined as the angular distribution of radiance scattered by the surface normalized by the irradiance incident on the surface. A goniometric optical scatter instrument has been developed to perform the BRDF measurements on polarized light scattering on wafer surfaces for the diameter and distribution measurements of metallic nanoparticles. The designed optical scatter instrument is capable of distinguishing various types of optical scattering characteristics, which are corresponding to the diameters of the metallic nanoparticles, near surfaces by using the Mueller matrix calculation. The metallic nanoparticle diameter of measurement is 60 nm on 2 inch thin film wafers. These measurement results demonstrate that the polarization of light scattered by metallic particles can be used to determine the size of metallic nanoparticles on silicon wafers.

Fabrication of Total-Dose-Radiation-Hardened (TDRH) SOI wafer with embedded silicon nanoclusters

NASA Astrophysics Data System (ADS)

Wu, Aimin; Wang, Xi; Wei, Xing; Chen, Jing; Chen, Ming; Zhang, Zhengxuan

2009-05-01

Si ion-implantation and post annealing of silicon wafers prior to wafer bonding were used to radiation-harden the thermal oxide layer of Silicon on Insulator structures. After grinding and polishing, Total-Dose-Radiation-Hardened SOI (TDRH-SOI) wafers with several-micron-thick device layers were prepared. Electrical characterization before and after X-ray irradiation showed that the flatband voltage shift induced by irradiation was reduced by this preprocessing. Photoluminescence Spectroscopy (PL), Transmission Electron Microscopy (TEM) and X-ray photoelectron spectroscopy (XPS) results indicated that the improvement of the total dose response of the TDRH-SOI wafer was associated with formation of Si nanoclusters in the implanted oxide layer, suggesting that these were the likely candidates for electron and proton trapping centers that reduce the positive charge buildup effect in the buried oxide.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

Characterization of silicon-on-insulator wafers

NASA Astrophysics Data System (ADS)

Park, Ki Hoon

The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

Porous Silicon Nanowires

PubMed Central

Qu, Yongquan; Zhou, Hailong; Duan, Xiangfeng

2011-01-01

In this minreview, we summarize recent progress in the synthesis, properties and applications of a new type of one-dimensional nanostructures — single crystalline porous silicon nanowires. The growth of porous silicon nanowires starting from both p- and n-type Si wafers with a variety of dopant concentrations can be achieved through either one-step or two-step reactions. The mechanistic studies indicate the dopant concentration of Si wafers, oxidizer concentration, etching time and temperature can affect the morphology of the as-etched silicon nanowires. The porous silicon nanowires are both optically and electronically active and have been explored for potential applications in diverse areas including photocatalysis, lithium ion battery, gas sensor and drug delivery. PMID:21869999

Silicon Alignment Pins: An Easy Way to Realize a Wafer-to-Wafer Alignment

NASA Technical Reports Server (NTRS)

Jung-Kubiak, Cecile; Reck, Theodore J.; Lin, Robert H.; Peralta, Alejandro; Gill, John J.; Lee, Choonsup; Siles, Jose; Toda, Risaku; Chattopadhyay, Goutam; Cooper, Ken B.;

Determination of thicknesses and temperatures of crystalline silicon wafers from optical measurements in the far infrared region

NASA Astrophysics Data System (ADS)

Franta, Daniel; Franta, Pavel; Vohánka, Jiří; Čermák, Martin; Ohlídal, Ivan

2018-05-01

Optical measurements of transmittance in the far infrared region performed on crystalline silicon wafers exhibit partially coherent interference effects appropriate for the determination of thicknesses of the wafers. The knowledge of accurate spectral and temperature dependencies of the optical constants of crystalline silicon in this spectral region is crucial for the determination of its thickness and vice versa. The recently published temperature dependent dispersion model of crystalline silicon is suitable for this purpose. Because the linear thermal expansion of crystalline silicon is known, the temperatures of the wafers can be determined with high precision from the evolution of the interference patterns at elevated temperatures.

Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

NASA Astrophysics Data System (ADS)

Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

2017-08-01

Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

Imaging Study of Multi-Crystalline Silicon Wafers Throughout the Manufacturing Process: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Zaunbracher, K.

2011-07-01

Imaging techniques are applied to multi-crystalline silicon bricks, wafers at various process steps, and finished solar cells. Photoluminescence (PL) imaging is used to characterize defects and material quality on bricks and wafers. Defect regions within the wafers are influenced by brick position within an ingot and height within the brick. The defect areas in as-cut wafers are compared to imaging results from reverse-bias electroluminescence and dark lock-in thermography and cell parameters of near-neighbor finished cells. Defect areas are also characterized by defect band emissions. The defect areas measured by these techniques on as-cut wafers are shown to correlate to finishedmore » cell performance.« less

Large-aperture focusing of x rays with micropore optics using dry etching of silicon wafers.

PubMed

Ezoe, Yuichiro; Moriyama, Teppei; Ogawa, Tomohiro; Kakiuchi, Takuya; Mitsuishi, Ikuyuki; Mitsuda, Kazuhisa; Aoki, Tatsuhiko; Morishita, Kohei; Nakajima, Kazuo

2012-03-01

Large-aperture focusing of Al K(α) 1.49 keV x-ray photons using micropore optics made from a dry-etched 4 in. (100 mm) silicon wafer is demonstrated. Sidewalls of the micropores are smoothed with high-temperature annealing to work as x-ray mirrors. The wafer is bent to a spherical shape to collect parallel x rays into a focus. Our result supports that this new type of optics allows for the manufacturing of ultralight-weight and high-performance x-ray imaging optics with large apertures at low cost. © 2012 Optical Society of America

Fabrication of a high aspect ratio thick silicon wafer mold and electroplating using flipchip bonding for MEMS applications

NASA Astrophysics Data System (ADS)

Kim, Bong-Hwan; Kim, Jong-Bok

2009-06-01

We have developed a microfabrication process for high aspect ratio thick silicon wafer molds and electroplating using flipchip bonding with THB 151N negative photoresist (JSR micro). This fabrication technique includes large area and high thickness silicon wafer mold electroplating. The process consists of silicon deep reactive ion etching (RIE) of the silicon wafer mold, photoresist bonding between the silicon mold and the substrate, nickel electroplating and a silicon removal process. High thickness silicon wafer molds were made by deep RIE and flipchip bonding. In addition, nickel electroplating was developed. Dry film resist (ORDYL MP112, TOK) and thick negative-tone photoresist (THB 151N, JSR micro) were used as bonding materials. In order to measure the bonding strength, the surface energy was calculated using a blade test. The surface energy of the bonding wafers was found to be 0.36-25.49 J m-2 at 60-180 °C for the dry film resist and 0.4-1.9 J m-2 for THB 151N in the same temperature range. Even though ORDYL MP112 has a better value of surface energy than THB 151N, it has a critical disadvantage when it comes to removing residue after electroplating. The proposed process can be applied to high aspect ratio MEMS structures, such as air gap inductors or vertical MEMS probe tips.

VLED for Si wafer-level packaging

NASA Astrophysics Data System (ADS)

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-03-01

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Aerosol-Assisted Extraction of Silicon Nanoparticles from Wafer Slicing Waste for Lithium Ion Batteries

NASA Astrophysics Data System (ADS)

Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

2015-03-01

A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

Aerosol-Assisted Extraction of Silicon Nanoparticles from Wafer Slicing Waste for Lithium Ion Batteries

PubMed Central

Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

2015-01-01

A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing. PMID:25819285

Application of neutron transmutation doping method to initially p-type silicon material.

PubMed

Kim, Myong-Seop; Kang, Ki-Doo; Park, Sang-Jun

2009-01-01

The neutron transmutation doping (NTD) method was applied to the initially p-type silicon in order to extend the NTD applications at HANARO. The relationship between the irradiation neutron fluence and the final resistivity of the initially p-type silicon material was investigated. The proportional constant between the neutron fluence and the resistivity was determined to be 2.3473x10(19)nOmegacm(-1). The deviation of the final resistivity from the target for almost all the irradiation results of the initially p-type silicon ingots was at a range from -5% to 2%. In addition, the burn-up effect of the boron impurities, the residual (32)P activity and the effect of the compensation characteristics for the initially p-type silicon were studied. Conclusively, the practical methodology to perform the neutron transmutation doping of the initially p-type silicon ingot was established.

Fabricating capacitive micromachined ultrasonic transducers with a novel silicon-nitride-based wafer bonding process.

PubMed

Logan, Andrew; Yeow, John T W

2009-05-01

We report the fabrication and experimental testing of 1-D 23-element capacitive micromachined ultrasonic transducer (CMUT) arrays that have been fabricated using a novel wafer-bonding process whereby the membrane and the insulation layer are both silicon nitride. The membrane and cell cavities are deposited and patterned on separate wafers and fusion-bonded in a vacuum environment to create CMUT cells. A user-grown silicon-nitride membrane layer avoids the need for expensive silicon-on-insulator (SOI) wafers, reduces parasitic capacitance, and reduces dielectric charging. It allows more freedom in selecting the membrane thickness while also providing the benefits of wafer-bonding fabrication such as excellent fill factor, ease of vacuum sealing, and a simplified fabrication process when compared with the more standard sacrificial release process. The devices fabricated have a cell diameter of 22 microm, a membrane thickness of 400 nm, a gap depth of 150 nm, and an insulation thickness of 250 nm. The resonant frequency of the CMUT in air is 17 MHz and has an attenuation compensated center frequency of approximately 9 MHz in immersion with a -6 dB fractional bandwidth of 123%. This paper presents the fabrication process and some characterization results.

RF performances of inductors integrated on localized p+-type porous silicon regions

PubMed Central

2012-01-01

To study the influence of localized porous silicon regions on radiofrequency performances of passive devices, inductors were integrated on localized porous silicon regions, full porous silicon sheet, bulk silicon and glass substrates. In this work, a novel strong, resistant fluoropolymer mask is introduced to localize the porous silicon on the silicon wafer. Then, the quality factors and resonant frequencies obtained with the different substrates are presented. A first comparison is done between the performances of inductors integrated on same-thickness localized and full porous silicon sheet layers. The effect of the silicon regions in the decrease of performances of localized porous silicon is discussed. Then, the study shows that the localized porous silicon substrate significantly reduces losses in comparison with high-resistivity silicon or highly doped silicon bulks. These results are promising for the integration of both passive and active devices on the same silicon/porous silicon hybrid substrate. PMID:23009746

Photo-EMF sensitivity of porous silicon thin layer-crystalline silicon heterojunction to ammonia adsorption.

PubMed

Vashpanov, Yuriy; Jung, Jae Il; Kwack, Kae Dal

2011-01-01

A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light.

Photo-EMF Sensitivity of Porous Silicon Thin Layer–Crystalline Silicon Heterojunction to Ammonia Adsorption

PubMed Central

Vashpanov, Yuriy; Jung, Jae Il; Kwack, Kae Dal

2011-01-01

A new method of using photo-electromotive force in detecting gas and controlling sensitivity is proposed. Photo-electromotive force on the heterojunction between porous silicon thin layer and crystalline silicon wafer depends on the concentration of ammonia in the measurement chamber. A porous silicon thin layer was formed by electrochemical etching on p-type silicon wafer. A gas and light transparent electrical contact was manufactured to this porous layer. Photo-EMF sensitivity corresponding to ammonia concentration in the range from 10 ppm to 1,000 ppm can be maximized by controlling the intensity of illumination light. PMID:22319353

P/N InP solar cells on Ge wafers

NASA Technical Reports Server (NTRS)

Wojtczuk, Steven; Vernon, Stanley; Burke, Edward A.

1994-01-01

Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented

Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

NASA Astrophysics Data System (ADS)

Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

2018-04-01

Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

Comparison of Photoluminescence Imaging on Starting Multi-Crystalline Silicon Wafers to Finished Cell Performance: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Johnston, S.; Yan, F.; Dorn, D.

2012-06-01

Photoluminescence (PL) imaging techniques can be applied to multicrystalline silicon wafers throughout the manufacturing process. Both band-to-band PL and defect-band emissions, which are longer-wavelength emissions from sub-bandgap transitions, are used to characterize wafer quality and defect content on starting multicrystalline silicon wafers and neighboring wafers processed at each step through completion of finished cells. Both PL imaging techniques spatially highlight defect regions that represent dislocations and defect clusters. The relative intensities of these imaged defect regions change with processing. Band-to-band PL on wafers in the later steps of processing shows good correlation to cell quality and performance. The defect bandmore » images show regions that change relative intensity through processing, and better correlation to cell efficiency and reverse-bias breakdown is more evident at the starting wafer stage as opposed to later process steps. We show that thermal processing in the 200 degrees - 400 degrees C range causes impurities to diffuse to different defect regions, changing their relative defect band emissions.« less

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE PAGES

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes; ...

2015-10-15

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high-efficiency solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hofstetter, Jasmin; del Cañizo, Carlos; Wagner, Hannes

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer-growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect-management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled tomore » effective control of fast-diffusing species during cell processing, is critical to enable high cell efficiencies. As a result, to accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection-dependent lifetime measurements.« less

Investigation of diffusion length distribution on polycrystalline silicon wafers via photoluminescence methods

PubMed Central

Lou, Shishu; Zhu, Huishi; Hu, Shaoxu; Zhao, Chunhua; Han, Peide

2015-01-01

Characterization of the diffusion length of solar cells in space has been widely studied using various methods, but few studies have focused on a fast, simple way to obtain the quantified diffusion length distribution on a silicon wafer. In this work, we present two different facile methods of doing this by fitting photoluminescence images taken in two different wavelength ranges or from different sides. These methods, which are based on measuring the ratio of two photoluminescence images, yield absolute values of the diffusion length and are less sensitive to the inhomogeneity of the incident laser beam. A theoretical simulation and experimental demonstration of this method are presented. The diffusion length distributions on a polycrystalline silicon wafer obtained by the two methods show good agreement. PMID:26364565

Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

NASA Astrophysics Data System (ADS)

Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

2018-03-01

A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

Development of AC-coupled, poly-silicon biased, p-on-n silicon strip detectors in India for HEP experiments

NASA Astrophysics Data System (ADS)

Jain, Geetika; Dalal, Ranjeet; Bhardwaj, Ashutosh; Ranjan, Kirti; Dierlamm, Alexander; Hartmann, Frank; Eber, Robert; Demarteau, Marcel

2018-02-01

P-on-n silicon strip sensors having multiple guard-ring structures have been developed for High Energy Physics applications. The study constitutes the optimization of the sensor design, and fabrication of AC-coupled, poly-silicon biased sensors of strip width of 30 μm and strip pitch of 55 μm. The silicon wafers used for the fabrication are of 4 inch n-type, having an average resistivity of 2-5 k Ω cm, with a thickness of 300 μm. The electrical characterization of these detectors comprises of: (a) global measurements of total leakage current, and backplane capacitance; (b) strip and voltage scans of strip leakage current, poly-silicon resistance, interstrip capacitance, interstrip resistance, coupling capacitance, and dielectric current; and (c) charge collection measurements using ALiBaVa setup. The results of the same are reported here.

Silicon surface passivation by polystyrenesulfonate thin films

NASA Astrophysics Data System (ADS)

Chen, Jianhui; Shen, Yanjiao; Guo, Jianxin; Chen, Bingbing; Fan, Jiandong; Li, Feng; Liu, Haixu; Xu, Ying; Mai, Yaohua

2017-02-01

The use of polystyrenesulfonate (PSS) thin films in a high-quality passivation scheme involving the suppression of minority carrier recombination at the silicon surface is presented. PSS has been used as a dispersant for aqueous poly-3,4-ethylenedioxythiophene. In this work, PSS is coated as a form of thin film on a Si surface. A millisecond level minority carrier lifetime on a high resistivity Si wafer is obtained. The film thickness, oxygen content, and relative humidity are found to be important factors affecting the passivation quality. While applied to low resistivity silicon wafers, which are widely used for photovoltaic cell fabrication, this scheme yields relatively shorter lifetime, for example, 2.40 ms on n-type and 2.05 ms on p-type wafers with a resistivity of 1-5 Ω.cm. However, these lifetimes are still high enough to obtain high implied open circuit voltages (Voc) of 708 mV and 697 mV for n-type and p-type wafers, respectively. The formation of oxides at the PSS/Si interface is suggested to be responsible for the passivation mechanism.

"Silicon millefeuille": From a silicon wafer to multiple thin crystalline films in a single step

NASA Astrophysics Data System (ADS)

Hernández, David; Trifonov, Trifon; Garín, Moisés; Alcubilla, Ramon

2013-04-01

During the last years, many techniques have been developed to obtain thin crystalline films from commercial silicon ingots. Large market applications are foreseen in the photovoltaic field, where important cost reductions are predicted, and also in advanced microelectronics technologies as three-dimensional integration, system on foil, or silicon interposers [Dross et al., Prog. Photovoltaics 20, 770-784 (2012); R. Brendel, Thin Film Crystalline Silicon Solar Cells (Wiley-VCH, Weinheim, Germany 2003); J. N. Burghartz, Ultra-Thin Chip Technology and Applications (Springer Science + Business Media, NY, USA, 2010)]. Existing methods produce "one at a time" silicon layers, once one thin film is obtained, the complete process is repeated to obtain the next layer. Here, we describe a technology that, from a single crystalline silicon wafer, produces a large number of crystalline films with controlled thickness in a single technological step.

Oxygen precipitation and bulk microdefects induced by the pre- and postepitaxial annealing in N/N + (100) silicon wafers

NASA Astrophysics Data System (ADS)

Wijaranakula, W.; Matlock, J. H.; Mollenkopf, H.

1987-12-01

Substrate wafers used for fabrication of epitaxial silicon wafers heavily doped with antimony at the concentration of 1020 atoms/cm3 were preannealed at a temperature between 500 and 900 °C prior to epitaxial deposition. Device fabrication thermal simulation was performed by heat treating the preannealed epitaxial wafers at 1050 °C in dry oxygen ambient for 16 h. Postepitaxial nucleation heat treatment at 750 °C for 4 h prior to the 1050 °C heat treament cycle was also applied on some epitaxial wafers for the purpose of enhancing the oxygen precipitation in silicon. It was observed that morphology and density of the bulk defects induced by the thermal treatment are affected by the preannealing temperature. The results also indicate that nucleation and growth kinetics of oxygen precipitates in preannealed n+ degenerate silicon substrate is strongly governed by oxygen and point defect diffusion.

Fabrication of spherical microlens array by combining lapping on silicon wafer and rapid surface molding

NASA Astrophysics Data System (ADS)

Liu, Xiaohua; Zhou, Tianfeng; Zhang, Lin; Zhou, Wenchen; Yu, Jianfeng; Lee, L. James; Yi, Allen Y.

2018-07-01

Silicon is a promising mold material for compression molding because of its properties of hardness and abrasion resistance. Silicon wafers with carbide-bonded graphene coating and micro-patterns were evaluated as molds for the fabrication of microlens arrays. This study presents an efficient but flexible manufacturing method for microlens arrays that combines a lapping method and a rapid molding procedure. Unlike conventional processes for microstructures on silicon wafers, such as diamond machining and photolithography, this research demonstrates a unique approach by employing precision steel balls and diamond slurries to create microlenses with accurate geometry. The feasibility of this method was demonstrated by the fabrication of several microlens arrays with different aperture sizes and pitches on silicon molds. The geometrical accuracy and surface roughness of the microlens arrays were measured using an optical profiler. The measurement results indicated good agreement with the optical profile of the design. The silicon molds were then used to copy the microstructures onto polymer substrates. The uniformity and quality of the samples molded through rapid surface molding were also assessed and statistically quantified. To further evaluate the optical functionality of the molded microlens arrays, the focal lengths of the microlens arrays were measured using a simple optical setup. The measurements showed that the microlens arrays molded in this research were compatible with conventional manufacturing methods. This research demonstrated an alternative low-cost and efficient method for microstructure fabrication on silicon wafers, together with the follow-up optical molding processes.

Brewster's angle silicon wafer terahertz linear polarizer.

PubMed

Wojdyla, Antoine; Gallot, Guilhem

2011-07-18

We present a new cost-effective terahertz linear polarizer made from a stack of silicon wafers at Brewster's angle, andevaluate its performances. We show that this polarizer is wide-band, has a high extinction ratio (> 6 × 10(3)) and very small insertion losses (< 1%). We provide measurements of the temporal waveforms after linearly polarizing the THz beam and show that there is no distortion of the pulse. We compare its performances with a commercial wire-grid polarizer, and show that the Brewster's angle polarizer can conveniently be used to control the power of a terahertz beam.

Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers

NASA Technical Reports Server (NTRS)

Anthony, Thomas R. (Inventor)

1983-01-01

Alignment-enhancing electrically conductive feed-through paths are provided for the high-speed low-loss transfer of electrical signals between integrated circuits of a plurality of silicon-on-sapphire bodies arrayed in a stack. The alignment-enhancing feed-throughs are made by a process involving the drilling of holes through the body, double-sided sputtering, electroplating, and the filling of the holes with solder by capillary action. The alignment-enhancing feed-throughs are activated by forming a stack of wafers and remelting the solder whereupon the wafers, and the feed-through paths, are pulled into alignment by surface tension forces.

Delta-Doping at Wafer Level for High Throughput, High Yield Fabrication of Silicon Imaging Arrays

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Nikzad, Shoulch (Inventor); Jones, Todd J. (Inventor); Greer, Frank (Inventor); Carver, Alexander G. (Inventor)

2014-01-01

Systems and methods for producing high quantum efficiency silicon devices. A silicon MBE has a preparation chamber that provides for cleaning silicon surfaces using an oxygen plasma to remove impurities and a gaseous (dry) NH3 + NF3 room temperature oxide removal process that leaves the silicon surface hydrogen terminated. Silicon wafers up to 8 inches in diameter have devices that can be fabricated using the cleaning procedures and MBE processing, including delta doping.

Contacting graphene in a 200 mm wafer silicon technology environment

NASA Astrophysics Data System (ADS)

Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

2018-06-01

Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

Texturization of diamond-wire-sawn multicrystalline silicon wafer using Cu, Ag, or Ag/Cu as a metal catalyst

NASA Astrophysics Data System (ADS)

Wang, Shing-Dar; Chen, Ting-Wei

2018-06-01

In this work, Cu, Ag, or Ag/Cu was used as a metal catalyst to study the surface texturization of diamond-wire-sawn (DWS) multi-crystalline silicon (mc-Si) wafer by a metal-assisted chemical etching (MACE) method. The DWS wafer was first etched by standard HF-HNO3 acidic etching, and it was labeled as AE-DWS wafer. The effects of ratios of Cu(NO3)2:HF, AgNO3:HF, and AgNO3:Cu(NO3)2 on the morphology of AE-DWS wafer were investigated. After the process of MACE, the wafer was treated with a NaF/H2O2 solution. In this process, H2O2 etched the nanostructure, and NaF removed the oxidation layer. The Si {1 1 1} plane was revealed by etching the wafer in a mixture of 0.03 M Cu(NO3)2 and 1 M HF at 55 °C for 2.5 min. These parallel Si {1 1 1} planes replaced some parallel saw marks on the surface of AE-DWS wafers without forming a positive pyramid or an inverted pyramid structure. The main topography of the wafer is comprised of silicon nanowires grown in <1 0 0> direction when Ag or Ag/Cu was used as a metal catalyst. When silicon is etched in a mixed solution of Cu(NO3)2, AgNO3, HF and H2O2 at 55 °C with a concentration ratio of [Cu2+]/[Ag+] of 50 or at 65 °C with a concentration ratio of [Cu2+]/[Ag+] of 33, a quasi-inverted pyramid structure can be obtained. The reflectivity of the AE-DWS wafers treated with MACE is lower than that of the multiwire-slurry-sawn (MWSS) mc-Si wafers treated with traditional HF + HNO3 etching.

Space optics with silicon wafers and slumped glass

NASA Astrophysics Data System (ADS)

Hudec, R.; Semencova, V.; Inneman, A.; Skulinova, M.; Sveda, L.; Míka, M.; Sik, J.; Lorenc, M.

2017-11-01

The future space X-ray astronomy imaging missions require very large collecting areas at still fine angular resolution and reasonable weight. The novel substrates for X-ray mirrors such as Silicon wafers and thin thermally formed glass enable wide applications of precise and very light weight (volume densities 2.3 to 2.5 gcm-3) optics. The recent status of novel technologies as well as developed test samples with emphasis on precise optical surfaces based on novel materials and their space applications is presented and discussed.

Characterization of deliberately nickel-doped silicon wafers and solar cells. [microstructure, electrical properties, and energy conversion efficiency

NASA Technical Reports Server (NTRS)

Salama, A. M.

1980-01-01

Microstructural and electrical evaluation tests were performed on nickel-doped p-type silicon wafers before and after solar cell fabrication. The concentration levels of nickel in silicon were 5 x 10 to the 14th power, 4 x 10 to the 15th power, and 8 x 10 to the 15th power atoms/cu cm. It was found that nickel precipitated out during the growth process in all three ingots. Clumps of precipitates, some of which exhibited star shape, were present at different depths. If the clumps are distributed at depths approximately 20 micron apart and if they are larger than 10 micron in diameter, degradation occurs in solar cell electrical properties and cell conversion efficiency. The larger the size of the precipitate clump, the greater the degradation in solar cell efficiency. A large grain boundary around the cell effective area acted as a gettering center for the precipitates and impurities and caused improvement in solar cell efficiency. Details of the evaluation test results are given.

New electron trap in p-type Czochralski silicon

NASA Technical Reports Server (NTRS)

Mao, B.-Y.; Lagowski, J.; Gatos, H. C.

1984-01-01

A new electron trap (acceptor level) was discovered in p-type Czochralski (CZ) silicon by current transient spectroscopy. The behavior of this trap was found to be similar to that of the oxygen thermal donors; thus, 450 C annealing increases the trap concentration while high-temperature annealing (1100-1200 C) leads to the virtual elimination of the trap. The new trap is not observed in either float-zone or n-type CZ silicon. Its energy level depends on the group III doping element in the sample. These findings suggest that the trap is related to oxygen, and probably to the acceptor impurity as well.

Switchable static friction of piezoelectric composite—silicon wafer contacts

NASA Astrophysics Data System (ADS)

van den Ende, D. A.; Fischer, H. R.; Groen, W. A.; van der Zwaag, S.

2013-04-01

The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and a silicon wafer counter surface rests solely on the matrix region of the piezocomposite surface. When actuated, the piezoelectric ceramic fibers protrude from the surface and the wafer rests solely on these protrusions. A threefold decrease in engineering static friction coefficient upon actuation of the piezocomposite was observed: from μ* = 1.65 to μ* = 0.50. These experimental results could be linked to the change in contact surface area and roughness using capillary adhesion theory, which relates the adhesive force to the number and size of the contacting asperities for the different surface states.

Uncertainty evaluation of thickness and warp of a silicon wafer measured by a spectrally resolved interferometer

NASA Astrophysics Data System (ADS)

Praba Drijarkara, Agustinus; Gergiso Gebrie, Tadesse; Lee, Jae Yong; Kang, Chu-Shik

2018-06-01

Evaluation of uncertainty of thickness and gravity-compensated warp of a silicon wafer measured by a spectrally resolved interferometer is presented. The evaluation is performed in a rigorous manner, by analysing the propagation of uncertainty from the input quantities through all the steps of measurement functions, in accordance with the ISO Guide to the Expression of Uncertainty in Measurement. In the evaluation, correlation between input quantities as well as uncertainty attributed to thermal effect, which were not included in earlier publications, are taken into account. The temperature dependence of the group refractive index of silicon was found to be nonlinear and varies widely within a wafer and also between different wafers. The uncertainty evaluation described here can be applied to other spectral interferometry applications based on similar principles.

Performance Evaluations of Ceramic Wafer Seals

NASA Technical Reports Server (NTRS)

Dunlap, Patrick H., Jr.; DeMange, Jeffrey J.; Steinetz, Bruce M.

2006-01-01

Future hypersonic vehicles will require high temperature, dynamic seals in advanced ramjet/scramjet engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Seal temperatures in these locations can exceed 2000 F, especially when the seals are in contact with hot ceramic matrix composite sealing surfaces. NASA Glenn Research Center is developing advanced ceramic wafer seals to meet the needs of these applications. High temperature scrub tests performed between silicon nitride wafers and carbon-silicon carbide rub surfaces revealed high friction forces and evidence of material transfer from the rub surfaces to the wafer seals. Stickage between adjacent wafers was also observed after testing. Several design changes to the wafer seals were evaluated as possible solutions to these concerns. Wafers with recessed sides were evaluated as a potential means of reducing friction between adjacent wafers. Alternative wafer materials are also being considered as a means of reducing friction between the seals and their sealing surfaces and because the baseline silicon nitride wafer material (AS800) is no longer commercially available.

An experimental investigation of silicon wafer surface roughness and its effect on the full strength of plated metals

NASA Technical Reports Server (NTRS)

Spiers, G. D.

1981-01-01

Plated silicon wafers with surface roughness ranging from 0.4 to 130 microinches were subjected to tensile pull strength tests. Electroless Ni/electroless Cu/electroplated Cu and electroless Ni/electroplated Cu were the two types of plate contacts tested. It was found that smoother surfaces had higher pull strength than rougher, chemically etched surfaces. The presence of the electroless Cu layer was found to be important to adhesion. The mode of fracture of the contact as it left the silicon was studied, and it was found that in almost all cases separation was due to fracture of the bulk silicon phase. The correlation between surface roughness and mode of contact failure is presented and interpreted.

Hybrid single quantum well InP/Si nanobeam lasers for silicon photonics.

PubMed

Fegadolli, William S; Kim, Se-Heon; Postigo, Pablo Aitor; Scherer, Axel

2013-11-15

We report on a hybrid InP/Si photonic crystal nanobeam laser emitting at 1578 nm with a low threshold power of ~14.7 μW. Laser gain is provided from a single InAsP quantum well embedded in a 155 nm InP layer bonded on a standard silicon-on-insulator wafer. This miniaturized nanolaser, with an extremely small modal volume of 0.375(λ/n)(3), is a promising and efficient light source for silicon photonics.

a Study of Oxygen Precipitation in Heavily Doped Silicon.

NASA Astrophysics Data System (ADS)

Graupner, Robert Kurt

processes. This could lead to more effective control and use of oxygen precipitation for gettering. One of the principal purposes of this thesis is the extension of the infrared interstitial oxygen measurement technique to situations outside the measurement capacities of the standard technique. These situations include silicon slices exhibiting interfering precipitate absorption bands and heavily doped n-type silicon wafers. A new method is presented for correcting for the effect of multiple reflections in silicon wafers with optically rough surfaces. The technique for the measurement of interstitial oxygen in heavily doped n-type wafers is then used to perform a comparative study of oxygen precipitation in heavily antimony doped (.035 ohm-cm) silicon and lightly doped p-type silicon. A model is presented to quantitatively explain the observed suppression of defect formation in heavily doped n-type wafers.

Coherent spin transport through a 350 micron thick silicon wafer.

PubMed

Huang, Biqin; Monsma, Douwe J; Appelbaum, Ian

2007-10-26

We use all-electrical methods to inject, transport, and detect spin-polarized electrons vertically through a 350-micron-thick undoped single-crystal silicon wafer. Spin precession measurements in a perpendicular magnetic field at different accelerating electric fields reveal high spin coherence with at least 13pi precession angles. The magnetic-field spacing of precession extrema are used to determine the injector-to-detector electron transit time. These transit time values are associated with output magnetocurrent changes (from in-plane spin-valve measurements), which are proportional to final spin polarization. Fitting the results to a simple exponential spin-decay model yields a conduction electron spin lifetime (T1) lower bound in silicon of over 500 ns at 60 K.

Flat-plate solar array project. Volume 3: Silicon sheet: Wafers and ribbons

NASA Technical Reports Server (NTRS)

Briglio, A.; Dumas, K.; Leipold, M.; Morrison, A.

1986-01-01

The primary objective of the Silicon Sheet Task of the Flat-Plate Solar Array (FSA) Project was the development of one or more low cost technologies for producing silicon sheet suitable for processing into cost-competitive solar cells. Silicon sheet refers to high purity crystalline silicon of size and thickness for fabrication into solar cells. Areas covered in the project were ingot growth and casting, wafering, ribbon growth, and other sheet technologies. The task made and fostered significant improvements in silicon sheet including processing of both ingot and ribbon technologies. An additional important outcome was the vastly improved understanding of the characteristics associated with high quality sheet, and the control of the parameters required for higher efficiency solar cells. Although significant sheet cost reductions were made, the technology advancements required to meet the task cost goals were not achieved.

Silicon Chemical Vapor Deposition Process Using a Half-Inch Silicon Wafer for Minimal Manufacturing System

NASA Astrophysics Data System (ADS)

Li, Ning; Habuka, Hitoshi; Ikeda, Shin-ichi; Hara, Shiro

A chemical vapor deposition reactor for producing thin silicon films was designed and developed for achieving a new electronic device production system, the Minimal Manufacturing, using a half-inch wafer. This system requires a rapid process by a small footprint reactor. This was designed and verified by employing the technical issues, such as (i) vertical gas flow, (ii) thermal operation using a highly concentrated infrared flux, and (iii) reactor cleaning by chlorine trifluoride gas. The combination of (i) and (ii) could achieve a low heating power and a fast cooling designed by the heat balance of the small wafer placed at a position outside of the reflector. The cleaning process could be rapid by (iii). The heating step could be skipped because chlorine trifluoride gas was reactive at any temperature higher than room temperature.

Determination of the implantation dose in silicon wafers by X-ray fluorescence analysis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Klockenkaemper, R.; Becker, M.; Bubert, H.

1990-08-01

The ion dose implanted in silicon wafers was determined by X-ray fluorescence analysis after the implantation process. As only near-surface layers below 1-{mu}m thickness were considered, the calibration could be carried out with external standards consisting of thin films of doped gelatine spread on pure wafers. Dose values for Cr and Co were determined between 4 {times} 10{sup 15} and 2 {times} 10{sup 17} atoms/cm{sup 2}, the detection limits being about 3 {times} 10{sup 14} atoms/cm{sup 2}. The results are precise and accurate apart from a residual scatter of less than 7%. This was confirmed by flame atomic absorption spectrometrymore » after volatilization of the silicon matrix as SiF{sub 4}. It was found that ion-current measurements carried out during the implantation process can have considerable systematic errors.« less

Studying post-etching silicon crystal defects on 300mm wafer by automatic defect review AFM

NASA Astrophysics Data System (ADS)

Zandiatashbar, Ardavan; Taylor, Patrick A.; Kim, Byong; Yoo, Young-kook; Lee, Keibock; Jo, Ahjin; Lee, Ju Suk; Cho, Sang-Joon; Park, Sang-il

2016-03-01

Single crystal silicon wafers are the fundamental elements of semiconductor manufacturing industry. The wafers produced by Czochralski (CZ) process are very high quality single crystalline materials with known defects that are formed during the crystal growth or modified by further processing. While defects can be unfavorable for yield for some manufactured electrical devices, a group of defects like oxide precipitates can have both positive and negative impacts on the final device. The spatial distribution of these defects may be found by scattering techniques. However, due to limitations of scattering (i.e. light wavelength), many crystal defects are either poorly classified or not detected. Therefore a high throughput and accurate characterization of their shape and dimension is essential for reviewing the defects and proper classification. While scanning electron microscopy (SEM) can provide high resolution twodimensional images, atomic force microscopy (AFM) is essential for obtaining three-dimensional information of the defects of interest (DOI) as it is known to provide the highest vertical resolution among all techniques [1]. However AFM's low throughput, limited tip life, and laborious efforts for locating the DOI have been the limitations of this technique for defect review for 300 mm wafers. To address these limitations of AFM, automatic defect review AFM has been introduced recently [2], and is utilized in this work for studying DOI on 300 mm silicon wafer. In this work, we carefully etched a 300 mm silicon wafer with a gaseous acid in a reducing atmosphere at a temperature and for a sufficient duration to decorate and grow the crystal defects to a size capable of being detected as light scattering defects [3]. The etched defects form a shallow structure and their distribution and relative size are inspected by laser light scattering (LLS). However, several groups of defects couldn't be properly sized by the LLS due to the very shallow depth and low

Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

NASA Astrophysics Data System (ADS)

Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

2014-03-01

Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

Study on chemical mechanical polishing of silicon wafer with megasonic vibration assisted.

PubMed

Zhai, Ke; He, Qing; Li, Liang; Ren, Yi

2017-09-01

Chemical mechanical polishing (CMP) is the primary method to realize the global planarization of silicon wafer. In order to improve this process, a novel method which combined megasonic vibration to assist chemical mechanical polishing (MA-CMP) is developed in this paper. A matching layer structure of polishing head was calculated and designed. Silicon wafers are polished by megasonic assisted chemical mechanical polishing and traditional chemical mechanical polishing respectively, both coarse polishing and precision polishing experiments were carried out. With the use of megasonic vibration, the surface roughness values Ra reduced from 22.260nm to 17.835nm in coarse polishing, and the material removal rate increased by approximately 15-25% for megasonic assisted chemical mechanical polishing relative to traditional chemical mechanical polishing. Average Surface roughness values Ra reduced from 0.509nm to 0.387nm in precision polishing. The results show that megasonic assisted chemical mechanical polishing is a feasible method to improve polishing efficiency and surface quality. The material removal and finishing mechanisms of megasonic vibration assisted polishing are investigated too. Copyright © 2017 Elsevier B.V. All rights reserved.

An all-silicon single-wafer micro-g accelerometer with a combined surface and bulk micromachining process

NASA Technical Reports Server (NTRS)

Yazdi, N.; Najafi, K.

2000-01-01

This paper reports an all-silicon fully symmetrical z-axis micro-g accelerometer that is fabricated on a single-silicon wafer using a combined surface and bulk fabrication process. The microaccelerometer has high device sensitivity, low noise, and low/controllable damping that are the key factors for attaining micro g and sub-micro g resolution in capacitive accelerometers. The microfabrication process produces a large proof mass by using the whole wafer thickness and a large sense capacitance by utilizing a thin sacrificial layer. The sense/feedback electrodes are formed by a deposited 2-3 microns polysilicon film with embedded 25-35 microns-thick vertical stiffeners. These electrodes, while thin, are made very stiff by the thick embedded stiffeners so that force rebalancing of the proof mass becomes possible. The polysilicon electrodes are patterned to create damping holes. The microaccelerometers are batch-fabricated, packaged, and tested successfully. A device with a 2-mm x 1-mm proof mass and a full bridge support has a measured sensitivity of 2 pF/g. The measured sensitivity of a 4-mm x 1-mm accelerometer with a cantilever support is 19.4 pF/g. The calculated noise floor of these devices at atmosphere are 0.23 micro g/sqrt(Hz) and 0.16 micro g/sqrt(Hz), respectively.

Comparison of cross-sectional transmission electron microscope studies of thin germanium epilayers grown on differently oriented silicon wafers.

PubMed

Norris, D J; Myronov, M; Leadley, D R; Walther, T

2017-12-01

We compare transmission electron microscopical analyses of the onset of islanding in the germanium-on-silicon (Ge/Si) system for three different Si substrate orientations: (001), (11¯0) and (11¯1)Si. The Ge was deposited by reduced pressure chemical vapour deposition and forms islands on the surface of all Si wafers; however, the morphology (aspect ratio) of the deposited islands is different for each type of wafer. Moreover, the mechanism for strain relaxation is different for each type of wafer owing to the different orientation of the (111) slip planes with the growth surface. Ge grown on (001)Si is initially pseudomorphically strained, yielding small, almost symmetrical islands of high aspect ratio (clusters or domes) on top interdiffused SiGe pedestals, without any evidence of plastic relaxation by dislocations, which would nucleate later-on when the islands might have coalesced and then the Matthews-Blakeslee limit is reached. For (11¯0)Si, islands are flatter and more asymmetric, and this is correlated with plastic relaxation of some islands by dislocations. In the case of growth on (11¯1)Si wafers, there is evidence of immediate strain relaxation taking place by numerous dislocations and also twinning. In the case of untwined film/substrate interfaces, Burgers circuits drawn around certain (amorphous-like) regions show a nonclosure with an edge-type a/4[1¯12] Burgers vector component visible in projection along [110]. Microtwins of multiples of half unit cells in thickness have been observed which occur at the growth interface between the Si(11¯1) buffer layer and the overlying Ge material. Models of the growth mechanisms to explain the interfacial configurations of each type of wafer are suggested. © 2017 The Authors Journal of Microscopy © 2017 Royal Microscopical Society.

Bulk lifetime characterization of corona charged silicon wafers with high resistivity by means of microwave detected photoconductivity

NASA Astrophysics Data System (ADS)

Engst, C. R.; Rommel, M.; Bscheid, C.; Eisele, I.; Kutter, C.

2017-12-01

Minority carrier lifetime (lifetime) measurements are performed on corona-charged silicon wafers by means of Microwave Detected Photoconductivity (MDP). The corona charge is deposited on the front and back sides of oxidized wafers in order to adjust accumulation conditions. Once accumulation is established, interface recombination is suppressed and bulk lifetimes are obtained. Neither contacts nor non-CMOS compatible preparation techniques are required in order to achieve accumulation conditions, which makes the method ideally suited for inline characterization. The novel approach, termed ChargedMDP (CMDP), is used to investigate neutron transmutation doped (NTD) float zone silicon with resistivities ranging from 6.0 to 8.2 kΩ cm. The bulk properties of 150 mm NTD wafers are analyzed in detail by performing measurements of the carrier lifetime and the steady-state photoconductivity at various injection levels. The results are compared with MDP measurements of uncharged wafers as well as to the established charged microwave detected Photoconductance Decay (charge-PCD) method. Besides analyzing whole wafers, CMDP measurements are performed on oxide test-structures on a patterned wafer. Finally, the oxide properties are characterized by means of charge-PCD as well as capacitance-voltage measurements. With CMDP, average bulk lifetimes up to 33.1 ms are measured, whereby significant variations are observed among wafers, which are produced out of the same ingot but oxidized in different furnaces. The observed lifetime variations are assumed to be caused by contaminations, which are introduced during the oxidation process. The results obtained by CMDP were neither accessible by means of conventional MDP measurements of uncharged wafers nor with the established charge-PCD method.

Control of grown-in defects and oxygen precipitates in silicon wafers with DZ-IG structure by ultrahigh-temperature rapid thermal oxidation

NASA Astrophysics Data System (ADS)

Maeda, Susumu; Sudo, Haruo; Okamura, Hideyuki; Nakamura, Kozo; Sueoka, Koji; Izunome, Koji

2018-04-01

A new control technique for achieving compatibility between crystal quality and gettering ability for heavy metal impurities was demonstrated for a nitrogen-doped Czochralski silicon wafer with a diameter of 300 mm via ultra-high temperature rapid thermal oxidation (UHT-RTO) processing. We have found that the DZ-IG structure with surface denuded zone and the wafer bulk with dense oxygen precipitates were formed by the control of vacancies in UHT-RTO process at temperature exceeding 1300 °C. It was also confirmed that most of the void defects were annihilated from the sub-surface of the wafer due to the interstitial Si atoms that were generated at the SiO2/Si interface. These results indicated that vacancies corresponded to dominant species, despite numerous interstitial silicon injections. We have explained these prominent features by the degree of super-saturation for the interstitial silicon due to oxidation and the precise thermal properties of the vacancy and interstitial silicon.

Nanostructured silicon ferromagnet collected by a permanent neodymium magnet.

PubMed

Okuno, Takahisa; Thürmer, Stephan; Kanoh, Hirofumi

2017-11-30

Nanostructured silicon (N-Si) was prepared by anodic electroetching of p-type silicon wafers. The obtained magnetic particles were separated by a permanent neodymium magnet as a magnetic nanostructured silicon (mN-Si). The N-Si and mN-Si exhibited different magnetic properties: the N-Si exhibited ferromagnetic-like behaviour, whereas the mN-Si exhibited superparamagnetic-like behaviour.

Automated and inexpensive method to manufacture solid- state nanopores and micropores in robust silicon wafers

NASA Astrophysics Data System (ADS)

Vega, M.; Granell, P.; Lasorsa, C.; Lerner, B.; Perez, M.

2016-02-01

In this work an easy, reproducible and inexpensive technique for the production of solid state nanopores and micropores using silicon wafer substrate is proposed. The technique is based on control of pore formation, by neutralization etchant (KOH) with a strong acid (HCl). Thus, a local neutralization is produced around the nanopore, which stops the silicon etching. The etching process was performed with 7M KOH at 80°C, where 1.23µm/min etching speed was obtained, similar to those published in literature. The control of the pore formation with the braking acid method was done using 12M HCl and different extreme conditions: i) at 25°C, ii) at 80°C and iii) at 80°C applying an electric potential. In these studies, it was found that nanopores and micropores can be obtained automatically and at a low cost. Additionally, the process was optimized to obtain clean silicon wafers after the pore fabrication process. This method opens the possibility for an efficient scale-up from laboratory production.

Enhancing the far-ultraviolet sensitivity of silicon complementary metal oxide semiconductor imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, Kurt D.; Bai, Yibin; Ryu, Kevin K.; Gregory, James A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winters, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2015-10-01

We report our progress toward optimizing backside-illuminated silicon P-type intrinsic N-type complementary metal oxide semiconductor devices developed by Teledyne Imaging Sensors (TIS) for far-ultraviolet (UV) planetary science applications. This project was motivated by initial measurements at Southwest Research Institute of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures, which revealed a promising QE in the 100 to 200 nm range. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include the following: (1) representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory; (2) preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; (3) detector fabrication was completed through the pre-MBE step; and (4) initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments.

Cu gettering by phosphorus-doped emitters in p-type silicon: Effect on light-induced degradation

NASA Astrophysics Data System (ADS)

Inglese, Alessandro; Laine, Hannu S.; Vähänissi, Ville; Savin, Hele

2018-01-01

The presence of copper (Cu) contamination is known to cause relevant light-induced degradation (Cu-LID) effects in p-type silicon. Due to its high diffusivity, Cu is generally regarded as a relatively benign impurity, which can be readily relocated during device fabrication from the wafer bulk, i.e. the region affected by Cu-LID, to the surface phosphorus-doped emitter. This contribution examines in detail the impact of gettering by industrially relevant phosphorus layers on the strength of Cu-LID effects. We find that phosphorus gettering does not always prevent the occurrence of Cu-LID. Specifically, air-cooling after an isothermal anneal at 800°C results in only weak impurity segregation to the phosphorus-doped layer, which turns out to be insufficient for effectively mitigating Cu-LID effects. Furthermore, we show that the gettering efficiency can be enhanced through the addition of a slow cooling ramp (-4°C/min) between 800°C and 600°C, resulting in the nearly complete disappearance of Cu-LID effects.

Dual ohmic contact to N- and P-type silicon carbide

NASA Technical Reports Server (NTRS)

Okojie, Robert S. (Inventor)

2013-01-01

Simultaneous formation of electrical ohmic contacts to silicon carbide (SiC) semiconductor having donor and acceptor impurities (n- and p-type doping, respectively) is disclosed. The innovation provides for ohmic contacts formed on SiC layers having n- and p-doping at one process step during the fabrication of the semiconductor device. Further, the innovation provides a non-discriminatory, universal ohmic contact to both n- and p-type SiC, enhancing reliability of the specific contact resistivity when operated at temperatures in excess of 600.degree. C.

A method for determining average damage depth of sawn crystalline silicon wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, B.; Devayajanam, S.; Basnyat, P.

2016-04-01

The depth of surface damage (or simply, damage) in crystalline silicon wafers, caused by wire sawing of ingots, is determined by performing a series of minority carrier lifetime (MCLT) measurements. Samples are sequentially etched to remove thin layers from each surface and MCLT is measured after each etch step. The thickness-removed (..delta..t) at which the lifetime reaches a peak value corresponds to the damage depth. This technique also allows the damage to be quantified in terms of effective surface recombination velocity (Seff). To accomplish this, the MCLT data are converted into an Seff vs ..delta..t plot, which represents a quantitativemore » distribution of the degree of damage within the surface layer. We describe a wafer preparation procedure to attain reproducible etching and MCLT measurement results. We also describe important characteristics of an etchant used for controllably removing thin layers from the wafer surfaces. Some typical results showing changes in the MCLT vs ..delta..t plots for different cutting parameters are given.« less

Iridium-coated micropore x-ray optics using dry etching of a silicon wafer and atomic layer deposition.

PubMed

Ogawa, Tomohiro; Ezoe, Yuichiro; Moriyama, Teppei; Mitsuishi, Ikuyuki; Kakiuchi, Takuya; Ohashi, Takaya; Mitsuda, Kazuhisa; Putkonen, Matti

2013-08-20

To enhance x-ray reflectivity of silicon micropore optics using dry etching of silicon (111) wafers, iridium coating is tested by use of atomic layer deposition. An iridium layer is successfully formed on sidewalls of tiny micropores with a pore width of 20 μm and depth of 300 μm. The film thickness is ∼20  nm. An enhanced x-ray reflectivity compared to that of silicon is confirmed at Ti K_α 4.51 keV, for what we believe to be the first time, with this type of optics. Some discrepancies from a theoretical reflectivity curve of iridium-coated silicon are noticed at small incident angles <1.3°. When a geometrical shadowing effect due to occultation by a ridge existing on the sidewalls is taken into account, the observed reflectivity becomes well represented by the modified theoretical curve. An estimated surface micro roughness of ∼1  nm rms is consistent with atomic force microscope measurements of the sidewalls.

Plasma-deposited fluoropolymer film mask for local porous silicon formation

PubMed Central

2012-01-01

The study of an innovative fluoropolymer masking layer for silicon anodization is proposed. Due to its high chemical resistance to hydrofluoric acid even under anodic bias, this thin film deposited by plasma has allowed the formation of deep porous silicon regions patterned on the silicon wafer. Unlike most of other masks, fluoropolymer removal after electrochemical etching is rapid and does not alter the porous layer. Local porous regions were thus fabricated both in p+-type and low-doped n-type silicon substrates. PMID:22734507

Support apparatus for semiconductor wafer processing

DOEpatents

Griffiths, Stewart K.; Nilson, Robert H.; Torres, Kenneth J.

2003-06-10

A support apparatus for minimizing gravitational stress in semiconductor wafers, and particularly silicon wafers, during thermal processing. The support apparatus comprises two concentric circular support structures disposed on a common support fixture. The two concentric circular support structures, located generally at between 10 and 70% and 70 and 100% and preferably at 35 and 82.3% of the semiconductor wafer radius, can be either solid rings or a plurality of spaced support points spaced apart from each other in a substantially uniform manner. Further, the support structures can have segments removed to facilitate wafer loading and unloading. In order to withstand the elevated temperatures encountered during semiconductor wafer processing, the support apparatus, including the concentric circular support structures and support fixture can be fabricated from refractory materials, such as silicon carbide, quartz and graphite. The claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.

Optimization of Controllable Factors in the Aluminum Silicon Eutectic Paste and Rear Silicon Nitride Mono-Passivation Layer of PERC Solar Cells

NASA Astrophysics Data System (ADS)

Park, Sungeun; Park, Hyomin; Kim, Dongseop; Yang, JungYup; Lee, Dongho; Kim, Young-Su; Kim, Hyun-Jong; Suh, Dongchul; Min, Byoung Koun; Kim, Kyung Nam; Park, Se Jin; Kim, Donghwan; Lee, Hae-Seok; Nam, Junggyu; Kang, Yoonmook

2018-05-01

Passivated emitter and rear contact (PERC) is a promising technology owing to high efficiency can be achieved with p-type wafer and their easily applicable to existing lines. In case of using p-type mono wafer, 0.5-1% efficiency increase is expected with PERC technologies compared to existing Al BSF solar cells, while for multi-wafer solar cells it is 0.5-0.8%. We addressed the optimization of PERC solar cells using the Al paste. The paste was prepared from the aluminum-silicon alloy with eutectic composition to avoid the formation of voids that degrade the open-circuit voltage. The glass frit of the paste was changed to improve adhesion. Scanning electron microscopy revealed voids and local back surface field between the aluminum electrode and silicon base. We confirmed the conditions on the SiNx passivation layer for achieving higher efficiency and better adhesion for long-term stability. The cell characteristics were compared across cells containing different pastes. PERC solar cells with the Al/Si eutectic paste exhibited the efficiency of 19.6%.

Accurate determination of electronic transport properties of silicon wafers by nonlinear photocarrier radiometry with multiple pump beam sizes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Qian; University of the Chinese Academy of Sciences, Beijing 100039; Li, Bincheng, E-mail: bcli@uestc.ac.cn

2015-12-07

In this paper, photocarrier radiometry (PCR) technique with multiple pump beam sizes is employed to determine simultaneously the electronic transport parameters (the carrier lifetime, the carrier diffusion coefficient, and the front surface recombination velocity) of silicon wafers. By employing the multiple pump beam sizes, the influence of instrumental frequency response on the multi-parameter estimation is totally eliminated. A nonlinear PCR model is developed to interpret the PCR signal. Theoretical simulations are performed to investigate the uncertainties of the estimated parameter values by investigating the dependence of a mean square variance on the corresponding transport parameters and compared to that obtainedmore » by the conventional frequency-scan method, in which only the frequency dependences of the PCR amplitude and phase are recorded at single pump beam size. Simulation results show that the proposed multiple-pump-beam-size method can improve significantly the accuracy of the determination of the electronic transport parameters. Comparative experiments with a p-type silicon wafer with resistivity 0.1–0.2 Ω·cm are performed, and the electronic transport properties are determined simultaneously. The estimated uncertainties of the carrier lifetime, diffusion coefficient, and front surface recombination velocity are approximately ±10.7%, ±8.6%, and ±35.4% by the proposed multiple-pump-beam-size method, which is much improved than ±15.9%, ±29.1%, and >±50% by the conventional frequency-scan method. The transport parameters determined by the proposed multiple-pump-beam-size PCR method are in good agreement with that obtained by a steady-state PCR imaging technique.« less

Depth profiles of oxygen precipitates in nitride-coated silicon wafers subjected to rapid thermal annealing

NASA Astrophysics Data System (ADS)

Voronkov, V. V.; Falster, R.; Kim, TaeHyeong; Park, SoonSung; Torack, T.

2013-07-01

Silicon wafers, coated with a silicon nitride layer and subjected to high temperature Rapid Thermal Annealing (RTA) in Ar, show—upon a subsequent two-step precipitation anneal cycle (such as 800 °C + 1000 °C)—peculiar depth profiles of oxygen precipitate densities. Some profiles are sharply peaked near the wafer surface, sometimes with a zero bulk density. Other profiles are uniform in depth. The maximum density is always the same. These profiles are well reproduced by simulations assuming that precipitation starts from a uniformly distributed small oxide plates originated from RTA step and composed of oxygen atoms and vacancies ("VO2 plates"). During the first step of the precipitation anneal, an oxide layer propagates around this core plate by a process of oxygen attachment, meaning that an oxygen-only ring-shaped plate emerges around the original plate. These rings, depending on their size, then either dissolve or grow during the second part of the anneal leading to a rich variety of density profiles.

Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

NASA Astrophysics Data System (ADS)

Sun, Q. M.; Melnikov, A.; Mandelis, A.

2015-06-01

Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

Large-size, high-uniformity, random silver nanowire networks as transparent electrodes for crystalline silicon wafer solar cells.

PubMed

Xie, Shouyi; Ouyang, Zi; Jia, Baohua; Gu, Min

2013-05-06

Metal nanowire networks are emerging as next generation transparent electrodes for photovoltaic devices. We demonstrate the application of random silver nanowire networks as the top electrode on crystalline silicon wafer solar cells. The dependence of transmittance and sheet resistance on the surface coverage is measured. Superior optical and electrical properties are observed due to the large-size, highly-uniform nature of these networks. When applying the nanowire networks on the solar cells with an optimized two-step annealing process, we achieved as large as 19% enhancement on the energy conversion efficiency. The detailed analysis reveals that the enhancement is mainly caused by the improved electrical properties of the solar cells due to the silver nanowire networks. Our result reveals that this technology is a promising alternative transparent electrode technology for crystalline silicon wafer solar cells.

Determination of the p-spray profile for n+ p silicon sensors using a MOSFET

NASA Astrophysics Data System (ADS)

Fretwurst, E.; Garutti, E.; Klanner, R.; Kopsalis, I.; Schwandt, J.; Weberpals, M.

2017-09-01

The standard technique to electrically isolate the n+ implants of segmented silicon sensors fabricated on high-ohmic p-type silicon are p+-implants. Although the knowledge of the p+-implant dose and of the doping profile is highly relevant for the understanding and optimisation of sensors, this information is usually not available from the vendors, and methods to obtain it are highly welcome. The paper presents methods to obtain this information from circular MOSFETs fabricated as test structures on the same wafer as the sensors. Two circular MOSFETs, one with and one without a p+-implant under the gate, are used for this study. They were produced on Magnetic Czochralski silicon doped with ≈ 3 . 5 × 1012cm-2 of boron and 〈 100 〉 crystal orientation. The drain-source current as function of gate voltage for different back-side voltages is measured at a drain-source voltage of 50 mV in the linear MOSFET region, and the values of threshold voltage and mobility extracted using the standard MOSFET formulae. To determine the bulk doping, the implantation dose and profile from the data, two methods are used, which give compatible results. The doping profile, which varies between 3 . 5 × 1012cm-3 and 2 × 1015cm-3 for the MOSFET with p+-implant, is determined down to a distance of a fraction of a μm from the Si-SiO2 interface. The method of extracting the doping profiles is verified using data from a TCAD simulation of the two MOSFETs. The details of the methods and of the problems encountered are discussed.

Predictable quantum efficient detector based on n-type silicon photodiodes

NASA Astrophysics Data System (ADS)

Dönsberg, Timo; Manoocheri, Farshid; Sildoja, Meelis; Juntunen, Mikko; Savin, Hele; Tuovinen, Esa; Ronkainen, Hannu; Prunnila, Mika; Merimaa, Mikko; Tang, Chi Kwong; Gran, Jarle; Müller, Ingmar; Werner, Lutz; Rougié, Bernard; Pons, Alicia; Smîd, Marek; Gál, Péter; Lolli, Lapo; Brida, Giorgio; Rastello, Maria Luisa; Ikonen, Erkki

2017-12-01

PQEDs is no longer dependent on the availability of a certain type of very lightly doped p-type silicon wafers.

Effect of Anisotropy on Shape Measurement Accuracy of Silicon Wafer Using Three-Point-Support Inverting Method

NASA Astrophysics Data System (ADS)

Ito, Yukihiro; Natsu, Wataru; Kunieda, Masanori

This paper describes the influences of anisotropy found in the elastic modulus of monocrystalline silicon wafers on the measurement accuracy of the three-point-support inverting method which can measure the warp and thickness of thin large panels simultaneously. Deflection due to gravity depends on the crystal orientation relative to the positions of the three-point-supports. Thus the deviation of actual crystal orientation from the direction indicated by the notch fabricated on the wafer causes measurement errors. Numerical analysis of the deflection confirmed that the uncertainty of thickness measurement increases from 0.168µm to 0.524µm due to this measurement error. In addition, experimental results showed that the rotation of crystal orientation relative to the three-point-supports is effective for preventing wafer vibration excited by disturbance vibration because the resonance frequency of wafers can be changed. Thus, surface shape measurement accuracy was improved by preventing resonant vibration during measurement.

Highly organised and dense vertical silicon nanowire arrays grown in porous alumina template on <100> silicon wafers

PubMed Central

2013-01-01

In this work, nanoimprint lithography combined with standard anodization etching is used to make perfectly organised triangular arrays of vertical cylindrical alumina nanopores onto standard <100>−oriented silicon wafers. Both the pore diameter and the period of alumina porous array are well controlled and can be tuned: the periods vary from 80 to 460 nm, and the diameters vary from 15 nm to any required diameter. These porous thin layers are then successfully used as templates for the guided epitaxial growth of organised mono-crystalline silicon nanowire arrays in a chemical vapour deposition chamber. We report the densities of silicon nanowires up to 9 × 109 cm−2 organised in highly regular arrays with excellent diameter distribution. All process steps are demonstrated on surfaces up to 2 × 2 cm2. Specific emphasis was made to select techniques compatible with microelectronic fabrication standards, adaptable to large surface samples and with a reasonable cost. Achievements made in the quality of the porous alumina array, therefore on the silicon nanowire array, widen the number of potential applications for this technology, such as optical detectors or biological sensors. PMID:23773702

P-Type Silicon Strip Sensors for the new CMS Tracker at HL-LHC

NASA Astrophysics Data System (ADS)

Adam, W.; Bergauer, T.; Brondolin, E.; Dragicevic, M.; Friedl, M.; Frühwirth, R.; Hoch, M.; Hrubec, J.; König, A.; Steininger, H.; Waltenberger, W.; Alderweireldt, S.; Beaumont, W.; Janssen, X.; Lauwers, J.; Van Mechelen, P.; Van Remortel, N.; Van Spilbeeck, A.; Beghin, D.; Brun, H.; Clerbaux, B.; Delannoy, H.; De Lentdecker, G.; Fasanella, G.; Favart, L.; Goldouzian, R.; Grebenyuk, A.; Karapostoli, G.; Lenzi, Th.; Léonard, A.; Luetic, J.; Postiau, N.; Seva, T.; Vanlaer, P.; Vannerom, D.; Wang, Q.; Zhang, F.; Abu Zeid, S.; Blekman, F.; De Bruyn, I.; De Clercq, J.; D'Hondt, J.; Deroover, K.; Lowette, S.; Moortgat, S.; Moreels, L.; Python, Q.; Skovpen, K.; Van Mulders, P.; Van Parijs, I.; Bakhshiansohi, H.; Bondu, O.; Brochet, S.; Bruno, G.; Caudron, A.; Delaere, C.; Delcourt, M.; De Visscher, S.; Francois, B.; Giammanco, A.; Jafari, A.; Komm, M.; Krintiras, G.; Lemaitre, V.; Magitteri, A.; Mertens, A.; Michotte, D.; Musich, M.; Piotrzkowski, K.; Quertenmont, L.; Szilasi, N.; Vidal Marono, M.; Wertz, S.; Beliy, N.; Caebergs, T.; Daubie, E.; Hammad, G. H.; Härkönen, J.; Lampén, T.; Luukka, P.; Peltola, T.; Tuominen, E.; Tuovinen, E.; Eerola, P.; Tuuva, T.; Baulieu, G.; Boudoul, G.; Caponetto, L.; Combaret, C.; Contardo, D.; Dupasquier, T.; Gallbit, G.; Lumb, N.; Mirabito, L.; Perries, S.; Vander Donckt, M.; Viret, S.; Agram, J.-L.; Andrea, J.; Bloch, D.; Bonnin, C.; Brom, J.-M.; Chabert, E.; Chanon, N.; Charles, L.; Conte, E.; Fontaine, J.-Ch.; Gross, L.; Hosselet, J.; Jansova, M.; Tromson, D.; Autermann, C.; Feld, L.; Karpinski, W.; Kiesel, K. M.; Klein, K.; Lipinski, M.; Ostapchuk, A.; Pierschel, G.; Preuten, M.; Rauch, M.; Schael, S.; Schomakers, C.; Schulz, J.; Schwering, G.; Wlochal, M.; Zhukov, V.; Pistone, C.; Fluegge, G.; Kuensken, A.; Pooth, O.; Stahl, A.; Aldaya, M.; Asawatangtrakuldee, C.; Beernaert, K.; Bertsche, D.; Contreras-Campana, C.; Eckerlin, G.; Eckstein, D.; Eichhorn, T.; Gallo, E.; Garay Garcia, J.; Hansen, K.; Haranko, M.; Harb, A.; Hauk, J.; Keaveney, J.; Kalogeropoulos, A.; Kleinwort, C.; Lohmann, W.; Mankel, R.; Maser, H.; Mittag, G.; Muhl, C.; Mussgiller, A.; Pitzl, D.; Reichelt, O.; Savitskyi, M.; Schuetze, P.; Walsh, R.; Zuber, A.; Biskop, H.; Buhmann, P.; Centis-Vignali, M.; Garutti, E.; Haller, J.; Hoffmann, M.; Lapsien, T.; Matysek, M.; Perieanu, A.; Scharf, Ch.; Schleper, P.; Schmidt, A.; Schwandt, J.; Sonneveld, J.; Steinbrück, G.; Vormwald, B.; Wellhausen, J.; Abbas, M.; Amstutz, C.; Barvich, T.; Barth, Ch.; Boegelspacher, F.; De Boer, W.; Butz, E.; Caselle, M.; Colombo, F.; Dierlamm, A.; Freund, B.; Hartmann, F.; Heindl, S.; Husemann, U.; Kornmayer, A.; Kudella, S.; Muller, Th.; Simonis, H. J.; Steck, P.; Weber, M.; Weiler, Th.; Anagnostou, G.; Asenov, P.; Assiouras, P.; Daskalakis, G.; Kyriakis, A.; Loukas, D.; Paspalaki, L.; Siklér, F.; Veszprémi, V.; Bhardwaj, A.; Dalal, R.; Jain, G.; Ranjan, K.; Bakhshiansohl, H.; Behnamian, H.; Khakzad, M.; Naseri, M.; Cariola, P.; Creanza, D.; De Palma, M.; De Robertis, G.; Fiore, L.; Franco, M.; Loddo, F.; Silvestris, L.; Maggi, G.; Martiradonna, S.; My, S.; Selvaggi, G.; Albergo, S.; Cappello, G.; Chiorboli, M.; Costa, S.; Di Mattia, A.; Giordano, F.; Potenza, R.; Saizu, M. A.; Tricomi, A.; Tuve, C.; Barbagli, G.; Brianzi, M.; Ciaranfi, R.; Ciulli, V.; Civinini, C.; D'Alessandro, R.; Focardi, E.; Latino, G.; Lenzi, P.; Meschini, M.; Paoletti, S.; Russo, L.; Scarlini, E.; Sguazzoni, G.; Strom, D.; Viliani, L.; Ferro, F.; Lo Vetere, M.; Robutti, E.; Dinardo, M. E.; Fiorendi, S.; Gennai, S.; Malvezzi, S.; Manzoni, R. A.; Menasce, D.; Moroni, L.; Pedrini, D.; Azzi, P.; Bacchetta, N.; Bisello, D.; Dall'Osso, M.; Pozzobon, N.; Tosi, M.; De Canio, F.; Gaioni, L.; Manghisoni, M.; Nodari, B.; Riceputi, E.; Re, V.; Traversi, G.; Comotti, D.; Ratti, L.; Alunni Solestizi, L.; Biasini, M.; Bilei, G. M.; Cecchi, C.; Checcucci, B.; Ciangottini, D.; Fanò, L.; Gentsos, C.; Ionica, M.; Leonardi, R.; Manoni, E.; Mantovani, G.; Marconi, S.; Mariani, V.; Menichelli, M.; Modak, A.; Morozzi, A.; Moscatelli, F.; Passeri, D.; Placidi, P.; Postolache, V.; Rossi, A.; Saha, A.; Santocchia, A.; Storchi, L.; Spiga, D.; Androsov, K.; Azzurri, P.; Arezzini, S.; Bagliesi, G.; Basti, A.; Boccali, T.; Borrello, L.; Bosi, F.; Castaldi, R.; Ciampa, A.; Ciocci, M. A.; Dell'Orso, R.; Donato, S.; Fedi, G.; Giassi, A.; Grippo, M. T.; Ligabue, F.; Lomtadze, T.; Magazzu, G.; Martini, L.; Mazzoni, E.; Messineo, A.; Moggi, A.; Morsani, F.; Palla, F.; Palmonari, F.; Raffaelli, F.; Rizzi, A.; Savoy-Navarro, A.; Spagnolo, P.; Tenchini, R.; Tonelli, G.; Venturi, A.; Verdini, P. G.; Bellan, R.; Costa, M.; Covarelli, R.; Da Rocha Rolo, M.; Demaria, N.; Rivetti, A.; Dellacasa, G.; Mazza, G.; Migliore, E.; Monteil, E.; Pacher, L.; Ravera, F.; Solano, A.; Fernandez, M.; Gomez, G.; Jaramillo Echeverria, R.; Moya, D.; Gonzalez Sanchez, F. J.; Vila, I.; Virto, A. L.; Abbaneo, D.; Ahmed, I.; Albert, E.; Auzinger, G.; Berruti, G.; Bianchi, G.; Blanchot, G.; Bonnaud, J.; Caratelli, A.; Ceresa, D.; Christiansen, J.; Cichy, K.; Daguin, J.; D'Auria, A.; Detraz, S.; Deyrail, D.; Dondelewski, O.; Faccio, F.; Frank, N.; Gadek, T.; Gill, K.; Honma, A.; Hugo, G.; Jara Casas, L. M.; Kaplon, J.; Kornmayer, A.; Kottelat, L.; Kovacs, M.; Krammer, M.; Lenoir, P.; Mannelli, M.; Marchioro, A.; Marconi, S.; Mersi, S.; Martina, S.; Michelis, S.; Moll, M.; Onnela, A.; Orfanelli, S.; Pavis, S.; Peisert, A.; Pernot, J.-F.; Petagna, P.; Petrucciani, G.; Postema, H.; Rose, P.; Tropea, P.; Troska, J.; Tsirou, A.; Vasey, F.; Vichoudis, P.; Verlaat, B.; Zwalinski, L.; Bachmair, F.; Becker, R.; di Calafiori, D.; Casal, B.; Berger, P.; Djambazov, L.; Donega, M.; Grab, C.; Hits, D.; Hoss, J.; Kasieczka, G.; Lustermann, W.; Mangano, B.; Marionneau, M.; Martinez Ruiz del Arbol, P.; Masciovecchio, M.; Meinhard, M.; Perozzi, L.; Roeser, U.; Starodumov, A.; Tavolaro, V.; Wallny, R.; Zhu, D.; Amsler, C.; Bösiger, K.; Caminada, L.; Canelli, F.; Chiochia, V.; de Cosa, A.; Galloni, C.; Hreus, T.; Kilminster, B.; Lange, C.; Maier, R.; Ngadiuba, J.; Pinna, D.; Robmann, P.; Taroni, S.; Yang, Y.; Bertl, W.; Deiters, K.; Erdmann, W.; Horisberger, R.; Kaestli, H.-C.; Kotlinski, D.; Langenegger, U.; Meier, B.; Rohe, T.; Streuli, S.; Cussans, D.; Flacher, H.; Goldstein, J.; Grimes, M.; Jacob, J.; Seif El Nasr-Storey, S.; Cole, J.; Hoad, C.; Hobson, P.; Morton, A.; Reid, I. D.; Auzinger, G.; Bainbridge, R.; Dauncey, P.; Hall, G.; James, T.; Magnan, A.-M.; Pesaresi, M.; Raymond, D. M.; Uchida, K.; Garabedian, A.; Heintz, U.; Narain, M.; Nelson, J.; Sagir, S.; Speer, T.; Swanson, J.; Tersegno, D.; Watson-Daniels, J.; Chertok, M.; Conway, J.; Conway, R.; Flores, C.; Lander, R.; Pellett, D.; Ricci-Tam, F.; Squires, M.; Thomson, J.; Yohay, R.; Burt, K.; Ellison, J.; Hanson, G.; Olmedo, M.; Si, W.; Yates, B. R.; Gerosa, R.; Sharma, V.; Vartak, A.; Yagil, A.; Zevi Della Porta, G.; Dutta, V.; Gouskos, L.; Incandela, J.; Kyre, S.; Mullin, S.; Patterson, A.; Qu, H.; White, D.; Dominguez, A.; Bartek, R.; Cumalat, J. P.; Ford, W. T.; Jensen, F.; Johnson, A.; Krohn, M.; Leontsinis, S.; Mulholland, T.; Stenson, K.; Wagner, S. R.; Apresyan, A.; Bolla, G.; Burkett, K.; Butler, J. N.; Canepa, A.; Cheung, H. W. K.; Chramowicz, J.; Christian, D.; Cooper, W. E.; Deptuch, G.; Derylo, G.; Gingu, C.; Grünendahl, S.; Hasegawa, S.; Hoff, J.; Howell, J.; Hrycyk, M.; Jindariani, S.; Johnson, M.; Kahlid, F.; Lei, C. M.; Lipton, R.; Lopes De Sá, R.; Liu, T.; Los, S.; Matulik, M.; Merkel, P.; Nahn, S.; Prosser, A.; Rivera, R.; Schneider, B.; Sellberg, G.; Shenai, A.; Spiegel, L.; Tran, N.; Uplegger, L.; Voirin, E.; Berry, D. R.; Chen, X.; Ennesser, L.; Evdokimov, A.; Evdokimov, O.; Gerber, C. E.; Hofman, D. J.; Makauda, S.; Mills, C.; Sandoval Gonzalez, I. D.; Alimena, J.; Antonelli, L. J.; Francis, B.; Hart, A.; Hill, C. S.; Parashar, N.; Stupak, J.; Bortoletto, D.; Bubna, M.; Hinton, N.; Jones, M.; Miller, D. H.; Shi, X.; Tan, P.; Baringer, P.; Bean, A.; Khalil, S.; Kropivnitskaya, A.; Majumder, D.; Wilson, G.; Ivanov, A.; Mendis, R.; Mitchell, T.; Skhirtladze, N.; Taylor, R.; Anderson, I.; Fehling, D.; Gritsan, A.; Maksimovic, P.; Martin, C.; Nash, K.; Osherson, M.; Swartz, M.; Xiao, M.; Bloom, K.; Claes, D. R.; Fangmeier, C.; Gonzalez Suarez, R.; Monroy, J.; Siado, J.; Hahn, K.; Sevova, S.; Sung, K.; Trovato, M.; Bartz, E.; Gershtein, Y.; Halkiadakis, E.; Kyriacou, S.; Lath, A.; Nash, K.; Osherson, M.; Schnetzer, S.; Stone, R.; Walker, M.; Malik, S.; Norberg, S.; Ramirez Vargas, J. E.; Alyari, M.; Dolen, J.; Godshalk, A.; Harrington, C.; Iashvili, I.; Kharchilava, A.; Nguyen, D.; Parker, A.; Rappoccio, S.; Roozbahani, B.; Alexander, J.; Chaves, J.; Chu, J.; Dittmer, S.; McDermott, K.; Mirman, N.; Rinkevicius, A.; Ryd, A.; Salvati, E.; Skinnari, L.; Soffi, L.; Tao, Z.; Thom, J.; Tucker, J.; Zientek, M.; Akgün, B.; Ecklund, K. M.; Kilpatrick, M.; Nussbaum, T.; Zabel, J.; Betchart, B.; Covarelli, R.; Demina, R.; Hindrichs, O.; Petrillo, G.; Eusebi, R.; Osipenkov, I.; Perloff, A.; Ulmer, K. A.

2017-06-01

The upgrade of the LHC to the High-Luminosity LHC (HL-LHC) is expected to increase the LHC design luminosity by an order of magnitude. This will require silicon tracking detectors with a significantly higher radiation hardness. The CMS Tracker Collaboration has conducted an irradiation and measurement campaign to identify suitable silicon sensor materials and strip designs for the future outer tracker at the CMS experiment. Based on these results, the collaboration has chosen to use n-in-p type silicon sensors and focus further investigations on the optimization of that sensor type. This paper describes the main measurement results and conclusions that motivated this decision.

Thermal stress during RTP processes and its possible effect on the light induced degradation in Cz-Si wafers

NASA Astrophysics Data System (ADS)

Kouhlane, Yacine; Bouhafs, Djoudi; Khelifati, Nabil; Guenda, Abdelkader; Demagh, Nacer-Eddine; Demagh, Assia; Pfeiffer, Pierre; Mezghiche, Salah; Hetatache, Warda; Derkaoui, Fahima; Nasraoui, Chahinez; Nwadiaru, Ogechi Vivian

2018-04-01

In this study, the carrier lifetime variation of p-type boron-doped Czochralski silicon (Cz-Si) wafers was investigated after a direct rapid thermal processing (RTP). Two wafers were passivated by silicon nitride (SiNx:H) layers, deposited by a PECVD system on both surfaces. Then the wafers were subjected to an RTP cycle at a peak temperature of 620 °C. The first wafer was protected (PW) from the direct radiative heating of the RTP furnace by placing the wafer between two as-cut Cz-Si shield wafers during the heat processing. The second wafer was not protected (NPW) and followed the same RTP cycle procedure. The carrier lifetime τ eff was measured using the QSSPC technique before and after illumination for 5 h duration at 0.5 suns. The immediate results of the measured lifetime (τ RTP ) after the RTP process have shown a regeneration in the lifetime of the two wafers with the PW wafer exhibiting an important enhancement in τ RTP as compared to the NPW wafer. The QSSPC measurements have indicated a good stable lifetime (τ d ) and a weak degradation effect was observed in the case of the PW wafer as compared to their initial lifetime value. Interferometry technique analyses have shown an enhancement in the surface roughness for the NPW wafer as compared to the protected one. Additionally, to improve the correlation between the RTP heat radiation stress and the carrier lifetime behavior, a simulation of the thermal stress and temperature profile using the finite element method on the wafers surface at RTP peak temperature of 620 °C was performed. The results confirm the reduction of the thermal stress with less heat losses for the PW wafer. Finally, the proposed method can lead to improving the lifetime of wafers by an RTP process at minimum energy costs.

InP-based photonic integrated circuit platform on SiC wafer.

PubMed

Takenaka, Mitsuru; Takagi, Shinichi

2017-11-27

We have numerically investigated the properties of an InP-on-SiC wafer as a photonic integrated circuit (PIC) platform. By bonding a thin InP-based semiconductor on a SiC wafer, SiC can be used as waveguide cladding, a heat sink, and a support substrate simultaneously. Since the refractive index of SiC is sufficiently low, PICs can be fabricated using InP-based strip and rib waveguides with a minimum bend radius of approximately 7 μm. High-thermal-conductivity SiC underneath an InP-based waveguide core markedly improves heat dissipation, resulting in superior thermal properties of active devices such as laser diodes. The InP-on-SiC wafer has significantly smaller thermal stress than InP-on-SiO 2 /Si wafer, which prevents the thermal degradation of InP-based devices during high-temperature processes. Thus, InP on SiC provides an ideal platform for high-performance PICs.

Sensitivity analysis of add-on price estimate for select silicon wafering technologies

NASA Technical Reports Server (NTRS)

Mokashi, A. R.

1982-01-01

The cost of producing wafers from silicon ingots is a major component of the add-on price of silicon sheet. Economic analyses of the add-on price estimates and their sensitivity internal-diameter (ID) sawing, multiblade slurry (MBS) sawing and fixed-abrasive slicing technique (FAST) are presented. Interim price estimation guidelines (IPEG) are used for estimating a process add-on price. Sensitivity analysis of price is performed with respect to cost parameters such as equipment, space, direct labor, materials (blade life) and utilities, and the production parameters such as slicing rate, slices per centimeter and process yield, using a computer program specifically developed to do sensitivity analysis with IPEG. The results aid in identifying the important cost parameters and assist in deciding the direction of technology development efforts.

Characteristics of nanocomposites and semiconductor heterostructure wafers using THz spectroscopy

NASA Astrophysics Data System (ADS)

Altan, Hakan

All optical, THz-Time Domain Spectroscopic (THz-TDS) methods were employed towards determining the electrical characteristics of Single Walled Carbon Nanotubes, Ion Implanted Si nanoclusters and Si1-xGe x, HFO2, SiO2 on p-type Si wafers. For the nanoscale composite materials, Visible Pump/THz Probe spectroscopy measurements were performed after observing that the samples were not sensitive to the THz radiation alone. The results suggest that the photoexcited nanotubes exhibit localized transport due to Lorentz-type photo-induced localized states from 0.2 to 0.7THz. The THz transmission is modeled through the photoexcited layer with an effective dielectric constant described by a Drude + Lorentz model and given by Maxwell-Garnett theory. Comparisons are made with other prevalent theories that describe electronic transport. Similar experiments were repeated for ion-implanted, 3-4nm Si nanoclusters in fused silica for which a similar behavior was observed. In addition, a change in reflection from Si1-xGex on Si, 200mm diameter semiconductor heterostructure wafers with 10% or 15% Ge content, was measured using THz-TDS methods. Drude model is utilized for the transmission/reflection measurements and from the reflection data the mobility of each wafer is estimated. Furthermore, the effect of high-kappa dielectric material (HfO2) on the electrical properties of p-type silicon wafers was characterized by utilizing non-contact, differential (pump-pump off) spectroscopic methods to differ between HfO2 and SiO 2 on Si wafers. The measurements are analyzed in two distinct transmission models, where one is an exact representation of the layered structure for each wafer and the other assumed that the response observed from the differential THz transmission was solely due to effects from interfacial traps between the dielectric layer and the substrate. The latter gave a more accurate picture of the carrier dynamics. From these measurements the effect of interfacial defects on

Nanoscale solely amorphous layer in silicon wafers induced by a newly developed diamond wheel

PubMed Central

Zhang, Zhenyu; Guo, Liangchao; Cui, Junfeng; Wang, Bo; Kang, Renke; Guo, Dongming

2016-01-01

Nanoscale solely amorphous layer is achieved in silicon (Si) wafers, using a developed diamond wheel with ceria, which is confirmed by high resolution transmission electron microscopy (HRTEM). This is different from previous reports of ultraprecision grinding, nanoindentation and nanoscratch, in which an amorphous layer at the top, followed by a crystalline damaged layer beneath. The thicknesses of amorphous layer are 43 and 48 nm at infeed rates of 8 and 15 μm/min, respectively, which is verified using HRTEM. Diamond-cubic Si-I phase is verified in Si wafers using selected area electron diffraction patterns, indicating the absence of high pressure phases. Ceria plays an important role in the diamond wheel for achieving ultrasmooth and bright surfaces using ultraprecision grinding. PMID:27734934

The uses of Man-Made diamond in wafering applications

NASA Technical Reports Server (NTRS)

Fallon, D. B.

1982-01-01

The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

Recycling of silicon: from industrial waste to biocompatible nanoparticles for nanomedicine

NASA Astrophysics Data System (ADS)

Kozlov, N. K.; Natashina, U. A.; Tamarov, K. P.; Gongalsky, M. B.; Solovyev, V. V.; Kudryavtsev, A. A.; Sivakov, V.; Osminkina, L. A.

2017-09-01

The formation of photoluminescent porous silicon (PSi) nanoparticles (NPs) is usually based on an expensive semiconductor grade wafers technology. Here, we report a low-cost method of PSi NPs synthesis from the industrial silicon waste remained after the wafer production. The proposed method is based on metal-assisted wet-chemical etching (MACE) of the silicon surface of cm-sized metallurgical grade silicon stones which leads to a nanostructuring of the surface due to an anisotropic etching, with subsequent ultrasound fracturing in water. The obtained PSi NPs exhibit bright red room temperature photoluminescence (PL) and demonstrate similar microstructure and physical characteristics in comparison with the nanoparticles synthesized from semiconductor grade Si wafers. PSi NPs prepared from metallurgical grade silicon stones, similar to silicon NPs synthesized from high purity silicon wafer, show low toxicity to biological objects that open the possibility of using such type of NPs in nanomedicine.

P-Type Silicon Strip Sensors for the new CMS Tracker at HL-LHC

DOE PAGES

Adam, W.; Bergauer, T.; Brondolin, E.; ...

2017-06-27

The upgrade of the LHC to the High-Luminosity LHC (HL-LHC) is expected to increase the LHC design luminosity by an order of magnitude. This will require silicon tracking detectors with a significantly higher radiation hardness. The CMS Tracker Collaboration has conducted an irradiation and measurement campaign to identify suitable silicon sensor materials and strip designs for the future outer tracker at the CMS experiment. Based on these results, the collaboration has chosen to use n-in-p type silicon sensors and focus further investigations on the optimization of that sensor type. Furthermore, this paper describes the main measurement results and conclusions thatmore » motivated this decision.« less

P-Type Silicon Strip Sensors for the new CMS Tracker at HL-LHC

DOE Office of Scientific and Technical Information (OSTI.GOV)

Adam, W.; Bergauer, T.; Brondolin, E.

The upgrade of the LHC to the High-Luminosity LHC (HL-LHC) is expected to increase the LHC design luminosity by an order of magnitude. This will require silicon tracking detectors with a significantly higher radiation hardness. The CMS Tracker Collaboration has conducted an irradiation and measurement campaign to identify suitable silicon sensor materials and strip designs for the future outer tracker at the CMS experiment. Based on these results, the collaboration has chosen to use n-in-p type silicon sensors and focus further investigations on the optimization of that sensor type. Furthermore, this paper describes the main measurement results and conclusions thatmore » motivated this decision.« less

Effect of dose and size on defect engineering in carbon cluster implanted silicon wafers

NASA Astrophysics Data System (ADS)

Okuyama, Ryosuke; Masada, Ayumi; Shigematsu, Satoshi; Kadono, Takeshi; Hirose, Ryo; Koga, Yoshihiro; Okuda, Hidehiko; Kurita, Kazunari

2018-01-01

Carbon-cluster-ion-implanted defects were investigated by high-resolution cross-sectional transmission electron microscopy toward achieving high-performance CMOS image sensors. We revealed that implantation damage formation in the silicon wafer bulk significantly differs between carbon-cluster and monomer ions after implantation. After epitaxial growth, small and large defects were observed in the implanted region of carbon clusters. The electron diffraction pattern of both small and large defects exhibits that from bulk crystalline silicon in the implanted region. On the one hand, we assumed that the silicon carbide structure was not formed in the implanted region, and small defects formed because of the complex of carbon and interstitial silicon. On the other hand, large defects were hypothesized to originate from the recrystallization of the amorphous layer formed by high-dose carbon-cluster implantation. These defects are considered to contribute to the powerful gettering capability required for high-performance CMOS image sensors.

Silicon nanostructure arrays prepared by single step metal assisted chemical etching from single crystal wafer

NASA Astrophysics Data System (ADS)

Sarkar, Kalyan; Das, Debajyoti

2018-04-01

Arrays of silicon nanostructures have been produced by single step Metal Assisted Chemical Etching (MACE) of single crystal Si-wafers at room temp and normal atmospheric condition. By studying optical and structural properties of the silicon nanowire like structures synthesized by Ag catalyst assisted chemical etching, a significant change in the reflectance spectra has been obtained leading to a gross reduction in reflectance from ˜31% to less than 1%. In comparison with bulk c-Si, the surface areas of the nanostructured samples have been increased significantly with the etching time, leading to an efficient absorption of light, favorable for photovoltaic applications.

p-type doping by platinum diffusion in low phosphorus doped silicon

NASA Astrophysics Data System (ADS)

Ventura, L.; Pichaud, B.; Vervisch, W.; Lanois, F.

2003-07-01

In this work we show that the cooling rate following a platinum diffusion strongly influences the electrical conductivity in weakly phosphorus doped silicon. Diffusions were performed at the temperature of 910 °C in the range of 8 32 hours in 0.6, 30, and 60 Ωrm cm phosphorus doped silicon samples. Spreading resistance profile analyses clearly show an n-type to p-type conversion under the surface when samples are cooled slowly. On the other hand, a compensation of the phosphorus donors can only be observed when samples are quenched. One Pt related acceptor deep level at 0.43 eV from the valence band is assumed to be at the origin of the type conversion mechanism. Its concentration increases by lowering the applied cooling rate. A complex formation with fast species such as interstitial Pt atoms or intrinsic point defects is expected. In 0.6 Ωrm cm phosphorus doped silicon, no acceptor deep level in the lower band gap is detected by DLTS measurement. This removes the opportunity of a pairing between phosphorus and platinum and suggests the possibility of a Fermi level controlled complex formation.

Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

PubMed

Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

2012-07-17

Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

Probing photo-carrier collection efficiencies of individual silicon nanowire diodes on a wafer substrate.

PubMed

Schmitt, S W; Brönstrup, G; Shalev, G; Srivastava, S K; Bashouti, M Y; Döhler, G H; Christiansen, S H

2014-07-21

Vertically aligned silicon nanowire (SiNW) diodes are promising candidates for the integration into various opto-electronic device concepts for e.g. sensing or solar energy conversion. Individual SiNW p-n diodes have intensively been studied, but to date an assessment of their device performance once integrated on a silicon substrate has not been made. We show that using a scanning electron microscope (SEM) equipped with a nano-manipulator and an optical fiber feed-through for tunable (wavelength, power using a tunable laser source) sample illumination, the dark and illuminated current-voltage (I-V) curve of individual SiNW diodes on the substrate wafer can be measured. Surprisingly, the I-V-curve of the serially coupled system composed of SiNW/wafers is accurately described by an equivalent circuit model of a single diode and diode parameters like series and shunting resistivity, diode ideality factor and photocurrent can be retrieved from a fit. We show that the photo-carrier collection efficiency (PCE) of the integrated diode illuminated with variable wavelength and intensity light directly gives insight into the quality of the device design at the nanoscale. We find that the PCE decreases for high light intensities and photocurrent densities, due to the fact that considerable amounts of photo-excited carriers generated within the substrate lead to a decrease in shunting resistivity of the SiNW diode and deteriorate its rectification. The PCE decreases systematically for smaller wavelengths of visible light, showing the possibility of monitoring the effectiveness of the SiNW device surface passivation using the shown measurement technique. The integrated device was pre-characterized using secondary ion mass spectrometry (SIMS), TCAD simulations and electron beam induced current (EBIC) measurements to validate the properties of the characterized material at the single SiNW diode level.

Surface-pattern geometry, topography, and chemical modifications during KrF excimer laser micro-drilling of p-type Si (111) wafers in ambient environment of HCl fumes in air

NASA Astrophysics Data System (ADS)

Zakria Butt, Muhammad; Saher, Sobia; Waqas Khaliq, Muhammad; Siraj, Khurram

2016-11-01

Eight mirror-like polished p-type Si (111) wafers were irradiated with 100, 200, 300, 400, 800, 1200, 1600, and 2000 KrF excimer laser pulses in ambient environment of HCl fumes in air. The laser parameters were: wavelength = 248 nm, pulse width = 20 ns, pulse energy = 20 mJ, and repetition rate = 20 Hz. For each set of laser pulses, characterization of the rectangular etched patterns formed on target surface was done by optical/scanning electron microscopy, XRD, and EDX techniques. The average etched depth increased with the increase in number of laser pulses from 100 to 2000 in accord with Sigmoidal (Boltzmann) function, whereas the average etch rate followed an exponential decay with the increase in number of laser pulses. However, the etched area, maximum etched depth, and maximum etch rate were found to increase linearly with the number of laser pulses, but the rate of increase was faster for 100-400 laser pulses (region I) than that for 800-2000 laser pulses (region II). The elemental composition for each etched-pattern determined by EDX shows that both O and Cl contents increase progressively with the increase in the number of laser shots in region I. However, in region II both O and Cl contents attain saturation values of about 39.33 wt.% and 0.14 wt.%, respectively. Perforation of Si wafers was achieved on irradiation with 1200-2000 laser pulses. XRD analysis confirmed the formation of SiO2, SiCl2 and SiCl4 phases in Si (111) wafers due to chemical reaction of silicon with both HCl fumes and oxygen in air.

Silicon direct bonding approach to high voltage power device (insulated gate bipolar transistors)

NASA Astrophysics Data System (ADS)

Cha, Giho; Kim, Youngchul; Jang, Hyungwoo; Kang, Hyunsoon; Song, Changsub

2001-10-01

Silicon direct bonding technique was successfully applied for the fabrication of high voltage IGBT (Insulated Gate Bipolar Transistor). In this work, 5 inch, p-type CZ wafer for handle wafer and n-type FZ wafer for device wafer were used and bonding the two wafers was performed at reduced pressure (1mmTorr) using a modified vacuum bonding machine. Since the breakdown voltage in high voltage device has been determined by the remained thickness of device layer, grinding and CMP steps should be carefully designed in order to acquire better uniformity of device layer. In order to obtain the higher removal rate and the final better uniformity of device layer, the harmony of the two processes must be considered. We found that the concave type of grinding profile and the optimal thickness of ground wafer was able to reduce the process time of CMP step and also to enhance the final thickness uniformity of device layer up to +/- 1%. Finally, when compared epitaxy layer with SDB wafer, the SDB wafer was found to be more favorable in terms of cost and electrical characteristics.

Using the surface charge profiler for in-line monitoring of doping concentration in silicon epitaxial wafer manufacturing

NASA Astrophysics Data System (ADS)

Tower, Joshua P.; Kamieniecki, Emil; Nguyen, M. C.; Danel, Adrien

1999-08-01

The Surface Charge Profiler (SCP) has been introduced for monitoring and development of silicon epitaxial processes. The SCP measures the near-surface doping concentration and offers advantages that lead to yield enhancement in several ways. First, non-destructive measurement technology enables in-line process monitoring, eliminating the need to sacrifice production wafers for resistivity measurements. Additionally, the full-wafer mapping capability helps in development of improved epitaxial growth processes and early detection of reactor problems. As examples, we present the use of SCP to study the effects of susceptor degradation in barrel reactors and to study autodoping for development of improved dopant uniformity.

Theoretical analysis of improved efficiency of silicon-wafer solar cells with textured nanotriangular grating structure

NASA Astrophysics Data System (ADS)

Zhang, Yaoju; Zheng, Jun; Zhao, Xuesong; Ruan, Xiukai; Cui, Guihua; Zhu, Haiyong; Dai, Yuxing

2018-03-01

A practical model of crystalline silicon-wafer solar cells is proposed in order to enhance the light absorption and improve the conversion efficiency of silicon solar cells. In the model, the front surface of the silicon photovoltaic film is designed to be a textured-triangular-grating (TTG) structure, and the ITO contact film and the antireflection coating (ARC) of glass are coated on the TTG surface of silicon solar cells. The optical absorption spectrum of solar cells are simulated by applying the finite difference time domain method. Electrical parameters of the solar cells are calculated using two models with and without carrier loss. The effect of structure parameters on the performance of the TTG cell is discussed in detail. It is found that the thickness (tg) of the ARC, period (p) of grating, and base angle (θ) of triangle have a crucial influence on the conversion efficiency. The optimal structure of the TTG cell is designed. The TTG solar cell can produce higher efficiency in a wide range of solar incident angle and the average efficiency of the optimal TTG cell over 7:30-16:30 time of day is 8% higher than that of the optimal plane solar cell. In addition, the study shows that the bulk recombination of carriers has an influence on the conversion efficiency of the cell, the conversion efficiency of the actual solar cell with carrier recombination is reduced by 20.0% of the ideal cell without carrier recombination.

Ultrafast carrier dynamics in a p-type GaN wafer under different carrier distributions

NASA Astrophysics Data System (ADS)

Fang, Yu; Yang, Junyi; Yang, Yong; Wu, Xingzhi; Xiao, Zhengguo; Zhou, Feng; Song, Yinglin

2016-02-01

The dependence of the carrier distribution on photoexcited carrier dynamics in a p-type Mg-doped GaN (GaN:Mg) wafer were systematically measured by femtosecond transient absorption (TA) spectroscopy. The homogeneity of the carrier distribution was modified by tuning the wavelength of the UV pulse excitation around the band gap of GaN:Mg. The TA kinetics appeared to be biexponential for all carrier distributions, and only the slower component decayed faster as the inhomogeneity of the carrier distribution increased. It was concluded that the faster component (50-70 ps) corresponded to the trap process of holes by the Mg acceptors, and the slower component (150-600 ps) corresponded to the combination of non-radiative surface recombination and intrinsic carrier recombination via dislocations. Moreover, the slower component increased gradually with the incident fluence due to the saturation of surface states.

Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer.

PubMed

Yu, Yang; Fong, Patrick W K; Wang, Shifeng; Surya, Charles

2016-11-29

High quality wafer-scale free-standing WS 2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS 2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS 2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS 2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS 2 , which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS 2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm 2 at -1 V which shows superior performances compared to the directly grown WS 2 /GaN heterojunctions.

Development of megasonic cleaning for silicon wafers

NASA Technical Reports Server (NTRS)

Mayer, A.

1980-01-01

A cleaning and drying system for processing at least 2500 three in. diameter wafers per hour was developed with a reduction in process cost. The system consists of an ammonia hydrogen peroxide bath in which both surfaces of 3/32 in. spaced, ion implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of megasonic transducers. The wafers are dried in the novel room temperature, high velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis.

P-stop isolation study of irradiated n-in-p type silicon strip sensors for harsh radiation environments

NASA Astrophysics Data System (ADS)

Printz, Martin; CMS Tracker Collaboration

2016-09-01

In order to determine the most radiation hard silicon sensors for the CMS Experiment after the Phase II Upgrade in 2023 a comprehensive study of silicon sensors after a fluence of up to 1.5 ×1015neq /cm2 corresponding to 3000fb-1 after the HL-LHC era has been carried out. The results led to the decision that the future Outer Tracker (20 cm < R < 110 cm) of CMS will consist of n-in-p type sensors. This technology is more radiation hard but also the manufacturing is more challenging compared to p-in-n type sensors due to additional process steps in order to suppress the accumulation of electrons between the readout strips. One possible isolation technique of adjacent strips is the p-stop structure which is a p-type material implantation with a certain pattern for each individual strip. However, electrical breakdown and charge collection studies indicate that the process parameters of the p-stop structure have to be carefully calibrated in order to achieve a sufficient strip isolation but simultaneously high breakdown voltages. Therefore a study of the isolation characteristics with four different silicon sensor manufacturers has been executed in order to determine the most suitable p-stop parameters for the harsh radiation environment during HL-LHC. Several p-stop doping concentrations, doping depths and different p-stop pattern have been realized and experiments before and after irradiation with protons and neutrons have been performed and compared to T-CAD simulation studies with Synopsys Sentaurus. The measurements combine the electrical characteristics measured with a semi-automatic probestation with Sr90 signal measurements and analogue readout. Furthermore, some samples have been investigated with the help of a cosmic telescope with high resolution allowing charge collection studies of MIPs penetrating the sensor between two strips.

Stress analysis in tungsten and Si 3N 4 coated silicon wafers

NASA Astrophysics Data System (ADS)

Ogilvie, Robert E.; Nicolich, Jeffrey

2009-08-01

A paper by G. Gerald Stoney [Gerald Stoney, The Tension of Metallic Films Deposited by Electrolysis, Proc. R. Soc. Lond. A 82 (1909) 172-175], entitled "The Tension of Metallic Films deposited by Electrolysis," was presented to the Royal Society of London by the Hon. C. A. Parsons. It was well known at that time that films deposited electrolytically were liable to peel off when exceeding a certain thickness. After examining many thin Steel rules of thickness d which have a thin, t, deposit of Nickel, which curved the Rule to a radius r. Taking the moments about the point b for the steel, Stoney then arrived at the following equation where the integral must be equal to zero; ∫d0(E/r)(b-x)xdx=0sothat b=2/3d From the solution of Eq. (1), we obtain the important fact that the neutral plane is at 2/3 the thickness of the rule from film surface. This also implies that the absolute value of the stress on the film side is twice that on the opposite side of the steel rule. The important point is that if the absolute stress in the silicon on the film side is twice that on the opposite side then the position of the neutral plane must be at 2/3 d. The purpose of this paper is to show that the neutral plane in silicon wafers, which have a thin film (~ 3 μm) of tungsten or Si 3N 4 is indeed at 2/3 the thickness of the wafer.

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

NASA Technical Reports Server (NTRS)

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Dry etch method for texturing silicon and device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gershon, Talia S.; Haight, Richard A.; Kim, Jeehwan

2017-07-25

A method for texturing silicon includes loading a silicon wafer into a vacuum chamber, heating the silicon wafer and thermal cracking a gas to generate cracked sulfur species. The silicon wafer is exposed to the cracked sulfur species for a time duration in accordance with a texture characteristic needed for a surface of the silicon wafer.

Dissolution of Oxygen Precipitate Nuclei in n-Type CZ-Si Wafers to Improve Their Material Quality: Experimental Results

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sopori, Bhushan; Basnyat, Prakash; Devayajanam, Srinivas

2017-01-01

We present experimental results which show that oxygen-related precipitate nuclei (OPN) present in p-doped, n-type, Czochralski wafers can be dissolved using a flash-annealing process, yielding very high quality wafers for high-efficiency solar cells. Flash annealing consists of heating a wafer in an optical furnace to temperature between 1150 and 1250 degrees C for a short time. This process produces a large increase in the minority carrier lifetime (MCLT) and homogenizes each wafer. We have tested wafers from different axial locations of two ingots. All wafers reach nearly the same high value of MCLT. The OPN dissolution is confirmed by oxygenmore » analysis using Fourier transform infrared spectra and injection-level dependence of MCLT.« less

Germanium photodetectors fabricated on 300 mm silicon wafers for near-infrared focal plane arrays

NASA Astrophysics Data System (ADS)

Zeller, John W.; Rouse, Caitlin; Efstathiadis, Harry; Dhar, Nibir K.; Wijewarnasuriya, Priyalal; Sood, Ashok K.

2017-09-01

SiGe p-i-n photodetectors have been fabricated on 300 mm (12") diameter silicon (Si) wafers utilizing high throughput, large-area complementary metal-oxide semiconductor (CMOS) technologies. These Ge photodetectors are designed to operate in room temperature environments without cooling, and thus have potential size and cost advantages over conventional cooled infrared detectors. The two-step fabrication process for the p-i-n photodetector devices, designed to minimize the formation of defects and threading dislocations, involves low temperature epitaxial growth of a thin p+ (boron) Ge seed/buffer layer, followed by higher temperature deposition of a thicker Ge intrinsic layer. Scanning electron microscopy (SEM) and transmission electron microscopy (TEM) demonstrated uniform layer compositions with well defined layer interfaces and reduced dislocation density. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) was likewise employed to analyze the doping levels of the p+ and n+ layers. Current-voltage (I-V) measurements demonstrated that these SiGe photodetectors, when exposed to incident visible-NIR radiation, exhibited dark currents down below 1 μA and significant enhancement in photocurrent at -1 V. The zero-bias photocurrent was also relatively high, showing a minimal drop compared to that at -1 V bias.

Six Sigma-based approach to optimise the diffusion process of crystalline silicon solar cell manufacturing

NASA Astrophysics Data System (ADS)

Prasad, A. Guru; Saravanan, S.; Gijo, E. V.; Dasari, Sreenivasa Murty; Tatachar, Raghu; Suratkar, Prakash

2016-02-01

Silicon-based photovoltaics (PV) plays the dominant role in the history of PV due to the continuous process and technology improvement in silicon solar cells and its manufacturing flow. In general, silicon solar cell process uses either p-type- or n-type-doped silicon as the starting material. Currently, most of the PV industries use p-type, boron-doped silicon wafer as the starting material. In this work too, the boron-doped wafers were considered as the starting material to create pn junction and phosphorus was used as n-type doping material. Industries use either phosphorous oxy chloride (POCl3) or ortho phosphoric acid (H3PO4) as the precursor for doping phosphorous. While the industries use POCl3 as the precursor, the throughput is lesser than that of the industries' use of H3PO4 due to the manufacturing limitations of the POCl3-based equipments. Hence, in order to achieve the operational excellence in POCl3-based equipments, business strategies such as the Six Sigma methodology have to be adapted. This paper describes the application of Six Sigma Define-Measure-Analyze-Improve-Control methodology for throughput improvement of the phosphorus doping process. The optimised recipe has been implemented in the production and it is running successfully. As a result of this project, an effective gain of 0.9 MW was reported per annum.

Investigation of Backside Textures for Genesis Solar Wind Silicon Collectors

NASA Technical Reports Server (NTRS)

Gonzalez, C. P.; Burkett, P. J.; Rodriguez, M. C.; Allton, J. H.

2014-01-01

Genesis solar wind collectors were comprised of a suite of 15 types of ultrapure materials. The single crystal, pure silicon collectors were fabricated by two methods: float zone (FZ) and Czochralski (CZ). Because of slight differences in bulk purity and surface cleanliness among the fabrication processes and the specific vendor, it is desirable to know which variety of silicon and identity of vendor, so that appropriate reference materials can be used. The Czochralski method results in a bulk composition with slightly higher oxygen, for example. The CZ silicon array wafers that were Genesis-flown were purchased from MEMC Electronics. Most of the Genesis-flown FZ silicon was purchased from Unisil and cleaned by MEMC, although a few FZ wafers were acquired from International Wafer Service (IWS).

Locally-enhanced light scattering by a monocrystalline silicon wafer

NASA Astrophysics Data System (ADS)

Ma, Li; Zhang, Pan; Li, Zhen-Hua; Liu, Chun-Xiang; Li, Xing; Zhan, Zi-Jun; Ren, Xiao-Rong; He, Chang-Wei; Chen, Chao; Cheng, Chuan-Fu

2018-03-01

We study the optical properties of light scattering by a monocrystalline silicon wafer, by using transparent material to replicate its surface structure and illuminating a fabricated sample with a laser source. The experimental results show that the scattering field contains four spots of concentrated intensity with high local energy, and these spots are distributed at the four vertices of a square with lines of intensity linking adjacent spots. After discussing simulations of and theory about the formation of this light scattering, we conclude that the scattering field is formed by the effects of both geometrical optics and physical optics. Moreover, we calculate the central angle of the spots in the light field, and the result indicates that the locally-enhanced intensity spots have a definite scattering angle. These results may possibly provide a method for improving energy efficiency within mono-Si based solar cells.

High-Speed Scalable Silicon-MoS2 P-N Heterojunction Photodetectors

PubMed Central

Dhyani, Veerendra; Das, Samaresh

2017-01-01

Two-dimensional molybdenum disulfide (MoS2) is a promising material for ultrasensitive photodetector owing to its favourable band gap and high absorption coefficient. However, their commercial applications are limited by the lack of high quality p-n junction and large wafer scale fabrication process. A high speed Si/MoS2 p-n heterojunction photodetector with simple and CMOS compatible approach has been reported here. The large area MoS2 thin film on silicon platform has been synthesized by sulfurization of RF-sputtered MoO3 films. The fabricated molecular layers of MoS2 on silicon offers high responsivity up to 8.75 A/W (at 580 nm and 3 V bias) with ultra-fast response of 10 μsec (rise time). Transient measurements of Si/MoS2 heterojunction under the modulated light reveal that the devices can function up to 50 kHz. The Si/MoS2 heterojunction is found to be sensitive to broadband wavelengths ranging from visible to near-infrared light with maximum detectivity up to ≈1.4 × 1012 Jones (2 V bias). Reproducible low dark current and high responsivity from over 20 devices in the same wafer has been measured. Additionally, the MoS2/Si photodetectors exhibit excellent stability in ambient atmosphere. PMID:28281652

Fabrication of WS2/GaN p-n Junction by Wafer-Scale WS2 Thin Film Transfer

PubMed Central

Yu, Yang; Fong, Patrick W. K.; Wang, Shifeng; Surya, Charles

2016-01-01

High quality wafer-scale free-standing WS2 grown by van der Waals rheotaxy (vdWR) using Ni as a texture promoting layer is reported. The microstructure of vdWR grown WS2 was significantly modified from mixture of crystallites with their c-axes both parallel to (type I) and perpendicular to (type II) the substrate to large type II crystallites. Wafer-scale transfer of vdWR grown WS2 onto different substrates by an etching-free technique was demonstrated for the first time that utilized the hydrophobic property of WS2 and hydrophilic property of sapphire. Our results show that vdWR is a reliable technique to obtain type-II textured crystallites in WS2, which is the key factor for the wafer-scale etching-free transfer. The transferred films were found to be free of observable wrinkles, cracks, or polymer residues. High quality p-n junctions fabricated by room-temperature transfer of the p-type WS2 onto an n-type GaN was demonstrated with a small leakage current density of 29.6 μA/cm2 at −1 V which shows superior performances compared to the directly grown WS2/GaN heterojunctions. PMID:27897210

Silicon (100)/SiO2 by XPS

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jensen, David S.; Kanyal, Supriya S.; Madaan, Nitesh

2013-09-25

Silicon (100) wafers are ubiquitous in microfabrication and, accordingly, their surface characteristics are important. Herein, we report the analysis of Si (100) via X-ray photoelectron spectroscopy (XPS) using monochromatic Al K radiation. Survey scans show that the material is primarily silicon and oxygen, and the Si 2p region shows two peaks that correspond to elemental silicon and silicon dioxide. Using these peaks the thickness of the native oxide (SiO2) was estimated using the equation of Strohmeier.1 The oxygen peak is symmetric. The material shows small amounts of carbon, fluorine, and nitrogen contamination. These silicon wafers are used as the basemore » material for subsequent growth of templated carbon nanotubes.« less

Water-assisted pulsed Er:YAG laser interaction with silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Jaehun; Ki, Hyungson, E-mail: hski@unist.ac.kr

2015-07-07

Silicon is virtually transparent to the Er:YAG laser with a wavelength of 2.94 μm. In this study, we report that moderately doped silicon (1–10 Ω cm) can be processed by a pulsed Er:YAG laser with a pulse duration of 350 μs and a peak laser intensity of 1.7 × 10{sup 5} W/cm{sup 2} by applying a thin water layer on top of silicon as a light absorbing medium. In this way, water is heated first by strongly absorbing the laser energy and then heats up the silicon wafer indirectly. As the silicon temperature rises, the free carrier concentration and therefore the absorption coefficient of silicon willmore » increase significantly, which may enable the silicon to get directly processed by the Er:YAG laser when the water is vaporized completely. We also believe that the change in surface morphology after melting could contribute to the increase in the laser beam absorptance. It was observed that 525 nm-thick p-type wafer specimens were fully penetrated after 15 laser pulses were irradiated. Bright yellow flames were observed during the process, which indicates that the silicon surface reached the melting point.« less

Electrically Conductive and Optically Active Porous Silicon Nanowires

PubMed Central

Qu, Yongquan; Liao, Lei; Li, Yujing; Zhang, Hua; Huang, Yu; Duan, Xiangfeng

2009-01-01

We report the synthesis of vertical silicon nanowire array through a two-step metal-assisted chemical etching of highly doped n-type silicon (100) wafers in a solution of hydrofluoric acid and hydrogen peroxide. The morphology of the as-grown silicon nanowires is tunable from solid nonporous nanowires, nonporous/nanoporous core/shell nanowires, and entirely nanoporous nanowires by controlling the hydrogen peroxide concentration in the etching solution. The porous silicon nanowires retain the single crystalline structure and crystallographic orientation of the starting silicon wafer, and are electrically conductive and optically active with visible photoluminescence. The combination of electronic and optical properties in the porous silicon nanowires may provide a platform for the novel optoelectronic devices for energy harvesting, conversion and biosensing. PMID:19807130

A novel approach of high speed scratching on silicon wafers at nanoscale depths of cut

PubMed Central

Zhang, Zhenyu; Guo, Dongming; Wang, Bo; Kang, Renke; Zhang, Bi

2015-01-01

In this study, a novel approach of high speed scratching is carried out on silicon (Si) wafers at nanoscale depths of cut to investigate the fundamental mechanisms in wafering of solar cells. The scratching is conducted on a Si wafer of 150 mm diameter with an ultraprecision grinder at a speed of 8.4 to 15 m/s. Single-point diamonds of a tip radius of 174, 324, and 786 nm, respectively, are used in the study. The study finds that at the onset of chip formation, an amorphous layer is formed at the topmost of the residual scratch, followed by the pristine crystalline lattice beneath. This is different from the previous findings in low speed scratching and high speed grinding, in which there is an amorphous layer at the top and a damaged layer underneath. The final width and depth of the residual scratch at the onset of chip formation measured vary from 288 to 316 nm, and from 49 to 62 nm, respectively. High pressure phases are absent from the scratch at the onset of either chip or crack formation. PMID:26548771

2-dimensional ion velocity distributions measured by laser-induced fluorescence above a radio-frequency biased silicon wafer

NASA Astrophysics Data System (ADS)

Moore, Nathaniel B.; Gekelman, Walter; Pribyl, Patrick; Zhang, Yiting; Kushner, Mark J.

2013-08-01

The dynamics of ions traversing sheaths in low temperature plasmas are important to the formation of the ion energy distribution incident onto surfaces during microelectronics fabrication. Ion dynamics have been measured using laser-induced fluorescence (LIF) in the sheath above a 30 cm diameter, 2.2 MHz-biased silicon wafer in a commercial inductively coupled plasma processing reactor. The velocity distribution of argon ions was measured at thousands of positions above and radially along the surface of the wafer by utilizing a planar laser sheet from a pulsed, tunable dye laser. Velocities were measured both parallel and perpendicular to the wafer over an energy range of 0.4-600 eV. The resulting fluorescence was recorded using a fast CCD camera, which provided resolution of 0.4 mm in space and 30 ns in time. Data were taken at eight different phases during the 2.2 MHz cycle. The ion velocity distributions (IVDs) in the sheath were found to be spatially non-uniform near the edge of the wafer and phase-dependent as a function of height. Several cm above the wafer the IVD is Maxwellian and independent of phase. Experimental results were compared with simulations. The experimental time-averaged ion energy distribution function as a function of height compare favorably with results from the computer model.

Low-temperature wafer direct bonding of silicon and quartz glass by a two-step wet chemical surface cleaning

NASA Astrophysics Data System (ADS)

Wang, Chenxi; Xu, Jikai; Zeng, Xiaorun; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

2018-02-01

We demonstrate a facile bonding process for combining silicon and quartz glass wafers by a two-step wet chemical surface cleaning. After a post-annealing at 200 °C, strong bonding interfaces with no defects or microcracks were obtained. On the basis of the detailed surface and bonding interface characterizations, the bonding mechanism was explored and discussed. The amino groups terminated on the cleaned surfaces might contribute to the bonding strength enhancement during the annealing. This cost-effective bonding process has great potentials for silicon- and glass-based heterogeneous integrations without requiring a vacuum system.

W-Band On-Wafer Measurement of Uniplanar Slot-Type Antennas

NASA Technical Reports Server (NTRS)

Raman, Sanjay; Gauthier, Gildas P.; Rebeiz, Gabriel M.

1997-01-01

Uniplanar slot-type antennas such as coplanar waveguide fed single- and dual-polarized slot-ring antennas and double folded-slot antennas are characterized using a millimeter-wave network analyzer and on-wafer measurement techniques. The antennas are designed to be mounted on a dielectric lens to minimize power loss into substrate modes and realize high-gain antenna patterns. On-wafer measurements are performed by placing the antenna wafer on a thick dielectric spacer of similar e(sub t) and eliminating the reflection from the probe station chuck with time-domain gating. The measured results agree well with method-of-moments simulations.

Commercial silicon-on-insulator (SOI) wafers as a versatile substrate for laser desorption/ionization mass spectrometry.

PubMed

Kim, Shin Hye; Kim, Jeongkwon; Moon, Dae Won; Han, Sang Yun

2013-01-01

We report here that a commercial silicon-on-insulator (SOI) wafer offers an opportunity for laser desorption/ionization (LDI) of peptide molecules, which occurs directly from its flat surface without requiring special surface preparation. The LDI-on-SOI exhibits intact ionization of peptides with a good detection limit of lower than 20 fmol, of which the mass range is demonstrated up to insulin with citric acid additives. The LDI process most likely arises from laser-induced surface heating promoted by two-dimensional thermal confinement in the thin Si surface layer of the SOI wafer. As a consequence of the thermal process, the LDI-on-SOI method is also capable of creating post-source decay (PSD) of the resulting peptide LDI ions, which is suitable for peptide sequencing using conventional TOF/TOF mass spectrometry.

Real-time direct and diffraction X-ray imaging of irregular silicon wafer breakage.

PubMed

Rack, Alexander; Scheel, Mario; Danilewsky, Andreas N

2016-03-01

Fracture and breakage of single crystals, particularly of silicon wafers, are multi-scale problems: the crack tip starts propagating on an atomic scale with the breaking of chemical bonds, forms crack fronts through the crystal on the micrometre scale and ends macroscopically in catastrophic wafer shattering. Total wafer breakage is a severe problem for the semiconductor industry, not only during handling but also during temperature treatments, leading to million-dollar costs per annum in a device production line. Knowledge of the relevant dynamics governing perfect cleavage along the {111} or {110} faces, and of the deflection into higher indexed {hkl} faces of higher energy, is scarce due to the high velocity of the process. Imaging techniques are commonly limited to depicting only the state of a wafer before the crack and in the final state. This paper presents, for the first time, in situ high-speed crack propagation under thermal stress, imaged simultaneously in direct transmission and diffraction X-ray imaging. It shows how the propagating crack tip and the related strain field can be tracked in the phase-contrast and diffracted images, respectively. Movies with a time resolution of microseconds per frame reveal that the strain and crack tip do not propagate continuously or at a constant speed. Jumps in the crack tip position indicate pinning of the crack tip for about 1-2 ms followed by jumps faster than 2-6 m s(-1), leading to a macroscopically observed average velocity of 0.028-0.055 m s(-1). The presented results also give a proof of concept that the described X-ray technique is compatible with studying ultra-fast cracks up to the speed of sound.

Liquid-phase-deposited siloxane-based capping layers for silicon solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Veith-Wolf, Boris; Wang, Jianhui; Hannu-Kuure, Milja

2015-02-02

We apply non-vacuum processing to deposit dielectric capping layers on top of ultrathin atomic-layer-deposited aluminum oxide (AlO{sub x}) films, used for the rear surface passivation of high-efficiency crystalline silicon solar cells. We examine various siloxane-based liquid-phase-deposited (LPD) materials. Our optimized AlO{sub x}/LPD stacks show an excellent thermal and chemical stability against aluminum metal paste, as demonstrated by measured surface recombination velocities below 10 cm/s on 1.3 Ωcm p-type silicon wafers after firing in a belt-line furnace with screen-printed aluminum paste on top. Implementation of the optimized LPD layers into an industrial-type screen-printing solar cell process results in energy conversion efficiencies ofmore » up to 19.8% on p-type Czochralski silicon.« less

Silicon micro-mold

DOEpatents

Morales, Alfredo M [Livermore, CA

2006-10-24

The present invention describes a method for rapidly fabricating a robust 3-dimensional silicon-mold for use in preparing complex metal micro-components. The process begins by depositing a conductive metal layer onto one surface of a silicon wafer. A thin photoresist and a standard lithographic mask are then used to transfer a trace image pattern onto the opposite surface of the wafer by exposing and developing the resist. The exposed portion of the silicon substrate is anisotropically etched through the wafer thickness down to conductive metal layer to provide an etched pattern consisting of a series of rectilinear channels and recesses in the silicon which serve as the silicon micro-mold. Microcomponents are prepared with this mold by first filling the mold channels and recesses with a metal deposit, typically by electroplating, and then removing the silicon micro-mold by chemical etching.

Slicing of silicon into sheet material. Silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project. Third quarterly report, September 20, 1976--December 19, 1976

DOE Office of Scientific and Technical Information (OSTI.GOV)

Holden, S.C.

1976-12-27

The stability of tensioned blades used in multiblade sawing does not seem to be the limitation in cutting with thin blades. So far, 0.010 cm thick blades have been totally unsuccessful. Recently, 0.015 cm blades have proven successful in wafering, offering an 0.005 cm reduction in the silicon used per slice. The failure of thin blades is characterized as a possible result of blade misalignment or from the inherent uncontrollability of the loose abrasive multiblade process. Corrective procedures will be employed in the assembly of packages to eliminate one type of blade misalignment. Two ingots were sliced with the samemore » batch of standard silicon carbide abrasive slurry to determine the useful lifetime of this expendable material. After 250 slices, the cutting efficiency had not degraded. Further tests will be continued to establish the maximum lifetime of both silicon carbide and boron carbide abrasive. Electron microscopy will be employed to evaluate the wear of abrasive particles in the failure of abrasive slurry. The surface damage of silicon wafers has been characterized as predominantly subsurface fracture. Damage with No. 600 SiC is between 10 and 15 microns into the wafer surface. This agrees well with previous investigations of damage from silicon carbide abrasive papers.« less

Uncertainty of a hybrid surface temperature sensor for silicon wafers and comparison with an embedded thermocouple.

PubMed

Iuchi, Tohru; Gogami, Atsushi

2009-12-01

We have developed a user-friendly hybrid surface temperature sensor. The uncertainties of temperature readings associated with this sensor and a thermocouple embedded in a silicon wafer are compared. The expanded uncertainties (k=2) of the hybrid temperature sensor and the embedded thermocouple are 2.11 and 2.37 K, respectively, in the temperature range between 600 and 1000 K. In the present paper, the uncertainty evaluation and the sources of uncertainty are described.

Experimental setup for camera-based measurements of electrically and optically stimulated luminescence of silicon solar cells and wafers.

PubMed

Hinken, David; Schinke, Carsten; Herlufsen, Sandra; Schmidt, Arne; Bothe, Karsten; Brendel, Rolf

2011-03-01

We report in detail on the luminescence imaging setup developed within the last years in our laboratory. In this setup, the luminescence emission of silicon solar cells or silicon wafers is analyzed quantitatively. Charge carriers are excited electrically (electroluminescence) using a power supply for carrier injection or optically (photoluminescence) using a laser as illumination source. The luminescence emission arising from the radiative recombination of the stimulated charge carriers is measured spatially resolved using a camera. We give details of the various components including cameras, optical filters for electro- and photo-luminescence, the semiconductor laser and the four-quadrant power supply. We compare a silicon charged-coupled device (CCD) camera with a back-illuminated silicon CCD camera comprising an electron multiplier gain and a complementary metal oxide semiconductor indium gallium arsenide camera. For the detection of the luminescence emission of silicon we analyze the dominant noise sources along with the signal-to-noise ratio of all three cameras at different operation conditions.

Surface quality of silicon wafer improved by hydrodynamic effect polishing

NASA Astrophysics Data System (ADS)

Peng, Wenqiang; Guan, Chaoliang; Li, Shengyi

2014-08-01

Differing from the traditional pad polishing, hydrodynamic effect polishing (HEP) is non-contact polishing with the wheel floated on the workpiece. A hydrodynamic lubricated film is established between the wheel and the workpiece when the wheel rotates at a certain speed in HEP. Nanoparticles mixed with deionized water are employed as the polishing slurry, and with action of the dynamic pressure, nanoparticles with high chemisorption due to the high specific surface area can easily reacted with the surface atoms forming a linkage with workpiece surface. The surface atoms are dragged away when nanoparticles are transported to separate by the flow shear stress. The development of grand scale integration put extremely high requirements on the surface quality on the silicon wafer with surface roughness at subnanometer and extremely low surface damage. In our experiment a silicon sample was processed by HEP, and the surface topography before and after polishing was observed by the atomic force microscopy. Experiment results show that plastic pits and bumpy structures on the initial surface have been removed away clearly with the removal depth of 140nm by HEP process. The processed surface roughness has been improved from 0.737nm RMS to 0.175nm RMS(10μm×10μm) and the section profile shows peaks of the process surface are almost at the same height. However, the machining ripples on the wheel surface will duplicate on the silicon surface under the action of the hydrodynamic effect. Fluid dynamic simulation demonstrated that the coarse surface on the wheel has greatly influence on the distribution of shear stress and dynamic pressure on the workpiece surface.

Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

NASA Astrophysics Data System (ADS)

Turner, K. T.; Spearing, S. M.

2002-12-01

Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

Exceptional gettering response of epitaxially grown kerfless silicon

DOE PAGES

Powell, D. M.; Markevich, V. P.; Hofstetter, J.; ...

2016-02-08

The bulk minority-carrier lifetime in p- and n-type kerfless epitaxial (epi) crystalline silicon wafers is shown to increase >500 during phosphorus gettering. We employ kinetic defect simulations and microstructural characterization techniques to elucidate the root cause of this exceptional gettering response. Simulations and deep-level transient spectroscopy (DLTS) indicate that a high concentra- tion of point defects (likely Pt) is “locked in” during fast (60 C/min) cooling during epi wafer growth. The fine dispersion of moderately fast-diffusing recombination-active point defects limits as-grown lifetime but can also be removed during gettering, confirmed by DLTS measurements. Synchrotron-based X-ray fluorescence microscopy indicates metal agglomeratesmore » at structural defects, yet the structural defect density is sufficiently low to enable high lifetimes. Consequently, after phosphorus diffusion gettering, epi silicon exhibits a higher lifetime than materials with similar bulk impurity contents but higher densities of structural defects, including multicrystalline ingot and ribbon silicon materials. As a result, device simulations suggest a solar-cell efficiency potential of this material >23%.« less

1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10more » billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).« less

Surface chemistry of a hydrogenated mesoporous p-type silicon

NASA Astrophysics Data System (ADS)

Media, El-Mahdi; Outemzabet, Ratiba

2017-02-01

The finality of this work is devoted to the grafting of organic molecules on hydrogen passivated mesoporous silicon surfaces. The study would aid in the development for the formation of organic monolayers on silicon surface to be exploited for different applications such as the realisation of biosensors and medical devices. The basic material is silicon which has been first investigated by FTIR at atomistic plane during the anodic forward and backward polarization (i.e. "go" and "return"). For this study, we applied a numerical program based on least squares method to infrared absorbance spectra obtained by an in situ attenuated total reflection on p-type silicon in diluted HF electrolyte. Our numerical treatment is based on the fitting of the different bands of IR absorbance into Gaussians corresponding to the different modes of vibration of molecular groups such as siloxanes and hydrides. An adjustment of these absorbance bands is done systematically. The areas under the fitted bands permit one to follow the intensity of the different modes of vibration that exist during the anodic forward and backward polarization in order to compare the reversibility of the phenomenon of the anodic dissolution of silicon. It permits also to follow the evolution between the hydrogen silicon termination at forward and backward scanning applied potential. Finally a comparison between the states of the initial and final surface was carried out. We confirm the presence of clearly four and three distinct vibration modes of siloxanes/hydroxide, SiOx, and hydrides, SiHx, respectively. The results show clearly that the adsorbed species found in the final stage after an electrochemical treatment consist of surface hydrogen and they show also that the surface morphology is different compared to the starting one, which is considered as reference. It is clear that the H-terminated of porous silicon surface is hydrophobic in nature. The hydrophobic character of this surface makes difficult

Process Research on Polycrystalline Silicon Material (PROPSM)

NASA Technical Reports Server (NTRS)

Culik, J. S.

1983-01-01

The performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was investigated by measuring the illuminated current voltage (I-V) characteristics of the minicell wafer set. The average short circuit current on different wafers is 3 to 14 percent lower than that of single crystal Czochralski silicon. The scatter was typically less than 3 percent. The average open circuit voltage is 20 to 60 mV less than that of single crystal silicon. The scatter in the open circuit voltage of most of the polycrystalline silicon wafers was 15 to 20 mV, although two wafers had significantly greater scatter than this value. The fill factor of both polycrystalline and single crystal silicon cells was typically in the range of 60 to 70 percent; however several polycrystalline silicon wafers have fill factor averages which are somewhat lower and have a significantly larger degree of scatter.

Microbridge testing of plasma-enhanced chemical-vapor deposited silicon oxide films on silicon wafers

NASA Astrophysics Data System (ADS)

Cao, Zhiqiang; Zhang, Tong-Yi; Zhang, Xin

2005-05-01

Plasma-enhanced chemical-vapor deposited (PECVD) silane-based oxides (SiOx) have been widely used in both microelectronics and microelectromechanical systems (MEMS) to form electrical and/or mechanical components. In this paper, a nanoindentation-based microbridge testing method is developed to measure both the residual stresses and Young's modulus of PECVD SiOx films on silicon wafers. Theoretically, we considered both the substrate deformation and residual stress in the thin film and derived a closed formula of deflection versus load. The formula fitted the experimental curves almost perfectly, from which the residual stresses and Young's modulus of the film were determined. Experimentally, freestanding microbridges made of PECVD SiOx films were fabricated using the silicon undercut bulk micromachining technique. Some microbridges were subjected to rapid thermal annealing (RTA) at a temperature of 400 °C, 600 °C, or 800 °C to simulate the thermal process in the device fabrication. The results showed that the as-deposited PECVD SiOx films had a residual stress of -155±17MPa and a Young's modulus of 74.8±3.3GPa. After the RTA, Young's modulus remained relatively unchanged at around 75 GPa, however, significant residual stress hysteresis was found in all the films. A microstructure-based mechanism was then applied to explain the experimental results of the residual stress changes in the PECVD SiOx films after the thermal annealing.

High purith low defect FZ silicon

NASA Technical Reports Server (NTRS)

Kimura, H.; Robertson, G.

1985-01-01

The most common intrinsic defects in dislocation-free float zone (FZ) silicon crystals are the A- and B-type swirl defects. The mechanisms of their formation and annihilation have been extensively studied. Another type of defect in dislocation-free FZ crystals is referred to as a D-type defect. Concentrations of these defects can be minimized by optimizing the growth conditions, and the residual swirls can be reduced by the post-growth extrinsic gettering process. Czochralski (Cz) silicon wafers are known to exhibit higher resistance to slip and warpage due to thermal stress than do FZ wafers. The Cz crystals containing dislocations are more resistant to dislocation movement than dislocated FZ crystals because of the locking of dislocations by oxygen atoms present in the Cz crystals. Recently a transverse magnetic field was applied during the FZ growth of extrinsic silicon. Resultant flow patterns, as revealed by striation etching and spreading resistance in Ga-doped silicon crystals, indicate strong effects of the transverse magnetic field on the circulation within the melt. At fields of 5500 gauss, the fluid flow in the melt volume is so altered as to affect the morphology of the growing crystal.

Sub-Micrometer Zeolite Films on Gold-Coated Silicon Wafers with Single-Crystal-Like Dielectric Constant and Elastic Modulus

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tiriolo, Raffaele; Rangnekar, Neel; Zhang, Han

A low-temperature synthesis coupled with mild activation produces zeolite films exhibiting low dielectric constant (low-k) matching the theoretically predicted and experimentally measured values for single crystals. This synthesis and activation method allows for the fabrication of a device consisting of a b-oriented film of the pure-silica zeolite MFI (silicalite-1) supported on a gold-coated silicon wafer. The zeolite seeds are assembled by a manual assembly process and subjected to optimized secondary growth conditions that do not cause corrosion of the gold underlayer, while strongly promoting in-plane growth. The traditional calcination process is replaced with a non-thermal photochemical activation to ensure preservationmore » of an intact gold layer. The dielectric constant (k), obtained through measurement of electrical capacitance in a metal-insulator-metal configuration, highlights the ultralow k approximate to 1.7 of the synthetized films, which is among the lowest values reported for an MFI film. There is large improvement in elastic modulus of the film (E approximate to 54 GPa) over previous reports, potentially allowing for integration into silicon wafer processing technology.« less

Method using laser irradiation for the production of atomically clean crystalline silicon and germanium surfaces

DOEpatents

Ownby, G.W.; White, C.W.; Zehner, D.M.

1979-12-28

This invention relates to a new method for removing surface impurities from crystalline silicon or germanium articles, such as off-the-shelf p- or n-type wafers to be doped for use as junction devices. The principal contaminants on such wafers are oxygen and carbon. The new method comprises laser-irradiating the contaminated surface in a non-reactive atmosphere, using one or more of Q-switched laser pulses whose parameters are selected to effect melting of the surface without substantial vaporization thereof. In a typical application, a plurality of pulses is used to convert a surface region of an off-the-shelf silicon wafer to an atomically clean region. This can be accomplished in a system at a pressure below 10-/sup 8/ Torr, using Q-switched ruber-laser pulses having an energy density in the range of from about 60 to 190 MW/cm/sup 2/.

Method using laser irradiation for the production of atomically clean crystalline silicon and germanium surfaces

DOEpatents

Ownby, Gary W.; White, Clark W.; Zehner, David M.

1981-01-01

This invention relates to a new method for removing surface impurities from crystalline silicon or germanium articles, such as off-the-shelf p- or n-type wafers to be doped for use as junction devices. The principal contaminants on such wafers are oxygen and carbon. The new method comprises laser-irradiating the contaminated surface in a non-reactive atmosphere, using one or more of Q-switched laser pulses whose parameters are selected to effect melting of the surface without substantial vaporization thereof. In a typical application, a plurality of pulses is used to convert a surface region of an off-the-shelf silicon wafer to an automatically clean region. This can be accomplished in a system at a pressure below 10.sup.-8 Torr, using Q-switched ruby-laser pulses having an energy density in the range of from about 60 to 190 MW/cm.sup.2.

N-type nano-silicon powders with ultra-low electrical resistivity as anode materials in lithium ion batteries

NASA Astrophysics Data System (ADS)

Yue, Zhihao; Zhou, Lang; Jin, Chenxin; Xu, Guojun; Liu, Liekai; Tang, Hao; Li, Xiaomin; Sun, Fugen; Huang, Haibin; Yuan, Jiren

2017-06-01

N-type silicon wafers with electrical resistivity of 0.001 Ω cm were ball-milled to powders and part of them was further mechanically crushed by sand-milling to smaller particles of nano-size. Both the sand-milled and ball-milled silicon powders were, respectively, mixed with graphite powder (silicon:graphite = 5:95, weight ratio) as anode materials for lithium ion batteries. Electrochemical measurements, including cycle and rate tests, present that anode using sand-milled silicon powder performed much better. The first discharge capacity of sand-milled silicon anode is 549.7 mAh/g and it is still up to 420.4 mAh/g after 100 cycles. Besides, the D50 of sand-milled silicon powder shows ten times smaller in particle size than that of ball-milled silicon powder, and they are 276 nm and 2.6 μm, respectively. In addition, there exist some amorphous silicon components in the sand-milled silicon powder excepting the multi-crystalline silicon, which is very different from the ball-milled silicon powder made up of multi-crystalline silicon only.

New insight into the discharge mechanism of silicon-air batteries using electrochemical impedance spectroscopy.

PubMed

Cohn, Gil; Eichel, Rüdiger A; Ein-Eli, Yair

2013-03-07

The mechanism of discharge termination in silicon-air batteries, employing a silicon wafer anode, a room-temperature fluorohydrogenate ionic liquid electrolyte and an air cathode membrane, is investigated using a wide range of tools. EIS studies indicate that the interfacial impedance between the electrolyte and the silicon wafer increases upon continuous discharge. In addition, it is shown that the impedance of the air cathode-electrolyte interface is several orders of magnitude lower than that of the anode. Equivalent circuit fitting parameters indicate the difference in the anode-electrolyte interface characteristics for different types of silicon wafers. Evolution of porous silicon surfaces at the anode and their properties, by means of estimated circuit parameters, is also presented. Moreover, it is found that the silicon anode potential has the highest negative impact on the battery discharge voltage, while the air cathode potential is actually stable and invariable along the whole discharge period. The discharge capacity of the battery can be increased significantly by mechanically replacing the silicon anode.

Micromachined silicon electrostatic chuck

DOEpatents

Anderson, R.A.; Seager, C.H.

1996-12-10

An electrostatic chuck is faced with a patterned silicon plate, created by micromachining a silicon wafer, which is attached to a metallic base plate. Direct electrical contact between the chuck face (patterned silicon plate`s surface) and the silicon wafer it is intended to hold is prevented by a pattern of flat-topped silicon dioxide islands that protrude less than 5 micrometers from the otherwise flat surface of the chuck face. The islands may be formed in any shape. Islands may be about 10 micrometers in diameter or width and spaced about 100 micrometers apart. One or more concentric rings formed around the periphery of the area between the chuck face and wafer contain a low-pressure helium thermal-contact gas used to assist heat removal during plasma etching of a silicon wafer held by the chuck. The islands are tall enough and close enough together to prevent silicon-to-silicon electrical contact in the space between the islands, and the islands occupy only a small fraction of the total area of the chuck face, typically 0.5 to 5 percent. The pattern of the islands, together with at least one hole bored through the silicon veneer into the base plate, will provide sufficient gas-flow space to allow the distribution of the helium thermal-contact gas. 6 figs.

Micromachined silicon electrostatic chuck

DOEpatents

Anderson, Robert A.; Seager, Carleton H.

1996-01-01

An electrostatic chuck is faced with a patterned silicon plate 11, created y micromachining a silicon wafer, which is attached to a metallic base plate 13. Direct electrical contact between the chuck face 15 (patterned silicon plate's surface) and the silicon wafer 17 it is intended to hold is prevented by a pattern of flat-topped silicon dioxide islands 19 that protrude less than 5 micrometers from the otherwise flat surface of the chuck face 15. The islands 19 may be formed in any shape. Islands may be about 10 micrometers in diameter or width and spaced about 100 micrometers apart. One or more concentric rings formed around the periphery of the area between the chuck face 15 and wafer 17 contain a low-pressure helium thermal-contact gas used to assist heat removal during plasma etching of a silicon wafer held by the chuck. The islands 19 are tall enough and close enough together to prevent silicon-to-silicon electrical contact in the space between the islands, and the islands occupy only a small fraction of the total area of the chuck face 15, typically 0.5 to 5 percent. The pattern of the islands 19, together with at least one hole 12 bored through the silicon veneer into the base plate, will provide sufficient gas-flow space to allow the distribution of the helium thermal-contact gas.

Development of n+-in-p large-area silicon microstrip sensors for very high radiation environments - ATLAS12 design and initial results

NASA Astrophysics Data System (ADS)

Unno, Y.; Edwards, S. O.; Pyatt, S.; Thomas, J. P.; Wilson, J. A.; Kierstead, J.; Lynn, D.; Carter, J. R.; Hommels, L. B. A.; Robinson, D.; Bloch, I.; Gregor, I. M.; Tackmann, K.; Betancourt, C.; Jakobs, K.; Kuehn, S.; Mori, R.; Parzefall, U.; Wiik-Fucks, L.; Clark, A.; Ferrere, D.; Gonzalez Sevilla, S.; Ashby, J.; Blue, A.; Bates, R.; Buttar, C.; Doherty, F.; Eklund, L.; McMullen, T.; McEwan, F.; O`Shea, V.; Kamada, S.; Yamamura, K.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Nishimura, R.; Takashima, R.; Chilingarov, A.; Fox, H.; Affolder, A. A.; Allport, P. P.; Casse, G.; Dervan, P.; Forshaw, D.; Greenall, A.; Wonsak, S.; Wormald, M.; Cindro, V.; Kramberger, G.; Mandic, I.; Mikuz, M.; Gorelov, I.; Hoeferkamp, M.; Palni, P.; Seidel, S.; Taylor, A.; Toms, K.; Wang, R.; Hessey, N. P.; Valencic, N.; Arai, Y.; Hanagaki, K.; Dolezal, Z.; Kodys, P.; Bohm, J.; Mikestikova, M.; Bevan, A.; Beck, G.; Ely, S.; Fadeyev, V.; Galloway, Z.; Grillo, A. A.; Martinez-McKinney, F.; Ngo, J.; Parker, C.; Sadrozinski, H. F.-W.; Schumacher, D.; Seiden, A.; French, R.; Hodgson, P.; Marin-Reyes, H.; Parker, K.; Paganis, S.; Jinnouchi, O.; Motohashi, K.; Todome, K.; Yamaguchi, D.; Hara, K.; Hagihara, M.; Garcia, C.; Jimenez, J.; Lacasta, C.; Marti i Garcia, S.; Soldevila, U.

2014-11-01

We have been developing a novel radiation-tolerant n+-in-p silicon microstrip sensor for very high radiation environments, aiming for application in the high luminosity large hadron collider. The sensors are fabricated in 6 in., p-type, float-zone wafers, where large-area strip sensor designs are laid out together with a number of miniature sensors. Radiation tolerance has been studied with ATLAS07 sensors and with independent structures. The ATLAS07 design was developed into new ATLAS12 designs. The ATLAS12A large-area sensor is made towards an axial strip sensor and the ATLAS12M towards a stereo strip sensor. New features to the ATLAS12 sensors are two dicing lines: standard edge space of 910 μm and slim edge space of 450 μm, a gated punch-through protection structure, and connection of orphan strips in a triangular corner of stereo strips. We report the design of the ATLAS12 layouts and initial measurements of the leakage current after dicing and the resistivity of the wafers.

Forming electrical interconnections through semiconductor wafers

NASA Technical Reports Server (NTRS)

Anthony, T. R.

1981-01-01

An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

Tantalum oxide/silicon nitride: A negatively charged surface passivation stack for silicon solar cells

NASA Astrophysics Data System (ADS)

Wan, Yimao; Bullock, James; Cuevas, Andres

2015-05-01

This letter reports effective passivation of crystalline silicon (c-Si) surfaces by thermal atomic layer deposited tantalum oxide (Ta2O5) underneath plasma enhanced chemical vapour deposited silicon nitride (SiNx). Cross-sectional transmission electron microscopy imaging shows an approximately 2 nm thick interfacial layer between Ta2O5 and c-Si. Surface recombination velocities as low as 5.0 cm/s and 3.2 cm/s are attained on p-type 0.8 Ω.cm and n-type 1.0 Ω.cm c-Si wafers, respectively. Recombination current densities of 25 fA/cm2 and 68 fA/cm2 are measured on 150 Ω/sq boron-diffused p+ and 120 Ω/sq phosphorus-diffused n+ c-Si, respectively. Capacitance-voltage measurements reveal a negative fixed insulator charge density of -1.8 × 1012 cm-2 for the Ta2O5 film and -1.0 × 1012 cm-2 for the Ta2O5/SiNx stack. The Ta2O5/SiNx stack is demonstrated to be an excellent candidate for surface passivation of high efficiency silicon solar cells.

Microscopic Distributions of Defect Luminescence From Subgrain Boundaries in Multicrystalline Silicon Wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nguyen, Hieu T.; Jensen, Mallory A.; Li, Li

We investigate the microscopic distributions of sub-band-gap luminescence emission (the so-called D-lines D1/D2/D3/D4) and the band-to-band luminescence intensity, near recombination-active sub-grain boundaries in multicrystalline silicon wafers for solar cells. We find that the sub-band-gap luminescence from decorating defects/impurities (D1/D2) and from intrinsic dislocations (D3/D4) have distinctly different spatial distributions, and are asymmetric across the sub-grain boundaries. The presence of D1/D2 is correlated with a strong reduction in the band-to-band luminescence, indicating a higher recombination activity. In contrast, D3/D4 emissions are not strongly correlated with the band-to-band intensity. Based on spatially-resolved, synchrotron-based micro-X-ray fluorescence measurements of metal impurities, we confirm thatmore » high densities of metal impurities are present at locations with strong D1/D2 emission but low D3/D4 emission. Finally, we show that the observed asymmetry of the sub-band-gap luminescence across the sub-grain boundaries is due to their inclination below the wafer surface. Based on the luminescence asymmetries, the sub-grain boundaries are shown to share a common inclination locally, rather than be orientated randomly.« less

Preparation of wafer-level glass cavities by a low-cost chemical foaming process (CFP).

PubMed

Shang, Jintang; Chen, Boyin; Lin, Wei; Wong, Ching-Ping; Zhang, Di; Xu, Chao; Liu, Junwen; Huang, Qing-An

2011-04-21

A novel foaming process-chemical foaming process (CFP)-using foaming agents to fabricate wafer-level micro glass cavities including channels and bubbles was investigated. The process consists of the following steps sequentially: (1) shallow cavities were fabricated by a wet etching on a silicon wafer; (2) powders of a proper foaming agent were placed in a silicon cavity, named 'mother cavity', on the etched silicon surface; (3) the silicon cavities were sealed with a glass wafer by anodic bonding; (4) the bonded wafers were heated to above the softening point of the glass, and baked for several minutes, when the gas released by the decomposition of the foaming agent in the 'mother cavity' went into the other sealed interconnected silicon cavities to foam the softened glass into cylindrical channels named 'daughter channels', or spherical bubbles named 'son bubbles'. Results showed that wafer-level micro glass cavities with smooth wall surfaces were achieved successfully without contamination by the CFP. A model for the CFP was proposed to predict the final shape of the glass cavity. Experimental results corresponded with model predictions. The CFP provides a low-cost avenue to preparation of micro glass cavities of high quality for applications such as micro-reactors, micro total analysis systems (μTAS), analytical and bio-analytical applications, and MEMS packaging.

Effect of electroless etching parameters on the growth and reflection properties of silicon nanowires.

PubMed

Ozdemir, Baris; Kulakci, Mustafa; Turan, Rasit; Unalan, Husnu Emrah

2011-04-15

Vertically aligned silicon nanowire (Si NW) arrays have been fabricated over large areas using an electroless etching (EE) method, which involves etching of silicon wafers in a silver nitrate and hydrofluoric acid based solution. A detailed parametric study determining the relationship between nanowire morphology and time, temperature, solution concentration and starting wafer characteristics (doping type, resistivity, crystallographic orientation) is presented. The as-fabricated Si NW arrays were analyzed by field emission scanning electron microscope (FE-SEM) and a linear dependency of nanowire length to both temperature and time was obtained and the change in the growth rate of Si NWs at increased etching durations was shown. Furthermore, the effects of EE parameters on the optical reflectivity of the Si NWs were investigated in this study. Reflectivity measurements show that the 42.8% reflectivity of the starting silicon wafer drops to 1.3%, recorded for 10 µm long Si NW arrays. The remarkable decrease in optical reflectivity indicates that Si NWs have a great potential to be utilized in radial or coaxial p-n heterojunction solar cells that could provide orthogonal photon absorption and enhanced carrier collection.

Effect of electroless etching parameters on the growth and reflection properties of silicon nanowires

NASA Astrophysics Data System (ADS)

Ozdemir, Baris; Kulakci, Mustafa; Turan, Rasit; Emrah Unalan, Husnu

2011-04-01

Vertically aligned silicon nanowire (Si NW) arrays have been fabricated over large areas using an electroless etching (EE) method, which involves etching of silicon wafers in a silver nitrate and hydrofluoric acid based solution. A detailed parametric study determining the relationship between nanowire morphology and time, temperature, solution concentration and starting wafer characteristics (doping type, resistivity, crystallographic orientation) is presented. The as-fabricated Si NW arrays were analyzed by field emission scanning electron microscope (FE-SEM) and a linear dependency of nanowire length to both temperature and time was obtained and the change in the growth rate of Si NWs at increased etching durations was shown. Furthermore, the effects of EE parameters on the optical reflectivity of the Si NWs were investigated in this study. Reflectivity measurements show that the 42.8% reflectivity of the starting silicon wafer drops to 1.3%, recorded for 10 µm long Si NW arrays. The remarkable decrease in optical reflectivity indicates that Si NWs have a great potential to be utilized in radial or coaxial p-n heterojunction solar cells that could provide orthogonal photon absorption and enhanced carrier collection.

Disposable attenuated total reflection-infrared crystals from silicon wafer: a versatile approach to surface infrared spectroscopy.

PubMed

Karabudak, Engin; Kas, Recep; Ogieglo, Wojciech; Rafieian, Damon; Schlautmann, Stefan; Lammertink, R G H; Gardeniers, Han J G E; Mul, Guido

2013-01-02

Attenuated total reflection-infrared (ATR-IR) spectroscopy is increasingly used to characterize solids and liquids as well as (catalytic) chemical conversion. Here we demonstrate that a piece of silicon wafer cut by a dicing machine or cleaved manually can be used as disposable internal reflection element (IRE) without the need for polishing and laborious edge preparation. Technical aspects, fundamental differences, and pros and cons of these novel disposable IREs and commercial IREs are discussed. The use of a crystal (the Si wafer) in a disposable manner enables simultaneous preparation and analysis of substrates and application of ATR spectroscopy in high temperature processes that may lead to irreversible interaction between the crystal and the substrate. As representative application examples, the disposable IREs were used to study high temperature thermal decomposition and chemical changes of polyvinyl alcohol (PVA) in a titania (TiO(2)) matrix and assemblies of 65-450 nm thick polystyrene (PS) films.

Diffusion lengths in irradiated N/P InP-on-Si solar cells

NASA Technical Reports Server (NTRS)

Wojtczuk, Steven; Colerico, Claudia; Summers, Geoffrey P.; Walters, Robert J.; Burke, Edward A.

1995-01-01

Indium phosphide (InP) solar cells are being made on silicon (Si) wafers (InP/Si) to take advantage of both the radiation-hardness properties of the InP solar cell and the light weight and low cost of Si wafers compared to InP or germanium (Ge) wafers. The InP/Si cell application is for long duration and/or high radiation orbit space missions. InP/Si cells have higher absolute efficiency after a high radiation dose than gallium arsenide (GaAs) or silicon (Si) solar cells. In this work, base electron diffusion lengths in the N/P cell are extracted from measured AM0 short-circuit photocurrent at various irradiation levels out to an equivalent 1 MeV fluence of 1017 1 MeV electrons/sq cm for a 1 sq cm 12% BOL InP/Si cell. These values are then checked for consistency by comparing measured Voc data with a theoretical Voc model that includes a dark current term that depends on the extracted diffusion lengths.

The influence of flash lamp annealing on the minority carrier lifetime of Czochralski silicon wafers

NASA Astrophysics Data System (ADS)

Kissinger, G.; Kot, D.; Sattler, A.

2014-02-01

Flash lamp annealing of moderately B-doped CZ silicon wafers for 20 ms with a normalized irradiance of about 0.9 was used to efficiently suppress oxygen precipitation during subsequent thermal processing. In this way, the minority carrier lifetime measured at high injection level by microwave-detected photo-conductance decay (μ-PCD) was increased from about 30 microseconds to about 300 microseconds after a thermal process consisting of 780 °C 3 h + 1000 °C 16 h. The grown-in oxide precipitate nuclei were shrunken to a subcritical size during the flash lamp anneal which prevents further growth during subsequent thermal processing.

1366 Project Silicon: Reclaiming US Silicon PV Leadership

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lorenz, Adam

1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling ofmore » 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. Sun

Robustness up to 400°C of the passivation of c-Si by p-type a-Si:H thanks to ion implantation

NASA Astrophysics Data System (ADS)

Defresne, A.; Plantevin, O.; Roca i Cabarrocas, Pere

2016-12-01

Heterojunction solar cells based on crystalline silicon (c-Si) passivated by hydrogenated amorphous silicon (a-Si:H) thin films are one of the most promising architectures for high energy conversion efficiency. Indeed, a-Si:H thin films can passivate both p-type and n-type wafers and can be deposited at low temperature (<200°C) using PECVD. However, such passivation layers, in particular p-type a-Si:H, show a dramatic degradation in passivation quality above 200°C. Yet, annealing at 300 - 400°C the TCO layer and metallic contacts is highly desirable to reduce the contact resistance as well as the TCO optical absorption. In this work, we show that as expected, ion implantation (5 - 30 keV) introduces defects at the c-Si/a-Si:H interface which strongly degrade the effective lifetime, down to a few micro-seconds. However, the passivation quality can be restored and lifetime values can be improved up to 2 ms over the initial value with annealing. We show here that effective lifetimes above 1 ms can be maintained up to 380°C, opening up the possibility for higher process temperatures in silicon heterojunction device fabrication.

Tripodal penta(p-phenylene) for the biofunctionalization of alkynyl-modified silicon surfaces

NASA Astrophysics Data System (ADS)

Sánchez-Molina, María; Díaz, Amelia; Valpuesta, María; Contreras-Cáceres, Rafael; López-Romero, J. Manuel; López-Ramírez, M. Rosa

2018-07-01

Here we report the optimization on the covalent grafting methodology of a tripod-shaped penta(p-phenylene), 1, on alkynyl-terminated silicon surfaces, and the incorporation of an active theophylline derivative, 2, for the specific immobilization of proteins. The tripodal molecule presents azide-terminal groups to be attached onto a silicon surface containing an alkynyl monolayer. Initially, compound 1 has been covalently incorporated on alkynyl-terminated Si wafers, by the copper catalyzed alkyne-azide 1,3-dipolar cycloaddition (CuAAC, a click reaction). The tripod density on the silicon surface is tuned by performing the CuAAC reaction at different concentrations of 1, as well as under different experimental conditions (T, base, copper source, shaking). Then, tripod 1-modified surface has also been biofunctionalized with 2. The effective preparation of this silicon-modified surface allowed us to study the streptavidin immobilization on the surface. Characterization of the different surfaces has been carried out by X-ray Photoelectron Spectroscopy (XPS), Atomic Force Microscopy (AFM) and Bright-Field Optical Transmission Microscopy (Confocal) techniques. We also include density functional theory (DFT) analysis of the organic structures to confirm the height-profile and the tripod-surface relative configuration extracted from AFM images.

Characterization of perovskite layer on various nanostructured silicon wafer

NASA Astrophysics Data System (ADS)

Rostan, Nur Fairuz Mohd; Sepeai, Suhaila; Ramli, Noor Fadhilah; Azhari, Ayu Wazira; Ludin, Norasikin Ahmad; Teridi, Mohd Asri Mat; Ibrahim, Mohd Adib; Zaidi, Saleem H.

2017-05-01

Crystalline silicon (c-Si) solar cell dominates 90% of photovoltaic (PV) market. The c-Si is the most mature of all PV technologies and expected to remain leading the PV technology by 2050. The attractive characters of Si solar cell are stability, long lasting and higher lifetime. Presently, the efficiency of c-Si solar cell is still stuck at 25% for one and half decades. Tandem approach is one of the attempts to improve the Si solar cell efficiency with higher bandgap layer is stacked on top of Si bottom cell. Perovskite offers a big potential to be inserted into a tandem solar cell. Perovskite with bandgap of 1.6 to 1.9 eV will be able to absorb high energy photons, meanwhile c-Si with bandgap of 1.124 eV will absorb low energy photons. The high carrier mobility, high carrier lifetime, highly compatible with both solution and evaporation techniques makes perovskite an eligible candidate for perovskite-Si tandem configuration. The solution of methyl ammonium lead iodide (MAPbI3) was prepared by single step precursor process. The perovskite layer was deposited on different c-Si surface structure, namely planar, textured and Si nanowires (SiNWs) by using spin-coating technique at different rotation speeds. The nanostructure of Si surface was textured using alkaline based wet chemical etching process and SiNW was grown using metal assisted etching technique. The detailed surface morphology and absorbance of perovskite were studied in this paper. The results show that the thicknesses of MAPbI3 were reduced with the increasing of rotation speed. In addition, the perovskite layer deposited on the nanostructured Si wafer became rougher as the etching time and rotation speed increased. The average surface roughness increased from ˜24 nm to ˜38 nm for etching time range between 5-60 min at constant low rotation speed (2000 rpm) for SiNWs Si wafer.

Slicing of silicon into sheet material: Silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project

NASA Technical Reports Server (NTRS)

Holden, S. C.

1976-01-01

Multiblade slurry sawing is used to slice 10 cm diameter silicon ingots into wafers 0.024 cm thick using 0.050 cm of silicon per slice (0.026 cm kerf loss). Total slicing time is less than twenty hours, and 143 slices are produced simultaneously. Productivity (slice area per hour per blade) is shown as a function or blade load and thickness, and abrasive size. Finer abrasive slurries cause a reduction in slice productivity, and thin blades cause a reduction of wafer accuracy. Sawing induced surface damage is found to extend 18 microns into the wafer.

Noncontact Measurement of Doping Profile for Bare Silicon

NASA Astrophysics Data System (ADS)

Kohno, Motohiro; Matsubara, Hideaki; Okada, Hiroshi; Hirae, Sadao; Sakai, Takamasa

1998-10-01

In this study, we evaluate the doping concentrations of bare silicon wafers by noncontact capacitance voltage (C V) measurements. The metal-air-insulator-semiconductor (MAIS) method enables the measurement of C V characteristics of silicon wafers without oxidation and electrode preparation. This method has the advantage that a doping profile close to the wafer surface can be obtained. In our experiment, epitaxial silicon wafers were used to compare the MAIS method with the conventional MIS method. The experimental results obtained from the two methods showed good agreement. Then, doping profiles of boron-doped Czochralski (CZ) wafers were measured by the MAIS method. The result indicated a significant reduction of the doping concentration near the wafer surface. This observation is attributed to the well-known deactivation of boron with atomic hydrogen which permeated the silicon bulk during the polishing process. This deactivation was recovered by annealing in air at 180°C for 120 min.

Improvement of silicon solar cell efficiency by ion beam sputtered deposition of AlOxNy thin films.

PubMed

Chen, Sheng-Hui; Hsu, Chun-Che; Wang, Hsuan-Wen; Yeh, Chi-Li; Tseng, Shao-Ze; Lin, Hung-Ju; Lee, Cheng-Chung; Peng, Cheng-Yu

2011-03-20

Negative charge material, AlOxNy, has been fabricated to passivate the surface of p-type silicon. The fabrication of AlOxNy was possible by using ion beam sputtering deposition to deposit AlN thin film on the surface of a p-type silicon wafer and following annealing in oxygen ambient. Capacitance-voltage analysis shows the fixed charge density has increased from 10(11) cm(-2) to 2.26×10(12) cm(-2) after annealing. The solar cell efficiency increased from 15.9% to 17.3%, which is also equivalent to the reduction of surface recombination velocity from 1×10(5)  to 32 cm/s.

Ultrafast-laser dicing of thin silicon wafers: strategies to improve front- and backside breaking strength

NASA Astrophysics Data System (ADS)

Domke, Matthias; Egle, Bernadette; Stroj, Sandra; Bodea, Marius; Schwarz, Elisabeth; Fasching, Gernot

2017-12-01

Thin 50-µm silicon wafers are used to improve heat dissipation of chips with high power densities. However, mechanical dicing methods cause chipping at the edges of the separated dies that reduce the mechanical stability. Thermal load changes may then lead to sudden chip failure. Recent investigations showed that the mechanical stability of the cut chips could be increased using ultrashort-pulsed lasers, but only at the laser entrance (front) side and not at the exit (back) side. The goal of this study was to find strategies to improve both front- and backside breaking strength of chips that were cut out of an 8″ wafer with power metallization using an ultrafast laser. In a first experiment, chips were cut by scanning the laser beam in single lines across the wafer using varying fluencies and scan speeds. Three-point bending tests of the cut chips were performed to measure front and backside breaking strengths. The results showed that the breaking strength of both sides increased with decreasing accumulated fluence per scan. Maximum breaking strengths of about 1100 MPa were achieved at the front side, but only below 600 MPa were measured for the backside. A second experiment was carried out to optimize the backside breaking strength. Here, parallel line scans to increase the distance between separated dies and step cuts to minimize the effect of decreasing fluence during scribing were performed. Bending tests revealed that breaking strengths of about 1100 MPa could be achieved also on the backside using the step cut. A reason for the superior performance could be found by calculating the fluence absorbed by the sidewalls. The calculations suggested that an optimal fluence level to minimize thermal side effects and periodic surface structures was achieved due to the step cut. Remarkably, the best breaking strengths values achieved in this study were even higher than the values obtained on state of the art ns-laser and mechanical dicing machines. This is the first

Characterization of Ag-porous silicon nanostructured layer formed by an electrochemical etching of p-type silicon surface for bio-application

NASA Astrophysics Data System (ADS)

Naddaf, M.; Al-Mariri, A.; Haj-Mhmoud, N.

2017-06-01

Nanostructured layers composed of silver-porous silicon (Ag-PS) have been formed by an electrochemical etching of p-type (1 1 1) silicon substrate in a AgNO3:HF:C2H5OH solution at different etching times (10 min-30 min). Scanning electron microscopy (SEM) and energy-dispersive x-ray spectroscopy (EDS) results reveal that the produced layers consist of Ag dendrites and a silicon-rich porous structure. The nanostructuring nature of the layer has been confirmed by spatial micro-Raman scattering and x-ray diffraction techniques. The Ag dendrites exhibit a surface-enhanced Raman scattering (SERS) spectrum, while the porous structure shows a typical PS Raman spectrum. Upon increasing the etching time, the average size of silicon nanocrystallite in the PS network decreases, while the average size of Ag nanocrystals is slightly affected. In addition, the immobilization of prokaryote Salmonella typhimurium DNA via physical adsorption onto the Ag-PS layer has been performed to demonstrate its efficiency as a platform for detection of biological molecules using SERS.

An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

NASA Astrophysics Data System (ADS)

Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

2017-06-01

Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

Carrier transport and sensitivity issues in heterojunction with intrinsic thin layer solar cells on N-type crystalline silicon: A computer simulation study

NASA Astrophysics Data System (ADS)

Rahmouni, M.; Datta, A.; Chatterjee, P.; Damon-Lacoste, J.; Ballif, C.; Roca i Cabarrocas, P.

2010-03-01

Heterojunction with intrinsic thin layer or "HIT" solar cells are considered favorable for large-scale manufacturing of solar modules, as they combine the high efficiency of crystalline silicon (c-Si) solar cells, with the low cost of amorphous silicon technology. In this article, based on experimental data published by Sanyo, we simulate the performance of a series of HIT cells on N-type crystalline silicon substrates with hydrogenated amorphous silicon (a-Si:H) emitter layers, to gain insight into carrier transport and the general functioning of these devices. Both single and double HIT structures are modeled, beginning with the initial Sanyo cells having low open circuit voltages but high fill factors, right up to double HIT cells exhibiting record values for both parameters. The one-dimensional numerical modeling program "Amorphous Semiconductor Device Modeling Program" has been used for this purpose. We show that the simulations can correctly reproduce the electrical characteristics and temperature dependence for a set of devices with varying I-layer thickness. Under standard AM1.5 illumination, we show that the transport is dominated by the diffusion mechanism, similar to conventional P/N homojunction solar cells, and tunneling is not required to describe the performance of state-of-the art devices. Also modeling has been used to study the sensitivity of N-c-Si HIT solar cell performance to various parameters. We find that the solar cell output is particularly sensitive to the defect states on the surface of the c-Si wafer facing the emitter, to the indium tin oxide/P-a-Si:H front contact barrier height and to the band gap and activation energy of the P-a-Si:H emitter, while the I-a-Si:H layer is necessary to achieve both high Voc and fill factor, as it passivates the defects on the surface of the c-Si wafer. Finally, we describe in detail for most parameters how they affect current transport and cell properties.

Design, modeling, and fabrication of crab-shape capacitive microphone using silicon-on-isolator wafer

NASA Astrophysics Data System (ADS)

Ganji, Bahram Azizollah; Sedaghat, Sedighe Babaei; Roncaglia, Alberto; Belsito, Luca; Ansari, Reza

2018-01-01

This paper presents design, modeling, and fabrication of a crab-shape microphone using silicon-on-isolator (SOI) wafer. SOI wafer is used to prevent the additional deposition of sacrificial and diaphragm layers. The holes have been made on diaphragm to prevent back plate etching. Dry etching is used for removing the sacrificial layer, because wet etching causes adhesion between the diaphragm and the back plate. Crab legs around the perforated diaphragm allow for improving the microphone performance and reducing the mechanical stiffness and air damping of the microphone. In this structure, the supply voltage is decreased due to the uniform deflection of the diaphragm due to the designed low-K (spring constant) structure. An analytical model of the structure for description of microphone behavior is presented. The proposed method for estimating the basic parameters of the microphone is based on the calculation of the spring constant using the energy method. The microphone is fabricated using only one mask to pattern the crab-shape diaphragm, resulting in a low-cost and easy fabrication process. The diaphragm size is 0.3 mm×0.3 mm, which is smaller than the conventional microelectromechanical systems capacitive microphone. The results show that the analytical equations have a good agreement with measurement results. The device has the pull-in voltage of 14.3 V, a resonant frequency of 90 kHz, an open-circuit sensitivity of 1.33 mV/Pa under bias voltage of 5 V. Comparing with previous works, this microphone has several advantages: SOI wafer decreases the fabrication process steps, the microphone is smaller than the previous works, and crab-shape diaphragm improves the microphone performances.

Thinning of PLZT ceramic wafers for sensor integration

NASA Astrophysics Data System (ADS)

Jin, Na; Liu, Weiguo

2010-08-01

Characteristics of transparent PLZT ceramics can be tailored by controlling the component of them, and therefore showed excellent dielectric, piezoelectric, pyroelectric and ferroelectric properties. To integrate the ceramics with microelectronic circuit to realize integrated applications, the ceramic wafers have to be thinned down to micrometer scale in thickness. A7/65/35 PLZT ceramic wafer was selected in this study for the thinning process. Size of the wafer was 10×10mm with an initial thickness of 300μm. A novel membrane transfer process (MTP) was developed for the thinning and integration of the ceramic wafers. In the MTP process, the ceramic wafer was bonded to silicon wafer using a polymer bonding method. Mechanical grinding method was applied to reduce the thickness of the ceramic. To minimize the surface damage in the ceramic wafer caused by the mechanical grinding, magnetorheological finishing (MRF) method was utilized to polish the wafer. White light interference (WLI) apparatus was used to monitor the surface qualities of the grinded and ploished ceramic wafers. For the PLZT membrane obtained from the MTP process, the final thickness of the thinned and polished wafer was 10μm, the surface roughness was below 1nm in rms, and the flatness was better than λ/5.

Silicon sample holder for molecular beam epitaxy on pre-fabricated integrated circuits

NASA Technical Reports Server (NTRS)

Hoenk, Michael E. (Inventor); Grunthaner, Paula J. (Inventor); Grunthaner, Frank J. (Inventor)

1994-01-01

The sample holder of the invention is formed of the same semiconductor crystal as the integrated circuit on which the molecular beam expitaxial process is to be performed. In the preferred embodiment, the sample holder comprises three stacked micro-machined silicon wafers: a silicon base wafer having a square micro-machined center opening corresponding in size and shape to the active area of a CCD imager chip, a silicon center wafer micro-machined as an annulus having radially inwardly pointing fingers whose ends abut the edges of and center the CCD imager chip within the annulus, and a silicon top wafer micro-machined as an annulus having cantilevered membranes which extend over the top of the CCD imager chip. The micro-machined silicon wafers are stacked in the order given above with the CCD imager chip centered in the center wafer and sandwiched between the base and top wafers. The thickness of the center wafer is about 20% less than the thickness of the CCD imager chip. Preferably, four titanium wires, each grasping the edges of the top and base wafers, compress all three wafers together, flexing the cantilever fingers of the top wafer to accommodate the thickness of the CCD imager chip, acting as a spring holding the CCD imager chip in place.

Porosity and thickness effect of porous silicon layer on photoluminescence spectra

NASA Astrophysics Data System (ADS)

Husairi, F. S.; Eswar, K. A.; Guliling, Muliyadi; Khusaimi, Z.; Rusop, M.; Abdullah, S.

2018-05-01

The porous silicon nanostructures was prepared by electrochemical etching of p-type silicon wafer. Porous silicon prepared by using different current density and fix etching time with assistance of halogen lamp. The physical structure of porous silicon measured by the parameters used which know as experimental factor. In this work, we select one of those factors to correlate which optical properties of porous silicon. We investigated the surface morphology by using Surface Profiler (SP) and photoluminescence using Photoluminescence (PL) spectrometer. Different physical characteristics of porous silicon produced when current density varied. Surface profiler used to measure the thickness of porous and the porosity calculated using mass different of silicon. Photoluminescence characteristics of porous silicon depend on their morphology because the size and distribution of pore its self will effect to their exciton energy level. At J=30 mA/cm2 the shorter wavelength produced and it followed the trend of porosity with current density applied.

Influence of fluids on the abrasion of silicon by diamond

NASA Technical Reports Server (NTRS)

Danyluk, S.

1982-01-01

Silicon wafers ((100)-p-type) were abraded at room temperature in acetone, absolute ethanol and water by a pyramid diamond and the resulting groove depth was measured as a function of normal force on the diamond and the absorbed fluids, while all other experimental conditions were held constant. The groove depth rates are in the ratio of 1:2:3 for water, absolute ethanol, and acetone, respectively, for a constant normal force. The groove depth rate is lower when the normal force is decreased. The silicon abraded in the presence of water was chipped as expected for a classical brittle material while the surfaces abraded in the other two fluids showed ductile ploughing as the main mechanism for silicon removal.

Slicing of Silicon into Sheet Material. Silicon Sheet Growth Development for the Large Area Silicon Sheet Task of the Low Cost Solar Array Project

NASA Technical Reports Server (NTRS)

Fleming, J. R.; Holden, S. C.; Wolfson, R. G.

1979-01-01

The use of multiblade slurry sawing to produce silicon wafers from ingots was investigated. The commercially available state of the art process was improved by 20% in terms of area of silicon wafers produced from an ingot. The process was improved 34% on an experimental basis. Economic analyses presented show that further improvements are necessary to approach the desired wafer costs, mostly reduction in expendable materials costs. Tests which indicate that such reduction is possible are included, although demonstration of such reduction was not completed. A new, large capacity saw was designed and tested. Performance comparable with current equipment (in terms of number of wafers/cm) was demonstrated.

Dehydration and dehydroxylation of C-S-H phases synthesized on silicon wafers

NASA Astrophysics Data System (ADS)

Giraudo, Nicolas; Bergdolt, Samuel; Laye, Fabrice; Krolla, Peter; Lahann, Joerg; Thissen, Peter

2018-03-01

In this work, the synthesis of specific ultrathin Calcium-Silicate-Hydrate (C-S-H) phases on silicon wafers and their transformation into C-S phases is achieved. Specific mineral phases are identified, and the synthesis is successful controlled. Samples are investigated by means of Fourier Transform Infrared (FTIR) spectroscopy and X-ray Diffraction (XRD) and the results are analyzed based on first-principles calculations. When C-S-H phases are transformed into C-S phases, only a few reflexes are detected on XRD, and the coherent scattering domains decrease with the increment of the temperature and time of exposure. This behavior is explained by the Ca/Si changes, which are identified by changes in the FTIR spectra. A thermodynamic analysis is performed with the help of first-principles calculations to underline the influence of the calcium-to-silicon (Ca/Si) ratio in the process of dehydroxylation. To increase the Ca/Si ratio water is partially substituted by methanol at the synthesis. This is observed in the FTIR spectra and is confirmed by lower temperatures of dehydroxylation. The catalytic nature of calcium towards the dehydroxylation is confirmed. The core of this work lies in the preparation of a model, which perfection makes possible to model reactivity, stability and mechanical properties using first-principles calculations, and is the starting point for the synthesis of many others.

Microwave characterization of slotline on high resistivity silicon for antenna feed network

NASA Technical Reports Server (NTRS)

Simons, Rainee N.; Taub, Susan R.; Lee, Richard Q.; Young, Paul G.

1993-01-01

Conventional silicon wafers have low resistivity and consequently unacceptably high value of dielectric attenuation constant. Microwave circuits for phased array antenna systems fabricated on these wafers therefore have low efficiency. By choosing a silicon substrate with sufficiently high resistivity it is possible to make the dielectric attenuation constant of the interconnecting microwave transmission lines approach those of GaAs or InP. In order for this to be possible, the transmission lines must be characterized. In this presentation, the effective dielectric constant (epsilon sub eff) and attenuation constant (alpha) of a slotline on high resistivity (5000 to 10 000 ohm-cm) silicon wafer will be discussed. The epsilon sub eff and alpha are determined from the measured resonant frequencies and the corresponding insertion loss of a slotline ring resonator. The results for slotline will be compared with microstrip line and coplanar waveguide.

SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution

NASA Astrophysics Data System (ADS)

Voorkamp, R.; Verschuuren, M. A.; van Brakel, R.

2016-10-01

Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 - 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and

Passivated p-type silicon: Hole injection tunable anode material for organic light emission

NASA Astrophysics Data System (ADS)

Zhao, W. Q.; Ran, G. Z.; Xu, W. J.; Qin, G. G.

2008-02-01

We find that hole injection can be enhanced simply by selecting a lower-resistivity p-Si anode to match an electron injection enhancement for organic light emitting diodes with ultrathin-SiO2-layer-passivated p-Si anode (Si-OLED). For a Si-OLED with ordinary AlQ electron transport layer, the optimized resistivity of the p-Si anode is 40Ωcm; for that with n-doped Bphen electron transport layer, it decreases to 5Ωcm. Correspondingly, the maximum power efficiency increases from 0.3to1.9lm /W, even higher than that of an indium tin oxide control device (1.4lm/W). This passivated p-type silicon is a hole injection tunable anode material for OLED.

Combination of grazing incidence x-ray fluorescence with x-ray reflectivity in one table-top spectrometer for improved characterization of thin layer and implants on/in silicon wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ingerle, D.; Schiebl, M.; Streli, C.

2014-08-15

As Grazing Incidence X-ray Fluorescence (GIXRF) analysis does not provide unambiguous results for the characterization of nanometre layers as well as nanometre depth profiles of implants in silicon wafers by its own, the approach of providing additional information using the signal from X-ray Reflectivity (XRR) was tested. As GIXRF already uses an X-ray beam impinging under grazing incidence and the variation of the angle of incidence, a GIXRF spectrometer was adapted with an XRR unit to obtain data from the angle dependent fluorescence radiation as well as data from the reflected beam. A θ-2θ goniometer was simulated by combining amore » translation and tilt movement of a Silicon Drift detector, which allows detecting the reflected beam over 5 orders of magnitude. HfO{sub 2} layers as well as As implants in Silicon wafers in the nanometre range were characterized using this new setup. A just recently published combined evaluation approach was used for data evaluation.« less

Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

NASA Astrophysics Data System (ADS)

Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

2014-10-01

The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

Investigation of Defects Origin in p-Type Si for Solar Applications

NASA Astrophysics Data System (ADS)

Gwóźdź, Katarzyna; Placzek-Popko, Ewa; Mikosza, Maciej; Zielony, Eunika; Pietruszka, Rafal; Kopalko, Krzysztof; Godlewski, Marek

2017-07-01

In order to improve the efficiency of a solar cell based on silicon, one must find a compromise between its price and crystalline quality. That is precisely why the knowledge of defects present in the material is of primary importance. This paper studies the defects in commercially available cheap Schottky titanium/gold silicon wafers. The electrical properties of the diodes were defined by using current-voltage and capacitance-voltage measurements. Low series resistance and ideality factor are proofs of the good quality of the sample. The concentration of the acceptors is in accordance with the manufacturer's specifications. Deep level transient spectroscopy measurements were used to identify the defects. Three hole traps were found with activation energies equal to 0.093 eV, 0.379 eV, and 0.535 eV. Comparing the values with the available literature, the defects were determined as connected to the presence of iron interstitials in the silicon. The quality of the silicon wafer seems good enough to use it as a substrate for the solar cell heterojunctions.

Doping of silicon by carbon during laser ablation process

NASA Astrophysics Data System (ADS)

Raciukaitis, G.; Brikas, M.; Kazlauskiene, V.; Miskinis, J.

2007-04-01

Effect of laser ablation on properties of remaining material was investigated in silicon. It was established that laser cutting of wafers in air induced doping of silicon by carbon. The effect was found to be more distinct by the use of higher laser power or UV radiation. Carbon ions created bonds with silicon in the depth of silicon. Formation of the silicon carbide type bonds was confirmed by SIMS, XPS and AES measurements. Modeling of the carbon diffusion was performed to clarify its depth profile in silicon. Photo-chemical reactions of such type changed the structure of material and could be a reason for the reduced quality of machining. A controlled atmosphere was applied to prevent carbonization of silicon during laser cutting.

Passivation mechanism in silicon heterojunction solar cells with intrinsic hydrogenated amorphous silicon oxide layers

NASA Astrophysics Data System (ADS)

Deligiannis, Dimitrios; van Vliet, Jeroen; Vasudevan, Ravi; van Swaaij, René A. C. M. M.; Zeman, Miro

2017-02-01

In this work, we use intrinsic hydrogenated amorphous silicon oxide layers (a-SiOx:H) with varying oxygen content (cO) but similar hydrogen content to passivate the crystalline silicon wafers. Using our deposition conditions, we obtain an effective lifetime (τeff) above 5 ms for cO ≤ 6 at. % for passivation layers with a thickness of 36 ± 2 nm. We subsequently reduce the thickness of the layers using an accurate wet etching method to ˜7 nm and deposit p- and n-type doped layers fabricating a device structure. After the deposition of the doped layers, τeff appears to be predominantly determined by the doped layers themselves and is less dependent on the cO of the a-SiOx:H layers. The results suggest that τeff is determined by the field-effect rather than by chemical passivation.

Reticle variation influence on manufacturing line and wafer device performance

NASA Astrophysics Data System (ADS)

Nistler, John L.; Spurlock, Kyle

1994-01-01

Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

Etching Selectivity of Cr, Fe and Ni Masks on Si & SiO2 Wafers

NASA Astrophysics Data System (ADS)

Garcia, Jorge; Lowndes, Douglas H.

2000-10-01

During this Summer 2000 I joined the Semiconductors and Thin Films group led by Dr. Douglas H. Lowndes at Oak Ridge National Laboratory’s Solid State Division. Our objective was to evaluate the selectivity that Trifluoromethane (CHF3), and Sulfur Hexafluoride (SF6) plasmas have for Si, SiO2 wafers and the Ni, Cr, and Fe masks; being this etching selectivity the ratio of the etching rates of the plasmas for each of the materials. We made use of Silicon and Silicon Dioxide-coated wafers that have Fe, Cr or Ni masks. In the semiconductor field, metal layers are often used as masks to protect layers underneath during processing steps; when these wafers are taken to the dry etching process, both the wafer and the mask layers’ thickness are reduced.

Enhancing the far-UV sensitivity of silicon CMOS imaging arrays

NASA Astrophysics Data System (ADS)

Retherford, K. D.; Bai, Yibin; Ryu, Kevin K.; Gregory, J. A.; Welander, Paul B.; Davis, Michael W.; Greathouse, Thomas K.; Winter, Gregory S.; Suntharalingam, Vyshnavi; Beletic, James W.

2014-07-01

We report our progress toward optimizing backside-illuminated silicon PIN CMOS devices developed by Teledyne Imaging Sensors (TIS) for far-UV planetary science applications. This project was motivated by initial measurements at Southwest Research Institute (SwRI) of the far-UV responsivity of backside-illuminated silicon PIN photodiode test structures described in Bai et al., SPIE, 2008, which revealed a promising QE in the 100-200 nm range as reported in Davis et al., SPIE, 2012. Our effort to advance the capabilities of thinned silicon wafers capitalizes on recent innovations in molecular beam epitaxy (MBE) doping processes. Key achievements to date include: 1) Representative silicon test wafers were fabricated by TIS, and set up for MBE processing at MIT Lincoln Laboratory (LL); 2) Preliminary far-UV detector QE simulation runs were completed to aid MBE layer design; 3) Detector fabrication was completed through the pre-MBE step; and 4) Initial testing of the MBE doping process was performed on monitoring wafers, with detailed quality assessments. Early results suggest that potential challenges in optimizing the UV-sensitivity of silicon PIN type CMOS devices, compared with similar UV enhancement methods established for CCDs, have been mitigated through our newly developed methods. We will discuss the potential advantages of our approach and briefly describe future development steps.

Investigation of MeV-Cu implantation and channeling effects into porous silicon formation

NASA Astrophysics Data System (ADS)

Ahmad, M.; Naddaf, M.

2011-11-01

P-type (1 1 1) silicon wafers were implanted by copper ions (2.5 MeV) in channeling and random directions using ion beam accelerator of the Atomic Energy Commission of Syria (AECS). The effect of implantation direction on formation process of porous silicon (PS) using electrochemical etching method has been investigated using scanning electron microscope (SEM) and photoluminescence (PL) techniques. SEM observations revealed that the size, shape and density of the formed pores are highly affected by the direction of beam implantation. This in turn is seen to influence the PL behavior of the PS.

Metallization of Large Silicon Wafers

NASA Technical Reports Server (NTRS)

Pryor, R. A.

1978-01-01

A metallization scheme was developed which allows selective plating of silicon solar cell surfaces. The system is comprised of three layers. Palladium, through the formation of palladium silicide at 300 C in nitrogen, makes ohmic contact to the silicon surface. Nickel, plated on top of the palladium silicide layer, forms a solderable interface. Lead-tin solder on the nickel provides conductivity and allows a convenient means for interconnection of cells. To apply this metallization, three chemical plating baths are employed.

Hybrid Integrated Platforms for Silicon Photonics

PubMed Central

Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

2010-01-01

A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

Silicon micro-mold and method for fabrication

DOEpatents

Morales, Alfredo M.

2005-01-11

The present invention describes a method for rapidly fabricating a robust 3-dimensional silicon micro-mold for use in preparing complex metal micro-components. The process begins by depositing a conductive metal layer onto one surface of a silicon wafer. A thin photoresist and a standard lithographic mask are then used to transfer a trace image pattern onto the opposite surface of the wafer by exposing and developing the resist. The exposed portion of the silicon substrate is anisotropically etched through the wafer thickness down to conductive metal layer to provide an etched pattern consisting of a series of rectilinear channels and recesses in the silicon which serve as the silicon micro-mold. Microcomponents are prepared with this mold by first filling the mold channels and recesses with a metal deposit, typically by electroplating, and then removing the silicon micro-mold by chemical etching.

Detection of protein kinases P38 based on reflectance spectroscopy with n-type porous silicon microcavities for diagnosing hydatidosis hydatid disease

NASA Astrophysics Data System (ADS)

Lv, Xiaoyi; Lv, Guodong; Jia, Zhenhong; Wang, Jiajia; Mo, Jiaqing

2014-11-01

Detection of protein kinases P38 of Echinococcus granulosus and its homologous antibody have great value for early diagnosis and treatment of hydatidosis hydatid disease. In this experiment, n-type mesoporous silicon microcavities have been successfully fabricated without KOH etching or oxidants treatment that reported in other literature. We observed the changes of the reflectivity spectrum before and after the antigen-antibody reaction by n-type mesoporous silicon microcavities. The binding of protein kinases P38 and its homologous antibody causes red shifts in the reflection spectrum of the sensor, and the red shift was proportional to the protein kinases P38 concentration with linear relationship.

Electrostatic bonding of thin (approximately 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (approximately 2 mil) silicon wafers and solar cells

NASA Technical Reports Server (NTRS)

Egelkrout, D. W.; Horne, W. E.

1980-01-01

Electrostatic bonding (ESB) of thin (3 mil) Corning 7070 cover glasses to Ta2O5 AR-coated thin (2 mil) silicon wafers and solar cells is investigated. An experimental program was conducted to establish the effects of variations in pressure, voltage, temperature, time, Ta2O5 thickness, and various prebond glass treatments. Flat wafers without contact grids were used to study the basic effects for bonding to semiconductor surfaces typical of solar cells. Solar cells with three different grid patterns were used to determine additional requirements caused by the raised metallic contacts.

Doping of silicon with carbon during laser ablation process

NASA Astrophysics Data System (ADS)

Račiukaitis, G.; Brikas, M.; Kazlauskienė, V.; Miškinis, J.

2006-12-01

The effect of laser ablation on properties of remaining material in silicon was investigated. It was found that laser cutting of wafers in the air induced the doping of silicon with carbon. The effect was more distinct when using higher laser power or UV radiation. Carbon ions created bonds with silicon atoms in the depth of the material. Formation of the silicon carbide type bonds was confirmed by SIMS, XPS and AES measurements. Modeling of the carbon diffusion to clarify its depth profile in silicon was performed. Photochemical reactions of such type changed the structure of material and could be the reason of the reduced machining quality. The controlled atmosphere was applied to prevent carbonization of silicon during laser cutting.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1991-01-01

This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Process for the controlled growth of single-crystal films of silicon carbide polytypes on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Larkin, David J. (Inventor); Powell, J. Anthony (Inventor)

1992-01-01

A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.

Formation of silicon carbide by laser ablation in graphene oxide-N-methyl-2-pyrrolidone suspension on silicon surface

NASA Astrophysics Data System (ADS)

Jaleh, Babak; Ghasemi, Samaneh; Torkamany, Mohammad Javad; Salehzadeh, Sadegh; Maleki, Farahnaz

2018-01-01

Laser ablation of a silicon wafer in graphene oxide-N-methyl-2-pyrrolidone (GO-NMP) suspension was carried out with a pulsed Nd:YAG laser (pulse duration = 250 ns, wavelength = 1064 nm). The surface of silicon wafer before and after laser ablation was studied using optical microscopy, scanning electron microscopy (SEM) and energy dispersive X-ray analysis (EDX). The results showed that the ablation of silicon surface in liquid by pulsed laser was done by the process of melt expulsion under the influence of the confined plasma-induced pressure or shock wave trapped between the silicon wafer and the liquid. The X-ray diffraction‌ (XRD) pattern of Si wafer after laser ablation showed that 4H-SiC layer is formed on its surface. The formation of the above layer was also confirmed by Raman spectroscopy, and X-ray photoelectron spectroscopy‌ (XPS), as well as EDX was utilized. The reflectance of samples decreased with increasing pulse energy. Therefore, the morphological alteration and the formation of SiC layer at high energy increase absorption intensity in the UV‌-vis regions. Theoretical calculations confirm that the formation of silicon carbide from graphene oxide and silicon wafer is considerably endothermic. Development of new methods for increasing the reflectance without causing harmful effects is still an important issue for crystalline Si solar cells. By using the method described in this paper, the optical properties of solar cells can be improved.

Sidewall patterning—a new wafer-scale method for accurate patterning of vertical silicon structures

NASA Astrophysics Data System (ADS)

Westerik, P. J.; Vijselaar, W. J. C.; Berenschot, J. W.; Tas, N. R.; Huskens, J.; Gardeniers, J. G. E.

2018-01-01

For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that allows for reproducible sub-micrometer resolution local modification along vertical silicon sidewalls. Instead of optical lithography, this method makes smart use of inclined ion beam etching to selectively etch the top parts of structures, and controlled retraction of a conformal layer to define a hard mask in the vertical direction. The top, bottom or middle part of a structure could be selectively exposed, and it was shown that these exposed regions can, for example, be selectively covered with a catalyst, doped, or structured further.

A thermal microprobe fabricated with wafer-stage processing

NASA Astrophysics Data System (ADS)

Zhang, Yongxia; Zhang, Yanwei; Blaser, Juliana; Sriram, T. S.; Enver, Ahsan; Marcus, R. B.

1998-05-01

A thermal microprobe has been designed and built for high resolution temperature sensing. The thermal sensor is a thin-film thermocouple junction at the tip of an atomic force microprobe (AFM) silicon probe needle. Only wafer-stage processing steps are used for the fabrication. For high resolution temperature sensing it is essential that the junction be confined to a short distance at the AFM tip. This confinement is achieved by a controlled photoresist coating process. Experiment prototypes have been made with an Au/Pd junction confined to within 0.5 μm of the tip, with the two metals separated elsewhere by a thin insulating oxide layer. Processing begins with double-polished, n-type, 4 in. diameter, 300-μm-thick silicon wafers. Atomically sharp probe tips are formed by a combination of dry and wet chemical etching, and oxidation sharpening. The metal layers are sputtering deposited and the cantilevers are released by a combination of KOH and dry etching. A resistively heated calibration device was made for temperature calibration of the thermal microprobe over the temperature range 25-110 °C. Over this range the thermal outputs of two microprobes are 4.5 and 5.6 μV/K and is linear. Thermal and topographical images are also obtained from a heated tungsten thin film fuse.

Characterizing SOI Wafers By Use Of AOTF-PHI

NASA Technical Reports Server (NTRS)

Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

1995-01-01

Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

Silicon Hybrid Wafer Scale Integration Interconnect Evaluation

DTIC Science & Technology

1989-12-01

perform Wafer Scale Integration on a routine basis is being vigorously pursued by a number of interests in military, academic , and commercial sectors...A iliciosi rip1 St -110 illic. (;11ptai / W. -a ;,tcd Ihat Ilesc hybhrid futl liods separiltely soI lie llixiiiul’upw~v~ ielts andl ~il (otii’ie thli

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

PubMed

Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

2008-07-30

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

Post exposure bake unit equipped with wafer-shape compensation technology

NASA Astrophysics Data System (ADS)

Goto, Shigehiro; Morita, Akihiko; Oyama, Kenichi; Hori, Shimpei; Matsuchika, Keiji; Taniguchi, Hideyuki

2007-03-01

In 193nm lithography, it is well known that Critical Dimension Uniformity (CDU) within wafer is especially influenced by temperature variation during Post Exposure Bake (PEB) process. This temperature variation has been considered to be caused by the hot plate unit, and improvement of temperature uniformity within hot plate itself has been focused to achieve higher CDU. However, we have found that the impact of the wafer shape on temperature uniformity within wafer can not be ignored when the conventional PEB processing system is applied to an advanced resist technology. There are two factors concerned with the wafer shape. First, gravity force of the wafer itself generates wafer shape bending because wafer is simply supported by a few proximity gaps on the conventional hot plate. Next, through the semiconductor manufacturing process, wafer is gradually warped due to the difference of the surface stress between silicon and deposited film layers (Ex. Si-Oxide, Si-Nitride). Therefore, the variation of the clearance between wafer backside and hot plate surface leads to non-uniform thermal conductivity within wafer during PEB processing, and eventually impacts on the CDU within wafer. To overcome this problem concerned with wafer shape during PEB processing, we have developed the new hot plate equipped with the wafer shape compensation technology. As a result of evaluation, we have confirmed that this new PEB system has an advantage not only for warped wafer but also for flat (bare) wafer.

Proceedings of the Low-Cost Solar Array Wafering Workshop

NASA Technical Reports Server (NTRS)

Morrison, A. D.

1982-01-01

The technology and economics of silicon ingot wafering for low cost solar arrays were discussed. Fixed and free abrasive sawing wire, ID, and multiblade sawing, materials, mechanisms, characterization, and innovative concepts were considered.

I-line stepper based overlay evaluation method for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2018-03-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules additionally require to process the backside of the wafer; thus require an accurate alignment between the front and backside of the wafer. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 µm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8-9]. In this work, the non-contact infrared alignment system of the Nikon® i-line Stepper NSR-SF150 for both alignment and the overlay determination of bonded wafer stacks with embedded alignment marks are used to achieve an accurate alignment between the different wafer sides. The embedded field image alignment (FIA) marks of the interface and the device wafer top layer are measured in a single measurement job. By taking the

Study of thin film production of ceramic ZrO2 on silicon wafer using second harmonic Nd-Yag laser with pulsed laser deposition technique

NASA Astrophysics Data System (ADS)

Suliyanti, Maria M.; Hidayah, Affi Nur; Kurniawan, K. H.

2012-06-01

Study about thin film production using technique pulsed laser deposition have been done. The Pulsed Laser Deposition (PLD) method has been used for growing thin film of ZrO2 on silicon wafer substrate (111 single crystal, thickness 400μm and diameter 7.5 cm). The target made from Zirconia oxide powder mixing with PVA and press using pressure 100kgN. The laser beam was focused by a lens (f = 100mm) through a quartz window onto the sample surface and the substrate was placed in parallel line with target. The distance between the target and the substrate is about 1 cm. The early results of this synthesis using 75 mJ Nd-YAG second harmonic laser pulse (532 nm Nd-YAG) and low pressure chamber surrounding gas 5 Torr. The irradiation of laser take around 6000 shoots or 10 minutes using frequencies laser 10 Hz. The micro thickness of film can be produced on silicon wafer using this technique. The results of ZrO2 thin film on substrate about 26.92%.

Vertical integration of array-type miniature interferometers at wafer level by using multistack anodic bonding

NASA Astrophysics Data System (ADS)

Wang, Wei-Shan; Wiemer, Maik; Froemel, Joerg; Enderlein, Tom; Gessner, Thomas; Lullin, Justine; Bargiel, Sylwester; Passilly, Nicolas; Albero, Jorge; Gorecki, Christophe

2016-04-01

In this work, vertical integration of miniaturized array-type Mirau interferometers at wafer level by using multi-stack anodic bonding is presented. Mirau interferometer is suitable for MEMS metrology and for medical imaging according to its vertical-, lateral- resolutions and working distances. Miniaturized Mirau interferometer can be a promising candidate as a key component of an optical coherence tomography (OCT) system. The miniaturized array-type interferometer consists of a microlens doublet, a Si-based MEMS Z scanner, a spacer for focus-adjustment and a beam splitter. Therefore, bonding technologies which are suitable for heterogeneous substrates are of high interest and necessary for the integration of MEMS/MOEMS devices. Multi-stack anodic bonding, which meets the optical and mechanical requirements of the MOEMS device, is adopted to integrate the array-type interferometers. First, the spacer and the beam splitter are bonded, followed by bonding of the MEMS Z scanner. In the meanwhile, two microlenses, which are composed of Si and glass wafers, are anodically bonded to form a microlens doublet. Then, the microlens doublet is aligned and bonded with the scanner/spacer/beam splitter stack. The bonded array-type interferometer is a 7- wafer stack and the thickness is approximately 5mm. To separate such a thick wafer stack with various substrates, 2-step laser cutting is used to dice the bonded stack into Mirau chips. To simplify fabrication process of each component, electrical connections are created at the last step by mounting a Mirau chip onto a flip chip PCB instead of through wafer vias. Stability of Au/Ti films on the MEMS Z scanner after anodic bonding, laser cutting and flip chip bonding are discussed as well.

Passivation of c-Si surfaces by sub-nm amorphous silicon capped with silicon nitride

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wan, Yimao, E-mail: yimao.wan@anu.edu.au; Yan, Di; Bullock, James

2015-12-07

A sub-nm hydrogenated amorphous silicon (a-Si:H) film capped with silicon nitride (SiN{sub x}) is shown to provide a high level passivation to crystalline silicon (c-Si) surfaces. When passivated by a 0.8 nm a-Si:H/75 nm SiN{sub x} stack, recombination current density J{sub 0} values of 9, 11, 47, and 87 fA/cm{sup 2} are obtained on 10 Ω·cm n-type, 0.8 Ω·cm p-type, 160 Ω/sq phosphorus-diffused, and 120 Ω/sq boron-diffused silicon surfaces, respectively. The J{sub 0} on n-type 10 Ω·cm wafers is further reduced to 2.5 ± 0.5 fA/cm{sup 2} when the a-Si:H film thickness exceeds 2.5 nm. The passivation by the sub-nm a-Si:H/SiN{sub x} stack is thermally stable at 400 °C in N{sub 2} formore » 60 min on all four c-Si surfaces. Capacitance–voltage measurements reveal a reduction in interface defect density and film charge density with an increase in a-Si:H thickness. The nearly transparent sub-nm a-Si:H/SiN{sub x} stack is thus demonstrated to be a promising surface passivation and antireflection coating suitable for all types of surfaces encountered in high efficiency c-Si solar cells.« less

Optimal mask characterization by Surrogate Wafer Print (SWaP) method

NASA Astrophysics Data System (ADS)

Kimmel, Kurt R.; Hoellein, Ingo; Peters, Jan Hendrick; Ackmann, Paul; Connolly, Brid; West, Craig

2008-10-01

Traditionally, definition of mask specifications is done completely by the mask user, while characterization of the mask relative to the specifications is done completely by the mask maker. As the challenges of low-k1 imaging continue to grow in scope of designs and in absolute complexity, the inevitable partnership between wafer lithographers and mask makers has strengthened as well. This is reflected in the jointly owned mask facilities and device manufacturers' continued maintenance of fully captive mask shops which foster the closer mask-litho relationships. However, while some device manufacturers have leveraged this to optimize mask specifications before the mask is built and, therefore, improve mask yield and cost, the opportunity for post-fabrication partnering on mask characterization is more apparent and compelling. The Advanced Mask Technology Center (AMTC) has been investigating the concept of assessing how a mask images, rather than the mask's physical attributes, as a technically superior and lower-cost method to characterize a mask. The idea of printing a mask under its intended imaging conditions, then characterizing the imaged wafer as a surrogate for traditional mask inspections and measurements represents the ultimate method to characterize a mask's performance, which is most meaningful to the user. Surrogate wafer print (SWaP) is already done as part of leading-edge wafer fab mask qualification to validate defect and dimensional performance. In the past, the prospect of executing this concept has generally been summarily discarded as technically untenable and logistically intractable. The AMTC published a paper at BACUS 2007 successfully demonstrating the performance of SWaP for the characterization of defects as an alternative to traditional mask inspection [1]. It showed that this concept is not only feasible, but, in some cases, desirable. This paper expands on last year's work at AMTC to assess the full implementation of SWaP as an

Resonance ultrasonic diagnostics of defects in full-size silicon wafers

NASA Astrophysics Data System (ADS)

Belyaev, A.; Ostapenko, S.

2001-12-01

A resonance acoustic effect was observed recently in full-size 200 mm Cz-Si wafers and applied to characterize as-grown and process-induced defects. Ultrasonic vibrations can be excited into wafers using an external ultrasonic transducer and their amplitude is recorded using a scanning air-coupled acoustic probe operated in a non-contact mode. By sweeping driving frequency, f, of the transducer, we observed an amplification of a specific acoustic mode referred to as ‘whistle’. In this paper, we performed theoretical modeling of the whistle which allowed in attributing this mode to resonant flexural vibrations in a thin circular plate. We calculated normal frequencies of the flexural vibrations of a circular plate of radius ρ in the case of the free edge. The model gives an excellent fit to experimental data with regard to whistle spatial distribution. The results of calculation allow the evaluation of resonance acoustic effect in wafers of different geometries employed in the industry.

Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

NASA Astrophysics Data System (ADS)

Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

2018-03-01

It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up

Contactless measurement of electrical conductivity of semiconductor wafers using the reflection of millimeter waves

NASA Astrophysics Data System (ADS)

Ju, Yang; Inoue, Kojiro; Saka, Masumi; Abe, Hiroyuki

2002-11-01

We present a method for quantitative measurement of electrical conductivity of semiconductor wafers in a contactless fashion by using millimeter waves. A focusing sensor was developed to focus a 110 GHz millimeter wave beam on the surface of a silicon wafer. The amplitude and the phase of the reflection coefficient of the millimeter wave signal were measured by which electrical conductivity of the wafer was determined quantitatively, independent of the permittivity and thickness of the wafers. The conductivity obtained by this method agrees well with that measured by the conventional four-point-probe method.

Optimization of the Surface Structure on Black Silicon for Surface Passivation

NASA Astrophysics Data System (ADS)

Jia, Xiaojie; Zhou, Chunlan; Wang, Wenjing

2017-03-01

Black silicon shows excellent anti-reflection and thus is extremely useful for photovoltaic applications. However, its high surface recombination velocity limits the efficiency of solar cells. In this paper, the effective minority carrier lifetime of black silicon is improved by optimizing metal-catalyzed chemical etching (MCCE) method, using an Al2O3 thin film deposited by atomic layer deposition (ALD) as a passivation layer. Using the spray method to eliminate the impact on the rear side, single-side black silicon was obtained on n-type solar grade silicon wafers. Post-etch treatment with NH4OH/H2O2/H2O mixed solution not only smoothes the surface but also increases the effective minority lifetime from 161 μs of as-prepared wafer to 333 μs after cleaning. Moreover, adding illumination during the etching process results in an improvement in both the numerical value and the uniformity of the effective minority carrier lifetime.

Optimization of the Surface Structure on Black Silicon for Surface Passivation.

PubMed

Jia, Xiaojie; Zhou, Chunlan; Wang, Wenjing

2017-12-01

Black silicon shows excellent anti-reflection and thus is extremely useful for photovoltaic applications. However, its high surface recombination velocity limits the efficiency of solar cells. In this paper, the effective minority carrier lifetime of black silicon is improved by optimizing metal-catalyzed chemical etching (MCCE) method, using an Al 2 O 3 thin film deposited by atomic layer deposition (ALD) as a passivation layer. Using the spray method to eliminate the impact on the rear side, single-side black silicon was obtained on n-type solar grade silicon wafers. Post-etch treatment with NH 4 OH/H 2 O 2 /H 2 O mixed solution not only smoothes the surface but also increases the effective minority lifetime from 161 μs of as-prepared wafer to 333 μs after cleaning. Moreover, adding illumination during the etching process results in an improvement in both the numerical value and the uniformity of the effective minority carrier lifetime.

Silicon crystals: Process for manufacturing wafer-like silicon crystals with a columnar structure

NASA Technical Reports Server (NTRS)

Authier, B.

1978-01-01

Wafer-like crystals suitable for making solar cells are formed by pouring molten Si containing suitable dopants into a mold of the desired shape and allowing it to solidify in a temperature gradient, whereby the large surface of the melt in contact with the mold is kept at less than 200 D and the free surface is kept at a temperature of 200-1000 D higher, but below the melting point of Si. The mold can also be made in the form of a slit, whereby the 2 sides of the mold are kept at different temperatures. A mold was milled in the surface of a cylindrical graphite block 200 mm in diameter. The granite block was induction heated and the bottom of the mold was cooled by means of a water-cooled Cu plate, so that the surface of the mold in contact with one of the largest surfaces of the melt was held at approximately 800 D. The free surface of the melt was subjected to thermal radiation from a graphite plate located 2 mm from the surface and heated to 1500 D. The Si crystal formed after slow cooling to room temperature had a columnar structure and was cut with a diamond saw into wafers approximately 500 mm thick. Solar cells prepared from these wafers had efficiencies of 10 to 11%.

Inversion layer solar cell fabrication and evaluation. [etching on silicon films

NASA Technical Reports Server (NTRS)

Call, R. L.

1974-01-01

Inversion layer solar cells were fabricated by etching through the diffused layer on p-type silicon wafers in a comb-like contact pattern. The charge separation comes from an induced p-n junction at the surface. The inverted surface is caused by a layer of transparent material applied to the surface that either contains free positive ions or that creates donor states at the interface. Cells are increased from 3 ma I sub sc to 100 ma by application of sodium silicate. The action is unstable, however, and decays. Non-mesa contaminated oxide cells were fabricated with short circuit currents of over 100 ma measured in the sun. Cells of this type have demonstrated stability.

Tantalum oxide/silicon nitride: A negatively charged surface passivation stack for silicon solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wan, Yimao, E-mail: yimao.wan@anu.edu.au; Bullock, James; Cuevas, Andres

2015-05-18

This letter reports effective passivation of crystalline silicon (c-Si) surfaces by thermal atomic layer deposited tantalum oxide (Ta{sub 2}O{sub 5}) underneath plasma enhanced chemical vapour deposited silicon nitride (SiN{sub x}). Cross-sectional transmission electron microscopy imaging shows an approximately 2 nm thick interfacial layer between Ta{sub 2}O{sub 5} and c-Si. Surface recombination velocities as low as 5.0 cm/s and 3.2 cm/s are attained on p-type 0.8 Ω·cm and n-type 1.0 Ω·cm c-Si wafers, respectively. Recombination current densities of 25 fA/cm{sup 2} and 68 fA/cm{sup 2} are measured on 150 Ω/sq boron-diffused p{sup +} and 120 Ω/sq phosphorus-diffused n{sup +} c-Si, respectively. Capacitance–voltage measurements reveal a negativemore » fixed insulator charge density of −1.8 × 10{sup 12 }cm{sup −2} for the Ta{sub 2}O{sub 5} film and −1.0 × 10{sup 12 }cm{sup −2} for the Ta{sub 2}O{sub 5}/SiN{sub x} stack. The Ta{sub 2}O{sub 5}/SiN{sub x} stack is demonstrated to be an excellent candidate for surface passivation of high efficiency silicon solar cells.« less

Improved method of preparing p-i-n junctions in amorphous silicon semiconductors

DOEpatents

Madan, A.

1984-12-10

A method of preparing p/sup +/-i-n/sup +/ junctions for amorphous silicon semiconductors includes depositing amorphous silicon on a thin layer of trivalent material, such as aluminum, indium, or gallium at a temperature in the range of 200/sup 0/C to 250/sup 0/C. At this temperature, the layer of trivalent material diffuses into the amorphous silicon to form a graded p/sup +/-i junction. A layer of n-type doped material is then deposited onto the intrinsic amorphous silicon layer in a conventional manner to finish forming the p/sup +/-i-n/sup +/ junction.

Pyroelectric, piezoelectric, and photoeffects in hydroxyapatite thin films on silicon

NASA Astrophysics Data System (ADS)

Lang, S. B.; Tofail, S. A. M.; Gandhi, A. A.; Gregor, M.; Wolf-Brandstetter, C.; Kost, J.; Bauer, S.; Krause, M.

2011-03-01

Hydroxyapatite (HA) is the major component of bone and is used in artificial form in many biomedical applications. It was once believed to have a centrosymmetric crystal structure. In theoretical and experimental studies published in 2005, it was shown to have a monoclinic P21 structure. In the work reported here, 500 nm films of HA were spin-coated on silicon wafers. The materials were not poled. They had a nonuniform polarization distribution and exhibited pyroelectricity, piezoelectricity, and photoeffects. Structures of this type may have a number of technological applications.

Laser treatment of plasma-hydrogenated silicon wafers for thin layer exfoliation

NASA Astrophysics Data System (ADS)

Ghica, Corneliu; Nistor, Leona Cristina; Teodorescu, Valentin Serban; Maraloiu, Adrian; Vizireanu, Sorin; Scarisoreanu, Nae Doinel; Dinescu, Maria

2011-03-01

We have studied by transmission electron microscopy the microstructural effects induced by pulsed laser annealing in comparison with thermal treatments of RF plasma hydrogenated Si wafers aiming for further application in the smart-cut procedure. While thermal annealing mainly produces a slight decrease of the density of plasma-induced planar defects and an increase of the size and number of plasma-induced nanocavities in the Si matrix, pulsed laser annealing of RF plasma hydrogenated Si wafers with a 355 nm wavelength radiation results in both the healing of defects adjacent to the wafer surface and the formation of a well defined layer of nanometric cavities at a depth of 25-50 nm. In this way, a controlled fracture of single crystal layers of Si thinner than 50 nm is favored.

Wafer-scale epitaxial graphene on SiC for sensing applications

NASA Astrophysics Data System (ADS)

Karlsson, Mikael; Wang, Qin; Zhao, Yichen; Zhao, Wei; Toprak, Muhammet S.; Iakimov, Tihomir; Ali, Amer; Yakimova, Rositza; Syväjärvi, Mikael; Ivanov, Ivan G.

2015-12-01

The epitaxial graphene-on-silicon carbide (SiC-G) has advantages of high quality and large area coverage owing to a natural interface between graphene and SiC substrate with dimension up to 100 mm. It enables cost effective and reliable solutions for bridging the graphene-based sensors/devices from lab to industrial applications and commercialization. In this work, the structural, optical and electrical properties of wafer-scale graphene grown on 2'' 4H semi-insulating (SI) SiC utilizing sublimation process were systemically investigated with focus on evaluation of the graphene's uniformity across the wafer. As proof of concept, two types of glucose sensors based on SiC-G/Nafion/Glucose-oxidase (GOx) and SiC-G/Nafion/Chitosan/GOx were fabricated and their electrochemical properties were characterized by cyclic voltammetry (CV) measurements. In addition, a few similar glucose sensors based on graphene by chemical synthesis using modified Hummer's method were also fabricated for comparison.

Process for the homoepitaxial growth of single-crystal silicon carbide films on silicon carbide wafers

NASA Technical Reports Server (NTRS)

Powell, J. Anthony (Inventor)

1993-01-01

The invention is a method for growing homoepitaxial films of SiC on low tilt angle vicinal (0001) SiC wafers. The invention proposes and teaches a new theoretical model for the homoepitaxial growth of SiC films on (0001) SiC substrates. The inventive method consists of preparing the growth surface of SiC wafers slightly off-axis (from less the 0.1 to 6 deg) from the (0001) plane, subjecting the growth surface to a suitable etch, and then growing the homoepitaxial film using conventional SiC growth techniques.

Characterization of wafer-level bonded hermetic packages using optical leak detection

NASA Astrophysics Data System (ADS)

Duan, Ani; Wang, Kaiying; Aasmundtveit, Knut; Hoivik, Nils

2009-07-01

For MEMS devices required to be operated in a hermetic environment, one of the main reliability issues is related to the packaging methods applied. In this paper, an optical method for testing low volume hermetic cavities formed by anodic bonding between glass and SOI (silicon on insulator) wafer is presented. Several different cavity-geometry structures have been designed, fabricated and applied to monitor the hermeticity of wafer level anodic bonding. SOI wafer was used as the cap wafer on which the different-geometry structures were fabricated using standard MEMS technology. The test cavities were bonded using SOI wafers to glass wafers at 400C and 1000mbar pressure inside a vacuum bonding chamber. The bonding voltage varies from 200V to 600V. The bonding strength between glass and SOI wafer was mechanically tested using shear tester. The deformation amplitudes of the cavity cap surface were monitored by using an optical interferometer. The hermeticity of the glass-to-SOI wafer level bonding was characterized through observing the surface deformation in a 6 months period in atmospheric environment. We have observed a relatively stable micro vacuum-cavity.

Novel Bonding Technology for Hermetically Sealed Silicon Micropackage

NASA Astrophysics Data System (ADS)

Lee, Duck-Jung; Ju, Byeong-Kwon; Choi, Woo-Beom; Jeong, Jee-Won; Lee, Yun-Hi; Jang, Jin; Lee, Kwang-Bae; Oh, Myung-Hwan

1999-01-01

We performed glass-to-silicon bonding and fabricated a hermetically sealed silicon wafer using silicon direct bonding followed by anodic bonding (SDAB). The hydrophilized glass and silicon wafers in solution were dried and initially bonded in atmosphere as in the silicon direct bonding (SDB) process, but annealing at high temperature was not performed. Anodic bonding was subsequently carried out for the initially bonded specimens. Then the wafer pairs bonded by the SDAB method were different from those bonded by the anodic bonding process only. The effects of the bonding process on the bonded area and tensile strength were investigated as functions of bonding temperature and voltage. Using scanning electron microscopy (SEM), the cross-sectional view of the bonded interface region was observed. In order to investigate the migration of the sodium ions in the bonding process, the concentration of the bonded glass was compared with that of standard glass. The specimen bonded using the SDAB process had higher efficiency than that using the anodic bonding process only.

Roll up nanowire battery from silicon chips

PubMed Central

Vlad, Alexandru; Reddy, Arava Leela Mohana; Ajayan, Anakha; Singh, Neelam; Gohy, Jean-François; Melinte, Sorin; Ajayan, Pulickel M.

2012-01-01

Here we report an approach to roll out Li-ion battery components from silicon chips by a continuous and repeatable etch-infiltrate-peel cycle. Vertically aligned silicon nanowires etched from recycled silicon wafers are captured in a polymer matrix that operates as Li+ gel-electrolyte and electrode separator and peeled off to make multiple battery devices out of a single wafer. Porous, electrically interconnected copper nanoshells are conformally deposited around the silicon nanowires to stabilize the electrodes over extended cycles and provide efficient current collection. Using the above developed process we demonstrate an operational full cell 3.4 V lithium-polymer silicon nanowire (LIPOSIL) battery which is mechanically flexible and scalable to large dimensions. PMID:22949696

CROSS-DISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Excellent Passivation of p-Type Si Surface by Sol-Gel Al2O3 Films

NASA Astrophysics Data System (ADS)

Xiao, Hai-Qing; Zhou, Chun-Lan; Cao, Xiao-Ning; Wang, Wen-Jing; Zhao, Lei; Li, Hai-Ling; Diao, Hong-Wei

2009-08-01

Al2O3 films with a thickness of about 100 nm synthesized by spin coating and thermally treated are applied for field-induced surface passivation of p-type crystalline silicon. The level of surface passivation is determined by techniques based on photoconductance. An effective surface recombination velocity below 100 cm/s is obtained on 10Ω ·cm p-type c-Si wafers (Cz Si). A high density of negative fixed charges in the order of 1012 cm-2 is detected in the Al2O3 films and its impact on the level of surface passivation is demonstrated experimentally. Furthermore, a comparison between the surface passivation achieved for thermal SiO2 and plasma enhanced chemical vapor deposition SiNx:H films on the same c-Si is presented. The high negative fixed charge density explains the excellent passivation of p-type c-Si by Al2O3.

Formation and characterization of ZnS/CdS nanocomposite materials into porous silicon

NASA Astrophysics Data System (ADS)

Xue, Tao; Lv, Xiao-yi; Jia, Zhen-hong; Hou, Jun-wei; Jian, Ji-kang

2008-11-01

ZnS/CdS were deposited by chemical vapor deposition (CVD) technique on porous silicon substrates formed by electrochemical anodization of n-type (100) silicon wafer. The optical properties of ZnS/CdS porous silicon composite materials are studied. The results showed that new luminescence characteristics such as strong and stable visible-light emissions with different colors were observed from the ZnS/CdS-PS nanocomposite materials at room temperature.

Investigating reliability attributes of silicon photovoltaic cells - An overview

NASA Technical Reports Server (NTRS)

Royal, E. L.

1982-01-01

Reliability attributes are being developed on a wide variety of advanced single-crystal silicon solar cells. Two separate investigations: cell-contact integrity (metal-to-silicon adherence), and cracked cells identified with fracture-strength-reducing flaws are discussed. In the cell-contact-integrity investigation, analysis of contact pull-strength data shows that cell types made with different metallization technologies, i.e., vacuum, plated, screen-printed and soldered, have appreciably different reliability attributes. In the second investigation, fracture strength was measured using Czochralski wafers and cells taken at various stages of processing and differences were noted. Fracture strength, which is believed to be governed by flaws introduced during wafer sawing, was observed to improve (increase) after chemical polishing and other process steps that tend to remove surface and edge flaws.

One-step preparation of multiwall carbon nanotube/silicon hybrids for solar energy conversion

NASA Astrophysics Data System (ADS)

Lobiak, Egor V.; Bychanok, Dzmitry S.; Shlyakhova, Elena V.; Kuzhir, Polina P.; Maksimenko, Sergey A.; Bulusheva, Lyubov G.; Okotrub, Alexander V.

2016-03-01

The hybrid material consisting of a thin layer of multiwall carbon nanotubes (MWCNTs) on an n-doped silicon wafer was obtained in one step using an aerosol-assisted catalytic chemical vapor deposition. The MWCNTs were grown from a mixture of acetone and ethanol with ˜0.2 wt.% of iron polyoxomolybdate nanocluster of the keplerate-type structure. The samples produced at 800°C and 1050°C were tested as a solar energy converter. It was shown that photoresponse of the hybrid material significantly depends on the presence of structural defects in MWCNTs, being much higher in the case of more defective nanotubes. This is because defects lead to p-doping of nanotubes, whereas the p-n heterojunction between MWCNTs and silicon provides a high efficiency of the solar cell.

Recombination activity of light-activated copper defects in p-type silicon studied by injection- and temperature-dependent lifetime spectroscopy

NASA Astrophysics Data System (ADS)

Inglese, Alessandro; Lindroos, Jeanette; Vahlman, Henri; Savin, Hele

2016-09-01

The presence of copper contamination is known to cause strong light-induced degradation (Cu-LID) in silicon. In this paper, we parametrize the recombination activity of light-activated copper defects in terms of Shockley—Read—Hall recombination statistics through injection- and temperature dependent lifetime spectroscopy (TDLS) performed on deliberately contaminated float zone silicon wafers. We obtain an accurate fit of the experimental data via two non-interacting energy levels, i.e., a deep recombination center featuring an energy level at Ec-Et=0.48 -0.62 eV with a moderate donor-like capture asymmetry ( k =1.7 -2.6 ) and an additional shallow energy state located at Ec-Et=0.1 -0.2 eV , which mostly affects the carrier lifetime only at high-injection conditions. Besides confirming these defect parameters, TDLS measurements also indicate a power-law temperature dependence of the capture cross sections associated with the deep energy state. Eventually, we compare these results with the available literature data, and we find that the formation of copper precipitates is the probable root cause behind Cu-LID.

Low temperature spalling of silicon: A crack propagation study

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bertoni, Mariana; Uberg Naerland, Tine; Stoddard, Nathan

2017-06-08

Spalling is a promising kerfless method for cutting thin silicon wafers while doubling the yield of a silicon ingot. The main obstacle in this technology is the high total thickness variation of the spalled wafers, often as high as 100% of the wafer thickness. It has been suggested before that a strong correlation exists between low crack velocities and a smooth surface, but this correlation has never been shown during a spalling process in silicon. The reason lies in the challenge associated to measuring such velocities. In this contribution, we present a new approach to assess, in real time, themore » crack velocity as it propagates during a low temperature spalling process. Understanding the relationship between crack velocity and surface roughness during spalling can pave the way to attain full control on the surface quality of the spalled wafer.« less

New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

NASA Astrophysics Data System (ADS)

Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

2017-06-01

In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

Within-wafer CD variation induced by wafer shape

NASA Astrophysics Data System (ADS)

Huang, Chi-hao; Yang, Mars; Yang, Elvis; Yang, T. H.; Chen, K. C.

2016-03-01

In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity. The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer

Surface property modification of silicon

NASA Technical Reports Server (NTRS)

Danyluk, S.

1984-01-01

The main emphasis of this work has been to determine the wear rate of silicon in fluid environments and the parameters that influence wear. Three tests were carried out on single crystal Czochralski silicon wafers: circular and linear multiple-scratch tests in fluids by a pyramidal diamond simulated fixed-particle abrasion; microhardness and three-point bend tests were used to determine the hardness and fracture toughness of abraded silicon and the extent of damage induced by abrasion. The wear rate of (100) and (111) n and p-type single crystal Cz silicon abraded by a pyramidal diamond in ethanol, methanol, acetone and de-ionized water was determined by measuring the cross-sectional areas of grooves of the circular and linear multiple-scratch tests. The wear rate depends on the loads on the diamond and is highest for ethanol and lowest for de-ionized water. The surface morphology of the grooves showed lateral and median cracks as well as a plastically deformed region. The hardness and fracture toughness are critical parameters that influence the wear rate. Microhardness tests were conducted to determine the hardness as influenced by fluids. Median cracks and the damage zone surrounding the indentations were also related to the fluid properties.

Influence of the transition region between p- and n-type polycrystalline silicon passivating contacts on the performance of interdigitated back contact silicon solar cells

NASA Astrophysics Data System (ADS)

Reichel, Christian; Müller, Ralph; Feldmann, Frank; Richter, Armin; Hermle, Martin; Glunz, Stefan W.

2017-11-01

Passivating contacts based on thin tunneling oxides (SiOx) and n- and p-type semi-crystalline or polycrystalline silicon (poly-Si) enable high passivation quality and low contact resistivity, but the integration of these p+/n emitter and n+/n back surface field junctions into interdigitated back contact silicon solar cells poses a challenge due to high recombination at the transition region from p-type to n-type poly-Si. Here, the transition region was created in different configurations—(a) p+ and n+ poly-Si regions are in direct contact with each other ("pn-junction"), using a local overcompensation (counterdoping) as a self-aligning process, (b) undoped (intrinsic) poly-Si remains between the p+ and n+ poly-Si regions ("pin-junction"), and (c) etched trenches separate the p+ and n+ poly-Si regions ("trench")—in order to investigate the recombination characteristics and the reverse breakdown behavior of these solar cells. Illumination- and injection-dependent quasi-steady state photoluminescence (suns-PL) and open-circuit voltage (suns-Voc) measurements revealed that non-ideal recombination in the space charge regions with high local ideality factors as well as recombination in shunted regions strongly limited the performance of solar cells without a trench. In contrast, solar cells with a trench allowed for open-circuit voltage (Voc) of 720 mV, fill factor of 79.6%, short-circuit current (Jsc) of 41.3 mA/cm2, and a conversion efficiencies (η) of 23.7%, showing that a lowly conducting and highly passivating intermediate layer between the p+ and n+ poly-Si regions is mandatory. Independent of the configuration, no hysteresis was observed upon multiple stresses in reverse direction, indicating a controlled and homogeneously distributed breakdown, but with different breakdown characteristics.

Characterization and modelling of the boron-oxygen defect activation in compensated n-type silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schön, J.; Niewelt, T.; Broisch, J.

2015-12-28

A study of the activation of the light-induced degradation in compensated n-type Czochralski grown silicon is presented. A kinetic model is established that verifies the existence of both the fast and the slow components known from p-type and proves the quadratic dependence of the defect generation rates of both defects on the hole concentration. The model allows for the description of lifetime degradation kinetics in compensated n-type silicon under various intensities and is in accordance with the findings for p-type silicon. We found that the final concentrations of the slow defect component in compensated n-type silicon only depend on themore » interstitial oxygen concentration and on neither the boron concentration nor the equilibrium electron concentration n{sub 0}. The final concentrations of the fast defect component slightly increase with increasing boron concentration. The results on n-type silicon give new insight to the origin of the BO defect and question the existing models for the defect composition.« less

Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

PubMed

Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

2013-03-25

n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

From Si wafers to cheap and efficient Si electrodes for Li-ion batteries

NASA Astrophysics Data System (ADS)

Gauthier, Magali; Reyter, David; Mazouzi, Driss; Moreau, Philippe; Guyomard, Dominique; Lestriez, Bernard; Roué, Lionel

2014-06-01

High-energy ball milling is used to recycle Si wafers to produce Si powders for negative electrodes of Li-ion batteries. The resulting Si powder consists in micrometric Si agglomerates made of cold-welded submicrometric nanocrystalline Si particles. Silicon-based composite electrodes prepared with ball-milled Si wafer can achieve more than 900 cycles with a capacity of 1200 mAh g-1 of Si (880 mAh g-1 of electrode) and a coulombic efficiency higher than 99%. This excellent electrochemical performance lies in the use of nanostructured Si produced by ball milling, the electrode formulation in a pH 3 buffer solution with CMC as binder and the use of FEC/VC additives in the electrolyte. This work opens the way to an economically attractive recycling of Si wastes.

Effect of void shape in Czochralski-Si wafers on the intensity of laser-scattering

NASA Astrophysics Data System (ADS)

Takahashi, J.; Kawakami, K.; Nakai, K.

2001-06-01

The shape effect of anisotropic-shaped microvoid defects in Czochralski-grown silicon wafers on the intensity of laser scattering has been investigated. The size and shape of the defects were examined by means of transmission electron microscopy. Octahedral voids in conventional (nitrogen-undoped) wafers showed an almost isotropic scattering property under the incident condition of a p-polarization beam. On the other hand, parallelepiped-plate-shaped voids in nitrogen-doped wafers showed an anisotropic scattering property on both p- and s-polarized components of scattered light, depending strongly on the incident laser direction. The measured results were explained not by scattering calculation using Born approximation but by calculation based on Rayleigh scattering. It was found that the s component is explained by an inclination of a dipole moment induced on a defect from the scattering plane. Furthermore, using numerical electromagnetic analysis it was shown that the asymmetric behavior of the s component on the parallelepiped-plate voids is ascribed to the parallelepiped shape effect. These results suggest that correction of the scattering intensity is necessary to evaluate the size and volume of anisotropic-shaped defects from the scattered intensity.

Wafer screening device and methods for wafer screening

DOEpatents

Sopori, Bhushan; Rupnowski, Przemyslaw

2014-07-15

Wafer breakage is a serious problem in the photovoltaic industry because a large fraction of wafers (between 5 and 10%) break during solar cell/module fabrication. The major cause of this excessive wafer breakage is that these wafers have residual microcracks--microcracks that were not completely etched. Additional propensity for breakage is caused by texture etching and incomplete edge grinding. To eliminate the cost of processing the wafers that break, it is best to remove them prior to cell fabrication. Some attempts have been made to develop optical techniques to detect microcracks. Unfortunately, it is very difficult to detect microcracks that are embedded within the roughness/texture of the wafers. Furthermore, even if such detection is successful, it is not straightforward to relate them to wafer breakage. We believe that the best way to isolate the wafers with fatal microcracks is to apply a stress to wafers--a stress that mimics the highest stress during cell/module processing. If a wafer survives this stress, it has a high probability of surviving without breakage during cell/module fabrication. Based on this, we have developed a high throughput, noncontact method for applying a predetermined stress to a wafer. The wafers are carried on a belt through a chamber that illuminates the wafer with an intense light of a predetermined intensity distribution that can be varied by changing the power to the light source. As the wafers move under the light source, each wafer undergoes a dynamic temperature profile that produces a preset elastic stress. If this stress exceeds the wafer strength, the wafer will break. The broken wafers are separated early, eliminating cost of processing into cell/module. We will describe details of the system and show comparison of breakage statistics with the breakage on a production line.

Low resistance Ohmic contact to p-type crystalline silicon via nitrogen-doped copper oxide films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Xinyu, E-mail: xinyu.zhang@anu.edu.au; Wan, Yimao; Bullock, James

2016-08-01

This work explores the application of transparent nitrogen doped copper oxide (CuO{sub x}:N) films deposited by reactive sputtering to create hole-selective contacts for p-type crystalline silicon (c-Si) solar cells. It is found that CuO{sub x}:N sputtered directly onto crystalline silicon is able to form an Ohmic contact. X-ray photoelectron spectroscopy and Raman spectroscopy measurements are used to characterise the structural and physical properties of the CuO{sub x}:N films. Both the oxygen flow rate and the substrate temperature during deposition have a significant impact on the film composition, as well as on the resulting contact resistivity. After optimization, a low contactmore » resistivity of ∼10 mΩ cm{sup 2} has been established. This result offers significant advantages over conventional contact structures in terms of carrier transport and device fabrication.« less

Fabrication and Modification of Nanoporous Silicon Particles

NASA Technical Reports Server (NTRS)

Ferrari, Mauro; Liu, Xuewu

2010-01-01

Silicon-based nanoporous particles as biodegradable drug carriers are advantageous in permeation, controlled release, and targeting. The use of biodegradable nanoporous silicon and silicon dioxide, with proper surface treatments, allows sustained drug release within the target site over a period of days, or even weeks, due to selective surface coating. A variety of surface treatment protocols are available for silicon-based particles to be stabilized, functionalized, or modified as required. Coated polyethylene glycol (PEG) chains showed the effective depression of both plasma protein adsorption and cell attachment to the modified surfaces, as well as the advantage of long circulating. Porous silicon particles are micromachined by lithography. Compared to the synthesis route of the nanomaterials, the advantages include: (1) the capability to make different shapes, not only spherical particles but also square, rectangular, or ellipse cross sections, etc.; (2) the capability for very precise dimension control; (3) the capacity for porosity and pore profile control; and (4) allowance of complex surface modification. The particle patterns as small as 60 nm can be fabricated using the state-of-the-art photolithography. The pores in silicon can be fabricated by exposing the silicon in an HF/ethanol solution and then subjecting the pores to an electrical current. The size and shape of the pores inside silicon can be adjusted by the doping of the silicon, electrical current application, the composition of the electrolyte solution, and etching time. The surface of the silicon particles can be modified by many means to provide targeted delivery and on-site permanence for extended release. Multiple active agents can be co-loaded into the particles. Because the surface modification of particles can be done on wafers before the mechanical release, asymmetrical surface modification is feasible. Starting from silicon wafers, a treatment, such as KOH dipping or reactive ion

High-efficiency silicon heterojunction solar cells: Status and perspectives

DOE Office of Scientific and Technical Information (OSTI.GOV)

De Wolf, S.

Silicon heterojunction technology (HJT) uses silicon thin-film deposition techniques to fabricate photovoltaic devices from mono-crystalline silicon wafers (c-Si). This enables energy-conversion efficiencies above 21 %, also at industrial-production level. In this presentation we review the present status of this technology and point out recent trends. We first discuss how the properties of thin hydrogenated amorphous silicon (a-Si:H) films can be exploited to fabricate passivating contacts, which is the key to high- efficiency HJT solar cells. Such contacts enable very high operating voltages, approaching the theoretical limits, and yield small temperature coefficients. With this approach, an increasing number of groups aremore » reporting devices with conversion efficiencies well over 20 % on n-type wafers, Panasonic leading the field with 24.7 %. Exciting results have also been obtained on p-type wafers. Despite these high voltages, important efficiency gains can still be made in fill factor and optical design. This requires improved understanding of carrier transport across device interfaces and reduced parasitic absorption in HJT solar cells. For the latter, several strategies can be followed: Short- wavelength losses can be reduced by replacing the front a-Si:H films with wider-bandgap window layers, such as silicon alloys or even metal oxides. Long-wavelength losses are mitigated by introducing new high-mobility TCO’s such as hydrogenated indium oxide, and also by designing new rear reflectors. Optical shadow losses caused by the front metalisation grid are significantly reduced by replacing printed silver electrodes with fine-line plated copper contacts, leading also to possible cost advantages. The ultimate approach to minimize optical losses is the implementation of back-contacted architectures, which are completely devoid of grid shadow losses and parasitic absorption in the front layers can be minimized irrespective of electrical transport

Synthesis and Characterization of Silicon Nanowires by Electroless Etching

NASA Astrophysics Data System (ADS)

Bhujel, Rabina; Rizal, Umesh; Agarwal, Amit; Swain, Bhabani S.; Swain, Bibhu P.

2018-02-01

Silicon nanowires (SiNWs) were synthesized by two-step electroless etching of p-type Si (100) wafer and characterized by field emission scanning electron microscopy, UV-Vis spectroscopy, x-ray photoelectron spectroscopy, Fourier transform infrared spectroscopy and Raman spectroscopy. The vibrational signature at 1108 and 2087 cm-1 confirmed SiNWs were passivated by both oxygen and hydrogen atoms. Raman peak at 517 cm-1 indicated crystalline SiNWs with tailing toward redshift due to Fano effect. The Si(2p) and Si(2s) core orbital spectra of SiNWs were found at 99.8 and 150.5 eV, respectively. Moreover, the reflection of SiNWs is minimized to 1 to 5% in the 650-nm wavelength.

Silicon micromachined waveguides for millimeter and submillimeter wavelengths

NASA Technical Reports Server (NTRS)

Yap, Markus; Tai, Yu-Chong; Mcgrath, William R.; Walker, Christopher

1992-01-01

The majority of radio receivers, transmitters, and components operating at millimeter and submillimeter wavelengths utilize rectangular waveguides in some form. However, conventional machining techniques for waveguides operating above a few hundred GHz are complicated and costly. This paper reports on the development of silicon micromachining techniques to create silicon-based waveguide circuits which can operate at millimeter and submillimeter wavelengths. As a first step, rectangular WR-10 waveguide structures have been fabricated from (110) silicon wafers using micromachining techniques. The waveguide is split along the broad wall. Each half is formed by first etching a channel completely through a wafer. Potassium hydroxide is used to etch smooth mirror-like vertical walls and LPCVD silicon nitride is used as a masking layer. This wafer is then bonded to another flat wafer using a polyimide bonding technique and diced into the U-shaped half wavelengths. Finally, a gold layer is applied to the waveguide walls. Insertion loss measurements show losses comparable to those of standard metal waveguides. It is suggested that active devices and planar circuits can be integrated with the waveguides, solving the traditional mounting problems. Potential applications in terahertz instrumentation technology are further discussed.

Nanostructure size determination in p-type porous silicon by the use of transmission electron diffraction image processing

NASA Astrophysics Data System (ADS)

Ramirez-Porras, A.

2005-06-01

The structure of p-type porous silicon (PS) has been investigated by the use of transmission electron diffraction (TED) microscopy and image processing. The results suggest the presence of well oriented crystalline phases and polycrystalline phases characterized by random orientation. These phases are believed to be formed by spheres with a mean diameter of 4.3 nm and a standard deviation of 1.3 nm.

Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

NASA Astrophysics Data System (ADS)

Kim, Chihoon; Ahn, Jae Sung; Ji, Taeksoo; Eom, Joo Beom

2017-04-01

We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz-800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis.

Zirconium oxide surface passivation of crystalline silicon

NASA Astrophysics Data System (ADS)

Wan, Yimao; Bullock, James; Hettick, Mark; Xu, Zhaoran; Yan, Di; Peng, Jun; Javey, Ali; Cuevas, Andres

2018-05-01

This letter reports effective passivation of crystalline silicon (c-Si) surfaces by thermal atomic layer deposited zirconium oxide (ZrOx). The optimum layer thickness and activation annealing conditions are determined to be 20 nm and 300 °C for 20 min. Cross-sectional transmission electron microscopy imaging shows an approximately 1.6 nm thick SiOx interfacial layer underneath an 18 nm ZrOx layer, consistent with ellipsometry measurements (˜20 nm). Capacitance-voltage measurements show that the annealed ZrOx film features a low interface defect density of 1.0 × 1011 cm-2 eV-1 and a low negative film charge density of -6 × 1010 cm-2. Effective lifetimes of 673 μs and 1.1 ms are achieved on p-type and n-type 1 Ω cm undiffused c-Si wafers, respectively, corresponding to an implied open circuit voltage above 720 mV in both cases. The results demonstrate that surface passivation quality provided by ALD ZrOx is consistent with the requirements of high efficiency silicon solar cells.

Slicing of silicon into sheet material. Silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project

NASA Technical Reports Server (NTRS)

Holden, S. C.; Fleming, J. R.

1978-01-01

Fabrication of a prototype large capacity multiple blade slurry saw is considered. Design of the bladehead which will tension up to 1000 blades, and cut a 45 cm long silicon ingot as large as 12 cm in diameter is given. The large blade tensioning force of 270,000 kg is applied through two bolts acting on a pair of scissor toggles, significantly reducing operator set-up time. Tests with an upside-down cutting technique resulted in 100% wafering yields and the highest wafer accuracy yet experienced with MS slicing. Variations in oil and abrasives resulted only in degraded slicing results. A technique of continuous abrasive slurry separation to remove silicon debris is described.

The chemo-mechanical effect of cutting fluid on material removal in diamond scribing of silicon

NASA Astrophysics Data System (ADS)

Kumar, Arkadeep; Melkote, Shreyes N.

2017-07-01

The mechanical integrity of silicon wafers cut by diamond wire sawing depends on the damage (e.g., micro-cracks) caused by the cutting process. The damage type and extent depends on the material removal mode, i.e., ductile or brittle. This paper investigates the effect of cutting fluid on the mode of material removal in diamond scribing of single crystal silicon, which simulates the material removal process in diamond wire sawing of silicon wafers. We conducted scribing experiments with a diamond tipped indenter in the absence (dry) and in the presence of a water-based cutting fluid. We found that the cutting mode is more ductile when scribing in the presence of cutting fluid compared to dry scribing. We explain the experimental observations by the chemo-mechanical effect of the cutting fluid on silicon, which lowers its hardness and promotes ductile mode material removal.

Silicon etching using only Oxygen at high temperature: An alternative approach to Si micro-machining on 150 mm Si wafers

NASA Astrophysics Data System (ADS)

Chai, Jessica; Walker, Glenn; Wang, Li; Massoubre, David; Tan, Say Hwa; Chaik, Kien; Hold, Leonie; Iacopi, Alan

2015-12-01

Using a combination of low-pressure oxygen and high temperatures, isotropic and anisotropic silicon (Si) etch rates can be controlled up to ten micron per minute. By varying the process conditions, we show that the vertical-to-lateral etch rate ratio can be controlled from 1:1 isotropic etch to 1.8:1 anisotropic. This simple Si etching technique combines the main respective advantages of both wet and dry Si etching techniques such as fast Si etch rate, stiction-free, and high etch rate uniformity across a wafer. In addition, this alternative O2-based Si etching technique has additional advantages not commonly associated with dry etchants such as avoiding the use of halogens and has no toxic by-products, which improves safety and simplifies waste disposal. Furthermore, this process also exhibits very high selectivity (>1000:1) with conventional hard masks such as silicon carbide, silicon dioxide and silicon nitride, enabling deep Si etching. In these initial studies, etch rates as high as 9.2 μm/min could be achieved at 1150 °C. Empirical estimation for the calculation of the etch rate as a function of the feature size and oxygen flow rate are presented and used as proof of concepts.

Optical surface analysis: a new technique for the inspection and metrology of optoelectronic films and wafers

NASA Astrophysics Data System (ADS)

Bechtler, Laurie; Velidandla, Vamsi

2003-04-01

In response to demand for higher volumes and greater product capability, integrated optoelectronic device processing is rapidly increasing in complexity, benefiting from techniques developed for conventional silicon integrated circuit processing. The needs for high product yield and low manufacturing cost are also similar to the silicon wafer processing industry. This paper discusses the design and use of an automated inspection instrument called the Optical Surface Analyzer (OSA) to evaluate two critical production issues in optoelectronic device manufacturing: (1) film thickness uniformity, and (2) defectivity at various process steps. The OSA measurement instrument is better suited to photonics process development than most equipment developed for conventional silicon wafer processing in two important ways: it can handle both transparent and opaque substrates (unlike most inspection and metrology tools), and it is a full-wafer inspection method that captures defects and film variations over the entire substrate surface (unlike most film thickness measurement tools). Measurement examples will be provided in the paper for a variety of films and substrates used for optoelectronics manufacturing.

Evaluation and verification of epitaxial process sequence for silicon solar-cell production

NASA Technical Reports Server (NTRS)

Redfield, D.

1981-01-01

To achieve the program goals, 28 minimodules were fabricated and tested, using 600 cells made from three-inch-diameter wafers processed by the sequence chosen for this purpose. Of these 600 cells, half were made from epitaxially grown layers on potentially low-cost substrates. The other half were made from commercial semiconductor-grade (SG), single-crystal silicon wafers that served as controls. Cell processing was normally performed on mixed lots containing significant numbers of each of these two types of wafers. After evaluation of the performance of all cells, they were separated by types for incorporation into modules that were to be tested for electrical performance and response to environmental stress. A simplified flow chart displaying this scheme, for quantities representing half of the planned total to be processed, is presented.

Band-to-Band Tunneling Transistors: Scalability and Circuit Performance

DTIC Science & Technology

2013-05-01

to this point. The inability to create GaN ingots as cost effective substrates (or Silicon Carbide ingots coupled with GaN deposition) means that...was vastly different than standard Silicon CMOS (e.g. HEMTs and GaN channel devices were included, but not III-V-channel MOS or Germanium-channel MOS...the same wafer, wafer bonding has been used by Chung et al. to attach GaN to Silicon wafers, where a p-type Si device can be used [15]. Since

Origin of dislocation luminescence centers and their reorganization in p-type silicon crystal subjected to plastic deformation and high temperature annealing.

PubMed

Pavlyk, Bohdan; Kushlyk, Markiyan; Slobodzyan, Dmytro

2017-12-01

Changes of the defect structure of silicon p-type crystal surface layer under the influence of plastic deformation and high temperature annealing in oxygen atmosphere were investigated by deep-level capacitance-modulation spectroscopy (DLCMS) and IR spectroscopy of molecules and atom vibrational levels. Special role of dislocations in the surface layer of silicon during the formation of its energy spectrum and rebuilding the defective structure was established. It is shown that the concentration of linear defects (N ≥ 10 4  cm -2 ) enriches surface layer with electrically active complexes (dislocation-oxygen, dislocation-vacancy, and dislocation-interstitial atoms of silicon) which are an effective radiative recombination centers.

Wet-chemical systems and methods for producing black silicon substrates

DOEpatents

Yost, Vernon; Yuan, Hao-Chih; Page, Matthew

2015-05-19

A wet-chemical method of producing a black silicon substrate. The method comprising soaking single crystalline silicon wafers in a predetermined volume of a diluted inorganic compound solution. The substrate is combined with an etchant solution that forms a uniform noble metal nanoparticle induced Black Etch of the silicon wafer, resulting in a nanoparticle that is kinetically stabilized. The method comprising combining with an etchant solution having equal volumes acetonitrile/acetic acid:hydrofluoric acid:hydrogen peroxide.

Addressable Inverter Matrix Tests Integrated-Circuit Wafer

NASA Technical Reports Server (NTRS)

Buehler, Martin G.

1988-01-01

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Light Enhanced Hydrofluoric Acid Passivation: A Sensitive Technique for Detecting Bulk Silicon Defects

PubMed Central

Grant, Nicholas E.

2016-01-01

A procedure to measure the bulk lifetime (>100 µsec) of silicon wafers by temporarily attaining a very high level of surface passivation when immersing the wafers in hydrofluoric acid (HF) is presented. By this procedure three critical steps are required to attain the bulk lifetime. Firstly, prior to immersing silicon wafers into HF, they are chemically cleaned and subsequently etched in 25% tetramethylammonium hydroxide. Secondly, the chemically treated wafers are then placed into a large plastic container filled with a mixture of HF and hydrochloric acid, and then centered over an inductive coil for photoconductance (PC) measurements. Thirdly, to inhibit surface recombination and measure the bulk lifetime, the wafers are illuminated at 0.2 suns for 1 min using a halogen lamp, the illumination is switched off, and a PC measurement is immediately taken. By this procedure, the characteristics of bulk silicon defects can be accurately determined. Furthermore, it is anticipated that a sensitive RT surface passivation technique will be imperative for examining bulk silicon defects when their concentration is low (<1012 cm-3). PMID:26779939

Critical technology limits to silicon material and sheet production

NASA Technical Reports Server (NTRS)

Leipold, M. H.

1982-01-01

Earlier studies have indicated that expenditures related to the preparation of high-purity silicon and its conversion to silicon sheet represent from 40 to 52 percent of the cost of the entire panel. The present investigation is concerned with the elements which were selected for study in connection with the Flat-Plate Solar Array (FSA) Project. The first of two technologies which are being developed within the FSA Project involves the conversion of metallurgical-grade silicon through a silane purification process to silicon particles. The second is concerned with the conversion of trichlorosilane to dichlorosilane, and the subsequent production of silicon using modified rod reactors of the Siemens type. With respect to silicon sheet preparation, efforts have been focused both on the preparation of ingots, followed by wafering, and the direct crystallization of molten silicon into a ribbon or film.

Study of p-type and intrinsic materials for amorphous silicon based solar cells

NASA Astrophysics Data System (ADS)

Du, Wenhui

This dissertation summarizes the research work on the investigation and optimization of high efficiency hydrogenated amorphous silicon (a-Si:H) based thin film n-i-p single-junction and multi-junction solar cells, deposited using radio frequency (RF) and very high frequency (VHF) plasma enhanced chemical vapor deposition (PECVD) techniques. The fabrication and characterization of high quality p-type and intrinsic materials for a-Si:H based solar cells have been systematically and intensively studied. Hydrogen dilution, substrate temperature, gas flow rate, RF- or VHF-power density, and films deposition time have been optimized to obtain "on-the-edge" materials. To understand the material structure of the silicon p-layer providing a high Voc a-Si:H solar cell, hydrogenated amorphous, protocrystalline, and nanocrystalline silicon p-layers have been prepared using RF-PECVD and characterized by Raman spectroscopy and high resolution transmission electronic microscopy (HRTEM). It was found that the optimum Si:H p-layer for n-i-p a-Si:H solar cells is composed of fine-grained nanocrystals with crystallite sizes in the range of 3-5 nm embedded in an amorphous network. Using the optimized p-layer, an a-Si:H single-junction solar cell with a very high Voc value of 1.042 V and a FF value of 0.74 has been obtained. a-Si:H, a-SiGe:H and nc-Si:H i-layers have been prepared using RF- and VHF-PECVD techniques and monitored by different optical and electrical characterizations. Single-junction a-Si:H, a-SiGe and nc-Si:H cells have been developed and optimized. Intermediate bandgap a-SiGe:H solar cells achieved efficiencies over 12.5%. On the basis of optimized component cells, we achieved a-Si:Hla-SiGe:H tandem solar cells with efficiencies of ˜12.9% and a-Si:H/a-SiGe:H/a-SiGe:H triple-junction cells with efficiencies of ˜12.03%. VHF-PECVD technique was used to increase the deposition rates of the narrow bandgap materials. The deposition rate for a-SiGe:H i-layer attained 9 A

Non-contact defect diagnostics in Cz-Si wafers using resonance ultrasonic vibrations

NASA Astrophysics Data System (ADS)

Belyaev, A.; Kochelap, V. A.; Tarasov, I.; Ostapenko, S.

2001-01-01

A new resonance effect of generation of sub-harmonic acoustic vibrations was applied to characterize defects in as-grown and processed Cz-Si wafers. Ultrasonic vibrations were generated into standard 8″ wafers using an external ultrasonic transducer and their amplitude recorded in a non-contact mode using a scanning acoustic probe. By tuning the frequency, f, of the transducer we observed generation of intense sub-harmonic acoustic mode ("whistle" or w-mode) with f/2 frequency. The characteristics of the w-mode-amplitude dependence, frequency scans, spatial distribution allow a clear distinction versus harmonic vibrations of the same wafer. The origin of sub-harmonic vibrations observed on 8″ Cz-Si wafers is attributed to a parametric resonance of flexural vibrations in thin silicon circular plates. We present evidence that "whistle" effect shows a strong dependence on the wafer's growth and processing history and can be used for quality assurance purposes.

Resonance ultrasonic vibrations in Cz-Si wafers as a possible diagnostic technique in ion implantation

NASA Astrophysics Data System (ADS)

Zhao, Z. Y.; Ostapenko, S.; Anundson, R.; Tvinnereim, M.; Belyaev, A.; Anthony, M.

2001-07-01

The semiconductor industry does not have effective metrology for well implants. The ability to measure such deep level implants will become increasingly important as we progress along the technology road map. This work explores the possibility of using the acoustic whistle effect on ion implanted silicon wafers. The technique detects the elastic stress and defects in silicon wafers by measuring the sub-harmonic f/2 resonant vibrations on a wafer induced via backside contact to create standing waves, which are measured by a non-contact ultrasonic probe. Preliminary data demonstrates that it is sensitive to implant damage, and there is a direct correlation between this sub-harmonic acoustic mode and some of the implant and anneal conditions. This work presents the results of a feasibility study to assess and quantify the correspondent whistle effect to implant damage, residual damage after annealing and intrinsic defects.

Electrostatic bonding of thin (cycle sine 3 mil) 7070 cover glass to Ta2O5 AR-coated thin (cycle sine 2 mil) silicon wafers and solar cells

NASA Technical Reports Server (NTRS)

Egelkrout, D. W.

1981-01-01

Electrostatic bonding of thin cover glass to thin solar cells was researched. Silicon solar cells, wafers, and Corning 7070 glass of from about 0.002" to about 0.003" in thickness were used in the investigation to establish optimum parameters for producing mechanically acceptable bonds while minimizing thermal stresses and resultant solar cell electrical parameter degradation.

Plasma deposition of amorphous silicon carbide thin films irradiated with neutrons

NASA Astrophysics Data System (ADS)

Huran, J.; Bohacek, P.; Kucera, M.; Kleinova, A.; Sasinkova, V.; IEE SAS, Bratislava, Slovakia Team; Polymer Institute, SAS, Bratislava, Slovakia Team; Institute of Chemistry, SAS, Bratislava, Slovakia Team

2015-09-01

Amorphous silicon carbide and N-doped silicon carbide thin films were deposited on P-type Si(100) wafer by plasma enhanced chemical vapor deposition (PECVD) technology using silane, methane, ammonium and argon gases. The concentration of elements in the films was determined by RBS and ERDA method. Chemical compositions were analyzed by FTIR spectroscopy. Photoluminescence properties were studied by photoluminescence spectroscopy (PL). Irradiation of samples with various neutron fluencies was performed at room temperature. The films contain silicon, carbon, hydrogen, nitrogen and small amount of oxygen. From the IR spectra, the films contained Si-C, Si-H, C-H, Si-N, N-H and Si-O bonds. No significance effect on the IR spectra after neutron irradiation was observed. PL spectroscopy results of films showed decreasing PL intensity after neutron irradiation and PL intensity decreased with increased neutron fluencies. The measured current of the prepared structures increased after irradiation with neutrons and rise up with neutron fluencies.

Low-temperature TCT characterization of heavily proton irradiated p-type magnetic Czochralski silicon detectors

NASA Astrophysics Data System (ADS)

Härkönen, J.; Tuovinen, E.; Luukka, P.; Kassamakov, I.; Autioniemi, M.; Tuominen, E.; Sane, P.; Pusa, P.; Räisänen, J.; Eremin, V.; Verbitskaya, E.; Li, Z.

2007-12-01

n +/p -/p + pad detectors processed at the Microelectronics Center of Helsinki University of Technology on boron-doped p-type high-resistivity magnetic Czochralski (MCz-Si) silicon substrates have been investigated by the transient current technique (TCT) measurements between 100 and 240 K. The detectors were irradiated by 9 MeV protons at the Accelerator Laboratory of University of Helsinki up to 1 MeV neutron equivalent fluence of 2×10 15 n/cm 2. In some of the detectors the thermal donors (TD) were introduced by intentional heat treatment at 430 °C. Hole trapping time constants and full depletion voltage values were extracted from the TCT data. We observed that hole trapping times in the order of 10 ns were found in heavily (above 1×10 15 n eq/cm 2) irradiated samples. These detectors could be fully depleted below 500 V in the temperature range of 140-180 K.

Investigation of radiation hardened SOI wafer fabricated by ion-cut technique

NASA Astrophysics Data System (ADS)

Chang, Yongwei; Wei, Xing; Zhu, Lei; Su, Xin; Gao, Nan; Dong, Yemin

2018-07-01

Total ionizing dose (TID) effect on Silicon-on-Insulator (SOI) wafers due to inherent buried oxide (BOX) is a significant concern as it leads to the degradation of electrical properties of SOI-based devices and circuits, even failures of the systems associated with them. This paper reports the radiation hardening implementation of SOI wafer fabricated by ion-cut technique integrated with low-energy Si+ implantation. The electrical properties and radiation response of pseudo-MOS transistors are analyzed. The results demonstrate that the hardening process can significantly improve the TID tolerance of SOI wafers by generating Si nanocrystals (Si-NCs) within the BOX. The presence of Si-NCs created through Si+ implantation is evidenced by high-resolution transmission electron microscopy (HR-TEM). Under the pass gate (PG) irradiation bias, the anti-radiation properties of H-gate SOI nMOSFETs suggest that the radiation hardened SOI wafers with optimized Si implantation dose can perform effectively in a radiation environment. The radiation hardening process provides an excellent way to reinforce the TID tolerance of SOI wafers.

Transparent electrodes in silicon heterojunction solar cells: Influence on contact passivation

DOE PAGES

Tomasi, Andrea; Sahli, Florent; Seif, Johannes Peter; ...

2015-10-26

Charge carrier collection in silicon heterojunction solar cells occurs via intrinsic/doped hydrogenated amorphous silicon layer stacks deposited on the crystalline silicon wafer surfaces. Usually, both the electron and hole collecting stacks are externally capped by an n-type transparent conductive oxide, which is primarily needed for carrier extraction. Earlier, it has been demonstrated that the mere presence of such oxides can affect the carrier recombination in the crystalline silicon absorber. Here, we present a detailed investigation of the impact of this phenomenon on both the electron and hole collecting sides, including its consequences for the operating voltages of silicon heterojunction solarmore » cells. As a result, we define guiding principles for improved passivating contact design for high-efficiency silicon solar cells.« less

Transparent electrodes in silicon heterojunction solar cells: Influence on contact passivation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tomasi, Andrea; Sahli, Florent; Seif, Johannes Peter

Charge carrier collection in silicon heterojunction solar cells occurs via intrinsic/doped hydrogenated amorphous silicon layer stacks deposited on the crystalline silicon wafer surfaces. Usually, both the electron and hole collecting stacks are externally capped by an n-type transparent conductive oxide, which is primarily needed for carrier extraction. Earlier, it has been demonstrated that the mere presence of such oxides can affect the carrier recombination in the crystalline silicon absorber. Here, we present a detailed investigation of the impact of this phenomenon on both the electron and hole collecting sides, including its consequences for the operating voltages of silicon heterojunction solarmore » cells. As a result, we define guiding principles for improved passivating contact design for high-efficiency silicon solar cells.« less

Processing of n+/p-/p+ strip detectors with atomic layer deposition (ALD) grown Al2O3 field insulator on magnetic Czochralski silicon (MCz-si) substrates

NASA Astrophysics Data System (ADS)

Härkönen, J.; Tuovinen, E.; Luukka, P.; Gädda, A.; Mäenpää, T.; Tuominen, E.; Arsenovich, T.; Junkes, A.; Wu, X.; Li, Z.

2016-08-01

Detectors manufactured on p-type silicon material are known to have significant advantages in very harsh radiation environment over n-type detectors, traditionally used in High Energy Physics experiments for particle tracking. In p-type (n+ segmentation on p substrate) position-sensitive strip detectors, however, the fixed oxide charge in the silicon dioxide is positive and, thus, causes electron accumulation at the Si/SiO2 interface. As a result, unless appropriate interstrip isolation is applied, the n-type strips are short-circuited. Widely adopted methods to terminate surface electron accumulation are segmented p-stop or p-spray field implantations. A different approach to overcome the near-surface electron accumulation at the interface of silicon dioxide and p-type silicon is to deposit a thin film field insulator with negative oxide charge. We have processed silicon strip detectors on p-type Magnetic Czochralski silicon (MCz-Si) substrates with aluminum oxide (Al2O3) thin film insulator, grown with Atomic Layer Deposition (ALD) method. The electrical characterization by current-voltage and capacitance-voltage measurement shows reliable performance of the aluminum oxide. The final proof of concept was obtained at the test beam with 200 GeV/c muons. For the non-irradiated detector the charge collection efficiency (CCE) was nearly 100% with a signal-to-noise ratio (S/N) of about 40, whereas for the 2×1015 neq/cm2 proton irradiated detector the CCE was 35%, when the sensor was biased at 500 V. These results are comparable with the results from p-type detectors with the p-spray and p-stop interstrip isolation techniques. In addition, interestingly, when the aluminum oxide was irradiated with Co-60 gamma-rays, an accumulation of negative fixed oxide charge in the oxide was observed.

Fabrication of Cantilever-Bump Type Si Probe Card

NASA Astrophysics Data System (ADS)

Park, Jeong-Yong; Lee, Dong-Seok; Kim, Dong-Kwon; Lee, Jong-Hyun

2000-12-01

Probe card is most important part in the test system which selects the good or bad chip of integrated circuit (IC) chips. Silicon vertical probe card is able to test multiple semiconductor chips simultaneously. We presented cantilever-bump type vertical probe card. It was fabricated by dry etching using RIE(reactive ion etching) technique and porous silicon micromachining using silicon direct bonded (SDB) wafer. Cantilevers and bumps were fabricated by isotropic etching using RIE@. 3-dimensional structures were formed by porous silicon micromachining technique using SDB wafer. Contact resistance of fabricated probe card was less than 2 Ω and its life time was more than 200,000 turns. The process used in this work is very simple and reproducible, which has good controllability in the tip dimension and spacing. It is expected that the fabricated probe card can reduce testing time, can promote productivity and enables burn-in test.

Surface plasmons based terahertz modulator consisting of silicon-air-metal-dielectric-metal layers

NASA Astrophysics Data System (ADS)

Wang, Wei; Yang, Dongxiao; Qian, Zhenhai

2018-05-01

An optically controlled modulator of the terahertz wave, which is composed of a metal-dielectric-metal structure etched with circular loop arrays on both the metal layers and a photoexcited silicon wafer separated by an air layer, is proposed. Simulation results based on experimentally measured complex permittivities predict that modification of complex permittivity of the silicon wafer through excitation laser leads to a significant tuning of transmission characteristics of the modulator, forming the modulation depths of 59.62% and 96.64% based on localized surface plasmon peak and propagating surface plasmon peak, respectively. The influences of the complex permittivity of the silicon wafer and the thicknesses of both the air layer and the silicon wafer are numerically studied for better understanding the modulation mechanism. This study proposes a feasible methodology to design an optically controlled terahertz modulator with large modulation depth, high speed and suitable insertion loss, which is useful for terahertz applications in the future.

Vertically aligned silicon microwire arrays of various lengths by repeated selective vapor-liquid-solid growth of n-type silicon/n-type silicon

NASA Astrophysics Data System (ADS)

Ikedo, Akihito; Kawashima, Takahiro; Kawano, Takeshi; Ishida, Makoto

2009-07-01

Repeated vapor-liquid-solid (VLS) growth with Au and PH3-Si2H6 mixture gas as the growth catalyst and silicon source, respectively, was used to construct n-type silicon/n-type silicon wire arrays of various lengths. Silicon wires of various lengths within an array could be grown by employing second growth over the first VLS grown wire. Additionally, the junction at the interface between the first and the second wires were examined. Current-voltage measurements of the wires exhibited linear behavior with a resistance of 850 Ω, confirming nonelectrical barriers at the junction, while bending tests indicated that the mechanical properties of the wire did not change.

Dip coating process: Silicon sheet growth development for the large-area silicon sheet task of the low-cost silicon solar array project

NASA Technical Reports Server (NTRS)

Heaps, J. D.; Maciolek, R. B.; Harrison, W. B.; Wolner, H. A.; Hendrickson, G.; Nelson, L. D.

1976-01-01

To date, an experimental dip-coating facility was constructed. Using this facility, relatively thin (1 mm) mullite and alumina substrates were successfully dip-coated with 2.5 - 3.0 ohm-cm, p-type silicon with areas of approximately 20 sq cm. The thickness and grain size of these coatings are influenced by the temperature of the melt and the rate at which the substrate is pulled from the melt. One mullite substrate had dendrite-like crystallites of the order of 1 mm wide and 1 to 2 cm long. Their axes were aligned along the direction of pulling. A large variety of substrate materials were purchased or developed enabling the program to commence a substrate definition evaluation. Due to the insulating nature of the substrate, the bottom layer of the p-n junction may have to be made via the top surface. The feasibility of accomplishing this was demonstrated using single crystal wafers.

Influence of the doping level on the porosity of silicon nanowires prepared by metal-assisted chemical etching

NASA Astrophysics Data System (ADS)

Geyer, Nadine; Wollschläger, Nicole; Fuhrmann, Bodo; Tonkikh, Alexander; Berger, Andreas; Werner, Peter; Jungmann, Marco; Krause-Rehberg, Reinhard; Leipner, Hartmut S.

2015-06-01

A systematic method to control the porosity of silicon nanowires is presented. This method is based on metal-assisted chemical etching (MACE) and takes advantage of an HF/H2O2 etching solution and a silver catalyst in the form of a thin patterned film deposited on a doped silicon wafer. It is found that the porosity of the etched nanowires can be controlled by the doping level of the wafer. For low doping concentrations, the wires are primarily crystalline and surrounded by only a very thin layer of porous silicon (pSi) layer, while for highly doped silicon, they are porous in their entire volume. We performed a series of controlled experiments to conclude that there exists a well-defined critical doping concentration separating the crystalline and porous regimes. Furthermore, transmission electron microscopy investigations showed that the pSi has also a crystalline morphology on a length scale smaller than the pore size, determined from positron annihilation lifetime spectroscopy to be mesoscopic. Based on the experimental evidence, we devise a theoretical model of the pSi formation during MACE and apply it for better control of the nanowire morphology.

1.3-microm optically-pumped semiconductor disk laser by wafer fusion.

PubMed

Lyytikäinen, Jari; Rautiainen, Jussi; Toikkanen, Lauri; Sirbu, Alexei; Mereuta, Alexandru; Caliman, Andrei; Kapon, Eli; Okhotnikov, Oleg G

2009-05-25

We report a wafer-fused high power optically-pumped semiconductor disk laser operating at 1.3 microm. An InP-based active medium was fused with a GaAs/AlGaAs distributed Bragg reflector, resulting in an integrated monolithic gain mirror. Over 2.7 W of output power, obtained at temperature of 15 degrees C, represents the best achievement reported to date for this type of lasers. The results reveal an essential advantage of the wafer fusing technique over both monolithically grown AlGaInAs/GaInAsP- and GaInNAs-based structures.

Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

NASA Astrophysics Data System (ADS)

Syed, Ahmed Rashid

Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

Wafer integrated micro-scale concentrating photovoltaics

NASA Astrophysics Data System (ADS)

Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

2017-09-01

Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

Structural, Optical and Electrical Properties of ZnS/Porous Silicon Heterostructures

NASA Astrophysics Data System (ADS)

Wang, Cai-Feng; Li, Qing-Shan; Lv, Lei; Zhang, Li-Chun; Qi, Hong-Xia; Chen, Hou

2007-03-01

ZnS films are deposited by pulsed laser deposition on porous silicon (PS) substrates formed by electrochemical anodization of p-type (100) silicon wafer. Scanning electron microscope images reveal that the surface of ZnS films is unsmoothed, and there are some cracks in the ZnS films due to the roughness of the PS surface. The x-ray diffraction patterns show that the ZnS films on PS surface are grown in preferring orientation along cubic phase β-ZnS (111) direction. White light emission is obtained by combining the blue-green emission from ZnS films with the orange-red emission from PS layers. Based on the I-V characteristic, the ZnS/PS heterojunction exhibits the rectifying junction behaviour, and an ideality factor n is calculated to be 77 from the I-V plot.

Quantification issues of trace metal contaminants on silicon wafers by means of TOF-SIMS, ICP-MS, and TXRF

NASA Astrophysics Data System (ADS)

Rostam-Khani, P.; Hopstaken, M. J. P.; Vullings, P.; Noij, G.; O'Halloran, O.; Claassen, W.

2004-06-01

Measurement of surface metal contamination on silicon wafers is essential for yield enhancement in IC manufacturing. Vapor phase decomposition coupled with either inductively coupled plasma mass spectrometry (VPD-ICP-MS), or total reflection X-ray fluorescence (VPD-TXRF), TXRF and more recently time of flight secondary ion mass spectrometry (TOF-SIMS) are used to monitor surface metal contamination. These techniques complement each other in their respective strengths and weaknesses. For reliable and accurate quantification, so-called relative sensitivity factors (RSF) are required for TOF-SIMS analysis. For quantification purposes in VPD, the collection efficiency (CE) is important to ensure complete collection of contamination. A standard procedure has been developed that combines the determination of these RSFs as well as the collection efficiency using all the analytical techniques mentioned above. Therefore, sample wafers were intentionally contaminated and analyzed (by TOF-SIMS) directly after preparation. After VPD-ICP-MS, several scanned surfaces were analyzed again by TOF-SIMS. Comparing the intensities of the specific metals before and after the VPD-DC procedure on the scanned surface allows the determination of so-called removing efficiency (RE). In general, very good agreement was obtained comparing the four analytical techniques after updating the RSFs for TOF-SIMS. Progress has been achieved concerning the CE evaluation as well as determining the RSFs more precisely for TOF-SIMS.

Prediction and Measurement of Temperature Fields in Silicon-on-Insulator Electronic Circuits

DTIC Science & Technology

1995-08-01

common dimensions are given in Table 1. Almost all of the device power is dissipated in the channel. The electri- cally insulating implanted layer...data. Region or Component substrate Material SOI implanted insulating layers single-crystal silicon, 3 x 1015 boron atoms cm -3 Thermal... implanted silicon-dioxide layer in SOI wafers. The data for each device for varying powers fall near a line originating at P = 0 and T0 = 303 K

New optoelectronic methodology for nondestructive evaluation of MEMS at the wafer level

NASA Astrophysics Data System (ADS)

Furlong, Cosme; Ferguson, Curtis F.; Melson, Michael J.

2004-02-01

One of the approaches to fabrication of MEMS involves surface micromachining to define dies on single crystal silicon wafers, dicing of the wafers to separate the dies, and electronic packaging of the individual dies. Dicing and packaging of MEMS accounts for a large fraction of the fabrication costs, therefore, nondestructive evaluation at the wafer level, before dicing, can have significant implications on improving production yield and costs. In this paper, advances in development of optoelectronic holography (OEH) techniques for nondestructive, noninvasive, full-field of view evaluation of MEMS at the wafer level are described. With OEH techniques, quantitative measurements of shape and deformation of MEMS, as related to their performance and integrity, are obtained with sub-micrometer spatial resolution and nanometer measuring accuracy. To inspect an entire wafer with OEH methodologies, measurements of overlapping regions of interest (ROI) on a wafer are recorded and adjacent ROIs are stitched together through efficient 3D correlation analysis algorithms. Capabilities of the OEH techniques are illustrated with representative applications, including determination of optimal inspection conditions to minimize inspection time while achieving sufficient levels of accuracy and resolution.

Low temperature InP /Si wafer bonding using boride treated surface

NASA Astrophysics Data System (ADS)

Huang, Hui; Ren, Xiaomin; Wang, Wenjuan; Song, Hailan; Wang, Qi; Cai, Shiwei; Huang, Yongqing

2007-04-01

An approach for InP /Si wafer bonding based on boride-solution treatment was presented. The bonding energy is higher than the InP fracture energy by annealing at 280°C. An In0.53Ga0.47As/InP multiple-quantum-well (MQW) structure grown on InP was transferred onto Si substrate via the bonding process. X-ray diffraction and photoluminescence reveal that crystal quality of the bonded MQW was preserved. A thin B2O3-POx-SiO2 oxide layer of about 28nm thick at the bonding interface was detected. X-ray photoelectron spectroscopy and Raman analyses indicate that the formation of oxygen bridging bonds by boride treatment is responsible for the strong fusion obtained at such low temperature.

Performance and temperature dependencies of proton irradiated n/p and p/n GaAs and n/p silicon cells

NASA Technical Reports Server (NTRS)

Weinberg, I.; Swartz, C. K.; Hart, R. E., Jr.

1985-01-01

n/p homojunction GaAs cells are found to be more radiation resistant than p/n heteroface GaAs under 10 MeV proton irradiation. Both GaAs cell types outperform conventional silicon n/p cells under the same conditions. An increased temperature dependency of maximum power for the GaAs n/p cells is attributed to differences in Voc between the two GaAs cell types. These results and diffusion length considerations are consistent with the conclusion that p-type GaAs is more radiation resistant than n-type and therefore that the n/p configuration is possibly favored for use in the space radiation environment. However, it is concluded that additional work is required in order to choose between the two GaAs cell configurations.

Hybrid integrated single-wavelength laser with silicon micro-ring reflector

NASA Astrophysics Data System (ADS)

Ren, Min; Pu, Jing; Krishnamurthy, Vivek; Xu, Zhengji; Lee, Chee-Wei; Li, Dongdong; Gonzaga, Leonard; Toh, Yeow T.; Tjiptoharsono, Febi; Wang, Qian

2018-02-01

A hybrid integrated single-wavelength laser with silicon micro-ring reflector is demonstrated theoretically and experimentally. It consists of a heterogeneously integrated III-V section for optical gain, an adiabatic taper for light coupling, and a silicon micro-ring reflector for both wavelength selection and light reflection. Heterogeneous integration processes for multiple III-V chips bonded to an 8-inch Si wafer have been developed, which is promising for massive production of hybrid lasers on Si. The III-V layer is introduced on top of a 220-nm thick SOI layer through low-temperature wafer-boning technology. The optical coupling efficiency of >85% between III-V and Si waveguide has been achieved. The silicon micro-ring reflector, as the key element of the hybrid laser, is studied, with its maximized reflectivity of 85.6% demonstrated experimentally. The compact single-wavelength laser enables fully monolithic integration on silicon wafer for optical communication and optical sensing application.

Investigation of direct current electrical properties of electrochemically etched mesoporous silicon carbide

NASA Astrophysics Data System (ADS)

Gautier, G.; Biscarrat, J.; Defforge, T.; Fèvre, A.; Valente, D.; Gary, A.; Menard, S.

2014-12-01

In this study, we show I-V characterizations of various metal/porous silicon carbide (pSiC)/silicon carbide (SiC) structures. SiC wafers were electrochemically etched from the Si and C faces in the dark or under UV lighting leading to different pSiC morphologies. In the case of low porosity pSiC etched in the dark, the I-V characteristics were found to be almost linear and the extracted resistivities of pSiC were around 1.5 × 104 Ω cm at 30 °C for the Si face. This is around 6 orders of magnitude higher than the resistivity of doped SiC wafers. In the range of 20-200 °C, the activation energy was around 50 meV. pSiC obtained from the C face was less porous and the measured average resistivity was 10 Ω cm. In the case high porosity pSiC etched under UV illumination, the resistivity was found to be much higher, around 1014 Ω cm at room temperature. In this case, the extracted activation energy was estimated to be 290 meV.

CuO-Functionalized Silicon Photoanodes for Photoelectrochemical Water Splitting Devices.

PubMed

Shi, Yuanyuan; Gimbert-Suriñach, Carolina; Han, Tingting; Berardi, Serena; Lanza, Mario; Llobet, Antoni

2016-01-13

One main difficulty for the technological development of photoelectrochemical (PEC) water splitting (WS) devices is the fabrication of active, stable and cost-effective photoelectrodes that ensure high performance. Here, we report the development of a CuO/Silicon based photoanode, which shows an onset potential for the water oxidation of 0.53 V vs SCE at pH 9, that is, an overpotential of 75 mV, and high stability above 10 h. These values account for a photovoltage of 420 mV due to the absorbed photons by silicon, as proven by comparing with analogous CuO/FTO electrodes that are not photoactive. The photoanodes have been fabricated by sputtering a thin film of Cu(0) on commercially available n-type Si wafers, followed by a photoelectrochemical treatment in basic pH conditions. The resulting CuO/Cu layer acts as (1) protective layer to avoid the corrosion of nSi, (2) p-type hole conducting layer for efficient charge separation and transportation, and (3) electrocatalyst to reduce the overpotential of the water oxidation reaction. The low cost, low toxicity, and good performance of CuO-based coatings can be an attractive solution to functionalize unstable materials for solar energy conversion.

High-alignment-accuracy transfer printing of passive silicon waveguide structures.

PubMed

Ye, Nan; Muliuk, Grigorij; Trindade, Antonio Jose; Bower, Chris; Zhang, Jing; Uvin, Sarah; Van Thourhout, Dries; Roelkens, Gunther

2018-01-22

We demonstrate the transfer printing of passive silicon devices on a silicon-on-insulator target waveguide wafer. Adiabatic taper structures and directional coupler structures were designed for 1310 nm and 1600 nm wavelength coupling tolerant for ± 1 µm misalignment. The release of silicon devices from the silicon substrate was realized by underetching the buried oxide layer while protecting the back-end stack. Devices were successfully picked by a PDMS stamp, by breaking the tethers that kept the silicon coupons in place on the source substrate, and printed with high alignment accuracy on a silicon photonic target wafer. Coupling losses of -1.5 +/- 0.5 dB for the adiabatic taper at 1310 nm wavelength and -0.5 +/- 0.5 dB for the directional coupler at 1600 nm wavelength are obtained.

Silicon materials task of the low-cost solar array project. Phase 4: Effects of impurities and processing on silicon solar cells

NASA Technical Reports Server (NTRS)

Hopkins, R. H.; Hanes, M. H.; Davis, J. R.; Rohatgi, A.; Raichoudhury, P.; Mollenkopf, H. C.

1981-01-01

The results of the study form a basis for silicon producers, wafer manufacturers, and cell fabricators to develop appropriate cost-benefit relationships for the use of less pure, less costly solar grade silicon. Cr is highly mobile in silicon even at temperatures as low as 600 C. Contrasting with earlier data for Mo, Ti, and V, Cr concentrations vary from place to place in polycrystalline silicon wafers and the electrically-active Cr concentration in the polysilicon is more than an order of magnitude smaller than would be projected from single crystal impurity data. We hypothesize that Cr diffuses during ingot cooldown after growth, preferentially segregates to grain and becomes electrically deactivated. Accelerated aging data from Ni-contaminated silicon imply that no significant impurity-induced cell performance reduction should be expected over a twenty year device lifetime.

Optimizing photon-pair generation electronically using a p-i-n diode incorporated in a silicon microring resonator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Savanier, Marc, E-mail: msavanier@eng.ucsd.edu; Kumar, Ranjeet; Mookherjea, Shayan, E-mail: smookherjea@eng.ucsd.edu

Silicon photonic microchips may be useful for compact, inexpensive, room-temperature optically pumped photon-pair sources, which unlike conventional photon-pair generators based on crystals or optical fibers, can be manufactured using CMOS-compatible processes on silicon wafers. It has been shown that photon pairs can be created in simple structures such as microring resonators at a rate of a few hundred kilohertz using less than a milliwatt of optical pump power, based on the process of spontaneous four-wave mixing. To create a practical photon-pair source, however, also requires some way of monitoring the device and aligning the pump wavelength when the temperature varies,more » since silicon resonators are highly sensitive to temperature. In fact, monitoring photodiodes are standard components in classical laser diodes, but the incorporation of germanium or InGaAs photodiodes would raise the cost and fabrication complexity. Here, we present a simple and effective all-electronic technique for finding the optimum operating point for the microring used to generate photon pairs, based on measuring the reverse-biased current in a silicon p-i-n junction diode fabricated across the waveguide that constitutes the silicon microring. We show that by monitoring the current, and using it to tune the pump laser wavelength, the photon-pair generation properties of the microring can be preserved over a temperature range of more than 30 °C.« less

Fabrication of silicon films from patterned protruded seeds

NASA Astrophysics Data System (ADS)

Zeng, Huang; Zhang, Wei; Li, Jizhou; Wang, Cong; Yang, Hui; Chen, Yigang; Chen, Xiaoyuan; Liu, Dongfang

2017-05-01

Thin, flexible silicon crystals are starting up applications such as light-weighted flexible solar cells, SOI, flexible IC chips, 3D ICs imagers and 3D CMOS imagers on the demand of high performance with low cost. Kerfless wafering technology by direct conversion of source gases into mono-crystalline wafers on reusable substrates is highly cost-effective and feedstock-effective route to cheap wafers with the thickness down to several microns. Here we show a prototype for direct conversion of silicon source gases to wafers by using the substrate with protruded seeds. A reliable and controllable method of wafer-scaled preparation of protruded seed patterns has been developed by filling liquid wax into a rod array as the mask for the selective removal of oxide layer on the rod head. Selectively epitaxial growth is performed on the protruded seeds, and the voidless film is formed by the merging of neighboring seeds through growing. And structured hollows are formed between the grown film and the substrate, which would offer the transferability of the grown film and the reusability of the protruded seeds.

Fabrication of SOI structures with buried cavities using Si wafer direct bonding and electrochemical etch-stop

NASA Astrophysics Data System (ADS)

Chung, Gwiy-Sang

2003-10-01

This paper describes the fabrication of SOI structures with buried cavities using SDB and electrochemical etch-stop. These methods are suitable for thick membrane fabrication with accurate thickness, uniformity, and flatness. After a feed-through hole for supplied voltage and buried cavities was formed on a handle Si wafer with p-type, the handle wafer was bonded to an active Si wafer consisting of a p-type substrate with an n-type epitaxial layer corresponding to membrane thickness. The bonded pair was then thinned until electrochemical etch-stop occurred at the pn junction during electrochemical etchback. By using the SDB SOI structure with buried cavities, active membranes, which have a free standing structure with a dimension of 900×900 μm2, were fabricated. It is confirmed that the fabrication process of the SDB SOI structure with buried cavities is a powerful and versatile technology for new MEMS applications.

Correlation of 150-mm silicon wafer site flatness with stepper performance for deep submicron applications

NASA Astrophysics Data System (ADS)

Huff, Howard R.; Vigil, Joseph C.; Kuyel, Birol; Chan, David Y.; Nguyen, Long P.

1992-06-01

An experimental study was conducted to correlate wafer site flatness SFQD with stepper performance for half-micron lines and spaces. CD measurements were taken on wafers patterned on both GCA pre-production XLS i-line and SVGL Micrascan-90 DUV steppers as well as focus measurements on the Micrascan-90. Wafer site flatness SFQD less than 0.3 micrometers was observed to be a sufficiently small variable in CD non-uniformities for these initial half-micron stepper applications.

Carbon dioxide capture using resin-wafer electrodeionization

DOEpatents

Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

2015-09-08

The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

Fabrication of Silicon Backshorts with Improved Out-of-Band Rejection for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

Boron Partitioning Coefficient above Unity in Laser Crystallized Silicon.

PubMed

Lill, Patrick C; Dahlinger, Morris; Köhler, Jürgen R

2017-02-16

Boron pile-up at the maximum melt depth for laser melt annealing of implanted silicon has been reported in numerous papers. The present contribution examines the boron accumulation in a laser doping setting, without dopants initially incorporated in the silicon wafer. Our numerical simulation models laser-induced melting as well as dopant diffusion, and excellently reproduces the secondary ion mass spectroscopy-measured boron profiles. We determine a partitioning coefficient k p above unity with k p = 1 . 25 ± 0 . 05 and thermally-activated diffusivity D B , with a value D B ( 1687 K ) = ( 3 . 53 ± 0 . 44 ) × 10 - 4 cm 2 ·s - 1 of boron in liquid silicon. For similar laser parameters and process conditions, our model predicts the anticipated boron profile of a laser doping experiment.

Method for forming silicon on a glass substrate

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method by which single-crystal silicon microelectronics may be fabricated on glass substrates at unconventionally low temperatures. This is achieved by fabricating a thin film of silicon on glass and subsequently forming the doped components by a short wavelength (excimer) laser doping procedure and conventional patterning techniques. This method may include introducing a heavily boron doped etch stop layer on a silicon wafer using an excimer laser, which permits good control of the etch stop layer removal process. This method additionally includes dramatically reducing the remaining surface roughness of the silicon thin films after etching in the fabrication of silicon on insulator wafers by scanning an excimer laser across the surface of the silicon thin film causing surface melting, whereby the surface tension of the melt causes smoothing of the surface during recrystallization. Applications for this method include those requiring a transparent or insulating substrate, such as display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard and high temperature electronics.

Method for forming silicon on a glass substrate

DOEpatents

McCarthy, A.M.

1995-03-07

A method by which single-crystal silicon microelectronics may be fabricated on glass substrates at unconventionally low temperatures. This is achieved by fabricating a thin film of silicon on glass and subsequently forming the doped components by a short wavelength (excimer) laser doping procedure and conventional patterning techniques. This method may include introducing a heavily boron doped etch stop layer on a silicon wafer using an excimer laser, which permits good control of the etch stop layer removal process. This method additionally includes dramatically reducing the remaining surface roughness of the silicon thin films after etching in the fabrication of silicon on insulator wafers by scanning an excimer laser across the surface of the silicon thin film causing surface melting, whereby the surface tension of the melt causes smoothing of the surface during recrystallization. Applications for this method include those requiring a transparent or insulating substrate, such as display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard and high temperature electronics. 15 figs.

High-efficiency impurity activation by precise control of cooling rate during atmospheric pressure thermal plasma jet annealing of 4H-SiC wafer

NASA Astrophysics Data System (ADS)

Maruyama, Keisuke; Hanafusa, Hiroaki; Ashihara, Ryuhei; Hayashi, Shohei; Murakami, Hideki; Higashi, Seiichiro

2015-06-01

We have investigated high-temperature and rapid annealing of a silicon carbide (SiC) wafer by atmospheric pressure thermal plasma jet (TPJ) irradiation for impurity activation. To reduce the temperature gradient in the SiC wafer, a DC current preheating system and the lateral back-and-forth motion of the wafer were introduced. A maximum surface temperature of 1835 °C within 2.4 s without sample breakage was achieved, and aluminum (Al), phosphorus (P), and arsenic (As) activations in SiC were demonstrated. We have investigated precise control of heating rate (Rh) and cooling rate (Rc) during rapid annealing of P+-implanted 4H-SiC and its impact on impurity activation. No dependence of resistivity on Rh was observed, while increasing Rc significantly decreased resistivity. A minimum resistivity of 0.0025 Ω·cm and a maximum carrier concentration of 2.9 × 1020 cm-3 were obtained at Rc = 568 °C/s.

Temperature Dependent Electrical Properties of PZT Wafer

NASA Astrophysics Data System (ADS)

Basu, T.; Sen, S.; Seal, A.; Sen, A.

2016-04-01

The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

Characterization of Carrier Concentration and Mobility in n-type SiC Wafers Using Infrared Reflectance Spectroscopy

NASA Astrophysics Data System (ADS)

Narita, Katsutoshi; Hijikata, Yasuto; Yaguchi, Hiroyuki; Yoshida, Sadafumi; Nakashima, Shinichi

2004-08-01

We have estimated the free-carrier concentration and drift mobility in n-type 6H-SiC wafers in the carrier concentration range of 1017-1019 cm-3 from far- and mid-infrared (30-2000 cm-1) reflectance spectra obtained at room temperature. A modified classical dielectric function model was employed for the analysis. We found good agreement between the electrical properties derived from infrared reflectance spectroscopy and those derived from Hall effect measurements. We have demonstrated the spatial mapping of carrier concentration and mobility for commercially produced 2 inch SiC wafers.

Fabrication of optical filters using multilayered porous silicon

NASA Astrophysics Data System (ADS)

Gaber, Noha; Khalil, Diaa; Shaarawi, Amr

2011-02-01

In this work we describe a method for fabricating optical filters using multilayered porous silicon 1D photonic structure. An electrochemical cell is constructed to control the porosity of variable layers in p-type Si wafers. Porous silicon multilayered structures are formed of λ/4 (or multiples) thin films that construct optical interference filters. By changing the anodizing current density of the cell during fabrication, different porosities can be obtained as the optical refractive index is a direct function of the layer porosity. To determine the morphology, the wavelength dependent refractive index n and absorption coefficient α, first, porous silicon free standing mono-layers have been fabricated at different conditions and characterized in the near infrared region (from 1000 to 2500nm). Large difference in refractive index (between 1.6 and 2.6) is obtained. Subsequently, multilayer structures have been fabricated and tested. Their spectral response has been measured and it shows good agreement with numerical simulations. A technique based on inserting etching breaks is adopted to ensure the depth homogeneity. The effect of differing etching/break times on the reproducibility of the filters is studied.

Strategy optimization for mask rule check in wafer fab

NASA Astrophysics Data System (ADS)

Yang, Chuen Huei; Lin, Shaina; Lin, Roger; Wang, Alice; Lee, Rachel; Deng, Erwin

2015-07-01

Photolithography process is getting more and more sophisticated for wafer production following Moore's law. Therefore, for wafer fab, consolidated and close cooperation with mask house is a key to achieve silicon wafer success. However, generally speaking, it is not easy to preserve such partnership because many engineering efforts and frequent communication are indispensable. The inattentive connection is obvious in mask rule check (MRC). Mask houses will do their own MRC at job deck stage, but the checking is only for identification of mask process limitation including writing, etching, inspection, metrology, etc. No further checking in terms of wafer process concerned mask data errors will be implemented after data files of whole mask are composed in mask house. There are still many potential data errors even post-OPC verification has been done for main circuits. What mentioned here are the kinds of errors which will only occur as main circuits combined with frame and dummy patterns to form whole reticle. Therefore, strategy optimization is on-going in UMC to evaluate MRC especially for wafer fab concerned errors. The prerequisite is that no impact on mask delivery cycle time even adding this extra checking. A full-mask checking based on job deck in gds or oasis format is necessary in order to secure acceptable run time. Form of the summarized error report generated by this checking is also crucial because user friendly interface will shorten engineers' judgment time to release mask for writing. This paper will survey the key factors of MRC in wafer fab.

Silicon release coating, method of making same, and method of using same

DOEpatents

Jonczyk, Ralf [Wilmington, DE

2011-11-22

A method of making a release coating includes the following steps: forming a mixture that includes (a) solid components comprising (i) 20-99% silicon by weight and (ii) 1-80% silicon nitride by weight and (b) a solvent; applying the mixture to an inner portion of a crucible or graphite board adapted to form an ingot or wafer comprising silicon; and annealing the mixture in a nitrogen atmosphere at a temperature ranging from 1000 to 2000.degree. C. The invention may also relate to release coatings and methods of making a silicon ingot or wafer including the use of a release coating.

Study and development of non-aqueous silicon-air battery

NASA Astrophysics Data System (ADS)

Cohn, Gil; Ein-Eli, Yair

Silicon-air battery utilizing a single-crystal heavily doped n-type silicon wafer anode and an air cathode is reported in this paper. The battery employs hydrophilic 1-ethyl-3-methylimidazolium oligofluorohydrogenate [EMI·(HF) 2.3F] room temperature ionic liquid electrolyte. Electrochemical studies, including polarization and galvanostatic experiments, performed on various silicon types reveal the predominance performance of heavily doped n-type. Cell discharging at constant current densities of 10, 50, 100 and 300 μA cm -2 in ambient atmosphere, shows working voltages of 1.1-0.8 V. The study shows that as discharge advances, the moist interface of the air electrode is covered by discharge products, which prevent a continuous diffusion of oxygen to the electrode-electrolyte interface. The oxygen suffocation, governed by the settlement of the cell reaction products, is the main factor for an early failure of the cells. Based on the results obtained from scanning electron microscopy, energy-dispersive X-ray spectroscopy and X-ray photoelectron spectroscopy studies, we propose a series of reactions governing the discharge process in silicon-air batteries, as well as a detailed mechanism for silicon oxide deposition on the air electrode porous carbon.

Validation of Direct Analysis Real Time source/Time-of-Flight Mass Spectrometry for organophosphate quantitation on wafer surface.

PubMed

Hayeck, Nathalie; Ravier, Sylvain; Gemayel, Rachel; Gligorovski, Sasho; Poulet, Irène; Maalouly, Jacqueline; Wortham, Henri

2015-11-01

Microelectronic wafers are exposed to airborne molecular contamination (AMC) during the fabrication process of microelectronic components. The organophosphate compounds belonging to the dopant group are one of the most harmful groups. Once adsorbed on the wafer surface these compounds hardly desorb and could diffuse in the bulk of the wafer and invert the wafer from p-type to n-type. The presence of these compounds on wafer surface could have electrical effect on the microelectronic components. For these reasons, it is of importance to control the amount of these compounds on the surface of the wafer. As a result, a fast quantitative and qualitative analytical method, nondestructive for the wafers, is needed to be able to adjust the process and avoid the loss of an important quantity of processed wafers due to the contamination by organophosphate compounds. Here we developed and validated an analytical method for the determination of organic compounds adsorbed on the surface of microelectronic wafers using the Direct Analysis in Real Time-Time of Flight-Mass Spectrometry (DART-ToF-MS) system. Specifically, the developed methodology concerns the organophosphate group. Copyright © 2015 Elsevier B.V. All rights reserved.

Efficiency of silicon solar cells containing chromium

DOEpatents

Frosch, Robert A. Administrator of the National Aeronautics and Space; Salama, Amal M.

1982-01-01

Efficiency of silicon solar cells containing about 10.sup.15 atoms/cm.sup.3 of chromium is improved about 26% by thermal annealing of the silicon wafer at a temperature of 200.degree. C. to form chromium precipitates having a diameter of less than 1 Angstrom. Further improvement in efficiency is achieved by scribing laser lines onto the back surface of the wafer at a spacing of at least 0.5 mm and at a depth of less than 13 micrometers to preferentially precipitate chromium near the back surface and away from the junction region of the device. This provides an economical way to improve the deleterious effects of chromium, one of the impurities present in metallurgical grade silicon material.

High performance InAs quantum dot lasers on silicon substrates by low temperature Pd-GaAs wafer bonding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Zihao; Preble, Stefan F.; Yao, Ruizhe

2015-12-28

InAs quantum dot (QD) laser heterostructures have been grown by molecular beam epitaxy system on GaAs substrates, and then transferred to silicon substrates by a low temperature (250 °C) Pd-mediated wafer bonding process. A low interfacial resistivity of only 0.2 Ω cm{sup 2} formed during the bonding process is characterized by the current-voltage measurements. The InAs QD lasers on Si exhibit comparable characteristics to state-of-the-art QD lasers on silicon substrates, where the threshold current density J{sub th} and differential quantum efficiency η{sub d} of 240 A/cm{sup 2} and 23.9%, respectively, at room temperature are obtained with laser bars of cavity length and waveguide ridgemore » of 1.5 mm and 5 μm, respectively. The InAs QD lasers also show operation up to 100 °C with a threshold current density J{sub th} and differential quantum efficiency η{sub d} of 950 A/cm{sup 2} and 9.3%, respectively. The temperature coefficient T{sub 0} of 69 K from 60 to 100 °C is characterized from the temperature dependent J{sub th} measurements.« less

KEY COMPARISON: CCQM-K32 key comparison and P84 pilot study: Amount of silicon oxide as a thickness of SiO2 on Si

NASA Astrophysics Data System (ADS)

Seah, M. P.

2008-01-01

CCQM-K32 and P84 were conducted following the pilot study P-38 to demonstrate and document the capability of interested National Metrology Institutes to measure the amount of silicon oxide on silicon wafers expressed as a thickness of SiO2 for nominal thicknesses in the range 1.5 nm to 8 nm. 'Amount of substance' may be expressed in many ways and here the measurand is the thickness of the silicon oxide layer on each of a total of 9 samples of nominal thicknesses in the range 1.5 to 8 nm on (100) and (111) Si substrates, expressed as the thickness of SiO2. This report presents the results from K32 and P84. It includes the data received for the measured values and their associated uncertainties, at 95% confidence, for the 9 samples prior to the deadline for receipt of data. The materials are grown by thermal oxidation in very clean furnaces designed for high quality gate oxides on Si wafers in European and US facilities at the same time as those for the pilot study, P-38. Separate samples were provided to each institute in special containers limiting the carbonaceous contamination to below about 0.3 nm. The 9 samples included 5 samples of ultra-thin SiO2 on (100) orientated wafers of Si and 4 samples of ultra-thin SiO2 on (111) orientated wafers of Si. The measurements from the 11 participating laboratories were conducted using ellipsometry, neutron reflectivity (NR), x-ray photoelectron spectroscopy (XPS) or x-ray reflectivity measurements (XRR), guided by the protocol developed in the pilot study P-38 and reproduced in the Appendix. The measurements are given in tables 2 and 3. A very small correction is then made for the different samples that each laboratory received as in table 4. Where appropriate, method offset values deduced from the pilot study P-38 are given in table 5 leading to comparative data in tables 6 and 7. Values for the key comparison reference values (KCRVs) and their associated uncertainties are made from the weighted means and the expanded

Silicon solar cell process development, fabrication and analysis

NASA Technical Reports Server (NTRS)

Yoo, H. I.; Iles, P. A.; Leung, D. C.

1981-01-01

Solar cells were fabricated from EFG ribbons dendritic webs, cast ingots by heat exchanger method, and cast ingots by ubiquitous crystallization process. Baseline and other process variations were applied to fabricate solar cells. EFG ribbons grown in a carbon-containing gas atmosphere showed significant improvement in silicon quality. Baseline solar cells from dendritic webs of various runs indicated that the quality of the webs under investigation was not as good as the conventional CZ silicon, showing an average minority carrier diffusion length of about 60 um versus 120 um of CZ wafers. Detail evaluation of large cast ingots by HEM showed ingot reproducibility problems from run to run and uniformity problems of sheet quality within an ingot. Initial evaluation of the wafers prepared from the cast polycrystalline ingots by UCP suggested that the quality of the wafers from this process is considerably lower than the conventional CZ wafers. Overall performance was relatively uniform, except for a few cells which showed shunting problems caused by inclusions.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, A.M.

1997-10-07

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50 C or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense. 57 figs.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, Anthony M.

1997-01-01

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50.degree. C. or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense.

Fabrication of a Silicon Backshort Assembly for Waveguide-Coupled Superconducting Detectors

NASA Technical Reports Server (NTRS)

Crowe, Erik J.; Bennett, Charles L.; Chuss, David T.; Denis, Kevin L.; Eimer, Joseph; Lourie, Nathan; Marriage, Tobias; Moseley, Samuel H.; Rostem, Karwan; Stevenson, Thomas R.;

High-Efficiency Thin-Film Silicon-on-GaP Solar Cell for Improved Radiation Resistance.

DTIC Science & Technology

1987-09-01

UNCLASSIFIED MyUM 21 LIX E / 82H M D 132 11111_Lt5l1. t FILE UPI" AD-A190 268 AFWAL-TR-87-2070 HIGH-EFFICIENCY THIN- FILM SILICON-ON-GaP SOLAR CELL...EFFICIENCY THIN- FILM SILICON-ON-GaP SOLAR CELL FOR IMPROVED RADIATION RESISTANCE 12. PERSONAL AUTHOR(S) JEROME S. CULIK 13a. TYPE OF REPORT 13b. TIME...C tinue on reverse if necessary and identify by block number) 10 01 SILICONs THIN* FILM , . HETEROEPITAXIAL, RADIATION, 10 01 i GALLIUM PHOSPHIDE 19

1D silicon refractive lenses for surface scattering with high energy x-rays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bertram, F.; Gutowski, O.; Schroer, C.

2016-07-27

At the high energy X-ray beamline P07 at PETRA III, 1D focusing down to 4 micrometer vertical beam height while preserving a horizontal beam width of 0.5 mm was established by refractive lenses etched into a silicon wafer. A single wafer with 8 different lens structures can cover the full energy range between 50 and 120 keV. For surface diffraction on ultrathin films a factor of 4 in intensity can be achieved compared to the already established Al-compound refractive 2D-lenses.

Silicon Technologies Adjust to RF Applications

NASA Technical Reports Server (NTRS)

Reinecke Taub, Susan; Alterovitz, Samuel A.

1994-01-01

Silicon (Si), although not traditionally the material of choice for RF and microwave applications, has become a serious challenger to other semiconductor technologies for high-frequency applications. Fine-line electron- beam and photolithographic techniques are now capable of fabricating silicon gate sizes as small as 0.1 micron while commonly-available high-resistivity silicon wafers support low-loss microwave transmission lines. These advances, coupled with the recent development of silicon-germanium (SiGe), arm silicon integrated circuits (ICs) with the speed required for increasingly higher-frequency applications.

Performance and temperature dependencies of proton irradiated n/p GaAs and n/p silicon cells

NASA Technical Reports Server (NTRS)

Weinberg, I.; Swartz, C. K.; Hart, R. E., Jr.

1985-01-01

The n/p homojunction GaAs cell is found to be more radiation resistant than p/nheteroface GaAs under 10 MeV proton irradiation. Both GaAs cell types outperform conventional silicon n/p cells under the same conditions. An increase temperature dependency of maximum power for the GaAs n/p cells is attributed largely to differences in Voc between the two GaAs cell types. These results and diffusion length considerations are consistent with the conclusion that p-type GaAs is more radiation resistant than n-type and therefore that the n/p configuration is possibly favored for use in the space radiation environment. However, it is concluded that additional work is required in order to choose between the two GaAs cell configurations.

Low loss poly-silicon for high performance capacitive silicon modulators.

PubMed

Douix, Maurin; Baudot, Charles; Marris-Morini, Delphine; Valéry, Alexia; Fowler, Daivid; Acosta-Alba, Pablo; Kerdilès, Sébastien; Euvrard, Catherine; Blanc, Romuald; Beneyton, Rémi; Souhaité, Aurélie; Crémer, Sébastien; Vulliet, Nathalie; Vivien, Laurent; Boeuf, Frédéric

2018-03-05

Optical properties of poly-silicon material are investigated to be integrated in new silicon photonics devices, such as capacitive modulators. Test structure fabrication is done on 300 mm wafer using LPCVD deposition: 300 nm thick amorphous silicon layers are deposited on thermal oxide, followed by solid phase crystallization anneal. Rib waveguides are fabricated and optical propagation losses measured at 1.31 µm. Physical analysis (TEM ASTAR, AFM and SIMS) are used to assess the origin of losses. Optimal deposition and annealing conditions have been defined, resulting in 400 nm-wide rib waveguides with only 9.2-10 dB/cm losses.

All silicon electrode photocapacitor for integrated energy storage and conversion.

PubMed

Cohn, Adam P; Erwin, William R; Share, Keith; Oakes, Landon; Westover, Andrew S; Carter, Rachel E; Bardhan, Rizia; Pint, Cary L

2015-04-08

We demonstrate a simple wafer-scale process by which an individual silicon wafer can be processed into a multifunctional platform where one side is adapted to replace platinum and enable triiodide reduction in a dye-sensitized solar cell and the other side provides on-board charge storage as an electrochemical supercapacitor. This builds upon electrochemical fabrication of dual-sided porous silicon and subsequent carbon surface passivation for silicon electrochemical stability. The utilization of this silicon multifunctional platform as a combined energy storage and conversion system yields a total device efficiency of 2.1%, where the high frequency discharge capability of the integrated supercapacitor gives promise for dynamic load-leveling operations to overcome current and voltage fluctuations during solar energy harvesting.

Scale-dependent diffusion anisotropy in nanoporous silicon

PubMed Central

Kondrashova, Daria; Lauerer, Alexander; Mehlhorn, Dirk; Jobic, Hervé; Feldhoff, Armin; Thommes, Matthias; Chakraborty, Dipanjan; Gommes, Cedric; Zecevic, Jovana; de Jongh, Petra; Bunde, Armin; Kärger, Jörg; Valiullin, Rustem

2017-01-01

Nanoporous silicon produced by electrochemical etching of highly B-doped p-type silicon wafers can be prepared with tubular pores imbedded in a silicon matrix. Such materials have found many technological applications and provide a useful model system for studying phase transitions under confinement. This paper reports a joint experimental and simulation study of diffusion in such materials, covering displacements from molecular dimensions up to tens of micrometers with carefully selected probe molecules. In addition to mass transfer through the channels, diffusion (at much smaller rates) is also found to occur in directions perpendicular to the channels, thus providing clear evidence of connectivity. With increasing displacements, propagation in both axial and transversal directions is progressively retarded, suggesting a scale-dependent, hierarchical distribution of transport resistances (“constrictions” in the channels) and of shortcuts (connecting “bridges”) between adjacent channels. The experimental evidence from these studies is confirmed by molecular dynamics (MD) simulation in the range of atomistic displacements and rationalized with a simple model of statistically distributed “constrictions” and “bridges” for displacements in the micrometer range via dynamic Monte Carlo (DMC) simulation. Both ranges are demonstrated to be mutually transferrable by DMC simulations based on the pore space topology determined by electron tomography. PMID:28106047

Effects of trap-assisted tunneling on gate-induced drain leakage in silicon-germanium channel p-type FET for scaled supply voltages

NASA Astrophysics Data System (ADS)

Tiwari, Vishal A.; Divakaruni, Rama; Hook, Terence B.; Nair, Deleep R.

2016-04-01

Silicon-germanium is considered as an alternative channel material to silicon p-type FET (pFET) for the development of energy efficient high performance transistors for 28 nm and beyond in a high-k metal gate technology because of its lower threshold voltage and higher mobility. However, gate-induced drain leakage (GIDL) is a concern for high threshold voltage device design because of tunneling at reduced bandgap. In this work, the trap-assisted tunneling and band-to-band tunneling (BTBT) effects on GIDL is analyzed and modeled for SiGe pFETs. Experimental results and Monte Carlo simulation results reveal that the pre-halo germanium pre-amorphization implant used to contain the short channel effects contribute to GIDL at the drain sidewall in addition to GIDL due to BTBT in SiGe devices. The results are validated by comparing the experimental observations with the numerical simulation and a set of calibrated models are used to describe the GIDL mechanisms for various drain and gate bias.

Glass-silicon column

DOEpatents

Yu, Conrad M.

2003-12-30

A glass-silicon column that can operate in temperature variations between room temperature and about 450.degree. C. The glass-silicon column includes large area glass, such as a thin Corning 7740 boron-silicate glass bonded to a silicon wafer, with an electrode embedded in or mounted on glass of the column, and with a self alignment silicon post/glass hole structure. The glass/silicon components are bonded, for example be anodic bonding. In one embodiment, the column includes two outer layers of silicon each bonded to an inner layer of glass, with an electrode imbedded between the layers of glass, and with at least one self alignment hole and post arrangement. The electrode functions as a column heater, and one glass/silicon component is provided with a number of flow channels adjacent the bonded surfaces.

N-Type delta Doping of High-Purity Silicon Imaging Arrays

NASA Technical Reports Server (NTRS)

Blacksberg, Jordana; Hoenk, Michael; Nikzad, Shouleh

2005-01-01

A process for n-type (electron-donor) delta doping has shown promise as a means of modifying back-illuminated image detectors made from n-doped high-purity silicon to enable them to detect high-energy photons (ultraviolet and x-rays) and low-energy charged particles (electrons and ions). This process is applicable to imaging detectors of several types, including charge-coupled devices, hybrid devices, and complementary metal oxide/semiconductor detector arrays. Delta doping is so named because its density-vs.-depth characteristic is reminiscent of the Dirac delta function (impulse function): the dopant is highly concentrated in a very thin layer. Preferably, the dopant is concentrated in one or at most two atomic layers in a crystal plane and, therefore, delta doping is also known as atomic-plane doping. The use of doping to enable detection of high-energy photons and low-energy particles was reported in several prior NASA Tech Briefs articles. As described in more detail in those articles, the main benefit afforded by delta doping of a back-illuminated silicon detector is to eliminate a "dead" layer at the back surface of the silicon wherein high-energy photons and low-energy particles are absorbed without detection. An additional benefit is that the delta-doped layer can serve as a back-side electrical contact. Delta doping of p-type silicon detectors is well established. The development of the present process addresses concerns specific to the delta doping of high-purity silicon detectors, which are typically n-type. The present process involves relatively low temperatures, is fully compatible with other processes used to fabricate the detectors, and does not entail interruption of those processes. Indeed, this process can be the last stage in the fabrication of an imaging detector that has, in all other respects, already been fully processed, including metallized. This process includes molecular-beam epitaxy (MBE) for deposition of three layers, including

2.3 µm range InP-based type-II quantum well Fabry-Perot lasers heterogeneously integrated on a silicon photonic integrated circuit.

PubMed

Wang, Ruijun; Sprengel, Stephan; Boehm, Gerhard; Muneeb, Muhammad; Baets, Roel; Amann, Markus-Christian; Roelkens, Gunther

2016-09-05

Heterogeneously integrated InP-based type-II quantum well Fabry-Perot lasers on a silicon waveguide circuit emitting in the 2.3 µm wavelength range are demonstrated. The devices consist of a "W"-shaped InGaAs/GaAsSb multi-quantum-well gain section, III-V/silicon spot size converters and two silicon Bragg grating reflectors to form the laser cavity. In continuous-wave (CW) operation, we obtain a threshold current density of 2.7 kA/cm² and output power of 1.3 mW at 5 °C for 2.35 μm lasers. The lasers emit over 3.7 mW of peak power with a threshold current density of 1.6 kA/cm² in pulsed regime at room temperature. This demonstration of heterogeneously integrated lasers indicates that the material system and heterogeneous integration method are promising to realize fully integrated III-V/silicon photonics spectroscopic sensors in the 2 µm wavelength range.

Decontaminating Solar Wind Samples with the Genesis Ultra-Pure Water Megasonic Wafer Spin Cleaner

NASA Technical Reports Server (NTRS)

Calaway, Michael J.; Rodriquez, M. C.; Allton, J. H.; Stansbery, E. K.

2009-01-01

The Genesis sample return capsule, though broken during the landing impact, contained most of the shattered ultra-pure solar wind collectors comprised of silicon and other semiconductor wafers materials. Post-flight analysis revealed that all wafer fragments were littered with surface particle contamination from spacecraft debris as well as soil from the impact site. This particulate contamination interferes with some analyses of solar wind. In early 2005, the Genesis science team decided to investigate methods for removing the surface particle contamination prior to solar wind analysis.

Studies of SERS efficiency of gold coated porous silicon formed on rough silicon backside

NASA Astrophysics Data System (ADS)

Dridi, H.; Haji, L.; Moadhen, A.

2017-12-01

Starting from a rough backside of silicon wafer, we have formed a porous layer by electrochemical anodization and then coated by a thin film of gold. The morphological characteristics of the porous silicon and in turn the metal film are governed by the anodization process and also by the starting surface. So, in order to investigate the Plasmonic aspect of such rough surface which combines roughness inherent to the porous nature and that due to rough starting surface, we have used a dye target molecule to study its SERS signal using a porous silicon layer obtained on the rough backside surface. The use of unusual backside of silicon wafer could be, beside the others, an interesting way to made SERS effective substrate thanks to reproducible rough porous gold on porous layer from this starting face. The morphological results correspond to the silicon rough surface as a function of the crystallographic orientation showed the presence of two different substrate structure. The optical reflectivity results obtained of gold deposited on oxidized porous silicon showed a dependence of its Localized Surface Plasmon band frequency of the deposit time. SERS results, obtained for a dye target molecule (Rhodamine 6G), show a higher intensities in the case of the 〈110〉 orientation, which characterized by the higher roughness surface. Voici "the most relevant and important aspects of our work".

Optima XE Single Wafer High Energy Ion Implanter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Satoh, Shu; Ferrara, Joseph; Bell, Edward

2008-11-03

The Optima XE is the first production worthy single wafer high energy implanter. The new system combines a state-of-art single wafer endstation capable of throughputs in excess of 400 wafers/hour with a production-proven RF linear accelerator technology. Axcelis has been evolving and refining RF Linac technology since the introduction of the NV1000 in 1986. The Optima XE provides production worthy beam currents up to energies of 1.2 MeV for P{sup +}, 2.9 MeV for P{sup ++}, and 1.5 MeV for B{sup +}. Energies as low as 10 keV and tilt angles as high as 45 degrees are also available., allowingmore » the implanter to be used for a wide variety of traditional medium current implants to ensure high equipment utilization. The single wafer endstation provides precise implant angle control across wafer and wafer to wafer. In addition, Optima XE's unique dose control system allows compensation of photoresist outgassing effects without relying on traditional pressure-based methods. We describe the specific features, angle control and dosimetry of the Optima XE and their applications in addressing the ever-tightening demands for more precise process controls and higher productivity.« less

Ultra-Shallow Depth Profiling of Arsenic Implants in Silicon by Hydride Generation-Inductively Coupled Plasma Atomic Emission Spectrometry

NASA Astrophysics Data System (ADS)

Matsubara, Atsuko; Kojima, Hisao; Itoga, Toshihiko; Kanehori, Keiichi

1995-08-01

High resolution depth profiling of arsenic (As) implanted into silicon wafers by a chemical technique is described. Silicon wafers are precisely etched through repeated oxidation by hydrogen peroxide solution and dissolution of the oxide by hydrofluoric acid solution. The etched silicon thickness is determined by inductively-coupled plasma atomic emission spectrometry (ICP-AES). Arsenic concentration is determined by hydride generation ICP-AES (HG-ICP-AES) with prereduction using potassium iodide. The detection limit of As in a 4-inch silicon wafer is 2.4×1018 atoms/cm3. The etched silicon thickness is controlled to less than 4±2 atomic layers. Depth profiling of an ultra-shallow As diffusion layer with the proposed method shows good agreement with profiling using the four-probe method or secondary ion mass spectrometry.

Structured Antireflective Coating for Silicon at Submillimeter Frequencies

NASA Astrophysics Data System (ADS)

Padilla, Estefania

2018-01-01

Observations at millimeter and submillimeter wavelengths are useful for many astronomical studies, such as the polarization of the cosmic microwave background or the formation and evolution of galaxy clusters. In order to allow observations over a broad spectral bandwidth (approximatively from 70 to 420 GHz), innovative broadband anti-reflective (AR) optics must be utilized in submillimeter telescopes. Due to its low loss and high refractive index, silicon is a fine optical material at these frequencies, but an AR coating with multiple layers is required to maximize its transmission over a wide bandwidth. Structured multilayer AR coatings for silicon are currently being developed at Caltech and JPL. The development process includes the design of the structured layers with commercial electromagnetic simulation software, the fabrication by using deep reactive ion etching, and the test of the transmission and reflection of the patterned wafers. Geometrical 3D patterns have successfully been etched at the surface of the silicon wafers creating up to 2 layers with different effective refractive indices. The transmission and reflection of single AR layer wafers, measured between 75 and 330 GHz, are close to the simulation predictions. These results allow the development of new designs with 5 or 6 AR layers in order to improve the bandwidth and transmission of the silicon AR coatings.

Direct ultrasensitive electrical detection of prostate cancer biomarkers with CMOS-compatible n- and p-type silicon nanowire sensor arrays

NASA Astrophysics Data System (ADS)

Gao, Anran; Lu, Na; Dai, Pengfei; Fan, Chunhai; Wang, Yuelin; Li, Tie

2014-10-01

Sensitive and quantitative analysis of proteins is central to disease diagnosis, drug screening, and proteomic studies. Here, a label-free, real-time, simultaneous and ultrasensitive prostate-specific antigen (PSA) sensor was developed using CMOS-compatible silicon nanowire field effect transistors (SiNW FET). Highly responsive n- and p-type SiNW arrays were fabricated and integrated on a single chip with a complementary metal oxide semiconductor (CMOS) compatible anisotropic self-stop etching technique which eliminated the need for a hybrid method. The incorporated n- and p-type nanowires revealed complementary electrical response upon PSA binding, providing a unique means of internal control for sensing signal verification. The highly selective, simultaneous and multiplexed detection of PSA marker at attomolar concentrations, a level useful for clinical diagnosis of prostate cancer, was demonstrated. The detection ability was corroborated to be effective by comparing the detection results at different pH values. Furthermore, the real-time measurement was also carried out in a clinically relevant sample of blood serum, indicating the practicable development of rapid, robust, high-performance, and low-cost diagnostic systems.Sensitive and quantitative analysis of proteins is central to disease diagnosis, drug screening, and proteomic studies. Here, a label-free, real-time, simultaneous and ultrasensitive prostate-specific antigen (PSA) sensor was developed using CMOS-compatible silicon nanowire field effect transistors (SiNW FET). Highly responsive n- and p-type SiNW arrays were fabricated and integrated on a single chip with a complementary metal oxide semiconductor (CMOS) compatible anisotropic self-stop etching technique which eliminated the need for a hybrid method. The incorporated n- and p-type nanowires revealed complementary electrical response upon PSA binding, providing a unique means of internal control for sensing signal verification. The highly

Technology of silicon charged-particle detectors developed at the Institute of Electron Technology (ITE)

NASA Astrophysics Data System (ADS)

Wegrzecka, Iwona; Panas, Andrzej; Bar, Jan; Budzyński, Tadeusz; Grabiec, Piotr; Kozłowski, Roman; Sarnecki, Jerzy; Słysz, Wojciech; Szmigiel, Dariusz; Wegrzecki, Maciej; Zaborowski, Michał

2013-07-01

The paper discusses the technology of silicon charged-particle detectors developed at the Institute of Electron Technology (ITE). The developed technology enables the fabrication of both planar and epiplanar p+-ν-n+ detector structures with an active area of up to 50 cm2. The starting material for epiplanar structures are silicon wafers with a high-resistivity n-type epitaxial layer ( ν layer - ρ < 3 kΩcm) deposited on a highly doped n+-type substrate (ρ< 0,02Ωcm) developed and fabricated at the Institute of Electronic Materials Technology. Active layer thickness of the epiplanar detectors (νlayer) may range from 10 μm to 150 μm. Imported silicon with min. 5 kΩcm resistivity is used to fabricate planar detectors. Active layer thickness of the planar detectors (ν) layer) may range from 200 μm to 1 mm. This technology enables the fabrication of both discrete and multi-junction detectors (monolithic detector arrays), such as single-sided strip detectors (epiplanar and planar) and double-sided strip detectors (planar). Examples of process diagrams for fabrication of the epiplanar and planar detectors are presented in the paper, and selected technological processes are discussed.

Method for fabricating an ultra-low expansion mask blank having a crystalline silicon layer

DOEpatents

Cardinale, Gregory F.

2002-01-01

A method for fabricating masks for extreme ultraviolet lithography (EUVL) using Ultra-Low Expansion (ULE) substrates and crystalline silicon. ULE substrates are required for the necessary thermal management in EUVL mask blanks, and defect detection and classification have been obtained using crystalline silicon substrate materials. Thus, this method provides the advantages for both the ULE substrate and the crystalline silicon in an Extreme Ultra-Violet (EUV) mask blank. The method is carried out by bonding a crystalline silicon wafer or member to a ULE wafer or substrate and thinning the silicon to produce a 5-10 .mu.m thick crystalline silicon layer on the surface of the ULE substrate. The thinning of the crystalline silicon may be carried out, for example, by chemical mechanical polishing and if necessary or desired, oxidizing the silicon followed by etching to the desired thickness of the silicon.

Phosphorus diffusion gettering process of multicrystalline silicon using a sacrificial porous silicon layer

PubMed Central

2012-01-01

The aims of this work are to getter undesirable impurities from low-cost multicrystalline silicon (mc-Si) wafers and then enhance their electronic properties. We used an efficient process which consists of applying phosphorus diffusion into a sacrificial porous silicon (PS) layer in which the gettered impurities have been trapped after the heat treatment. As we have expected, after removing the phosphorus-rich PS layer, the electrical properties of the mc-Si wafers were significantly improved. The PS layers, realized on both sides of the mc-Si substrates, were formed by the stain-etching technique. The phosphorus treatment was achieved using a liquid POCl3-based source on both sides of the mc-Si wafers. The realized phosphorus/PS/Si/PS/phosphorus structures were annealed at a temperature ranging between 700°C and 950°C under a controlled O2 atmosphere, which allows phosphorus to diffuse throughout the PS layers and to getter eventual metal impurities towards the phosphorus-doped PS layer. The effect of this gettering procedure was investigated by means of internal quantum efficiency and the dark current–voltage (I-V) characteristics. The minority carrier lifetime measurements were made using a WTC-120 photoconductance lifetime tester. The serial resistance and the shunt resistance carried out from the dark I-V curves confirm this gettering-related solar cell improvement. It has been shown that the photovoltaic parameters of the gettered silicon solar cells were improved with regard to the ungettered one, which proves the beneficial effect of this gettering process on the conversion efficiency of the multicrystalline silicon solar cells. PMID:22846070

Advanced process control and novel test methods for PVD silicon and elastomeric silicone coatings utilized on ion implant disks, heatsinks and selected platens

DOE Office of Scientific and Technical Information (OSTI.GOV)

Springer, J.; Allen, B.; Wriggins, W.

Coatings play multiple key roles in the proper functioning of mature and current ion implanters. Batch and serial implanters require strategic control of elemental and particulate contamination which often includes scrutiny of the silicon surface coatings encountering direct beam contact. Elastomeric Silicone Coatings must accommodate wafer loading and unloading as well as direct backside contact during implant plus must maintain rigid elemental and particulate specifications. The semiconductor industry has had a significant and continuous effort to obtain ultra-pure silicon coatings with sustained process performance and long life. Low particles and reduced elemental levels for silicon coatings are a major requirementmore » for process engineers, OEM manufacturers, and second source suppliers. Relevant data will be presented. Some emphasis and detail will be placed on the structure and characteristics of a relatively new PVD Silicon Coating process that is very dense and homogeneous. Wear rate under typical ion beam test conditions will be discussed. The PVD Silicon Coating that will be presented here is used on disk shields, wafer handling fingers/fences, exclusion zones of heat sinks, beam dumps and other beamline components. Older, legacy implanters can now provide extended process capability using this new generation PVD silicon - even on implanter systems that were shipped long before the advent of silicon coating for contamination control. Low particles and reduced elemental levels are critical performance criteria for the silicone elastomers used on disk heatsinks and serial implanter platens. Novel evaluation techniques and custom engineered tools are used to investigate the surface interaction characteristics of multiple Elastomeric Silicone Coatings currently in use by the industry - specifically, friction and perpendicular stiction. These parameters are presented as methods to investigate the critical wafer load and unload function. Unique tools and

Advanced process control and novel test methods for PVD silicon and elastomeric silicone coatings utilized on ion implant disks, heatsinks and selected platens

NASA Astrophysics Data System (ADS)

Springer, J.; Allen, B.; Wriggins, W.; Kuzbyt, R.; Sinclair, R.

2012-11-01

Coatings play multiple key roles in the proper functioning of mature and current ion implanters. Batch and serial implanters require strategic control of elemental and particulate contamination which often includes scrutiny of the silicon surface coatings encountering direct beam contact. Elastomeric Silicone Coatings must accommodate wafer loading and unloading as well as direct backside contact during implant plus must maintain rigid elemental and particulate specifications. The semiconductor industry has had a significant and continuous effort to obtain ultra-pure silicon coatings with sustained process performance and long life. Low particles and reduced elemental levels for silicon coatings are a major requirement for process engineers, OEM manufacturers, and second source suppliers. Relevant data will be presented. Some emphasis and detail will be placed on the structure and characteristics of a relatively new PVD Silicon Coating process that is very dense and homogeneous. Wear rate under typical ion beam test conditions will be discussed. The PVD Silicon Coating that will be presented here is used on disk shields, wafer handling fingers/fences, exclusion zones of heat sinks, beam dumps and other beamline components. Older, legacy implanters can now provide extended process capability using this new generation PVD silicon - even on implanter systems that were shipped long before the advent of silicon coating for contamination control. Low particles and reduced elemental levels are critical performance criteria for the silicone elastomers used on disk heatsinks and serial implanter platens. Novel evaluation techniques and custom engineered tools are used to investigate the surface interaction characteristics of multiple Elastomeric Silicone Coatings currently in use by the industry - specifically, friction and perpendicular stiction. These parameters are presented as methods to investigate the critical wafer load and unload function. Unique tools and test

Fabrication of ultrathin and highly uniform silicon on insulator by numerically controlled plasma chemical vaporization machining.

PubMed

Sano, Yasuhisa; Yamamura, Kazuya; Mimura, Hidekazu; Yamauchi, Kazuto; Mori, Yuzo

2007-08-01

Metal-oxide semiconductor field-effect transistors fabricated on a silicon-on-insulator (SOI) wafer operate faster and at a lower power than those fabricated on a bulk silicon wafer. Scaling down, which improves their performances, demands thinner SOI wafers. In this article, improvement on the thinning of SOI wafers by numerically controlled plasma chemical vaporization machining (PCVM) is described. PCVM is a gas-phase chemical etching method in which reactive species generated in atmospheric-pressure plasma are used. Some factors affecting uniformity are investigated and methods for improvements are presented. As a result of thinning a commercial 8 in. SOI wafer, the initial SOI layer thickness of 97.5+/-4.7 nm was successfully thinned and made uniform at 7.5+/-1.5 nm.

Nanoparticle-based etching of silicon surfaces

DOEpatents

Branz, Howard [Boulder, CO; Duda, Anna [Denver, CO; Ginley, David S [Evergreen, CO; Yost, Vernon [Littleton, CO; Meier, Daniel [Atlanta, GA; Ward, James S [Golden, CO

2011-12-13

A method (300) of texturing silicon surfaces (116) such to reduce reflectivity of a silicon wafer (110) for use in solar cells. The method (300) includes filling (330, 340) a vessel (122) with a volume of an etching solution (124) so as to cover the silicon surface 116) of a wafer or substrate (112). The etching solution (124) is made up of a catalytic nanomaterial (140) and an oxidant-etchant solution (146). The catalytic nanomaterial (140) may include gold or silver nanoparticles or noble metal nanoparticles, each of which may be a colloidal solution. The oxidant-etchant solution (146) includes an etching agent (142), such as hydrofluoric acid, and an oxidizing agent (144), such as hydrogen peroxide. Etching (350) is performed for a period of time including agitating or stirring the etching solution (124). The etch time may be selected such that the etched silicon surface (116) has a reflectivity of less than about 15 percent such as 1 to 10 percent in a 350 to 1000 nanometer wavelength range.

Electrical and optical properties of sub-10 nm nickel silicide films for silicon solar cells

NASA Astrophysics Data System (ADS)

Brahmi, Hatem; Ravipati, Srikanth; Yarali, Milad; Shervin, Shahab; Wang, Weijie; Ryou, Jae-Hyun; Mavrokefalos, Anastassios

2017-01-01

Highly conductive and transparent films of ultra-thin p-type nickel silicide films have been prepared by RF magnetron sputtering of nickel on silicon substrates followed by rapid thermal annealing in an inert environment in the temperature range 400-600 °C. The films are uniform throughout the wafer with thicknesses in the range of 3-6 nm. The electrical and optical properties are presented for nickel silicide films with varying thickness. The Drude-Lorentz model and Fresnel equations were used to calculate the dielectric properties, sheet resistance, absorption and transmission of the films. These ultrathin nickel silicide films have excellent optoelectronic properties for p-type contacts with optical transparencies up to 80% and sheet resistance as low as ~0.15 µΩ cm. Furthermore, it was shown that the use of a simple anti-reflection (AR) coating can recover most of the reflected light approaching the values of a standard Si solar cell with the same AR coating. Overall, the combination of ultra-low thickness, high transmittance, low sheet resistance and ability to recover the reflected light by utilizing standard AR coating makes them ideal for utilization in silicon based photovoltaic technologies as a p-type transparent conductor.

Micro-spectroscopy on silicon wafers and solar cells

PubMed Central

2011-01-01

Micro-Raman (μRS) and micro-photoluminescence spectroscopy (μPLS) are demonstrated as valuable characterization techniques for fundamental research on silicon as well as for technological issues in the photovoltaic production. We measure the quantitative carrier recombination lifetime and the doping density with submicron resolution by μPLS and μRS. μPLS utilizes the carrier diffusion from a point excitation source and μRS the hole density-dependent Fano resonances of the first order Raman peak. This is demonstrated on micro defects in multicrystalline silicon. In comparison with the stress measurement by μRS, these measurements reveal the influence of stress on the recombination activity of metal precipitates. This can be attributed to the strong stress dependence of the carrier mobility (piezoresistance) of silicon. With the aim of evaluating technological process steps, Fano resonances in μRS measurements are analyzed for the determination of the doping density and the carrier lifetime in selective emitters, laser fired doping structures, and back surface fields, while μPLS can show the micron-sized damage induced by the respective processes. PMID:21711723

The Development of High-Density Vertical Silicon Nanowires and Their Application in a Heterojunction Diode.

PubMed

Chang, Wen-Chung; Su, Sheng-Chien; Wu, Chia-Ching

2016-06-30

Vertically aligned p-type silicon nanowire (SiNW) arrays were fabricated through metal-assisted chemical etching (MACE) of Si wafers. An indium tin oxide/indium zinc oxide/silicon nanowire (ITO/IZO/SiNW) heterojunction diode was formed by depositing ITO and IZO thin films on the vertically aligned SiNW arrays. The structural and electrical properties of the resulting ITO/IZO/SiNW heterojunction diode were characterized by field emission scanning electron microscopy (FE-SEM), X-ray diffraction (XRD), and current-voltage (I-V) measurements. Nonlinear and rectifying I-V properties confirmed that a heterojunction diode was successfully formed in the ITO/IZO/SiNW structure. The diode had a well-defined rectifying behavior, with a rectification ratio of 550.7 at 3 V and a turn-on voltage of 2.53 V under dark conditions.

The Development of High-Density Vertical Silicon Nanowires and Their Application in a Heterojunction Diode

PubMed Central

Chang, Wen-Chung; Su, Sheng-Chien; Wu, Chia-Ching

2016-01-01

Vertically aligned p-type silicon nanowire (SiNW) arrays were fabricated through metal-assisted chemical etching (MACE) of Si wafers. An indium tin oxide/indium zinc oxide/silicon nanowire (ITO/IZO/SiNW) heterojunction diode was formed by depositing ITO and IZO thin films on the vertically aligned SiNW arrays. The structural and electrical properties of the resulting ITO/IZO/SiNW heterojunction diode were characterized by field emission scanning electron microscopy (FE-SEM), X-ray diffraction (XRD), and current−voltage (I−V) measurements. Nonlinear and rectifying I−V properties confirmed that a heterojunction diode was successfully formed in the ITO/IZO/SiNW structure. The diode had a well-defined rectifying behavior, with a rectification ratio of 550.7 at 3 V and a turn-on voltage of 2.53 V under dark conditions. PMID:28773656

A silicon technology for millimeter-wave monolithic circuits

NASA Astrophysics Data System (ADS)

Stabile, P. J.; Rosen, A.

1984-12-01

A silicon millimeter-wave integrated-circuit (SIMMWIC) technology that includes high-energy ion implantation and pulsed-laser annealing, secondary ion mass spectrometry (SIMS) profile diagnostics, and novel wafer thinning has been developed. This technology has been applied to a SIMMWIC single-pole single-throw (SPST) switch and to IMPATT and p-i-n diode fabrication schemes. Thus, the SIMMWIC technology is a proven base for monolithic millimeter-wave sources and control circuit applications.

Commissioning a p-type silicon diode for use in clinical electron beams.

PubMed

Eveling, J N; Morgan, A M; Pitchford, W G

1999-01-01

Commissioning measurements were carried out on a p-type silicon diode detector for use in patient monitoring in high energy electron beams. Characteristics specific to the diode were examined. The variation in diode sensitivity with dose per pulse was found to be less than 1% over a range 0.069-0.237 mGy/pulse. The diode exhibited a sensitivity variation with accumulated dose of 10% per kGy and a sensitivity variation with surface temperature of 0.26%/degree C. The dependence of the diode response on the direction of the incident electron beam was investigated. Results were found to exceed the manufacturer's specifications. Output factors measured with the diode agree to within 1.5% of those measured with an NACP-02 air ionization chamber. The detector showed a variation in response with energy of 0.8% over the energy range 4-15 MeV. Prior to introducing the diode into clinical use, an assessment of beam perturbation directly behind the diode was made. The maximum reduction in local dose directly behind the diode at a depth of 1.0 cm below the surface was approximately 13% at 4 and 15 MeV.

Low-frequency noise reduction in vertical MOSFETs having tunable threshold voltage fabricated with 60 nm CMOS technology on 300 mm wafer process

NASA Astrophysics Data System (ADS)

Imamoto, Takuya; Ma, Yitao; Muraguchi, Masakazu; Endoh, Tetsuo

2015-04-01

In this paper, DC and low-frequency noise (LFN) characteristics have been investigated with actual measurement data in both n- and p-type vertical MOSFETs (V-MOSFETs) for the first time. The V-MOSFETs which was fabricated on 300 mm bulk silicon wafer process have realized excellent DC performance and a significant reduction of flicker (1/f) noise. The measurement results show that the fabricated V-MOSFETs with 60 nm silicon pillar and 100 nm gate length achieve excellent steep sub-threshold swing (69 mV/decade for n-type and 66 mV/decade for p-type), good on-current (281 µA/µm for n-type 149 µA/µm for p-type), low off-leakage current (28.1 pA/µm for n-type and 79.6 pA/µm for p-type), and excellent on-off ratio (1 × 107 for n-type and 2 × 106 for p-type). In addition, it is demonstrated that our fabricated V-MOSFETs can control the threshold voltage (Vth) by changing the channel doping condition, which is the useful and low-cost technique as it has been widely used in the conventional bulk planar MOSFET. This result indicates that V-MOSFETs can control Vth more finely and flexibly by the combined the use of the doping technique with other techniques such as work function engineering of metal-gate. Moreover, it is also shown that V-MOSFETs can suppress 1/f noise (L\\text{gate}WS\\text{Id}/I\\text{d}2 of 10-13-10-11 µm2/Hz for n-type and 10-12-10-10 µm2/Hz for p-type) to one or two order lower level than previously reported nanowire type MOSFET, FinFET, Tri-Gate, and planar MOSFETs. The results have also proved that both DC and 1/f noise performances are independent from the bias voltage which is applied to substrate or well layer. Therefore, it is verified that V-MOSFETs can eliminate the effects from substrate or well layer, which always adversely affects the circuit performances due to this serial connection.

Process Research on Polycrystalline Silicon Material (PROPSM)

NASA Technical Reports Server (NTRS)

Culik, J. S.

1982-01-01

The investigation of the performance limiting mechanisms in large grain (greater than 1-2 mm in diameter) polycrystalline silicon was continued by fabricating a set of minicell wafers on a selection of 10 cm x 10 cm wafers. A minicell wafer consists of an array of small (approximately 0.2 sq cm in area) photodiodes which are isolated from one another by a mesa structure. The junction capacitance of each minicell was used to obtain the dopant concentration, and therefore the resistivity, as a function of position across each wafer. The results indicate that there is no significant variation in resistivity with position for any of the polycrystalline wafers, whether Semix or Wacker. However, the resistivity of Semix brick 71-01E did decrease slightly from bottom to top.

Suppression of interfacial voids formation during silane (SiH4)-based silicon oxide bonding with a thin silicon nitride capping layer

NASA Astrophysics Data System (ADS)

Lee, Kwang Hong; Bao, Shuyu; Wang, Yue; Fitzgerald, Eugene A.; Seng Tan, Chuan

2018-01-01

The material properties and bonding behavior of silane-based silicon oxide layers deposited by plasma-enhanced chemical vapor deposition were investigated. Fourier transform infrared spectroscopy was employed to determine the chemical composition of the silicon oxide films. The incorporation of hydroxyl (-OH) groups and moisture absorption demonstrates a strong correlation with the storage duration for both as-deposited and annealed silicon oxide films. It is observed that moisture absorption is prevalent in the silane-based silicon oxide film due to its porous nature. The incorporation of -OH groups and moisture absorption in the silicon oxide films increase with the storage time (even in clean-room environments) for both as-deposited and annealed silicon oxide films. Due to silanol condensation and silicon oxidation reactions that take place at the bonding interface and in the bulk silicon, hydrogen (a byproduct of these reactions) is released and diffused towards the bonding interface. The trapped hydrogen forms voids over time. Additionally, the absorbed moisture could evaporate during the post-bond annealing of the bonded wafer pair. As a consequence, defects, such as voids, form at the bonding interface. To address the problem, a thin silicon nitride capping film was deposited on the silicon oxide layer before bonding to serve as a diffusion barrier to prevent moisture absorption and incorporation of -OH groups from the ambient. This process results in defect-free bonded wafers.

Solar fuels: visible-light-driven generation of dihydrogen at p-type silicon electrocatalysed by molybdenum hydrides.

PubMed

Webster, Lee R; Ibrahim, Saad K; Wright, Joseph A; Pickett, Christopher J

2012-09-10

We show that a robust molybdenum hydride system can sustain photoelectrocatalysis of a hydrogen evolution reaction at boron-doped, hydrogen-terminated, p-type silicon. The photovoltage for the system is about 600-650 mV and the current densities, which can be sustained at the photocathode in non-catalytic and catalytic regimes, are similar to those at a photoinert vitreous carbon electrode. The kinetics of electrocatalysed hydrogen evolution at the photocathode are also very similar to those measured at vitreous carbon-evidently visible light does not significantly perturb the catalytic mechanism. Importantly, we show that the doped (1-10 Ω cm) p-type Si can function perfectly well in the dark as an ohmic conductor and this has allowed direct comparison of the cyclic voltammetric behaviour of the response of the system under dark and illuminated conditions at the same electrode. The p-type Si we have employed optimally harvests light energy in the 600-700 nm region and with 37 mW cm(-2) illumination in this range; the light to electrochemical energy conversion is estimated to be 2.8 %. The current yield of hydrogen under broad tungsten halide lamp illumination at 90 mW cm(-2) is (91±5) % with a corresponding chemical yield of (98±5) %. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Phosphorus out-diffusion in laser molten silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Köhler, J. R.; Eisele, S. J.

2015-04-14

Laser doping via liquid phase diffusion enables the formation of defect free pn junctions and a tailoring of diffusion profiles by varying the laser pulse energy density and the overlap of laser pulses. We irradiate phosphorus diffused 100 oriented p-type float zone silicon wafers with a 5 μm wide line focused 6.5 ns pulsed frequency doubled Nd:YVO{sub 4} laser beam, using a pulse to pulse overlap of 40%. By varying the number of laser scans N{sub s} = 1, 2, 5, 10, 20, 40 at constant pulse energy density H = 1.3 J/cm{sup 2} and H = 0.79 J/cm{sup 2} we examine the out-diffusion of phosphorus atoms performing secondary ionmore » mass spectroscopy concentration measurements. Phosphorus doping profiles are calculated by using a numerical simulation tool. The tool models laser induced melting and re-solidification of silicon as well as the out-diffusion of phosphorus atoms in liquid silicon during laser irradiation. We investigate the observed out-diffusion process by comparing simulations with experimental concentration measurements. The result is a pulse energy density independent phosphorus out-diffusion velocity v{sub out} = 9 ± 1 cm/s in liquid silicon, a partition coefficient of phosphorus 1 < k{sub p} < 1.1 and a diffusion coefficient D = 1.4(±0.2)cm{sup 2}/s × 10{sup −3 }× exp[−183 meV/(k{sub B}T)].« less

Reflectance modeling of electrochemically P-type porosified silicon by Drude-Lorentz model

NASA Astrophysics Data System (ADS)

Kadi, M.; Media, E. M.; Gueddaoui, H.; Outemzabet, R.

2014-09-01

Porous silicon remains a promising material for optoelectronic application; in this field monitoring of the refractive index profile of the porous layer is required. We present in this work a procedure based on Drude-Lorentz model for calculating the optical parameters such as the high- and low-frequency dielectric constants, the plasma frequency by fitting the reflectance spectra. The experimental data of different porous silicon layer created above the bulk silicon material by electrochemical etching are extracted from reflectance measurements. The reflectance spectra are recorded in the spectral range 350-2500 nm. First, our computational procedure has been validated by its application on mono-crystalline silicon for the determination of its optical parameters. A good agreement between our results and those found in other works has been achieved in the visible-NIR range. In the second step, the model was applied to porous silicon (PS) layers. Useful optical parameters like the refractive index and the extinction coefficient, respectively, n (λ) and κ(λ), the band gap Eg, of different fabricated porous silicon layer are determined from simulated reflectance spectra. The correlation between the optical properties and the conditions of the electrochemical treatment was observed and analyzed. The main conclusion is that the reflected light from the porous silicon surface, although non-homogeneous and thus possessing the light scattering, is essentially smaller than the reflected light from the bulk crystalline silicon. These results show that the porous surface layer can act as an antireflection coating for silicon and could be used, in particular, in solar cells.

Direct metallization local Al-back surface field for high efficiency screen printed crystalline silicon solar cells.

PubMed

Lee, Jonghwan; Park, Cheolmin; Dao, Vinh Ai; Lee, Youn-Jung; Ryu, Kyungyul; Choi, Gyuho; Kim, Bonggi; Ju, Minkyu; Jeong, Chaehwan; Yi, Junsin

2013-11-01

In this paper, we present a detailed study on the local back contact (LBC) formation of rear-surface-passivated silicon solar cells, where both the LBC opening and metallization are realized by one-step alloying of a dot of fine pattern screen-printed aluminum paste with the silicon substrate. Based on energy dispersive spectrometer (EDS) and scanning electron microscopy (SEM) characterizations, we suggest that the aluminum distribution and the silicon concentration determine the local-back-surface-field (Al-p+) layer thickness, resistivity of the Al-p+ and hence the quality of the Al-p+ formation. The highest penetration of silicon concentration of 78.17% in aluminum resulted in the formation of a 5 microm-deep Al-p+ layer, and the minimum LBC resistivity of 0.92 x 10-6 omega cm2. The degradation of the rear-surface passivation due to high temperature of the LBC formation process can be fully recovered by forming gas annealing (FGA) at temperature and hydrogen content of 450 degrees C and 15%, respectively. The application of the optimized LBC of rear-surface-passivated by a dot of fine pattern screen(-) printed aluminum paste resulted in efficiency of up to 19.98% for the p-type czochralski (CZ) silicon wafers with 10.24 cm2 cell size at 649 mV open circuit voltage. By FGA for rear-surface passivation recovery, efficiencies up to 20.35% with a V(OC) of 662 mV, FF of 82%, and J(SC) of 37.5 mA/cm2 were demonstrated.

Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

NASA Astrophysics Data System (ADS)

Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

2018-05-01

A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.