Lift-off process with bi-layer photoresist patterns for conformal-coated superhydrophilic pulsed plasma chemical vapor deposition-SiOx on SiCx for lab-on-a-chip applications

NASA Astrophysics Data System (ADS)

Konishi, Satoshi; Nakagami, Chise; Kobayashi, Taizo; Tonomura, Wataru; Kaizuma, Yoshihiro

2015-04-01

In this work, a lift-off process with bi-layer photoresist patterns was applied to the formation of hydrophobic/hydrophilic micropatterns on practical polymer substrates used in healthcare diagnostic commercial products. The bi-layer photoresist patterns with undercut structures made it possible to peel the conformal-coated silicon oxide (SiOx) films from substrates. SiOx and silicon carbide (SiCx) layers were deposited by pulsed plasma chemical vapor deposition (PPCVD) method which can form roughened surfaces to enhance hydrophilicity of SiOx and hydrophobicity of SiCx. Microfluidic applications using hydrophobic/hydrophilic patterns were also demonstrated on low-cost substrates such as poly(ethylene terephthalate) (PET) and paper films.

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Laser desorption ionization and peptide sequencing on laser induced silicon microcolumn arrays

DOEpatents

Vertes, Akos [Reston, VA; Chen, Yong [San Diego, CA

2011-12-27

The present invention provides a method of producing a laser-patterned silicon surface, especially silicon wafers for use in laser desorption ionization (LDI-MS) (including MALDI-MS and SELDI-MS), devices containing the same, and methods of testing samples employing the same. The surface is prepared by subjecting a silicon substrate to multiple laser shots from a high-power picosecond or femtosecond laser while in a processing environment, e.g., underwater, and generates a remarkable homogenous microcolumn array capable of providing an improved substrate for LDI-MS.

Nanofabrication on unconventional substrates using transferred hard masks

DOE PAGES

Li, Luozhou; Bayn, Igal; Lu, Ming; ...

2015-01-15

Here, a major challenge in nanofabrication is to pattern unconventional substrates that cannot be processed for a variety of reasons, such as incompatibility with spin coating, electron beam lithography, optical lithography, or wet chemical steps. Here, we present a versatile nanofabrication method based on re-usable silicon membrane hard masks, patterned using standard lithography and mature silicon processing technology. These masks, transferred precisely onto targeted regions, can be in the millimetre scale. They allow for fabrication on a wide range of substrates, including rough, soft, and non-conductive materials, enabling feature linewidths down to 10 nm. Plasma etching, lift-off, and ion implantationmore » are realized without the need for scanning electron/ion beam processing, UV exposure, or wet etching on target substrates.« less

Direct observation of resonance scattering patterns in single silicon nanoparticles

NASA Astrophysics Data System (ADS)

Valuckas, Vytautas; Paniagua-Domínguez, Ramón; Fu, Yuan Hsing; Luk'yanchuk, Boris; Kuznetsov, Arseniy I.

2017-02-01

We present the first direct observation of the scattering patterns of electric and magnetic dipole resonances excited in a single silicon nanosphere. Almost perfectly spherical silicon nanoparticles were fabricated and deposited on a 30 nm-thick silicon nitride membrane in an attempt to minimize particle—substrate interaction. Measurements were carried out at visible wavelengths by means of the Fourier microscopy in a dark-field illumination setup. The obtained back-focal plane images clearly reveal the characteristic scattering patterns associated with each resonance and are found to be in a good agreement with the simulated results.

Nanopattern-guided growth of single-crystal silicon on amorphous substrates and high-performance sub-100 nm thin-film transistors for three-dimensional integrated circuits

NASA Astrophysics Data System (ADS)

Gu, Jian

This thesis explores how nanopatterns can be used to control the growth of single-crystal silicon on amorphous substrates at low temperature, with potential applications on flat panel liquid-crystal display and 3-dimensional (3D) integrated circuits. I first present excimer laser annealing of amorphous silicon (a-Si) nanostructures on thermally oxidized silicon wafer for controlled formation of single-crystal silicon islands. Preferential nucleation at pattern center is observed due to substrate enhanced edge heating. Single-grain silicon is obtained in a 50 nm x 100 nm rectangular pattern by super lateral growth (SLG). Narrow lines (such as 20-nm-wide) can serve as artificial heterogeneous nucleation sites during crystallization of large patterns, which could lead to the formation of single-crystal silicon islands in a controlled fashion. In addition to eximer laser annealing, NanoPAtterning and nickel-induced lateral C&barbelow;rystallization (NanoPAC) of a-Si lines is presented. Single-crystal silicon is achieved by NanoPAC. The line width of a-Si affects the grain structure of crystallized silicon lines significantly. Statistics show that single-crystal silicon is formed for all lines with width between 50 nm to 200 nm. Using in situ transmission electron microscopy (TEM), nickel-induced lateral crystallization (Ni-ILC) of a-Si inside a pattern is revealed; lithography-constrained single seeding (LISS) is proposed to explain the single-crystal formation. Intragrain line and two-dimensional defects are also studied. To test the electrical properties of NanoPAC silicon films, sub-100 nm thin-film transistors (TFTs) are fabricated using Patten-controlled crystallization of Ṯhin a-Si channel layer and H&barbelow;igh temperature (850°C) annealing, coined PaTH process. PaTH TFTs show excellent device performance over traditional solid phase crystallized (SPC) TFTs in terms of threshold voltage, threshold voltage roll-off, leakage current, subthreshold swing, on/off current ratio, device-to-device uniformity etc. Two-dimensional device simulations show that PaTH TFTs are comparable to silicon-on-insulator (SOI) devices, making it a promising candidate for the fabrication of future high performance, low-power 3D integrated circuits. Finally, an ultrafast nanolithography technique, laser-assisted direct imprint (LADI) is introduced. LADI shows the ability of patterning nanostructures directly in silicon in nanoseconds with sub-10 nm resolution. The process has potential applications in multiple disciplines, and could be extended to other materials and processes.

Method for providing an arbitrary three-dimensional microstructure in silicon using an anisotropic deep etch

DOEpatents

Morales, Alfredo M.; Gonzales, Marcela

2004-06-15

The present invention describes a method for fabricating an embossing tool or an x-ray mask tool, providing microstructures that smoothly vary in height from point-to-point in etched substrates, i.e., structure which can vary in all three dimensions. The process uses a lithographic technique to transfer an image pattern in the surface of a silicon wafer by exposing and developing the resist and then etching the silicon substrate. Importantly, the photoresist is variably exposed so that when developed some of the resist layer remains. The remaining undeveloped resist acts as an etchant barrier to the reactive plasma used to etch the silicon substrate and therefore provides the ability etch structures of variable depths.

Fabrication of patterned surface by soft lithographic technique for confinement of lipid bilayer

NASA Astrophysics Data System (ADS)

Moulick, Ranjita Ghosh; Mayer, Dirk

2018-04-01

In this paper we demonstrated that a 3D pattern can be well transferred from a silicon Master to a gold substrate using µcontact printing. In this process 1-Octadecanthiol served as an ink and printing followed by etching generated the desired pattern on the gold substrate. The prepatterned substrate was also used for lipid vesicle fusion and revealed that lipid molecules selectively bind to the gold layer.

Nanoparticle assembly on patterned "plus/minus" surfaces from electrospray of colloidal dispersion.

PubMed

Lenggoro, I Wuled; Lee, Hye Moon; Okuyama, Kikuo

2006-11-01

Selective deposition of metal (Au) and oxide (SiO2) nanoparticles with a size range of 10-30 nm on patterned silicon-silicon oxide substrate was performed using the electrospray method. Electrical charging characteristics of particles produced by the electrospray and patterned area created by contact charging of the electrical conductor with non- or semi-conductors were investigated. Colloidal droplets were electrosprayed and subsequently dried as individual nanoparticles which then were deposited on substrates, and observed using field emission-scanning electron microscopy. The number of elementary charge units on particles generated by the electrospray was 0.4-148, and patterned area created by contact charging contained sufficient negative charges to attract multiple charged particles. Locations where nanoparticles were (reversibly) deposited depended on voltage polarity applied to the spraying colloidal droplet and the substrate, and the existence of additional ions such as those from a stabilizer.

Fabrication Methods for Adaptive Deformable Mirrors

NASA Technical Reports Server (NTRS)

Toda, Risaku; White, Victor E.; Manohara, Harish; Patterson, Keith D.; Yamamoto, Namiko; Gdoutos, Eleftherios; Steeves, John B.; Daraio, Chiara; Pellegrino, Sergio

2013-01-01

Previously, it was difficult to fabricate deformable mirrors made by piezoelectric actuators. This is because numerous actuators need to be precisely assembled to control the surface shape of the mirror. Two approaches have been developed. Both approaches begin by depositing a stack of piezoelectric films and electrodes over a silicon wafer substrate. In the first approach, the silicon wafer is removed initially by plasmabased reactive ion etching (RIE), and non-plasma dry etching with xenon difluoride (XeF2). In the second approach, the actuator film stack is immersed in a liquid such as deionized water. The adhesion between the actuator film stack and the substrate is relatively weak. Simply by seeping liquid between the film and the substrate, the actuator film stack is gently released from the substrate. The deformable mirror contains multiple piezoelectric membrane layers as well as multiple electrode layers (some are patterned and some are unpatterned). At the piezolectric layer, polyvinylidene fluoride (PVDF), or its co-polymer, poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) is used. The surface of the mirror is coated with a reflective coating. The actuator film stack is fabricated on silicon, or silicon on insulator (SOI) substrate, by repeatedly spin-coating the PVDF or P(VDFTrFE) solution and patterned metal (electrode) deposition. In the first approach, the actuator film stack is prepared on SOI substrate. Then, the thick silicon (typically 500-micron thick and called handle silicon) of the SOI wafer is etched by a deep reactive ion etching process tool (SF6-based plasma etching). This deep RIE stops at the middle SiO2 layer. The middle SiO2 layer is etched by either HF-based wet etching or dry plasma etch. The thin silicon layer (generally called a device layer) of SOI is removed by XeF2 dry etch. This XeF2 etch is very gentle and extremely selective, so the released mirror membrane is not damaged. It is possible to replace SOI with silicon substrate, but this will require tighter DRIE process control as well as generally longer and less efficient XeF2 etch. In the second approach, the actuator film stack is first constructed on a silicon wafer. It helps to use a polyimide intermediate layer such as Kapton because the adhesion between the polyimide and silicon is generally weak. A mirror mount ring is attached by using adhesive. Then, the assembly is partially submerged in liquid water. The water tends to seep between the actuator film stack and silicon substrate. As a result, the actuator membrane can be gently released from the silicon substrate. The actuator membrane is very flat because it is fixed to the mirror mount prior to the release. Deformable mirrors require extremely good surface optical quality. In the technology described here, the deformable mirror is fabricated on pristine substrates such as prime-grade silicon wafers. The deformable mirror is released by selectively removing the substrate. Therefore, the released deformable mirror surface replicates the optical quality of the underlying pristine substrate.

Method for forming silicon on a glass substrate

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method by which single-crystal silicon microelectronics may be fabricated on glass substrates at unconventionally low temperatures. This is achieved by fabricating a thin film of silicon on glass and subsequently forming the doped components by a short wavelength (excimer) laser doping procedure and conventional patterning techniques. This method may include introducing a heavily boron doped etch stop layer on a silicon wafer using an excimer laser, which permits good control of the etch stop layer removal process. This method additionally includes dramatically reducing the remaining surface roughness of the silicon thin films after etching in the fabrication of silicon on insulator wafers by scanning an excimer laser across the surface of the silicon thin film causing surface melting, whereby the surface tension of the melt causes smoothing of the surface during recrystallization. Applications for this method include those requiring a transparent or insulating substrate, such as display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard and high temperature electronics.

Method for forming silicon on a glass substrate

DOEpatents

McCarthy, A.M.

1995-03-07

A method by which single-crystal silicon microelectronics may be fabricated on glass substrates at unconventionally low temperatures. This is achieved by fabricating a thin film of silicon on glass and subsequently forming the doped components by a short wavelength (excimer) laser doping procedure and conventional patterning techniques. This method may include introducing a heavily boron doped etch stop layer on a silicon wafer using an excimer laser, which permits good control of the etch stop layer removal process. This method additionally includes dramatically reducing the remaining surface roughness of the silicon thin films after etching in the fabrication of silicon on insulator wafers by scanning an excimer laser across the surface of the silicon thin film causing surface melting, whereby the surface tension of the melt causes smoothing of the surface during recrystallization. Applications for this method include those requiring a transparent or insulating substrate, such as display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard and high temperature electronics. 15 figs.

Silicon vertical microstructure fabrication by catalytic etching

NASA Astrophysics Data System (ADS)

Huang, Mao-Jung; Yang, Chii-Rong; Chang, Chun-Ming; Chu, Nien-Nan; Shiao, Ming-Hua

2012-08-01

This study presents an effective, simple and inexpensive process for forming micro-scale vertical structures on a (1 0 0) silicon wafer. Several modified etchants and micro-patterns including rectangular, snake-like, circular and comb patterns were employed to determine the optimum etching process. We found that an etchant solution consisting of 4.6 M hydrofluoric acid, 0.44 M hydrogen peroxide and isopropyl alcohol produces microstructures at an etching rate of 0.47 µm min-1 and surface roughness of 17.4 nm. All the patterns were transferred faithfully to the silicon substrate.

Patterned forests of vertically-aligned multiwalled carbon nanotubes using metal salt catalyst solutions.

PubMed

Garrett, David J; Flavel, Benjamin S; Baronian, Keith H R; Downard, Alison J

2013-01-01

A simple method for producing patterned forests of multiwalled carbon nanotubes (MWCNTs) is described. An aqueous metal salt solution is spin-coated onto a substrate patterned with photoresist by standard methods. The photoresist is removed by acetone washing leaving the acetone-insoluble catalyst pattern on the substrate. Dense forests of vertically aligned (VA) MWCNTs are grown on the patterned catalyst layers by chemical vapour deposition. The procedures have been demonstrated by growing MWCNT forests on two substrates: silicon and conducting graphitic carbon films. The forests adhere strongly to the substrates and when grown directly on carbon film, offer a simple method of preparing MWCNT electrodes.

Large-Area Direct Hetero-Epitaxial Growth of 1550-nm InGaAsP Multi-Quantum-Well Structures on Patterned Exact-Oriented (001) Silicon Substrates by Metal Organic Chemical Vapor Deposition

NASA Astrophysics Data System (ADS)

Megalini, Ludovico; Cabinian, Brian C.; Zhao, Hongwei; Oakley, Douglas C.; Bowers, John E.; Klamkin, Jonathan

2018-02-01

We employ a simple two-step growth technique to grow large-area 1550-nm laser structures by direct hetero-epitaxy of III-V compounds on patterned exact-oriented (001) silicon (Si) substrates by metal organic chemical vapor deposition. Densely-packed, highly uniform, flat and millimeter-long indium phosphide (InP) nanowires were grown from Si v-grooves separated by silicon dioxide (SiO2) stripes with various widths and pitches. Following removal of the SiO2 patterns, the InP nanowires were coalesced and, subsequently, 1550-nm laser structures were grown in a single overgrowth without performing any polishing for planarization. X-ray diffraction, photoluminescence, atomic force microscopy and transmission electron microscopy analyses were used to characterize the epitaxial material. PIN diodes were fabricated and diode-rectifying behavior was observed.

Gray scale x-ray mask

DOEpatents

Morales, Alfredo M [Livermore, CA; Gonzales, Marcela [Seattle, WA

2006-03-07

The present invention describes a method for fabricating an embossing tool or an x-ray mask tool, providing microstructures that smoothly vary in height from point-to-point in etched substrates, i.e., structure which can vary in all three dimensions. The process uses a lithographic technique to transfer an image pattern in the surface of a silicon wafer by exposing and developing the resist and then etching the silicon substrate. Importantly, the photoresist is variably exposed so that when developed some of the resist layer remains. The remaining undeveloped resist acts as an etchant barrier to the reactive plasma used to etch the silicon substrate and therefore provides the ability etch structures of variable depths.

A simple approach to patterned protein immobilization on silicon via electrografting from diazonium salt solutions.

PubMed

Flavel, Benjamin S; Gross, Andrew J; Garrett, David J; Nock, Volker; Downard, Alison J

2010-04-01

A highly versatile method utilizing diazonium salt chemistry has been developed for the fabrication of protein arrays. Conventional ultraviolet mask lithography was used to pattern micrometer sized regions into a commercial photoresist on a highly doped p-type silicon (100) substrate. These patterned regions were used as a template for the electrochemical grafting of the in situ generated p-aminobenzenediazonium cation to form patterns of aminophenyl film on silicon. Immobilization of biomolecules was demonstrated by coupling biotin to the aminophenyl regions followed by reaction with fluorescently labeled avidin and visualization with fluorescence microscopy. This simple patterning strategy is promising for future application in biosensor devices.

Soft lithographic functionalization and patterning oxide-free silicon and germanium.

PubMed

Bowers, Carleen M; Toone, Eric J; Clark, Robert L; Shestopalov, Alexander A

2011-12-16

The development of hybrid electronic devices relies in large part on the integration of (bio)organic materials and inorganic semiconductors through a stable interface that permits efficient electron transport and protects underlying substrates from oxidative degradation. Group IV semiconductors can be effectively protected with highly-ordered self-assembled monolayers (SAMs) composed of simple alkyl chains that act as impervious barriers to both organic and aqueous solutions. Simple alkyl SAMs, however, are inert and not amenable to traditional patterning techniques. The motivation for immobilizing organic molecular systems on semiconductors is to impart new functionality to the surface that can provide optical, electronic, and mechanical function, as well as chemical and biological activity. Microcontact printing (μCP) is a soft-lithographic technique for patterning SAMs on myriad surfaces. Despite its simplicity and versatility, the approach has been largely limited to noble metal surfaces and has not been well developed for pattern transfer to technologically important substrates such as oxide-free silicon and germanium. Furthermore, because this technique relies on the ink diffusion to transfer pattern from the elastomer to substrate, the resolution of such traditional printing is essentially limited to near 1 μm. In contrast to traditional printing, inkless μCP patterning relies on a specific reaction between a surface-immobilized substrate and a stamp-bound catalyst. Because the technique does not rely on diffusive SAM formation, it significantly expands the diversity of patternable surfaces. In addition, the inkless technique obviates the feature size limitations imposed by molecular diffusion, facilitating replication of very small (<200 nm) features. However, up till now, inkless μCP has been mainly used for patterning relatively disordered molecular systems, which do not protect underlying surfaces from degradation. Here, we report a simple, reliable high-throughput method for patterning passivated silicon and germanium with reactive organic monolayers and demonstrate selective functionalization of the patterned substrates with both small molecules and proteins. The technique utilizes a preformed NHS-reactive bilayered system on oxide-free silicon and germanium. The NHS moiety is hydrolyzed in a pattern-specific manner with a sulfonic acid-modified acrylate stamp to produce chemically distinct patterns of NHS-activated and free carboxylic acids. A significant limitation to the resolution of many μCP techniques is the use of PDMS material which lacks the mechanical rigidity necessary for high fidelity transfer. To alleviate this limitation we utilized a polyurethane acrylate polymer, a relatively rigid material that can be easily functionalized with different organic moieties. Our patterning approach completely protects both silicon and germanium from chemical oxidation, provides precise control over the shape and size of the patterned features, and gives ready access to chemically discriminated patterns that can be further functionalized with both organic and biological molecules. The approach is general and applicable to other technologically-relevant surfaces.

Nanoscale Cu{sub 2}O films: Radio-frequency magnetron sputtering and structural and optical studies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kudryashov, D. A., E-mail: kudryashovda@apbau.ru; Gudovskikh, A. S.; Babichev, A. V.

2017-01-15

Nanoscale copper (I) oxide layers are formed by magnetron-assisted sputtering onto glassy and silicon substrates in an oxygen-free environment at room temperature, and the structural and optical properties of the layers are studied. It is shown that copper oxide formed on a silicon substrate exhibits a lower degree of disorder than that formed on a glassy substrate, which is supported by the observation of a higher intensity and a smaller half-width of reflections in the diffraction pattern. The highest intensity of reflections in the diffraction pattern is observed for Cu{sub 2}O films grown on silicon at a magnetron power ofmore » 150 W. The absorption and transmittance spectra of these Cu{sub 2}O films are in agreement with the well-known spectra of bulk crystals. In the Raman spectra of the films, phonons inherent in the crystal lattice of cubic Cu{sub 2}O crystals are identified.« less

Process for Smoothing an Si Substrate after Etching of SiO2

NASA Technical Reports Server (NTRS)

Turner, Tasha; Wu, Chi

2003-01-01

A reactive-ion etching (RIE) process for smoothing a silicon substrate has been devised. The process is especially useful for smoothing those silicon areas that have been exposed by etching a pattern of holes in a layer of silicon dioxide that covers the substrate. Applications in which one could utilize smooth silicon surfaces like those produced by this process include fabrication of optical waveguides, epitaxial deposition of silicon on selected areas of silicon substrates, and preparation of silicon substrates for deposition of adherent metal layers. During etching away of a layer of SiO2 that covers an Si substrate, a polymer becomes deposited on the substrate, and the substrate surface becomes rough (roughness height approximately equal to 50 nm) as a result of over-etching or of deposition of the polymer. While it is possible to smooth a silicon substrate by wet chemical etching, the undesired consequences of wet chemical etching can include compromising the integrity of the SiO2 sidewalls and undercutting of the adjacent areas of the silicon dioxide that are meant to be left intact. The present RIE process results in anisotropic etching that removes the polymer and reduces height of roughness of the silicon substrate to less than 10 nm while leaving the SiO2 sidewalls intact and vertical. Control over substrate versus sidewall etching (in particular, preferential etching of the substrate) is achieved through selection of process parameters, including gas flow, power, and pressure. Such control is not uniformly and repeatably achievable in wet chemical etching. The recipe for the present RIE process is the following: Etch 1 - A mixture of CF4 and O2 gases flowing at rates of 25 to 75 and 75 to 125 standard cubic centimeters per minute (stdcm3/min), respectively; power between 44 and 55 W; and pressure between 45 and 55 mtorr (between 6.0 and 7.3 Pa). The etch rate lies between approximately equal to 3 and approximately equal to 6 nm/minute. Etch 2 - O2 gas flowing at 75 to 125 stdcm3/min, power between 44 and 55 W, and pressure between 50 and 100 mtorr (between 6.7 and 13.3 Pa).

Porous silicon carbide (SIC) semiconductor device

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1996-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Method of fabricating porous silicon carbide (SiC)

NASA Technical Reports Server (NTRS)

Shor, Joseph S. (Inventor); Kurtz, Anthony D. (Inventor)

1995-01-01

Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.

Plasma-deposited fluoropolymer film mask for local porous silicon formation

PubMed Central

2012-01-01

The study of an innovative fluoropolymer masking layer for silicon anodization is proposed. Due to its high chemical resistance to hydrofluoric acid even under anodic bias, this thin film deposited by plasma has allowed the formation of deep porous silicon regions patterned on the silicon wafer. Unlike most of other masks, fluoropolymer removal after electrochemical etching is rapid and does not alter the porous layer. Local porous regions were thus fabricated both in p+-type and low-doped n-type silicon substrates. PMID:22734507

Simple method for the growth of 4H silicon carbide on silicon substrate

NASA Astrophysics Data System (ADS)

Asghar, M.; Shahid, M. Y.; Iqbal, F.; Fatima, K.; Nawaz, Muhammad Asif; Arbi, H. M.; Tsu, R.

2016-03-01

In this study we report thermal evaporation technique as a simple method for the growth of 4H silicon carbide on p-type silicon substrate. A mixture of Si and C60 powder of high purity (99.99%) was evaporated from molybdenum boat. The as grown film was characterized by XRD, FTIR, UV-Vis Spectrophotometer and Hall Measurements. The XRD pattern displayed four peaks at 2Θ angles 28.550, 32.700, 36.100 and 58.900 related to Si (1 1 1), 4H-SiC (1 0 0), 4H-SiC (1 1 1) and 4H-SiC (2 2 2), respectively. FTIR, UV-Vis spectrophotometer and electrical properties further strengthened the 4H-SiC growth.

Silicon micro-mold and method for fabrication

DOEpatents

Morales, Alfredo M.

2005-01-11

The present invention describes a method for rapidly fabricating a robust 3-dimensional silicon micro-mold for use in preparing complex metal micro-components. The process begins by depositing a conductive metal layer onto one surface of a silicon wafer. A thin photoresist and a standard lithographic mask are then used to transfer a trace image pattern onto the opposite surface of the wafer by exposing and developing the resist. The exposed portion of the silicon substrate is anisotropically etched through the wafer thickness down to conductive metal layer to provide an etched pattern consisting of a series of rectilinear channels and recesses in the silicon which serve as the silicon micro-mold. Microcomponents are prepared with this mold by first filling the mold channels and recesses with a metal deposit, typically by electroplating, and then removing the silicon micro-mold by chemical etching.

Silicon micro-mold

DOEpatents

Morales, Alfredo M [Livermore, CA

2006-10-24

The present invention describes a method for rapidly fabricating a robust 3-dimensional silicon-mold for use in preparing complex metal micro-components. The process begins by depositing a conductive metal layer onto one surface of a silicon wafer. A thin photoresist and a standard lithographic mask are then used to transfer a trace image pattern onto the opposite surface of the wafer by exposing and developing the resist. The exposed portion of the silicon substrate is anisotropically etched through the wafer thickness down to conductive metal layer to provide an etched pattern consisting of a series of rectilinear channels and recesses in the silicon which serve as the silicon micro-mold. Microcomponents are prepared with this mold by first filling the mold channels and recesses with a metal deposit, typically by electroplating, and then removing the silicon micro-mold by chemical etching.

Graphene fixed-end beam arrays based on mechanical exfoliation

NASA Astrophysics Data System (ADS)

Li, Peng; You, Zheng; Haugstad, Greg; Cui, Tianhong

2011-06-01

A low-cost mechanical exfoliation method is presented to transfer graphite to graphene for free-standing beam arrays. Nickel film or photoresist is used to peel off and transfer patterned single-layer or multilayer graphene onto substrates with macroscopic continuity. Free-standing graphene beam arrays are fabricated on both silicon and polymer substrates. Their mechanical properties are studied by atomic force microscopy. Finally, a graphene based radio frequency switch is demonstrated, with its pull-in voltage and graphene-silicon junction investigated.

Fabrication of silicon films from patterned protruded seeds

NASA Astrophysics Data System (ADS)

Zeng, Huang; Zhang, Wei; Li, Jizhou; Wang, Cong; Yang, Hui; Chen, Yigang; Chen, Xiaoyuan; Liu, Dongfang

2017-05-01

Thin, flexible silicon crystals are starting up applications such as light-weighted flexible solar cells, SOI, flexible IC chips, 3D ICs imagers and 3D CMOS imagers on the demand of high performance with low cost. Kerfless wafering technology by direct conversion of source gases into mono-crystalline wafers on reusable substrates is highly cost-effective and feedstock-effective route to cheap wafers with the thickness down to several microns. Here we show a prototype for direct conversion of silicon source gases to wafers by using the substrate with protruded seeds. A reliable and controllable method of wafer-scaled preparation of protruded seed patterns has been developed by filling liquid wax into a rod array as the mask for the selective removal of oxide layer on the rod head. Selectively epitaxial growth is performed on the protruded seeds, and the voidless film is formed by the merging of neighboring seeds through growing. And structured hollows are formed between the grown film and the substrate, which would offer the transferability of the grown film and the reusability of the protruded seeds.

Folded Coplanar Waveguide Slot Antenna on Silicon Substrates With a Polyimide Interface Layer

NASA Technical Reports Server (NTRS)

Bacon, Andrew; Ponchak, George E.; Papapolymerou, John; Bushyager, Nathan; Tentzeris, Manos; Williams, W. D. (Technical Monitor)

2002-01-01

A novel mm-wave Coplanar Waveguide (CPW) folded slot antenna is characterized on low-resistivity Si substrate (1 omega-cm) and a high resistivity Si substrate with a polyimide interface layer for the first time. The antenna resonates around 30 GHz with a return loss greater than 14.6 dB. Measured radiation patterns indicate the existence of a main lobe, but the radiation pattern is affected by a strong surface wave mode, which is greater in the high resistivity Si wafer.

Reprogramming hMSCs morphology with silicon/porous silicon geometric micro-patterns.

PubMed

Ynsa, M D; Dang, Z Y; Manso-Silvan, M; Song, J; Azimi, S; Wu, J F; Liang, H D; Torres-Costa, V; Punzon-Quijorna, E; Breese, M B H; Garcia-Ruiz, J P

2014-04-01

Geometric micro-patterned surfaces of silicon combined with porous silicon (Si/PSi) have been manufactured to study the behaviour of human Mesenchymal Stem Cells (hMSCs). These micro-patterns consist of regular silicon hexagons surrounded by spaced columns of silicon equilateral triangles separated by PSi. The results show that, at an early culture stage, the hMSCs resemble quiescent cells on the central hexagons with centered nuclei and actin/β-catenin and a microtubules network denoting cell adhesion. After 2 days, hMSCs adapted their morphology and cytoskeleton proteins from cell-cell dominant interactions at the center of the hexagonal surface. This was followed by an intermediate zone with some external actin fibres/β-catenin interactions and an outer zone where the dominant interactions are cell-silicon. Cells move into silicon columns to divide, migrate and communicate. Furthermore, results show that Runx2 and vitamin D receptors, both specific transcription factors for skeleton-derived cells, are expressed in cells grown on micropatterned silicon under all observed circumstances. On the other hand, non-phenotypic alterations are under cell growth and migration on Si/PSi substrates. The former consideration strongly supports the use of micro-patterned silicon surfaces to address pending questions about the mechanisms of human bone biogenesis/pathogenesis and the study of bone scaffolds.

Study on Buckling of Stiff Thin Films on Soft Substrates as Functional Materials

NASA Astrophysics Data System (ADS)

Ma, Teng

In engineering, buckling is mechanical instability of walls or columns under compression and usually is a problem that engineers try to prevent. In everyday life buckles (wrinkles) on different substrates are ubiquitous -- from human skin to a rotten apple they are a commonly observed phenomenon. It seems that buckles with macroscopic wavelengths are not technologically useful; over the past decade or so, however, thanks to the widespread availability of soft polymers and silicone materials micro-buckles with wavelengths in submicron to micron scale have received increasing attention because it is useful for generating well-ordered periodic microstructures spontaneously without conventional lithographic techniques. This thesis investigates the buckling behavior of thin stiff films on soft polymeric substrates and explores a variety of applications, ranging from optical gratings, optical masks, energy harvest to energy storage. A laser scanning technique is proposed to detect micro-strain induced by thermomechanical loads and a periodic buckling microstructure is employed as a diffraction grating with broad wavelength tunability, which is spontaneously generated from a metallic thin film on polymer substrates. A mechanical strategy is also presented for quantitatively buckling nanoribbons of piezoelectric material on polymer substrates involving the combined use of lithographically patterning surface adhesion sites and transfer printing technique. The precisely engineered buckling configurations provide a route to energy harvesters with extremely high levels of stretchability. This stiff-thin-film/polymer hybrid structure is further employed into electrochemical field to circumvent the electrochemically-driven stress issue in silicon-anode-based lithium ion batteries. It shows that the initial flat silicon-nanoribbon-anode on a polymer substrate tends to buckle to mitigate the lithiation-induced stress so as to avoid the pulverization of silicon anode. Spontaneously generated submicron buckles of film/polymer are also used as an optical mask to produce submicron periodic patterns with large filling ratio in contrast to generating only ˜100 nm edge submicron patterns in conventional near-field soft contact photolithography. This thesis aims to deepen understanding of buckling behavior of thin films on compliant substrates and, in turn, to harness the fundamental properties of such instability for diverse applications.

Fabrication of terahertz metamaterials using electrohydrodynamic jet printing for sensitive detection of yeast

NASA Astrophysics Data System (ADS)

Pradhipta Tenggara, Ayodya; Park, S. J.; Teguh Yudistira, Hadi; Ahn, Y. H.; Byun, Doyoung

2017-03-01

We demonstrated the fabrication of terahertz metamaterial sensor for the accurate and on-site detection of yeast using electrohydrodynamic jet printing, which is inexpensive, simple, and environmentally friendly. The very small sized pattern up to 5 µm-width of electrical split ring resonator unit structures could be printed on a large area on both a rigid substrate and flexible substrate, i.e. silicon wafer and polyimide film using the drop on demand technique to eject liquid ink containing silver nanoparticles. Experimental characterization and simulation were performed to study their performances in detecting yeast of different weights. It was shown that the metamaterial sensor fabricated on a flexible polyimide film had higher sensitivity by more than six times than the metamaterial sensor fabricated on a silicon wafer, due to the low refractive index of the PI substrate and due to the extremely thin substrate thickness which lowers the effective index further. The resonance frequency shift saturated when the yeast weights were 145 µg and 215 µg for metamaterial structures with gap size 6.5 µm fabricated on the silicon substrate and on the polyimide substrate, respectively.

Directed dewetting of amorphous silicon film by a donut-shaped laser pulse.

PubMed

Yoo, Jae-Hyuck; In, Jung Bin; Zheng, Cheng; Sakellari, Ioanna; Raman, Rajesh N; Matthews, Manyalibo J; Elhadj, Selim; Grigoropoulos, Costas P

2015-04-24

Irradiation of a thin film with a beam-shaped laser is proposed to achieve site-selectively controlled dewetting of the film into nanoscale structures. As a proof of concept, the laser-directed dewetting of an amorphous silicon thin film on a glass substrate is demonstrated using a donut-shaped laser beam. Upon irradiation of a single laser pulse, the silicon film melts and dewets on the substrate surface. The irradiation with the donut beam induces an unconventional lateral temperature profile in the film, leading to thermocapillary-induced transport of the molten silicon to the center of the beam spot. Upon solidification, the ultrathin amorphous silicon film is transformed to a crystalline silicon nanodome of increased height. This morphological change enables further dimensional reduction of the nanodome as well as removal of the surrounding film material by isotropic silicon etching. These results suggest that laser-based dewetting of thin films can be an effective way for scalable manufacturing of patterned nanostructures.

Self-organized nickel nanoparticles on nanostructured silicon substrate intermediated by a titanium oxynitride (TiNxOy) interface

NASA Astrophysics Data System (ADS)

Morales, M.; Droppa, R., Jr.; de Mello, S. R. S.; Figueroa, C. A.; Zanatta, A. R.; Alvarez, F.

2018-01-01

In this work we report an experimental approach by combining in situ sequential top-down and bottom-up processes to induce the organization of nanosized nickel particles. The top-down process consists in xenon ion bombardment of a crystalline silicon substrate to generate a pattern, followed by depositing a ˜15 nm titanium oxynitride thin film to act as a metallic diffusion barrier. Then, metallic nanoparticles are deposited by argon ion sputtering a pure nickel target, and the sample is annealed to promote the organization of the nickel nanoparticles (a bottom-up process). According to the experimental results, the surface pattern and the substrate biaxial surface strain are the driving forces behind the alignment and organization of the nickel nanoparticles. Moreover, the ratio between the F of metallic atoms arriving at the substrate relative to its surface diffusion mobility determines the nucleation regime of the nickel nanoparticles. These features are presented and discussed considering the existing technical literature on the subject.

Submicron Surface-Patterned Fibers and Textiles

DTIC Science & Technology

2016-11-04

These authors contributed equally Keywords: grating, fiber, polymer , patterning, textile Distribution A: approved for public release...requirements. Second, textile materials are primarily polymer -based, while most surface-patterning techniques have been developed for silicon...Alternative substrates, especially flexible polymers , remain challenging to pattern [25,26] due to the highly specific surface chemistry of different

Self-assembled molecular magnets on patterned silicon substrates: bridging bio-molecules with nanoelectronics.

PubMed

Chang, Chia-Ching; Sun, Kien Wen; Lee, Shang-Fan; Kan, Lou-Sing

2007-04-01

The paper reports the methods of preparing molecular magnets and patterning of the molecules on a semiconductor surface. A highly magnetically aligned metallothionein containing Mn and Cd (Mn,Cd-MT-2) is first synthesized, and the molecules are then placed into nanopores prepared on silicon (001) surfaces using electron beam lithography and reactive ion-etching techniques. We have observed the self-assemble growth of the MT molecules on the patterned Si surface such that the MT molecules have grown into rod or ring type three-dimensional nanostructures, depending on the patterned nanostructures on the surface. We also provide scanning electron microscopy, atomic force microscopy, and magnetic force microscope studies of the molecular nanostructures. This engineered molecule shows molecular magnetization and is biocompatible with conventional semiconductors. These features make Mn,Cd-MT-2 a good candidate for biological applications and sensing sources of new nanodevices. Using molecular self-assembly and topographical patterning of the semiconductor substrate, we can close the gap between bio-molecules and nanoelectronics built into the semiconductor chip.

Three-dimensional whispering gallery modes in InGaAs nanoneedle lasers on silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tran, T.-T. D.; Chen, R.; Ng, K. W.

2014-09-15

As-grown InGaAs nanoneedle lasers, synthesized at complementary metal–oxide–semiconductor compatible temperatures on polycrystalline and crystalline silicon substrates, were studied in photoluminescence experiments. Radiation patterns of three-dimensional whispering gallery modes were observed upon optically pumping the needles above the lasing threshold. Using the radiation patterns as well as finite-difference-time-domain simulations and polarization measurements, all modal numbers of the three-dimensional whispering gallery modes could be identified.

High Aspect Ratio Sub-15 nm Silicon Trenches From Block Copolymer Templates

NASA Astrophysics Data System (ADS)

Gu, Xiaodan; Liu, Zuwei; Gunkel, Ilja; Olynick, Deirdre; Russell, Thomas; University of Massachusetts Amherst Collaboration; Oxford Instrument Collaboration; Lawrence Berkeley National Lab Collaboration

2013-03-01

High-aspect-ratio sub-15 nm silicon trenches are fabricated directly from plasma etching of a block copolymer (BCP) mask. Polystyrene-b-poly(2-vinyl pyridine) (PS-b-P2VP) 40k-b-18k was spin coated and solvent annealed to form cylindrical structures parallel to the silicon substrate. The BCP thin film was reconstructed by immersion in ethanol and then subjected to an oxygen and argon reactive ion etching to fabricate the polymer mask. A low temperature ion coupled plasma with sulfur hexafluoride and oxygen was used to pattern transfer block copolymer structure to silicon with high selectivity (8:1) and fidelity. The silicon pattern was characterized by scanning electron microscopy and grazing incidence x-ray scattering. We also demonstrated fabrication of silicon nano-holes using polystyrene-b-polyethylene oxide (PS-b-PEO) using same methodology described above for PS-b-P2VP. Finally, we show such silicon nano-strucutre serves as excellent nano-imprint master template to pattern various functional materials like poly 3-hexylthiophene (P3HT).

X-ray mask and method for providing same

DOEpatents

Morales, Alfredo M [Pleasanton, CA; Skala, Dawn M [Fremont, CA

2004-09-28

The present invention describes a method for fabricating an x-ray mask tool which can achieve pattern features having lateral dimension of less than 1 micron. The process uses a thin photoresist and a standard lithographic mask to transfer an trace image pattern in the surface of a silicon wafer by exposing and developing the resist. The exposed portion of the silicon substrate is then anisotropically etched to provide an etched image of the trace image pattern consisting of a series of channels in the silicon having a high depth-to-width aspect ratio. These channels are then filled by depositing a metal such as gold to provide an inverse image of the trace image and thereby providing a robust x-ray mask tool.

X-ray mask and method for providing same

DOEpatents

Morales, Alfredo M.; Skala, Dawn M.

2002-01-01

The present invention describes a method for fabricating an x-ray mask tool which can achieve pattern features having lateral dimension of less than 1 micron. The process uses a thin photoresist and a standard lithographic mask to transfer an trace image pattern in the surface of a silicon wafer by exposing and developing the resist. The exposed portion of the silicon substrate is then anisotropically etched to provide an etched image of the trace image pattern consisting of a series of channels in the silicon having a high depth-to-width aspect ratio. These channels are then filled by depositing a metal such as gold to provide an inverse image of the trace image and thereby providing a robust x-ray mask tool.

Methods to introduce sub-micrometer, symmetry-breaking surface corrugation to silicon substrates to increase light trapping

DOE Office of Scientific and Technical Information (OSTI.GOV)

Han, Sang Eon; Hoard, Brittany R.; Han, Sang M.

Provided is a method for fabricating a nanopatterned surface. The method includes forming a mask on a substrate, patterning the substrate to include a plurality of symmetry-breaking surface corrugations, and removing the mask. The mask includes a pattern defined by mask material portions that cover first surface portions of the substrate and a plurality of mask space portions that expose second surface portions of the substrate, wherein the plurality of mask space portions are arranged in a lattice arrangement having a row and column, and the row is not oriented parallel to a [110] direction of the substrate. The patterningmore » the substrate includes anisotropically removing portions of the substrate exposed by the plurality of spaces.« less

The Design, Fabrication and Characterization of a Transparent Atom Chip

PubMed Central

Chuang, Ho-Chiao; Huang, Chia-Shiuan; Chen, Hung-Pin; Huang, Chi-Sheng; Lin, Yu-Hsin

2014-01-01

This study describes the design and fabrication of transparent atom chips for atomic physics experiments. A fabrication process was developed to define the wire patterns on a transparent glass substrate to create the desired magnetic field for atom trapping experiments. An area on the chip was reserved for the optical access, so that the laser light can penetrate directly through the glass substrate for the laser cooling process. Furthermore, since the thermal conductivity of the glass substrate is poorer than other common materials for atom chip substrate, for example silicon, silicon carbide, aluminum nitride. Thus, heat dissipation copper blocks are designed on the front and back of the glass substrate to improve the electrical current conduction. The testing results showed that a maximum burnout current of 2 A was measured from the wire pattern (with a width of 100 μm and a height of 20 μm) without any heat dissipation design and it can increase to 2.5 A with a heat dissipation design on the front side of the atom chips. Therefore, heat dissipation copper blocks were designed and fabricated on the back of the glass substrate just under the wire patterns which increases the maximum burnout current to 4.5 A. Moreover, a maximum burnout current of 6 A was achieved when the entire backside glass substrate was recessed and a thicker copper block was electroplated, which meets most requirements of atomic physics experiments. PMID:24922456

Silica substrate or portion formed from oxidation of monocrystalline silicon

DOEpatents

Matzke, Carolyn M.; Rieger, Dennis J.; Ellis, Robert V.

2003-07-15

A method is disclosed for forming an inclusion-free silica substrate using a monocrystalline silicon substrate as the starting material and oxidizing the silicon substrate to convert it entirely to silica. The oxidation process is performed from both major surfaces of the silicon substrate using a conventional high-pressure oxidation system. The resulting product is an amorphous silica substrate which is expected to have superior etching characteristics for microfabrication than conventional fused silica substrates. The present invention can also be used to convert only a portion of a monocrystalline silicon substrate to silica by masking the silicon substrate and locally thinning a portion the silicon substrate prior to converting the silicon portion entirely to silica. In this case, the silica formed by oxidizing the thinned portion of the silicon substrate can be used, for example, as a window to provide optical access through the silicon substrate.

The pathway to intelligent implants: osteoblast response to nano silicon-doped hydroxyapatite patterning

PubMed Central

Munir, G.; Koller, G.; Di Silvio, L.; Edirisinghe, M. J.; Bonfield, W.; Huang, J.

2011-01-01

Bioactive hydroxyapatite (HA) with addition of silicon (Si) in the crystal structure (silicon-doped hydroxyapatite (SiHA)) has become a highly attractive alternative to conventional HA in bone replacement owing to the significant improvement in the in vivo bioactivity and osteoconductivity. Nanometre-scaled SiHA (nanoSiHA), which closely resembles the size of bone mineral, has been synthesized in this study. Thus, the silicon addition provides an extra chemical cue to stimulate and enhance bone formation for new generation coatings, and the next stage in metallic implantation design is to further improve cellular adhesion and proliferation by control of cell alignment. Topography has been found to provide a powerful set of signals for cells and form contact guidance. Using the recently developed novel technique of template-assisted electrohydrodynamic atomization (TAEA), patterns of pillars and tracks of various dimensions of nanoSiHA were achieved. Modifying the parameters of TAEA, the resolution of pattern structures was controlled, enabling the topography of a substrate to be modified accordingly. Spray time, flow rate and distance between the needle and substrate were varied to improve the pattern formation of pillars and tracks. The 15 min deposition time provided the most consistent patterned topography with a distance of 50 mm and flow rate of 4 µl min−1. A titanium substrate was patterned with pillars and tracks of varying widths, line lengths and distances under the optimized TAEA processing condition. A fast bone-like apatite formation rate was found on nanoSiHA after immersion in simulated body fluid, thus demonstrating its high in vitro bioactivity. Primary human osteoblast (HOB) cells responded to SiHA patterns by stretching of the filopodia between track and pillar, attaching to the apex of the pillar pattern and stretching between two. HOB cells responded to the track pattern by elongating along and between the track, and the length of HOB cells was proportional to the gaps between track patterns, but this relationship was not observed on the pillar patterns. The study has therefore provided an insight for future design of next generation implant surfaces to control and guide cellular responses, while TAEA patterning provides a controllable technique to provide topography to medical implants. PMID:21208969

Direct patterning of silver particles on porous silicon by inkjet printing of a silver salt via in-situ reduction

PubMed Central

2012-01-01

We have developed a method for obtaining a direct pattern of silver nanoparticles (NPs) on porous silicon (p-Si) by means of inkjet printing (IjP) of a silver salt. Silver NPs were obtained by p-Si mediated in-situ reduction of Ag+ cations using solutions based on AgNO3 which were directly printed on p-Si according to specific geometries and process parameters. The main difference with respect to existing literature is that normally, inkjet printing is applied to silver (metal) NP suspensions, while in our experiment the NPs are formed after jetting the solution on the reactive substrate. We performed both optical and scanning electron microscopes on the NPs traces, correlating the morphology features with the IjP parameters, giving an insight on the synthesis kinetics. The patterned NPs show good performances as SERS substrates. PMID:22953722

Understanding and improving the low optical emission of InGaAs quantum wells grown on oxidized patterned (001) silicon substrate

NASA Astrophysics Data System (ADS)

Roque, J.; Haas, B.; David, S.; Rochat, N.; Bernier, N.; Rouvière, J. L.; Salem, B.; Gergaud, P.; Moeyaert, J.; Martin, M.; Bertin, F.; Baron, T.

2018-05-01

In 0.3 Ga 0.7 As quantum wells (QW) embedded in AlGaAs barriers and grown on oxidized patterned (001) silicon substrates by metalorganic chemical vapor deposition using the aspect ratio trapping method are studied. An appropriate method combining cathodoluminescence and high resolution scanning transmission electron microscopy characterization is performed to spatially correlate the optical and structural properties of the QW. A triple period (TP) ordering along the ⟨111⟩ direction induced by the temperature decrease during the growth to favor indium incorporation and aligned along the oxidized patterns is observed in the QW. Local ordering affects the band gap and contributes to the decrease of the optical emission efficiency. Using thermal annealing, we were able to remove the TP ordering and improve the QW optical emission by two orders of magnitude.

Simple method for the growth of 4H silicon carbide on silicon substrate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Asghar, M.; Shahid, M. Y.; Iqbal, F.

In this study we report thermal evaporation technique as a simple method for the growth of 4H silicon carbide on p-type silicon substrate. A mixture of Si and C{sub 60} powder of high purity (99.99%) was evaporated from molybdenum boat. The as grown film was characterized by XRD, FTIR, UV-Vis Spectrophotometer and Hall Measurements. The XRD pattern displayed four peaks at 2Θ angles 28.55{sup 0}, 32.70{sup 0}, 36.10{sup 0} and 58.90{sup 0} related to Si (1 1 1), 4H-SiC (1 0 0), 4H-SiC (1 1 1) and 4H-SiC (2 2 2), respectively. FTIR, UV-Vis spectrophotometer and electrical properties further strengthenedmore » the 4H-SiC growth.« less

Surface-micromachined chain for use in microelectromechanical structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vernon, Sr., George E.

2001-01-01

A surface-micromachined chain and a microelectromechanical (MEM) structure incorporating such a chain are disclosed. The surface-micromachined chain can be fabricated in place on a substrate (e.g. a silicon substrate) by depositing and patterning a plurality of alternating layers of a chain-forming material (e.g. polycrystalline silicon) and a sacrificial material (e.g. silicon dioxide or a silicate glass). The sacrificial material is then removed by etching to release the chain for movement. The chain has applications for forming various types of MEM devices which include a microengine (e.g. an electrostatic motor) connected to rotate a drive sprocket, with the surface-micromachined chain beingmore » connected between the drive sprocket and one or more driven sprockets.« less

Plasmonic integrated circuits comprising metal waveguides, multiplexer/demultiplexer, detectors, and logic circuits on a silicon substrate

NASA Astrophysics Data System (ADS)

Fukuda, M.; Ota, M.; Sumimura, A.; Okahisa, S.; Ito, M.; Ishii, Y.; Ishiyama, T.

2017-05-01

A plasmonic integrated circuit configuration comprising plasmonic and electronic components is presented and the feasibility for high-speed signal processing applications is discussed. In integrated circuits, plasmonic signals transmit data at high transfer rates with light velocity. Plasmonic and electronic components such as wavelength-divisionmultiplexing (WDM) networks comprising metal wires, plasmonic multiplexers/demultiplexers, and crossing metal wires are connected via plasmonic waveguides on the nanometer or micrometer scales. To merge plasmonic and electronic components, several types of plasmonic components were developed. To ensure that the plasmonic components could be easily fabricated and monolithically integrated onto a silicon substrate using silicon complementary metal-oxide-semiconductor (CMOS)-compatible processes, the components were fabricated on a Si substrate and made from silicon, silicon oxides, and metal; no other materials were used in the fabrication. The plasmonic components operated in the 1300- and 1550-nm-wavelength bands, which are typically employed in optical fiber communication systems. The plasmonic logic circuits were formed by patterning a silicon oxide film on a metal film, and the operation as a half adder was confirmed. The computed plasmonic signals can propagate through the plasmonic WDM networks and be connected to electronic integrated circuits at high data-transfer rates.

SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution

NASA Astrophysics Data System (ADS)

Voorkamp, R.; Verschuuren, M. A.; van Brakel, R.

2016-10-01

Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 - 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and yield. Soft stamps, usually based on silicone rubber, behave fundamentally different compared to rigid stamps on the macro-, micro- and nanometer level. The main limitation of traditional silicones is that they are too soft to support sub-micron features against surface tension based stamp deformation and collapse [4] and handling a soft stamp to achieve accurate feature placement on wafer scales to allow overlay alignment with sub-100nm overlay accuracy.

Quantum-Well Infrared Photodetector (QWIP) Focal Plane Assembly

NASA Technical Reports Server (NTRS)

Jhabvala, Murzy; Jhabvala, Christine A.; Ewin, Audrey J.; Hess, Larry A.; Hartmann, Thomas M.; La, Anh T.

2012-01-01

A paper describes the Thermal Infrared Sensor (TIRS), a QWIP-based instrument intended to supplement the Operational Land Imager (OLI) for the Landsat Data Continuity Mission (LDCM). The TIRS instrument is a far-infrared imager operating in the pushbroom mode with two IR channels: 10.8 and 12 microns. The focal plane will contain three 640x512 QWIP arrays mounted on a silicon substrate. The silicon substrate is a custom-fabricated carrier board with a single layer of aluminum interconnects. The general fabrication process starts with a 4-in. (approx.10-cm) diameter silicon wafer. The wafer is oxidized, a single substrate contact is etched, and aluminum is deposited, patterned, and alloyed. This technology development is aimed at incorporating three large-format infrared detecting arrays based on GaAs QWIP technology onto a common focal plane with precision alignment of all three arrays. This focal plane must survive the rigors of flight qualification and operate at a temperature of 43 K (-230 C) for five years while orbiting the Earth. The challenges presented include ensuring thermal compatibility among all the components, designing and building a compact, somewhat modular system and ensuring alignment to very tight levels. The multi-array focal plane integrated onto a single silicon substrate is a new application of both QWIP array development and silicon wafer scale integration. The Invar-based assembly has been tested to ensure thermal reliability.

Method to fabricate multi-level silicon-based microstructures via use of an etching delay layer

DOEpatents

Manginell, Ronald P.; Schubert, W. Kent; Shul, Randy J.

2005-08-16

New methods for fabrication of silicon microstructures have been developed. In these methods, an etching delay layer is deposited and patterned so as to provide differential control on the depth of features being etched into a substrate material. Structures having features with different depth can be formed thereby in a single etching step.

Self-assembly of microscopic chiplets at a liquid–liquid–solid interface forming a flexible segmented monocrystalline solar cell

PubMed Central

Knuesel, Robert J.; Jacobs, Heiko O.

2010-01-01

This paper introduces a method for self-assembling and electrically connecting small (20–60 micrometer) semiconductor chiplets at predetermined locations on flexible substrates with high speed (62500 chips/45 s), accuracy (0.9 micrometer, 0.14°), and yield (> 98%). The process takes place at the triple interface between silicone oil, water, and a penetrating solder-patterned substrate. The assembly is driven by a stepwise reduction of interfacial free energy where chips are first collected and preoriented at an oil-water interface before they assemble on a solder-patterned substrate that is pulled through the interface. Patterned transfer occurs in a progressing linear front as the liquid layers recede. The process eliminates the dependency on gravity and sedimentation of prior methods, thereby extending the minimal chip size to the sub-100 micrometer scale. It provides a new route for the field of printable electronics to enable the integration of microscopic high performance inorganic semiconductors on foreign substrates with the freedom to choose target location, pitch, and integration density. As an example we demonstrate a fault-tolerant segmented flexible monocrystalline silicon solar cell, reducing the amount of Si that is used when compared to conventional rigid cells. PMID:20080682

Patterned growth of carbon nanotubes on Si substrates without predeposition of metal catalysts

NASA Astrophysics Data System (ADS)

Chen, Y.; Yu, J.

2005-07-01

Aligned carbon nanotubes (CNTs) can be readily synthesized on quartz or silicon-oxide-coated Si substrates using a chemical vapor deposition method, but it is difficult to grow them on pure Si substrates without predeposition of metal catalysts. We report that aligned CNTs were grown by pyrolysis of iron phthalocyanine at 1000°C on the templates created on Si substrates with simple mechanical scratching. Scanning electron microscopy and x-ray energy spectroscopy analysis revealed that the trenches and patterns created on the surface of Si substrates were preferred nucleation sites for nanotube growth due to a high surface energy, metastable surface structure, and possible capillarity effect. A two-step pyrolysis process maintained Fe as an active catalyst.

Silane coupling agent bearing a photoremovable succinimidyl carbonate for patterning amines on glass and silicon surfaces with controlled surface densities.

PubMed

Nakayama, Hidekazu; Nakanishi, Jun; Shimizu, Takahiro; Yoshino, Yutaro; Iwai, Hideo; Kaneko, Shingo; Horiike, Yasuhiro; Yamaguchi, Kazuo

2010-03-01

Patterned immobilization of synthetic and biological ligands on material surfaces with controlled surface densities is important for various bioanalytical and cell biological purposes. This paper describes the synthesis, characterization, and application of a novel silane coupling agent bearing a photoremovable succinimidyl carbonate, which enables the photopatterning of various primary amines on glass and silicon surfaces. The silane coupling agent is 1-[5-methoxy-2-nitro-4-(3-trimethoxysilylpropyloxy)phenyl]ethyl N-succinimidyl carbonate. The distinct feature of this molecule is that it has a photocleavable 2-nitrobenzyl switch between a trimethoxysilyl group and a succinimidyl carbonate, each reactive to the hydroxy groups of inorganic oxides and primary amines. Based on this molecular design, the compound allows for the one-step introduction of succinimidyl carbonates onto the surface of glass and silicon, immobilization of primary amines, and region-selective and dose-dependent release of the amines by near-UV irradiation. Therefore, we were able to pattern amine ligands on the substrates in given surface densities and arbitrary geometries by controlling the doses and regions of photoirradiation. These features were verified by UV-vis spectroscopy, contact angle measurements, infrared (IR) spectroscopy, X-ray photoelectron spectroscopy (XPS), ellipsometry, and atomic force microscopy (AFM). The compound was applied to form a chemical density gradient of amino-biotin on a silicon substrate in a range of 0.87-0.12 chains/nm(2) by controlling photoirradiation under a standard fluorescence microscope. Furthermore, we also succeeded in forming a chemical density gradient at a lower surface density range (0.15-0.011 chains/nm(2)) on the substrate by diluting the feed amino-biotin with an inert control amine.

Electron-beam-induced information storage in hydrogenated amorphous silicon devices

DOEpatents

Yacobi, B.G.

1985-03-18

A method for recording and storing information in a hydrogenated amorphous silicon device, comprising: depositing hydrogenated amorphous silicon on a substrate to form a charge collection device; and generating defects in the hydrogenated amorphous silicon device, wherein the defects act as recombination centers that reduce the lifetime of carriers, thereby reducing charge collection efficiency and thus in the charge collection mode of scanning probe instruments, regions of the hydrogenated amorphous silicon device that contain the defects appear darker in comparison to regions of the device that do not contain the defects, leading to a contrast formation for pattern recognition and information storage.

Patterned carbon nanotubes fabricated by the combination of microcontact printing and diblock copolymer micelles.

PubMed

Xu, Peng; Ji, Xin; Qi, Junlei; Yang, Hongmin; Zheng, Weitao; Abetz, Volker; Jiang, Shimei; Shen, Jiacong

2010-01-01

A convenient approach to synthesize patterned carbon nanotubes (CNTs) of three morphologies on printed substrates by combination of microcontact printing (microCP) and a plasma-enhanced chemical vapor deposition (PECVD) process is presented. Micelles of polystyrene-block-poly-(2-vinylpyridine) (PS-b-P2VP) in toluene were used as nanoreactors to fabricate FeCl3 in the core domains, and the complex solution was used as an ink to print films with polydimethylsiloxane (PDMS) stamps, different morphologies (porous, dots and stripes patterns) of the FeCl3-loaded micellar films were left onto silicon substrates after printed. After removing the polymer by thermal decomposition, the left iron oxide cluster arrays on the substrate were used as catalysts for the growth of CNTs by the process of PECVD, where the CNTs uniformly distributed on the substrates according to the morphologies of patterned catalysts arrays.

Rapid Biochemical Mixture Screening by Three-Dimensional Patterned Multifunctional Substrate with Ultra-Thin Layer Chromatography (UTLC) and Surface Enhanced Raman Scattering (SERS).

PubMed

Lee, Bi-Shen; Lin, Pi-Chen; Lin, Ding-Zheng; Yen, Ta-Jen

2018-01-11

We present a three-dimensional patterned (3DP) multifunctional substrate with the functions of ultra-thin layer chromatography (UTLC) and surface enhanced Raman scattering (SERS), which simultaneously enables mixture separation, target localization and label-free detection. This multifunctional substrate is comprised of a 3DP silicon nanowires array (3DP-SiNWA), decorated with silver nano-dendrites (AgNDs) atop. The 3DP-SiNWA is fabricated by a facile photolithographic process and low-cost metal assisted chemical etching (MaCE) process. Then, the AgNDs are decorated onto 3DP-SiNWA by a wet chemical reduction process, obtaining 3DP-AgNDs@SiNWA multifunctional substrates. With various patterns designed on the substrates, the signal intensity could be maximized by the excellent confinement and concentrated effects of patterns. By using this 3DP-AgNDs@SiNWA substrate to scrutinize the mixture of two visible dyes, the individual target could be recognized and further boosted the Raman signal of target 15.42 times comparing to the un-patterned AgNDs@SiNWA substrate. Therefore, such a three-dimensional patterned multifunctional substrate empowers rapid mixture screening, and can be readily employed in practical applications for biochemical assays, food safety and other fields.

High-fidelity large area nano-patterning of silicon with femtosecond light sheet

NASA Astrophysics Data System (ADS)

Sidhu, Mehra S.; Munjal, Pooja; Singh, Kamal P.

2018-01-01

We employ a femtosecond light sheet generated by a cylindrical lens to rapidly produce high-fidelity nano-structures over large area on silicon surface. The Fourier analysis of electron microscopy images of the laser-induced surface structures reveals sharp peaks indicating good homogeneity. We observed an emergence of second-order spatial periodicity on increasing the scan speed. Our reliable approach may rapidly nano-pattern curved solid surfaces and tiny objects for diverse potential applications in optical devices, structural coloring, plasmonic substrates and in high-harmonic generation.

III/V nano ridge structures for optical applications on patterned 300 mm silicon substrate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kunert, B.; Guo, W.; Mols, Y.

We report on an integration approach of III/V nano ridges on patterned silicon (Si) wafers by metal organic vapor phase epitaxy (MOVPE). Trenches of different widths (≤500 nm) were processed in a silicon oxide (SiO{sub 2}) layer on top of a 300 mm (001) Si substrate. The MOVPE growth conditions were chosen in a way to guarantee an efficient defect trapping within narrow trenches and to form a box shaped ridge with increased III/V volume when growing out of the trench. Compressively strained InGaAs/GaAs multi-quantum wells with 19% indium were deposited on top of the fully relaxed GaAs ridges as an activemore » material for optical applications. Transmission electron microcopy investigation shows that very flat quantum well (QW) interfaces were realized. A clear defect trapping inside the trenches is observed whereas the ridge material is free of threading dislocations with only a very low density of planar defects. Pronounced QW photoluminescence (PL) is detected from different ridge sizes at room temperature. The potential of these III/V nano ridges for laser integration on Si substrates is emphasized by the achieved ridge volume which could enable wave guidance and by the high crystal quality in line with the distinct PL.« less

Interface effects in the dissolution of silicon into thin gold films

NASA Technical Reports Server (NTRS)

Sankur, H.; Mccaldin, J. O.

1975-01-01

The dissolution of crystalline Si and amorphous Si substrates into thin films of evaporated Au was studied with an electron microprobe and scanning electron microscopy. The dissolution pattern was found to be nonuniform along the plane of the surface and dependent on the crystalline orientation of the Si substrate. The dissolution is greatly facilitated when a very thin layer of Pd is evaporated between the Si substrate and the Au film.

Characterization of nanostructured CuO-porous silicon matrix formed on copper-coated silicon substrate via electrochemical etching

NASA Astrophysics Data System (ADS)

Naddaf, M.; Mrad, O.; Al-zier, A.

2014-06-01

A pulsed anodic etching method has been utilized for nanostructuring of a copper-coated p-type (100) silicon substrate, using HF-based solution as electrolyte. Scanning electron microscopy reveals the formation of a nanostructured matrix that consists of island-like textures with nanosize grains grown onto fiber-like columnar structures separated with etch pits of grooved porous structures. Spatial micro-Raman scattering analysis indicates that the island-like texture is composed of single-phase cupric oxide (CuO) nanocrystals, while the grooved porous structure is barely related to formation of porous silicon (PS). X-ray diffraction shows that both the grown CuO nanostructures and the etched silicon layer have the same preferred (220) orientation. Chemical composition obtained by means of X-ray photoelectron spectroscopic (XPS) analysis confirms the presence of the single-phase CuO on the surface of the patterned CuO-PS matrix. As compared to PS formed on the bare silicon substrate, the room-temperature photoluminescence (PL) from the CuO-PS matrix exhibits an additional weak `blue' PL band as well as a blue shift in the PL band of PS (S-band). This has been revealed from XPS analysis to be associated with the enhancement in the SiO2 content as well as formation of the carbonyl group on the surface in the case of the CuO-PS matrix.

Fabrication of planarised conductively patterned diamond for bio-applications.

PubMed

Tong, Wei; Fox, Kate; Ganesan, Kumaravelu; Turnley, Ann M; Shimoni, Olga; Tran, Phong A; Lohrmann, Alexander; McFarlane, Thomas; Ahnood, Arman; Garrett, David J; Meffin, Hamish; O'Brien-Simpson, Neil M; Reynolds, Eric C; Prawer, Steven

2014-10-01

The development of smooth, featureless surfaces for biomedical microelectronics is a challenging feat. Other than the traditional electronic materials like silicon, few microelectronic circuits can be produced with conductive features without compromising the surface topography and/or biocompatibility. Diamond is fast becoming a highly sought after biomaterial for electrical stimulation, however, its inherent surface roughness introduced by the growth process limits its applications in electronic circuitry. In this study, we introduce a fabrication method for developing conductive features in an insulating diamond substrate whilst maintaining a planar topography. Using a combination of microwave plasma enhanced chemical vapour deposition, inductively coupled plasma reactive ion etching, secondary diamond growth and silicon wet-etching, we have produced a patterned substrate in which the surface roughness at the interface between the conducting and insulating diamond is approximately 3 nm. We also show that the patterned smooth topography is capable of neuronal cell adhesion and growth whilst restricting bacterial adhesion. Copyright © 2014 Elsevier B.V. All rights reserved.

Periodically structured Si pillars for high-performing heterojunction photodetectors

NASA Astrophysics Data System (ADS)

Melvin David Kumar, M.; Yun, Ju-Hyung; Kim, Joondong

2015-03-01

A periodical array of silicon (Si) micro pillar structures was fabricated on Si substrates using PR etching process. Indium tin oxide (ITO) layer of 80 nm thickness was deposited over patterned Si substrates so as to make ITO/n-Si heterojunction devices. The influences of width and period of pillars on the optical and electrical properties of prepared devices were investigated. The surface morphology of the Si substrates revealed the uniform array of pillar structures. The 5/10 (width/period) Si pillar pattern reduced the optical reflectance to 6.5% from 17% which is of 5/7 pillar pattern. The current rectifying ratio was found higher for the device in which the pillars are situated in optimum periods. At both visible (600 nm) and near infrared (900 nm) range of wavelengths, the 5/7 and 5/10 pillar patterned device exhibited the better photoresponses which are suitable for making advanced photodetectors. This highly transmittance and photoresponsive pillar patterned Si substrates with an ITO layer would be a promising device for various photoelectric applications.

Amorphous Silicon Nanowires Grown on Silicon Oxide Film by Annealing

NASA Astrophysics Data System (ADS)

Yuan, Zhishan; Wang, Chengyong; Chen, Ke; Ni, Zhonghua; Chen, Yunfei

2017-08-01

In this paper, amorphous silicon nanowires (α-SiNWs) were synthesized on (100) Si substrate with silicon oxide film by Cu catalyst-driven solid-liquid-solid mechanism (SLS) during annealing process (1080 °C for 30 min under Ar/H2 atmosphere). Micro size Cu pattern fabrication decided whether α-SiNWs can grow or not. Meanwhile, those micro size Cu patterns also controlled the position and density of wires. During the annealing process, Cu pattern reacted with SiO2 to form Cu silicide. More important, a diffusion channel was opened for Si atoms to synthesis α-SiNWs. What is more, the size of α-SiNWs was simply controlled by the annealing time. The length of wire was increased with annealing time. However, the diameter showed the opposite tendency. The room temperature resistivity of the nanowire was about 2.1 × 103 Ω·cm (84 nm diameter and 21 μm length). This simple fabrication method makes application of α-SiNWs become possible.

Method of forming crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method for fabricating single-crystal silicon microelectronic components on a silicon substrate and transferring same to a glass substrate. This is achieved by utilizing conventional silicon processing techniques for fabricating components of electronic circuits and devices on bulk silicon, wherein a bulk silicon surface is prepared with epitaxial layers prior to the conventional processing. The silicon substrate is bonded to a glass substrate and the bulk silicon is removed leaving the components intact on the glass substrate surface. Subsequent standard processing completes the device and circuit manufacturing. This invention is useful in applications requiring a transparent or insulating substrate, particularly for display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard electronics, and high temperature electronics.

Dewetting and deposition of thin films with insoluble surfactants from curved silicone hydrogel substrates.

PubMed

Bhamla, M Saad; Balemans, Caroline; Fuller, Gerald G

2015-07-01

We investigate the stabilizing effect of insoluble surfactant monolayers on thin aqueous films. We first describe an experimental platform that enables the formation of aqueous films laden with dipalmitoylphosphatidylcholine (DPPC) monolayers on curved silicone hydrogel (SiHy) substrates. We show that these surfactant layers extend the lifetime of the aqueous films. The films eventually "dewet" by the nucleation and growth of dry areas and the onset of this dewetting can be controlled by the surface rheology of the DPPC layer. We thus demonstrate that increasing the interfacial rheology of the DPPC layer leads to stable films that delay dewetting. We also show that dewetting can be exploited to controllably pattern the underlying curved SiHy substrates with DPPC layers. Copyright © 2015 Elsevier Inc. All rights reserved.

Gallium nitride heterostructures on 3D structured silicon.

PubMed

Fündling, Sönke; Sökmen, Unsal; Peiner, Erwin; Weimann, Thomas; Hinze, Peter; Jahn, Uwe; Trampert, Achim; Riechert, Henning; Bakin, Andrey; Wehmann, Hergo-Heinrich; Waag, Andreas

2008-10-08

We investigated GaN-based heterostructures grown on three-dimensionally patterned Si(111) substrates by metal organic vapour phase epitaxy, with the goal of fabricating well controlled high quality, defect reduced GaN-based nanoLEDs. The high aspect ratios of such pillars minimize the influence of the lattice mismatched substrate and improve the material quality. In contrast to other approaches, we employed deep etched silicon substrates to achieve a controlled pillar growth. For that a special low temperature inductively coupled plasma etching process has been developed. InGaN/GaN multi-quantum-well structures have been incorporated into the pillars. We found a pronounced dependence of the morphology of the GaN structures on the size and pitch of the pillars. Spatially resolved optical properties of the structures are analysed by cathodoluminescence.

Simple and fast polydimethylsiloxane (PDMS) patterning using a cutting plotter and vinyl adhesives to achieve etching results.

PubMed

Hyun Kim; Sun-Young Yoo; Ji Sung Kim; Zihuan Wang; Woon Hee Lee; Kyo-In Koo; Jong-Mo Seo; Dong-Il Cho

2017-07-01

Inhibition of polydimethylsiloxane (PDMS) polymerization could be observed when spin-coated over vinyl substrates. The degree of polymerization, partially curing or fully curing, depended on the PDMS thickness coated over the vinyl substrate. This characteristic was exploited to achieve simple and fast PDMS patterning method using a vinyl adhesive layer patterned through a cutting plotter. The proposed patterning method showed results resembling PDMS etching. Therefore, patterning PDMS over PDMS, glass, silicon, and gold substrates were tested to compare the results with conventional etching methods. Vinyl stencils with widths ranging from 200μm to 1500μm were used for the procedure. To evaluate the accuracy of the cutting plotter, stencil designed on the AutoCAD software and the actual stencil widths were compared. Furthermore, this method's accuracy was also evaluated by comparing the widths of the actual stencils and etched PDMS results.

Polarized luminescence of nc-Si-SiO x nanostructures on silicon substrates with patterned surface

NASA Astrophysics Data System (ADS)

Michailovska, Katerina; Mynko, Viktor; Indutnyi, Ivan; Shepeliavyi, Petro

2018-05-01

Polarization characteristics and spectra of photoluminescence (PL) of nc-Si-SiO x structures formed on the patterned and plane c-Si substrates are studied. The interference lithography with vacuum chalcogenide photoresist and anisotropic wet etching are used to form a periodic relief (diffraction grating) on the surface of the substrates. The studied nc-Si-SiO x structures were produced by oblique-angle deposition of Si monoxide in vacuum and the subsequent high-temperature annealing. The linear polarization memory (PM) effect in PL of studied structure on plane substrate is manifested only after the treatment of the structures in HF and is explained by the presence of elongated Si nanoparticles in the SiO x nanocolumns. But the PL output from the nc-Si-SiO x structure on the patterned substrate depends on how this radiation is polarized with respect to the grating grooves and is much less dependent on the polarization of the exciting light. The measured reflection spectra of nc-Si-SiO x structure on the patterned c-Si substrate confirmed the influence of pattern on the extraction of polarized PL.

Spontaneous Periodic Delamination of Thin Films To Form Crack-Free Metal and Silicon Ribbons with High Stretchability.

PubMed

Zhang, Qiuting; Tang, Yichao; Hajfathalian, Maryam; Chen, Chunxu; Turner, Kevin T; Dikin, Dmitriy A; Lin, Gaojian; Yin, Jie

2017-12-27

Design of electronic materials with high stretchability is of great importance for realizing soft and conformal electronics. One strategy of realizing stretchable metals and semiconductors is to exploit the buckling of materials bonded to elastomers. However, the level of stretchability is often limited by the cracking and fragmentation of the materials that occurs when constrained buckling occurs while bonded to the substrate. Here, we exploit a failure mechanism, spontaneous buckling-driven periodic delamination, to achieve high stretchability in metal and silicon films that are deposited on prestrained elastomer substrates. We find that both globally periodic buckle-delaminated pattern and ordered cracking patterns over large areas are observed in the spontaneously buckle-delaminated thin films. The geometry of periodic delaminated buckles and cracking periodicity can be predicted by theoretical models. By patterning the films into ribbons with widths smaller than the predicted cracking periodicity, we demonstrate the design of crack-free and spontaneous delaminated ribbons on highly prestrained elastomer substrates, which provides a high stretchability of about 120% and 400% in Si and Au ribbons, respectively. We find that the high stretchability is mainly attributed to the largely relaxed strain in the ribbons via spontaneous buckling-driven delamination, as made evident by the small maximum tensile strain in both ribbons, which is measured to be over 100 times smaller than that of the substrate prestrain.

Selective-area growth of GaN nanowires on SiO{sub 2}-masked Si (111) substrates by molecular beam epitaxy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kruse, J. E.; Doundoulakis, G.; Institute of Electronic Structure and Laser, Foundation for Research and Technology–Hellas, N. Plastira 100, 70013 Heraklion

2016-06-14

We analyze a method to selectively grow straight, vertical gallium nitride nanowires by plasma-assisted molecular beam epitaxy (MBE) at sites specified by a silicon oxide mask, which is thermally grown on silicon (111) substrates and patterned by electron-beam lithography and reactive-ion etching. The investigated method requires only one single molecular beam epitaxy MBE growth process, i.e., the SiO{sub 2} mask is formed on silicon instead of on a previously grown GaN or AlN buffer layer. We present a systematic and analytical study involving various mask patterns, characterization by scanning electron microscopy, transmission electron microscopy, and photoluminescence spectroscopy, as well asmore » numerical simulations, to evaluate how the dimensions (window diameter and spacing) of the mask affect the distribution of the nanowires, their morphology, and alignment, as well as their photonic properties. Capabilities and limitations for this method of selective-area growth of nanowires have been identified. A window diameter less than 50 nm and a window spacing larger than 500 nm can provide single nanowire nucleation in nearly all mask windows. The results are consistent with a Ga diffusion length on the silicon dioxide surface in the order of approximately 1 μm.« less

Magnetic Dirac Fermions and Chern Insulator Supported on Pristine Silicon Surface

NASA Astrophysics Data System (ADS)

Fu, Huixia; Liu, Zheng; Sun, Jia-Tao; Meng, Sheng

Emergence of ferromagnetism in non-magnetic semiconductors is strongly desirable, especially in topological materials thanks to the possibility to achieve quantum anomalous Hall effect. Based on first principles calculations, we propose that for Si thin film grown on metal substrate, the pristine Si(111)-r3xr3 surface with a spontaneous weak reconstruction has a strong tendency of ferromagnetism and nontrivial topological properties, characterized by spin polarized Dirac-fermion surface states. In contrast to conventional routes relying on introduction of alien charge carriers or specially patterned substrates, the spontaneous magnetic order and spin-orbit coupling on the pristine silicon surface together gives rise to quantized anomalous Hall effect with a finite Chern number C = -1. This work suggests exciting opportunities in silicon-based spintronics and quantum computing free from alien dopants or proximity effects.

Method of forming crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1995-03-21

A method is disclosed for fabricating single-crystal silicon microelectronic components on a silicon substrate and transferring same to a glass substrate. This is achieved by utilizing conventional silicon processing techniques for fabricating components of electronic circuits and devices on bulk silicon, wherein a bulk silicon surface is prepared with epitaxial layers prior to the conventional processing. The silicon substrate is bonded to a glass substrate and the bulk silicon is removed leaving the components intact on the glass substrate surface. Subsequent standard processing completes the device and circuit manufacturing. This invention is useful in applications requiring a transparent or insulating substrate, particularly for display manufacturing. Other applications include sensors, actuators, optoelectronics, radiation hard electronics, and high temperature electronics. 7 figures.

Dielectric fluid directional spreading under the action of corona discharge

NASA Astrophysics Data System (ADS)

Zhou, Shangru; Liu, Jie; Hu, Qun; Jiang, Teng; Yang, Jinchu; Liu, Sheng; Zheng, Huai

2018-01-01

Liquid spreading is a very common nature phenomenon and of significant importance for a broad range of applications. In this study, a dielectric fluid directional spreading phenomenon is presented. Under the action of corona discharge, a dielectric fluid, here a typical silicone directionally spreads along conductive patterns on conductive/nonconductive substrates. Directional spreading behaviors of silicone were experimentally observed on different conductive patterns in detail. Spreading speeds were analyzed at different driving voltages, which induced the corona discharge. The presented phenomenon may be useful to inspire several techniques of manipulating liquid transportation and fabricating micropatterns.

Fabrication of amorphous silica nanowires via oxygen plasma treatment of polymers on silicon

NASA Astrophysics Data System (ADS)

Chen, Zhuojie; She, Didi; Chen, Qinghua; Li, Yanmei; Wu, Wengang

2018-02-01

We demonstrate a facile non-catalytic method of fabricating silica nanowires at room temperature. Different polymers including photoresists, parylene C and polystyrene are patterned into pedestals on the silicon substrates. The silica nanowires are obtained via the oxygen plasma treatment on those pedestals. Compared to traditional strategies of silica nanowire fabrication, this method is much simpler and low-cost. Through designing the proper initial patterns and plasma process parameters, the method can be used to fabricate various regiment nano-scale silica structure arrays in any laboratory with a regular oxygen-plasma-based cleaner or reactive-ion-etching equipment.

Metallic coatings on silicon substrates, and methods of forming metallic coatings on silicon substrates

DOEpatents

Branagan, Daniel J [Idaho Falls, ID; Hyde, Timothy A [Idaho Falls, ID; Fincke, James R [Los Alamos, NM

2008-03-11

The invention includes methods of forming a metallic coating on a substrate which contains silicon. A metallic glass layer is formed over a silicon surface of the substrate. The invention includes methods of protecting a silicon substrate. The substrate is provided within a deposition chamber along with a deposition target. Material from the deposition target is deposited over at least a portion of the silicon substrate to form a protective layer or structure which contains metallic glass. The metallic glass comprises iron and one or more of B, Si, P and C. The invention includes structures which have a substrate containing silicon and a metallic layer over the substrate. The metallic layer contains less than or equal to about 2 weight % carbon and has a hardness of at least 9.2 GPa. The metallic layer can have an amorphous microstructure or can be devitrified to have a nanocrystalline microstructure.

Fabrication of resonant patterns using thermal nano-imprint lithography for thin-film photovoltaic applications.

PubMed

Khaleque, Tanzina; Svavarsson, Halldor Gudfinnur; Magnusson, Robert

2013-07-01

A single-step, low-cost fabrication method to generate resonant nano-grating patterns on poly-methyl-methacrylate (PMMA; plexiglas) substrates using thermal nano-imprint lithography is reported. A guided-mode resonant structure is obtained by subsequent deposition of thin films of transparent conductive oxide and amorphous silicon on the imprinted area. Referenced to equivalent planar structures, around 25% and 45% integrated optical absorbance enhancement is observed over the 450-nm to 900-nm wavelength range in one- and two-dimensional patterned samples, respectively. The fabricated elements provided have 300-nm periods. Thermally imprinted thermoplastic substrates hold potential for low-cost fabrication of nano-patterned thin-film solar cells for efficient light management.

Laser processing for strengthening of the self-restoring metal-elastomer interface on a silicone sheet

NASA Astrophysics Data System (ADS)

Yasuda, Kiyokazu

2012-08-01

A self-restoring microsystem is a unique concept which realizes the sensing functionality and robust interface which mechanically and electrically connects a deformable object such as a human body with printed electronic devices. For this purpose, the formation of conductive wiring on an elastomer substrate was attempted using the nickel ink printing process. Before the wiring process, surface patterning of a silicone sheet by a galvano-scanned infrared laser was conducted for the enhancement of interface adhesion of the metal deposit and polymer. Characterization of the fabricated pattern was conducted by optical microscopy. The novel method was successfully demonstrated as a fabrication of selective patterns of metal particles on self-restoring MEMS.

Mechanism of the growth of amorphous and microcrystalline silicon from silicon tetrafluoride and hydrogen

NASA Astrophysics Data System (ADS)

Okada, Y.; Chen, J.; Campbell, I. H.; Fauchet, P. M.; Wagner, S.

1990-02-01

We study the growth of amorphous (a-Si:H,F) and of microcrystalline (μc-Si) silicon over trench patterns in crystalline silicon substrates. We vary the conditions of the SiF4-H2 glow discharge from deposition to etching. All deposited films form lips at the trench mouth and are uniformly thick on the trench walls. Therefore, surface diffusion is not important. The results of a Monte Carlo simulation suggest that film growth is governed by a single growth species with a low (˜0.2) sticking coefficient, in combination with a highly reactive etching species.

Method for fabricating an ultra-low expansion mask blank having a crystalline silicon layer

DOEpatents

Cardinale, Gregory F.

2002-01-01

A method for fabricating masks for extreme ultraviolet lithography (EUVL) using Ultra-Low Expansion (ULE) substrates and crystalline silicon. ULE substrates are required for the necessary thermal management in EUVL mask blanks, and defect detection and classification have been obtained using crystalline silicon substrate materials. Thus, this method provides the advantages for both the ULE substrate and the crystalline silicon in an Extreme Ultra-Violet (EUV) mask blank. The method is carried out by bonding a crystalline silicon wafer or member to a ULE wafer or substrate and thinning the silicon to produce a 5-10 .mu.m thick crystalline silicon layer on the surface of the ULE substrate. The thinning of the crystalline silicon may be carried out, for example, by chemical mechanical polishing and if necessary or desired, oxidizing the silicon followed by etching to the desired thickness of the silicon.

Flexible Nonstick Replica Mold for Transfer Printing of Ag Ink.

PubMed

Lee, Bong Kuk; Yu, Han Young; Kim, Yarkyeon; Yoon, Yong Sun; Jang, Won Ik; Do, Lee-Mi; Park, Ji-Ho; Park, Jaehoon

2016-03-01

We report the fabrication of flexible replica molds for transfer printing of Ag ink on a rigid glass substrate. As mold precursors, acrylic mixtures were prepared from silsesquioxane-based materials, silicone acrylate, poly(propylene glycol) diacrylate, 3,3,4,4,5,5,6,6,7,7,8,8, 9,9,10,10,10-heptadecafluorodecyl methacrylate, and photoinitiator. By using these materials, the replica molds were fabricated from a silicon master onto a flexible substrate by means of UV-assisted molding process at room temperature. The wettability of Ag ink decreased with increase in the water contact angle of replica molds. On the other hand, the transfer rate of Ag ink onto adhesive-modified substrates increased with increase in the water contact angle of replica molds. Transferred patterns were found to be thermally stable on the photocurable adhesive layer, whereas Ag-ink patterns transferred on non-photocurable adhesives were distorted by thermal treatment. We believe that these characteristics of replica molds and adhesives offer a new strategy for the development of the transfer printing of solution-based ink materials.

Enhancement of phonon backscattering due to confinement of ballistic phonon pathways in silicon as studied with a microfabricated phonon spectrometer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Otelaja, O. O.; Robinson, R. D., E-mail: rdr82@cornell.edu

2015-10-26

In this work, the mechanism for enhanced phonon backscattering in silicon is investigated. An understanding of phonon propagation through substrates has implications for engineering heat flow at the nanoscale, for understanding sources of decoherence in quantum systems, and for realizing efficient phonon-mediated particle detectors. In these systems, phonons that backscatter from the bottom of substrates, within the crystal or from interfaces, often contribute to the overall detector signal. We utilize a microscale phonon spectrometer, comprising superconducting tunnel junction emitters and detectors, to specifically probe phonon backscattering in silicon substrates (∼500 μm thick). By etching phonon “enhancers” or deep trenches (∼90 μm) aroundmore » the detectors, we show that the backscattered signal level increases by a factor of ∼2 for two enhancers versus one enhancer. Using a geometric analysis of the phonon pathways, we show that the mechanism of the backscattered phonon enhancement is due to confinement of the ballistic phonon pathways and increased scattering off the enhancer walls. Our result is applicable to the geometric design and patterning of substrates that are employed in phonon-mediated detection devices.« less

Development of a templated approach to fabricate diamond patterns on various substrates.

PubMed

Shimoni, Olga; Cervenka, Jiri; Karle, Timothy J; Fox, Kate; Gibson, Brant C; Tomljenovic-Hanic, Snjezana; Greentree, Andrew D; Prawer, Steven

2014-06-11

We demonstrate a robust templated approach to pattern thin films of chemical vapor deposited nanocrystalline diamond grown from monodispersed nanodiamond (mdND) seeds. The method works on a range of substrates, and we herein demonstrate the method using silicon, aluminum nitride (AlN), and sapphire substrates. Patterns are defined using photo- and e-beam lithography, which are seeded with mdND colloids and subsequently introduced into microwave assisted chemical vapor deposition reactor to grow patterned nanocrystalline diamond films. In this study, we investigate various factors that affect the selective seeding of different substrates to create high quality diamond thin films, including mdND surface termination, zeta potential, surface treatment, and plasma cleaning. Although the electrostatic interaction between mdND colloids and substrates is the main process driving adherence, we found that chemical reaction (esterification) or hydrogen bonding can potentially dominate the seeding process. Leveraging the knowledge on these different interactions, we optimize fabrication protocols to eliminate unwanted diamond nucleation outside the patterned areas. Furthermore, we have achieved the deposition of patterned diamond films and arrays over a range of feature sizes. This study contributes to a comprehensive understanding of the mdND-substrate interaction that will enable the fabrication of integrated nanocrystalline diamond thin films for microelectronics, sensors, and tissue culturing applications.

Role of near-field enhancement in plasmonic laser nanoablation using gold nanorods on a silicon substrate.

PubMed

Harrison, R K; Ben-Yakar, Adela

2010-10-11

We present experimental results for the plasmonic laser ablation of silicon with nanoscale features as small as 22 x 66 nm using single near-infrared, femtosecond laser pulses incident on gold nanorods. Near the ablation threshold, these features are photo-imprints of gold nanorod particles positioned on the surface of the silicon and have feature sizes similar to the nanorods. The single rod-shaped ablation pattern matches the enhancement patterns of the Poynting vector magnitude on the surface of silicon, implying that the ablation is a result of the plasmonic enhancement of the incident electromagnetic waves in the near-field of the particles. Interestingly, the ablation pattern is different from the two separated holes at the ends of the nanorod, as would be expected from the electric field--|E|(2) enhancement pattern. We measured the plasmonic ablation threshold fluence to be almost two orders of magnitude less than the femtosecond laser ablation threshold of silica, present in the thin native oxide layer on the surface of silicon. This value also agrees with the enhancement of the Poynting vector of a nanorod on silicon as calculated with electromagnetic simulations. We thus conclude that plasmonic ablation with plasmonic nanoparticles depends directly on the polarization and the value of the near-field enhancement of the Poynting vector and not the square of the electric field as previously suggested.

Strain induced on (TMTSF){2}ReO{4} microwires deposited on a silicon substrate

NASA Astrophysics Data System (ADS)

Colin, C. V.; Joo, N.; Pasquier, C. R.

2009-12-01

We present the successful recrystallization of Bechgaard salts with the microwire shape using the drop casting method. The samples are deposited on a substrate with previously prepared patterns made by optical lithography. The physical properties of the microwires are shown. The excellent transport properties show that this technique provides a new method for the tuning of the physical properties of molecular conductors and the first step toward applications. The pressure effects of the substrate on the conduction are discussed.

Thin Film Transistors On Plastic Substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

2004-01-20

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

Optical and electrical properties of GaN-based light emitting diodes grown on micro- and nano-scale patterned Si substrate

NASA Astrophysics Data System (ADS)

Chiu, Ching-Hsueh; Lin, Chien-Chung; Deng, Dongmei; Kuo, Hao-Chung; Lau, Kei-May

2011-10-01

We investigate the optical and electrical characteristics of the GaN-based light emitting diodes (LEDs) grown on Micro and Nano-scale Patterned silicon substrate (MPLEDs and NPLEDs). The transmission electron microscopy (TEM) images reveal the suppression of threading dislocation density in InGaN/GaN structure on nano-pattern substrate due to nanoscale epitaxial lateral overgrowth (NELOG). The plan-view and cross-section cathodoluminescence (CL) mappings show less defective and more homogeneous active quantum well region growth on nano-porous substrates. From temperature dependent photoluminescence (PL) and low temperature time-resolved photoluminescence (TRPL) measurement, NPLEDs has better carrier confinement and higher radiative recombination rate than MPLEDs. In terms of device performance, NPLEDs exhibits smaller electroluminescence (EL) peak wavelength blue shift, lower reverse leakage current and decreases efficiency droop compared with the MPLEDs. These results suggest the feasibility of using NPSi for the growth of high quality and power LEDs on Si substrates.

Fabrication of Buried Nanochannels From Nanowire Patterns

NASA Technical Reports Server (NTRS)

Choi, Daniel; Yang, Eui-Hyeok

2007-01-01

A method of fabricating channels having widths of tens of nanometers in silicon substrates and burying the channels under overlying layers of dielectric materials has been demonstrated. With further refinement, the method might be useful for fabricating nanochannels for manipulation and analysis of large biomolecules at single-molecule resolution. Unlike in prior methods, burying the channels does not involve bonding of flat wafers to the silicon substrates to cover exposed channels in the substrates. Instead, the formation and burying of the channels are accomplished in a more sophisticated process that is less vulnerable to defects in the substrates and less likely to result in clogging of, or leakage from, the channels. In this method, the first step is to establish the channel pattern by forming an array of sacrificial metal nanowires on an SiO2-on-Si substrate. In particular, the wire pattern is made by use of focused-ion-beam (FIB) lithography and a subsequent metallization/lift-off process. The pattern of metal nanowires is then transferred onto the SiO2 layer by reactive-ion etching, which yields sacrificial SiO2 nanowires covered by metal. After removal of the metal covering the SiO2 nanowires, what remains are SiO2 nanowires on an Si substrate. Plasma-enhanced chemical vapor deposition (PECVD) is used to form a layer of a dielectric material over the Si substrate and over the SiO2 wires on the surface of the substrate. FIB milling is then performed to form trenches at both ends of each SiO2 wire. The trenches serve as openings for the entry of chemicals that etch SiO2 much faster than they etch Si. Provided that the nanowires are not so long that the diffusion of the etching chemicals is blocked, the sacrificial SiO2 nanowires become etched out from between the dielectric material and the Si substrate, leaving buried channels. At the time of reporting the information for this article, channels 3 m long, 20 nm deep, and 80 nm wide (see figure) had been fabricated by this method.

PVD Silicon Carbide as a Thin Film Packaging Technology for Antennas on LCP Substrates for Harsh Environments

NASA Technical Reports Server (NTRS)

Scardelletti, Maximilian C.; Stanton, John W.; Ponchak, George E.; Jordan, Jennifer L.; Zorman, Christian A.

2010-01-01

This paper describes an effort to develop a thin film packaging technology for microfabricated planar antennas on polymeric substrates based on silicon carbide (SiC) films deposited by physical vapor deposition (PVD). The antennas are coplanar waveguide fed dual frequency folded slot antennas fabricated on liquid crystal polymer (LCP) substrates. The PVD SiC thin films were deposited directly onto the antennas by RF sputtering at room temperature at a chamber pressure of 30 mTorr and a power level of 300 W. The SiC film thickness is 450 nm. The return loss and radiation patterns were measured before and after the SiC-coated antennas were submerged into perchloric acid for 1 hour. No degradation in RF performance or physical integrity of the antenna was observed.

Selective Growth of Metallic and Semiconducting Single Walled Carbon Nanotubes on Textured Silicon.

PubMed

Jang, Mira; Lee, Jongtaek; Park, Teahee; Lee, Junyoung; Yang, Jonghee; Yi, Whikun

2016-03-01

We fabricated the etched Si substrate having the pyramidal pattern size from 0.5 to 4.2 μm by changing the texturing process parameters, i.e., KOH concentration, etching time, and temperature. Single walled carbon nanotubes (SWNTs) were then synthesized on the etched Si substrates with different pyramidal pattern by chemical vapor deposition. We investigated the optical and electronic properties of SWNT film grown on the etched Si substrates of different morphology by using scanning electron microscopy, Raman spectroscopy and conducting probe atomic force microscopy. We confirmed that the morphology of substrate strongly affected the selective growth of the SWNT film. Semiconducting SWNTs were formed on larger pyramidal sized Si wafer with higher ratio compared with SWNTs on smaller pyramidal sized Si.

Silicon on insulator self-aligned transistors

DOEpatents

McCarthy, Anthony M.

2003-11-18

A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

RF performances of inductors integrated on localized p+-type porous silicon regions

PubMed Central

2012-01-01

To study the influence of localized porous silicon regions on radiofrequency performances of passive devices, inductors were integrated on localized porous silicon regions, full porous silicon sheet, bulk silicon and glass substrates. In this work, a novel strong, resistant fluoropolymer mask is introduced to localize the porous silicon on the silicon wafer. Then, the quality factors and resonant frequencies obtained with the different substrates are presented. A first comparison is done between the performances of inductors integrated on same-thickness localized and full porous silicon sheet layers. The effect of the silicon regions in the decrease of performances of localized porous silicon is discussed. Then, the study shows that the localized porous silicon substrate significantly reduces losses in comparison with high-resistivity silicon or highly doped silicon bulks. These results are promising for the integration of both passive and active devices on the same silicon/porous silicon hybrid substrate. PMID:23009746

Amorphous Silicon Nanowires Grown on Silicon Oxide Film by Annealing.

PubMed

Yuan, Zhishan; Wang, Chengyong; Chen, Ke; Ni, Zhonghua; Chen, Yunfei

2017-08-10

In this paper, amorphous silicon nanowires (α-SiNWs) were synthesized on (100) Si substrate with silicon oxide film by Cu catalyst-driven solid-liquid-solid mechanism (SLS) during annealing process (1080 °C for 30 min under Ar/H 2 atmosphere). Micro size Cu pattern fabrication decided whether α-SiNWs can grow or not. Meanwhile, those micro size Cu patterns also controlled the position and density of wires. During the annealing process, Cu pattern reacted with SiO 2 to form Cu silicide. More important, a diffusion channel was opened for Si atoms to synthesis α-SiNWs. What is more, the size of α-SiNWs was simply controlled by the annealing time. The length of wire was increased with annealing time. However, the diameter showed the opposite tendency. The room temperature resistivity of the nanowire was about 2.1 × 10 3  Ω·cm (84 nm diameter and 21 μm length). This simple fabrication method makes application of α-SiNWs become possible.

Preferred orientations of laterally grown silicon films over amorphous substrates using the vapor-liquid-solid technique

NASA Astrophysics Data System (ADS)

LeBoeuf, J. L.; Brodusch, N.; Gauvin, R.; Quitoriano, N. J.

2014-12-01

A novel method has been optimized so that adhesion layers are no longer needed to reliably deposit patterned gold structures on amorphous substrates. Using this technique allows for the fabrication of amorphous oxide templates known as micro-crucibles, which confine a vapor-liquid-solid (VLS) catalyst of nominally pure gold to a specific geometry. Within these confined templates of amorphous materials, faceted silicon crystals have been grown laterally. The novel deposition technique, which enables the nominally pure gold catalyst, involves the undercutting of an initial chromium adhesion layer. Using electron backscatter diffraction it was found that silicon nucleated in these micro-crucibles were 30% single crystals, 45% potentially twinned crystals and 25% polycrystals for the experimental conditions used. Single, potentially twinned, and polycrystals all had an aversion to growth with the {1 0 0} surface parallel to the amorphous substrate. Closer analysis of grain boundaries of potentially twinned and polycrystalline samples revealed that the overwhelming majority of them were of the 60° Σ3 coherent twin boundary type. The large amount of coherent twin boundaries present in the grown, two-dimensional silicon crystals suggest that lateral VLS growth occurs very close to thermodynamic equilibrium. It is suggested that free energy fluctuations during growth or cooling, and impurities were the causes for this twinning.

Acoustic backing in 3-D integration of CMUT with front-end electronics.

PubMed

Berg, Sigrid; Rønnekleiv, Arne

2012-07-01

Capacitive micromachined ultrasonic transducers (CMUTs) have shown promising qualities for medical imaging. However, there are still some problems to be investigated, and some challenges to overcome. Acoustic backing is necessary to prevent SAWs excited in the surface of the silicon substrate from affecting the transmit pattern from the array. In addition, echoes resulting from bulk waves in the substrate must be removed. There is growing interest in integrating electronic circuits to do some of the beamforming directly below the transducer array. This may be easier to achieve for CMUTs than for traditional piezoelectric transducers. We will present simulations showing that the thickness of the silicon substrate and thicknesses and acoustic properties of the bonding material must be considered, especially when designing highfrequency transducers. Through simulations, we compare the acoustic properties of 3-D stacks bonded with three different bonding techniques; solid-liquid interdiffusion (SLID) bonding, direct fusion bonding, and anisotropic conductive adhesives (ACA). We look at a CMUT array with a center frequency of 30 MHz and three silicon wafers underneath, having a total silicon thickness of 100 μm. We find that fusion bonding is most beneficial if we want to prevent surface waves from damaging the array response, but SLID and ACA are also promising if bonding layer thicknesses can be reduced.

Investigation on nonlinear optical properties of MoS2 nanoflakes grown on silicon and quartz substrates

NASA Astrophysics Data System (ADS)

Bayesteh, Samaneh; Zahra Mortazavi, Seyedeh; Reyhani, Ali

2018-05-01

In this study, MoS2 nanoflakes were directly grown on different substrates—Si/SiO2 and quartz—by one-step thermal chemical vapor deposition using MoO3 and sulfide powders as precursors. Scanning electron microscopy and x-ray diffraction patterns demonstrated the formation of MoS2 structures on both substrates. Moreover, UV-visible and photoluminescence analysis confirmed the formation of MoS2 few-layer structures. According to Raman spectroscopy, by assessment of the line width and frequency shift differences between the and A 1g, it was inferred that the MoS2 grown on the silicon substrate was monolayer and that grown on the quartz substrate was multilayer. In addition, open-aperture and close-aperture Z-scan techniques were employed to study the nonlinear optical properties including nonlinear absorption and nonlinear refraction of the grown MoS2. All experiments were performed using a diode laser with a wavelength of 532 nm as the light source. It is noticeable that both samples demonstrate obvious self-defocusing behavior. The monolayer MoS2 grown on the silicon substrate displayed considerable two-photon absorption while, the multilayer MoS2 synthesized on the quartz exhibited saturable absorption. In general, few-layered MoS2 would be useful for the development of nanophotonic devices like optical limiters, optical switchers, etc.

Nanostructured Diamond Device for Biomedical Applications.

PubMed

Fijalkowski, M; Karczemska, A; Lysko, J M; Zybala, R; KozaneckI, M; Filipczak, P; Ralchenko, V; Walock, M; Stanishevsky, A; Mitura, S

2015-02-01

Diamond is increasingly used in biomedical applications because of its unique properties such as the highest thermal conductivity, good optical properties, high electrical breakdown voltage as well as excellent biocompatibility and chemical resistance. Diamond has also been introduced as an excellent substrate to make the functional microchip structures for electrophoresis, which is the most popular separation technique for the determination of analytes. In this investigation, a diamond electrophoretic chip was manufactured by a replica method using a silicon mold. A polycrystalline 300 micron-thick diamond layer was grown by the microwave plasma-assisted CVD (MPCVD) technique onto a patterned silicon substrate followed by the removal of the substrate. The geometry of microstructure, chemical composition, thermal and optical properties of the resulting free-standing diamond electrophoretic microchip structure were examined by CLSM, SFE, UV-Vis, Raman, XRD and X-ray Photoelectron Spectroscopy, and by a modified laser flash method for thermal property measurements.

Deconvoluting the mechanism of microwave annealing of block copolymer thin films.

PubMed

Jin, Cong; Murphy, Jeffrey N; Harris, Kenneth D; Buriak, Jillian M

2014-04-22

The self-assembly of block copolymer (BCP) thin films is a versatile method for producing periodic nanoscale patterns with a variety of shapes. The key to attaining a desired pattern or structure is the annealing step undertaken to facilitate the reorganization of nanoscale phase-segregated domains of the BCP on a surface. Annealing BCPs on silicon substrates using a microwave oven has been shown to be very fast (seconds to minutes), both with and without contributions from solvent vapor. The mechanism of the microwave annealing process remains, however, unclear. This work endeavors to uncover the key steps that take place during microwave annealing, which enable the self-assembly process to proceed. Through the use of in situ temperature monitoring with a fiber optic temperature probe in direct contact with the sample, we have demonstrated that the silicon substrate on which the BCP film is cast is the dominant source of heating if the doping of the silicon wafer is sufficiently low. Surface temperatures as high as 240 °C are reached in under 1 min for lightly doped, high resistivity silicon wafers (n- or p-type). The influence of doping, sample size, and BCP composition was analyzed to rule out other possible mechanisms. In situ temperature monitoring of various polymer samples (PS, P2VP, PMMA, and the BCPs used here) showed that the polymers do not heat to any significant extent on their own with microwave irradiation of this frequency (2.45 GHz) and power (∼600 W). It was demonstrated that BCP annealing can be effectively carried out in 60 s on non-microwave-responsive substrates, such as highly doped silicon, indium tin oxide (ITO)-coated glass, glass, and Kapton, by placing a piece of high resistivity silicon wafer in contact with the sample-in this configuration, the silicon wafer is termed the heating element. Annealing and self-assembly of polystyrene-block-poly(2-vinylpyridine) (PS-b-P2VP) and polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) BCPs into horizontal cylinder structures were shown to take place in under 1 min, using a silicon wafer heating element, in a household microwave oven. Defect densities were calculated and were shown to decrease with higher maximum obtained temperatures. Conflicting results in the literature regarding BCP annealing with microwave are explained in light of the results obtained in this study.

Fabrication of poly(ethylene glycol) hydrogel microstructures using photolithography

NASA Technical Reports Server (NTRS)

Revzin, A.; Russell, R. J.; Yadavalli, V. K.; Koh, W. G.; Deister, C.; Hile, D. D.; Mellott, M. B.; Pishko, M. V.

2001-01-01

The fabrication of hydrogel microstructures based upon poly(ethylene glycol) diacrylates, dimethacrylates, and tetraacrylates patterned photolithographically on silicon or glass substrates is described. A silicon/silicon dioxide surface was treated with 3-(trichlorosilyl)propyl methacrylate to form a self-assembled monolayer (SAM) with pendant acrylate groups. The SAM presence on the surface was verified using ellipsometry and time-of-flight secondary ion mass spectrometry. A solution containing an acrylated or methacrylated poly(ethylene glycol) derivative and a photoinitiator (2,2-dimethoxy-2-phenylacetophenone) was spin-coated onto the treated substrate, exposed to 365 nm ultraviolet light through a photomask, and developed with either toluene, water, or supercritical CO2. As a result of this process, three-dimensional, cross-linked PEG hydrogel microstructures were immobilized on the surface. Diameters of cylindrical array members were varied from 600 to 7 micrometers by the use of different photomasks, while height varied from 3 to 12 micrometers, depending on the molecular weight of the PEG macromer. In the case of 7 micrometers diameter elements, as many as 400 elements were reproducibly generated in a 1 mm2 square pattern. The resultant hydrogel patterns were hydrated for as long as 3 weeks without delamination from the substrate. In addition, micropatterning of different molecular weights of PEG was demonstrated. Arrays of hydrogel disks containing an immobilized protein conjugated to a pH sensitive fluorophore were also prepared. The pH sensitivity of the gel-immobilized dye was similar to that in an aqueous buffer, and no leaching of the dye-labeled protein from the hydrogel microstructure was observed over a 1 week period. Changes in fluorescence were also observed for immobilized fluorophore labeled acetylcholine esterase upon the addition of acetyl acholine.

Study of surface reaction during selective epitaxy growth of silicon by thermodynamic analysis and density functional theory calculation

NASA Astrophysics Data System (ADS)

Mayangsari, Tirta R.; Yusup, Luchana L.; Park, Jae-Min; Blanquet, Elisabeth; Pons, Michel; Jung, Jongwan; Lee, Won-Jun

2017-06-01

We modeled and simulated the surface reaction of silicon precursor on different surfaces by thermodynamic analysis and density functional theory calculation. We considered SiH2Cl2 and argon as the silicon precursor and the carrier gas without etchant gas. First, the equilibrium composition of both gaseous and solid species was analyzed as a function of process temperature. SiCl4 is the dominant gaseous species at below 750 °C, and SiCl2 and HCl are dominant at higher temperatures, and the yield of silicon decreases with increasing temperature over 700 °C due to the etching of silicon by HCl. The yield of silicon for SiO2 substrate is lower than that for silicon substrate, especially at 1000 °C or higher. Zero deposition yield and the etching of SiO2 substrate at higher temperatures leads to selective growth on silicon substrate. Next, the adsorption and the reaction of silicon precursor was simulated on H-terminated silicon (100) substrate and on OH-terminated β-cristobalite substrate. The adsorption and reaction of a SiH2Cl2 molecule are spontaneous for both Si and SiO2 substrates. However, the energy barrier for reaction is very small (6×10-4 eV) for Si substrate, whereas the energy barrier is high (0.33 eV) for SiO2 substrate. This makes the differences in growth rate, which also supports the experimental results in literature.

Epitaxial growth of silicon for layer transfer

DOEpatents

Teplin, Charles; Branz, Howard M

2015-03-24

Methods of preparing a thin crystalline silicon film for transfer and devices utilizing a transferred crystalline silicon film are disclosed. The methods include preparing a silicon growth substrate which has an interface defining substance associated with an exterior surface. The methods further include depositing an epitaxial layer of silicon on the silicon growth substrate at the surface and separating the epitaxial layer from the substrate substantially along the plane or other surface defined by the interface defining substance. The epitaxial layer may be utilized as a thin film of crystalline silicon in any type of semiconductor device which requires a crystalline silicon layer. In use, the epitaxial transfer layer may be associated with a secondary substrate.

Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

NASA Astrophysics Data System (ADS)

Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

2003-06-01

We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

Anti-reflective device having an anti-reflective surface formed of silicon spikes with nano-tips

NASA Technical Reports Server (NTRS)

Bae, Youngsam (Inventor); Manohara, Harish (Inventor); Mobasser, Sohrab (Inventor); Lee, Choonsup (Inventor)

2011-01-01

Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.

Anti- reflective device having an anti-reflection surface formed of silicon spikes with nano-tips

NASA Technical Reports Server (NTRS)

Bae, Youngsman (Inventor); Mooasser, Sohrab (Inventor); Manohara, Harish (Inventor); Lee, Choonsup (Inventor); Bae, Kungsam (Inventor)

2009-01-01

Described is a device having an anti-reflection surface. The device comprises a silicon substrate with a plurality of silicon spikes formed on the substrate. A first metallic layer is formed on the silicon spikes to form the anti-reflection surface. The device further includes an aperture that extends through the substrate. A second metallic layer is formed on the substrate. The second metallic layer includes a hole that is aligned with the aperture. A spacer is attached with the silicon substrate to provide a gap between an attached sensor apparatus. Therefore, operating as a Micro-sun sensor, light entering the hole passes through the aperture to be sensed by the sensor apparatus. Additionally, light reflected by the sensor apparatus toward the first side of the silicon substrate is absorbed by the first metallic layer and silicon spikes and is thereby prevented from being reflected back toward the sensor apparatus.

Composite Reflective Absorptive IR-Blocking Filters Embedded in Metamaterial Antireflection Coated Silicon

NASA Technical Reports Server (NTRS)

Munson, C. D.; Choi, S. K.; Coughlin, K. P.; McMahon, J. J.; Miller, K. H.; Page, L. A.; Wollack, E. J.

2017-01-01

Infrared (IR)-blocking filters are crucial for controlling the radiative loading on cryogenic systems and for optimizing the sensitivity of bolometric detectors in the far-IR. We present a new IR filter approach based on a combination of patterned frequency-selective structures on silicon and a thin (2575 micron thick) absorptive composite based on powdered reststrahlen absorbing materials. For a 300 K blackbody, this combination reflects approximately 50% of the incoming light and blocks greater than.99.8% of the total power with negligible thermal gradients and excellent low-frequency transmission. This allows a reduction in the IR thermal loading to negligible levels in a single cold filter. These composite filters are fabricated on silicon substrates, which provide excellent thermal transport laterally through the filter and ensure that the entire area of the absorptive filter stays near the bath temperature. A metamaterial antireflection coating cut into these substrates reduces in-band reflections to below 1%, and the in-band absorption of the powder mix is below 1% for signal bands below 750 GHz. This type of filter can be directly incorporated into silicon refractive optical elements.

Roll-to-roll continuous patterning and transfer of graphene via dispersive adhesion

NASA Astrophysics Data System (ADS)

Choi, Taejun; Kim, Sang Jin; Park, Subeom; Hwang, Taek Yong; Jeon, Youngro; Hong, Byung Hee

2015-04-01

We present a roll-to-roll, continuous patterning and transfer of graphene sheets capable of residue-free and fast patterning. The graphene sheet is supported with dispersive adhesion. Graphene is continuously patterned by the difference in adhesion forces with a pre-defined embossed roller. The patterned graphene sheet adheres to the polyethylene terephthalate (PET)/silicone with very low strength and can be easily transferred to various substrates without the aid of any heating mechanism. The width of the patterned film was 120 mm and a production rate of 15 m min-1 for patterning was achieved. Large-area uniformity was confirmed by observing the optical images on 4 inch Si wafer and Raman mapping spectra for 50 × 50 mm2.We present a roll-to-roll, continuous patterning and transfer of graphene sheets capable of residue-free and fast patterning. The graphene sheet is supported with dispersive adhesion. Graphene is continuously patterned by the difference in adhesion forces with a pre-defined embossed roller. The patterned graphene sheet adheres to the polyethylene terephthalate (PET)/silicone with very low strength and can be easily transferred to various substrates without the aid of any heating mechanism. The width of the patterned film was 120 mm and a production rate of 15 m min-1 for patterning was achieved. Large-area uniformity was confirmed by observing the optical images on 4 inch Si wafer and Raman mapping spectra for 50 × 50 mm2. Electronic supplementary information (ESI) available. See DOI: 10.1039/c4nr06991a

Ceramic with preferential oxygen reactive layer

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor); Luthra, Krishan Lal (Inventor)

2001-01-01

An article comprises a silicon-containing substrate and an external environmental/thermal barrier coating. The external environmental/thermal barrier coating is permeable to diffusion of an environmental oxidant and the silicon-containing substrate is oxidizable by reaction with oxidant to form at least one gaseous product. The article comprises an intermediate layer/coating between the silicon-containing substrate and the environmental/thermal barrier coating that is oxidizable to a nongaseous product by reaction with the oxidant in preference to reaction of the silicon-containing substrate with the oxidant. A method of forming an article, comprises forming a silicon-based substrate that is oxidizable by reaction with oxidant to at least one gaseous product and applying an intermediate layer/coating onto the substrate, wherein the intermediate layer/coating is oxidizable to a nongaseous product by reaction with the oxidant in preference to reaction of the silicon-containing substrate with the oxidant.

Control of biaxial strain in single-layer molybdenite using local thermal expansion of the substrate

NASA Astrophysics Data System (ADS)

Plechinger, Gerd; Castellanos-Gomez, Andres; Buscema, Michele; van der Zant, Herre S. J.; Steele, Gary A.; Kuc, Agnieszka; Heine, Thomas; Schüller, Christian; Korn, Tobias

2015-03-01

Single-layer MoS2 is a direct-gap semiconductor whose electronic band structure strongly depends on the strain applied to its crystal lattice. While uniaxial strain can be easily applied in a controlled way, e.g., by bending of a flexible substrate with the atomically thin MoS2 layer on top, experimental realization of biaxial strain is more challenging. Here, we exploit the large mismatch between the thermal expansion coefficients of MoS2 and a silicone-based substrate to apply a controllable biaxial tensile strain by heating the substrate with a focused laser. The effect of this biaxial strain is directly observable in optical spectroscopy as a redshift of the MoS2 photoluminescence. We also demonstrate the potential of this method to engineer more complex strain patterns by employing highly absorptive features on the substrate to achieve non-uniform heat profiles. By comparison of the observed redshift to strain-dependent band structure calculations, we estimate the biaxial strain applied by the silicone-based substrate to be up to 0.2%, corresponding to a band gap modulation of 105 meV per percentage of biaxial tensile strain.

Protecting the properties of monolayer MoS 2 on silicon based substrates with an atomically thin buffer

DOE PAGES

Man, Michael K. L.; Deckoff-Jones, Skylar; Winchester, Andrew; ...

2016-02-12

Semiconducting 2D materials, like transition metal dichalcogenides (TMDs), have gained much attention for their potential in opto-electronic devices, valleytronic schemes, and semi-conducting to metallic phase engineering. However, like graphene and other atomically thin materials, they lose key properties when placed on a substrate like silicon, including quenching of photoluminescence, distorted crystalline structure, and rough surface morphology. The ability to protect these properties of monolayer TMDs, such as molybdenum disulfide (MoS 2), on standard Si-based substrates, will enable their use in opto-electronic devices and scientific investigations. Here we show that an atomically thin buffer layer of hexagonal-boron nitride (hBN) protects themore » range of key opto-electronic, structural, and morphological properties of monolayer MoS 2 on Si-based substrates. The hBN buffer restores sharp diffraction patterns, improves monolayer flatness by nearly two-orders of magnitude, and causes over an order of magnitude enhancement in photoluminescence, compared to bare Si and SiO 2 substrates. Lastly, our demonstration provides a way of integrating MoS 2 and other 2D monolayers onto standard Si-substrates, thus furthering their technological applications and scientific investigations.« less

Control of the ZnO nanowires nucleation site using microfluidic channels.

PubMed

Lee, Sang Hyun; Lee, Hyun Jung; Oh, Dongcheol; Lee, Seog Woo; Goto, Hiroki; Buckmaster, Ryan; Yasukawa, Tomoyuki; Matsue, Tomokazu; Hong, Soon-Ku; Ko, HyunChul; Cho, Meoung-Whan; Yao, Takafumi

2006-03-09

We report on the growth of uniquely shaped ZnO nanowires with high surface area and patterned over large areas by using a poly(dimethylsiloxane) (PDMS) microfluidic channel technique. The synthesis uses first a patterned seed template fabricated by zinc acetate solution flowing though a microfluidic channel and then growth of ZnO nanowire at the seed using thermal chemical vapor deposition on a silicon substrate. Variations the ZnO nanowire by seed pattern formed within the microfluidic channel were also observed for different substrates and concentrations of the zinc acetate solution. The photocurrent properties of the patterned ZnO nanowires with high surface area, due to their unique shape, were also investigated. These specialized shapes and patterning technique increase the possibility of realizing one-dimensional nanostructure devices such as sensors and optoelectric devices.

Rapid bio-patterning method based on the fabrication of PEG microstructures and layer-by-layer polymeric thin film

NASA Astrophysics Data System (ADS)

Shim, Hyun-Woo; Lee, Ji-Hye; Choi, Chang-Hyoung; Song, Hwan-Moon; Kim, Bo-Yeol; Kim, Dong-Pyo; Lee, Chang-Soo

2007-12-01

The patterning of biomolecules in well-defined microstructures is critical issue for the development of biosensors and biochips. However, the fabrication of microstructures with well-ordered and spatially discrete forms to provide the patterned surface for the immobilization of biomolecules is difficult because of the lack of distinct physical and chemical barriers separating patterns. This study present rapid biomolecule patterning using micromolding in capillaries (MIMIC), soft-lithographic fabrication of PEG microstructures for prevention of nonspecific binding as a biological barrier, and self assembled polymeric thin film for efficient immobilization of proteins or cells. For the proof of concept, protein (FITC-BSA), bacteria (E.coli BL21-pET23b-GFP) were used for biomolecules patterning on polyelectrolyte coated surface within PEG microstructures. The novel approach of MIMIC combined with LbL coating provides a general platform for patterning a broad range of materials because it can be easily applied to various substrates such as glass, silicon, silicon dioxide, and polymers.

Fabrication of implantable microelectrode arrays by laser cutting of silicone rubber and platinum foil.

PubMed

Schuettler, M; Stiess, S; King, B V; Suaning, G J

2005-03-01

A new method for fabrication of microelectrode arrays comprised of traditional implant materials is presented. The main construction principle is the use of spun-on medical grade silicone rubber as insulating substrate material and platinum foil as conductor (tracks, pads and electrodes). The silicone rubber and the platinum foil are patterned by laser cutting using an Nd:YAG laser and a microcontroller-driven, stepper-motor operated x-y table. The method does not require expensive clean room facilities and offers an extremely short design-to-prototype time of below 1 day. First prototypes demonstrate a minimal achievable feature size of about 30 microm.

Back contact to film silicon on metal for photovoltaic cells

DOEpatents

Branz, Howard M.; Teplin, Charles; Stradins, Pauls

2013-06-18

A crystal oriented metal back contact for solar cells is disclosed herein. In one embodiment, a photovoltaic device and methods for making the photovoltaic device are disclosed. The photovoltaic device includes a metal substrate with a crystalline orientation and a heteroepitaxial crystal silicon layer having the same crystal orientation of the metal substrate. A heteroepitaxial buffer layer having the crystal orientation of the metal substrate is positioned between the substrate and the crystal silicon layer to reduce diffusion of metal from the metal foil into the crystal silicon layer and provide chemical compatibility with the heteroepitaxial crystal silicon layer. Additionally, the buffer layer includes one or more electrically conductive pathways to electrically couple the crystal silicon layer and the metal substrate.

Surface treatment effect on Si (111) substrate for carbon deposition using DC unbalanced magnetron sputtering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aji, A. S., E-mail: aji.ravazes70@gmail.com; Sahdan, M. F.; Hendra, I. B.

In this work, we studied the effect of HF treatment in silicon (111) substrate surface for depositing thin layer carbon. We performed the deposition of carbon by using DC Unbalanced Magnetron Sputtering with carbon pallet (5% Fe) as target. From SEM characterization results it can be concluded that the carbon layer on HF treated substrate is more uniform than on substrate without treated. Carbon deposition rate is higher as confirmed by AFM results if the silicon substrate is treated by HF solution. EDAX characterization results tell that silicon (111) substrate with HF treatment have more carbon fraction than substrate withoutmore » treatment. These results confirmed that HF treatment on silicon Si (111) substrates could enhance the carbon deposition by using DC sputtering. Afterward, the carbon atomic arrangement on silicon (111) surface is studied by performing thermal annealing process to 900 °C. From Raman spectroscopy results, thin film carbon is not changing until 600 °C thermal budged. But, when temperature increase to 900 °C, thin film carbon is starting to diffuse to silicon (111) substrates.« less

Selective epitaxy using the gild process

DOEpatents

Weiner, Kurt H.

1992-01-01

The present invention comprises a method of selective epitaxy on a semiconductor substrate. The present invention provides a method of selectively forming high quality, thin GeSi layers in a silicon circuit, and a method for fabricating smaller semiconductor chips with a greater yield (more error free chips) at a lower cost. The method comprises forming an upper layer over a substrate, and depositing a reflectivity mask which is then removed over selected sections. Using a laser to melt the unmasked sections of the upper layer, the semiconductor material in the upper layer is heated and diffused into the substrate semiconductor material. By varying the amount of laser radiation, the epitaxial layer is formed to a controlled depth which may be very thin. When cooled, a single crystal epitaxial layer is formed over the patterned substrate. The present invention provides the ability to selectively grow layers of mixed semiconductors over patterned substrates such as a layer of Ge.sub.x Si.sub.1-x grown over silicon. Such a process may be used to manufacture small transistors that have a narrow base, heavy doping, and high gain. The narrowness allows a faster transistor, and the heavy doping reduces the resistance of the narrow layer. The process does not require high temperature annealing; therefore materials such as aluminum can be used. Furthermore, the process may be used to fabricate diodes that have a high reverse breakdown voltage and a low reverse leakage current.

The automated array assembly task of the low-cost silicon solar array project, phase 2

NASA Technical Reports Server (NTRS)

Coleman, M. G.; Pryor, R. A.; Sparks, T. G.; Legge, R.; Saltzman, D. L.

1980-01-01

Several specific processing steps as part of a total process sequence for manufacturing silicon solar cells were studied. Ion implantation was identified as the preferred process step for impurity doping. Unanalyzed beam ion implantation was shown to have major cost advantages over analyzed beam implantation. Further, high quality cells were fabricated using a high current unanalyzed beam. Mechanically masked plasma patterning of silicon nitride was shown to be capable of forming fine lines on silicon surfaces with spacings between mask and substrate as great as 250 micrometers. Extensive work was performed on advances in plated metallization. The need for the thick electroless palladium layer was eliminated. Further, copper was successfully utilized as a conductor layer utilizing nickel as a barrier to copper diffusion into the silicon. Plasma etching of silicon for texturing and saw damage removal was shown technically feasible but not cost effective compared to wet chemical etching techniques.

Electron-beam-induced information storage in hydrogenated amorphous silicon device

DOEpatents

Yacobi, Ben G.

1986-01-01

A method for recording and storing information in a hydrogenated amorphous silicon device, comprising: depositing hydrogenated amorphous silicon on a substrate to form a charge-collection device; and generating defects in the hydrogenated amorphous silicon device, wherein the defects act as recombination centers that reduce the lifetime of carriers, thereby reducing charge-collection efficiency; and thus in the charge-collection mode of scanning probe instruments, regions of the hydrogenated amorphous silicon device that contain the defects appear darker in comparison to regions of the device that do not contain the defects, leading to a contrast formation for pattern recognition and information storage, in the device, which darkened areas can be restored to their original charge-collection efficiency by heating the hydrogenated amorphous silicon to a temperature of about 100.degree. C. to 250.degree. C. for a sufficient period of time to provide for such restoration.

The growth of ultralong and highly blue luminescent gallium oxide nanowires and nanobelts, and direct horizontal nanowire growth on substrates.

PubMed

Kuo, Chi-Liang; Huang, Michael H

2008-04-16

We report the growth of ultralong β-Ga(2)O(3) nanowires and nanobelts on silicon substrates using a vapor phase transport method. The growth was carried out in a tube furnace, with gallium metal serving as the gallium source. The nanowires and nanobelts can grow to lengths of hundreds of nanometers and even millimeters. Their full lengths have been captured by both scanning electron microscope (SEM) and optical images. X-ray diffraction (XRD) patterns and transmission electron microscope (TEM) images have been used to study the crystal structures of these nanowires and nanobelts. Strong blue emission from these ultralong nanostructures can be readily observed by irradiation with an ultraviolet (UV) lamp. Diffuse reflectance spectroscopy measurements gave a band gap of 4.56 eV for these nanostructures. The blue emission shows a band maximum at 470 nm. Interestingly, by annealing the silicon substrates in an oxygen atmosphere to form a thick SiO(2) film, and growing Ga(2)O(3) nanowires over the sputtered gold patterned regions, horizontal Ga(2)O(3) nanowire growth in the non-gold-coated regions can be observed. These horizontal nanowires can grow to as long as over 10 µm in length. Their composition has been confirmed by TEM characterization. This represents one of the first examples of direct horizontal growth of oxide nanowires on substrates.

A novel self-aligned oxygen (SALOX) implanted SOI MOSFET device structure

NASA Astrophysics Data System (ADS)

Tzeng, J. C.; Baerg, W.; Ting, C.; Siu, B.

The morphology of the novel self-aligned oxygen implanted SOI (SALOX SOI) [1] MOSFET was studied. The channel silicon of SALOX SOI was confirmed to be undamaged single crystal silicon and was connected with the substrate. Buried oxide formed by oxygen implantation in this SALOX SOI structure was shown by a cross section transmission electron micrograph (X-TEM) to be amorphous. The source/drain silicon on top of the buried oxide was single crystal, as shown by the transmission electron diffraction (TED) pattern. The source/drain regions were elevated due to the buried oxide volume expansion. A sharp silicon—silicon dioxide interface between the source/drain silicon and buried oxide was observed by Auger electron spectroscopy (AES). Well behaved n-MOS transistor current voltage characteristics were obtained and showed no I-V kink.

Direct-patterned optical waveguides on amorphous silicon films

DOEpatents

Vernon, Steve; Bond, Tiziana C.; Bond, Steven W.; Pocha, Michael D.; Hau-Riege, Stefan

2005-08-02

An optical waveguide structure is formed by embedding a core material within a medium of lower refractive index, i.e. the cladding. The optical index of refraction of amorphous silicon (a-Si) and polycrystalline silicon (p-Si), in the wavelength range between about 1.2 and about 1.6 micrometers, differ by up to about 20%, with the amorphous phase having the larger index. Spatially selective laser crystallization of amorphous silicon provides a mechanism for controlling the spatial variation of the refractive index and for surrounding the amorphous regions with crystalline material. In cases where an amorphous silicon film is interposed between layers of low refractive index, for example, a structure comprised of a SiO.sub.2 substrate, a Si film and an SiO.sub.2 film, the formation of guided wave structures is particularly simple.

Rear-Sided Passivation by SiNx:H Dielectric Layer for Improved Si/PEDOT:PSS Hybrid Heterojunction Solar Cells.

PubMed

Sun, Yiling; Gao, Pingqi; He, Jian; Zhou, Suqiong; Ying, Zhiqin; Yang, Xi; Xiang, Yong; Ye, Jichun

2016-12-01

Silicon/organic hybrid solar cells have recently attracted great attention because they combine the advantages of silicon (Si) and the organic cells. In this study, we added a patterned passivation layer of silicon nitride (SiNx:H) onto the rear surface of the Si substrate in a Si/poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) ( PSS) hybrid solar cell, enabling an improvement of 0.6 % in the power conversion efficiency (PCE). The addition of the SiNx:H layer boosted the open circuit voltage (V oc) from 0.523 to 0.557 V, suggesting the well-passivation property of the patterned SiNx:H thin layer that was created by plasma-enhanced chemical vapor deposition and lithography processes. The passivation properties that stemmed from front PSS, rear-SiNx:H, front PSS/rear-SiNx:H, etc. are thoroughly investigated, in consideration of the process-related variations.

Preferred orientations of laterally grown silicon films over amorphous substrates using the vapor–liquid–solid technique

DOE Office of Scientific and Technical Information (OSTI.GOV)

LeBoeuf, J. L., E-mail: jerome.leboeuf@mail.mcgill.ca; Brodusch, N.; Gauvin, R.

2014-12-28

A novel method has been optimized so that adhesion layers are no longer needed to reliably deposit patterned gold structures on amorphous substrates. Using this technique allows for the fabrication of amorphous oxide templates known as micro-crucibles, which confine a vapor–liquid–solid (VLS) catalyst of nominally pure gold to a specific geometry. Within these confined templates of amorphous materials, faceted silicon crystals have been grown laterally. The novel deposition technique, which enables the nominally pure gold catalyst, involves the undercutting of an initial chromium adhesion layer. Using electron backscatter diffraction it was found that silicon nucleated in these micro-crucibles were 30%more » single crystals, 45% potentially twinned crystals and 25% polycrystals for the experimental conditions used. Single, potentially twinned, and polycrystals all had an aversion to growth with the (1 0 0) surface parallel to the amorphous substrate. Closer analysis of grain boundaries of potentially twinned and polycrystalline samples revealed that the overwhelming majority of them were of the 60° Σ3 coherent twin boundary type. The large amount of coherent twin boundaries present in the grown, two-dimensional silicon crystals suggest that lateral VLS growth occurs very close to thermodynamic equilibrium. It is suggested that free energy fluctuations during growth or cooling, and impurities were the causes for this twinning.« less

a Model for the Dynamical Behavior of Patterned Thin Film Structures on Silicon

NASA Astrophysics Data System (ADS)

Every, A. G.; Maznev, A. A.

2010-02-01

Metrology of metal-dielectric thin film structures fabricated on silicon wafers has emerged as a major application area of laser ultrasonics. The measurements are oftentimes performed on structures comprised of periodic line arrays, which as regards their dynamical behavior, form a distinct class of phononic crystals. Recently reported measurements of laser-generated surface acoustic modes in Cu-SiO2 line arrays on silicon have uncovered a number of interesting phenomena. The goal of this paper is to provide a simple theoretical model capturing the salient features of the experiment and leading to a better understanding of the physical nature of the observed phenomena. The structure is simulated by a uniform layer on a substrate with periodic mass loading applied to its upper surface, and is treated by the plane wave expansion method. We establish that the large bandgap observed inside the Brillouin zone originates from the hybridization of the Rayleigh and Sezawa modes of the film-substrate structure. The displacement pattern in the Rayleigh and Sezawa waves explains their strong interaction, leading to a larger bandgap than the ones formed at the zone boundary. Unexpectedly low radiation loss of the hybridized Rayleigh-Sezawa mode in the "supersonic" domain, is also reproduced by the model.

Deposition method for producing silicon carbide high-temperature semiconductors

DOEpatents

Hsu, George C.; Rohatgi, Naresh K.

1987-01-01

An improved deposition method for producing silicon carbide high-temperature semiconductor material comprising placing a semiconductor substrate composed of silicon carbide in a fluidized bed silicon carbide deposition reactor, fluidizing the bed particles by hydrogen gas in a mildly bubbling mode through a gas distributor and heating the substrate at temperatures around 1200.degree.-1500.degree. C. thereby depositing a layer of silicon carbide on the semiconductor substrate.

Directed assembly of nanomaterials for miniaturized sensors by dip-pen nanolithography using precursor inks

NASA Astrophysics Data System (ADS)

Su, Ming

The advent of nanomaterials with enhanced properties and the means to pattern them in a controlled fashion have paved the way to construct miniaturized sensors for improved detection. However it remains a challenge for the traditional methods to create such sensors and sensor arrays. Dip pen nanolithography (DPN) can form nanostructures on a substrate by controlling the transfer of molecule inks. However, previous DPN can not pattern solid materials on insulating surfaces, which are necessary to form functional electronic devices. In the dissertation, the concept of reactive precursor inks for DPN is developed for the generation of solid functional nanostructures of the following materials: organic molecule, sol-gel material, and conducting polymer. First, the covalent bonding is unnecessary for DPN as shown in the colored ink DPN; therefore the numbers of molecules that can be patterned is extended beyond thiol or thiolated molecules. Subsequently, a reactive precursor strategy (sol) is developed to pattern inorganic or organic/inorganic composite nanostructures on silicon based substrates. The method works by hydrolysis of metal precursors in the water meniscus and allows the preparation of solid structures with controlled geometry beyond the individual molecule level. Then the SnO 2 nanostructures patterned between the gaps of electrodes are tested as gas sensors. Proof-of-concept experiments are demonstrated on miniaturized sensors that show fast response and recovery to certain gases. Furthermore, an eight-unit sensor array is fabricated on a chip using SnO2 sols that are doped with different metals. The multiplexed device can recognize different gases by comparing the response patterns with the reference patterns of known gases generated on the same array. At last, the idea of precursor ink for DPN is extended to construct conducting polymer based devices. By using an acid promoted polymerization approach, conducting polymers are patterned on silicon dioxide substrates. The patterned organic solids response to light and behave as miniaturized photo-detectors. The microstructures are studied using microscopic and spectroscopic techniques.

Toward three-dimensional microelectronic systems: directed self-assembly of silicon microcubes via DNA surface functionalization.

PubMed

Lämmerhardt, Nico; Merzsch, Stephan; Ledig, Johannes; Bora, Achyut; Waag, Andreas; Tornow, Marc; Mischnick, Petra

2013-07-02

The huge and intelligent processing power of three-dimensional (3D) biological "processors" like the human brain with clock speeds of only 0.1 kHz is an extremely fascinating property, which is based on a massively parallel interconnect strategy. Artificial silicon microprocessors are 7 orders of magnitude faster. Nevertheless, they do not show any indication of intelligent processing power, mostly due to their very limited interconnectivity. Massively parallel interconnectivity can only be realized in three dimensions. Three-dimensional artificial processors would therefore be at the root of fabricating artificially intelligent systems. A first step in this direction would be the self-assembly of silicon based building blocks into 3D structures. We report on the self-assembly of such building blocks by molecular recognition, and on the electrical characterization of the formed assemblies. First, planar silicon substrates were functionalized with self-assembling monolayers of 3-aminopropyltrimethoxysilane for coupling of oligonucleotides (single stranded DNA) with glutaric aldehyde. The oligonucleotide immobilization was confirmed and quantified by hybridization with fluorescence-labeled complementary oligonucleotides. After the individual processing steps, the samples were analyzed by contact angle measurements, ellipsometry, atomic force microscopy, and fluorescence microscopy. Patterned DNA-functionalized layers were fabricated by microcontact printing (μCP) and photolithography. Silicon microcubes of 3 μm edge length as model objects for first 3D self-assembly experiments were fabricated out of silicon-on-insulator (SOI) wafers by a combination of reactive ion etching (RIE) and selective wet etching. The microcubes were then surface-functionalized using the same protocol as on planar substrates, and their self-assembly was demonstrated both on patterned silicon surfaces (88% correctly placed cubes), and to cube aggregates by complementary DNA functionalization and hybridization. The yield of formed aggregates was found to be about 44%, with a relative fraction of dimers of some 30%. Finally, the electrical properties of the formed dimers were characterized using probe tips inside a scanning electron microscope.

An investigation on physical properties of SiOx nanowires deposited by chemical vapor deposition method: The effect of substrate to boat distance

NASA Astrophysics Data System (ADS)

Heidaryan, Narges; Eshghi, Hosein

2017-09-01

Large-scale silicon oxide nanowires (SiOx NWs) with a diameter about 250 nm on silicon wafers were synthesized by thermal evaporation of silicon monoxide (SiO) powder. In order to investigate the role of distance on the physical properties of SiOx NWs, Si substrates were positioned at 5 cm and 10 cm apart from the boat position set at 1150∘C. The local temperatues of the samples were 1100∘C and 1050∘C, respectively. The SEM images and EDS spectra showed interweaved networks of SiOx NWs with x = 0.62 and 0.65 in these layers. The XRD patterns showed S1 has a polycrystalline structure (cristobalite), while S2 has amorphous nature. The PL spectra showed an intense blue peak at 468 nm in S1, and a violet peak at 427 nm in S2 that could be related to the differences in the crystallite structures and oxygen vacancies in these samples.

Surface wettability of silicon substrates enhanced by laser ablation

NASA Astrophysics Data System (ADS)

Tseng, Shih-Feng; Hsiao, Wen-Tse; Chen, Ming-Fei; Huang, Kuo-Cheng; Hsiao, Sheng-Yi; Lin, Yung-Sheng; Chou, Chang-Pin

2010-11-01

Laser-ablation techniques have been widely applied for removing material from a solid surface using a laser-beam irradiating apparatus. This paper presents a surface-texturing technique to create rough patterns on a silicon substrate using a pulsed Nd:YAG laser system. The different degrees of microstructure and surface roughness were adjusted by the laser fluence and laser pulse duration. A scanning electron microscope (SEM) and a 3D confocal laser-scanning microscope are used to measure the surface micrograph and roughness of the patterns, respectively. The contact angle variations between droplets on the textured surface were measured using an FTA 188 video contact angle analyzer. The results indicate that increasing the values of laser fluence and laser pulse duration pushes more molten slag piled around these patterns to create micro-sized craters and leads to an increase in the crater height and surface roughness. A typical example of a droplet on a laser-textured surface shows that the droplet spreads very quickly and almost disappears within 0.5167 s, compared to a contact angle of 47.9° on an untextured surface. This processing technique can also be applied to fabricating Si solar panels to increase the absorption efficiency of light.

Biolithography: Slime mould patterning of polyaniline

NASA Astrophysics Data System (ADS)

Berzina, Tatiana; Dimonte, Alice; Adamatzky, Andrew; Erokhin, Victor; Iannotta, Salvatore

2018-03-01

Slime mould Physarum polycephalum develops intricate patterns of protoplasmic networks when foraging on a non-nutrient substrates. The networks are optimised for spanning larger spaces with minimum body mass and for quick transfer of nutrients and metabolites inside the slime mould's body. We hybridise the slime mould's networks with conductive polymer polyaniline and thus produce micro-patterns of conductive networks. This unconventional lithographic method opens new perspectives in development of living technology devices, biocompatible non-silicon hardware for applications in integrated circuits, bioelectronics, and biosensing.

Lateral solid phase epitaxy of silicon and application to the fabrication of metal oxide semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Greene, Brian Joseph

Thin film silicon on insulator fabrication is an increasingly important technology requirement for improving performance in future generation devices and circuits. One process for SOI fabrication that has recently been generating renewed interest is Lateral Solid Phase Epitaxy (LSPE) of silicon over oxide. This process involves annealing amorphous silicon that has been deposited on oxide patterned Si wafers. The (001) Si substrate forms the crystalline seed for epitaxial growth, permitting the generation of Si films that are both single crystal, and oriented to the substrate. This method is particularly attractive to fabrication that requires low temperature processing, because the Si films are deposited in the amorphous phase at temperatures near 525°C, and crystallized at temperatures near 570°C. It is also attractive for applications requiring three dimensional stacking of active silicon device layers, due to the relatively low temperatures involved. For sub-50 nm gate length MOSFET fabrication, an SOI thickness on the order of 10 nm will be required. One limitation of the LSPE process has been the need for thick films (0.5--2 mum) and/or heavy P doping (10 19--1020 cm-3) to increase the maximum achievable lateral growth distance, and therefore minimize the area on the substrate occupied by seed holes. This dissertation discusses the characterization and optimization of process conditions for large area LSPE silicon film growth, as well as efforts to adapt the traditional LSPE process to achieve ultra-thin SOI layers (Tsilicon ≤ 25 nm) while avoiding the use of heavy active doping layers. MOSFETs fabricated in these films that exhibit electron mobility comparable to the Universal Si MOS Mobility are described.

Application Of Optical Processing For Growth Of Silicon Dioxide

DOEpatents

Sopori, Bhushan L.

1997-06-17

A process for producing a silicon dioxide film on a surface of a silicon substrate. The process comprises illuminating a silicon substrate in a substantially pure oxygen atmosphere with a broad spectrum of visible and infrared light at an optical power density of from about 3 watts/cm.sup.2 to about 6 watts/cm.sup.2 for a time period sufficient to produce a silicon dioxide film on the surface of the silicon substrate. An optimum optical power density is about 4 watts/cm.sup.2 for growth of a 100.ANG.-300.ANG. film at a resultant temperature of about 400.degree. C. Deep level transient spectroscopy analysis detects no measurable impurities introduced into the silicon substrate during silicon oxide production and shows the interface state density at the SiO.sub.2 /Si interface to be very low.

Fabricating amorphous silicon solar cells by varying the temperature _of the substrate during deposition of the amorphous silicon layer

DOEpatents

Carlson, David E.

1982-01-01

An improved process for fabricating amorphous silicon solar cells in which the temperature of the substrate is varied during the deposition of the amorphous silicon layer is described. Solar cells manufactured in accordance with this process are shown to have increased efficiencies and fill factors when compared to solar cells manufactured with a constant substrate temperature during deposition of the amorphous silicon layer.

Self-organized broadband light trapping in thin film amorphous silicon solar cells.

PubMed

Martella, C; Chiappe, D; Delli Veneri, P; Mercaldo, L V; Usatii, I; Buatier de Mongeot, F

2013-06-07

Nanostructured glass substrates endowed with high aspect ratio one-dimensional corrugations are prepared by defocused ion beam erosion through a self-organized gold (Au) stencil mask. The shielding action of the stencil mask is amplified by co-deposition of gold atoms during ion bombardment. The resulting glass nanostructures enable broadband anti-reflection functionality and at the same time ensure a high efficiency for diffuse light scattering (Haze). It is demonstrated that the patterned glass substrates exhibit a better photon harvesting than the flat glass substrate in p-i-n type thin film a-Si:H solar cells.

High Precision Metal Thin Film Liftoff Technique

NASA Technical Reports Server (NTRS)

Brown, Ari D. (Inventor); Patel, Amil A. (Inventor)

2015-01-01

A metal film liftoff process includes applying a polymer layer onto a silicon substrate, applying a germanium layer over the polymer layer to create a bilayer lift off mask, applying a patterned photoresist layer over the germanium layer, removing an exposed portion of the germanium layer, removing the photoresist layer and a portion of the polymer layer to expose a portion of the substrate and create an overhanging structure of the germanium layer, depositing a metal film over the exposed portion of the substrate and the germanium layer, and removing the polymer and germanium layers along with the overlaying metal film.

Printing line/space patterns on nonplanar substrates using a digital micromirror device-based point-array scanning technique

NASA Astrophysics Data System (ADS)

Kuo, Hung-Fei; Kao, Guan-Hsuan; Zhu, Liang-Xiu; Hung, Kuo-Shu; Lin, Yu-Hsin

2018-02-01

This study used a digital micromirror device (DMD) to produce point-array patterns and employed a self-developed optical system to define line-and-space patterns on nonplanar substrates. First, field tracing was employed to analyze the aerial images of the lithographic system, which comprised an optical system and the DMD. Multiobjective particle swarm optimization was then applied to determine the spot overlapping rate used. The objective functions were set to minimize linewidth and maximize image log slope, through which the dose of the exposure agent could be effectively controlled and the quality of the nonplanar lithography could be enhanced. Laser beams with 405-nm wavelength were employed as the light source. Silicon substrates coated with photoresist were placed on a nonplanar translation stage. The DMD was used to produce lithographic patterns, during which the parameters were analyzed and optimized. The optimal delay time-sequence combinations were used to scan images of the patterns. Finally, an exposure linewidth of less than 10 μm was successfully achieved using the nonplanar lithographic process.

Scalable maskless patterning of nanostructures using high-speed scanning probe arrays

NASA Astrophysics Data System (ADS)

Chen, Chen; Akella, Meghana; Du, Zhidong; Pan, Liang

2017-08-01

Nanoscale patterning is the key process to manufacture important products such as semiconductor microprocessors and data storage devices. Many studies have shown that it has the potential to revolutionize the functions of a broad range of products for a wide variety of applications in energy, healthcare, civil, defense and security. However, tools for mass production of these devices usually cost tens of million dollars each and are only affordable to the established semiconductor industry. A new method, nominally known as "pattern-on-the- y", that involves scanning an array of optical or electrical probes at high speed to form nanostructures and offers a new low-cost approach for nanoscale additive patterning. In this paper, we report some progress on using this method to pattern self-assembled monolayers (SAMs) on silicon substrate. We also functionalize the substrate with gold nanoparticle based on the SAM to show the feasibility of preparing amphiphilic and multi-functional surfaces.

Characterization of Silicon Moth-Eye Antireflection Coatings for Astronomical Applications in the Infrared

NASA Astrophysics Data System (ADS)

Jeram, Sarik; Ge, Jian; Jiang, Peng; Phillips, Blayne

2016-01-01

Silicon moth-eye antireflective structures have emerged to be an excellent approachfor reducing the amount of light that is lost upon incidence on a given surface of optics made of silicon. This property has been exploited for a wide variety of products ranging from eyeglasses and flat-panel displays to solar panels. These materials typically come in the form of coatings that are applied to an optical substrate such as glass. Moth-eye coatings, made of a periodic array of subwavelength pillars on silicon substrates or other substrates, can produce the desired antireflection (AR) performance for a broad wavelength range and over a wide range of incident angles. In the field of astronomy, every photon striking a detector is significant - and thus, losses from reflectivity at the various optical interfaces before a detector can have significant implications to the science at hand. Moth-eye AR coatings on these optical interfaces may minimize their reflection losses while maximizing light throughput for a multitude of different astronomical instruments. In addition, moth-eye AR coatings, which are patterned directly on silicon surfaces, can significantly enhance the coating durability. At the University of Florida, we tested two moth-eye filters designed for use in the near-infrared regime at 1-8 microns by examining their optical properties, such as transmission, the scattered light, and wavefront quality, and testing the coatings at cryogenic temperatures to characterize their viability for use in both ground- and space-based infrared instruments. This presentation will report our lab evaluation results.

Hexagonal Ag nanoarrays induced enhancement of blue light emission from amorphous oxidized silicon nitride via localized surface plasmon coupling.

PubMed

Ma, Zhongyuan; Ni, Xiaodong; Zhang, Wenping; Jiang, Xiaofan; Yang, Huafeng; Yu, Jie; Wang, Wen; Xu, Ling; Xu, Jun; Chen, Kunji; Feng, Duan

2014-11-17

A significant enhancement of blue light emission from amorphous oxidized silicon nitride (a-SiNx:O) films is achieved by introduction of ordered and size-controllable arrays of Ag nanoparticles between the silicon substrate and a-SiNx:O films. Using hexagonal arrays of Ag nanoparticles fabricated by nanosphere lithography, the localized surface plasmons (LSPs) resonance can effectively increase the internal quantum efficiency from 3.9% to 13.3%. Theoretical calculation confirms that the electromagnetic field-intensity enhancement is through the dipole surface plasma coupling with the excitons of a-SiNx:O films, which demonstrates a-SiNx:O films with enhanced blue emission are promising for silicon-based light-emitting applications by patterned Ag arrays.

Monolayer Contact Doping of Silicon Surfaces and Nanowires Using Organophosphorus Compounds

PubMed Central

Hazut, Ori; Agarwala, Arunava; Subramani, Thangavel; Waichman, Sharon; Yerushalmi, Roie

2013-01-01

Monolayer Contact Doping (MLCD) is a simple method for doping of surfaces and nanostructures1. MLCD results in the formation of highly controlled, ultra shallow and sharp doping profiles at the nanometer scale. In MLCD process the dopant source is a monolayer containing dopant atoms. In this article a detailed procedure for surface doping of silicon substrate as well as silicon nanowires is demonstrated. Phosphorus dopant source was formed using tetraethyl methylenediphosphonate monolayer on a silicon substrate. This monolayer containing substrate was brought to contact with a pristine intrinsic silicon target substrate and annealed while in contact. Sheet resistance of the target substrate was measured using 4 point probe. Intrinsic silicon nanowires were synthesized by chemical vapor deposition (CVD) process using a vapor-liquid-solid (VLS) mechanism; gold nanoparticles were used as catalyst for nanowire growth. The nanowires were suspended in ethanol by mild sonication. This suspension was used to dropcast the nanowires on silicon substrate with a silicon nitride dielectric top layer. These nanowires were doped with phosphorus in similar manner as used for the intrinsic silicon wafer. Standard photolithography process was used to fabricate metal electrodes for the formation of nanowire based field effect transistor (NW-FET). The electrical properties of a representative nanowire device were measured by a semiconductor device analyzer and a probe station. PMID:24326774

Three-dimensional patterning in polymer optical waveguides using focused ion beam milling

NASA Astrophysics Data System (ADS)

Kruse, Kevin; Burrell, Derek; Middlebrook, Christopher

2016-07-01

Waveguide (WG) photonic-bridge taper modules are designed for symmetric planar coupling between silicon WGs and single-mode fibers (SMFs) to minimize photonic chip and packaging footprint requirements with improving broadband functionality. Micromachined fabrication and evaluation of polymer WG tapers utilizing high-resolution focused ion beam (FIB) milling is performed and presented. Polymer etch rates utilizing the FIB and optimal methods for milling polymer tapers are identified for three-dimensional patterning. Polymer WG tapers with low sidewall roughness are manufactured utilizing FIB milling and optically tested for fabrication loss. FIB platforms utilize a focused beam of ions (Ga+) to etch submicron patterns into substrates. Fabricating low-loss polymer WG taper prototypes with the FIB before moving on to mass-production techniques provides theoretical understanding of the polymer taper and its feasibility for connectorization devices between silicon WGs and SMFs.

Electroless epitaxial etching for semiconductor applications

DOEpatents

McCarthy, Anthony M.

2002-01-01

A method for fabricating thin-film single-crystal silicon on insulator substrates using electroless etching for achieving efficient etch stopping on epitaxial silicon substrates. Microelectric circuits and devices are prepared on epitaxial silicon wafers in a standard fabrication facility. The wafers are bonded to a holding substrate. The silicon bulk is removed using electroless etching leaving the circuit contained within the epitaxial layer remaining on the holding substrate. A photolithographic operation is then performed to define streets and wire bond pad areas for electrical access to the circuit.

High Efficiency, Low Cost Solar Cells Manufactured Using 'Silicon Ink' on Thin Crystalline Silicon Wafers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Antoniadis, H.

Reported are the development and demonstration of a 17% efficient 25mm x 25mm crystalline Silicon solar cell and a 16% efficient 125mm x 125mm crystalline Silicon solar cell, both produced by Ink-jet printing Silicon Ink on a thin crystalline Silicon wafer. To achieve these objectives, processing approaches were developed to print the Silicon Ink in a predetermined pattern to form a high efficiency selective emitter, remove the solvents in the Silicon Ink and fuse the deposited particle Silicon films. Additionally, standard solar cell manufacturing equipment with slightly modified processes were used to complete the fabrication of the Silicon Ink highmore » efficiency solar cells. Also reported are the development and demonstration of a 18.5% efficient 125mm x 125mm monocrystalline Silicon cell, and a 17% efficient 125mm x 125mm multicrystalline Silicon cell, by utilizing high throughput Ink-jet and screen printing technologies. To achieve these objectives, Innovalight developed new high throughput processing tools to print and fuse both p and n type particle Silicon Inks in a predetermined pat-tern applied either on the front or the back of the cell. Additionally, a customized Ink-jet and screen printing systems, coupled with customized substrate handling solution, customized printing algorithms, and a customized ink drying process, in combination with a purchased turn-key line, were used to complete the high efficiency solar cells. This development work delivered a process capable of high volume producing 18.5% efficient crystalline Silicon solar cells and enabled the Innovalight to commercialize its technology by the summer of 2010.« less

Thermally-isolated silicon-based integrated circuits and related methods

DOEpatents

Wojciechowski, Kenneth; Olsson, Roy H.; Clews, Peggy J.; Bauer, Todd

2017-05-09

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Method for forming metallic silicide films on silicon substrates by ion beam deposition

DOEpatents

Zuhr, Raymond A.; Holland, Orin W.

1990-01-01

Metallic silicide films are formed on silicon substrates by contacting the substrates with a low-energy ion beam of metal ions while moderately heating the substrate. The heating of the substrate provides for the diffusion of silicon atoms through the film as it is being formed to the surface of the film for interaction with the metal ions as they contact the diffused silicon. The metallic silicide films provided by the present invention are contaminant free, of uniform stoichiometry, large grain size, and exhibit low resistivity values which are of particular usefulness for integrated circuit production.

Method for imaging informational biological molecules on a semiconductor substrate

NASA Technical Reports Server (NTRS)

Coles, L. Stephen (Inventor)

1994-01-01

Imaging biological molecules such as DNA at rates several times faster than conventional imaging techniques is carried out using a patterned silicon wafer having nano-machined grooves which hold individual molecular strands and periodically spaced unique bar codes permitting repeatably locating all images. The strands are coaxed into the grooves preferably using gravity and pulsed electric fields which induce electric charge attraction to the molecular strands in the bottom surfaces of the grooves. Differential imaging removes substrate artifacts.

Back-side hydrogenation technique for defect passivation in silicon solar cells

DOEpatents

Sopori, Bhushan L.

1994-01-01

A two-step back-side hydrogenation process includes the steps of first bombarding the back side of the silicon substrate with hydrogen ions with intensities and for a time sufficient to implant enough hydrogen atoms into the silicon substrate to potentially passivate substantially all of the defects and impurities in the silicon substrate, and then illuminating the silicon substrate with electromagnetic radiation to activate the implanted hydrogen, so that it can passivate the defects and impurities in the substrate. The illumination step also annihilates the hydrogen-induced defects. The illumination step is carried out according to a two-stage illumination schedule, the first or low-power stage of which subjects the substrate to electromagnetic radiation that has sufficient intensity to activate the implanted hydrogen, yet not drive the hydrogen from the substrate. The second or high-power illumination stage subjects the substrate to higher intensity electromagnetic radiation, which is sufficient to annihilate the hydrogen-induced defects and sinter/alloy the metal contacts.

Back-side hydrogenation technique for defect passivation in silicon solar cells

DOEpatents

Sopori, B.L.

1994-04-19

A two-step back-side hydrogenation process includes the steps of first bombarding the back side of the silicon substrate with hydrogen ions with intensities and for a time sufficient to implant enough hydrogen atoms into the silicon substrate to potentially passivate substantially all of the defects and impurities in the silicon substrate, and then illuminating the silicon substrate with electromagnetic radiation to activate the implanted hydrogen, so that it can passivate the defects and impurities in the substrate. The illumination step also annihilates the hydrogen-induced defects. The illumination step is carried out according to a two-stage illumination schedule, the first or low-power stage of which subjects the substrate to electromagnetic radiation that has sufficient intensity to activate the implanted hydrogen, yet not drive the hydrogen from the substrate. The second or high-power illumination stage subjects the substrate to higher intensity electromagnetic radiation, which is sufficient to annihilate the hydrogen-induced defects and sinter/alloy the metal contacts. 3 figures.

Silicone substrate with in situ strain relief for stretchable thin-film transistors

NASA Astrophysics Data System (ADS)

Graz, Ingrid M.; Cotton, Darryl P. J.; Robinson, Adam; Lacour, Stéphanie P.

2011-03-01

We have manufactured stretchable thin-film transistors and interconnects directly onto an engineered silicone matrix with localized and graded mechanical compliance. The fabrication only involves planar and standard processing. Brittle active device materials are patterned on non deformable elastomer regions (strain <1% at all times) while interconnects run smoothly from "stiff" to "soft" elastomer. Pentacene thin-film transistors sustain applied strain up to 13% without electrical degradation and mechanical fracture. This integrated approach opens promising options for the manufacture of physically adaptable and transformable circuitry.

High quality silicon-based substrates for microwave and millimeter wave passive circuits

NASA Astrophysics Data System (ADS)

Belaroussi, Y.; Rack, M.; Saadi, A. A.; Scheen, G.; Belaroussi, M. T.; Trabelsi, M.; Raskin, J.-P.

2017-09-01

Porous silicon substrate is very promising for next generation wireless communication requiring the avoidance of high-frequency losses originating from the bulk silicon. In this work, new variants of porous silicon (PSi) substrates have been introduced. Through an experimental RF performance, the proposed PSi substrates have been compared with different silicon-based substrates, namely, standard silicon (Std), trap-rich (TR) and high resistivity (HR). All of the mentioned substrates have been fabricated where identical samples of CPW lines have been integrated on. The new PSi substrates have shown successful reduction in the substrate's effective relative permittivity to values as low as 3.7 and great increase in the substrate's effective resistivity to values higher than 7 kΩ cm. As a concept proof, a mm-wave bandpass filter (MBPF) centred at 27 GHz has been integrated on the investigated substrates. Compared with the conventional MBPF implemented on standard silicon-based substrates, the measured S-parameters of the PSi-based MBPF have shown high filtering performance, such as a reduction in insertion loss and an enhancement of the filter selectivity, with the joy of having the same filter performance by varying the temperature. Therefore, the efficiency of the proposed PSi substrates has been well highlighted. From 1994 to 1995, she was assistant of physics at (USTHB), Algiers . From 1998 to 2011, she was a Researcher at characterization laboratory in ionized media and laser division at the Advanced Technologies Development Center. She has integrated the Analog Radio Frequency Integrated Circuits team as Researcher since 2011 until now in Microelectronic and Nanotechnology Division at Advanced Technologies Development Center (CDTA), Algiers. She has been working towards her Ph.D. degree jointly at CDTA and Ecole Nationale Polytechnique, Algiers, since 2012. Her research interest includes fabrication and characterization of microwave passive devices on porous silicon as new substrate, such as characterization of FinFET components.

Application of optical processing for growth of silicon dioxide

DOEpatents

Sopori, B.L.

1997-06-17

A process for producing a silicon dioxide film on a surface of a silicon substrate is disclosed. The process comprises illuminating a silicon substrate in a substantially pure oxygen atmosphere with a broad spectrum of visible and infrared light at an optical power density of from about 3 watts/cm{sup 2} to about 6 watts/cm{sup 2} for a time period sufficient to produce a silicon dioxide film on the surface of the silicon substrate. An optimum optical power density is about 4 watts/cm{sup 2} for growth of a 100{angstrom}-300{angstrom} film at a resultant temperature of about 400 C. Deep level transient spectroscopy analysis detects no measurable impurities introduced into the silicon substrate during silicon oxide production and shows the interface state density at the SiO{sub 2}/Si interface to be very low. 1 fig.

Site-Controlled Growth of Monolithic InGaAs/InP Quantum Well Nanopillar Lasers on Silicon.

PubMed

Schuster, Fabian; Kapraun, Jonas; Malheiros-Silveira, Gilliard N; Deshpande, Saniya; Chang-Hasnain, Connie J

2017-04-12

In this Letter, we report the site-controlled growth of InP nanolasers on a silicon substrate with patterned SiO 2 nanomasks by low-temperature metal-organic chemical vapor deposition, compatible with silicon complementary metal-oxide-semiconductor (CMOS) post-processing. A two-step growth procedure is presented to achieve smooth wurtzite faceting of vertical nanopillars. By incorporating InGaAs multiquantum wells, the nanopillar emission can be tuned over a wide spectral range. Enhanced quality factors of the intrinsic InP nanopillar cavities promote lasing at 0.87 and 1.21 μm, located within two important optical telecommunication bands. This is the first demonstration of a site-controlled III-V nanolaser monolithically integrated on silicon with a silicon-transparent emission wavelength, paving the way for energy-efficient on-chip optical links at typical telecommunication wavelengths.

Method for rapid, controllable growth and thickness, of epitaxial silicon films

DOEpatents

Wang, Qi [Littleton, CO; Stradins, Paul [Golden, CO; Teplin, Charles [Boulder, CO; Branz, Howard M [Boulder, CO

2009-10-13

A method of producing epitaxial silicon films on a c-Si wafer substrate using hot wire chemical vapor deposition by controlling the rate of silicon deposition in a temperature range that spans the transition from a monohydride to a hydrogen free silicon surface in a vacuum, to obtain phase-pure epitaxial silicon film of increased thickness is disclosed. The method includes placing a c-Si substrate in a HWCVD reactor chamber. The method also includes supplying a gas containing silicon at a sufficient rate into the reaction chamber to interact with the substrate to deposit a layer containing silicon thereon at a predefined growth rate to obtain phase-pure epitaxial silicon film of increased thickness.

Method of Forming Three-Dimensional Semiconductors Structures

NASA Technical Reports Server (NTRS)

Fathauer, Robert W. (Inventor)

2002-01-01

Silicon and metal are coevaporated onto a silicon substrate in a molecular beam epitaxy system with a larger than stoichiometric amount of silicon so as to epitaxially grow columns of metal silicide embedded in a matrix of single crystal, epitaxially grown silicon. Higher substrate temperatures and lower deposition rates yield larger columns that are farther apart while more silicon produces smaller columns. Column shapes and locations are selected by seeding the substrate with metal silicide starting regions. A variety of 3-dimensional, exemplary electronic devices are disclosed.

Method of bonding silver to glass and mirrors produced according to this method

DOEpatents

Pitts, J.R.; Thomas, T.M.; Czanderna, A.W.

1984-07-31

A method for adhering silver to a glass substrate for producing mirrors includes attaining a silicon enriched substrate surface by reducing the oxygen therein in a vacuum and then vacuum depositing a silver layer onto the silicon enriched surface. The silicon enrichment can be attained by electron beam bombardment, ion beam bombardment, or neutral beam bombardment. It can also be attained by depositing a metal, such as aluminum, on the substrate surface, allowing the metal to oxidize by pulling oxygen from the substrate surface, thereby leaving a silicon enriched surface, and then etching or eroding the metal oxide layer away to expose the silicon enriched surface. Ultraviolet rays can be used to maintain dangling silicon bonds on the enriched surface until covalent bonding with the silver can occur. This disclosure also includes encapsulated mirrors with diffusion layers built therein. One of these mirrors is assembled on a polymer substrate.

Method of bonding silver to glass and mirrors produced according to this method

DOEpatents

Pitts, John R.; Thomas, Terence M.; Czanderna, Alvin W.

1985-01-01

A method for adhering silver to a glass substrate for producing mirrors includes attaining a silicon enriched substrate surface by reducing the oxygen therein in a vacuum and then vacuum depositing a silver layer onto the silicon enriched surface. The silicon enrichment can be attained by electron beam bombardment, ion beam bombardment, or neutral beam bombardment. It can also be attained by depositing a metal, such as aluminum, on the substrate surface, allowing the metal to oxidize by pulling oxygen from the substrate surface, thereby leaving a silicon enriched surface, and then etching or eroding the metal oxide layer away to expose the silicon enriched surface. Ultraviolet rays can be used to maintain dangling silicon bonds on the enriched surface until covalent bonding with the silver can occur. This disclosure also includes encapsulated mirrors with diffusion layers built therein. One of these mirrors is assembled on a polymer substrate.

Investigations of different doping concentration of phosphorus and boron into silicon substrate on the variable temperature Raman characteristics

NASA Astrophysics Data System (ADS)

Li, Xiaoli; Ding, Kai; Liu, Jian; Gao, Junxuan; Zhang, Weifeng

2018-01-01

Different doped silicon substrates have different device applications and have been used to fabricate solar panels and large scale integrated circuits. The thermal transport in silicon substrates are dominated by lattice vibrations, doping type, and doping concentration. In this paper, a variable-temperature Raman spectroscopic system is applied to record the frequency and linewidth changes of the silicon peak at 520 cm-1 in five chips of silicon substrate with different doping concentration of phosphorus and boron at the 83K to 1473K temperature range. The doping has better heat sensitive to temperature on the frequency shift over the low temperature range from 83K to 300K but on FWHM in high temperature range from 300K to 1473K. The results will be helpful for fundamental study and practical applications of silicon substrates.

Deposition of thermal and hot-wire chemical vapor deposition copper thin films on patterned substrates.

PubMed

Papadimitropoulos, G; Davazoglou, D

2011-09-01

In this work we study the hot-wire chemical vapor deposition (HWCVD) of copper films on blanket and patterned substrates at high filament temperatures. A vertical chemical vapor deposition reactor was used in which the chemical reactions were assisted by a tungsten filament heated at 650 degrees C. Hexafluoroacetylacetonate Cu(I) trimethylvinylsilane (CupraSelect) vapors were used, directly injected into the reactor with the aid of a liquid injection system using N2 as carrier gas. Copper thin films grown also by thermal and hot-wire CVD. The substrates used were oxidized silicon wafers on which trenches with dimensions of the order of 500 nm were formed and subsequently covered with LPCVD W. HWCVD copper thin films grown at filament temperature of 650 degrees C showed higher growth rates compared to the thermally ones. They also exhibited higher resistivities than thermal and HWCVD films grown at lower filament temperatures. Thermally grown Cu films have very uniform deposition leading to full coverage of the patterned substrates while the HWCVD films exhibited a tendency to vertical growth, thereby creating gaps and incomplete step coverage.

Fabrication of thermal microphotonic sensors and sensor arrays

DOEpatents

Shaw, Michael J.; Watts, Michael R.; Nielson, Gregory N.

2010-10-26

A thermal microphotonic sensor is fabricated on a silicon substrate by etching an opening and a trench into the substrate, and then filling in the opening and trench with silicon oxide which can be deposited or formed by thermally oxidizing a portion of the silicon substrate surrounding the opening and trench. The silicon oxide forms a support post for an optical resonator which is subsequently formed from a layer of silicon nitride, and also forms a base for an optical waveguide formed from the silicon nitride layer. Part of the silicon substrate can be selectively etched away to elevate the waveguide and resonator. The thermal microphotonic sensor, which is useful to detect infrared radiation via a change in the evanescent coupling of light between the waveguide and resonator, can be formed as a single device or as an array.

Method to control artifacts of microstructural fabrication

DOEpatents

Shul, Randy J.; Willison, Christi G.; Schubert, W. Kent; Manginell, Ronald P.; Mitchell, Mary-Anne; Galambos, Paul C.

2006-09-12

New methods for fabrication of silicon microstructures have been developed. In these methods, an etching delay layer is deposited and patterned so as to provide differential control on the depth of features being etched into a substrate material. Compensation for etching-related structural artifacts can be accomplished by proper use of such an etching delay layer.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dong, Rui; Moore, Logan; Ocola, Leonidas E.

The mask-free patterning technique is employed to fabricate arrays of MoS2 and WS2 structures on silicon and graphene substrates with quality interfaces. By depositing precursor inks with the AFM cantilevers and subsequent heat treatment in the CVD furnace, it is demonstrated that MoS2 and WS2 structures can be formed on graphene surfaces at predefined device architectures.

Electrical leakage phenomenon in heteroepitaxial cubic silicon carbide on silicon

NASA Astrophysics Data System (ADS)

Pradeepkumar, Aiswarya; Zielinski, Marcin; Bosi, Matteo; Verzellesi, Giovanni; Gaskill, D. Kurt; Iacopi, Francesca

2018-06-01

Heteroepitaxial 3C-SiC films on silicon substrates are of technological interest as enablers to integrate the excellent electrical, electronic, mechanical, thermal, and epitaxial properties of bulk silicon carbide into well-established silicon technologies. One critical bottleneck of this integration is the establishment of a stable and reliable electronic junction at the heteroepitaxial interface of the n-type SiC with the silicon substrate. We have thus investigated in detail the electrical and transport properties of heteroepitaxial cubic silicon carbide films grown via different methods on low-doped and high-resistivity silicon substrates by using van der Pauw Hall and transfer length measurements as test vehicles. We have found that Si and C intermixing upon or after growth, particularly by the diffusion of carbon into the silicon matrix, creates extensive interstitial carbon traps and hampers the formation of a stable rectifying or insulating junction at the SiC/Si interface. Although a reliable p-n junction may not be realistic in the SiC/Si system, we can achieve, from a point of view of the electrical isolation of in-plane SiC structures, leakage suppression through the substrate by using a high-resistivity silicon substrate coupled with deep recess etching in between the SiC structures.

Gauge Factor and Stretchability of Silicon-on-Polymer Strain Gauges

PubMed Central

Yang, Shixuan; Lu, Nanshu

2013-01-01

Strain gauges are widely applied to measure mechanical deformation of structures and specimens. While metallic foil gauges usually have a gauge factor slightly over 2, single crystalline silicon demonstrates intrinsic gauge factors as high as 200. Although silicon is an intrinsically stiff and brittle material, flexible and even stretchable strain gauges have been achieved by integrating thin silicon strips on soft and deformable polymer substrates. To achieve a fundamental understanding of the large variance in gauge factor and stretchability of reported flexible/stretchable silicon-on-polymer strain gauges, finite element and analytically models are established to reveal the effects of the length of the silicon strip, and the thickness and modulus of the polymer substrate. Analytical results for two limiting cases, i.e., infinitely thick substrate and infinitely long strip, have found good agreement with FEM results. We have discovered that strains in silicon resistor can vary by orders of magnitude with different substrate materials whereas strip length or substrate thickness only affects the strain level mildly. While the average strain in silicon reflects the gauge factor, the maximum strain in silicon governs the stretchability of the system. The tradeoff between gauge factor and stretchability of silicon-on-polymer strain gauges has been proposed and discussed. PMID:23881128

Dip-Coating Fabrication of Solar Cells

NASA Technical Reports Server (NTRS)

Koepke, B.; Suave, D.

1982-01-01

Inexpensive silicon solar cells made by simple dip technique. Cooling shoes direct flow of helium on graphite-coated ceramic substrate to solidify film of liquid silicon on graphite surface as substrate is withdrawn from molten silicon. After heaters control cooling of film and substrate to prevent cracking. Gas jets exit at points about 10 mm from substrate surfaces and 6 to 10 mm above melt surface.

Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction

DOEpatents

Toet, Daniel; Sigmon, Thomas W.

2004-12-07

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

Process For Direct Integration Of A Thin-Film Silicon P-N Junction Diode With A Magnetic Tunnel Junction

DOEpatents

Toet, Daniel; Sigmon, Thomas W.

2005-08-23

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

Process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction

DOEpatents

Toet, Daniel; Sigmon, Thomas W.

2003-01-01

A process for direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory (MRAM) cells for high performance, non-volatile memory arrays. The process is based on pulsed laser processing for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metals deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of at least one layer of silicon, either in an amorphous or a polycrystalline phase on a metal layer. Dopants may be introduced in the silicon film during or after deposition. The film is then irradiated with short pulse laser energy that is efficiently absorbed in the silicon, which results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The silicon film can be patterned either before or after crystallization.

VLED for Si wafer-level packaging

NASA Astrophysics Data System (ADS)

Chu, Chen-Fu; Chen, Chiming; Yen, Jui-Kang; Chen, Yung-Wei; Tsou, Chingfu; Chang, Chunming; Doan, Trung; Tran, Chuong Anh

2012-03-01

In this paper, we introduced the advantages of Vertical Light emitting diode (VLED) on copper alloy with Si-wafer level packaging technologies. The silicon-based packaging substrate starts with a <100> dou-ble-side polished p-type silicon wafer, then anisotropic wet etching technology is done to construct the re-flector depression and micro through-holes on the silicon substrate. The operating voltage, at a typical cur-rent of 350 milli-ampere (mA), is 3.2V. The operation voltage is less than 3.7V under higher current driving conditions of 1A. The VLED chip on Si package has excellent heat dissipation and can be operated at high currents up to 1A without efficiency degradation. The typical spatial radiation pattern emits a uniform light lambertian distribution from -65° to 65° which can be easily fit for secondary optics. The correlated color temperature (CCT) has only 5% variation for daylight and less than 2% variation for warm white, when the junction temperature is increased from 25°C to 110°C, suggesting a stable CCT during operation for general lighting application. Coupled with aspheric lens and micro lens array in a wafer level process, it has almost the same light distribution intensity for special secondary optics lighting applications. In addition, the ul-tra-violet (UV) VLED, featuring a silicon substrate and hard glass cover, manufactured by wafer level pack-aging emits high power UV wavelengths appropriate for curing, currency, document verification, tanning, medical, and sterilization applications.

Enhanced Raman scattering in porous silicon grating.

PubMed

Wang, Jiajia; Jia, Zhenhong; Lv, Changwu

2018-03-19

The enhancement of Raman signal on monocrystalline silicon gratings with varying groove depths and on porous silicon grating were studied for a highly sensitive surface enhanced Raman scattering (SERS) response. In the experiment conducted, porous silicon gratings were fabricated. Silver nanoparticles (Ag NPs) were then deposited on the porous silicon grating to enhance the Raman signal of the detective objects. Results show that the enhancement of Raman signal on silicon grating improved when groove depth increased. The enhanced performance of Raman signal on porous silicon grating was also further improved. The Rhodamine SERS response based on Ag NPs/ porous silicon grating substrates was enhanced relative to the SERS response on Ag NPs/ porous silicon substrates. Ag NPs / porous silicon grating SERS substrate system achieved a highly sensitive SERS response due to the coupling of various Raman enhancement factors.

High-Temperature Annealing as a Method for the Silicon Nanoclusters Growth in Stoichiometric Silicon Dioxide

NASA Astrophysics Data System (ADS)

Ivanova, E. V.; Dementev, P. A.; Sitnikova, A. A.; Aleksandrov, O. V.; Zamoryanskaya, M. V.

2018-07-01

A method for the growth of nanocomposite layers in stoichiometric amorphous silicon dioxide is proposed. It is shown that, after annealing at a temperature of 1150°C in nitrogen atmosphere, a layer containing silicon nanoclusters is formed. Silicon nanoclusters have a crystal structure and a size of 3-6 nm. In a film grown on a n-type substrate, a layer of silicon nanoclusters with a thickness of about 10 nm is observed. In the case of a film grown on a p-type substrate, a nanocomposite layer with a thickness of about 100 nm is observed. The difference in the formation of a nanocomposite layer in films on various substrates is associated with the doping of silicon dioxide with impurities from the substrate during the growth of the film. The formation of the nanocomposite layer was confirmed by transmission electron microscopy, XPS and local cathodoluminescence studies.

Selective-area catalyst-free MBE growth of GaN nanowires using a patterned oxide layer.

PubMed

Schumann, T; Gotschke, T; Limbach, F; Stoica, T; Calarco, R

2011-03-04

GaN nanowires (NWs) were grown selectively in holes of a patterned silicon oxide mask, by rf-plasma-assisted molecular beam epitaxy (PAMBE), without any metal catalyst. The oxide was deposited on a thin AlN buffer layer previously grown on a Si(111) substrate. Regular arrays of holes in the oxide layer were obtained using standard e-beam lithography. The selectivity of growth has been studied varying the substrate temperature, gallium beam equivalent pressure and patterning layout. Adjusting the growth parameters, GaN NWs can be selectively grown in the holes of the patterned oxide with complete suppression of the parasitic growth in between the holes. The occupation probability of a hole with a single or multiple NWs depends strongly on its diameter. The selectively grown GaN NWs have one common crystallographic orientation with respect to the Si(111) substrate via the AlN buffer layer, as proven by x-ray diffraction (XRD) measurements. Based on the experimental data, we present a schematic model of the GaN NW formation in which a GaN pedestal is initially grown in the hole.

Advancements in n-Type Base Crystalline Silicon Solar Cells and Their Emergence in the Photovoltaic Industry

PubMed Central

ur Rehman, Atteq; Lee, Soo Hong

2013-01-01

The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed. PMID:24459433

Advancements in n-type base crystalline silicon solar cells and their emergence in the photovoltaic industry.

PubMed

ur Rehman, Atteq; Lee, Soo Hong

2013-01-01

The p-type crystalline silicon wafers have occupied most of the solar cell market today. However, modules made with n-type crystalline silicon wafers are actually the most efficient modules up to date. This is because the material properties offered by n-type crystalline silicon substrates are suitable for higher efficiencies. Properties such as the absence of boron-oxygen related defects and a greater tolerance to key metal impurities by n-type crystalline silicon substrates are major factors that underline the efficiency of n-type crystalline silicon wafer modules. The bi-facial design of n-type cells with good rear-side electronic and optical properties on an industrial scale can be shaped as well. Furthermore, the development in the industrialization of solar cell designs based on n-type crystalline silicon substrates also highlights its boost in the contributions to the photovoltaic industry. In this paper, a review of various solar cell structures that can be realized on n-type crystalline silicon substrates will be given. Moreover, the current standing of solar cell technology based on n-type substrates and its contribution in photovoltaic industry will also be discussed.

Control of the sidewall angle of an absorber stack using the Faraday cage system for the change of pattern printability in EUVL

NASA Astrophysics Data System (ADS)

Jang, Il-Yong; Huh, Sung-Min; Moon, Seong-Yong; Woo, Sang-Gyun; Lee, Jin-Kwan; Moon, Sang Heup; Cho, HanKu

2008-10-01

A patterned TaN substrate, which is candidate for a mask absorber in extreme ultra-violet lithography (EUVL), was etched to have inclined sidewalls by using a Faraday cage system under the condition of a 2-step process that allowed the high etch selectivity of TaN over the resist. The sidewall angle (SWA) of the patterned substrate, which was in the shape of a parallelogram after etching, could be controlled by changing the slope of a substrate holder that was placed in the Faraday cage. The performance of an EUV mask, which contained the TaN absorber of an oblique pattern over the molybdenum/silicon multi-layer, was simulated for different cases of SWA. The results indicated that the optical properties, such as the critical dimension (CD), an offset in the CD bias between horizontal and vertical patterns (H-V bias), and a shift in the image position on the wafer, could be controlled by changing the SWA of the absorber stack. The simulation result showed that the effect of the SWA on the optical properties became more significant at larger thicknesses of the absorber and smaller sizes of the target CD. Nevertheless, the contrast of the aerial images was not significantly decreased because the shadow effect caused by either sidewall of the patterned substrate cancelled with each other.

Wafer-Level Membrane-Transfer Process for Fabricating MEMS

NASA Technical Reports Server (NTRS)

Yang, Eui-Hyeok; Wiberg, Dean

2003-01-01

A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

Process for utilizing low-cost graphite substrates for polycrystalline solar cells

NASA Technical Reports Server (NTRS)

Chu, T. L. (Inventor)

1978-01-01

Low cost polycrystalline silicon solar cells supported on substrates were prepared by depositing successive layers of polycrystalline silicon containing appropriate dopants over supporting substrates of a member selected from the group consisting of metallurgical grade polycrystalline silicon, graphite and steel coated with a diffusion barrier of silica, borosilicate, phosphosilicate, or mixtures thereof such that p-n junction devices were formed which effectively convert solar energy to electrical energy. To improve the conversion efficiency of the polycrystalline silicon solar cells, the crystallite size in the silicon was substantially increased by melting and solidifying a base layer of polycrystalline silicon before depositing the layers which form the p-n junction.

Silicon based substrate with calcium aluminosilicate/thermal barrier layer

NASA Technical Reports Server (NTRS)

Eaton, Jr., Harry Edwin (Inventor); Allen, William Patrick (Inventor); Miller, Robert Alden (Inventor); Jacobson, Nathan S. (Inventor); Smialek, James L. (Inventor); Opila, Elizabeth J. (Inventor); Lee, Kang N. (Inventor); Nagaraj, Bangalore A. (Inventor); Wang, Hongyu (Inventor); Meschter, Peter Joel (Inventor)

2001-01-01

A barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment comprises a calcium alumino silicate.

Silicon based substrate with environmental/thermal barrier layer

NASA Technical Reports Server (NTRS)

Eaton, Jr., Harry Edwin (Inventor); Allen, William Patrick (Inventor); Jacobson, Nathan S. (Inventor); Bansal, Narottam P. (Inventor); Opila, Elizabeth J. (Inventor); Smialek, James L. (Inventor); Lee, Kang N. (Inventor); Spitsberg, Irene T. (Inventor); Wang, Hongyu (Inventor); Meschter, Peter Joel (Inventor)

2002-01-01

A barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment comprises a barium-strontium alumino silicate.

Silicon based substrate with environmental/ thermal barrier layer

NASA Technical Reports Server (NTRS)

Eaton, Jr., Harry Edwin (Inventor); Allen, William Patrick (Inventor); Jacobson, Nathan S. (Inventor); Bansal, Nanottam P. (Inventor); Opila, Elizabeth J. (Inventor); Smialek, James L. (Inventor); Lee, Kang N. (Inventor); Spitsberg, Irene T. (Inventor); Wang, Hongyu (Inventor); Meschter, Peter Joel (Inventor)

2002-01-01

A barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment comprises a barium-strontium alumino silicate.

Single-crystal silicon trench etching for fabrication of highly integrated circuits

NASA Astrophysics Data System (ADS)

Engelhardt, Manfred

1991-03-01

The development of single crystal silicon trench etching for fabrication of memory cells in 4 16 and 64Mbit DRAMs is reviewed in this paper. A variety of both etch tools and process gases used for the process development is discussed since both equipment and etch chemistry had to be improved and changed respectively to meet the increasing requirements for high fidelity pattern transfer with increasing degree of integration. In additon to DRAM cell structures etch results for deep trench isolation in advanced bipolar ICs and ASICs are presented for these applications grooves were etched into silicon through a highly doped buried layer and at the borderline of adjacent p- and n-well areas respectively. Shallow trench etching of large and small exposed areas with identical etch rates is presented as an approach to replace standard LOCOS isolation by an advanced isolation technique. The etch profiles were investigated with SEM TEM and AES to get information on contathination and damage levels and on the mechanism leading to anisotropy in the dry etch process. Thermal wave measurements were performed on processed single crystal silicon substrates for a fast evaluation of the process with respect to plasma-induced substrate degradation. This useful technique allows an optimization ofthe etch process regarding high electrical performance of the fully processed memory chip. The benefits of the use of magnetic fields for the development of innovative single crystal silicon dry

Buried oxide layer in silicon

DOEpatents

Sadana, Devendra Kumar; Holland, Orin Wayne

2001-01-01

A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Silicon based substrate with calcium aluminosilicate environmental/thermal barrier layer

NASA Technical Reports Server (NTRS)

Eaton, Jr., Harry Edwin (Inventor); Allen, William Patrick (Inventor); Miller, Robert Alden (Inventor); Jacobson, Nathan S. (Inventor); Smialek, James L. (Inventor); Opila, Elizabeth J. (Inventor); Lee, Kang N. (Inventor); Nagaraj, Bangalore A. (Inventor); Wang, Hongyu (Inventor); Meschter, Peter Joel (Inventor)

2001-01-01

A barrier layer for a silicon containing substrate which inhibits the formation of gaseous species of silicon when exposed to a high temperature aqueous environment comprises a calcium alumino silicate.

Wet-chemical systems and methods for producing black silicon substrates

DOEpatents

Yost, Vernon; Yuan, Hao-Chih; Page, Matthew

2015-05-19

A wet-chemical method of producing a black silicon substrate. The method comprising soaking single crystalline silicon wafers in a predetermined volume of a diluted inorganic compound solution. The substrate is combined with an etchant solution that forms a uniform noble metal nanoparticle induced Black Etch of the silicon wafer, resulting in a nanoparticle that is kinetically stabilized. The method comprising combining with an etchant solution having equal volumes acetonitrile/acetic acid:hydrofluoric acid:hydrogen peroxide.

Fabrication of 3D nano-structures using reverse imprint lithography

NASA Astrophysics Data System (ADS)

Han, Kang-Soo; Hong, Sung-Hoon; Kim, Kang-In; Cho, Joong-Yeon; Choi, Kyung-woo; Lee, Heon

2013-02-01

In spite of the fact that the fabrication process of three-dimensional nano-structures is complicated and expensive, it can be applied to a range of devices to increase their efficiency and sensitivity. Simple and inexpensive fabrication of three-dimensional nano-structures is necessary. In this study, reverse imprint lithography (RIL) with UV-curable benzylmethacrylate, methacryloxypropyl terminated poly-dimethylsiloxane (M-PDMS) resin and ZnO-nano-particle-dispersed resin was used to fabricate three-dimensional nano-structures. UV-curable resins were placed between a silicon stamp and a PVA transfer template, followed by a UV curing process. Then, the silicon stamp was detached and a 2D pattern layer was transferred to the substrate using diluted UV-curable glue. Consequently, three-dimensional nano-structures were formed by stacking the two-dimensional nano-patterned layers. RIL was applied to a light-emitting diode (LED) to evaluate the optical effects of a nano-patterned layer. As a result, the light extraction of the patterned LED was increased by about 12% compared to an unpatterned LED.

Fabrication of 3D nano-structures using reverse imprint lithography.

PubMed

Han, Kang-Soo; Hong, Sung-Hoon; Kim, Kang-In; Cho, Joong-Yeon; Choi, Kyung-Woo; Lee, Heon

2013-02-01

In spite of the fact that the fabrication process of three-dimensional nano-structures is complicated and expensive, it can be applied to a range of devices to increase their efficiency and sensitivity. Simple and inexpensive fabrication of three-dimensional nano-structures is necessary. In this study, reverse imprint lithography (RIL) with UV-curable benzylmethacrylate, methacryloxypropyl terminated poly-dimethylsiloxane (M-PDMS) resin and ZnO-nano-particle-dispersed resin was used to fabricate three-dimensional nano-structures.UV-curable resins were placed between a silicon stamp and a PVA transfer template, followed by a UV curing process. Then, the silicon stamp was detached and a 2D pattern layer was transferred to the substrate using diluted UV-curable glue. Consequently, three-dimensional nano-structures were formed by stacking the two-dimensional nano-patterned layers. RIL was applied to a light-emitting diode (LED) to evaluate the optical effects of a nano-patterned layer. As a result, the light extraction of the patterned LED was increased by about 12% compared to an unpatterned LED.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rodríguez-González, R.; Martínez-Orozco, J. C.; Madrigal-Melchor, J.

In this work we use the standard T-matrix method to study the tunneling of Dirac electrons through graphene multilayers. A graphene sheet is deposited on top of slabs of Silicon-Oxide (SiO{sub 2}) and Silicon-Carbide (SiC) substrates, in which we applied the Cantor’s series. We calculate the transmittance as a function of energy for different incident angles and different generations of the Cantor’s series. Comparing the transmittance, we found three types of self-similarity: (a) local - into generations, (b) between incident angles and (c) between generations. We also compute the angular distribution of the transmittance for fixed energies finding a self-similarmore » pattern between generations. To our knowledge is the first time that four different self-similar patterns are presented in Cantor-based multilayers.« less

Pattern manipulation via on-chip phase modulation between orbital angular momentum beams

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Huanlu; School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LP; Strain, Michael J.

2015-08-03

An integrated approach to thermal modulation of relative phase between two optical vortices with opposite chirality has been demonstrated on a silicon-on-insulator substrate. The device consists of a silicon-integrated optical vortex emitter and a phase controlled 3 dB coupler. The relative phase between two optical vortices can be actively modulated on chip by applying a voltage on the integrated heater. The phase shift is shown to be linearly proportional to applied electrical power, and the rotation angle of the interference pattern is observed to be inversely proportional to topological charge. This scheme can be used in lab-on-chip, communications and sensing applications.more » It can be intentionally implemented with other modulation elements to achieve more complicated applications.« less

Photovoltaic device using single wall carbon nanotubes and method of fabricating the same

DOEpatents

Biris, Alexandru S.; Li, Zhongrui

2012-11-06

A photovoltaic device and methods for forming the same. In one embodiment, the photovoltaic device has a silicon substrate, and a film comprising a plurality of single wall carbon nanotubes disposed on the silicon substrate, wherein the plurality of single wall carbon nanotubes forms a plurality of heterojunctions with the silicon in the substrate.

Surface thiolation of silicon for antifouling application.

PubMed

Zhang, Xiaoning; Gao, Pei; Hollimon, Valerie; Brodus, DaShan; Johnson, Arion; Hu, Hongmei

2018-02-07

Thiol groups grafted silicon surface was prepared as previously described. 1H,1H,2H,2H-perfluorodecanethiol (PFDT) molecules were then immobilized on such a surface through disulfide bonds formation. To investigate the contribution of PFDT coating to antifouling, the adhesion behaviors of Botryococcus braunii (B. braunii) and Escherichia coli (E. coli) were studied through biofouling assays in the laboratory. The representative microscope images suggest reduced B. braunii and E. coli accumulation densities on PFDT integrated silicon substrate. However, the antifouling performance of PFDT integrated silicon substrate decreased over time. By incubating the aged substrate in 10 mM TCEP·HCl solution for 1 h, the fouled PFDT coating could be removed as the disulfide bonds were cleaved, resulting in reduced absorption of algal cells and exposure of non-fouled silicon substrate surface. Our results indicate that the thiol-terminated substrate can be potentially useful for restoring the fouled surface, as well as maximizing the effective usage of the substrate.

Metallization and Biopatterning on Ultra-Flexible Substrates via Dextran Sacrificial Layers

PubMed Central

Tseng, Peter; Pushkarsky, Ivan; Di Carlo, Dino

2014-01-01

Micro-patterning tools adopted from the semiconductor industry have mostly been optimized to pattern features onto rigid silicon and glass substrates, however, recently the need to pattern on soft substrates has been identified in simulating cellular environments or developing flexible biosensors. We present a simple method of introducing a variety of patterned materials and structures into ultra-flexible polydimethylsiloxane (PDMS) layers (elastic moduli down to 3 kPa) utilizing water-soluble dextran sacrificial thin films. Dextran films provided a stable template for photolithography, metal deposition, particle adsorption, and protein stamping. These materials and structures (including dextran itself) were then readily transferrable to an elastomer surface following PDMS (10 to 70∶1 base to crosslinker ratios) curing over the patterned dextran layer and after sacrificial etch of the dextran in water. We demonstrate that this simple and straightforward approach can controllably manipulate surface wetting and protein adsorption characteristics of PDMS, covalently link protein patterns for stable cell patterning, generate composite structures of epoxy or particles for study of cell mechanical response, and stably integrate certain metals with use of vinyl molecular adhesives. This method is compatible over the complete moduli range of PDMS, and potentially generalizable over a host of additional micro- and nano-structures and materials. PMID:25153326

Structural properties of templated Ge quantum dot arrays: impact of growth and pre-pattern parameters

NASA Astrophysics Data System (ADS)

Tempeler, J.; Danylyuk, S.; Brose, S.; Loosen, P.; Juschkin, L.

2018-07-01

In this study we analyze the impact of process and growth parameters on the structural properties of germanium (Ge) quantum dot (QD) arrays. The arrays were deposited by molecular-beam epitaxy on pre-patterned silicon (Si) substrates. Periodic arrays of pits with diameters between 120 and 20 nm and pitches ranging from 200 nm down to 40 nm were etched into the substrate prior to growth. The structural perfection of the two-dimensional QD arrays was evaluated based on SEM images. The impact of two processing steps on the directed self-assembly of Ge QD arrays is investigated. First, a thin Si buffer layer grown on a pre-patterned substrate reshapes the pre-pattern pits and determines the nucleation and initial shape of the QDs. Subsequently, the deposition parameters of the Ge define the overall shape and uniformity of the QDs. In particular, the growth temperature and the deposition rate are relevant and need to be optimized according to the design of the pre-pattern. Applying this knowledge, we are able to fabricate regular arrays of pyramid shaped QDs with dot densities up to 7.2 × 1010 cm‑2.

Structural properties of templated Ge quantum dot arrays: impact of growth and pre-pattern parameters.

PubMed

Tempeler, J; Danylyuk, S; Brose, S; Loosen, P; Juschkin, L

2018-07-06

In this study we analyze the impact of process and growth parameters on the structural properties of germanium (Ge) quantum dot (QD) arrays. The arrays were deposited by molecular-beam epitaxy on pre-patterned silicon (Si) substrates. Periodic arrays of pits with diameters between 120 and 20 nm and pitches ranging from 200 nm down to 40 nm were etched into the substrate prior to growth. The structural perfection of the two-dimensional QD arrays was evaluated based on SEM images. The impact of two processing steps on the directed self-assembly of Ge QD arrays is investigated. First, a thin Si buffer layer grown on a pre-patterned substrate reshapes the pre-pattern pits and determines the nucleation and initial shape of the QDs. Subsequently, the deposition parameters of the Ge define the overall shape and uniformity of the QDs. In particular, the growth temperature and the deposition rate are relevant and need to be optimized according to the design of the pre-pattern. Applying this knowledge, we are able to fabricate regular arrays of pyramid shaped QDs with dot densities up to 7.2 × 10 10 cm -2 .

Band gaps and Brekhovskikh attenuation of laser-generated surface acoustic waves in a patterned thin film structure on silicon

NASA Astrophysics Data System (ADS)

Maznev, A. A.

2008-10-01

Surface acoustic modes of a periodic array of copper and SiO2 lines on a silicon substrate are studied using a laser-induced transient grating technique. It is found that the band gap formed inside the Brillouin zone due to “avoided crossing” of Rayleigh and Sezawa modes is much greater than the band gap in the Rayleigh wave dispersion formed at the zone boundary. Another unexpected finding is that a very strong periodicity-induced attenuation is observed above the longitudinal threshold rather than above the transverse threshold.

Advanced detectors and signal processing

NASA Technical Reports Server (NTRS)

Greve, D. W.; Rasky, P. H. L.; Kryder, M. H.

1986-01-01

Continued progress is reported toward development of a silicon on garnet technology which would allow fabrication of advanced detection and signal processing circuits on bubble memories. The first integrated detectors and propagation patterns have been designed and incorporated on a new mask set. In addition, annealing studies on spacer layers are performed. Based on those studies, a new double layer spacer is proposed which should reduce contamination of the silicon originating in the substrate. Finally, the magnetic sensitivity of uncontaminated detectors from the last lot of wafers is measured. The measured sensitivity is lower than anticipated but still higher than present magnetoresistive detectors.

Optimization and characterization of biomolecule immobilization on silicon substrates using (3-aminopropyl)triethoxysilane (APTES) and glutaraldehyde linker

NASA Astrophysics Data System (ADS)

Gunda, Naga Siva Kumar; Singh, Minashree; Norman, Lana; Kaur, Kamaljit; Mitra, Sushanta K.

2014-06-01

In the present work, we developed and optimized a technique to produce a thin, stable silane layer on silicon substrate in a controlled environment using (3-aminopropyl)triethoxysilane (APTES). The effect of APTES concentration and silanization time on the formation of silane layer is studied using spectroscopic ellipsometry and Fourier transform infrared spectroscopy (FTIR). Biomolecules of interest are immobilized on optimized silane layer formed silicon substrates using glutaraldehyde linker. Surface analytical techniques such as ellipsometry, FTIR, contact angle measurement system, and atomic force microscopy are employed to characterize the bio-chemically modified silicon surfaces at each step of the biomolecule immobilization process. It is observed that a uniform, homogenous and highly dense layer of biomolecules are immobilized with optimized silane layer on the silicon substrate. The developed immobilization method is successfully implemented on different silicon substrates (flat and pillar). Also, different types of biomolecules such as anti-human IgG (rabbit monoclonal to human IgG), Listeria monocytogenes, myoglobin and dengue capture antibodies were successfully immobilized. Further, standard sandwich immunoassay (antibody-antigen-antibody) is employed on respective capture antibody coated silicon substrates. Fluorescence microscopy is used to detect the respective FITC tagged detection antibodies bound to the surface after immunoassay.

Surface modification of silicon wafer by grafting zwitterionic polymers to improve its antifouling property

NASA Astrophysics Data System (ADS)

Sun, Yunlong; Chen, Changlin; Xu, Heng; Lei, Kun; Xu, Guanzhe; Zhao, Li; Lang, Meidong

2017-10-01

Silicon (111) wafer was modified by triethoxyvinylsilane containing double bond as an intermedium, and then P4VP (polymer 4-vinyl pyridine) brush was "grafted" onto the surface of silicon wafer containing reactive double bonds by adopting the "grafting from" way and Si-P4VP substrate (silicon wafer grafted by P4VP) was obtained. Finally, P4VP brush of Si-P4VP substrate was modified by 1,3-propanesulfonate fully to obtain P4VP-psl brush (zwitterionic polypyridinium salt) and the functional Si-P4VP-psl substrate (silicon wafer grafted by zwitterionic polypyridinium salt based on polymer 4-vinyl pyridine) was obtained successfully. The antifouling property of the silicon wafer, the Si-P4VP substrate and the Si-P4VP-psl substrate was investigated by using bovine serum albumin, mononuclear macrophages (RAW 264.7) and Escherichia coli (E. coli) ATTC25922 as model bacterium. The results showed that compared with the blank sample-silicon wafer, the Si-P4VP-psl substrate had excellent anti-adhesion ability against bovine serum albumin, cells and bacterium, due to zwitterionic P4VP-psl brush (polymer 4-vinyl pyridine salt) having special functionality like antifouling ability on biomaterial field.

Ceramic with zircon coating

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor)

2003-01-01

An article comprises a silicon-containing substrate and a zircon coating. The article can comprise a silicon carbide/silicon (SiC/Si) substrate, a zircon (ZrSiO.sub.4) intermediate coating and an external environmental/thermal barrier coating.

Superhydrophobic SERS substrates based on silicon hierarchical nanostructures

NASA Astrophysics Data System (ADS)

Chen, Xuexian; Wen, Jinxiu; Zhou, Jianhua; Zheng, Zebo; An, Di; Wang, Hao; Xie, Weiguang; Zhan, Runze; Xu, Ningsheng; Chen, Jun; She, Juncong; Chen, Huanjun; Deng, Shaozhi

2018-02-01

Silicon nanostructures have been cultivated as promising surface enhanced Raman scattering (SERS) substrates in terms of their low-loss optical resonance modes, facile functionalization, and compatibility with today’s state-of-the-art CMOS techniques. However, unlike their plasmonic counterparts, the electromagnetic field enhancements induced by silicon nanostructures are relatively small, which restrict their SERS sensing limit to around 10-7 M. To tackle this problem, we propose here a strategy for improving the SERS performance of silicon nanostructures by constructing silicon hierarchical nanostructures with a superhydrophobic surface. The hierarchical nanostructures are binary structures consisted of silicon nanowires (NWs) grown on micropyramids (MPs). After being modified with perfluorooctyltriethoxysilane (PFOT), the nanostructure surface shows a stable superhydrophobicity with a high contact angle of ˜160°. The substrate can allow for concentrating diluted analyte solutions into a specific area during the evaporation of the liquid droplet, whereby the analytes are aggregated into a small volume and can be easily detected by the silicon nanostructure SERS substrate. The analyte molecules (methylene blue: MB) enriched from an aqueous solution lower than 10-8 M can be readily detected. Such a detection limit is ˜100-fold lower than the conventional SERS substrates made of silicon nanostructures. Additionally, the detection limit can be further improved by functionalizing gold nanoparticles onto silicon hierarchical nanostructures, whereby the superhydrophobic characteristics and plasmonic field enhancements can be combined synergistically to give a detection limit down to ˜10-11 M. A gold nanoparticle-functionalized superhydrophobic substrate was employed to detect the spiked melamine in liquid milk. The results showed that the detection limit can be as low as 10-5 M, highlighting the potential of the proposed superhydrophobic SERS substrate in practical food safety inspection applications.

Preparation of freestanding GaN wafer by hydride vapor phase epitaxy on porous silicon

NASA Astrophysics Data System (ADS)

Wu, Xian; Li, Peng; Liang, Renrong; Xiao, Lei; Xu, Jun; Wang, Jing

2018-05-01

A freestanding GaN wafer was prepared on porous Si (111) substrate using hydride vapor phase epitaxy (HVPE). To avoid undesirable effects of the porous surface on the crystallinity of the GaN, a GaN seed layer was first grown on the Si (111) bare wafer. A pattern with many apertures was fabricated in the GaN seed layer using lithography and etching processes. A porous layer was formed in the Si substrate immediately adjacent to the GaN seed layer by an anodic etching process. A 500-μm-thick GaN film was then grown on the patterned GaN seed layer using HVPE. The GaN film was separated from the Si substrate through the formation of cracks in the porous layer caused by thermal mismatch stress during the cooling stage of the HVPE. Finally, the GaN film was polished to obtain a freestanding GaN wafer.

Quantum model of a solid-state spin qubit: Ni cluster on a silicon surface by the generalized spin Hamiltonian and X-ray absorption spectroscopy investigations

NASA Astrophysics Data System (ADS)

Farberovich, Oleg V.; Mazalova, Victoria L.; Soldatov, Alexander V.

2015-11-01

We present here the quantum model of a Ni solid-state electron spin qubit on a silicon surface with the use of a density-functional scheme for the calculation of the exchange integrals in the non-collinear spin configurations in the generalized spin Hamiltonian (GSH) with the anisotropic exchange coupling parameters linking the nickel ions with a silicon substrate. In this model the interaction of a spin qubit with substrate is considered in GSH at the calculation of exchange integrals Jij of the nanosystem Ni7-Si in the one-electron approach taking into account chemical bonds of all Si-atoms of a substrate (environment) with atoms of the Ni7-cluster. The energy pattern was found from the effective GSH Hamiltonian acting in the restricted spin space of the Ni ions by the application of the irreducible tensor operators (ITO) technique. In this paper we offer the model of the quantum solid-state N-spin qubit based on the studying of the spin structure and the spin-dynamics simulations of the 3d-metal Ni clusters on the silicon surface. The solution of the problem of the entanglement between spin states in the N-spin systems is becoming more interesting when considering clusters or molecules with a spectral gap in their density of states. For quantifying the distribution of the entanglement between the individual spin eigenvalues (modes) in the spin structure of the N-spin system we use the density of entanglement (DOE). In this study we have developed and used the advanced high-precision numerical techniques to accurately assess the details of the decoherence process governing the dynamics of the N-spin qubits interacting with a silicon surface. We have studied the Rabi oscillations to evaluate the N-spin qubits system as a function of the time and the magnetic field. We have observed the stabilized Rabi oscillations and have stabilized the quantum dynamical qubit state and Rabi driving after a fixed time (0.327 μs). The comparison of the energy pattern with the anisotropic exchange models conventionally used for the analysis of this system and, with the results of the experimental XANES spectra, shows that our complex investigations provide a good description of the pattern of the spin levels and the spin structures of the nanomagnetic Ni7 qubit. The results are discussed in the view of the general problem of the solid-state spin qubits and the spin structure of the Ni cluster.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojciechowski, Kenneth; Olsson, Roy; Clews, Peggy J.

Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

Design of a patterned nanostructure array using a nanosecond pulsed laser

NASA Astrophysics Data System (ADS)

Yoshida, Yutaka; Ohnishi, Ko; Matsuo, Yasutaka; Watanabe, Seiichi

2018-04-01

For design the patterned nanostructure array (PNSA) on material surface using a nanosecond pulsed laser, we investigated the influence of phase shift between scattered lights on silicon (Si) substrate using 30-nm-wide gold lines (GLs) spacings. At a spacing of 5,871 nm, ten nanodot (ND) arrays were formed at intervals of 533 nm by nanosecond pulsed laser. The results show that the formation of the PNSA was affected by the resonance of scattered light. We conclude that ND arrays were formed with a spacing of Λ = nλ. And we have designed PNSA comprising two ND arrays on the substrate. The PNSA with dimensions of 1,600 nm × 1,600 nm was prepared using GLs.

The Impact of GaN/Substrate Thermal Boundary Resistance on a HEMT Device

DTIC Science & Technology

2011-11-01

stack between the GaN and Substrate layers. The University of Bristol recently reported that this TBR in commercial devices on Silicon Carbide ( SiC ...Circuit RF Radio Frequency PA Power Amplifier SiC Silicon Carbide FEA Finite Element Analysis heff Effective Heat transfer Coefficient (W/m 2 K...substrate material switched from sapphire to silicon , and by another factor of two from silicon to SiC . TABLE 1: SAMPLE RESULTS FROM DOUGLAS ET AL. FOR

Cryogenic High Pressure Sensor Module

NASA Technical Reports Server (NTRS)

Chapman, John J. (Inventor); Shams, Qamar A. (Inventor); Powers, William T. (Inventor)

1999-01-01

A pressure sensor is provided for cryogenic, high pressure applications. A highly doped silicon piezoresistive pressure sensor is bonded to a silicon substrate in an absolute pressure sensing configuration. The absolute pressure sensor is bonded to an aluminum nitride substrate. Aluminum nitride has appropriate coefficient of thermal expansion for use with highly doped silicon at cryogenic temperatures. A group of sensors, either two sensors on two substrates or four sensors on a single substrate are packaged in a pressure vessel.

Cryogenic, Absolute, High Pressure Sensor

NASA Technical Reports Server (NTRS)

Chapman, John J. (Inventor); Shams. Qamar A. (Inventor); Powers, William T. (Inventor)

2001-01-01

A pressure sensor is provided for cryogenic, high pressure applications. A highly doped silicon piezoresistive pressure sensor is bonded to a silicon substrate in an absolute pressure sensing configuration. The absolute pressure sensor is bonded to an aluminum nitride substrate. Aluminum nitride has appropriate coefficient of thermal expansion for use with highly doped silicon at cryogenic temperatures. A group of sensors, either two sensors on two substrates or four sensors on a single substrate are packaged in a pressure vessel.

Compensated amorphous silicon solar cell

DOEpatents

Devaud, Genevieve

1983-01-01

An amorphous silicon solar cell including an electrically conductive substrate, a layer of glow discharge deposited hydrogenated amorphous silicon over said substrate and having regions of differing conductivity with at least one region of intrinsic hydrogenated amorphous silicon. The layer of hydrogenated amorphous silicon has opposed first and second major surfaces where the first major surface contacts the electrically conductive substrate and an electrode for electrically contacting the second major surface. The intrinsic hydrogenated amorphous silicon region is deposited in a glow discharge with an atmosphere which includes not less than about 0.02 atom percent mono-atomic boron. An improved N.I.P. solar cell is disclosed using a BF.sub.3 doped intrinsic layer.

Role of Cellulose Nanocrystals on the Microstructure of Maleic Anhydride Plasma Polymer Thin Films.

PubMed

Brioude, Michel M; Roucoules, Vincent; Haidara, Hamidou; Vonna, Laurent; Laborie, Marie-Pierre

2015-07-01

Recently, it was shown that the microstructure of a maleic anhydride plasma polymer (MAPP) could be tailored ab initio by adjusting the plasma process parameters. In this work, we aim to investigate the ability of cellulose nanocrystals (CNCs) to induce topographical structuration. Thus, a new approach was designed based on the deposition of MAPP on CNCs model surfaces. The nanocellulosic surfaces were produced by spin-coating the CNC suspension on a silicon wafer substrate and on a hydrophobic silicon wafer substrate patterned with circular hydrophilic microsized domains (diameter of 86.9 ± 4.9 μm), resulting in different degrees of CNC aggregation. By depositing the MAPP over these surfaces, it was possible to observe that the surface fraction of nanostructures increased from 20% to 35%. This observation suggests that CNCs can act as nucleation points resulting in more structures, although a critical density of the CNCs is required.

Properties of Nanocrystalline Cubic Silicon Carbide Thin Films Prepared by Hot-Wire Chemical Vapor Deposition Using SiH4/CH4/H2 at Various Substrate Temperatures

NASA Astrophysics Data System (ADS)

Tabata, Akimori; Komura, Yusuke; Hoshide, Yoshiki; Narita, Tomoki; Kondo, Akihiro

2008-01-01

Silicon carbide (SiC) thin films were prepared by hot-wire chemical vapor deposition from SiH4/CH4/H2 gases, and the influence of substrate temperature, Ts (104 < Ts < 434 °C), on the properties of the SiC thin films was investigated. X-ray diffraction patterns and Raman scattering spectra revealed that nanocrystalline cubic SiC (nc-3C-SiC) films grew at Ts above 187 °C, while completely amorphous films grew at Ts = 104 °C. Fourier transform infrared absorption spectra revealed that the crystallinity of the nc-3C-SiC was improved with increasing Ts up to 282 °C and remained almost unchanged with a further increase in Ts from 282 to 434 °C. The spin density was reduced monotonically with increasing Ts.

Polymerizable Supramolecular Approach to Highly Conductive PEDOT:PSS Patterns.

PubMed

Kim, Tae Geun; Ha, Su Ryong; Choi, Hyosung; Uh, Kyungchan; Kundapur, Umesha; Park, Sumin; Lee, Chan Woo; Lee, Sang-Hwa; Kim, Jaeyong; Kim, Jong-Man

2017-06-07

Owing to its high conductivity, solution processability, mechanical flexibility, and transparency, poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) has been extensively explored for use in functional devices including solar cells, sensors, light-emitting diodes, and supercapacitors. The ability to fabricate patterned PEDOT:PSS on a solid substrate is of significant importance to develop practical applications of this conducting polymer. Herein, we describe a new approach to obtain PEDOT:PSS patterns that are based on a polymerizable supramolecular concept. Specifically, we found that UV irradiation of a photopolymerizable diacetylene containing PEDOT:PSS film followed by development in deionized water and subsequent treatment with sulfuric acid (glass and silicon wafer) or formic acid (PET) produces micron-sized PEDOT:PSS patterns on solid substrates. The newly designed photolithographic method, which can be employed to generate highly conductive (>1000 S/cm) PEDOT:PSS patterns, has many advantages including the use of aqueous process conditions, a reduced number of process steps, and no requirement for plasma etching procedures.

Laser patterning of diamond films

NASA Astrophysics Data System (ADS)

Narayan, J.; Chen, X.

1992-04-01

Selective deposition and fine-scale patterning of hot filament deposited diamond films by the use of pulsed laser irradiation on silicon and copper substrates are reported. The substrates were abraded with diamond and alumina powders before hot-filament chemical vapor deposition. A drastic enhancement in diamond nucleation (using hot-filament chemical vapor deposition) was observed on specimens treated with diamond powder, whereas enhancement on specimens pretreated with alumina powder was relatively insignificant. It is found that the seeding of diamond crystals was substantially reduced by pulsed laser annealing/melting which removes the plastic damage as well as the seed crystals introduced by diamond powder pretreatment. The selective deposition or fine-scale patterning of diamond films was achieved either by a shadow masking or by scanning a focused laser beam to generate desired patterns. The nucleation can also be enhanced by laser deposition of thin films, such as diamond-like carbon and tungsten carbide (WC), and selective deposition and patterning achieved by controlled removal or deposition of the above films.

Low-stress photosensitive polyimide suspended membrane for improved thermal isolation performance

NASA Astrophysics Data System (ADS)

Fan, J.; Xing, R. Y.; Wu, W. J.; Liu, H. F.; Liu, J. Q.; Tu, L. C.

2017-11-01

In this paper, we introduce a method of isolating thermal conduction from silicon substrate for accommodating thermal-sensitive micro-devices. This method lies in fabrication of a low-stress photosensitive polyimide (PSPI) suspension structure which has lower thermal conductivity than silicon. First, a PSPI layer was patterned on a silicon wafer and hard baked. Then, a cavity was etched from the backside of the silicon substrate to form a membrane or a bridge-shape PSPI structure. After releasing, a slight deformation of about 20 nm was observed in the suspended structures, suggesting ultralow residual stress which is essential for accommodating micro-devices. In order to investigate the thermal isolation performance of the suspended PSPI structures, micro Pirani vacuum gauges, which are thermal-sensitive, had been fabricated on the PSPI structures. The measurement results illustrated that the Pirani gauges worked as expected in the range from 1- 470 Pa. Moreover, the results of the Pirani gauges based on the membrane and bridge structures were comparable, indicating that the commonly used bridge-shape structure for further reducing thermal conduction was unnecessary. Due to the excellent thermal isolation performance of PSPI, the suspended PSPI membrane is promising to be an outstanding candidate for thermal isolation applications.

RF Sputtering for preparing substantially pure amorphous silicon monohydride

DOEpatents

Jeffrey, Frank R.; Shanks, Howard R.

1982-10-12

A process for controlling the dihydride and monohydride bond densities in hydrogenated amorphous silicon produced by reactive rf sputtering of an amorphous silicon target. There is provided a chamber with an amorphous silicon target and a substrate therein with the substrate and the target positioned such that when rf power is applied to the target the substrate is in contact with the sputtering plasma produced thereby. Hydrogen and argon are fed to the chamber and the pressure is reduced in the chamber to a value sufficient to maintain a sputtering plasma therein, and then rf power is applied to the silicon target to provide a power density in the range of from about 7 watts per square inch to about 22 watts per square inch to sputter an amorphous silicon hydride onto the substrate, the dihydride bond density decreasing with an increase in the rf power density. Substantially pure monohydride films may be produced.

Method of forming buried oxide layers in silicon

DOEpatents

Sadana, Devendra Kumar; Holland, Orin Wayne

2000-01-01

A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Room-temperature bonding of epitaxial layer to carbon-cluster ion-implanted silicon wafers for CMOS image sensors

NASA Astrophysics Data System (ADS)

Koga, Yoshihiro; Kadono, Takeshi; Shigematsu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Okuyama, Ryousuke; Okuda, Hidehiko; Kurita, Kazunari

2018-06-01

We propose a fabrication process for silicon wafers by combining carbon-cluster ion implantation and room-temperature bonding for advanced CMOS image sensors. These carbon-cluster ions are made of carbon and hydrogen, which can passivate process-induced defects. We demonstrated that this combination process can be used to form an epitaxial layer on a carbon-cluster ion-implanted Czochralski (CZ)-grown silicon substrate with a high dose of 1 × 1016 atoms/cm2. This implantation condition transforms the top-surface region of the CZ-grown silicon substrate into a thin amorphous layer. Thus, an epitaxial layer cannot be grown on this implanted CZ-grown silicon substrate. However, this combination process can be used to form an epitaxial layer on the amorphous layer of this implanted CZ-grown silicon substrate surface. This bonding wafer has strong gettering capability in both the wafer-bonding region and the carbon-cluster ion-implanted projection range. Furthermore, this wafer inhibits oxygen out-diffusion to the epitaxial layer from the CZ-grown silicon substrate after device fabrication. Therefore, we believe that this bonding wafer is effective in decreasing the dark current and white-spot defect density for advanced CMOS image sensors.

Low temperature deposition of polycrystalline silicon thin films on a flexible polymer substrate by hot wire chemical vapor deposition

NASA Astrophysics Data System (ADS)

Lee, Sang-hoon; Jung, Jae-soo; Lee, Sung-soo; Lee, Sung-bo; Hwang, Nong-moon

2016-11-01

For the applications such as flexible displays and solar cells, the direct deposition of crystalline silicon films on a flexible polymer substrate has been a great issue. Here, we investigated the direct deposition of polycrystalline silicon films on a polyimide film at the substrate temperature of 200 °C. The low temperature deposition of crystalline silicon on a flexible substrate has been successfully made based on two ideas. One is that the Si-Cl-H system has a retrograde solubility of silicon in the gas phase near the substrate temperature. The other is the new concept of non-classical crystallization, where films grow by the building block of nanoparticles formed in the gas phase during hot-wire chemical vapor deposition (HWCVD). The total amount of precipitation of silicon nanoparticles decreased with increasing HCl concentration. By adding HCl, the amount and the size of silicon nanoparticles were reduced remarkably, which is related with the low temperature deposition of silicon films of highly crystalline fraction with a very thin amorphous incubation layer. The dark conductivity of the intrinsic film prepared at the flow rate ratio of RHCl=[HCl]/[SiH4]=3.61 was 1.84×10-6 Scm-1 at room temperature. The Hall mobility of the n-type silicon film prepared at RHCl=3.61 was 5.72 cm2 V-1s-1. These electrical properties of silicon films are high enough and could be used in flexible electric devices.

Silicon Carbide Etching Using Chlorine Trifluoride Gas

NASA Astrophysics Data System (ADS)

Habuka, Hitoshi; Oda, Satoko; Fukai, Yasushi; Fukae, Katsuya; Takeuchi, Takashi; Aihara, Masahiko

2005-03-01

The etch rate, chemical reactions and etched surface of β-silicon carbide are studied in detail using chlorine trifluoride gas. The etch rate is greater than 10 μm min-1 at 723 K with a flow rate of 0.1 \\ell min-1 at atmospheric pressure in a horizontal reactor. The maximum etch rate at a substrate temperature of 773 K is 40 μm min-1 with a flow rate of 0.25 \\ell min-1. The step-like pattern that initially exists on the β-silicon carbide surface tends to be smoothed; the root-mean-square surface roughness decreases from its initial value of 5 μm to 1 μm within 15 min; this minimum value is maintained for more than 15 min. Therefore, chlorine trifluoride gas is considered to have a large etch rate for β-silicon carbide associated with making a rough surface smooth.

Silicon nanowire photodetectors made by metal-assisted chemical etching

NASA Astrophysics Data System (ADS)

Xu, Ying; Ni, Chuan; Sarangan, Andrew

2016-09-01

Silicon nanowires have unique optical effects, and have potential applications in photodetectors. They can exhibit simple optical effects such as anti-reflection, but can also produce quantum confined effects. In this work, we have fabricated silicon photodetectors, and then post-processed them by etching nanowires on the incident surface. These nanowires were produced by a wet-chemical etching process known as the metal-assisted-chemical etching, abbreviated as MACE. N-type silicon substrates were doped by thermal diffusion from a solid ceramic source, followed by etching, patterning and contact metallization. The detectors were first tested for functionality and optical performance. The nanowires were then made by depositing an ultra-thin film of gold below its percolation thickness to produce an interconnected porous film. This was then used as a template to etch high aspect ratio nanowires into the face of the detectors with a HF:H2O2 mixture.

A MEMS Infrared Thermopile Fabricated from Silicon-On-Insulator with Phononic Crystal Structures and Carbon Nanotube Absorption Layer

NASA Astrophysics Data System (ADS)

Gray, Kory Forrest

The goal of this project was to examine the possibility of creating a novel thermal infrared detector based on silicon CMOS technology that has been enhanced by the latest nano-engineering discoveries. Silicon typically is not thought as an efficient thermoelectric material. However recent advancements in nanotechnology have improved the potential for a highly sensitive infrared detector based on nano-structured silicon. The thermal conductivity of silicon has been shown to be reduced from 150 W/mK down to 60 W/mK just by decreasing the scale of the silicon from bulk down to the sub-micron scale. Further reduction of the thermal conductivity has been shown by patterning silicon with a phonon crystal structure which has been reported to have thermal conductivities down to 10 W/mK. The phonon crystal structure consists of a 2D array of holes that are etched into the silicon. The size and pitch of the holes are on the order of the mean free path of the phonons in silicon which is approximately 200-500nm. This particular device had 200nm holes on a 400nm pitch. The Seebeck coefficient of silicon can also be enhanced by the reduction of the material from the bulk to sub-micron scale and with degenerate level doping. The combination of decreased thermal conductivity and increased Seebeck coefficient allow silicon to be a promising material for thermoelectric infrared detectors. The highly doped silicon is desired to reduce the electrical resistance of the device. The low electrical resistance is required to reduce the Johnson noise of the device which is the dominant noise source for most thermal detectors. This project designed a MEMS thermopile using a silicon-on-insulator substrate, and a CMOS compatible process. The basic thermopile consists of a silicon dioxide membrane with phononic crystal patterned silicon thermocouples around the edges of the membrane. Vertical aligned, multi-walled, carbon nanotubes were used as the infrared absorption layer. A MEMS thermoelectric detector with a D* of 3 * 107 cm Hz 0.5/W was demonstrated with a time response of 3-10 milliseconds. With this initial research, it is possible to improve the D* to the high 108 cm Hz 0.5/W range by slightly changing the design of the thermopile and patterning the absorption layer.

Visible-blind ultraviolet photodetectors on porous silicon carbide substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Naderi, N.; Hashim, M.R., E-mail: roslan@usm.my

2013-06-01

Highlights: • Highly reliable UV detectors are fabricated on porous silicon carbide substrates. • The optical properties of samples are enhanced by increasing the current density. • The optimized sample exhibits enhanced sensitivity to the incident UV radiation. - Abstract: Highly reliable visible-blind ultraviolet (UV) photodetectors were successfully fabricated on porous silicon carbide (PSC) substrates. High responsivity and high photoconductive gain were observed in a metal–semiconductor–metal ultraviolet photodetector that was fabricated on an optimized PSC substrate. The PSC samples were prepared via the UV-assisted photo-electrochemical etching of an n-type hexagonal silicon carbide (6H-SiC) substrate using different etching current densities. Themore » optical results showed that the current density is an outstanding etching parameter that controls the porosity and uniformity of PSC substrates. A highly porous substrate was synthesized using a suitable etching current density to enhance its light absorption, thereby improving the sensitivity of UV detector with this substrate. The electrical characteristics of fabricated devices on optimized PSC substrates exhibited enhanced sensitivity and responsivity to the incident radiation.« less

Laboratory studies of silicon vapor deposition, phase A. [feasibility of producing thin films for photovoltaic applications

NASA Technical Reports Server (NTRS)

Frost, R. T.; Racette, G. W.; Stockhoff, E. H.

1977-01-01

A system is described capable of carrying out silicon vapor deposition experiments in the low 10 to the minus 10th power torr vacuum range. The system was assembled and tested for use in a program aimed at exploration of vacuum heteroepitaxy of silicon on several substrates of potential interest for photovoltaic applications. An experiment is described in which a silicon layer 2.5 microns thick was deposited on a pyrolytically cleaned tungsten substrate held at a temperature of 400 C. Using a resistance heated silicon source, thicker layers can be deposited in periods of hours by utilizing closer source to substrate distances.

Highly stable, protein resistant thin films on SiC-modified silicon substrates.

PubMed

Qin, Guoting; Zhang, Rui; Makarenko, Boris; Kumar, Amit; Rabalais, Wayne; López Romero, J Manuel; Rico, Rodrigo; Cai, Chengzhi

2010-05-21

Thin films terminated with oligo(ethylene glycol) (OEG) could be photochemically grafted onto ultrathin silicon carbide layers that were generated on silicon substrates via carbonization with acetylene at 820 degrees C. The OEG coating reduced the non-specific adsorption of fibrinogen on the substrates by 99.5% and remained resistant after storage in PBS for 4 weeks at 37 degrees C.

Spalling of a Thin Si Layer by Electrodeposit-Assisted Stripping

NASA Astrophysics Data System (ADS)

Kwon, Youngim; Yang, Changyol; Yoon, Sang-Hwa; Um, Han-Don; Lee, Jung-Ho; Yoo, Bongyoung

2013-11-01

A major goal in solar cell research is to reduce the cost of the final module. Reducing the thickness of the crystalline silicon substrate to several tens of micrometers can reduce material costs. In this work, we describe the electrodeposition of a Ni-P alloy, which induces high stress in the silicon substrate at room temperature. The induced stress enables lift-off of the thin-film silicon substrate. After lift-off of the thin Si film, the mother substrate can be reused, reducing material costs. Moreover, the low-temperature process expected to be improved Si substrate quality.

Forming high efficiency silicon solar cells using density-graded anti-reflection surfaces

DOEpatents

Yuan, Hao-Chih; Branz, Howard M.; Page, Matthew R.

2014-09-09

A method (50) is provided for processing a graded-density AR silicon surface (14) to provide effective surface passivation. The method (50) includes positioning a substrate or wafer (12) with a silicon surface (14) in a reaction or processing chamber (42). The silicon surface (14) has been processed (52) to be an AR surface with a density gradient or region of black silicon. The method (50) continues with heating (54) the chamber (42) to a high temperature for both doping and surface passivation. The method (50) includes forming (58), with a dopant-containing precursor in contact with the silicon surface (14) of the substrate (12), an emitter junction (16) proximate to the silicon surface (14) by doping the substrate (12). The method (50) further includes, while the chamber is maintained at the high or raised temperature, forming (62) a passivation layer (19) on the graded-density silicon anti-reflection surface (14).

Forming high-efficiency silicon solar cells using density-graded anti-reflection surfaces

DOEpatents

Yuan, Hao-Chih; Branz, Howard M.; Page, Matthew R.

2015-07-07

A method (50) is provided for processing a graded-density AR silicon surface (14) to provide effective surface passivation. The method (50) includes positioning a substrate or wafer (12) with a silicon surface (14) in a reaction or processing chamber (42). The silicon surface (14) has been processed (52) to be an AR surface with a density gradient or region of black silicon. The method (50) continues with heating (54) the chamber (42) to a high temperature for both doping and surface passivation. The method (50) includes forming (58), with a dopant-containing precursor in contact with the silicon surface (14) of the substrate (12), an emitter junction (16) proximate to the silicon surface (14) by doping the substrate (12). The method (50) further includes, while the chamber is maintained at the high or raised temperature, forming (62) a passivation layer (19) on the graded-density silicon anti-reflection surface (14).

Macroscale Transformation Optics Enabled by Photoelectrochemical Etching.

PubMed

Barth, David S; Gladden, Christopher; Salandrino, Alessandro; O'Brien, Kevin; Ye, Ziliang; Mrejen, Michael; Wang, Yuan; Zhang, Xiang

2015-10-28

Photoelectrochemical etching of silicon can be used to form lateral refractive index gradients for transformation optical devices. This technique allows the fabrication of macroscale devices with large refractive index gradients. Patterned porous layers can also be lifted from the substrate and transferred to other materials, creating more possibilities for novel devices. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Nanoscale silicon substrate patterns from self-assembly of cylinder forming poly(styrene)-block-poly(dimethylsiloxane) block copolymer on silane functionalized surfaces.

PubMed

Borah, Dipu; Cummins, Cian; Rasappa, Sozaraj; Watson, Scott M D; Pike, Andrew R; Horrocks, Benjamin R; Fulton, David A; Houlton, Andrew; Liontos, George; Ntetsikas, Konstantinos; Avgeropoulos, Apostolos; Morris, Michael A

2017-01-27

Poly(styrene)-block-poly(dimethylsiloxane) (PS-b-PDMS) is an excellent block copolymer (BCP) system for self-assembly and inorganic template fabrication because of its high Flory-Huggins parameter (χ ∼ 0.26) at room temperature in comparison to other BCPs, and high selective etch contrast between PS and PDMS block for nanopatterning. In this work, self-assembly in PS-b-PDMS BCP is achieved by combining hydroxyl-terminated poly(dimethylsiloxane) (PDMS-OH) brush surfaces with solvent vapor annealing. As an alternative to standard brush chemistry, we report a simple method based on the use of surfaces functionalized with silane-based self-assembled monolayers (SAMs). A solution-based approach to SAM formation was adopted in this investigation. The influence of the SAM-modified surfaces upon BCP films was compared with polymer brush-based surfaces. The cylinder forming PS-b-PDMS BCP and PDMS-OH polymer brush were synthesized by sequential living anionic polymerization. It was observed that silane SAMs provided the appropriate surface chemistry which, when combined with solvent annealing, led to microphase segregation in the BCP. It was also demonstrated that orientation of the PDMS cylinders may be controlled by judicious choice of the appropriate silane. The PDMS patterns were successfully used as an on-chip etch mask to transfer the BCP pattern to underlying silicon substrate with sub-25 nm silicon nanoscale features. This alternative SAM/BCP approach to nanopattern formation shows promising results, pertinent in the field of nanotechnology, and with much potential for application, such as in the fabrication of nanoimprint lithography stamps, nanofluidic devices or in narrow and multilevel interconnected lines.

Nanoscale silicon substrate patterns from self-assembly of cylinder forming poly(styrene)-block-poly(dimethylsiloxane) block copolymer on silane functionalized surfaces

NASA Astrophysics Data System (ADS)

Borah, Dipu; Cummins, Cian; Rasappa, Sozaraj; Watson, Scott M. D.; Pike, Andrew R.; Horrocks, Benjamin R.; Fulton, David A.; Houlton, Andrew; Liontos, George; Ntetsikas, Konstantinos; Avgeropoulos, Apostolos; Morris, Michael A.

2017-01-01

Poly(styrene)-block-poly(dimethylsiloxane) (PS-b-PDMS) is an excellent block copolymer (BCP) system for self-assembly and inorganic template fabrication because of its high Flory-Huggins parameter (χ ˜ 0.26) at room temperature in comparison to other BCPs, and high selective etch contrast between PS and PDMS block for nanopatterning. In this work, self-assembly in PS-b-PDMS BCP is achieved by combining hydroxyl-terminated poly(dimethylsiloxane) (PDMS-OH) brush surfaces with solvent vapor annealing. As an alternative to standard brush chemistry, we report a simple method based on the use of surfaces functionalized with silane-based self-assembled monolayers (SAMs). A solution-based approach to SAM formation was adopted in this investigation. The influence of the SAM-modified surfaces upon BCP films was compared with polymer brush-based surfaces. The cylinder forming PS-b-PDMS BCP and PDMS-OH polymer brush were synthesized by sequential living anionic polymerization. It was observed that silane SAMs provided the appropriate surface chemistry which, when combined with solvent annealing, led to microphase segregation in the BCP. It was also demonstrated that orientation of the PDMS cylinders may be controlled by judicious choice of the appropriate silane. The PDMS patterns were successfully used as an on-chip etch mask to transfer the BCP pattern to underlying silicon substrate with sub-25 nm silicon nanoscale features. This alternative SAM/BCP approach to nanopattern formation shows promising results, pertinent in the field of nanotechnology, and with much potential for application, such as in the fabrication of nanoimprint lithography stamps, nanofluidic devices or in narrow and multilevel interconnected lines.

Germanium growth on electron beam lithography patterned Si3N4/Si(001) substrate using molecular beam epitaxy

NASA Astrophysics Data System (ADS)

Sarkar, Subhendu Sinha; Katiyar, Ajit K.; Sarkar, Arijit; Dhar, Achintya; Rudra, Arun; Khatri, Ravinder K.; Ray, Samit Kumar

2018-04-01

It is important to investigate the growth dynamics of Ge adatoms under different surface stress regimes of the patterned dielectric to control the selective growth of self-assembled Ge nanostructures on silicon. In the present work, we have studied the growth of Ge by molecular beam epitaxy on nanometer scale patterned Si3N4/Si(001) substrates generated using electron beam lithography. The pitch of the patterns has been varied to investigate its effect on the growth of Ge in comparison to un-patterned Si3N4. For the patterned Si3N4 film, Ge did not desorbed completely from the Si3N4 film and hence no site selective growth pattern is observed. Instead, depending upon the pitch, Ge growth has occurred in different growth modes around the openings in the Si3N4. For the un-patterned substrate, the morphology exhibits the occurrence of uniform 3D clustering of Ge adatoms on Si3N4 film. This variation in the growth modes of Ge is attributed to the variation of residual stress in the Si3N4 film for different pitch of holes, which has been confirmed theoretically through Comsol Multiphysics simulation. The variation in stress for different pitches resulted in modulation of surface energy of the Si3N4 film leading to the different growth modes of Ge.

Growth of carbon nanotubes by Fe-catalyzed chemical vapor processes on silicon-based substrates

NASA Astrophysics Data System (ADS)

Angelucci, Renato; Rizzoli, Rita; Vinciguerra, Vincenzo; Fortuna Bevilacqua, Maria; Guerri, Sergio; Corticelli, Franco; Passini, Mara

2007-03-01

In this paper, a site-selective catalytic chemical vapor deposition synthesis of carbon nanotubes on silicon-based substrates has been developed in order to get horizontally oriented nanotubes for field effect transistors and other electronic devices. Properly micro-fabricated silicon oxide and polysilicon structures have been used as substrates. Iron nanoparticles have been obtained both from a thin Fe film evaporated by e-gun and from iron nitrate solutions accurately dispersed on the substrates. Single-walled nanotubes with diameters as small as 1 nm, bridging polysilicon and silicon dioxide “pillars”, have been grown. The morphology and structure of CNTs have been characterized by SEM, AFM and Raman spectroscopy.

Process for depositing an oxide epitaxially onto a silicon substrate and structures prepared with the process

DOEpatents

McKee, Rodney A.; Walker, Frederick J.

1993-01-01

A process and structure involving a silicon substrate utilizes an ultra high vacuum and molecular beam epitaxy (MBE) methods to grow an epitaxial oxide film upon a surface of the substrate. As the film is grown, the lattice of the compound formed at the silicon interface becomes stabilized, and a base layer comprised of an oxide having a sodium chloride-type lattice structure grows epitaxially upon the compound so as to cover the substrate surface. A perovskite may then be grown epitaxially upon the base layer to render a product which incorporates silicon, with its electronic capabilities, with a perovskite having technologically-significant properties of its own.

New non-chemically amplified molecular resist design with switchable sensitivity for multi-lithography applications and nanopatterning

NASA Astrophysics Data System (ADS)

Thakur, Neha; Guruprasad Reddy, Pulikanti; Nandi, Santu; Yogesh, Midathala; Sharma, Satinder K.; Pradeep, Chullikkattil P.; Ghosh, Subrata; Gonsalves, Kenneth E.

2017-12-01

The development of new photoresist materials for multi-lithography applications is crucial but a challenging task for semiconductor industries. During the last few decades, given the need for new resists to meet the requirements of semiconductor industries, several research groups have developed different resist materials for specific lithography applications. In this context, we have successfully synthesized a new molecular non-chemically amplified resist (n-CAR) (C3) based on the functionalization of aromatic hydroxyl core (4,4‧-(9H-fluorene-9,9-diyl)diphenol) with radiation sensitive sulfonium triflates for various lithography applications. While, micron scale features have been developed using i-line (365 nm) and DUVL (254 nm) exposure tools, electron beam studies on C3 thin films enabled us to pattern 20 nm line features with L/3S (line/space) characteristics on the silicon substrate. The sensitivity and contrast were calculated from the contrast curve analysis as 280 µC cm-2 and 0.025 respectively. Being an important parameter for any newly developed resists, the line edge roughness (LER) of 30 nm (L/5S) features were calculated, using SUMMIT metrology package, to be 3.66  ±  0.3 nm and found to be within the acceptable range. AFM analysis further confirmed 20 nm line width with smooth pattern wall. No deformation of patterned features was observed during AFM analysis which indicated good adhesion property between patterned resists and silicon substrates.

The effect of concentration in the patterning of silica particles by the soft lithographic technique

NASA Astrophysics Data System (ADS)

Singh, Akanksha; Malek, Chantal Khan; Kulkarni, Sulabha K.

2008-12-01

Soft lithography provides remarkable surface patterning techniques to organize colloidal particles for a wide variety of applications. In particular, micromolding in capillaries (MIMIC) has emerged as a patterning method in the nanometer to micrometer scale in a single step by using templating and directing nanoparticles via capillary forces in the channel. The present work reports the results of the micropatterning of monodispersed silica particles of ~338 ± 2 nm size in ethanol medium, using MIMIC on silicon substrates. The effect of the concentration of silica particles on the patterning has been investigated. The patterns are well aligned and completely filled at 2 wt% concentration of silica particles.

Adhesion of single- and multi-walled carbon nanotubes to silicon substrate: atomistic simulations and continuum analysis

NASA Astrophysics Data System (ADS)

Yuan, Xuebo; Wang, Youshan

2017-10-01

The radial deformation of carbon nanotubes (CNTs) adhering to a substrate may prominently affect their mechanical and physical properties. In this study, both classical atomistic simulations and continuum analysis are carried out, to investigate the lateral adhesion of single-walled CNTs (SWCNTs) and multi-walled CNTs (MWCNTs) to a silicon substrate. A linear elastic model for analyzing the adhesion of 2D shells to a rigid semi-infinite substrate is constructed in the framework of continuum mechanics. Good agreement is achieved between the cross-section profiles of adhesive CNTs obtained by the continuum model and by the atomistic simulation approach. It is found that the adhesion of a CNT to the silicon substrate is significantly influenced by its initial diameter and the number of walls. CNTs with radius larger than a certain critical radius are deformed radially on the silicon substrate with flat contact regions. With increasing number of walls, the extent of radial deformation of a MWCNT on the substrate decreases dramatically, and the flat contact area reduces—and eventually vanishes—due to increasing equivalent bending stiffness. It is analytically predicted that large-diameter MWCNTs with a large number of walls are likely to ‘stand’ on the silicon substrate. The present work can be useful for understanding the radial deformation of CNTs adhering to a solid planar substrate.

Fabrication of polycrystalline solar cells on low-cost substrates

NASA Technical Reports Server (NTRS)

Chu, T. L. (Inventor)

1976-01-01

A new method of producing p-n junction semiconductors for solar cells was described; the principal objective of this investigation is to reduce production costs significantly by depositing polycrystalline silicon on a relatively cheap substrate such as metallurgical-grade silicon, graphite, or steel. The silicon layer contains appropriate dopants, and the substrates are coated with a diffusion barrier of silica, borosilicate, phosphosilicate, or mixtures of these compounds.

Porous Silicon Covered with Silver Nanoparticles as Surface-Enhanced Raman Scattering (SERS) Substrate for Ultra-Low Concentration Detection.

PubMed

Kosović, Marin; Balarin, Maja; Ivanda, Mile; Đerek, Vedran; Marciuš, Marijan; Ristić, Mira; Gamulin, Ozren

2015-12-01

Microporous and macro-mesoporous silicon templates for surface-enhanced Raman scattering (SERS) substrates were produced by anodization of low doped p-type silicon wafers. By immersion plating in AgNO3, the templates were covered with silver metallic film consisting of different silver nanostructures. Scanning electron microscopy (SEM) micrographs of these SERS substrates showed diverse morphology with significant difference in an average size and size distribution of silver nanoparticles. Ultraviolet-visible-near-infrared (UV-Vis-NIR) reflection spectroscopy showed plasmonic absorption at 398 and 469 nm, which is in accordance with the SEM findings. The activity of the SERS substrates was tested using rhodamine 6G (R6G) dye molecules and 514.5 nm laser excitation. Contrary to the microporous silicon template, the SERS substrate prepared from macro-mesoporous silicon template showed significantly broader size distribution of irregular silver nanoparticles as well as localized surface plasmon resonance closer to excitation laser wavelength. Such silver morphology has high SERS sensitivity that enables ultralow concentration detection of R6G dye molecules up to 10(-15) M. To our knowledge, this is the lowest concentration detected of R6G dye molecules on porous silicon-based SERS substrates, which might even indicate possible single molecule detection.

Studies of silicon quantum dots prepared at different substrate temperatures

NASA Astrophysics Data System (ADS)

Al-Agel, Faisal A.; Suleiman, Jamal; Khan, Shamshad A.

2017-03-01

In this research work, we have synthesized silicon quantum dots at different substrate temperatures 193, 153 and 123 K at a fixed working pressure 5 Torr. of Argon gas. The structural studies of these silicon quantum dots have been undertaken using X-ray diffraction, Field Emission Scanning Electron Microscopy (FESEM) and High Resolution Transmission Electron Microscopy (HRTEM). The optical and electrical properties have been studied using UV-visible spectroscopy, Fourier transform infrared (FTIR) spectroscopy, Fluorescence spectroscopy and I-V measurement system. X-ray diffraction pattern of Si quantum dots prepared at different temperatures show the amorphous nature except for the quantum dots synthesized at 193 K which shows polycrystalline nature. FESEM images of samples suggest that the size of quantum dots varies from 2 to 8 nm. On the basis of UV-visible spectroscopy measurements, a direct band gap has been observed for Si quantum dots. FTIR spectra suggest that as-grown Si quantum dots are partially oxidized which is due exposure of as-prepared samples to air after taking out from the chamber. PL spectra of the synthesized silicon quantum dots show an intense peak at 444 nm, which may be attributed to the formation of Si quantum dots. Temperature dependence of dc conductivity suggests that the dc conductivity enhances exponentially by raising the temperature. On the basis above properties i.e. direct band gap, high absorption coefficient and high conductivity, these silicon quantum dots will be useful for the fabrication of solar cells.

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor); Zheng, Xinyu (Inventor)

2002-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

NASA Technical Reports Server (NTRS)

Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

2005-01-01

Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

Increased voltage photovoltaic cell

NASA Technical Reports Server (NTRS)

Ross, B.; Bickler, D. B.; Gallagher, B. D. (Inventor)

1985-01-01

A photovoltaic cell, such as a solar cell, is provided which has a higher output voltage than prior cells. The improved cell includes a substrate of doped silicon, a first layer of silicon disposed on the substrate and having opposite doping, and a second layer of silicon carbide disposed on the first layer. The silicon carbide preferably has the same type of doping as the first layer.

Molybdenum enhanced low-temperature deposition of crystalline silicon nitride

DOEpatents

Lowden, Richard A.

1994-01-01

A process for chemical vapor deposition of crystalline silicon nitride which comprises the steps of: introducing a mixture of a silicon source, a molybdenum source, a nitrogen source, and a hydrogen source into a vessel containing a suitable substrate; and thermally decomposing the mixture to deposit onto the substrate a coating comprising crystalline silicon nitride containing a dispersion of molybdenum silicide.

Dislocation-free strained silicon-on-silicon by in-place bonding

NASA Astrophysics Data System (ADS)

Cohen, G. M.; Mooney, P. M.; Paruchuri, V. K.; Hovel, H. J.

2005-06-01

In-place bonding is a technique where silicon-on-insulator (SOI) slabs are bonded by hydrophobic attraction to the underlying silicon substrate when the buried oxide is undercut in dilute HF. The bonding between the exposed surfaces of the SOI slab and the substrate propagates simultaneously with the buried oxide etching. As a result, the slabs maintain their registration and are referred to as "bonded in-place". We report the fabrication of dislocation-free strained silicon slabs from pseudomorphic trilayer Si/SiGe/SOI by in-place bonding. Removal of the buried oxide allows the compressively strained SiGe film to relax elastically and induce tensile strain in the top and bottom silicon films. The slabs remain bonded to the substrate by van der Waals forces when the wafer is dried. Subsequent annealing forms a covalent bond such that when the upper Si and the SiGe layer are removed, the bonded silicon slab remains strained.

Nanotechnology in Science and Art

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bearinger, J

2007-02-21

The burgeoning field of nanotechnology opens windows between science and art. Exploration of this interplay encourages interaction between scientists, artists and educators alike. The image below serves as an example of the fertile ground for exchange. The substrate that this image captures is made of silicon, the material from which computer chips are made. A thin ({approx}1 nm thick) chemical coating was applied homogeneously to the silicon. Specific regions of the coating, 600 nm wide (approximately 150 times smaller than the diameter of a human hair), were then locally removed from the silicon via photocatalytic nanolithography (PCNL(Bearinger, Hiddessen et al.more » 2005)). PCNL engages light, such as from a light emitting diode or an ultraviolet source, to activate molecules that are attached to a transparent mask above the silicon substrate. These molecules can be compounds similar to chlorophyll, the photoactive material that aids plants in photosynthesis, or may be semiconductor materials, such as TiO{sub 2}. Once these molecules are activated, chemical reactions result in local destruction of the coating on the silicon. Thus, only regions of the coated silicon in close contact with mask are affected. A non-fouling polymer hydrogel ({approx}10 nm thick) was then grafted to the retained coating. Hydrogels are superabsorbent and are therefore used on the bulk scale in common items including contact lenses and diapers. They also find utility in topical drug delivery and tissue engineering applications. Because the hydrogel is so absorbent, exposing the silicon chip with patterned hydrogel to water vapor from one's breath reveals the pattern that the lithography dictates(Lopez, Biebuyck et al. 1993). The myriad of colors seen in the image are due to optical interference. The thickness of the swollen layer determines the colors that are visible. While the field of view immediately following hydration appears like a big drop of oil shining in the sun, the oil drop appearance breaks up into many small domains as the water vapor evaporates. The base silicon does not retain the water in the same way that the way the hydrogel does, due to differences in surface tension. Thus, the pattern stands out from the background. In addition to bringing together nanotechnology, polymer chemistry, materials science and optics, this image suggests imposing order to an otherwise chaotic world. This is a repeated theme in nature across multiple orders of magnitude. The interface of this order and chaos is amorphous, and render a Klimt-like vision of reflected light. As this image is just a still in time, it also reminds us that all things and states are transient and that the materials of the earth, just as we individuals, are constantly evolving.« less

Optimization of imprintable nanostructured a-Si solar cells: FDTD study.

PubMed

Fisker, Christian; Pedersen, Thomas Garm

2013-03-11

We present a finite-difference time-domain (FDTD) study of an amorphous silicon (a-Si) thin film solar cell, with nano scale patterns on the substrate surface. The patterns, based on the geometry of anisotropically etched silicon gratings, are optimized with respect to the period and anti-reflection (AR) coating thickness for maximal absorption in the range of the solar spectrum. The structure is shown to increase the cell efficiency by 10.2% compared to a similar flat solar cell with an optimized AR coating thickness. An increased back reflection can be obtained with a 50 nm zinc oxide layer on the back reflector, which gives an additional efficiency increase, leading to a total of 14.9%. In addition, the patterned cells are shown to be up to 3.8% more efficient than an optimized textured reference cell based on the Asahi U-type glass surface. The effects of variations of the optimized solar cell structure due to the manufacturing process are investigated, and shown to be negligible for variations below ±10%.

Method of deposition of silicon carbide layers on substrates

DOEpatents

Angelini, P.; DeVore, C.E.; Lackey, W.J.; Blanco, R.E.; Stinton, D.P.

1982-03-19

A method for direct chemical vapor deposition of silicon carbide to substrates, especially nuclear waste particles, is provided by the thermal decomposition of methylsilane at 800 to 1050/sup 0/C when the substrates have been confined within a suitable coating environment.

Evaluation of substrate noise suppression method to mitigate crosstalk among trough-silicon vias

NASA Astrophysics Data System (ADS)

Araga, Yuuki; Kikuchi, Katsuya; Aoyagi, Masahiro

2018-04-01

Substrate noise from a single through-silicon via (TSV) and the noise attenuation by a substrate tap and a guard ring are clarified. A CMOS test vehicle is designed, and 6-µm-diameter TSVs are manufactured on a 20-µm-thick silicon substrate by the via-last method. An on-chip waveform-capturing circuitry is embedded in the test vehicle to capture transient waveforms of substrate noise. The embedded waveform-capturing circuitry demonstrates small and local noise propagation. Experimental results show increased substrate noise level induced by TSVs and the effectiveness of the substrate tap and guard ring for mitigating the crosstalk among TSVs. An analytical model to explain substrate noise propagation is developed to validate experimental results. Results obtained using the substrate model with a multilayer mesh shows good consistency with experimental results, indicating that the model can be used for examination of noise suppression methods.

Light-Induced Buckles Localized by Polymeric Inks Printed on Bilayer Films.

PubMed

Park, Sungjune; Nallainathan, Umaash; Mondal, Kunal; Sen, Pratik; Dickey, Michael D

2018-04-16

Buckling instabilities generate microscale features in thin films in a facile manner. Buckles can form, for example, by heating a metal/polymer film stack on a rigid substrate. Thermal expansion differences of the individual layers generate compressive stress that causes the metal to buckle over the entire surface. The ability to dictate and confine the location of buckle formation can enable patterns with more than one length scale, including hierarchical patterns. Here, sacrificial "ink" patterned on top of the film stack localizes the buckles via two mechanisms. First, stiff inks suppress buckles such that only the non-inked regions buckle in response to infrared light. The metal in the non-inked regions absorbs the infrared light and thus gets sufficiently hot to induce buckles. Second, soft inks that absorb light get hot faster than the non-inked regions and promote buckling when exposed to visible light. The exposed metal in the non-inked regions reflects the light and thus never get sufficiently hot to induce buckles. This second method works on glass substrates, but not silicon substrates, due to the superior thermal insulation of glass. The patterned ink can be removed, leaving behind hierarchical patterns consisting of regions of buckles among non-buckled regions. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Flexible MEMS: A novel technology to fabricate flexible sensors and electronics

NASA Astrophysics Data System (ADS)

Tu, Hongen

This dissertation presents the design and fabrication techniques used to fabricate flexible MEMS (Micro Electro Mechanical Systems) devices. MEMS devices and CMOS(Complementary Metal-Oxide-Semiconductor) circuits are traditionally fabricated on rigid substrates with inorganic semiconductor materials such as Silicon. However, it is highly desirable that functional elements like sensors, actuators or micro fluidic components to be fabricated on flexible substrates for a wide variety of applications. Due to the fact that flexible substrate is temperature sensitive, typically only low temperature materials, such as polymers, metals, and organic semiconductor materials, can be directly fabricated on flexible substrates. A novel technology based on XeF2(xenon difluoride) isotropic silicon etching and parylene conformal coating, which is able to monolithically incorporate high temperature materials and fluidic channels, was developed at Wayne State University. The technology was first implemented in the development of out-of-plane parylene microneedle arrays that can be individually addressed by integrated flexible micro-channels. These devices enable the delivery of chemicals with controlled temporal and spatial patterns and allow us to study neurotransmitter-based retinal prosthesis. The technology was further explored by adopting the conventional SOI-CMOS processes. High performance and high density CMOS circuits can be first fabricated on SOI wafers, and then be integrated into flexible substrates. Flexible p-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect-Transistors) were successfully integrated and tested. Integration of pressure sensors and flow sensors based on single crystal silicon has also been demonstrated. A novel smart yarn technology that enables the invisible integration of sensors and electronics into fabrics has been developed. The most significant advantage of this technology is its post-MEMS and post-CMOS compatibility. Various high-performance MEMS devices and electronics can be integrated into flexible substrates. The potential of our technology is enormous. Many wearable and implantable devices can be developed based on this technology.

Molybdenum enhanced low-temperature deposition of crystalline silicon nitride

DOEpatents

Lowden, R.A.

1994-04-05

A process for chemical vapor deposition of crystalline silicon nitride is described which comprises the steps of: introducing a mixture of a silicon source, a molybdenum source, a nitrogen source, and a hydrogen source into a vessel containing a suitable substrate; and thermally decomposing the mixture to deposit onto the substrate a coating comprising crystalline silicon nitride containing a dispersion of molybdenum silicide. 5 figures.

Electron Beam "Writes" Silicon On Sapphire

NASA Technical Reports Server (NTRS)

Heinemann, Klaus

1988-01-01

Method of growing silicon on sapphire substrate uses beam of electrons to aid growth of semiconductor material. Silicon forms as epitaxial film in precisely localized areas in micron-wide lines. Promising fabrication method for fast, densely-packed integrated circuits. Silicon deposited preferentially in contaminated substrate zones and in clean zone irradiated by electron beam. Electron beam, like surface contamination, appears to stimulate decomposition of silane atmosphere.

Polycrystalline silicon thin-film transistors fabricated by Joule-heating-induced crystallization

NASA Astrophysics Data System (ADS)

Hong, Won-Eui; Ro, Jae-Sang

2015-01-01

Joule-heating-induced crystallization (JIC) of amorphous silicon (a-Si) films is carried out by applying an electric pulse to a conductive layer located beneath or above the films. Crystallization occurs across the whole substrate surface within few tens of microseconds. Arc instability, however, is observed during crystallization, and is attributed to dielectric breakdown in the conductor/insulator/transformed polycrystalline silicon (poly-Si) sandwich structures at high temperatures during electrical pulsing for crystallization. In this study, we devised a method for the crystallization of a-Si films while preventing arc generation; this method consisted of pre-patterning an a-Si active layer into islands and then depositing a gate oxide and gate electrode. Electric pulsing was then applied to the gate electrode formed using a Mo layer. The Mo layer was used as a Joule-heat source for the crystallization of pre-patterned active islands of a-Si films. JIC-processed poly-Si thin-film transistors (TFTs) were fabricated successfully, and the proposed method was found to be compatible with the standard processing of coplanar top-gate poly-Si TFTs.

Spectroellipsometric detection of silicon substrate damage caused by radiofrequency sputtering of niobium oxide

NASA Astrophysics Data System (ADS)

Lohner, Tivadar; Serényi, Miklós; Szilágyi, Edit; Zolnai, Zsolt; Czigány, Zsolt; Khánh, Nguyen Quoc; Petrik, Péter; Fried, Miklós

2017-11-01

Substrate surface damage induced by deposition of metal atoms by radiofrequency (rf) sputtering or ion beam sputtering onto single-crystalline silicon (c-Si) surface has been characterized earlier by electrical measurements. The question arises whether it is possible to characterize surface damage using spectroscopic ellipsometry (SE). In our experiments niobium oxide layers were deposited by rf sputtering on c-Si substrates in gas mixture of oxygen and argon. Multiple angle of incidence spectroscopic ellipsometry measurements were performed, a four-layer optical model (surface roughness layer, niobium oxide layer, native silicon oxide layer and ion implantation-amorphized silicon [i-a-Si] layer on a c-Si substrate) was created in order to evaluate the spectra. The evaluations yielded thicknesses of several nm for the i-a-Si layer. Better agreement could be achieved between the measured and the generated spectra by inserting a mixed layer (with components of c-Si and i-a-Si applying the effective medium approximation) between the silicon oxide layer and the c-Si substrate. High depth resolution Rutherford backscattering (RBS) measurements were performed to investigate the interface disorder between the deposited niobium oxide layer and the c-Si substrate. Atomic resolution cross-sectional transmission electron microscopy investigation was applied to visualize the details of the damaged subsurface region of the substrate.

Impact of the silicon substrate resistivity and growth condition on the deep levels in Ni-Au/AlN/Si MIS Capacitors

NASA Astrophysics Data System (ADS)

Wang, Chong; Simoen, Eddy; Zhao, Ming; Li, Wei

2017-10-01

Deep levels formed under different growth conditions of a 200 nm AlN buffer layer on B-doped Czochralski Si(111) substrates with different resistivity were investigated by deep-level transient spectroscopy (DLTS) on metal-insulator-semiconductor capacitors. Growth-temperature-dependent Al diffusion in the Si substrate was derived from the free carrier density obtained by capacitance-voltage measurement on samples grown on p- substrates. The DLTS spectra revealed a high concentration of point and extended defects in the p- and p+ silicon substrates, respectively. This indicated a difference in the electrically active defects in the silicon substrate close to the AlN/Si interface, depending on the B doping concentration.

Fabrication of Highly Ordered Anodic Aluminium Oxide Templates on Silicon Substrates

DTIC Science & Technology

2007-01-01

highly ordered anodic aluminium oxide ( AAO ) templates of unprecedented pore uniformity directly on Si, enabled by new advances on two fronts – direct...field emitter, sensors, oscillators and photodetectors. 15. SUBJECT TERMS Anodic aluminum oxide , template-assisted nanofabrication, carbon nanotube...Fabrication of the aligned and patterned carbon nanotube field emitters using the anodic aluminum oxide nano-template on a Si wafer’, Synth. Met

Multi-Channel Electronically Scanned Cryogenic Pressure Sensor And Method For Making Same

NASA Technical Reports Server (NTRS)

Chapman, John J. (Inventor); Hopson, Purnell, Jr. (Inventor); Holloway, Nancy M. (Inventor)

2001-01-01

A miniature, multi-channel, electronically scanned pressure measuring device uses electrostatically bonded silicon dies in a multi-element array. These dies are bonded at specific sites on a glass, pre-patterned substrate. Thermal data is multiplexed and recorded on each individual pressure measuring diaphragm. The device functions in a cryogenic environment without the need of heaters to keep the sensor at constant temperatures.

Optimization of solar cells for air mass zero operation and a study of solar cells at high temperatures

NASA Technical Reports Server (NTRS)

Hovel, H. J.; Vernon, S. M.

1982-01-01

The power to weight ratio of GaAs cells can be reduced by fabricating devices using thin GaAs films on low density substrate materials (silicon, glass, plastics). A graphoepitaxy technique was developed which uses fine geometric patterns in the substrate to affect growth. Initial substrates were processed by etching 25 microns deep grooves into 100 oriented wafers; fine-grained polycrystalline GaAs layers 25-50 microns thick were then deposited on these and recrystallization was performed, heating the substrates to above the GaAs melting point in ASH3 atmosphere, resulting in large grain regrowth oriented along the groove dimensions. Experiments with smaller groove depths and spacings were initially encouraging; single large GaAs grains would totally cover one and often two groove fields of 14 groove each spanning several hundred microns. Dielectric coatings on the grooved substrates were also used to modify the growth.

Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies

DOEpatents

Blewer, Robert S.; Gullinger, Terry R.; Kelly, Michael J.; Tsao, Sylvia S.

1991-01-01

A method of forming a multiple level porous silicon substrate for semiconductor integrated circuits including anodizing non-porous silicon layers of a multi-layer silicon substrate to form multiple levels of porous silicon. At least one porous silicon layer is then oxidized to form an insulating layer and at least one other layer of porous silicon beneath the insulating layer is metallized to form a buried conductive layer. Preferably the insulating layer and conductive layer are separated by an anodization barrier formed of non-porous silicon. By etching through the anodization barrier and subsequently forming a metallized conductive layer, a fully or partially insulated buried conductor may be fabricated under single crystal silicon.

Purified silicon production system

DOEpatents

Wang, Tihu; Ciszek, Theodore F.

2004-03-30

Method and apparatus for producing purified bulk silicon from highly impure metallurgical-grade silicon source material at atmospheric pressure. Method involves: (1) initially reacting iodine and metallurgical-grade silicon to create silicon tetraiodide and impurity iodide byproducts in a cold-wall reactor chamber; (2) isolating silicon tetraiodide from the impurity iodide byproducts and purifying it by distillation in a distillation chamber; and (3) transferring the purified silicon tetraiodide back to the cold-wall reactor chamber, reacting it with additional iodine and metallurgical-grade silicon to produce silicon diiodide and depositing the silicon diiodide onto a substrate within the cold-wall reactor chamber. The two chambers are at atmospheric pressure and the system is open to allow the introduction of additional source material and to remove and replace finished substrates.

Submillimeter-wave antennas on thin membranes

NASA Technical Reports Server (NTRS)

Rebeiz, Gabriel M.; Regehr, Wade G.; Rutledge, David B.; Savage, Richard L.; Luhmann, Neville C., Jr.

1987-01-01

Submillimeter-wave antennas have been fabricated on 1-micron thick silicon-oxynitride membranes. This approach results in better patterns than previous lens-coupled antennas, and eliminates the dielectric loss associated with the substrate lens. Measurements on a wideband log-periodic antenna at 700 GHz, 370 GHz and 167 GHz show no sidelobes and 3-dB beamwidths between 40 and 60 deg. A linear imaging array has similar patterns at 700 GHz. Possible applications for membrane antennas include wideband superconducting tunnel-junction receivers for radio astronomy and imaging arrays for radiometry and plasma diagnostics.

Dip coating process: Silicon sheet growth development for the large-area silicon sheet task of the low-cost silicon solar array project

NASA Technical Reports Server (NTRS)

Heaps, J. D.; Maciolek, R. B.; Harrison, W. B.; Wolner, H. A.; Hendrickson, G.; Nelson, L. D.

1976-01-01

To date, an experimental dip-coating facility was constructed. Using this facility, relatively thin (1 mm) mullite and alumina substrates were successfully dip-coated with 2.5 - 3.0 ohm-cm, p-type silicon with areas of approximately 20 sq cm. The thickness and grain size of these coatings are influenced by the temperature of the melt and the rate at which the substrate is pulled from the melt. One mullite substrate had dendrite-like crystallites of the order of 1 mm wide and 1 to 2 cm long. Their axes were aligned along the direction of pulling. A large variety of substrate materials were purchased or developed enabling the program to commence a substrate definition evaluation. Due to the insulating nature of the substrate, the bottom layer of the p-n junction may have to be made via the top surface. The feasibility of accomplishing this was demonstrated using single crystal wafers.

Silicon carbide thyristor

NASA Technical Reports Server (NTRS)

Edmond, John A. (Inventor); Palmour, John W. (Inventor)

1996-01-01

The SiC thyristor has a substrate, an anode, a drift region, a gate, and a cathode. The substrate, the anode, the drift region, the gate, and the cathode are each preferably formed of silicon carbide. The substrate is formed of silicon carbide having one conductivity type and the anode or the cathode, depending on the embodiment, is formed adjacent the substrate and has the same conductivity type as the substrate. A drift region of silicon carbide is formed adjacent the anode or cathode and has an opposite conductivity type as the anode or cathode. A gate is formed adjacent the drift region or the cathode, also depending on the embodiment, and has an opposite conductivity type as the drift region or the cathode. An anode or cathode, again depending on the embodiment, is formed adjacent the gate or drift region and has an opposite conductivity type than the gate.

Bidisperse silica nanoparticles close-packed monolayer on silicon substrate by three step spin method

NASA Astrophysics Data System (ADS)

Khanna, Sakshum; Marathey, Priyanka; Utsav, Chaliawala, Harsh; Mukhopadhyay, Indrajit

2018-05-01

We present the studies on the structural properties of monolayer Bidisperse silica (SiO2) nanoparticles (BDS) on Silicon (Si-100) substrate using spin coating technique. The Bidisperse silica nanoparticle was synthesised by the modified sol-gel process. Nanoparticles on the substrate are generally assembled in non-close/close-packed monolayer (CPM) form. The CPM form is obtained by depositing the colloidal suspension onto the silicon substrate using complex techniques. Here we report an effective method for forming a monolayer of bidisperse silica nanoparticle by three step spin coating technique. The samples were prepared by mixing the monodisperse solutions of different particles size 40 and 100 nm diameters. The bidisperse silica nanoparticles were self-assembled on the silicon substrate forming a close-packed monolayer film. The scanning electron microscope images of bidisperse films provided in-depth film structure of the film. The maximum surface coverage obtained was around 70-80%.

Fabrication of novel plasmonics-active substrates

NASA Astrophysics Data System (ADS)

Dhawan, Anuj; Gerhold, Michael; Du, Yan; Misra, Veena; Vo-Dinh, Tuan

2009-02-01

This paper describes methodologies for fabricating of highly efficient plasmonics-active SERS substrates - having metallic nanowire structures with pointed geometries and sub-5 nm gap between the metallic nanowires enabling concentration of high EM fields in these regions - on a wafer-scale by a reproducible process that is compatible with large-scale development of these substrates. Excitation of surface plasmons in these nanowire structures leads to substantial enhancement in the Raman scattering signal obtained from molecules lying in the vicinity of the nanostructure surface. The methodologies employed included metallic coating of silicon nanowires fabricated by employing deep UV lithography as well as controlled growth of silicon germanium on silicon nanostructures to form diamond-shaped nanowire structures followed by metallic coating. These SERS substrates were employed for detecting chemical and biological molecules of interest. In order to characterize the SERS substrates developed in this work, we obtained SERS signals from molecules such as p-mercaptobenzoic acid (pMBA) and cresyl fast violet (CFV) attached to or adsorbed on the metal-coated SERS substrates. It was observed that both gold-coated triangular shaped nanowire substrates as well as gold-coated diamond shaped nanowire substrates provided very high SERS signals for the nanowires having sub-15 nm gaps and that the SERS signal depends on the closest spacing between the metal-coated silicon and silicon germanium nanowires. SERS substrates developed by the different processes were also employed for detection of biological molecules such as DPA (Dipicolinic Acid), an excellent marker for spores of bacteria such as Anthrax.

Crystalline silicon growth in nickel/a-silicon bilayer

NASA Astrophysics Data System (ADS)

Mohiddon, Md Ahamad; Naidu, K. Lakshun; Dalba, G.; Rocca, F.; Krishna, M. Ghanashyam

2013-02-01

The effect of substrate temperature on amorphous Silicon crystallization, mediated by metal impurity is reported. Bilayers of Ni(200nm)/Si(400nm) are deposited on fused silica substrate by electron beam evaporator at 200 and 500 °C. Raman mapping shows that, 2 to 5 micron size crystalline silicon clusters are distributed over the entire surface of the sample. X-ray diffraction and X-ray absorption spectroscopy studies demonstrate silicon crystallizes over the metal silicide seeds and grow with the annealing temperature.

Solar cell with silicon oxynitride dielectric layer

DOEpatents

Shepherd, Michael; Smith, David D

2015-04-28

Solar cells with silicon oxynitride dielectric layers and methods of forming silicon oxynitride dielectric layers for solar cell fabrication are described. For example, an emitter region of a solar cell includes a portion of a substrate having a back surface opposite a light receiving surface. A silicon oxynitride (SiO.sub.xN.sub.y, 0

Fabrication of heterojunction solar cells by improved tin oxide deposition on insulating layer

DOEpatents

Feng, Tom; Ghosh, Amal K.

1980-01-01

Highly efficient tin oxide-silicon heterojunction solar cells are prepared by heating a silicon substrate, having an insulating layer thereon, to provide a substrate temperature in the range of about 300.degree. C. to about 400.degree. C. and thereafter spraying the so-heated substrate with a solution of tin tetrachloride in a organic ester boiling below about 250.degree. C. Preferably the insulating layer is naturally grown silicon oxide layer.

Direct Growth of Graphene on Silicon by Metal-Free Chemical Vapor Deposition

NASA Astrophysics Data System (ADS)

Tai, Lixuan; Zhu, Daming; Liu, Xing; Yang, Tieying; Wang, Lei; Wang, Rui; Jiang, Sheng; Chen, Zhenhua; Xu, Zhongmin; Li, Xiaolong

2018-06-01

The metal-free synthesis of graphene on single-crystal silicon substrates, the most common commercial semiconductor, is of paramount significance for many technological applications. In this work, we report the growth of graphene directly on an upside-down placed, single-crystal silicon substrate using metal-free, ambient-pressure chemical vapor deposition. By controlling the growth temperature, in-plane propagation, edge-propagation, and core-propagation, the process of graphene growth on silicon can be identified. This process produces atomically flat monolayer or bilayer graphene domains, concave bilayer graphene domains, and bulging few-layer graphene domains. This work would be a significant step toward the synthesis of large-area and layer-controlled, high-quality graphene on single-crystal silicon substrates. [Figure not available: see fulltext.

Methods of repairing a substrate

NASA Technical Reports Server (NTRS)

Riedell, James A. (Inventor); Easler, Timothy E. (Inventor)

2011-01-01

A precursor of a ceramic adhesive suitable for use in a vacuum, thermal, and microgravity environment. The precursor of the ceramic adhesive includes a silicon-based, preceramic polymer and at least one ceramic powder selected from the group consisting of aluminum oxide, aluminum nitride, boron carbide, boron oxide, boron nitride, hafnium boride, hafnium carbide, hafnium oxide, lithium aluminate, molybdenum silicide, niobium carbide, niobium nitride, silicon boride, silicon carbide, silicon oxide, silicon nitride, tin oxide, tantalum boride, tantalum carbide, tantalum oxide, tantalum nitride, titanium boride, titanium carbide, titanium oxide, titanium nitride, yttrium oxide, zirconium boride, zirconium carbide, zirconium oxide, and zirconium silicate. Methods of forming the ceramic adhesive and of repairing a substrate in a vacuum and microgravity environment are also disclosed, as is a substrate repaired with the ceramic adhesive.

Method for deposition of a conductor in integrated circuits

DOEpatents

Creighton, J. Randall; Dominguez, Frank; Johnson, A. Wayne; Omstead, Thomas R.

1997-01-01

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten.

Structural, Optical and Electrical Properties of ZnS/Porous Silicon Heterostructures

NASA Astrophysics Data System (ADS)

Wang, Cai-Feng; Li, Qing-Shan; Lv, Lei; Zhang, Li-Chun; Qi, Hong-Xia; Chen, Hou

2007-03-01

ZnS films are deposited by pulsed laser deposition on porous silicon (PS) substrates formed by electrochemical anodization of p-type (100) silicon wafer. Scanning electron microscope images reveal that the surface of ZnS films is unsmoothed, and there are some cracks in the ZnS films due to the roughness of the PS surface. The x-ray diffraction patterns show that the ZnS films on PS surface are grown in preferring orientation along cubic phase β-ZnS (111) direction. White light emission is obtained by combining the blue-green emission from ZnS films with the orange-red emission from PS layers. Based on the I-V characteristic, the ZnS/PS heterojunction exhibits the rectifying junction behaviour, and an ideality factor n is calculated to be 77 from the I-V plot.

YBa2Cu307 superconducting microbolometer linear arrays

NASA Astrophysics Data System (ADS)

Johnson, Burgess R.; Ohnstein, Thomas R.; Marsh, Holly A.; Dunham, Scott B.; Kruse, Paul W.

1992-09-01

Single pixels and linear arrays of microbolometers employing the high-T(subscript c) superconductor YBa(subscript 2)Cu(subscript 3)O(subscript 7) have been fabricated by silicon micromachining techniques. The substrates are 3 in. diameter silicon wafers upon which buffer layers of Si(subscript 3)N(subscript 4) and yttria-stabilized zirconia (YSZ) have been deposited. The YBa(subscript 2)Cu(subscript 3)O(subscript 7) was deposited by ion beam sputtering upon the yttria-stabilized zirconia (YSZ), then photolithographically patterned into serpentines 4 micrometers wide. Anisotropic etching in KOH removed the silicon underlying each pixel, thereby providing the necessary thermal isolation. When operated at 70 degree(s)K with 1 (mu) A dc bias, the D(superscript *) is 7.5 X 10(superscript 8) cm Hz(superscript 1/2)/Watt with a thermal response time of 24 msec.

Method of deposition of silicon carbide layers on substrates and product

DOEpatents

Angelini, Peter; DeVore, Charles E.; Lackey, Walter J.; Blanco, Raymond E.; Stinton, David P.

1984-01-01

A method for direct chemical vapor deposition of silicon carbide to substrates, especially nuclear waste particles, is provided by the thermal decomposition of methylsilane at about 800.degree. C. to 1050.degree. C. when the substrates have been confined within a suitable coating environment.

Etching process for improving the strength of a laser-machined silicon-based ceramic article

DOEpatents

Copley, Stephen M.; Tao, Hongyi; Todd-Copley, Judith A.

1991-01-01

A process for improving the strength of laser-machined articles formed of a silicon-based ceramic material such as silicon nitride, in which the laser-machined surface is immersed in an etching solution of hydrofluoric acid and nitric acid for a duration sufficient to remove substantially all of a silicon film residue on the surface but insufficient to allow the solution to unduly attack the grain boundaries of the underlying silicon nitride substrate. This effectively removes the silicon film as a source of cracks that otherwise could propagate downwardly into the silicon nitride substrate and significantly reduce its strength.

Etching process for improving the strength of a laser-machined silicon-based ceramic article

DOEpatents

Copley, S.M.; Tao, H.; Todd-Copley, J.A.

1991-06-11

A process is disclosed for improving the strength of laser-machined articles formed of a silicon-based ceramic material such as silicon nitride, in which the laser-machined surface is immersed in an etching solution of hydrofluoric acid and nitric acid for a duration sufficient to remove substantially all of a silicon film residue on the surface but insufficient to allow the solution to unduly attack the grain boundaries of the underlying silicon nitride substrate. This effectively removes the silicon film as a source of cracks that otherwise could propagate downwardly into the silicon nitride substrate and significantly reduce its strength. 1 figure.

SEMICONDUCTOR TECHNOLOGY: Reduction of proximity effect in fabricating nanometer-spaced nanopillars by two-step exposure

NASA Astrophysics Data System (ADS)

Yang, Zhang; Renping, Zhang; Weihua, Han; Jian, Liu; Xiang, Yang; Ying, Wang; Chian Chiu, Li; Fuhua, Yang

2009-11-01

A two-step exposure method to effectively reduce the proximity effect in fabricating nanometer-spaced nanopillars is presented. In this method, nanopillar patterns on poly-methylmethacrylate (PMMA) were partly cross-linked in the first-step exposure. After development, PMMA between nanopillar patterns was removed, and hence the proximity effect would not take place there in the subsequent exposure. In the second-step exposure, PMMA masks were completely cross-linked to achieve good resistance in inductively coupled plasma etching. Accurate pattern transfer of rows of nanopillars with spacing down to 40 nm was realized on a silicon-on-insulator substrate.

Improved toughness of silicon carbide

NASA Technical Reports Server (NTRS)

Palm, J. A.

1976-01-01

Impact energy absorbing layers (EALs) comprised of partially densified silicon carbide were formed in situ on fully sinterable silicon carbide substrates. After final sintering, duplex silicon carbide structures resulted which were comprised of a fully sintered, high density silicon carbide substrate or core, overlayed with an EAL of partially sintered silicon carbide integrally bonded to its core member. Thermal cycling tests proved such structures to be moderately resistant to oxidation and highly resistant to thermal shock stresses. The strength of the developed structures in some cases exceeded but essentially it remained the same as the fully sintered silicon carbide without the EAL. Ballistic impact tests indicated that substantial improvements in the toughness of sintered silicon carbide were achieved by the use of the partially densified silicon carbide EALs.

Fabrication Process of Silicone-based Dielectric Elastomer Actuators

PubMed Central

Rosset, Samuel; Araromi, Oluwaseun A.; Schlatter, Samuel; Shea, Herbert R.

2016-01-01

This contribution demonstrates the fabrication process of dielectric elastomer transducers (DETs). DETs are stretchable capacitors consisting of an elastomeric dielectric membrane sandwiched between two compliant electrodes. The large actuation strains of these transducers when used as actuators (over 300% area strain) and their soft and compliant nature has been exploited for a wide range of applications, including electrically tunable optics, haptic feedback devices, wave-energy harvesting, deformable cell-culture devices, compliant grippers, and propulsion of a bio-inspired fish-like airship. In most cases, DETs are made with a commercial proprietary acrylic elastomer and with hand-applied electrodes of carbon powder or carbon grease. This combination leads to non-reproducible and slow actuators exhibiting viscoelastic creep and a short lifetime. We present here a complete process flow for the reproducible fabrication of DETs based on thin elastomeric silicone films, including casting of thin silicone membranes, membrane release and prestretching, patterning of robust compliant electrodes, assembly and testing. The membranes are cast on flexible polyethylene terephthalate (PET) substrates coated with a water-soluble sacrificial layer for ease of release. The electrodes consist of carbon black particles dispersed into a silicone matrix and patterned using a stamping technique, which leads to precisely-defined compliant electrodes that present a high adhesion to the dielectric membrane on which they are applied. PMID:26863283

Dip coating process: Silicon sheet growth development for the large-area silicon sheet task of the low-cost silicon solar array project

NASA Technical Reports Server (NTRS)

Heaps, J. D.; Maciolek, R. B.; Zook, J. D.; Harrison, W. B.; Scott, M. W.; Hendrickson, G.; Wolner, H. A.; Nelson, L. D.; Schuller, T. L.; Peterson, A. A.

1976-01-01

The technical and economic feasibility of producing solar cell quality sheet silicon by dip-coating one surface of carbonized ceramic substrates with a thin layer of large grain polycrystalline silicon was investigated. The dip-coating methods studied were directed toward a minimum cost process with the ultimate objective of producing solar cells with a conversion efficiency of 10% or greater. The technique shows excellent promise for low cost, labor-saving, scale-up potentialities and would provide an end product of sheet silicon with a rigid and strong supportive backing. An experimental dip-coating facility was designed and constructed, several substrates were successfully dip-coated with areas as large as 25 sq cm and thicknesses of 12 micron to 250 micron. There appears to be no serious limitation on the area of a substrate that could be coated. Of the various substrate materials dip-coated, mullite appears to best satisfy the requirement of the program. An inexpensive process was developed for producing mullite in the desired geometry.

Interaction of a single acetophenone molecule with group III-IV elements mediated by Si(001)

NASA Astrophysics Data System (ADS)

Racis, A.; Jurczyszyn, L.; Radny, M. W.

2018-03-01

A theoretical study of an influence of the acetophenone molecule adsorbed on the Si(001) on the local chemical reactivity of silicon surface is presented. The obtained results indicate that the interaction of the molecule with silicon substrate breaks the intra-dimer π bonds in four surface silicon dimers interacting directly with adsorbed molecule. This leads to the formation of two pairs of unpaired dangling bonds at two opposite sides of the molecule. It is demonstrated that these dangling bonds increase considerably the local chemical reactivity of the silicon substrate in the vicinity of the adsorbed molecule. Consequently, it is shown that such molecule bonded with Si(001) can stabilize the position of In and Pb adatoms diffusing on silicon substrate at two sides and initiate the one-dimensional aggregation of the metallic adatoms on the Si(001) substrate anchored at both sides of the adsorbed molecule. This type of aggregation leads to the growth of chain-like atomic structures in opposite directions, pinned to adsorbed molecule and oriented perpendicular to the rows of surface silicon dimers.

Low-Power RIE of SiO2 in CHF3 To Obtain Steep Sidewalls

NASA Technical Reports Server (NTRS)

Turner, Tasha; Wu, Chi

2003-01-01

A reactive-ion etching (RIE) process has been developed to enable the formation of holes with steep sidewalls in a layer of silicon dioxide that covers a silicon substrate. The holes in question are through the thickness of the SiO2 and are used to define silicon substrate areas to be etched or to be built upon through epitaxial deposition of silicon. The sidewalls of these holes are required to be vertical in order to ensure that the sidewalls of the holes to be etched in the substrate or the sidewalls of the epitaxial deposits, respectively, also turn out to be vertical.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1995-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Purification and deposition of silicon by an iodide disproportionation reaction

DOEpatents

Wang, Tihu; Ciszek, Theodore F.

2002-01-01

Method and apparatus for producing purified bulk silicon from highly impure metallurgical-grade silicon source material at atmospheric pressure. Method involves: (1) initially reacting iodine and metallurgical-grade silicon to create silicon tetraiodide and impurity iodide byproducts in a cold-wall reactor chamber; (2) isolating silicon tetraiodide from the impurity iodide byproducts and purifying it by distillation in a distillation chamber; and (3) transferring the purified silicon tetraiodide back to the cold-wall reactor chamber, reacting it with additional iodine and metallurgical-grade silicon to produce silicon diiodide and depositing the silicon diiodide onto a substrate within the cold-wall reactor chamber. The two chambers are at atmospheric pressure and the system is open to allow the introduction of additional source material and to remove and replace finished substrates.

Composition Comprising Silicon Carbide

NASA Technical Reports Server (NTRS)

Mehregany, Mehran (Inventor); Zorman, Christian A. (Inventor); Fu, Xiao-An (Inventor); Dunning, Jeremy L. (Inventor)

2012-01-01

A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties.

Method and apparatus for forming conformal SiN.sub.x films

DOEpatents

Wang, Qi

2007-11-27

A silicon nitride film formation method includes: Heating a substrate to be subjected to film formation to a substrate temperature; heating a wire to a wire temperature; supplying silane, ammonia, and hydrogen gases to the heating member; and forming a silicon nitride film on the substrate.

Amorphous silicon as high index photonic material

NASA Astrophysics Data System (ADS)

Lipka, T.; Harke, A.; Horn, O.; Amthor, J.; Müller, J.

2009-05-01

Silicon-on-Insulator (SOI) photonics has become an attractive research topic within the area of integrated optics. This paper aims to fabricate SOI-structures for optical communication applications with lower costs compared to standard fabrication processes as well as to provide a higher flexibility with respect to waveguide and substrate material choice. Amorphous silicon is deposited on thermal oxidized silicon wafers with plasma-enhanced chemical vapor deposition (PECVD). The material is optimized in terms of optical light transmission and refractive index. Different a-Si:H waveguides with low propagation losses are presented. The waveguides were processed with CMOS-compatible fabrication technologies and standard DUV-lithography enabling high volume production. To overcome the large mode-field diameter mismatch between incoupling fiber and sub-μm waveguides three dimensional, amorphous silicon tapers were fabricated with a KOH etched shadow mask for patterning. Using ellipsometric and Raman spectroscopic measurements the material properties as refractive index, layer thickness, crystallinity and material composition were analyzed. Rapid thermal annealing (RTA) experiments of amorphous thin films and rib waveguides were performed aiming to tune the refractive index of the deposited a-Si:H waveguide core layer after deposition.

Integration of lateral porous silicon membranes into planar microfluidics.

PubMed

Leïchlé, Thierry; Bourrier, David

2015-02-07

In this work, we present a novel fabrication process that enables the monolithic integration of lateral porous silicon membranes into single-layer planar microchannels. This fabrication technique relies on the patterning of local electrodes to guide pore formation horizontally within the membrane and on the use of silicon-on-insulator substrates to spatially localize porous silicon within the channel depth. The feasibility of our approach is studied by current flow analysis using the finite element method and supported by creating 10 μm long mesoporous membranes within 20 μm deep microchannels. The fabricated membranes are demonstrated to be potentially useful for dead-end microfiltration by adequately retaining 300 nm diameter beads while macromolecules such as single-stranded DNA and immunoglobulin G permeate the membrane. The experimentally determined fluidic resistance is in accordance with the theoretical value expected from the estimated pore size and porosity. The work presented here is expected to greatly simplify the integration of membranes capable of size exclusion based separation into fluidic devices and opens doors to the use of porous silicon in planar lab on a chip devices.

Fabrication of a sensing module using micromachined biosensors.

PubMed

Suzuki, H; Arakawa, H; Karube, I

2001-12-01

Micromachining is a powerful tool in constructing micro biosensors and micro systems which incorporate them. A sensing module for blood components was fabricated using the technology. The analytes include glucose, urea, uric acid, creatine, and creatinine. Transducers used to construct the corresponding sensors were a Severinghaus-type carbon dioxide electrode for the urea sensor and a Clark-type oxygen electrode for the other analytes. In these electrodes, detecting electrode patterns were formed on a glass substrate by photolithography and the micro container for the internal electrolyte solution was formed on a silicon substrate by anisotropic etching. A through-hole was formed in the sensitive area, where a silicone gas-permeable membrane was formed and an enzyme was immobilized. The sensors were characterized in terms of pH and temperature dependence and calibration curves along with detection limits. Furthermore, the sensors were incorporated in an acrylate flow cell. Simultaneous operation of these sensors was successfully conducted and distinct and stable responses were observed for respective sensors.

Memory switches based on metal oxide thin films

NASA Technical Reports Server (NTRS)

Ramesham, Rajeshuni (Inventor); Thakoor, Anilkumar P. (Inventor); Lambe, John J. (Inventor)

1990-01-01

MnO.sub.2-x thin films (12) exhibit irreversible memory switching (28) with an OFF/ON resistance ratio of at least about 10.sup.3 and the tailorability of ON state (20) resistance. Such films are potentially extremely useful as a connection element in a variety of microelectronic circuits and arrays (24). Such films provide a pre-tailored, finite, non-volatile resistive element at a desired place in an electric circuit, which can be electrically turned OFF (22) or disconnected as desired, by application of an electrical pulse. Microswitch structures (10) constitute the thin film element, contacted by a pair of separate electrodes (16a, 16b) and have a finite, pre-selected ON resistance which is ideally suited, for example, as a programmable binary synaptic connection for electronic implementation of neural network architectures. The MnO.sub.2-x microswitch is non-volatile, patternable, insensitive to ultraviolet light, and adherent to a variety of insulating substrates (14), such as glass and silicon dioxide-coated silicon substrates.

Monolithic integration of InGaAs/InP multiple quantum wells on SOI substrates for photonic devices

NASA Astrophysics Data System (ADS)

Li, Zhibo; Wang, Mengqi; Fang, Xin; Li, Yajie; Zhou, Xuliang; Yu, Hongyan; Wang, Pengfei; Wang, Wei; Pan, Jiaoqing

2018-02-01

A direct epitaxy of III-V nanowires with InGaAs/InP multiple quantum wells on v-shaped trenches patterned silicon on insulator (SOI) substrates was realized by combining the standard semiconductor fabrication process with the aspect ratio trapping growth technique. Silicon thickness as well as the width and gap of each nanowire were carefully designed to accommodate essential optical properties and appropriate growth conditions. The III-V element ingredient, crystalline quality, and surface topography of the grown nanowires were characterized by X-ray diffraction spectroscopy, photoluminescence, and scanning electron microscope. Geometrical details and chemical information of multiple quantum wells were revealed by transmission electron microscopy and energy dispersive spectroscopy. Numerical simulations confirmed that the optical guided mode supported by one single nanowire was able to propagate 50 μm with ˜30% optical loss. This proposed integration scheme opens up an alternative pathway for future photonic integrations of III-V devices on the SOI platform at nanoscale.

Silicon on Ceramic Process: Silicon Sheet Growth and Device Development for the Large-area Silicon Sheet and Cell Development Tasks of the Low-cost Solar Array Project

NASA Technical Reports Server (NTRS)

Chapman, P. W.; Zook, J. D.; Heaps, J. D.; Pickering, C.; Grung, B. L.; Koepke, B.; Schuldt, S. B.

1979-01-01

The technical and economic feasibility of producing solar cell quality sheet silicon was investigated. It was hoped this could be done by coating one surface of carbonized ceramic substrates with a thin layer of large-grain polycrystalline silicon from the melt. Work was directed towards the solution of unique cell processing/design problems encountered with the silicon-ceramic (SOC) material due to its intimate contact with the ceramic substrate. Significant progress was demonstrated in the following areas; (1) the continuous coater succeeded in producing small-area coatings exhibiting unidirectional solidification and substatial grain size; (2) dip coater succeeded in producing thick (more than 500 micron) dendritic layers at coating speeds of 0.2-0.3 cm/sec; and (3) a standard for producing total area SOC solar cells using slotted ceramic substrates was developed.

Effect of specific surface microstructures on substrate endothelialisation and thrombogenicity: Importance for stent design.

PubMed

Lutter, Christoph; Nothhaft, Matthias; Rzany, Alexander; Garlichs, Christoph D; Cicha, Iwona

2015-01-01

In coronary artery disease, highly stenosed arteries are frequently treated by stent implantation, which thereafter necessitates a dual-antiplatelet therapy (DAPT) in order to prevent stent-thrombosis. We hypothesized that specific patterns of microstructures on stents can accelerate endothelialisation thereby reducing their thrombogenicity and the DAPT duration. Differently designed, 2-5 μm high elevations or hollows were lithographically etched on silicon plates, subsequently coated with silicon carbide. Smooth silicon plates and bare metal substrates were used as controls. To assess attachment and growth of human umbilical vein endothelial cells under static or flow conditions, actin cytoskeleton was visualised with green phalloidin. Endothelial migration was assessed in a modified barrier assay. To investigate surface thrombogenicity, platelets were incubated on the structured surfaces in static and flow conditions, and visualised with fluorescein-conjugated P-selectin antibody. Images were taken with incident-light fluorescent microscope for non-transparent objects. Compared to smooth surface, flat cubic elevations (5 μm edge length) improved endothelial cell attachment and growth under static and dynamic conditions, whereas smaller, spiky structures (2 μm edge length) had a negative influence on endothelialisation. Endothelial cell migration was fastest on flat cubic elevations, hollows, and smooth surfaces, whereas spiky structures and bare metal had a negative effect on endothelial migration. Thrombogenicity assays under static and flow conditions showed that platelet adhesion was reduced on the flat elevations and the smooth surface, as compared to the spiky structures, the hollow design and the bare metal substrates. Surface microstructures strongly influence endothelialisation of substrates. Designing stents with surface topography which accelerates endothelialisation and reduces thrombogenicity may be of clinical benefit by improving the safety profile of coronary interventions.

Polycrystalline silicon on tungsten substrates

NASA Technical Reports Server (NTRS)

Bevolo, A. J.; Schmidt, F. A.; Shanks, H. R.; Campisi, G. J.

1979-01-01

Thin films of electron-beam-vaporized silicon were deposited on fine-grained tungsten substrates under a pressure of about 1 x 10 to the -10th torr. Mass spectra from a quadrupole residual-gas analyzer were used to determine the partial pressure of 13 residual gases during each processing step. During separate silicon depositions, the atomically clean substrates were maintained at various temperatures between 400 and 780 C, and deposition rates were between 20 and 630 A min. Surface contamination and interdiffusion were monitored by in situ Auger electron spectrometry before and after cleaning, deposition, and annealing. Auger depth profiling, X-ray analysis, and SEM in the topographic and channeling modes were utilized to characterize the samples with respect to silicon-metal interface, interdiffusion, silicide formation, and grain size of silicon. The onset of silicide formation was found to occur at approximately 625 C. Above this temperature tungsten silicides were formed at a rate faster than the silicon deposition. Fine-grain silicon films were obtained at lower temperatures.

Improvement in crystal quality and optical properties of n-type GaN employing nano-scale SiO2 patterned n-type GaN substrate.

PubMed

Jo, Min Sung; Sadasivam, Karthikeyan Giri; Tawfik, Wael Z; Yang, Seung Bea; Lee, Jung Ju; Ha, Jun Seok; Moon, Young Boo; Ryu, Sang Wan; Lee, June Key

2013-01-01

n-type GaN epitaxial layers were regrown on the patterned n-type GaN substrate (PNS) with different size of silicon dioxide (SiO2) nano dots to improve the crystal quality and optical properties. PNS with SiO2 nano dots promotes epitaxial lateral overgrowth (ELOG) for defect reduction and also acts as a light scattering point. Transmission electron microscopy (TEM) analysis suggested that PNS with SiO2 nano dots have superior crystalline properties. Hall measurements indicated that incrementing values in electron mobility were clear indication of reduction in threading dislocation and it was confirmed by TEM analysis. Photoluminescence (PL) intensity was enhanced by 2.0 times and 3.1 times for 1-step and 2-step PNS, respectively.

RF sputtering for controlling dihydride and monohydride bond densities in amorphous silicon hydride

DOEpatents

Jeffery, F.R.; Shanks, H.R.

1980-08-26

A process is described for controlling the dihydride and monohydride bond densities in hydrogenated amorphous silicone produced by reactive rf sputtering of an amorphous silicon target. There is provided a chamber with an amorphous silicon target and a substrate therein with the substrate and the target positioned such that when rf power is applied to the target the substrate is in contact with the sputtering plasma produced thereby. Hydrogen and argon are fed to the chamber and the pressure is reduced in the chamber to a value sufficient to maintain a sputtering plasma therein, and then rf power is applied to the silicon target to provide a power density in the range of from about 7 watts per square inch to about 22 watts per square inch to sputter an amorphous solicone hydride onto the substrate, the dihydride bond density decreasing with an increase in the rf power density. Substantially pure monohydride films may be produced.

Diamond Synthesis Employing Nanoparticle Seeds

NASA Technical Reports Server (NTRS)

Uppireddi, Kishore (Inventor); Morell, Gerardo (Inventor); Weiner, Brad R. (Inventor)

2014-01-01

Iron nanoparticles were employed to induce the synthesis of diamond on molybdenum, silicon, and quartz substrates. Diamond films were grown using conventional conditions for diamond synthesis by hot filament chemical vapor deposition, except that dispersed iron oxide nanoparticles replaced the seeding. This approach to diamond induction can be combined with dip pen nanolithography for the selective deposition of diamond and diamond patterning while avoiding surface damage associated to diamond-seeding methods.

Effect of plasticity and atmospheric pressure on the formation of donut- and croissantlike buckles.

PubMed

Hamade, S; Durinck, J; Parry, G; Coupeau, C; Cimetière, A; Grilhé, J; Colin, J

2015-01-01

The formation of donut- and croissantlike buckles has been observed onto the free surface of gold thin films deposited on silicon substrates. Numerical simulations clearly evidence that the coupling effect between the atmospheric pressure acting on the free surface and the plastic folding of the ductile film is responsible for the circular blister destabilization and the formation of the donut- and croissantlike buckling patterns.

SOI-silicon as structural layer for NEMS applications

NASA Astrophysics Data System (ADS)

Villarroya, Maria; Figueras, Eduard; Perez-Murano, Francesc; Campabadal, Francesca; Esteve, Jaume; Barniol, Nuria

2003-04-01

The objective of this paper is to present the compatibilization between a standard CMOS on bulk silicon process and the fabrication of nanoelectromechanical systems using Silicon On Insulator (SOI) wafers as substrate. This compatibilization is required as first step to fabricate a very high sensitive mass sensor based on a resonant cantilever with nanometer dimensions using the crystal silicon COI layer as the structural layer. The cantilever is driven electrostatically to its resonance frequency by an electrode placed parallel to the cantilever. A capacitive readout is performed. To achieve very high resolution, very small dimensions of the cantilever (nanometer range) are needed. For this reason, the control and excitation circuitry has to be integrated on the same substrate than the cantilever. Prior to the development of this sensor, it is necessary to develop a substrate able to be used first to integrate a standard CMOS circuit and afterwards to fabricate the nano-resonator. Starting from a SOI wafer and using very simple processes, the SOI silicon layer is removed, except from the areas in which nano-structures will be fabricated; obtaining a silicon substrate with islands with a SOI structure. The CMOS circuitry will be integrated on the bulk silicon region, while the remainder SOI region will be used for the nanoresonator. The silicon oxide of this SOI region is used as insulator; and as sacrificial layer, etched to release the cantilever from the substrate. To assure the cover of the different CMOS layers over the step of the islands, it is essential to avoid very sharp steps.

Method for deposition of a conductor in integrated circuits

DOEpatents

Creighton, J.R.; Dominguez, F.; Johnson, A.W.; Omstead, T.R.

1997-09-02

A method is described for fabricating integrated semiconductor circuits and, more particularly, for the selective deposition of a conductor onto a substrate employing a chemical vapor deposition process. By way of example, tungsten can be selectively deposited onto a silicon substrate. At the onset of loss of selectivity of deposition of tungsten onto the silicon substrate, the deposition process is interrupted and unwanted tungsten which has deposited on a mask layer with the silicon substrate can be removed employing a halogen etchant. Thereafter, a plurality of deposition/etch back cycles can be carried out to achieve a predetermined thickness of tungsten. 2 figs.

Etching nano-holes in silicon carbide using catalytic platinum nano-particles

NASA Astrophysics Data System (ADS)

Moyen, E.; Wulfhekel, W.; Lee, W.; Leycuras, A.; Nielsch, K.; Gösele, U.; Hanbücken, M.

2006-09-01

The catalytic reaction of platinum during a hydrogen etching process has been used to perform controlled vertical nanopatterning of silicon carbide substrates. A first set of experiments was performed with platinum powder randomly distributed on the SiC surface. Subsequent hydrogen etching in a hot wall reactor caused local atomic hydrogen production at the catalyst resulting in local SiC etching and hole formation. Secondly, a highly regular and monosized distribution of Pt was obtained by sputter deposition of Pt through an Au membrane serving as a contact mask. After the lift-off of the mask, the hydrogen etching revealed the onset of well-controlled vertical patterned holes on the SiC surface.

High-Performance Ultrathin Organic-Inorganic Hybrid Silicon Solar Cells via Solution-Processed Interface Modification.

PubMed

Zhang, Jie; Zhang, Yinan; Song, Tao; Shen, Xinlei; Yu, Xuegong; Lee, Shuit-Tong; Sun, Baoquan; Jia, Baohua

2017-07-05

Organic-inorganic hybrid solar cells based on n-type crystalline silicon and poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) exhibited promising efficiency along with a low-cost fabrication process. In this work, ultrathin flexible silicon substrates, with a thickness as low as tens of micrometers, were employed to fabricate hybrid solar cells to reduce the use of silicon materials. To improve the light-trapping ability, nanostructures were built on the thin silicon substrates by a metal-assisted chemical etching method (MACE). However, nanostructured silicon resulted in a large amount of surface-defect states, causing detrimental charge recombination. Here, the surface was smoothed by solution-processed chemical treatment to reduce the surface/volume ratio of nanostructured silicon. Surface-charge recombination was dramatically suppressed after surface modification with a chemical, associated with improved minority charge-carrier lifetime. As a result, a power conversion efficiency of 9.1% was achieved in the flexible hybrid silicon solar cells, with a substrate thickness as low as ∼14 μm, indicating that interface engineering was essential to improve the hybrid junction quality and photovoltaic characteristics of the hybrid devices.

Circularly polarized Raman study on diamond structure crystals

NASA Astrophysics Data System (ADS)

Lee, Je-Ho; Kim, Sera; Seong, Maeng-Je

2018-01-01

Circularly polarized Raman and/or photoluminescence (PL) analyses have recently been very important in studying physical properties of many layered materials that were either mechanically exfoliated or grown by chemical-vapor-deposition (CVD) on silicon substrates. Since silicon Raman signal is always accompanied by the circularly polarized Raman and/or PL signal from the layered materials, observation of proper circularly polarized Raman selection rules on silicon substrates would be extremely good indicator that the circularly polarized Raman and/or PL measurements on the layered materials were done properly. We have performed circularly polarized Raman measurements on silicon substrates and compared the results with the Raman intensities calculated by using Raman tensors of the diamond crystal structure. Our experimental results were in excellent agreement with the calculation. Similar circularly polarized Raman analysis done on germanium substrate also showed good agreement.

Passivation coating for flexible substrate mirrors

DOEpatents

Tracy, C. Edwin; Benson, David K.

1990-01-01

A protective diffusion barrier for metalized mirror structures is provided by a layer or coating of silicon nitride which is a very dense, transparent, dielectric material that is impervious to water, alkali, and other impurities and corrosive substances that typically attack the metal layers of mirrors and cause degradation of the mirrors' reflectivity. The silicon nitride layer can be deposited on the substrate before metal deposition thereon to stabilize the metal/substrate interface, and it can be deposited over the metal to encapsulate it and protect the metal from corrosion or other degradation. Mirrors coated with silicon nitride according to this invention can also be used as front surface mirrors. Also, the silver or other reflective metal layer on mirrors comprising thin, lightweight, flexible substrates of metal or polymer sheets coated with glassy layers can be protected with silicon nitride according to this invention.

Direct metallization local Al-back surface field for high efficiency screen printed crystalline silicon solar cells.

PubMed

Lee, Jonghwan; Park, Cheolmin; Dao, Vinh Ai; Lee, Youn-Jung; Ryu, Kyungyul; Choi, Gyuho; Kim, Bonggi; Ju, Minkyu; Jeong, Chaehwan; Yi, Junsin

2013-11-01

In this paper, we present a detailed study on the local back contact (LBC) formation of rear-surface-passivated silicon solar cells, where both the LBC opening and metallization are realized by one-step alloying of a dot of fine pattern screen-printed aluminum paste with the silicon substrate. Based on energy dispersive spectrometer (EDS) and scanning electron microscopy (SEM) characterizations, we suggest that the aluminum distribution and the silicon concentration determine the local-back-surface-field (Al-p+) layer thickness, resistivity of the Al-p+ and hence the quality of the Al-p+ formation. The highest penetration of silicon concentration of 78.17% in aluminum resulted in the formation of a 5 microm-deep Al-p+ layer, and the minimum LBC resistivity of 0.92 x 10-6 omega cm2. The degradation of the rear-surface passivation due to high temperature of the LBC formation process can be fully recovered by forming gas annealing (FGA) at temperature and hydrogen content of 450 degrees C and 15%, respectively. The application of the optimized LBC of rear-surface-passivated by a dot of fine pattern screen(-) printed aluminum paste resulted in efficiency of up to 19.98% for the p-type czochralski (CZ) silicon wafers with 10.24 cm2 cell size at 649 mV open circuit voltage. By FGA for rear-surface passivation recovery, efficiencies up to 20.35% with a V(OC) of 662 mV, FF of 82%, and J(SC) of 37.5 mA/cm2 were demonstrated.

Elemental and compound semiconductor surface chemistry: Intelligent interfacial design facilitated through novel functionalization and deposition strategies

NASA Astrophysics Data System (ADS)

Porter, Lon Alan, Jr.

The fundamental understanding of silicon surface chemistry is an essential tool for silicon's continued dominance of the semiconductor industry in the years to come. By tapping into the vast library of organic functionalities, the synthesis of organic monolayers may be utilized to prepare interfaces, tailored to a myriad of applications ranging from silicon VLSI device optimization and MEMS to physiological implants and chemical sensors. Efforts in our lab to form stable organic monolayers on porous silicon through direct silicon-carbon linkages have resulted in several efficient functionalization methods. In the first chapter of this thesis a comprehensive review of these methods, and many others is presented. The following chapter and the appendix serve to demonstrate both potential applications and studies aimed at developing a fundamental understanding of the chemistry behind the organic functionalization of silicon surfaces. The remainder of this thesis attempts to demonstrate new methods of metal deposition onto both elemental and compound semiconductor surfaces. Currently, there is considerable interest in producing patterned metallic structures with reduced dimensions for use in technologies such as ULSI device fabrication, MEMS, and arrayed nanosensors, without sacrificing throughput or cost effectiveness. Research in our laboratory has focused on the preparation of precious metal thin films on semiconductor substrates via electroless deposition. Continuous metallic films form spontaneously under ambient conditions, in the absence of a fluoride source or an externally applied current. In order to apply this metallization method toward the development of useful technologies, patterning utilizing photolithography, microcontact printing, and scanning probe nanolithography has been demonstrated.

Modification of surface properties of cellulosic substrates by quaternized silicone emulsions.

PubMed

Purohit, Parag S; Somasundaran, P

2014-07-15

The present work describes the effect of quaternization of silicones as well as the relevant treatment parameter pH on the frictional, morphological and relaxation properties of fabric substrates. Due to their unique surface properties, silicone polymers are extensively used to modify surface properties of various materials, although the effects of functionalization of silicones and relevant process conditions on modification of substrates are not well understood. Specifically we show a considerable reduction in fabric friction, roughness and waviness upon treatment with quaternized silicones. The treatment at acidic pH results in better deposition of silicone polymers onto the fabric as confirmed through streaming potential measurements which show charge reversal of the fabric. Interestingly, Raman spectroscopy studies show the band of C-O ring stretching mode at ∼1095 cm(-1) shift towards higher wavenumber indicating lowering of stress in fibers upon appropriate silicone treatment. Thus along with the morphological and frictional properties being altered, silicone treatment can lead to a reduction in fabric strain. It is concluded that the electrostatic interactions play an initial role in modification of the fiber substrate followed by multilayer deposition of polymer. This multi-technique approach to study fiber properties upon treatment by combining macro to molecular level methods has helped in understanding of new functional coating materials. Copyright © 2014 Elsevier Inc. All rights reserved.

Modifying Surface Fluctuations of Polymer Melt Films with Substrate Modification

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhou, Yang; He, Qiming; Zhang, Fan

Deposition of a plasma polymerized film on a silicon substrate substantially changes the fluctuations on the surface of a sufficiently thin, melt polystyrene (PS) film atop the substrate. Surface fluctuation relaxation times measured with X-ray photon correlation spectroscopy (XPCS) for ca. 4R g thick melt films of 131 kg/mol linear PS on silicon and on a plasma polymer modified silicon wafer can both be described using a hydrodynamic continuum theory (HCT) that assumes the film is characterized throughout its depth by the bulk viscosity. However, when the film thickness is reduced to ~3R g, confinement effects are evident. The surfacemore » fluctuations are slower than predicted using the HCT, and the confinement effect for the PS on silicon is larger than that for the PS on the plasma polymerized film. This deviation is thus due to a difference in the thicknesses of the strongly adsorbed layers at the substrate which are impacted by the substrate surface energy.« less

Modifying Surface Fluctuations of Polymer Melt Films with Substrate Modification

DOE PAGES

Zhou, Yang; He, Qiming; Zhang, Fan; ...

2017-08-14

Deposition of a plasma polymerized film on a silicon substrate substantially changes the fluctuations on the surface of a sufficiently thin, melt polystyrene (PS) film atop the substrate. Surface fluctuation relaxation times measured with X-ray photon correlation spectroscopy (XPCS) for ca. 4R g thick melt films of 131 kg/mol linear PS on silicon and on a plasma polymer modified silicon wafer can both be described using a hydrodynamic continuum theory (HCT) that assumes the film is characterized throughout its depth by the bulk viscosity. However, when the film thickness is reduced to ~3R g, confinement effects are evident. The surfacemore » fluctuations are slower than predicted using the HCT, and the confinement effect for the PS on silicon is larger than that for the PS on the plasma polymerized film. This deviation is thus due to a difference in the thicknesses of the strongly adsorbed layers at the substrate which are impacted by the substrate surface energy.« less

Fabrication of 3D surface structures using grayscale lithography

NASA Astrophysics Data System (ADS)

Stilson, Christopher; Pal, Rajan; Coutu, Ronald A.

2014-03-01

The ability to design and develop 3D microstructures is important for microelectromechanical systems (MEMS) fabrication. Previous techniques used to create 3D devices included tedious steps in direct writing and aligning patterns onto a substrate followed by multiple photolithography steps using expensive, customized equipment. Additionally, these techniques restricted batch processing and placed limits on achievable shapes. Gray-scale lithography enables the fabrication of a variety of shapes using a single photolithography step followed by reactive ion etching (RIE). Micromachining 3D silicon structures for MEMS can be accomplished using gray-scale lithography along with dry anisotropic etching. In this study, we investigated: using MATLAB for mask designs; feasibility of using 1 μm Heidelberg mask maker to direct write patterns onto photoresist; using RIE processing to etch patterns into a silicon substrate; and the ability to tailor etch selectivity for precise fabrication. To determine etch rates and to obtain desired etch selectivity, parameters such as gas mixture, gas flow, and electrode power were studied. This process successfully demonstrates the ability to use gray-scale lithography and RIE for use in the study of micro-contacts. These results were used to produce a known engineered non-planer surface for testing micro-contacts. Surface structures are between 5 μm and 20 μm wide with varying depths and slopes based on mask design and etch rate selectivity. The engineered surfaces will provide more insight into contact geometries and failure modes of fixed-fixed micro-contacts.

Diamond Composite Films for Protective Coatings on Metals and Method of Formation

NASA Technical Reports Server (NTRS)

Ong, Tiong P. (Inventor); Shing, Yuh-Han (Inventor)

1997-01-01

Composite films consisting of diamond crystallites and hard amorphous films such as diamond-like carbon, titanium nitride, and titanium oxide are provided as protective coatings for metal substrates against extremely harsh environments. A composite layer having diamond crystallites and a hard amorphous film is affixed to a metal substrate via an interlayer including a bottom metal silicide film and a top silicon carbide film. The interlayer is formed either by depositing metal silicide and silicon carbide directly onto the metal substrate, or by first depositing an amorphous silicon film, then allowing top and bottom portions of the amorphous silicon to react during deposition of the diamond crystallites, to yield the desired interlayer structure.

Silicon nitride films deposited with an electron beam created plasma

NASA Technical Reports Server (NTRS)

Bishop, D. C.; Emery, K. A.; Rocca, J. J.; Thompson, L. R.; Zamani, H.; Collins, G. J.

1984-01-01

The electron beam assisted chemical vapor deposition (EBCVD) of silicon nitride films using NH3, N2, and SiH4 as the reactant gases is reported. The films have been deposited on aluminum, SiO2, and polysilicon film substrates as well as on crystalline silicon substrates. The range of experimental conditions under which silicon nitrides have been deposited includes substrate temperatures from 50 to 400 C, electron beam currents of 2-40 mA, electron beam energies of 1-5 keV, total ambient pressures of 0.1-0.4 Torr, and NH3/SiH4 mass flow ratios of 1-80. The physical, electrical, and chemical properties of the EBCVD films are discussed.

Transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1995-05-09

A method is disclosed for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, Anthony M.

1997-01-01

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed.

Method for fabricating transistors using crystalline silicon devices on glass

DOEpatents

McCarthy, A.M.

1997-09-02

A method for fabricating transistors using single-crystal silicon devices on glass. This method overcomes the potential damage that may be caused to the device during high voltage bonding and employs a metal layer which may be incorporated as part of the transistor. This is accomplished such that when the bonding of the silicon wafer or substrate to the glass substrate is performed, the voltage and current pass through areas where transistors will not be fabricated. After removal of the silicon substrate, further metal may be deposited to form electrical contact or add functionality to the devices. By this method both single and gate-all-around devices may be formed. 13 figs.

Rough SERS substrate based on gold coated porous silicon layer prepared on the silicon backside surface

NASA Astrophysics Data System (ADS)

Dridi, H.; Haji, L.; Moadhen, A.

2017-04-01

We report in this paper a novel method to elaborate rough Surface Enhanced Raman Scattering (SERS) substrate. A single layer of porous silicon was formed on the silicon backside surface. Morphological characteristics of the porous silicon layer before and after gold deposition were influenced by the rough character (gold size). The reflectance measurements showed a dependence of the gold nano-grains size on the surface nature, through the Localized Surface Plasmon (LSP) band properties. SERS signal of Rhodamine 6G used as a model analyte, adsorbed on the rough porous silicon layer revealed a marked enhancement of its vibrational modes intensities.

Silicon Nanowire Growth at Chosen Positions and Orientations

NASA Technical Reports Server (NTRS)

Getty, Stephanie A.

2009-01-01

It is now possible to grow silicon nanowires at chosen positions and orientations by a method that involves a combination of standard microfabrication processes. Because their positions and orientations can be chosen with unprecedented precision, the nanowires can be utilized as integral parts of individually electronically addressable devices in dense arrays. Nanowires made from silicon and perhaps other semiconductors hold substantial promise for integration into highly miniaturized sensors, field-effect transistors, optoelectronic devices, and other electronic devices. Like bulk semiconductors, inorganic semiconducting nanowires are characterized by electronic energy bandgaps that render them suitable as means of modulating or controlling electronic signals through electrostatic gating, in response to incident light, or in response to molecules of interest close to their surfaces. There is now potential for fabricating arrays of uniform, individually electronically addressable nanowires tailored to specific applications. The method involves formation of metal catalytic particles at the desired positions on a substrate, followed by heating the substrate in the presence of silane gas. The figure illustrates an example in which a substrate includes a silicon dioxide surface layer that has been etched into an array of pillars and the catalytic (in this case, gold) particles have been placed on the right-facing sides of the pillars. The catalytic thermal decomposition of the silane to silicon and hydrogen causes silicon columns (the desired nanowires) to grow outward from the originally catalyzed spots on the substrate, carrying the catalytic particles at their tips. Thus, the position and orientation of each silicon nanowire is determined by the position of its originally catalyzed spot on the substrate surface, and the orientation of the nanowire is perpendicular to the substrate surface at the originally catalyzed spot.

Quantification and significance of fluid shear stress field in biaxial cell stretching device.

PubMed

Thompson, Mark S; Abercrombie, Stuart R; Ott, Claus-Eric; Bieler, Friederike H; Duda, Georg N; Ventikos, Yiannis

2011-07-01

A widely used commercially available system for the investigation of mechanosensitivity applies a biaxial strain field to cells cultured on a compliant silicone substrate membrane stretched over a central post. As well as intended substrate strain, this device also provides a fluid flow environment for the cultured cells. In order to interpret the relevance of experiments using this device to the in vivo and clinical situation, it is essential to characterise both substrate and fluid environments. While previous work has detailed the substrate strain, the fluid shear stresses, to which bone cells are known to be sensitive, are unknown. Therefore, a fluid structure interaction computational fluid dynamics model was constructed, incorporating a finite element technique capable of capturing the contact between the post and the silicone substrate membrane, to the underside of which the pump control pressure was applied. Flow verification experiments using 10-μm-diameter fluorescent microspheres were carried out. Fluid shear stress increased approximately linearly with radius along the on-post substrate membrane, with peak values located close to the post edge. Changes in stimulation frequency and culture medium viscosity effected proportional changes in the magnitude of the fluid shear stress (peak fluid shear stresses varied in the range 0.09-3.5 Pa), with minor effects on temporal and spatial distribution. Good agreement was obtained between predicted and measured radial flow patterns. These results suggest a reinterpretation of previous data obtained using this device to include the potential for a strong role of fluid shear stress in mechanosensitivity.

Direct comparison of the performance of commonly used e-beam resists during nano-scale plasma etching of Si, SiO2, and Cr

NASA Astrophysics Data System (ADS)

Goodyear, Andy; Boettcher, Monika; Stolberg, Ines; Cooke, Mike

2015-03-01

Electron beam writing remains one of the reference pattern generation techniques, and plasma etching continues to underpin pattern transfer. We report a systematic study of the plasma etch resistance of several e-beam resists, both negative and positive as well as classical and Chemically Amplified Resists: HSQ[1,2] (Dow Corning), PMMA[3] (Allresist GmbH), AR-P6200 (Allresist GmbH), ZEP520 (Zeon Corporation), CAN028 (TOK), CAP164 (TOK), and an additional pCAR (non-disclosed provider). Their behaviour under plasma exposure to various nano-scale plasma etch chemistries was examined (SF6/C4F8 ICP silicon etch, CHF3/Ar RIE SiO2 etch, Cl2/O2 RIE and ICP chrome etch, and HBr ICP silicon etch). Samples of each resist type were etched simultaneously to provide a direct comparison of their etch resistance. Resist thicknesses (and hence resist erosion rates) were measured by spectroscopic ellipsometer in order to provide the highest accuracy for the resist comparison. Etch selectivities (substrate:mask etch rate ratio) are given, with recommendations for the optimum resist choice for each type of etch chemistry. Silicon etch profiles are also presented, along with the exposure and etch conditions to obtain the most vertical nano-scale pattern transfer. We identify one resist that gave an unusually high selectivity for chlorinated and brominated etches which could enable pattern transfer below 10nm without an additional hard mask. In this case the resist itself acts as a hard mask. We also highlight the differing effects of fluorine and bromine-based Silicon etch chemistries on resist profile evolution and hence etch fidelity.

Thin film transistors on plastic substrates with reflective coatings for radiation protection

DOEpatents

Wolfe, Jesse D.; Theiss, Steven D.; Carey, Paul G.; Smith, Patrick M.; Wickboldt, Paul

2003-11-04

Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

Thin film transistors on plastic substrates with reflective coatings for radiation protection

DOEpatents

Wolfe, Jesse D [Fairfield, CA; Theiss, Steven D [Woodbury, MN; Carey, Paul G [Mountain View, CA; Smith, Patrick M [San Ramon, CA; Wickbold, Paul [Walnut Creek, CA

2006-09-26

Fabrication of silicon thin film transistors (TFT) on low-temperature plastic substrates using a reflective coating so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The TFT can be used in large area low cost electronics, such as flat panel displays and portable electronics such as video cameras, personal digital assistants, and cell phones.

Patterning layer-by-layer self-assembled multilayer by lithography and its applications to thin film devices

NASA Astrophysics Data System (ADS)

Hua, Feng

Nanoparticles are exciting materials because they exhibit unique electronic, catalytic, and optical properties. As a novel and promising nanobuilding block, it attracts considerable research efforts in its integration into a wide variety of thin film devices. Nanoparticles were adsorbed onto the substrate with layer-by-layer self-assembly which becomes of great interest due to its suitability in colloid particle assembly. Without extremely high temperatures and sophisticated equipment, molecularly organized films in an exactly pre-designed order can grow on almost all the substrates in nature. Two approaches generating spatially separated patterns comprised of nanoparticles are demonstrated, as well as two approaches patterning more than one type of nonoparticle on a silicon wafer. The structure of the thin film patterned by these approaches are analyzed and considered suitable to the thin film device. Finally, the combination of lithography and layer-by-layer (lbl) self-assembly is utilized to realize the microelectronic device with functional nonoparticles. The lbl self-assembly is the way to coat the nonoparticles and the lighography to pattern them. Based on the coating and patterning technique, a MOS-capacitor, a MOS field-effect-transistor and magnetic thin film cantilever are fabricated.

Formation of porous silicon oxide from substrate-bound silicon rich silicon oxide layers by continuous-wave laser irradiation

NASA Astrophysics Data System (ADS)

Wang, Nan; Fricke-Begemann, Th.; Peretzki, P.; Ihlemann, J.; Seibt, M.

2018-03-01

Silicon nanocrystals embedded in silicon oxide that show room temperature photoluminescence (PL) have great potential in silicon light emission applications. Nanocrystalline silicon particle formation by laser irradiation has the unique advantage of spatially controlled heating, which is compatible with modern silicon micro-fabrication technology. In this paper, we employ continuous wave laser irradiation to decompose substrate-bound silicon-rich silicon oxide films into crystalline silicon particles and silicon dioxide. The resulting microstructure is studied using transmission electron microscopy techniques with considerable emphasis on the formation and properties of laser damaged regions which typically quench room temperature PL from the nanoparticles. It is shown that such regions consist of an amorphous matrix with a composition similar to silicon dioxide which contains some nanometric silicon particles in addition to pores. A mechanism referred to as "selective silicon ablation" is proposed which consistently explains the experimental observations. Implications for the damage-free laser decomposition of silicon-rich silicon oxides and also for controlled production of porous silicon dioxide films are discussed.

Galvanic displacement reaction and rapid thermal annealing in size/shape controlling silver nanoparticles on silicon substrate

NASA Astrophysics Data System (ADS)

Ghosh, Tapas; Satpati, Biswarup

2017-05-01

The effect of the thermal annealing on silver nanoparticles deposited on silicon surface has been studied. The silver nanoparticles have been deposited by the galvanic displacement reaction. Rapid thermal annealing (RTA) has been performed on the Si substrate, containing the silver nanoparticles. The scanning transmission electron microscopy (STEM), energy dispersive X-ray (EDX) spectroscopy and scanning electron microscopy (SEM) study show that the galvanic displacement reaction and subsequent rapid thermal annealing could lead to well separated and spherical shaped larger silver nanoparticles on silicon substrate.

Development of refractory armored silicon carbide by infrared transient liquid phase processing

NASA Astrophysics Data System (ADS)

Hinoki, Tatsuya; Snead, Lance L.; Blue, Craig A.

2005-12-01

Tungsten (W) and molybdenum (Mo) were coated on silicon carbide (SiC) for use as a refractory armor using a high power plasma arc lamp at powers up to 23.5 MW/m 2 in an argon flow environment. Both tungsten powder and molybdenum powder melted and formed coating layers on silicon carbide within a few seconds. The effect of substrate pre-treatment (vapor deposition of titanium (Ti) and tungsten, and annealing) and sample heating conditions on microstructure of the coating and coating/substrate interface were investigated. The microstructure was observed by scanning electron microscopy (SEM) and optical microscopy (OM). The mechanical properties of the coated materials were evaluated by four-point flexural tests. A strong tungsten coating was successfully applied to the silicon carbide substrate. Tungsten vapor deposition and pre-heating at 5.2 MW/m 2 made for a refractory layer containing no cracks propagating into the silicon carbide substrate. The tungsten coating was formed without the thick reaction layer. For this study, small tungsten carbide grains were observed adjacent to the interface in all conditions. In addition, relatively large, widely scattered tungsten carbide grains and a eutectic structure of tungsten and silicon were observed through the thickness in the coatings formed at lower powers and longer heating times. The strength of the silicon carbide substrate was somewhat decreased as a result of the processing. Vapor deposition of tungsten prior to powder coating helped prevent this degradation. In contrast, molybdenum coating was more challenging than tungsten coating due to the larger coefficient of thermal expansion (CTE) mismatch as compared to tungsten and silicon carbide. From this work it is concluded that refractory armoring of silicon carbide by Infrared Transient Liquid Phase Processing is possible. The tungsten armored silicon carbide samples proved uniform, strong, and capable of withstanding thermal fatigue testing.

Fully CMOS-compatible titanium nitride nanoantennas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Briggs, Justin A., E-mail: jabriggs@stanford.edu; Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305; Naik, Gururaj V.

CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements onmore » plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.« less

Graphoepitaxy integration and pattern transfer of lamellar silicon-containing high-chi block copolymers

NASA Astrophysics Data System (ADS)

Bézard, P.; Chevalier, X.; Legrain, A.; Navarro, C.; Nicolet, C.; Fleury, G.; Cayrefourcq, I.; Tiron, R.; Zelsmann, M.

2018-03-01

In this work, we present our recent achievements on the integration and transfer etching of a novel silicon-containing high-χ block copolymer for lines/spaces applications. Developed carbo-silane BCPs are synthesized under industrial conditions and present periodicities as low as 14 nm. A full directed self-assembly by graphoepitaxy process is shown using standard photolithography stacks and all processes are performed on 300 mm wafer compatible tools. Specific plasma processes are developed to isolate perpendicular lamellae and sub-12 nm features are finally transferred into silicon substrates. The quality of the final BCP hard mask (CDU, LWR, LER) are also investigated. Finally, thanks to the development of dedicated neutral layers and top-coats allowing perpendicular orientations, it was possible to investigate plasma etching experiments on full-sheets at 7 nm resolution, opening the way to the integration of these polymers in chemoepitaxy stacks.

Improving performance of Si/CdS micro-/nanoribbon p-n heterojunction light emitting diodes by trenched structure

NASA Astrophysics Data System (ADS)

Huang, Shiyuan; Wu, Yuanpeng; Ma, Xiangyang; Yang, Zongyin; Liu, Xu; Yang, Qing

2018-05-01

Realizing high performance silicon based light sources has been an unremitting pursuit for researchers. In this letter, we propose a simple structure to enhance electroluminescence emission and reduce the threshold of injected current of silicon/CdS micro-/nanoribbon p-n heterojunction visible light emitting diodes, by fabricating trenched structure on silicon substrate to mount CdS micro-/nanoribbon. A series of experiments and simulation analysis favors the rationality and validity of our mounting design. After mounting the CdS micro-/nanoribbon, the optical field confinement increases, and absorption and losses from high refractive silicon substrate are effectively reduced. Meanwhile the sharp change of silicon substrate near heterojunction also facilitates the balance between electron current and hole current, which substantially conduces to the stable amplification of electroluminescence emission in CdS micro-/nanoribbon.

Between Scylla and Charybdis: Hydrophobic Graphene-Guided Water Diffusion on Hydrophilic Substrates

PubMed Central

Kim, Jin-Soo; Choi, Jin Sik; Lee, Mi Jung; Park, Bae Ho; Bukhvalov, Danil; Son, Young-Woo; Yoon, Duhee; Cheong, Hyeonsik; Yun, Jun-Nyeong; Jung, Yousung; Park, Jeong Young; Salmeron, Miquel

2013-01-01

The structure of water confined in nanometer-sized cavities is important because, at this scale, a large fraction of hydrogen bonds can be perturbed by interaction with the confining walls. Unusual fluidity properties can thus be expected in the narrow pores, leading to new phenomena like the enhanced fluidity reported in carbon nanotubes. Crystalline mica and amorphous silicon dioxide are hydrophilic substrates that strongly adsorb water. Graphene, on the other hand, interacts weakly with water. This presents the question as to what determines the structure and diffusivity of water when intercalated between hydrophilic substrates and hydrophobic graphene. Using atomic force microscopy, we have found that while the hydrophilic substrates determine the structure of water near its surface, graphene guides its diffusion, favouring growth of intercalated water domains along the C-C bond zigzag direction. Molecular dynamics and density functional calculations are provided to help understand the highly anisotropic water stripe patterns observed. PMID:23896759

A reliable method to grow vertically-aligned silicon nanowires by a novel ramp-cooling process

NASA Astrophysics Data System (ADS)

Ho, Tzuen-Wei; Hong, Franklin Chau-Nan

2012-08-01

We have grown silicon nanowires (SiNWs) on Si (1 1 1) substrates by gold-catalyzed vapor-liquid-solid (VLS) process using tetrachlorosilane (SiCl4) in a hot-wall chemical vapor deposition reactor. Even under the optimized conditions including H2 annealing to reduce the surface native oxide, epitaxial SiNWs of 150-200 nm in diameter often grew along all four <1 1 1> family directions with one direction vertical and three others inclined to the surface. Therefore, the growth of high degree ordered SiNW arrays along [1 1 1] only was attempted on Au-coated Si (1 1 1) by a ramp-cooling process utilizing the liquid phase epitaxy (LPE) mechanism. The Au-coated Si substrate was first annealed in H2 at 650 °C to form Au-Si alloy nanoparticles, and then ramp-cooled at a controlled rate to precipitate epitaxial Si seeds on the substrate based on LPE mechanism. The substrate was further heated in SiCl4/H2 to 850 °C for the VLS growths of SiNWs on the Si seeds. Thus, almost 100% vertically-aligned SiNWs along [1 1 1] only could be reproducibly grown on Si (1 1 1), without using a template or patterning the metal catalyst. The high-density vertically-aligned SiNWs have good potentials for solar cells and nano-devices.

Hybrid emitter all back contact solar cell

DOEpatents

Loscutoff, Paul; Rim, Seung

2016-04-12

An all back contact solar cell has a hybrid emitter design. The solar cell has a thin dielectric layer formed on a backside surface of a single crystalline silicon substrate. One emitter of the solar cell is made of doped polycrystalline silicon that is formed on the thin dielectric layer. The other emitter of the solar cell is formed in the single crystalline silicon substrate and is made of doped single crystalline silicon. The solar cell includes contact holes that allow metal contacts to connect to corresponding emitters.

Silicon carbide and other films and method of deposition

NASA Technical Reports Server (NTRS)

Mehregany, Mehran (Inventor); Zorman, Christian A. (Inventor); Fu, Xiao-An (Inventor); Dunning, Jeremy L. (Inventor)

2007-01-01

A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties.

Coated silicon comprising material for protection against environmental corrosion

NASA Technical Reports Server (NTRS)

Hazel, Brian Thomas (Inventor)

2009-01-01

In accordance with an embodiment of the invention, an article is disclosed. The article comprises a gas turbine engine component substrate comprising a silicon material; and an environmental barrier coating overlying the substrate, wherein the environmental barrier coating comprises cerium oxide, and the cerium oxide reduces formation of silicate glass on the substrate upon exposure to corrodant sulfates.

Silicon carbide and other films and method of deposition

NASA Technical Reports Server (NTRS)

Mehregany, Mehran (Inventor); Zorman, Christian A. (Inventor); Fu, Xiao-An (Inventor); Dunning, Jeremy (Inventor)

2011-01-01

A method of depositing a ceramic film, particularly a silicon carbide film, on a substrate is disclosed in which the residual stress, residual stress gradient, and resistivity are controlled. Also disclosed are substrates having a deposited film with these controlled properties and devices, particularly MEMS and NEMS devices, having substrates with films having these properties.

EUVL mask patterning with blanks from commercial suppliers

NASA Astrophysics Data System (ADS)

Yan, Pei-Yang; Zhang, Guojing; Nagpal, Rajesh; Shu, Emily Y.; Li, Chaoyang; Qu, Ping; Chen, Frederick T.

2004-12-01

Extreme Ultraviolet Lithography (EUVL) reflective mask blank development includes low thermal expansion material fabrication, mask substrate finishing, reflective multi-layer (ML) and capping layer deposition, buffer (optional)/absorber stack deposition, EUV specific metrology, and ML defect inspection. In the past, we have obtained blanks deposited with various layer stacks from several vendors. Some of them are not commercial suppliers. As a result, the blank and patterned mask qualities are difficult to maintain and improve. In this paper we will present the evaluation results of the EUVL mask pattering processes with the complete EUVL mask blanks supplied by the commercial blank supplier. The EUVL mask blanks used in this study consist of either quartz or ULE substrates which is a type of low thermal expansion material (LTEM), 40 pairs of molybdenum/silicon (Mo/Si) ML layer, thin ruthenium (Ru) capping layer, tantalum boron nitride (TaBN) absorber, and chrome (Cr) backside coating. No buffer layer is used. Our study includes the EUVL mask blank characterization, patterned EUVL mask characterization, and the final patterned EUVL mask flatness evaluation.

Enhanced optical output power of InGaN/GaN light-emitting diodes grown on a silicon (111) substrate with a nanoporous GaN layer.

PubMed

Lee, Kwang Jae; Chun, Jaeyi; Kim, Sang-Jo; Oh, Semi; Ha, Chang-Soo; Park, Jung-Won; Lee, Seung-Jae; Song, Jae-Chul; Baek, Jong Hyeob; Park, Seong-Ju

2016-03-07

We report the growth of InGaN/GaN multiple quantum wells blue light-emitting diodes (LEDs) on a silicon (111) substrate with an embedded nanoporous (NP) GaN layer. The NP GaN layer is fabricated by electrochemical etching of n-type GaN on the silicon substrate. The crystalline quality of crack-free GaN grown on the NP GaN layer is remarkably improved and the residual tensile stress is also decreased. The optical output power is increased by 120% at an injection current of 20 mA compared with that of conventional LEDs without a NP GaN layer. The large enhancement of optical output power is attributed to the reduction of threading dislocation, effective scattering of light in the LED, and the suppression of light propagation into the silicon substrate by the NP GaN layer.

Oxidation resistant high temperature thermal cycling resistant coatings on silicon-based substrates and process for the production thereof

DOEpatents

Sarin, V.K.

1990-08-21

An oxidation resistant, high temperature thermal cycling resistant coated ceramic article for ceramic heat engine applications is disclosed. The substrate is a silicon-based material, i.e. a silicon nitride- or silicon carbide-based monolithic or composite material. The coating is a graded coating of at least two layers: an intermediate AlN or Al[sub x]N[sub y]O[sub z] layer and an aluminum oxide or zirconium oxide outer layer. The composition of the coating changes gradually from that of the substrate to that of the AlN or Al[sub x]N[sub y]O[sub z] layer and further to the composition of the aluminum oxide or zirconium oxide outer layer. Other layers may be deposited over the aluminum oxide layer. A CVD process for depositing the graded coating on the substrate is also disclosed.

Oxidation resistant high temperature thermal cycling resistant coatings on silicon-based substrates and process for the production thereof

DOEpatents

Sarin, Vinod K.

1990-01-01

An oxidation resistant, high temperature thermal cycling resistant coated ceramic article for ceramic heat engine applications. The substrate is a silicon-based material, i.e. a silicon nitride- or silicon carbide-based monolithic or composite material. The coating is a graded coating of at least two layers: an intermediate AlN or Al.sub.x N.sub.y O.sub.z layer and an aluminum oxide or zirconium oxide outer layer. The composition of the coating changes gradually from that of the substrate to that of the AlN or Al.sub.x N.sub.y O.sub.z layer and further to the composition of the aluminum oxide or zirconium oxide outer layer. Other layers may be deposited over the aluminum oxide layer. A CVD process for depositing the graded coating on the substrate is also disclosed.

Study on Silicon Microstructure Processing Technology Based on Porous Silicon

NASA Astrophysics Data System (ADS)

Shang, Yingqi; Zhang, Linchao; Qi, Hong; Wu, Yalin; Zhang, Yan; Chen, Jing

2018-03-01

Aiming at the heterogeneity of micro - sealed cavity in silicon microstructure processing technology, the technique of preparing micro - sealed cavity of porous silicon is proposed. The effects of different solutions, different substrate doping concentrations, different current densities, and different etching times on the rate, porosity, thickness and morphology of the prepared porous silicon were studied. The porous silicon was prepared by different process parameters and the prepared porous silicon was tested and analyzed. For the test results, optimize the process parameters and experiments. The experimental results show that the porous silicon can be controlled by optimizing the parameters of the etching solution and the doping concentration of the substrate, and the preparation of porous silicon with different porosity can be realized by different doping concentration, so as to realize the preparation of silicon micro-sealed cavity, to solve the sensor sensitive micro-sealed cavity structure heterogeneous problem, greatly increasing the application of the sensor.

Crystallization of amorphous silicon thin films deposited by PECVD on nickel-metalized porous silicon.

PubMed

Ben Slama, Sonia; Hajji, Messaoud; Ezzaouia, Hatem

2012-08-17

Porous silicon layers were elaborated by electrochemical etching of heavily doped p-type silicon substrates. Metallization of porous silicon was carried out by immersion of substrates in diluted aqueous solution of nickel. Amorphous silicon thin films were deposited by plasma-enhanced chemical vapor deposition on metalized porous layers. Deposited amorphous thin films were crystallized under vacuum at 750°C. Obtained results from structural, optical, and electrical characterizations show that thermal annealing of amorphous silicon deposited on Ni-metalized porous silicon leads to an enhancement in the crystalline quality and physical properties of the silicon thin films. The improvement in the quality of the film is due to the crystallization of the amorphous film during annealing. This simple and easy method can be used to produce silicon thin films with high quality suitable for thin film solar cell applications.

Crystallization of amorphous silicon thin films deposited by PECVD on nickel-metalized porous silicon

PubMed Central

2012-01-01

Porous silicon layers were elaborated by electrochemical etching of heavily doped p-type silicon substrates. Metallization of porous silicon was carried out by immersion of substrates in diluted aqueous solution of nickel. Amorphous silicon thin films were deposited by plasma-enhanced chemical vapor deposition on metalized porous layers. Deposited amorphous thin films were crystallized under vacuum at 750°C. Obtained results from structural, optical, and electrical characterizations show that thermal annealing of amorphous silicon deposited on Ni-metalized porous silicon leads to an enhancement in the crystalline quality and physical properties of the silicon thin films. The improvement in the quality of the film is due to the crystallization of the amorphous film during annealing. This simple and easy method can be used to produce silicon thin films with high quality suitable for thin film solar cell applications. PMID:22901341

Application of cyclic fluorocarbon/argon discharges to device patterning

DOE Office of Scientific and Technical Information (OSTI.GOV)

Metzler, Dominik, E-mail: dmetzler@umd.edu; Uppireddi, Kishore; Bruce, Robert L.

2016-01-15

With increasing demands on device patterning to achieve smaller critical dimensions and pitches for the 5 nm node and beyond, the need for atomic layer etching (ALE) is steadily increasing. In this work, a cyclic fluorocarbon/Ar plasma is successfully used for ALE patterning in a manufacturing scale reactor. Self-limited etching of silicon oxide is observed. The impact of various process parameters on the etch performance is established. The substrate temperature has been shown to play an especially significant role, with lower temperatures leading to higher selectivity and lower etch rates, but worse pattern fidelity. The cyclic ALE approach established with thismore » work is shown to have great potential for small scale device patterning, showing self-limited etching, improved uniformity and resist mask performance.« less

Application of cyclic fluorocarbon/argon discharges to device patterning

DOE PAGES

Metzler, Dominik; Uppiredi, Kishore; Bruce, Robert L.; ...

2015-11-13

With increasing demands on device patterning to achieve smaller critical dimensions and pitches for the 5nm node and beyond, the need for atomic layer etching (ALE) is steadily increasing. In this study, a cyclic fluorocarbon/Ar plasma is successfully used for ALE patterning in a manufacturing scale reactor. Self-limited etching of silicon oxide is observed. The impact of various process parameters on the etch performance is established. The substrate temperature has been shown to play an especially significant role, with lower temperatures leading to higher selectivity and lower etch rates, but worse pattern fidelity. The cyclic ALE approach established with thismore » work is shown to have great potential for small scale device patterning, showing self-limited etching, improved uniformity and resist mask performance.« less

Substrate for thin silicon solar cells

DOEpatents

Ciszek, Theodore F.

1995-01-01

A photovoltaic device for converting solar energy into electrical signals comprises a substrate, a layer of photoconductive semiconductor material grown on said substrate, wherein the substrate comprises an alloy of boron and silicon, the boron being present in a range of from 0.1 to 1.3 atomic percent, the alloy having a lattice constant substantially matched to that of the photoconductive semiconductor material and a resistivity of less than 1.times.10.sup.-3 ohm-cm.

Effect of the substrate on the insulator-metal transition of vanadium dioxide films

NASA Astrophysics Data System (ADS)

Kovács, György J.; Bürger, Danilo; Skorupa, Ilona; Reuther, Helfried; Heller, René; Schmidt, Heidemarie

2011-03-01

Single-phase vanadium dioxide films grown on (0001) sapphire and (001) silicon substrates show a very different insulator-metal electronic transition. A detailed description of the growth mechanisms and the substrate-film interaction is given, and the characteristics of the electronic transition are described by the morphology and grain boundary structure. (Tri-)epitaxy-stabilized columnar growth of VO2 takes place on the sapphire substrate, whereas on silicon the expected Zone II growth is identified. We have found that in the case of the Si substrate the reasons for the broader hysteresis and the lower switching amplitude are the formation of an amorphous insulating VOx (x > 2.6) phase coexisting with VO2 and the high vanadium vacancy concentration of the VO2. These phenomena are the result of the excess oxygen during the growth and the interaction between the silicon substrate and the growing film.

Die singulation method

DOEpatents

Swiler, Thomas P.; Garcia, Ernest J.; Francis, Kathryn M.

2013-06-11

A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with an HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

Die singulation method

DOEpatents

Swiler, Thomas P [Albuquerque, NM; Garcia, Ernest J [Albuquerque, NM; Francis, Kathryn M [Rio Rancho, NM

2014-01-07

A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with a HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

Planar digital nanoliter dispensing system based on thermocapillary actuation.

PubMed

Darhuber, Anton A; Valentino, Joseph P; Troian, Sandra M

2010-04-21

We provide guidelines for the design and operation of a planar digital nanodispensing system based on thermocapillary actuation. Thin metallic microheaters embedded within a chemically patterned glass substrate are electronically activated to generate and control 2D surface temperature distributions which either arrest or trigger liquid flow and droplet formation on demand. This flow control is a consequence of the variation of a liquid's surface tension with temperature, which is used to draw liquid toward cooler regions of the supporting substrate. A liquid sample consisting of several microliters is placed on a flat rectangular supply cell defined by chemical patterning. Thermocapillary switches are then activated to extract a slender fluid filament from the cell and to divide the filament into an array of droplets whose position and volume are digitally controlled. Experimental results for the power required to extract a filament and to divide it into two or more droplets as a function of geometric and operating parameters are in excellent agreement with hydrodynamic simulations. The capability to dispense ultralow volumes onto a 2D substrate extends the functionality of microfluidic devices based on thermocapillary actuation previously shown effective in routing and mixing nanoliter liquid samples on glass or silicon substrates.

Growing Gallium Arsenide On Silicon

NASA Technical Reports Server (NTRS)

Radhakrishnan, Gouri

1989-01-01

Epitaxial layers of high quality formed on <111> crystal plane. Present work reports successful growth of 1- and 2-micrometer thick layers of n-type, 7-ohms per cm, 2-inch diameter, Si<111> substrate. Growth conducted in Riber-2300(R) MBE system. Both doped and undoped layers of GaAs grown. Chamber equipped with electron gun and camera for in-situ reflection high-energy-electron diffraction measurements. RHEED patterns of surface monitored continuously during slow growth stage.

Innovative Ge Quantum Dot Functional Sensing and Metrology Devices

DTIC Science & Technology

2017-08-21

information latency and power consumption . In contrast, optical interconnects have shown tremendous promise for replacing electrical wires thanks to...single oxidation step of Si0.85Ge0.15 nano-pillars patterned over a buffer layer of Si3N4 on top of the n-Si substrate. During the high- temperature ...exquisitely-controlled dynamic balance between the fluxes of oxygen and silicon interstitials. Results and Discussion: 1. Self-organized, gate

4 channel × 10 Gb/s bidirectional optical subassembly using silicon optical bench with precise passive optical alignment.

PubMed

Kang, Eun Kyu; Lee, Yong Woo; Ravindran, Sooraj; Lee, Jun Ki; Choi, Hee Ju; Ju, Gun Wu; Min, Jung Wook; Song, Young Min; Sohn, Ik-Bu; Lee, Yong Tak

2016-05-16

We demonstrate an advanced structure for optical interconnect consisting of 4 channel × 10 Gb/s bidirectional optical subassembly (BOSA) formed using silicon optical bench (SiOB) with tapered fiber guiding holes (TFGHs) for precise and passive optical alignment of vertical-cavity surface-emitting laser (VCSEL)-to-multi mode fiber (MMF) and MMF-to-photodiode (PD). The co-planar waveguide (CPW) transmission line (Tline) was formed on the backside of silicon substrate to reduce the insertion loss of electrical data signal. The 4 channel VCSEL and PD array are attached at the end of CPW Tline using a flip-chip bonder and solder pad. The 12-channel ribbon fiber is simply inserted into the TFGHs of SiOB and is passively aligned to the VCSEL and PD in which no additional coupling optics are required. The fabricated BOSA shows high coupling efficiency and good performance with the clearly open eye patterns and a very low bit error rate of less than 10^-12 order at a data rate of 10 Gb/s with a PRBS pattern of 2³¹-1.

Progress in the Development of SERS-Active Substrates Based on Metal-Coated Porous Silicon

PubMed Central

Girel, Kseniya V.; Panarin, Andrei; Terekhov, Sergei N.

2018-01-01

The present work gives an overview of the developments in surface-enhanced Raman scattering (SERS) with metal-coated porous silicon used as an active substrate. We focused this review on the research referenced to SERS-active materials based on porous silicon, beginning from the patent application in 2002 and enclosing the studies of this year. Porous silicon and metal deposition technologies are discussed. Since the earliest studies, a number of fundamentally different plasmonic nanostructures including metallic dendrites, quasi-ordered arrays of metallic nanoparticles (NPs), and metallic nanovoids have been grown on porous silicon, defined by the morphology of this host material. SERS-active substrates based on porous silicon have been found to combine a high and well-reproducible signal level, storage stability, cost-effective technology and handy use. They make it possible to identify and study many compounds including biomolecules with a detection limit varying from milli- to femtomolar concentrations. The progress reviewed here demonstrates the great prospects for the extensive use of the metal-coated porous silicon for bioanalysis by SERS-spectroscopy. PMID:29883382

High-speed and on-chip graphene blackbody emitters for optical communications by remote heat transfer.

PubMed

Miyoshi, Yusuke; Fukazawa, Yusuke; Amasaka, Yuya; Reckmann, Robin; Yokoi, Tomoya; Ishida, Kazuki; Kawahara, Kenji; Ago, Hiroki; Maki, Hideyuki

2018-03-29

High-speed light emitters integrated on silicon chips can enable novel architectures for silicon-based optoelectronics, such as on-chip optical interconnects, and silicon photonics. However, conventional light sources based on compound semiconductors face major challenges for their integration with a silicon-based platform because of their difficulty of direct growth on a silicon substrate. Here we report ultra-high-speed (100-ps response time), highly integrated graphene-based on-silicon-chip blackbody emitters in the near-infrared region including telecommunication wavelength. Their emission responses are strongly affected by the graphene contact with the substrate depending on the number of graphene layers. The ultra-high-speed emission can be understood by remote quantum thermal transport via surface polar phonons of the substrates. We demonstrated real-time optical communications, integrated two-dimensional array emitters, capped emitters operable in air, and the direct coupling of optical fibers to the emitters. These emitters can open new routes to on-Si-chip, small footprint, and high-speed emitters for highly integrated optoelectronics and silicon photonics.

Progress in the Development of SERS-Active Substrates Based on Metal-Coated Porous Silicon.

PubMed

Bandarenka, Hanna V; Girel, Kseniya V; Zavatski, Sergey A; Panarin, Andrei; Terekhov, Sergei N

2018-05-21

The present work gives an overview of the developments in surface-enhanced Raman scattering (SERS) with metal-coated porous silicon used as an active substrate. We focused this review on the research referenced to SERS-active materials based on porous silicon, beginning from the patent application in 2002 and enclosing the studies of this year. Porous silicon and metal deposition technologies are discussed. Since the earliest studies, a number of fundamentally different plasmonic nanostructures including metallic dendrites, quasi-ordered arrays of metallic nanoparticles (NPs), and metallic nanovoids have been grown on porous silicon, defined by the morphology of this host material. SERS-active substrates based on porous silicon have been found to combine a high and well-reproducible signal level, storage stability, cost-effective technology and handy use. They make it possible to identify and study many compounds including biomolecules with a detection limit varying from milli- to femtomolar concentrations. The progress reviewed here demonstrates the great prospects for the extensive use of the metal-coated porous silicon for bioanalysis by SERS-spectroscopy.

Study of the photovoltaic effect in thin film barium titanate

NASA Technical Reports Server (NTRS)

Grannemann, W. W.; Dharmadhikari, V. S.

1982-01-01

Ferroelectric films of barium titanate were synthesized on silicon and quartz substrates, and the photoelectric effect in the structure consisting of metal deposited ferroelectric barium titanate film silicon was studied. A photovoltage with polarity that depends on the direction of the remanent polarization was observed. The deposition of BaTiO3 on silicon and fused quartz substrates was accomplished by an rf sputtering technique. A series of experiments to study the growth of ferroelectric BaTiO3 films on single crystal silicon and fused quartz substrates were conducted. The ferroelectric character in these films was found on the basis of evidence from the polarization electric field hysteresis loops, capacitance voltage and capacitance temperature techniques and from X-ray diffraction studies.

Biofunctionalization on alkylated silicon substrate surfaces via "click" chemistry.

PubMed

Qin, Guoting; Santos, Catherine; Zhang, Wen; Li, Yan; Kumar, Amit; Erasquin, Uriel J; Liu, Kai; Muradov, Pavel; Trautner, Barbara Wells; Cai, Chengzhi

2010-11-24

Biofunctionalization of silicon substrates is important to the development of silicon-based biosensors and devices. Compared to conventional organosiloxane films on silicon oxide intermediate layers, organic monolayers directly bound to the nonoxidized silicon substrates via Si-C bonds enhance the sensitivity of detection and the stability against hydrolytic cleavage. Such monolayers presenting a high density of terminal alkynyl groups for bioconjugation via copper-catalyzed azide-alkyne 1,3-dipolar cycloaddition (CuAAC, a "click" reaction) were reported. However, yields of the CuAAC reactions on these monolayer platforms were low. Also, the nonspecific adsorption of proteins on the resultant surfaces remained a major obstacle for many potential biological applications. Herein, we report a new type of "clickable" monolayers grown by selective, photoactivated surface hydrosilylation of α,ω-alkenynes, where the alkynyl terminal is protected with a trimethylgermanyl (TMG) group, on hydrogen-terminated silicon substrates. The TMG groups on the film are readily removed in aqueous solutions in the presence of Cu(I). Significantly, the degermanylation and the subsequent CuAAC reaction with various azides could be combined into a single step in good yields. Thus, oligo(ethylene glycol) (OEG) with an azido tag was attached to the TMG-alkyne surfaces, leading to OEG-terminated surfaces that reduced the nonspecific adsorption of protein (fibrinogen) by >98%. The CuAAC reaction could be performed in microarray format to generate arrays of mannose and biotin with varied densities on the protein-resistant OEG background. We also demonstrated that the monolayer platform could be functionalized with mannose for highly specific capturing of living targets (Escherichia coli expressing fimbriae) onto the silicon substrates.

Quantum cascade lasers grown on silicon.

PubMed

Nguyen-Van, Hoang; Baranov, Alexei N; Loghmari, Zeineb; Cerutti, Laurent; Rodriguez, Jean-Baptiste; Tournet, Julie; Narcy, Gregoire; Boissier, Guilhem; Patriarche, Gilles; Bahriz, Michael; Tournié, Eric; Teissier, Roland

2018-05-08

Technological platforms offering efficient integration of III-V semiconductor lasers with silicon electronics are eagerly awaited by industry. The availability of optoelectronic circuits combining III-V light sources with Si-based photonic and electronic components in a single chip will enable, in particular, the development of ultra-compact spectroscopic systems for mass scale applications. The first circuits of such type were fabricated using heterogeneous integration of semiconductor lasers by bonding the III-V chips onto silicon substrates. Direct epitaxial growth of interband III-V laser diodes on silicon substrates has also been reported, whereas intersubband emitters grown on Si have not yet been demonstrated. We report the first quantum cascade lasers (QCLs) directly grown on a silicon substrate. These InAs/AlSb QCLs grown on Si exhibit high performances, comparable with those of the devices fabricated on their native InAs substrate. The lasers emit near 11 µm, the longest emission wavelength of any laser integrated on Si. Given the wavelength range reachable with InAs/AlSb QCLs, these results open the way to the development of a wide variety of integrated sensors.

Method for enhancing the solubility of dopants in silicon

DOEpatents

Sadigh, Babak; Lenosky, Thomas J.; De La Rubia, Tomas Diaz

2003-09-30

A method for enhancing the equilibrium solid solubility of dopants in silicon, germanium and silicon-germanium alloys. The method involves subjecting silicon-based substrate to biaxial or compression strain. It has been determined that boron solubility was largely enhanced (more than 100%) by a compressive bi-axial strain, based on a size-mismatch theory since the boron atoms are smaller than the silicon atoms. It has been found that the large enhancement or mixing properties of dopants in silicon and germanium substrates is primarily governed by their, and to second order by their size-mismatch with the substrate. Further, it has been determined that the dopant solubility enhancement with strain is most effective when the charge and the size-mismatch of the impurity favor the same type of strain. Thus, the solid solubility of small p-type (e.g., boron) as well as large n-type (e.g., arsenic) dopants can be raised most dramatically by appropriate bi-axial (compressive) strain, and that solubility of a large p-type dopant (e.g, indium) in silicon will be raised due to size-mismatch with silicon, which favors tensile strain, while its negative charge prefers compressive strain, and thus the two effects counteract each other.

Stretchable metal oxide thin film transistors on engineered substrate for electronic skin applications.

PubMed

Romeo, Alessia; Lacour, Stphanie P

2015-08-01

Electronic skins aim at providing distributed sensing and computation in a large-area and elastic membrane. Control and addressing of high-density soft sensors will be achieved when thin film transistor matrices are also integrated in the soft carrier substrate. Here, we report on the design, manufacturing and characterization of metal oxide thin film transistors on these stretchable substrates. The TFTs are integrated onto an engineered silicone substrate with embedded strain relief to protect the devices from catastrophic cracking. The TFT stack is composed of an amorphous In-Ga-Zn-O active layer, a hybrid AlxOy/Parylene dielectric film, gold electrodes and interconnects. All layers are prepared and patterned with planar, low temperature and dry processing. We demonstrate the interconnected IGZO TFTs sustain applied tensile strain up to 20% without electrical degradation and mechanical fracture. Active devices are critical for distributed sensing. The compatibility of IGZO TFTs with soft and biocompatible substrates is an encouraging step towards wearable electronic skins.

Fabrication and characterization of physically defined quantum dots on a boron-doped silicon-on-insulator substrate

NASA Astrophysics Data System (ADS)

Mizoguchi, Seiya; Shimatani, Naoki; Kobayashi, Mizuki; Makino, Takaomi; Yamaoka, Yu; Kodera, Tetsuo

2018-04-01

We study hole transport properties in physically defined p-type silicon quantum dots (QDs) on a heavily doped silicon-on-insulator (SOI) substrate. We observe Coulomb diamonds using single QDs and estimate the charging energy as ∼1.6 meV. We obtain the charge stability diagram of double QDs using single QDs as a charge sensor. This is the first demonstration of charge sensing in p-type heavily doped silicon QDs. For future time-resolved measurements, we apply radio-frequency reflectometry using impedance matching of LC circuits to the device. We observe the resonance and estimate the capacitance as ∼0.12 pF from the resonant frequency. This value is smaller than that of the devices with top gates on nondoped SOI substrate. This indicates that high-frequency signals can be applied efficiently to p-type silicon QDs without top gates.

Microelectromechanical pump utilizing porous silicon

DOEpatents

Lantz, Jeffrey W [Albuquerque, NM; Stalford, Harold L [Norman, OK

2011-07-19

A microelectromechanical (MEM) pump is disclosed which includes a porous silicon region sandwiched between an inlet chamber and an outlet chamber. The porous silicon region is formed in a silicon substrate and contains a number of pores extending between the inlet and outlet chambers, with each pore having a cross-section dimension about equal to or smaller than a mean free path of a gas being pumped. A thermal gradient is provided along the length of each pore by a heat source which can be an electrical resistance heater or an integrated circuit (IC). A channel can be formed through the silicon substrate so that inlet and outlet ports can be formed on the same side of the substrate, or so that multiple MEM pumps can be connected in series to form a multi-stage MEM pump. The MEM pump has applications for use in gas-phase MEM chemical analysis systems, and can also be used for passive cooling of ICs.

Silicon nanomembranes as a means to evaluate stress evolution in deposited thin films

Treesearch

Anna M. Clausen; Deborah M. Paskiewicz; Alireza Sadeghirad; Joseph Jakes; Donald E. Savage; Donald S. Stone; Feng Liu; Max G. Lagally

2014-01-01

Thin-film deposition on ultra-thin substrates poses unique challenges because of the potential for a dynamic response to the film stress during deposition. While theoretical studies have investigated film stress related changes in bulk substrates, little has been done to learn how stress might evolve in a film growing on a compliant substrate. We use silicon...

Indium-bump-free antimonide superlattice membrane detectors on silicon substrates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zamiri, M., E-mail: mzamiri@chtm.unm.edu, E-mail: skrishna@chtm.unm.edu; Klein, B.; Schuler-Sandy, T.

2016-02-29

We present an approach to realize antimonide superlattices on silicon substrates without using conventional Indium-bump hybridization. In this approach, PIN superlattices are grown on top of a 60 nm Al{sub 0.6}Ga{sub 0.4}Sb sacrificial layer on a GaSb host substrate. Following the growth, the individual pixels are transferred using our epitaxial-lift off technique, which consists of a wet-etch to undercut the pixels followed by a dry-stamp process to transfer the pixels to a silicon substrate prepared with a gold layer. Structural and optical characterization of the transferred pixels was done using an optical microscope, scanning electron microscopy, and photoluminescence. The interface betweenmore » the transferred pixels and the new substrate was abrupt, and no significant degradation in the optical quality was observed. An Indium-bump-free membrane detector was then fabricated using this approach. Spectral response measurements provided a 100% cut-off wavelength of 4.3 μm at 77 K. The performance of the membrane detector was compared to a control detector on the as-grown substrate. The membrane detector was limited by surface leakage current. The proposed approach could pave the way for wafer-level integration of photonic detectors on silicon substrates, which could dramatically reduce the cost of these detectors.« less

PDMS spreading morphological patterns on substrates of different hydrophilicity in air vacuum and water.

PubMed

Zbik, Marek S; Frost, Ray L

2010-04-15

In paper has been to investigate the morphological patterns and kinetics of PDMS spreading on silicon wafer using combination of techniques like ellipsometry, atomic force microscope (AFM), scanning electron microscope (SEM) and optical microscopy. A macroscopic silicone oil drops as well as PDMS water based emulsions were studied after deposition on a flat surface of silicon wafer in air, water and vacuum. Our own measurements using an imaging ellipsometer, which also clearly shows the presence of a precursor film. The diffusion constant of this film, measured with a 60,000 cS PDMS sample spreading on a hydrophilic silicon wafer is D(f)=1.4x10(-11) m(2)/s. Regardless of their size, density and method of deposition, droplets on both types of wafer (hydrophilic and hydrophobic) flatten out over a period of many hours, up to 3 days. During this process neighbouring droplets may coalesce, but there is strong evidence that some of the PDMS from the droplets migrates into a thin, continuous film that covers the surface in between droplets. The thin film appears to be ubiquitous if there has been any deposition of PDMS. However, this statement needs further verification. One question is whether the film forms immediately after forced drying, or whether in some or all cases it only forms by spreading from isolated droplets as they slowly flatten out. 2010 Elsevier Inc. All rights reserved.

Towards substrate engineering of graphene-silicon Schottky diode photodetectors.

PubMed

Selvi, Hakan; Unsuree, Nawapong; Whittaker, Eric; Halsall, Matthew P; Hill, Ernie W; Thomas, Andrew; Parkinson, Patrick; Echtermeyer, Tim J

2018-02-15

Graphene-silicon Schottky diode photodetectors possess beneficial properties such as high responsivities and detectivities, broad spectral wavelength operation and high operating speeds. Various routes and architectures have been employed in the past to fabricate devices. Devices are commonly based on the removal of the silicon-oxide layer on the surface of silicon by wet-etching before deposition of graphene on top of silicon to form the graphene-silicon Schottky junction. In this work, we systematically investigate the influence of the interfacial oxide layer, the fabrication technique employed and the silicon substrate on the light detection capabilities of graphene-silicon Schottky diode photodetectors. The properties of devices are investigated over a broad wavelength range from near-UV to short-/mid-infrared radiation, radiation intensities covering over five orders of magnitude as well as the suitability of devices for high speed operation. Results show that the interfacial layer, depending on the required application, is in fact beneficial to enhance the photodetection properties of such devices. Further, we demonstrate the influence of the silicon substrate on the spectral response and operating speed. Fabricated devices operate over a broad spectral wavelength range from the near-UV to the short-/mid-infrared (thermal) wavelength regime, exhibit high photovoltage responses approaching 10 6 V W -1 and short rise- and fall-times of tens of nanoseconds.

Solution and interfacial behavior of modified silicone polymers and their interactions with solid substrates

NASA Astrophysics Data System (ADS)

Purohit, Parag

Surface treatment is very important step in many applications such as fabric finishing, coatings, cosmetics and personal care. Silicone polymers are a class of organic/inorganic materials that show unique properties such as weak intermolecular forces and high flexibility enabling even a very high molecular weight chain to achieve optimal orientation on surfaces. Material properties such as softness, repellency, bounciness and friction can therefore be tailored by using appropriately modified silicone polymers. Despite wide applications, the underlying mechanisms of material modification are unknown and tailoring silicones for applications remains mostly empirical. Thus the objective of this research is to understand the solution and interfacial behavior of functionalized silicone polymers, which govern their performance in material modification. Modified silicones are simultaneously hydrophobic and oleophobic in nature and due to this nearly universal non-compatibility, the studies of these polymers present unusual challenges. Due to this incompatible nature, the functionalized silicone polymers were emulsified into O/W emulsions to study their solution and interfacial properties. The colloidal properties such as electrokinetic and droplet distribution of these emulsions are assumed to play an important role in the observed surface and physical properties of solid substrates (in present study, cellulosic substrates) as well the stability of emulsions itself. To understand the effects of modified silicones on cellulosic substrates a variety of techniques such as frictional analysis, scanning electron microscopy and atomic force microscopy that can probe from macro to nano level were used. It is hypothesized that the size distribution and charge of silicone emulsions as well as the physiochemical conditions such as pH, control silicone conformation which in turn affect the modification of the substrate properties. With bimodal droplet distribution of silicone emulsions, the nano-sized droplets can penetrate deeper into the substrate to provide bounciness, whereas macro-sized droplets can coat the top layer leading to friction reduction. It was observed that at pH 5.5 the silicone treatment resulted in charge reversal of fibers as opposed to treatment at pH 9.5. On a macroscopic scale 20% reduction in frictional coefficient of the fabric was observed after treatment with quaternized (cationically modified) silicones as compared to untreated fibers. It was also observed using AFM that the fibrils treated with quaternized silicones are uniform, well stacked and smoother than the untreated fibers. Spectroscopic analysis of treated fibers using Raman spectroscopy indicated a decrease in fiber stress as a function of modification of silicone polymer and the interaction pH. It is concluded that the protonated amine functional silicone (below pH 7) as well as the quaternized silicone interacts with the negatively charged cellulose fibers primarily through electrostatic interactions. It is proposed that this initial surface coating is a uniform thin film which allows further deposition of polymer from the emulsion. It was observed that at high pH the zetapotential of silicone emulsions decreases drastically and the nano emulsions turn turbid. It is proposed that the observed electrophoretic and nephelometric behavior at high pH is due to flocculation of nanosized droplets to micron size, which eventually leads to droplets coalescing and emulsion destabilization. It is also postulated that the nano emulsion possess a critical dilution concentration (CDC), above which dilution leads to rapid coalescence. This critical dilution phase was further confirmed through polarity parameter and excimer formation studies which show significantly different polymer and surfactant microstructures near the CDC. Hence it is concluded that the observed surface properties of the substrate obtained above the CDC are significantly different than those below the CDC. The results reveal the vital role of physiochemical parameters such as pH, droplet size, and concentration on the emulsion stability as well as the observed physical/chemical properties of the substrates.

Substrate for thin silicon solar cells

DOEpatents

Ciszek, T.F.

1995-03-28

A photovoltaic device for converting solar energy into electrical signals comprises a substrate, a layer of photoconductive semiconductor material grown on said substrate, wherein the substrate comprises an alloy of boron and silicon, the boron being present in a range of from 0.1 to 1.3 atomic percent, the alloy having a lattice constant substantially matched to that of the photoconductive semiconductor material and a resistivity of less than 1{times}10{sup {minus}3} ohm-cm. 4 figures.

Measured Propagation Characteristics of Finite Ground Coplanar Waveguide on Silicon with a Thick Polyimide Interface Layer

NASA Technical Reports Server (NTRS)

Ponchak, George E.; Papapolymerou, John; Tentzeris, Emmanouil M.; Williams, W. O. (Technical Monitor)

2002-01-01

Measured propagation characteristics of Finite Ground Coplanar (FGC) waveguide on silicon substrates with resistivities spanning 3 orders of magnitude (0.1 to 15.5 Ohm cm) and a 20 micron thick polyimide interface layer is presented as a function of the FGC geometry. Results show that there is an optimum FGC geometry for minimum loss, and silicon with a resistivity of 0.1 Ohm cm has greater loss than substrates with higher and lower resistivity. Lastly, substrates with a resistivity of 10 Ohm cm or greater have acceptable loss.

Silicon-integrated thin-film structure for electro-optic applications

DOEpatents

McKee, Rodney A.; Walker, Frederick Joseph

2000-01-01

A crystalline thin-film structure suited for use in any of an number of electro-optic applications, such as a phase modulator or a component of an interferometer, includes a semiconductor substrate of silicon and a ferroelectric, optically-clear thin film of the perovskite BaTiO.sub.3 overlying the surface of the silicon substrate. The BaTiO.sub.3 thin film is characterized in that substantially all of the dipole moments associated with the ferroelectric film are arranged substantially parallel to the surface of the substrate to enhance the electro-optic qualities of the film.

Coated article and method of making

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor); Lee, Kang Neung (Inventor)

2003-01-01

An article includes a silicon-containing substrate and a modified mullite coating. The modified mullite coating comprises mullite and a modifier component that reduces cracks in the modified mullite coating. The article can further comprise a thermal barrier coating applied to the modified mullite coating. The modified mullite coating functions as a bond coating between the external environmental/thermal barrier coating and the silicon-containing substrate. In a method of forming an article, a silicon-containing substrate is formed and a modified mullite coating is applied. The modified mullite coating comprises mullite and a modifier component that reduces cracks in the modified mullite coating.

Coated article and method of making

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor); Lee, Kang Neung (Inventor)

2002-01-01

An article includes a silicon-containing substrate and a modified mullite coating. The modified mullite coating comprises mullite and a modifier component that reduces cracks in the modified mullite coating. The article can further comprise a thermal barrier coating applied to the modified mullite coating. The modified mullite coating functions as a bond coating between the external environmental/thermal barrier coating and the silicon-containing substrate. In a method of forming an article, a silicon-containing substrate is formed and a modified mullite coating is applied. The modified mullite coating comprises mullite and a modifier component that reduces cracks in the modified mullite coating.

RF Transmission Lines on Silicon Substrates

NASA Technical Reports Server (NTRS)

Ponchak, George E.

1999-01-01

A review of RF transmission lines on silicon substrates is presented. Through measurements and calculated results, it is shown that attenuation is dominated by conductor loss if silicon substrates with a resistivity greater than 2500 Ohm-cm are used. Si passivation layers affect the transmission line attenuation; however, measured results demonstrate that passivation layers do not necessarily increase attenuation. If standard, low resistivity Si wafers must be used, alternative transmission lines such as thin film microstrip and Co-Planar Waveguide (CPW) on thick polyimide layers must be used. Measured results presented here show that low loss per unit length is achievable with these transmission lines.

Charge-coupled device for low background observations

NASA Technical Reports Server (NTRS)

Loh, Edwin D. (Inventor); Cheng, Edward S. (Inventor)

2002-01-01

A charge-coupled device with a low-emissivity metal layer located between a sensing layer and a substrate provides reduction in ghost images. In a typical charge-coupled device of a silicon sensing layer, a silicon dioxide insulating layer, with a glass substrate and a metal carrier layer, a near-infrared photon, not absorbed in the first pass, enters the glass substrate, reflects from the metal carrier, thereby returning far from the original pixel in its entry path. The placement of a low-emissivity metal layer between the glass substrate and the sensing layer reflects near infrared photons before they reach the substrate so that they may be absorbed in the silicon nearer the pixel of their points of entry so that the reflected ghost image is coincident with the primary image for a sharper, brighter image.

Highly efficient color filter array using resonant Si3N4 gratings.

PubMed

Uddin, Mohammad Jalal; Magnusson, Robert

2013-05-20

We demonstrate the design and fabrication of a highly efficient guided-mode resonant color filter array. The device is designed using numerical methods based on rigorous coupled-wave analysis and is patterned using UV-laser interferometric lithography. It consists of a 60-nm-thick subwavelength silicon nitride grating along with a 105-nm-thick homogeneous silicon nitride waveguide on a glass substrate. The fabricated device exhibits blue, green, and red color response for grating periods of 274, 327, and 369 nm, respectively. The pixels have a spectral bandwidth of ~12 nm with efficiencies of 94%, 96%, and 99% at the center wavelength of blue, green, and red color filter, respectively. These are higher efficiencies than reported in the literature previously.

Trends and Techniques for Space Base Electronics

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Wade, T. E.; Gassaway, J. D.

1979-01-01

Simulations of various phosphorus and boron diffusions in SOS were completed and a sputtering system, furnaces, and photolithography related equipment were set up. Double layer metal experiments initially utilized wet chemistry techniques. By incorporating ultrasonic etching of the vias, premetal cleaning a modified buffered HF, phosphorus doped vapox, and extended sintering, yields of 98% were obtained using the standard test pattern. A two dimensional modeling program was written for simulating short channel MOSFETs with nonuniform substrate doping. A key simplifying assumption used is that the majority carriers can be represented by a sheet charge at the silicon dioxide silicon interface. Although the program is incomplete, the two dimensional Poisson equation for the potential distribution was achieved. The status of other Z-D MOSFET simulation programs is summarized.

Microstructured block copolymer surfaces for control of microbe capture and aggregation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hansen, Ryan R; Shubert, Katherine R; Morrell, Jennifer L.

2014-01-01

The capture and arrangement of surface-associated microbes is influenced by biochemical and physical properties of the substrate. In this report, we develop lectin-functionalized substrates containing patterned, three-dimensional polymeric structures of varied shapes and densities and use these to investigate the effects of topology and spatial confinement on lectin-mediated microbe capture. Films of poly(glycidyl methacrylate)-block-4,4-dimethyl-2-vinylazlactone (PGMA-b-PVDMA) were patterned on silicon surfaces into line or square grid patterns with 5 m wide features and varied edge spacing. The patterned films had three-dimensional geometries with 900 nm film thickness. After surface functionalization with wheat germ agglutinin, the size of Pseudomonas fluorescens aggregates capturedmore » was dependent on the pattern dimensions. Line patterns with edge spacing of 5 m or less led to the capture of individual microbes with minimal formation of aggregates, while grid patterns with the same spacing also captured individual microbes with further reduction in aggregation. Both geometries allowed for increases in aggregate size distribution with increased in edge spacing. These engineered surfaces combine spatial confinement with affinity-based microbe capture based on exopolysaccharide content to control the degree of microbe aggregation, and can also be used as a platform to investigate intercellular interactions and biofilm formation in microbial populations of controlled sizes.« less

Study on the fabrication of back surface reflectors in nano-crystalline silicon thin-film solar cells by using random texturing aluminum anodization

NASA Astrophysics Data System (ADS)

Shin, Kang Sik; Jang, Eunseok; Cho, Jun-Sik; Yoo, Jinsu; Park, Joo Hyung; Byungsung, O.

2015-09-01

In recent decades, researchers have improved the efficiency of amorphous silicon solar cells in many ways. One of the easiest and most practical methods to improve solar-cell efficiency is adopting a back surface reflector (BSR) as the bottom layer or as the substrate. The BSR reflects the incident light back to the absorber layer in a solar cell, thus elongating the light path and causing the so-called "light trapping effect". The elongation of the light path in certain wavelength ranges can be enhanced with the proper scale of BSR surface structure or morphology. An aluminum substrate with a surface modified by aluminum anodizing is used to improve the optical properties for applications in amorphous silicon solar cells as a BSR in this research due to the high reflectivity and the low material cost. The solar cells with a BSR were formed and analyzed by using the following procedures: First, the surface of the aluminum substrate was degreased by using acetone, ethanol and distilled water, and it was chemically polished in a dilute alkali solution. After the cleaning process, the aluminum surface's morphology was modified by using a controlled anodization in a dilute acid solution to form oxide on the surface. The oxidized film was etched off by using an alkali solution to leave an aluminum surface with randomly-ordered dimple-patterns of approximately one micrometer in size. The anodizing conditions and the anodized aluminum surfaces after the oxide layer had been removed were systematically investigated according to the applied voltage. Finally, amorphous silicon solar cells were deposited on a modified aluminum plate by using dc magnetron sputtering. The surfaces of the anodized aluminum were observed by using field-emission scanning electron microscopy. The total and the diffuse reflectances of the surface-modified aluminum sheets were measured by using UV spectroscopy. We observed that the diffuse reflectances increased with increasing anodizing voltage. The properties of the solar cells on anodized aluminum substrates were analyzed by using a solar simulator.

Low-temperature silicon thin films for large-area electronics: Device fabrication using soft lithography and laser-crystallization by sequential lateral solidification

NASA Astrophysics Data System (ADS)

Jin, Hyun-Chul

This work demonstrates possible routes for fabricating large-area electronic devices on glass or plastic substrates using low-temperature materials deposition and soft lithographic device patterning. Hydrogenated amorphous silicon (a-Si:H) and polycrystalline silicon (poly-Si) have been extensively studied as the semiconducting material for flat panel displays and solar cells. On glass substrates, we have deposited a-Si:H films at a temperature lower than 125°C, and we have used pulsed excimer laser crystallization in the sequential lateral solidification (SLS) regime to fabricate poly-Si films. We use micromolding in capillaries (MIMIC), a form of soft lithography involving micrometer-scale polymer molding, as a means to fabricate amorphous silicon thin-film transistors (TFTs), and photoconductive sensor arrays on both planar and curved substrates. The use of non-planar substrates has captured considerable attention in the field because it would open up new applications and new designs. Field-effect transistors made by SLS poly-Si show excellent mobility and on/off current ratio; however, the microstructure of the material had never been well documented. We determined the microtexture using electron backscattering diffraction (EBSD): the first crystallites formed in the a-Si layer are random; along the direction of the solidification, a strong <100> in-plane orientation quickly develops due to competitive growth and occlusion. The misorientation angle between neighboring grains is also analyzed. A large fraction of the boundaries within the material are low-angle and coincidence site lattice (CSL) types. We discuss the implications of the findings on the defect generation mechanism and on the electrical properties of the films. We have analyzed the electrical properties of SLS poly-Si films on oxidized Si wafer using the pseudo-MOSFET geometry; the majority carrier mobility is extracted from the transconductance. However, the data are non-ideal due to large contact resistance and current spreading. We discuss the future use of these electrical characterization techniques to analyze the properties of individual grain boundaries in thin film Si bicrystals formed by SLS.

High-alignment-accuracy transfer printing of passive silicon waveguide structures.

PubMed

Ye, Nan; Muliuk, Grigorij; Trindade, Antonio Jose; Bower, Chris; Zhang, Jing; Uvin, Sarah; Van Thourhout, Dries; Roelkens, Gunther

2018-01-22

We demonstrate the transfer printing of passive silicon devices on a silicon-on-insulator target waveguide wafer. Adiabatic taper structures and directional coupler structures were designed for 1310 nm and 1600 nm wavelength coupling tolerant for ± 1 µm misalignment. The release of silicon devices from the silicon substrate was realized by underetching the buried oxide layer while protecting the back-end stack. Devices were successfully picked by a PDMS stamp, by breaking the tethers that kept the silicon coupons in place on the source substrate, and printed with high alignment accuracy on a silicon photonic target wafer. Coupling losses of -1.5 +/- 0.5 dB for the adiabatic taper at 1310 nm wavelength and -0.5 +/- 0.5 dB for the directional coupler at 1600 nm wavelength are obtained.

Comparative study of initial stages of copper immersion deposition on bulk and porous silicon

NASA Astrophysics Data System (ADS)

Bandarenka, Hanna; Prischepa, Sergey L.; Fittipaldi, Rosalba; Vecchione, Antonio; Nenzi, Paolo; Balucani, Marco; Bondarenko, Vitaly

2013-02-01

Initial stages of Cu immersion deposition in the presence of hydrofluoric acid on bulk and porous silicon were studied. Cu was found to deposit both on bulk and porous silicon as a layer of nanoparticles which grew according to the Volmer-Weber mechanism. It was revealed that at the initial stages of immersion deposition, Cu nanoparticles consisted of crystals with a maximum size of 10 nm and inherited the orientation of the original silicon substrate. Deposited Cu nanoparticles were found to be partially oxidized to Cu2O while CuO was not detected for all samples. In contrast to porous silicon, the crystal orientation of the original silicon substrate significantly affected the sizes, density, and oxidation level of Cu nanoparticles deposited on bulk silicon.

Process for Polycrystalline film silicon growth

DOEpatents

Wang, Tihu; Ciszek, Theodore F.

2001-01-01

A process for depositing polycrystalline silicon on substrates, including foreign substrates, occurs in a chamber at about atmospheric pressure, wherein a temperature gradient is formed, and both the atmospheric pressure and the temperature gradient are maintained throughout the process. Formation of a vapor barrier within the chamber that precludes exit of the constituent chemicals, which include silicon, iodine, silicon diiodide, and silicon tetraiodide. The deposition occurs beneath the vapor barrier. One embodiment of the process also includes the use of a blanketing gas that precludes the entrance of oxygen or other impurities. The process is capable of repetition without the need to reset the deposition zone conditions.

Formation of ordered microphase-separated pattern during spin coating of ABC triblock copolymer.

PubMed

Huang, Weihuan; Luo, Chunxia; Zhang, Jilin; Han, Yanchun

2007-03-14

In this paper, the authors have systematically studied the microphase separation and crystallization during spin coating of an ABC triblock copolymer, polystyrene-b-poly(2-vinylpyridine)-b-poly(ethylene oxide) (PS-b-P2VP-b-PEO). The microphase separation of PS-b-P2VP-b-PEO and the crystallization of PEO blocks can be modulated by the types of the solvent and the substrate, the spinning speed, and the copolymer concentration. Ordered microphase-separated pattern, where PEO and P2VP blocks adsorbed to the substrate and PS blocks protrusions formed hexagonal dots above the P2VP domains, can only be obtained when PS-b-P2VP-b-PEO is dissolved in N,N-dimethylformamide and the films are spin coated onto the polar substrate, silicon wafers or mica. The mechanism of the formation of regular pattern by microphase separation is found to be mainly related to the inducement of the substrate (middle block P2VP wetting the polar substrate), the quick vanishment of the solvent during the early stage of the spin coating, and the slow evaporation of the remaining solvent during the subsequent stage. On the other hand, the probability of the crystallization of PEO blocks during spin coating decreases with the reduced film thickness. When the film thickness reaches a certain value (3.0 nm), the extensive crystallization of PEO is effectively prohibited and ordered microphase-separated pattern over large areas can be routinely prepared. When the film thickness exceeds another definite value (12.0 nm), the crystallization of PEO dominates the surface morphology. For films with thickness between these two values, microphase separation and crystallization can simultaneously occur.

High-T(sub c) Edge-geometry SNS Weak Links on Silicon-on-sapphire Substrates

NASA Technical Reports Server (NTRS)

Hunt, B.; Foote, M.; Pike, W.; Barner, J.; Vasquez, R.

1994-01-01

High-quality superconductor/normal-metal/superconductor(SNS) edge-geometry weak links have been produced on silicon-on-sapphire (SOS) substrates using a new SrTiO(sub 3)/'seed layer'/cubic-zirconia (YS2) buffer system.

Electron beam recrystallization of amorphous semiconductor materials

NASA Technical Reports Server (NTRS)

Evans, J. C., Jr.

1968-01-01

Nucleation and growth of crystalline films of silicon, germanium, and cadmium sulfide on substrates of plastic and glass were investigated. Amorphous films of germanium, silicon, and cadmium sulfide on amorphous substrates of glass and plastic were converted to the crystalline condition by electron bombardment.

Influence of design variables on radiation hardness of silicon MINP solar cells

NASA Technical Reports Server (NTRS)

Anderson, W. A.; Solaun, S.; Rao, B. B.; Banerjee, S.

1985-01-01

Metal-insulator-N/P silicon (MINP) solar cells were fabricated using different substrate resistivity values, different N-layer designs, and different I-layer designs. A shallow junction into an 0.3 ohm-cm substrate gave best efficiency whereas a deeper junction into a 1 to 4 ohm-cm substrate gave improved radiation hardness. I-layer design variation did little to influence radiation hardness.

Environmental barrier coating

DOEpatents

Pujari, Vimal K.; Vartabedian, Ara; Collins, William T.; Woolley, David; Bateman, Charles

2012-12-18

The present invention relates generally to a multi-layered article suitable for service in severe environments. The article may be formed of a substrate, such as silicon carbide and/or silicon nitride. The substrate may have a first layer of a mixture of a rare earth silicate and Cordierite. The substrate may also have a second layer of a rare earth silicate or a mixture of a rare earth silicate and cordierite.

Development of Mullite Substrates and Containers

NASA Technical Reports Server (NTRS)

Sibold, J. D.

1979-01-01

The mullite-molten silicon interaction was evaluated through fabrication of a series of bodies made with variations in density, alumina-silica ratio, and glass-crystalline ratio. The materials were tested in a sessile drop technique. None of the variations stood up to extended exposure to molten silicon sufficiently to be recommended as a container material. However, directional solidification experiments suggest that, under proper conditions, contamination of the silicon by mullite containers can be minimized. To improve an already good thermal expansion match between mullite and silicon, compositional variations were studied. Altering of the alumina-silica ratio was determined to give a continuously varying thermal expansion. A standard mullite composition was selected and substrates 40 x 4 x .040 inches were fabricated. Slotted substrates of various configurations and various compositions were also fabricated.

Fabrication of silicon-embedded low resistance high-aspect ratio planar copper microcoils

NASA Astrophysics Data System (ADS)

Syed Mohammed, Zishan Ali; Puiu, Poenar Daniel; Aditya, Sheel

2018-01-01

Low resistance is an important requirement for microcoils which act as a signal receiver to ensure low thermal noise during signal detection. High-aspect ratio (HAR) planar microcoils entrenched in blind silicon trenches have features that make them more attractive than their traditional counterparts employing electroplating through a patterned thick polymer or achieved through silicon vias. However, challenges met in fabrication of such coils have not been discussed in detail until now. This paper reports the realization of such HAR microcoils embedded in Si blind trenches, fabricated with a single lithography step by first etching blind trenches in the silicon substrate with an aspect ratio of almost 3∶1 and then filling them up using copper electroplating. The electroplating was followed by chemical wet etching as a faster way of removing excess copper than traditional chemical mechanical polishing. Electrical resistance was further reduced by annealing the microcoils. The process steps and challenges faced in the realization of such structures are reported here followed by their electrical characterization. The obtained electrical resistances are then compared with those of other similar microcoils embedded in blind vias.

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

PubMed

Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

2008-07-30

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

Photolithography and Fluorescence Correlation Spectroscopy used to examine the rates of exchange in reverse micelle systems

NASA Astrophysics Data System (ADS)

Norris, Zach; Mawson, Cara; Johnson, Kyron; Kessler, Sarah; Rebecca, Anne; Wolf, Nathan; Lim, Michael; Nucci, Nathaniel

Reverse micelles are molecular complexes that encapsulate a nanoscale pool of water in a surfactant shell dissolved in non-polar solvent. These complexes have a wide range of applications, and in all cases, the degree to which reverse micelles (RM) exchange their contents is relevant for their use. Despite its importance, this aspect of RM behavior is poorly understood. Photolithography is employed here to create micro and nano scale fluidic systems in which mixing rates can be precisely measured using fluorescence correlation spectroscopy (FCS). Micro-channel patterns are etched using reactive ion etching process into a layer of silicon dioxide on crystalline silicon substrates. Solutions containing mixtures of reverse micelles, proteins, and fluorophores are placed into reservoirs in the patterns, while diffusion and exchange between RMs is monitored using a FCS system built from a modified confocal Raman spectrometer. Using this approach, the diffusion and exchange rates for RM systems are measured as a function of the components of the RM mixture. Funding provided by Rowan University.

Profiling of patterned metal layers by laser ablation inductively coupled plasma mass spectrometry (LA-ICP-MS)

NASA Astrophysics Data System (ADS)

Bi, Melody; Ruiz, Antonio M.; Gornushkin, Igor; Smith, Ben W.; Winefordner, James D.

2000-02-01

Laser ablation inductively coupled plasma mass spectrometry (LA-ICP-MS) was used for profiling patterned thin metal layers on a polymer/silicon substrate. The parameters of the laser and ICP-MS operating conditions have been studied and optimized for this purpose. A new laser ablation chamber was designed and built to achieve the best spatial resolution. The results of the profiling by LA-ICP-MS were compared to those obtained from a laser ablation optical emission spectrometry (LA-OES) instrument, which measured the emission of the plasma at the sample surface, and thus, eliminated the time delay caused by the sample transport into the ICP-MS system. Emission spectra gave better spatial resolution than mass spectra. However, LA-ICP-MS provided much better sensitivity and was able to profile thin metal layers (on the order of a few nanometers) on the silicon surface. A lateral spatial resolution of 45 μm was achieved.

Laser-assisted solar cell metallization processing

NASA Technical Reports Server (NTRS)

Dutta, S.

1984-01-01

Laser assisted processing techniques utilized to produce the fine line, thin metal grid structures that are required to fabricate high efficiency solar cells are investigated. The tasks comprising these investigations are summarized. Metal deposition experiments are carried out utilizing laser assisted pyrolysis of a variety of metal bearing polymer films and metalloorganic inks spun onto silicon substrates. Laser decomposition of spun on silver neodecanoate ink yields very promising results. Solar cell comb metallization patterns are written using this technique.

Vertical group III-V nanowires on si, heterostructures, flexible arrays and fabrication

DOEpatents

Wang, Deli; Soci, Cesare; Bao, Xinyu; Wei, Wei; Jing, Yi; Sun, Ke

2015-01-13

Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures. An array of Group III-V nanowire structures is embedded in polymer. A fabrication method forms the vertical nanowires on a substrate, e.g., a silicon substrate. Preferably, the nanowires are formed by the preferred methods for fabrication of Group III-V nanowires on silicon. Devices can be formed with core/shell and core/multi-shell nanowires and the devices are released from the substrate upon which the nanowires were formed to create a flexible structure that includes an array of vertical nanowires embedded in polymer.

Investigation of ZnSe-coated silicon substrates for GaAs solar cells

NASA Technical Reports Server (NTRS)

Huber, Daniel A.; Olsen, Larry C.; Dunham, Glen; Addis, F. William

1993-01-01

Studies are being carried out to determine the feasibility of using ZnSe as a buffer layer for GaAs solar cells grown on silicon. This study was motivated by reports in the literature indicating ZnSe films had been grown by metallorganic chemical vapor deposition (MOCVD) onto silicon with EPD values of 2 x 10(exp 5) cm(sup -2), even though the lattice mismatch between silicon and ZnSe is 4.16 percent. These results combined with the fact that ZnSe and GaAs are lattice matched to within 0.24 percent suggest that the prospects for growing high efficiency GaAs solar cells onto ZnSe-coated silicon are very good. Work to date has emphasized development of procedures for MOCVD growth of (100) ZnSe onto (100) silicon wafers, and subsequent growth of GaAs films on ZnSe/Si substrates. In order to grow high quality single crystal GaAs with a (100) orientation, which is desirable for solar cells, one must grow single crystal (100) ZnSe onto silicon substrates. A process for growth of (100) ZnSe was developed involving a two-step growth procedure at 450 C. Single crystal, (100) GaAs films were grown onto the (100) ZnSe/Si substrates at 610 C that are adherent and specular. Minority carrier diffusion lengths for the GaAs films grown on ZnSe/Si substrates were determined from photoresponse properties of Al/GaAs Schottky barriers. Diffusion lengths for n-type GaAs films are currently on the order of 0.3 microns compared to 2.0 microns for films grown simultaneously by homoepitaxy.

Ion irradiation of the native oxide/silicon surface increases the thermal boundary conductance across aluminum/silicon interfaces

NASA Astrophysics Data System (ADS)

Gorham, Caroline S.; Hattar, Khalid; Cheaito, Ramez; Duda, John C.; Gaskins, John T.; Beechem, Thomas E.; Ihlefeld, Jon F.; Biedermann, Laura B.; Piekos, Edward S.; Medlin, Douglas L.; Hopkins, Patrick E.

2014-07-01

The thermal boundary conductance across solid-solid interfaces can be affected by the physical properties of the solid boundary. Atomic composition, disorder, and bonding between materials can result in large deviations in the phonon scattering mechanisms contributing to thermal boundary conductance. Theoretical and computational studies have suggested that the mixing of atoms around an interface can lead to an increase in thermal boundary conductance by creating a region with an average vibrational spectra of the two materials forming the interface. In this paper, we experimentally demonstrate that ion irradiation and subsequent modification of atoms at solid surfaces can increase the thermal boundary conductance across solid interfaces due to a change in the acoustic impedance of the surface. We measure the thermal boundary conductance between thin aluminum films and silicon substrates with native silicon dioxide layers that have been subjected to proton irradiation and post-irradiation surface cleaning procedures. The thermal boundary conductance across the Al/native oxide/Si interfacial region increases with an increase in proton dose. Supported with statistical simulations, we hypothesize that ion beam mixing of the native oxide and silicon substrate within ˜2.2nm of the silicon surface results in the observed increase in thermal boundary conductance. This ion mixing leads to the spatial gradation of the silicon native oxide into the silicon substrate, which alters the acoustic impedance and vibrational characteristics at the interface of the aluminum film and native oxide/silicon substrate. We confirm this assertion with picosecond acoustic analyses. Our results demonstrate that under specific conditions, a "more disordered and defected" interfacial region can have a lower resistance than a more "perfect" interface.

Ultrasmooth Patterned Metals for Plasmonics and Metamaterials

NASA Astrophysics Data System (ADS)

Nagpal, Prashant; Lindquist, Nathan C.; Oh, Sang-Hyun; Norris, David J.

2009-07-01

Surface plasmons are electromagnetic waves that can exist at metal interfaces because of coupling between light and free electrons. Restricted to travel along the interface, these waves can be channeled, concentrated, or otherwise manipulated by surface patterning. However, because surface roughness and other inhomogeneities have so far limited surface-plasmon propagation in real plasmonic devices, simple high-throughput methods are needed to fabricate high-quality patterned metals. We combined template stripping with precisely patterned silicon substrates to obtain ultrasmooth pure metal films with grooves, bumps, pyramids, ridges, and holes. Measured surface-plasmon-propagation lengths on the resulting surfaces approach theoretical values for perfectly flat films. With the use of our method, we demonstrated structures that exhibit Raman scattering enhancements above 107 for sensing applications and multilayer films for optical metamaterials.

Tuning cell adhesion by direct nanostructuring silicon into cell repulsive/adhesive patterns

DOE Office of Scientific and Technical Information (OSTI.GOV)

Premnath, Priyatha, E-mail: priyatha.premnath@ryerson.ca; Tavangar, Amirhossein, E-mail: atavanga@ryerson.ca; Tan, Bo, E-mail: tanbo@ryerson.ca

2015-09-10

Developing platforms that allow tuning cell functionality through incorporating physical, chemical, or mechanical cues onto the material surfaces is one of the key challenges in research in the field of biomaterials. In this respect, various approaches have been proposed and numerous structures have been developed on a variety of materials. Most of these approaches, however, demand a multistep process or post-chemical treatment. Therefore, a simple approach would be desirable to develop bio-functionalized platforms for effectively modulating cell adhesion and consequently programming cell functionality without requiring any chemical or biological surface treatment. This study introduces a versatile yet simple laser approachmore » to structure silicon (Si) chips into cytophobic/cytophilic patterns in order to modulate cell adhesion and proliferation. These patterns are fabricated on platforms through direct laser processing of Si substrates, which renders a desired computer-generated configuration into patterns. We investigate the morphology, chemistry, and wettability of the platform surfaces. Subsequently, we study the functionality of the fabricated platforms on modulating cervical cancer cells (HeLa) behaviour. The results from in vitro studies suggest that the nanostructures efficiently repel HeLa cells and drive them to migrate onto untreated sites. The study of the morphology of the cells reveals that cells evade the cytophobic area by bending and changing direction. Additionally, cell patterning, cell directionality, cell channelling, and cell trapping are achieved by developing different platforms with specific patterns. The flexibility and controllability of this approach to effectively structure Si substrates to cell-repulsive and cell-adhesive patterns offer perceptible outlook for developing bio-functionalized platforms for a variety of biomedical devices. Moreover, this approach could pave the way for developing anti-cancer platforms that selectively repel cancer cells while favoring the adhesion of normal cells. - Highlights: • Si platforms with cytophobic/philic patterns were developed to program cell growth. • Both nanotopography and chemistry contributed to the cytophobic property. • Cytophobic zones efficiently repel and drive HeLa cells to migrate to adhesive sites. • The approach enables cell patterning, directionality, channelling, and trapping. • This approach paves the way for developing anti-cancer platforms.« less

Deposition of hydrogenated silicon clusters for efficient epitaxial growth.

PubMed

Le, Ha-Linh Thi; Jardali, Fatme; Vach, Holger

2018-06-13

Epitaxial silicon thin films grown from the deposition of plasma-born hydrogenated silicon nanoparticles using plasma-enhanced chemical vapor deposition have widely been investigated due to their potential applications in photovoltaic and nanoelectronic device technologies. However, the optimal experimental conditions and the underlying growth mechanisms leading to the high-speed epitaxial growth of thin silicon films from hydrogenated silicon nanoparticles remain far from being understood. In the present work, extensive molecular dynamics simulations were performed to study the epitaxial growth of silicon thin films resulting from the deposition of plasma-born hydrogenated silicon clusters at low substrate temperatures under realistic reactor conditions. There is strong evidence that a temporary phase transition of the substrate area around the cluster impact site to the liquid state is necessary for the epitaxial growth to take place. We predict further that a non-normal incidence angle for the cluster impact significantly facilitates the epitaxial growth of thin crystalline silicon films.

Formation of microchannels from low-temperature plasma-deposited silicon oxynitride

DOEpatents

Matzke, Carolyn M.; Ashby, Carol I. H.; Bridges, Monica M.; Manginell, Ronald P.

2000-01-01

A process for forming one or more fluid microchannels on a substrate is disclosed that is compatible with the formation of integrated circuitry on the substrate. The microchannels can be formed below an upper surface of the substrate, above the upper surface, or both. The microchannels are formed by depositing a covering layer of silicon oxynitride over a mold formed of a sacrificial material such as photoresist which can later be removed. The silicon oxynitride is deposited at a low temperature (.ltoreq.100.degree. C.) and preferably near room temperature using a high-density plasma (e.g. an electron-cyclotron resonance plasma or an inductively-coupled plasma). In some embodiments of the present invention, the microchannels can be completely lined with silicon oxynitride to present a uniform material composition to a fluid therein. The present invention has applications for forming microchannels for use in chromatography and electrophoresis. Additionally, the microchannels can be used for electrokinetic pumping, or for localized or global substrate cooling.

Ablative performance of uncoated silicone-modified and shuttle baseline reinforced carbon composites

NASA Technical Reports Server (NTRS)

Dicus, D. L.; Hopko, R. N.; Brown, R. D.

1976-01-01

The relative ablative performance of uncoated silicone-modified reinforced carbon composite (RCC) and uncoated shuttle baseline RCC substrates was investigated. The test specimens were 13 plies (5.3 to 5.8 millimeters) thick and had a 25-millimeter-diameter test face. Prior to arc tunnel testing, all specimens were subjected to a heat treatment simulating the RCC coating process. During arc tunnel testing, the specimens were exposed to cold wall heating rates of 178 to 529 kilowatts/sq m and stagnation pressures ranging from 0.015 to 0.046 atmosphere at Mach 4.6 in air, with and without preheating in nitrogen. The results show that the ablative performance of uncoated silicone-modified RCC substrates is significantly superior to that of uncoated shuttle baseline RCC substrates over the range of heating conditions used. These results indicate that the silicone-modified RCC substrate would yield a substantially greater safety margin in the event of complete coating loss on the shuttle orbiter.

Profilometry of thin films on rough substrates by Raman spectroscopy

PubMed Central

Ledinský, Martin; Paviet-Salomon, Bertrand; Vetushka, Aliaksei; Geissbühler, Jonas; Tomasi, Andrea; Despeisse, Matthieu; De Wolf , Stefaan; Ballif , Christophe; Fejfar, Antonín

2016-01-01

Thin, light-absorbing films attenuate the Raman signal of underlying substrates. In this article, we exploit this phenomenon to develop a contactless thickness profiling method for thin films deposited on rough substrates. We demonstrate this technique by probing profiles of thin amorphous silicon stripes deposited on rough crystalline silicon surfaces, which is a structure exploited in high-efficiency silicon heterojunction solar cells. Our spatially-resolved Raman measurements enable the thickness mapping of amorphous silicon over the whole active area of test solar cells with very high precision; the thickness detection limit is well below 1 nm and the spatial resolution is down to 500 nm, limited only by the optical resolution. We also discuss the wider applicability of this technique for the characterization of thin layers prepared on Raman/photoluminescence-active substrates, as well as its use for single-layer counting in multilayer 2D materials such as graphene, MoS2 and WS2. PMID:27922033

RF sputtered silicon and hafnium nitrides as applied to 440C steel

NASA Technical Reports Server (NTRS)

Grill, A.; Aron, P. R.

1984-01-01

Silicon nitride and hafnium nitride coatings were deposited on oxidized and unoxidized 440C stainless steel substrates. Sputtering was done in mixtures of argon and nitrogen gases from pressed powder silicon nitride and from hafnium metal targets. The coatings and the interface between the coating and substrate were investigated by X-ray diffractometry, scanning electron microscopy, energy dispersive X-ray analysis and Auger electron spectroscopy. Oxide was found at all interfaces with an interface width of at least 600 A for the oxidized substrates and at least 300 A for the unoxidized substrates. Scratch test results demonstrate that the adhesion of hafnium nitride to both oxidized and unoxidized 440C is superior to that of silicon nitride. Oxidized 440C is found to have increased adhesion, to both nitrides, over that of unoxidized 440C. Coatings of both nitrides deposited at 8 mtorr were found to have increased adhesion to both oxidized and unoxidized 440C over those deposited at 20 mtorr.

Plasma cleaning of nanoparticles from EUV mask materials by electrostatics

NASA Astrophysics Data System (ADS)

Lytle, W. M.; Raju, R.; Shin, H.; Das, C.; Neumann, M. J.; Ruzic, D. N.

2008-03-01

Particle contamination on surfaces used in extreme ultraviolet (EUV) mask blank deposition, mask fabrication, and patterned mask handling must be avoided since the contamination can create significant distortions and loss of reflectivity. Particles on the order of 10nm are problematic during MLM mirror fabrication, since the introduced defects disrupt the local Bragg planes. The most serious problem is the accumulation of particles on surfaces of patterned blanks during EUV light exposure, since > 25nm particles will be printed without an out-of-focus pellicle. Particle contaminants are also a problem with direct imprint processes since defects are printed every time. Plasma Assisted Cleaning by Electrostatics (PACE) works by utilizing a helicon plasma as well as a pulsed DC substrate bias to charge particle and repel them electrostatically from the surface. Removal of this nature is a dry cleaning method and removes contamination perpendicular from the surface instead of rolling or sweeping the particles off the surface, a benefit when cleaning patterned surfaces where contamination can be rolled or trapped between features. Also, an entire mask can be cleaned at once since the plasma can cover the entire surface, thus there is no need to focus in on an area to clean. Sophisticated particle contamination detection system utilizing high power laser called DEFCON is developed to analyze the particle removal after PACE cleaning process. PACE has shown greater than 90 % particle removal efficiencies for 30 to 220 nm PSL particles on ruthenium capped quartz. Removal results for silicon surfaces and quartz surfaces show similar removal efficiencies. Results of cleaning 80 nm PSL spheres from silicon substrates will be shown.

Plasmonic and silicon spherical nanoparticle antireflective coatings

NASA Astrophysics Data System (ADS)

Baryshnikova, K. V.; Petrov, M. I.; Babicheva, V. E.; Belov, P. A.

2016-03-01

Over the last decade, plasmonic antireflecting nanostructures have been extensively studied to be utilized in various optical and optoelectronic systems such as lenses, solar cells, photodetectors, and others. The growing interest to all-dielectric photonics as an alternative optical technology along with plasmonics motivates us to compare antireflective properties of plasmonic and all-dielectric nanoparticle coatings based on silver and crystalline silicon respectively. Our simulation results for spherical nanoparticles array on top of amorphous silicon show that both silicon and silver coatings demonstrate strong antireflective properties in the visible spectral range. For the first time, we show that zero reflectance from the structure with silicon coatings originates from the destructive interference of electric- and magnetic-dipole responses of nanoparticle array with the wave reflected from the substrate, and we refer to this reflection suppression as substrate-mediated Kerker effect. We theoretically compare the silicon and silver coating effectiveness for the thin-film photovoltaic applications. Silver nanoparticles can be more efficient, enabling up to 30% increase of the overall absorbance in semiconductor layer. Nevertheless, silicon coatings allow up to 64% absorbance increase in the narrow band spectral range because of the substrate-mediated Kerker effect, and band position can be effectively tuned by varying the nanoparticles sizes.

Plasmonic and silicon spherical nanoparticle antireflective coatings

PubMed Central

Baryshnikova, K. V.; Petrov, M. I.; Babicheva, V. E.; Belov, P. A.

2016-01-01

Over the last decade, plasmonic antireflecting nanostructures have been extensively studied to be utilized in various optical and optoelectronic systems such as lenses, solar cells, photodetectors, and others. The growing interest to all-dielectric photonics as an alternative optical technology along with plasmonics motivates us to compare antireflective properties of plasmonic and all-dielectric nanoparticle coatings based on silver and crystalline silicon respectively. Our simulation results for spherical nanoparticles array on top of amorphous silicon show that both silicon and silver coatings demonstrate strong antireflective properties in the visible spectral range. For the first time, we show that zero reflectance from the structure with silicon coatings originates from the destructive interference of electric- and magnetic-dipole responses of nanoparticle array with the wave reflected from the substrate, and we refer to this reflection suppression as substrate-mediated Kerker effect. We theoretically compare the silicon and silver coating effectiveness for the thin-film photovoltaic applications. Silver nanoparticles can be more efficient, enabling up to 30% increase of the overall absorbance in semiconductor layer. Nevertheless, silicon coatings allow up to 64% absorbance increase in the narrow band spectral range because of the substrate-mediated Kerker effect, and band position can be effectively tuned by varying the nanoparticles sizes. PMID:26926602

Evaluation of the Effect of Silicone Contamination on Various Bond Systems and the Feasibility of Removing the Contamination

NASA Technical Reports Server (NTRS)

Stanley, Stephanie D.

2008-01-01

Silicone is a contaminant that can cause catastrophic failure of a bond system depending on the materials and processes used to fabricate the bond system, Unfortunately, more and more materials are fabricated using silicone. The purpose of this testing was to evaluate which bond systems are sensitive to silicone contamination and whether or not a cleaning process could be utilized to remove the silicone to bring the bond system performance back to baseline. Due to the extensive nature of the testing attempts will be made to generalize the understanding within classes of substrates, bond systems, and surface preparation and cleaning methods. This study was done by contaminating various meta! (steel, inconel, and aluminum), phenolic (carbon cloth phenolic and glass cloth phenolic), and rubber (natural rubber, asbestos-silicone dioxide filled natural butyldiene rubber, silica-filled ethylene propylenediene monomer, and carbon-filled ethylene propylenediene monomer) substrates which were then bonded using various adhesives and coatings (epoxy-based adhesives, paints, ablative compounds, and Chemlok adhesives) to determine the effect silicone contamination has on a given bond system's performance. The test configurations depended on the bond system being evaluated. The study also evaluated the feasibility of removing the silicone contamination by cleaning the contaminated substrate prior to bonding. The cleaning processes also varied depending on bond system.

In situ micro-Raman analysis and X-ray diffraction of nickel silicide thin films on silicon.

PubMed

Bhaskaran, M; Sriram, S; Perova, T S; Ermakov, V; Thorogood, G J; Short, K T; Holland, A S

2009-01-01

This article reports on the in situ analysis of nickel silicide (NiSi) thin films formed by thermal processing of nickel thin films deposited on silicon substrates. The in situ techniques employed for this study include micro-Raman spectroscopy (microRS) and X-ray diffraction (XRD); in both cases the variations for temperatures up to 350 degrees C has been studied. Nickel silicide thin films formed by vacuum annealing of nickel on silicon were used as a reference for these measurements. In situ analysis was carried out on nickel thin films on silicon, while the samples were heated from room temperature to 350 degrees C. Data was gathered at regular temperature intervals and other specific points of interest (such as 250 degrees C, where the reaction between nickel and silicon to form Ni(2)Si is expected). The transformations from the metallic state, through the intermediate reaction states, until the desired metal-silicon reaction product is attained, are discussed. The evolution of nickel silicide from the nickel film can be observed from both the microRS and XRD in situ studies. Variations in the evolution of silicide from metal for different silicon substrates are discussed, and these include (100) n-type, (100) p-type, and (110) p-type silicon substrates.

Patterned Growth of Carbon Nanotubes or Nanofibers

NASA Technical Reports Server (NTRS)

Delzeit, Lance D.

2004-01-01

A method and apparatus for the growth of carbon nanotubes or nanofibers in a desired pattern has been invented. The essence of the method is to grow the nanotubes or nanofibers by chemical vapor deposition (CVD) onto a patterned catalyst supported by a substrate. The figure schematically depicts salient aspects of the method and apparatus in a typical application. A substrate is placed in a chamber that contains both ion-beam sputtering and CVD equipment. The substrate can be made of any of a variety of materials that include several forms of silicon or carbon, and selected polymers, metals, ceramics, and even some natural minerals and similar materials. Optionally, the substrate is first coated with a noncatalytic metal layer (which could be a single layer or could comprise multiple different sublayers) by ion-beam sputtering. The choice of metal(s) and thickness(es) of the first layer (if any) and its sublayers (if any) depends on the chemical and electrical properties required for subsequent deposition of the catalyst and the subsequent CVD of the carbon nanotubes. A typical first-sublayer metal is Pt, Pd, Cr, Mo, Ti, W, or an alloy of two or more of these elements. A typical metal for the second sublayer or for an undivided first layer is Al at a thickness .1 nm or Ir at a thickness .5 nm. Proper choice of the metal for a second sublayer of a first layer makes it possible to use a catalyst that is chemically incompatible with the substrate. In the next step, a mask having holes in the desired pattern is placed over the coated substrate. The catalyst is then deposited on the coated substrate by ion-beam sputtering through the mask. Optionally, the catalyst could be deposited by a technique other than sputtering and/or patterned by use of photolithography, electron- beam lithography, or another suitable technique. The catalytic metal can be Fe, Co, Ni, or an alloy of two or more of these elements, deposited to a typical thickness in the range from 0.1 to 20 nm.

Rapid Covalent Modification of Silicon Oxide Surfaces through Microwave-Assisted Reactions with Alcohols.

PubMed

Lee, Austin W H; Gates, Byron D

2016-07-26

We demonstrate the method of a rapid covalent modification of silicon oxide surfaces with alcohol-containing compounds with assistance by microwave reactions. Alcohol-containing compounds are prevalent reagents in the laboratory, which are also relatively easy to handle because of their stability against exposure to atmospheric moisture. The condensation of these alcohols with the surfaces of silicon oxides is often hindered by slow reaction kinetics. Microwave radiation effectively accelerates this condensation reaction by heating the substrates and/or solvents. A variety of substrates were modified in this demonstration, such as silicon oxide films of various thicknesses, glass substrates such as microscope slides (soda lime), and quartz. The monolayers prepared through this strategy demonstrated the successful formation of covalent surface modifications of silicon oxides with water contact angles of up to 110° and typical hysteresis values of 2° or less. An evaluation of the hydrolytic stability of these monolayers demonstrated their excellent stability under acidic conditions. The techniques introduced in this article were successfully applied to tune the surface chemistry of silicon oxides to achieve hydrophobic, oleophobic, and/or charged surfaces.

Mechanically flexible optically transparent silicon fabric with high thermal budget devices from bulk silicon (100)

NASA Astrophysics Data System (ADS)

Hussain, Muhammad M.; Rojas, Jhonathan P.; Torres Sevilla, Galo A.

2013-05-01

Today's information age is driven by silicon based electronics. For nearly four decades semiconductor industry has perfected the fabrication process of continuingly scaled transistor - heart of modern day electronics. In future, silicon industry will be more pervasive, whose application will range from ultra-mobile computation to bio-integrated medical electronics. Emergence of flexible electronics opens up interesting opportunities to expand the horizon of electronics industry. However, silicon - industry's darling material is rigid and brittle. Therefore, we report a generic batch fabrication process to convert nearly any silicon electronics into a flexible one without compromising its (i) performance; (ii) ultra-large-scale-integration complexity to integrate billions of transistors within small areas; (iii) state-of-the-art process compatibility, (iv) advanced materials used in modern semiconductor technology; (v) the most widely used and well-studied low-cost substrate mono-crystalline bulk silicon (100). In our process, we make trenches using anisotropic reactive ion etching (RIE) in the inactive areas (in between the devices) of a silicon substrate (after the devices have been fabricated following the regular CMOS process), followed by a dielectric based spacer formation to protect the sidewall of the trench and then performing an isotropic etch to create caves in silicon. When these caves meet with each other the top portion of the silicon with the devices is ready to be peeled off from the bottom silicon substrate. Release process does not need to use any external support. Released silicon fabric (25 μm thick) is mechanically flexible (5 mm bending radius) and the trenches make it semi-transparent (transparency of 7%).

Some material structural properties of SOI substrates produced by SDB technology

NASA Astrophysics Data System (ADS)

Hui, Li; Guo-Liang, Sun; Juan, Zhan; Qin-Yi, Tong

1987-10-01

SOI substrates have been produced by silicon direct bonding (SDB) technology. Thermal oxides ranging in thickness from native oxide to 1 μm or even more, on either or both wafers have been bonded successfully. The fracture strength of the SOI layer is 130-200 kg/cm 2 which is similar to the value of intrinsic bulk silicon. Dislocations have been shown to be concentrated on the backsides of the substrate and no additional defects have been developed within 80 μm of the Si-SiO 2 bonding area. Mobility and minority carrier lifetime similar to that of the original bulk silicon have been obtained after annealing.

Efficient Surface Enhanced Raman Scattering substrates from femtosecond laser based fabrication

NASA Astrophysics Data System (ADS)

Parmar, Vinod; Kanaujia, Pawan K.; Bommali, Ravi Kumar; Vijaya Prakash, G.

2017-10-01

A fast and simple femtosecond laser based methodology for efficient Surface Enhanced Raman Scattering (SERS) substrate fabrication has been proposed. Both nano scaffold silicon (black silicon) and gold nanoparticles (Au-NP) are fabricated by femtosecond laser based technique for mass production. Nano rough silicon scaffold enables large electromagnetic fields for the localized surface plasmons from decorated metallic nanoparticles. Thus giant enhancement (approximately in the order of 104) of Raman signal arises from the mixed effects of electron-photon-phonon coupling, even at nanomolar concentrations of test organic species (Rhodamine 6G). Proposed process demonstrates the low-cost and label-less application ability from these large-area SERS substrates.

Deposition of device quality, low hydrogen content, hydrogenated amorphous silicon at high deposition rates with increased stability using the hot wire filament technique

DOEpatents

Molenbroek, Edith C.; Mahan, Archie Harvin; Gallagher, Alan C.

2000-09-26

A method or producing hydrogenated amorphous silicon on a substrate, comprising the steps of: positioning the substrate in a deposition chamber at a distance of about 0.5 to 3.0 cm from a heatable filament in the deposition chamber; maintaining a pressure in said deposition chamber in the range of about 10 to 100 millitorr and pressure times substrate-filament spacing in the range of about 10 to 100 millitorr-cm, heating the filament to a temperature in the range of about 1,500 to 2,000.degree. C., and heating the substrate to a surface temperature in the range of about 280 to 475.degree. C.; and flowing silicohydride gas into the deposition chamber with said heated filament, decomposing said silicohydride gas into silicon and hydrogen atomic species and allowing products of gas reactions between said atomic species and the silicohydride gas to migrate to and deposit on said substrate while adjusting and maintaining said pressure times substrate-filament spacing in said deposition chamber at a value in said 10 to 100 millitorr range to produce statistically about 3 to 50 atomic collisions between the silicon and hydrogen atomic species migrating to said substrate and undecomposed molecules of the silane or other silicohydride gas in the deposition chamber.

Vacuum die attach for integrated circuits

DOEpatents

Schmitt, E.H.; Tuckerman, D.B.

1991-09-10

A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required. 1 figure.

Vacuum die attach for integrated circuits

DOEpatents

Schmitt, Edward H.; Tuckerman, David B.

1991-01-01

A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required.

Method of making a ceramic with preferential oxygen reactive layer

NASA Technical Reports Server (NTRS)

Wang, Hongyu (Inventor); Luthra, Krishan Lal (Inventor)

2003-01-01

A method of forming an article. The method comprises forming a silicon-based substrate that is oxidizable by reaction with an oxidant to form at least one gaseous product and applying an intermediate layer/coating onto the substrate, wherein the intermediate layer/coating is oxidizable to a nongaseous product by reaction with the oxidant in preference to reaction of the silicon-containing substrate with the oxidant.

Formation of thin-film resistors on silicon substrates

DOEpatents

Schnable, George L.; Wu, Chung P.

1988-11-01

The formation of thin-film resistors by the ion implantation of a metallic conductive layer in the surface of a layer of phosphosilicate glass or borophosphosilicate glass which is deposited on a silicon substrate. The metallic conductive layer materials comprise one of the group consisting of tantalum, ruthenium, rhodium, platinum and chromium silicide. The resistor is formed and annealed prior to deposition of metal, e.g. aluminum, on the substrate.

NT-SiC (new-technology silicon carbide) : Φ 650mm optical space mirror substrate of high-strength reaction-sintered silicon carbide

NASA Astrophysics Data System (ADS)

Suyama, Shoko; Itoh, Yoshiyasu; Tsuno, Katsuhiko; Ohno, Kazuhiko

2005-08-01

Silicon carbide (SiC) is the most advantageous as the material of various telescope mirrors, because of high stiffness, low density, low coefficient of thermal expansion, high thermal conductivity and thermal stability. Newly developed high-strength reaction-sintered silicon carbide (NTSIC), which has two times higher strength than sintered SiC, is one of the most promising candidates for lightweight optical mirror substrate, because of fully dense, lightweight, small sintering shrinkage (+/-1 %), good shape capability and low processing temperature. In this study, 650mm in diameter mirror substrate of NTSIC was developed for space telescope applications. Three developed points describe below. The first point was to realize the lightweight to thin the thickness of green bodies. Ribs down to 3mm thickness can be obtained by strengthen the green body. The second point was to enlarge the mirror size. 650mm in diameter of mirror substrate can be fabricated with enlarging the diameter in order. The final point was to realize the homogeneity of mirror substrate. Some properties, such as density, bending strength, coefficient of thermal expansion, Young's modulus, Poisson's ratio, fracture toughness, were measured by the test pieces cutting from the fabricated mirror substrates.

Silicon Micromachined Microlens Array for THz Antennas

NASA Technical Reports Server (NTRS)

Lee, Choonsup; Chattopadhyay, Goutam; Mehdi, IImran; Gill, John J.; Jung-Kubiak, Cecile D.; Llombart, Nuria

2013-01-01

5 5 silicon microlens array was developed using a silicon micromachining technique for a silicon-based THz antenna array. The feature of the silicon micromachining technique enables one to microfabricate an unlimited number of microlens arrays at one time with good uniformity on a silicon wafer. This technique will resolve one of the key issues in building a THz camera, which is to integrate antennas in a detector array. The conventional approach of building single-pixel receivers and stacking them to form a multi-pixel receiver is not suited at THz because a single-pixel receiver already has difficulty fitting into mass, volume, and power budgets, especially in space applications. In this proposed technique, one has controllability on both diameter and curvature of a silicon microlens. First of all, the diameter of microlens depends on how thick photoresist one could coat and pattern. So far, the diameter of a 6- mm photoresist microlens with 400 m in height has been successfully microfabricated. Based on current researchers experiences, a diameter larger than 1-cm photoresist microlens array would be feasible. In order to control the curvature of the microlens, the following process variables could be used: 1. Amount of photoresist: It determines the curvature of the photoresist microlens. Since the photoresist lens is transferred onto the silicon substrate, it will directly control the curvature of the silicon microlens. 2. Etching selectivity between photoresist and silicon: The photoresist microlens is formed by thermal reflow. In order to transfer the exact photoresist curvature onto silicon, there needs to be etching selectivity of 1:1 between silicon and photoresist. However, by varying the etching selectivity, one could control the curvature of the silicon microlens. The figure shows the microfabricated silicon microlens 5 x5 array. The diameter of the microlens located in the center is about 2.5 mm. The measured 3-D profile of the microlens surface has a smooth curvature. The measured height of the silicon microlens is about 280 microns. In this case, the original height of the photoresist was 210 microns. The change was due to the etching selectivity of 1.33 between photoresist and silicon. The measured surface roughness of the silicon microlens shows the peak-to-peak surface roughness of less than 0.5 microns, which is adequate in THz frequency. For example, the surface roughness should be less than 7 microns at 600 GHz range. The SEM (scanning electron microscope) image of the microlens confirms the smooth surface. The beam pattern at 550 GHz shows good directivity.

Silicon accumulation and distribution in petunia and sunflower

USDA-ARS?s Scientific Manuscript database

Silicon (Si) is a beneficial element that has been shown to protect plants during periods of abiotic and biotic stress. Plant-available Si can be supplied through substrate components, substrate amendments, liquid fertilization, or foliar sprays. The objective of this study was to compare Si accum...

Microdynamic Devices Fabricated on Silicon-On-Sapphire Substrates.

DTIC Science & Technology

Silicon-on-sapphire substrates are provided for the fabrication of micromechanical devices, such as micromotors . The high voltage stand-off...a consequence, the electrostatically driven devices, micromotors , can be incorporated in the integrated circuits and yet be powered at elevated voltages to increase their work potential.

Tuning the Phase and Microstructural Properties of TiO2 Films Through Pulsed Laser Deposition and Exploring Their Role as Buffer Layers for Conductive Films

NASA Astrophysics Data System (ADS)

Agarwal, S.; Haseman, M. S.; Leedy, K. D.; Winarski, D. J.; Saadatkia, P.; Doyle, E.; Zhang, L.; Dang, T.; Vasilyev, V. S.; Selim, F. A.

2018-04-01

Titanium oxide (TiO2) is a semiconducting oxide of increasing interest due to its chemical and thermal stability and broad applicability. In this study, thin films of TiO2 were deposited by pulsed laser deposition on sapphire and silicon substrates under various growth conditions, and characterized by x-ray diffraction (XRD), atomic force microscopy (AFM), optical absorption spectroscopy and Hall-effect measurements. XRD patterns revealed that a sapphire substrate is more suitable for the formation of the rutile phase in TiO2, while a silicon substrate yields a pure anatase phase, even at high-temperature growth. AFM images showed that the rutile TiO2 films grown at 805°C on a sapphire substrate have a smoother surface than anatase films grown at 620°C. Optical absorption spectra confirmed the band gap energy of 3.08 eV for the rutile phase and 3.29 eV for the anatase phase. All the deposited films exhibited the usual high resistivity of TiO2; however, when employed as a buffer layer, anatase TiO2 deposited on sapphire significantly improves the conductivity of indium gallium zinc oxide thin films. The study illustrates how to control the formation of TiO2 phases and reveals another interesting application for TiO2 as a buffer layer for transparent conducting oxides.

Method of forming silicon structures with selectable optical characteristics

NASA Technical Reports Server (NTRS)

Fathauer, Robert W. (Inventor); Schowalter, Leo (Inventor)

1993-01-01

Silicon and metal are coevaporated onto a silicon substrate in a molecular beam epitaxy system with a larger than stoichiometric amount of silicon so as to epitaxially grow particles of metal silicide embedded in a matrix of single crystal epitaxially grown silicon. The particles interact with incident photons by resonant optical absorption at the surface plasmon resonance frequency. Controlling the substrate temperature and deposition rate and time allows the aspect ratio of the particles to be tailored to desired wavelength photons and polarizations. The plasmon energy may decay as excited charge carriers or phonons, either of which can be monitored to indicate the amount of incident radiation at the selected frequency and polarization.

Method of manufacturing a hybrid emitter all back contact solar cell

DOEpatents

Loscutoff, Paul; Rim, Seung

2017-02-07

A method of manufacturing an all back contact solar cell which has a hybrid emitter design. The solar cell has a thin dielectric layer formed on a backside surface of a single crystalline silicon substrate. One emitter of the solar cell is made of doped polycrystalline silicon that is formed on the thin dielectric layer. A second emitter of the solar cell is formed in the single crystalline silicon substrate and is made of doped single crystalline silicon. The method further includes forming contact holes that allow metal contacts to connect to corresponding emitters.

Method of fabricating germanium and gallium arsenide devices

NASA Technical Reports Server (NTRS)

Jhabvala, Murzban (Inventor)

1990-01-01

A method of semiconductor diode fabrication is disclosed which relies on the epitaxial growth of a precisely doped thickness layer of gallium arsenide or germanium on a semi-insulating or intrinsic substrate, respectively, of gallium arsenide or germanium by either molecular beam epitaxy (MBE) or by metal-organic chemical vapor deposition (MOCVD). The method involves: depositing a layer of doped or undoped silicon dioxide on a germanium or gallium arsenide wafer or substrate, selectively removing the silicon dioxide layer to define one or more surface regions for a device to be fabricated thereon, growing a matched epitaxial layer of doped germanium or gallium arsenide of an appropriate thickness using MBE or MOCVD techniques on both the silicon dioxide layer and the defined one or more regions; and etching the silicon dioxide and the epitaxial material on top of the silicon dioxide to leave a matched epitaxial layer of germanium or gallium arsenide on the germanium or gallium arsenide substrate, respectively, and upon which a field effect device can thereafter be formed.

Deep level transient spectroscopic investigation of phosphorus-doped silicon by self-assembled molecular monolayers.

PubMed

Gao, Xuejiao; Guan, Bin; Mesli, Abdelmadjid; Chen, Kaixiang; Dan, Yaping

2018-01-09

It is known that self-assembled molecular monolayer doping technique has the advantages of forming ultra-shallow junctions and introducing minimal defects in semiconductors. In this paper, we report however the formation of carbon-related defects in the molecular monolayer-doped silicon as detected by deep-level transient spectroscopy and low-temperature Hall measurements. The molecular monolayer doping process is performed by modifying silicon substrate with phosphorus-containing molecules and annealing at high temperature. The subsequent rapid thermal annealing drives phosphorus dopants along with carbon contaminants into the silicon substrate, resulting in a dramatic decrease of sheet resistance for the intrinsic silicon substrate. Low-temperature Hall measurements and secondary ion mass spectrometry indicate that phosphorus is the only electrically active dopant after the molecular monolayer doping. However, during this process, at least 20% of the phosphorus dopants are electrically deactivated. The deep-level transient spectroscopy shows that carbon-related defects are responsible for such deactivation.

Microfabricated instrument for tissue biopsy and analysis

DOEpatents

Krulevitch, Peter A.; Lee, Abraham P.; Northrup, M. Allen; Benett, William J.

2001-01-01

A microfabricated biopsy/histology instrument which has several advantages over the conventional procedures, including minimal specimen handling, smooth cutting edges with atomic sharpness capable of slicing very thin specimens (approximately 2 .mu.m or greater), micro-liter volumes of chemicals for treating the specimens, low cost, disposable, fabrication process which renders sterile parts, and ease of use. The cutter is a "cheese-grater" style design comprising a block or substrate of silicon and which uses anisotropic etching of the silicon to form extremely sharp and precise cutting edges. As a specimen is cut, it passes through the silicon cutter and lies flat on a piece of glass which is bonded to the cutter. Microchannels are etched into the glass or silicon substrates for delivering small volumes of chemicals for treating the specimen. After treatment, the specimens can be examined through the glass substrate.

Substrate and Passivation Techniques for Flexible Amorphous Silicon-Based X-ray Detectors

PubMed Central

Marrs, Michael A.; Raupp, Gregory B.

2016-01-01

Flexible active matrix display technology has been adapted to create new flexible photo-sensing electronic devices, including flexible X-ray detectors. Monolithic integration of amorphous silicon (a-Si) PIN photodiodes on a flexible substrate poses significant challenges associated with the intrinsic film stress of amorphous silicon. This paper examines how altering device structuring and diode passivation layers can greatly improve the electrical performance and the mechanical reliability of the device, thereby eliminating one of the major weaknesses of a-Si PIN diodes in comparison to alternative photodetector technology, such as organic bulk heterojunction photodiodes and amorphous selenium. A dark current of 0.5 pA/mm2 and photodiode quantum efficiency of 74% are possible with a pixelated diode structure with a silicon nitride/SU-8 bilayer passivation structure on a 20 µm-thick polyimide substrate. PMID:27472329

Substrate and Passivation Techniques for Flexible Amorphous Silicon-Based X-ray Detectors.

PubMed

Marrs, Michael A; Raupp, Gregory B

2016-07-26

Flexible active matrix display technology has been adapted to create new flexible photo-sensing electronic devices, including flexible X-ray detectors. Monolithic integration of amorphous silicon (a-Si) PIN photodiodes on a flexible substrate poses significant challenges associated with the intrinsic film stress of amorphous silicon. This paper examines how altering device structuring and diode passivation layers can greatly improve the electrical performance and the mechanical reliability of the device, thereby eliminating one of the major weaknesses of a-Si PIN diodes in comparison to alternative photodetector technology, such as organic bulk heterojunction photodiodes and amorphous selenium. A dark current of 0.5 pA/mm² and photodiode quantum efficiency of 74% are possible with a pixelated diode structure with a silicon nitride/SU-8 bilayer passivation structure on a 20 µm-thick polyimide substrate.

Integrated circuit with dissipative layer for photogenerated carriers

DOEpatents

Myers, D.R.

1988-04-20

The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissipative layer of silicon nitride between a silicon substrate and the active device. Free carriers generated in the substrate are dissipated by the layer before they can build up charge on the active device. 1 fig.

Crystallization and growth of Ni-Si alloy thin films on inert and on silicon substrates

NASA Astrophysics Data System (ADS)

Grimberg, I.; Weiss, B. Z.

1995-04-01

The crystallization kinetics and thermal stability of NiSi2±0.2 alloy thin films coevaporated on two different substrates were studied. The substrates were: silicon single crystal [Si(100)] and thermally oxidized silicon single crystal. In situ resistance measurements, transmission electron microscopy, x-ray diffraction, Auger electron spectroscopy, and Rutherford backscattering spectroscopy were used. The postdeposition microstructure consisted of a mixture of amorphous and crystalline phases. The amorphous phase, independent of the composition, crystallizes homogeneously to NiSi2 at temperatures lower than 200 °C. The activation energy, determined in the range of 1.4-2.54 eV, depends on the type of the substrate and on the composition of the alloyed films. The activation energy for the alloys deposited on the inert substrate was found to be lower than for the alloys deposited on silicon single crystal. The lowest activation energy was obtained for nonstoichiometric NiSi2.2, the highest for NiSi2—on both substrates. The crystallization mode depends on the structure of the as-deposited films, especially the density of the existing crystalline nuclei. Substantial differences were observed in the thermal stability of the NiSi2 compound on both substrates. With the alloy films deposited on the Si substrate, only the NiSi2 phase was identified after annealing to temperatures up to 800 °C. In the films deposited on the inert substrate, NiSi and NiSi2 phases were identified when the Ni content in the alloy exceeded 33 at. %. The effects of composition and the type of substrate on the crystallization kinetics and thermal stability are discussed.

Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer

DOEpatents

Warren, William L.; Vanheusden, Karel J. R.; Schwank, James R.; Fleetwood, Daniel M.; Shaneyfelt, Marty R.; Winokur, Peter S.; Devine, Roderick A. B.

1998-01-01

A method for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus-voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer.

The Growth of Expitaxial GaAs and GaAlAs on Silicon Substrates by OMVPE

DTIC Science & Technology

1988-08-01

structures have been grown on semi-insulating gallium arsenide substrates, and on high-resistivity silicon substrates using a two stage growth technique...fully in Quarter 9. 2. MATERIALS GROWTH 2.1 DOPING OF GALLIUM ARSENIDE FOR FETs As reported in quarter 7, doping levels for GaAs/SI 4ere found to be a...FET structures on both GaAs and Si substrates. A number of FET layers have been grown to the GAT4 specification on semi-insulating gallium arsenide

Atomic layer deposition on phase-shift lithography generated photoresist patterns for 1D nanochannel fabrication.

PubMed

Güder, Firat; Yang, Yang; Krüger, Michael; Stevens, Gregory B; Zacharias, Margit

2010-12-01

A versatile, low-cost, and flexible approach is presented for the fabrication of millimeter-long, sub-100 nm wide 1D nanochannels with tunable wall properties (wall thickness and material) over wafer-scale areas on glass, alumina, and silicon surfaces. This approach includes three fabrication steps. First, sub-100 nm photoresist line patterns were generated by near-field contact phase-shift lithography (NFC-PSL) using an inexpensive homemade borosilicate mask (NFC-PSM). Second, various metal oxides were directly coated on the resist patterns with low-temperature atomic layer deposition (ALD). Finally, the remaining photoresist was removed via an acetone dip, and then planar nanochannel arrays were formed on the substrate. In contrast to all the previous fabrication routes, the sub-100 nm photoresist line patterns produced by NFC-PSL are directly employed as a sacrificial layer for the creation of nanochannels. Because both the NFC-PSL and the ALD deposition are highly reproducible processes, the strategy proposed here can be regarded as a general route for nanochannel fabrication in a simplified and reliable manner. In addition, the fabricated nanochannels were used as templates to synthesize various organic and inorganic 1D nanostructures on the substrate surface.

Epitaxy of GaN in high aspect ratio nanoscale holes over silicon substrate

NASA Astrophysics Data System (ADS)

Wang, Kejia; Wang, Anqi; Ji, Qingbin; Hu, Xiaodong; Xie, Yahong; Sun, Ying; Cheng, Zhiyuan

2017-12-01

Dislocation filtering in gallium nitride (GaN) by epitaxial growth through patterned nanoscale holes is studied. GaN grown from extremely high aspect ratio holes by metalorganic chemical vapor deposition is examined by transmission electron microscopy and high-resolution transmission electron microscopy. This selective area epitaxial growth method with a reduced epitaxy area and an increased depth to width ratio of holes leads to effective filtering of dislocations within the hole and improves the quality of GaN significantly.

Nanometer-scale ablation using focused, coherent extreme ultraviolet/soft x-ray light

DOEpatents

Menoni, Carmen S [Fort Collins, CO; Rocca, Jorge J [Fort Collins, CO; Vaschenko, Georgiy [San Diego, CA; Bloom, Scott [Encinitas, CA; Anderson, Erik H [El Cerrito, CA; Chao, Weilun [El Cerrito, CA; Hemberg, Oscar [Stockholm, SE

2011-04-26

Ablation of holes having diameters as small as 82 nm and having clean walls was obtained in a poly(methyl methacrylate) on a silicon substrate by focusing pulses from a Ne-like Ar, 46.9 nm wavelength, capillary-discharge laser using a freestanding Fresnel zone plate diffracting into third order is described. Spectroscopic analysis of light from the ablation has also been performed. These results demonstrate the use of focused coherent EUV/SXR light for the direct nanoscale patterning of materials.

Method of construction of a multi-cell solar array

NASA Technical Reports Server (NTRS)

Routh, D. E.; Hollis, B. R., Jr.; Feltner, W. R. (Inventor)

1979-01-01

The method of constructing a high voltage, low power, multicell solar array is described. A solar cell base region is formed in a substrate such as but not limited to silicon or sapphire. A protective coating is applied on the base and a patterned etching of the coating and base forms discrete base regions. A semiconductive junction and upper active region are formed in each base region, and defined by photolithography. Thus, discrete cells which are interconnected by metallic electrodes are formed.

Wetting of silicone oil onto a cell-seeded substrate

NASA Astrophysics Data System (ADS)

Lu, Yongjie; Chan, Yau Kei; Chao, Youchuang; Shum, Ho Cheung

2017-11-01

Wetting behavior of solid substrates in three-phase systems containing two immiscible liquids are widely studied. There exist many three-phase systems in biological environments, such as droplet-based microfluidics or tamponade of silicone oil for eye surgery. However, few studies focus on wetting behavior of biological surfaces with cells. Here we investigate wetting of silicone oil onto cell-seeded PMMA sheet immersed in water. Using a simple parallel-plate cell, we show the effect of cell density, viscosity of silicone oil, morphology of silicone oil drops and interfacial tension on the wetting phenomenon. The dynamics of wetting is also observed by squeezing silicone oil drop using two parallel plates. Experimental results are explained based on disjoining pressure which is dependent on the interaction of biological surfaces and liquid used. These findings are useful for explaining emulsification of silicone oil in ophthalmological applications.

Complex dewetting scenarios of ultrathin silicon films for large-scale nanoarchitectures

PubMed Central

Naffouti, Meher; Backofen, Rainer; Salvalaglio, Marco; Bottein, Thomas; Lodari, Mario; Voigt, Axel; David, Thomas; Benkouider, Abdelmalek; Fraj, Ibtissem; Favre, Luc; Ronda, Antoine; Berbezier, Isabelle; Grosso, David; Abbarchi, Marco; Bollani, Monica

2017-01-01

Dewetting is a ubiquitous phenomenon in nature; many different thin films of organic and inorganic substances (such as liquids, polymers, metals, and semiconductors) share this shape instability driven by surface tension and mass transport. Via templated solid-state dewetting, we frame complex nanoarchitectures of monocrystalline silicon on insulator with unprecedented precision and reproducibility over large scales. Phase-field simulations reveal the dominant role of surface diffusion as a driving force for dewetting and provide a predictive tool to further engineer this hybrid top-down/bottom-up self-assembly method. Our results demonstrate that patches of thin monocrystalline films of metals and semiconductors share the same dewetting dynamics. We also prove the potential of our method by fabricating nanotransfer molding of metal oxide xerogels on silicon and glass substrates. This method allows the novel possibility of transferring these Si-based patterns on different materials, which do not usually undergo dewetting, offering great potential also for microfluidic or sensing applications. PMID:29296680

Complex dewetting scenarios of ultrathin silicon films for large-scale nanoarchitectures.

PubMed

Naffouti, Meher; Backofen, Rainer; Salvalaglio, Marco; Bottein, Thomas; Lodari, Mario; Voigt, Axel; David, Thomas; Benkouider, Abdelmalek; Fraj, Ibtissem; Favre, Luc; Ronda, Antoine; Berbezier, Isabelle; Grosso, David; Abbarchi, Marco; Bollani, Monica

2017-11-01

Dewetting is a ubiquitous phenomenon in nature; many different thin films of organic and inorganic substances (such as liquids, polymers, metals, and semiconductors) share this shape instability driven by surface tension and mass transport. Via templated solid-state dewetting, we frame complex nanoarchitectures of monocrystalline silicon on insulator with unprecedented precision and reproducibility over large scales. Phase-field simulations reveal the dominant role of surface diffusion as a driving force for dewetting and provide a predictive tool to further engineer this hybrid top-down/bottom-up self-assembly method. Our results demonstrate that patches of thin monocrystalline films of metals and semiconductors share the same dewetting dynamics. We also prove the potential of our method by fabricating nanotransfer molding of metal oxide xerogels on silicon and glass substrates. This method allows the novel possibility of transferring these Si-based patterns on different materials, which do not usually undergo dewetting, offering great potential also for microfluidic or sensing applications.

Acoustic Emission Characteristics of Nanocrystalline Porous Silicon Device Driven as an Ultrasonic Speaker

NASA Astrophysics Data System (ADS)

Tsubaki, Kenji; Komoda, Takuya; Koshida, Nobuyoshi

2006-04-01

It is shown that the dc-superimposed driving mode is more useful for the efficient operation of a novel thermally induced ultrasonic emitter based on nanocrystalline porous silicon (nc-PS) than the conventional simple ac-voltage driving mode. The nc-PS device is composed of a patterned heater electrode, an nc-PS layer and a single crystalline silicon (c-Si) substrate. The almost complete thermally insulating property of nc-PS as a quantum-sized system makes it possible to apply the nc-PS device as an ultrasonic generator by efficient thermo acoustic conversion without any mechanical vibrations. In the dc-superimposed driving mode, the output frequency is the same as the input frequency and a stationary temperature rise is kept constant independent of input peak-to-peak voltage. In addition, power efficiency is significantly increases compared with that in the ac-voltage driving mode without affecting on the temperature rise. The present results suggest the further possibility of the nc-PS device being used as a functional speaker.

Template-Stripped Tunable Plasmonic Devices on Stretchable and Rollable Substrates

PubMed Central

2015-01-01

We use template stripping to integrate metallic nanostructures onto flexible, stretchable, and rollable substrates. Using this approach, high-quality patterned metals that are replicated from reusable silicon templates can be directly transferred to polydimethylsiloxane (PDMS) substrates. First we produce stretchable gold nanohole arrays and show that their optical transmission spectra can be modulated by mechanical stretching. Next we fabricate stretchable arrays of gold pyramids and demonstrate a modulation of the wavelength of light resonantly scattered from the tip of the pyramid by stretching the underlying PDMS film. The use of a flexible transfer layer also enables template stripping using a cylindrical roller as a substrate. As an example, we demonstrate roller template stripping of metallic nanoholes, nanodisks, wires, and pyramids onto the cylindrical surface of a glass rod lens. These nonplanar metallic structures produced via template stripping with flexible and stretchable films can facilitate many applications in sensing, display, plasmonics, metasurfaces, and roll-to-roll fabrication. PMID:26402066

A continuous silicon-coating facility

NASA Technical Reports Server (NTRS)

Butter, C.; Heaps, J. D.

1979-01-01

Automatic continuous silicon-coating facility is used to process 100 by 10 cm graphite-coated ceramic substrates for silicon solar cells. Process reduces contamination associated with conventional dip-coating processes, improving material service life.

Broadly tunable terahertz difference-frequency generation in quantum cascade lasers on silicon

NASA Astrophysics Data System (ADS)

Jung, Seungyong; Kim, Jae Hyun; Jiang, Yifan; Vijayraghavan, Karun; Belkin, Mikhail A.

2018-01-01

We report broadly tunable terahertz (THz) sources based on intracavity Cherenkov difference-frequency generation in quantum cascade lasers transfer-printed on high-resistivity silicon substrates. Spectral tuning from 1.3 to 4.3 THz was obtained from a 2-mm long laser chip using a modified Littrow external cavity setup. The THz power output and the midinfrared-to-THz conversion efficiency of the devices transferred on silicon are dramatically enhanced, compared with the devices on a native semi-insulating InP substrate. Enhancement is particularly significant at higher THz frequencies, where the tail of the Reststrahlen band results in a strong absorption of THz light in the InP substrate.

Designed porosity materials in nuclear reactor components

DOEpatents

Yacout, A. M.; Pellin, Michael J.; Stan, Marius

2016-09-06

A nuclear fuel pellet with a porous substrate, such as a carbon or tungsten aerogel, on which at least one layer of a fuel containing material is deposited via atomic layer deposition, and wherein the layer deposition is controlled to prevent agglomeration of defects. Further, a method of fabricating a nuclear fuel pellet, wherein the method features the steps of selecting a porous substrate, depositing at least one layer of a fuel containing material, and terminating the deposition when the desired porosity is achieved. Also provided is a nuclear reactor fuel cladding made of a porous substrate, such as silicon carbide aerogel or silicon carbide cloth, upon which layers of silicon carbide are deposited.

Joining of Silicon Carbide: Diffusion Bond Optimization and Characterization

NASA Technical Reports Server (NTRS)

Halbig, Michael C.; Singh, Mrityunjay

2008-01-01

Joining and integration methods are critically needed as enabling technologies for the full utilization of advanced ceramic components in aerospace and aeronautics applications. One such application is a lean direct injector for a turbine engine to achieve low NOx emissions. In the application, several SiC substrates with different hole patterns to form fuel and combustion air channels are bonded to form the injector. Diffusion bonding is a joining approach that offers uniform bonds with high temperature capability, chemical stability, and high strength. Diffusion bonding was investigated with the aid of titanium foils and coatings as the interlayer between SiC substrates to aid bonding. The influence of such variables as interlayer type, interlayer thickness, substrate finish, and processing time were investigated. Optical microscopy, scanning electron microscopy, and electron microprobe analysis were used to characterize the bonds and to identify the reaction formed phases.

Monolithically interconnected silicon-film™ module technology

NASA Astrophysics Data System (ADS)

DelleDonne, E. J.; Ford, D. H.; Hall, R. B.; Ingram, A. E.; Rand, J. A.; Barnett, A. M.

1999-03-01

AstroPower is developing an advanced thin-silicon-based, photovoltaic module product. A low-cost monolithic interconnected device is being integrated into a module that combines the design and process features of advanced light trapped, thin-silicon solar cells. This advanced product incorporates a low-cost substrate, a nominally 50-μm thick grown silicon layer with minority carrier diffusion lengths exceeding the active layer thickness, light trapping due to back-surface reflection, and back-surface passivation. The thin silicon layer enables high solar cell performance and can lead to a module conversion efficiency as high as 19%. These performance design features, combined with low-cost manufacturing using relatively low-cost capital equipment, continuous processing and a low-cost substrate, will lead to high-performance, low-cost photovoltaic panels.

Evanescent Microwave Probes on High-Resistivity Silicon and its Application in Characterization of Semiconductors

NASA Technical Reports Server (NTRS)

Tabib-Azar, M.; Akinwande, D.; Ponchak, George E.; LeClair, S. R.

1999-01-01

In this article we report the design, fabrication, and characterization of very high quality factor 10 GHz microstrip resonators on high-resistivity (high-rho) silicon substrates. Our experiments show that an external quality factor of over 13 000 can be achieved on microstripline resonators on high-rho silicon substrates. Such a high Q factor enables integration of arrays of previously reported evanescent microwave probe (EMP) on silicon cantilever beams. We also demonstrate that electron-hole pair recombination and generation lifetimes of silicon can be conveniently measured by illuminating the resonator using a pulsed light. Alternatively, the EMP was also used to nondestructively monitor excess carrier generation and recombination process in a semiconductor placed near the two-dimensional resonator.

Evaluation of the Effect of Silicone Contamination on Various Bond Systems and the Feasibility of Removing the Contamination

NASA Technical Reports Server (NTRS)

Stanley, Stephanie D.

2008-01-01

Silicone is a contaminant that can cause catastrophic failure of a bond system depending on the materials and processes used to fabricate the bond system. Unfortunately, more and more materials are fabricated using silicone. The purpose of this testing was to evaluate which bond systems are sensitive to silicone contamination and whether or not a cleaning process could be utilized to remove the silicone to bring the bond system performance back to baseline. Due to the extensive nature of the testing, attempts will be made to generalize the understanding within classes of substrates, bond systems, and surface preparation and cleaning methods. This study was done by contaminating various metal (steel, Inconel, and aluminum), phenolic (carbon-cloth phenolic [CCP] and glass-cloth phenolic [GCP]), and rubber (natural rubber, asbestos-silicone dioxide filled natural butyldiene rubber [ASNBR]; silica-filled ethylene propylenediene monomer [SFEPDM], and carbon-filled ethylene propylenediene monomer [CFEPDM]) substrates which were then bonded using various adhesives and coatings (epoxy-based adhesives, paints, ablative compounds, and Chemlok adhesives) to determine the effect silicone contamination has on a given bond system's performance. The test configurations depended on the bond system being evaluated. The study also evaluated the feasibility of removing the silicone contamination by cleaning the contaminated substrate prior to bonding. The cleaning processes also varied depending on bond system.

Silicon on ceramic process. Silicon sheet growth development for the large-area silicon sheet task of the low-cost silicon solar array project

NASA Technical Reports Server (NTRS)

Zook, J. D.; Heaps, J. D.; Maciolek, R. B.; Koepke, B. G.; Butter, C. D.; Schuldt, S. B.

1977-01-01

The technical and economic feasibility of producing solar-cell-quality sheet silicon was investigated. The sheets were made by coating one surface of carbonized ceramic substrates with a thin layer of large-grain polycrystalline silicon from the melt. Significant progress was made in all areas of the program.

Effects of varying oxygen partial pressure on molten silicon-ceramic substrate interactions

NASA Technical Reports Server (NTRS)

Ownby, D. P.; Barsoum, M. W.

1980-01-01

The silicon sessile drop contact angle was measured on hot pressed silicon nitride, silicon nitride coated on hot pressed silicon nitride, silicon carbon coated on graphite, and on Sialon to determine the degree to which silicon wets these substances. The post-sessile drop experiment samples were sectioned and photomicrographs were taken of the silicon-substrate interface to observe the degree of surface dissolution and degradation. Of these materials, silicon did not form a true sessile drop on the SiC on graphite due to infiltration of the silicon through the SiC coating, nor on the Sialon due to the formation of a more-or-less rigid coating on the liquid silicon. The most wetting was obtained on the coated Si3N4 with a value of 42 deg. The oxygen concentrations in a silicon ribbon furnace and in a sessile drop furnace were measured using the protable thoria-yttria solid solution electrolyte oxygen sensor. Oxygen partial pressures of 10 to the minus 7 power atm and 10 to the minus 8 power atm were obtained at the two facilities. These measurements are believed to represent nonequilibrium conditions.

AES study on the chemical composition of ferroelectric BaTiO3 thin films RF sputter-deposited on silicon

NASA Technical Reports Server (NTRS)

Dharmadhikari, V. S.; Grannemann, W. W.

1983-01-01

AES depth profiling data are presented for thin films of BaTiO3 deposited on silicon by RF sputtering. By profiling the sputtered BaTiO3/silicon structures, it was possible to study the chemical composition and the interface characteristics of thin films deposited on silicon at different substrate temperatures. All the films showed that external surface layers were present, up to a few tens of angstroms thick, the chemical composition of which differed from that of the main layer. The main layer had stable composition, whereas the intermediate film-substrate interface consisted of reduced TiO(2-x) oxides. The thickness of this intermediate layer was a function of substrate temperature. All the films showed an excess of barium at the interface. These results are important in the context of ferroelectric phenomena observed in BaTiO3 thin films.

Optical substrate materials for synchrotron radiation beamlines

DOE Office of Scientific and Technical Information (OSTI.GOV)

Howells, M.R.; Paquin, R.A.

1997-06-01

The authors consider the materials choices available for making optical substrates for synchrotron radiation beam lines. They find that currently the optical surfaces can only be polished to the required finish in fused silica and other glasses, silicon, CVD silicon carbide, electroless nickel and 17-4 PH stainless steel. Substrates must therefore be made of one of these materials or of a metal that can be coated with electroless nickel. In the context of material choices for mirrors they explore the issues of dimensional stability, polishing, bending, cooling, and manufacturing strategy. They conclude that metals are best from an engineering andmore » cost standpoint while the ceramics are best from a polishing standpoint. They then give discussions of specific materials as follows: silicon carbide, silicon, electroless nickel, Glidcop{trademark}, aluminum, precipitation-hardening stainless steel, mild steel, invar and superinvar. Finally they summarize conclusions and propose ideas for further research.« less

Stoichiometry of Silicon Dioxide Films Obtained by Ion-Beam Sputtering

NASA Astrophysics Data System (ADS)

Telesh, E. V.; Dostanko, A. P.; Gurevich, O. V.

2018-03-01

The composition of SiOx films produced by ion-beam sputtering (IBS) of silicon and quartz targets were studied by infrared spectrometry. Films with thicknesses of 150-390 nm were formed on silicon substrates. It was found that increase in the partial pressure of oxygen in the working gas, increase in the temperature of the substrate, and the presence of a positive potential on the target during reactive IBS of silicon shifted the main absorption band νas into the high-frequency region and increased the composition index from 1.41 to 1.85. During IBS of a quartz target the stoichiometry of the films deteriorates with increase of the energy of the sputtering argon ions. This may be due to increase of the deposition rate. Increase in the current of the thermionic compensator, increase of the substrate temperature, and addition of oxygen led to the formation of SiOx films with improved stoichiometry.

Method to fabricate silicon chromatographic column comprising fluid ports

DOEpatents

Manginell, Ronald P.; Frye-Mason, Gregory C.; Heller, Edwin J.; Adkins, Douglas R.

2004-03-02

A new method for fabricating a silicon chromatographic column comprising through-substrate fluid ports has been developed. This new method enables the fabrication of multi-layer interconnected stacks of silicon chromatographic columns.

Curvature Control of Silicon Microlens for THz Dielectric Antenna

NASA Technical Reports Server (NTRS)

Lee, Choonsup; Chattopadhyay, Goutam; Cooper, Ken; Mehdi, Imran

2012-01-01

We have controlled the curvature of silicon microlens by changing the amount of photoresist in order to microfabricate hemispherical silicon microlens which can improve the directivity and reduce substrate mode losses.

Micromachined cutting blade formed from {211}-oriented silicon

DOEpatents

Fleming, James G.; Sniegowski, Jeffry J.; Montague, Stephen

2003-09-09

A cutting blade is disclosed fabricated of micromachined silicon. The cutting blade utilizes a monocrystalline silicon substrate having a {211} crystalline orientation to form one or more cutting edges that are defined by the intersection of {211} crystalline planes of silicon with {111} crystalline planes of silicon. This results in a cutting blade which has a shallow cutting-edge angle .theta. of 19.5.degree.. The micromachined cutting blade can be formed using an anisotropic wet etching process which substantially terminates etching upon reaching the {111} crystalline planes of silicon. This allows multiple blades to be batch fabricated on a common substrate and separated for packaging and use. The micromachined cutting blade, which can be mounted to a handle in tension and optionally coated for increased wear resistance and biocompatibility, has multiple applications including eye surgery (LASIK procedure).

Micromachined cutting blade formed from {211}-oriented silicon

DOEpatents

Fleming, James G [Albuquerque, NM; Fleming, legal representative, Carol; Sniegowski, Jeffry J [Tijeras, NM; Montague, Stephen [Albuquerque, NM

2011-08-09

A cutting blade is disclosed fabricated of micromachined silicon. The cutting blade utilizes a monocrystalline silicon substrate having a {211} crystalline orientation to form one or more cutting edges that are defined by the intersection of {211} crystalline planes of silicon with {111} crystalline planes of silicon. This results in a cutting blade which has a shallow cutting-edge angle .theta. of 19.5.degree.. The micromachined cutting blade can be formed using an anisotropic wet etching process which substantially terminates etching upon reaching the {111} crystalline planes of silicon. This allows multiple blades to be batch fabricated on a common substrate and separated for packaging and use. The micromachined cutting blade, which can be mounted to a handle in tension and optionally coated for increased wear resistance and biocompatibility, has multiple applications including eye surgery (LASIK procedure).

MBE growth and optical properties of GaN layers on SiC/Si(111) hybrid substrate

NASA Astrophysics Data System (ADS)

Reznik, R. R.; Kotlyar, K. P.; Soshnikov, I. P.; Kukushkin, S. A.; Osipov, A. V.; Nikitina, E. V.; Cirlin, G. E.

2017-11-01

The fundamental possibility of the growth of GaN layers by molecular-beam epitaxy on a silicon substrate with nanoscale buffer layer of silicon carbide without any AlN layers has been demonstrated for the first time. Morphological properties of the resulting system have been studied.

Influence of calcium and silicon supplementation into Pleurotus ostreatus substrates on quality of fresh and canned mushrooms.

PubMed

Thongsook, T; Kongbangkerd, T

2011-08-01

Supplements of gypsum (calcium source), pumice (silicon source) and pumice sulfate (silicon and calcium source) into substrates for oyster mushrooms (Pleurotus ostreatus) were searched for their effects on production as well as qualities of fresh and canned mushrooms. The addition of pumice up to 30% had no effect on total yield, size distribution and cap diameters. The supplementation of gypsum at 10% decreased the total yield; and although gypsum at 5% did not affect total yield, the treatment increased the proportion of large-sized caps. High content (>10%) of pumice sulfate resulted in the lower yield. Calcium and silicon contents in the fruit bodies were not influenced by supplementations. The centrifugal drip loss values and solid content of fresh mushrooms, and the percentage of weight gained and firmness of canned mushrooms, cultivated in substrates supplemented with gypsum, pumice and pumice sulfate were significantly (p≤0.05) higher than those of the control. Scanning electron micrographs revealed the more compacted hyphae of mushroom stalks supplemented with silicon and/or calcium after heat treatment, compared to the control. Supplementation of P. ostreatus substrates with 20% pumice was the most practical treatment because it showed no effect on yield and the most cost-effective.

Porous silicon-copper phthalocyanine heterostructure based photoelectrochemical cell

NASA Astrophysics Data System (ADS)

A. Betty, C.; N, Padma; Arora, Shalav; Survaiya, Parth; Bhattacharya, Debarati; Choudhury, Sipra; Roy, Mainak

2018-01-01

A hybrid solar cell consisting of nanostructured p-type porous silicon (PS) deposited with visible light absorbing dye, Copper Phthalocyanine (CuPc) has been prepared in the photoelectrochemical cell configuration. P-type PS with (100) and (111) orientations which have different porous structures were used for studying the effects of the substrate morphology on the cell efficiency. Heterostructures were prepared by depositing three different thicknesses of CuPc for optimizing the cell efficiency. Structural and surface characterizations were studied using XRD, Raman, SEM and AFM on the PS-CuPc heterostructure. XRD spectrum on both plane silicon and porous silicon indicates the π-π stacking of CuPc with increased disorder for CuPc film on porous silicon. Electrochemical characterizations under sun light type radiation have been carried out to evaluate the photosensitivity of the heterostructure. Between the two different substrates, (100) PS gives better photocurrent, possibly due to the higher surface area and lower series resistance of the structure. Among the (100) PS substrates, (100) PS with 15 nm CuPc film gives Voc more than 1 V resulting in higher efficiency for the cell. The study suggests the scope for optimization of solar cell efficiency using various combinations of the substrate structure and thickness of the sensitizing layer.

Oxygen ion-beam microlithography

DOEpatents

Tsuo, Y.S.

1991-08-20

A method of providing and developing a resist on a substrate for constructing integrated circuit (IC) chips includes the following steps: of depositing a thin film of amorphous silicon or hydrogenated amorphous silicon on the substrate and exposing portions of the amorphous silicon to low-energy oxygen ion beams to oxidize the amorphous silicon at those selected portions. The nonoxidized portions are then removed by etching with RF-excited hydrogen plasma. Components of the IC chip can then be constructed through the removed portions of the resist. The entire process can be performed in an in-line vacuum production system having several vacuum chambers. Nitrogen or carbon ion beams can also be used. 5 figures.

Oxygen ion-beam microlithography

DOEpatents

Tsuo, Y. Simon

1991-01-01

A method of providing and developing a resist on a substrate for constructing integrated circuit (IC) chips includes the following steps: of depositing a thin film of amorphous silicon or hydrogenated amorphous silicon on the substrate and exposing portions of the amorphous silicon to low-energy oxygen ion beams to oxidize the amorphous silicon at those selected portions. The nonoxidized portions are then removed by etching with RF-excited hydrogen plasma. Components of the IC chip can then be constructed through the removed portions of the resist. The entire process can be performed in an in-line vacuum production system having several vacuum chambers. Nitrogen or carbon ion beams can also be used.

Silicon nitride protective coatings for silvered glass mirrors

DOEpatents

Tracy, C. Edwin; Benson, David K.

1988-01-01

A protective diffusion barrier for metalized mirror structures is provided by a layer or coating of silicon nitride which is a very dense, transparent, dielectric material that is impervious to water, alkali, and other impurities and corrosive substances that typically attack the metal layers of mirrors and cause degradation of the mirrors' reflectivity. The silicon nitride layer can be deposited on the substrate before metal deposition to stabilize the metal/substrate interface, and it can be deposited over the metal to encapsulate it and protect the metal from corrosion or other degradation. Mirrors coated with silicon nitride according to this invention can also be used as front surface mirrors.

Silicon nitride protective coatings for silvered glass mirrors

DOEpatents

Tracy, C.E.; Benson, D.K.

1984-07-20

A protective diffusion barrier for metalized mirror structures is provided by a layer or coating of silicon nitride which is a very dense, transparent, dielectric material that is impervious to water, alkali, and other impurities and corrosive substances that typically attack the metal layers of mirrors and cause degradation of the mirrors' reflectivity. The silicon nitride layer can be deposited on the substrate prior to metal deposition thereon to stabilize the metal/substrate interface, and it can be deposited over the metal to encapsulate it and protect the metal from corrosion or other degradation. Mirrors coated with silicon nitride according to this invention can also be used as front surface mirrors.

Study of thickness and uniformity of oxide passivation with DI-O3 on silicon substrate for electronic and photonic applications

NASA Astrophysics Data System (ADS)

Sharma, Mamta; Hazra, Purnima; Singh, Satyendra Kumar

2018-05-01

Since the beginning of semiconductor fabrication technology evolution, clean and passivated substrate surface is one of the prime requirements for fabrication of Electronic and optoelectronic device fabrication. However, as the scale of silicon circuits and device architectures are continuously decreased from micrometer to nanometer (from VLSI to ULSI technology), the cleaning methods to achieve better wafer surface qualities has raised research interests. The development of controlled and uniform silicon dioxide is the most effective and reliable way to achieve better wafer surface quality for fabrication of electronic devices. On the other hand, in order to meet the requirement of high environment safety/regulatory standards, the innovation of cleaning technology is also in demand. The controlled silicon dioxide layer formed by oxidant de-ionized ozonated water has better uniformity. As the uniformity of the controlled silicon dioxide layer is improved on the substrate, it enhances the performance of the devices. We can increase the thickness of oxide layer, by increasing the ozone time treatment. We reported first time to measurement of thickness of controlled silicon dioxide layer and obtained the uniform layer for same ozone time.

Laser generation in microdisc resonators with InAs/GaAs quantum dots transferred on a silicon substrate

NASA Astrophysics Data System (ADS)

Nadtochiy, A. M.; Kryzhanovskaya, N. V.; Maximov, M. V.; Zhukov, A. E.; Moiseev, E. I.; Kulagina, M. M.; Vashanova, K. A.; Zadiranov, Yu. M.; Mukhin, I. S.; Arakcheeva, E. M.; Livshits, D.; Lipovskii, A. A.

2013-09-01

Microdisc resonators based on InAs/GaAs quantum dots separated from a GaAs substrate by selective etching and fixed to a silicon substrate by epoxy glue are studied using luminescence spectroscopy. A disc resonator 6 μm in diameter exhibits quasi-single-mode laser generation at a temperature of 78 K with a threshold power of 320 μW and λ/Δλ ˜ 27000.

Silicon-on-ceramic process: Silicon sheet growth and device development for the large-area silicon sheet task of the low-cost solar array project

NASA Technical Reports Server (NTRS)

Whitehead, A. B.; Zook, J. D.; Grung, B. L.; Heaps, J. D.; Schmit, F.; Schuldt, S. B.; Chapman, P. W.

1981-01-01

The technical feasibility of producing solar cell quality sheet silicon to meet the DOE 1986 cost goal of 70 cents/watt was investigated. The silicon on ceramic approach is to coat a low cost ceramic substrate with large grain polycrystalline silicon by unidirectional solidification of molten silicon. Results and accomplishments are summarized.

Preparation of Mica and Silicon Substrates for DNA Origami Analysis and Experimentation

PubMed Central

Pillers, Michelle A.; Shute, Rebecca; Farchone, Adam; Linder, Keenan P.; Doerfler, Rose; Gavin, Corey; Goss, Valerie; Lieberman, Marya

2015-01-01

The designed nature and controlled, one-pot synthesis of DNA origami provides exciting opportunities in many fields, particularly nanoelectronics. Many of these applications require interaction with and adhesion of DNA nanostructures to a substrate. Due to its atomically flat and easily cleaned nature, mica has been the substrate of choice for DNA origami experiments. However, the practical applications of mica are relatively limited compared to those of semiconductor substrates. For this reason, a straightforward, stable, and repeatable process for DNA origami adhesion on derivatized silicon oxide is presented here. To promote the adhesion of DNA nanostructures to silicon oxide surface, a self-assembled monolayer of 3-aminopropyltriethoxysilane (APTES) is deposited from an aqueous solution that is compatible with many photoresists. The substrate must be cleaned of all organic and metal contaminants using Radio Corporation of America (RCA) cleaning processes and the native oxide layer must be etched to ensure a flat, functionalizable surface. Cleanrooms are equipped with facilities for silicon cleaning, however many components of DNA origami buffers and solutions are often not allowed in them due to contamination concerns. This manuscript describes the set-up and protocol for in-lab, small-scale silicon cleaning for researchers who do not have access to a cleanroom or would like to incorporate processes that could cause contamination of a cleanroom CMOS clean bench. Additionally, variables for regulating coverage are discussed and how to recognize and avoid common sample preparation problems is described. PMID:26274888

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Yu; School of Mechanical and Electrical Engineering, Wuhan Institute of Technology, Wuhan 430073; Guo, Zhiguang, E-mail: zguo@licp.cas.cn

Graphical abstract: A double-metal-assisted chemical etching method is employed to fabricate superhydrophobic surfaces, showing a good superhydrophobicity with the contact angle of about 170°, and the sliding angle of about 0°. Meanwhile, the potential formation mechanism about it is also presented. Highlights: ► A double-metal-assisted chemical etching method is employed to fabricate superhydrophobic surfaces. ► The obtained surfaces show good superhydrophobicity with a high contact angle and low sliding angle. ► The color of the etched substrate dark brown or black and it is so-called black silicon. -- Abstract: Silicon substrates treated by metal-assisted chemical etching have been studied formore » many years since they could be employed in a variety of electronic and optical devices such as integrated circuits, photovoltaics, sensors and detectors. However, to the best of our knowledge, the chemical etching treatment on the same silicon substrate with the assistance of two or more kinds of metals has not been reported. In this paper, we mainly focus on the etching time and finally obtain a series of superhydrophobic silicon surfaces with novel etching structures through two successive etching processes of Cu-assisted and Ag-assisted chemical etching. It is shown that large-scale homogeneous but locally irregular wire-like structures are obtained, and the superhydrophobic surfaces with low hysteresis are prepared after the modifications with low surface energy materials. It is worth noting that the final silicon substrates not only possess high static contact angle and low hysteresis angle, but also show a black color, indicating that the superhydrophobic silicon substrate has an extremely low reflectance in a certain range of wavelengths. In our future work, we will go a step further to discuss the effect of temperature, the size of Cu nanoparticles and solution concentration on the final topography and superhydrophobicity.« less

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, A.M.

1997-10-07

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50 C or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense. 57 figs.

Silicon on insulator achieved using electrochemical etching

DOEpatents

McCarthy, Anthony M.

1997-01-01

Bulk crystalline silicon wafers are transferred after the completion of circuit fabrication to form thin films of crystalline circuitry on almost any support, such as metal, semiconductor, plastic, polymer, glass, wood, and paper. In particular, this technique is suitable to form silicon-on-insulator (SOI) wafers, whereby the devices and circuits formed exhibit superior performance after transfer due to the removal of the silicon substrate. The added cost of the transfer process to conventional silicon fabrication is insignificant. No epitaxial, lift-off, release or buried oxide layers are needed to perform the transfer of single or multiple wafers onto support members. The transfer process may be performed at temperatures of 50.degree. C. or less, permits transparency around the circuits and does not require post-transfer patterning. Consequently, the technique opens up new avenues for the use of integrated circuit devices in high-brightness, high-resolution video-speed color displays, reduced-thickness increased-flexibility intelligent cards, flexible electronics on ultrathin support members, adhesive electronics, touch screen electronics, items requiring low weight materials, smart cards, intelligent keys for encryption systems, toys, large area circuits, flexible supports, and other applications. The added process flexibility also permits a cheap technique for increasing circuit speed of market driven technologies such as microprocessors at little added expense.

Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

NASA Astrophysics Data System (ADS)

Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

2018-03-01

A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

Distributed Capacitive Sensor for Sample Mass Measurement

NASA Technical Reports Server (NTRS)

Toda, Risaku; McKinney, Colin; Jackson, Shannon P.; Mojarradi, Mohammad; Manohara, Harish; Trebi-Ollennu, Ashitey

2011-01-01

Previous robotic sample return missions lacked in situ sample verification/ quantity measurement instruments. Therefore, the outcome of the mission remained unclear until spacecraft return. In situ sample verification systems such as this Distributed Capacitive (DisC) sensor would enable an unmanned spacecraft system to re-attempt the sample acquisition procedures until the capture of desired sample quantity is positively confirmed, thereby maximizing the prospect for scientific reward. The DisC device contains a 10-cm-diameter pressure-sensitive elastic membrane placed at the bottom of a sample canister. The membrane deforms under the weight of accumulating planetary sample. The membrane is positioned in close proximity to an opposing rigid substrate with a narrow gap. The deformation of the membrane makes the gap narrower, resulting in increased capacitance between the two parallel plates (elastic membrane and rigid substrate). C-V conversion circuits on a nearby PCB (printed circuit board) provide capacitance readout via LVDS (low-voltage differential signaling) interface. The capacitance method was chosen over other potential approaches such as the piezoelectric method because of its inherent temperature stability advantage. A reference capacitor and temperature sensor are embedded in the system to compensate for temperature effects. The pressure-sensitive membranes are aluminum 6061, stainless steel (SUS) 403, and metal-coated polyimide plates. The thicknesses of these membranes range from 250 to 500 m. The rigid substrate is made with a 1- to 2-mm-thick wafer of one of the following materials depending on the application requirements glass, silicon, polyimide, PCB substrate. The glass substrate is fabricated by a microelectromechanical systems (MEMS) fabrication approach. Several concentric electrode patterns are printed on the substrate. The initial gap between the two plates, 100 m, is defined by a silicon spacer ring that is anodically bonded to the glass substrate. The fabricated proof-of-concept devices have successfully demonstrated tens to hundreds of picofarads of capacitance change when a simulated sample (100 g to 500 g) is placed on the membrane.

Metal Oxide Thin Film Transistors on Paper Substrate: Fabrication, Characterization, and Printing Process

NASA Astrophysics Data System (ADS)

Choi, Nack-Bong

Flexible electronics is an emerging next-generation technology that offers many advantages such as light weight, durability, comfort, and flexibility. These unique features enable many new applications such as flexible display, flexible sensors, conformable electronics, and so forth. For decades, a variety of flexible substrates have been demonstrated for the application of flexible electronics. Most of them are plastic films and metal foils so far. For the fundamental device of flexible circuits, thin film transistors (TFTs) using poly silicon, amorphous silicon, metal oxide and organic semiconductor have been successfully demonstrated. Depending on application, low-cost and disposable flexible electronics will be required for convenience. Therefore it is important to study inexpensive substrates and to explore simple processes such as printing technology. In this thesis, paper is introduced as a new possible substrate for flexible electronics due to its low-cost and renewable property, and amorphous indium gallium zinc oxide (a-IGZO) TFTs are realized as the promising device on the paper substrate. The fabrication process and characterization of a-IGZO TFT on the paper substrate are discussed. a-IGZO TFTs using a polymer gate dielectric on the paper substrate demonstrate excellent performances with field effect mobility of ˜20 cm2 V-1 s-1, on/off current ratio of ˜106, and low leakage current, which show the enormous potential for flexible electronics application. In order to complement the n-channel a-IGZO TFTs and then enable complementary metal-oxide semiconductor (CMOS) circuit architectures, cuprous oxide is studied as a candidate material of p-channel oxide TFTs. In this thesis, a printing process is investigated as an alternative method for the fabrication of low-cost and disposable electronics. Among several printing methods, a modified offset roll printing that prints high resolution patterns is presented. A new method to fabricate a high resolution printing plate is investigated and the most favorable condition to transfer ink from a blanket to a cliche is studied. Consequently, a high resolution cliche is demonstrated and the printed patterns of 10mum width and 6mum line spacing are presented. In addition, the top gate a-IGZO TFTs with channel width/length of 12/6mum is successfully demonstrated by printing etch-resists. This work validates the compatibility of a-IGZO TFT on paper substrate for the disposable microelectronics application and presents the potential of low-cost and high resolution printing technology.

High performance and reusable SERS substrates using Ag/ZnO heterostructure on periodic silicon nanotube substrate

NASA Astrophysics Data System (ADS)

Lai, Yi-Chen; Ho, Hsin-Chia; Shih, Bo-Wei; Tsai, Feng-Yu; Hsueh, Chun-Hway

2018-05-01

Surface-enhanced Raman scattering (SERS) substrate with a higher surface area, enhanced light harvesting, multiple hot spots and strong electromagnetic field enhancements would exhibit enhanced Raman signals. Herein, the Ag nanoparticle/ZnO nanowire heterostructure decorated periodic silicon nanotube (Ag@ZnO@SiNT) substrate was proposed and fabricated. The proposed structure employed as SERS-active substrate was examined, and the results showed both the high performance in terms of high sensitivity and good reproducibility. Furthermore, the Ag@ZnO@SiNT substrate demonstrated the self-cleaning performance through the photocatalytic degradation of probed molecules upon UV-irradiation. The results showed that the proposed nanostructure had high performance, good reproducibility and reusability, and it is a promising SERS-active substrate for molecular sensing and cleaning.

Fabrication of spherical microlens array by combining lapping on silicon wafer and rapid surface molding

NASA Astrophysics Data System (ADS)

Liu, Xiaohua; Zhou, Tianfeng; Zhang, Lin; Zhou, Wenchen; Yu, Jianfeng; Lee, L. James; Yi, Allen Y.

2018-07-01

Silicon is a promising mold material for compression molding because of its properties of hardness and abrasion resistance. Silicon wafers with carbide-bonded graphene coating and micro-patterns were evaluated as molds for the fabrication of microlens arrays. This study presents an efficient but flexible manufacturing method for microlens arrays that combines a lapping method and a rapid molding procedure. Unlike conventional processes for microstructures on silicon wafers, such as diamond machining and photolithography, this research demonstrates a unique approach by employing precision steel balls and diamond slurries to create microlenses with accurate geometry. The feasibility of this method was demonstrated by the fabrication of several microlens arrays with different aperture sizes and pitches on silicon molds. The geometrical accuracy and surface roughness of the microlens arrays were measured using an optical profiler. The measurement results indicated good agreement with the optical profile of the design. The silicon molds were then used to copy the microstructures onto polymer substrates. The uniformity and quality of the samples molded through rapid surface molding were also assessed and statistically quantified. To further evaluate the optical functionality of the molded microlens arrays, the focal lengths of the microlens arrays were measured using a simple optical setup. The measurements showed that the microlens arrays molded in this research were compatible with conventional manufacturing methods. This research demonstrated an alternative low-cost and efficient method for microstructure fabrication on silicon wafers, together with the follow-up optical molding processes.

Patterning and photoluminescent properties of perovskite-type organic/inorganic hybrid luminescent films by soft lithography

NASA Astrophysics Data System (ADS)

Cheng, Z. Y.; Wang, Z.; Xing, R. B.; Han, Y. C.; Lin, J.

2003-07-01

Perovskite-type organic/inorganic hybrid layered compound (C 6H 5C 2H 4NH 3) 2PbI 4 was synthesized. The patterning of (C 6H 5C 2H 4NH 3) 2PbI 4 thin films on silicon substrate was realized by the micromolding in capillaries (MIMIC) process, a kind of soft lithography. Bright green luminescent stripes with different widths (50, 15, 0.8 μm) have been obtained. The structure and optical properties of (C 6H 5C 2H 4NH 3) 2PbI 4 films were characterized by X-ray diffraction (XRD), UV/Vis absorption and photoluminescence excitation and emission spectra, respectively. It is shown that the organic-inorganic layered (C 6H 5C 2H 4NH 3) 2PbI 4 film was c-axis oriented, paralleling to the substrate plane. Green exciton emission at 525 nm was observed in the film, and the explanations for it were given.

Understanding and controlling the step bunching instability in aqueous silicon etching

NASA Astrophysics Data System (ADS)

Bao, Hailing

Chemical etching of silicon has been widely used for more than half a century in the semiconductor industry. It not only forms the basis for current wafer cleaning processes, it also serves as a powerful tool to create a variety of surface morphologies for different applications. Its potential for controlling surface morphology at the atomic scale over micron-size regions is especially appealing. In spite of its wide usage, the chemistry of silicon etching is poorly understood. Many seemingly simple but fundamental questions have not been answered. As a result, the development of new etchants and new etching protocols are based on expensive and tedious trial-and-error experiments. A better understanding of the etching mechanism would direct the rational formulation of new etchants that produce controlled etch morphologies. Particularly, micron-scale step bunches spontaneously develop on the vicinal Si(111) surface etched in KOH or other anisotropic aqueous etchants. The ability to control the size, orientation, density and regularity of these surface features would greatly improve the performance of microelectromechanical devices. This study is directed towards understanding the chemistry and step bunching instability in aqueous anisotropic etching of silicon through a combination of experimental techniques and theoretical simulations. To reveal the cause of step-bunching instability, kinetic Monte Carlo simulations were constructed based on an atomistic model of the silicon lattice and a modified kinematic wave theory. The simulations showed that inhomogeneity was the origin of step-bunching, which was confirmed through STM studies of etch morphologies created under controlled flow conditions. To quantify the size of the inhomogeneities in different etchants and to clarify their effects, a five-parallel-trench pattern was fabricated. This pattern used a nitride mask to protect most regions of the wafer; five evenly spaced etch windows were opened to the Si(110) substrate. Combining data from these etched patterns and surface IR spectra, a modified mechanism, which explained most experimental observations, was proposed. Control of the step-bunching instability was accomplished with a second micromachined etch barrier pattern which consisted of a circular array of seventy-two long, narrow trenches in an etch mask. Using this pattern, well aligned, regularly shaped, evenly-distributed, near-atomically flat terraces in micron size were produced controllably.

Physical and biological evaluations of sintered hydroxyapatite/silicone composite with covalent bonding for a percutaneous implant material.

PubMed

Furuzono, Tsutomu; Wang, Pao-Li; Korematsu, Arata; Miyazaki, Kozo; Oido-Mori, Mari; Kowashi, Yusuke; Ohura, Kiyoshi; Tanaka, Junzo; Kishida, Akio

2003-05-15

A composite (HA/silicone) of hydroxyapatite (HA) microparticles with an average diameter of 2.0 micro m covalently linked to a silicone substrate has been developed, and its physical and biological properties as a percutaneous soft-tissue-compatible material have been evaluated. In tensile property measurement, samples of HA/silicone and the original silicone were similar in tensile strength, ca. 7.8 MPa, and elongation at break, ca. 570%. It was found that chemical surface modification with HA particles presented no mechanical disadvantage. In an adhesive-tape peeling test, scanning electron microscopic (SEM) observation showed that HA particles coupled directly to the substrate were not removed. HA particles may bond strongly with the substrate. In human periodontal ligament fibroblast attachment and proliferation experiments, the number of cells attached to HA/silicone was 14 times greater than that attached to the original silicone after 24 h of incubation. The value on HA/silicone was ca. 80% versus that on a tissue-culture plastic used as a positive control. After 72 h of incubation, the number of cells grown on HA/silicone increased to the level of the positive control. In observation of fluorescence microscopy stained by Hoechst 33342, cells appeared to tightly adhere to HA particles coupled to the silicone sheet due to intact nuclear morphology. Observation of cells by fluorescence dye with rhodamin phalloidin showed an extensive F-actin cytoskeleton on HA/silicone. In a 4-week animal implant test, force required to pull out the HA/silicone sheet was 15 times that of the original silicone. HA-particle coating on silicone with covalent linkage gave the inert surface bioactivity. The HA composite thus effectively prevents germ infection percutaneously. Copyright 2003 Wiley Periodicals, Inc. J Biomed Mater Res Part B: Appl Biomater 65B: 217-226, 2003

Method of Forming Textured Silicon Substrate by Maskless Cryogenic Etching

NASA Technical Reports Server (NTRS)

Yee, Karl Y. (Inventor); Homyk, Andrew P. (Inventor)

2014-01-01

Disclosed herein is a textured substrate comprising a base comprising silicon, the base having a plurality of needle like structures depending away from the base, wherein at least one of the needle like structures has a depth of greater than or equal to about 50 micrometers determined perpendicular to the base, and wherein at least one of the needle like structures has a width of less than or equal to about 50 micrometers determined parallel to the base. An anode and a lithium ion battery comprising the textured substrate, and a method of producing the textured substrate are also disclosed.

A sub-atmospheric chemical vapor deposition process for deposition of oxide liner in high aspect ratio through silicon vias.

PubMed

Lisker, Marco; Marschmeyer, Steffen; Kaynak, Mehmet; Tekin, Ibrahim

2011-09-01

The formation of a Through Silicon Via (TSV) includes a deep Si trench etching and the formation of an insulating layer along the high-aspect-ratio trench and the filling of a conductive material into the via hole. The isolation of the filling conductor from the silicon substrate becomes more important for higher frequencies due to the high coupling of the signal to the silicon. The importance of the oxide thickness on the via wall isolation can be verified using electromagnetic field simulators. To satisfy the needs on the Silicon dioxide deposition, a sub-atmospheric chemical vapor deposition (SA-CVD) process has been developed to deposit an isolation oxide to the walls of deep silicon trenches. The technique provides excellent step coverage of the 100 microm depth silicon trenches with the high aspect ratio of 20 and more. The developed technique allows covering the deep silicon trenches by oxide and makes the high isolation of TSVs from silicon substrate feasible which is the key factor for the performance of TSVs for mm-wave 3D packaging.

Light-induced V{sub oc} increase and decrease in high-efficiency amorphous silicon solar cells

DOE Office of Scientific and Technical Information (OSTI.GOV)

Stuckelberger, M., E-mail: michael.stuckelberger@epfl.ch; Riesen, Y.; Despeisse, M.

High-efficiency amorphous silicon (a-Si:H) solar cells were deposited with different thicknesses of the p-type amorphous silicon carbide layer on substrates of varying roughness. We observed a light-induced open-circuit voltage (V{sub oc}) increase upon light soaking for thin p-layers, but a decrease for thick p-layers. Further, the V{sub oc} increase is enhanced with increasing substrate roughness. After correction of the p-layer thickness for the increased surface area of rough substrates, we can exclude varying the effective p-layer thickness as the cause of the substrate roughness dependence. Instead, we explain the observations by an increase of the dangling-bond density in both themore » p-layer—causing a V{sub oc} increase—and in the intrinsic absorber layer, causing a V{sub oc} decrease. We present a mechanism for the light-induced increase and decrease, justified by the investigation of light-induced changes of the p-layer and supported by Advanced Semiconductor Analysis simulation. We conclude that a shift of the electron quasi-Fermi level towards the conduction band is the reason for the observed V{sub oc} enhancements, and poor amorphous silicon quality on rough substrates enhances this effect.« less