Execution of parallel algorithms on a heterogeneous multicomputer

NASA Astrophysics Data System (ADS)

Isenstein, Barry S.; Greene, Jonathon

1995-04-01

Many aerospace/defense sensing and dual-use applications require high-performance computing, extensive high-bandwidth interconnect and realtime deterministic operation. This paper will describe the architecture of a scalable multicomputer that includes DSP and RISC processors. A single chassis implementation is capable of delivering in excess of 10 GFLOPS of DSP processing power with 2 Gbytes/s of realtime sensor I/O. A software approach to implementing parallel algorithms called the Parallel Application System (PAS) is also presented. An example of applying PAS to a DSP application is shown.

SpaceWire Driver Software for Special DSPs

NASA Technical Reports Server (NTRS)

Clark, Douglas; Lux, James; Nishimoto, Kouji; Lang, Minh

2003-01-01

A computer program provides a high-level C-language interface to electronics circuitry that controls a SpaceWire interface in a system based on a space qualified version of the ADSP-21020 digital signal processor (DSP). SpaceWire is a spacecraft-oriented standard for packet-switching data-communication networks that comprise nodes connected through bidirectional digital serial links that utilize low-voltage differential signaling (LVDS). The software is tailored to the SMCS-332 application-specific integrated circuit (ASIC) (also available as the TSS901E), which provides three highspeed (150 Mbps) serial point-to-point links compliant with the proposed Institute of Electrical and Electronics Engineers (IEEE) Standard 1355.2 and equivalent European Space Agency (ESA) Standard ECSS-E-50-12. In the specific application of this software, the SpaceWire ASIC was combined with the DSP processor, memory, and control logic in a Multi-Chip Module DSP (MCM-DSP). The software is a collection of low-level driver routines that provide a simple message-passing application programming interface (API) for software running on the DSP. Routines are provided for interrupt-driven access to the two styles of interface provided by the SMCS: (1) the "word at a time" conventional host interface (HOCI); and (2) a higher performance "dual port memory" style interface (COMI).

Control of automated behavior: insights from the discrete sequence production task

PubMed Central

Abrahamse, Elger L.; Ruitenberg, Marit F. L.; de Kleine, Elian; Verwey, Willem B.

2013-01-01

Work with the discrete sequence production (DSP) task has provided a substantial literature on discrete sequencing skill over the last decades. The purpose of the current article is to provide a comprehensive overview of this literature and of the theoretical progress that it has prompted. We start with a description of the DSP task and the phenomena that are typically observed with it. Then we propose a cognitive model, the dual processor model (DPM), which explains performance of (skilled) discrete key-press sequences. Key features of this model are the distinction between a cognitive processor and a motor system (i.e., motor buffer and motor processor), the interplay between these two processing systems, and the possibility to execute familiar sequences in two different execution modes. We further discuss how this model relates to several related sequence skill research paradigms and models, and we outline outstanding questions for future research throughout the paper. We conclude by sketching a tentative neural implementation of the DPM. PMID:23515430

High performance 3D adaptive filtering for DSP based portable medical imaging systems

NASA Astrophysics Data System (ADS)

Bockenbach, Olivier; Ali, Murtaza; Wainwright, Ian; Nadeski, Mark

2015-03-01

Portable medical imaging devices have proven valuable for emergency medical services both in the field and hospital environments and are becoming more prevalent in clinical settings where the use of larger imaging machines is impractical. Despite their constraints on power, size and cost, portable imaging devices must still deliver high quality images. 3D adaptive filtering is one of the most advanced techniques aimed at noise reduction and feature enhancement, but is computationally very demanding and hence often cannot be run with sufficient performance on a portable platform. In recent years, advanced multicore digital signal processors (DSP) have been developed that attain high processing performance while maintaining low levels of power dissipation. These processors enable the implementation of complex algorithms on a portable platform. In this study, the performance of a 3D adaptive filtering algorithm on a DSP is investigated. The performance is assessed by filtering a volume of size 512x256x128 voxels sampled at a pace of 10 MVoxels/sec with an Ultrasound 3D probe. Relative performance and power is addressed between a reference PC (Quad Core CPU) and a TMS320C6678 DSP from Texas Instruments.

Communication-Driven Codesign for Multiprocessor Systems

DTIC Science & Technology

2004-01-01

processors, FPGA or ASIC subsystems, mi- croprocessors, and microcontrollers. When a processor is embedded within a SLOT architecture, one or more...Broderson, Low-power CMOS digital design, IEEE Journal of Solid-State Circuits 27 (1992), no. 4, 473–484. [25] L. Chao and E. Sha , Scheduling data-flow...1997), 239– 256 . [82] P. K. Murthy, E. G. Cohen, and S. Rowland, System Canvas: A new design en- vironment for embedded DSP and telecommunications

A DSP-based neural network non-uniformity correction algorithm for IRFPA

NASA Astrophysics Data System (ADS)

Liu, Chong-liang; Jin, Wei-qi; Cao, Yang; Liu, Xiu

2009-07-01

An effective neural network non-uniformity correction (NUC) algorithm based on DSP is proposed in this paper. The non-uniform response in infrared focal plane array (IRFPA) detectors produces corrupted images with a fixed-pattern noise(FPN).We introduced and analyzed the artificial neural network scene-based non-uniformity correction (SBNUC) algorithm. A design of DSP-based NUC development platform for IRFPA is described. The DSP hardware platform designed is of low power consumption, with 32-bit fixed point DSP TMS320DM643 as the kernel processor. The dependability and expansibility of the software have been improved by DSP/BIOS real-time operating system and Reference Framework 5. In order to realize real-time performance, the calibration parameters update is set at a lower task priority then video input and output in DSP/BIOS. In this way, calibration parameters updating will not affect video streams. The work flow of the system and the strategy of real-time realization are introduced. Experiments on real infrared imaging sequences demonstrate that this algorithm requires only a few frames to obtain high quality corrections. It is computationally efficient and suitable for all kinds of non-uniformity.

Single Event Effects (SEE) Testing of Embedded DSP Cores within Microsemi RTAX4000D Field Programmable Gate Array (FPGA) Devices

NASA Technical Reports Server (NTRS)

Perez, Christopher E.; Berg, Melanie D.; Friendlich, Mark R.

2011-01-01

Motivation for this work is: (1) Accurately characterize digital signal processor (DSP) core single-event effect (SEE) behavior (2) Test DSP cores across a large frequency range and across various input conditions (3) Isolate SEE analysis to DSP cores alone (4) Interpret SEE analysis in terms of single-event upsets (SEUs) and single-event transients (SETs) (5) Provide flight missions with accurate estimate of DSP core error rates and error signatures.

Computer Algorithms and Architectures for Three-Dimensional Eddy-Current Nondestructive Evaluation. Volume 3. Chapters 6-11

DTIC Science & Technology

1989-01-20

addressable memory can be loaded or off- loaded as the number crunching continues. Modem VLSI processors can often process data faster than today’s...Available DSP Chips Texas Instruments was one of the first serious manufacturers of DSP chips. With the Texas Instruments TMS310 DSP chip, modem , voice...Can handle double presicion data types. Texas Instruments TMS32010 T’s first-generation DSP design: a fixed-point DSP that has found its way into modem

Low-Power Embedded DSP Core for Communication Systems

NASA Astrophysics Data System (ADS)

Tsao, Ya-Lan; Chen, Wei-Hao; Tan, Ming Hsuan; Lin, Maw-Ching; Jou, Shyh-Jye

2003-12-01

This paper proposes a parameterized digital signal processor (DSP) core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility. The features of this DSP core include parameterized data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low-power structure, which includes the gray-code addressing mode, pipeline sharing, and advanced hardware looping. Users can select the parameters and special functional blocks based on the character of their applications and then generating a DSP core. The DSP core has been implemented via a cell-based design method using a synthesizable Verilog code with TSMC 0.35[InlineEquation not available: see fulltext.]m SPQM and 0.25[InlineEquation not available: see fulltext.]m 1P5M library. The equivalent gate count of the core area without memory is approximately 50 k. Moreover, the maximum operating frequency of a[InlineEquation not available: see fulltext.] version is 100 MHz (0.35[InlineEquation not available: see fulltext.]m) and 140 MHz (0.25[InlineEquation not available: see fulltext.]m).

A pipelined architecture for real time correction of non-uniformity in infrared focal plane arrays imaging system using multiprocessors

NASA Astrophysics Data System (ADS)

Zou, Liang; Fu, Zhuang; Zhao, YanZheng; Yang, JunYan

2010-07-01

This paper proposes a kind of pipelined electric circuit architecture implemented in FPGA, a very large scale integrated circuit (VLSI), which efficiently deals with the real time non-uniformity correction (NUC) algorithm for infrared focal plane arrays (IRFPA). Dual Nios II soft-core processors and a DSP with a 64+ core together constitute this image system. Each processor undertakes own systematic task, coordinating its work with each other's. The system on programmable chip (SOPC) in FPGA works steadily under the global clock frequency of 96Mhz. Adequate time allowance makes FPGA perform NUC image pre-processing algorithm with ease, which has offered favorable guarantee for the work of post image processing in DSP. And at the meantime, this paper presents a hardware (HW) and software (SW) co-design in FPGA. Thus, this systematic architecture yields an image processing system with multiprocessor, and a smart solution to the satisfaction with the performance of the system.

High frequency signal acquisition and control system based on DSP+FPGA

NASA Astrophysics Data System (ADS)

Liu, Xiao-qi; Zhang, Da-zhi; Yin, Ya-dong

2017-10-01

This paper introduces a design and implementation of high frequency signal acquisition and control system based on DSP + FPGA. The system supports internal/external clock and internal/external trigger sampling. It has a maximum sampling rate of 400MBPS and has a 1.4GHz input bandwidth for the ADC. Data can be collected continuously or periodically in systems and they are stored in DDR2. At the same time, the system also supports real-time acquisition, the collected data after digital frequency conversion and Cascaded Integrator-Comb (CIC) filtering, which then be sent to the CPCI bus through the high-speed DSP, can be assigned to the fiber board for subsequent processing. The system integrates signal acquisition and pre-processing functions, which uses high-speed A/D, high-speed DSP and FPGA mixed technology and has a wide range of uses in data acquisition and recording. In the signal processing, the system can be seamlessly connected to the dedicated processor board. The system has the advantages of multi-selectivity, good scalability and so on, which satisfies the different requirements of different signals in different projects.

Realization of a single image haze removal system based on DaVinci DM6467T processor

NASA Astrophysics Data System (ADS)

Liu, Zhuang

2014-10-01

Video monitoring system (VMS) has been extensively applied in domains of target recognition, traffic management, remote sensing, auto navigation and national defence. However the VMS has a strong dependence on the weather, for instance, in foggy weather, the quality of images received by the VMS are distinct degraded and the effective range of VMS is also decreased. All in all, the VMS performs terribly in bad weather. Thus the research of fog degraded images enhancement has very high theoretical and practical application value. A design scheme of a fog degraded images enhancement system based on the TI DaVinci processor is presented in this paper. The main function of the referred system is to extract and digital cameras capture images and execute image enhancement processing to obtain a clear image. The processor used in this system is the dual core TI DaVinci DM6467T - ARM@500MHz+DSP@1GH. A MontaVista Linux operating system is running on the ARM subsystem which handles I/O and application processing. The DSP handles signal processing and the results are available to the ARM subsystem in shared memory.The system benefits from the DaVinci processor so that, with lower power cost and smaller volume, it provides the equivalent image processing capability of a X86 computer. The outcome shows that the system in this paper can process images at 25 frames per second on D1 resolution.

Real-Time Neural Signals Decoding onto Off-the-Shelf DSP Processors for Neuroprosthetic Applications.

PubMed

Pani, Danilo; Barabino, Gianluca; Citi, Luca; Meloni, Paolo; Raspopovic, Stanisa; Micera, Silvestro; Raffo, Luigi

2016-09-01

The control of upper limb neuroprostheses through the peripheral nervous system (PNS) can allow restoring motor functions in amputees. At present, the important aspect of the real-time implementation of neural decoding algorithms on embedded systems has been often overlooked, notwithstanding the impact that limited hardware resources have on the efficiency/effectiveness of any given algorithm. Present study is addressing the optimization of a template matching based algorithm for PNS signals decoding that is a milestone for its real-time, full implementation onto a floating-point digital signal processor (DSP). The proposed optimized real-time algorithm achieves up to 96% of correct classification on real PNS signals acquired through LIFE electrodes on animals, and can correctly sort spikes of a synthetic cortical dataset with sufficiently uncorrelated spike morphologies (93% average correct classification) comparably to the results obtained with top spike sorter (94% on average on the same dataset). The power consumption enables more than 24 h processing at the maximum load, and latency model has been derived to enable a fair performance assessment. The final embodiment demonstrates the real-time performance onto a low-power off-the-shelf DSP, opening to experiments exploiting the efferent signals to control a motor neuroprosthesis.

Portable laser speckle perfusion imaging system based on digital signal processor.

PubMed

Tang, Xuejun; Feng, Nengyun; Sun, Xiaoli; Li, Pengcheng; Luo, Qingming

2010-12-01

The ability to monitor blood flow in vivo is of major importance in clinical diagnosis and in basic researches of life science. As a noninvasive full-field technique without the need of scanning, laser speckle contrast imaging (LSCI) is widely used to study blood flow with high spatial and temporal resolution. Current LSCI systems are based on personal computers for image processing with large size, which potentially limit the widespread clinical utility. The need for portable laser speckle contrast imaging system that does not compromise processing efficiency is crucial in clinical diagnosis. However, the processing of laser speckle contrast images is time-consuming due to the heavy calculation for enormous high-resolution image data. To address this problem, a portable laser speckle perfusion imaging system based on digital signal processor (DSP) and the algorithm which is suitable for DSP is described. With highly integrated DSP and the algorithm, we have markedly reduced the size and weight of the system as well as its energy consumption while preserving the high processing speed. In vivo experiments demonstrate that our portable laser speckle perfusion imaging system can obtain blood flow images at 25 frames per second with the resolution of 640 × 480 pixels. The portable and lightweight features make it capable of being adapted to a wide variety of application areas such as research laboratory, operating room, ambulance, and even disaster site.

Modis, SeaWIFS, and Pathfinder funded activities

NASA Technical Reports Server (NTRS)

Evans, Robert H.

1995-01-01

MODIS (Moderate Resolution Imaging Spectrometer), SeaWIFS (Sea-viewing Wide Field Sensor), Pathfinder, and DSP (Digital Signal Processor) objectives are summarized. An overview of current progress is given for the automatic processing database, client/server status, matchup database, and DSP support.

Parallel processing approach to transform-based image coding

NASA Astrophysics Data System (ADS)

Normile, James O.; Wright, Dan; Chu, Ken; Yeh, Chia L.

1991-06-01

This paper describes a flexible parallel processing architecture designed for use in real time video processing. The system consists of floating point DSP processors connected to each other via fast serial links, each processor has access to a globally shared memory. A multiple bus architecture in combination with a dual ported memory allows communication with a host control processor. The system has been applied to prototyping of video compression and decompression algorithms. The decomposition of transform based algorithms for decompression into a form suitable for parallel processing is described. A technique for automatic load balancing among the processors is developed and discussed, results ar presented with image statistics and data rates. Finally techniques for accelerating the system throughput are analyzed and results from the application of one such modification described.

A distributed control system for the lower-hybrid current drive system on the Tokamak de Varennes

NASA Astrophysics Data System (ADS)

Bagdoo, J.; Guay, J. M.; Chaudron, G.-A.; Decoste, R.; Demers, Y.; Hubbard, A.

1990-08-01

An rf current drive system with an output power of 1 MW at 3.7 GHz is under development for the Tokamak de Varennes. The control system is based on an Ethernet local-area network of programmable logic controllers as front end, personal computers as consoles, and CAMAC-based DSP processors. The DSP processors ensure the PID control of the phase and rf power of each klystron, and the fast protection of high-power rf hardware, all within a 40 μs loop. Slower control and protection, event sequencing and the run-time database are provided by the programmable logic controllers, which communicate, via the LAN, with the consoles. The latter run a commercial process-control console software. The LAN protocol respects the first four layers of the ISO/OSI 802.3 standard. Synchronization with the tokamak control system is provided by commercially available CAMAC timing modules which trigger shot-related events and reference waveform generators. A detailed description of each subsystem and a performance evaluation of the system will be presented.

Code Compression for DSP

DTIC Science & Technology

1998-12-01

PAGES 6 19a. NAME OF RESPONSIBLE PERSON a. REPORT unclassified b . ABSTRACT unclassified c. THIS PAGE unclassified Standard Form 298 (Rev. 8...Automation Conference, June 1998. [Liao95] S. Liao, S. Devadas , K. Keutzer, “Code Density Optimization for Embedded DSP Processors Using Data Compression

The research and application of multi-biometric acquisition embedded system

NASA Astrophysics Data System (ADS)

Deng, Shichao; Liu, Tiegen; Guo, Jingjing; Li, Xiuyan

2009-11-01

The identification technology based on multi-biometric can greatly improve the applicability, reliability and antifalsification. This paper presents a multi-biometric system bases on embedded system, which includes: three capture daughter boards are applied to obtain different biometric: one each for fingerprint, iris and vein of the back of hand; FPGA (Field Programmable Gate Array) is designed as coprocessor, which uses to configure three daughter boards on request and provides data path between DSP (digital signal processor) and daughter boards; DSP is the master processor and its functions include: control the biometric information acquisition, extracts feature as required and responsible for compare the results with the local database or data server through network communication. The advantages of this system were it can acquire three different biometric in real time, extracts complexity feature flexibly in different biometrics' raw data according to different purposes and arithmetic and network interface on the core-board will be the solution of big data scale. Because this embedded system has high stability, reliability, flexibility and fit for different data scale, it can satisfy the demand of multi-biometric recognition.

MoNET: media over net gateway processor for next-generation network

NASA Astrophysics Data System (ADS)

Elabd, Hammam; Sundar, Rangarajan; Dedes, John

2001-12-01

MoNETTM (Media over Net) SX000 product family is designed using a scalable voice, video and packet-processing platform to address applications with channel densities from few voice channels to four OC3 per card. This platform is developed for bridging public circuit-switched network to the next generation packet telephony and data network. The platform consists of a DSP farm, RISC processors and interface modules. DSP farm is required to execute voice compression, image compression and line echo cancellation algorithms for large number of voice, video, fax, and modem or data channels. RISC CPUs are used for performing various packetizations based on RTP, UDP/IP and ATM encapsulations. In addition, RISC CPUs also participate in the DSP farm load management and communication with the host and other MoP devices. The MoNETTM S1000 communications device is designed for voice processing and for bridging TDM to ATM and IP packet networks. The S1000 consists of the DSP farm based on Carmel DSP core and 32-bit RISC CPU, along with Ethernet, Utopia, PCI, and TDM interfaces. In this paper, we will describe the VoIP infrastructure, building blocks of the S500, S1000 and S3000 devices, algorithms executed on these device and associated channel densities, detailed DSP architecture, memory architecture, data flow and scheduling.

Feasibility of an ultra-low power digital signal processor platform as a basis for a fully implantable brain-computer interface system.

PubMed

Wang, Po T; Gandasetiawan, Keulanna; McCrimmon, Colin M; Karimi-Bidhendi, Alireza; Liu, Charles Y; Heydari, Payam; Nenadic, Zoran; Do, An H

2016-08-01

A fully implantable brain-computer interface (BCI) can be a practical tool to restore independence to those affected by spinal cord injury. We envision that such a BCI system will invasively acquire brain signals (e.g. electrocorticogram) and translate them into control commands for external prostheses. The feasibility of such a system was tested by implementing its benchtop analogue, centered around a commercial, ultra-low power (ULP) digital signal processor (DSP, TMS320C5517, Texas Instruments). A suite of signal processing and BCI algorithms, including (de)multiplexing, Fast Fourier Transform, power spectral density, principal component analysis, linear discriminant analysis, Bayes rule, and finite state machine was implemented and tested in the DSP. The system's signal acquisition fidelity was tested and characterized by acquiring harmonic signals from a function generator. In addition, the BCI decoding performance was tested, first with signals from a function generator, and subsequently using human electroencephalogram (EEG) during eyes opening and closing task. On average, the system spent 322 ms to process and analyze 2 s of data. Crosstalk (<;-65 dB) and harmonic distortion (~1%) were minimal. Timing jitter averaged 49 μs per 1000 ms. The online BCI decoding accuracies were 100% for both function generator and EEG data. These results show that a complex BCI algorithm can be executed on an ULP DSP without compromising performance. This suggests that the proposed hardware platform may be used as a basis for future, fully implantable BCI systems.

Design and evaluation of an architecture for a digital signal processor for instrumentation applications

NASA Astrophysics Data System (ADS)

Fellman, Ronald D.; Kaneshiro, Ronald T.; Konstantinides, Konstantinos

1990-03-01

The authors present the design and evaluation of an architecture for a monolithic, programmable, floating-point digital signal processor (DSP) for instrumentation applications. An investigation of the most commonly used algorithms in instrumentation led to a design that satisfies the requirements for high computational and I/O (input/output) throughput. In the arithmetic unit, a 16- x 16-bit multiplier and a 32-bit accumulator provide the capability for single-cycle multiply/accumulate operations, and three format adjusters automatically adjust the data format for increased accuracy and dynamic range. An on-chip I/O unit is capable of handling data block transfers through a direct memory access port and real-time data streams through a pair of parallel I/O ports. I/O operations and program execution are performed in parallel. In addition, the processor includes two data memories with independent addressing units, a microsequencer with instruction RAM, and multiplexers for internal data redirection. The authors also present the structure and implementation of a design environment suitable for the algorithmic, behavioral, and timing simulation of a complete DSP system. Various benchmarking results are reported.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Poivey, C.; Notebaert, O.; Garnier, P.

The ARIANE5 On Board Computer (OBC) and Inertial Reference System (SRI) are based on Motorola MC68020 processor and MC68882 coprocessor. The SRI data acquisition board also uses the DSP TMS320C25 from Texas Instruments. These devices were characterized to proton induced SEUs. But representativeness of SEU test results on processors was questioned during ARIANE5 studies. Protons test of these devices were also performed in the actual equipments with flight (or representative of) softwares. The results show that the On Board Computer and the Inertial Reference System can satisfy the requirements of the ARIANE5 missions.

[Image processing system of visual prostheses based on digital signal processor DM642].

PubMed

Xie, Chengcheng; Lu, Yanyu; Gu, Yun; Wang, Jing; Chai, Xinyu

2011-09-01

This paper employed a DSP platform to create the real-time and portable image processing system, and introduced a series of commonly used algorithms for visual prostheses. The results of performance evaluation revealed that this platform could afford image processing algorithms to be executed in real time.

System on a chip with MPEG-4 capability

NASA Astrophysics Data System (ADS)

Yassa, Fathy; Schonfeld, Dan

2002-12-01

Current products supporting video communication applications rely on existing computer architectures. RISC processors have been used successfully in numerous applications over several decades. DSP processors have become ubiquitous in signal processing and communication applications. Real-time applications such as speech processing in cellular telephony rely extensively on the computational power of these processors. Video processors designed to implement the computationally intensive codec operations have also been used to address the high demands of video communication applications (e.g., cable set-top boxes and DVDs). This paper presents an overview of a system-on-chip (SOC) architecture used for real-time video in wireless communication applications. The SOC specifications answer to the system requirements imposed by the application environment. A CAM-based video processor is used to accelerate data intensive video compression tasks such as motion estimations and filtering. Other components are dedicated to system level data processing and audio processing. A rich set of I/Os allows the SOC to communicate with other system components such as baseband and memory subsystems.

Advanced Power Electronic Interfaces for Distributed Energy Systems, Part 2: Modeling, Development, and Experimental Evaluation of Advanced Control Functions for Single-Phase Utility-Connected Inverter

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chakraborty, S.; Kroposki, B.; Kramer, W.

Integrating renewable energy and distributed generations into the Smart Grid architecture requires power electronic (PE) for energy conversion. The key to reaching successful Smart Grid implementation is to develop interoperable, intelligent, and advanced PE technology that improves and accelerates the use of distributed energy resource systems. This report describes the simulation, design, and testing of a single-phase DC-to-AC inverter developed to operate in both islanded and utility-connected mode. It provides results on both the simulations and the experiments conducted, demonstrating the ability of the inverter to provide advanced control functions such as power flow and VAR/voltage regulation. This report alsomore » analyzes two different techniques used for digital signal processor (DSP) code generation. Initially, the DSP code was written in C programming language using Texas Instrument's Code Composer Studio. In a later stage of the research, the Simulink DSP toolbox was used to self-generate code for the DSP. The successful tests using Simulink self-generated DSP codes show promise for fast prototyping of PE controls.« less

Real-time separation of multineuron recordings with a DSP32C signal processor.

PubMed

Gädicke, R; Albus, K

1995-04-01

We have developed a hardware and software package for real-time discrimination of multiple-unit activities recorded simultaneously from multiple microelectrodes using a VME-Bus system. Compared with other systems cited in literature or commercially available, our system has the following advantages. (1) Each electrode is served by its own preprocessor (DSP32C); (2) On-line spike discrimination is performed independently for each electrode. (3) The VME-bus allows processing of data received from 16 electrodes. The digitized (62.5 kHz) spike form is itself used as the model spike; the algorithm allows for comparing and sorting complete wave forms in real time into 8 different models per electrode.

DDGIPS: a general image processing system in robot vision

NASA Astrophysics Data System (ADS)

Tian, Yuan; Ying, Jun; Ye, Xiuqing; Gu, Weikang

2000-10-01

Real-Time Image Processing is the key work in robot vision. With the limitation of the hardware technique, many algorithm-oriented firmware systems were designed in the past. But their architectures were not flexible enough to achieve a multi-algorithm development system. Because of the rapid development of microelectronics technique, many high performance DSP chips and high density FPGA chips have come to life, and this makes it possible to construct a more flexible architecture in real-time image processing system. In this paper, a Double DSP General Image Processing System (DDGIPS) is concerned. We try to construct a two-DSP-based FPGA-computational system with two TMS320C6201s. The TMS320C6x devices are fixed-point processors based on the advanced VLIW CPU, which has eight functional units, including two multipliers and six arithmetic logic units. These features make C6x a good candidate for a general purpose system. In our system, the two TMS320C6201s each has a local memory space, and they also have a shared system memory space which enables them to intercommunicate and exchange data efficiently. At the same time, they can be directly inter-connected in star-shaped architecture. All of these are under the control of a FPGA group. As the core of the system, FPGA plays a very important role: it takes charge of DPS control, DSP communication, memory space access arbitration and the communication between the system and the host machine. And taking advantage of reconfiguring FPGA, all of the interconnection between the two DSP or between DSP and FPGA can be changed. In this way, users can easily rebuild the real-time image processing system according to the data stream and the task of the application and gain great flexibility.

DDGIPS: a general image processing system in robot vision

NASA Astrophysics Data System (ADS)

Tian, Yuan; Ying, Jun; Ye, Xiuqing; Gu, Weikang

2000-10-01

Real-Time Image Processing is the key work in robot vision. With the limitation of the hardware technique, many algorithm-oriented firmware systems were designed in the past. But their architectures were not flexible enough to achieve a multi- algorithm development system. Because of the rapid development of microelectronics technique, many high performance DSP chips and high density FPGA chips have come to life, and this makes it possible to construct a more flexible architecture in real-time image processing system. In this paper, a Double DSP General Image Processing System (DDGIPS) is concerned. We try to construct a two-DSP-based FPGA-computational system with two TMS320C6201s. The TMS320C6x devices are fixed-point processors based on the advanced VLIW CPU, which has eight functional units, including two multipliers and six arithmetic logic units. These features make C6x a good candidate for a general purpose system. In our system, the two TMS320C6210s each has a local memory space, and they also have a shared system memory space which enable them to intercommunicate and exchange data efficiently. At the same time, they can be directly interconnected in star- shaped architecture. All of these are under the control of FPGA group. As the core of the system, FPGA plays a very important role: it takes charge of DPS control, DSP communication, memory space access arbitration and the communication between the system and the host machine. And taking advantage of reconfiguring FPGA, all of the interconnection between the two DSP or between DSP and FPGA can be changed. In this way, users can easily rebuild the real-time image processing system according to the data stream and the task of the application and gain great flexibility.

Architectures for single-chip image computing

NASA Astrophysics Data System (ADS)

Gove, Robert J.

1992-04-01

This paper will focus on the architectures of VLSI programmable processing components for image computing applications. TI, the maker of industry-leading RISC, DSP, and graphics components, has developed an architecture for a new-generation of image processors capable of implementing a plurality of image, graphics, video, and audio computing functions. We will show that the use of a single-chip heterogeneous MIMD parallel architecture best suits this class of processors--those which will dominate the desktop multimedia, document imaging, computer graphics, and visualization systems of this decade.

Modular uncooled video engines based on a DSP processor

NASA Astrophysics Data System (ADS)

Schapiro, F.; Milstain, Y.; Aharon, A.; Neboshchik, A.; Ben-Simon, Y.; Kogan, I.; Lerman, I.; Mizrahi, U.; Maayani, S.; Amsterdam, A.; Vaserman, I.; Duman, O.; Gazit, R.

2011-06-01

The market demand for low SWaP (Size, Weight and Power) uncooled engines keeps growing. Low SWaP is especially critical in battery-operated applications such as goggles and Thermal Weapon Sights. A new approach for the design of the engines was implemented by SCD to optimize size and power consumption at system level. The new approach described in the paper, consists of: 1. A modular hardware design that allows the user to define the exact level of integration needed for his system 2. An "open architecture" based on the OMAPTM530 DSP that allows the integrator to take advantage of unused hardware (FPGA) and software (DSP) resources, for implementation of additional algorithms or functionality. The approach was successfully implemented on the first generation of 25μm pitch BIRD detectors, and more recently on the new, 640 x480, 17 μm pitch detector.

Low-power wireless ECG acquisition and classification system for body sensor networks.

PubMed

Lee, Shuenn-Yuh; Hong, Jia-Hua; Hsieh, Cheng-Han; Liang, Ming-Chun; Chang Chien, Shih-Yu; Lin, Kuang-Hao

2015-01-01

A low-power biosignal acquisition and classification system for body sensor networks is proposed. The proposed system consists of three main parts: 1) a high-pass sigma delta modulator-based biosignal processor (BSP) for signal acquisition and digitization, 2) a low-power, super-regenerative on-off keying transceiver for short-range wireless transmission, and 3) a digital signal processor (DSP) for electrocardiogram (ECG) classification. The BSP and transmitter circuits, which are the body-end circuits, can be operated for over 80 days using two 605 mAH zinc-air batteries as the power supply; the power consumption is 586.5 μW. As for the radio frequency receiver and DSP, which are the receiving-end circuits that can be integrated in smartphones or personal computers, power consumption is less than 1 mW. With a wavelet transform-based digital signal processing circuit and a diagnosis control by cardiologists, the accuracy of beat detection and ECG classification are close to 99.44% and 97.25%, respectively. All chips are fabricated in TSMC 0.18-μm standard CMOS process.

Dataflow Integration and Simulation Techniques for DSP System Design Tools

DTIC Science & Technology

2007-01-01

Lebak, M. Richards , and D. Campbell, “VSIPL: An object-based open standard API for vector, signal, and image processing,” in Proceedings of the...Inc., document Version 0.98a. [56] P. Marwedel and G. Goossens , Eds., Code Generation for Embedded Processors. Kluwer Academic Publishers, 1995. [57

Automatic calibration system for analog instruments based on DSP and CCD sensor

NASA Astrophysics Data System (ADS)

Lan, Jinhui; Wei, Xiangqin; Bai, Zhenlong

2008-12-01

Currently, the calibration work of analog measurement instruments is mainly completed by manual and there are many problems waiting for being solved. In this paper, an automatic calibration system (ACS) based on Digital Signal Processor (DSP) and Charge Coupled Device (CCD) sensor is developed and a real-time calibration algorithm is presented. In the ACS, TI DM643 DSP processes the data received by CCD sensor and the outcome is displayed on Liquid Crystal Display (LCD) screen. For the algorithm, pointer region is firstly extracted for improving calibration speed. And then a math model of the pointer is built to thin the pointer and determine the instrument's reading. Through numbers of experiments, the time of once reading is no more than 20 milliseconds while it needs several seconds if it is done manually. At the same time, the error of the instrument's reading satisfies the request of the instruments. It is proven that the automatic calibration system can effectively accomplish the calibration work of the analog measurement instruments.

DSP Implementation of the Retinex Image Enhancement Algorithm

NASA Technical Reports Server (NTRS)

Hines, Glenn; Rahman, Zia-Ur; Jobson, Daniel; Woodell, Glenn

2004-01-01

The Retinex is a general-purpose image enhancement algorithm that is used to produce good visual representations of scenes. It performs a non-linear spatial/spectral transform that synthesizes strong local contrast enhancement and color constancy. A real-time, video frame rate implementation of the Retinex is required to meet the needs of various potential users. Retinex processing contains a relatively large number of complex computations, thus to achieve real-time performance using current technologies requires specialized hardware and software. In this paper we discuss the design and development of a digital signal processor (DSP) implementation of the Retinex. The target processor is a Texas Instruments TMS320C6711 floating point DSP. NTSC video is captured using a dedicated frame-grabber card, Retinex processed, and displayed on a standard monitor. We discuss the optimizations used to achieve real-time performance of the Retinex and also describe our future plans on using alternative architectures.

Texas Instruments-Digital Signal Processor(TI-DSP)SMJ320F20 SEL Testing

NASA Technical Reports Server (NTRS)

Sanders, Anthony B.; Poivey, C.; Kim, H. S.; Gee, George B.

2006-01-01

This viewgraph presentation reviews the testing of the Texas Instrument Digital Signal Processor(TI-DSP)SMJ320F20. Tests were performed to screen for susceptibility to Single Event Latchup (SEL) and measure sensitivity as a function of Linear Energy Transfer (LET) for an application specific test setup. The Heavy Ion Testing of two TI-DSP SMJ320F240 devices experienced Single Event Latchup (SEL) conditions at an LET of 1.8 MeV/(mg/square cm) The devices were exposed from a fluence of 1.76 x l0(exp 3) to 5.00 x 10(exp 6) particles/square cm of the Neon, Argon and Krypton ion beams. For DI(sub DD) an average latchup current occurred at about 700mA, which is a magnitude of 10 over the nominal current of 700mA.

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Monenegro, Justino (Technical Monitor)

2002-01-01

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Low-cost, digital lock-in module with external reference for coating glass transmission/reflection spectrophotometer

NASA Astrophysics Data System (ADS)

Alonso, R.; Villuendas, F.; Borja, J.; Barragán, L. A.; Salinas, I.

2003-05-01

A versatile, low-cost, digital signal processor (DSP) based lock-in module with external reference is described. This module is used to implement an industrial spectrophotometer for measuring spectral transmission and reflection of automotive and architectonic coating glasses over the ultraviolet, visible and near-infrared wavelength range. The light beams are modulated with an optical chopper. A digital phase-locked loop (DPLL) is used to lock the lock-in to the chop frequency. The lock-in rejects the ambient radiation and permits the spectrophotometer to work in the presence of ambient light. The algorithm that implements the dual lock-in and the DPLL in the DSP56002 evaluation module from Motorola is described. The use of a DSP allows implementation of the lock-in and DPLL by software, which gives flexibility and programmability to the system. Lock-in module cost, under 300 euro, is an important parameter taking into account that two modules are used in the system. Besides, the algorithms implemented in this DSP can be directly implemented in the latest DSP generations. The DPLL performance and the spectrophotometer are characterized. Capture and lock DPLL ranges have been measured and checked to be greater than the chop frequency drifts. The lock-in measured frequency response shows that the lock-in performs as theoretically predicted.

Single-Scale Retinex Using Digital Signal Processors

NASA Technical Reports Server (NTRS)

Hines, Glenn; Rahman, Zia-Ur; Jobson, Daniel; Woodell, Glenn

2005-01-01

The Retinex is an image enhancement algorithm that improves the brightness, contrast and sharpness of an image. It performs a non-linear spatial/spectral transform that provides simultaneous dynamic range compression and color constancy. It has been used for a wide variety of applications ranging from aviation safety to general purpose photography. Many potential applications require the use of Retinex processing at video frame rates. This is difficult to achieve with general purpose processors because the algorithm contains a large number of complex computations and data transfers. In addition, many of these applications also constrain the potential architectures to embedded processors to save power, weight and cost. Thus we have focused on digital signal processors (DSPs) and field programmable gate arrays (FPGAs) as potential solutions for real-time Retinex processing. In previous efforts we attained a 21 (full) frame per second (fps) processing rate for the single-scale monochromatic Retinex with a TMS320C6711 DSP operating at 150 MHz. This was achieved after several significant code improvements and optimizations. Since then we have migrated our design to the slightly more powerful TMS320C6713 DSP and the fixed point TMS320DM642 DSP. In this paper we briefly discuss the Retinex algorithm, the performance of the algorithm executing on the TMS320C6713 and the TMS320DM642, and compare the results with the TMS320C6711.

Segmentation of financial seals and its implementation on a DSP-based system

NASA Astrophysics Data System (ADS)

He, Jin; Liu, Tiegen; Guo, Jingjing; Zhang, Hao

2009-11-01

Automatic seal imprint identification is an important part of modern financial security. Accurate segmentation is the basis of correct identification. In this paper, a DSP (digital signal processor) based identification system was designed, and an adaptive algorithm was proposed to extract binary seal images from financial instruments. As the kernel of the identification system, a DSP chip of TMS320DM642 was used to implement image processing, controlling and coordinating works of each system module. The proposed algorithm consisted of three stages, including extraction of grayscale seal image, denoising and binarization. A grayscale seal image was extracted by color transform from a financial instrument image. Adaptive morphological operations were used to highlight details of the extracted grayscale seal image and smooth the background. After median filter for noise elimination, the filtered seal image was binarized by Otsu's method. The algorithm was developed based on the DSP development environment CCS and real-time operation system DSP/BIOS. To simplify the implementation of the proposed algorithm, the calibration of white balance and the coarse positioning of the seal imprint were implemented by TMS320DM642 controlling image acquisition. IMGLIB of TMS320DM642 was used for the efficiency improvement. The experiment result showed that financial seal imprints, even with intricate and dense strokes can be correctly segmented by the proposed algorithm. Adhesion and incompleteness distortions in the segmentation results were reduced, even when the original seal imprint had a poor quality.

SpaceCubeX: A Framework for Evaluating Hybrid Multi-Core CPU FPGA DSP Architectures

NASA Technical Reports Server (NTRS)

Schmidt, Andrew G.; Weisz, Gabriel; French, Matthew; Flatley, Thomas; Villalpando, Carlos Y.

2017-01-01

The SpaceCubeX project is motivated by the need for high performance, modular, and scalable on-board processing to help scientists answer critical 21st century questions about global climate change, air quality, ocean health, and ecosystem dynamics, while adding new capabilities such as low-latency data products for extreme event warnings. These goals translate into on-board processing throughput requirements that are on the order of 100-1,000 more than those of previous Earth Science missions for standard processing, compression, storage, and downlink operations. To study possible future architectures to achieve these performance requirements, the SpaceCubeX project provides an evolvable testbed and framework that enables a focused design space exploration of candidate hybrid CPU/FPGA/DSP processing architectures. The framework includes ArchGen, an architecture generator tool populated with candidate architecture components, performance models, and IP cores, that allows an end user to specify the type, number, and connectivity of a hybrid architecture. The framework requires minimal extensions to integrate new processors, such as the anticipated High Performance Spaceflight Computer (HPSC), reducing time to initiate benchmarking by months. To evaluate the framework, we leverage a wide suite of high performance embedded computing benchmarks and Earth science scenarios to ensure robust architecture characterization. We report on our projects Year 1 efforts and demonstrate the capabilities across four simulation testbed models, a baseline SpaceCube 2.0 system, a dual ARM A9 processor system, a hybrid quad ARM A53 and FPGA system, and a hybrid quad ARM A53 and DSP system.

CORDIC-based digital signal processing (DSP) element for adaptive signal processing

NASA Astrophysics Data System (ADS)

Bolstad, Gregory D.; Neeld, Kenneth B.

1995-04-01

The High Performance Adaptive Weight Computation (HAWC) processing element is a CORDIC based application specific DSP element that, when connected in a linear array, can perform extremely high throughput (100s of GFLOPS) matrix arithmetic operations on linear systems of equations in real time. In particular, it very efficiently performs the numerically intense computation of optimal least squares solutions for large, over-determined linear systems. Most techniques for computing solutions to these types of problems have used either a hard-wired, non-programmable systolic array approach, or more commonly, programmable DSP or microprocessor approaches. The custom logic methods can be efficient, but are generally inflexible. Approaches using multiple programmable generic DSP devices are very flexible, but suffer from poor efficiency and high computation latencies, primarily due to the large number of DSP devices that must be utilized to achieve the necessary arithmetic throughput. The HAWC processor is implemented as a highly optimized systolic array, yet retains some of the flexibility of a programmable data-flow system, allowing efficient implementation of algorithm variations. This provides flexible matrix processing capabilities that are one to three orders of magnitude less expensive and more dense than the current state of the art, and more importantly, allows a realizable solution to matrix processing problems that were previously considered impractical to physically implement. HAWC has direct applications in RADAR, SONAR, communications, and image processing, as well as in many other types of systems.

A real-time tracking system of infrared dim and small target based on FPGA and DSP

NASA Astrophysics Data System (ADS)

Rong, Sheng-hui; Zhou, Hui-xin; Qin, Han-lin; Wang, Bing-jian; Qian, Kun

2014-11-01

A core technology in the infrared warning system is the detection tracking of dim and small targets with complicated background. Consequently, running the detection algorithm on the hardware platform has highly practical value in the military field. In this paper, a real-time detection tracking system of infrared dim and small target which is used FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) as the core was designed and the corresponding detection tracking algorithm and the signal flow is elaborated. At the first stage, the FPGA obtain the infrared image sequence from the sensor, then it suppresses background clutter by mathematical morphology method and enhances the target intensity by Laplacian of Gaussian operator. At the second stage, the DSP obtain both the original image and the filtered image form the FPGA via the video port. Then it segments the target from the filtered image by an adaptive threshold segmentation method and gets rid of false target by pipeline filter. Experimental results show that our system can achieve higher detection rate and lower false alarm rate.

DSP code optimization based on cache

NASA Astrophysics Data System (ADS)

Xu, Chengfa; Li, Chengcheng; Tang, Bin

2013-03-01

DSP program's running efficiency on board is often lower than which via the software simulation during the program development, which is mainly resulted from the user's improper use and incomplete understanding of the cache-based memory. This paper took the TI TMS320C6455 DSP as an example, analyzed its two-level internal cache, and summarized the methods of code optimization. Processor can achieve its best performance when using these code optimization methods. At last, a specific algorithm application in radar signal processing is proposed. Experiment result shows that these optimization are efficient.

On-Board, Real-Time Preprocessing System for Optical Remote-Sensing Imagery

PubMed Central

Qi, Baogui; Zhuang, Yin; Chen, He; Chen, Liang

2018-01-01

With the development of remote-sensing technology, optical remote-sensing imagery processing has played an important role in many application fields, such as geological exploration and natural disaster prevention. However, relative radiation correction and geometric correction are key steps in preprocessing because raw image data without preprocessing will cause poor performance during application. Traditionally, remote-sensing data are downlinked to the ground station, preprocessed, and distributed to users. This process generates long delays, which is a major bottleneck in real-time applications for remote-sensing data. Therefore, on-board, real-time image preprocessing is greatly desired. In this paper, a real-time processing architecture for on-board imagery preprocessing is proposed. First, a hierarchical optimization and mapping method is proposed to realize the preprocessing algorithm in a hardware structure, which can effectively reduce the computation burden of on-board processing. Second, a co-processing system using a field-programmable gate array (FPGA) and a digital signal processor (DSP; altogether, FPGA-DSP) based on optimization is designed to realize real-time preprocessing. The experimental results demonstrate the potential application of our system to an on-board processor, for which resources and power consumption are limited. PMID:29693585

Very low cost real time histogram-based contrast enhancer utilizing fixed-point DSP processing

NASA Astrophysics Data System (ADS)

McCaffrey, Nathaniel J.; Pantuso, Francis P.

1998-03-01

A real time contrast enhancement system utilizing histogram- based algorithms has been developed to operate on standard composite video signals. This low-cost DSP based system is designed with fixed-point algorithms and an off-chip look up table (LUT) to reduce the cost considerably over other contemporary approaches. This paper describes several real- time contrast enhancing systems advanced at the Sarnoff Corporation for high-speed visible and infrared cameras. The fixed-point enhancer was derived from these high performance cameras. The enhancer digitizes analog video and spatially subsamples the stream to qualify the scene's luminance. Simultaneously, the video is streamed through a LUT that has been programmed with the previous calculation. Reducing division operations by subsampling reduces calculation- cycles and also allows the processor to be used with cameras of nominal resolutions. All values are written to the LUT during blanking so no frames are lost. The enhancer measures 13 cm X 6.4 cm X 3.2 cm, operates off 9 VAC and consumes 12 W. This processor is small and inexpensive enough to be mounted with field deployed security cameras and can be used for surveillance, video forensics and real- time medical imaging.

On-Board, Real-Time Preprocessing System for Optical Remote-Sensing Imagery.

PubMed

Qi, Baogui; Shi, Hao; Zhuang, Yin; Chen, He; Chen, Liang

2018-04-25

With the development of remote-sensing technology, optical remote-sensing imagery processing has played an important role in many application fields, such as geological exploration and natural disaster prevention. However, relative radiation correction and geometric correction are key steps in preprocessing because raw image data without preprocessing will cause poor performance during application. Traditionally, remote-sensing data are downlinked to the ground station, preprocessed, and distributed to users. This process generates long delays, which is a major bottleneck in real-time applications for remote-sensing data. Therefore, on-board, real-time image preprocessing is greatly desired. In this paper, a real-time processing architecture for on-board imagery preprocessing is proposed. First, a hierarchical optimization and mapping method is proposed to realize the preprocessing algorithm in a hardware structure, which can effectively reduce the computation burden of on-board processing. Second, a co-processing system using a field-programmable gate array (FPGA) and a digital signal processor (DSP; altogether, FPGA-DSP) based on optimization is designed to realize real-time preprocessing. The experimental results demonstrate the potential application of our system to an on-board processor, for which resources and power consumption are limited.

Overview of the DART project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berry, K.R.; Hansen, F.R.; Napolitano, L.M.

1992-01-01

DART (DSP Arrary for Reconfigurable Tasks) is a parallel architecture of two high-performance SDP (digital signal processing) chips with the flexibility to handle a wide range of real-time applications. Each of the 32-bit floating-point DSP processes in DART is programmable in a high-level languate ( C'' or Ada). We have added extensions to the real-time operating system used by DART in order to support parallel processor. The combination of high-level language programmability, a real-time operating system, and parallel processing support significantly reduces the development cost of application software for signal processing and control applications. We have demonstrated this capability bymore » using DART to reconstruct images in the prototype VIP (Video Imaging Projectile) groundstation.« less

Overview of the DART project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berry, K.R.; Hansen, F.R.; Napolitano, L.M.

1992-01-01

DART (DSP Arrary for Reconfigurable Tasks) is a parallel architecture of two high-performance SDP (digital signal processing) chips with the flexibility to handle a wide range of real-time applications. Each of the 32-bit floating-point DSP processes in DART is programmable in a high-level languate (``C`` or Ada). We have added extensions to the real-time operating system used by DART in order to support parallel processor. The combination of high-level language programmability, a real-time operating system, and parallel processing support significantly reduces the development cost of application software for signal processing and control applications. We have demonstrated this capability by usingmore » DART to reconstruct images in the prototype VIP (Video Imaging Projectile) groundstation.« less

Automated speech understanding: the next generation

NASA Astrophysics Data System (ADS)

Picone, J.; Ebel, W. J.; Deshmukh, N.

1995-04-01

Modern speech understanding systems merge interdisciplinary technologies from Signal Processing, Pattern Recognition, Natural Language, and Linguistics into a unified statistical framework. These systems, which have applications in a wide range of signal processing problems, represent a revolution in Digital Signal Processing (DSP). Once a field dominated by vector-oriented processors and linear algebra-based mathematics, the current generation of DSP-based systems rely on sophisticated statistical models implemented using a complex software paradigm. Such systems are now capable of understanding continuous speech input for vocabularies of several thousand words in operational environments. The current generation of deployed systems, based on small vocabularies of isolated words, will soon be replaced by a new technology offering natural language access to vast information resources such as the Internet, and provide completely automated voice interfaces for mundane tasks such as travel planning and directory assistance.

The research of laser marking control technology

NASA Astrophysics Data System (ADS)

Zhang, Qiue; Zhang, Rong

2009-08-01

In the area of Laser marking, the general control method is insert control card to computer's mother board, it can not support hot swap, it is difficult to assemble or it. Moreover, the one marking system must to equip one computer. In the system marking, the computer can not to do the other things except to transmit marking digital information. Otherwise it can affect marking precision. Based on traditional control methods existed some problems, introduced marking graphic editing and digital processing by the computer finish, high-speed digital signal processor (DSP) control marking the whole process. The laser marking controller is mainly contain DSP2812, digital memorizer, DAC (digital analog converting) transform unit circuit, USB interface control circuit, man-machine interface circuit, and other logic control circuit. Download the marking information which is processed by computer to U disk, DSP read the information by USB interface on time, then processing it, adopt the DSP inter timer control the marking time sequence, output the scanner control signal by D/A parts. Apply the technology can realize marking offline, thereby reduce the product cost, increase the product efficiency. The system have good effect in actual unit markings, the marking speed is more quickly than PCI control card to 20 percent. It has application value in practicality.

A customizable system for real-time image processing using the Blackfin DSProcessor and the MicroC/OS-II real-time kernel

NASA Astrophysics Data System (ADS)

Coffey, Stephen; Connell, Joseph

2005-06-01

This paper presents a development platform for real-time image processing based on the ADSP-BF533 Blackfin processor and the MicroC/OS-II real-time operating system (RTOS). MicroC/OS-II is a completely portable, ROMable, pre-emptive, real-time kernel. The Blackfin Digital Signal Processors (DSPs), incorporating the Analog Devices/Intel Micro Signal Architecture (MSA), are a broad family of 16-bit fixed-point products with a dual Multiply Accumulate (MAC) core. In addition, they have a rich instruction set with variable instruction length and both DSP and MCU functionality thus making them ideal for media based applications. Using the MicroC/OS-II for task scheduling and management, the proposed system can capture and process raw RGB data from any standard 8-bit greyscale image sensor in soft real-time and then display the processed result using a simple PC graphical user interface (GUI). Additionally, the GUI allows configuration of the image capture rate and the system and core DSP clock rates thereby allowing connectivity to a selection of image sensors and memory devices. The GUI also allows selection from a set of image processing algorithms based in the embedded operating system.

Integrated optical 3D digital imaging based on DSP scheme

NASA Astrophysics Data System (ADS)

Wang, Xiaodong; Peng, Xiang; Gao, Bruce Z.

2008-03-01

We present a scheme of integrated optical 3-D digital imaging (IO3DI) based on digital signal processor (DSP), which can acquire range images independently without PC support. This scheme is based on a parallel hardware structure with aid of DSP and field programmable gate array (FPGA) to realize 3-D imaging. In this integrated scheme of 3-D imaging, the phase measurement profilometry is adopted. To realize the pipeline processing of the fringe projection, image acquisition and fringe pattern analysis, we present a multi-threads application program that is developed under the environment of DSP/BIOS RTOS (real-time operating system). Since RTOS provides a preemptive kernel and powerful configuration tool, with which we are able to achieve a real-time scheduling and synchronization. To accelerate automatic fringe analysis and phase unwrapping, we make use of the technique of software optimization. The proposed scheme can reach a performance of 39.5 f/s (frames per second), so it may well fit into real-time fringe-pattern analysis and can implement fast 3-D imaging. Experiment results are also presented to show the validity of proposed scheme.

High Speed A/D DSP Interface for Carrier Doppler Tracking

NASA Technical Reports Server (NTRS)

Baggett, Timothy

1998-01-01

As on-board satellite systems continue to increase in ability to perform self diagnostic checks, it will become more important for satellites to initiate ground communications contact. Currently, the NASA Space Network requires users to pre-arranged times for satellite communications links through the Tracking and Data Relay Satellite (TDRS). One of the challenges in implementing an on-demand access protocol into the Space Network, is the fact that a low Earth orbiting (LEO) satellite's communications will be subject to a doppler shift which is outside the capability of the NASA ground station to lock onto. In a prearranged system, the satellite's doppler is known a priori, and the ground station is able to lock onto the satellite's signal. This paper describes the development of a high speed analog to digital interface into a Digital Signal Processor (DSP). This system will be used for identifying the doppler shift of a LEO satellite through the Space Network, and aiding the ground station equipment in locking onto the signal. Although this interface is specific to one application, it can be used as a basis for interfacing other devices with a DSP.

A DSP equipped digitizer for online analysis of nuclear detector signals

NASA Astrophysics Data System (ADS)

Pasquali, G.; Ciaranfi, R.; Bardelli, L.; Bini, M.; Boiano, A.; Giannelli, F.; Ordine, A.; Poggi, G.

2007-01-01

In the framework of the NUCL-EX collaboration, a DSP equipped fast digitizer has been implemented and it has now reached the production stage. Each sampling channel is implemented on a separate daughter-board to be plugged on a VME mother-board. Each channel features a 12-bit, 125 MSamples/s ADC and a Digital Signal Processor (DSP) for online analysis of detector signals. A few algorithms have been written and successfully tested on detectors of different types (scintillators, solid-state, gas-filled), implementing pulse shape discrimination, constant fraction timing, semi-Gaussian shaping, gated integration.

JPRS Report Science & Technology Europe.

DTIC Science & Technology

1992-09-17

9 Jul 92] 48 HERA Project Gets Green Light for Quark Structure Analysis [DuesseldorfVDI NACHRICHTEN, 12 Jul 92] .... 48 TELECOMMUNICATIONS...communicating with the control station. The demonstrator is the product of research performed at the Robot and Artificial Intel - ligence Unit of...from the microphones, speedometers, or tachometers. Each board is linked to a Motorola DSP [digital signal processor ]. Although the system has been

Long-Wavelength Beam Steerer Based on a Micro-Electromechanical Mirror

PubMed Central

Kos, Anthony B; Gerecht, Eyal

2013-01-01

Commercially available mirrors for scanning long-wavelength beams are too large for high-speed imaging. There is a need for a smaller, more agile pointing apparatus to provide images in seconds, not minutes or hours. A fast long-wavelength beam steerer uses a commercial micro-electro-mechanical system (MEMS) mirror controlled by a high-performance digital signal processor (DSP). The DSP allows high-speed raster scanning of the incident radiation, which is focused to a small waist onto the 9mm2, gold-coated, MEMS mirror surface, while simultaneously acquiring an undistorted, high spatial-resolution image of an object. The beam steerer hardware, software and performance are described. The system can also serve as a miniaturized, high-performance long-wavelength beam chopper for lock-in detection. PMID:26401426

Ambulatory REACT: real-time seizure detection with a DSP microprocessor.

PubMed

McEvoy, Robert P; Faul, Stephen; Marnane, William P

2010-01-01

REACT (Real-Time EEG Analysis for event deteCTion) is a Support Vector Machine based technology which, in recent years, has been successfully applied to the problem of automated seizure detection in both adults and neonates. This paper describes the implementation of REACT on a commercial DSP microprocessor; the Analog Devices Blackfin®. The primary aim of this work is to develop a prototype system for use in ambulatory or in-ward automated EEG analysis. Furthermore, the complexity of the various stages of the REACT algorithm on the Blackfin processor is analysed; in particular the EEG feature extraction stages. This hardware profile is used to select a reduced, platform-aware feature set, in order to evaluate the seizure classification accuracy of a lower-complexity, lower-power REACT system.

Design of an anti-Rician-fading modem for mobile satellite communication systems

NASA Technical Reports Server (NTRS)

Kojima, Toshiharu; Ishizu, Fumio; Miyake, Makoto; Murakami, Keishi; Fujino, Tadashi

1995-01-01

To design a demodulator applicable to mobile satellite communication systems using differential phase shift keying modulation, we have developed key technologies including an anti-Rician-fading demodulation scheme, an initial acquisition scheme, automatic gain control (AGC), automatic frequency control (AFC), and bit timing recovery (BTR). Using these technologies, we have developed one-chip digital signal processor (DSP) modem for mobile terminal, which is compact, of light weight, and of low power consumption. Results of performance test show that the developed DSP modem achieves good performance in terms of bit error ratio in mobile satellite communication environment, i.e., Rician fading channel. It is also shown that the initial acquisition scheme acquires received signal rapidly even if the carrier-to-noise power ratio (CNR) of the received signal is considerably low.

Stereo and IMU-Assisted Visual Odometry for Small Robots

NASA Technical Reports Server (NTRS)

2012-01-01

This software performs two functions: (1) taking stereo image pairs as input, it computes stereo disparity maps from them by cross-correlation to achieve 3D (three-dimensional) perception; (2) taking a sequence of stereo image pairs as input, it tracks features in the image sequence to estimate the motion of the cameras between successive image pairs. A real-time stereo vision system with IMU (inertial measurement unit)-assisted visual odometry was implemented on a single 750 MHz/520 MHz OMAP3530 SoC (system on chip) from TI (Texas Instruments). Frame rates of 46 fps (frames per second) were achieved at QVGA (Quarter Video Graphics Array i.e. 320 240), or 8 fps at VGA (Video Graphics Array 640 480) resolutions, while simultaneously tracking up to 200 features, taking full advantage of the OMAP3530's integer DSP (digital signal processor) and floating point ARM processors. This is a substantial advancement over previous work as the stereo implementation produces 146 Mde/s (millions of disparities evaluated per second) in 2.5W, yielding a stereo energy efficiency of 58.8 Mde/J, which is 3.75 better than prior DSP stereo while providing more functionality.

Preliminary Study of Image Reconstruction Algorithm on a Digital Signal Processor

DTIC Science & Technology

2014-03-01

5.2 Comparison of CPU-GPU, CPU-FPGA, and CPU-DSP Designs The work for implementing VHDL description of the back-projection algorithm on a physical...FPGA was not complete. Hence, the DSP implementation results are compared with the simulated results for the VHDL design. Simulating VHDL provides an...rather than at the software level. Depending on an application’s characteristics, FPGA implementations can provide a significant performance

Feasibility Study on a Portable Field Pest Classification System Design Based on DSP and 3G Wireless Communication Technology

PubMed Central

Han, Ruizhen; He, Yong; Liu, Fei

2012-01-01

This paper presents a feasibility study on a real-time in field pest classification system design based on Blackfin DSP and 3G wireless communication technology. This prototype system is composed of remote on-line classification platform (ROCP), which uses a digital signal processor (DSP) as a core CPU, and a host control platform (HCP). The ROCP is in charge of acquiring the pest image, extracting image features and detecting the class of pest using an Artificial Neural Network (ANN) classifier. It sends the image data, which is encoded using JPEG 2000 in DSP, to the HCP through the 3G network at the same time for further identification. The image transmission and communication are accomplished using 3G technology. Our system transmits the data via a commercial base station. The system can work properly based on the effective coverage of base stations, no matter the distance from the ROCP to the HCP. In the HCP, the image data is decoded and the pest image displayed in real-time for further identification. Authentication and performance tests of the prototype system were conducted. The authentication test showed that the image data were transmitted correctly. Based on the performance test results on six classes of pests, the average accuracy is 82%. Considering the different live pests’ pose and different field lighting conditions, the result is satisfactory. The proposed technique is well suited for implementation in field pest classification on-line for precision agriculture. PMID:22736996

Feasibility study on a portable field pest classification system design based on DSP and 3G wireless communication technology.

PubMed

Han, Ruizhen; He, Yong; Liu, Fei

2012-01-01

This paper presents a feasibility study on a real-time in field pest classification system design based on Blackfin DSP and 3G wireless communication technology. This prototype system is composed of remote on-line classification platform (ROCP), which uses a digital signal processor (DSP) as a core CPU, and a host control platform (HCP). The ROCP is in charge of acquiring the pest image, extracting image features and detecting the class of pest using an Artificial Neural Network (ANN) classifier. It sends the image data, which is encoded using JPEG 2000 in DSP, to the HCP through the 3G network at the same time for further identification. The image transmission and communication are accomplished using 3G technology. Our system transmits the data via a commercial base station. The system can work properly based on the effective coverage of base stations, no matter the distance from the ROCP to the HCP. In the HCP, the image data is decoded and the pest image displayed in real-time for further identification. Authentication and performance tests of the prototype system were conducted. The authentication test showed that the image data were transmitted correctly. Based on the performance test results on six classes of pests, the average accuracy is 82%. Considering the different live pests' pose and different field lighting conditions, the result is satisfactory. The proposed technique is well suited for implementation in field pest classification on-line for precision agriculture.

Interior Noise Reduction by Adaptive Feedback Vibration Control

NASA Technical Reports Server (NTRS)

Lim, Tae W.

1998-01-01

The objective of this project is to investigate the possible use of adaptive digital filtering techniques in simultaneous, multiple-mode identification of the modal parameters of a vibrating structure in real-time. It is intended that the results obtained from this project will be used for state estimation needed in adaptive structural acoustics control. The work done in this project is basically an extension of the work on real-time single mode identification, which was performed successfully using a digital signal processor (DSP) at NASA, Langley. Initially, in this investigation the single mode identification work was duplicated on a different processor, namely the Texas Instruments TMS32OC40 DSP. The system identification results for the single mode case were very good. Then an algorithm for simultaneous two mode identification was developed and tested using analytical simulation. When it successfully performed the expected tasks, it was implemented in real-time on the DSP system to identify the first two modes of vibration of a cantilever aluminum beam. The results of the simultaneous two mode case were good but some problems were identified related to frequency warping and spurious mode identification. The frequency warping problem was found to be due to the bilinear transformation used in the algorithm to convert the system transfer function from the continuous-time domain to the discrete-time domain. An alternative approach was developed to rectify the problem. The spurious mode identification problem was found to be associated with high sampling rates. Noise in the signal is suspected to be the cause of this problem but further investigation will be needed to clarify the cause. For simultaneous identification of more than two modes, it was found that theoretically an adaptive digital filter can be designed to identify the required number of modes, but the algebra became very complex which made it impossible to implement in the DSP system used in this study. The on-line identification algorithm developed in this research will be useful in constructing a state estimator for feedback vibration control.

PCI-based WILDFIRE reconfigurable computing engines

NASA Astrophysics Data System (ADS)

Fross, Bradley K.; Donaldson, Robert L.; Palmer, Douglas J.

1996-10-01

WILDFORCE is the first PCI-based custom reconfigurable computer that is based on the Splash 2 technology transferred from the National Security Agency and the Institute for Defense Analyses, Supercomputing Research Center (SRC). The WILDFORCE architecture has many of the features of the WILDFIRE computer, such as field- programmable gate array (FPGA) based processing elements, linear array and crossbar interconnection, and high- performance memory and I/O subsystems. New features introduced in the PCI-based WILDFIRE systems include memory/processor options that can be added to any processing element. These options include static and dynamic memory, digital signal processors (DSPs), FPGAs, and microprocessors. In addition to memory/processor options, many different application specific connectors can be used to extend the I/O capabilities of the system, including systolic I/O, camera input and video display output. This paper also discusses how this new PCI-based reconfigurable computing engine is used for rapid-prototyping, real-time video processing and other DSP applications.

Night-day-night sleep-wakefulness monitoring by ambulatory integrated circuit memories.

PubMed

Yamamoto, M; Nakao, M; Katayama, N; Waku, M; Suzuki, K; Irokawa, K; Abe, M; Ueno, T

1999-04-01

A medium-sized portable digital recorder with fully integrated circuit (IC) memories for sleep monitoring has been developed. It has five amplifiers for EEG, EMG, EOG, ECG, and a signal of body acceleration or respiration sound, four event markers, an 8 ch A/D converter, a digital signal processor (DSP), 192 Mbytes IC flash memories, and batteries. The whole system weighs 1200 g including batteries and is put into a small bag worn on the subject's waist or carried in their hand. The sampling rate for each input channel is programmable through the DSP. This apparatus is valuable for continuously monitoring the states of sleep-wakefulness over 24 h, making a night-day-night recording possible in a hospital, home, or car.

Fast and robust control of nanopositioning systems: Performance limits enabled by field programmable analog arrays.

PubMed

Baranwal, Mayank; Gorugantu, Ram S; Salapaka, Srinivasa M

2015-08-01

This paper aims at control design and its implementation for robust high-bandwidth precision (nanoscale) positioning systems. Even though modern model-based control theoretic designs for robust broadband high-resolution positioning have enabled orders of magnitude improvement in performance over existing model independent designs, their scope is severely limited by the inefficacies of digital implementation of the control designs. High-order control laws that result from model-based designs typically have to be approximated with reduced-order systems to facilitate digital implementation. Digital systems, even those that have very high sampling frequencies, provide low effective control bandwidth when implementing high-order systems. In this context, field programmable analog arrays (FPAAs) provide a good alternative to the use of digital-logic based processors since they enable very high implementation speeds, moreover with cheaper resources. The superior flexibility of digital systems in terms of the implementable mathematical and logical functions does not give significant edge over FPAAs when implementing linear dynamic control laws. In this paper, we pose the control design objectives for positioning systems in different configurations as optimal control problems and demonstrate significant improvements in performance when the resulting control laws are applied using FPAAs as opposed to their digital counterparts. An improvement of over 200% in positioning bandwidth is achieved over an earlier digital signal processor (DSP) based implementation for the same system and same control design, even when for the DSP-based system, the sampling frequency is about 100 times the desired positioning bandwidth.

Achieving supercomputer performance for neural net simulation with an array of digital signal processors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Muller, U.A.; Baumle, B.; Kohler, P.

1992-10-01

Music, a DSP-based system with a parallel distributed-memory architecture, provides enormous computing power yet retains the flexibility of a general-purpose computer. Reaching a peak performance of 2.7 Gflops at a significantly lower cost, power consumption, and space requirement than conventional supercomputers, Music is well suited to computationally intensive applications such as neural network simulation. 12 refs., 9 figs., 2 tabs.

Implantable control, telemetry, and solar energy system in the moving actuator type total artificial heart.

PubMed

Ahn, J M; Lee, J H; Choi, S W; Kim, W E; Omn, K S; Park, S K; Kim, W G; Roh, J R; Min, B G

1998-03-01

The moving actuator type total artificial heart (TAH) developed in the Seoul National University has numerous design improvements based upon the digital signal processor (DSP). These improvements include the implantability of all electronics, an automatic control algorithm, and extension of the battery run-time in connection with an amorphous silicon solar system (SS). The implantable electronics consist of the motor drive, main processor, intelligent Li ion battery management (LIBM) based upon the DSP, telemetry system, and transcutaneous energy transmission (TET) system. Major changes in the implantable electronics include decreasing the temperature rise by over 21 degrees C on the motor drive, volume reduction (40 x 55 x 33 mm, 7 cell assembly) of the battery pack using a Li ion (3.6 V/cell, 900 mA.h), and improvement of the battery run-time (over 40 min) while providing the cardiac output (CO) of 5 L/min at 100 mm Hg afterload when the external battery for testing is connected with the SS (2.5 W, 192.192, 1 kg) for the external battery recharge or the partial TAH drive. The phase locked loop (PLL) based telemetry system was implemented to improve stability and the error correction DSP algorithm programmed to achieve high accuracy. A field focused light emitting diode (LED) was used to obtain low light scattering along the propagation path, similar to the optical property of the laser and miniature sized, mounted on the pancake type TET coils. The TET operating resonance frequency was self tuned in a range of 360 to 410 kHz to provide enough power even at high afterloads. An automatic cardiac output regulation algorithm was developed based on interventricular pressure analysis and carried out in several animal experiments successfully. All electronics have been evaluated in vitro and in vivo and prepared for implantation of the TAH. Substantial progress has been made in designing a completely implantable TAH at the preclinical stage.

Multiformat decoder for a DSP-based IP set-top box

NASA Astrophysics Data System (ADS)

Pescador, F.; Garrido, M. J.; Sanz, C.; Juárez, E.; Samper, D.; Antoniello, R.

2007-05-01

Internet Protocol Set-Top Boxes (IP STBs) based on single-processor architectures have been recently introduced in the market. In this paper, the implementation of an MPEG-4 SP/ASP video decoder for a multi-format IP STB based on a TMS320DM641 DSP is presented. An initial decoder for PC platform was fully tested and ported to the DSP. Using this code an optimization process was started achieving a 90% speedup. This process allows real-time MPEG-4 SP/ASP decoding. The MPEG-4 decoder has been integrated in an IP STB and tested in a real environment using DVD movies and TV channels with excellent results.

Fast neural net simulation with a DSP processor array.

PubMed

Muller, U A; Gunzinger, A; Guggenbuhl, W

1995-01-01

This paper describes the implementation of a fast neural net simulator on a novel parallel distributed-memory computer. A 60-processor system, named MUSIC (multiprocessor system with intelligent communication), is operational and runs the backpropagation algorithm at a speed of 330 million connection updates per second (continuous weight update) using 32-b floating-point precision. This is equal to 1.4 Gflops sustained performance. The complete system with 3.8 Gflops peak performance consumes less than 800 W of electrical power and fits into a 19-in rack. While reaching the speed of modern supercomputers, MUSIC still can be used as a personal desktop computer at a researcher's own disposal. In neural net simulation, this gives a computing performance to a single user which was unthinkable before. The system's real-time interfaces make it especially useful for embedded applications.

Developing infrared array controller with software real time operating system

NASA Astrophysics Data System (ADS)

Sako, Shigeyuki; Miyata, Takashi; Nakamura, Tomohiko; Motohara, Kentaro; Uchimoto, Yuka Katsuno; Onaka, Takashi; Kataza, Hirokazu

2008-07-01

Real-time capabilities are required for a controller of a large format array to reduce a dead-time attributed by readout and data transfer. The real-time processing has been achieved by dedicated processors including DSP, CPLD, and FPGA devices. However, the dedicated processors have problems with memory resources, inflexibility, and high cost. Meanwhile, a recent PC has sufficient resources of CPUs and memories to control the infrared array and to process a large amount of frame data in real-time. In this study, we have developed an infrared array controller with a software real-time operating system (RTOS) instead of the dedicated processors. A Linux PC equipped with a RTAI extension and a dual-core CPU is used as a main computer, and one of the CPU cores is allocated to the real-time processing. A digital I/O board with DMA functions is used for an I/O interface. The signal-processing cores are integrated in the OS kernel as a real-time driver module, which is composed of two virtual devices of the clock processor and the frame processor tasks. The array controller with the RTOS realizes complicated operations easily, flexibly, and at a low cost.

An Intrinsically Digital Amplification Scheme for Hearing Aids

NASA Astrophysics Data System (ADS)

Blamey, Peter J.; Macfarlane, David S.; Steele, Brenton R.

2005-12-01

Results for linear and wide-dynamic range compression were compared with a new 64-channel digital amplification strategy in three separate studies. The new strategy addresses the requirements of the hearing aid user with efficient computations on an open-platform digital signal processor (DSP). The new amplification strategy is not modeled on prior analog strategies like compression and linear amplification, but uses statistical analysis of the signal to optimize the output dynamic range in each frequency band independently. Using the open-platform DSP processor also provided the opportunity for blind trial comparisons of the different processing schemes in BTE and ITE devices of a high commercial standard. The speech perception scores and questionnaire results show that it is possible to provide improved audibility for sound in many narrow frequency bands while simultaneously improving comfort, speech intelligibility in noise, and sound quality.

Parallel processor for real-time structural control

NASA Astrophysics Data System (ADS)

Tise, Bert L.

1993-07-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-to-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection to host computer, parallelizing code generator, and look- up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating- point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An OpenWindows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.

Field oriented control of induction motors

NASA Technical Reports Server (NTRS)

Burrows, Linda M.; Zinger, Don S.; Roth, Mary Ellen

1990-01-01

Induction motors have always been known for their simple rugged construction, but until lately were not suitable for variable speed or servo drives due to the inherent complexity of the controls. With the advent of field oriented control (FOC), however, the induction motor has become an attractive option for these types of drive systems. An FOC system which utilizes the pulse population modulation method to synthesize the motor drive frequencies is examined. This system allows for a variable voltage to frequency ratio and enables the user to have independent control of both the speed and torque of an induction motor. A second generation of the control boards were developed and tested with the next point of focus being the minimization of the size and complexity of these controls. Many options were considered with the best approach being the use of a digital signal processor (DSP) due to its inherent ability to quickly evaluate control algorithms. The present test results of the system and the status of the optimization process using a DSP are discussed.

The design of an adaptive predictive coder using a single-chip digital signal processor

NASA Astrophysics Data System (ADS)

Randolph, M. A.

1985-01-01

A speech coding processor architecture design study has been performed in which Texas Instruments TMS32010 has been selected from among three commercially available digital signal processing integrated circuits and evaluated in an implementation study of real-time Adaptive Predictive Coding (APC). The TMS32010 has been compared with AR&T Bell Laboratories DSP I and Nippon Electric Co. PD7720 and was found to be most suitable for a single chip implementation of APC. A preliminary design system based on TMS32010 has been performed, and several of the hardware and software design issues are discussed. Particular attention was paid to the design of an external memory controller which permits rapid sequential access of external RAM. As a result, it has been determined that a compact hardware implementation of the APC algorithm is feasible based of the TSM32010. Originator-supplied keywords include: vocoders, speech compression, adaptive predictive coding, digital signal processing microcomputers, speech processor architectures, and special purpose processor.

Universal sensor interface module (USIM)

NASA Astrophysics Data System (ADS)

King, Don; Torres, A.; Wynn, John

1999-01-01

A universal sensor interface model (USIM) is being developed by the Raytheon-TI Systems Company for use with fields of unattended distributed sensors. In its production configuration, the USIM will be a multichip module consisting of a set of common modules. The common module USIM set consists of (1) a sensor adapter interface (SAI) module, (2) digital signal processor (DSP) and associated memory module, and (3) a RF transceiver model. The multispectral sensor interface is designed around a low-power A/D converted, whose input/output interface consists of: -8 buffered, sampled inputs from various devices including environmental, acoustic seismic and magnetic sensors. The eight sensor inputs are each high-impedance, low- capacitance, differential amplifiers. The inputs are ideally suited for interface with discrete or MEMS sensors, since the differential input will allow direct connection with high-impedance bridge sensors and capacitance voltage sources. Each amplifier is connected to a 22-bit (Delta) (Sigma) A/D converter to enable simultaneous samples. The low power (Delta) (Sigma) converter provides 22-bit resolution at sample frequencies up to 142 hertz (used for magnetic sensors) and 16-bit resolution at frequencies up to 1168 hertz (used for acoustic and seismic sensors). The video interface module is based around the TMS320C5410 DSP. It can provide sensor array addressing, video data input, data calibration and correction. The processor module is based upon a MPC555. It will be used for mode control, synchronization of complex sensors, sensor signal processing, array processing, target classification and tracking. Many functions of the A/D, DSP and transceiver can be powered down by using variable clock speeds under software command or chip power switches. They can be returned to intermediate or full operation by DSP command. Power management may be based on the USIM's internal timer, command from the USIM transceiver, or by sleep mode processing management. The low power detection mode is implemented by monitoring any of the sensor analog outputs at lower sample rates for detection over a software controllable threshold.

Real-Time Visualization of Tissue Ischemia

NASA Technical Reports Server (NTRS)

Bearman, Gregory H. (Inventor); Chrien, Thomas D. (Inventor); Eastwood, Michael L. (Inventor)

2000-01-01

A real-time display of tissue ischemia which comprises three CCD video cameras, each with a narrow bandwidth filter at the correct wavelength is discussed. The cameras simultaneously view an area of tissue suspected of having ischemic areas through beamsplitters. The output from each camera is adjusted to give the correct signal intensity for combining with, the others into an image for display. If necessary a digital signal processor (DSP) can implement algorithms for image enhancement prior to display. Current DSP engines are fast enough to give real-time display. Measurement at three, wavelengths, combined into a real-time Red-Green-Blue (RGB) video display with a digital signal processing (DSP) board to implement image algorithms, provides direct visualization of ischemic areas.

Implementation of an RBF neural network on embedded systems: real-time face tracking and identity verification.

PubMed

Yang, Fan; Paindavoine, M

2003-01-01

This paper describes a real time vision system that allows us to localize faces in video sequences and verify their identity. These processes are image processing techniques based on the radial basis function (RBF) neural network approach. The robustness of this system has been evaluated quantitatively on eight video sequences. We have adapted our model for an application of face recognition using the Olivetti Research Laboratory (ORL), Cambridge, UK, database so as to compare the performance against other systems. We also describe three hardware implementations of our model on embedded systems based on the field programmable gate array (FPGA), zero instruction set computer (ZISC) chips, and digital signal processor (DSP) TMS320C62, respectively. We analyze the algorithm complexity and present results of hardware implementations in terms of the resources used and processing speed. The success rates of face tracking and identity verification are 92% (FPGA), 85% (ZISC), and 98.2% (DSP), respectively. For the three embedded systems, the processing speeds for images size of 288 /spl times/ 352 are 14 images/s, 25 images/s, and 4.8 images/s, respectively.

Parallel processor for real-time structural control

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tise, B.L.

1992-01-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection tomore » host computer, parallelizing code generator, and look-up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating-point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An Open Windows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.« less

Digital Audio Signal Processing and Nde: AN Unlikely but Valuable Partnership

NASA Astrophysics Data System (ADS)

Gaydecki, Patrick

2008-02-01

In the Digital Signal Processing (DSP) group, within the School of Electrical and Electronic Engineering at The University of Manchester, research is conducted into two seemingly distinct and disparate subjects: instrumentation for nondestructive evaluation, and DSP systems & algorithms for digital audio. We have often found that many of the hardware systems and algorithms employed to recover, extract or enhance audio signals may also be applied to signals provided by ultrasonic or magnetic NDE instruments. Furthermore, modern DSP hardware is so fast (typically performing hundreds of millions of operations per second), that much of the processing and signal reconstruction may be performed in real time. Here, we describe some of the hardware systems we have developed, together with algorithms that can be implemented both in real time and offline. A next generation system has now been designed, which incorporates a processor operating at 0.55 Giga MMACS, six input and eight output analogue channels, digital input/output in the form of S/PDIF, a JTAG and a USB interface. The software allows the user, with no knowledge of filter theory or programming, to design and run standard or arbitrary FIR, IIR and adaptive filters. Using audio as a vehicle, we can demonstrate the remarkable properties of modern reconstruction algorithms when used in conjunction with such hardware; applications in NDE include signal enhancement and recovery in acoustic, ultrasonic, magnetic and eddy current modalities.

Real-Time Data Processing in the muon system of the D0 detector.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Neeti Parashar et al.

2001-07-03

This paper presents a real-time application of the 16-bit fixed point Digital Signal Processors (DSPs), in the Muon System of the D0 detector located at the Fermilab Tevatron, presently the world's highest-energy hadron collider. As part of the Upgrade for a run beginning in the year 2000, the system is required to process data at an input event rate of 10 KHz without incurring significant deadtime in readout. The ADSP21csp01 processor has high I/O bandwidth, single cycle instruction execution and fast task switching support to provide efficient multisignal processing. The processor's internal memory consists of 4K words of Program Memorymore » and 4K words of Data Memory. In addition there is an external memory of 32K words for general event buffering and 16K words of Dual port Memory for input data queuing. This DSP fulfills the requirement of the Muon subdetector systems for data readout. All error handling, buffering, formatting and transferring of the data to the various trigger levels of the data acquisition system is done in software. The algorithms developed for the system complete these tasks in about 20 {micro}s per event.« less

A portable detection instrument based on DSP for beef marbling

NASA Astrophysics Data System (ADS)

Zhou, Tong; Peng, Yankun

2014-05-01

Beef marbling is one of the most important indices to assess beef quality. Beef marbling is graded by the measurement of the fat distribution density in the rib-eye region. However quality grades of beef in most of the beef slaughtering houses and businesses depend on trainees using their visual senses or comparing the beef slice to the Chinese standard sample cards. Manual grading demands not only great labor but it also lacks objectivity and accuracy. Aiming at the necessity of beef slaughtering houses and businesses, a beef marbling detection instrument was designed. The instrument employs Charge-coupled Device (CCD) imaging techniques, digital image processing, Digital Signal Processor (DSP) control and processing techniques and Liquid Crystal Display (LCD) screen display techniques. The TMS320DM642 digital signal processor of Texas Instruments (TI) is the core that combines high-speed data processing capabilities and real-time processing features. All processes such as image acquisition, data transmission, image processing algorithms and display were implemented on this instrument for a quick, efficient, and non-invasive detection of beef marbling. Structure of the system, working principle, hardware and software are introduced in detail. The device is compact and easy to transport. The instrument can determine the grade of beef marbling reliably and correctly.

a Continuous Health Monitoring Guided Wave Fmd System for Retrofit to Existing Offshore Oilrigs

NASA Astrophysics Data System (ADS)

Mijarez, R.; Solis, L.; Martinez, F.

2010-02-01

An automatic health monitoring guided wave flood member detection (FMD) system, for retrofit to existing offshore oilrigs is presented. The system employs a microcontroller piezoelectric (PZT) based transmitter and a receiver instrumentation package composed of a PZT 40 kHz ultrasound transducer and a digital signal processor (DSP) module connected to a PC via USB for monitoring purposes. The transmitter and receiver were attached, non-intrusively, to the external wall of a steel tube; 1 m×27 cm×2 mm. Experiments performed in the laboratory have successfully identified automatically flooded tubes.

Research on grid connection control technology of double fed wind generator

NASA Astrophysics Data System (ADS)

Ling, Li

2017-01-01

The composition and working principle of variable speed constant frequency doubly fed wind power generation system is discussed in this thesis. On the basis of theoretical analysis and control on the modeling, the doubly fed wind power generation simulation control system is designed based on a TMS320F2407 digital signal processor (DSP), and has done a large amount of experimental research, which mainly include, variable speed constant frequency, constant pressure, Grid connected control experiment. The running results show that the design of simulation control system is reasonable and can meet the need of experimental research.

FPGA-Based Reconfigurable Processor for Ultrafast Interlaced Ultrasound and Photoacoustic Imaging

PubMed Central

Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

2016-01-01

In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models. PMID:22828830

FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

PubMed

Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

2012-07-01

In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

Scalable Multiprocessor for High-Speed Computing in Space

NASA Technical Reports Server (NTRS)

Lux, James; Lang, Minh; Nishimoto, Kouji; Clark, Douglas; Stosic, Dorothy; Bachmann, Alex; Wilkinson, William; Steffke, Richard

2004-01-01

A report discusses the continuing development of a scalable multiprocessor computing system for hard real-time applications aboard a spacecraft. "Hard realtime applications" signifies applications, like real-time radar signal processing, in which the data to be processed are generated at "hundreds" of pulses per second, each pulse "requiring" millions of arithmetic operations. In these applications, the digital processors must be tightly integrated with analog instrumentation (e.g., radar equipment), and data input/output must be synchronized with analog instrumentation, controlled to within fractions of a microsecond. The scalable multiprocessor is a cluster of identical commercial-off-the-shelf generic DSP (digital-signal-processing) computers plus generic interface circuits, including analog-to-digital converters, all controlled by software. The processors are computers interconnected by high-speed serial links. Performance can be increased by adding hardware modules and correspondingly modifying the software. Work is distributed among the processors in a parallel or pipeline fashion by means of a flexible master/slave control and timing scheme. Each processor operates under its own local clock; synchronization is achieved by broadcasting master time signals to all the processors, which compute offsets between the master clock and their local clocks.

Compact lidar system using laser diode, binary continuous wave power modulation, and an avalanche photodiode-based receiver controlled by a digital signal processor

NASA Astrophysics Data System (ADS)

Ardanuy, Antoni; Comerón, Adolfo

2018-04-01

We analyze the practical limits of a lidar system based on the use of a laser diode, random binary continuous wave power modulation, and an avalanche photodiode (APD)-based photereceiver, combined with the control and computing power of the digital signal processors (DSP) currently available. The target is to design a compact portable lidar system made all in semiconductor technology, with a low-power demand and an easy configuration of the system, allowing change in some of its features through software. Unlike many prior works, we emphasize the use of APDs instead of photomultiplier tubes to detect the return signal and the application of the system to measure not only hard targets, but also medium-range aerosols and clouds. We have developed an experimental prototype to evaluate the behavior of the system under different environmental conditions. Experimental results provided by the prototype are presented and discussed.

Servo Platform Circuit Design of Pendulous Gyroscope Based on DSP

NASA Astrophysics Data System (ADS)

Tan, Lilong; Wang, Pengcheng; Zhong, Qiyuan; Zhang, Cui; Liu, Yunfei

2018-03-01

In order to solve the problem when a certain type of pendulous gyroscope in the initial installation deviation more than 40 degrees, that the servo platform can not be up to the speed of the gyroscope in the rough north seeking phase. This paper takes the digital signal processor TMS320F28027 as the core, uses incremental digital PID algorithm, carries out the circuit design of the servo platform. Firstly, the hardware circuit is divided into three parts: DSP minimum system, motor driving circuit and signal processing circuit, then the mathematical model of incremental digital PID algorithm is established, based on the model, writes the PID control program in CCS3.3, finally, the servo motor tracking control experiment is carried out, it shows that the design can significantly improve the tracking ability of the servo platform, and the design has good engineering practice.

Development, implementation, and characterization of a standalone embedded viscosity measurement system based on the impedance spectroscopy of a vibrating wire sensor

NASA Astrophysics Data System (ADS)

Santos, José; Janeiro, Fernando M.; Ramos, Pedro M.

2015-10-01

This paper presents an embedded liquid viscosity measurement system based on a vibrating wire sensor. Although multiple viscometers based on different working principles are commercially available, there is still a market demand for a dedicated measurement system capable of performing accurate, fast measurements and requiring little or no operator training for simple systems and solution monitoring. The developed embedded system is based on a vibrating wire sensor that works by measuring the impedance response of the sensor, which depends on the viscosity and density of the liquid in which the sensor is immersed. The core of the embedded system is a digital signal processor (DSP) which controls the waveform generation and acquisitions for the measurement of the impedance frequency response. The DSP also processes the acquired waveforms and estimates the liquid viscosity. The user can interact with the measurement system through a keypad and an LCD or through a computer with a USB connection for data logging and processing. The presented system is tested on a set of viscosity standards and the estimated values are compared with the standard manufacturer specified viscosity values. A stability study of the measurement system is also performed.

Implementation of a High-Speed FPGA and DSP Based FFT Processor for Improving Strain Demodulation Performance in a Fiber-Optic-Based Sensing System

NASA Technical Reports Server (NTRS)

Farley, Douglas L.

2005-01-01

NASA's Aviation Safety and Security Program is pursuing research in on-board Structural Health Management (SHM) technologies for purposes of reducing or eliminating aircraft accidents due to system and component failures. Under this program, NASA Langley Research Center (LaRC) is developing a strain-based structural health-monitoring concept that incorporates a fiber optic-based measuring system for acquiring strain values. This fiber optic-based measuring system provides for the distribution of thousands of strain sensors embedded in a network of fiber optic cables. The resolution of strain value at each discrete sensor point requires a computationally demanding data reduction software process that, when hosted on a conventional processor, is not suitable for near real-time measurement. This report describes the development and integration of an alternative computing environment using dedicated computing hardware for performing the data reduction. Performance comparison between the existing and the hardware-based system is presented.

Noise generator for tinnitus treatment based on look-up tables

NASA Astrophysics Data System (ADS)

Uriz, Alejandro J.; Agüero, Pablo; Tulli, Juan C.; Castiñeira Moreira, Jorge; González, Esteban; Hidalgo, Roberto; Casadei, Manuel

2016-04-01

Treatment of tinnitus by means of masking sounds allows to obtain a significant improve of the quality of life of the individual that suffer that condition. In view of that, it is possible to develop noise synthesizers based on random number generators in digital signal processors (DSP), which are used in almost any digital hearing aid devices. DSP architecture have limitations to implement a pseudo random number generator, due to it, the noise statistics can be not as good as expectations. In this paper, a technique to generate additive white gaussian noise (AWGN) or other types of filtered noise using coefficients stored in program memory of the DSP is proposed. Also, an implementation of the technique is carried out on a dsPIC from Microchip®. Objective experiments and experimental measurements are performed to analyze the proposed technique.

A VHDL Core for Intrinsic Evolution of Discrete Time Filters with Signal Feedback

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; Dutton, Kenneth

2005-01-01

The design of an Evolvable Machine VHDL Core is presented, representing a discrete-time processing structure capable of supporting control system applications. This VHDL Core is implemented in an FPGA and is interfaced with an evolutionary algorithm implemented in firmware on a Digital Signal Processor (DSP) to create an evolvable system platform. The salient features of this architecture are presented. The capability to implement IIR filter structures is presented along with the results of the intrinsic evolution of a filter. The robustness of the evolved filter design is tested and its unique characteristics are described.

Research of real-time video processing system based on 6678 multi-core DSP

NASA Astrophysics Data System (ADS)

Li, Xiangzhen; Xie, Xiaodan; Yin, Xiaoqiang

2017-10-01

In the information age, the rapid development in the direction of intelligent video processing, complex algorithm proposed the powerful challenge on the performance of the processor. In this article, through the FPGA + TMS320C6678 frame structure, the image to fog, merge into an organic whole, to stabilize the image enhancement, its good real-time, superior performance, break through the traditional function of video processing system is simple, the product defects such as single, solved the video application in security monitoring, video, etc. Can give full play to the video monitoring effectiveness, improve enterprise economic benefits.

The impact of Moore's Law and loss of Dennard scaling: Are DSP SoCs an energy efficient alternative to x86 SoCs?

NASA Astrophysics Data System (ADS)

Johnsson, L.; Netzer, G.

2016-10-01

Moore's law, the doubling of transistors per unit area for each CMOS technology generation, is expected to continue throughout the decade, while Dennard voltage scaling resulting in constant power per unit area stopped about a decade ago. The semiconductor industry's response to the loss of Dennard scaling and the consequent challenges in managing power distribution and dissipation has been leveled off clock rates, a die performance gain reduced from about a factor of 2.8 to 1.4 per technology generation, and multi-core processor dies with increased cache sizes. Increased caches sizes offers performance benefits for many applications as well as energy savings. Accessing data in cache is considerably more energy efficient than main memory accesses. Further, caches consume less power than a corresponding amount of functional logic. As feature sizes continue to be scaled down an increasing fraction of the die must be “underutilized” or “dark” due to power constraints. With power being a prime design constraint there is a concerted effort to find significantly more energy efficient chip architectures than dominant in servers today, with chips potentially incorporating several types of cores to cover a range of applications, or different functions in an application, as is already common for the mobile processor market. Digital Signal Processors (DSPs), largely targeting the embedded and mobile processor markets, typically have been designed for a power consumption of 10% or less of a typical x86 CPU, yet with much more than 10% of the floating-point capability of the same technology generation x86 CPUs. Thus, DSPs could potentially offer an energy efficient alternative to x86 CPUs. Here we report an assessment of the Texas Instruments TMS320C6678 DSP in regards to its energy efficiency for two common HPC benchmarks: STREAM (memory system benchmark) and HPL (CPU benchmark)

QI2S - Quick Image Interpretation System

NASA Astrophysics Data System (ADS)

Naghmouchi, Jamin; Aviely, Peleg; Ginosar, Ran; Ober, Giovanna; Bischoff, Ole; Nadler, Ron; Guiser, David; Citroen, Meira; Freddi, Riccardo; Berekovic, Mladen

2015-09-01

The evolution of the Earth Observation mission will be driven by many factors, and the deveploment of new processing paradigms to facilitate data downlink, handling and storage will be a key factor. Next generation EO satellites will generate a great amount of data at a very high data rate, both radar and optical. Real-time onboard processing can be the solution to reduce data downlink and management on ground. Radiometric, geometric, and atmospheric corrections of EO data as well as material/object detection in addition to the well-known needs for image compression and signal processing can be performed directly on board and the aim of QI2S project is to demonstrate this. QI2S, a concept prototype system for novel onboard image processing and image interpretation which has been designed, developed and validated in the framework of an EU FP7 project, targets these needs and makes a significant step towards exceeding current roadmaps of leading space agencies for future payload processors. The QI2S system features multiple chip components of the RC64, a novel rad-hard 64-core signal processing chip, which targets DSP performance of 75 GMACs (16bit), 150 GOPS and 38 single precision GFLOPS while dissipating less than 10 Watts. It integrates advanced DSP cores with a multibank shared memory and a hardware scheduler, also supporting DDR2/3 memory and twelve 3.125 Gbps full duplex high-speed serial links using SpaceFibre and other protocols. The processor is being developed within the European FP7 Framework Program and will be qualified to the highest space standards.

Design and implementation of a hybrid sub-band acoustic echo canceller (AEC)

NASA Astrophysics Data System (ADS)

Bai, Mingsian R.; Yang, Cheng-Ken; Hur, Ker-Nan

2009-04-01

An efficient method is presented for implementing an acoustic echo canceller (AEC) that makes use of hybrid sub-band approach. The hybrid system is comprised of a fixed processor and an adaptive filter in each sub-band. The AEC aims at reducing the echo resulting from the acoustic feedback in loudspeaker-enclosure-microphone (LEM) systems such as teleconferencing and hands-free systems. In order to cancel the acoustical echo efficiently, various processing architectures including fixed filters, hybrid processors, and sub-band structure are investigated. A double-talk detector is incorporated into the proposed AEC to prevent the adaptive filter from diverging in double-talk situations. A de-correlation filter is also used alongside sub-band processing in order to enhance the performance and efficiency of AEC. All algorithms are implemented and verified on the platform of a fixed-point digital signal processor (DSP). The AECs are evaluated in terms of cancellation performance and computation complexity. In addition, listening tests are conducted to assess the subjective performance of the AECs. From the results, the proposed hybrid sub-band AEC was found to be the most effective among all methods in terms of echo reduction and timbral quality.

Implementation of MPEG-2 encoder to multiprocessor system using multiple MVPs (TMS320C80)

NASA Astrophysics Data System (ADS)

Kim, HyungSun; Boo, Kenny; Chung, SeokWoo; Choi, Geon Y.; Lee, YongJin; Jeon, JaeHo; Park, Hyun Wook

1997-05-01

This paper presents the efficient algorithm mapping for the real-time MPEG-2 encoding on the KAIST image computing system (KICS), which has a parallel architecture using five multimedia video processors (MVPs). The MVP is a general purpose digital signal processor (DSP) of Texas Instrument. It combines one floating-point processor and four fixed- point DSPs on a single chip. The KICS uses the MVP as a primary processing element (PE). Two PEs form a cluster, and there are two processing clusters in the KICS. Real-time MPEG-2 encoder is implemented through the spatial and the functional partitioning strategies. Encoding process of spatially partitioned half of the video input frame is assigned to ne processing cluster. Two PEs perform the functionally partitioned MPEG-2 encoding tasks in the pipelined operation mode. One PE of a cluster carries out the transform coding part and the other performs the predictive coding part of the MPEG-2 encoding algorithm. One MVP among five MVPs is used for system control and interface with host computer. This paper introduces an implementation of the MPEG-2 algorithm with a parallel processing architecture.

Fault-Tolerant, Radiation-Hard DSP

NASA Technical Reports Server (NTRS)

Czajkowski, David

2011-01-01

Commercial digital signal processors (DSPs) for use in high-speed satellite computers are challenged by the damaging effects of space radiation, mainly single event upsets (SEUs) and single event functional interrupts (SEFIs). Innovations have been developed for mitigating the effects of SEUs and SEFIs, enabling the use of very-highspeed commercial DSPs with improved SEU tolerances. Time-triple modular redundancy (TTMR) is a method of applying traditional triple modular redundancy on a single processor, exploiting the VLIW (very long instruction word) class of parallel processors. TTMR improves SEU rates substantially. SEFIs are solved by a SEFI-hardened core circuit, external to the microprocessor. It monitors the health of the processor, and if a SEFI occurs, forces the processor to return to performance through a series of escalating events. TTMR and hardened-core solutions were developed for both DSPs and reconfigurable field-programmable gate arrays (FPGAs). This includes advancement of TTMR algorithms for DSPs and reconfigurable FPGAs, plus a rad-hard, hardened-core integrated circuit that services both the DSP and FPGA. Additionally, a combined DSP and FPGA board architecture was fully developed into a rad-hard engineering product. This technology enables use of commercial off-the-shelf (COTS) DSPs in computers for satellite and other space applications, allowing rapid deployment at a much lower cost. Traditional rad-hard space computers are very expensive and typically have long lead times. These computers are either based on traditional rad-hard processors, which have extremely low computational performance, or triple modular redundant (TMR) FPGA arrays, which suffer from power and complexity issues. Even more frustrating is that the TMR arrays of FPGAs require a fixed, external rad-hard voting element, thereby causing them to lose much of their reconfiguration capability and in some cases significant speed reduction. The benefits of COTS high-performance signal processing include significant increase in onboard science data processing, enabling orders of magnitude reduction in required communication bandwidth for science data return, orders of magnitude improvement in onboard mission planning and critical decision making, and the ability to rapidly respond to changing mission environments, thus enabling opportunistic science and orders of magnitude reduction in the cost of mission operations through reduction of required staff. Additional benefits of COTS-based, high-performance signal processing include the ability to leverage considerable commercial and academic investments in advanced computing tools, techniques, and infra structure, and the familiarity of the science and IT community with these computing environments.

Advanced one-dimensional optical strain measurement system, phase 4

NASA Technical Reports Server (NTRS)

Lant, Christian T.

1992-01-01

An improved version of the speckle-shift strain measurement system was developed. The system uses a two-dimensional sensor array to maintain speckle correlation in the presence of large off-axis rigid body motions. A digital signal processor (DSP) is used to calculate strains at a rate near the RS-170 camera frame rate. Strain measurements were demonstrated on small diameter wires and fibers used in composite materials research. Accurate values of Young's modulus were measured on tungsten wires, and silicon carbide and sapphire fibers. This optical technique has measured surface strains at specimen temperatures above 750 C and has shown the potential for measurements at much higher temperatures.

Automatic efficiency optimization of an axial compressor with adjustable inlet guide vanes

NASA Astrophysics Data System (ADS)

Li, Jichao; Lin, Feng; Nie, Chaoqun; Chen, Jingyi

2012-04-01

The inlet attack angle of rotor blade reasonably can be adjusted with the change of the stagger angle of inlet guide vane (IGV); so the efficiency of each condition will be affected. For the purpose to improve the efficiency, the DSP (Digital Signal Processor) controller is designed to adjust the stagger angle of IGV automatically in order to optimize the efficiency at any operating condition. The A/D signal collection includes inlet static pressure, outlet static pressure, outlet total pressure, rotor speed and torque signal, the efficiency can be calculated in the DSP, and the angle signal for the stepping motor which control the IGV will be sent out from the D/A. Experimental investigations are performed in a three-stage, low-speed axial compressor with variable inlet guide vanes. It is demonstrated that the DSP designed can well adjust the stagger angle of IGV online, the efficiency under different conditions can be optimized. This establishment of DSP online adjustment scheme may provide a practical solution for improving performance of multi-stage axial flow compressor when its operating condition is varied.

A Wireless Electronic Nose System Using a Fe2O3 Gas Sensing Array and Least Squares Support Vector Regression

PubMed Central

Song, Kai; Wang, Qi; Liu, Qi; Zhang, Hongquan; Cheng, Yingguo

2011-01-01

This paper describes the design and implementation of a wireless electronic nose (WEN) system which can online detect the combustible gases methane and hydrogen (CH4/H2) and estimate their concentrations, either singly or in mixtures. The system is composed of two wireless sensor nodes—a slave node and a master node. The former comprises a Fe2O3 gas sensing array for the combustible gas detection, a digital signal processor (DSP) system for real-time sampling and processing the sensor array data and a wireless transceiver unit (WTU) by which the detection results can be transmitted to the master node connected with a computer. A type of Fe2O3 gas sensor insensitive to humidity is developed for resistance to environmental influences. A threshold-based least square support vector regression (LS-SVR)estimator is implemented on a DSP for classification and concentration measurements. Experimental results confirm that LS-SVR produces higher accuracy compared with artificial neural networks (ANNs) and a faster convergence rate than the standard support vector regression (SVR). The designed WEN system effectively achieves gas mixture analysis in a real-time process. PMID:22346587

Ship detection in panchromatic images: a new method and its DSP implementation

NASA Astrophysics Data System (ADS)

Yao, Yuan; Jiang, Zhiguo; Zhang, Haopeng; Wang, Mengfei; Meng, Gang

2016-03-01

In this paper, a new ship detection method is proposed after analyzing the characteristics of panchromatic remote sensing images and ship targets. Firstly, AdaBoost(Adaptive Boosting) classifiers trained by Haar features are utilized to make coarse detection of ship targets. Then LSD (Line Segment Detector) is adopted to extract the line features in target slices to make fine detection. Experimental results on a dataset of panchromatic remote sensing images with a spatial resolution of 2m show that the proposed algorithm can achieve high detection rate and low false alarm rate. Meanwhile, the algorithm can meet the needs of practical applications on DSP (Digital Signal Processor).

On-board multicarrier demodulator for mobile applications using DSP implementation

NASA Astrophysics Data System (ADS)

Yim, W. H.; Kwan, C. C. D.; Coakley, F. P.; Evans, B. G.

1990-11-01

This paper describes the design and implementation of an on-board multicarrier demodulator using commercial digital signal processors. This is for use in a mobile satellite communication system employing an up-link SCPC/FDMA scheme. Channels are separated by a flexible multistage digital filter bank followed by a channel multiplexed digital demodulator array. The cross/dot product design approach of error detector leads to a new QPSK frequency control algorithm that allows fast acquisition without special preamble pattern. Timing correction is performed digitally using an extended stack of polyphase sub-filters.

Spacecube: A Family of Reconfigurable Hybrid On-Board Science Data Processors

NASA Technical Reports Server (NTRS)

Flatley, Thomas P.

2015-01-01

SpaceCube is a family of Field Programmable Gate Array (FPGA) based on-board science data processing systems developed at the NASA Goddard Space Flight Center (GSFC). The goal of the SpaceCube program is to provide 10x to 100x improvements in on-board computing power while lowering relative power consumption and cost. SpaceCube is based on the Xilinx Virtex family of FPGAs, which include processor, FPGA logic and digital signal processing (DSP) resources. These processing elements are leveraged to produce a hybrid science data processing platform that accelerates the execution of algorithms by distributing computational functions to the most suitable elements. This approach enables the implementation of complex on-board functions that were previously limited to ground based systems, such as on-board product generation, data reduction, calibration, classification, eventfeature detection, data mining and real-time autonomous operations. The system is fully reconfigurable in flight, including data parameters, software and FPGA logic, through either ground commanding or autonomously in response to detected eventsfeatures in the instrument data stream.

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Montenegro, Justino (Technical Monitor)

2002-01-01

Much has been made of the capabilities of Field Programmable Gate Arrays (FPGA's) in the hardware implementation of fast digital signal processing functions. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used Proportional-Integral-Derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a Digital Signal Processor (DSP) device or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using DSP devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, Pulse Width Modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacemap. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive-control algorithm approaches. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Interband cascade laser-based ppbv-level mid-infrared methane detection using two digital lock-in amplifier schemes

NASA Astrophysics Data System (ADS)

Song, Fang; Zheng, Chuantao; Yu, Di; Zhou, Yanwen; Yan, Wanhong; Ye, Weilin; Zhang, Yu; Wang, Yiding; Tittel, Frank K.

2018-03-01

A parts-per-billion in volume (ppbv) level mid-infrared methane (CH4) sensor system was demonstrated using second-harmonic wavelength modulation spectroscopy (2 f-WMS). A 3291 nm interband cascade laser (ICL) and a multi-pass gas cell (MPGC) with a 16 m optical path length were adopted in the reported sensor system. Two digital lock-in amplifier (DLIA) schemes, a digital signal processor (DSP)-based DLIA and a LabVIEW-based DLIA, were used for harmonic signal extraction. A limit of detection (LoD) of 13.07 ppbv with an averaging time of 2 s was achieved using the DSP-based DLIA and a LoD of 5.84 ppbv was obtained using the LabVIEW-based DLIA with the same averaging time. A rise time of 0→2 parts-per-million in volume (ppmv) and fall time of 2→0 ppmv were observed. Outdoor atmospheric CH4 concentration measurements were carried out to evaluate the sensor performance using the two DLIA schemes.

27 CFR 19.55 - Other businesses.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 27 Alcohol, Tobacco Products and Firearms 1 2011-04-01 2011-04-01 false Other businesses. 19.55... Plants Rules for Location and Use of A Dsp § 19.55 Other businesses. (a) The appropriate TTB officer may authorize the conduct of a business other than that of a distiller, warehouseman, or processor on the...

27 CFR 19.55 - Other businesses.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 27 Alcohol, Tobacco Products and Firearms 1 2012-04-01 2012-04-01 false Other businesses. 19.55... Plants Rules for Location and Use of A Dsp § 19.55 Other businesses. (a) The appropriate TTB officer may authorize the conduct of a business other than that of a distiller, warehouseman, or processor on the...

27 CFR 19.55 - Other businesses.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 27 Alcohol, Tobacco Products and Firearms 1 2014-04-01 2014-04-01 false Other businesses. 19.55... Plants Rules for Location and Use of A Dsp § 19.55 Other businesses. (a) The appropriate TTB officer may authorize the conduct of a business other than that of a distiller, warehouseman, or processor on the...

27 CFR 19.55 - Other businesses.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 27 Alcohol, Tobacco Products and Firearms 1 2013-04-01 2013-04-01 false Other businesses. 19.55... Plants Rules for Location and Use of A Dsp § 19.55 Other businesses. (a) The appropriate TTB officer may authorize the conduct of a business other than that of a distiller, warehouseman, or processor on the...

Signal Processing and Calibration of Continuous-Wave Focused CO2 Doppler Lidars for Atmospheric Backscatter Measurement

NASA Technical Reports Server (NTRS)

Rothermel, Jeffry; Chambers, Diana M.; Jarzembski, Maurice A.; Srivastava, Vandana; Bowdle, David A.; Jones, William D.

1996-01-01

Two continuous-wave(CW)focused C02 Doppler lidars (9.1 and 10.6 micrometers) were developed for airborne in situ aerosol backscatter measurements. The complex path of reliably calibrating these systems, with different signal processors, for accurate derivation of atmospheric backscatter coefficients is documented. Lidar calibration for absolute backscatter measurement for both lidars is based on range response over the lidar sample volume, not solely at focus. Both lidars were calibrated with a new technique using well-characterized aerosols as radiometric standard targets and related to conventional hard-target calibration. A digital signal processor (DSP), a surface acoustic and spectrum analyzer and manually tuned spectrum analyzer signal analyzers were used. The DSP signals were analyzed with an innovative method of correcting for systematic noise fluctuation; the noise statistics exhibit the chi-square distribution predicted by theory. System parametric studies and detailed calibration improved the accuracy of conversion from the measured signal-to-noise ratio to absolute backscatter. The minimum backscatter sensitivity is approximately 3 x 10(exp -12)/m/sr at 9.1 micrometers and approximately 9 x 10(exp -12)/m/sr at 10.6 micrometers. Sample measurements are shown for a flight over the remote Pacific Ocean in 1990 as part of the NASA Global Backscatter Experiment (GLOBE) survey missions, the first time to our knowledge that 9.1-10.6 micrometer lidar intercomparisons were made. Measurements at 9.1 micrometers, a potential wavelength for space-based lidar remote-sensing applications, are to our knowledge the first based on the rare isotope C-12 O(2)-18 gas.

A Next Generation Digital Counting System For Low-Level Tritium Studies (Project Report)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bowman, P.

2016-10-03

Since the early seventies, SRNL has pioneered low-level tritium analysis using various nuclear counting technologies and techniques. Since 1999, SRNL has successfully performed routine low-level tritium analyses with counting systems based on digital signal processor (DSP) modules developed in the late 1990s. Each of these counting systems are complex, unique to SRNL, and fully dedicated to performing routine tritium analyses of low-level environmental samples. It is time to modernize these systems due to a variety of issues including (1) age, (2) lack of direct replacement electronics modules and (3) advances in digital signal processing and computer technology. There has beenmore » considerable development in many areas associated with the enterprise of performing low-level tritium analyses. The objective of this LDRD project was to design, build, and demonstrate a Next Generation Tritium Counting System (NGTCS), while not disrupting the routine low-level tritium analyses underway in the facility on the legacy counting systems. The work involved (1) developing a test bed for building and testing new counting system hardware that does not interfere with our routine analyses, (2) testing a new counting system based on a modern state of the art DSP module, and (3) evolving the low-level tritium counter design to reflect the state of the science.« less

Adaptive Signal Processing Testbed: VME-based DSP board market survey

NASA Astrophysics Data System (ADS)

Ingram, Rick E.

1992-04-01

The Adaptive Signal Processing Testbed (ASPT) is a real-time multiprocessor system utilizing digital signal processor technology on VMEbus based printed circuit boards installed on a Sun workstation. The ASPT has specific requirements, particularly as regards to the signal excision application, with respect to interfacing with current and planned data generation equipment, processing of the data, storage to disk of final and intermediate results, and the development tools for applications development and integration into the overall EW/COM computing environment. A prototype ASPT was implemented using three VME-C-30 boards from Applied Silicon. Experience gained during the prototype development led to the conclusions that interprocessor communications capability is the most significant contributor to overall ASPT performance. In addition, the host involvement should be minimized. Boards using different processors were evaluated with respect to the ASPT system requirements, pricing, and availability. Specific recommendations based on various priorities are made as well as recommendations concerning the integration and interaction of various tools developed during the prototype implementation.

New design environment for defect detection in web inspection systems

NASA Astrophysics Data System (ADS)

Hajimowlana, S. Hossain; Muscedere, Roberto; Jullien, Graham A.; Roberts, James W.

1997-09-01

One of the aims of industrial machine vision is to develop computer and electronic systems destined to replace human vision in the process of quality control of industrial production. In this paper we discuss the development of a new design environment developed for real-time defect detection using reconfigurable FPGA and DSP processor mounted inside a DALSA programmable CCD camera. The FPGA is directly connected to the video data-stream and outputs data to a low bandwidth output bus. The system is targeted for web inspection but has the potential for broader application areas. We describe and show test results of the prototype system board, mounted inside a DALSA camera and discuss some of the algorithms currently simulated and implemented for web inspection applications.

SpaceCube Version 1.5

NASA Technical Reports Server (NTRS)

Geist, Alessandro; Lin, Michael; Flatley, Tom; Petrick, David

2013-01-01

SpaceCube 1.5 is a high-performance and low-power system in a compact form factor. It is a hybrid processing system consisting of CPU (central processing unit), FPGA (field-programmable gate array), and DSP (digital signal processor) processing elements. The primary processing engine is the Virtex- 5 FX100T FPGA, which has two embedded processors. The SpaceCube 1.5 System was a bridge to the SpaceCube 2.0 and SpaceCube 2.0 Mini processing systems. The SpaceCube 1.5 system was the primary avionics in the successful SMART (Small Rocket/Spacecraft Technology) Sounding Rocket mission that was launched in the summer of 2011. For SMART and similar missions, an avionics processor is required that is reconfigurable, has high processing capability, has multi-gigabit interfaces, is low power, and comes in a rugged/compact form factor. The original SpaceCube 1.0 met a number of the criteria, but did not possess the multi-gigabit interfaces that were required and is a higher-cost system. The SpaceCube 1.5 was designed with those mission requirements in mind. The SpaceCube 1.5 features one Xilinx Virtex-5 FX100T FPGA and has excellent size, weight, and power characteristics [4×4×3 in. (approx. = 10×10×8 cm), 3 lb (approx. = 1.4 kg), and 5 to 15 W depending on the application]. The estimated computing power of the two PowerPC 440s in the Virtex-5 FPGA is 1100 DMIPS each. The SpaceCube 1.5 includes two Gigabit Ethernet (1 Gbps) interfaces as well as two SATA-I/II interfaces (1.5 to 3.0 Gbps) for recording to data drives. The SpaceCube 1.5 also features DDR2 SDRAM (double data rate synchronous dynamic random access memory); 4- Gbit Flash for storing application code for the CPU, FPGA, and DSP processing elements; and a Xilinx Platform Flash XL to store FPGA configuration files or application code. The system also incorporates a 12 bit analog to digital converter with the ability to read 32 discrete analog sensor inputs. The SpaceCube 1.5 design also has a built-in accelerometer. In addition, the system has 12 receive and transmit RS- 422 interfaces for legacy support. The SpaceCube 1.5 processor card represents the first NASA Goddard design in a compact form factor featuring the Xilinx Virtex- 5. The SpaceCube 1.5 incorporates backward compatibility with the Space- Cube 1.0 form factor and stackable architecture. It also makes use of low-cost commercial parts, but is designed for operation in harsh environments.

Video sensor architecture for surveillance applications.

PubMed

Sánchez, Jordi; Benet, Ginés; Simó, José E

2012-01-01

This paper introduces a flexible hardware and software architecture for a smart video sensor. This sensor has been applied in a video surveillance application where some of these video sensors are deployed, constituting the sensory nodes of a distributed surveillance system. In this system, a video sensor node processes images locally in order to extract objects of interest, and classify them. The sensor node reports the processing results to other nodes in the cloud (a user or higher level software) in the form of an XML description. The hardware architecture of each sensor node has been developed using two DSP processors and an FPGA that controls, in a flexible way, the interconnection among processors and the image data flow. The developed node software is based on pluggable components and runs on a provided execution run-time. Some basic and application-specific software components have been developed, in particular: acquisition, segmentation, labeling, tracking, classification and feature extraction. Preliminary results demonstrate that the system can achieve up to 7.5 frames per second in the worst case, and the true positive rates in the classification of objects are better than 80%.

Video Sensor Architecture for Surveillance Applications

PubMed Central

Sánchez, Jordi; Benet, Ginés; Simó, José E.

2012-01-01

This paper introduces a flexible hardware and software architecture for a smart video sensor. This sensor has been applied in a video surveillance application where some of these video sensors are deployed, constituting the sensory nodes of a distributed surveillance system. In this system, a video sensor node processes images locally in order to extract objects of interest, and classify them. The sensor node reports the processing results to other nodes in the cloud (a user or higher level software) in the form of an XML description. The hardware architecture of each sensor node has been developed using two DSP processors and an FPGA that controls, in a flexible way, the interconnection among processors and the image data flow. The developed node software is based on pluggable components and runs on a provided execution run-time. Some basic and application-specific software components have been developed, in particular: acquisition, segmentation, labeling, tracking, classification and feature extraction. Preliminary results demonstrate that the system can achieve up to 7.5 frames per second in the worst case, and the true positive rates in the classification of objects are better than 80%. PMID:22438723

Speech coding at 4800 bps for mobile satellite communications

NASA Technical Reports Server (NTRS)

Gersho, Allen; Chan, Wai-Yip; Davidson, Grant; Chen, Juin-Hwey; Yong, Mei

1988-01-01

A speech compression project has recently been completed to develop a speech coding algorithm suitable for operation in a mobile satellite environment aimed at providing telephone quality natural speech at 4.8 kbps. The work has resulted in two alternative techniques which achieve reasonably good communications quality at 4.8 kbps while tolerating vehicle noise and rather severe channel impairments. The algorithms are embodied in a compact self-contained prototype consisting of two AT and T 32-bit floating-point DSP32 digital signal processors (DSP). A Motorola 68HC11 microcomputer chip serves as the board controller and interface handler. On a wirewrapped card, the prototype's circuit footprint amounts to only 200 sq cm, and consumes about 9 watts of power.

Multichannel Phase and Power Detector

NASA Technical Reports Server (NTRS)

Li, Samuel; Lux, James; McMaster, Robert; Boas, Amy

2006-01-01

An electronic signal-processing system determines the phases of input signals arriving in multiple channels, relative to the phase of a reference signal with which the input signals are known to be coherent in both phase and frequency. The system also gives an estimate of the power levels of the input signals. A prototype of the system has four input channels that handle signals at a frequency of 9.5 MHz, but the basic principles of design and operation are extensible to other signal frequencies and greater numbers of channels. The prototype system consists mostly of three parts: An analog-to-digital-converter (ADC) board, which coherently digitizes the input signals in synchronism with the reference signal and performs some simple processing; A digital signal processor (DSP) in the form of a field-programmable gate array (FPGA) board, which performs most of the phase- and power-measurement computations on the digital samples generated by the ADC board; and A carrier board, which allows a personal computer to retrieve the phase and power data. The DSP contains four independent phase-only tracking loops, each of which tracks the phase of one of the preprocessed input signals relative to that of the reference signal (see figure). The phase values computed by these loops are averaged over intervals, the length of which is chosen to obtain output from the DSP at a desired rate. In addition, a simple sum of squares is computed for each channel as an estimate of the power of the signal in that channel. The relative phases and the power level estimates computed by the DSP could be used for diverse purposes in different settings. For example, if the input signals come from different elements of a phased-array antenna, the phases could be used as indications of the direction of arrival of a received signal and/or as feedback for electronic or mechanical beam steering. The power levels could be used as feedback for automatic gain control in preprocessing of incoming signals. For another example, the system could be used to measure the phases and power levels of outputs of multiple power amplifiers to enable adjustment of the amplifiers for optimal power combining.

Implementation theory of distortion-invariant pattern recognition for optical and digital signal processing systems

NASA Astrophysics Data System (ADS)

Lhamon, Michael Earl

A pattern recognition system which uses complex correlation filter banks requires proportionally more computational effort than single-real valued filters. This introduces increased computation burden but also introduces a higher level of parallelism, that common computing platforms fail to identify. As a result, we consider algorithm mapping to both optical and digital processors. For digital implementation, we develop computationally efficient pattern recognition algorithms, referred to as, vector inner product operators that require less computational effort than traditional fast Fourier methods. These algorithms do not need correlation and they map readily onto parallel digital architectures, which imply new architectures for optical processors. These filters exploit circulant-symmetric matrix structures of the training set data representing a variety of distortions. By using the same mathematical basis as with the vector inner product operations, we are able to extend the capabilities of more traditional correlation filtering to what we refer to as "Super Images". These "Super Images" are used to morphologically transform a complicated input scene into a predetermined dot pattern. The orientation of the dot pattern is related to the rotational distortion of the object of interest. The optical implementation of "Super Images" yields feature reduction necessary for using other techniques, such as artificial neural networks. We propose a parallel digital signal processor architecture based on specific pattern recognition algorithms but general enough to be applicable to other similar problems. Such an architecture is classified as a data flow architecture. Instead of mapping an algorithm to an architecture, we propose mapping the DSP architecture to a class of pattern recognition algorithms. Today's optical processing systems have difficulties implementing full complex filter structures. Typically, optical systems (like the 4f correlators) are limited to phase-only implementation with lower detection performance than full complex electronic systems. Our study includes pseudo-random pixel encoding techniques for approximating full complex filtering. Optical filter bank implementation is possible and they have the advantage of time averaging the entire filter bank at real time rates. Time-averaged optical filtering is computational comparable to billions of digital operations-per-second. For this reason, we believe future trends in high speed pattern recognition will involve hybrid architectures of both optical and DSP elements.

High Resolution Imaging Testbed Utilizing Sodium Laser Guide Star Adaptive Optics: The Real Time Wavefront Reconstructor Computer

DTIC Science & Technology

2008-07-31

Unlike the Lyrtech, each DSP on a Bittware board offers 3 MB of on-chip memory and 3 GFLOPs of 32-bit peak processing power. Based on the performance...Each NVIDIA 8800 Ultra features 576 GFLOPS on 128 612-MHz single-precision floating-point SIMD processors, arranged in 16 clusters of eight. Each

Design of Small MEMS Microphone Array Systems for Direction Finding of Outdoors Moving Vehicles

PubMed Central

Zhang, Xin; Huang, Jingchang; Song, Enliang; Liu, Huawei; Li, Baoqing; Yuan, Xiaobing

2014-01-01

In this paper, a MEMS microphone array system scheme is proposed which implements real-time direction of arrival (DOA) estimation for moving vehicles. Wind noise is the primary source of unwanted noise on microphones outdoors. A multiple signal classification (MUSIC) algorithm is used in this paper for direction finding associated with spatial coherence to discriminate between the wind noise and the acoustic signals of a vehicle. The method is implemented in a SHARC DSP processor and the real-time estimated DOA is uploaded through Bluetooth or a UART module. Experimental results in different places show the validity of the system and the deviation is no bigger than 6° in the presence of wind noise. PMID:24603636

Design of small MEMS microphone array systems for direction finding of outdoors moving vehicles.

PubMed

Zhang, Xin; Huang, Jingchang; Song, Enliang; Liu, Huawei; Li, Baoqing; Yuan, Xiaobing

2014-03-05

In this paper, a MEMS microphone array system scheme is proposed which implements real-time direction of arrival (DOA) estimation for moving vehicles. Wind noise is the primary source of unwanted noise on microphones outdoors. A multiple signal classification (MUSIC) algorithm is used in this paper for direction finding associated with spatial coherence to discriminate between the wind noise and the acoustic signals of a vehicle. The method is implemented in a SHARC DSP processor and the real-time estimated DOA is uploaded through Bluetooth or a UART module. Experimental results in different places show the validity of the system and the deviation is no bigger than 6° in the presence of wind noise.

Energy efficient sensor network implementations

DOE Office of Scientific and Technical Information (OSTI.GOV)

Frigo, Janette R; Raby, Eric Y; Brennan, Sean M

In this paper, we discuss a low power embedded sensor node architecture we are developing for distributed sensor network systems deployed in a natural environment. In particular, we examine the sensor node for energy efficient processing-at-the-sensor. We analyze the following modes of operation; event detection, sleep(wake-up), data acquisition, data processing modes using low power, high performance embedded technology such as specialized embedded DSP processors and a low power FPGAs at the sensing node. We use compute intensive sensor node applications: an acoustic vehicle classifier (frequency domain analysis) and a video license plate identification application (learning algorithm) as a case study.more » We report performance and total energy usage for our system implementations and discuss the system architecture design trade offs.« less

Multiple-function multi-input/multi-output digital control and on-line analysis

NASA Technical Reports Server (NTRS)

Hoadley, Sherwood T.; Wieseman, Carol D.; Mcgraw, Sandra M.

1992-01-01

The design and capabilities of two digital controller systems for aeroelastic wind-tunnel models are described. The first allowed control of flutter while performing roll maneuvers with wing load control as well as coordinating the acquisition, storage, and transfer of data for on-line analysis. This system, which employs several digital signal multi-processor (DSP) boards programmed in high-level software languages, is housed in a SUN Workstation environment. A second DCS provides a measure of wind-tunnel safety by functioning as a trip system during testing in the case of high model dynamic response or in case the first DCS fails. The second DCS uses National Instruments LabVIEW Software and Hardware within a Macintosh environment.

High-resolution streaming video integrated with UGS systems

NASA Astrophysics Data System (ADS)

Rohrer, Matthew

2010-04-01

Imagery has proven to be a valuable complement to Unattended Ground Sensor (UGS) systems. It provides ultimate verification of the nature of detected targets. However, due to the power, bandwidth, and technological limitations inherent to UGS, sacrifices have been made to the imagery portion of such systems. The result is that these systems produce lower resolution images in small quantities. Currently, a high resolution, wireless imaging system is being developed to bring megapixel, streaming video to remote locations to operate in concert with UGS. This paper will provide an overview of how using Wifi radios, new image based Digital Signal Processors (DSP) running advanced target detection algorithms, and high resolution cameras gives the user an opportunity to take high-powered video imagers to areas where power conservation is a necessity.

Research on numerical control system based on S3C2410 and MCX314AL

NASA Astrophysics Data System (ADS)

Ren, Qiang; Jiang, Tingbiao

2008-10-01

With the rapid development of micro-computer technology, embedded system, CNC technology and integrated circuits, numerical control system with powerful functions can be realized by several high-speed CPU chips and RISC (Reduced Instruction Set Computing) chips which have small size and strong stability. In addition, the real-time operating system also makes the attainment of embedded system possible. Developing the NC system based on embedded technology can overcome some shortcomings of common PC-based CNC system, such as the waste of resources, low control precision, low frequency and low integration. This paper discusses a hardware platform of ENC (Embedded Numerical Control) system based on embedded processor chip ARM (Advanced RISC Machines)-S3C2410 and DSP (Digital Signal Processor)-MCX314AL and introduces the process of developing ENC system software. Finally write the MCX314AL's driver under the embedded Linux operating system. The embedded Linux operating system can deal with multitask well moreover satisfy the real-time and reliability of movement control. NC system has the advantages of best using resources and compact system with embedded technology. It provides a wealth of functions and superior performance with a lower cost. It can be sure that ENC is the direction of the future development.

Known-plaintext attack on the double phase encoding and its implementation with parallel hardware

NASA Astrophysics Data System (ADS)

Wei, Hengzheng; Peng, Xiang; Liu, Haitao; Feng, Songlin; Gao, Bruce Z.

2008-03-01

A known-plaintext attack on the double phase encryption scheme implemented with parallel hardware is presented. The double random phase encoding (DRPE) is one of the most representative optical cryptosystems developed in mid of 90's and derives quite a few variants since then. Although the DRPE encryption system has a strong power resisting to a brute-force attack, the inherent architecture of DRPE leaves a hidden trouble due to its linearity nature. Recently the real security strength of this opto-cryptosystem has been doubted and analyzed from the cryptanalysis point of view. In this presentation, we demonstrate that the optical cryptosystems based on DRPE architecture are vulnerable to known-plain text attack. With this attack the two encryption keys in the DRPE can be accessed with the help of the phase retrieval technique. In our approach, we adopt hybrid input-output algorithm (HIO) to recover the random phase key in the object domain and then infer the key in frequency domain. Only a plaintext-ciphertext pair is sufficient to create vulnerability. Moreover this attack does not need to select particular plaintext. The phase retrieval technique based on HIO is an iterative process performing Fourier transforms, so it fits very much into the hardware implementation of the digital signal processor (DSP). We make use of the high performance DSP to accomplish the known-plaintext attack. Compared with the software implementation, the speed of the hardware implementation is much fast. The performance of this DSP-based cryptanalysis system is also evaluated.

PPM-based System for Guided Waves Communication Through Corrosion Resistant Multi-wire Cables

NASA Astrophysics Data System (ADS)

Trane, G.; Mijarez, R.; Guevara, R.; Pascacio, D.

Novel wireless communication channels are a necessity in applications surrounded by harsh environments, for instance down-hole oil reservoirs. Traditional radio frequency (RF) communication schemes are not capable of transmitting signals through metal enclosures surrounded by corrosive gases and liquids. As an alternative to RF, a pulse position modulation (PPM) guided waves communication system has been developed and evaluated using a corrosion resistant 4H18 multi-wire cable, commonly used to descend electronic gauges in down-hole oil applications, as the communication medium. The system consists of a transmitter and a receiver that utilizes a PZT crystal, for electrical/mechanical coupling, attached to each extreme of the multi-wire cable. The modulator is based on a microcontroller, which transmits60 kHz guided wave pulses, and the demodulator is based on a commercial digital signal processor (DSP) module that performs real time DSP algorithms. Experimental results are presented, which were obtained using a 1m corrosion resistant 4H18multi-wire cable, commonly used with downhole electronic gauges in the oil sector. Although there was significant dispersion and multiple mode excitations of the transmitted guided wave energy pulses, the results show that data rates on the order of 500 bits per second are readily available employing PPM and simple communications techniques.

Real-time co-registered ultrasound and photoacoustic imaging system based on FPGA and DSP architecture

NASA Astrophysics Data System (ADS)

Alqasemi, Umar; Li, Hai; Aguirre, Andres; Zhu, Quing

2011-03-01

Co-registering ultrasound (US) and photoacoustic (PA) imaging is a logical extension to conventional ultrasound because both modalities provide complementary information of tumor morphology, tumor vasculature and hypoxia for cancer detection and characterization. In addition, both modalities are capable of providing real-time images for clinical applications. In this paper, a Field Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) module-based real-time US/PA imaging system is presented. The system provides real-time US/PA data acquisition and image display for up to 5 fps* using the currently implemented DSP board. It can be upgraded to 15 fps, which is the maximum pulse repetition rate of the used laser, by implementing an advanced DSP module. Additionally, the photoacoustic RF data for each frame is saved for further off-line processing. The system frontend consists of eight 16-channel modules made of commercial and customized circuits. Each 16-channel module consists of two commercial 8-channel receiving circuitry boards and one FPGA board from Analog Devices. Each receiving board contains an IC† that combines. 8-channel low-noise amplifiers, variable-gain amplifiers, anti-aliasing filters, and ADC's‡ in a single chip with sampling frequency of 40MHz. The FPGA board captures the LVDSξ Double Data Rate (DDR) digital output of the receiving board and performs data conditioning and subbeamforming. A customized 16-channel transmission circuitry is connected to the two receiving boards for US pulseecho (PE) mode data acquisition. A DSP module uses External Memory Interface (EMIF) to interface with the eight 16-channel modules through a customized adaptor board. The DSP transfers either sub-beamformed data (US pulse-echo mode or PAI imaging mode) or raw data from FPGA boards to its DDR-2 memory through the EMIF link, then it performs additional processing, after that, it transfer the data to the PC** for further image processing. The PC code performs image processing including demodulation, beam envelope detection and scan conversion. Additionally, the PC code pre-calculates the delay coefficients used for transmission focusing and receiving dynamic focusing for different types of transducers to speed up the imaging process. To further speed up the imaging process, a multi-threads technique is implemented in order to allow formation of previous image frame data and acquisition of the next one simultaneously. The system is also capable of doing semi-real-time automated SO2 imaging at 10 seconds per frame by changing the wavelength knob of the laser automatically using a stepper motor controlled by the system. Initial in vivo experiments were performed on animal tumors to map out its vasculature and hypoxia level, which were superimposed on co-registered US images. The real-time system allows capturing co-registered US/PA images free of motion artifacts and also provides dynamitic information when contrast agents are used.

Digital Low Level RF Systems for Fermilab Main Ring and Tevatron

NASA Astrophysics Data System (ADS)

Chase, B.; Barnes, B.; Meisner, K.

1997-05-01

At Fermilab, a new Low Level RF system is successfully installed and operating in the Main Ring. Installation is proceeding for a Tevatron system. This upgrade replaces aging CAMAC/NIM components for an increase in accuracy, reliability, and flexibility. These VXI systems are based on a custom three channel direct digital synthesizer(DDS) module. Each synthesizer channel is capable of independent or ganged operation for both frequency and phase modulation. New frequency and phase values are computed at a 100kHz rate on the module's Analog Devices ADSP21062 (SHARC) digital signal processor. The DSP concurrently handles feedforward, feedback, and beam manipulations. Higher level state machines and the control system interface are handled at the crate level using the VxWorks operating system. This paper discusses the hardware, software and operational aspects of these LLRF systems.

Research on control law accelerator of digital signal process chip TMS320F28035 for real-time data acquisition and processing

NASA Astrophysics Data System (ADS)

Zhao, Shuangle; Zhang, Xueyi; Sun, Shengli; Wang, Xudong

2017-08-01

TI C2000 series digital signal process (DSP) chip has been widely used in electrical engineering, measurement and control, communications and other professional fields, DSP TMS320F28035 is one of the most representative of a kind. When using the DSP program, need data acquisition and data processing, and if the use of common mode C or assembly language programming, the program sequence, analogue-to-digital (AD) converter cannot be real-time acquisition, often missing a lot of data. The control low accelerator (CLA) processor can run in parallel with the main central processing unit (CPU), and the frequency is consistent with the main CPU, and has the function of floating point operations. Therefore, the CLA coprocessor is used in the program, and the CLA kernel is responsible for data processing. The main CPU is responsible for the AD conversion. The advantage of this method is to reduce the time of data processing and realize the real-time performance of data acquisition.

A Nonlinear Digital Control Solution for a DC/DC Power Converter

NASA Technical Reports Server (NTRS)

Zhu, Minshao

2002-01-01

A digital Nonlinear Proportional-Integral-Derivative (NPID) control algorithm was proposed to control a 1-kW, PWM, DC/DC, switching power converter. The NPID methodology is introduced and a practical hardware control solution is obtained. The design of the controller was completed using Matlab (trademark) Simulink, while the hardware-in-the-loop testing was performed using both the dSPACE (trademark) rapid prototyping system, and a stand-alone Texas Instruments (trademark) Digital Signal Processor (DSP)-based system. The final Nonlinear digital control algorithm was implemented and tested using the ED408043-1 Westinghouse DC-DC switching power converter. The NPID test results are discussed and compared to the results of a standard Proportional-Integral (PI) controller.

Real-time 3D adaptive filtering for portable imaging systems

NASA Astrophysics Data System (ADS)

Bockenbach, Olivier; Ali, Murtaza; Wainwright, Ian; Nadeski, Mark

2015-03-01

Portable imaging devices have proven valuable for emergency medical services both in the field and hospital environments and are becoming more prevalent in clinical settings where the use of larger imaging machines is impractical. 3D adaptive filtering is one of the most advanced techniques aimed at noise reduction and feature enhancement, but is computationally very demanding and hence often not able to run with sufficient performance on a portable platform. In recent years, advanced multicore DSPs have been introduced that attain high processing performance while maintaining low levels of power dissipation. These processors enable the implementation of complex algorithms like 3D adaptive filtering, improving the image quality of portable medical imaging devices. In this study, the performance of a 3D adaptive filtering algorithm on a digital signal processor (DSP) is investigated. The performance is assessed by filtering a volume of size 512x256x128 voxels sampled at a pace of 10 MVoxels/sec.

JSATS Detector Field Manual

DOE Office of Scientific and Technical Information (OSTI.GOV)

Choi, Eric Y.; Flory, Adam E.; Lamarche, Brian L.

2014-06-01

The Juvenile Salmon Acoustic Telemetry System (JSATS) Detector is a software and hardware system that captures JSATS Acoustic Micro Transmitter (AMT) signals. The system uses hydrophones to capture acoustic signals in the water. This analog signal is then amplified and processed by the Analog to Digital Converter (ADC) and Digital Signal Processor (DSP) board in the computer. This board digitizes and processes the acoustic signal to determine if a possible JSATS tag is present. With this detection, the data will be saved to the computer for further analysis. This document details the features and functionality of the JSATS Detector software.more » The document covers how to install the software, setup and run the detector software. The document will also go over the raw binary waveform file format and CSV files containing RMS values« less

Emergency product generation for disaster management using RISAT and DMSAR quick look SAR processors

NASA Astrophysics Data System (ADS)

Desai, Nilesh; Sharma, Ritesh; Kumar, Saravana; Misra, Tapan; Gujraty, Virendra; Rana, SurinderSingh

2006-12-01

Since last few years, ISRO has embarked upon the development of two complex Synthetic Aperture Radar (SAR) missions, viz. Spaceborne Radar Imaging Satellite (RISAT) and Airborne SAR for Disaster Mangement (DMSAR), as a capacity building measure under country's Disaster Management Support (DMS) Program, for estimating the extent of damage over large areas (~75 Km) and also assess the effectiveness of the relief measures undertaken during natural disasters such as cyclones, epidemics, earthquakes, floods and landslides, forest fires, crop diseases etc. Synthetic Aperture Radar (SAR) has an unique role to play in mapping and monitoring of large areas affected by natural disasters especially floods, owing to its unique capability to see through clouds as well as all-weather imaging capability. The generation of SAR images with quick turn around time is very essential to meet the above DMS objectives. Thus the development of SAR Processors, for these two SAR systems poses considerable challenges and design efforts. Considering the growing user demand and inevitable necessity for a full-fledged high throughput processor, to process SAR data and generate image in real or near-real time, the design and development of a generic SAR Processor has been taken up and evolved, which will meet the SAR processing requirements for both Airborne and Spaceborne SAR systems. This hardware SAR processor is being built, to the extent possible, using only Commercial-Off-The-Shelf (COTS) DSP and other hardware plug-in modules on a Compact PCI (cPCI) platform. Thus, the major thrust has been on working out Multi-processor Digital Signal Processor (DSP) architecture and algorithm development and optimization rather than hardware design and fabrication. For DMSAR, this generic SAR Processor operates as a Quick Look SAR Processor (QLP) on-board the aircraft to produce real time full swath DMSAR images and as a ground based Near-Real Time high precision full swath Processor (NRTP). It will generate full-swath (6 to 75 Kms) DMSAR images in 1m / 3m / 5m / 10m / 30m resolution SAR operating modes. For RISAT mission, this generic Quick Look SAR Processor will be mainly used for browse product generation at NRSA-Shadnagar (SAN) ground receive station. RISAT QLP/NRTP is also proposed to provide an alternative emergency SAR product generation chain. For this, the S/C aux data appended in Onboard SAR Frame Format (x, y, z, x', y', z', roll, pitch, yaw) and predicted orbit from previous days Orbit Determination data will be used. The QLP / NRTP will produce ground range images in real / near real time. For emergency data product generation, additional Off-line tasks like geo-tagging, masking, QC etc needs to be performed on the processed image. The QLP / NRTP would generate geo-tagged images from the annotation data available from the SAR P/L data itself. Since the orbit & attitude information are taken as it is, the location accuracy will be poorer compared to the product generated using ADIF, where smoothened attitude and orbit are made available. Additional tasks like masking, output formatting and Quality checking of the data product will be carried out at Balanagar, NRSA after the image annotated data from QLP / NRTP is sent to Balanagar. The necessary interfaces to the QLP/NRTP for Emergency product generation are also being worked out. As is widely acknowledged, QLP/NRTP for RISAT and DMSAR is an ambitious effort and the technology of future. It is expected that by the middle of next decade, the next generation SAR missions worldwide will have onboard SAR Processors of varying capabilities and generate SAR Data products and Information products onboard instead of SAR raw data. Thus, it is also envisaged that these activities related to QLP/NRTP implementation for RISAT ground segment and DMSAR will be a significant step which will directly feed into the development of onboard real time processing systems for ISRO's future space borne SAR missions. This paper describes the design requirements, configuration details and salient features, apart from highlighting the utility of these Quick Look SAR processors for RISAT and DMSAR, for generation of emergency products for Disaster management.

Use of Field Programmable Gate Array Technology in Future Space Avionics

NASA Technical Reports Server (NTRS)

Ferguson, Roscoe C.; Tate, Robert

2005-01-01

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.

Development of a Real-Time General-Purpose Digital Signal Processing Laboratory System.

DTIC Science & Technology

1983-12-01

should serve several important purposes: to familiarize students with the use of common DSP tools in an instructional environment, to serve as a research ...of Dayton Research Institute researchers for DSP software and DSP system design insight. 3. Formulation of statement of requirements for development...Neither the University of Dayton nor its Research Institute have a DSP computer system. While UD offered no software or DSP system design information

VLSI processors for signal detection in SETI

NASA Technical Reports Server (NTRS)

Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

VLSI processors for signal detection in SETI.

PubMed

Duluk, J F; Linscott, I R; Peterson, A M; Burr, J; Ekroot, B; Twicken, J

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

Research on phase locked loop in optical memory servo system

NASA Astrophysics Data System (ADS)

Qin, Liqin; Ma, Jianshe; Zhang, Jianyong; Pan, Longfa; Deng, Ming

2005-09-01

Phase locked loop (PLL) is a closed loop automatic control system, which can track the phase of input signal. It widely applies in each area of electronic technology. This paper research the phase locked loop in optical memory servo area. This paper introduces the configuration of digital phase locked loop (PLL) and phase locked servo system, the control theory, and analyses system's stability. It constructs the phase locked loop experiment system of optical disk spindle servo, which based on special chip. DC motor is main object, this system adopted phase locked servo technique and digital signal processor (DSP) to achieve constant linear velocity (CLV) in controlling optical spindle motor. This paper analyses the factors that affect the stability of phase locked loop in spindle servo system, and discusses the affection to the optical disk readout signal and jitter due to the stability of phase locked loop.

A low-cost FMCW radar for footprint detection from a mobile platform

NASA Astrophysics Data System (ADS)

Boutte, David; Taylor, Paul; Hunt, Allan

2015-05-01

Footprint and human trail detection in rugged all-weather environments is an important and challenging problem for perimeter security, passive surveillance and reconnaissance. To address this challenge a low-cost, wideband, frequency-modulated continuous wave (FMCW) radar operating at 33.4GHz - 35.5GHz is being developed through a Department of Homeland Security Science and Technology Directorate Phase I SBIR and has been experimentally demonstrated to be capable of detecting footprints and footprint trails on unimproved roads in an experimental setting. It uses a low-cost digital signal processor (DSP) that makes important operating parameters reconfigurable and allows for frequency sweep linearization, a key technique developed to increase footprint signal-to-noise ratio (SNR). This paper discusses the design, DSP implementation and experimental results of a low-cost FMCW radar for mobile footprint detection. A technique for wideband sweep linearization is detailed along with system performance metrics and experimental results showing receive-SNR from footprint trails in sand and on unimproved dirt roads. Results from a second stepped frequency CW (SFCW) Ka-band system are also shown, verifying the ability of both systems to detect footprints and footprint trails in an experimental setting. The results show that there is sufficient receive-SNR to detect even shallow footprints (~1cm) using a radar based detection system in Ka-band. Field experimental results focus on system proof of concept from a static position with mobile results also presented highlighting necessary improvements to both systems.

Encoder fault analysis system based on Moire fringe error signal

NASA Astrophysics Data System (ADS)

Gao, Xu; Chen, Wei; Wan, Qiu-hua; Lu, Xin-ran; Xie, Chun-yu

2018-02-01

Aiming at the problem of any fault and wrong code in the practical application of photoelectric shaft encoder, a fast and accurate encoder fault analysis system is researched from the aspect of Moire fringe photoelectric signal processing. DSP28335 is selected as the core processor and high speed serial A/D converter acquisition card is used. And temperature measuring circuit using AD7420 is designed. Discrete data of Moire fringe error signal is collected at different temperatures and it is sent to the host computer through wireless transmission. The error signal quality index and fault type is displayed on the host computer based on the error signal identification method. The error signal quality can be used to diagnosis the state of error code through the human-machine interface.

A plug-in to Eclipse for VHDL source codes: functionalities

NASA Astrophysics Data System (ADS)

Niton, B.; Poźniak, K. T.; Romaniuk, R. S.

The paper presents an original application, written by authors, which supports writing and edition of source codes in VHDL language. It is a step towards fully automatic, augmented code writing for photonic and electronic systems, also systems based on FPGA and/or DSP processors. An implementation is described, based on VEditor. VEditor is a free license program. Thus, the work presented in this paper supplements and extends this free license. The introduction characterizes shortly available tools on the market which serve for aiding the design processes of electronic systems in VHDL. Particular attention was put on plug-ins to the Eclipse environment and Emacs program. There are presented detailed properties of the written plug-in such as: programming extension conception, and the results of the activities of formatter, re-factorizer, code hider, and other new additions to the VEditor program.

Hierarchical Fuzzy Control Applied to Parallel Connected UPS Inverters Using Average Current Sharing Scheme

NASA Astrophysics Data System (ADS)

Singh, Santosh Kumar; Ghatak Choudhuri, Sumit

2018-05-01

Parallel connection of UPS inverters to enhance power rating is a widely accepted practice. Inter-modular circulating currents appear when multiple inverter modules are connected in parallel to supply variable critical load. Interfacing of modules henceforth requires an intensive design, using proper control strategy. The potentiality of human intuitive Fuzzy Logic (FL) control with imprecise system model is well known and thus can be utilised in parallel-connected UPS systems. Conventional FL controller is computational intensive, especially with higher number of input variables. This paper proposes application of Hierarchical-Fuzzy Logic control for parallel connected Multi-modular inverters system for reduced computational burden on the processor for a given switching frequency. Simulated results in MATLAB environment and experimental verification using Texas TMS320F2812 DSP are included to demonstrate feasibility of the proposed control scheme.

Low-power wearable respiratory sound sensing.

PubMed

Oletic, Dinko; Arsenali, Bruno; Bilas, Vedran

2014-04-09

Building upon the findings from the field of automated recognition of respiratory sound patterns, we propose a wearable wireless sensor implementing on-board respiratory sound acquisition and classification, to enable continuous monitoring of symptoms, such as asthmatic wheezing. Low-power consumption of such a sensor is required in order to achieve long autonomy. Considering that the power consumption of its radio is kept minimal if transmitting only upon (rare) occurrences of wheezing, we focus on optimizing the power consumption of the digital signal processor (DSP). Based on a comprehensive review of asthmatic wheeze detection algorithms, we analyze the computational complexity of common features drawn from short-time Fourier transform (STFT) and decision tree classification. Four algorithms were implemented on a low-power TMS320C5505 DSP. Their classification accuracies were evaluated on a dataset of prerecorded respiratory sounds in two operating scenarios of different detection fidelities. The execution times of all algorithms were measured. The best classification accuracy of over 92%, while occupying only 2.6% of the DSP's processing time, is obtained for the algorithm featuring the time-frequency tracking of shapes of crests originating from wheezing, with spectral features modeled using energy.

Integration of plug-in hybrid electric vehicles (PHEV) with grid connected residential photovoltaic energy systems

NASA Astrophysics Data System (ADS)

Nagarajan, Adarsh; Shireen, Wajiha

2013-06-01

This paper proposes an approach for integrating Plug-In Hybrid Electric Vehicles (PHEV) to an existing residential photovoltaic system, to control and optimize the power consumption of residential load. Control involves determining the source from which residential load will be catered, where as optimization of power flow reduces the stress on the grid. The system built to achieve the goal is a combination of the existing residential photovoltaic system, PHEV, Power Conditioning Unit (PCU), and a controller. The PCU involves two DC-DC Boost Converters and an inverter. This paper emphasizes on developing the controller logic and its implementation in order to accommodate the flexibility and benefits of the proposed integrated system. The proposed controller logic has been simulated using MATLAB SIMULINK and further implemented using Digital Signal Processor (DSP) microcontroller, TMS320F28035, from Texas Instruments

Digital Intermediate Frequency Receiver Module For Use In Airborne Sar Applications

DOEpatents

Tise, Bertice L.; Dubbert, Dale F.

2005-03-08

A digital IF receiver (DRX) module directly compatible with advanced radar systems such as synthetic aperture radar (SAR) systems. The DRX can combine a 1 G-Sample/sec 8-bit ADC with high-speed digital signal processor, such as high gate-count FPGA technology or ASICs to realize a wideband IF receiver. DSP operations implemented in the DRX can include quadrature demodulation and multi-rate, variable-bandwidth IF filtering. Pulse-to-pulse (Doppler domain) filtering can also be implemented in the form of a presummer (accumulator) and an azimuth prefilter. An out of band noise source can be employed to provide a dither signal to the ADC, and later be removed by digital signal processing. Both the range and Doppler domain filtering operations can be implemented using a unique pane architecture which allows on-the-fly selection of the filter decimation factor, and hence, the filter bandwidth. The DRX module can include a standard VME-64 interface for control, status, and programming. An interface can provide phase history data to the real-time image formation processors. A third front-panel data port (FPDP) interface can send wide bandwidth, raw phase histories to a real-time phase history recorder for ground processing.

Indirect rotor position sensing in real time for brushless permanent magnet motor drives

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ertugrul, N.; Acarnley, P.P.

1998-07-01

This paper describes a modern solution to real-time rotor position estimation of brushless permanent magnet (PM) motor drives. The position estimation scheme, based on flux linkage and line-current estimation, is implemented in real time by using the abc reference frame, and it is tested dynamically. The position estimation model of the test motor, development of hardware, and basic operation of the digital signal processor (DSP) are discussed. The overall position estimation strategy is accomplished with a fast DSP (TMS320C30). The method is a shaft position sensorless method that is applicable to a wide range of excitation types in brushless PMmore » motors without any restriction on the motor model and the current excitation. Both rectangular and sinewave-excited brushless PM motor drives are examined, and the results are given to demonstrate the effectiveness of the method with dynamic loads in closed estimated position loop.« less

High-Speed Current dq PI Controller for Vector Controlled PMSM Drive

PubMed Central

Reaz, Mamun Bin Ibne; Rahman, Labonnah Farzana; Chang, Tae Gyu

2014-01-01

High-speed current controller for vector controlled permanent magnet synchronous motor (PMSM) is presented. The controller is developed based on modular design for faster calculation and uses fixed-point proportional-integral (PI) method for improved accuracy. Current dq controller is usually implemented in digital signal processor (DSP) based computer. However, DSP based solutions are reaching their physical limits, which are few microseconds. Besides, digital solutions suffer from high implementation cost. In this research, the overall controller is realizing in field programmable gate array (FPGA). FPGA implementation of the overall controlling algorithm will certainly trim down the execution time significantly to guarantee the steadiness of the motor. Agilent 16821A Logic Analyzer is employed to validate the result of the implemented design in FPGA. Experimental results indicate that the proposed current dq PI controller needs only 50 ns of execution time in 40 MHz clock, which is the lowest computational cycle for the era. PMID:24574913

Autonomous vision networking: miniature wireless sensor networks with imaging technology

NASA Astrophysics Data System (ADS)

Messinger, Gioia; Goldberg, Giora

2006-09-01

The recent emergence of integrated PicoRadio technology, the rise of low power, low cost, System-On-Chip (SOC) CMOS imagers, coupled with the fast evolution of networking protocols and digital signal processing (DSP), created a unique opportunity to achieve the goal of deploying large-scale, low cost, intelligent, ultra-low power distributed wireless sensor networks for the visualization of the environment. Of all sensors, vision is the most desired, but its applications in distributed sensor networks have been elusive so far. Not any more. The practicality and viability of ultra-low power vision networking has been proven and its applications are countless, from security, and chemical analysis to industrial monitoring, asset tracking and visual recognition, vision networking represents a truly disruptive technology applicable to many industries. The presentation discusses some of the critical components and technologies necessary to make these networks and products affordable and ubiquitous - specifically PicoRadios, CMOS imagers, imaging DSP, networking and overall wireless sensor network (WSN) system concepts. The paradigm shift, from large, centralized and expensive sensor platforms, to small, low cost, distributed, sensor networks, is possible due to the emergence and convergence of a few innovative technologies. Avaak has developed a vision network that is aided by other sensors such as motion, acoustic and magnetic, and plans to deploy it for use in military and commercial applications. In comparison to other sensors, imagers produce large data files that require pre-processing and a certain level of compression before these are transmitted to a network server, in order to minimize the load on the network. Some of the most innovative chemical detectors currently in development are based on sensors that change color or pattern in the presence of the desired analytes. These changes are easily recorded and analyzed by a CMOS imager and an on-board DSP processor. Image processing at the sensor node level may also be required for applications in security, asset management and process control. Due to the data bandwidth requirements posed on the network by video sensors, new networking protocols or video extensions to existing standards (e.g. Zigbee) are required. To this end, Avaak has designed and implemented an ultra-low power networking protocol designed to carry large volumes of data through the network. The low power wireless sensor nodes that will be discussed include a chemical sensor integrated with a CMOS digital camera, a controller, a DSP processor and a radio communication transceiver, which enables relaying of an alarm or image message, to a central station. In addition to the communications, identification is very desirable; hence location awareness will be later incorporated to the system in the form of Time-Of-Arrival triangulation, via wide band signaling. While the wireless imaging kernel already exists specific applications for surveillance and chemical detection are under development by Avaak, as part of a co-founded program from ONR and DARPA. Avaak is also designing vision networks for commercial applications - some of which are undergoing initial field tests.

A digital-signal-processor-based optical tomographic system for dynamic imaging of joint diseases

NASA Astrophysics Data System (ADS)

Lasker, Joseph M.

Over the last decade, optical tomography (OT) has emerged as viable biomedical imaging modality. Various imaging systems have been developed that are employed in preclinical as well as clinical studies, mostly targeting breast imaging, brain imaging, and cancer related studies. Of particular interest are so-called dynamic imaging studies where one attempts to image changes in optical properties and/or physiological parameters as they occur during a system perturbation. To successfully perform dynamic imaging studies, great effort is put towards system development that offers increasingly enhanced signal-to-noise performance at ever shorter data acquisition times, thus capturing high fidelity tomographic data within narrower time periods. Towards this goal, I have developed in this thesis a dynamic optical tomography system that is, unlike currently available analog instrumentation, based on digital data acquisition and filtering techniques. At the core of this instrument is a digital signal processor (DSP) that collects, collates, and processes the digitized data set. Complementary protocols between the DSP and a complex programmable logic device synchronizes the sampling process and organizes data flow. Instrument control is implemented through a comprehensive graphical user interface which integrates automated calibration, data acquisition, and signal post-processing. Real-time data is generated at frame rates as high as 140 Hz. An extensive dynamic range (˜190 dB) accommodates a wide scope of measurement geometries and tissue types. Performance analysis demonstrates very low system noise (˜1 pW rms noise equivalent power), excellent signal precision (˜0.04%--0.2%) and long term system stability (˜1% over 40 min). Experiments on tissue phantoms validate spatial and temporal accuracy of the system. As a potential new application of dynamic optical imaging I present the first application of this method to use vascular hemodynamics as a means of characterizing joint diseases, especially effects of rheumatoid arthritis (RA) in the proximal interphalangeal finger joints. Using a dual-wavelength tomographic imaging system and previously implemented reconstruction scheme, I have performed initial dynamic imaging case studies on healthy volunteers and patients diagnosed with RA. These studies support our hypothesis that differences in the vascular and metabolic reactivity exist between affected and unaffected joints and can be used for diagnostic purposes.

Design and implementation of a hybrid digital phase-locked loop with a TMS320C25: An application to a transponder receiver breadboard

NASA Technical Reports Server (NTRS)

Yeh, H.-G.; Nguyen, T. M.

1994-01-01

Design, modeling, analysis, and simulation of a phase-locked loop (PLL) with a digital loop filter are presented in this article. A TMS320C25 digital signal processor (DSP) is used to implement this digital loop filter. In order to keep the compatibility, the main design goal was to replace the analog PLL (APLL) of the Deep-Space Transponder (DST) receiver breadboard's loop filter with a digital loop filter without changing anything else. This replacement results in a hybrid digital PLL (HDPLL). Both the original APLL and the designed HDPLL are Type I second-order systems. The real-time performance of the HDPLL and the receiver is provided and evaluated.

A Succinct Naming Convention for Lengthy Hexadecimal Numbers

NASA Technical Reports Server (NTRS)

Grant, Michael S.

1997-01-01

Engineers, computer scientists, mathematicians and others must often deal with lengthy hexadecimal numbers. As memory requirements for software increase, the associated memory address space for systems necessitates the use of longer and longer strings of hexadecimal characters to describe a given number. For example, the address space of some digital signal processors (DSP's) now ranges in the billions of words, requiring eight hexadecimal characters for many of the addresses. This technical memorandum proposes a simple grouping scheme for more clearly representing lengthy hexadecimal numbers in written material, as well as a "code" for naming and more quickly verbalizing such numbers. This should facilitate communications among colleagues in engineering and related fields, and aid in comprehension and temporary memorization of important hexadecimal numbers during design work.

FPGA wavelet processor design using language for instruction-set architectures (LISA)

NASA Astrophysics Data System (ADS)

Meyer-Bäse, Uwe; Vera, Alonzo; Rao, Suhasini; Lenk, Karl; Pattichis, Marios

2007-04-01

The design of an microprocessor is a long, tedious, and error-prone task consisting of typically three design phases: architecture exploration, software design (assembler, linker, loader, profiler), architecture implementation (RTL generation for FPGA or cell-based ASIC) and verification. The Language for instruction-set architectures (LISA) allows to model a microprocessor not only from instruction-set but also from architecture description including pipelining behavior that allows a design and development tool consistency over all levels of the design. To explore the capability of the LISA processor design platform a.k.a. CoWare Processor Designer we present in this paper three microprocessor designs that implement a 8/8 wavelet transform processor that is typically used in today's FBI fingerprint compression scheme. We have designed a 3 stage pipelined 16 bit RISC processor (NanoBlaze). Although RISC μPs are usually considered "fast" processors due to design concept like constant instruction word size, deep pipelines and many general purpose registers, it turns out that DSP operations consume essential processing time in a RISC processor. In a second step we have used design principles from programmable digital signal processor (PDSP) to improve the throughput of the DWT processor. A multiply-accumulate operation along with indirect addressing operation were the key to achieve higher throughput. A further improvement is possible with today's FPGA technology. Today's FPGAs offer a large number of embedded array multipliers and it is now feasible to design a "true" vector processor (TVP). A multiplication of two vectors can be done in just one clock cycle with our TVP, a complete scalar product in two clock cycles. Code profiling and Xilinx FPGA ISE synthesis results are provided that demonstrate the essential improvement that a TVP has compared with traditional RISC or PDSP designs.

Spacewire on Earth orbiting scatterometers

NASA Technical Reports Server (NTRS)

Bachmann, Alex; Lang, Minh; Lux, James; Steffke, Richard

2002-01-01

The need for a high speed, reliable and easy to implement communication link has led to the development of a space flight oriented version of IEEE 1355 called SpaceWire. SpaceWire is based on high-speed (200 Mbps) serial point-to-point links using Low Voltage Differential Signaling (LVDS). SpaceWIre has provisions for routing messages between a large network of processors, using wormhole routing for low overhead and latency. {additionally, there are available space qualified hybrids, which provide the Link layer to the user's bus}. A test bed of multiple digital signal processor breadboards, demonstrating the ability to meet signal processing requirements for an orbiting scatterometer has been implemented using three Astrium MCM-DSPs, each breadboard consists of a Multi Chip Module (MCM) that combines a space qualified Digital Signal Processor and peripherals, including IEEE-1355 links. With the addition of appropriate physical layer interfaces and software on the DSP, the SpaceWire link is used to communicate between processors on the test bed, e.g. sending timing references, commands, status, and science data among the processors. Results are presented on development issues surrounding the use of SpaceWire in this environment, from physical layer implementation (cables, connectors, LVDS drivers) to diagnostic tools, driver firmware, and development methodology. The tools, methods, and hardware, software challenges and preliminary performance are investigated and discussed.

Adaptive Suppression of Noise in Voice Communications

NASA Technical Reports Server (NTRS)

Kozel, David; DeVault, James A.; Birr, Richard B.

2003-01-01

A subsystem for the adaptive suppression of noise in a voice communication system effects a high level of reduction of noise that enters the system through microphones. The subsystem includes a digital signal processor (DSP) plus circuitry that implements voice-recognition and spectral- manipulation techniques. The development of the adaptive noise-suppression subsystem was prompted by the following considerations: During processing of the space shuttle at Kennedy Space Center, voice communications among test team members have been significantly impaired in several instances because some test participants have had to communicate from locations with high ambient noise levels. Ear protection for the personnel involved is commercially available and is used in such situations. However, commercially available noise-canceling microphones do not provide sufficient reduction of noise that enters through microphones and thus becomes transmitted on outbound communication links.

A single-board NMR spectrometer based on a software defined radio architecture

NASA Astrophysics Data System (ADS)

Tang, Weinan; Wang, Weimin

2011-01-01

A single-board software defined radio (SDR) spectrometer for nuclear magnetic resonance (NMR) is presented. The SDR-based architecture, realized by combining a single field programmable gate array (FPGA) and a digital signal processor (DSP) with peripheral radio frequency (RF) front-end circuits, makes the spectrometer compact and reconfigurable. The DSP, working as a pulse programmer, communicates with a personal computer via a USB interface and controls the FPGA through a parallel port. The FPGA accomplishes digital processing tasks such as a numerically controlled oscillator (NCO), digital down converter (DDC) and gradient waveform generator. The NCO, with agile control of phase, frequency and amplitude, is part of a direct digital synthesizer that is used to generate an RF pulse. The DDC performs quadrature demodulation, multistage low-pass filtering and gain adjustment to produce a bandpass signal (receiver bandwidth from 3.9 kHz to 10 MHz). The gradient waveform generator is capable of outputting shaped gradient pulse waveforms and supports eddy-current compensation. The spectrometer directly acquires an NMR signal up to 30 MHz in the case of baseband sampling and is suitable for low-field (<0.7 T) application. Due to the featured SDR architecture, this prototype has flexible add-on ability and is expected to be suitable for portable NMR systems.

VPI - VIBRATION PATTERN IMAGER: A CONTROL AND DATA ACQUISITION SYSTEM FOR SCANNING LASER VIBROMETERS

NASA Technical Reports Server (NTRS)

Rizzi, S. A.

1994-01-01

The Vibration Pattern Imager (VPI) system was designed to control and acquire data from laser vibrometer sensors. The PC computer based system uses a digital signal processing (DSP) board and an analog I/O board to control the sensor and to process the data. The VPI system was originally developed for use with the Ometron VPI Sensor (Ometron Limited, Kelvin House, Worsley Bridge Road, London, SE26 5BX, England), but can be readily adapted to any commercially available sensor which provides an analog output signal and requires analog inputs for control of mirror positioning. VPI's graphical user interface allows the operation of the program to be controlled interactively through keyboard and mouse-selected menu options. The main menu controls all functions for setup, data acquisition, display, file operations, and exiting the program. Two types of data may be acquired with the VPI system: single point or "full field". In the single point mode, time series data is sampled by the A/D converter on the I/O board at a user-defined rate for the selected number of samples. The position of the measuring point, adjusted by mirrors in the sensor, is controlled via a mouse input. In the "full field" mode, the measurement point is moved over a user-selected rectangular area with up to 256 positions in both x and y directions. The time series data is sampled by the A/D converter on the I/O board and converted to a root-mean-square (rms) value by the DSP board. The rms "full field" velocity distribution is then uploaded for display and storage. VPI is written in C language and Texas Instruments' TMS320C30 assembly language for IBM PC series and compatible computers running MS-DOS. The program requires 640K of RAM for execution, and a hard disk with 10Mb or more of disk space is recommended. The program also requires a mouse, a VGA graphics display, a Four Channel analog I/O board (Spectrum Signal Processing, Inc.; Westborough, MA), a break-out box and a Spirit-30 board (Sonitech International, Inc.; Wellesley, MA) which includes a TMS320C30 DSP processor, 256Kb zero wait state SRAM, and a daughter board with 8Mb one wait state DRAM. Please contact COSMIC for additional information on required hardware and software. In order to compile the provided VPI source code, a Microsoft C version 6.0 compiler, a Texas Instruments' TMS320C30 assembly language compiler, and the Spirit 30 run time libraries are required. A math co-processor is highly recommended. A sample MS-DOS executable is provided on the distribution medium. The standard distribution medium for this program is one 5.25 inch 360K MS-DOS format diskette. The contents of the diskettes are compressed using the PKWARE archiving tools. The utility to unarchive the files, PKUNZIP.EXE, is included. VPI was developed in 1991-1992.

Noise-Canceling Helmet Audio System

NASA Technical Reports Server (NTRS)

Seibert, Marc A.; Culotta, Anthony J.

2007-01-01

A prototype helmet audio system has been developed to improve voice communication for the wearer in a noisy environment. The system was originally intended to be used in a space suit, wherein noise generated by airflow of the spacesuit life-support system can make it difficult for remote listeners to understand the astronaut s speech and can interfere with the astronaut s attempt to issue vocal commands to a voice-controlled robot. The system could be adapted to terrestrial use in helmets of protective suits that are typically worn in noisy settings: examples include biohazard, fire, rescue, and diving suits. The system (see figure) includes an array of microphones and small loudspeakers mounted at fixed positions in a helmet, amplifiers and signal-routing circuitry, and a commercial digital signal processor (DSP). Notwithstanding the fixed positions of the microphones and loudspeakers, the system can accommodate itself to any normal motion of the wearer s head within the helmet. The system operates in conjunction with a radio transceiver. An audio signal arriving via the transceiver intended to be heard by the wearer is adjusted in volume and otherwise conditioned and sent to the loudspeakers. The wearer s speech is collected by the microphones, the outputs of which are logically combined (phased) so as to form a microphone- array directional sensitivity pattern that discriminates in favor of sounds coming from vicinity of the wearer s mouth and against sounds coming from elsewhere. In the DSP, digitized samples of the microphone outputs are processed to filter out airflow noise and to eliminate feedback from the loudspeakers to the microphones. The resulting conditioned version of the wearer s speech signal is sent to the transceiver.

LIBS data analysis using a predictor-corrector based digital signal processor algorithm

NASA Astrophysics Data System (ADS)

Sanders, Alex; Griffin, Steven T.; Robinson, Aaron

2012-06-01

There are many accepted sensor technologies for generating spectra for material classification. Once the spectra are generated, communication bandwidth limitations favor local material classification with its attendant reduction in data transfer rates and power consumption. Transferring sensor technologies such as Cavity Ring-Down Spectroscopy (CRDS) and Laser Induced Breakdown Spectroscopy (LIBS) require effective material classifiers. A result of recent efforts has been emphasis on Partial Least Squares - Discriminant Analysis (PLS-DA) and Principle Component Analysis (PCA). Implementation of these via general purpose computers is difficult in small portable sensor configurations. This paper addresses the creation of a low mass, low power, robust hardware spectra classifier for a limited set of predetermined materials in an atmospheric matrix. Crucial to this is the incorporation of PCA or PLS-DA classifiers into a predictor-corrector style implementation. The system configuration guarantees rapid convergence. Software running on multi-core Digital Signal Processor (DSPs) simulates a stream-lined plasma physics model estimator, reducing Analog-to-Digital (ADC) power requirements. This paper presents the results of a predictorcorrector model implemented on a low power multi-core DSP to perform substance classification. This configuration emphasizes the hardware system and software design via a predictor corrector model that simultaneously decreases the sample rate while performing the classification.

Design of a broadband active silencer using μ-synthesis

NASA Astrophysics Data System (ADS)

Bai, Mingsian R.; Zeung, Pingshun

2004-01-01

A robust spatially feedforward controller is developed for broadband attenuation of noise in ducts. To meet the requirements of robust performance and robust stability in the presence of plant uncertainties, a μ-synthesis procedure via D- K iteration is exploited to obtain the optimal controller. This approach considers uncertainties as modelling errors of the nominal plant in high frequency and is implemented using a floating point digital signal processor (DSP). Experimental investigation was undertaken on a finite-length duct to justify the proposed controller. The μ- controller is compared to other control algorithms such as the H2 method, the H∞ method and the filtered-U least mean square (FULMS) algorithm. Experimental results indicate that the proposed system has attained 25.8 dB maximal attenuation in the band 250-650 Hz.

High precision locating control system based on VCM for Talbot lithography

NASA Astrophysics Data System (ADS)

Yao, Jingwei; Zhao, Lixin; Deng, Qian; Hu, Song

2016-10-01

Aiming at the high precision and efficiency requirements of Z-direction locating in Talbot lithography, a control system based on Voice Coil Motor (VCM) was designed. In this paper, we built a math model of VCM and its moving characteristic was analyzed. A double-closed loop control strategy including position loop and current loop were accomplished. The current loop was implemented by driver, in order to achieve the rapid follow of the system current. The position loop was completed by the digital signal processor (DSP) and the position feedback was achieved by high precision linear scales. Feed forward control and position feedback Proportion Integration Differentiation (PID) control were applied in order to compensate for dynamic lag and improve the response speed of the system. And the high precision and efficiency of the system were verified by simulation and experiments. The results demonstrated that the performance of Z-direction gantry was obviously improved, having high precision, quick responses, strong real-time and easily to expend for higher precision.

An embedded multi-core parallel model for real-time stereo imaging

NASA Astrophysics Data System (ADS)

He, Wenjing; Hu, Jian; Niu, Jingyu; Li, Chuanrong; Liu, Guangyu

2018-04-01

The real-time processing based on embedded system will enhance the application capability of stereo imaging for LiDAR and hyperspectral sensor. The task partitioning and scheduling strategies for embedded multiprocessor system starts relatively late, compared with that for PC computer. In this paper, aimed at embedded multi-core processing platform, a parallel model for stereo imaging is studied and verified. After analyzing the computing amount, throughout capacity and buffering requirements, a two-stage pipeline parallel model based on message transmission is established. This model can be applied to fast stereo imaging for airborne sensors with various characteristics. To demonstrate the feasibility and effectiveness of the parallel model, a parallel software was designed using test flight data, based on the 8-core DSP processor TMS320C6678. The results indicate that the design performed well in workload distribution and had a speed-up ratio up to 6.4.

FPGA Acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods.

PubMed

Zierke, Stephanie; Bakos, Jason D

2010-04-12

Likelihood (ML)-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. This method is used in applications such as RAxML, GARLI, MrBayes, PAML, and PAUP. The Phylogenetic Likelihood Function (PLF) is an important kernel computation for this method. The PLF consists of a loop with no conditional behavior or dependencies between iterations. As such it contains a high potential for exploiting parallelism using micro-architectural techniques. In this paper, we describe a technique for mapping the PLF and supporting logic onto a Field Programmable Gate Array (FPGA)-based co-processor. By leveraging the FPGA's on-chip DSP modules and the high-bandwidth local memory attached to the FPGA, the resultant co-processor can accelerate ML-based methods and outperform state-of-the-art multi-core processors. We use the MrBayes 3 tool as a framework for designing our co-processor. For large datasets, we estimate that our accelerated MrBayes, if run on a current-generation FPGA, achieves a 10x speedup relative to software running on a state-of-the-art server-class microprocessor. The FPGA-based implementation achieves its performance by deeply pipelining the likelihood computations, performing multiple floating-point operations in parallel, and through a natural log approximation that is chosen specifically to leverage a deeply pipelined custom architecture. Heterogeneous computing, which combines general-purpose processors with special-purpose co-processors such as FPGAs and GPUs, is a promising approach for high-performance phylogeny inference as shown by the growing body of literature in this field. FPGAs in particular are well-suited for this task because of their low power consumption as compared to many-core processors and Graphics Processor Units (GPUs).

Hardware design and implementation of fast DOA estimation method based on multicore DSP

NASA Astrophysics Data System (ADS)

Guo, Rui; Zhao, Yingxiao; Zhang, Yue; Lin, Qianqiang; Chen, Zengping

2016-10-01

In this paper, we present a high-speed real-time signal processing hardware platform based on multicore digital signal processor (DSP). The real-time signal processing platform shows several excellent characteristics including high performance computing, low power consumption, large-capacity data storage and high speed data transmission, which make it able to meet the constraint of real-time direction of arrival (DOA) estimation. To reduce the high computational complexity of DOA estimation algorithm, a novel real-valued MUSIC estimator is used. The algorithm is decomposed into several independent steps and the time consumption of each step is counted. Based on the statistics of the time consumption, we present a new parallel processing strategy to distribute the task of DOA estimation to different cores of the real-time signal processing hardware platform. Experimental results demonstrate that the high processing capability of the signal processing platform meets the constraint of real-time direction of arrival (DOA) estimation.

Compilation time analysis to minimize run-time overhead in preemptive scheduling on multiprocessors

NASA Astrophysics Data System (ADS)

Wauters, Piet; Lauwereins, Rudy; Peperstraete, J.

1994-10-01

This paper describes a scheduling method for hard real-time Digital Signal Processing (DSP) applications, implemented on a multi-processor. Due to the very high operating frequencies of DSP applications (typically hundreds of kHz) runtime overhead should be kept as small as possible. Because static scheduling introduces very little run-time overhead it is used as much as possible. Dynamic pre-emption of tasks is allowed if and only if it leads to better performance in spite of the extra run-time overhead. We essentially combine static scheduling with dynamic pre-emption using static priorities. Since we are dealing with hard real-time applications we must be able to guarantee at compile-time that all timing requirements will be satisfied at run-time. We will show that our method performs at least as good as any static scheduling method. It also reduces the total amount of dynamic pre-emptions compared with run time methods like deadline monotonic scheduling.

CATAVIÑA: new infrared camera for OAN-SPM

NASA Astrophysics Data System (ADS)

Iriarte, Arturo; Cruz-González, Irene; Martínez, Luis A.; Tinoco, Silvio; Lara, Gerardo; Ruiz, Elfego; Sohn, Erika; Bernal, Abel; Angeles, Fernando; Moreno, Arturo; Murillo, Francisco; Langarica, Rosalía; Luna, Esteban; Salas, Luis; Cajero, Vicente

2006-06-01

CATAVIÑA is a near-infrared camera system to be operated in conjunction with the existing multi-purpose nearinfrared optical bench "CAMALEON" in OAN-SPM. Observing modes include direct imaging, spectroscopy, Fabry- Perot interferometry and polarimetry. This contribution focuses on the optomechanics and detector controller description of CATAVIÑA, which is planned to start operating later in 2006. The camera consists of an 8 inch LN2 dewar containing a 10 filter carousel, a radiation baffle and the detector circuit board mount. The system is based on a Rockwell 1024x1024 HgCdTe (HAWAII-I) FPA, operating in the 1 to 2.5 micron window. The detector controller/readout system was designed and developed at UNAM Instituto de Astronomia. It is based on five Texas Instruments DSK digital signal processor (DSP) modules. One module generates the detector and ADC-system control, while the remaining four are in charge of the acquisition of each of the detector's quadrants. Each DSP has a built-in expanded memory module in order to store more than one image. The detector read-out and signal driver subsystems are mounted onto the dewar in a "back-pack" fashion, each containing four independent pre-amplifiers, converters and signal drivers, that communicate through fiber optics with their respective DSPs. This system has the possibility of programming the offset input voltage and converter gain. The controller software architecture is based on a client/server model. The client sends commands through the TCP/IP protocol and acquires the image. The server consists of a microcomputer with an embedded Linux operating system, which runs the main program that receives the user commands and interacts with the timing and acquisition DSPs. The observer's interface allows for several readout and image processing modes.

Progress in video immersion using Panospheric imaging

NASA Astrophysics Data System (ADS)

Bogner, Stephen L.; Southwell, David T.; Penzes, Steven G.; Brosinsky, Chris A.; Anderson, Ron; Hanna, Doug M.

1998-09-01

Having demonstrated significant technical and marketplace advantages over other modalities for video immersion, PanosphericTM Imaging (PI) continues to evolve rapidly. This paper reports on progress achieved since AeroSense 97. The first practical field deployment of the technology occurred in June-August 1997 during the NASA-CMU 'Atacama Desert Trek' activity, where the Nomad mobile robot was teleoperated via immersive PanosphericTM imagery from a distance of several thousand kilometers. Research using teleoperated vehicles at DRES has also verified the exceptional utility of the PI technology for achieving high levels of situational awareness, operator confidence, and mission effectiveness. Important performance enhancements have been achieved with the completion of the 4th Generation PI DSP-based array processor system. The system is now able to provide dynamic full video-rate generation of spatial and computational transformations, resulting in a programmable and fully interactive immersive video telepresence. A new multi- CCD camera architecture has been created to exploit the bandwidth of this processor, yielding a well-matched PI system with greatly improved resolution. While the initial commercial application for this technology is expected to be video tele- conferencing, it also appears to have excellent potential for application in the 'Immersive Cockpit' concept. Additional progress is reported in the areas of Long Wave Infrared PI Imaging, Stereo PI concepts, PI based Video-Servoing concepts, PI based Video Navigation concepts, and Foveation concepts (to merge localized high-resolution views with immersive views).

Optimized design of embedded DSP system hardware supporting complex algorithms

NASA Astrophysics Data System (ADS)

Li, Yanhua; Wang, Xiangjun; Zhou, Xinling

2003-09-01

The paper presents an optimized design method for a flexible and economical embedded DSP system that can implement complex processing algorithms as biometric recognition, real-time image processing, etc. It consists of a floating-point DSP, 512 Kbytes data RAM, 1 Mbytes FLASH program memory, a CPLD for achieving flexible logic control of input channel and a RS-485 transceiver for local network communication. Because of employing a high performance-price ratio DSP TMS320C6712 and a large FLASH in the design, this system permits loading and performing complex algorithms with little algorithm optimization and code reduction. The CPLD provides flexible logic control for the whole DSP board, especially in input channel, and allows convenient interface between different sensors and DSP system. The transceiver circuit can transfer data between DSP and host computer. In the paper, some key technologies are also introduced which make the whole system work efficiently. Because of the characters referred above, the hardware is a perfect flat for multi-channel data collection, image processing, and other signal processing with high performance and adaptability. The application section of this paper presents how this hardware is adapted for the biometric identification system with high identification precision. The result reveals that this hardware is easy to interface with a CMOS imager and is capable of carrying out complex biometric identification algorithms, which require real-time process.

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Ormsby, John (Technical Monitor)

2002-01-01

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

ELITE-3 active vibration isolation workstation

NASA Astrophysics Data System (ADS)

Anderson, Eric H.; Houghton, Bowie

2001-06-01

This paper describes the development and capabilities of ELITE-3, a product that incorporates piezoelectric actuators to provide ultrastable work surfaces for very high resolution wafer production, metrology, microscopy, and other applications. The electromechanical, electronic, and software/firmware parts of the ELITE-3 active workstation are described, with an emphasis on considerations relating to the piezoelectric transducers. Performance of the system and its relation to the smart materials is discussed. As the floor beneath a vibration-sensitive instrument supported by ELITE-3 moves, piezoelectrics are controlled to minimize the motion of the instrument. A digital signal processor (DSP) determines the appropriate signals to apply to the actuators. A PC-based interface allows reprogramming of control algorithms and resetting of other parameters within the firmware. The modular product allows incorporation of vibration isolator, actuator and sensor modules into original equipment manufacturer (OEM) products. Alternatively, a workstation can be integrated as an integrated standalone system. The paper describes the system architecture, overall approach to vibration isolation, and various system components, and summarizes motivations for key design approaches.

Infrared hyperspectral imaging sensor for gas detection

NASA Astrophysics Data System (ADS)

Hinnrichs, Michele

2000-11-01

A small light weight man portable imaging spectrometer has many applications; gas leak detection, flare analysis, threat warning, chemical agent detection, just to name a few. With support from the US Air Force and Navy, Pacific Advanced Technology has developed a small man portable hyperspectral imaging sensor with an embedded DSP processor for real time processing that is capable of remotely imaging various targets such as gas plums, flames and camouflaged targets. Based upon their spectral signature the species and concentration of gases can be determined. This system has been field tested at numerous places including White Mountain, CA, Edwards AFB, and Vandenberg AFB. Recently evaluation of the system for gas detection has been performed. This paper presents these results. The system uses a conventional infrared camera fitted with a diffractive optic that images as well as disperses the incident radiation to form spectral images that are collected in band sequential mode. Because the diffractive optic performs both imaging and spectral filtering, the lens system consists of only a single element that is small, light weight and robust, thus allowing man portability. The number of spectral bands are programmable such that only those bands of interest need to be collected. The system is entirely passive, therefore, easily used in a covert operation. Currently Pacific Advanced Technology is working on the next generation of this camera system that will have both an embedded processor as well as an embedded digital signal processor in a small hand held camera configuration. This will allow the implementation of signal and image processing algorithms for gas detection and identification in real time. This paper presents field test data on gas detection and identification as well as discuss the signal and image processing used to enhance the gas visibility. Flow rates as low as 0.01 cubic feet per minute have been imaged with this system.

Modulated Fourier Transform Raman Fiber-Optic Spectroscopy

NASA Technical Reports Server (NTRS)

Jensen, Brian J. (Inventor); Cooper, John B. (Inventor); Wise, Kent L. (Inventor)

2000-01-01

A modification to a commercial Fourier Transform (FT) Raman spectrometer is presented for the elimination of thermal backgrounds in the FT Raman spectra. The modification involves the use of a mechanical optical chopper to modulate the continuous wave laser, remote collection of the signal via fiber optics, and connection of a dual-phase digital-signal-processor (DSP) lock-in amplifier between the detector and the spectrometer's collection electronics to demodulate and filter the optical signals. The resulting Modulated Fourier Transform Raman Fiber-Optic Spectrometer is capable of completely eliminating thermal backgrounds at temperatures exceeding 300 C.

Shuttle orbiter - IUS/DSP satellite interface contamination study

NASA Technical Reports Server (NTRS)

Rantanen, R. O.; Strange, D. A.

1978-01-01

The results of a contamination analysis on the Defense Support Program (DSP) satellite during launch and deployment by the Space Transportation System (STS) are presented. Predicted contaminant deposition was also included on critical DSP surfaces during the period soon after launch when the DSP is in the shuttle orbiter bay with the doors closed, the bay doors open, and during initial deployment. Additionally, a six sided box was placed at the spacecraft position to obtain directional contaminant flux information for a general payload while in the bay and during deployment. The analysis included contamination sources from the shuttle orbiter, IUS and cradle, the DSP sensor and the DSP support package.

Automatic generation of Web mining environments

NASA Astrophysics Data System (ADS)

Cibelli, Maurizio; Costagliola, Gennaro

1999-02-01

The main problem related to the retrieval of information from the world wide web is the enormous number of unstructured documents and resources, i.e., the difficulty of locating and tracking appropriate sources. This paper presents a web mining environment (WME), which is capable of finding, extracting and structuring information related to a particular domain from web documents, using general purpose indices. The WME architecture includes a web engine filter (WEF), to sort and reduce the answer set returned by a web engine, a data source pre-processor (DSP), which processes html layout cues in order to collect and qualify page segments, and a heuristic-based information extraction system (HIES), to finally retrieve the required data. Furthermore, we present a web mining environment generator, WMEG, that allows naive users to generate a WME specific to a given domain by providing a set of specifications.

Moving Object Detection Using Scanning Camera on a High-Precision Intelligent Holder.

PubMed

Chen, Shuoyang; Xu, Tingfa; Li, Daqun; Zhang, Jizhou; Jiang, Shenwang

2016-10-21

During the process of moving object detection in an intelligent visual surveillance system, a scenario with complex background is sure to appear. The traditional methods, such as "frame difference" and "optical flow", may not able to deal with the problem very well. In such scenarios, we use a modified algorithm to do the background modeling work. In this paper, we use edge detection to get an edge difference image just to enhance the ability of resistance illumination variation. Then we use a "multi-block temporal-analyzing LBP (Local Binary Pattern)" algorithm to do the segmentation. In the end, a connected component is used to locate the object. We also produce a hardware platform, the core of which consists of the DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) platforms and the high-precision intelligent holder.

A new instantaneous torque control of PM synchronous motor for high-performance direct-drive applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chung, S.K.; Kim, H.S.; Kim, C.G.

1998-05-01

a new instantaneous torque-control strategy is presented for high-performance control of a permanent magnet (PM) synchronous motor. In order to deal with the torque pulsating problem of a PM synchronous motor in a low-speed region, new torque estimation and control techniques are proposed. The linkage flux of a PM synchronous motor is estimated using a model reference adaptive system technique, and the developed torque is instantaneously controlled by the proposed torque controller combining a variable structure control (VSC) with a space-vector pulse-width modulation (PWM). The proposed control provides the advantage of reducing the torque pulsation caused by the nonsinusoidal fluxmore » distribution. This control strategy is applied to the high-torque PM synchronous motor drive system for direct-drive applications and implemented by using a software of the digital signal processor (DSP) TMS320C30. The simulations and experiments are carried out for this system, and the results well demonstrate the effectiveness of the proposed control.« less

DPP and DSP are Necessary for Maintaining TGF-β1 Activity in Dentin

PubMed Central

Yamakoshi, Y.; Kinoshita, S.; Izuhara, L.; Karakida, T.; Fukae, M.; Oida, S.

2014-01-01

Porcine dentin sialophosphoprotein (DSPP) is the most abundant non-collagenous protein in dentin. It is processed by proteases into 3 independent proteins: dentin sialoprotein (DSP), dentin glycoprotein (DGP), and dentin phosphoprotein (DPP). We fractionated DPP and DSP along with TGF-β activity by ion exchange (IE) chromatography from developing pig molars and measured their alkaline phosphatase (ALP)-stimulating activity in human periodontal (HPDL) cells with or without TGF-β receptor inhibitor. We then purified TGF-β-unbound or -bound DPP and DSP by reverse-phase high-performance liquid chromatography (RP-HPLC) using the ALP-HPDL system. The TGF-β isoform bound to DPP and DSP was identified as being TGF-β1 by both ELISA and LC-MS/MS analysis. We incubated carrier-free human recombinant TGF-β1 (CF-hTGF-β1) with TGF-β-unbound DPP or DSP and characterized the binding on IE-HPLC using the ALP-HPDL system. When only CF-hTGF-β1 was incubated, approximately 3.6% of the ALP-stimulating activity remained. DPP and DSP rescued the loss of TGF-β1 activity. Approximately 19% and 10% of the ALP stimulating activities were retained by the binding of TGF-β to DPP and DSP, respectively. The type I collagen infrequently bound to CF-hTGF-β1. We conclude that both DPP and DSP help retain TGF-β1 activity in porcine dentin. PMID:24799420

Monitoring of electric-cardio signals based on DSP

NASA Astrophysics Data System (ADS)

Yan, Yi-xin; Sun, Hui-nan; Lv, Shuang

2008-10-01

Monitoring of electric-cardio signals is the most direct method of discovering heart diseases. This article presents an electric-cardio signal acquisition and processing system based on DSP. According to the features of electric-cardio signals, the proposed system uses the AgCl electrode as electric-cardio signals sensor, and acquires analog signals with AD620 as the prepositional amplifier, and the digital system equipped is with TMS320LF2407A DSP. The design of digital filter and the analysis of heart rate variation are realized by programming in the DSP. Finally the ECG is obtained with P and T waves along with obvious QRS multi-wave characteristics. The system has low power dissipation, low cost and high precision, which meets the requirements for medical instruments.

A new high-speed IR camera system

NASA Technical Reports Server (NTRS)

Travis, Jeffrey W.; Shu, Peter K.; Jhabvala, Murzy D.; Kasten, Michael S.; Moseley, Samuel H.; Casey, Sean C.; Mcgovern, Lawrence K.; Luers, Philip J.; Dabney, Philip W.; Kaipa, Ravi C.

1994-01-01

A multi-organizational team at the Goddard Space Flight Center is developing a new far infrared (FIR) camera system which furthers the state of the art for this type of instrument by the incorporating recent advances in several technological disciplines. All aspects of the camera system are optimized for operation at the high data rates required for astronomical observations in the far infrared. The instrument is built around a Blocked Impurity Band (BIB) detector array which exhibits responsivity over a broad wavelength band and which is capable of operating at 1000 frames/sec, and consists of a focal plane dewar, a compact camera head electronics package, and a Digital Signal Processor (DSP)-based data system residing in a standard 486 personal computer. In this paper we discuss the overall system architecture, the focal plane dewar, and advanced features and design considerations for the electronics. This system, or one derived from it, may prove useful for many commercial and/or industrial infrared imaging or spectroscopic applications, including thermal machine vision for robotic manufacturing, photographic observation of short-duration thermal events such as combustion or chemical reactions, and high-resolution surveillance imaging.

Method and apparatus for optical encoding with compressible imaging

NASA Technical Reports Server (NTRS)

Leviton, Douglas B. (Inventor)

2006-01-01

The present invention presents an optical encoder with increased conversion rates. Improvement in the conversion rate is a result of combining changes in the pattern recognition encoder's scale pattern with an image sensor readout technique which takes full advantage of those changes, and lends itself to operation by modern, high-speed, ultra-compact microprocessors and digital signal processors (DSP) or field programmable gate array (FPGA) logic elements which can process encoder scale images at the highest speeds. Through these improvements, all three components of conversion time (reciprocal conversion rate)--namely exposure time, image readout time, and image processing time--are minimized.

BPSK Demodulation Using Digital Signal Processing

NASA Technical Reports Server (NTRS)

Garcia, Thomas R.

1996-01-01

A digital communications signal is a sinusoidal waveform that is modified by a binary (digital) information signal. The sinusoidal waveform is called the carrier. The carrier may be modified in amplitude, frequency, phase, or a combination of these. In this project a binary phase shift keyed (BPSK) signal is the communication signal. In a BPSK signal the phase of the carrier is set to one of two states, 180 degrees apart, by a binary (i.e., 1 or 0) information signal. A digital signal is a sampled version of a "real world" time continuous signal. The digital signal is generated by sampling the continuous signal at discrete points in time. The rate at which the signal is sampled is called the sampling rate (f(s)). The device that performs this operation is called an analog-to-digital (A/D) converter or a digitizer. The digital signal is composed of the sequence of individual values of the sampled BPSK signal. Digital signal processing (DSP) is the modification of the digital signal by mathematical operations. A device that performs this processing is called a digital signal processor. After processing, the digital signal may then be converted back to an analog signal using a digital-to-analog (D/A) converter. The goal of this project is to develop a system that will recover the digital information from a BPSK signal using DSP techniques. The project is broken down into the following steps: (1) Development of the algorithms required to demodulate the BPSK signal; (2) Simulation of the system; and (3) Implementation a BPSK receiver using digital signal processing hardware.

MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barhen, Jacob; Kerekes, Ryan A; ST Charles, Jesse Lee

2008-01-01

High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlationmore » processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core performs the matrix-vector multiplications, where the nominal matrix size is 256x256. The system clock is 125MHz. At each clock cycle, 128K multiply-and-add operations per second (OPS) are carried out, which yields a peak performance of 16 TeraOPS. IBM Cell Broadband Engine. The Cell processor is the extraordinary resulting product of 5 years of sustained, intensive R&D collaboration (involving over $400M investment) between IBM, Sony, and Toshiba. Its architecture comprises one multithreaded 64-bit PowerPC processor element (PPE) with VMX capabilities and two levels of globally coherent cache, and 8 synergistic processor elements (SPEs). Each SPE consists of a processor (SPU) designed for streaming workloads, local memory, and a globally coherent direct memory access (DMA) engine. Computations are performed in 128-bit wide single instruction multiple data streams (SIMD). An integrated high-bandwidth element interconnect bus (EIB) connects the nine processors and their ports to external memory and to system I/O. The Applied Software Engineering Research (ASER) Group at the ORNL is applying the Cell to a variety of text and image analysis applications. Research on Cell-equipped PlayStation3 (PS3) consoles has led to the development of a correlation-based image recognition engine that enables a single PS3 to process images at more than 10X the speed of state-of-the-art single-core processors. NVIDIA Graphics Processing Units. The ASER group is also employing the latest NVIDIA graphical processing units (GPUs) to accelerate clustering of thousands of text documents using recently developed clustering algorithms such as document flocking and affinity propagation.« less

An efficient HW and SW design of H.264 video compression, storage and playback on FPGA devices for handheld thermal imaging systems

NASA Astrophysics Data System (ADS)

Gunay, Omer; Ozsarac, Ismail; Kamisli, Fatih

2017-05-01

Video recording is an essential property of new generation military imaging systems. Playback of the stored video on the same device is also desirable as it provides several operational benefits to end users. Two very important constraints for many military imaging systems, especially for hand-held devices and thermal weapon sights, are power consumption and size. To meet these constraints, it is essential to perform most of the processing applied to the video signal, such as preprocessing, compression, storing, decoding, playback and other system functions on a single programmable chip, such as FPGA, DSP, GPU or ASIC. In this work, H.264/AVC (Advanced Video Coding) compatible video compression, storage, decoding and playback blocks are efficiently designed and implemented on FPGA platforms using FPGA fabric and Altera NIOS II soft processor. Many subblocks that are used in video encoding are also used during video decoding in order to save FPGA resources and power. Computationally complex blocks are designed using FPGA fabric, while blocks such as SD card write/read, H.264 syntax decoding and CAVLC decoding are done using NIOS processor to benefit from software flexibility. In addition, to keep power consumption low, the system was designed to require limited external memory access. The design was tested using 640x480 25 fps thermal camera on CYCLONE V FPGA, which is the ALTERA's lowest power FPGA family, and consumes lower than 40% of CYCLONE V 5CEFA7 FPGA resources on average.

SpaceCube 2.0: An Advanced Hybrid Onboard Data Processor

NASA Technical Reports Server (NTRS)

Lin, Michael; Flatley, Thomas; Godfrey, John; Geist, Alessandro; Espinosa, Daniel; Petrick, David

2011-01-01

The SpaceCube 2.0 is a compact, high performance, low-power onboard processing system that takes advantage of cutting-edge hybrid (CPU/FPGA/DSP) processing elements. The SpaceCube 2.0 design concept includes two commercial Virtex-5 field-programmable gate array (FPGA) parts protected by gradiation hardened by software" technology, and possesses exceptional size, weight, and power characteristics [5x5x7 in., 3.5 lb (approximately equal to 12.7 x 12.7 x 17.8 cm, 1.6 kg) 5-25 W, depending on the application fs required clock rate]. The two Virtex-5 FPGA parts are implemented in a unique back-toback configuration to maximize data transfer and computing performance. Draft computing power specifications for the SpaceCube 2.0 unit include four PowerPC 440s (1100 DMIPS each), 500+ DSP48Es (2x580 GMACS), 100+ LVDS high-speed serial I/Os (1.25 Gbps each), and 2x190 GFLOPS single-precision (65 GFLOPS double-precision) floating point performance. The SpaceCube 2.0 includes PROM memory for CPU boot, health and safety, and basic command and telemetry functionality; RAM memory for program execution; and FLASH/EEPROM memory to store algorithms and application code for the CPU, FPGA, and DSP processing elements. Program execution can be reconfigured in real time and algorithms can be updated, modified, and/or replaced at any point during the mission. Gigabit Ethernet, Spacewire, SATA and highspeed LVDS serial/parallel I/O channels are available for instrument/sensor data ingest, and mission-unique instrument interfaces can be accommodated using a compact PCI (cPCI) expansion card interface. The SpaceCube 2.0 can be utilized in NASA Earth Science, Helio/Astrophysics and Exploration missions, and Department of Defense satellites for onboard data processing. It can also be used in commercial communication and mapping satellites.

HrpN of Erwinia amylovora functions in the translocation of DspA/E into plant cells.

PubMed

Bocsanczy, Ana M; Nissinen, Riitta M; Oh, Chang-Sik; Beer, Steven V

2008-07-01

The type III secretion system (T3SS) is required by plant pathogenic bacteria for the translocation of certain bacterial proteins to the cytoplasm of plant cells or secretion of some proteins to the apoplast. The T3SS of Erwinia amylovora, which causes fire blight of pear, apple and other rosaceous plants, secretes DspA/E, which is an indispensable pathogenicity factor. Several other proteins, including HrpN, a critical virulence factor, are also secreted by the T3SS. Using a CyaA reporter system, we demonstrated that DspA/E is translocated into the cells of Nicotiana tabacum'Xanthi'. To determine if other T3-secreted proteins are needed for translocation of DspA/E, we examined its translocation in several mutants of E. amylovora strain Ea321. DspA/E was translocated by both hrpW and hrpK mutants, although with some delay, indicating that these two proteins are dispensable in the translocation of DspA/E. Remarkably, translocation of DspA/E was essentially abolished in both hrpN and hrpJ mutants; however, secretion of DspA/E into medium was not affected in any of the mentioned mutants. In contrast to the more virulent strain Ea273, secretion of HrpN was abolished in a hrpJ mutant of strain Ea321. In addition, HrpN was weakly translocated into plant cytoplasm. These results suggest that HrpN plays a significant role in the translocation of DspA/E, and HrpJ affects the translocation of DspA/E by affecting secretion or stability of HrpN. Taken together, these results explain the critical importance of HrpN and HrpJ to the development of fire blight.

Feasibility study of a real-time operating system for a multichannel MPEG-4 encoder

NASA Astrophysics Data System (ADS)

Lehtoranta, Olli; Hamalainen, Timo D.

2005-03-01

Feasibility of DSP/BIOS real-time operating system for a multi-channel MPEG-4 encoder is studied. Performances of two MPEG-4 encoder implementations with and without the operating system are compared in terms of encoding frame rate and memory requirements. The effects of task switching frequency and number of parallel video channels to the encoding frame rate are measured. The research is carried out on a 200 MHz TMS320C6201 fixed point DSP using QCIF (176x144 pixels) video format. Compared to a traditional DSP implementation without an operating system, inclusion of DSP/BIOS reduces total system throughput only by 1 QCIF frames/s. The operating system has 6 KB data memory overhead and program memory requirement of 15.7 KB. Hence, the overhead is considered low enough for resource critical mobile video applications.

Global rotational motion and displacement estimation of digital image stabilization based on the oblique vectors matching algorithm

NASA Astrophysics Data System (ADS)

Yu, Fei; Hui, Mei; Zhao, Yue-jin

2009-08-01

The image block matching algorithm based on motion vectors of correlative pixels in oblique direction is presented for digital image stabilization. The digital image stabilization is a new generation of image stabilization technique which can obtains the information of relative motion among frames of dynamic image sequences by the method of digital image processing. In this method the matching parameters are calculated from the vectors projected in the oblique direction. The matching parameters based on the vectors contain the information of vectors in transverse and vertical direction in the image blocks at the same time. So the better matching information can be obtained after making correlative operation in the oblique direction. And an iterative weighted least square method is used to eliminate the error of block matching. The weights are related with the pixels' rotational angle. The center of rotation and the global emotion estimation of the shaking image can be obtained by the weighted least square from the estimation of each block chosen evenly from the image. Then, the shaking image can be stabilized with the center of rotation and the global emotion estimation. Also, the algorithm can run at real time by the method of simulated annealing in searching method of block matching. An image processing system based on DSP was used to exam this algorithm. The core processor in the DSP system is TMS320C6416 of TI, and the CCD camera with definition of 720×576 pixels was chosen as the input video signal. Experimental results show that the algorithm can be performed at the real time processing system and have an accurate matching precision.

DSP-Based dual-polarity mass spectrum pattern recognition for bio-detection

DOE Office of Scientific and Technical Information (OSTI.GOV)

Riot, V; Coffee, K; Gard, E

2006-04-21

The Bio-Aerosol Mass Spectrometry (BAMS) instrument analyzes single aerosol particles using a dual-polarity time-of-flight mass spectrometer recording simultaneously spectra of thirty to a hundred thousand points on each polarity. We describe here a real-time pattern recognition algorithm developed at Lawrence Livermore National Laboratory that has been implemented on a nine Digital Signal Processor (DSP) system from Signatec Incorporated. The algorithm first preprocesses independently the raw time-of-flight data through an adaptive baseline removal routine. The next step consists of a polarity dependent calibration to a mass-to-charge representation, reducing the data to about five hundred to a thousand channels per polarity. Themore » last step is the identification step using a pattern recognition algorithm based on a library of known particle signatures including threat agents and background particles. The identification step includes integrating the two polarities for a final identification determination using a score-based rule tree. This algorithm, operating on multiple channels per-polarity and multiple polarities, is well suited for parallel real-time processing. It has been implemented on the PMP8A from Signatec Incorporated, which is a computer based board that can interface directly to the two one-Giga-Sample digitizers (PDA1000 from Signatec Incorporated) used to record the two polarities of time-of-flight data. By using optimized data separation, pipelining, and parallel processing across the nine DSPs it is possible to achieve a processing speed of up to a thousand particles per seconds, while maintaining the recognition rate observed on a non-real time implementation. This embedded system has allowed the BAMS technology to improve its throughput and therefore its sensitivity while maintaining a large dynamic range (number of channels and two polarities) thus maintaining the systems specificity for bio-detection.« less

Design, characterization and control of the Unique Mobility Corporation robot

NASA Technical Reports Server (NTRS)

Velasco, Virgilio B., Jr.; Newman, Wyatt S.; Steinetz, Bruce; Kopf, Carlo; Malik, John

1994-01-01

Space and mass are at a premium on any space mission, and thus any machinery designed for space use should be lightweight and compact, without sacrificing strength. It is for this reason that NASA/LeRC contracted Unique Mobility Corporation to exploit their novel actuator designs to build a robot that would advance the present state of technology with respect to these requirements. Custom-designed motors are the key feature of this robot. They are compact, high-performance dc brushless servo motors with a high pole count and low inductance, thus permitting high torque generation and rapid phase commutation. Using a custom-designed digital signal processor-based controller board, the pulse width modulation power amplifiers regulate the fast dynamics of the motor currents. In addition, the programmable digital signal processor (DSP) controller permits implementation of nonlinear compensation algorithms to account for motoring vs. regeneration, torque ripple, and back-EMF. As a result, the motors produce a high torque relative to their size and weight, and can do so with good torque regulation and acceptably high velocity saturation limits. This paper presents the Unique Mobility Corporation robot prototype: its actuators, its kinematic design, its control system, and its experimental characterization. Performance results, including saturation torques, saturation velocities and tracking accuracy tests are included.

Distributed Two-Dimensional Fourier Transforms on DSPs with an Application for Phase Retrieval

NASA Technical Reports Server (NTRS)

Smith, Jeffrey Scott

2006-01-01

Many applications of two-dimensional Fourier Transforms require fixed timing as defined by system specifications. One example is image-based wavefront sensing. The image-based approach has many benefits, yet it is a computational intensive solution for adaptive optic correction, where optical adjustments are made in real-time to correct for external (atmospheric turbulence) and internal (stability) aberrations, which cause image degradation. For phase retrieval, a type of image-based wavefront sensing, numerous two-dimensional Fast Fourier Transforms (FFTs) are used. To meet the required real-time specifications, a distributed system is needed, and thus, the 2-D FFT necessitates an all-to-all communication among the computational nodes. The 1-D floating point FFT is very efficient on a digital signal processor (DSP). For this study, several architectures and analysis of such are presented which address the all-to-all communication with DSPs. Emphasis of this research is on a 64-node cluster of Analog Devices TigerSharc TS-101 DSPs.

An Architecture for Measuring Joint Angles Using a Long Period Fiber Grating-Based Sensor

PubMed Central

Perez-Ramirez, Carlos A.; Almanza-Ojeda, Dora L.; Guerrero-Tavares, Jesus N.; Mendoza-Galindo, Francisco J.; Estudillo-Ayala, Julian M.; Ibarra-Manzano, Mario A.

2014-01-01

The implementation of signal filters in a real-time form requires a tradeoff between computation resources and the system performance. Therefore, taking advantage of low lag response and the reduced consumption of resources, in this article, the Recursive Least Square (RLS) algorithm is used to filter a signal acquired from a fiber-optics-based sensor. In particular, a Long-Period Fiber Grating (LPFG) sensor is used to measure the bending movement of a finger. After that, the Gaussian Mixture Model (GMM) technique allows us to classify the corresponding finger position along the motion range. For these measures to help in the development of an autonomous robotic hand, the proposed technique can be straightforwardly implemented on real time platforms such as Field Programmable Gate Array (FPGA) or Digital Signal Processors (DSP). Different angle measurements of the finger's motion are carried out by the prototype and a detailed analysis of the system performance is presented. PMID:25536002

Secure communication based on spatiotemporal chaos

NASA Astrophysics Data System (ADS)

Ren, Hai-Peng; Bai, Chao

2015-08-01

In this paper, we propose a novel approach to secure communication based on spatiotemporal chaos. At the transmitter end, the state variables of the coupled map lattice system are divided into two groups: one is used as the key to encrypt the plaintext in the N-shift encryption function, and the other is used to mix with the output of the N-shift function to further confuse the information to transmit. At the receiver end, the receiver lattices are driven by the received signal to synchronize with the transmitter lattices and an inverse procedure of the encoding is conducted to decode the information. Numerical simulation and experiment based on the TI TMS320C6713 Digital Signal Processor (DSP) show the feasibility and the validity of the proposed scheme. Project supported by the National Natural Science Foundation of China (Grant No. 61172070) and the Funds from the Science and Technology Innovation Team of Shaanxi Province, China (Grant No. 2013CKT-04).

Moving Object Detection Using Scanning Camera on a High-Precision Intelligent Holder

PubMed Central

Chen, Shuoyang; Xu, Tingfa; Li, Daqun; Zhang, Jizhou; Jiang, Shenwang

2016-01-01

During the process of moving object detection in an intelligent visual surveillance system, a scenario with complex background is sure to appear. The traditional methods, such as “frame difference” and “optical flow”, may not able to deal with the problem very well. In such scenarios, we use a modified algorithm to do the background modeling work. In this paper, we use edge detection to get an edge difference image just to enhance the ability of resistance illumination variation. Then we use a “multi-block temporal-analyzing LBP (Local Binary Pattern)” algorithm to do the segmentation. In the end, a connected component is used to locate the object. We also produce a hardware platform, the core of which consists of the DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) platforms and the high-precision intelligent holder. PMID:27775671

Noninvasive Ocular Drug Delivery System of Dexamethasone Sodium Phosphate in the Treatment of Experimental Uveitis Rabbit.

PubMed

Papangkorn, Kongnara; Prendergast, Eri; Higuchi, John W; Brar, Balbir; Higuchi, William I

2017-12-01

To investigate the efficacy and safety of dexamethasone sodium phosphate administered through Visulex system (DSP-Visulex) in treating experimental uveitis. Uveitis was induced in rabbits by subcutaneous injections of complete Freund's adjuvant and an intravitreal injection of H37RA antigen. After induction, the animals of the control group received no treatment and the others received various treatment regimens of DSP-Visulex. Each regimen was different in DSP strength (4%, 8%, and 15%), application time, or treatment frequency. Efficacy and safety of DSP-Visulex were evaluated by ophthalmic observations and histopathological examinations for ocular inflammations and pathology. The control group exhibited panuveitis with significant inflammation in the vitreous, choroid, and retina, but less in the conjunctiva, cornea, and anterior chamber. The uveitis occurred within 24 h after induction and persisted throughout the study in the control group. All treatments showed some reduction in inflammation in the vitreous, choroid, and retina. The higher dose regimens generally showed more rapid and higher degree of resolution than the lower dose regimens. The posterior eye tissues of the 15% and 8% DSP-Visulex appeared normal with minimal or no inflammation, whereas the untreated eye and the 4% DSP-Visulex eyes showed minimal response. All DSP-Visulex regimens suppressed the signs of inflammation and were well tolerated over the course of a 29-day study. The 8% and 15% DSP-Visulex treatment regimens were safe and efficacious for anterior, intermediate, and posterior uveitis. On the other hand, the 4% DSP-Visulex regimen may only be considered for anterior and intermediate uveitis.

Homology-based modeling of the Erwinia amylovora type III secretion chaperone DspF used to identify amino acids required for virulence and interaction with the effector DspE.

PubMed

Triplett, Lindsay R; Wedemeyer, William J; Sundin, George W

2010-09-01

The structure of DspF, a type III secretion system (T3SS) chaperone required for virulence of the fruit tree pathogen Erwinia amylovora, was modeled based on predicted structural homology to characterized T3SS chaperones. This model guided the selection of 11 amino acid residues that were individually mutated to alanine via site-directed mutagenesis. Each mutant was assessed for its effect on virulence complementation, dimerization and interaction with the N-terminal chaperone-binding site of DspE. Four amino acid residues were identified that did not complement the virulence defect of a dspF knockout mutant, and three of these residues were required for interaction with the N-terminus of DspE. This study supports the significance of the predicted beta-sheet helix-binding groove in DspF chaperone function. Copyright 2010 Elsevier Masson SAS. All rights reserved.

Analysis and simulation tools for solar array power systems

NASA Astrophysics Data System (ADS)

Pongratananukul, Nattorn

This dissertation presents simulation tools developed specifically for the design of solar array power systems. Contributions are made in several aspects of the system design phases, including solar source modeling, system simulation, and controller verification. A tool to automate the study of solar array configurations using general purpose circuit simulators has been developed based on the modeling of individual solar cells. Hierarchical structure of solar cell elements, including semiconductor properties, allows simulation of electrical properties as well as the evaluation of the impact of environmental conditions. A second developed tool provides a co-simulation platform with the capability to verify the performance of an actual digital controller implemented in programmable hardware such as a DSP processor, while the entire solar array including the DC-DC power converter is modeled in software algorithms running on a computer. This "virtual plant" allows developing and debugging code for the digital controller, and also to improve the control algorithm. One important task in solar arrays is to track the maximum power point on the array in order to maximize the power that can be delivered. Digital controllers implemented with programmable processors are particularly attractive for this task because sophisticated tracking algorithms can be implemented and revised when needed to optimize their performance. The proposed co-simulation tools are thus very valuable in developing and optimizing the control algorithm, before the system is built. Examples that demonstrate the effectiveness of the proposed methodologies are presented. The proposed simulation tools are also valuable in the design of multi-channel arrays. In the specific system that we have designed and tested, the control algorithm is implemented on a single digital signal processor. In each of the channels the maximum power point is tracked individually. In the prototype we built, off-the-shelf commercial DC-DC converters were utilized. At the end, the overall performance of the entire system was evaluated using solar array simulators capable of simulating various I-V characteristics, and also by using an electronic load. Experimental results are presented.

The Results of Complex Research of GSS "SBIRS-Geo 2" Behavior in the Orbit

NASA Astrophysics Data System (ADS)

Sukhov, P. P.; Epishev, V. P.; Sukhov, K. P.; Karpenko, G. F.; Motrunich, I. I.

2017-04-01

The new generation of geosynchronous satellites SBIRS of US Air Force early warning system series (Satellite Early Warning System) replaced the previous DSP-satellite series (Defense Support Program). Currently from the territory of Ukraine, several GSS of DSP series and one "SBIRS-Geo 2" are available to observation. During two years of observations, we have received and analyzed for two satellites more than 30 light curves in B, V, R photometric system. As a result of complex research, we propose a model of "SBIRS-Geo" 2 orbital behavior compared with the same one of the DSP-satellite. To control the entire surface of the Earth with 15-16 sec interval, including the polar regions, 4 SBIRS satellites located every 90 deg. along the equator are enough in GEO orbit. Since DSP-satellites provide the coverage of the Earth's surface to 83 deg. latitudes with a period of 50 sec, DSP-satellites should be 8. All the conclusions were made based on an analysis of photometric and coordinate observations using the simulation of the dynamics of their orbital behavior.

Flexible Peripheral Component Interconnect Input/Output Card

NASA Technical Reports Server (NTRS)

Bigelow, Kirk K.; Jerry, Albert L.; Baricio, Alisha G.; Cummings, Jon K.

2010-01-01

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Development of a material processing plant for lunar soil

NASA Technical Reports Server (NTRS)

Goettsch, Ulix; Ousterhout, Karl

1992-01-01

Currently there is considerable interest in developing in-situ materials processing plants for both the Moon and Mars. Two of the most important aspects of developing such a materials processing plant is the overall system design and the integration of the different technologies into a reliable, lightweight, and cost-effective unit. The concept of an autonomous materials processing plant that is capable of producing useful substances from lunar regolith was developed. In order for such a materials processing plant to be considered as a viable option, it must be totally self-contained, able to operate autonomously, cost effective, light weight, and fault tolerant. In order to assess the impact of different technologies on the overall systems design and integration, a one-half scale model was constructed that is capable of scooping up (or digging) lunar soil, transferring the soil to a solar furnace, heating the soil in the furnace to liberate the gasses, and transferring the spent soil to a 'tile' processing center. All aspects of the control system are handled by a 386 class PC via D/A, A/D, and DSP (Digital Signal Processor) control cards.

CMOS Image Sensor with a Built-in Lane Detector.

PubMed

Hsiao, Pei-Yung; Cheng, Hsien-Chein; Huang, Shih-Shinh; Fu, Li-Chen

2009-01-01

This work develops a new current-mode mixed signal Complementary Metal-Oxide-Semiconductor (CMOS) imager, which can capture images and simultaneously produce vehicle lane maps. The adopted lane detection algorithm, which was modified to be compatible with hardware requirements, can achieve a high recognition rate of up to approximately 96% under various weather conditions. Instead of a Personal Computer (PC) based system or embedded platform system equipped with expensive high performance chip of Reduced Instruction Set Computer (RISC) or Digital Signal Processor (DSP), the proposed imager, without extra Analog to Digital Converter (ADC) circuits to transform signals, is a compact, lower cost key-component chip. It is also an innovative component device that can be integrated into intelligent automotive lane departure systems. The chip size is 2,191.4 × 2,389.8 μm, and the package uses 40 pin Dual-In-Package (DIP). The pixel cell size is 18.45 × 21.8 μm and the core size of photodiode is 12.45 × 9.6 μm; the resulting fill factor is 29.7%.

Flexible communications for battlespace 2000

NASA Astrophysics Data System (ADS)

Seiler, Thomas M.

2000-08-01

The advent of software-defined radios (products of DSP) with embedded processors capable of performing, communications functions (i.e., modulation) makes it possible for networks of radios to operate efficiently by changing its transmission characteristics (waveform) to fit the input data bandwidth requirements commensurate with received Eb/N0. It is also now feasible to have embedded within the network of radios a networking system capable of allocating bandwidth in accordance with current needs and priorities. The subject of battlefield networking can now also be addressed. A system with the multiple degrees of freedom (e.g., ability to manually and automatically change communications parameters to improve communications performance, spectrum management and the ability to incorporate different mission processing support) will provide the warfighter, those who support the warfighter and the rapidly expanding mission of our armed forces (i.e., peacekeeping, anti-terrorism) to meet an ever-changing mission and operational environment. This paper will address how such a robust communications system will enhance the mission of the specialist and make the products of his efforts a real-time tool for the shooter who must operate within the digitized battlespace.

What does voice-processing technology support today?

PubMed Central

Nakatsu, R; Suzuki, Y

1995-01-01

This paper describes the state of the art in applications of voice-processing technologies. In the first part, technologies concerning the implementation of speech recognition and synthesis algorithms are described. Hardware technologies such as microprocessors and DSPs (digital signal processors) are discussed. Software development environment, which is a key technology in developing applications software, ranging from DSP software to support software also is described. In the second part, the state of the art of algorithms from the standpoint of applications is discussed. Several issues concerning evaluation of speech recognition/synthesis algorithms are covered, as well as issues concerning the robustness of algorithms in adverse conditions. Images Fig. 3 PMID:7479720

DSPACE hardware architecture for on-board real-time image/video processing in European space missions

NASA Astrophysics Data System (ADS)

Saponara, Sergio; Donati, Massimiliano; Fanucci, Luca; Odendahl, Maximilian; Leupers, Reiner; Errico, Walter

2013-02-01

The on-board data processing is a vital task for any satellite and spacecraft due to the importance of elaborate the sensing data before sending them to the Earth, in order to exploit effectively the bandwidth to the ground station. In the last years the amount of sensing data collected by scientific and commercial space missions has increased significantly, while the available downlink bandwidth is comparatively stable. The increasing demand of on-board real-time processing capabilities represents one of the critical issues in forthcoming European missions. Faster and faster signal and image processing algorithms are required to accomplish planetary observation, surveillance, Synthetic Aperture Radar imaging and telecommunications. The only available space-qualified Digital Signal Processor (DSP) free of International Traffic in Arms Regulations (ITAR) restrictions faces inadequate performance, thus the development of a next generation European DSP is well known to the space community. The DSPACE space-qualified DSP architecture fills the gap between the computational requirements and the available devices. It leverages a pipelined and massively parallel core based on the Very Long Instruction Word (VLIW) paradigm, with 64 registers and 8 operational units, along with cache memories, memory controllers and SpaceWire interfaces. Both the synthesizable VHDL and the software development tools are generated from the LISA high-level model. A Xilinx-XC7K325T FPGA is chosen to realize a compact PCI demonstrator board. Finally first synthesis results on CMOS standard cell technology (ASIC 180 nm) show an area of around 380 kgates and a peak performance of 1000 MIPS and 750 MFLOPS at 125MHz.

Development of a rapid cell-fusion-based phenotypic HIV-1 tropism assay

PubMed Central

Teeranaipong, Phairote; Hosoya, Noriaki; Kawana-Tachikawa, Ai; Fujii, Takeshi; Koibuchi, Tomohiko; Nakamura, Hitomi; Koga, Michiko; Kondo, Naoyuki; Gao, George F; Hoshino, Hiroo; Matsuda, Zene; Iwamoto, Aikichi

2013-01-01

Introduction A dual split reporter protein system (DSP), recombining Renilla luciferase (RL) and green fluorescent protein (GFP) split into two different constructs (DSP1–7 and DSP8–11), was adapted to create a novel rapid phenotypic tropism assay (PTA) for HIV-1 infection (DSP-Pheno). Methods DSP1–7 was stably expressed in the glioma-derived NP-2 cell lines, which expressed CD4/CXCR4 (N4X4) or CD4/CCR5 (N4R5), respectively. An expression vector with DSP8–11 (pRE11) was constructed. The HIV-1 envelope genes were subcloned in pRE11 (pRE11-env) and transfected into 293FT cells. Transfected 293FT cells were incubated with the indicator cell lines independently. In developing the assay, we selected the DSP1–7-positive clones that showed the highest GFP activity after complementation with DSP8–11. These cell lines, designated N4R5-DSP1–7, N4X4-DSP1–7 were used for subsequent assays. Results The env gene from the reference strains (BaL for R5 virus, NL4-3 for X4 virus, SF2 for dual tropic virus) subcloned in pRE11 and tested, was concordant with the expected co-receptor usage. Assay results were available in two ways (RL or GFP). The assay sensitivity by RL activity was comparable with those of the published phenotypic assays using pseudovirus. The shortest turnaround time was 5 days after obtaining the patient's plasma. All clinical samples gave positive RL signals on R5 indicator cells in the fusion assay. Median RLU value of the low CD4 group was significantly higher on X4 indicator cells and suggested the presence of more dual or X4 tropic viruses in this group of patients. Comparison of representative samples with Geno2Pheno [co-receptor] assay was concordant. Conclusions A new cell-fusion-based, high-throughput PTA for HIV-1, which would be suitable for in-house studies, was developed. Equipped with two-way reporter system, RL and GFP, DSP-Pheno is a sensitive test with short turnaround time. Although maintenance of cell lines and laboratory equipment is necessary, it provides a safe assay system without infectious viruses. With further validation against other conventional analyses, DSP-Pheno may prove to be a useful laboratory tool. The assay may be useful especially for the research on non-B subtype HIV-1 whose co-receptor usage has not been studied much. PMID:24050252

The Efficiency of Dentin Sialoprotein-Phosphophoryn Processing Is Affected by Mutations Both Flanking and Distant from the Cleavage Site*

PubMed Central

Yang, Robert T.; Lim, Glendale L.; Dong, Zhihong; Lee, Arthur M.; Yee, Colin T.; Fuller, Robert S.; Ritchie, Helena H.

2013-01-01

Normal dentin mineralization requires two highly acidic proteins, dentin sialoprotein (DSP) and phosphophoryn (PP). DSP and PP are synthesized as part of a single secreted precursor, DSP-PP, which is conserved in marsupial and placental mammals. Using a baculovirus expression system, we previously found that DSP-PP is accurately cleaved into DSP and PP after secretion into medium by an endogenous, secreted, zinc-dependent Sf9 cell activity. Here we report that mutation of conserved residues near and distant from the G447↓D448 cleavage site in DSP-PP240 had dramatic effects on cleavage efficiency by the endogenous Sf9 cell processing enzyme. We found that: 1) mutation of residues flanking the cleavage site from P4 to P4′ blocked, impaired, or enhanced DSP-PP240 cleavage; 2) certain conserved amino acids distant from the cleavage site were important for precursor cleavage; 3) modification of the C terminus by appending a C-terminal tag altered the pattern of processing; and 4) mutations in DSP-PP240 had similar effects on cleavage by recombinant human BMP1, a candidate physiological processing enzyme, as was seen with the endogenous Sf9 cell activity. An analysis of a partial TLR1 cDNA from Sf9 cells indicates that residues that line the substrate-binding cleft of Sf9 TLR1 and human BMP1 are nearly perfectly conserved, offering an explanation of why Sf9 cells so accurately process mammalian DSP-PP. The fact that several mutations in DSP-PP240 significantly modified the amount of PP240 product generated from DSP-PP240 precursor protein cleavage suggests that such mutation may affect the mineralization process. PMID:23297400

The efficiency of dentin sialoprotein-phosphophoryn processing is affected by mutations both flanking and distant from the cleavage site.

PubMed

Yang, Robert T; Lim, Glendale L; Dong, Zhihong; Lee, Arthur M; Yee, Colin T; Fuller, Robert S; Ritchie, Helena H

2013-02-22

Normal dentin mineralization requires two highly acidic proteins, dentin sialoprotein (DSP) and phosphophoryn (PP). DSP and PP are synthesized as part of a single secreted precursor, DSP-PP, which is conserved in marsupial and placental mammals. Using a baculovirus expression system, we previously found that DSP-PP is accurately cleaved into DSP and PP after secretion into medium by an endogenous, secreted, zinc-dependent Sf9 cell activity. Here we report that mutation of conserved residues near and distant from the G(447)↓D(448) cleavage site in DSP-PP(240) had dramatic effects on cleavage efficiency by the endogenous Sf9 cell processing enzyme. We found that: 1) mutation of residues flanking the cleavage site from P(4) to P(4)' blocked, impaired, or enhanced DSP-PP(240) cleavage; 2) certain conserved amino acids distant from the cleavage site were important for precursor cleavage; 3) modification of the C terminus by appending a C-terminal tag altered the pattern of processing; and 4) mutations in DSP-PP(240) had similar effects on cleavage by recombinant human BMP1, a candidate physiological processing enzyme, as was seen with the endogenous Sf9 cell activity. An analysis of a partial TLR1 cDNA from Sf9 cells indicates that residues that line the substrate-binding cleft of Sf9 TLR1 and human BMP1 are nearly perfectly conserved, offering an explanation of why Sf9 cells so accurately process mammalian DSP-PP. The fact that several mutations in DSP-PP(240) significantly modified the amount of PP(240) product generated from DSP-PP(240) precursor protein cleavage suggests that such mutation may affect the mineralization process.

Fast Fourier Transform Co-Processor (FFTC)- Towards Embedded GFLOPs

NASA Astrophysics Data System (ADS)

Kuehl, Christopher; Liebstueckel, Uwe; Tejerina, Isaac; Uemminghaus, Michael; Wite, Felix; Kolb, Michael; Suess, Martin; Weigand, Roland

2012-08-01

Many signal processing applications and algorithms perform their operations on the data in the transform domain to gain efficiency. The Fourier Transform Co- Processor has been developed with the aim to offload General Purpose Processors from performing these transformations and therefore to boast the overall performance of a processing module. The IP of the commercial PowerFFT processor has been selected and adapted to meet the constraints of the space environment.In frame of the ESA activity “Fast Fourier Transform DSP Co-processor (FFTC)” (ESTEC/Contract No. 15314/07/NL/LvH/ma) the objectives were the following:Production of prototypes of a space qualified version of the commercial PowerFFT chip called FFTC based on the PowerFFT IP.The development of a stand-alone FFTC Accelerator Board (FTAB) based on the FFTC including the Controller FPGA and SpaceWire Interfaces to verify the FFTC function and performance.The FFTC chip performs its calculations with floating point precision. Stand alone it is capable computing FFTs of up to 1K complex samples in length in only 10μsec. This corresponds to an equivalent processing performance of 4.7 GFlops. In this mode the maximum sustained data throughput reaches 6.4Gbit/s. When connected to up to 4 EDAC protected SDRAM memory banks the FFTC can perform long FFTs with up to 1M complex samples in length or multidimensional FFT- based processing tasks.A Controller FPGA on the FTAB takes care of the SDRAM addressing. The instructions commanded via the Controller FPGA are used to set up the data flow and generate the memory addresses.The presentation will give and overview on the project, including the results of the validation of the FFTC ASIC prototypes.

Fast Fourier Transform Co-processor (FFTC), towards embedded GFLOPs

NASA Astrophysics Data System (ADS)

Kuehl, Christopher; Liebstueckel, Uwe; Tejerina, Isaac; Uemminghaus, Michael; Witte, Felix; Kolb, Michael; Suess, Martin; Weigand, Roland; Kopp, Nicholas

2012-10-01

Many signal processing applications and algorithms perform their operations on the data in the transform domain to gain efficiency. The Fourier Transform Co-Processor has been developed with the aim to offload General Purpose Processors from performing these transformations and therefore to boast the overall performance of a processing module. The IP of the commercial PowerFFT processor has been selected and adapted to meet the constraints of the space environment. In frame of the ESA activity "Fast Fourier Transform DSP Co-processor (FFTC)" (ESTEC/Contract No. 15314/07/NL/LvH/ma) the objectives were the following: • Production of prototypes of a space qualified version of the commercial PowerFFT chip called FFTC based on the PowerFFT IP. • The development of a stand-alone FFTC Accelerator Board (FTAB) based on the FFTC including the Controller FPGA and SpaceWire Interfaces to verify the FFTC function and performance. The FFTC chip performs its calculations with floating point precision. Stand alone it is capable computing FFTs of up to 1K complex samples in length in only 10μsec. This corresponds to an equivalent processing performance of 4.7 GFlops. In this mode the maximum sustained data throughput reaches 6.4Gbit/s. When connected to up to 4 EDAC protected SDRAM memory banks the FFTC can perform long FFTs with up to 1M complex samples in length or multidimensional FFT-based processing tasks. A Controller FPGA on the FTAB takes care of the SDRAM addressing. The instructions commanded via the Controller FPGA are used to set up the data flow and generate the memory addresses. The paper will give an overview on the project, including the results of the validation of the FFTC ASIC prototypes.

Performance Characteristics and Comparison of Abbott and artus Real-Time Systems for Hepatitis B Virus DNA Quantification ▿

PubMed Central

Ismail, Ashrafali M.; Sivakumar, Jayashree; Anantharam, Raghavendran; Dayalan, Sujitha; Samuel, Prasanna; Fletcher, Gnanadurai J.; Gnanamony, Manu; Abraham, Priya

2011-01-01

Virological monitoring of hepatitis B virus (HBV) DNA is critical to the management of HBV infection. With several HBV DNA quantification assays available, it is important to use the most efficient testing system for virological monitoring. In this study, we evaluated the performance characteristics and comparability of three HBV DNA quantification systems: Abbott HBV real-time PCR (Abbott PCR), artus HBV real-time PCR with QIAamp DNA blood kit purification (artus-DB), and artus HBV real-time PCR with the QIAamp DSP virus kit purification (artus-DSP). The lower limits of detection of these systems were established against the WHO international standards for HBV DNA and were found to be 1.43, 82, and 9 IU/ml, respectively. The intra-assay and interassay coefficients of variation of plasma samples (1 to 6 log10 IU/ml) ranged between 0.05 to 8.34% and 0.16 to 3.48% for the Abbott PCR, 1.53 to 26.85% and 0.50 to 12.89% for artus-DB, and 0.29 to 7.42% and 0.94 to 3.01% for artus-DSP, respectively. Ninety HBV clinical samples were used for comparison of assays, and paired quantitative results showed strong correlation by linear regression analysis (artus-DB with Abbott PCR, r = 0.95; Abbott PCR with artus-DSP, r = 0.97; and artus-DSP with artus-DB, r = 0.94). Bland-Altman analysis showed a good level of agreement for Abbott PCR and artus-DSP, with a mean difference of 0.10 log10 IU/ml and limits of agreement of −0.91 to 1.11 log10 IU/ml. No genotype-specific bias was seen in all three systems for HBV genotypes A, C, and D, which are predominant in this region. This finding illustrates that the Abbott real-time HBV and artus-DSP systems show more comparable performance than the artus-DB system, meeting the current guidelines for assays to be used in the management of hepatitis B. PMID:21795507

Performance characteristics and comparison of Abbott and artus real-time systems for hepatitis B virus DNA quantification.

PubMed

Ismail, Ashrafali M; Sivakumar, Jayashree; Anantharam, Raghavendran; Dayalan, Sujitha; Samuel, Prasanna; Fletcher, Gnanadurai J; Gnanamony, Manu; Abraham, Priya

2011-09-01

Virological monitoring of hepatitis B virus (HBV) DNA is critical to the management of HBV infection. With several HBV DNA quantification assays available, it is important to use the most efficient testing system for virological monitoring. In this study, we evaluated the performance characteristics and comparability of three HBV DNA quantification systems: Abbott HBV real-time PCR (Abbott PCR), artus HBV real-time PCR with QIAamp DNA blood kit purification (artus-DB), and artus HBV real-time PCR with the QIAamp DSP virus kit purification (artus-DSP). The lower limits of detection of these systems were established against the WHO international standards for HBV DNA and were found to be 1.43, 82, and 9 IU/ml, respectively. The intra-assay and interassay coefficients of variation of plasma samples (1 to 6 log(10) IU/ml) ranged between 0.05 to 8.34% and 0.16 to 3.48% for the Abbott PCR, 1.53 to 26.85% and 0.50 to 12.89% for artus-DB, and 0.29 to 7.42% and 0.94 to 3.01% for artus-DSP, respectively. Ninety HBV clinical samples were used for comparison of assays, and paired quantitative results showed strong correlation by linear regression analysis (artus-DB with Abbott PCR, r = 0.95; Abbott PCR with artus-DSP, r = 0.97; and artus-DSP with artus-DB, r = 0.94). Bland-Altman analysis showed a good level of agreement for Abbott PCR and artus-DSP, with a mean difference of 0.10 log(10) IU/ml and limits of agreement of -0.91 to 1.11 log(10) IU/ml. No genotype-specific bias was seen in all three systems for HBV genotypes A, C, and D, which are predominant in this region. This finding illustrates that the Abbott real-time HBV and artus-DSP systems show more comparable performance than the artus-DB system, meeting the current guidelines for assays to be used in the management of hepatitis B.

Compact VLSI neural computer integrated with active pixel sensor for real-time ATR applications

NASA Astrophysics Data System (ADS)

Fang, Wai-Chi; Udomkesmalee, Gabriel; Alkalai, Leon

1997-04-01

A compact VLSI neural computer integrated with an active pixel sensor has been under development to mimic what is inherent in biological vision systems. This electronic eye- brain computer is targeted for real-time machine vision applications which require both high-bandwidth communication and high-performance computing for data sensing, synergy of multiple types of sensory information, feature extraction, target detection, target recognition, and control functions. The neural computer is based on a composite structure which combines Annealing Cellular Neural Network (ACNN) and Hierarchical Self-Organization Neural Network (HSONN). The ACNN architecture is a programmable and scalable multi- dimensional array of annealing neurons which are locally connected with their local neurons. Meanwhile, the HSONN adopts a hierarchical structure with nonlinear basis functions. The ACNN+HSONN neural computer is effectively designed to perform programmable functions for machine vision processing in all levels with its embedded host processor. It provides a two order-of-magnitude increase in computation power over the state-of-the-art microcomputer and DSP microelectronics. A compact current-mode VLSI design feasibility of the ACNN+HSONN neural computer is demonstrated by a 3D 16X8X9-cube neural processor chip design in a 2-micrometers CMOS technology. Integration of this neural computer as one slice of a 4'X4' multichip module into the 3D MCM based avionics architecture for NASA's New Millennium Program is also described.

Depletion of norepinephrine of the central nervous system Down-regulates the blood glucose level in d-glucose-fed and restraint stress models.

PubMed

Park, Soo-Hyun; Kim, Sung-Su; Lee, Jae-Ryeong; Sharma, Naveen; Suh, Hong-Won

2016-05-04

DSP-4[N-(2-chloroethyl)-N-ethyl-2-bromobenzylamine hydrochloride] is a neurotoxin that depletes norepinephrine. The catecholaminergic system has been implicated in the regulation of blood glucose level. In the present study, the effect of DSP-4 administered intracerebroventricularly (i.c.v.) or intrathecally (i.t.) on blood glucose level was examined in d-glucose-fed and restraint stress mice models. Mice were pretreated once i.c.v. or i.t. with DSP-4 (10-40μg) for 3days, and d-glucose (2g/kg) was fed orally. Blood glucose level was measured 0 (prior to glucose feeding or restraint stress), 30, 60, and 120min after d-glucose feeding or restraint stress. The i.c.v. or i.t. pretreatment with DSP-4 attenuated blood glucose level in the d-glucose-fed model. Plasma corticosterone level was downregulated in the d-glucose-fed model, whereas plasma insulin level increased in the d-glucose-fed group. The i.c.v. or i.t. pretreatment with DSP-4 reversed the downregulation of plasma corticosterone induced by feeding d-glucose. In addition, the d-glucose-induced increase in plasma insulin was attenuated by the DSP-4 pretreatment. Furthermore, i.c.v. or i.t. pretreatment with DSP-4 reduced restraint stress-induced increases in blood glucose levels. Restraint stress increased plasma corticosterone and insulin levels. The i.c.v. pretreatment with DSP-4 attenuated restraint stress-induced plasma corticosterone and insulin levels. Our results suggest that depleting norepinephrine at the supraspinal and spinal levels appears to be responsible for downregulating blood glucose levels in both d-glucose-fed and restraint stress models. Copyright © 2016 Elsevier Ireland Ltd. All rights reserved.

Preface

NASA Astrophysics Data System (ADS)

Zhuge, Qunbi; Chen, Xi

2018-02-01

Global IP traffic is predicted to increase nearly threefold over the next 5 years, driven by emerging high-bandwidth-demanding applications, such as cloud computing, 5G wireless, high-definition video streaming, and virtual reality. This results in a continuously increasing demand on the capacity of backbone optical networks. During the past decade, advanced digital signal processing (DSP), modulation formats, and forward error correction (FEC) were commercially realized to exploit the capacity potential of long-haul fiber channels, and have increased per channel data rate from 10 Gb/s to 400 Gb/s. DSP has played a crucial role in coherent transceivers to accommodate channel impairments including chromatic dispersion (CD), polarization mode dispersion (PMD), laser phase noise, fiber nonlinearities, clock jitter, and so forth. The advance of DSP has also enabled innovations in modulation formats to increase spectral efficiency, improve linear/nonlinear noise tolerance, and realize flexible bandwidth. Moving forward to next generation 1 Tb/s systems on conventional single mode fiber (SMF) platform, more innovations in DSP techniques are needed to further reduce cost per bit, increase network efficiency, and close the gap to the Shannon limit. To further increase capacity per fiber, spatial-division multiplexing (SDM) systems can be used. DSP techniques such as advanced channel equalization methods and distortion compensation can help SDM systems to achieve higher system capacity. In the area of short-reach transmission, the rapid increase of data center network traffic has driven the development of optical technologies for both intra- and inter-data center interconnects (DCI). In particular, DSP has been exploited in intensity-modulation direct detection (IM/DD) systems to realize 400 Gb/s pluggable optical transceivers. In addition, multi-dimensional direct detection modulation schemes are being investigated to increase the data rate per wavelength targeting 1 Tb/s interface.

Regulation of Effector Delivery by Type III Secretion Chaperone Proteins in Erwinia amylovora.

PubMed

Castiblanco, Luisa F; Triplett, Lindsay R; Sundin, George W

2018-01-01

Type III secretion (TTS) chaperones are critical for the delivery of many effector proteins from Gram-negative bacterial pathogens into host cells, functioning in the stabilization and hierarchical delivery of the effectors to the type III secretion system (TTSS). The plant pathogen Erwinia amylovora secretes at least four TTS effector proteins: DspE, Eop1, Eop3, and Eop4. DspE specifically interacts with the TTS chaperone protein DspF, which stabilizes the effector protein in the cytoplasm and promotes its efficient translocation through the TTSS. However, the role of E. amylovora chaperones in regulating the delivery of other secreted effectors is unknown. In this study, we identified functional interactions between the effector proteins DspE, Eop1, and Eop3 with the TTS chaperones DspF, Esc1 and Esc3 in yeast. Using site-directed mutagenesis, secretion, and translocation assays, we demonstrated that the three TTS chaperones have additive roles for the secretion and translocation of DspE into plant cells whereas DspF negatively affects the translocation of Eop1 and Eop3. Collectively, these results indicate that TTS chaperone proteins exhibit a cooperative behavior to orchestrate the effector secretion and translocation dynamics in E. amylovora .

High-speed parallel implementation of a modified PBR algorithm on DSP-based EH topology

NASA Astrophysics Data System (ADS)

Rajan, K.; Patnaik, L. M.; Ramakrishna, J.

1997-08-01

Algebraic Reconstruction Technique (ART) is an age-old method used for solving the problem of three-dimensional (3-D) reconstruction from projections in electron microscopy and radiology. In medical applications, direct 3-D reconstruction is at the forefront of investigation. The simultaneous iterative reconstruction technique (SIRT) is an ART-type algorithm with the potential of generating in a few iterations tomographic images of a quality comparable to that of convolution backprojection (CBP) methods. Pixel-based reconstruction (PBR) is similar to SIRT reconstruction, and it has been shown that PBR algorithms give better quality pictures compared to those produced by SIRT algorithms. In this work, we propose a few modifications to the PBR algorithms. The modified algorithms are shown to give better quality pictures compared to PBR algorithms. The PBR algorithm and the modified PBR algorithms are highly compute intensive, Not many attempts have been made to reconstruct objects in the true 3-D sense because of the high computational overhead. In this study, we have developed parallel two-dimensional (2-D) and 3-D reconstruction algorithms based on modified PBR. We attempt to solve the two problems encountered by the PBR and modified PBR algorithms, i.e., the long computational time and the large memory requirements, by parallelizing the algorithm on a multiprocessor system. We investigate the possible task and data partitioning schemes by exploiting the potential parallelism in the PBR algorithm subject to minimizing the memory requirement. We have implemented an extended hypercube (EH) architecture for the high-speed execution of the 3-D reconstruction algorithm using the commercially available fast floating point digital signal processor (DSP) chips as the processing elements (PEs) and dual-port random access memories (DPR) as channels between the PEs. We discuss and compare the performances of the PBR algorithm on an IBM 6000 RISC workstation, on a Silicon Graphics Indigo 2 workstation, and on an EH system. The results show that an EH(3,1) using DSP chips as PEs executes the modified PBR algorithm about 100 times faster than an LBM 6000 RISC workstation. We have executed the algorithms on a 4-node IBM SP2 parallel computer. The results show that execution time of the algorithm on an EH(3,1) is better than that of a 4-node IBM SP2 system. The speed-up of an EH(3,1) system with eight PEs and one network controller is approximately 7.85.

STS-44 DSP satellite and IUS during preflight processing at Cape Canaveral

NASA Image and Video Library

1991-10-19

S91-50773 (19 Oct 1991) --- At a processing facility on Cape Canaveral Air Force Station, the Defense Support Program (DSP) satellite is being transferred into the payload canister transporter for shipment to Launch Pad 39A at KSC. The DSP will be deployed during Space Shuttle Mission STS-44 later this year. It is a surveillance satellite, developed for the Department of Defense, which can detect missile and space launches, as well as nuclear detonations. The Inertial Upper Stage which will boost the DSP satellite to its proper orbital position is the lower portion of the payload. DSP satellites have comprised the spaceborne segment of NORAD's (North American Air Defense Command) Tactical Warning and Attack Assessment System since 1970. STS- 44, carrying a crew of six, will be a ten-day flight.

Expression of the bacterial type III effector DspA/E in Saccharomyces cerevisiae down-regulates the sphingolipid biosynthetic pathway leading to growth arrest.

PubMed

Siamer, Sabrina; Guillas, Isabelle; Shimobayashi, Mitsugu; Kunz, Caroline; Hall, Michael N; Barny, Marie-Anne

2014-06-27

Erwinia amylovora, the bacterium responsible for fire blight, relies on a type III secretion system and a single injected effector, DspA/E, to induce disease in host plants. DspA/E belongs to the widespread AvrE family of type III effectors that suppress plant defense responses and promote bacterial growth following infection. Ectopic expression of DspA/E in plant or in Saccharomyces cerevisiae is toxic, indicating that DspA/E likely targets a cellular process conserved between yeast and plant. To unravel the mode of action of DspA/E, we screened the Euroscarf S. cerevisiae library for mutants resistant to DspA/E-induced growth arrest. The most resistant mutants (Δsur4, Δfen1, Δipt1, Δskn1, Δcsg1, Δcsg2, Δorm1, and Δorm2) were impaired in the sphingolipid biosynthetic pathway. Exogenously supplied sphingolipid precursors such as the long chain bases (LCBs) phytosphingosine and dihydrosphingosine also suppressed the DspA/E-induced yeast growth defect. Expression of DspA/E in yeast down-regulated LCB biosynthesis and induced a rapid decrease in LCB levels, indicating that serine palmitoyltransferase (SPT), the first and rate-limiting enzyme of the sphingolipid biosynthetic pathway, was repressed. SPT down-regulation was mediated by dephosphorylation and activation of Orm proteins that negatively regulate SPT. A Δcdc55 mutation affecting Cdc55-PP2A protein phosphatase activity prevented Orm dephosphorylation and suppressed DspA/E-induced growth arrest. © 2014 by The American Society for Biochemistry and Molecular Biology, Inc.

Sensored Field Oriented Control of a Robust Induction Motor Drive Using a Novel Boundary Layer Fuzzy Controller

PubMed Central

Saghafinia, Ali; Ping, Hew Wooi; Uddin, Mohammad Nasir

2013-01-01

Physical sensors have a key role in implementation of real-time vector control for an induction motor (IM) drive. This paper presents a novel boundary layer fuzzy controller (NBLFC) based on the boundary layer approach for speed control of an indirect field-oriented control (IFOC) of an induction motor (IM) drive using physical sensors. The boundary layer approach leads to a trade-off between control performances and chattering elimination. For the NBLFC, a fuzzy system is used to adjust the boundary layer thickness to improve the tracking performance and eliminate the chattering problem under small uncertainties. Also, to eliminate the chattering under the possibility of large uncertainties, the integral filter is proposed inside the variable boundary layer. In addition, the stability of the system is analyzed through the Lyapunov stability theorem. The proposed NBLFC based IM drive is implemented in real-time using digital signal processor (DSP) board TI TMS320F28335. The experimental and simulation results show the effectiveness of the proposed NBLFC based IM drive at different operating conditions.

A digitally implemented preambleless demodulator for maritime and mobile data communications

NASA Astrophysics Data System (ADS)

Chalmers, Harvey; Shenoy, Ajit; Verahrami, Farhad B.

The hardware design and software algorithms for a low-bit-rate, low-cost, all-digital preambleless demodulator are described. The demodulator operates under severe high-noise conditions, fast Doppler frequency shifts, large frequency offsets, and multipath fading. Sophisticated algorithms, including a fast Fourier transform (FFT)-based burst acquisition algorithm, a cycle-slip resistant carrier phase tracker, an innovative Doppler tracker, and a fast acquisition symbol synchronizer, were developed and extensively simulated for reliable burst reception. The compact digital signal processor (DSP)-based demodulator hardware uses a unique personal computer test interface for downloading test data files. The demodulator test results demonstrate a near-ideal performance within 0.2 dB of theory.

UWB radar technique for arc detection in coaxial cables

NASA Astrophysics Data System (ADS)

Salvador, Sara; Maggiora, Riccardo

2010-11-01

UWB signals constituted by a sequence of chips (properly chosen to reduce side lobes and to improve detection accuracy) are transmitted along the transmission lines at a specified Pulse Repetition Frequency (PRF) and their echoes are received by means of directional couplers. The core of the receiver is an ultra high-speed correlator implemented in a Digital Signal Processor (DSP). When a target (arc) is detected, its position and its ``radar cross section'' are calculated to be able to provide the arc position along the transmission line and to be able to classify the type of detected arc. The ``background scattering'' is routinely extracted from the received signal at any pulse. This permits to be resilient to the background structure of transmission lines (bends, junctions, windows, etc.). Thanks to the localization feature, segmentation is also possible for creating sensed and non- sensed zones (for example, to be insensitive to antenna load variations). A complete test bed has been installed using standard coaxial cables (RG58) to demonstrate the system capabilities.

Automated digital magnetofluidics

NASA Astrophysics Data System (ADS)

Schneider, J.; Garcia, A. A.; Marquez, M.

2008-08-01

Drops can be moved in complex patterns on superhydrophobic surfaces using a reconfigured computer-controlled x-y metrology stage with a high degree of accuracy, flexibility, and reconfigurability. The stage employs a DMC-4030 controller which has a RISC-based, clock multiplying processor with DSP functions, accepting encoder inputs up to 22 MHz, provides servo update rates as high as 32 kHz, and processes commands at rates as fast as 40 milliseconds. A 6.35 mm diameter cylindrical NdFeB magnet is translated by the stage causing water drops to move by the action of induced magnetization of coated iron microspheres that remain in the drop and are attracted to the rare earth magnet through digital magnetofluidics. Water drops are easily moved in complex patterns in automated digital magnetofluidics at an average speed of 2.8 cm/s over a superhydrophobic polyethylene surface created by solvent casting. With additional components, some potential uses for this automated microfluidic system include characterization of superhydrophobic surfaces, water quality analysis, and medical diagnostics.

Suicide rates in China, 2004-2014: comparing data from two sample-based mortality surveillance systems.

PubMed

Sha, Feng; Chang, Qingsong; Law, Yik Wa; Hong, Qi; Yip, Paul S F

2018-02-13

The decreasing suicide rate in China has been regarded as a major contributor to the decline of global suicide rate in the past decade. However, previous estimations on China's suicide rates might not be accurate, since often they were based on the data from the Ministry of Health's Vital Registration ("MOH-VR") System, which is biased towards the better-off population. This study aims to compare suicide data extracted from the MOH-VR System with a more representative mortality surveillance system, namely the Center for Disease Control and Prevention's Disease Surveillance Points ("CDC-DSP") System, and update China's national and subnational suicide rates in the period of 2004-2014. The CDC-DSP data are obtained from the National Cause-of-Death Surveillance Dataset (2004-2014) and the MOH-VR data are from the Chinese Health Statistics Yearbooks (2005-2012) and the China Health and Family Planning Statistics Yearbooks (2013-2015). First, a negative binomial regression model was used to test the associations between the source of data (CDC-DSP/MOH-VR) and suicide rates in 2004-2014. Joinpoint regression analyses and Kitagawa's decomposition method are then applied to analyze the trends of the crude suicide rates. Both systems indicated China's suicide rates decreased over the study period. However, before the two systems merged in 2013, the CDC-DSP System reported significantly higher national suicide rates (IRR = 1.18, 95% Confidence Interval [CI]: 1.13-1.24) and rural suicide rates (IRR = 1.29, 95% CI: 1.21-1.38) than the MOH-VR System. The CDC-DSP System also showed significant reversing points in 2011 (95% CI: 2006-2012) and 2006 (95% CI: 2006-2008) on the rural and urban suicide trends. Moreover, the suicide rates in the east and central urban regions were reversed in 2011 and 2008. The biased MOH-VR System underestimated China's national and rural suicide rates. Although not widely appreciated in the field of suicide research, the CDC-DSP System provides more accurate estimations on China's suicide rates and is recommended for future studies to monitor the reversing trends of suicide rates in China's more developed areas.

Embedded real-time image processing hardware for feature extraction and clustering

NASA Astrophysics Data System (ADS)

Chiu, Lihu; Chang, Grant

2003-08-01

Printronix, Inc. uses scanner-based image systems to perform print quality measurements for line-matrix printers. The size of the image samples and image definition required make commercial scanners convenient to use. The image processing is relatively well defined, and we are able to simplify many of the calculations into hardware equations and "c" code. The process of rapidly prototyping the system using DSP based "c" code gets the algorithms well defined early in the development cycle. Once a working system is defined, the rest of the process involves splitting the task up for the FPGA and the DSP implementation. Deciding which of the two to use, the DSP or the FPGA, is a simple matter of trial benchmarking. There are two kinds of benchmarking: One for speed, and the other for memory. The more memory intensive algorithms should run in the DSP, and the simple real time tasks can use the FPGA most effectively. Once the task is split, we can decide which platform the algorithm should be executed. This involves prototyping all the code in the DSP, then timing various blocks of the algorithm. Slow routines can be optimized using the compiler tools, and if further reduction in time is needed, into tasks that the FPGA can perform.

Digital Analysis and Sorting of Fluorescence Lifetime by Flow Cytometry

PubMed Central

Houston, Jessica P.; Naivar, Mark A.; Freyer, James P.

2010-01-01

Frequency-domain flow cytometry techniques are combined with modifications to the digital signal processing capabilities of the Open Reconfigurable Cytometric Acquisition System (ORCAS) to analyze fluorescence decay lifetimes and control sorting. Real-time fluorescence lifetime analysis is accomplished by rapidly digitizing correlated, radiofrequency modulated detector signals, implementing Fourier analysis programming with ORCAS’ digital signal processor (DSP) and converting the processed data into standard cytometric list mode data. To systematically test the capabilities of the ORCAS 50 MS/sec analog-to-digital converter (ADC) and our DSP programming, an error analysis was performed using simulated light scatter and fluorescence waveforms (0.5–25 ns simulated lifetime), pulse widths ranging from 2 to 15 µs, and modulation frequencies from 2.5 to 16.667 MHz. The standard deviations of digitally acquired lifetime values ranged from 0.112 to >2 ns, corresponding to errors in actual phase shifts from 0.0142° to 1.6°. The lowest coefficients of variation (<1%) were found for 10-MHz modulated waveforms having pulse widths of 6 µs and simulated lifetimes of 4 ns. Direct comparison of the digital analysis system to a previous analog phase-sensitive flow cytometer demonstrated similar precision and accuracy on measurements of a range of fluorescent microspheres, unstained cells and cells stained with three common fluorophores. Sorting based on fluorescence lifetime was accomplished by adding analog outputs to ORCAS and interfacing with a commercial cell sorter with a radiofrequency modulated solid-state laser. Two populations of fluorescent microspheres with overlapping fluorescence intensities but different lifetimes (2 and 7 ns) were separated to ~98% purity. Overall, the digital signal acquisition and processing methods we introduce present a simple yet robust approach to phase-sensitive measurements in flow cytometry. The ability to simply and inexpensively implement this system on a commercial flow sorter will both allow better dissemination of this technology and better exploit the traditionally underutilized parameter of fluorescence lifetime. PMID:20662090

Evaluating the accuracy and large inaccuracy of two continuous glucose monitoring systems.

PubMed

Leelarathna, Lalantha; Nodale, Marianna; Allen, Janet M; Elleri, Daniela; Kumareswaran, Kavita; Haidar, Ahmad; Caldwell, Karen; Wilinska, Malgorzata E; Acerini, Carlo L; Evans, Mark L; Murphy, Helen R; Dunger, David B; Hovorka, Roman

2013-02-01

This study evaluated the accuracy and large inaccuracy of the Freestyle Navigator (FSN) (Abbott Diabetes Care, Alameda, CA) and Dexcom SEVEN PLUS (DSP) (Dexcom, Inc., San Diego, CA) continuous glucose monitoring (CGM) systems during closed-loop studies. Paired CGM and plasma glucose values (7,182 data pairs) were collected, every 15-60 min, from 32 adults (36.2±9.3 years) and 20 adolescents (15.3±1.5 years) with type 1 diabetes who participated in closed-loop studies. Levels 1, 2, and 3 of large sensor error with increasing severity were defined according to absolute relative deviation greater than or equal to ±40%, ±50%, and ±60% at a reference glucose level of ≥6 mmol/L or absolute deviation greater than or equal to ±2.4 mmol/L,±3.0 mmol/L, and ±3.6 mmol/L at a reference glucose level of <6 mmol/L. Median absolute relative deviation was 9.9% for FSN and 12.6% for DSP. Proportions of data points in Zones A and B of Clarke error grid analysis were similar (96.4% for FSN vs. 97.8% for DSP). Large sensor over-reading, which increases risk of insulin over-delivery and hypoglycemia, occurred two- to threefold more frequently with DSP than FSN (once every 2.5, 4.6, and 10.7 days of FSN use vs. 1.2, 2.0, and 3.7 days of DSP use for Level 1-3 errors, respectively). At levels 2 and 3, large sensor errors lasting 1 h or longer were absent with FSN but persisted with DSP. FSN and DSP differ substantially in the frequency and duration of large inaccuracy despite only modest differences in conventional measures of numerical and clinical accuracy. Further evaluations are required to confirm that FSN is more suitable for integration into closed-loop delivery systems.

Design of overload vehicle monitoring and response system based on DSP

NASA Astrophysics Data System (ADS)

Yu, Yan; Liu, Yiheng; Zhao, Xuefeng

2014-03-01

The overload vehicles are making much more damage to the road surface than the regular ones. Many roads and bridges are equipped with structural health monitoring system (SHM) to provide early-warning to these damage and evaluate the safety of road and bridge. However, because of the complex nature of SHM system, it's expensive to manufacture, difficult to install and not well-suited for the regular bridges and roads. Based on this application background, this paper designs a compact structural health monitoring system based on DSP, which is highly integrated, low-power, easy to install and inexpensive to manufacture. The designed system is made up of sensor arrays, the charge amplifier module, the DSP processing unit, the alarm system for overload, and the estimate for damage of the road and bridge structure. The signals coming from sensor arrays go through the charge amplifier. DSP processing unit will receive the amplified signals, estimate whether it is an overload signal or not, and convert analog variables into digital ones so that they are compatible with the back-end digital circuit for further processing. The system will also restrict certain vehicles that are overweight, by taking image of the car brand, sending the alarm, and transferring the collected pressure data to remote data center for further monitoring analysis by rain-flow counting method.

Glycosaminoglycan chain of dentin sialoprotein proteoglycan.

PubMed

Zhu, Q; Sun, Y; Prasad, M; Wang, X; Yamoah, A K; Li, Y; Feng, J; Qin, C

2010-08-01

Dentin sialophosphoprotein (DSPP) is processed into dentin sialoprotein (DSP) and dentin phosphoprotein. A molecular variant of rat DSP, referred to as "HMW-DSP", has been speculated to be a proteoglycan form of DSP. To determine if HMW-DSP is the proteoglycan form of DSP and to identify the glycosaminoglycan side-chain attachment site(s), we further characterized HMW-DSP. Chondroitinase ABC treatment reduced the migration rate for portions of rat HMW-DSP to the level of DSP. Disaccharide analysis showed that rat HMW-DSP contains glycosaminoglycan chains made of chondroitin-4-sulfate and has an average of 31-32 disaccharides/mol. These observations confirmed that HMW-DSP is the proteoglycan form of DSP (renamed "DSP-PG"). Edman degradation and mass spectrometric analyses of tryptic peptides from rat DSP-PG, along with substitution analyses of candidate Ser residues in mouse DSPP, confirmed that 2 glycosaminoglycan chains are attached to Ser(241) and Ser(253) in the rat, or Ser(242) and Ser(254) in the mouse DSPP sequence.

Fast, multi-channel real-time processing of signals with microsecond latency using graphics processing units.

PubMed

Rath, N; Kato, S; Levesque, J P; Mauel, M E; Navratil, G A; Peng, Q

2014-04-01

Fast, digital signal processing (DSP) has many applications. Typical hardware options for performing DSP are field-programmable gate arrays (FPGAs), application-specific integrated DSP chips, or general purpose personal computer systems. This paper presents a novel DSP platform that has been developed for feedback control on the HBT-EP tokamak device. The system runs all signal processing exclusively on a Graphics Processing Unit (GPU) to achieve real-time performance with latencies below 8 μs. Signals are transferred into and out of the GPU using PCI Express peer-to-peer direct-memory-access transfers without involvement of the central processing unit or host memory. Tests were performed on the feedback control system of the HBT-EP tokamak using forty 16-bit floating point inputs and outputs each and a sampling rate of up to 250 kHz. Signals were digitized by a D-TACQ ACQ196 module, processing done on an NVIDIA GTX 580 GPU programmed in CUDA, and analog output was generated by D-TACQ AO32CPCI modules.

Glycosaminoglycan Chain of Dentin Sialoprotein Proteoglycan

PubMed Central

Zhu, Q.; Sun, Y.; Prasad, M.; Wang, X.; Yamoah, A.K.; Li, Y.; Feng, J.; Qin, C.

2010-01-01

Dentin sialophosphoprotein (DSPP) is processed into dentin sialoprotein (DSP) and dentin phosphoprotein. A molecular variant of rat DSP, referred to as “HMW-DSP”, has been speculated to be a proteoglycan form of DSP. To determine if HMW-DSP is the proteoglycan form of DSP and to identify the glycosaminoglycan side-chain attachment site(s), we further characterized HMW-DSP. Chondroitinase ABC treatment reduced the migration rate for portions of rat HMW-DSP to the level of DSP. Disaccharide analysis showed that rat HMW-DSP contains glycosaminoglycan chains made of chondroitin-4-sulfate and has an average of 31-32 disaccharides/mol. These observations confirmed that HMW-DSP is the proteoglycan form of DSP (renamed “DSP-PG”). Edman degradation and mass spectrometric analyses of tryptic peptides from rat DSP-PG, along with substitution analyses of candidate Ser residues in mouse DSPP, confirmed that 2 glycosaminoglycan chains are attached to Ser241 and Ser253 in the rat, or Ser242 and Ser254 in the mouse DSPP sequence. PMID:20400719

Locomotive track detection for underground

NASA Astrophysics Data System (ADS)

Ma, Zhonglei; Lang, Wenhui; Li, Xiaoming; Wei, Xing

2017-08-01

In order to improve the PC-based track detection system, this paper proposes a method to detect linear track for underground locomotive based on DSP + FPGA. Firstly, the analog signal outputted from the camera is sampled by A / D chip. Then the collected digital signal is preprocessed by FPGA. Secondly, the output signal of FPGA is transmitted to DSP via EMIF port. Subsequently, the adaptive threshold edge detection, polar angle and radius constrain based Hough transform are implemented by DSP. Lastly, the detected track information is transmitted to host computer through Ethernet interface. The experimental results show that the system can not only meet the requirements of real-time detection, but also has good robustness.

Digital signal processing at Bell Labs-Foundations for speech and acoustics research

NASA Astrophysics Data System (ADS)

Rabiner, Lawrence R.

2004-05-01

Digital signal processing (DSP) is a fundamental tool for much of the research that has been carried out of Bell Labs in the areas of speech and acoustics research. The fundamental bases for DSP include the sampling theorem of Nyquist, the method for digitization of analog signals by Shannon et al., methods of spectral analysis by Tukey, the cepstrum by Bogert et al., and the FFT by Tukey (and Cooley of IBM). Essentially all of these early foundations of DSP came out of the Bell Labs Research Lab in the 1930s, 1940s, 1950s, and 1960s. This fundamental research was motivated by fundamental applications (mainly in the areas of speech, sonar, and acoustics) that led to novel design methods for digital filters (Kaiser, Golden, Rabiner, Schafer), spectrum analysis methods (Rabiner, Schafer, Allen, Crochiere), fast convolution methods based on the FFT (Helms, Bergland), and advanced digital systems used to implement telephony channel banks (Jackson, McDonald, Freeny, Tewksbury). This talk summarizes the key contributions to DSP made at Bell Labs, and illustrates how DSP was utilized in the areas of speech and acoustics research. It also shows the vast, worldwide impact of this DSP research on modern consumer electronics.

Secretion and translocation signals and DspB/F-binding domains in the type III effector DspA/E of Erwinia amylovora.

PubMed

Oh, Chang-Sik; Carpenter, Sara C D; Hayes, Marshall L; Beer, Steven V

2010-04-01

DspA/E is a type III effector of Erwinia amylovora, the bacterial pathogen that causes fire blight disease in roseaceous plants. This effector is indispensable for disease development, and it is translocated into plant cells. A DspA/E-specific chaperone, DspB/F, is necessary for DspA/E secretion and possibly for its translocation. In this work, DspB/F-binding sites and secretion and translocation signals in the DspA/E protein were determined. Based on yeast two-hybrid assays, DspB/F was found to bind DspA/E within the first 210 amino acids of the protein. Surprisingly, both DspB/F and OrfA, the putative chaperone of Eop1, also interacted with the C-terminal 1059 amino acids of DspA/E; this suggests another chaperone-binding site. Secretion and translocation assays using serial N-terminal lengths of DspA/E fused with the active form of AvrRpt2 revealed that at least the first 109 amino acids, including the first N-terminal chaperone-binding motif and DspB/F, were required for efficient translocation of DspA/E, although the first 35 amino acids were sufficient for its secretion and the presence of DspB/F was not required. These results indicate that secretion and translocation signals are present in the N terminus of DspA/E, and that at least one DspB/F-binding motif is required for efficient translocation into plant cells.

Determination of torque speed current characteristics of a brushless DC motor by utilizing back-EMF of non-energized phase

NASA Astrophysics Data System (ADS)

Jang, G. H.; Yeom, J. H.; Kim, M. G.

2007-03-01

This paper presents a method to determine the torque constant and the torque-speed-current characteristics of a brushless DC (BLDC) motor by utilizing back-EMF variation of nonenergized phase. It also develops a BLDC motor controller with a digital signal processor (DSP) to monitor its current, voltage and speed in real time. Torque-speed-current characteristics of a BLDC motor are determined by using the proposed method and the developed controller. They are compared with the torque-speed-current characteristics measured by dynamometer experimentally. This research shows that the proposed method is an effective method to determine the torque constant and the torque-speed-current characteristics of the BLDC motor without using dynamometer.

The design and implementation of signal decomposition system of CL multi-wavelet transform based on DSP builder

NASA Astrophysics Data System (ADS)

Huang, Yan; Wang, Zhihui

2015-12-01

With the development of FPGA, DSP Builder is widely applied to design system-level algorithms. The algorithm of CL multi-wavelet is more advanced and effective than scalar wavelets in processing signal decomposition. Thus, a system of CL multi-wavelet based on DSP Builder is designed for the first time in this paper. The system mainly contains three parts: a pre-filtering subsystem, a one-level decomposition subsystem and a two-level decomposition subsystem. It can be converted into hardware language VHDL by the Signal Complier block that can be used in Quartus II. After analyzing the energy indicator, it shows that this system outperforms Daubenchies wavelet in signal decomposition. Furthermore, it has proved to be suitable for the implementation of signal fusion based on SoPC hardware, and it will become a solid foundation in this new field.

Real-time Enhancement, Registration, and Fusion for an Enhanced Vision System

NASA Technical Reports Server (NTRS)

Hines, Glenn D.; Rahman, Zia-ur; Jobson, Daniel J.; Woodell, Glenn A.

2006-01-01

Over the last few years NASA Langley Research Center (LaRC) has been developing an Enhanced Vision System (EVS) to aid pilots while flying in poor visibility conditions. The EVS captures imagery using two infrared video cameras. The cameras are placed in an enclosure that is mounted and flown forward-looking underneath the NASA LaRC ARIES 757 aircraft. The data streams from the cameras are processed in real-time and displayed on monitors on-board the aircraft. With proper processing the camera system can provide better-than-human-observed imagery particularly during poor visibility conditions. However, to obtain this goal requires several different stages of processing including enhancement, registration, and fusion, and specialized processing hardware for real-time performance. We are using a real-time implementation of the Retinex algorithm for image enhancement, affine transformations for registration, and weighted sums to perform fusion. All of the algorithms are executed on a single TI DM642 digital signal processor (DSP) clocked at 720 MHz. The image processing components were added to the EVS system, tested, and demonstrated during flight tests in August and September of 2005. In this paper we briefly discuss the EVS image processing hardware and algorithms. We then discuss implementation issues and show examples of the results obtained during flight tests.

[Assessment of precision and accuracy of digital surface photogrammetry with the DSP 400 system].

PubMed

Krimmel, M; Kluba, S; Dietz, K; Reinert, S

2005-03-01

The objective of the present study was to evaluate the precision and accuracy of facial anthropometric measurements obtained through digital 3-D surface photogrammetry with the DSP 400 system in comparison to traditional 2-D photogrammetry. Fifty plaster casts of cleft infants were imaged and 21 standard anthropometric measurements were obtained. For precision assessment the measurements were performed twice in a subsample. Accuracy was determined by comparison of direct measurements and indirect 2-D and 3-D image measurements. Precision of digital surface photogrammetry was almost as good as direct anthropometry and clearly better than 2-D photogrammetry. Measurements derived from 3-D images showed better congruence to direct measurements than from 2-D photos. Digital surface photogrammetry with the DSP 400 system is sufficiently precise and accurate for craniofacial anthropometric examinations.

Advanced Health Management System for the Space Shuttle Main Engine

NASA Technical Reports Server (NTRS)

Davidson, Matt; Stephens, John; Rodela, Chris

2006-01-01

Pratt & Whitney Rocketdyne, Inc., in cooperation with NASA-Marshall Space Flight Center (MSFC), has developed a new Advanced Health Management System (AHMS) controller for the Space Shuttle Main Engine (SSME) that will increase the probability of successfully placing the shuttle into the intended orbit and increase the safety of the Space Transportation System (STS) launches. The AHMS is an upgrade o the current Block II engine controller whose primary component is an improved vibration monitoring system called the Real-Time Vibration Monitoring System (RTVMS) that can effectively and reliably monitor the state of the high pressure turbomachinery and provide engine protection through a new synchronous vibration redline which enables engine shutdown if the vibration exceeds predetermined thresholds. The introduction of this system required improvements and modification to the Block II controller such as redesigning the Digital Computer Unit (DCU) memory and the Flight Accelerometer Safety Cut-Off System (FASCOS) circuitry, eliminating the existing memory retention batteries, installation of the Digital Signal Processor (DSP) technology, and installation of a High Speed Serial Interface (HSSI) with accompanying outside world connectors. Test stand hot-fire testing along with lab testing have verified successful implementation and is expected to reduce the probability of catastrophic engine failures during the shuttle ascent phase and improve safely by about 23% according to the Quantitative Risk Assessment System (QRAS), leading to a safer and more reliable SSME.

High Speed and High Functional Inverter Power Supplies for Plasma Generation and Control, and their Performance

NASA Astrophysics Data System (ADS)

Uesugi, Yoshihiko; Razzak, Mohammad A.; Kondo, Kenji; Kikuchi, Yusuke; Takamura, Shuichi; Imai, Takahiro; Toyoda, Mitsuhiro

The Rapid development of high power and high speed semiconductor switching devices has led to their various applications in related plasma fields. Especially, a high speed inverter power supply can be used as an RF power source instead of conventional linear amplifiers and a power supply to control the magnetic field in a fusion plasma device. In this paper, RF thermal plasma production and plasma heating experiments are described emphasis placed on using a static induction transistor inverter at a frequency range between 200 kHz and 2.5 MHz as an RF power supply. Efficient thermal plasma production is achieved experimentally by using a flexible and easily operated high power semiconductor inverter power supply. Insulated gate bipolar transistor (IGBT) inverter power supplies driven by a high speed digital signal processor are applied as tokamak joule coil and vertical coil power supplies to control plasma current waveform and plasma equilibrium. Output characteristics, such as the arbitrary bipolar waveform generation of a pulse width modulation (PWM) inverter using digital signal processor (DSP) can be successfully applied to tokamak power supplies for flexible plasma current operation and fast position control of a small tokamak.

Factors associated with distal symmetric polyneuropathies in adult Zambians: A cross-sectional, observational study of the role of HIV, non-antiretroviral medication exposures, and nutrition.

PubMed

Kvalsund, Michelle; Chidumayo, Takondwa; Hamel, Johanna; Herrmann, David; Heimburger, Douglas; Peltier, Amanda; Birbeck, Gretchen

2018-05-15

Non-antiretroviral (ART) drug exposures and poor nutrition may be important modifiable risk factors for distal symmetric polyneuropathies (DSP) in sub-Saharan Africa. We conducted a cross-sectional study of DSP prevalence and factors associated with DSP among clinic attendees in urban and rural Zambia. All participants underwent neurologist-performed examination. Laboratory investigations seeking comorbid risk factors for DSP were performed for DSP cases. We identified 31/137 (22.6%) HIV+ and 21/177 (11.9%) HIV- DSP cases. DSP prevalence did not differ by urbanicity, although rural participants were significantly more likely to have one asymptomatic DSP sign. Low dietary diversity, history of syphilis, history of tuberculosis, and prior metronidazole and ciprofloxacin use were associated with DSP amongst HIV+ cases, while age and education were associated with DSP in HIV- participants (all p-values < 0·05). In a multivariate logistic regression model, HIV (p = 0·0001) and age (p < 0·0001), and ciprofloxacin exposure (p = 0·01) remained independently associated with DSP. While diabetes was rare, supoptimal micronutrients levels were common among DSP cases regardless of HIV status. While HIV infection is strongly associated with DSP in Zambia, history of non-ART drug exposures and low dietary diversity are also important determinants of DSP in HIV+ individuals. Treatable micronutrient deficiencies were common. Copyright © 2018 Elsevier B.V. All rights reserved.

Adaptive and mobile ground sensor array.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Holzrichter, Michael Warren; O'Rourke, William T.; Zenner, Jennifer

The goal of this LDRD was to demonstrate the use of robotic vehicles for deploying and autonomously reconfiguring seismic and acoustic sensor arrays with high (centimeter) accuracy to obtain enhancement of our capability to locate and characterize remote targets. The capability to accurately place sensors and then retrieve and reconfigure them allows sensors to be placed in phased arrays in an initial monitoring configuration and then to be reconfigured in an array tuned to the specific frequencies and directions of the selected target. This report reviews the findings and accomplishments achieved during this three-year project. This project successfully demonstrated autonomousmore » deployment and retrieval of a payload package with an accuracy of a few centimeters using differential global positioning system (GPS) signals. It developed an autonomous, multisensor, temporally aligned, radio-frequency communication and signal processing capability, and an array optimization algorithm, which was implemented on a digital signal processor (DSP). Additionally, the project converted the existing single-threaded, monolithic robotic vehicle control code into a multi-threaded, modular control architecture that enhances the reuse of control code in future projects.« less

Floating-to-Fixed-Point Conversion for Digital Signal Processors

NASA Astrophysics Data System (ADS)

Menard, Daniel; Chillet, Daniel; Sentieys, Olivier

2006-12-01

Digital signal processing applications are specified with floating-point data types but they are usually implemented in embedded systems with fixed-point arithmetic to minimise cost and power consumption. Thus, methodologies which establish automatically the fixed-point specification are required to reduce the application time-to-market. In this paper, a new methodology for the floating-to-fixed point conversion is proposed for software implementations. The aim of our approach is to determine the fixed-point specification which minimises the code execution time for a given accuracy constraint. Compared to previous methodologies, our approach takes into account the DSP architecture to optimise the fixed-point formats and the floating-to-fixed-point conversion process is coupled with the code generation process. The fixed-point data types and the position of the scaling operations are optimised to reduce the code execution time. To evaluate the fixed-point computation accuracy, an analytical approach is used to reduce the optimisation time compared to the existing methods based on simulation. The methodology stages are described and several experiment results are presented to underline the efficiency of this approach.

Model predictive controller design for boost DC-DC converter using T-S fuzzy cost function

NASA Astrophysics Data System (ADS)

Seo, Sang-Wha; Kim, Yong; Choi, Han Ho

2017-11-01

This paper proposes a Takagi-Sugeno (T-S) fuzzy method to select cost function weights of finite control set model predictive DC-DC converter control algorithms. The proposed method updates the cost function weights at every sample time by using T-S type fuzzy rules derived from the common optimal control engineering knowledge that a state or input variable with an excessively large magnitude can be penalised by increasing the weight corresponding to the variable. The best control input is determined via the online optimisation of the T-S fuzzy cost function for all the possible control input sequences. This paper implements the proposed model predictive control algorithm in real time on a Texas Instruments TMS320F28335 floating-point Digital Signal Processor (DSP). Some experimental results are given to illuminate the practicality and effectiveness of the proposed control system under several operating conditions. The results verify that our method can yield not only good transient and steady-state responses (fast recovery time, small overshoot, zero steady-state error, etc.) but also insensitiveness to abrupt load or input voltage parameter variations.

[Digital signal processing of a novel neuron discharge model stimulation strategy for cochlear implants].

PubMed

Yang, Yiwei; Xu, Yuejin; Miu, Jichang; Zhou, Linghong; Xiao, Zhongju

2012-10-01

To apply the classic leakage integrate-and-fire models, based on the mechanism of the generation of physiological auditory stimulation, in the information processing coding of cochlear implants to improve the auditory result. The results of algorithm simulation in digital signal processor (DSP) were imported into Matlab for a comparative analysis. Compared with CIS coding, the algorithm of membrane potential integrate-and-fire (MPIF) allowed more natural pulse discharge in a pseudo-random manner to better fit the physiological structures. The MPIF algorithm can effectively solve the problem of the dynamic structure of the delivered auditory information sequence issued in the auditory center and allowed integration of the stimulating pulses and time coding to ensure the coherence and relevance of the stimulating pulse time.

High-frequency ultrasound annular array imaging. Part II: digital beamformer design and imaging.

PubMed

Hu, Chang-Hong; Snook, Kevin A; Cao, Pei-Jie; Shung, K Kirk

2006-02-01

This is the second part of a two-paper series reporting a recent effort in the development of a high-frequency annular array ultrasound imaging system. In this paper an imaging system composed of a six-element, 43 MHz annular array transducer, a six-channel analog front-end, a field programmable gate array (FPGA)-based beamformer, and a digital signal processor (DSP) microprocessor-based scan converter will be described. A computer is used as the interface for image display. The beamformer that applies delays to the echoes for each channel is implemented with the strategy of combining the coarse and fine delays. The coarse delays that are integer multiples of the clock periods are achieved by using a first-in-first-out (FIFO) structure, and the fine delays are obtained with a fractional delay (FD) filter. Using this principle, dynamic receiving focusing is achieved. The image from a wire phantom obtained with the imaging system was compared to that from a prototype ultrasonic backscatter microscope with a 45 MHz single-element transducer. The improved lateral resolution and depth of field from the wire phantom image were observed. Images from an excised rabbit eye sample also were obtained, and fine anatomical structures were discerned.

Immunohistochemical localization of the NH(2)-terminal and COOH-terminal fragments of dentin sialoprotein in mouse teeth.

PubMed

Yuan, Guohua; Yang, Guobin; Song, Guangtai; Chen, Zhi; Chen, Shuo

2012-08-01

Dentin sialoprotein (DSP) is a major non-collagenous protein in dentin. Mutation studies in human, along with gene knockout and transgenic experiments in mice, have confirmed the critical role of DSP for dentin formation. Our previous study reported that DSP is processed into fragments in mouse odontoblast-like cells. In order to gain insights into the function of DSP fragments, we further evaluated the expression pattern of DSP in the mouse odontoblast-like cells using immunohistochemistry and western blot assay with antibodies against the NH(2)-terminal and COOH-terminal regions of DSP. Then, the distribution profiles of the DSP NH(2)-terminal and COOH-terminal fragments and osteopontin (OPN) were investigated in mouse teeth at different ages by immunohistochemistry. In the odontoblast-like cells, multiple low molecular weight DSP fragments were detected, suggesting that part of the DSP protein was processed in the odontoblast-like cells. In mouse first lower molars, immunoreactions for anti-DSP-NH(2) antibody were intense in the predentin matrix but weak in mineralized dentin; in contrast, for anti-DSP-COOH antibody, strong immunoreactions were found in mineralized dentin, in particular dentinal tubules but weak in predentin. Therefore, DSP NH(2)-terminal and COOH-terminal fragments from odontoblasts were secreted to different parts of teeth, suggesting that they may play distinct roles in dentinogenesis. Meanwhile, both DSP antibodies showed weak staining in reactionary dentin (RD), whereas osteopontin (OPN) was clearly positive in RD. Therefore, DSP may be less crucial for RD formation than OPN.

Immunohistochemical localization of the NH2-terminal and COOH-terminal fragments of dentin sialoprotein in mouse teeth

PubMed Central

Yuan, Guohua; Yang, Guobin; Song, Guangtai

2013-01-01

Dentin sialoprotein (DSP) is a major non-collagenous protein in dentin. Mutation studies in human, along with gene knockout and transgenic experiments in mice, have confirmed the critical role of DSP for dentin formation. Our previous study reported that DSP is processed into fragments in mouse odontoblast-like cells. In order to gain insights into the function of DSP fragments, we further evaluated the expression pattern of DSP in the mouse odontoblast-like cells using immunohistochemistry and western blot assay with antibodies against the NH2-terminal and COOH-terminal regions of DSP. Then, the distribution profiles of the DSP NH2-terminal and COOH-terminal fragments and osteopontin (OPN) were investigated in mouse teeth at different ages by immunohistochemistry. In the odontoblast-like cells, multiple low molecular weight DSP fragments were detected, suggesting that part of the DSP protein was processed in the odontoblast-like cells. In mouse first lower molars, immunoreactions for anti-DSP-NH2 antibody were intense in the predentin matrix but weak in mineralized dentin; in contrast, for anti-DSP-COOH antibody, strong immunoreactions were found in mineralized dentin, in particular dentinal tubules but weak in predentin. Therefore, DSP NH2-terminal and COOH-terminal fragments from odontoblasts were secreted to different parts of teeth, suggesting that they may play distinct roles in dentinogenesis. Meanwhile, both DSP antibodies showed weak staining in reactionary dentin (RD), whereas osteopontin (OPN) was clearly positive in RD. Therefore, DSP may be less crucial for RD formation than OPN. PMID:22581382

MASTERS: A Virtual Lab on Multimedia Systems for Telecommunications, Medical, and Remote Sensing Applications

ERIC Educational Resources Information Center

Alexiadis, D. S.; Mitianoudis, N.

2013-01-01

Digital signal processing (DSP) has been an integral part of most electrical, electronic, and computer engineering curricula. The applications of DSP in multimedia (audio, image, video) storage, transmission, and analysis are also widely taught at both the undergraduate and post-graduate levels, as digital multimedia can be encountered in most…

Colt: an experiment in wormhole run-time reconfiguration

NASA Astrophysics Data System (ADS)

Bittner, Ray; Athanas, Peter M.; Musgrove, Mark

1996-10-01

Wormhole run-time reconfiguration (RTR) is an attempt to create a refined computing paradigm for high performance computational tasks. By combining concepts from field programmable gate array (FPGA) technologies with data flow computing, the Colt/Stallion architecture achieves high utilization of hardware resources, and facilitates rapid run-time reconfiguration. Targeted mainly at DSP-type operations, the Colt integrated circuit -- a prototype wormhole RTR device -- compares favorably to contemporary DSP alternatives in terms of silicon area consumed per unit computation and in computing performance. Although emphasis has been placed on signal processing applications, general purpose computation has not been overlooked. Colt is a prototype that defines an architecture not only at the chip level but also in terms of an overall system design. As this system is realized, the concept of wormhole RTR will be applied to numerical computation and DSP applications including those common to image processing, communications systems, digital filters, acoustic processing, real-time control systems and simulation acceleration.

Dispatchable Solar Power Plant Project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Price, Henry

As penetration of intermittent renewable power increases, grid operators must manage greater variability in the supply and demand on the grid. One result is that utilities are planning to build many new natural gas peaking power plants that provide added flexibility needed for grid management. This report discusses the development of a dispatchable solar power (DSP) plant that can be used in place of natural gas peakers. Specifically, a new molten-salt tower (MST) plant has been developed that is designed to allow much more flexible operation than typically considered in concentrating solar power plants. As a result, this plant canmore » provide most of the capacity and ancillary benefits of a conventional natural gas peaker plant but without the carbon emissions. The DSP system presented was designed to meet the specific needs of the Arizona Public Service (APS) utility 2017 peaking capacity request for proposals (RFP). The goal of the effort was to design a MST peaker plant that had the operational capabilities required to meet the peaking requirements of the utility and be cost competitive with the natural gas alternative. The effort also addresses many perceived barriers facing the commercial deployment of MST technology in the US today. These include MST project development issues such as permitting, avian impacts, visual impacts of tower CSP projects, project schedule, and water consumption. The DSP plant design is based on considerable analyses using sophisticated solar system design tools and in-depth preliminary engineering design. The resulting DSP plant design uses a 250 MW steam power cycle, with solar field designed to fit on a square mile plot of land that has a design point thermal rating of 400 MWt. The DSP plant has an annual capacity factor of about 16% tailored to deliver greater than 90% capacity during the critical Arizona summer afternoon peak. The table below compares the All-In energy cost and capacity payment of conventional combustion turbines to DSP plants. These results estimate that the cost of the DSP plant is about 10% higher than a similarly-sized and operated frame combustion turbine and slightly cheaper than an aero derivative combustion turbine when APS reference fuel and emissions costs are included. The DSP plant cost is based on a single, first-of-a-kind plant, and it is likely that subsequent plants would be less expensive.« less

The analysis of behavior in orbit GSS two series of US early-warning system

NASA Astrophysics Data System (ADS)

Sukhov, P. P.; Epishev, V. P.; Sukhov, K. P.; Motrunych, I. I.

2016-09-01

Satellites Early Warning System Series class SBIRS US Air Force must replace on GEO early series DSP Series. During 2014-2016 the authors received more than 30 light curves "DSP-18 and "Sbirs-Geo 2". The analysis of the behavior of these satellites in orbit by a coordinate and photometric data. It is shown that for the monitoring of the Earth's surface is enough to place GEO 4 unit SBIRS across 90 deg.

Real-time Enhanced Vision System

NASA Technical Reports Server (NTRS)

Hines, Glenn D.; Rahman, Zia-Ur; Jobson, Daniel J.; Woodell, Glenn A.; Harrah, Steven D.

2005-01-01

Flying in poor visibility conditions, such as rain, snow, fog or haze, is inherently dangerous. However these conditions can occur at nearly any location, so inevitably pilots must successfully navigate through them. At NASA Langley Research Center (LaRC), under support of the Aviation Safety and Security Program Office and the Systems Engineering Directorate, we are developing an Enhanced Vision System (EVS) that combines image enhancement and synthetic vision elements to assist pilots flying through adverse weather conditions. This system uses a combination of forward-looking infrared and visible sensors for data acquisition. A core function of the system is to enhance and fuse the sensor data in order to increase the information content and quality of the captured imagery. These operations must be performed in real-time for the pilot to use while flying. For image enhancement, we are using the LaRC patented Retinex algorithm since it performs exceptionally well for improving low-contrast range imagery typically seen during poor visibility conditions. In general, real-time operation of the Retinex requires specialized hardware. To date, we have successfully implemented a single-sensor real-time version of the Retinex on several different Digital Signal Processor (DSP) platforms. In this paper we give an overview of the EVS and its performance requirements for real-time enhancement and fusion and we discuss our current real-time Retinex implementations on DSPs.

Real-time Enhancement, Registration, and Fusion for a Multi-Sensor Enhanced Vision System

NASA Technical Reports Server (NTRS)

Hines, Glenn D.; Rahman, Zia-ur; Jobson, Daniel J.; Woodell, Glenn A.

2006-01-01

Over the last few years NASA Langley Research Center (LaRC) has been developing an Enhanced Vision System (EVS) to aid pilots while flying in poor visibility conditions. The EVS captures imagery using two infrared video cameras. The cameras are placed in an enclosure that is mounted and flown forward-looking underneath the NASA LaRC ARIES 757 aircraft. The data streams from the cameras are processed in real-time and displayed on monitors on-board the aircraft. With proper processing the camera system can provide better-than- human-observed imagery particularly during poor visibility conditions. However, to obtain this goal requires several different stages of processing including enhancement, registration, and fusion, and specialized processing hardware for real-time performance. We are using a real-time implementation of the Retinex algorithm for image enhancement, affine transformations for registration, and weighted sums to perform fusion. All of the algorithms are executed on a single TI DM642 digital signal processor (DSP) clocked at 720 MHz. The image processing components were added to the EVS system, tested, and demonstrated during flight tests in August and September of 2005. In this paper we briefly discuss the EVS image processing hardware and algorithms. We then discuss implementation issues and show examples of the results obtained during flight tests. Keywords: enhanced vision system, image enhancement, retinex, digital signal processing, sensor fusion

Study of heterogeneous and reconfigurable architectures in the communication domain

NASA Astrophysics Data System (ADS)

Feldkaemper, H. T.; Blume, H.; Noll, T. G.

2003-05-01

One of the most challenging design issues for next generations of (mobile) communication systems is fulfilling the computational demands while finding an appropriate trade-off between flexibility and implementation aspects, especially power consumption. Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. Typical target architectures for future communication systems include embedded FPGAs, dedicated macros as well as programmable digital signal and control oriented processor cores as each of these has its specific advantages. These will be integrated as a System-on-Chip (SoC). For such a heterogeneous architecture a design space exploration and an appropriate partitioning plays a crucial role. On the exemplary vehicle of a Viterbi decoder as frequently used in communication systems we show which costs in terms of ATE complexity arise implementing typical components on different types of architecture blocks. A factor of about seven orders of magnitude spans between a physically optimised implementation and an implementation on a programmable DSP kernel. An implementation on an embedded FPGA kernel is in between these two representing an attractive compromise with high flexibility and low power consumption. Extending this comparison to further components, it is shown quantitatively that the cost ratio between different implementation alternatives is closely related to the operation to be performed. This information is essential for the appropriate partitioning of heterogeneous systems.

Real-time enhanced vision system

NASA Astrophysics Data System (ADS)

Hines, Glenn D.; Rahman, Zia-ur; Jobson, Daniel J.; Woodell, Glenn A.; Harrah, Steven D.

2005-05-01

Flying in poor visibility conditions, such as rain, snow, fog or haze, is inherently dangerous. However these conditions can occur at nearly any location, so inevitably pilots must successfully navigate through them. At NASA Langley Research Center (LaRC), under support of the Aviation Safety and Security Program Office and the Systems Engineering Directorate, we are developing an Enhanced Vision System (EVS) that combines image enhancement and synthetic vision elements to assist pilots flying through adverse weather conditions. This system uses a combination of forward-looking infrared and visible sensors for data acquisition. A core function of the system is to enhance and fuse the sensor data in order to increase the information content and quality of the captured imagery. These operations must be performed in real-time for the pilot to use while flying. For image enhancement, we are using the LaRC patented Retinex algorithm since it performs exceptionally well for improving low-contrast range imagery typically seen during poor visibility poor visibility conditions. In general, real-time operation of the Retinex requires specialized hardware. To date, we have successfully implemented a single-sensor real-time version of the Retinex on several different Digital Signal Processor (DSP) platforms. In this paper we give an overview of the EVS and its performance requirements for real-time enhancement and fusion and we discuss our current real-time Retinex implementations on DSPs.

Parallel Processing with Digital Signal Processing Hardware and Software

NASA Technical Reports Server (NTRS)

Swenson, Cory V.

1995-01-01

The assembling and testing of a parallel processing system is described which will allow a user to move a Digital Signal Processing (DSP) application from the design stage to the execution/analysis stage through the use of several software tools and hardware devices. The system will be used to demonstrate the feasibility of the Algorithm To Architecture Mapping Model (ATAMM) dataflow paradigm for static multiprocessor solutions of DSP applications. The individual components comprising the system are described followed by the installation procedure, research topics, and initial program development.

A Novel Dual Separate Paths (DSP) Algorithm Providing Fault-Tolerant Communication for Wireless Sensor Networks.

PubMed

Tien, Nguyen Xuan; Kim, Semog; Rhee, Jong Myung; Park, Sang Yoon

2017-07-25

Fault tolerance has long been a major concern for sensor communications in fault-tolerant cyber physical systems (CPSs). Network failure problems often occur in wireless sensor networks (WSNs) due to various factors such as the insufficient power of sensor nodes, the dislocation of sensor nodes, the unstable state of wireless links, and unpredictable environmental interference. Fault tolerance is thus one of the key requirements for data communications in WSN applications. This paper proposes a novel path redundancy-based algorithm, called dual separate paths (DSP), that provides fault-tolerant communication with the improvement of the network traffic performance for WSN applications, such as fault-tolerant CPSs. The proposed DSP algorithm establishes two separate paths between a source and a destination in a network based on the network topology information. These paths are node-disjoint paths and have optimal path distances. Unicast frames are delivered from the source to the destination in the network through the dual paths, providing fault-tolerant communication and reducing redundant unicast traffic for the network. The DSP algorithm can be applied to wired and wireless networks, such as WSNs, to provide seamless fault-tolerant communication for mission-critical and life-critical applications such as fault-tolerant CPSs. The analyzed and simulated results show that the DSP-based approach not only provides fault-tolerant communication, but also improves network traffic performance. For the case study in this paper, when the DSP algorithm was applied to high-availability seamless redundancy (HSR) networks, the proposed DSP-based approach reduced the network traffic by 80% to 88% compared with the standard HSR protocol, thus improving network traffic performance.

The MCNP-DSP code for calculations of time and frequency analysis parameters for subcritical systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Valentine, T.E.; Mihalczo, J.T.

1995-12-31

This paper describes a modified version of the MCNP code, the MCNP-DSP. Variance reduction features were disabled to have strictly analog particle tracking in order to follow fluctuating processes more accurately. Some of the neutron and photon physics routines were modified to better represent the production of particles. Other modifications are discussed.

Cloning and baculovirus expression of a desiccation stress gene from the beetle, Tenebrio molitor.

PubMed

Graham, L A; Bendena, W G; Walker, V K

1996-02-01

The cDNA sequence encoding a novel desiccation stress protein (dsp28) found in the hemolymph of the common yellow mealworm beetle, Tenebrio molitor, has been determined. The sequence encodes a 225 amino acid protein containing a 20 amino acid signal peptide. Dsp28 shows no significant similarity to any known nucleic acid or protein sequence. Levels of dsp28 mRNA were found to increase approx 5-fold following desiccation. Dsp28 cDNA has been cloned into a baculovirus expression vector and the expressed protein was compared to native dsp28. Both dsp28 expressed by recombinant baculovirus and native dsp28 are glycosylated and N-terminally processed. Although dsp28 is induced by cold in addition to desiccation stress, it does not contribute to the freezing point depression (thermal hysteresis) observed in Tenebrio hemolymph.

The Dentin Sialoprotein (DSP) Domain Regulates Dental Mesenchymal Cell Differentiation through a Novel Surface Receptor

PubMed Central

Wan, Chunyan; Yuan, Guohua; Luo, Daoshu; Zhang, Lu; Lin, Heng; Liu, Huan; Chen, Lei; Yang, Guobin; Chen, Shuo; Chen, Zhi

2016-01-01

Dentin sialophosphoprotein (DSPP) is a dentin extracellular matrix protein that is processed into dentin sialoprotein (DSP), dentin glycoprotein (DGP) and dentin phosphoprotein (DPP). DSP is mainly expressed in odontoblasts. We hypothesized that DSP interacts with cell surface receptors and subsequently activates intracellular signaling. Using DSP as bait for screening a protein library, we demonstrate that DSP acts as a ligand and binds to integrin β6. The 36 amino acid residues of DSP are sufficient to bind to integrin β6. This peptide promoted cell attachment, migration, differentiation and mineralization of dental mesenchymal cells. In addition, DSP aa183-219 stimulated phosphorylation of ERK1/2 and P38 kinases. This activation was inhibited by an anti-integrin β6 antibody and siRNA. Furthermore, we demonstrate that this DSP fragment induces SMAD1/5/8 phosphorylation and nuclear translocation via ERK1/2 and P38 signaling. SMAD1/5/8 binds to SMAD binding elements (SBEs) in the DSPP gene promoter. SBE mutations result in a decrease in DSPP transcriptional activity. Endogenous DSPP expression was up-regulated by DSP aa183-219 in dental mesenchymal cells. The data in the current study demonstrate for the first time that this DSP domain acts as a ligand in a RGD-independent manner and is involved in intracellular signaling via interacting with integrin β6. The DSP domain regulates DSPP expression and odontoblast homeostasis via a positive feedback loop. PMID:27430624

The Dentin Sialoprotein (DSP) Domain Regulates Dental Mesenchymal Cell Differentiation through a Novel Surface Receptor.

PubMed

Wan, Chunyan; Yuan, Guohua; Luo, Daoshu; Zhang, Lu; Lin, Heng; Liu, Huan; Chen, Lei; Yang, Guobin; Chen, Shuo; Chen, Zhi

2016-07-19

Dentin sialophosphoprotein (DSPP) is a dentin extracellular matrix protein that is processed into dentin sialoprotein (DSP), dentin glycoprotein (DGP) and dentin phosphoprotein (DPP). DSP is mainly expressed in odontoblasts. We hypothesized that DSP interacts with cell surface receptors and subsequently activates intracellular signaling. Using DSP as bait for screening a protein library, we demonstrate that DSP acts as a ligand and binds to integrin β6. The 36 amino acid residues of DSP are sufficient to bind to integrin β6. This peptide promoted cell attachment, migration, differentiation and mineralization of dental mesenchymal cells. In addition, DSP (aa183-219) stimulated phosphorylation of ERK1/2 and P38 kinases. This activation was inhibited by an anti-integrin β6 antibody and siRNA. Furthermore, we demonstrate that this DSP fragment induces SMAD1/5/8 phosphorylation and nuclear translocation via ERK1/2 and P38 signaling. SMAD1/5/8 binds to SMAD binding elements (SBEs) in the DSPP gene promoter. SBE mutations result in a decrease in DSPP transcriptional activity. Endogenous DSPP expression was up-regulated by DSP (aa183-219) in dental mesenchymal cells. The data in the current study demonstrate for the first time that this DSP domain acts as a ligand in a RGD-independent manner and is involved in intracellular signaling via interacting with integrin β6. The DSP domain regulates DSPP expression and odontoblast homeostasis via a positive feedback loop.

Parallel design patterns for a low-power, software-defined compressed video encoder

NASA Astrophysics Data System (ADS)

Bruns, Michael W.; Hunt, Martin A.; Prasad, Durga; Gunupudi, Nageswara R.; Sonachalam, Sekar

2011-06-01

Video compression algorithms such as H.264 offer much potential for parallel processing that is not always exploited by the technology of a particular implementation. Consumer mobile encoding devices often achieve real-time performance and low power consumption through parallel processing in Application Specific Integrated Circuit (ASIC) technology, but many other applications require a software-defined encoder. High quality compression features needed for some applications such as 10-bit sample depth or 4:2:2 chroma format often go beyond the capability of a typical consumer electronics device. An application may also need to efficiently combine compression with other functions such as noise reduction, image stabilization, real time clocks, GPS data, mission/ESD/user data or software-defined radio in a low power, field upgradable implementation. Low power, software-defined encoders may be implemented using a massively parallel memory-network processor array with 100 or more cores and distributed memory. The large number of processor elements allow the silicon device to operate more efficiently than conventional DSP or CPU technology. A dataflow programming methodology may be used to express all of the encoding processes including motion compensation, transform and quantization, and entropy coding. This is a declarative programming model in which the parallelism of the compression algorithm is expressed as a hierarchical graph of tasks with message communication. Data parallel and task parallel design patterns are supported without the need for explicit global synchronization control. An example is described of an H.264 encoder developed for a commercially available, massively parallel memorynetwork processor device.

Design of motion adjusting system for space camera based on ultrasonic motor

NASA Astrophysics Data System (ADS)

Xu, Kai; Jin, Guang; Gu, Song; Yan, Yong; Sun, Zhiyuan

2011-08-01

Drift angle is a transverse intersection angle of vector of image motion of the space camera. Adjusting the angle could reduce the influence on image quality. Ultrasonic motor (USM) is a new type of actuator using ultrasonic wave stimulated by piezoelectric ceramics. They have many advantages in comparison with conventional electromagnetic motors. In this paper, some improvement was designed for control system of drift adjusting mechanism. Based on ultrasonic motor T-60 was designed the drift adjusting system, which is composed of the drift adjusting mechanical frame, the ultrasonic motor, the driver of Ultrasonic Motor, the photoelectric encoder and the drift adjusting controller. The TMS320F28335 DSP was adopted as the calculation and control processor, photoelectric encoder was used as sensor of position closed loop system and the voltage driving circuit designed as generator of ultrasonic wave. It was built the mathematic model of drive circuit of the ultrasonic motor T-60 using matlab modules. In order to verify the validity of the drift adjusting system, was introduced the source of the disturbance, and made simulation analysis. It designed the control systems of motor drive for drift adjusting system with the improved PID control. The drift angle adjusting system has such advantages as the small space, simple configuration, high position control precision, fine repeatability, self locking property and low powers. It showed that the system could accomplish the mission of drift angle adjusting excellent.

Perception SoC Based on an Ultrasonic Array of Sensors: Efficient DSP Core Implementation and Subsequent Experimental Results

NASA Astrophysics Data System (ADS)

Kassem, A.; Sawan, M.; Boukadoum, M.; Haidar, A.

2005-12-01

We are concerned with the design, implementation, and validation of a perception SoC based on an ultrasonic array of sensors. The proposed SoC is dedicated to ultrasonic echography applications. A rapid prototyping platform is used to implement and validate the new architecture of the digital signal processing (DSP) core. The proposed DSP core efficiently integrates all of the necessary ultrasonic B-mode processing modules. It includes digital beamforming, quadrature demodulation of RF signals, digital filtering, and envelope detection of the received signals. This system handles 128 scan lines and 6400 samples per scan line with a[InlineEquation not available: see fulltext.] angle of view span. The design uses a minimum size lookup memory to store the initial scan information. Rapid prototyping using an ARM/FPGA combination is used to validate the operation of the described system. This system offers significant advantages of portability and a rapid time to market.

Pre-Hardware Optimization of Spacecraft Image Processing Algorithms and Hardware Implementation

NASA Technical Reports Server (NTRS)

Kizhner, Semion; Petrick, David J.; Flatley, Thomas P.; Hestnes, Phyllis; Jentoft-Nilsen, Marit; Day, John H. (Technical Monitor)

2002-01-01

Spacecraft telemetry rates and telemetry product complexity have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image data processing and color picture generation application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The proposed solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms, and reconfigurable computing hardware (RC) technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processors (DSP). It has been shown that this approach can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft.

Terabit bandwidth-adaptive transmission using low-complexity format-transparent digital signal processing.

PubMed

Zhuge, Qunbi; Morsy-Osman, Mohamed; Chagnon, Mathieu; Xu, Xian; Qiu, Meng; Plant, David V

2014-02-10

In this paper, we propose a low-complexity format-transparent digital signal processing (DSP) scheme for next generation flexible and energy-efficient transceiver. It employs QPSK symbols as the training and pilot symbols for the initialization and tracking stage of the receiver-side DSP, respectively, for various modulation formats. The performance is numerically and experimentally evaluated in a dual polarization (DP) 11 Gbaud 64QAM system. Employing the proposed DSP scheme, we conduct a system-level study of Tb/s bandwidth-adaptive superchannel transmissions with flexible modulation formats including QPSK, 8QAM and 16QAM. The spectrum bandwidth allocation is realized in the digital domain instead of turning on/off sub-channels, which improves the performance of higher order QAM. Various transmission distances ranging from 240 km to 6240 km are demonstrated with a colorless detection for hardware complexity reduction.

Effects of recombinant dentin sialoprotein in dental pulp cells.

PubMed

Lee, S-Y; Kim, S-Y; Park, S-H; Kim, J-J; Jang, J-H; Kim, E-C

2012-04-01

Dentin sialophosphoprotein (DSPP) is critical for dentin mineralization. However, the function of dentin sialoprotein (DSP), the cleaved product of DSPP, remains unclear. This study aimed to investigate the signal transduction pathways and effects of recombinant human DSP (rh-DSP) on proliferation, migration, and odontoblastic differentiation in human dental pulp cells (HDPCs). The exogenous addition of rh-DSP enhanced the proliferation and migration of HDPCs in dose- and time-dependent manners. rh-DSP markedly increased ALP activity, calcium nodule formation, and levels of odontoblastic marker mRNA. rh-DSP increased BMP-2 expression and Smad1/5/8 phosphorylation, which was blocked by the BMP antagonist, noggin. Furthermore, rh-DSP phosphorylated extracellular signal-regulated kinase (ERK), c-Jun N-terminal kinase (JNK), Akt, and IκB-α, and induced the nuclear translocation of the NF-κB p65 subunit. Analysis of these data demonstrates a novel signaling function of rh-DSP for the promotion of growth, migration, and differentiation in HDPCS via the BMP/Smad, JNK, ERK, MAPK, and NF-κB signaling pathways, suggesting that rh-DSP may have therapeutic utility in dentin regeneration or dental pulp tissue engineering.

Development of an 8000 bps voice codec for AvSat

NASA Technical Reports Server (NTRS)

Clark, Joseph F.

1988-01-01

Air-mobile speech communication applications share robustness and noise immunity requirements with other mobile applications. The quality requirements are stringent, especially in the cockpit where air safety is involved. Based on these considerations, a decision was made to test an intermediate data rate such as 8.0 and 9.6 kb/s as proven technologies. A number of vocoders and codec technologies were investigated at rates ranging from 2.4 kb/s up to and including 9.6 kb/s. The proven vocoders operating at 2.4 and 4.8 kb/s lacked the noise immunity or the robustness to operate reliably in a cabin noise environment. One very attractive alternative approach was Spectrally Encoded Residual Excited LPC (SE-RELP) which is used in a multi-rate voice processor (MRP) developed at the Naval Research Lab (NRL). The MRP uses SE-RELP at rates of 9.6 and 16 kb/s. The 9.6 kb/s rate can be lowered to 8.0 kb/s without loss of information by modifying the frame. An 8.0 kb/s vocoder was developed using SE-RELP as a demonstrator and testbed. This demonstrator is implemented in real time using two Compaq 2 portable computers, each equipped with an ARIEL DSP016 Data Acquisition Processor.

Rapid prototyping of an EEG-based brain-computer interface (BCI).

PubMed

Guger, C; Schlögl, A; Neuper, C; Walterspacher, D; Strein, T; Pfurtscheller, G

2001-03-01

The electroencephalogram (EEG) is modified by motor imagery and can be used by patients with severe motor impairments (e.g., late stage of amyotrophic lateral sclerosis) to communicate with their environment. Such a direct connection between the brain and the computer is known as an EEG-based brain-computer interface (BCI). This paper describes a new type of BCI system that uses rapid prototyping to enable a fast transition of various types of parameter estimation and classification algorithms to real-time implementation and testing. Rapid prototyping is possible by using Matlab, Simulink, and the Real-Time Workshop. It is shown how to automate real-time experiments and perform the interplay between on-line experiments and offline analysis. The system is able to process multiple EEG channels on-line and operates under Windows 95 in real-time on a standard PC without an additional digital signal processor (DSP) board. The BCI can be controlled over the Internet, LAN or modem. This BCI was tested on 3 subjects whose task it was to imagine either left or right hand movement. A classification accuracy between 70% and 95% could be achieved with two EEG channels after some sessions with feedback using an adaptive autoregressive (AAR) model and linear discriminant analysis (LDA).

Hardware for dynamic quantum computing experiments: Part I

NASA Astrophysics Data System (ADS)

Johnson, Blake; Ryan, Colm; Riste, Diego; Donovan, Brian; Ohki, Thomas

Static, pre-defined control sequences routinely achieve high-fidelity operation on superconducting quantum processors. Efforts toward dynamic experiments depending on real-time information have mostly proceeded through hardware duplication and triggers, requiring a combinatorial explosion in the number of channels. We provide a hardware efficient solution to dynamic control with a complete platform of specialized FPGA-based control and readout electronics; these components enable arbitrary control flow, low-latency feedback and/or feedforward, and scale far beyond single-qubit control and measurement. We will introduce the BBN Arbitrary Pulse Sequencer 2 (APS2) control system and the X6 QDSP readout platform. The BBN APS2 features: a sequencer built around implementing short quantum gates, a sequence cache to allow long sequences with branching structures, subroutines for code re-use, and a trigger distribution module to capture and distribute steering information. The X6 QDSP features a single-stage DSP pipeline that combines demodulation with arbitrary integration kernels, and multiple taps to inspect data flow for debugging and calibration. We will show system performance when putting it all together, including a latency budget for feedforward operations. This research was funded by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), through the Army Research Office Contract No. W911NF-10-1-0324.

Behavioral study and design of a digital interpolator filter for wireless reconfigurable transmitters

NASA Astrophysics Data System (ADS)

Ferragina, V.; Frassone, A.; Ghittori, N.; Malcovati, P.; Vigna, A.

2005-06-01

The behavioral analysis and the design in a 0.13 μm CMOS technology of a digital interpolator filter for wireless applications are presented. The proposed block is designed to be embedded in the baseband part of a reconfigurable transmitter (WLAN 802.11a, UMTS) to operate as a sampling frequency boost between the digital signal processor (DSP) and the digital-to-analog converter (DAC). In recent trends the DAC of such transmitters usually operates at high conversion frequencies (to allow a relaxed implementation of the following analog reconstruction filter), while the DSP output flows at low frequencies (typically Nyquist rate). Thus a block able to increase the digital data rate, like the one proposed, is needed before the DAC. For example, in the WLAN case, an interpolation factor of 4 has been used, allowing the digital data frequency to raise from 20 MHz to 80 MHz. Using a time-domain model of the TX chain, a behavioral analysis has been performed to determine the impact of the filter performance on the quality of the signal at the antenna. This study has led to the evaluation of the z-domain filter transfer function, together with the specifications concerning a finite precision implementation. A VHDL description has allowed an automatic synthesis of the circuit in a 0.13 μm CMOS technology (with a supply voltage of 1.2 V). Post-synthesis simulations have confirmed the effectiveness of the proposed study.

Efficacy of DSP30-IL2/TPA for detection of cytogenetic abnormalities in chronic lymphocytic leukaemia/small lymphocytic lymphoma.

PubMed

Holmes, P J; Peiper, S C; Uppal, G K; Gong, J Z; Wang, Z-X; Bajaj, R

2016-10-01

Chronic lymphocytic leukaemia (CLL) is the most prevalent leukaemia in the Western Hemisphere. Cytogenetic abnormalities in CLL are used for diagnosis, prognosis and treatment. However, detecting these is difficult because mature B cells do not readily divide in culture. Here, we present data on two mitogen cocktails: CpG-oligonucleotide DSP30/Interleukin-2 (IL-2) and DSP30/IL-2 in combination with 12-O-tetradecanoylphorbol-13-acetate (TPA). We analysed 165 cases of CLL with FISH and cytogenetics from January 2011 to June 2013. In 2011, three cultures were set-up: unstimulated, DSP30/IL-2-stimulated and TPA-stimulated. In 2012-2013, two cultures were set-up: unstimulated and stimulated with TPA/DSP30/IL-2. In 2011, FISH had a detection rate of 91% and cytogenetics using DSP30/IL2 had a detection rate of 91% (n = 22). In 2012-2013, FISH had a detection rate of 79% and cytogenetics using TPA/DSP30/IL-2 had a detection rate of 98% (n = 40). The percentage of cases with normal FISH but abnormal cytogenetics increased from 9% in 2011 to 21% in 2012-2013. The TPA/DSP30/IL-2 cultures in 2012-2013 detected more novel abnormalities (n = 5) as compared to DSP30/IL-2 alone (n = 3). TPA/DSP30/IL2 was as good as or better than DSP30/IL2 alone. TPA/DSP30/IL-2 offers a high detection rate for CLL abnormalities with a single stimulated culture and may increase detection of clinically significant abnormalities. © 2016 John Wiley & Sons Ltd.

DSP+FPGA-based real-time histogram equalization system of infrared image

NASA Astrophysics Data System (ADS)

Gu, Dongsheng; Yang, Nansheng; Pi, Defu; Hua, Min; Shen, Xiaoyan; Zhang, Ruolan

2001-10-01

Histogram Modification is a simple but effective method to enhance an infrared image. There are several methods to equalize an infrared image's histogram due to the different characteristics of the different infrared images, such as the traditional HE (Histogram Equalization) method, and the improved HP (Histogram Projection) and PE (Plateau Equalization) method and so on. If to realize these methods in a single system, the system must have a mass of memory and extremely fast speed. In our system, we introduce a DSP + FPGA based real-time procession technology to do these things together. FPGA is used to realize the common part of these methods while DSP is to do the different part. The choice of methods and the parameter can be input by a keyboard or a computer. By this means, the function of the system is powerful while it is easy to operate and maintain. In this article, we give out the diagram of the system and the soft flow chart of the methods. And at the end of it, we give out the infrared image and its histogram before and after the process of HE method.

Domain of dentine sialoprotein mediates proliferation and differentiation of human periodontal ligament stem cells.

PubMed

Ozer, Alkan; Yuan, Guohua; Yang, Guobin; Wang, Feng; Li, Wentong; Yang, Yuan; Guo, Feng; Gao, Qingping; Shoff, Lisa; Chen, Zhi; Gay, Isabel C; Donly, Kevin J; MacDougall, Mary; Chen, Shuo

2013-01-01

Classic embryological studies have documented the inductive role of root dentin on adjacent periodontal ligament differentiation.  The biochemical composition of root dentin includes collagens and cleavage products of dentin sialophosphoprotein (DSPP), such as dentin sialoprotein (DSP).  The high abundance of DSP in root dentin prompted us to ask the question whether DSP or peptides derived thereof would serve as potent biological matrix components to induce periodontal progenitors to further differentiate into periodontal ligament cells. Here, we test the hypothesis that domain of DSP influences cell fate. In situ hybridization and immunohistochemical analyses showed that the COOH-terminal DSP domain is expressed in mouse periodontium at various stages of root development. The recombinant COOH-terminal DSP fragment (rC-DSP) enhanced attachment and migration of human periodontal ligament stem cells (PDLSC), human primary PDL cells without cell toxicity. rC-DSP induced PDLSC cell proliferation as well as differentiation and mineralization of PDLSC and PDL cells by formation of mineralized tissue and ALPase activity. Effect of rC-DSP on cell proliferation and differentiation was to promote gene expression of tooth/bone-relate markers, transcription factors and growth factors. The results for the first time showed that rC-DSP may be one of the components of cell niche for stimulating stem/progenitor cell proliferation and differentiation and a natural scaffold for periodontal regeneration application.

Domain of Dentine Sialoprotein Mediates Proliferation and Differentiation of Human Periodontal Ligament Stem Cells

PubMed Central

Yang, Guobin; Wang, Feng; Li, Wentong; Yang, Yuan; Guo, Feng; Gao, Qingping; Shoff, Lisa; Chen, Zhi; Gay, Isabel C.; Donly, Kevin J.; MacDougall, Mary; Chen, Shuo

2013-01-01

Classic embryological studies have documented the inductive role of root dentin on adjacent periodontal ligament differentiation.  The biochemical composition of root dentin includes collagens and cleavage products of dentin sialophosphoprotein (DSPP), such as dentin sialoprotein (DSP).  The high abundance of DSP in root dentin prompted us to ask the question whether DSP or peptides derived thereof would serve as potent biological matrix components to induce periodontal progenitors to further differentiate into periodontal ligament cells. Here, we test the hypothesis that domain of DSP influences cell fate. In situ hybridization and immunohistochemical analyses showed that the COOH-terminal DSP domain is expressed in mouse periodontium at various stages of root development. The recombinant COOH-terminal DSP fragment (rC-DSP) enhanced attachment and migration of human periodontal ligament stem cells (PDLSC), human primary PDL cells without cell toxicity. rC-DSP induced PDLSC cell proliferation as well as differentiation and mineralization of PDLSC and PDL cells by formation of mineralized tissue and ALPase activity. Effect of rC-DSP on cell proliferation and differentiation was to promote gene expression of tooth/bone-relate markers, transcription factors and growth factors. The results for the first time showed that rC-DSP may be one of the components of cell niche for stimulating stem/progenitor cell proliferation and differentiation and a natural scaffold for periodontal regeneration application. PMID:24400037

New sensorless, efficient optimized and stabilized v/f control for pmsm machines

NASA Astrophysics Data System (ADS)

Jafari, Seyed Hesam

With the rapid advances in power electronics and motor drive technologies in recent decades, permanent magnet synchronous machines (PMSM) have found extensive applications in a variety of industrial systems due to its many desirable features such as high power density, high efficiency, and high torque to current ratio, low noise, and robustness. In low dynamic applications like pumps, fans and compressors where the motor speed is nearly constant, usage of a simple control algorithm that can be implemented with least number of the costly external hardware can be highly desirable for industry. In recent published works, for low power PMSMs, a new sensorless volts-per-hertz (V/f) controlling method has been proposed which can be used for PMSM drive applications where the motor speed is constant. Moreover, to minimize the cost of motor implementation, the expensive rotor damper winding was eliminated. By removing the damper winding, however, instability problems normally occur inside of the motor which in some cases can be harmful for a PMSM drive. As a result, to address the instability issue, a stabilizing loop was developed and added to the conventional V/f. By further studying the proposed sensorless stabilized V/f, and calculating power loss, it became known that overall motor efficiency still is needed to be improved and optimized. This thesis suggests a new V/f control method for PMSMs, where both efficiency and stability problems are addressed. Also, although in nearly all recent related research, methods have been applied to low power PMSM, for the first time, in this thesis, the suggested method is implemented for a medium power 15 kW PMSM. A C2000 F2833x Digital Signal Processor (DSP) is used as controller part for the student custom built PMSM drive, but instead of programming the DSP in Assembly or C, the main control algorithm was developed in a rapid prototype software environment which here Matlab Simulink embedded code library is used.

Advanced End-to-end Simulation for On-board Processing (AESOP)

NASA Technical Reports Server (NTRS)

Mazer, Alan S.

1994-01-01

Developers of data compression algorithms typically use their own software together with commercial packages to implement, evaluate and demonstrate their work. While convenient for an individual developer, this approach makes it difficult to build on or use another's work without intimate knowledge of each component. When several people or groups work on different parts of the same problem, the larger view can be lost. What's needed is a simple piece of software to stand in the gap and link together the efforts of different people, enabling them to build on each other's work, and providing a base for engineers and scientists to evaluate the parts as a cohesive whole and make design decisions. AESOP (Advanced End-to-end Simulation for On-board Processing) attempts to meet this need by providing a graphical interface to a developer-selected set of algorithms, interfacing with compiled code and standalone programs, as well as procedures written in the IDL and PV-Wave command languages. As a proof of concept, AESOP is outfitted with several data compression algorithms integrating previous work on different processors (AT&T DSP32C, TI TMS320C30, SPARC). The user can specify at run-time the processor on which individual parts of the compression should run. Compressed data is then fed through simulated transmission and uncompression to evaluate the effects of compression parameters, noise and error correction algorithms. The following sections describe AESOP in detail. Section 2 describes fundamental goals for usability. Section 3 describes the implementation. Sections 4 through 5 describe how to add new functionality to the system and present the existing data compression algorithms. Sections 6 and 7 discuss portability and future work.

22 CFR 126.13 - Required information.

Code of Federal Regulations, 2010 CFR

2010-04-01

... 22 Foreign Relations 1 2010-04-01 2010-04-01 false Required information. 126.13 Section 126.13... PROVISIONS § 126.13 Required information. (a) All applications for licenses (DSP-5, DSP-61, DSP-73, and DSP... are multiple consignors, consignees or freight forwarders, and all the required information cannot be...

High-precision positioning system of four-quadrant detector based on the database query

NASA Astrophysics Data System (ADS)

Zhang, Xin; Deng, Xiao-guo; Su, Xiu-qin; Zheng, Xiao-qiang

2015-02-01

The fine pointing mechanism of the Acquisition, Pointing and Tracking (APT) system in free space laser communication usually use four-quadrant detector (QD) to point and track the laser beam accurately. The positioning precision of QD is one of the key factors of the pointing accuracy to APT system. A positioning system is designed based on FPGA and DSP in this paper, which can realize the sampling of AD, the positioning algorithm and the control of the fast swing mirror. We analyze the positioning error of facular center calculated by universal algorithm when the facular energy obeys Gauss distribution from the working principle of QD. A database is built by calculation and simulation with MatLab software, in which the facular center calculated by universal algorithm is corresponded with the facular center of Gaussian beam, and the database is stored in two pieces of E2PROM as the external memory of DSP. The facular center of Gaussian beam is inquiry in the database on the basis of the facular center calculated by universal algorithm in DSP. The experiment results show that the positioning accuracy of the high-precision positioning system is much better than the positioning accuracy calculated by universal algorithm.

Chromosomal aberrations in chronic lymphocytic leukemia detected by conventional cytogenetics with DSP30 as a single agent: comparison with FISH.

PubMed

Kotkowska, Aleksandra; Wawrzyniak, Ewa; Blonski, Jerzy Z; Robak, Tadeusz; Korycka-Wolowiec, Anna

2011-08-01

The aim of our study was to estimate the usefulness for conventional cytogenetics (CC) of DSP30 as a single agent (CC-DSP30) for detecting the most important chromosomal aberrations revealed in CLL by FISH and to find other abnormalities possibly existing but undetected by FISH with standard probes. Using CC-DSP30, the metaphases suitable for analysis were obtained in 90% of patients. CC-DSP30 and FISH were similarly efficacious for detecting del(11)(q22) and trisomy 12, whereas FISH was more sensitive for del(13)(q14). Sole del(13)(q14) detected by FISH, in 50% of patients was associated with other aberrations revealed by CC-DSP30. Additionally, the most recurrent anomaly detected by CC-DSP30 were structural aberrations of chromosome 2. Copyright © 2011 Elsevier Ltd. All rights reserved.

Self-contained eye-safe laser radar using an erbium-doped fiber laser

NASA Astrophysics Data System (ADS)

Driscoll, Thomas A.; Radecki, Dan J.; Tindal, Nan E.; Corriveau, John P.; Denman, Richard

2003-07-01

An Eye-safe Laser Radar has been developed under White Sands Missile Range sponsorship. The SEAL system, the Self-contained Eyesafe Autonomous Laser system, is designed to measure target position within a 0.5 meter box. Targets are augmented with Scotchlite for ranging out to 6 km and augmented with a retroreflector for targets out to 20 km. The data latency is less than 1.5 ms, and the position update rate is 1 kHz. The system is air-cooled, contained in a single 200-lb, 6-cubic-foot box, and uses less than 600 watts of prime power. The angle-angle-range data will be used to measure target dynamics and to control a tracking mount. The optical system is built around a diode-pumped, erbium-doped fiber laser rated at 1.5 watts average power at 10 kHz repetition rate with 25 nsec pulse duration. An 8 inch-diameter, F/2.84 telescope is relayed to a quadrant detector at F/0.85 giving a 5 mrad field of view. Two detectors have been evaluated, a Germanium PIN diode and an Intevac TE-IPD. The receiver electronics uses a DSP network of 6 SHARC processors to implement ranging and angle error algorithms along with an Optical AGC, including beam divergence/FOV control loops.Laboratory measurements of the laser characteristics, and system range and angle accuracies will be compared to simulations. Field measurements against actual targets will be presented.

Embedded DSP-based telehealth radar system for remote in-door fall detection.

PubMed

Garripoli, Carmine; Mercuri, Marco; Karsmakers, Peter; Jack Soh, Ping; Crupi, Giovanni; Vandenbosch, Guy A E; Pace, Calogero; Leroux, Paul; Schreurs, Dominique

2015-01-01

Telehealth systems and applications are extensively investigated nowadays to enhance the quality-of-care and, in particular, to detect emergency situations and to monitor the well-being of elderly people, allowing them to stay at home independently as long as possible. In this paper, an embedded telehealth system for continuous, automatic, and remote monitoring of real-time fall emergencies is presented and discussed. The system, consisting of a radar sensor and base station, represents a cost-effective and efficient healthcare solution. The implementation of the fall detection data processing technique, based on the least-square support vector machines, through a digital signal processor and the management of the communication between radar sensor and base station are detailed. Experimental tests, for a total of 65 mimicked fall incidents, recorded with 16 human subjects (14 men and two women) that have been monitored for 320 min, have been used to validate the proposed system under real circumstances. The subjects' weight is between 55 and 90 kg with heights between 1.65 and 1.82 m, while their age is between 25 and 39 years. The experimental results have shown a sensitivity to detect the fall events in real time of 100% without reporting false positives. The tests have been performed in an area where the radar's operation was not limited by practical situations, namely, signal power, coverage of the antennas, and presence of obstacles between the subject and the antennas.

Multimedia systems in ultrasound image boundary detection and measurements

NASA Astrophysics Data System (ADS)

Pathak, Sayan D.; Chalana, Vikram; Kim, Yongmin

1997-05-01

Ultrasound as a medical imaging modality offers the clinician a real-time of the anatomy of the internal organs/tissues, their movement, and flow noninvasively. One of the applications of ultrasound is to monitor fetal growth by measuring biparietal diameter (BPD) and head circumference (HC). We have been working on automatic detection of fetal head boundaries in ultrasound images. These detected boundaries are used to measure BPD and HC. The boundary detection algorithm is based on active contour models and takes 32 seconds on an external high-end workstation, SUN SparcStation 20/71. Our goal has been to make this tool available within an ultrasound machine and at the same time significantly improve its performance utilizing multimedia technology. With the advent of high- performance programmable digital signal processors (DSP), the software solution within an ultrasound machine instead of the traditional hardwired approach or requiring an external computer is now possible. We have integrated our boundary detection algorithm into a programmable ultrasound image processor (PUIP) that fits into a commercial ultrasound machine. The PUIP provides both the high computing power and flexibility needed to support computationally-intensive image processing algorithms within an ultrasound machine. According to our data analysis, BPD/HC measurements made on PUIP lie within the interobserver variability. Hence, the errors in the automated BPD/HC measurements using the algorithm are on the same order as the average interobserver differences. On PUIP, it takes 360 ms to measure the values of BPD/HC on one head image. When processing multiple head images in sequence, it takes 185 ms per image, thus enabling 5.4 BPD/HC measurements per second. Reduction in the overall execution time from 32 seconds to a fraction of a second and making this multimedia system available within an ultrasound machine will help this image processing algorithm and other computer-intensive imaging applications become a practical tool for the sonographers in the feature.

Effect of Noradrenergic Neurotoxin DSP-4 and Maprotiline on Heart Rate Spectral Components in Stressed and Resting Rats.

PubMed

Kur'yanova, E V; Zhukova, Yu D; Teplyi, D L

2017-07-01

The effects of intraperitoneal DSP-4 (N-(2-chloroethyl)-N-ethyl-2-bromobenzylamine, a noradrenergic neurotoxin) and maprotiline (an inhibitor of norepinephrine reuptake in synapses) on spectral components of heart rhythm variability were examined in outbred male and female rats treated with these agents in daily doses of 10 mg/kg for 3 days. At rest, DSP-4 elevated LF and VLF spectral components in male and female rats. Maprotiline elevated LF and VLF components in males at rest, increased HR and reduced all spectral components in resting females. Stress against the background of DSP-4 treatment sharply increased heart rate and reduced the powers of all spectral components (especially LF and VLF components). In maprotiline-treated rats, stress increased the powers of LF and VLF components. Thus, the central noradrenergic system participates in the formation of LF and VLF spectral components of heart rate variability at rest and especially during stressful stimulation, which can determine the phasic character of changes in the heart rate variability observed in stressed organism.

Design of DSP-based high-power digital solar array simulator

NASA Astrophysics Data System (ADS)

Zhang, Yang; Liu, Zhilong; Tong, Weichao; Feng, Jian; Ji, Yibo

2013-12-01

To satisfy rigid performance specifications, a feedback control was presented for zoom optical lens plants. With the increasing of global energy consumption, research of the photovoltaic(PV) systems get more and more attention. Research of the digital high-power solar array simulator provides technical support for high-power grid-connected PV systems research.This paper introduces a design scheme of the high-power digital solar array simulator based on TMS320F28335. A DC-DC full-bridge topology was used in the system's main circuit. The switching frequency of IGBT is 25kHz.Maximum output voltage is 900V. Maximum output current is 20A. Simulator can be pre-stored solar panel IV curves.The curve is composed of 128 discrete points .When the system was running, the main circuit voltage and current values was feedback to the DSP by the voltage and current sensors in real-time. Through incremental PI,DSP control the simulator in the closed-loop control system. Experimental data show that Simulator output voltage and current follow a preset solar panels IV curve. In connection with the formation of high-power inverter, the system becomes gridconnected PV system. The inverter can find the simulator's maximum power point and the output power can be stabilized at the maximum power point (MPP).

DSP-based CSO cancellation technique for RoF transmission system implemented by using directly modulated laser.

PubMed

Kim, Byung Gon; Bae, Sung Hyun; Kim, Hoon; Chung, Yun C

2017-05-29

We propose and demonstrate a simple composite second-order (CSO) cancellation technique based on the digital signal processing (DSP) for the radio-over-fiber (RoF) transmission system implemented by using directly modulated lasers (DMLs). When the RoF transmission system is implemented by using DMLs, its performance could be limited by the CSO distortions caused by the interplay between the DML's chirp and fiber's chromatic dispersion. We present the theoretical analysis of these nonlinear distortions and show that they can be suppressed at the receiver by using a simple DSP. To verify the effectiveness of the proposed technique, we demonstrate the transmission of twenty-four 100-MHz filtered orthogonal frequency-division multiplexing (f-OFDM) signals in 64 quadrature amplitude modulation (QAM) format over 20 km of the standard single-mode fiber (SSMF). The results show that, by using the proposed technique, we can suppress the CSO distortion components by >10 dB and achieve the error-vector magnitude performance better than 6% even after the 20-km long SSMF transmission.

Extraction and downstream processing of plant-derived recombinant proteins.

PubMed

Buyel, J F; Twyman, R M; Fischer, R

2015-11-01

Plants offer the tantalizing prospect of low-cost automated manufacturing processes for biopharmaceutical proteins, but several challenges must be addressed before such goals are realized and the most significant hurdles are found during downstream processing (DSP). In contrast to the standardized microbial and mammalian cell platforms embraced by the biopharmaceutical industry, there are many different plant-based expression systems vying for attention, and those with the greatest potential to provide inexpensive biopharmaceuticals are also the ones with the most significant drawbacks in terms of DSP. This is because the most scalable plant systems are based on the expression of intracellular proteins in whole plants. The plant tissue must therefore be disrupted to extract the product, challenging the initial DSP steps with an unusually high load of both particulate and soluble contaminants. DSP platform technologies can accelerate and simplify process development, including centrifugation, filtration, flocculation, and integrated methods that combine solid-liquid separation, purification and concentration, such as aqueous two-phase separation systems. Protein tags can also facilitate these DSP steps, but they are difficult to transfer to a commercial environment and more generic, flexible and scalable strategies to separate target and host cell proteins are preferable, such as membrane technologies and heat/pH precipitation. In this context, clarified plant extracts behave similarly to the feed stream from microbes or mammalian cells and the corresponding purification methods can be applied, as long as they are adapted for plant-specific soluble contaminants such as the superabundant protein RuBisCO. Plant-derived pharmaceutical proteins cannot yet compete directly with established platforms but they are beginning to penetrate niche markets that allow the beneficial properties of plants to be exploited, such as the ability to produce 'biobetters' with tailored glycans, the ability to scale up production rapidly for emergency responses and the ability to produce commodity recombinant proteins on an agricultural scale. Copyright © 2015 Elsevier Inc. All rights reserved.

Mutational analysis of a predicted double β-propeller domain of the DspA/E effector of Erwinia amylovora.

PubMed

Siamer, Sabrina; Gaubert, Stéphane; Boureau, Tristan; Brisset, Marie-Noëlle; Barny, Marie-Anne

2013-05-01

The bacterium Erwinia amylovora causes fire blight, an invasive disease that threatens apple trees, pear trees and other plants of the Rosaceae family. Erwinia amylovora pathogenicity relies on a type III secretion system and on a single effector DspA/E. This effector belongs to the widespread AvrE family of effectors whose biological function is unknown. In this manuscript, we performed a bioinformatic analysis of DspA/E- and AvrE-related effectors. Motif search identified nuclear localization signals, peroxisome targeting signals, endoplasmic reticulum membrane retention signals and leucine zipper motifs, but none of these motifs were present in all the AvrE-related effectors analysed. Protein threading analysis, however, predicted a conserved double β-propeller domain in the N-terminal part of all the analysed effector sequences. We then performed a random pentapeptide mutagenesis of DspA/E, which led to the characterization of 13 new altered proteins with a five amino acids insertion. Eight harboured the insertion inside the predicted β-propeller domain and six of these eight insertions impaired DspA/E stability or function. Conversely, the two remaining insertions generated proteins that were functional and abundantly secreted in the supernatant suggesting that these two insertions stabilized the protein. © 2013 Federation of European Microbiological Societies. Published by Blackwell Publishing Ltd. All rights reserved.

Laser Speckle Imaging of Cerebral Blood Flow

NASA Astrophysics Data System (ADS)

Luo, Qingming; Jiang, Chao; Li, Pengcheng; Cheng, Haiying; Wang, Zhen; Wang, Zheng; Tuchin, Valery V.

Monitoring the spatio-temporal characteristics of cerebral blood flow (CBF) is crucial for studying the normal and pathophysiologic conditions of brain metabolism. By illuminating the cortex with laser light and imaging the resulting speckle pattern, relative CBF images with tens of microns spatial and millisecond temporal resolution can be obtained. In this chapter, a laser speckle imaging (LSI) method for monitoring dynamic, high-resolution CBF is introduced. To improve the spatial resolution of current LSI, a modified LSI method is proposed. To accelerate the speed of data processing, three LSI data processing frameworks based on graphics processing unit (GPU), digital signal processor (DSP), and field-programmable gate array (FPGA) are also presented. Applications for detecting the changes in local CBF induced by sensory stimulation and thermal stimulation, the influence of a chemical agent on CBF, and the influence of acute hyperglycemia following cortical spreading depression on CBF are given.

Delayed sleep phase: An important circadian subtype of sleep disturbance in bipolar disorders.

PubMed

Steinan, Mette Kvisten; Morken, Gunnar; Lagerberg, Trine V; Melle, Ingrid; Andreassen, Ole A; Vaaler, Arne E; Scott, Jan

2016-02-01

Theoretical models of Bipolar Disorder (BD) highlight that sleep disturbances may be a marker of underlying circadian dysregulation. However, few studies of sleep in BD have reported on the most prevalent circadian sleep abnormality, namely Delayed Sleep Phase (DSP). A cross-sectional study of 404 adults with BD who met published clinical criteria for insomnia, hypersomnia or DSP, and who had previously participated in a study of sleep in BD using a comprehensive structured interview assessment. About 10% of BD cases with a sleep problem met criteria for a DSP profile. The DSP group was younger and had a higher mean Body Mass Index (BMI) than the other groups. Also, DSP cases were significantly more likely to be prescribed mood stabilizers and antidepressant than insomnia cases. An exploratory analysis of selected symptom item ratings indicated that DSP was significantly more likely to be associated with impaired energy and activity levels. The cross-sectional design precludes examination of longitudinal changes. DSP is identified by sleep profile, not by diagnostic criteria or objective sleep records such as actigraphy. The study uses data from a previous study to identify and examine the DSP group. The DSP group identified in this study can be differentiated from hypersomnia and insomnia groups on the basis of clinical and demographic features. The association of DSP with younger age, higher BMI and impaired energy and activity also suggest that this clinical profile may be a good proxy for underlying circadian dysregulation. Copyright © 2015 Elsevier B.V. All rights reserved.

The assessment of clinical distal symmetric polyneuropathy in type 1 diabetes: a comparison of methodologies from the Pittsburgh Epidemiology of Diabetes Complications Cohort.

PubMed

Pambianco, G; Costacou, T; Strotmeyer, Elsa; Orchard, T J

2011-05-01

Distal symmetrical polyneuropathy (DSP) is the most common type of diabetic neuropathy, but often difficult to diagnose reliably. We evaluated the cross-sectional association between three point-of-care devices, Vibratron II, NC-stat(®), and Neurometer(®), and two clinical protocols, MNSI and monofilament, in identifying those with DSP, and/or amputation/ulcer/neuropathic pain (AUP), the two outcomes of major concern. This report presents data from 195 type 1 diabetic participants of the Epidemiology of Diabetes Complications (EDC) Study attending the 18-year examination (2004-2006). Participants with physician-diagnosed DSP, AUP or who were abnormal on the NC-stat, and the Vibratron II, MNSI, and monofilament were older (p<0.05) and had a longer duration of diabetes (p < 0.05). There was no difference by sex for DSP, AUP, or any testing modality, with the exception of NCstat (motor). The Vibratron II and MNSI showed the highest sensitivity for DSP (>87%) and AUP (>80%), whereas the monofilament had the highest specificity (98% DSP, 94% AUP) and positive predictive value (89% DSP, 47% AUP), but lowest sensitivity (20% DSP, 30% AUP). The MNSI also had the highest negative predictive value (83%) and Youden's Index (37%) and currently presents the single best combination of sensitivity and specificity of DSP in type 1 diabetes. Copyright © 2011 Elsevier Ireland Ltd. All rights reserved.

The assessment of clinical distal symmetric polyneuropathy in type 1 diabetes: A comparison of methodologies from the Pittsburgh Epidemiology of Diabetes Complications Cohort

PubMed Central

Pambianco, G.; Costacou, T.; Strotmeyer, Elsa; Orchard, T.J.

2011-01-01

Distal symmetrical polyneuropathy (DSP) is the most common type of diabetic neuropathy, but often difficult to diagnose reliably. We evaluated the cross-sectional association between three point-of-care devices, Vibratron II, NC-stat®, and Neurometer®, and two clinical protocols, MNSI and monofilament, in identifying those with DSP, and/or amputation/ulcer/neuropathic pain (AUP), the two outcomes of major concern. This report presents data from 195 type 1 diabetic participants of the Epidemiology of Diabetes Complications (EDC) Study attending the 18-year examination (2004–2006). Participants with physician-diagnosed DSP, AUP or who were abnormal on the NC-stat, and the Vibratron II, MNSI, and monofilament were older (p < 0.05) and had a longer duration of diabetes (p < 0.05). There was no difference by sex for DSP, AUP, or any testing modality, with the exception of NCstat (motor). The Vibratron II and MNSI showed the highest sensitivity for DSP (>87%) and AUP (>80%), whereas the monofilament had the highest specificity (98% DSP, 94% AUP) and positive predictive value (89% DSP, 47% AUP), but lowest sensitivity (20% DSP, 30% AUP). The MNSI also had the highest negative predictive value (83%) and Youden's Index (37%) and currently presents the single best combination of sensitivity and specificity of DSP in type 1 diabetes. PMID:21411172

Expression patterns of nestin and dentin sialoprotein during dentinogenesis in mice.

PubMed

Quispe-Salcedo, Angela; Ida-Yonemochi, Hiroko; Nakatomi, Mitsushiro; Ohshima, Hayato

2012-04-01

Differentiated odontoblasts could not be identified by one unique phenotypic marker, but the combination of expression of dentin phosphoprotein (Dpp), dentin sialoprotein (Dsp), dentin matrix protein 1 (Dmp1), and nestin may be valuable for the assessment of these cells. However, the findings using these proteins remain controversial. This study aimed to compare two odontoblast differentiation markers: nestin and Dsp in the process of dentinogenesis in mice. We performed immunohistochemistry and/or in situ hybridization technique for nestin and Dsp using 3-week-old incisors as well as postnatal 1-day- to 8-week-old molars. Preodontoblasts began to express nestin and Dsp proteins and Dsp mRNA, which increased in their intensity according to the progress of odontoblast differentiation in both incisors and developing molars. Nestin was consistently expressed in the differentiated odontoblasts even after the completion of dentin matrix deposition. The expression of Dsp mRNA coincided with the odontoblast secretory activity for dentin matrix deposition. In contrast, other pulpal cells, predentin matrix and dentinal tubules also showed a positive reaction for Dsp protein in addition to differentiated odontoblasts. In conclusion, nestin is valuable as a differentiation marker for odontoblasts, whereas Dsp mRNA is a functional marker for their secretory activity.

Research on the adaptive optical control technology based on DSP

NASA Astrophysics Data System (ADS)

Zhang, Xiaolu; Xue, Qiao; Zeng, Fa; Zhao, Junpu; Zheng, Kuixing; Su, Jingqin; Dai, Wanjun

2018-02-01

Adaptive optics is a real-time compensation technique using high speed support system for wavefront errors caused by atmospheric turbulence. However, the randomness and instantaneity of atmospheric changing introduce great difficulties to the design of adaptive optical systems. A large number of complex real-time operations lead to large delay, which is an insurmountable problem. To solve this problem, hardware operation and parallel processing strategy are proposed, and a high-speed adaptive optical control system based on DSP is developed. The hardware counter is used to check the system. The results show that the system can complete a closed loop control in 7.1ms, and improve the controlling bandwidth of the adaptive optical system. Using this system, the wavefront measurement and closed loop experiment are carried out, and obtain the good results.

A multi-channel low-power system-on-chip for single-unit recording and narrowband wireless transmission of neural signal.

PubMed

Bonfanti, A; Ceravolo, M; Zambra, G; Gusmeroli, R; Spinelli, A S; Lacaita, A L; Angotzi, G N; Baranauskas, G; Fadiga, L

2010-01-01

This paper reports a multi-channel neural recording system-on-chip (SoC) with digital data compression and wireless telemetry. The circuit consists of a 16 amplifiers, an analog time division multiplexer, an 8-bit SAR AD converter, a digital signal processor (DSP) and a wireless narrowband 400-MHz binary FSK transmitter. Even though only 16 amplifiers are present in our current die version, the whole system is designed to work with 64 channels demonstrating the feasibility of a digital processing and narrowband wireless transmission of 64 neural recording channels. A digital data compression, based on the detection of action potentials and storage of correspondent waveforms, allows the use of a 1.25-Mbit/s binary FSK wireless transmission. This moderate bit-rate and a low frequency deviation, Manchester-coded modulation are crucial for exploiting a narrowband wireless link and an efficient embeddable antenna. The chip is realized in a 0.35- εm CMOS process with a power consumption of 105 εW per channel (269 εW per channel with an extended transmission range of 4 m) and an area of 3.1 × 2.7 mm(2). The transmitted signal is captured by a digital TV tuner and demodulated by a wideband phase-locked loop (PLL), and then sent to a PC via an FPGA module. The system has been tested for electrical specifications and its functionality verified in in-vivo neural recording experiments.

Software Defined Radio (SDR) and Direct Digital Synthesizer (DDS) for NMR/MRI instruments at low-field.

PubMed

Asfour, Aktham; Raoof, Kosai; Yonnet, Jean-Paul

2013-11-27

A proof-of-concept of the use of a fully digital radiofrequency (RF) electronics for the design of dedicated Nuclear Magnetic Resonance (NMR) systems at low-field (0.1 T) is presented. This digital electronics is based on the use of three key elements: a Direct Digital Synthesizer (DDS) for pulse generation, a Software Defined Radio (SDR) for a digital receiving of NMR signals and a Digital Signal Processor (DSP) for system control and for the generation of the gradient signals (pulse programmer). The SDR includes a direct analog-to-digital conversion and a Digital Down Conversion (digital quadrature demodulation, decimation filtering, processing gain…). The various aspects of the concept and of the realization are addressed with some details. These include both hardware design and software considerations. One of the underlying ideas is to enable such NMR systems to "enjoy" from existing advanced technology that have been realized in other research areas, especially in telecommunication domain. Another goal is to make these systems easy to build and replicate so as to help research groups in realizing dedicated NMR desktops for a large palette of new applications. We also would like to give readers an idea of the current trends in this field. The performances of the developed electronics are discussed throughout the paper. First FID (Free Induction Decay) signals are also presented. Some development perspectives of our work in the area of low-field NMR/MRI will be finally addressed.

High mobility group protein DSP1 negatively regulates HSP70 transcription in Crassostrea hongkongensis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Miao, Zongyu; Xu, Delin; Cui, Miao

2016-06-10

HSP70 acts mostly as a molecular chaperone and plays important roles in facilitating the folding of nascent peptides as well as the refolding or degradation of the denatured proteins. Under stressed conditions, the expression level of HSP70 is upregulated significantly and rapidly, as is known to be achieved by various regulatory factors controlling the transcriptional level. In this study, a high mobility group protein DSP1 was identified by DNA-affinity purification from the nuclear extracts of Crassostrea hongkongensis using the ChHSP70 promoter as a bait. The specific interaction between the prokaryotically expressed ChDSP1 and the FITC-labeled ChHSP70 promoter was confirmed bymore » EMSA analysis. ChDSP1 was shown to negatively regulate ChHSP70 promoter expression by Luciferase Reporter Assay in the heterologous HEK293T cells. Both ChHSP70 and ChDSP1 transcriptions were induced by either thermal or CdCl{sub 2} stress, while the accumulated expression peaks of ChDSP1 were always slightly delayed when compared with that of ChHSP70. This indicates that ChDSP1 is involved, very likely to exert its suppressive role, in the recovery of the ChHSP70 expression from the induced level to its original state. This study is the first to report negative regulator of HSP70 gene transcription, and provides novel insights into the mechanisms controlling heat shock protein expression. -- Highlights: •HMG protein ChDSP1 shows affinity to ChHSP70 promoter in Crassostrea hongkongensis. •ChDSP1 negatively regulates ChHSP70 transcription. •ChHSP70 and ChDSP1 transcriptions were coordinately induced by thermal/Cd stress. •ChDSP1 may contribute to the recovery of the induced ChHSP70 to its original state. •This is the first report regarding negative regulator of HSP70 transcription.« less

A DSP-based readout and online processing system for a new focal-plane polarimeter at AGOR

NASA Astrophysics Data System (ADS)

Hagemann, M.; Bassini, R.; van den Berg, A. M.; Ellinghaus, F.; Frekers, D.; Hannen, V. M.; Häupke, T.; Heyse, J.; Jacobs, E.; Kirsch, M.; Krüsemann, B.; Rakers, S.; Sohlbach, H.; Wörtche, H. J.

1999-11-01

A Focal-Plane Polarimeter (FPP) for the large acceptance Big-Bite Spectrometer (BBS) at AGOR using a novel readout architecture has been commissioned at the KVI Groningen. The instrument is optimized for medium-energy polarized proton scattering near or at 0°. For the handling of the high counting rates at extreme forward angles and for the suppression of small-angle scattering in the graphite analyzer, a high-performance data processing DSP system connecting to the LeCroy FERA and PCOS ECL bus architecture has been made operational and tested successfully. Details of the system and the functions of the various electronic components are described.

Expression and purification recombinant human dentin sialoprotein in Escherichia coli and its effects on human dental pulp cells.

PubMed

Yun, Ye-Rang; Kim, Hae-Won; Kang, Wonmo; Jeon, Eunyi; Lee, Sujin; Lee, Hye-Young; Kim, Cheol-Hwan; Jang, Jun-Hyeog

2012-05-01

Dentin sialoprotein (DSP) is cleaved from dentin sialophosphoprotein (DSPP) and most abundant dentinal non-collagenous proteins in dentin. DSP is believed to participate in differentiation and mineralization of cells. In this study, we first constructed recombinant human DSP (rhDSP) in Escherichia coli (E. coli) and investigated its odontoblastic differentiation effects on human dental pulp cells (hDPCs). Cell adhesion activity was measured by crystal violet assay and cell proliferation activity was measured by MTT assay. To assess mineralization activity of rhDSP, Alizarin Red S staining was performed. In addition, the mRNA levels of collagen type І (Col І), alkaline phosphatase (ALP), and osteocalcin (OCN) were measured due to their use as mineralization markers for odontoblast-/osteoblast-like differentiation of hDPCs. The obtained rhDSP in E. coli was approximately identified by SDS-PAGE and Western blot. Initially, rhDSP significantly enhanced hDPCs adhesion activity and proliferation (p<0.05). In Alizarin Red S staining, stained hDPCs increased in a time-dependent manner. This odontoblastic differentiation activity was also verified through mRNA levels of odontoblast-related markers. Here, we first demonstrated that rhDSP may be an important regulatory ECM in determining the hDPCs fate including cell adhesion, proliferation, and odontoblastic differentiation activity. These findings indicate that rhDSP can induce growth and differentiation on hDPCs, leading to improve tooth repair and regeneration. Copyright © 2012 Elsevier Inc. All rights reserved.

The design of multi-core DSP parallel model based on message passing and multi-level pipeline

NASA Astrophysics Data System (ADS)

Niu, Jingyu; Hu, Jian; He, Wenjing; Meng, Fanrong; Li, Chuanrong

2017-10-01

Currently, the design of embedded signal processing system is often based on a specific application, but this idea is not conducive to the rapid development of signal processing technology. In this paper, a parallel processing model architecture based on multi-core DSP platform is designed, and it is mainly suitable for the complex algorithms which are composed of different modules. This model combines the ideas of multi-level pipeline parallelism and message passing, and summarizes the advantages of the mainstream model of multi-core DSP (the Master-Slave model and the Data Flow model), so that it has better performance. This paper uses three-dimensional image generation algorithm to validate the efficiency of the proposed model by comparing with the effectiveness of the Master-Slave and the Data Flow model.

Real-time multi-DSP control of three-phase current-source unity power factor PWM rectifier

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xiao Wang; Boon-Teck Ooi

1993-07-01

The design of a real-time multi-DSP controller for a high-quality six-valve three-phase current-source unity power factor PWM rectifier is discussed in this paper. With the decoupler preprocessor and the dynamic trilogic PWM trigger scheme, each of the three input currents can be controlled independently. Based on the a-b-c frame system model and the fast parallel computer control, the pole-placement control method is implemented successfully to achieve fast response in the ac currents. The low-frequency resonance in the ac filter L-C networks has been damped effectively. The experimental results are obtained from a 1-kVA bipolar transistor current-source PWM rectifier with amore » real-time controller using three TMS320C25 DSP's.« less

Introduction to the Special Issue on Digital Signal Processing in Radio Astronomy

NASA Astrophysics Data System (ADS)

Price, D. C.; Kocz, J.; Bailes, M.; Greenhill, L. J.

2016-03-01

Advances in astronomy are intimately linked to advances in digital signal processing (DSP). This special issue is focused upon advances in DSP within radio astronomy. The trend within that community is to use off-the-shelf digital hardware where possible and leverage advances in high performance computing. In particular, graphics processing units (GPUs) and field programmable gate arrays (FPGAs) are being used in place of application-specific circuits (ASICs); high-speed Ethernet and Infiniband are being used for interconnect in place of custom backplanes. Further, to lower hurdles in digital engineering, communities have designed and released general-purpose FPGA-based DSP systems, such as the CASPER ROACH board, ASTRON Uniboard, and CSIRO Redback board. In this introductory paper, we give a brief historical overview, a summary of recent trends, and provide an outlook on future directions.

Identification of two-phase flow regime based on electrical capacitance tomography and soft-sensing technique

NASA Astrophysics Data System (ADS)

Zhao, Ming-fu; Hu, Xin-Yu; Shao, Yun; Luo, Bin-bin; Wang, Xin

2008-10-01

This article analyses nowadays in common use of football robots in China, intended to improve the football robots' hardware platform system's capability, and designed a football robot which based on DSP core controller, and combined Fuzzy-PID control algorithm. The experiment showed, because of the advantages of DSP, such as quickly operation, various of interfaces, low power dissipation etc. It has great improvement on the football robot's performance of movement, controlling precision, real-time performance.

Chronic administration of DSP-7238, a novel, potent, specific and substrate-selective DPP IV inhibitor, improves glycaemic control and beta-cell damage in diabetic mice.

PubMed

Furuta, Y; Horiguchi, M; Sugaru, E; Ono-Kishino, M; Otani, M; Sakai, M; Masui, Y; Tsuchida, A; Sato, Y; Takubo, K; Hochigai, H; Kimura, H; Nakahira, H; Nakagawa, T; Taiji, M

2010-05-01

The purpose of this study is to assess the in vitro enzyme inhibition profile of DSP-7238, a novel non-cyanopyrrolidine dipeptidyl peptidase (DPP) IV inhibitor and to evaluate the acute and chronic effects of this compound on glucose metabolism in two different mouse models of type 2 diabetes. The in vitro enzyme inhibition profile of DSP-7238 was assessed using plasma and recombinant enzymes including DPP IV, DPP II, DPP8, DPP9 and fibroblast activation protein alpha (FAPalpha) with fluorogenic substrates. The inhibition type was evaluated based on the Lineweaver-Burk plot. Substrate selectivity of DSP-7238 and comparator DPP IV inhibitors (vildagliptin, sitagliptin, saxagliptin and linagliptin) was evaluated by mass spectrometry based on the changes in molecular weight of peptide substrates caused by release of N-terminal dipeptides. In the in vivo experiments, high-fat diet-induced obese (DIO) mice were subjected to oral glucose tolerance test (OGTT) following a single oral administration of DSP-7238. To assess the chronic effects of DSP-7238 on glycaemic control and pancreatic beta-cell damage, DSP-7238 was administered for 11 weeks to mice made diabetic by a combination of high-fat diet (HFD) and a low-dose of streptozotocin (STZ). After the dosing period, HbA1c was measured and pancreatic damage was evaluated by biological and histological analyses. DSP-7238 and sitagliptin both competitively inhibited recombinant human DPP IV (rhDPP IV) with K(i) values of 0.60 and 2.1 nM respectively. Neither vildagliptin nor saxagliptin exhibited competitive inhibition of rhDPP IV. DSP-7238 did not inhibit DPP IV-related enzymes including DPP8, DPP9, DPP II and FAPalpha, whereas vildagliptin and saxagliptin showed inhibition of DPP8 and DPP9. Inhibition of glucagon-like peptide-1 (GLP-1) degradation by DSP-7238 was apparently more potent than its inhibition of chemokine (C-X-C motif) ligand 10 (IP-10) or chemokine (C-X-C motif) ligand 12 (SDF-1alpha) degradation. In contrast, vildagliptin and saxagliptin showed similar degree of inhibition of degradation for all the substrates tested. Compared to treatment with the vehicle, single oral administration of DSP-7238 dose-dependently decreased plasma DPP IV activity and improved glucose tolerance in DIO mice. In addition, DSP-7238 significantly decreased HbA1c and ameliorated pancreatic damage following 11 weeks of chronic treatment in HFD/STZ mice. We have shown in this study that DSP-7238 is a potent DPP IV inhibitor that has high specificity for DPP IV and substrate selectivity against GLP-1. We have also found that chronic treatment with DSP-7238 improves glycaemic control and ameliorates beta-cell damage in a mouse model with impaired insulin sensitivity and secretion. These findings indicate that DSP-7238 may be a new therapeutic agent for the treatment of type 2 diabetes.

Demodulator electronics for laser vibrometry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dudzik, G.; Waz, A. T.; Kaczmarek, P. R.

2012-06-13

One of the most important parts of a fiber-laser vibrometer is demodulation electronic section. The distortion, nonlinearity, offset and added noise of measured signal come from electronic circuits and they have direct influence on finale measuring results. Two main parameters of an investigated vibrating object: velocity V(t) and displacement s(t), influence of detected beat signals. They are: the Doppler frequency deviation f(t) and phase shift {phi}(t), respectively. Because of wide range of deviations it is difficult to use just one demodulator. That is the reason why we use three different types of demodulators. The first one is the IQ demodulator,more » which is the most sensitive one and its output is proportional to the displacement. Each IQ channel is sampled simultaneously by an analog to digital converter (ADC) integrated in a digital signal processor (DSP). The output signals from the two FM demodulators are proportional to the frequency deviation of heterodyne signals. They are sensitive directly to the velocity of the object. The main disadvantage of scattered light interferometry system is a ''speckle effect'', appearing in relatively large amplitude fluctuation of a heterodyne signal. To minimize ''speckle effect'' influence on quality of beat signals we applied the automatic gain control (AGC) system. Data acquisition, further signal processing (e.g. vibration frequency spectra) and presentation of results is realized by PC via USB interface.« less

Design and Implementation of Sound Searching Robots in Wireless Sensor Networks

PubMed Central

Han, Lianfu; Shen, Zhengguang; Fu, Changfeng; Liu, Chao

2016-01-01

A sound target-searching robot system which includes a 4-channel microphone array for sound collection, magneto-resistive sensor for declination measurement, and a wireless sensor networks (WSN) for exchanging information is described. It has an embedded sound signal enhancement, recognition and location method, and a sound searching strategy based on a digital signal processor (DSP). As the wireless network nodes, three robots comprise the WSN a personal computer (PC) in order to search the three different sound targets in task-oriented collaboration. The improved spectral subtraction method is used for noise reduction. As the feature of audio signal, Mel-frequency cepstral coefficient (MFCC) is extracted. Based on the K-nearest neighbor classification method, we match the trained feature template to recognize sound signal type. This paper utilizes the improved generalized cross correlation method to estimate time delay of arrival (TDOA), and then employs spherical-interpolation for sound location according to the TDOA and the geometrical position of the microphone array. A new mapping has been proposed to direct the motor to search sound targets flexibly. As the sink node, the PC receives and displays the result processed in the WSN, and it also has the ultimate power to make decision on the received results in order to improve their accuracy. The experiment results show that the designed three-robot system implements sound target searching function without collisions and performs well. PMID:27657088

Design and Implementation of Sound Searching Robots in Wireless Sensor Networks.

PubMed

Han, Lianfu; Shen, Zhengguang; Fu, Changfeng; Liu, Chao

2016-09-21

A sound target-searching robot system which includes a 4-channel microphone array for sound collection, magneto-resistive sensor for declination measurement, and a wireless sensor networks (WSN) for exchanging information is described. It has an embedded sound signal enhancement, recognition and location method, and a sound searching strategy based on a digital signal processor (DSP). As the wireless network nodes, three robots comprise the WSN a personal computer (PC) in order to search the three different sound targets in task-oriented collaboration. The improved spectral subtraction method is used for noise reduction. As the feature of audio signal, Mel-frequency cepstral coefficient (MFCC) is extracted. Based on the K-nearest neighbor classification method, we match the trained feature template to recognize sound signal type. This paper utilizes the improved generalized cross correlation method to estimate time delay of arrival (TDOA), and then employs spherical-interpolation for sound location according to the TDOA and the geometrical position of the microphone array. A new mapping has been proposed to direct the motor to search sound targets flexibly. As the sink node, the PC receives and displays the result processed in the WSN, and it also has the ultimate power to make decision on the received results in order to improve their accuracy. The experiment results show that the designed three-robot system implements sound target searching function without collisions and performs well.

1 kHz 2D Visual Motion Sensor Using 20 × 20 Silicon Retina Optical Sensor and DSP Microcontroller.

PubMed

Liu, Shih-Chii; Yang, MinHao; Steiner, Andreas; Moeckel, Rico; Delbruck, Tobi

2015-04-01

Optical flow sensors have been a long running theme in neuromorphic vision sensors which include circuits that implement the local background intensity adaptation mechanism seen in biological retinas. This paper reports a bio-inspired optical motion sensor aimed towards miniature robotic and aerial platforms. It combines a 20 × 20 continuous-time CMOS silicon retina vision sensor with a DSP microcontroller. The retina sensor has pixels that have local gain control and adapt to background lighting. The system allows the user to validate various motion algorithms without building dedicated custom solutions. Measurements are presented to show that the system can compute global 2D translational motion from complex natural scenes using one particular algorithm: the image interpolation algorithm (I2A). With this algorithm, the system can compute global translational motion vectors at a sample rate of 1 kHz, for speeds up to ±1000 pixels/s, using less than 5 k instruction cycles (12 instructions per pixel) per frame. At 1 kHz sample rate the DSP is 12% occupied with motion computation. The sensor is implemented as a 6 g PCB consuming 170 mW of power.

Development of Fast Measurement System of Neutron Emission Profile Using a Digital Signal Processing Technique in JT-60U

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ishikawa, M.; Shinohara, K.; Itoga, T.

2008-03-12

Neutron emission profiles are routinely measured in JT-60U Tokamak. Stinbene neuron detectors (SNDs), which combine a Stilbene organic crystal scintillation detector (Stilbene detector) with an analog neutron-gamma pulse shape discrimination (PSD) circuit, have been used to measure neutron flux efficiently. Although the SND has many advantages as a neutron detector, the maximum count rate is limited up to {approx}1x 10{sup 5} counts/s due to the dead time of the analog PSD circuit. To overcome this issue, a digital signal processing (DSP) system using a Flash-ADC has been developed. In this system, anode signals from the photomultiplier of the Stilbene detectormore » are fed to the Flash ADC and digitized. Then, the PSD between neutrons and gamma-rays are performed using software. The photomultiplier tube is also modified to suppress and correct gain fluctuation of the photomultiplier. The DSP system has been installed in the center channel of the vertical neutron collimator system in JT-60U and applied to measurements of neutron flux in JT-60U experiments. Neutron flux are successfully measured with count rate up to {approx}1x 10{sup 6} counts/s without the effect of pile up of detected pulses. The performance of the DSP system as a neutron detector is demonstrated.« less

A retrospective descriptive study of the characteristics of deliberate self-poisoning patients with single or repeat presentations to an Australian emergency medicine network in a one year period.

PubMed

Martin, Catherine A; Chapman, Rose; Rahman, Asheq; Graudins, Andis

2014-08-23

A proportion of deliberate self-poisoning (DSP) patients present repeatedly to the emergency department (ED). Understanding the characteristics of frequent DSP patients and their presentation is a first step to implementing interventions that are designed to prevent repeated self-poisoning. All DSP presentations to three networked Australian ED's were retrospectively identified from the ED electronic medical record and hospital scanned medical records for 2011. Demographics, types of drugs ingested, emergency department length of stay and disposition for the repeat DSP presenters were extracted and compared to those who presented once with DSP in a one year period. Logistic regression was used to analyse repeat versus single DSP data. The study determined 755 single presenters and 93 repeat DSP presenters. The repeat presenters contributed to 321 DSP presentations. They were more likely to be unemployed (61.0% versus 39.9%, p = 0.008) and have a psychiatric illness compared to single presenters (36.6% versus 15.5%, p < 0.001). Repeat presenters were less likely to receive a toxicology consultation (11.5% versus 27.3%, p < 0.001) and were more likely to abscond from the ED (7.5% versus 3.4%, p = 0.004). Repeat presenters were more likely to ingest paracetamol and antipsychotics than single presenters. The defined daily dose for the most common antipsychotic ingested, quetiapine, was less in the repeat presenter group (median 1.9 [IQR: 1.3-3.5]) compared with the single presenter group (4 [1.4-9.5]), (OR 0.85, 95% CI 0.74-0.99). Patients who present repeatedly to the ED with DSP have pre-existing disadvantages, with increased likelihood of being unemployed and having a mental illness. These patients are also more likely to have health service inequities given the greater likelihood to abscond from the ED and lower likelihood of receiving toxicology consultation for their DSP. Early recognition of repeat DSP patients in the ED may facilitate the development of individualised care plans with the aim to reduce repeat episodes of self-poisoning and subsequent risk of successful suicide.

Accuracy concerns in digital speckle photography combined with Fresnel digital holographic interferometry

NASA Astrophysics Data System (ADS)

Zhao, Yuchen; Zemmamouche, Redouane; Vandenrijt, Jean-François; Georges, Marc P.

2018-05-01

A combination of digital holographic interferometry (DHI) and digital speckle photography (DSP) allows in-plane and out-of-plane displacement measurement between two states of an object. The former can be determined by correlating the two speckle patterns whereas the latter is given by the phase difference obtained from DHI. We show that the amplitude of numerically reconstructed object wavefront obtained from Fresnel in-line digital holography (DH), in combination with phase shifting techniques, can be used as speckle patterns in DSP. The accuracy of in-plane measurement is improved after correcting the phase errors induced by reference wave during reconstruction process. Furthermore, unlike conventional imaging system, Fresnel DH offers the possibility to resize the pixel size of speckle patterns situated on the reconstruction plane under the same optical configuration simply by zero-padding the hologram. The flexibility of speckle size adjustment in Fresnel DH ensures the accuracy of estimation result using DSP.

High-Speed Data Acquisition and Digital Signal Processing System for PET Imaging Techniques Applied to Mammography

NASA Astrophysics Data System (ADS)

Martinez, J. D.; Benlloch, J. M.; Cerda, J.; Lerche, Ch. W.; Pavon, N.; Sebastia, A.

2004-06-01

This paper is framed into the Positron Emission Mammography (PEM) project, whose aim is to develop an innovative gamma ray sensor for early breast cancer diagnosis. Currently, breast cancer is detected using low-energy X-ray screening. However, functional imaging techniques such as PET/FDG could be employed to detect breast cancer and track disease changes with greater sensitivity. Furthermore, a small and less expensive PET camera can be utilized minimizing main problems of whole body PET. To accomplish these objectives, we are developing a new gamma ray sensor based on a newly released photodetector. However, a dedicated PEM detector requires an adequate data acquisition (DAQ) and processing system. The characterization of gamma events needs a free-running analog-to-digital converter (ADC) with sampling rates of more than 50 Ms/s and must achieve event count rates up to 10 MHz. Moreover, comprehensive data processing must be carried out to obtain event parameters necessary for performing the image reconstruction. A new generation digital signal processor (DSP) has been used to comply with these requirements. This device enables us to manage the DAQ system at up to 80 Ms/s and to execute intensive calculi over the detector signals. This paper describes our designed DAQ and processing architecture whose main features are: very high-speed data conversion, multichannel synchronized acquisition with zero dead time, a digital triggering scheme, and high throughput of data with an extensive optimization of the signal processing algorithms.

Low-complexity camera digital signal imaging for video document projection system

NASA Astrophysics Data System (ADS)

Hsia, Shih-Chang; Tsai, Po-Shien

2011-04-01

We present high-performance and low-complexity algorithms for real-time camera imaging applications. The main functions of the proposed camera digital signal processing (DSP) involve color interpolation, white balance, adaptive binary processing, auto gain control, and edge and color enhancement for video projection systems. A series of simulations demonstrate that the proposed method can achieve good image quality while keeping computation cost and memory requirements low. On the basis of the proposed algorithms, the cost-effective hardware core is developed using Verilog HDL. The prototype chip has been verified with one low-cost programmable device. The real-time camera system can achieve 1270 × 792 resolution with the combination of extra components and can demonstrate each DSP function.

PHOTOSENSITIVE 2,5-DISTYRYLPYRAZINE PARTICLES PRODUCED FROM RAPID EXPANSION OF SUPERCRITICAL SOLUTIONS. (R826648)

EPA Science Inventory

Solvent-free, photoreactive particles of 2,5-distyrylpyrazine (DSP) monomer were developed by rapid precipitation from an expanding supercritical chlorodifluoromethane solution. DSP polymer particles were produced by solid-state photopolymerization. DSP particles below a criti...

Design and implementation of new control room system in Damavand tokamak

NASA Astrophysics Data System (ADS)

Rasouli, H.; Zamanian, H.; Gheidi, M.; Kheiri-Fard, M.; Kouhi, A.

2017-07-01

The aim of this paper is design and implementation of an up-to-date control room. The previous control room had a lot of constraints and it was not apposite to the sophisticated diagnostic systems as well as to the modern control and multivariable systems. Although it provided the best output for the considered experiments and implementing offline algorithms among all similar plants, it needed to be developed to provide more capability for complex algorithm mechanisms and this work introduces our efforts in this area. Accordingly, four leading systems were designed and implemented, including real-time control system, online Data Acquisition System (DAS), offline DAS, monitoring and data transmission system. In the control system, three real-time control modules were established based on Digital Signal Processor (DSP). Thanks to them, implementation of the classic and linear and nonlinear intelligent controllers was possible to control the plasma position and its elongation. Also, online DAS was constructed in two modules. Using them, voltages and currents of charge for the capacitor banks and pressure of different parts in vacuum vessel were measured and monitored. Likewise, by real-time processing of the online data, the safety protocol of plant performance was accomplished. In addition, the offline DAS was organized in 13 modules based on Field Programmable Gate Array (FPGA). This system can be used for gathering all diagnostic, control, and performance data in 156 channels. Data transmission system and storing mechanism in the server was provided by data transmitting network and MDSplus standard protocol. Moreover, monitoring software was designed so that it could display the required plots for physical analyses. Taking everything into account, this new platform can improve the quality and quantity of research activities in plasma physics for Damavand tokamak.

FPGA-accelerated adaptive optics wavefront control

NASA Astrophysics Data System (ADS)

Mauch, S.; Reger, J.; Reinlein, C.; Appelfelder, M.; Goy, M.; Beckert, E.; Tünnermann, A.

2014-03-01

The speed of real-time adaptive optical systems is primarily restricted by the data processing hardware and computational aspects. Furthermore, the application of mirror layouts with increasing numbers of actuators reduces the bandwidth (speed) of the system and, thus, the number of applicable control algorithms. This burden turns out a key-impediment for deformable mirrors with continuous mirror surface and highly coupled actuator influence functions. In this regard, specialized hardware is necessary for high performance real-time control applications. Our approach to overcome this challenge is an adaptive optics system based on a Shack-Hartmann wavefront sensor (SHWFS) with a CameraLink interface. The data processing is based on a high performance Intel Core i7 Quadcore hard real-time Linux system. Employing a Xilinx Kintex-7 FPGA, an own developed PCie card is outlined in order to accelerate the analysis of a Shack-Hartmann Wavefront Sensor. A recently developed real-time capable spot detection algorithm evaluates the wavefront. The main features of the presented system are the reduction of latency and the acceleration of computation For example, matrix multiplications which in general are of complexity O(n3 are accelerated by using the DSP48 slices of the field-programmable gate array (FPGA) as well as a novel hardware implementation of the SHWFS algorithm. Further benefits are the Streaming SIMD Extensions (SSE) which intensively use the parallelization capability of the processor for further reducing the latency and increasing the bandwidth of the closed-loop. Due to this approach, up to 64 actuators of a deformable mirror can be handled and controlled without noticeable restriction from computational burdens.

Erwinia amylovora Expresses Fast and Simultaneously hrp/dsp Virulence Genes during Flower Infection on Apple Trees

PubMed Central

Pester, Doris; Milčevičová, Renáta; Schaffer, Johann; Wilhelm, Eva; Blümel, Sylvia

2012-01-01

Background Pathogen entry through host blossoms is the predominant infection pathway of the Gram-negative bacterium Erwinia amylovora leading to manifestation of the disease fire blight. Like in other economically important plant pathogens, E. amylovora pathogenicity depends on a type III secretion system encoded by hrp genes. However, timing and transcriptional order of hrp gene expression during flower infections are unknown. Methodology/Principal Findings Using quantitative real-time PCR analyses, we addressed the questions of how fast, strong and uniform key hrp virulence genes and the effector dspA/E are expressed when bacteria enter flowers provided with the full defense mechanism of the apple plant. In non-invasive bacterial inoculations of apple flowers still attached to the tree, E. amylovora activated expression of key type III secretion genes in a narrow time window, mounting in a single expression peak of all investigated hrp/dspA/E genes around 24–48 h post inoculation (hpi). This single expression peak coincided with a single depression in the plant PR-1 expression at 24 hpi indicating transient manipulation of the salicylic acid pathway as one target of E. amylovora type III effectors. Expression of hrp/dspA/E genes was highly correlated to expression of the regulator hrpL and relative transcript abundances followed the ratio: hrpA>hrpN>hrpL>dspA/E. Acidic conditions (pH 4) in flower infections led to reduced virulence/effector gene expression without the typical expression peak observed under natural conditions (pH 7). Conclusion/Significance The simultaneous expression of hrpL, hrpA, hrpN, and the effector dspA/E during early floral infection indicates that speed and immediate effector transmission is important for successful plant invasion. When this delicate balance is disturbed, e.g., by acidic pH during infection, virulence gene expression is reduced, thus partly explaining the efficacy of acidification in fire blight control on a molecular level. PMID:22412891

Expression of Mineralized Tissue Associated Proteins: Dentin Sialoprotein and Phosphophoryn in Rodent Hair Follicles

PubMed Central

Tang, Xu-na; Zhu, Ya-qin; Marcelo, Cynthia L.; Ritchie, Helena H.

2012-01-01

Background Mammalian hair development and tooth development are controlled by a series of reciprocal epithelial-mesenchymal interactions. Similar growth factors and transcription factors, such as fibroblast growth factor (FGF), sonic hedgehog homolog (SHH), bone morphogenetic proteins (BMPs) and Wnt10a, were reported to be involved in both of these interactions. Dentin sialoprotein (DSP) and phosphophoryn (PP) are the two major non-collagenous proteins secreted by odontoblasts that participate in dentin mineralization during tooth development. Because of striking similarities between tooth development and hair follicle development, we investigated whether DSP and/or PP proteins may also play a role in hair follicle development. Objective In this study, we examined the presence and location of DSP/PP proteins during hair follicle development. Methods Rat PP proteins were detected using immunohistochemical/immunofluorescent staining. DSP-PP mRNAs were detected by in situ hybridization with riboprobes. LacZ expression was detected in mouse tissues using a DSP-PP promoter-driven LUC in transgenic mice. Results We found that PP proteins and DSP-PP mRNAs are present in rat hair follicles. We also demonstrate that an 8 kb DSP-PP promoter is able to drive lacZ expression in hair follicles. Conclusion We have firmly established the presence of DSP/PP in mouse and rat hair follicles by immunohistochemical/immunofluorescent staining, in situ hybridization with riboprobes and transgenic mice studies. The expression of DSP/PP in hair follicles is the first demonstration that major mineralization proteins likely may also contribute to soft tissue development. This finding opens a new avenue for future investigations into the molecular-genetic management of soft tissue development. PMID:21908176

Expression of mineralized tissue associated proteins: dentin sialoprotein and phosphophoryn in rodent hair follicles.

PubMed

Tang, Xu-na; Zhu, Ya-qin; Marcelo, Cynthia L; Ritchie, Helena H

2011-11-01

Mammalian hair development and tooth development are controlled by a series of reciprocal epithelial-mesenchymal interactions. Similar growth factors and transcription factors, such as fibroblast growth factor (FGF), sonic hedgehog homolog (SHH), bone morphogenetic proteins (BMPs) and Wnt10a, were reported to be involved in both of these interactions. Dentin sialoprotein (DSP) and phosphophoryn (PP) are the two major non-collagenous proteins secreted by odontoblasts that participate in dentin mineralization during tooth development. Because of striking similarities between tooth development and hair follicle development, we investigated whether DSP and/or PP proteins may also play a role in hair follicle development. In this study, we examined the presence and location of DSP/PP proteins during hair follicle development. Rat PP proteins were detected using immunohistochemical/immunofluorescent staining. DSP-PP mRNAs were detected by in situ hybridization with riboprobes. LacZ expression was detected in mouse tissues using a DSP-PP promoter-driven LUC in transgenic mice. We found that PP proteins and DSP-PP mRNAs are present in rat hair follicles. We also demonstrate that an 8 kb DSP-PP promoter is able to drive lacZ expression in hair follicles. We have firmly established the presence of DSP/PP in mouse and rat hair follicles by immunohistochemical/immunofluorescent staining, in situ hybridization with riboprobes and transgenic mice studies. The expression of DSP/PP in hair follicles is the first demonstration that major mineralization proteins likely may also contribute to soft tissue development. This finding opens a new avenue for future investigations into the molecular-genetic management of soft tissue development. Copyright © 2011 Japanese Society for Investigative Dermatology. Published by Elsevier Ireland Ltd. All rights reserved.

Advanced digital signal processing for short-haul and access network

NASA Astrophysics Data System (ADS)

Zhang, Junwen; Yu, Jianjun; Chi, Nan

2016-02-01

Digital signal processing (DSP) has been proved to be a successful technology recently in high speed and high spectrum-efficiency optical short-haul and access network, which enables high performances based on digital equalizations and compensations. In this paper, we investigate advanced DSP at the transmitter and receiver side for signal pre-equalization and post-equalization in an optical access network. A novel DSP-based digital and optical pre-equalization scheme has been proposed for bandwidth-limited high speed short-distance communication system, which is based on the feedback of receiver-side adaptive equalizers, such as least-mean-squares (LMS) algorithm and constant or multi-modulus algorithms (CMA, MMA). Based on this scheme, we experimentally demonstrate 400GE on a single optical carrier based on the highest ETDM 120-GBaud PDM-PAM-4 signal, using one external modulator and coherent detection. A line rate of 480-Gb/s is achieved, which enables 20% forward-error correction (FEC) overhead to keep the 400-Gb/s net information rate. The performance after fiber transmission shows large margin for both short range and metro/regional networks. We also extend the advanced DSP for short haul optical access networks by using high order QAMs. We propose and demonstrate a high speed multi-band CAP-WDM-PON system on intensity modulation, direct detection and digital equalizations. A hybrid modified cascaded MMA post-equalization schemes are used to equalize the multi-band CAP-mQAM signals. Using this scheme, we successfully demonstrates 550Gb/s high capacity WDMPON system with 11 WDM channels, 55 sub-bands, and 10-Gb/s per user in the downstream over 40-km SMF.

An opto-electronic joint detection system based on DSP aiming at early cervical cancer screening

NASA Astrophysics Data System (ADS)

Wang, Weiya; Jia, Mengyu; Gao, Feng; Yang, Lihong; Qu, Pengpeng; Zou, Changping; Liu, Pengxi; Zhao, Huijuan

2015-02-01

The cervical cancer screening at a pre-cancer stage is beneficial to reduce the mortality of women. An opto-electronic joint detection system based on DSP aiming at early cervical cancer screening is introduced in this paper. In this system, three electrodes alternately discharge to the cervical tissue and three light emitting diodes in different wavelengths alternately irradiate the cervical tissue. Then the relative optical reflectance and electrical voltage attenuation curve are obtained by optical and electrical detection, respectively. The system is based on DSP to attain the portable and cheap instrument. By adopting the relative reflectance and the voltage attenuation constant, the classification algorithm based on Support Vector Machine (SVM) discriminates abnormal cervical tissue from normal. We use particle swarm optimization to optimize the two key parameters of SVM, i.e. nuclear factor and cost factor. The clinical data were collected on 313 patients to build a clinical database of tissue responses under optical and electrical stimulations with the histopathologic examination as the gold standard. The classification result shows that the opto-electronic joint detection has higher total coincidence rate than separate optical detection or separate electrical detection. The sensitivity, specificity, and total coincidence rate increase with the increasing of sample numbers in the training set. The average total coincidence rate of the system can reach 85.1% compared with the histopathologic examination.

Current signature sensor

NASA Technical Reports Server (NTRS)

Perotti, Jose M. (Inventor); Lucena, Angel (Inventor); Ihlefeld, Curtis (Inventor); Burns, Bradley (Inventor); Bassignani, Karin E. (Inventor)

2005-01-01

A solenoid health monitoring system uses a signal conditioner and controller assembly in one embodiment that includes analog circuitry and a DSP controller. The analog circuitry provides signal conditioning to the low-level raw signal coming from a signal acquisition assembly. Software running in a DSP analyzes the incoming data (recorded current signature) and determines the state of the solenoid whether it is energized, de-energized, or in a transitioning state. In one embodiment, the software identifies key features in the current signature during the transition phase and is able to determine the health of the solenoid.

Shared performance monitor in a multiprocessor system

DOEpatents

Chiu, George; Gara, Alan G.; Salapura, Valentina

2012-07-24

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU comprises: a plurality of performance counters each for counting signals representing occurrences of events from one or more the plurality of processor units in the multiprocessor system; and, a plurality of input devices for receiving the event signals from one or more processor devices of the plurality of processor units, the plurality of input devices programmable to select event signals for receipt by one or more of the plurality of performance counters for counting, wherein the PMU is shared between multiple processing units, or within a group of processors in the multiprocessing system. The PMU is further programmed to monitor event signals issued from non-processor devices.

Effects of methylphenidate on attention in Wistar rats treated with the neurotoxin N-(2-chloroethyl)-N-ethyl-2-bromobenzylamine (DSP4).

PubMed

Hauser, Joachim; Reissmann, Andreas; Sontag, Thomas-A; Tucha, Oliver; Lange, Klaus W

2017-05-01

The aim of this study was to assess the effects of the neurotoxin N-(2-chloroethyl)-N-ethyl-2-bromobenzylamine (DSP4) on attention in rats as measured using the 5-choice-serial-reaction-time task (5CSRTT) and to investigate whether methylphenidate has effects on DSP4-treated rats. Methylphenidate is a noradrenaline and dopamine reuptake inhibitor and commonly used in the pharmacological treatment of individuals with attention deficit/hyperactivity disorder (ADHD). Wistar rats were trained in the 5CSRTT and treated with one of three doses of DSP4 or saline. Following the DSP4 treatment rats were injected with three doses of methylphenidate or saline and again tested in the 5CSRTT. The treatment with DSP4 caused a significant decline of performance in the number of correct responses and a decrease in response accuracy. A reduction in activity could also be observed. Whether or not the cognitive impairments are due to attention deficits or changes in explorative behaviour or activity remains to be investigated. The treatment with methylphenidate had no beneficial effect on the rats' performance regardless of the DSP4 treatment. In the group without DSP4 treatment, methylphenidate led to a reduction in response accuracy and bidirectional effects in regard to parameters related to attention. These findings support the role of noradrenaline in modulating attention and call for further investigations concerning the effects of methylphenidate on attentional processes in rats.

Low cost coherent demodulation for mobile satellite terminals

NASA Technical Reports Server (NTRS)

Dutta, Santanu; Henely, Steven J.

1993-01-01

This paper describes some low cost approaches to coherent BPSK demodulation for mobile satellite receivers. The specific application is an Inmarsat-C Land Mobile Earth Station (LMES), but the techniques are applicable to any PSK demodulator. The techniques discussed include combined sampling and quadrature downconversion with a single A/D and novel DSP algorithms for carrier acquisition offering both superior performance and economy of DSP resources. The DSP algorithms run at 5.7 MIPS, and the entire DSP subsystem, built with commercially available parts, costs under $60 at quantity-10,000.

Dominant de novo DSP mutations cause erythrokeratodermia-cardiomyopathy syndrome

PubMed Central

Boyden, Lynn M.; Kam, Chen Y.; Hernández-Martín, Angela; Zhou, Jing; Craiglow, Brittany G.; Sidbury, Robert; Mathes, Erin F.; Maguiness, Sheilagh M.; Crumrine, Debra A.; Williams, Mary L.; Hu, Ronghua; Lifton, Richard P.; Elias, Peter M.; Green, Kathleen J.; Choate, Keith A.

2016-01-01

Disorders of keratinization (DOK) show marked genotypic and phenotypic heterogeneity. In most cases, disease is primarily cutaneous, and further clinical evaluation is therefore rarely pursued. We have identified subjects with a novel DOK featuring erythrokeratodermia and initially-asymptomatic, progressive, potentially fatal cardiomyopathy, a finding not previously associated with erythrokeratodermia. We show that de novo missense mutations clustered tightly within a single spectrin repeat of DSP cause this novel cardio-cutaneous disorder, which we term erythrokeratodermia-cardiomyopathy (EKC) syndrome. We demonstrate that DSP mutations in our EKC syndrome subjects affect localization of desmosomal proteins and connexin 43 in the skin, and result in desmosome aggregation, widening of intercellular spaces, and lipid secretory defects. DSP encodes desmoplakin, a primary component of desmosomes, intercellular adhesion junctions most abundant in the epidermis and heart. Though mutations in DSP are known to cause other disorders, our cohort features the unique clinical finding of severe whole-body erythrokeratodermia, with distinct effects on localization of desmosomal proteins and connexin 43. These findings add a severe, previously undescribed syndrome featuring erythrokeratodermia and cardiomyopathy to the spectrum of disease caused by mutation in DSP, and identify a specific region of the protein critical to the pathobiology of EKC syndrome and to DSP function in the heart and skin. PMID:26604139

Ectopic expression of dentin sialoprotein during amelogenesis hardens bulk enamel.

PubMed

White, Shane N; Paine, Michael L; Ngan, Amanda Y W; Miklus, Vetea G; Luo, Wen; Wang, HongJun; Snead, Malcolm L

2007-02-23

Dentin sialophosphpoprotein (Dspp) is transiently expressed in the early stage of secretory ameloblasts. The secretion of ameloblast-derived Dspp is short-lived, correlates to the establishment of the dentinoenamel junction (DEJ), and is consistent with Dspp having a role in producing the specialized first-formed harder enamel adjacent to the DEJ. Crack diffusion by branching and dissipation within this specialized first-formed enamel close to the DEJ prevents catastrophic interfacial damage and tooth failure. Once Dspp is secreted, it is subjected to proteolytic cleavage that results in two distinct proteins referred to as dentin sialoprotein (Dsp) and dentin phosphoprotein (Dpp). The purpose of this study was to investigate the biological and mechanical contribution of Dsp and Dpp to enamel formation. Transgenic mice were engineered to overexpress either Dsp or Dpp in their enamel organs. The mechanical properties (hardness and toughness) of the mature enamel of transgenic mice were compared with genetically matched and age-matched nontransgenic animals. Dsp and Dpp contributions to enamel formation greatly differed. The inclusion of Dsp in bulk enamel significantly and uniformly increased enamel hardness (20%), whereas the inclusion of Dpp weakened the bulk enamel. Thus, Dsp appears to make a unique contribution to the physical properties of the DEJ. Dsp transgenic animals have been engineered with superior enamel mechanical properties.

A retrospective descriptive study of the characteristics of deliberate self-poisoning patients with single or repeat presentations to an Australian emergency medicine network in a one year period

PubMed Central

2014-01-01

Background A proportion of deliberate self-poisoning (DSP) patients present repeatedly to the emergency department (ED). Understanding the characteristics of frequent DSP patients and their presentation is a first step to implementing interventions that are designed to prevent repeated self-poisoning. Methods All DSP presentations to three networked Australian ED’s were retrospectively identified from the ED electronic medical record and hospital scanned medical records for 2011. Demographics, types of drugs ingested, emergency department length of stay and disposition for the repeat DSP presenters were extracted and compared to those who presented once with DSP in a one year period. Logistic regression was used to analyse repeat versus single DSP data. Results The study determined 755 single presenters and 93 repeat DSP presenters. The repeat presenters contributed to 321 DSP presentations. They were more likely to be unemployed (61.0% versus 39.9%, p = 0.008) and have a psychiatric illness compared to single presenters (36.6% versus 15.5%, p < 0.001). Repeat presenters were less likely to receive a toxicology consultation (11.5% versus 27.3%, p < 0.001) and were more likely to abscond from the ED (7.5% versus 3.4%, p = 0.004). Repeat presenters were more likely to ingest paracetamol and antipsychotics than single presenters. The defined daily dose for the most common antipsychotic ingested, quetiapine, was less in the repeat presenter group (median 1.9 [IQR: 1.3-3.5]) compared with the single presenter group (4 [1.4-9.5]), (OR 0.85, 95% CI 0.74-0.99). Conclusion Patients who present repeatedly to the ED with DSP have pre-existing disadvantages, with increased likelihood of being unemployed and having a mental illness. These patients are also more likely to have health service inequities given the greater likelihood to abscond from the ED and lower likelihood of receiving toxicology consultation for their DSP. Early recognition of repeat DSP patients in the ED may facilitate the development of individualised care plans with the aim to reduce repeat episodes of self-poisoning and subsequent risk of successful suicide. PMID:25148692

Pre-Hardware Optimization and Implementation Of Fast Optics Closed Control Loop Algorithms

NASA Technical Reports Server (NTRS)

Kizhner, Semion; Lyon, Richard G.; Herman, Jay R.; Abuhassan, Nader

2004-01-01

One of the main heritage tools used in scientific and engineering data spectrum analysis is the Fourier Integral Transform and its high performance digital equivalent - the Fast Fourier Transform (FFT). The FFT is particularly useful in two-dimensional (2-D) image processing (FFT2) within optical systems control. However, timing constraints of a fast optics closed control loop would require a supercomputer to run the software implementation of the FFT2 and its inverse, as well as other image processing representative algorithm, such as numerical image folding and fringe feature extraction. A laboratory supercomputer is not always available even for ground operations and is not feasible for a night project. However, the computationally intensive algorithms still warrant alternative implementation using reconfigurable computing technologies (RC) such as Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGA), which provide low cost compact super-computing capabilities. We present a new RC hardware implementation and utilization architecture that significantly reduces the computational complexity of a few basic image-processing algorithm, such as FFT2, image folding and phase diversity for the NASA Solar Viewing Interferometer Prototype (SVIP) using a cluster of DSPs and FPGAs. The DSP cluster utilization architecture also assures avoidance of a single point of failure, while using commercially available hardware. This, combined with the control algorithms pre-hardware optimization, or the first time allows construction of image-based 800 Hertz (Hz) optics closed control loops on-board a spacecraft, based on the SVIP ground instrument. That spacecraft is the proposed Earth Atmosphere Solar Occultation Imager (EASI) to study greenhouse gases CO2, C2H, H2O, O3, O2, N2O from Lagrange-2 point in space. This paper provides an advanced insight into a new type of science capabilities for future space exploration missions based on on-board image processing for control and for robotics missions using vision sensors. It presents a top-level description of technologies required for the design and construction of SVIP and EASI and to advance the spatial-spectral imaging and large-scale space interferometry science and engineering.

Low-Cutoff, High-Pass Digital Filtering of Neural Signals

NASA Technical Reports Server (NTRS)

Mojarradi,Mohammad; Johnson, Travis; Ortiz, Monico; Cunningham, Thomas; Andersen, Richard

2004-01-01

The figure depicts the major functional blocks of a system, now undergoing development, for conditioning neural signals acquired by electrodes implanted in a brain. The overall functions to be performed by this system can be summarized as preamplification, multiplexing, digitization, and high-pass filtering. Other systems under development for recording neural signals typically contain resistor-capacitor analog low-pass filters characterized by cutoff frequencies in the vicinity of 100 Hz. In the application for which this system is being developed, there is a requirement for a cutoff frequency of 5 Hz. Because the resistors needed to obtain such a low cutoff frequency would be impractically large, it was decided to perform low-pass filtering by use of digital rather than analog circuitry. In addition, it was decided to timemultiplex the digitized signals from the multiple input channels into a single stream of data in a single output channel. The signal in each input channel is first processed by a preamplifier having a voltage gain of approximately 50. Embedded in each preamplifier is a low-pass anti-aliasing filter having a cutoff frequency of approximately 10 kHz. The anti-aliasing filters make it possible to couple the outputs of the preamplifiers to the input ports of a multiplexer. The output of the multiplexer is a single stream of time-multiplexed samples of analog signals. This stream is processed by a main differential amplifier, the output of which is sent to an analog-to-digital converter (ADC). The output of the ADC is sent to a digital signal processor (DSP).

Multi-Core Processor Memory Contention Benchmark Analysis Case Study

NASA Technical Reports Server (NTRS)

Simon, Tyler; McGalliard, James

2009-01-01

Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

Enhanced ground bounce noise reduction in a low-leakage CMOS multiplier

NASA Astrophysics Data System (ADS)

Verma, Bipin Kumar; Akashe, Shyam; Sharma, Sanjay

2015-09-01

In this paper, various parameters are used to reduce leakage power, leakage current and noise margin of circuits to enhance their performance. A multiplier is proposed with low-leakage current and low ground bounce noise for the microprocessor, digital signal processors (DSP) and graphics engines. The ground bounce noise problem appears when a conventional power-gating circuit transits from sleep-to-active mode. This paper discusses a reduction in leakage current in the stacking power-gating technique by three modes - sleep, active and sleep-to-active. The simulation results are performed on a 4 × 4 carry-save multiplier for leakage current, active power, leakage power and ground bounce noise, and comparison made for different nanoscales. Ground bounce noise is limited to 90%. The leakage current of the circuit is decimated up to 80% and the active power is reduced to 31%. We performed simulations using cadence virtuoso 180 and 45 nm at room temperature at various supply voltages.

Methods and systems for providing reconfigurable and recoverable computing resources

NASA Technical Reports Server (NTRS)

Stange, Kent (Inventor); Hess, Richard (Inventor); Kelley, Gerald B (Inventor); Rogers, Randy (Inventor)

2010-01-01

A method for optimizing the use of digital computing resources to achieve reliability and availability of the computing resources is disclosed. The method comprises providing one or more processors with a recovery mechanism, the one or more processors executing one or more applications. A determination is made whether the one or more processors needs to be reconfigured. A rapid recovery is employed to reconfigure the one or more processors when needed. A computing system that provides reconfigurable and recoverable computing resources is also disclosed. The system comprises one or more processors with a recovery mechanism, with the one or more processors configured to execute a first application, and an additional processor configured to execute a second application different than the first application. The additional processor is reconfigurable with rapid recovery such that the additional processor can execute the first application when one of the one more processors fails.

Coding, testing and documentation of processors for the flight design system

NASA Technical Reports Server (NTRS)

1980-01-01

The general functional design and implementation of processors for a space flight design system are briefly described. Discussions of a basetime initialization processor; conic, analytical, and precision coasting flight processors; and an orbit lifetime processor are included. The functions of several utility routines are also discussed.

Shared performance monitor in a multiprocessor system

DOEpatents

Chiu, George; Gara, Alan G; Salapura, Valentina

2014-12-02

A performance monitoring unit (PMU) and method for monitoring performance of events occurring in a multiprocessor system. The multiprocessor system comprises a plurality of processor devices units, each processor device for generating signals representing occurrences of events in the processor device, and, a single shared counter resource for performance monitoring. The performance monitor unit is shared by all processor cores in the multiprocessor system. The PMU is further programmed to monitor event signals issued from non-processor devices.

Systems design study of the Pioneer Venus spacecraft. Appendices to volume 1, sections 8-11 (part 3 of 3). [power subsystem/cost tradeoffs for Venus probe

NASA Technical Reports Server (NTRS)

1973-01-01

Power subsystem cost/weight tradeoffs are discussed for the Venus probe spacecraft. The cost estimations of power subsystem units were based upon DSCS-2, DSP, and Pioneer 10 and 11 hardware design and development and manufacturing experience. Parts count and degree of modification of existing hardware were factored into the estimate of manufacturing and design and development costs. Cost data includes sufficient quantities of units to equip probe bus and orbiter versions. It was based on the orbiter complement of equipment, but the savings in fewer slices for the probe bus balance the cost of the different probe bus battery. The preferred systems for the Thor/Delta and for the Atlas/Centaur are discussed. The weights of the candidate designs were based upon slice or tray weights for functionally equivalent circuitry measured on existing hardware such as Pioneers 10 and 11, Intelsat 3, DSCS-2, or DSP programs. Battery weights were based on measured cell weight data adjusted for case weight or off-the-shelf battery weights. The solar array weight estimate was based upon recent hardware experience on DSCS-2 and DSP arrays.

Performance evaluation of the QIAGEN EZ1 DSP Virus Kit with Abbott RealTime HIV-1, HBV and HCV assays.

PubMed

Schneider, George J; Kuper, Kevin G; Abravaya, Klara; Mullen, Carolyn R; Schmidt, Marion; Bunse-Grassmann, Astrid; Sprenger-Haussels, Markus

2009-04-01

Automated sample preparation systems must meet the demands of routine diagnostics laboratories with regard to performance characteristics and compatibility with downstream assays. In this study, the performance of QIAGEN EZ1 DSP Virus Kit on the BioRobot EZ1 DSP was evaluated in combination with the Abbott RealTime HIV-1, HCV, and HBV assays, followed by thermalcycling and detection on the Abbott m2000rt platform. The following performance characteristics were evaluated: linear range and precision, sensitivity, cross-contamination, effects of interfering substances and correlation. Linearity was observed within the tested ranges (for HIV-1: 2.0-6.0 log copies/ml, HCV: 1.3-6.9 log IU/ml, HBV: 1.6-7.6 log copies/ml). Excellent precision was obtained (inter-assay standard deviation for HIV-1: 0.06-0.17 log copies/ml (>2.17 log copies/ml), HCV: 0.05-0.11 log IU/ml (>2.09 log IU/ml), HBV: 0.03-0.07 log copies/ml (>2.55 log copies/ml)), with good sensitivity (95% hit rates for HIV-1: 50 copies/ml, HCV: 12.5 IU/ml, HBV: 10 IU/ml). No cross-contamination was observed, as well as no negative impact of elevated levels of various interfering substances. In addition, HCV and HBV viral load measurements after BioRobot EZ1 DSP extraction correlated well with those obtained after Abbott m2000sp extraction. This evaluation demonstrates that the QIAGEN EZ1 DSP Virus Kit provides an attractive solution for fully automated, low throughput sample preparation for use with the Abbott RealTime HIV-1, HCV, and HBV assays.

An advanced real-time digital signal processing system for linear systems emulation, with special emphasis on network and acoustic response characterization

NASA Astrophysics Data System (ADS)

Gaydecki, Patrick; Fernandes, Bosco

2003-11-01

A fast digital signal processing (DSP) system is described that can perform real-time emulation of a wide variety of linear audio-bandwidth systems and networks, such as reverberant spaces, musical instrument bodies and very high order filter networks. The hardware design is based upon a Motorola DSP56309 operating at 110 million multiplication-accumulations per second and a dual-channel 24 bit codec with a maximum sampling frequency of 192 kHz. High level software has been developed to express complex vector frequency responses as both infinite impulse response (IIR) and finite impulse response (FIR) coefficients, in a form suitable for real-time convolution by the firmware installed in the DSP system memory. An algorithm has also been devised to express IIR filters as equivalent FIR structures, thereby obviating the potential instabilities associated with recursive equations and negating the traditional deficiencies of FIR filters respecting equivalent analogue designs. The speed and dynamic range of the system is such that, when sampling at 48 kHz, the frequency response can be specified to a spectral precision of 22 Hz when sampling at 10 kHz, this resolution increases to 0.9 Hz. Moreover, it is also possible to control the phase of any frequency band with a theoretical precision of 10-5 degrees in all cases. The system has been applied in the study of analogue filter networks, real-time Hilbert transformation, phase-shift systems and musical instrument body emulation, where it is providing valuable new insights into the understanding of psychoacoustic mechanisms.

Technicians listen to instructions during STS-44 DSP / IUS transfer operation

NASA Technical Reports Server (NTRS)

1991-01-01

Clean-suited technicians, wearing headsets, listen to instructions during Defense Support Program (DSP) satellite / inertial upper stage (IUS) transfer operations in a processing facility at Cape Canaveral Air Force Station. In the background, the DSP satellite atop an inertial upper stage (IUS) is readied for transfer to a payload canister transporter. DSP, a surveillance satellite that can detect missle and space launches as well as nuclear detonations will be boosted into geosynchronous Earth orbit by the IUS during STS-44 mission. View provided by the Kennedy Space Center (KSC) with alternate number KSC-91PC-1748.

Dominant de novo DSP mutations cause erythrokeratodermia-cardiomyopathy syndrome.

PubMed

Boyden, Lynn M; Kam, Chen Y; Hernández-Martín, Angela; Zhou, Jing; Craiglow, Brittany G; Sidbury, Robert; Mathes, Erin F; Maguiness, Sheilagh M; Crumrine, Debra A; Williams, Mary L; Hu, Ronghua; Lifton, Richard P; Elias, Peter M; Green, Kathleen J; Choate, Keith A

2016-01-15

Disorders of keratinization (DOK) show marked genotypic and phenotypic heterogeneity. In most cases, disease is primarily cutaneous, and further clinical evaluation is therefore rarely pursued. We have identified subjects with a novel DOK featuring erythrokeratodermia and initially-asymptomatic, progressive, potentially fatal cardiomyopathy, a finding not previously associated with erythrokeratodermia. We show that de novo missense mutations clustered tightly within a single spectrin repeat of DSP cause this novel cardio-cutaneous disorder, which we term erythrokeratodermia-cardiomyopathy (EKC) syndrome. We demonstrate that DSP mutations in our EKC syndrome subjects affect localization of desmosomal proteins and connexin 43 in the skin, and result in desmosome aggregation, widening of intercellular spaces, and lipid secretory defects. DSP encodes desmoplakin, a primary component of desmosomes, intercellular adhesion junctions most abundant in the epidermis and heart. Though mutations in DSP are known to cause other disorders, our cohort features the unique clinical finding of severe whole-body erythrokeratodermia, with distinct effects on localization of desmosomal proteins and connexin 43. These findings add a severe, previously undescribed syndrome featuring erythrokeratodermia and cardiomyopathy to the spectrum of disease caused by mutation in DSP, and identify a specific region of the protein critical to the pathobiology of EKC syndrome and to DSP function in the heart and skin. © The Author 2015. Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oup.com.

Modeling heterogeneous processor scheduling for real time systems

NASA Technical Reports Server (NTRS)

Leathrum, J. F.; Mielke, R. R.; Stoughton, J. W.

1994-01-01

A new model is presented to describe dataflow algorithms implemented in a multiprocessing system. Called the resource/data flow graph (RDFG), the model explicitly represents cyclo-static processor schedules as circuits of processor arcs which reflect the order that processors execute graph nodes. The model also allows the guarantee of meeting hard real-time deadlines. When unfolded, the model identifies statically the processor schedule. The model therefore is useful for determining the throughput and latency of systems with heterogeneous processors. The applicability of the model is demonstrated using a space surveillance algorithm.

Servomotor and Controller Having Large Dynamic Range

NASA Technical Reports Server (NTRS)

Alhorn, Dean C.; Howard, David E.; Smith, Dennis A.; Dutton, Ken; Paulson, M. Scott

2007-01-01

A recently developed micro-commanding rotational-position-control system offers advantages of less mechanical complexity, less susceptibility to mechanical resonances, less power demand, less bulk, less weight, and lower cost, relative to prior rotational-position-control systems based on stepping motors and gear drives. This system includes a digital-signal- processor (DSP)-based electronic controller, plus a shaft-angle resolver and a servomotor mounted on the same shaft. Heretofore, micro-stepping has usually been associated with stepping motors, but in this system, the servomotor is micro-commanded in response to rotational-position feedback from the shaft-angle resolver. The shaft-angle resolver is of a four-speed type chosen because it affords four times the resolution of a single-speed resolver. A key innovative aspect of this system is its position-feedback signal- conditioning circuits, which condition the resolver output signal for multiple ranges of rotational speed. In the preferred version of the system, two rotational- speed ranges are included, but any number of ranges could be added to expand the speed range or increase resolution in particular ranges. In the preferred version, the resolver output is conditioned with two resolver-to-digital converters (RDCs). One RDC is used for speeds from 0.00012 to 2.5 rpm; the other RDC is used for speeds of 2.5 to 6,000 rpm. For the lower speed range, the number of discrete steps of RDC output per revolution was set at 262,144 (4 quadrants at 16 bits per quadrant). For the higher speed range, the number of discrete steps per revolution was set at 4,096 (4 quadrants at 10 bits per quadrant).

Design and evaluation of online arithmetic for signal processing applications on FPGAs

NASA Astrophysics Data System (ADS)

Galli, Reto; Tenca, Alexandre F.

2001-11-01

This paper shows the design and the evaluation of on-line arithmetic modules for the most common operators used in DSP applications, using FPGAs as the target technology. The designs are highly optimized for the target technology and the common range of precision in DSP. The results are based on experimental data collected using CAD tools. All designs are synthesized for the same type of devices (Xilinx XC4000) for comparison, avoiding rough estimates of the system performance, and generating a more reliable and detailed comparison of on-line signal processing solutions with other state of the art approaches, such as distributed arithmetic. We show that on-line designs have a hard stand for basic DSP applications that use only addition and multiplication. However, we also show that on-line designs are able to overtake other approaches as the applications become more sophisticated, e.g. when data dependencies exist, or when non constant multiplicands restrict the use of other approaches.

Video Guidance Sensor and Time-of-Flight Rangefinder

NASA Technical Reports Server (NTRS)

Bryan, Thomas; Howard, Richard; Bell, Joseph L.; Roe, Fred D.; Book, Michael L.

2007-01-01

A proposed video guidance sensor (VGS) would be based mostly on the hardware and software of a prior Advanced VGS (AVGS), with some additions to enable it to function as a time-of-flight rangefinder (in contradistinction to a triangulation or image-processing rangefinder). It would typically be used at distances of the order of 2 or 3 kilometers, where a typical target would appear in a video image as a single blob, making it possible to extract the direction to the target (but not the orientation of the target or the distance to the target) from a video image of light reflected from the target. As described in several previous NASA Tech Briefs articles, an AVGS system is an optoelectronic system that provides guidance for automated docking of two vehicles. In the original application, the two vehicles are spacecraft, but the basic principles of design and operation of the system are applicable to aircraft, robots, objects maneuvered by cranes, or other objects that may be required to be aligned and brought together automatically or under remote control. In a prior AVGS system of the type upon which the now-proposed VGS is largely based, the tracked vehicle is equipped with one or more passive targets that reflect light from one or more continuous-wave laser diode(s) on the tracking vehicle, a video camera on the tracking vehicle acquires images of the targets in the reflected laser light, the video images are digitized, and the image data are processed to obtain the direction to the target. The design concept of the proposed VGS does not call for any memory or processor hardware beyond that already present in the prior AVGS, but does call for some additional hardware and some additional software. It also calls for assignment of some additional tasks to two subsystems that are parts of the prior VGS: a field-programmable gate array (FPGA) that generates timing and control signals, and a digital signal processor (DSP) that processes the digitized video images. The additional timing and control signals generated by the FPGA would cause the VGS to alternate between an imaging (direction-finding) mode and a time-of-flight (range-finding mode) and would govern operation in the range-finding mode.

Profiling of Extracellular Toxins Associated with Diarrhetic Shellfish Poison in Prorocentrum lima Culture Medium by High-Performance Liquid Chromatography Coupled with Mass Spectrometry

PubMed Central

Pan, Lei; Chen, Junhui; Shen, Huihui; He, Xiuping; Li, Guangjiu; Song, Xincheng; Zhou, Deshan; Sun, Chengjun

2017-01-01

Extracellular toxins released by marine toxigenic algae into the marine environment have attracted increasing attention in recent years. In this study, profiling, characterization and quantification of extracellular toxin compounds associated with diarrhetic shellfish poison (DSP) in the culture medium of toxin-producing dinoflagellates were performed using high-performance liquid chromatography–high-resolution mass spectrometry/tandem mass spectrometry for the first time. Results showed that solid-phase extraction can effectively enrich and clean the DSP compounds in the culture medium of Prorocentrum lima (P. lima), and the proposed method achieved satisfactory recoveries (94.80%–100.58%) and repeatability (relative standard deviation ≤9.27%). Commercial software associated with the accurate mass information of known DSP toxins and their derivatives was used to screen and identify DSP compounds. Nine extracellular DSP compounds were identified, of which seven toxins (including OA-D7b, OA-D9b, OA-D10a/b, and so on) were found in the culture medium of P. lima for the first time. The results of quantitative analysis showed that the contents of extracellular DSP compounds in P. lima culture medium were relatively high, and the types and contents of intracellular and extracellular toxins apparently varied in the different growth stages of P. lima. The concentrations of extracellular okadaic acid and dinophysistoxin-1 were within 19.9–34.0 and 15.2–27.9 μg/L, respectively. The total concentration of the DSP compounds was within the range of 57.70–79.63 μg/L. The results showed that the proposed method is an effective tool for profiling the extracellular DSP compounds in the culture medium of marine toxigenic algae. PMID:28974018

Combined effects of dentin sialoprotein and bone morphogenetic protein-2 on differentiation in human cementoblasts.

PubMed

Lee, So-Youn; Auh, Q-Schick; Kang, Soo-Kyung; Kim, Hyung-Joon; Lee, Jung-Woo; Noh, Kwantae; Jang, Jun-Hyeog; Kim, Eun-Cheol

2014-07-01

The aim of this study is to determine the effects of the combination of recombinant human BMP-2 (rh-BMP-2) and dentin sialoprotein (rh-DSP) on growth and differentiation in human cementoblasts and determine the underlying signal transduction mechanism. Compared to treatment of cementoblasts with either rh-BMP-2 or rh-DSP alone, the combination of rh-BMP-2 and rh-DSP synergistically increased cell growth, ALP activity, nodule formation and expression of differentiation markers. The differentiation-promoting effect was also observed in periodontal ligament cells and an osteoblastic cell line. Likewise, combination of rh-DSP and rh-BMP-2 increased BMP-2 mRNA expression and Smad1/5/8 phosphorylation, which was blocked by the BMP antagonist noggin. The expression levels of α2β1 integrin and RhoA, as well as the phosphorylation status of FAK and Akt, were increased by the combination of rh-BMP-2 and rh-DSP in a time-dependent manner. In addition, rh-BMP-2 and rh-DSP enhanced expression of Wnt ligands, β-catenin activation and GSK-3β phosphorylation, all of which were inhibited by the Wnt receptor antagonist DKK1. Furthermore, treatment with rh-DSP plus rh-BMP-2 resulted in phosphorylation of extracellular signal-regulated kinase (ERK), c-Jun N-terminal kinase (JNK) and p38 and also induced the nuclear translocation of the NF-κB p65 subunit, which was blocked by noggin. This study demonstrates for the first time that rh-DSP and rh-BMP-2 act synergistically, enhancing each other's ability to stimulate cementoblastic cell growth and differentiation in vitro via autocrine BMP, integrin, Wnt/β-catenin, MAP kinase and NF-κB pathways. These results support the therapeutic potential of a combination strategy for aiding periodontal regeneration.

Effects of immunization against alpha-inhibin using two adjuvants on daily sperm production and hormone concentrations in ram lambs.

PubMed

Voge, J L; Parker, J B; Wheaton, J E

2009-11-01

Twenty-five ram lambs were immunized against alpha-inhibin peptide emulsified in Freund's adjuvant (FRA), Emulsigen (EML) containing an oligodeoxynucleotide as an immunostimulant, or adjuvant without alpha-inhibin antigen (control). Four immunizations were administered during an 85-d period, after which testes were obtained for determination of daily sperm production (DSP) and histological evaluation. alpha-Inhibin antibody (Ab) titers were 70-fold greater in lambs treated with FRA than in EML-treated ram lambs. alpha-Inhibin immunization had no effect on testes weight or on plasma concentrations of follicle-stimulating hormone (FSH), luteinizing hormone (LH), and testosterone. Mean DSP/g tended (P=0.1) to be greater in alpha-inhibin-immunized (EML=17.6x10(6); FRA=15.8x10(6)) ram lambs than in control animals (14.4x10(6)). One of the 8 control ram lambs had an elevated DSP/g, which was a statistical outlier. Without data from this lamb, DSP/g was increased (P<0.01) in alpha-inhibin-immunized ram lambs by 28% over controls. No association was found between the titer of alpha-inhibin Ab developed and DSP/g. Histologically, the percentage of testicular area occupied by seminiferous tubules differed (P=0.01) by treatment and was greatest (82%) in EML-treated ram alpha-inhibin-immunized lambs and lowest (74%) in control animals. Percentage tubular area and DSP/g were correlated (r=0.57, P=0.003). Findings show that (1) the extent of the increase in DSP/g is not dependent on the titer of alpha-inhibin Ab; (2) the increase in DSP/g is achieved through an increase in the mass of seminiferous tubules; and (3) FRA elicits a greater alpha-inhibin Ab titer than EML containing an oligodeoxynucleotide.

Profiling of Extracellular Toxins Associated with Diarrhetic Shellfish Poison in Prorocentrum lima Culture Medium by High-Performance Liquid Chromatography Coupled with Mass Spectrometry.

PubMed

Pan, Lei; Chen, Junhui; Shen, Huihui; He, Xiuping; Li, Guangjiu; Song, Xincheng; Zhou, Deshan; Sun, Chengjun

2017-09-30

Extracellular toxins released by marine toxigenic algae into the marine environment have attracted increasing attention in recent years. In this study, profiling, characterization and quantification of extracellular toxin compounds associated with diarrhetic shellfish poison (DSP) in the culture medium of toxin-producing dinoflagellates were performed using high-performance liquid chromatography-high-resolution mass spectrometry/tandem mass spectrometry for the first time. Results showed that solid-phase extraction can effectively enrich and clean the DSP compounds in the culture medium of Prorocentrum lima ( P. lima ), and the proposed method achieved satisfactory recoveries (94.80%-100.58%) and repeatability (relative standard deviation ≤9.27%). Commercial software associated with the accurate mass information of known DSP toxins and their derivatives was used to screen and identify DSP compounds. Nine extracellular DSP compounds were identified, of which seven toxins (including OA-D7b, OA-D9b, OA-D10a/b, and so on) were found in the culture medium of P. lima for the first time. The results of quantitative analysis showed that the contents of extracellular DSP compounds in P. lima culture medium were relatively high, and the types and contents of intracellular and extracellular toxins apparently varied in the different growth stages of P. lima . The concentrations of extracellular okadaic acid and dinophysistoxin-1 were within 19.9-34.0 and 15.2-27.9 μg/L, respectively. The total concentration of the DSP compounds was within the range of 57.70-79.63 μg/L. The results showed that the proposed method is an effective tool for profiling the extracellular DSP compounds in the culture medium of marine toxigenic algae.

The Status of the ACRF Millimeter Wave Cloud Radars (MMCRs), the Path Forward for Future MMCR Upgrades, the Concept of 3D Volume Imaging Radar and the UAV Radar

DOE Office of Scientific and Technical Information (OSTI.GOV)

P Kollias; MA Miller; KB Widener

2005-12-30

The United States (U.S.) Department of Energy (DOE) Atmospheric Radiation Measurement (ARM) Climate Research Facility (ACRF) operates millimeter wavelength cloud radars (MMCRs) in several climatological regimes. The MMCRs, are the primary observing tool for quantifying the properties of nearly all radiatively important clouds over the ACRF sites. The first MMCR was installed at the ACRF Southern Great Plains (SGP) site nine years ago and its original design can be traced to the early 90s. Since then, several MMCRs have been deployed at the ACRF sites, while no significant hardware upgrades have been performed. Recently, a two-stage upgrade (first C-40 Digitalmore » Signal Processors [DSP]-based, and later the PC-Integrated Radar AcQuisition System [PIRAQ-III] digital receiver) of the MMCR signal-processing units was completed. Our future MMCR related goals are: 1) to have a cloud radar system that continues to have high reliability and uptime and 2) to suggest potential improvements that will address increased sensitivity needs, superior sampling and low cost maintenance of the MMCRs. The Traveling Wave Tube (TWT) technology, the frequency (35-GHz), the radio frequency (RF) layout, antenna, the calibration and radar control procedure and the environmental enclosure of the MMCR remain assets for our ability to detect the profile of hydrometeors at all heights in the troposphere at the ACRF sites.« less

Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system

DOEpatents

Atac, R.; Fischler, M.S.; Husby, D.E.

1991-01-15

A bus switching apparatus and method for multiple processor computer systems comprises a plurality of bus switches interconnected by branch buses. Each processor or other module of the system is connected to a spigot of a bus switch. Each bus switch also serves as part of a backplane of a modular crate hardware package. A processor initiates communication with another processor by identifying that other processor. The bus switch to which the initiating processor is connected identifies and secures, if possible, a path to that other processor, either directly or via one or more other bus switches which operate similarly. If a particular desired path through a given bus switch is not available to be used, an alternate path is considered, identified and secured. 11 figures.

Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system

DOEpatents

Atac, Robert; Fischler, Mark S.; Husby, Donald E.

1991-01-01

A bus switching apparatus and method for multiple processor computer systems comprises a plurality of bus switches interconnected by branch buses. Each processor or other module of the system is connected to a spigot of a bus switch. Each bus switch also serves as part of a backplane of a modular crate hardware package. A processor initiates communication with another processor by identifying that other processor. The bus switch to which the initiating processor is connected identifies and secures, if possible, a path to that other processor, either directly or via one or more other bus switches which operate similarly. If a particular desired path through a given bus switch is not available to be used, an alternate path is considered, identified and secured.

Autonomous chemical and biological miniature wireless-sensor

NASA Astrophysics Data System (ADS)

Goldberg, Bar-Giora

2005-05-01

The presentation discusses a new concept and a paradigm shift in biological, chemical and explosive sensor system design and deployment. From large, heavy, centralized and expensive systems to distributed wireless sensor networks utilizing miniature platforms (nodes) that are lightweight, low cost and wirelessly connected. These new systems are possible due to the emergence and convergence of new innovative radio, imaging, networking and sensor technologies. Miniature integrated radio-sensor networks, is a technology whose time has come. These network systems are based on large numbers of distributed low cost and short-range wireless platforms that sense and process their environment and communicate data thru a network to a command center. The recent emergence of chemical and explosive sensor technology based on silicon nanostructures, coupled with the fast evolution of low-cost CMOS imagers, low power DSP engines and integrated radio chips, has created an opportunity to realize the vision of autonomous wireless networks. These threat detection networks will perform sophisticated analysis at the sensor node and convey alarm information up the command chain. Sensor networks of this type are expected to revolutionize the ability to detect and locate biological, chemical, or explosive threats. The ability to distribute large numbers of low-cost sensors over large areas enables these devices to be close to the targeted threats and therefore improve detection efficiencies and enable rapid counter responses. These sensor networks will be used for homeland security, shipping container monitoring, and other applications such as laboratory medical analysis, drug discovery, automotive, environmental and/or in-vivo monitoring. Avaak"s system concept is to image a chromatic biological, chemical and/or explosive sensor utilizing a digital imager, analyze the images and distribute alarm or image data wirelessly through the network. All the imaging, processing and communications would take place within the miniature, low cost distributed sensor platforms. This concept however presents a significant challenge due to a combination and convergence of required new technologies, as mentioned above. Passive biological and chemical sensors with very high sensitivity and which require no assaying are in development using a technique to optically and chemically encode silicon wafers with tailored nanostructures. The silicon wafer is patterned with nano-structures designed to change colors ad patterns when exposed to the target analytes (TICs, TIMs, VOC). A small video camera detects the color and pattern changes on the sensor. To determine if an alarm condition is present, an on board DSP processor, using specialized image processing algorithms and statistical analysis, determines if color gradient changes occurred on the sensor array. These sensors can detect several agents simultaneously. This system is currently under development by Avaak, with funding from DARPA through an SBIR grant.

System and method for representing and manipulating three-dimensional objects on massively parallel architectures

DOEpatents

Karasick, Michael S.; Strip, David R.

1996-01-01

A parallel computing system is described that comprises a plurality of uniquely labeled, parallel processors, each processor capable of modelling a three-dimensional object that includes a plurality of vertices, faces and edges. The system comprises a front-end processor for issuing a modelling command to the parallel processors, relating to a three-dimensional object. Each parallel processor, in response to the command and through the use of its own unique label, creates a directed-edge (d-edge) data structure that uniquely relates an edge of the three-dimensional object to one face of the object. Each d-edge data structure at least includes vertex descriptions of the edge and a description of the one face. As a result, each processor, in response to the modelling command, operates upon a small component of the model and generates results, in parallel with all other processors, without the need for processor-to-processor intercommunication.

Real-time blind image deconvolution based on coordinated framework of FPGA and DSP

NASA Astrophysics Data System (ADS)

Wang, Ze; Li, Hang; Zhou, Hua; Liu, Hongjun

2015-10-01

Image restoration takes a crucial place in several important application domains. With the increasing of computation requirement as the algorithms become much more complexity, there has been a significant rise in the need for accelerating implementation. In this paper, we focus on an efficient real-time image processing system for blind iterative deconvolution method by means of the Richardson-Lucy (R-L) algorithm. We study the characteristics of algorithm, and an image restoration processing system based on the coordinated framework of FPGA and DSP (CoFD) is presented. Single precision floating-point processing units with small-scale cascade and special FFT/IFFT processing modules are adopted to guarantee the accuracy of the processing. Finally, Comparing experiments are done. The system could process a blurred image of 128×128 pixels within 32 milliseconds, and is up to three or four times faster than the traditional multi-DSPs systems.

Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems

NASA Technical Reports Server (NTRS)

Downie, John D.; Goodman, Joseph W.

1989-01-01

The accuracy requirements of optical processors in adaptive optics systems are determined by estimating the required accuracy in a general optical linear algebra processor (OLAP) that results in a smaller average residual aberration than that achieved with a conventional electronic digital processor with some specific computation speed. Special attention is given to an error analysis of a general OLAP with regard to the residual aberration that is created in an adaptive mirror system by the inaccuracies of the processor, and to the effect of computational speed of an electronic processor on the correction. Results are presented on the ability of an OLAP to compete with a digital processor in various situations.

DspA/E Contributes to Apoplastic Accumulation of ROS in Non-host A. thaliana

PubMed Central

Launay, Alban; Patrit, Oriane; Wénès, Estelle; Fagard, Mathilde

2016-01-01

The bacterium Erwinia amylovora is responsible for the fire blight disease of Maleae, which provokes necrotic symptoms on aerial parts. The pathogenicity of this bacterium in hosts relies on its type three-secretion system (T3SS), a molecular syringe that allows the bacterium to inject effectors into the plant cell. E. amylovora-triggered disease in host plants is associated with the T3SS-dependent production of reactive oxygen species (ROS), although ROS are generally associated with resistance in other pathosystems. We showed previously that E. amylovora can multiply transiently in the non-host plant Arabidopsis thaliana and that a T3SS-dependent production of intracellular ROS occurs during this interaction. In the present work we characterize the localization and source of hydrogen peroxide accumulation following E. amylovora infection. Transmission electron microscope (TEM) analysis of infected tissues showed that hydrogen peroxide accumulation occurs in the cytosol, plastids, peroxisomes, and mitochondria as well as in the apoplast. Furthermore, TEM analysis showed that an E. amylovora dspA/E-deficient strain does not induce hydrogen peroxide accumulation in the apoplast. Consistently, a transgenic line expressing DspA/E accumulated ROS in the apoplast. The NADPH oxidase-deficient rbohD mutant showed a very strong reduction in hydrogen peroxide accumulation in response to E. amylovora inoculation. However, we did not find an increase in bacterial titers of E. amylovora in the rbohD mutant and the rbohD mutation did not suppress the toxicity of DspA/E when introgressed into a DspA/E-expressing transgenic line. Co-inoculation of E. amylovora with cycloheximide (CHX), which we found previously to suppress callose deposition and allow strong multiplication of E. amylovora in A. thaliana leaves, led to a strong reduction of apoplastic ROS accumulation but did not affect intracellular ROS. Our data strongly suggest that apoplastic ROS accumulation is one layer of the non-host defense response triggered by the type three effector (T3E) DspA/E, together with callose deposition. PMID:27200021

Laura Pittman: The Nation's First Credentialed Direct Support Professional

ERIC Educational Resources Information Center

King, Tom

2007-01-01

This article profiles Laura Pittman, the nation's first credentialed Direct Support Professional (DSP). Laura is a DSP at the Orange Grove Center (OGC) in Chattanooga, Tennessee and has been working there for almost ten years. She has been a DSP for seven of those years, and in that role, supported four women at one of the Orange Grove Center…

Sex determination using the Probabilistic Sex Diagnosis (DSP: Diagnose Sexuelle Probabiliste) tool in a virtual environment.

PubMed

Chapman, Tara; Lefevre, Philippe; Semal, Patrick; Moiseev, Fedor; Sholukha, Victor; Louryan, Stéphane; Rooze, Marcel; Van Sint Jan, Serge

2014-01-01

The hip bone is one of the most reliable indicators of sex in the human body due to the fact it is the most dimorphic bone. Probabilistic Sex Diagnosis (DSP: Diagnose Sexuelle Probabiliste) developed by Murail et al., in 2005, is a sex determination method based on a worldwide hip bone metrical database. Sex is determined by comparing specific measurements taken from each specimen using sliding callipers and computing the probability of specimens being female or male. In forensic science it is sometimes not possible to sex a body due to corpse decay or injury. Skeletalization and dissection of a body is a laborious process and desecrates the body. There were two aims to this study. The first aim was to examine the accuracy of the DSP method in comparison with a current visual sexing method on sex determination. A further aim was to see if it was possible to virtually utilise the DSP method on both the hip bone and the pelvic girdle in order to utilise this method for forensic sciences. For the first part of the study, forty-nine dry hip bones of unknown sex were obtained from the Body Donation Programme of the Université Libre de Bruxelles (ULB). A comparison was made between DSP analysis and visual sexing on dry bone by two researchers. CT scans of bones were then analysed to obtain three-dimensional (3D) virtual models and the method of DSP was analysed virtually by importing the models into a customised software programme called lhpFusionBox which was developed at ULB. The software enables DSP distances to be measured via virtually-palpated bony landmarks. There was found to be 100% agreement of sex between the manual and virtual DSP method. The second part of the study aimed to further validate the method by analysing thirty-nine supplementary pelvic girdles of known sex blind. There was found to be a 100% accuracy rate further demonstrating that the virtual DSP method is robust. Statistically significant differences were found in the identification of sex between researchers in the visual sexing method although both researchers identified the same sex in all cases in the manual and virtual DSP methods for both the hip bones and pelvic girdles. Copyright © 2013 Elsevier Ireland Ltd. All rights reserved.

Flight design system level C requirements. Solid rocket booster and external tank impact prediction processors. [space transportation system

NASA Technical Reports Server (NTRS)

Seale, R. H.

1979-01-01

The prediction of the SRB and ET impact areas requires six separate processors. The SRB impact prediction processor computes the impact areas and related trajectory data for each SRB element. Output from this processor is stored on a secure file accessible by the SRB impact plot processor which generates the required plots. Similarly the ET RTLS impact prediction processor and the ET RTLS impact plot processor generates the ET impact footprints for return-to-launch-site (RTLS) profiles. The ET nominal/AOA/ATO impact prediction processor and the ET nominal/AOA/ATO impact plot processor generate the ET impact footprints for non-RTLS profiles. The SRB and ET impact processors compute the size and shape of the impact footprints by tabular lookup in a stored footprint dispersion data base. The location of each footprint is determined by simulating a reference trajectory and computing the reference impact point location. To insure consistency among all flight design system (FDS) users, much input required by these processors will be obtained from the FDS master data base.

In-Plane Behaviour of a Reinforcement Concrete Frame with a Dry Stack Masonry Panel

PubMed Central

Lin, Kun; Totoev, Yuri Zarevich; Liu, Hongjun; Guo, Tianyou

2016-01-01

In order to improve the energy dissipation of the masonry infilled frame structure while decreasing the stiffening and strengthening effects of the infill panels, a new dry stacked panel (DSP) semi-interlocking masonry (SIM) infill panel has been developed. In this paper, the material properties of DSP and a traditional unreinforced masonry (URM) panel have been evaluated experimentally. A series of cyclic tests were performed to investigate the cyclic behaviour of the reinforcement concrete (RC) frame with different infill panels. The failure modes, damage evolution, hysteretic behaviour, stiffness degradation and energy dissipation were compared and analysed. We concluded that DSP is capable of significantly improving the seismic energy dissipation due to its hysteretic behaviour when the frame is in elastic stage without increasing the stiffness of the frame. Therefore, DSP or SIM panels can be considered as frictional dampers. Based on the experimental results, the influence of DSP was examined. Using the parallel model, the hysteretic loops of DSP subjected to different load cases were achieved. The typical full hysteretic loop for DSP could be divided into three distinct stages of behaviour: packing stage, constant friction stage and equivalent strut stage. The connection between the panel and the frame had a great effect on the transferring of different mechanical stages. The constant friction stage was verified to provide substantial energy dissipation and benefits to the ductility of the structure, which, therefore, is suggested to be prolonged in reality. PMID:28787906

In-Plane Behaviour of a Reinforcement Concrete Frame with a Dry Stack Masonry Panel.

PubMed

Lin, Kun; Totoev, Yuri Zarevich; Liu, Hongjun; Guo, Tianyou

2016-02-11

In order to improve the energy dissipation of the masonry infilled frame structure while decreasing the stiffening and strengthening effects of the infill panels, a new dry stacked panel (DSP) semi-interlocking masonry (SIM) infill panel has been developed. In this paper, the material properties of DSP and a traditional unreinforced masonry (URM) panel have been evaluated experimentally. A series of cyclic tests were performed to investigate the cyclic behaviour of the reinforcement concrete (RC) frame with different infill panels. The failure modes, damage evolution, hysteretic behaviour, stiffness degradation and energy dissipation were compared and analysed. We concluded that DSP is capable of significantly improving the seismic energy dissipation due to its hysteretic behaviour when the frame is in elastic stage without increasing the stiffness of the frame. Therefore, DSP or SIM panels can be considered as frictional dampers. Based on the experimental results, the influence of DSP was examined. Using the parallel model, the hysteretic loops of DSP subjected to different load cases were achieved. The typical full hysteretic loop for DSP could be divided into three distinct stages of behaviour: packing stage, constant friction stage and equivalent strut stage. The connection between the panel and the frame had a great effect on the transferring of different mechanical stages. The constant friction stage was verified to provide substantial energy dissipation and benefits to the ductility of the structure, which, therefore, is suggested to be prolonged in reality.

Real-time implementations of acoustic signal enhancement techniques for aerial based surveillance and rescue applications

NASA Astrophysics Data System (ADS)

Ramos, Antonio L. L.; Shao, Zhili; Holthe, Aleksander; Sandli, Mathias F.

2017-05-01

The introduction of the System-on-Chip (SoC) technology has brought exciting new opportunities for the development of smart low cost embedded systems spanning a wide range of applications. Currently available SoC devices are capable of performing high speed digital signal processing tasks in software while featuring relatively low development costs and reduced time-to-market. Unmanned aerial vehicles (UAV) are an application example that has shown tremendous potential in an increasing number of scenarios, ranging from leisure to surveillance as well as in search and rescue missions. Video capturing from UAV platforms is a relatively straightforward task that requires almost no preprocessing. However, that does not apply to audio signals, especially in cases where the data is to be used to support real-time decision making. In fact, the enormous amount of acoustic interference from the surroundings, including the noise from the UAVs propellers, becomes a huge problem. This paper discusses a real-time implementation of the NLMS adaptive filtering algorithm applied to enhancing acoustic signals captured from UAV platforms. The model relies on a combination of acoustic sensors and a computational inexpensive algorithm running on a digital signal processor. Given its simplicity, this solution can be incorporated into the main processing system of an UAV using the SoC technology, and run concurrently with other required tasks, such as flight control and communications. Simulations and real-time DSP-based implementations have shown significant signal enhancement results by efficiently mitigating the interference from the noise generated by the UAVs propellers as well as from other external noise sources.

Digital active material processing platform effort (DAMPER), SBIR phase 2

NASA Technical Reports Server (NTRS)

Blackburn, John; Smith, Dennis

1992-01-01

Applied Technology Associates, Inc., (ATA) has demonstrated that inertial actuation can be employed effectively in digital, active vibration isolation systems. Inertial actuation involves the use of momentum exchange to produce corrective forces which act directly on the payload being actively isolated. In a typical active vibration isolation system, accelerometers are used to measure the inertial motion of the payload. The signals from the accelerometers are then used to calculate the corrective forces required to counteract, or 'cancel out' the payload motion. Active vibration isolation is common technology, but the use of inertial actuation in such systems is novel, and is the focus of the DAMPER project. A May 1991 report was completed which documented the successful demonstration of inertial actuation, employed in the control of vibration in a single axis. In the 1 degree-of-freedom (1DOF) experiment a set of air bearing rails was used to suspend the payload, simulating a microgravity environment in a single horizontal axis. Digital Signal Processor (DSP) technology was used to calculate in real time, the control law between the accelerometer signals and the inertial actuators. The data obtained from this experiment verified that as much as 20 dB of rejection could be realized by this type of system. A discussion is included of recent tests performed in which vibrations were actively controlled in three axes simultaneously. In the three degree-of-freedom (3DOF) system, the air bearings were designed in such a way that the payload is free to rotate about the azimuth axis, as well as translate in the two horizontal directions. The actuator developed for the DAMPER project has applications beyond payload isolation, including structural damping and source vibration isolation. This report includes a brief discussion of these applications, as well as a commercialization plan for the actuator.

Digital active material processing platform effort (DAMPER), SBIR phase 2

NASA Astrophysics Data System (ADS)

Blackburn, John; Smith, Dennis

1992-11-01

Applied Technology Associates, Inc., (ATA) has demonstrated that inertial actuation can be employed effectively in digital, active vibration isolation systems. Inertial actuation involves the use of momentum exchange to produce corrective forces which act directly on the payload being actively isolated. In a typical active vibration isolation system, accelerometers are used to measure the inertial motion of the payload. The signals from the accelerometers are then used to calculate the corrective forces required to counteract, or 'cancel out' the payload motion. Active vibration isolation is common technology, but the use of inertial actuation in such systems is novel, and is the focus of the DAMPER project. A May 1991 report was completed which documented the successful demonstration of inertial actuation, employed in the control of vibration in a single axis. In the 1 degree-of-freedom (1DOF) experiment a set of air bearing rails was used to suspend the payload, simulating a microgravity environment in a single horizontal axis. Digital Signal Processor (DSP) technology was used to calculate in real time, the control law between the accelerometer signals and the inertial actuators. The data obtained from this experiment verified that as much as 20 dB of rejection could be realized by this type of system. A discussion is included of recent tests performed in which vibrations were actively controlled in three axes simultaneously. In the three degree-of-freedom (3DOF) system, the air bearings were designed in such a way that the payload is free to rotate about the azimuth axis, as well as translate in the two horizontal directions. The actuator developed for the DAMPER project has applications beyond payload isolation, including structural damping and source vibration isolation. This report includes a brief discussion of these applications, as well as a commercialization plan for the actuator.

Behavioral Priming 2.0: Enter a Dynamical Systems Perspective

PubMed Central

Krpan, Dario

2017-01-01

On a daily basis, people are exposed to numerous stimuli, ranging from colors and smells to sounds and words, that could potentially activate different cognitive constructs and influence their actions. This type of influence on human behavior is referred to as priming. Roughly two decades ago, behavioral priming was hailed as one of the core forces that shape automatic behavior. However, failures to replicate some of the representative findings in this domain soon followed, which posed the following question: “How robust are behavioral priming effects, and to what extent are they actually important in shaping people's actions?” To shed a new light on this question, I revisit behavioral priming through the prism of a dynamical systems perspective (DSP). The DSP is a scientific paradigm that has been developed through a combined effort of many different academic disciplines, ranging from mathematics and physics to biology, economics, psychology, etc., and it deals with behavior of simple and complex systems over time. In the present paper, I use conceptual and methodological tools stemming from the DSP to propose circumstances under which behavioral priming effects are likely to occur. More precisely, I outline three possible types of the influence of priming on human behavior, to which I refer as emergence, readjustment, and attractor switch, and propose experimental designs to examine them. Finally, I discuss relevant implications for behavioral priming effects and their replications. PMID:28769846

Hot Chips and Hot Interconnects for High End Computing Systems

NASA Technical Reports Server (NTRS)

Saini, Subhash

2005-01-01

I will discuss several processors: 1. The Cray proprietary processor used in the Cray X1; 2. The IBM Power 3 and Power 4 used in an IBM SP 3 and IBM SP 4 systems; 3. The Intel Itanium and Xeon, used in the SGI Altix systems and clusters respectively; 4. IBM System-on-a-Chip used in IBM BlueGene/L; 5. HP Alpha EV68 processor used in DOE ASCI Q cluster; 6. SPARC64 V processor, which is used in the Fujitsu PRIMEPOWER HPC2500; 7. An NEC proprietary processor, which is used in NEC SX-6/7; 8. Power 4+ processor, which is used in Hitachi SR11000; 9. NEC proprietary processor, which is used in Earth Simulator. The IBM POWER5 and Red Storm Computing Systems will also be discussed. The architectures of these processors will first be presented, followed by interconnection networks and a description of high-end computer systems based on these processors and networks. The performance of various hardware/programming model combinations will then be compared, based on latest NAS Parallel Benchmark results (MPI, OpenMP/HPF and hybrid (MPI + OpenMP). The tutorial will conclude with a discussion of general trends in the field of high performance computing, (quantum computing, DNA computing, cellular engineering, and neural networks).

Porcine dentin sialoprotein glycosylation and glycosaminoglycan attachments.

PubMed

Yamakoshi, Yasuo; Nagano, Takatoshi; Hu, Jan Cc; Yamakoshi, Fumiko; Simmer, James P

2011-02-03

Dentin sialophosphoprotein (Dspp) is a multidomain, secreted protein that is critical for the formation of tooth dentin. Mutations in DSPP cause inherited dentin defects categorized as dentin dysplasia type II and dentinogenesis imperfecta type II and type III. Dentin sialoprotein (Dsp), the N-terminal domain of dentin sialophosphoprotein (Dspp), is a highly glycosylated proteoglycan, but little is known about the number, character, and attachment sites of its carbohydrate moieties. To identify its carbohydrate attachment sites we isolated Dsp from developing porcine molars and digested it with endoproteinase Glu-C or pronase, fractionated the digestion products, identified fractions containing glycosylated peptides using a phenol sulfuric acid assay, and characterized the glycopeptides by N-terminal sequencing, amino acid analyses, or LC/MSMS. To determine the average number of sialic acid attachments per N-glycosylation, we digested Dsp with glycopeptidase A, labeled the released N-glycosylations with 2-aminobenzoic acid, and quantified the moles of released glycosylations by comparison to labeled standards of known concentration. Sialic acid was released by sialidase digestion and quantified by measuring β-NADH reduction of pyruvic acid, which was generated stoichiometrically from sialic acid by aldolase. To determine its forms, sialic acid released by sialidase digestion was labeled with 1,2-diamino-4,5-methyleneoxybenzene (DMB) and compared to a DMB-labeled sialic acid reference panel by RP-HPLC. To determine the composition of Dsp glycosaminoglycan (GAG) attachments, we digested Dsp with chondroitinase ABC and compared the chromotagraphic profiles of the released disaccharides to commercial standards. N-glycosylations were identified at Asn37, Asn77, Asn136, Asn155, Asn161, and Asn176. Dsp averages one sialic acid per N-glycosylation, which is always in the form of N-acetylneuraminic acid. O-glycosylations were tentatively assigned at Thr200, Thr216 and Thr316. Porcine Dsp GAG attachments were found at Ser238 and Ser250 and were comprised of chondroitin 6-sulfate and chondroitin 4-sulfate in a ratio of 7 to 3, respectively. The distribution of porcine Dsp posttranslational modifications indicate that porcine Dsp has an N-terminal domain with at least six N-glycosylations and a C-terminal domain with two GAG attachments and at least two O-glycosylations.

Monitoring of DSP toxins in small-sized plankton fraction of seawater collected in Mutsu Bay, Japan, by ELISA method: relation with toxin contamination of scallop.

PubMed

Imai, Ichiro; Sugioka, Hikaru; Nishitani, Goh; Mitsuya, Tadashi; Hamano, Yonekazu

2003-01-01

Monitorings were conducted on DSP toxins in mid-gut gland of scallop (mouse assay), cell numbers of toxic dinoflagellate species of Dinophysis, and diarrhetic shellfish poisoning (DSP) toxins in small-sized (0.7-5 microm) plankton fraction of seawater collected from surface (0 m) and 20 m depth at a station in Mutsu Bay, Aomori Prefecture, Japan, in 2000. A specific enzyme-linked immunosorbent assay (ELISA) was employed for the analysis of DSP toxins in small-sized plankton fraction using a mouse monoclonal anti-okadaic acid antibody which recognizes okadaic acid, dinophysistoxin-1, and dinophysistoxin-3. DSP toxins were detected twice in the mid-gut gland of scallops at 1.1-2.3 MU (mouse units) g(-1) on 26 June and at 0.6-1.2 MU g(-1) on 3 July, respectively. Relatively high cell densities of D. fortii were observed on 26 June and 11 September, and may only contribute to the bivalve toxicity during late June to early July. D. acuminata did not appear to be responsible for the toxicity of scallops in Mutsu Bay in 2000. ELISA monitoring of small-sized plankton fraction in seawater could detect DSP toxins two weeks before the detection of the toxin in scallops, and could do so two weeks after the loss of the bivalve toxicity by mouse assay. On 17 July, toxic D. fortii was detected at only small number, <10 cells l(-1), but DSP toxins were detected by the ELISA assay, suggesting a presence of other toxic small-sized plankton in seawater. For the purpose of reducing negative impacts of DSP occurrences, monitorings have been carried out hitherto on DSP toxins of bivalve tissues by mouse assay and on cell densities of "toxic" species of Dinophysis. Here we propose a usefulness of ELISA monitoring of plankton toxicity, especially in small-sized fraction, which are possible foods of mixotrophic Dinophysis, as a practical tool for detecting and predicting DSPs in coastal areas of fisheries grounds of bivalve aquaculture.

Processor architecture for airborne SAR systems

NASA Technical Reports Server (NTRS)

Glass, C. M.

1983-01-01

Digital processors for spaceborne imaging radars and application of the technology developed for airborne SAR systems are considered. Transferring algorithms and implementation techniques from airborne to spaceborne SAR processors offers obvious advantages. The following topics are discussed: (1) a quantification of the differences in processing algorithms for airborne and spaceborne SARs; and (2) an overview of three processors for airborne SAR systems.

Fast neutron-gamma discrimination on neutron emission profile measurement on JT-60U.

PubMed

Ishii, K; Shinohara, K; Ishikawa, M; Baba, M; Isobe, M; Okamoto, A; Kitajima, S; Sasao, M

2010-10-01

A digital signal processing (DSP) system is applied to stilbene scintillation detectors of the multichannel neutron emission profile monitor in JT-60U. Automatic analysis of the neutron-γ pulse shape discrimination is a key issue to diminish the processing time in the DSP system, and it has been applied using the two-dimensional (2D) map. Linear discriminant function is used to determine the dividing line between neutron events and γ-ray events on a 2D map. In order to verify the validity of the dividing line determination, the pulse shape discrimination quality is evaluated. As a result, the γ-ray contamination in most of the beam heating phase was negligible compared with the statistical error with 10 ms time resolution.

Fast neutron-gamma discrimination on neutron emission profile measurement on JT-60U

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ishii, K.; Okamoto, A.; Kitajima, S.

2010-10-15

A digital signal processing (DSP) system is applied to stilbene scintillation detectors of the multichannel neutron emission profile monitor in JT-60U. Automatic analysis of the neutron-{gamma} pulse shape discrimination is a key issue to diminish the processing time in the DSP system, and it has been applied using the two-dimensional (2D) map. Linear discriminant function is used to determine the dividing line between neutron events and {gamma}-ray events on a 2D map. In order to verify the validity of the dividing line determination, the pulse shape discrimination quality is evaluated. As a result, the {gamma}-ray contamination in most of themore » beam heating phase was negligible compared with the statistical error with 10 ms time resolution.« less

System and method for representing and manipulating three-dimensional objects on massively parallel architectures

DOEpatents

Karasick, M.S.; Strip, D.R.

1996-01-30

A parallel computing system is described that comprises a plurality of uniquely labeled, parallel processors, each processor capable of modeling a three-dimensional object that includes a plurality of vertices, faces and edges. The system comprises a front-end processor for issuing a modeling command to the parallel processors, relating to a three-dimensional object. Each parallel processor, in response to the command and through the use of its own unique label, creates a directed-edge (d-edge) data structure that uniquely relates an edge of the three-dimensional object to one face of the object. Each d-edge data structure at least includes vertex descriptions of the edge and a description of the one face. As a result, each processor, in response to the modeling command, operates upon a small component of the model and generates results, in parallel with all other processors, without the need for processor-to-processor intercommunication. 8 figs.

Buffered coscheduling for parallel programming and enhanced fault tolerance

DOEpatents

Petrini, Fabrizio [Los Alamos, NM; Feng, Wu-chun [Los Alamos, NM

2006-01-31

A computer implemented method schedules processor jobs on a network of parallel machine processors or distributed system processors. Control information communications generated by each process performed by each processor during a defined time interval is accumulated in buffers, where adjacent time intervals are separated by strobe intervals for a global exchange of control information. A global exchange of the control information communications at the end of each defined time interval is performed during an intervening strobe interval so that each processor is informed by all of the other processors of the number of incoming jobs to be received by each processor in a subsequent time interval. The buffered coscheduling method of this invention also enhances the fault tolerance of a network of parallel machine processors or distributed system processors

Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology.

PubMed

Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

2015-07-22

This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode's current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm(2) of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA.

Next Generation Space Telescope Integrated Science Module Data System

NASA Technical Reports Server (NTRS)

Schnurr, Richard G.; Greenhouse, Matthew A.; Jurotich, Matthew M.; Whitley, Raymond; Kalinowski, Keith J.; Love, Bruce W.; Travis, Jeffrey W.; Long, Knox S.

1999-01-01

The Data system for the Next Generation Space Telescope (NGST) Integrated Science Module (ISIM) is the primary data interface between the spacecraft, telescope, and science instrument systems. This poster includes block diagrams of the ISIM data system and its components derived during the pre-phase A Yardstick feasibility study. The poster details the hardware and software components used to acquire and process science data for the Yardstick instrument compliment, and depicts the baseline external interfaces to science instruments and other systems. This baseline data system is a fully redundant, high performance computing system. Each redundant computer contains three 150 MHz power PC processors. All processors execute a commercially available real time multi-tasking operating system supporting, preemptive multi-tasking, file management and network interfaces. These six processors in the system are networked together. The spacecraft interface baseline is an extension of the network, which links the six processors. The final selection for Processor busses, processor chips, network interfaces, and high-speed data interfaces will be made during mid 2002.

Design and DSP implementation of star image acquisition and star point fast acquiring and tracking

NASA Astrophysics Data System (ADS)

Zhou, Guohui; Wang, Xiaodong; Hao, Zhihang

2006-02-01

Star sensor is a special high accuracy photoelectric sensor. Attitude acquisition time is an important function index of star sensor. In this paper, the design target is to acquire 10 samples per second dynamic performance. On the basis of analyzing CCD signals timing and star image processing, a new design and a special parallel architecture for improving star image processing are presented in this paper. In the design, the operation moving the data in expanded windows including the star to the on-chip memory of DSP is arranged in the invalid period of CCD frame signal. During the CCD saving the star image to memory, DSP processes the data in the on-chip memory. This parallelism greatly improves the efficiency of processing. The scheme proposed here results in enormous savings of memory normally required. In the scheme, DSP HOLD mode and CPLD technology are used to make a shared memory between CCD and DSP. The efficiency of processing is discussed in numerical tests. Only in 3.5ms is acquired the five lightest stars in the star acquisition stage. In 43us, the data in five expanded windows including stars are moved into the internal memory of DSP, and in 1.6ms, five star coordinates are achieved in the star tracking stage.

REVIEW ARTICLE: Spectrophotometric applications of digital signal processing

NASA Astrophysics Data System (ADS)

Morawski, Roman Z.

2006-09-01

Spectrophotometry is more and more often the method of choice not only in analysis of (bio)chemical substances, but also in the identification of physical properties of various objects and their classification. The applications of spectrophotometry include such diversified tasks as monitoring of optical telecommunications links, assessment of eating quality of food, forensic classification of papers, biometric identification of individuals, detection of insect infestation of seeds and classification of textiles. In all those applications, large numbers of data, generated by spectrophotometers, are processed by various digital means in order to extract measurement information. The main objective of this paper is to review the state-of-the-art methodology for digital signal processing (DSP) when applied to data provided by spectrophotometric transducers and spectrophotometers. First, a general methodology of DSP applications in spectrophotometry, based on DSP-oriented models of spectrophotometric data, is outlined. Then, the most important classes of DSP methods for processing spectrophotometric data—the methods for DSP-aided calibration of spectrophotometric instrumentation, the methods for the estimation of spectra on the basis of spectrophotometric data, the methods for the estimation of spectrum-related measurands on the basis of spectrophotometric data—are presented. Finally, the methods for preprocessing and postprocessing of spectrophotometric data are overviewed. Throughout the review, the applications of DSP are illustrated with numerous examples related to broadly understood spectrophotometry.

Communications Processor Operating System Study. Executive Summary,

DTIC Science & Technology

1980-11-01

AD-A095 b36 ROME AIR DEVELOPMENT CENTER GRIFFISS AFB NY F/e 17/2 COMMUNICATIONS PROCESSOR OPERATING SYSTEM STUDY. EXECUTIVE SUMM—ETC(U) NOV 80 J...COMMUNICATIONS PROCESSOR OPERATING SYSTEM STUDY Julian Gitlih SPTIC ELECTE«^ FEfi 2 6 1981^ - E APPROVED FOR PUBLIC RELEASE; DISTRIBUTION UNLIMITED "a O...Subtitle) EXECUTIVE^SUMMARY 0F> COMMUNICATIONS PROCESSOR OPERATING SYSTEM $t - • >X W tdLl - ’•• • 7 AUTHORf«! ! , Julian

Dentine sialoprotein and collagen I expression after experimental pulp capping in humans using emdogain gel.

PubMed

Fransson, H; Petersson, K; Davies, J R

2011-03-01

To characterize the hard tissue formed in human teeth experimentally pulp capped either with calcium hydroxide or with Emdogain Gel (Biora AB, Malmö, Sweden) - a derivative of enamel matrix (EMD), using two markers for dentine; dentine sialoprotein (DSP) and type 1 collagen (Col I). Affinity-purified rabbit anti-Col I and anti-DSP polyclonal antibodies were used to stain histological sections from nine pairs of contra-lateral premolars that had been experimentally pulp amputated and randomly capped with EMDgel or calcium hydroxide. Twelve weeks after the teeth had been pulp capped, they were extracted, fixed, demineralized and serially sectioned prior to immunohistochemical staining. In the calcium hydroxide treated teeth DSP was seen in the new hard tissue which formed a bridge. DSP was also seen in the newly formed hard tissue in the EMDgel-treated teeth. Proliferated pulp tissue partly filled the space initially occupied by EMDgel and DSP-stained hard tissue was observed alongside exposed dentine surfaces as well as in isolated masses within the proliferated pulp tissue, although the new hard tissue did not cover the pulp exposure. DSP staining was also seen in the cells lining the hard tissue in both groups. Col I staining was seen in the newly formed hard tissue in both groups. The new hard tissue formed after pulp capping with EMDgel or calcium hydroxide contained DSP and Col I, considered to be markers for dentine. Thus, the newly formed hard tissue can be characterized as dentine rather than unspecific hard tissue. © 2010 International Endodontic Journal.

Comparison of diabetes patients with “demyelinating” diabetic sensorimotor polyneuropathy to those diagnosed with CIDP

PubMed Central

Dunnigan, Samantha K; Ebadi, Hamid; Breiner, Ari; Katzberg, Hans D; Lovblom, Leif E; Perkins, Bruce A; Bril, Vera

2013-01-01

Background We have previously identified a subset of diabetic sensorimotor polyneuropathy (DSP) patients with probable demyelination related to poor glycemic control. We aimed to determine whether the clinical characteristics and electrodiagnostic classification of nerve injury in diabetes patients with “demyelinating” DSP (D-DSP) differed from those diagnosed with chronic inflammatory demyelinating polyneuropathy (CIDP) (CIDP + diabetes mellitus [DM]). Methods D-DSP (56) and CIDP + DM (67) subjects underwent clinical examination and nerve conduction studies (NCS), and were compared using analysis of variance, contingency tables, and Kruskal–Wallis analyses. Results Of the 123 subjects with a mean age of 60.5 ± 15.6 years and mean hemoglobin A1c (HbA1c) of 8.2 ± 2.2%, 54% had CIDP + DM and 46% had D-DSP. CIDP + DM subjects were older (P = 0.0003), had shorter duration of diabetes (P = 0.005), and more severe neuropathy as indicated by Toronto Clinical Neuropathy Score (TCNS) (P = 0.003), deep tendon reflexes (P = 0.02), and vibration perception thresholds (VPT) (P = 0.01, P = 0.02). The mean HbA1c value for D-DSP subjects (8.9 ± 2.3%) was higher than in CIDP + DM subjects (7.7 ± 2.0%, P = 0.02). Conclusions The clinical phenotype and electrophysiological profile of CIDP + DM patients is marked by more severe neuropathy and better glycemic control than in patients with D-DSP. These findings indicate that these two conditions – despite similarities in their electrophysiological pattern of demyelination – likely differ in etiology. PMID:24363969

An FPGA Architecture for Extracting Real-Time Zernike Coefficients from Measured Phase Gradients

NASA Astrophysics Data System (ADS)

Moser, Steven; Lee, Peter; Podoleanu, Adrian

2015-04-01

Zernike modes are commonly used in adaptive optics systems to represent optical wavefronts. However, real-time calculation of Zernike modes is time consuming due to two factors: the large factorial components in the radial polynomials used to define them and the large inverse matrix calculation needed for the linear fit. This paper presents an efficient parallel method for calculating Zernike coefficients from phase gradients produced by a Shack-Hartman sensor and its real-time implementation using an FPGA by pre-calculation and storage of subsections of the large inverse matrix. The architecture exploits symmetries within the Zernike modes to achieve a significant reduction in memory requirements and a speed-up of 2.9 when compared to published results utilising a 2D-FFT method for a grid size of 8×8. Analysis of processor element internal word length requirements show that 24-bit precision in precalculated values of the Zernike mode partial derivatives ensures less than 0.5% error per Zernike coefficient and an overall error of <1%. The design has been synthesized on a Xilinx Spartan-6 XC6SLX45 FPGA. The resource utilisation on this device is <3% of slice registers, <15% of slice LUTs, and approximately 48% of available DSP blocks independent of the Shack-Hartmann grid size. Block RAM usage is <16% for Shack-Hartmann grid sizes up to 32×32.

A Spaceflight Magnetic Bearing Equipped Optical Chopper with Six-Axis Active Control

NASA Technical Reports Server (NTRS)

Blumenstock, Kenneth A.; Lee, Kenneth Y.; Schepis, Joseph P.

1998-01-01

This paper describes the development of an ETU (Engineering Test Unit) rotary optical chopper with magnetic bearings. An ETU is required to be both flight-like, nearly identical to a flight unit without the need for material certifications, and demonstrate structural and performance integrity. A prototype breadboard design previously demonstrated the feasibility of meeting flight performance requirements using magnetic bearings. The chopper mechanism is a critical component of the High Resolution Dynamics Limb Sounder (HIRDLS) which will be flown on EOS-CHEM (Earth Observing System-Chemistry). Particularly noteworthy are the science requirements which demand high precision positioning and minimal power consumption along with full redundancy of coils and sensors in a miniature, lightweight package. The magnetic bearings are unique in their pole design to minimize parasitic losses and utilize collocated optical sensing. The motor is of an unusual disk-type ironless stator design. The ETU design has evolved from the breadboard design. A number of improvements have been incorporated into the ETU design. Active thrust control has been added along with changes to improve sensor stability, motor efficiency, and touchdown and launch survivability. It was necessary to do all this while simultaneously reducing the mechanism volume. Flight-like electronics utilize a DSP (Digital Signal Processor) and contain all sensor electronics and drivers on a single five inch by nine inch circuit board. Performance test results are reported including magnetic bearing and motor rotational losses.

FPGA implementation of image dehazing algorithm for real time applications

NASA Astrophysics Data System (ADS)

Kumar, Rahul; Kaushik, Brajesh Kumar; Balasubramanian, R.

2017-09-01

Weather degradation such as haze, fog, mist, etc. severely reduces the effective range of visual surveillance. This degradation is a spatially varying phenomena, which makes this problem non trivial. Dehazing is an essential preprocessing stage in applications such as long range imaging, border security, intelligent transportation system, etc. However, these applications require low latency of the preprocessing block. In this work, single image dark channel prior algorithm is modified and implemented for fast processing with comparable visual quality of the restored image/video. Although conventional single image dark channel prior algorithm is computationally expensive, it yields impressive results. Moreover, a two stage image dehazing architecture is introduced, wherein, dark channel and airlight are estimated in the first stage. Whereas, transmission map and intensity restoration are computed in the next stages. The algorithm is implemented using Xilinx Vivado software and validated by using Xilinx zc702 development board, which contains an Artix7 equivalent Field Programmable Gate Array (FPGA) and ARM Cortex A9 dual core processor. Additionally, high definition multimedia interface (HDMI) has been incorporated for video feed and display purposes. The results show that the dehazing algorithm attains 29 frames per second for the image resolution of 1920x1080 which is suitable of real time applications. The design utilizes 9 18K_BRAM, 97 DSP_48, 6508 FFs and 8159 LUTs.

Short- and long-term performance of a tripolar down-sized single lead for implantable cardioverter defibrillator treatment: a randomized prospective European multicenter study. European Endotak DSP Investigator Group.

PubMed

Sandstedt, B; Kennergren, C; Schaumann, A; Herse, B; Neuzner, J

1998-11-01

A new, thinner (10 Fr) and more flexible, single-pass transvenous endocardial ICD lead, Endotak DSP, was compared with a conventional lead, Endotak C, as a control in a prospective randomized multicenter study in combination with a nonactive can ICD. A total of 123 patients were enrolled, 55 of whom received a down-sized DSP lead. Lead-alone configuration was successfully implanted in 95% of the DSP patients vs 88% in the control group. The mean defibrillation threshold (DFT) was determined by means of a step-down protocol, and was identical in the two groups, 10.5 +/- 4.8 J in the DSP group versus 10.5 +/- 4.8 J in the control group. At implantation, the DSP mean pacing threshold was lower, 0.51 +/- 0.18 V versus 0.62 +/- 0.35 V (p < 0.05) in the control group, and the mean pacing impedance higher, 594 +/- 110 omega vs 523 +/- 135 omega (p < 0.05). During the follow-up period, the statistically significant difference in thresholds disappeared, while the difference in impedance remained. Tachyarrhythmia treatment by shock or antitachycardia pacing (ATP) was delivered in 53% and 41%, respectively, of the patients with a 100% success rate. In the DSP group, all 28 episodes of polymorphic ventricular tachycardia or ventricular fibrillation were converted by the first shock as compared to 57 of 69 episodes (83%) in the control group (p < 0.05). Monomorphic ventricular tachycardias were terminated by ATP alone in 96% versus 94%. Lead related problems were minor and observed in 5% and 7%, respectively. In summary, both leads were safe and efficacious in the detection and treatment of ventricular tachyarrhythmias. There were no differences between the DSP and control groups regarding short- or long-term lead related complications.

Simultaneous acquisition of 3D shape and deformation by combination of interferometric and correlation-based laser speckle metrology.

PubMed

Dekiff, Markus; Berssenbrügge, Philipp; Kemper, Björn; Denz, Cornelia; Dirksen, Dieter

2015-12-01

A metrology system combining three laser speckle measurement techniques for simultaneous determination of 3D shape and micro- and macroscopic deformations is presented. While microscopic deformations are determined by a combination of Digital Holographic Interferometry (DHI) and Digital Speckle Photography (DSP), macroscopic 3D shape, position and deformation are retrieved by photogrammetry based on digital image correlation of a projected laser speckle pattern. The photogrammetrically obtained data extend the measurement range of the DHI-DSP system and also increase the accuracy of the calculation of the sensitivity vector. Furthermore, a precise assignment of microscopic displacements to the object's macroscopic shape for enhanced visualization is achieved. The approach allows for fast measurements with a simple setup. Key parameters of the system are optimized, and its precision and measurement range are demonstrated. As application examples, the deformation of a mandible model and the shrinkage of dental impression material are measured.

LANDSAT-D flight segment operations manual. Appendix B: OBC software operations

NASA Technical Reports Server (NTRS)

Talipsky, R.

1981-01-01

The LANDSAT 4 satellite contains two NASA standard spacecraft computers and 65,536 words of memory. Onboard computer software is divided into flight executive and applications processors. Both applications processors and the flight executive use one or more of 67 system tables to obtain variables, constants, and software flags. Output from the software for monitoring operation is via 49 OBC telemetry reports subcommutated in the spacecraft telemetry. Information is provided about the flight software as it is used to control the various spacecraft operations and interpret operational OBC telemetry. Processor function descriptions, processor operation, software constraints, processor system tables, processor telemetry, and processor flow charts are presented.

Sliding-mode control of single input multiple output DC-DC converter

NASA Astrophysics Data System (ADS)

Zhang, Libo; Sun, Yihan; Luo, Tiejian; Wan, Qiyang

2016-10-01

Various voltage levels are required in the vehicle mounted power system. A conventional solution is to utilize an independent multiple output DC-DC converter whose cost is high and control scheme is complicated. In this paper, we design a novel SIMO DC-DC converter with sliding mode controller. The proposed converter can boost the voltage of a low-voltage input power source to a controllable high-voltage DC bus and middle-voltage output terminals, which endow the converter with characteristics of simple structure, low cost, and convenient control. In addition, the sliding mode control (SMC) technique applied in our converter can enhance the performances of a certain SIMO DC-DC converter topology. The high-voltage DC bus can be regarded as the main power source to the high-voltage facility of the vehicle mounted power system, and the middle-voltage output terminals can supply power to the low-voltage equipment on an automobile. In the respect of control algorithm, it is the first time to propose the SMC-PID (Proportion Integration Differentiation) control algorithm, in which the SMC algorithm is utilized and the PID control is attended to the conventional SMC algorithm. The PID control increases the dynamic ability of the SMC algorithm by establishing the corresponding SMC surface and introducing the attached integral of voltage error, which endow the sliding-control system with excellent dynamic performance. At last, we established the MATLAB/SIMULINK simulation model, tested performance of the system, and built the hardware prototype based on Digital Signal Processor (DSP). Results show that the sliding mode control is able to track a required trajectory, which has robustness against the uncertainties and disturbances.

Sliding-mode control of single input multiple output DC-DC converter.

PubMed

Zhang, Libo; Sun, Yihan; Luo, Tiejian; Wan, Qiyang

2016-10-01

Various voltage levels are required in the vehicle mounted power system. A conventional solution is to utilize an independent multiple output DC-DC converter whose cost is high and control scheme is complicated. In this paper, we design a novel SIMO DC-DC converter with sliding mode controller. The proposed converter can boost the voltage of a low-voltage input power source to a controllable high-voltage DC bus and middle-voltage output terminals, which endow the converter with characteristics of simple structure, low cost, and convenient control. In addition, the sliding mode control (SMC) technique applied in our converter can enhance the performances of a certain SIMO DC-DC converter topology. The high-voltage DC bus can be regarded as the main power source to the high-voltage facility of the vehicle mounted power system, and the middle-voltage output terminals can supply power to the low-voltage equipment on an automobile. In the respect of control algorithm, it is the first time to propose the SMC-PID (Proportion Integration Differentiation) control algorithm, in which the SMC algorithm is utilized and the PID control is attended to the conventional SMC algorithm. The PID control increases the dynamic ability of the SMC algorithm by establishing the corresponding SMC surface and introducing the attached integral of voltage error, which endow the sliding-control system with excellent dynamic performance. At last, we established the MATLAB/SIMULINK simulation model, tested performance of the system, and built the hardware prototype based on Digital Signal Processor (DSP). Results show that the sliding mode control is able to track a required trajectory, which has robustness against the uncertainties and disturbances.

Concept of a programmable maintenance processor applicable to multiprocessing systems

NASA Technical Reports Server (NTRS)

Glover, Richard D.

1988-01-01

A programmable maintenance processor concept applicable to multiprocessing systems has been developed at the NASA Ames Research Center's Dryden Flight Research Facility. This stand-alone-processor is intended to provide support for system and application software testing as well as hardware diagnostics. An initial machanization has been incorporated into the extended aircraft interrogation and display system (XAIDS) which is multiprocessing general-purpose ground support equipment. The XAIDS maintenance processor has independent terminal and printer interfaces and a dedicated magnetic bubble memory that stores system test sequences entered from the terminal. This report describes the hardware and software embodied in this processor and shows a typical application in the check-out of a new XAIDS.

Verification of ECMWF System 4 for seasonal hydrological forecasting in a northern climate

NASA Astrophysics Data System (ADS)

Bazile, Rachel; Boucher, Marie-Amélie; Perreault, Luc; Leconte, Robert

2017-11-01

Hydropower production requires optimal dam and reservoir management to prevent flooding damage and avoid operation losses. In a northern climate, where spring freshet constitutes the main inflow volume, seasonal forecasts can help to establish a yearly strategy. Long-term hydrological forecasts often rely on past observations of streamflow or meteorological data. Another alternative is to use ensemble meteorological forecasts produced by climate models. In this paper, those produced by the ECMWF (European Centre for Medium-Range Forecast) System 4 are examined and bias is characterized. Bias correction, through the linear scaling method, improves the performance of the raw ensemble meteorological forecasts in terms of continuous ranked probability score (CRPS). Then, three seasonal ensemble hydrological forecasting systems are compared: (1) the climatology of simulated streamflow, (2) the ensemble hydrological forecasts based on climatology (ESP) and (3) the hydrological forecasts based on bias-corrected ensemble meteorological forecasts from System 4 (corr-DSP). Simulated streamflow computed using observed meteorological data is used as benchmark. Accounting for initial conditions is valuable even for long-term forecasts. ESP and corr-DSP both outperform the climatology of simulated streamflow for lead times from 1 to 5 months depending on the season and watershed. Integrating information about future meteorological conditions also improves monthly volume forecasts. For the 1-month lead time, a gain exists for almost all watersheds during winter, summer and fall. However, volume forecasts performance for spring varies from one watershed to another. For most of them, the performance is close to the performance of ESP. For longer lead times, the CRPS skill score is mostly in favour of ESP, even if for many watersheds, ESP and corr-DSP have comparable skill. Corr-DSP appears quite reliable but, in some cases, under-dispersion or bias is observed. A more complex bias-correction method should be further investigated to remedy this weakness and take more advantage of the ensemble forecasts produced by the climate model. Overall, in this study, bias-corrected ensemble meteorological forecasts appear to be an interesting source of information for hydrological forecasting for lead times up to 1 month. They could also complement ESP for longer lead times.

The software system development for the TAMU real-time fan beam scatterometer data processors

NASA Technical Reports Server (NTRS)

Clark, B. V.; Jean, B. R.

1980-01-01

A software package was designed and written to process in real-time any one quadrature channel pair of radar scatterometer signals form the NASA L- or C-Band radar scatterometer systems. The software was successfully tested in the C-Band processor breadboard hardware using recorded radar and NERDAS (NASA Earth Resources Data Annotation System) signals as the input data sources. The processor development program and the overall processor theory of operation and design are described. The real-time processor software system is documented and the results of the laboratory software tests, and recommendations for the efficient application of the data processing capabilities are presented.

Development of a compact and cost effective multi-input digital signal processing system

NASA Astrophysics Data System (ADS)

Darvish-Molla, Sahar; Chin, Kenrick; Prestwich, William V.; Byun, Soo Hyun

2018-01-01

A prototype digital signal processing system (DSP) was developed using a microcontroller interfaced with a 12-bit sampling ADC, which offers a considerably inexpensive solution for processing multiple detectors with high throughput. After digitization of the incoming pulses, in order to maximize the output counting rate, a simple algorithm was employed for pulse height analysis. Moreover, an algorithm aiming at the real-time pulse pile-up deconvolution was implemented. The system was tested using a NaI(Tl) detector in comparison with a traditional analogue and commercial digital systems for a variety of count rates. The performance of the prototype system was consistently superior to the analogue and the commercial digital systems up to the input count rate of 61 kcps while was slightly inferior to the commercial digital system but still superior to the analogue system in the higher input rates. Considering overall cost, size and flexibility, this custom made multi-input digital signal processing system (MMI-DSP) was the best reliable choice for the purpose of the 2D microdosimetric data collection, or for any measurement in which simultaneous multi-data collection is required.

DSP-Based Hands-On Laboratory Experiments for Photovoltaic Power Systems

ERIC Educational Resources Information Center

Muoka, Polycarp I.; Haque, Md. Enamul; Gargoom, Ameen; Negnetvitsky, Michael

2015-01-01

This paper presents a new photovoltaic (PV) power systems laboratory module that was developed to experimentally reinforce students' understanding of design principles, operation, and control of photovoltaic power conversion systems. The laboratory module is project-based and is designed to support a renewable energy course. By using MATLAB…

DSP30 enhances the immunosuppressive properties of mesenchymal stromal cells and protects their suppressive potential from lipopolysaccharide effects: A potential role of adenosine.

PubMed

Sangiorgi, Bruno; De Freitas, Helder Teixeira; Schiavinato, Josiane Lilian Dos Santos; Leão, Vitor; Haddad, Rodrigo; Orellana, Maristela Delgado; Faça, Vitor Marcel; Ferreira, Germano Aguiar; Covas, Dimas Tadeu; Zago, Marco Antônio; Panepucci, Rodrigo Alexandre

2016-07-01

Multipotent mesenchymal stromal cells (MSC) are imbued with an immunosuppressive phenotype that extends to several immune system cells. In this study, we evaluated how distinct Toll-like receptor (TLR) agonists impact immunosuppressive properties of bone marrow (BM)-MSC and explored the potential mechanisms involved. We show that TLR4 stimulation by lipopolysaccharide (LPS) restricted the ability of MSC to suppress the proliferation of T lymphocytes, increasing the gene expression of interleukin (IL)-1β and IL-6. In contrast, stimulation of TLR9 by DSP30 induced proliferation and the suppressive potential of BM-MSC, coinciding with reducing tumor necrosis factor (TNF)-α expression, increased expression of transforming growth factor (TGF)-β1, increased percentages of BM-MSC double positive for the ectonucleotidases CD39+CD73+ and adenosine levels. Importantly, following simultaneous stimulation with LPS and DSP30, BM-MSC's ability to suppress T lymphocyte proliferation was comparable with that of non-stimulated BM-MSC levels. Moreover, stimulation of BM-MSC with LPS reduced significantly the gene expression levels, on co-cultured T lymphocyte, of IL-10 and interferon (IFN)γ, a cytokine with potential to enhance the immunosuppression mediated by MSC and ameliorate the clinical outcome of patients with graft-versus-host disease (GVHD). Altogether, our findings reiterate the harmful effects of LPS on MSC immunosuppression, besides indicating that DSP30 could provide a protective effect against LPS circulating in the blood of GVHD patients who receive BM-MSC infusions, ensuring a more predictable immunosuppressive effect. The novel effects and potential mechanisms following the stimulation of BM-MSC by DSP30 might impact their clinical use, by allowing the derivation of optimal "licensing" protocols for obtaining therapeutically efficient MSC. Copyright © 2016 International Society for Cellular Therapy. Published by Elsevier Inc. All rights reserved.

Design and initial validation of a wireless control system based on WSN

NASA Astrophysics Data System (ADS)

Yu, Yan; Li, Luyu; Li, Peng; Wang, Xu; Liu, Hang; Ou, Jinping

2013-04-01

At present, cantilever structure used widely in civil structures will generate continuous vibration by external force due to their low damping characteristic, which leads to a serious impact on the working performance and service time. Therefore, it is very important to control the vibration of these structures. The active vibration control is the primary means of controlling the vibration with high precision and strong adaptive ability. Nowadays, there are many researches using piezoelectric materials in the structural vibration control. Piezoelectric materials are cheap, reliable and they can provide braking and sensing method harmless to the structure, therefore they have broad usage. They are used for structural vibration control in a lot of civil engineering research currently. In traditional sensor applications, information exchanges with the monitoring center or a computer system through wires. If wireless sensor networks(WSN) technology is used, cabling links is not needed, thus the cost of the whole system is greatly reduced. Based on the above advantages, a wireless control system is designed and validated through preliminary tests. The system consists of a cantilever, PVDF as sensor, signal conditioning circuit(SCM), A/D acquisition board, control arithmetic unit, D/A output board, power amplifier, piezoelectric bimorph as actuator. DSP chip is used as the control arithmetic unit and PD control algorithm is embedded in it. PVDF collects the parameters of vibration, sends them to the SCM after A/D conversion. SCM passes the data to the DSP through wireless technology, and DSP calculates and outputs the control values according to the control algorithm. The output signal is amplified by the power amplifier to drive the piezoelectric bimorph for vibration control. The structural vibration duration reduces to 1/4 of the uncontrolled case, which verifies the feasibility of the system.

Porcine dentin sialoprotein glycosylation and glycosaminoglycan attachments

PubMed Central

2011-01-01

Background Dentin sialophosphoprotein (Dspp) is a multidomain, secreted protein that is critical for the formation of tooth dentin. Mutations in DSPP cause inherited dentin defects categorized as dentin dysplasia type II and dentinogenesis imperfecta type II and type III. Dentin sialoprotein (Dsp), the N-terminal domain of dentin sialophosphoprotein (Dspp), is a highly glycosylated proteoglycan, but little is known about the number, character, and attachment sites of its carbohydrate moieties. Results To identify its carbohydrate attachment sites we isolated Dsp from developing porcine molars and digested it with endoproteinase Glu-C or pronase, fractionated the digestion products, identified fractions containing glycosylated peptides using a phenol sulfuric acid assay, and characterized the glycopeptides by N-terminal sequencing, amino acid analyses, or LC/MSMS. To determine the average number of sialic acid attachments per N-glycosylation, we digested Dsp with glycopeptidase A, labeled the released N-glycosylations with 2-aminobenzoic acid, and quantified the moles of released glycosylations by comparison to labeled standards of known concentration. Sialic acid was released by sialidase digestion and quantified by measuring β-NADH reduction of pyruvic acid, which was generated stoichiometrically from sialic acid by aldolase. To determine its forms, sialic acid released by sialidase digestion was labeled with 1,2-diamino-4,5-methyleneoxybenzene (DMB) and compared to a DMB-labeled sialic acid reference panel by RP-HPLC. To determine the composition of Dsp glycosaminoglycan (GAG) attachments, we digested Dsp with chondroitinase ABC and compared the chromotagraphic profiles of the released disaccharides to commercial standards. N-glycosylations were identified at Asn37, Asn77, Asn136, Asn155, Asn161, and Asn176. Dsp averages one sialic acid per N-glycosylation, which is always in the form of N-acetylneuraminic acid. O-glycosylations were tentatively assigned at Thr200, Thr216 and Thr316. Porcine Dsp GAG attachments were found at Ser238 and Ser250 and were comprised of chondroitin 6-sulfate and chondroitin 4-sulfate in a ratio of 7 to 3, respectively. Conclusions The distribution of porcine Dsp posttranslational modifications indicate that porcine Dsp has an N-terminal domain with at least six N-glycosylations and a C-terminal domain with two GAG attachments and at least two O-glycosylations. PMID:21291557

DSP30 and interleukin-2 as a mitotic stimulant in B-cell disorders including those with a low disease burden.

PubMed

Dun, Karen A; Riley, Louise A; Diano, Giuseppe; Adams, Leanne B; Chiu, Eleanor; Sharma, Archna

2018-05-01

Chromosome abnormalities detected during cytogenetic investigations for B-cell malignancy offer prognostic information that can have wide ranging clinical impacts on patients. These impacts may include monitoring frequency, treatment type, and disease staging level. The use of the synthetic oligonucleotide DSP30 combined with interleukin 2 (IL2) has been described as an effective mitotic stimulant in B-cell disorders, not only in chronic lymphocytic leukemia (CLL) but also in a range of other B-cell malignancies. Here, we describe the comparison of two B-cell mitogens, lipopolysaccharide (LPS), and DSP30 combined with IL2 as mitogens in a range of common B-cell disorders excluding CLL. The results showed that DSP30/IL2 was an effective mitogen in mature B-cell disorders, revealing abnormal cytogenetic results in a range of B-cell malignancies. The abnormality rate increased when compared to the use of LPS to 64% (DSP30/IL2) from 14% (LPS). In a number of cases the disease burden was proportionally very low, less than 10% of white cells. In 37% of these cases, the DSP30 culture revealed abnormal results. Importantly, we also obtained abnormal conventional cytogenetics results in 3 bone marrow cases in which immunophenotyping showed an absence of an abnormal B-cell clone. In these cases, the cytogenetics results correlated with the provisional diagnosis and altered their staging level. The use of DSP30 and IL2 is recommended for use in many B-cell malignancies as an effective mitogen and their use has been shown to enable successful culture of the malignant clone, even at very low levels of disease. © 2018 Wiley Periodicals, Inc.

Development of a Novel, Two-Processor Architecture for a Small UAV Autopilot System,

DTIC Science & Technology

2006-07-26

is, and the control laws the user implements to control it. The flight control system board will contain the processor selected for this system...Unit (IMU). The IMU contains solid-state gyros and accelerometers and uses these to determine the attitude of the UAV within the three dimensions of...multiple-UAV swarming for combat support operations. The mission processor board will contain the processor selected to execute the mission

Neuroprotective effect and mechanism of daucosterol palmitate in ameliorating learning and memory impairment in a rat model of Alzheimer's disease.

PubMed

Ji, Zhi-Hong; Xu, Zhong-Qi; Zhao, Hong; Yu, Xin-Yu

2017-03-01

Alzheimer's disease (AD) is an age-related neurodegenerative disorder characterized by progressive memory decline and cognitive impairment. Amyloid beta (Aβ) has been proposed as the causative role for the pathogenesis of AD. Accumulating evidence demonstrates that Aβ neurotoxicity is mediated by glutamate excitotoxicity. Daucosterol palmitate (DSP), a plant steroid with anti-glutamate excitotoxicity effect, was isolated from the anti-aging traditional Chinese medicinal herb Alpinia oxyphylla Miq. in our previous study. Based on the anti-glutamate excitotoxicity effect of DSP, in this study we investigated potential benefit and mechanism of DSP in ameliorating learning and memory impairment in AD model rats. Results from this study showed that DSP administration effectively ameliorated Aβ-induced learning and memory impairment in rats, markedly inhibited Aβ-induced hippocampal ROS production, effectively prevented Aβ-induced hippocampal neuronal damage and significantly restored hippocampal synaptophysin expression level. This study suggests that DSP may be a potential candidate for development as a therapeutic agent for AD cognitive decline. Copyright © 2017 Elsevier Inc. All rights reserved.

Conditional load and store in a shared memory

DOEpatents

Blumrich, Matthias A; Ohmacht, Martin

2015-02-03

A method, system and computer program product for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of processor units and a shared memory cache, and each of the processor units has access to the memory cache. In one embodiment, the method comprises providing the memory cache with a series of reservation registers, and storing in these registers addresses reserved in the memory cache for the processor units as a result of issuing load-reserve requests. In this embodiment, when one of the processor units makes a request to store data in the memory cache using a store-conditional request, the reservation registers are checked to determine if an address in the memory cache is reserved for that processor unit. If an address in the memory cache is reserved for that processor, the data are stored at this address.

STS-44 Defense Support Program (DSP) / IUS during preflight operations

NASA Technical Reports Server (NTRS)

1991-01-01

STS-44 Defense Support Program (DSP) satellite atop the inertial upper stage (IUS) is prepared for transfer in a processing facility at Cape Canaveral Air Force Station. Clean-suited technicians overseeing the operation are dwarfed by the size of the 5,200-pound DSP satellite and the IUS. The underside of the IUS (bottom) mounted in the airborne support equipment (ASE) aft frame tilt actuator (AFTA) table and ASE forward frame is visible at the base. The umbilical boom between the two ASE frames and the forward frame keel trunnion are visible. DSP, a surveillance satellite that can detect missle and space launches as well as nuclear detonations will be boosted into geosynchronous Earth orbit by the IUS. View provided by KSC with alternate number KSC-91PC-1749.

Compromise decision support problems for hierarchical design involving uncertainty

NASA Astrophysics Data System (ADS)

Vadde, S.; Allen, J. K.; Mistree, F.

1994-08-01

In this paper an extension to the traditional compromise Decision Support Problem (DSP) formulation is presented. Bayesian statistics is used in the formulation to model uncertainties associated with the information being used. In an earlier paper a compromise DSP that accounts for uncertainty using fuzzy set theory was introduced. The Bayesian Decision Support Problem is described in this paper. The method for hierarchical design is demonstrated by using this formulation to design a portal frame. The results are discussed and comparisons are made with those obtained using the fuzzy DSP. Finally, the efficacy of incorporating Bayesian statistics into the traditional compromise DSP formulation is discussed and some pending research issues are described. Our emphasis in this paper is on the method rather than the results per se.

Verification of a Proposed Clinical Electroacoustic Test Protocol for Personal Digital Modulation Receivers Coupled to Cochlear Implant Sound Processors.

PubMed

Nair, Erika L; Sousa, Rhonda; Wannagot, Shannon

Guidelines established by the AAA currently recommend behavioral testing when fitting frequency modulated (FM) systems to individuals with cochlear implants (CIs). A protocol for completing electroacoustic measures has not yet been validated for personal FM systems or digital modulation (DM) systems coupled to CI sound processors. In response, some professionals have used or altered the AAA electroacoustic verification steps for fitting FM systems to hearing aids when fitting FM systems to CI sound processors. More recently steps were outlined in a proposed protocol. The purpose of this research is to review and compare the electroacoustic test measures outlined in a 2013 article by Schafer and colleagues in the Journal of the American Academy of Audiology titled "A Proposed Electroacoustic Test Protocol for Personal FM Receivers Coupled to Cochlear Implant Sound Processors" to the AAA electroacoustic verification steps for fitting FM systems to hearing aids when fitting DM systems to CI users. Electroacoustic measures were conducted on 71 CI sound processors and Phonak Roger DM systems using a proposed protocol and an adapted AAA protocol. Phonak's recommended default receiver gain setting was used for each CI sound processor manufacturer and adjusted if necessary to achieve transparency. Electroacoustic measures were conducted on Cochlear and Advanced Bionics (AB) sound processors. In this study, 28 Cochlear Nucleus 5/CP810 sound processors, 26 Cochlear Nucleus 6/CP910 sound processors, and 17 AB Naida CI Q70 sound processors were coupled in various combinations to Phonak Roger DM dedicated receivers (25 Phonak Roger 14 receivers-Cochlear dedicated receiver-and 9 Phonak Roger 17 receivers-AB dedicated receiver) and 20 Phonak Roger Inspiro transmitters. Employing both the AAA and the Schafer et al protocols, electroacoustic measurements were conducted with the Audioscan Verifit in a clinical setting on 71 CI sound processors and Phonak Roger DM systems to determine transparency and verify FM advantage, comparing speech inputs (65 dB SPL) in an effort to achieve equal outputs. If transparency was not achieved at Phonak's recommended default receiver gain, adjustments were made to the receiver gain. The integrity of the signal was monitored with the appropriate manufacturer's monitor earphones. Using the AAA hearing aid protocol, 50 of the 71 CI sound processors achieved transparency, and 59 of the 71 CI sound processors achieved transparency when using the proposed protocol at Phonak's recommended default receiver gain. After the receiver gain was adjusted, 3 of 21 CI sound processors still did not meet transparency using the AAA protocol, and 2 of 12 CI sound processors still did not meet transparency using the Schafer et al proposed protocol. Both protocols were shown to be effective in taking reliable electroacoustic measurements and demonstrate transparency. Both protocols are felt to be clinically feasible and to address the needs of populations that are unable to reliably report regarding the integrity of their personal DM systems. American Academy of Audiology

Development and analysis of the Software Implemented Fault-Tolerance (SIFT) computer

NASA Technical Reports Server (NTRS)

Goldberg, J.; Kautz, W. H.; Melliar-Smith, P. M.; Green, M. W.; Levitt, K. N.; Schwartz, R. L.; Weinstock, C. B.

1984-01-01

SIFT (Software Implemented Fault Tolerance) is an experimental, fault-tolerant computer system designed to meet the extreme reliability requirements for safety-critical functions in advanced aircraft. Errors are masked by performing a majority voting operation over the results of identical computations, and faulty processors are removed from service by reassigning computations to the nonfaulty processors. This scheme has been implemented in a special architecture using a set of standard Bendix BDX930 processors, augmented by a special asynchronous-broadcast communication interface that provides direct, processor to processor communication among all processors. Fault isolation is accomplished in hardware; all other fault-tolerance functions, together with scheduling and synchronization are implemented exclusively by executive system software. The system reliability is predicted by a Markov model. Mathematical consistency of the system software with respect to the reliability model has been partially verified, using recently developed tools for machine-aided proof of program correctness.

HST Imaging of the Eye of Horus, a Double Source Plane Gravitational Lens

NASA Astrophysics Data System (ADS)

Wong, Kenneth

2017-08-01

Double source plane (DSP) gravitational lenses are extremely rare alignments of a massive lens galaxy with two background sources at distinct redshifts. The presence of two source planes provides important constraints on cosmology and galaxy structure beyond that of typical lens systems by breaking degeneracies between parameters that vary with source redshift. While these systems are extremely valuable, only a handful are known. We have discovered the first DSP lens, the Eye of Horus, in the Hyper Suprime-Cam survey and have confirmed both source redshifts with follow-up spectroscopy, making this the only known DSP lens with both source redshifts measured. Furthermore, the brightest image of the most distant source (S2) is split into a pair of images by a mass component that is undetected in our ground-based data, suggesting the presence of a satellite or line-of-sight galaxy causing this splitting. In order to better understand this system and use it for cosmology and galaxy studies, we must construct an accurate lens model, accounting for the lensing effects of both the main lens galaxy and the intermediate source. Only with deep, high-resolution imaging from HST/ACS can we accurately model this system. Our proposed multiband imaging will clearly separate out the two sources by their distinct colors, allowing us to use their extended surface brightness distributions as constraints on our lens model. These data may also reveal the satellite galaxy responsible for the splitting of the brightest image of S2. With these observations, we will be able to take full advantage of the wealth of information provided by this system.

A Hydraulic Blowdown Servo System For Launch Vehicle

NASA Astrophysics Data System (ADS)

Chen, Anping; Deng, Tao

2016-07-01

This paper introduced a hydraulic blowdown servo system developed for a solid launch vehicle of the family of Chinese Long March Vehicles. It's the thrust vector control (TVC) system for the first stage. This system is a cold gas blowdown hydraulic servo system and consist of gas vessel, hydraulic reservoir, servo actuator, digital control unit (DCU), electric explosion valve, and pressure regulator etc. A brief description of the main assemblies and characteristics follows. a) Gas vessel is a resin/carbon fiber composite over wrapped pressure vessel with a titanium liner, The volume of the vessel is about 30 liters. b) Hydraulic reservoir is a titanium alloy piston type reservoir with a magnetostrictive sensor as the fluid level indicator. The volume of the reservoir is about 30 liters. c) Servo actuator is a equal area linear piston actuator with a 2-stage low null leakage servo valve and a linear variable differential transducer (LVDT) feedback the piston position, Its stall force is about 120kN. d) Digital control unit (DCU) is a compact digital controller based on digital signal processor (DSP), and deployed dual redundant 1553B digital busses to communicate with the on board computer. e) Electric explosion valve is a normally closed valve to confine the high pressure helium gas. f) Pressure regulator is a spring-loaded poppet pressure valve, and regulates the gas pressure from about 60MPa to about 24MPa. g) The whole system is mounted in the aft skirt of the vehicle. h) This system delivers approximately 40kW hydraulic power, by contrast, the total mass is less than 190kg. the power mass ratio is about 0.21. Have finished the development and the system test. Bench and motor static firing tests verified that all of the performances have met the design requirements. This servo system is complaint to use of the solid launch vehicle.

The role of neurologists and diagnostic tests in the management of distal symmetric polyneuropathy

PubMed Central

Callaghan, Brian C.; Kerber, Kevin A.; Lisabeth, Lynda L.; Morgenstern, Lewis B.; Longoria, Ruth; Rodgers, Ann; Longwell, Paxton; Feldman, Eva L.

2014-01-01

Importance Distal symmetric polyneuropathy (DSP) is a prevalent condition resulting in high costs from diagnostic testing. However, the role of neurologists and diagnostic tests on patient care is unknown. Objective To determine how often neurologists and diagnostic tests influence the diagnosis and management of DSP patients in a community setting. Design We utilized a validated case-capture method (ICD-9 screening technique with subsequent medical chart abstraction) to identify patients with a new DSP diagnosis (retrospective cohort). Using a structured data abstraction process, diagnostic testing, diagnoses rendered (before and after testing), and subsequent management were recorded. Setting Community neurologist’s outpatient offices in Corpus Christi, Texas. Participants Patients meeting the Toronto consensus criteria for probable DSP. Main Outcome Measure Changes in etiology and management after diagnostic testing by neurologists. Results Between 1/1/2010–3/31/2011, we identified 458 DSP patients followed for mean (SD) 435.3 (44.1) days. Neurologists identified a cause of DSP in 63.5% of cases prior to their diagnostic testing. Seventy-one patients (15.5%) had a new DSP cause discovered after testing by neurologists. The most common new diagnoses were pre-diabetes (N=28), B12 deficiency (N=20), diabetes (N=8), and thyroid disease (N=8). Management changes were common (63.1%), usually related to neuropathic pain management (77.5%). Disease modifying management changes occurred in 24.7% with diabetes management (N=45), starting vitamins (N=39), advising diet/exercise (N=33), and adjusting thyroid medications (N=10) the most common. Electrodiagnostic testing and MRIs of the neuroaxis rarely led to management changes. Conclusions and Relevance Neurologists diagnosed the cause of DSP in almost two-thirds of patients prior to their diagnostic testing. Inexpensive blood tests for diabetes, thyroid dysfunction, and B12 deficiency, allowed neurologists to identify a new etiology in 15.5% of patients. In contrast, expensive electrodiagnostic tests and MRIs rarely changed patient care. Neurologists also frequently made pain medication changes utilizing best evidence medications. PMID:25048157

Evaluation of Rapid, Early Warning Approaches to Track Shellfish Toxins Associated with Dinophysis and Alexandrium Blooms

PubMed Central

Hattenrath-Lehmann, Theresa K.; Lusty, Mark W.; Wallace, Ryan B.; Haynes, Bennie; Wang, Zhihong; Broadwater, Maggie; Deeds, Jonathan R.; Morton, Steve L.; Hastback, William; Porter, Leonora; Chytalo, Karen

2018-01-01

Marine biotoxin-contaminated seafood has caused thousands of poisonings worldwide this century. Given these threats, there is an increasing need for improved technologies that can be easily integrated into coastal monitoring programs. This study evaluates approaches for monitoring toxins associated with recurrent toxin-producing Alexandrium and Dinophysis blooms on Long Island, NY, USA, which cause paralytic and diarrhetic shellfish poisoning (PSP and DSP), respectively. Within contrasting locations, the dynamics of pelagic Alexandrium and Dinophysis cell densities, toxins in plankton, and toxins in deployed blue mussels (Mytilus edulis) were compared with passive solid-phase adsorption toxin tracking (SPATT) samplers filled with two types of resin, HP20 and XAD-2. Multiple species of wild shellfish were also collected during Dinophysis blooms and used to compare toxin content using two different extraction techniques (single dispersive and double exhaustive) and two different toxin analysis assays (liquid chromatography/mass spectrometry and the protein phosphatase inhibition assay (PP2A)) for the measurement of DSP toxins. DSP toxins measured in the HP20 resin were significantly correlated (R2 = 0.7–0.9, p < 0.001) with total DSP toxins in shellfish, but were detected more than three weeks prior to detection in deployed mussels. Both resins adsorbed measurable levels of PSP toxins, but neither quantitatively tracked Alexandrium cell densities, toxicity in plankton or toxins in shellfish. DSP extraction and toxin analysis methods did not differ significantly (p > 0.05), were highly correlated (R2 = 0.98–0.99; p < 0.001) and provided complete recovery of DSP toxins from standard reference materials. Blue mussels (Mytilus edulis) and ribbed mussels (Geukensia demissa) were found to accumulate DSP toxins above federal and international standards (160 ng g−1) during Dinophysis blooms while Eastern oysters (Crassostrea virginica) and soft shell clams (Mya arenaria) did not. This study demonstrated that SPATT samplers using HP20 resin coupled with PP2A technology could be used to provide early warning of DSP, but not PSP, events for shellfish management. PMID:29342840

Development of a wireless system for auditory neuroscience.

PubMed

Lukes, A J; Lear, A T; Snider, R K

2001-01-01

In order to study how the auditory cortex extracts communication sounds in a realistic acoustic environment, a wireless system is being developed that will transmit acoustic as well as neural signals. The miniature transmitter will be capable of transmitting two acoustic signals with 37.5 KHz bandwidths (75 KHz sample rate) and 56 neural signals with bandwidths of 9.375 KHz (18.75 KHz sample rate). These signals will be time-division multiplexed into one high bandwidth signal with a 1.2 MHz sample rate. This high bandwidth signal will then be frequency modulated onto a 2.4 GHz carrier, which resides in the industrial, scientic, and medical (ISM) band that is designed for low-power short-range wireless applications. On the receiver side, the signal will be demodulated from the 2.4 GHz carrier and then digitized by an analog-to-digital (A/D) converter. The acoustic and neural signals will be digitally demultiplexed from the multiplexed signal into their respective channels. Oversampling (20 MHz) will allow the reconstruction of the multiplexing clock by a digital signal processor (DSP) that will perform frame and bit synchronization. A frame is a subset of the signal that contains all the channels and several channels tied high and low will signal the start of a frame. This technological development will bring two benefits to auditory neuroscience. It will allow simultaneous recording of many neurons that will permit studies of population codes. It will also allow neural functions to be determined in higher auditory areas by correlating neural and acoustic signals without apriori knowledge of the necessary stimuli.

An image-processing strategy to extract important information suitable for a low-size stimulus pattern in a retinal prosthesis.

PubMed

Chen, Yili; Fu, Jixiang; Chu, Dawei; Li, Rongmao; Xie, Yaoqin

2017-11-27

A retinal prosthesis is designed to help the blind to obtain some sight. It consists of an external part and an internal part. The external part is made up of a camera, an image processor and an RF transmitter. The internal part is made up of an RF receiver, implant chip and microelectrode. Currently, the number of microelectrodes is in the hundreds, and we do not know the mechanism for using an electrode to stimulate the optic nerve. A simple hypothesis is that the pixels in an image correspond to the electrode. The images captured by the camera should be processed by suitable strategies to correspond to stimulation from the electrode. Thus, it is a question of how to obtain the important information from the image captured in the picture. Here, we use the region of interest (ROI), a useful algorithm for extracting the ROI, to retain the important information, and to remove the redundant information. This paper explains the details of the principles and functions of the ROI. Because we are investigating a real-time system, we need a fast processing ROI as a useful algorithm to extract the ROI. Thus, we simplified the ROI algorithm and used it in an outside image-processing digital signal processing (DSP) system of the retinal prosthesis. The results show that our image-processing strategies are suitable for a real-time retinal prosthesis and can eliminate redundant information and provide useful information for expression in a low-size image.

Jamming protection of spread spectrum RFID system

NASA Astrophysics Data System (ADS)

Mazurek, Gustaw

2006-10-01

This paper presents a new transform-domain processing algorithm for rejection of narrowband interferences in RFID/DS-CDMA systems. The performance of the proposed algorithm has been verified via computer simulations. Implementation issues have been discussed. The algorithm can be implemented in the FPGA or DSP technology.

Integrated High Resolution Digital Color Light Sensor in 130 nm CMOS Technology

PubMed Central

Strle, Drago; Nahtigal, Uroš; Batistell, Graciele; Zhang, Vincent Chi; Ofner, Erwin; Fant, Andrea; Sturm, Johannes

2015-01-01

This article presents a color light detection system integrated in 130 nm CMOS technology. The sensors and corresponding electronics detect light in a CIE XYZ color luminosity space using on-chip integrated sensors without any additional process steps, high-resolution analog-to-digital converter, and dedicated DSP algorithm. The sensor consists of a set of laterally arranged integrated photodiodes that are partly covered by metal, where color separation between the photodiodes is achieved by lateral carrier diffusion together with wavelength-dependent absorption. A high resolution, hybrid, ∑∆ ADC converts each photo diode’s current into a 22-bit digital result, canceling the dark current of the photo diodes. The digital results are further processed by the DSP, which calculates normalized XYZ or RGB color and intensity parameters using linear transformations of the three photo diode responses by multiplication of the data with a transformation matrix, where the coefficients are extracted by training in combination with a pseudo-inverse operation and the least-mean square approximation. The sensor system detects the color light parameters with 22-bit accuracy, consumes less than 60 μA on average at 10 readings per second, and occupies approx. 0.8 mm2 of silicon area (including three photodiodes and the analog part of the ADC). The DSP is currently implemented on FPGA. PMID:26205275

Potential of minicomputer/array-processor system for nonlinear finite-element analysis

NASA Technical Reports Server (NTRS)

Strohkorb, G. A.; Noor, A. K.

1983-01-01

The potential of using a minicomputer/array-processor system for the efficient solution of large-scale, nonlinear, finite-element problems is studied. A Prime 750 is used as the host computer, and a software simulator residing on the Prime is employed to assess the performance of the Floating Point Systems AP-120B array processor. Major hardware characteristics of the system such as virtual memory and parallel and pipeline processing are reviewed, and the interplay between various hardware components is examined. Effective use of the minicomputer/array-processor system for nonlinear analysis requires the following: (1) proper selection of the computational procedure and the capability to vectorize the numerical algorithms; (2) reduction of input-output operations; and (3) overlapping host and array-processor operations. A detailed discussion is given of techniques to accomplish each of these tasks. Two benchmark problems with 1715 and 3230 degrees of freedom, respectively, are selected to measure the anticipated gain in speed obtained by using the proposed algorithms on the array processor.

A universal computer control system for motors

NASA Technical Reports Server (NTRS)

Szakaly, Zoltan F. (Inventor)

1991-01-01

A control system for a multi-motor system such as a space telerobot, having a remote computational node and a local computational node interconnected with one another by a high speed data link is described. A Universal Computer Control System (UCCS) for the telerobot is located at each node. Each node is provided with a multibus computer system which is characterized by a plurality of processors with all processors being connected to a common bus, and including at least one command processor. The command processor communicates over the bus with a plurality of joint controller cards. A plurality of direct current torque motors, of the type used in telerobot joints and telerobot hand-held controllers, are connected to the controller cards and responds to digital control signals from the command processor. Essential motor operating parameters are sensed by analog sensing circuits and the sensed analog signals are converted to digital signals for storage at the controller cards where such signals can be read during an address read/write cycle of the command processing processor.

Rapid Damage Assessment. Volume II. Development and Testing of Rapid Damage Assessment System.

DTIC Science & Technology

1981-02-01

pixels/s Camera Line Rate 732.4 lines/s Pixels per Line 1728 video 314 blank 4 line number (binary) 2 run number (BCD) 2048 total Pixel Resolution 8 bits...sists of an LSI-ll microprocessor, a VDI -200 video display processor, an FD-2 dual floppy diskette subsystem, an FT-I function key-trackball module...COMPONENT LIST FOR IMAGE PROCESSOR SYSTEM IMAGE PROCESSOR SYSTEM VIEWS I VDI -200 Display Processor Racks, Table FD-2 Dual Floppy Diskette Subsystem FT-l

DHS Internship Paper

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dreyer, J

2007-09-18

During my internship at Lawrence Livermore National Laboratory I worked with microcalorimeter gamma-ray and fast-neutron detectors based on superconducting Transition Edge Sensors (TESs). These instruments are being developed for fundamental science and nuclear non-proliferation applications because of their extremely high energy resolution; however, this comes at the expense of a small pixel size and slow decay times. The small pixel sizes are being addressed by developing detector arrays while the low count rate is being addressed by developing Digital Signal Processors (DSPs) that allow higher throughput than traditional pulse processing algorithms. Traditionally, low-temperature microcalorimeter pulses have been processed off-line withmore » optimum filtering routines based on the measured spectral characteristics of the signal and the noise. These optimum filters rely on the spectral content of the signal being identical for all events, and therefore require capturing the entire pulse signal without pile-up. In contrast, the DSP algorithm being developed is based on differences in signal levels before and after a trigger event, and therefore does not require the waveform to fully decay, or even the signal level to be close to the base line. The readout system allows for real time data acquisition and analysis at count rates exceeding 100 Hz for pulses with several {approx}ms decay times with minimal loss of energy resolution. Originally developed for gamma-ray analysis with HPGe detectors we have modified the hardware and firmware of the system to accommodate the slower TES signals and optimized the parameters of the filtering algorithm to maximize either resolution or throughput. The following presents an overview of the digital signal processing hardware and discusses the results of characterization measurements made to determine the systems performance.« less

Ultrasound phase rotation beamforming on multi-core DSP.

PubMed

Ma, Jieming; Karadayi, Kerem; Ali, Murtaza; Kim, Yongmin

2014-01-01

Phase rotation beamforming (PRBF) is a commonly-used digital receive beamforming technique. However, due to its high computational requirement, it has traditionally been supported by hardwired architectures, e.g., application-specific integrated circuits (ASICs) or more recently field-programmable gate arrays (FPGAs). In this study, we investigated the feasibility of supporting software-based PRBF on a multi-core DSP. To alleviate the high computing requirement, the analog front-end (AFE) chips integrating quadrature demodulation in addition to analog-to-digital conversion were defined and used. With these new AFE chips, only delay alignment and phase rotation need to be performed by DSP, substantially reducing the computational load. We implemented the delay alignment and phase rotation modules on a Texas Instruments C6678 DSP with 8 cores. We found it takes 200 μs to beamform 2048 samples from 64 channels using 2 cores. With 4 cores, 20 million samples can be beamformed in one second. Therefore, ADC frequencies up to 40 MHz with 2:1 decimation in AFE chips or up to 20 MHz with no decimation can be supported as long as the ADC-to-DSP I/O requirement can be met. The remaining 4 cores can work on back-end processing tasks and applications, e.g., color Doppler or ultrasound elastography. One DSP being able to handle both beamforming and back-end processing could lead to low-power and low-cost ultrasound machines, benefiting ultrasound imaging in general, particularly portable ultrasound machines. Copyright © 2013 Elsevier B.V. All rights reserved.

Future applications of associative processor systems to operational KSC systems for optimizing cost and enhancing performance characteristics

NASA Technical Reports Server (NTRS)

Perkinson, J. A.

1974-01-01

The application of associative memory processor equipment to conventional host processors type systems is discussed. Efforts were made to demonstrate how such application relieves the task burden of conventional systems, and enhance system speed and efficiency. Data cover comparative theoretical performance analysis, demonstration of expanded growth capabilities, and demonstrations of actual hardware in simulated environment.

System Control Facilities: Head-Ends and Central Processors. A Survey of Technical Requirements for Broadband Cable Teleservices; Volume Four.

ERIC Educational Resources Information Center

Smith, Ernest K.; And Others

The system control facilities in broadband communication systems are discussed in this report. These facilities consist of head-ends and central processors. The first section summarizes technical problems and needs, and the second offers a cursory overview of systems, along with an incidental mention of processors. Section 3 looks at the question…

Design and testing of a 750MHz CW-EPR digital console for small animal imaging.

PubMed

Sato-Akaba, Hideo; Emoto, Miho C; Hirata, Hiroshi; Fujii, Hirotada G

2017-11-01

This paper describes the development of a digital console for three-dimensional (3D) continuous wave electron paramagnetic resonance (CW-EPR) imaging of a small animal to improve the signal-to-noise ratio and lower the cost of the EPR imaging system. A RF generation board, an RF acquisition board and a digital signal processing (DSP) & control board were built for the digital EPR detection. Direct sampling of the reflected RF signal from a resonator (approximately 750MHz), which contains the EPR signal, was carried out using a band-pass subsampling method. A direct automatic control system to reduce the reflection from the resonator was proposed and implemented in the digital EPR detection scheme. All DSP tasks were carried out in field programmable gate array ICs. In vivo 3D imaging of nitroxyl radicals in a mouse's head was successfully performed. Copyright © 2017 Elsevier Inc. All rights reserved.

Design and testing of a 750 MHz CW-EPR digital console for small animal imaging

NASA Astrophysics Data System (ADS)

Sato-Akaba, Hideo; Emoto, Miho C.; Hirata, Hiroshi; Fujii, Hirotada G.

2017-11-01

This paper describes the development of a digital console for three-dimensional (3D) continuous wave electron paramagnetic resonance (CW-EPR) imaging of a small animal to improve the signal-to-noise ratio and lower the cost of the EPR imaging system. A RF generation board, an RF acquisition board and a digital signal processing (DSP) & control board were built for the digital EPR detection. Direct sampling of the reflected RF signal from a resonator (approximately 750 MHz), which contains the EPR signal, was carried out using a band-pass subsampling method. A direct automatic control system to reduce the reflection from the resonator was proposed and implemented in the digital EPR detection scheme. All DSP tasks were carried out in field programmable gate array ICs. In vivo 3D imaging of nitroxyl radicals in a mouse's head was successfully performed.

Further optimization of SeDDaRA blind image deconvolution algorithm and its DSP implementation

NASA Astrophysics Data System (ADS)

Wen, Bo; Zhang, Qiheng; Zhang, Jianlin

2011-11-01

Efficient algorithm for blind image deconvolution and its high-speed implementation is of great value in practice. Further optimization of SeDDaRA is developed, from algorithm structure to numerical calculation methods. The main optimization covers that, the structure's modularization for good implementation feasibility, reducing the data computation and dependency of 2D-FFT/IFFT, and acceleration of power operation by segmented look-up table. Then the Fast SeDDaRA is proposed and specialized for low complexity. As the final implementation, a hardware system of image restoration is conducted by using the multi-DSP parallel processing. Experimental results show that, the processing time and memory demand of Fast SeDDaRA decreases 50% at least; the data throughput of image restoration system is over 7.8Msps. The optimization is proved efficient and feasible, and the Fast SeDDaRA is able to support the real-time application.

Green Secure Processors: Towards Power-Efficient Secure Processor Design

NASA Astrophysics Data System (ADS)

Chhabra, Siddhartha; Solihin, Yan

With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the software stack of a system, hardware attacks have become equally likely. Researchers have proposed Secure Processor Architectures which utilize hardware mechanisms for memory encryption and integrity verification to protect the confidentiality and integrity of data and computation, even from sophisticated hardware attacks. While there have been many works addressing performance and other system level issues in secure processor design, power issues have largely been ignored. In this paper, we first analyze the sources of power (energy) increase in different secure processor architectures. We then present a power analysis of various secure processor architectures in terms of their increase in power consumption over a base system with no protection and then provide recommendations for designs that offer the best balance between performance and power without compromising security. We extend our study to the embedded domain as well. We also outline the design of a novel hybrid cryptographic engine that can be used to minimize the power consumption for a secure processor. We believe that if secure processors are to be adopted in future systems (general purpose or embedded), it is critically important that power issues are considered in addition to performance and other system level issues. To the best of our knowledge, this is the first work to examine the power implications of providing hardware mechanisms for security.

Contextual classification on a CDC Flexible Processor system. [for photomapped remote sensing data

NASA Technical Reports Server (NTRS)

Smith, B. W.; Siegel, H. J.; Swain, P. H.

1981-01-01

A potential hardware organization for the Flexible Processor Array is presented. An algorithm that implements a contextual classifier for remote sensing data analysis is given, along with uniprocessor classification algorithms. The Flexible Processor algorithm is provided, as are simulated timings for contextual classifiers run on the Flexible Processor Array and another system. The timings are analyzed for context neighborhoods of sizes three and nine.

Imaging system design and image interpolation based on CMOS image sensor

NASA Astrophysics Data System (ADS)

Li, Yu-feng; Liang, Fei; Guo, Rui

2009-11-01

An image acquisition system is introduced, which consists of a color CMOS image sensor (OV9620), SRAM (CY62148), CPLD (EPM7128AE) and DSP (TMS320VC5509A). The CPLD implements the logic and timing control to the system. SRAM stores the image data, and DSP controls the image acquisition system through the SCCB (Omni Vision Serial Camera Control Bus). The timing sequence of the CMOS image sensor OV9620 is analyzed. The imaging part and the high speed image data memory unit are designed. The hardware and software design of the image acquisition and processing system is given. CMOS digital cameras use color filter arrays to sample different spectral components, such as red, green, and blue. At the location of each pixel only one color sample is taken, and the other colors must be interpolated from neighboring samples. We use the edge-oriented adaptive interpolation algorithm for the edge pixels and bilinear interpolation algorithm for the non-edge pixels to improve the visual quality of the interpolated images. This method can get high processing speed, decrease the computational complexity, and effectively preserve the image edges.

The ATLAS Level-1 Calorimeter Trigger: PreProcessor implementation and performance

NASA Astrophysics Data System (ADS)

Åsman, B.; Achenbach, R.; Allbrooke, B. M. M.; Anders, G.; Andrei, V.; Büscher, V.; Bansil, H. S.; Barnett, B. M.; Bauss, B.; Bendtz, K.; Bohm, C.; Bracinik, J.; Brawn, I. P.; Brock, R.; Buttinger, W.; Caputo, R.; Caughron, S.; Cerrito, L.; Charlton, D. G.; Childers, J. T.; Curtis, C. J.; Daniells, A. C.; Davis, A. O.; Davygora, Y.; Dorn, M.; Eckweiler, S.; Edmunds, D.; Edwards, J. P.; Eisenhandler, E.; Ellis, K.; Ermoline, Y.; Föhlisch, F.; Faulkner, P. J. W.; Fedorko, W.; Fleckner, J.; French, S. T.; Gee, C. N. P.; Gillman, A. R.; Goeringer, C.; Hülsing, T.; Hadley, D. R.; Hanke, P.; Hauser, R.; Heim, S.; Hellman, S.; Hickling, R. S.; Hidvégi, A.; Hillier, S. J.; Hofmann, J. I.; Hristova, I.; Ji, W.; Johansen, M.; Keller, M.; Khomich, A.; Kluge, E.-E.; Koll, J.; Laier, H.; Landon, M. P. J.; Lang, V. S.; Laurens, P.; Lepold, F.; Lilley, J. N.; Linnemann, J. T.; Müller, F.; Müller, T.; Mahboubi, K.; Martin, T. A.; Mass, A.; Meier, K.; Meyer, C.; Middleton, R. P.; Moa, T.; Moritz, S.; Morris, J. D.; Mudd, R. D.; Narayan, R.; zur Nedden, M.; Neusiedl, A.; Newman, P. R.; Nikiforov, A.; Ohm, C. C.; Perera, V. J. O.; Pfeiffer, U.; Plucinski, P.; Poddar, S.; Prieur, D. P. F.; Qian, W.; Rieck, P.; Rizvi, E.; Sankey, D. P. C.; Schäfer, U.; Scharf, V.; Schmitt, K.; Schröder, C.; Schultz-Coulon, H.-C.; Schumacher, C.; Schwienhorst, R.; Silverstein, S. B.; Simioni, E.; Snidero, G.; Staley, R. J.; Stamen, R.; Stock, P.; Stockton, M. C.; Tan, C. L. A.; Tapprogge, S.; Thomas, J. P.; Thompson, P. D.; Thomson, M.; True, P.; Watkins, P. M.; Watson, A. T.; Watson, M. F.; Weber, P.; Wessels, M.; Wiglesworth, C.; Williams, S. L.

2012-12-01

The PreProcessor system of the ATLAS Level-1 Calorimeter Trigger (L1Calo) receives about 7200 analogue signals from the electromagnetic and hadronic components of the calorimetric detector system. Lateral division results in cells which are pre-summed to so-called Trigger Towers of size 0.1 × 0.1 along azimuth (phi) and pseudorapidity (η). The received calorimeter signals represent deposits of transverse energy. The system consists of 124 individual PreProcessor modules that digitise the input signals for each LHC collision, and provide energy and timing information to the digital processors of the L1Calo system, which identify physics objects forming much of the basis for the full ATLAS first level trigger decision. This paper describes the architecture of the PreProcessor, its hardware realisation, functionality, and performance.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rey, D.; Ryan, W.; Ross, M.

A method for more efficiently utilizing the frequency bandwidth allocated for data transmission is presented. Current space and range communication systems use modulation and coding schemes that transmit 0.5 to 1.0 bits per second per Hertz of radio frequency bandwidth. The goal in this LDRD project is to increase the bandwidth utilization by employing advanced digital communications techniques. This is done with little or no increase in the transmit power which is usually very limited on airborne systems. Teaming with New Mexico State University, an implementation of trellis coded modulation (TCM), a coding and modulation scheme pioneered by Ungerboeck, wasmore » developed for this application and simulated on a computer. TCM provides a means for reliably transmitting data while simultaneously increasing bandwidth efficiency. The penalty is increased receiver complexity. In particular, the trellis decoder requires high-speed, application-specific digital signal processing (DSP) chips. A system solution based on the QualComm Viterbi decoder and the Graychip DSP receiver chips is presented.« less

DSP Synthesis Algorithm for Generating Florida Scrub Jay Calls

NASA Technical Reports Server (NTRS)

Lane, John; Pittman, Tyler

2017-01-01

A prototype digital signal processing (DSP) algorithm has been developed to approximate Florida scrub jay calls. The Florida scrub jay (Aphelocoma coerulescens), believed to have been in existence for 2 million years, living only in Florida, has a complicated social system that is evident by examining the spectrograms of its calls. Audio data was acquired at the Helen and Allan Cruickshank Sanctuary, Rockledge, Florida during the 2016 mating season using three digital recorders sampling at 44.1 kHz. The synthesis algorithm is a first step at developing a robust identification and call analysis algorithm. Since the Florida scrub jay is severely threatened by loss of habitat, it is important to develop effective methods to monitor their threatened population using autonomous means.

Digital system for structural dynamics simulation

NASA Technical Reports Server (NTRS)

Krauter, A. I.; Lagace, L. J.; Wojnar, M. K.; Glor, C.

1982-01-01

State-of-the-art digital hardware and software for the simulation of complex structural dynamic interactions, such as those which occur in rotating structures (engine systems). System were incorporated in a designed to use an array of processors in which the computation for each physical subelement or functional subsystem would be assigned to a single specific processor in the simulator. These node processors are microprogrammed bit-slice microcomputers which function autonomously and can communicate with each other and a central control minicomputer over parallel digital lines. Inter-processor nearest neighbor communications busses pass the constants which represent physical constraints and boundary conditions. The node processors are connected to the six nearest neighbor node processors to simulate the actual physical interface of real substructures. Computer generated finite element mesh and force models can be developed with the aid of the central control minicomputer. The control computer also oversees the animation of a graphics display system, disk-based mass storage along with the individual processing elements.

Coherent detection in optical fiber systems.

PubMed

Ip, Ezra; Lau, Alan Pak Tao; Barros, Daniel J F; Kahn, Joseph M

2008-01-21

The drive for higher performance in optical fiber systems has renewed interest in coherent detection. We review detection methods, including noncoherent, differentially coherent, and coherent detection, as well as a hybrid method. We compare modulation methods encoding information in various degrees of freedom (DOF). Polarization-multiplexed quadrature-amplitude modulation maximizes spectral efficiency and power efficiency, by utilizing all four available DOF, the two field quadratures in the two polarizations. Dual-polarization homodyne or heterodyne downconversion are linear processes that can fully recover the received signal field in these four DOF. When downconverted signals are sampled at the Nyquist rate, compensation of transmission impairments can be performed using digital signal processing (DSP). Linear impairments, including chromatic dispersion and polarization-mode dispersion, can be compensated quasi-exactly using finite impulse response filters. Some nonlinear impairments, such as intra-channel four-wave mixing and nonlinear phase noise, can be compensated partially. Carrier phase recovery can be performed using feedforward methods, even when phase-locked loops may fail due to delay constraints. DSP-based compensation enables a receiver to adapt to time-varying impairments, and facilitates use of advanced forward-error-correction codes. We discuss both single- and multi-carrier system implementations. For a given modulation format, using coherent detection, they offer fundamentally the same spectral efficiency and power efficiency, but may differ in practice, because of different impairments and implementation details. With anticipated advances in analog-to-digital converters and integrated circuit technology, DSP-based coherent receivers at bit rates up to 100 Gbit/s should become practical within the next few years.

A rigorous analysis of digital pre-emphasis and DAC resolution for interleaved DAC Nyquist-WDM signal generation in high-speed coherent optical transmission systems

NASA Astrophysics Data System (ADS)

Weng, Yi; Wang, Junyi; He, Xuan; Pan, Zhongqi

2018-02-01

The Nyquist spectral shaping techniques facilitate a promising solution to enhance spectral efficiency (SE) and further reduce the cost-per-bit in high-speed wavelength-division multiplexing (WDM) transmission systems. Hypothetically, any Nyquist WDM signals with arbitrary shapes can be generated by the use of the digital signal processing (DSP) based electrical filters (E-filter). Nonetheless, in actual 100G/ 200G coherent systems, the performance as well as DSP complexity are increasingly restricted by cost and power consumption. Henceforward it is indispensable to optimize DSP to accomplish the preferred performance at the least complexity. In this paper, we systematically investigated the minimum requirements and challenges of Nyquist WDM signal generation, particularly for higher-order modulation formats, including 16 quadrature amplitude modulation (QAM) or 64QAM. A variety of interrelated parameters, such as channel spacing and roll-off factor, have been evaluated to optimize the requirements of the digital-to-analog converter (DAC) resolution and transmitter E-filter bandwidth. The impact of spectral pre-emphasis has been predominantly enhanced via the proposed interleaved DAC architecture by at least 4%, and hence reducing the required optical signal to noise ratio (OSNR) at a bit error rate (BER) of 10-3 by over 0.45 dB at a channel spacing of 1.05 symbol rate and an optimized roll-off factor of 0.1. Furthermore, the requirements of sampling rate for different types of super-Gaussian E-filters are discussed for 64QAM Nyquist WDM transmission systems. Finally, the impact of the non-50% duty cycle error between sub-DACs upon the quality of the generated signals for the interleaved DAC structure has been analyzed.

Dual Active Bridge based DC Transformer LabVIEW FPGA Control Code

DOE Office of Scientific and Technical Information (OSTI.GOV)

In the area of power electronics control, Field Programmable Gate Arrays (FPGAs) have the capability to outperform their Digital Signal Processor (DSP) counterparts due to the FPGA’s ability to implement true parallel processing and therefore facilitate higher switching frequencies, higher control bandwidth, and/or enhanced functionality. National Instruments (NI) has developed two platforms, Compact RIO (cRIO) and Single Board RIO (sbRIO), which combine a real-time processor with an FPGA. The FPGA can be programmed with a subset of the well-known LabVIEW graphical programming language. The candidate software implements complete control algorithms in LabVIEW FPGA for a DC Transformer (DCX) based onmore » a dual active bridge (DAB). A DCX is an isolated bi-directional DC-DC converter designed to operate at unity conversion ratio, M, defined by where Vin is the primary-side DC bus voltage, Vout is the secondary-side DC bus voltage, and n is the turns ratio of the embedded high frequency transformer (HFX). The DCX based on a DAB incorporates two H-bridges, a resonant inductor, and an HFX to provide this functionality. The candidate software employs phase-shift modulation of the two H-bridges and a feedback loop to regulate the conversion ratio at unity. The software also includes alarm-handling capabilities as well as debugging and tuning tools. The software fits on the Xilinx Virtex V LX110 FPGA embedded in the NI cRIO-9118 FPGA chassis, and with a 40 MHz base clock, supports a modulation update rate of 40 MHz, and user-settable switching frequencies and synchronized control loop update rates of tens of kHz.« less

Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

DOEpatents

Tomkins, James L [Albuquerque, NM; Camp, William J [Albuquerque, NM

2009-03-17

A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

Image processing for a tactile/vision substitution system using digital CNN.

PubMed

Lin, Chien-Nan; Yu, Sung-Nien; Hu, Jin-Cheng

2006-01-01

In view of the parallel processing and easy implementation properties of CNN, we propose to use digital CNN as the image processor of a tactile/vision substitution system (TVSS). The digital CNN processor is used to execute the wavelet down-sampling filtering and the half-toning operations, aiming to extract important features from the images. A template combination method is used to embed the two image processing functions into a single CNN processor. The digital CNN processor is implemented on an intellectual property (IP) and is implemented on a XILINX VIRTEX II 2000 FPGA board. Experiments are designated to test the capability of the CNN processor in the recognition of characters and human subjects in different environments. The experiments demonstrates impressive results, which proves the proposed digital CNN processor a powerful component in the design of efficient tactile/vision substitution systems for the visually impaired people.

Life sciences flight experiments microcomputer

NASA Technical Reports Server (NTRS)

Bartram, Peter N.

1987-01-01

A promising microcomputer configuration for the Spacelab Life Sciences Lab. Equipment inventory consists of multiple processors. One processor's use is reserved, with additional processors dedicated to real time input and output operations. A simple form of such a configuration, with a processor board for analog to digital conversion and another processor board for digital to analog conversion, was studied. The system used digital parallel data lines between the boards, operating independently of the system bus. Good performance of individual components was demonstrated: the analog to digital converter was at over 10,000 samples per second. The combination of the data transfer between boards with the input or output functions on each board slowed performance, with a maximum throughput of 2800 to 2900 analog samples per second. Any of several techniques, such as use of the system bus for data transfer or the addition of direct memory access hardware to the processor boards, should give significantly improved performance.

Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition

DOEpatents

Chen, Dong; Giampapa, Mark; Heidelberger, Philip; Ohmacht, Martin; Satterfield, David L; Steinmacher-Burow, Burkhard; Sugavanam, Krishnan

2013-05-21

A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.

A scaleable integrated sensing and control system for NDE, monitoring, and control of medium to very large composite smart structures

NASA Astrophysics Data System (ADS)

Jones, Jerry; Rhoades, Valerie; Arner, Radford; Clem, Timothy; Cuneo, Adam

2007-04-01

NDE measurements, monitoring, and control of smart and adaptive composite structures requires that the central knowledge system have an awareness of the entire structure. Achieving this goal necessitates the implementation of an integrated network of significant numbers of sensors. Additionally, in order to temporally coordinate the data from specially distributed sensors, the data must be time relevant. Early adoption precludes development of sensor technology specifically for this application, instead it will depend on the ability to utilize legacy systems. Partially supported by the U.S. Department of Commerce, National Institute of Standards and Technology, Advanced Technology Development Program (NIST-ATP), a scalable integrated system has been developed to implement monitoring of structural integrity and the control of adaptive/intelligent structures. The project, called SHIELD (Structural Health Identification and Electronic Life Determination), was jointly undertaken by: Caterpillar, N.A. Tech., Motorola, and Microstrain. SHIELD is capable of operation with composite structures, metallic structures, or hybrid structures. SHIELD consists of a real-time processing core on a Motorola MPC5200 using a C language based real-time operating system (RTOS). The RTOS kernel was customized to include a virtual backplane which makes the system completely scalable. This architecture provides for multiple processes to be operating simultaneously. They may be embedded as multiple threads on the core hardware or as separate independent processors connected to the core using a software driver called a NAT-Network Integrator (NATNI). NATNI's can be created for any communications application. In it's current embodiment, NATNI's have been created for CAN bus, TCP/IP (Ethernet) - both wired and 802.11 b and g, and serial communications using RS485 and RS232. Since SHIELD uses standard C language, it is easy to port any monitoring or control algorithm, thus providing for legacy technology which may use other hardware processors and various communications means. For example, two demonstrations of SHIELD have been completed, in January and May 2005 respectively. One demonstration used algorithms in C running in multiple threads in the SHIELD core and utilizing two different sensor networks, one CAN bus and one wireless. The second had algorithms operating in C on the SHIELD core and other algorithms running on multiple Texas Instruments DSP processors using a NATNI that communicated via wired TCP/IP. A key feature of SHIELD is the implementation of a wireless ZIGBEE (802.15.4) network for implementing large numbers of small, low cost, low power sensors communication via a meshstar wireless network. While SHIELD was designed to integrate with a wide variety of existing communications protocols, a ZIGBEE network capability was implemented specifically for SHIELD. This will facilitate the monitoring of medium to very large structures including marine applications, utility scale multi-megawatt wind energy systems, and aircraft/spacecraft. The SHIELD wireless network will facilitate large numbers of sensors (up to 32000), accommodate sensors embedded into the composite material, can communicate to both sensors and actuators, and prevents obsolescence by providing for re-programming of the nodes via remote RF communications. The wireless network provides for ultra-low energy use, spatial location, and accurate timestamping, utilizing the beaconing feature of ZIGBEE.

Parallel machine architecture for production rule systems

DOEpatents

Allen, Jr., John D.; Butler, Philip L.

1989-01-01

A parallel processing system for production rule programs utilizes a host processor for storing production rule right hand sides (RHS) and a plurality of rule processors for storing left hand sides (LHS). The rule processors operate in parallel in the recognize phase of the system recognize -Act Cycle to match their respective LHS's against a stored list of working memory elements (WME) in order to find a self consistent set of WME's. The list of WME is dynamically varied during the Act phase of the system in which the host executes or fires rule RHS's for those rules for which a self-consistent set has been found by the rule processors. The host transmits instructions for creating or deleting working memory elements as dictated by the rule firings until the rule processors are unable to find any further self-consistent working memory element sets at which time the production rule system is halted.

Safe and Efficient Support for Embeded Multi-Processors in ADA

NASA Astrophysics Data System (ADS)

Ruiz, Jose F.

2010-08-01

New software demands increasing processing power, and multi-processor platforms are spreading as the answer to achieve the required performance. Embedded real-time systems are also subject to this trend, but in the case of real-time mission-critical systems, the properties of reliability, predictability and analyzability are also paramount. The Ada 2005 language defined a subset of its tasking model, the Ravenscar profile, that provides the basis for the implementation of deterministic and time analyzable applications on top of a streamlined run-time system. This Ravenscar tasking profile, originally designed for single processors, has proven remarkably useful for modelling verifiable real-time single-processor systems. This paper proposes a simple extension to the Ravenscar profile to support multi-processor systems using a fully partitioned approach. The implementation of this scheme is simple, and it can be used to develop applications amenable to schedulability analysis.

An enhanced Ada run-time system for real-time embedded processors

NASA Technical Reports Server (NTRS)

Sims, J. T.

1991-01-01

An enhanced Ada run-time system has been developed to support real-time embedded processor applications. The primary focus of this development effort has been on the tasking system and the memory management facilities of the run-time system. The tasking system has been extended to support efficient and precise periodic task execution as required for control applications. Event-driven task execution providing a means of task-asynchronous control and communication among Ada tasks is supported in this system. Inter-task control is even provided among tasks distributed on separate physical processors. The memory management system has been enhanced to provide object allocation and protected access support for memory shared between disjoint processors, each of which is executing a distinct Ada program.

System support software for the Space Ultrareliable Modular Computer (SUMC)

NASA Technical Reports Server (NTRS)

Hill, T. E.; Hintze, G. C.; Hodges, B. C.; Austin, F. A.; Buckles, B. P.; Curran, R. T.; Lackey, J. D.; Payne, R. E.

1974-01-01

The highly transportable programming system designed and implemented to support the development of software for the Space Ultrareliable Modular Computer (SUMC) is described. The SUMC system support software consists of program modules called processors. The initial set of processors consists of the supervisor, the general purpose assembler for SUMC instruction and microcode input, linkage editors, an instruction level simulator, a microcode grid print processor, and user oriented utility programs. A FORTRAN 4 compiler is undergoing development. The design facilitates the addition of new processors with a minimum effort and provides the user quasi host independence on the ground based operational software development computer. Additional capability is provided to accommodate variations in the SUMC architecture without consequent major modifications in the initial processors.

The implementation and use of Ada on distributed systems with reliability requirements

NASA Technical Reports Server (NTRS)

Reynolds, P. F.; Knight, J. C.; Urquhart, J. I. A.

1983-01-01

The issues involved in the use of the programming language Ada on distributed systems are discussed. The effects of Ada programs on hardware failures such as loss of a processor are emphasized. It is shown that many Ada language elements are not well suited to this environment. Processor failure can easily lead to difficulties on those processors which remain. As an example, the calling task in a rendezvous may be suspended forever if the processor executing the serving task fails. A mechanism for detecting failure is proposed and changes to the Ada run time support system are suggested which avoid most of the difficulties. Ada program structures are defined which allow programs to reconfigure and continue to provide service following processor failure.

Vibration Pattern Imager (VPI): A control and data acquisition system for scanning laser vibrometers

NASA Technical Reports Server (NTRS)

Rizzi, Stephen A.; Brown, Donald E.; Shaffer, Thomas A.

1993-01-01

The Vibration Pattern Imager (VPI) system was designed to control and acquire data from scanning laser vibrometer sensors. The PC computer based system uses a digital signal processing (DSP) board and an analog I/O board to control the sensor and to process the data. The VPI system was originally developed for use with the Ometron VPI Sensor, but can be readily adapted to any commercially available sensor which provides an analog output signal and requires analog inputs for control of mirror positioning. The sensor itself is not part of the VPI system. A graphical interface program, which runs on a PC under the MS-DOS operating system, functions in an interactive mode and communicates with the DSP and I/O boards in a user-friendly fashion through the aid of pop-up menus. Two types of data may be acquired with the VPI system: single point or 'full field.' In the single point mode, time series data is sampled by the A/D converter on the I/O board (at a user-defined sampling rate for a selectable number of samples) and is stored by the PC. The position of the measuring point (adjusted by mirrors in the sensor) is controlled via a mouse input. The mouse input is translated to output voltages by the D/A converter on the I/O board to control the mirror servos. In the 'full field' mode, the measurement point is moved over a user-selectable rectangular area. The time series data is sampled by the A/D converter on the I/O board (at a user-defined sampling rate for a selectable number of samples) and converted to a root-mean-square (rms) value by the DSP board. The rms 'full field' velocity distribution is then uploaded for display and storage on the PC.

Dentine sialoprotein expression in gingival crevicular fluid during trauma-induced root resorption.

PubMed

Kumar, V; Logani, A; Shah, N

2013-04-01

To detect and quantify dentine sialoprotein (DSP) in the gingival crevicular fluid (GCF) of luxated teeth. Eighteen subjects were enroled and distributed as follows. Group I (n = 6, positive control): subjects with primary second molar teeth undergoing physiological root resorption. Group II (n = 6, negative control): subjects with permanent mature maxillary central incisors. Subjects with a recent history (<1 week) of luxation injury were included in group III (n = 6, test group) and standardized digital radiographs with a superimposed mesh gauge were exposed at various time intervals. Percentage of radiographic root resorption (%RRR) was calculated. GCF was collected using microcapillary pipettes. DSP in the GCF was quantified using enzyme-linked immunosorbant assay. Group III was subjected to Spearman's rank test to establish the correlation between the concentration of DSP and %RRR at 6 weeks, 3 and 6 months. Quantifiable amounts of DSP were released in the GCF of subjects in Group I and III. However, the protein was not detected in Group II. Detectable quantities of DSP were observed in the GCF of luxated teeth before any radiographic evidence of root resorption (base line radiograph). A positive correlation was established at 6 weeks (r = 0.795), 3 (r = 0.755) and 6 month (r = 0.837) between the release of DSP and %RRR (P < 0.05). Dentine sialoprotein was released in the GCF of luxated teeth and its concentration correlated with the active and remission phases of this pathological process. Further investigation is required to establish a potentially noninvasive aid for diagnosing and monitoring root resorption. © 2012 International Endodontic Journal.

Academic performance in adolescents with delayed sleep phase.

PubMed

Sivertsen, Børge; Glozier, Nick; Harvey, Allison G; Hysing, Mari

2015-09-01

Delayed sleep phase (DSP) in adolescence has been linked to reduced academic performance, but there are few population-based studies examining this association using validated sleep measures and objective outcomes. The youth@hordaland-survey, a large population-based study from Norway conducted in 2012, surveyed 8347 high-school students aged 16-19 years (54% girls). DSP was assessed by self-report sleep measures, and it was operationalized according to the International Classification of Sleep Disorders - Second Edition. School performance (grade point average, GPA) was obtained from official administrative registries, and it was linked individually to health data. DSP was associated with increased odds for poor school performance. After adjusting for age and gender, DSP was associated with a threefold increased odds of poor GPA (lowest quartile) [odds ratio (OR) = 2.95; 95% confidence interval (CI): 2.03-4.30], and adjustment for sociodemographics and lifestyle factors did not, or only slightly, attenuate this association. Adjustment for nonattendance at school reduced the association substantially, and in the fully adjusted model, the effect of DSP on poor academic performance was reduced to a non-significant level. Mediation analyses confirmed both direct and significant indirect effects of DSP on school performance based on school absence, daytime sleepiness, and sleep duration. Poor academic performance may reflect an independent effect of underlying circadian disruption, which in part could be mediated by school attendance, as well as daytime sleepiness and short sleep duration. This suggests that careful assessment of sleep is warranted in addressing educational difficulties. Copyright © 2015 Elsevier B.V. All rights reserved.

Evidence Base Update for Autism Spectrum Disorder.

PubMed

Smith, Tristram; Iadarola, Suzannah

2015-01-01

This evidence base update examines the level of empirical support for interventions for children with autism spectrum disorder (ASD) younger than 5 years old. It focuses on research published since a previous review in this journal (Rogers & Vismara, 2008 ). We identified psychological or behavioral interventions that had been manualized and evaluated in either (a) experimental or quasi-experimental group studies or (b) systematic reviews of single-subject studies. We extracted data from all studies that met these criteria and were published after the previous review. Interventions were categorized across two dimensions. First, primary theoretical principles included applied behavior analysis (ABA), developmental social-pragmatic (DSP), or both. Second, practice elements included scope (comprehensive or focused), modality (individual intervention with the child, parent training, or classrooms), and intervention targets (e.g., spoken language or alternative and augmentative communication). We classified two interventions as well-established (individual, comprehensive ABA and teacher-implemented, focused ABA + DSP), 3 as probably efficacious (individual, focused ABA for augmentative and alternative communication; individual, focused ABA + DSP; and focused DSP parent training), and 5 as possibly efficacious (individual, comprehensive ABA + DSP; comprehensive ABA classrooms; focused ABA for spoken communication; focused ABA parent training; and teacher-implemented, focused DSP). The evidence base for ASD interventions has grown substantially since 2008. An increasing number of interventions have some empirical support; others are emerging as potentially efficacious. Priorities for future research include improving outcome measures, developing interventions for understudied ASD symptoms (e.g., repetitive behaviors), pinpointing mechanisms of action in interventions, and adapting interventions for implementation with fidelity by community providers.

A cross-sectional observation of the factors associated with deliberate self-poisoning with acetaminophen: impact of gender differences and psychiatric intervention.

PubMed

Zyoud, Sa'ed H; Awang, Rahmat; Sulaiman, Syed Azhar Syed; Al-Jabi, Samah W

2010-08-01

The objectives of this study were to determine the risk factors and life stressors that are prevalent among the acetaminophen deliberate self-poisoning (DSP) cases, to identify gender differences in the associated factors, and to determine the prevalence of psychiatric diagnosis and the patterns and types of psychotherapeutic interventions provided by psychiatrists. This is a cross-sectional study, a retrospective descriptive case review of hospital admissions for acetaminophen DSP. There were 177 incidences of DSP during the study period. The mean age of the cases was 23.1 +/- 7.3 years and 84.1% of them were females. The risk factors were more significantly associated with males: chronic ethanol intake (p = 0.04), higher reported dose ingested (p = 0.01), higher latency time (p = 0.04) and longer hospital stay (p = 0.03). The most commonly reported psychotherapeutic interventions used by psychiatrists were psychoeducation of the patient, followed by referral to a psychiatric clinic, family psychoeducation and psychotropic medication. Sertraline (SSRI) was the most frequently prescribed antidepressant. Males have been shown to use more toxic doses and to delay treatment due to high latency time. Most DSP patients have different life stressors and psychiatric diagnoses that may be associated with varying degrees of suicidal intent. All patients presenting following DSP need to be carefully screened for psychiatric illness. Randomized controlled studies need to be conducted on DSP patients with psychiatric illness to determine which treatments are effective. Copyright 2010 John Wiley & Sons, Ltd.

Conditions for space invariance in optical data processors used with coherent or noncoherent light.

PubMed

Arsenault, H R

1972-10-01

The conditions for space invariance in coherent and noncoherent optical processors are considered. All linear optical processors are shown to belong to one of two types. The conditions for space invariance are more stringent for noncoherent processors than for coherent processors, so that a system that is linear in coherent light may be nonlinear in noncoherent light. However, any processor that is linear in noncoherent light is also linear in the coherent limit.

Variable word length encoder reduces TV bandwith requirements

NASA Technical Reports Server (NTRS)

Sivertson, W. E., Jr.

1965-01-01

Adaptive variable resolution encoding technique provides an adaptive compression pseudo-random noise signal processor for reducing television bandwidth requirements. Complementary processors are required in both the transmitting and receiving systems. The pretransmission processor is analog-to-digital, while the postreception processor is digital-to-analog.

Designer Self-Assemble Peptides Maximize the Therapeutic Benefits of Neural Stem Cell Transplantation for Alzheimer's Disease via Enhancing Neuron Differentiation and Paracrine Action.

PubMed

Cui, Guo-hong; Shao, Shui-jin; Yang, Jia-jun; Liu, Jian-ren; Guo, Hai-dong

2016-03-01

The neuropathological hallmarks of Alzheimer's disease (AD) include the presence of extracellular amyloid-β peptide (Aβ) in the form of amyloid plaques and neuronal loss. Neural stem cell (NSC) is being scrutinized as a promising cell replacement therapy for various neurodegenerative diseases. However, the unfavorable niche at the site of degenerative disease is hostile to the survival and differentiation of transplanted cells. Here, we undertook in vitro and in vivo works to examine whether a designer self-assemble peptide (DSP), which contains one functional domain Tyr-Ile-Gly-Ser-Arg (YIGSR) derived from laminin, promotes the survival and neuronal differentiation of NSC and behavioral improvement. We found that DSP could undergo spontaneous assembly into well-ordered nanofibers, and it not only facilitated the cell viability in normal culture condition, but also decreased the number of apoptotic cells induced by Aβ in vitro. NSC seeded in DSP showed much more neuronal differentiation than that seeded in self-assemble peptide (SP) or alone. In the AD model, NSC transplantation in DSP-treated AD rats demonstrated much more obvious cognitive rescue with restoration of learning/memory function compared with NSC transplantation in SP, NSC alone, or DSP alone treated ones. Interestingly, DSP enhanced the survival and neuronal differentiation of transplanted NSC. Apoptosis levels in the CA1 region and Aβ level in the hippocampus were significantly decreased in the group of NSC transplantation in DSP. Moreover, synaptic function, indicated by the expression of pre-synaptic protein synapsin-1, was restored and the secretion of anti-inflammatory and neurotrophic factors were increased, such as IL-10, brain-derived neurotrophic factor (BDNF), ciliary neurotrophic factor (CNTF), and insulin-like growth factor 1 (IGF-1), while the expression of pro-inflammatory factors were decreased, such as TNF-α and IL-1β. These data firstly unveiled that the biomaterial DSP can maximize the therapeutic benefits of NSC transplantation for AD through improving the survival and differentiation of transplanted stem cells and promoting the effects of neuroprotection, anti-neuroinflammatory and paracrine action. Our results may have important clinical implications for the design of future NSC-based strategies using the biomaterials for various neurodegenerative diseases including AD.

Estimation of the rate and number of underreported deliberate self-poisoning attempts in western Iran in 2015

PubMed Central

2017-01-01

OBJECTIVES Rates of attempted deliberate self-poisoning (DSP) are subject to undercounting, underreporting, and denial of the suicide attempt. In this study, we estimated the rate of underreported DSP, which is the most common method of attempted suicide in Iran. METHODS We estimated the rate and number of unaccounted individuals who attempted DSP in western Iran in 2015 using a truncated count model. In this method, the number of people who attempted DSP but were not referred to any health care centers, n0, was calculated through integrating hospital and forensic data. The crude and age-adjusted rates of attempted DSP were estimated directly using the average population size of the city of Kermanshah and the World Health Organization (WHO) world standard population with and without accounting for underreporting. The Monte Carlo method was used to determine the confidence level. RESULTS The recorded number of people who attempted DSP was estimated by different methods to be in the range of 46.6 to 53.2% of the actual number of individuals who attempted DSP. The rate of underreported cases was higher among women than men and decreased as age increased. The rate of underreported cases decreased as the potency and intensity of toxic factors increased. The highest underreporting rates of 69.9, 51.2, and 21.5% were observed when oil and detergents (International Classification of Diseases, 10th revision [ICD-10] code: X66), medications (ICD-10 code: X60-X64), and agricultural toxins (ICD-10 codes: X68, X69) were used for poisoning, respectively. Crude rates, with and without accounting for underreporting, were estimated by the mixture method as 167.5 per 100,000 persons and 331.7 per 100,000 persons, respectively, which decreased to 129.8 per 100,000 persons and 253.1 per 100,000 persons after adjusting for age on the basis of the WHO world standard population. CONCLUSIONS Nearly half of individuals who attempted DSP were not referred to a hospital for treatment or denied the suicide attempt for political or sociocultural reasons. Individuals with no access to counseling services are at a higher risk for repeated suicide attempts and fatal suicides. PMID:28728353

FPGA-based multiprocessor system for injection molding control.

PubMed

Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P; Osornio-Rios, Roque A

2012-10-18

The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected.

Methodology for creating dedicated machine and algorithm on sunflower counting

NASA Astrophysics Data System (ADS)

Muracciole, Vincent; Plainchault, Patrick; Mannino, Maria-Rosaria; Bertrand, Dominique; Vigouroux, Bertrand

2007-09-01

In order to sell grain lots in European countries, seed industries need a government certification. This certification requests purity testing, seed counting in order to quantify specified seed species and other impurities in lots, and germination testing. These analyses are carried out within the framework of international trade according to the methods of the International Seed Testing Association. Presently these different analyses are still achieved manually by skilled operators. Previous works have already shown that seeds can be characterized by around 110 visual features (morphology, colour, texture), and thus have presented several identification algorithms. Until now, most of the works in this domain are computer based. The approach presented in this article is based on the design of dedicated electronic vision machine aimed to identify and sort seeds. This machine is composed of a FPGA (Field Programmable Gate Array), a DSP (Digital Signal Processor) and a PC bearing the GUI (Human Machine Interface) of the system. Its operation relies on the stroboscopic image acquisition of a seed falling in front of a camera. A first machine was designed according to this approach, in order to simulate all the vision chain (image acquisition, feature extraction, identification) under the Matlab environment. In order to perform this task into dedicated hardware, all these algorithms were developed without the use of the Matlab toolbox. The objective of this article is to present a design methodology for a special purpose identification algorithm based on distance between groups into dedicated hardware machine for seed counting.

A pipeline VLSI design of fast singular value decomposition processor for real-time EEG system based on on-line recursive independent component analysis.

PubMed

Huang, Kuan-Ju; Shih, Wei-Yeh; Chang, Jui Chung; Feng, Chih Wei; Fang, Wai-Chi

2013-01-01

This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor aims to solve the diagonal, inverse and inverse square root matrices of the target matrices in real time. Generally, SVD requires a huge amount of computation in hardware implementation. Therefore, this work proposes a novel design concept for data flow updating to assist the pipeline VLSI implementation. The SVD processor can greatly improve the feasibility of real-time EEG system applications such as brain computer interfaces (BCIs). The proposed architecture is implemented using TSMC 90 nm CMOS technology. The sample rate of EEG raw data adopts 128 Hz. The core size of the SVD processor is 580×580 um(2), and the speed of operation frequency is 20MHz. It consumes 0.774mW of power during the 8-channel EEG system per execution time.

Digital signal processing techniques for coherent optical communication

NASA Astrophysics Data System (ADS)

Goldfarb, Gilad

Coherent detection with subsequent digital signal processing (DSP) is developed, analyzed theoretically and numerically and experimentally demonstrated in various fiber-optic transmission scenarios. The use of DSP in conjunction with coherent detection unleashes the benefits of coherent detection which rely on the preservaton of full information of the incoming field. These benefits include high receiver sensitivity, the ability to achieve high spectral-efficiency and the use of advanced modulation formats. With the immense advancements in DSP speeds, many of the problems hindering the use of coherent detection in optical transmission systems have been eliminated. Most notably, DSP alleviates the need for hardware phase-locking and polarization tracking, which can now be achieved in the digital domain. The complexity previously associated with coherent detection is hence significantly diminished and coherent detection is once gain considered a feasible detection alternative. In this thesis, several aspects of coherent detection (with or without subsequent DSP) are addressed. Coherent detection is presented as a means to extend the dispersion limit of a duobinary signal using an analog decision-directed phase-lock loop. Analytical bit-error ratio estimation for quadrature phase-shift keying signals is derived. To validate the promise for high spectral efficiency, the orthogonal-wavelength-division multiplexing scheme is suggested. In this scheme the WDM channels are spaced at the symbol rate, thus achieving the spectral efficiency limit. Theory, simulation and experimental results demonstrate the feasibility of this approach. Infinite impulse response filtering is shown to be an efficient alternative to finite impulse response filtering for chromatic dispersion compensation. Theory, design considerations, simulation and experimental results relating to this topic are presented. Interaction between fiber dispersion and nonlinearity remains the last major challenge deterministic effects pose for long-haul optical data transmission. Experimental results which demonstrate the possibility to digitally mitigate both dispersion and nonlinearity are presented. Impairment compensation is achieved using backward propagation by implementing the split-step method. Efficient realizations of the dispersion compensation operator used in this implementation are considered. Infinite-impulse response and wavelet-based filtering are both investigated as a means to reduce the required computational load associated with signal backward-propagation. Possible future research directions conclude this dissertation.

The STAFF-DWP wave instrument on the DSP equatorial spacecraft: description and first results

NASA Astrophysics Data System (ADS)

Cornilleau-Wehrlin, N.; Alleyne, H. St. C.; Yearby, K. H.; de La Porte de Vaux, B.; Meyer, A.; Santolík, O.; Parrot, M.; Belmont, G.; Rezeau, L.; Le Contel, O.; Roux, A.; Attié, D.; Robert, P.; Bouzid, V.; Herment, D.; Cao, J.

2005-11-01

The STAFF-DWP wave instrument on board the equatorial spacecraft (TC1) of the Double Star Project consists of a combination of 2 instruments which are a heritage of the Cluster mission: the Spatio-Temporal Analysis of Field Fluctuations (STAFF) experiment and the Digital Wave-Processing experiment (DWP). On DSP-TC1 STAFF consists of a three-axis search coil magnetometer, used to measure magnetic fluctuations at frequencies up to 4 kHz and a waveform unit, up to 10 Hz, plus snapshots up to 180 Hz. DWP provides several onboard analysis tools: a complex FFT to fully characterise electromagnetic waves in the frequency range 10 Hz-4 kHz, a particle correlator linked to the PEACE electron experiment, and compression of the STAFF waveform data. The complementary Cluster and TC1 orbits, together with the similarity of the instruments, permits new multi-point studies. The first results show the capabilities of the experiment, with examples in the different regions of the magnetosphere-solar wind system that have been encountered by DSP-TC1 at the beginning of its operational phase. An overview of the different kinds of electromagnetic waves observed on the dayside from perigee to apogee is given, including the different whistler mode waves (hiss, chorus, lion roars) and broad-band ULF emissions. The polarisation and propagation characteristics of intense waves in the vicinity of a bow shock crossing are analysed using the dedicated PRASSADCO tool, giving results compatible with previous studies: the broad-band ULF waves consist of a superimposition of different wave modes, whereas the magnetosheath lion roars are right-handed and propagate close to the magnetic field. An example of a combined Cluster DSP-TC1 magnetopause crossing is given. This first case study shows that the ULF wave power intensity is higher at low latitude (DSP) than at high latitude (Cluster). On the nightside in the tail, a first wave event comparison - in a rather quiet time interval - is shown. It opens the doors to future studies, such as event timing during substorms, to possibly determine their onset location.

Parallel processing architecture for H.264 deblocking filter on multi-core platforms

NASA Astrophysics Data System (ADS)

Prasad, Durga P.; Sonachalam, Sekar; Kunchamwar, Mangesh K.; Gunupudi, Nageswara Rao

2012-03-01

Massively parallel computing (multi-core) chips offer outstanding new solutions that satisfy the increasing demand for high resolution and high quality video compression technologies such as H.264. Such solutions not only provide exceptional quality but also efficiency, low power, and low latency, previously unattainable in software based designs. While custom hardware and Application Specific Integrated Circuit (ASIC) technologies may achieve lowlatency, low power, and real-time performance in some consumer devices, many applications require a flexible and scalable software-defined solution. The deblocking filter in H.264 encoder/decoder poses difficult implementation challenges because of heavy data dependencies and the conditional nature of the computations. Deblocking filter implementations tend to be fixed and difficult to reconfigure for different needs. The ability to scale up for higher quality requirements such as 10-bit pixel depth or a 4:2:2 chroma format often reduces the throughput of a parallel architecture designed for lower feature set. A scalable architecture for deblocking filtering, created with a massively parallel processor based solution, means that the same encoder or decoder will be deployed in a variety of applications, at different video resolutions, for different power requirements, and at higher bit-depths and better color sub sampling patterns like YUV, 4:2:2, or 4:4:4 formats. Low power, software-defined encoders/decoders may be implemented using a massively parallel processor array, like that found in HyperX technology, with 100 or more cores and distributed memory. The large number of processor elements allows the silicon device to operate more efficiently than conventional DSP or CPU technology. This software programing model for massively parallel processors offers a flexible implementation and a power efficiency close to that of ASIC solutions. This work describes a scalable parallel architecture for an H.264 compliant deblocking filter for multi core platforms such as HyperX technology. Parallel techniques such as parallel processing of independent macroblocks, sub blocks, and pixel row level are examined in this work. The deblocking architecture consists of a basic cell called deblocking filter unit (DFU) and dependent data buffer manager (DFM). The DFU can be used in several instances, catering to different performance needs the DFM serves the data required for the different number of DFUs, and also manages all the neighboring data required for future data processing of DFUs. This approach achieves the scalability, flexibility, and performance excellence required in deblocking filters.

Effects of input processing and type of personal frequency modulation system on speech-recognition performance of adults with cochlear implants.

PubMed

Wolfe, Jace; Schafer, Erin; Parkinson, Aaron; John, Andrew; Hudson, Mary; Wheeler, Julie; Mucci, Angie

2013-01-01

The objective of this study was to compare speech recognition in quiet and in noise for cochlear implant recipients using two different types of personal frequency modulation (FM) systems (directly coupled [direct auditory input] versus induction neckloop) with each of two sound processors (Cochlear Nucleus Freedom versus Cochlear Nucleus 5). Two different experiments were conducted within this study. In both these experiments, mixing of the FM signal within the Freedom processor was implemented via the same scheme used clinically for the Freedom sound processor. In Experiment 1, the aforementioned comparisons were conducted with the Nucleus 5 programmed so that the microphone and FM signals were mixed and then the mixed signals were subjected to autosensitivity control (ASC). In Experiment 2, comparisons between the two FM systems and processors were conducted again with the Nucleus 5 programmed to provide a more complex multistage implementation of ASC during the preprocessing stage. This study was a within-subject, repeated-measures design. Subjects were recruited from the patient population at the Hearts for Hearing Foundation in Oklahoma City, OK. Fifteen subjects participated in Experiment 1, and 16 subjects participated in Experiment 2. Subjects were adults who had used either unilateral or bilateral cochlear implants for at least 1 year. In this experiment, no differences were found in speech recognition in quiet obtained with the two different FM systems or the various sound-processor conditions. With each sound processor, speech recognition in noise was better with the directly coupled direct auditory input system relative to the neckloop system. The multistage ASC processing of the Nucleus 5 sound processor provided better performance than the single-stage approach for the Nucleus 5 and the Nucleus Freedom sound processor. Speech recognition in noise is substantially affected by the type of sound processor, FM system, and implementation of ASC used by a Cochlear implant recipient.

32 CFR 319.5 - Procedures for requests pertaining to individual records in a record system.

Code of Federal Regulations, 2012 CFR

2012-07-01

... OF THE SECRETARY OF DEFENSE (CONTINUED) PRIVACY PROGRAM DEFENSE INTELLIGENCE AGENCY PRIVACY PROGRAM... seeking notification of whether a system of records, maintained by the Defense Intelligence Agency... request to the Defense Intelligence Agency, DSP-1A, Washington, DC 20340-3299 and indicate clearly on the...

32 CFR 319.5 - Procedures for requests pertaining to individual records in a record system.

Code of Federal Regulations, 2010 CFR

2010-07-01

... OF THE SECRETARY OF DEFENSE (CONTINUED) PRIVACY PROGRAM DEFENSE INTELLIGENCE AGENCY PRIVACY PROGRAM... seeking notification of whether a system of records, maintained by the Defense Intelligence Agency... request to the Defense Intelligence Agency, DSP-1A, Washington, DC 20340-3299 and indicate clearly on the...

32 CFR 319.5 - Procedures for requests pertaining to individual records in a record system.

Code of Federal Regulations, 2014 CFR

2014-07-01

... OF THE SECRETARY OF DEFENSE (CONTINUED) PRIVACY PROGRAM DEFENSE INTELLIGENCE AGENCY PRIVACY PROGRAM... seeking notification of whether a system of records, maintained by the Defense Intelligence Agency... request to the Defense Intelligence Agency, DSP-1A, Washington, DC 20340-3299 and indicate clearly on the...

Fiber Optics Deliver Real-Time Structural Monitoring

NASA Technical Reports Server (NTRS)

2013-01-01

To alter the shape of aircraft wings during flight, researchers at Dryden Flight Research Center worked on a fiber optic sensor system with Austin-based 4DSP LLC. The company has since commercialized a new fiber optic system for monitoring applications in health and medicine, oil and gas, and transportation, increasing company revenues by 60 percent.

Simulation of a master-slave event set processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Comfort, J.C.

1984-03-01

Event set manipulation may consume a considerable amount of the computation time spent in performing a discrete-event simulation. One way of minimizing this time is to allow event set processing to proceed in parallel with the remainder of the simulation computation. The paper describes a multiprocessor simulation computer, in which all non-event set processing is performed by the principal processor (called the host). Event set processing is coordinated by a front end processor (the master) and actually performed by several other functionally identical processors (the slaves). A trace-driven simulation program modeling this system was constructed, and was run with tracemore » output taken from two different simulation programs. Output from this simulation suggests that a significant reduction in run time may be realized by this approach. Sensitivity analysis was performed on the significant parameters to the system (number of slave processors, relative processor speeds, and interprocessor communication times). A comparison between actual and simulation run times for a one-processor system was used to assist in the validation of the simulation. 7 references.« less

Implementation of medical monitor system based on networks

NASA Astrophysics Data System (ADS)

Yu, Hui; Cao, Yuzhen; Zhang, Lixin; Ding, Mingshi

2006-11-01

In this paper, the development trend of medical monitor system is analyzed and portable trend and network function become more and more popular among all kinds of medical monitor devices. The architecture of medical network monitor system solution is provided and design and implementation details of medical monitor terminal, monitor center software, distributed medical database and two kind of medical information terminal are especially discussed. Rabbit3000 system is used in medical monitor terminal to implement security administration of data transfer on network, human-machine interface, power management and DSP interface while DSP chip TMS5402 is used in signal analysis and data compression. Distributed medical database is designed for hospital center according to DICOM information model and HL7 standard. Pocket medical information terminal based on ARM9 embedded platform is also developed to interactive with center database on networks. Two kernels based on WINCE are customized and corresponding terminal software are developed for nurse's routine care and doctor's auxiliary diagnosis. Now invention patent of the monitor terminal is approved and manufacture and clinic test plans are scheduled. Applications for invention patent are also arranged for two medical information terminals.

Passive coherent location system simulation and evaluation

NASA Astrophysics Data System (ADS)

Slezák, Libor; Kvasnička, Michael; Pelant, Martin; Vávra, Jiř; Plšek, Radek

2006-02-01

Passive Coherent Location (PCL) is going to be important and perspective system of passive location of non cooperative and stealth targets. It works with the sources of irradiation of opportunity. PCL is intended to be a part of mobile Air Command and Control System (ACCS) as a Deployable ACCS Component (DAC). The company ERA works on PCL system parameters verification program by complete PCL simulator development since the year 2003. The Czech DoD takes financial participation on this program. The moving targets scenario, the RCS calculation by method of moment, ground clutter scattering and signal processing method (the bottle neck of the PCL) are available up to now in simulator tool. The digital signal (DSP) processing algorithms are performed both on simulated data and on real data measured at NATO C3 Agency in their Haag experiment. The Institute of Information Theory and Automation of the Academy of Sciences of the Czech Republic takes part on the implementation of the DSP algorithms in FPGA. The paper describes the simulator and signal processing structure and results both on simulated and measured data.

State recovery and lockstep execution restart in a system with multiprocessor pairing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gara, Alan; Gschwind, Michael K; Salapura, Valentina

System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switchmore » or a bus. Each selectively paired processor core is includes a transactional execution facility, whereing the system is configured to enable processor rollback to a previous state and reinitialize lockstep execution in order to recover from an incorrect execution when an incorrect execution has been detected by the selective pairing facility.« less

System-wide power management control via clock distribution network

DOEpatents

Coteus, Paul W.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Reed, Don D.

2015-05-19

An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.

Development of the pulmonary surfactant system in two oviparous vertebrates.

PubMed

Johnston, S D; Orgeig, S; Lopatko, O V; Daniels, C B

2000-02-01

In birds and oviparous reptiles, hatching is often a lengthy and exhausting process, which commences with pipping followed by lung clearance and pulmonary ventilation. We examined the composition of pulmonary surfactant in the developing lungs of the chicken, Gallus gallus, and of the bearded dragon, Pogona vitticeps. Lung tissue was collected from chicken embryos at days 14, 16, 18 (prepipped), and 20 (postpipped) of incubation and from 1 day and 3 wk posthatch and adult animals. In chickens, surfactant protein A mRNA was detected using Northern blot analysis in lung tissue at all stages sampled, appearing relatively earlier in development compared with placental mammals. Chickens were lavaged at days 16, 18, and 20 of incubation and 1 day posthatch, whereas bearded dragons were lavaged at day 55, days 57-60 (postpipped), and days 58-61 (posthatched). In both species, total phospholipid (PL) from the lavage increased throughout incubation. Disaturated PL (DSP) was not measurable before 16 days of incubation in the chick embryo nor before 55 days in bearded dragons. However, the percentage of DSP/PL increased markedly throughout late development in both species. Because cholesterol (Chol) remained unchanged, the Chol/PL and Chol/DSP ratios decreased in both species. Thus the Chol and PL components are differentially regulated. The lizard surfactant system develops and matures over a relatively shorter time than that of birds and mammals. This probably reflects the highly precocial nature of hatchling reptiles.

HAMS II Quarterly Progress Report (Technical and Financial)

DTIC Science & Technology

2015-01-09

Resistance - Flow Relationships .................................................................................. 10 Figure 3. Pulse Oximeter Front-end...19 Figure 10. Pulse Oximeter versus NIRS...TMS320C5515 DSP Medical Development Kit (MDK) for Pulse Oximeter Implementation. This evaluation system provides the capability to leverage into the

Adolescent Emotional Maturation through Divergent Models of Brain Organization

PubMed Central

Oron Semper, Jose V.; Murillo, Jose I.; Bernacer, Javier

2016-01-01

In this article we introduce the hypothesis that neuropsychological adolescent maturation, and in particular emotional management, may have opposing explanations depending on the interpretation of the assumed brain architecture, that is, whether a componential computational account (CCA) or a dynamic systems perspective (DSP) is used. According to CCA, cognitive functions are associated with the action of restricted brain regions, and this association is temporally stable; by contrast, DSP argues that cognitive functions are better explained by interactions between several brain areas, whose engagement in specific functions is temporal and context-dependent and based on neural reuse. We outline the main neurobiological facts about adolescent maturation, focusing on the neuroanatomical and neurofunctional processes associated with adolescence. We then explain the importance of emotional management in adolescent maturation. We explain the interplay between emotion and cognition under the scope of CCA and DSP, both at neural and behavioral levels. Finally, we justify why, according to CCA, emotional management is understood as regulation, specifically because the cognitive aspects of the brain are in charge of regulating emotion-related modules. However, the key word in DSP is integration, since neural information from different brain areas is integrated from the beginning of the process. Consequently, although the terms should not be conceptually confused, there is no cognition without emotion, and vice versa. Thus, emotional integration is not an independent process that just happens to the subject, but a crucial part of personal growth. Considering the importance of neuropsychological research in the development of educational and legal policies concerning adolescents, we intend to expose that the holistic view of adolescents is dependent on whether one holds the implicit or explicit interpretation of brain functioning. PMID:27602012

A recessive mutation in the DSP gene linked to cardiomyopathy, skin fragility and hair defects impairs the binding of desmoplakin to epidermal keratins and the muscle-specific intermediate filament desmin.

PubMed

Favre, B; Begré, N; Borradori, L

2018-06-07

Desmoplakin (DSP) is a cytolinker of the plakin family. It mediates the connection of intermediate filaments (IFs) to desmosomes, intercellular adhesion junctions. The carboxyl (C)-terminal tail of DSP binds to IFs, while its amino-terminal part interacts with the armadillo proteins plakophilins and plakoglobin that in turn associate with the desmosomal cadherin desmogleins and desmocollins 1 . This article is protected by copyright. All rights reserved. This article is protected by copyright. All rights reserved.

Cancer Secretome May Influence BSP and DSP Expression in Human Salivary Gland Cells

PubMed Central

Hamilton, Samantha Lynn; Ferando, Blake; Eapen, Asha Sarah; Yu, Jennifer Chian; Joy, Anita Rose

2016-01-01

One of the biggest challenges in managing head and neck cancers, especially salivary gland cancers, is the identification of secreted biomarkers of the disease that can be evaluated noninvasively. A relevant source of enriched tumor markers could potentially be found in the tumor secretome. Although numerous studies have evaluated secretomes from various cancers, the influence of the cancer secretome derived from salivary gland cancers on the behavior of normal cells has not yet been elucidated. Our data indicate that secretome derived from salivary gland cancer cells can influence the expression of two potential biomarkers of oral cancer—namely, bone sialoprotein (BSP) and dentin sialoprotein (DSP)—in normal salivary gland cells. Using routine immunohistochemistry, immunofluorescence, and immunoblotting techniques, we demonstrate an enrichment of BSP and DSP in human salivary gland (HSG) cancer tissue, unique localizations of BSP and DSP in HSG cancer cells, and enriched expression of BSP and DSP in normal salivary gland cells exposed to a cancer secretome. The secretome domain of the cancer microenvironment could alter signaling cascades responsible for normal cell proliferation, migration, and invasion, thus enhancing cancer cell survival and the potential for cancer progression. The cancer secretome may be critical in maintaining and stimulating “cancer-ness,” thus potentially promoting specific hallmarks of metastasis. PMID:27881474

Cancer Secretome May Influence BSP and DSP Expression in Human Salivary Gland Cells.

PubMed

Hamilton, Samantha Lynn; Ferando, Blake; Eapen, Asha Sarah; Yu, Jennifer Chian; Joy, Anita Rose

2017-03-01

One of the biggest challenges in managing head and neck cancers, especially salivary gland cancers, is the identification of secreted biomarkers of the disease that can be evaluated noninvasively. A relevant source of enriched tumor markers could potentially be found in the tumor secretome. Although numerous studies have evaluated secretomes from various cancers, the influence of the cancer secretome derived from salivary gland cancers on the behavior of normal cells has not yet been elucidated. Our data indicate that secretome derived from salivary gland cancer cells can influence the expression of two potential biomarkers of oral cancer-namely, bone sialoprotein (BSP) and dentin sialoprotein (DSP)-in normal salivary gland cells. Using routine immunohistochemistry, immunofluorescence, and immunoblotting techniques, we demonstrate an enrichment of BSP and DSP in human salivary gland (HSG) cancer tissue, unique localizations of BSP and DSP in HSG cancer cells, and enriched expression of BSP and DSP in normal salivary gland cells exposed to a cancer secretome. The secretome domain of the cancer microenvironment could alter signaling cascades responsible for normal cell proliferation, migration, and invasion, thus enhancing cancer cell survival and the potential for cancer progression. The cancer secretome may be critical in maintaining and stimulating "cancer-ness," thus potentially promoting specific hallmarks of metastasis.

Scheduler for multiprocessor system switch with selective pairing

DOEpatents

Gara, Alan; Gschwind, Michael Karl; Salapura, Valentina

2015-01-06

System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.

Baseband processor development for the Advanced Communications Satellite Program

NASA Technical Reports Server (NTRS)

Moat, D.; Sabourin, D.; Stilwell, J.; Mccallister, R.; Borota, M.

1982-01-01

An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

System and method for controlling power consumption in a computer system based on user satisfaction

DOEpatents

Yang, Lei; Dick, Robert P; Chen, Xi; Memik, Gokhan; Dinda, Peter A; Shy, Alex; Ozisikyilmaz, Berkin; Mallik, Arindam; Choudhary, Alok

2014-04-22

Systems and methods for controlling power consumption in a computer system. For each of a plurality of interactive applications, the method changes a frequency at which a processor of the computer system runs, receives an indication of user satisfaction, determines a relationship between the changed frequency and the user satisfaction of the interactive application, and stores the determined relationship information. The determined relationship can distinguish between different users and different interactive applications. A frequency may be selected from the discrete frequencies at which the processor of the computer system runs based on the determined relationship information for a particular user and a particular interactive application running on the processor of the computer system. The processor may be adapted to run at the selected frequency.

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

NASA Astrophysics Data System (ADS)

Barr, David R. W.; Dudek, Piotr

2009-12-01

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.