Quantifying Nanoparticle Release from Nanotechnology: Scientific Operating Procedure Series: SOP C 3

DTIC Science & Technology

2017-02-01

Operating Procedure Series : SOP-C-3 En vi ro nm en ta l L ab or at or y David P. Martin, Aimee R. Poda, and Anthony J. Bednar February 2017...Operating Procedure Series : SOP-C-3 David P. Martin, Aimee R. Poda, and Anthony J. Bednar Environmental Laboratory U.S. Army Engineer Research and...so designated by other authorized documents. DESTROY THIS REPORT WHEN NO LONGER NEEDED. DO NOT RETURN IT TO THE ORIGINATOR. ERDC/EL SR-17-1 iii

Programmable synaptic chip for electronic neural networks

NASA Technical Reports Server (NTRS)

Moopenn, A.; Langenbacher, H.; Thakoor, A. P.; Khanna, S. K.

1988-01-01

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

PCI bus content-addressable-memory (CAM) implementation on FPGA for pattern recognition/image retrieval in a distributed environment

NASA Astrophysics Data System (ADS)

Megherbi, Dalila B.; Yan, Yin; Tanmay, Parikh; Khoury, Jed; Woods, C. L.

2004-11-01

Recently surveillance and Automatic Target Recognition (ATR) applications are increasing as the cost of computing power needed to process the massive amount of information continues to fall. This computing power has been made possible partly by the latest advances in FPGAs and SOPCs. In particular, to design and implement state-of-the-Art electro-optical imaging systems to provide advanced surveillance capabilities, there is a need to integrate several technologies (e.g. telescope, precise optics, cameras, image/compute vision algorithms, which can be geographically distributed or sharing distributed resources) into a programmable system and DSP systems. Additionally, pattern recognition techniques and fast information retrieval, are often important components of intelligent systems. The aim of this work is using embedded FPGA as a fast, configurable and synthesizable search engine in fast image pattern recognition/retrieval in a distributed hardware/software co-design environment. In particular, we propose and show a low cost Content Addressable Memory (CAM)-based distributed embedded FPGA hardware architecture solution with real time recognition capabilities and computing for pattern look-up, pattern recognition, and image retrieval. We show how the distributed CAM-based architecture offers a performance advantage of an order-of-magnitude over RAM-based architecture (Random Access Memory) search for implementing high speed pattern recognition for image retrieval. The methods of designing, implementing, and analyzing the proposed CAM based embedded architecture are described here. Other SOPC solutions/design issues are covered. Finally, experimental results, hardware verification, and performance evaluations using both the Xilinx Virtex-II and the Altera Apex20k are provided to show the potential and power of the proposed method for low cost reconfigurable fast image pattern recognition/retrieval at the hardware/software co-design level.

A Programmable and Configurable Mixed-Mode FPAA SoC

DTIC Science & Technology

2016-03-17

A Programmable and Configurable Mixed-Mode FPAA SoC Sahil Shah, Sihwan Kim, Farhan Adil, Jennifer Hasler, Suma George, Michelle Collins, Richard...Abstract: The authors present a Floating-Gate based, System-On-Chip large-scale Field- Programmable Analog Array IC that integrates divergent concepts...Floating-Gate, SoC, Command Word Classification This paper presents a Floating-Gate (FG) based, System- On-Chip (SoC) large-scale Field- Programmable

Programmable on-chip and off-chip network architecture on demand for flexible optical intra-datacenters.

PubMed

Rofoee, Bijan Rahimzadeh; Zervas, Georgios; Yan, Yan; Amaya, Norberto; Qin, Yixuan; Simeonidou, Dimitra

2013-03-11

The paper presents a novel network architecture on demand approach using on-chip and-off chip implementations, enabling programmable, highly efficient and transparent networking, well suited for intra-datacenter communications. The implemented FPGA-based adaptable line-card with on-chip design along with an architecture on demand (AoD) based off-chip flexible switching node, deliver single chip dual L2-Packet/L1-time shared optical network (TSON) server Network Interface Cards (NIC) interconnected through transparent AoD based switch. It enables hitless adaptation between Ethernet over wavelength switched network (EoWSON), and TSON based sub-wavelength switching, providing flexible bitrates, while meeting strict bandwidth, QoS requirements. The on and off-chip performance results show high throughput (9.86Ethernet, 8.68Gbps TSON), high QoS, as well as hitless switch-over.

PROGRAPE-1: A Programmable, Multi-Purpose Computer for Many-Body Simulations

NASA Astrophysics Data System (ADS)

Hamada, Tsuyoshi; Fukushige, Toshiyuki; Kawai, Atsushi; Makino, Junichiro

2000-10-01

We have developed PROGRAPE-1 (PROgrammable GRAPE-1), a programmable multi-purpose computer for many-body simulations. The main difference between PROGRAPE-1 and ``traditional'' GRAPE systems is that the former uses FPGA (Field Programmable Gate Array) chips as the processing elements, while the latter relies on a hardwired pipeline processor specialized to gravitational interactions. Since the logic implemented in FPGA chips can be reconfigured, we can use PROGRAPE-1 to calculate not only gravitational interactions, but also other forms of interactions, such as the van der Waals force, hydro\\-dynamical interactions in the SPHr calculation, and so on. PROGRAPE-1 comprises two Altera EPF10K100 FPGA chips, each of which contains nominally 100000 gates. To evaluate the programmability and performance of PROGRAPE-1, we implemented a pipeline for gravitational interactions similar to that of GRAPE-3. One pipeline is fitted into a single FPGA chip, operated at 16 MHz clock. Thus, for gravitational interactions, PROGRAPE-1 provided a speed of 0.96 Gflops-equivalent. PROGRAPE will prove to be useful for a wide-range of particle-based simulations in which the calculation cost of interactions other than gravity is high, such as the evaluation of SPH interactions.

A 50Mbit/Sec. CMOS Video Linestore System

NASA Astrophysics Data System (ADS)

Jeung, Yeun C.

1988-10-01

This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

Programmable Multi-Chip Module

DOEpatents

Kautz, David; Morgenstern, Howard; Blazek, Roy J.

2005-05-24

A multi-chip module comprising a low-temperature co-fired ceramic substrate having a first side on which are mounted active components and a second side on which are mounted passive components, wherein this segregation of components allows for hermetically sealing the active components with a cover while leaving accessible the passive components, and wherein the passive components are secured using a reflow soldering technique and are removable and replaceable so as to make the multi-chip module substantially programmable with regard to the passive components.

Programmable Multi-Chip Module

DOEpatents

Kautz, David; Morgenstern, Howard; Blazek, Roy J.

2004-11-16

A multi-chip module comprising a low-temperature co-fired ceramic substrate having a first side on which are mounted active components and a second side on which are mounted passive components, wherein this segregation of components allows for hermetically sealing the active components with a cover while leaving accessible the passive components, and wherein the passive components are secured using a reflow soldering technique and are removable and replaceable so as to make the multi-chip module substantially programmable with regard to the passive components.

Programmable multi-chip module

DOEpatents

Kautz, David; Morgenstern, Howard; Blazek, Roy J.

2004-03-02

A multi-chip module comprising a low-temperature co-fired ceramic substrate having a first side on which are mounted active components and a second side on which are mounted passive components, wherein this segregation of components allows for hermetically sealing the active components with a cover while leaving accessible the passive components, and wherein the passive components are secured using a reflow soldering technique and are removable and replaceable so as to make the multi-chip module substantially programmable with regard to the passive components.

An Innovative Method of Teaching Electronic System Design with PSoC

ERIC Educational Resources Information Center

Ye, Zhaohui; Hua, Chengying

2012-01-01

Programmable system-on-chip (PSoC), which provides a microprocessor and programmable analog and digital peripheral functions in a single chip, is very convenient for mixed-signal electronic system design. This paper presents the experience of teaching contemporary mixed-signal electronic system design with PSoC in the Department of Automation,…

Design and Implementation of an MC68020-Based Educational Computer Board

DTIC Science & Technology

1989-12-01

device and the other for a Macintosh personal computer. A stored program can be installed in 8K bytes Programmable Read Only Memory (PROM) to initialize...MHz. It includes four * Static Random Access Memory (SRAM) chips which provide a storage of 32K bytes. Two Programmable Array Logic (PAL) chips...device and the other for a Macintosh personal computer. A stored program can be installed in 8K bytes Programmable Read Only Memory (PROM) to

Convolutional Neural Network on Embedded Linux(trademark) System-on-Chip: A Methodology and Performance Benchmark

DTIC Science & Technology

2016-05-01

A9 CPU and 15 W for the i7 CPU. A method of accelerating this computation is by using a customized hardware unit called a field- programmable gate...implementation of custom logic to accelerate com- putational workloads. This FPGA fabric, in addition to the standard programmable logic, contains 220...chip; field- programmable gate array Daniel Gebhardt U U U U 18 (619) 553-2786 INITIAL DISTRIBUTION 84300 Library (2) 85300 Archive/Stock (1

Convolutional Neural Network on Embedded Linux System-on-Chip: A Methodology and Performance Benchmark

DTIC Science & Technology

2016-05-01

A9 CPU and 15 W for the i7 CPU. A method of accelerating this computation is by using a customized hardware unit called a field- programmable gate...implementation of custom logic to accelerate com- putational workloads. This FPGA fabric, in addition to the standard programmable logic, contains 220...chip; field- programmable gate array Daniel Gebhardt U U U U 18 (619) 553-2786 INITIAL DISTRIBUTION 84300 Library (2) 85300 Archive/Stock (1

Programmable bio-nano-chip system for saliva diagnostics

NASA Astrophysics Data System (ADS)

Christodoulides, Nicolaos; De La Garza, Richard; Simmons, Glennon W.; McRae, Michael P.; Wong, Jorge; Kosten, Thomas R.; Miller, Craig S.; Ebersole, Jeffrey L.; McDevitt, John

2014-06-01

This manuscript describes programmable Bio-Nano-Chip (p-BNC) approach that serves as miniaturized assay platform designed for the rapid detection and quantitation of multiple analytes in biological fluids along with the specific applications in salivary diagnostics intended for the point of need (PON). Included here are oral fluid-based tests for local periodontal disease, systemic cardiac disease and multiplexed tests for drugs of abuse.

Web surveillance system using platform-based design

NASA Astrophysics Data System (ADS)

Lin, Shin-Yo; Tsai, Tsung-Han

2004-04-01

A revolutionary methodology of SOPC platform-based design environment for multimedia communications will be developed. We embed a softcore processor to perform the image compression in FPGA. Then, we plug-in an Ethernet daughter board in the SOPC development platform system. Afterward, a web surveillance platform system is presented. The web surveillance system consists of three parts: image capture, web server and JPEG compression. In this architecture, user can control the surveillance system by remote. By the IP address configures to Ethernet daughter board, the user can access the surveillance system via browser. When user access the surveillance system, the CMOS sensor presently capture the remote image. After that, it will feed the captured image with the embedded processor. The embedded processor immediately performs the JPEG compression. Afterward, the user receives the compressed data via Ethernet. To sum up of the above mentioned, the all system will be implemented on APEX20K200E484-2X device.

Bending elasticity of lipid membranes in presence of beta 2 glycoprotein I in the surrounding solution

NASA Astrophysics Data System (ADS)

Pavlič, J. I.; Genova, J.; Zheliaskova, A.; Iglič, A.; Mitov, M. D.

2010-11-01

Thermally induced shape fluctuations of giant quasi-spherical lipid vesicles are used to study the bending elasticity modulus kc of a phospholipid (PHLP) membranes in presence of beta 2 glycoprotein I (β2-GPI) in the aqueous solution which surrounds the vesicle's membrane. The bending elastic modulus kc of PHLP - protein membrane was obtained for different mass concentrations of β2-GPI for pure neutral SOPC membranes and for mixed SOPC: Cardiolipin negatively charged membranes. The experimental results for the bending elastic modulus kc of the PHLP membranes does not show dependence on the concentration of β2-GPI in the range from 5.5 to 55 μg/ml, when β2-GPI is present in the aqueous solution surrounding the vesicle's membrane. Obtained results are in good agreement with predictions, based on different experiments, explaining the mechanism of binding of β2-GPI to neutral membranes.

A SOPC-BASED Evaluation of AES for 2.4 GHz Wireless Network

NASA Astrophysics Data System (ADS)

Ken, Cai; Xiaoying, Liang

In modern systems, data security is needed more than ever before and many cryptographic algorithms are utilized for security services. Wireless Sensor Networks (WSN) is an example of such technologies. In this paper an innovative SOPC-based approach for the security services evaluation in WSN is proposed that addresses the issues of scalability, flexible performance, and silicon efficiency for the hardware acceleration of encryption system. The design includes a Nios II processor together with custom designed modules for the Advanced Encryption Standard (AES) which has become the default choice for various security services in numerous applications. The objective of this mechanism is to present an efficient hardware realization of AES using very high speed integrated circuit hardware description language (Verilog HDL) and expand the usability for various applications. As compared to traditional customize processor design, the mechanism provides a very broad range of cost/performance points.

A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor System.

PubMed

Current, K W; Yuk, K; McConaghy, C; Gascoyne, P R C; Schwartz, J A; Vykoukal, J V; Andrews, C

2007-06-01

A high-voltage (HV) integrated circuit has been demonstrated to transport fluidic droplet samples on programmable paths across the array of driving electrodes on its hydrophobically coated surface. This exciter chip is the engine for dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip systems, creating field excitations that inject and move fluidic droplets onto and about the manipulation surface. The architecture of this chip is expandable to arrays of N X N identical HV electrode driver circuits and electrodes. The exciter chip is programmable in several senses. The routes of multiple droplets may be set arbitrarily within the bounds of the electrode array. The electrode excitation waveform voltage amplitude, phase, and frequency may be adjusted based on the system configuration and the signal required to manipulate a particular fluid droplet composition. The voltage amplitude of the electrode excitation waveform can be set from the minimum logic level up to the maximum limit of the breakdown voltage of the fabrication technology. The frequency of the electrode excitation waveform can also be set independently of its voltage, up to a maximum depending upon the type of droplets that must be driven. The exciter chip can be coated and its oxide surface used as the droplet manipulation surface or it can be used with a top-mounted, enclosed fluidic chamber consisting of a variety of materials. The HV capability of the exciter chip allows the generated DEP forces to penetrate into the enclosed chamber region and an adjustable voltage amplitude can accommodate a variety of chamber floor thicknesses. This demonstration exciter chip has a 32 x 32 array of nominally 100 V electrode drivers that are individually programmable at each time point in the procedure to either of two phases: 0deg and 180deg with respect to the reference clock. For this demonstration chip, while operating the electrodes with a 100-V peak-to-peak periodic waveform, the maximum HV electrode waveform frequency is about 200 Hz; and standard 5-V CMOS logic data communication rate is variable up to 250 kHz. This HV demonstration chip is fabricated in a 130-V 1.0-mum SOI CMOS fabrication technology, dissipates a maximum of 1.87 W, and is about 10.4 mm x 8.2 mm.

Chips: A Tool for Developing Software Interfaces Interactively.

ERIC Educational Resources Information Center

Cunningham, Robert E.; And Others

This report provides a detailed description of Chips, an interactive tool for developing software employing graphical/computer interfaces on Xerox Lisp machines. It is noted that Chips, which is implemented as a collection of customizable classes, provides the programmer with a rich graphical interface for the creation of rich graphical…

Neural dynamics in reconfigurable silicon.

PubMed

Basu, A; Ramakrishnan, S; Petre, C; Koziol, S; Brink, S; Hasler, P E

2010-10-01

A neuromorphic analog chip is presented that is capable of implementing massively parallel neural computations while retaining the programmability of digital systems. We show measurements from neurons with Hopf bifurcations and integrate and fire neurons, excitatory and inhibitory synapses, passive dendrite cables, coupled spiking neurons, and central pattern generators implemented on the chip. This chip provides a platform for not only simulating detailed neuron dynamics but also uses the same to interface with actual cells in applications such as a dynamic clamp. There are 28 computational analog blocks (CAB), each consisting of ion channels with tunable parameters, synapses, winner-take-all elements, current sources, transconductance amplifiers, and capacitors. There are four other CABs which have programmable bias generators. The programmability is achieved using floating gate transistors with on-chip programming control. The switch matrix for interconnecting the components in CABs also consists of floating-gate transistors. Emphasis is placed on replicating the detailed dynamics of computational neural models. Massive computational area efficiency is obtained by using the reconfigurable interconnect as synaptic weights, resulting in more than 50 000 possible 9-b accurate synapses in 9 mm(2).

Neuron array with plastic synapses and programmable dendrites.

PubMed

Ramakrishnan, Shubha; Wunderlich, Richard; Hasler, Jennifer; George, Suma

2013-10-01

We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style routing with local memory for intra-chip connectivity. We model neurons with biologically realistic channel models, synapses and dendrites. This chip is suitable for small-scale network simulations and can also be used for sequence detection, utilizing directional selectivity properties of dendrites, ultimately for use in word recognition.

Chronic Disease Risk Reduction with a Community-Based Lifestyle Change Programme

ERIC Educational Resources Information Center

Merrill, Ray M; Aldana, Steven G; Greenlaw, Roger L; Salberg, Audrey; Englert, Heike

2008-01-01

Objective To assess whether reduced health risks resulting from the Coronary Health Improvement Project (CHIP) persist through 18 months. Methods: The CHIP is a four-week health education course designed to help individuals reduce cardiovascular risk by improving nutrition and physical activity behaviors. Analyses were based on 211 CHIP enrollees,…

A High-Voltage Integrated Circuit Engine for a Dielectrophoresis-based Programmable Micro-Fluidic Processor

PubMed Central

Current, K. Wayne; Yuk, Kelvin; McConaghy, Charles; Gascoyne, Peter R. C.; Schwartz, Jon A.; Vykoukal, Jody V.; Andrews, Craig

2010-01-01

A high-voltage (HV) integrated circuit has been demonstrated to transport droplets on programmable paths across its coated surface. This chip is the engine for a dielectrophoresis (DEP)-based micro-fluidic lab-on-a-chip system. This chip creates DEP forces that move and help inject droplets. Electrode excitation voltage and frequency are variable. With the electrodes driven with a 100V peak-to-peak periodic waveform, the maximum high-voltage electrode waveform frequency is about 200Hz. Data communication rate is variable up to 250kHz. This demonstration chip has a 32×32 array of nominally 100V electrode drivers. It is fabricated in a 130V SOI CMOS fabrication technology, dissipates a maximum of 1.87W, and is about 10.4 mm × 8.2 mm. PMID:23989241

A Cell Programmable Assay (CPA) chip.

PubMed

Ju, Jongil; Warrick, Jay; Beebe, David J

2010-08-21

This article describes two kinds of "Cell Programmable Assay" (CPA) chips that utilize passive pumping for the culture and autonomous staining of cells to simply common protocols. One is a single timer channel CPA (sCPA) chip that has one timer channel and one main channel containing a cell culture chamber. The sCPA is used to culture and stain cells using Hoechst nuclear staining dye (a 2 step staining process). The other is a dual timer channel CPA (dCPA) chip that has two timer channels and one main channel with a chamber for cell culture. The dCPA is used here to culture, fix, permeablize, and stain cells using DAPI. The additional timer channel of the dCPA chip allows for automation of 3 steps. The CPA chips were successfully evaluated using HEK 293 cells. In addition, we provide a simplified equation for tuning or redesigning CPA chips to meet the needs of a variety of protocols that may require different timings. The equation is easy to use as it only depends upon the dimensions of microchannel and the volume of the reagent drops. The sCPA and dCPA chips can be readily modified to apply to a wide variety of common cell culture methods and procedures.

Role of chirality in peptide-induced formation of cholesterol-rich domains

PubMed Central

2005-01-01

The chiral specificity of the interactions of peptides that induce the formation of cholesterol-rich domains has not been extensively investigated. Both the peptide and most lipids are chiral, so there is a possibility that interactions between peptide and lipid could require chiral recognition. On the other hand, in our models with small peptides, the extent of folding of the peptide to form a specific binding pocket is limited. We have determined that replacing cholesterol with its enantiomer, ent-cholesterol, alters the modulation of lipid organization by peptides. The phase-transition properties of SOPC (1-stearoyl-2-oleoylphosphatidylcholine):cholesterol [in a 6:4 ratio with 0.2 mol% PtdIns(4,5)P2] are not significantly altered when ent-cholesterol replaces cholesterol. However, in the presence of 10 mol% of a 19-amino-acid, N-terminally myristoylated fragment (myristoyl-GGKLSKKKKGYNVNDEKAK-amide) of the protein NAP-22 (neuronal axonal membrane protein), the lipid mixture containing cholesterol undergoes separation into cholesterol-rich and cholesterol-depleted domains. This does not occur when ent-cholesterol replaces cholesterol. In another example, when N-acetyl-Leu-Trp-Tyr-Ile-Lys-amide (N-acetyl-LWYIK-amide) is added to SOPC:cholesterol (7:3 ratio), there is a marked increase in the transition enthalpy of the phospholipid, indicating separation of a cholesterol-depleted domain of SOPC. This phenomenon completely disappears when ent-cholesterol replaces cholesterol. The all-D-isomer of N-acetyl-LWYIK-amide also induces the formation of cholesterol-rich domains with natural cholesterol, but does so to a lesser extent with ent-cholesterol. Thus specific peptide chirality is not required for interaction with cholesterol-containing membranes. However, a specific chirality of membrane lipids is required for peptide-induced formation of cholesterol-rich domains. PMID:15929726

Single-chip pulse programmer for magnetic resonance imaging using a 32-bit microcontroller.

PubMed

Handa, Shinya; Domalain, Thierry; Kose, Katsumi

2007-08-01

A magnetic resonance imaging (MRI) pulse programmer has been developed using a single-chip microcontroller (ADmicroC7026). The microcontroller includes all the components required for the MRI pulse programmer: a 32-bit RISC CPU core, 62 kbytes of flash memory, 8 kbytes of SRAM, two 32-bit timers, four 12-bit DA converters, and 40 bits of general purpose I/O. An evaluation board for the microcontroller was connected to a host personal computer (PC), an MRI transceiver, and a gradient driver using interface circuitry. Target (embedded) and host PC programs were developed to enable MRI pulse sequence generation by the microcontroller. The pulse programmer achieved a (nominal) time resolution of approximately 100 ns and a minimum time delay between successive events of approximately 9 micros. Imaging experiments using the pulse programmer demonstrated the effectiveness of our approach.

Single-chip pulse programmer for magnetic resonance imaging using a 32-bit microcontroller

NASA Astrophysics Data System (ADS)

Handa, Shinya; Domalain, Thierry; Kose, Katsumi

2007-08-01

A magnetic resonance imaging (MRI) pulse programmer has been developed using a single-chip microcontroller (ADμC7026). The microcontroller includes all the components required for the MRI pulse programmer: a 32-bit RISC CPU core, 62kbytes of flash memory, 8kbytes of SRAM, two 32-bit timers, four 12-bit DA converters, and 40bits of general purpose I/O. An evaluation board for the microcontroller was connected to a host personal computer (PC), an MRI transceiver, and a gradient driver using interface circuitry. Target (embedded) and host PC programs were developed to enable MRI pulse sequence generation by the microcontroller. The pulse programmer achieved a (nominal) time resolution of approximately 100ns and a minimum time delay between successive events of approximately 9μs. Imaging experiments using the pulse programmer demonstrated the effectiveness of our approach.

Optically Programmable Field Programmable Gate Arrays (FPGA) Systems

DTIC Science & Technology

2004-01-01

VCSEL requires placing the array far enough as to overlap the entire footprint of the signal beam in order to record the hologram. Therefore, these...hologram that self-focuses, due to phase -conjugation, on the array of detectors in the chip. VC A 10 m m 10 mm 18mm 16mm SEL RRAY OPTICAL MEMORY LOGIC...the VCSEL array , the chip and the optical material, and the requirements they have to meet for their use in the OPGA system. Section

Toward Evolvable Hardware Chips: Experiments with a Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Stoica, Adrian

1998-01-01

Evolvable Hardware is reconfigurable hardware that self-configures under the control of an evolutionary algorithm. We search for a hardware configuration can be performed using software models or, faster and more accurate, directly in reconfigurable hardware. Several experiments have demonstrated the possibility to automatically synthesize both digital and analog circuits. The paper introduces an approach to automated synthesis of CMOS circuits, based on evolution on a Programmable Transistor Array (PTA). The approach is illustrated with a software experiment showing evolutionary synthesis of a circuit with a desired DC characteristic. A hardware implementation of a test PTA chip is then described, and the same evolutionary experiment is performed on the chip demonstrating circuit synthesis/self-configuration directly in hardware.

Morphological study of lipid vesicles in presence of amphotericin B via modification of the microfluidic CellASIC platform and LED illumination microscopy

NASA Astrophysics Data System (ADS)

Genova, J.; Decheva-Zarkova, M.; Pavlič, J. I.

2016-02-01

Giant lipid vesicles (liposomes) are the simplest model of the biological cell and can be easily formed from natural or synthetic lipid species with controlled composition and properties. This is the reason why they are the preferred objects for various scientific investigations. Amphotericin B (AmB) is a membrane active drug, used for treatment of systemic fungal infections. In this work we studied the morphological behavior of giant SOPC vesicles in asymmetrical presence of amphotericin B antibiotic in the vicinity of the lipid membrane. The visualization of the vesicles was carried out via inverted phase contrast microscopy. The illumination source was modified in a way that tungsten light bulb was replaced by 10 W white LED chip. All the experiments were performed using CellASIC ONIX Microfluidic Platform. The setup has been modified thus opening new opportunities for a variety of experimental realizations. The performed morphological studies showed strong and irreversible effect on the vesicle shape at the presence of amphotericin B in concentration 10-5 g/l in the outer for the liposome's membrane solution. At concentration 10-3 g/l AmB the effect was less visible and in 15-20 minutes the vesicles regained its initial spherical shape.

Field-programmable lab-on-a-chip based on microelectrode dot array architecture.

PubMed

Wang, Gary; Teng, Daniel; Lai, Yi-Tse; Lu, Yi-Wen; Ho, Yingchieh; Lee, Chen-Yi

2014-09-01

The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 × 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.

75 FR 32803 - Notice of Issuance of Final Determination Concerning a GTX Mobile+ Hand Held Computer

Federal Register 2010, 2011, 2012, 2013, 2014

2010-06-09

... Programmable Read-Only Memory (``PROM'') chip, substantially transformed the PROM into a U.S. article. The... parts (such as various connectors and an Electronically Erasable Programmable Read Only Memory, or...

Improved On-Chip Measurement of Delay in an FPGA or ASIC

NASA Technical Reports Server (NTRS)

Chen, Yuan; Burke, Gary; Sheldon, Douglas

2007-01-01

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Programmable lab-on-a-chip system for single cell analysis

NASA Astrophysics Data System (ADS)

Thalhammer, S.

2009-05-01

The collection, selection, amplification and detection of minimum genetic samples became a part of everyday life in medical and biological laboratories, to analyze DNA-fragments of pathogens, patient samples and traces on crime scenes. About a decade ago, a handful of researchers began discussing an intriguing idea. Could the equipment needed for everyday chemistry and biology procedures be shrunk to fit on a chip in the size of a fingernail? Miniature devices for, say, analysing DNA and proteins should be faster and cheaper than conventional versions. Lab-on-a-chip is an advanced technology that integrates a microfluidic system on a microscale chip device. The "laboratory" is created by means of channels, mixers, reservoirs, diffusion chambers, integrated electrodes, pumps, valves and more. With lab-ona- chip technology, complete laboratories on a square centimetre can be created. Here, a multifunctional programmable Lab-on-a-Chip driven by nanofluidics and controlled by surface acoustic waves (SAW) is presented. This system combines serial DNA-isolation-, amplification- and array-detection-process on a modified glass-platform. The fluid actuation is controlled via SAW by interdigital transducers implemented in the chemical modified chip surface. The chemical surface modification allows fluid handling in the sub-microliter range. Minute amount of sample material is extracted by laser-based microdissection out of e.g. histological sections at the single cell level. A few picogram of genetic material are isolated and transferred via a low-pressure transfer system (SPATS) onto the chip. Subsequently the genetic material inside single droplets, which behave like "virtual" beaker, is transported to the reaction and analysis centers on the chip surface via surface acoustic waves, mainly known as noise dumping filters in mobile phones. At these "biological reactors" the genetic material is processed, e.g. amplified via polymerase chain reaction methods, and genetically characterized.

Associative architecture for image processing

NASA Astrophysics Data System (ADS)

Adar, Rutie; Akerib, Avidan

1997-09-01

This article presents a new generation in parallel processing architecture for real-time image processing. The approach is implemented in a real time image processor chip, called the XiumTM-2, based on combining a fully associative array which provides the parallel engine with a serial RISC core on the same die. The architecture is fully programmable and can be programmed to implement a wide range of color image processing, computer vision and media processing functions in real time. The associative part of the chip is based on patented pending methodology of Associative Computing Ltd. (ACL), which condenses 2048 associative processors, each of 128 'intelligent' bits. Each bit can be a processing bit or a memory bit. At only 33 MHz and 0.6 micron manufacturing technology process, the chip has a computational power of 3 billion ALU operations per second and 66 billion string search operations per second. The fully programmable nature of the XiumTM-2 chip enables developers to use ACL tools to write their own proprietary algorithms combined with existing image processing and analysis functions from ACL's extended set of libraries.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

NASA Astrophysics Data System (ADS)

Liu, Lintao; Gao, Yuhan; Deng, Jun

2017-11-01

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm 2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication. Project supported by the National High Technology and Development Program of China (No. 2012AA012303).

Cascaded VLSI Chips Help Neural Network To Learn

NASA Technical Reports Server (NTRS)

Duong, Tuan A.; Daud, Taher; Thakoor, Anilkumar P.

1993-01-01

Cascading provides 12-bit resolution needed for learning. Using conventional silicon chip fabrication technology of VLSI, fully connected architecture consisting of 32 wide-range, variable gain, sigmoidal neurons along one diagonal and 7-bit resolution, electrically programmable, synaptic 32 x 31 weight matrix implemented on neuron-synapse chip. To increase weight nominally from 7 to 13 bits, synapses on chip individually cascaded with respective synapses on another 32 x 32 matrix chip with 7-bit resolution synapses only (without neurons). Cascade correlation algorithm varies number of layers effectively connected into network; adds hidden layers one at a time during learning process in such way as to optimize overall number of neurons and complexity and configuration of network.

Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs †.

PubMed

Nose, Atsushi; Yamazaki, Tomohiro; Katayama, Hironobu; Uehara, Shuji; Kobayashi, Masatsugu; Shida, Sayaka; Odahara, Masaki; Takamiya, Kenichi; Matsumoto, Shizunori; Miyashita, Leo; Watanabe, Yoshihiro; Izawa, Takashi; Muramatsu, Yoshinori; Nitta, Yoshikazu; Ishikawa, Masatoshi

2018-04-24

We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 × 2 binning) vision chip with 3D-stacked column-parallel Analog-to-Digital Converters (ADCs) and 140 Giga Operation per Second (GOPS) programmable Single Instruction Multiple Data (SIMD) column-parallel PEs for new sensing applications. The 3D-stacked structure and column parallel processing architecture achieve high sensitivity, high resolution, and high-accuracy object positioning.

Programmable neural processing on a smartdust for brain-computer interfaces.

PubMed

Yuwen Sun; Shimeng Huang; Oresko, Joseph J; Cheng, Allen C

2010-10-01

Brain-computer interfaces (BCIs) offer tremendous promise for improving the quality of life for disabled individuals. BCIs use spike sorting to identify the source of each neural firing. To date, spike sorting has been performed by either using off-chip analysis, which requires a wired connection penetrating the skull to a bulky external power/processing unit, or via custom application-specific integrated circuits that lack the programmability to perform different algorithms and upgrades. In this research, we propose and test the feasibility of performing on-chip, real-time spike sorting on a programmable smartdust, including feature extraction, classification, compression, and wireless transmission. A detailed power/performance tradeoff analysis using DVFS is presented. Our experimental results show that the execution time and power density meet the requirements to perform real-time spike sorting and wireless transmission on a single neural channel.

Punch Card Programmable Microfluidics

PubMed Central

Korir, George; Prakash, Manu

2015-01-01

Small volume fluid handling in single and multiphase microfluidics provides a promising strategy for efficient bio-chemical assays, low-cost point-of-care diagnostics and new approaches to scientific discoveries. However multiple barriers exist towards low-cost field deployment of programmable microfluidics. Incorporating multiple pumps, mixers and discrete valve based control of nanoliter fluids and droplets in an integrated, programmable manner without additional required external components has remained elusive. Combining the idea of punch card programming with arbitrary fluid control, here we describe a self-contained, hand-crank powered, multiplex and robust programmable microfluidic platform. A paper tape encodes information as a series of punched holes. A mechanical reader/actuator reads these paper tapes and correspondingly executes operations onto a microfluidic chip coupled to the platform in a plug-and-play fashion. Enabled by the complexity of codes that can be represented by a series of holes in punched paper tapes, we demonstrate independent control of 15 on-chip pumps with enhanced mixing, normally-closed valves and a novel on-demand impact-based droplet generator. We demonstrate robustness of operation by encoding a string of characters representing the word “PUNCHCARD MICROFLUIDICS” using the droplet generator. Multiplexing is demonstrated by implementing an example colorimetric water quality assays for pH, ammonia, nitrite and nitrate content in different water samples. With its portable and robust design, low cost and ease-of-use, we envision punch card programmable microfluidics will bring complex control of microfluidic chips into field-based applications in low-resource settings and in the hands of children around the world. PMID:25738834

Punch card programmable microfluidics.

PubMed

Korir, George; Prakash, Manu

2015-01-01

Small volume fluid handling in single and multiphase microfluidics provides a promising strategy for efficient bio-chemical assays, low-cost point-of-care diagnostics and new approaches to scientific discoveries. However multiple barriers exist towards low-cost field deployment of programmable microfluidics. Incorporating multiple pumps, mixers and discrete valve based control of nanoliter fluids and droplets in an integrated, programmable manner without additional required external components has remained elusive. Combining the idea of punch card programming with arbitrary fluid control, here we describe a self-contained, hand-crank powered, multiplex and robust programmable microfluidic platform. A paper tape encodes information as a series of punched holes. A mechanical reader/actuator reads these paper tapes and correspondingly executes operations onto a microfluidic chip coupled to the platform in a plug-and-play fashion. Enabled by the complexity of codes that can be represented by a series of holes in punched paper tapes, we demonstrate independent control of 15 on-chip pumps with enhanced mixing, normally-closed valves and a novel on-demand impact-based droplet generator. We demonstrate robustness of operation by encoding a string of characters representing the word "PUNCHCARD MICROFLUIDICS" using the droplet generator. Multiplexing is demonstrated by implementing an example colorimetric water quality assays for pH, ammonia, nitrite and nitrate content in different water samples. With its portable and robust design, low cost and ease-of-use, we envision punch card programmable microfluidics will bring complex control of microfluidic chips into field-based applications in low-resource settings and in the hands of children around the world.

Selective flow-induced vesicle rupture to sort by membrane mechanical properties

NASA Astrophysics Data System (ADS)

Pommella, Angelo; Brooks, Nicholas J.; Seddon, John M.; Garbin, Valeria

2015-08-01

Vesicle and cell rupture caused by large viscous stresses in ultrasonication is central to biomedical and bioprocessing applications. The flow-induced opening of lipid membranes can be exploited to deliver drugs into cells, or to recover products from cells, provided that it can be obtained in a controlled fashion. Here we demonstrate that differences in lipid membrane and vesicle properties can enable selective flow-induced vesicle break-up. We obtained vesicle populations with different membrane properties by using different lipids (SOPC, DOPC, or POPC) and lipid:cholesterol mixtures (SOPC:chol and DOPC:chol). We subjected vesicles to large deformations in the acoustic microstreaming flow generated by ultrasound-driven microbubbles. By simultaneously deforming vesicles with different properties in the same flow, we determined the conditions in which rupture is selective with respect to the membrane stretching elasticity. We also investigated the effect of vesicle radius and excess area on the threshold for rupture, and identified conditions for robust selectivity based solely on the mechanical properties of the membrane. Our work should enable new sorting mechanisms based on the difference in membrane composition and mechanical properties between different vesicles, capsules, or cells.

Selective flow-induced vesicle rupture to sort by membrane mechanical properties

PubMed Central

Pommella, Angelo; Brooks, Nicholas J.; Seddon, John M.; Garbin, Valeria

2015-01-01

Vesicle and cell rupture caused by large viscous stresses in ultrasonication is central to biomedical and bioprocessing applications. The flow-induced opening of lipid membranes can be exploited to deliver drugs into cells, or to recover products from cells, provided that it can be obtained in a controlled fashion. Here we demonstrate that differences in lipid membrane and vesicle properties can enable selective flow-induced vesicle break-up. We obtained vesicle populations with different membrane properties by using different lipids (SOPC, DOPC, or POPC) and lipid:cholesterol mixtures (SOPC:chol and DOPC:chol). We subjected vesicles to large deformations in the acoustic microstreaming flow generated by ultrasound-driven microbubbles. By simultaneously deforming vesicles with different properties in the same flow, we determined the conditions in which rupture is selective with respect to the membrane stretching elasticity. We also investigated the effect of vesicle radius and excess area on the threshold for rupture, and identified conditions for robust selectivity based solely on the mechanical properties of the membrane. Our work should enable new sorting mechanisms based on the difference in membrane composition and mechanical properties between different vesicles, capsules, or cells. PMID:26302783

Optimized FPGA Implementation of the Thyroid Hormone Secretion Mechanism Using CAD Tools.

PubMed

Alghazo, Jaafar M

2017-02-01

The goal of this paper is to implement the secretion mechanism of the Thyroid Hormone (TH) based on bio-mathematical differential eqs. (DE) on an FPGA chip. Hardware Descriptive Language (HDL) is used to develop a behavioral model of the mechanism derived from the DE. The Thyroid Hormone secretion mechanism is simulated with the interaction of the related stimulating and inhibiting hormones. Synthesis of the simulation is done with the aid of CAD tools and downloaded on a Field Programmable Gate Arrays (FPGAs) Chip. The chip output shows identical behavior to that of the designed algorithm through simulation. It is concluded that the chip mimics the Thyroid Hormone secretion mechanism. The chip, operating in real-time, is computer-independent stand-alone system.

Special-purpose computing for dense stellar systems

NASA Astrophysics Data System (ADS)

Makino, Junichiro

2007-08-01

I'll describe the current status of the GRAPE-DR project. The GRAPE-DR is the next-generation hardware for N-body simulation. Unlike the previous GRAPE hardwares, it is programmable SIMD machine with a large number of simple processors integrated into a single chip. The GRAPE-DR chip consists of 512 simple processors and operates at the clock speed of 500 MHz, delivering the theoretical peak speed of 512/226 Gflops (single/double precision). As of August 2006, the first prototype board with the sample chip successfully passed the test we prepared. The full GRAPE-DR system will consist of 4096 chips, reaching the theoretical peak speed of 2 Pflops.

Next Generation Programmable Bio-Nano-Chip System for On-Site Detection in Oral Fluids.

PubMed

Christodoulides, Nicolaos; De La Garza, Richard; Simmons, Glennon W; McRae, Michael P; Wong, Jorge; Newton, Thomas F; Kosten, Thomas R; Haque, Ahmed; McDevitt, John T

2015-11-23

Current on-site drug of abuse detection methods involve invasive sampling of blood and urine specimens, or collection of oral fluid, followed by qualitative screening tests using immunochromatographic cartridges. Test confirmation and quantitative assessment of a presumptive positive are then provided by remote laboratories, an inefficient and costly process decoupled from the initial sampling. Recently, a new noninvasive oral fluid sampling approach that is integrated with the chip-based Programmable Bio-Nano-Chip (p-BNC) platform has been developed for the rapid (~ 10 minutes), sensitive detection (~ ng/ml) and quantitation of 12 drugs of abuse. Furthermore, the system can provide the time-course of select drug and metabolite profiles in oral fluids. For cocaine, we observed three slope components were correlated with cocaine-induced impairment using this chip-based p-BNC detection modality. Thus, this p-BNC has significant potential for roadside drug testing by law enforcement officers. Initial work reported on chip-based drug detection was completed using 'macro' or "chip in the lab" prototypes, that included metal encased "flow cells", external peristaltic pumps and a bench-top analyzer system instrumentation. We now describe the next generation miniaturized analyzer instrumentation along with customized disposables and sampling devices. These tools will offer real-time oral fluid drug monitoring capabilities, to be used for roadside drug testing as well as testing in clinical settings as a non-invasive, quantitative, accurate and sensitive tool to verify patient adherence to treatment.

Characterization and recovery of Deep Sub Micron (DSM) technologies behavior under radiation

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Wang, Xiao

2005-01-01

This paper serves a twofold purpose: characterize the behavior of a reconfigurable chip exposed to radiation; and demonstrate a method for functionality recovery due to Total Ionizing Dose (TID) effects. The experiments are performed using a PL developed reconfigurable device, a Field Programmable Transistor Array (FPTA). The paper initially describes experiments on the characterization of the NMOS transistor behavior for TID values up to 300krad. The behavior of analog and digital circuits downloaded onto the FPTA chip is also assessed for TID effects. This paper also presents a novel approach for circuit functionality recovery due to radiation effects based on Evolvable Hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged components. Experiments with total radiation dose up to 300kRad show that while the functionality of a variety of circuits, including digital gates, a rectifier and a Digital to Analog Converter implemented on a FPTA-2 chip is degraded/lost at levels before 200kRad, the correct functionality can be recovered through the proposed evolutionary approach and the chips are able to survive higher radiation, for several functions in excess of total radiation dose of 250kRad.

Teaching Discrete and Programmable Logic Design Techniques Using a Single Laboratory Board

ERIC Educational Resources Information Center

Debiec, P.; Byczuk, M.

2011-01-01

Programmable logic devices (PLDs) are used at many universities in introductory digital logic laboratories, where kits containing a single high-capacity PLD replace "standard" sets containing breadboards, wires, and small- or medium-scale integration (SSI/MSI) chips. From the pedagogical point of view, two problems arise in these…

α-tocopherol is well designed to protect polyunsaturated phospholipids: MD simulations

DOE PAGES

Leng, Xiaoling; Kinnun, Jacob A.; Marquardt, Drew; ...

2015-10-20

Here, the presumptive function for alpha-tocopherol (αtoc) in membranes is to protect polyunsaturated lipids against oxidation. Although the chemistry of the process is well established, the role played by molecular structure that we address here with atomistic molecular-dynamics simulations remains controversial. The simulations were run in the constant particle NPT ensemble on hydrated lipid bilayers composed of SDPC (1-stearoyl-2-docosahexaenoylphosphatidylcholine, 18:0-22:6PC) and SOPC (1-stearoyl-2-oleoylphosphatidylcholine, 18:0-18:1PC) in the presence of 20 mol % αtoc at 37°C. SDPC with SA (stearic acid) for the sn-1 chain and DHA (docosahexaenoic acid) for the sn-2 chain is representative of polyunsaturated phospholipids, while SOPC with OAmore » (oleic acid) substituted for the sn-2 chain serves as a monounsaturated control. Solid-state 2H nuclear magnetic resonance and neutron diffraction experiments provide validation. The simulations demonstrate that high disorder enhances the probability that DHA chains at the sn-2 position in SDPC rise up to the bilayer surface, whereby they encounter the chromanol group on αtoc molecules. This behavior is reflected in the van der Waals energy of interaction between αtoc and acyl chains, and illustrated by density maps of distribution for acyl chains around αtoc molecules that were constructed. An ability to more easily penetrate deep into the bilayer is another attribute conferred upon the chromanol group in αtoc by the high disorder possessed by DHA. By examining the trajectory of single molecules, we found that αtoc flip-flops across the SDPC bilayer on a submicrosecond timescale that is an order-of-magnitude greater than in SOPC. Our results reveal mechanisms by which the sacrificial hydroxyl group on the chromanol group can trap lipid peroxyl radicals within the interior and near the surface of a polyunsaturated membrane. At the same time, water-soluble reducing agents that regenerate αtoc can access the chromanol group when it locates at the surface.« less

α-Tocopherol Is Well Designed to Protect Polyunsaturated Phospholipids: MD Simulations

PubMed Central

Leng, Xiaoling; Kinnun, Jacob J.; Marquardt, Drew; Ghefli, Mikel; Kučerka, Norbert; Katsaras, John; Atkinson, Jeffrey; Harroun, Thad A.; Feller, Scott E.; Wassall, Stephen R.

2015-01-01

The presumptive function for alpha-tocopherol (αtoc) in membranes is to protect polyunsaturated lipids against oxidation. Although the chemistry of the process is well established, the role played by molecular structure that we address here with atomistic molecular-dynamics simulations remains controversial. The simulations were run in the constant particle NPT ensemble on hydrated lipid bilayers composed of SDPC (1-stearoyl-2-docosahexaenoylphosphatidylcholine, 18:0-22:6PC) and SOPC (1-stearoyl-2-oleoylphosphatidylcholine, 18:0-18:1PC) in the presence of 20 mol % αtoc at 37°C. SDPC with SA (stearic acid) for the sn-1 chain and DHA (docosahexaenoic acid) for the sn-2 chain is representative of polyunsaturated phospholipids, while SOPC with OA (oleic acid) substituted for the sn-2 chain serves as a monounsaturated control. Solid-state 2H nuclear magnetic resonance and neutron diffraction experiments provide validation. The simulations demonstrate that high disorder enhances the probability that DHA chains at the sn-2 position in SDPC rise up to the bilayer surface, whereby they encounter the chromanol group on αtoc molecules. This behavior is reflected in the van der Waals energy of interaction between αtoc and acyl chains, and illustrated by density maps of distribution for acyl chains around αtoc molecules that were constructed. An ability to more easily penetrate deep into the bilayer is another attribute conferred upon the chromanol group in αtoc by the high disorder possessed by DHA. By examining the trajectory of single molecules, we found that αtoc flip-flops across the SDPC bilayer on a submicrosecond timescale that is an order-of-magnitude greater than in SOPC. Our results reveal mechanisms by which the sacrificial hydroxyl group on the chromanol group can trap lipid peroxyl radicals within the interior and near the surface of a polyunsaturated membrane. At the same time, water-soluble reducing agents that regenerate αtoc can access the chromanol group when it locates at the surface. PMID:26488652

α-Tocopherol Is Well Designed to Protect Polyunsaturated Phospholipids: MD Simulations.

PubMed

Leng, Xiaoling; Kinnun, Jacob J; Marquardt, Drew; Ghefli, Mikel; Kučerka, Norbert; Katsaras, John; Atkinson, Jeffrey; Harroun, Thad A; Feller, Scott E; Wassall, Stephen R

2015-10-20

The presumptive function for alpha-tocopherol (αtoc) in membranes is to protect polyunsaturated lipids against oxidation. Although the chemistry of the process is well established, the role played by molecular structure that we address here with atomistic molecular-dynamics simulations remains controversial. The simulations were run in the constant particle NPT ensemble on hydrated lipid bilayers composed of SDPC (1-stearoyl-2-docosahexaenoylphosphatidylcholine, 18:0-22:6PC) and SOPC (1-stearoyl-2-oleoylphosphatidylcholine, 18:0-18:1PC) in the presence of 20 mol % αtoc at 37°C. SDPC with SA (stearic acid) for the sn-1 chain and DHA (docosahexaenoic acid) for the sn-2 chain is representative of polyunsaturated phospholipids, while SOPC with OA (oleic acid) substituted for the sn-2 chain serves as a monounsaturated control. Solid-state (2)H nuclear magnetic resonance and neutron diffraction experiments provide validation. The simulations demonstrate that high disorder enhances the probability that DHA chains at the sn-2 position in SDPC rise up to the bilayer surface, whereby they encounter the chromanol group on αtoc molecules. This behavior is reflected in the van der Waals energy of interaction between αtoc and acyl chains, and illustrated by density maps of distribution for acyl chains around αtoc molecules that were constructed. An ability to more easily penetrate deep into the bilayer is another attribute conferred upon the chromanol group in αtoc by the high disorder possessed by DHA. By examining the trajectory of single molecules, we found that αtoc flip-flops across the SDPC bilayer on a submicrosecond timescale that is an order-of-magnitude greater than in SOPC. Our results reveal mechanisms by which the sacrificial hydroxyl group on the chromanol group can trap lipid peroxyl radicals within the interior and near the surface of a polyunsaturated membrane. At the same time, water-soluble reducing agents that regenerate αtoc can access the chromanol group when it locates at the surface. Copyright © 2015 Biophysical Society. Published by Elsevier Inc. All rights reserved.

High performance digital read out integrated circuit (DROIC) for infrared imaging

NASA Astrophysics Data System (ADS)

Mizuno, Genki; Olah, Robert; Oduor, Patrick; Dutta, Achyut K.; Dhar, Nibir K.

2016-05-01

Banpil Photonics has developed a high-performance Digital Read-Out Integrated Circuit (DROIC) for image sensors and camera systems targeting various military, industrial and commercial Infrared (IR) imaging applications. The on-chip digitization of the pixel output eliminates the necessity for an external analog-to-digital converter (ADC), which not only cuts costs, but also enables miniaturization of packaging to achieve SWaP-C camera systems. In addition, the DROIC offers new opportunities for greater on-chip processing intelligence that are not possible in conventional analog ROICs prevalent today. Conventional ROICs, which typically can enhance only one high performance attribute such as frame rate, power consumption or noise level, fail when simultaneously targeting the most aggressive performance requirements demanded in imaging applications today. Additionally, scaling analog readout circuits to meet such requirements leads to expensive, high-power consumption with large and complex systems that are untenable in the trend towards SWaP-C. We present the implementation of a VGA format (640x512 pixels 15μm pitch) capacitivetransimpedance amplifier (CTIA) DROIC architecture that incorporates a 12-bit ADC at the pixel level. The CTIA pixel input circuitry has two gain modes with programmable full-well capacity values of 100K e- and 500K e-. The DROIC has been developed with a system-on-chip architecture in mind, where all the timing and biasing are generated internally without requiring any critical external inputs. The chip is configurable with many parameters programmable through a serial programmable interface (SPI). It features a global shutter, low power, and high frame rates programmable from 30 up 500 frames per second in full VGA format supported through 24 LVDS outputs. This DROIC, suitable for hybridization with focal plane arrays (FPA) is ideal for high-performance uncooled camera applications ranging from near IR (NIR) and shortwave IR (SWIR) to mid-wave IR (MWIR) and long-wave IR (LWIR) spectral bands.

Rapid evolution of analog circuits configured on a field programmable transistor array

NASA Technical Reports Server (NTRS)

Stoica, A.; Ferguson, M. I.; Zebulum, R. S.; Keymeulen, D.; Duong, V.; Daud, T.

2002-01-01

The purpose of this paper is to illustrate evolution of analog circuits on a stand-alone board-level evolvable system (SABLES). SABLES is part of an effort to achieve integrated evolvable systems. SABLES provides autonomous, fast (tens to hundreds of seconds), on-chip circuit evolution involving about 100,000 circuit evaluations. Its main components are a JPL Field Programmable Transistor Array (FPTA) chip used as transistor-level reconfigurable hardware, and a TI DSP that implements the evolutionary algorithm controlling the FPTA reconfiguration. The paper details an example of evolution on SABLES and points out to certain transient and memory effects that affect the stability of solutions obtained reusing the same piece of hardware for rapid testing of individuals during evolution.

Effect of Amphotericin B antibiotic on the properties of model lipid membrane

NASA Astrophysics Data System (ADS)

Kiryakova, S.; Dencheva-Zarkova, M.; Genova, J.

2014-12-01

Model membranes formed from natural and synthetic lipids are an interesting object for scientific investigations due to their similarity to biological cell membrane and their simple structure with controlled composition and properties. Amphotericin B is an important polyene antifungal antibiotic, used for treatment of systemic fungal infections. It is known from the literature that the studied antibiotic has a substantial effect on the transmembrane ionic channel structures. When applied to the lipid membranes it has the tendency to create pores and in this way to affect the structure and the properties of the membrane lipid bilayer. In this work the thermally induced shape fluctuations of giant quasi-spherical liposomes have been used to study the influence of polyene antibiotic amphotericin B on the elastic properties of model lipid membranes. It have been shown experimentally that the presence of 3 mol % of AmB in the lipid membrane reduces the bending elasticity of the lipid membrane for both studied cases: pure SOPC membrane and mixed SOPC-Cholesterol membrane. Interaction of the amphotericin B with bilayer lipid membranes containing channels have been studied in this work. Model membranes were self-assembled using the patch-clamp and tip-dip patch clamp technique. We have found that amphotericin B is an ionophore and reduces the resistance of the lipid bilayer.

Reconfigurable virtual electrowetting channels.

PubMed

Banerjee, Ananda; Kreit, Eric; Liu, Yuguang; Heikenfeld, Jason; Papautsky, Ian

2012-02-21

Lab-on-a-chip systems rely on several microfluidic paradigms. The first uses a fixed layout of continuous microfluidic channels. Such lab-on-a-chip systems are almost always application specific and far from a true "laboratory." The second involves electrowetting droplet movement (digital microfluidics), and allows two-dimensional computer control of fluidic transport and mixing. The merging of the two paradigms in the form of programmable electrowetting channels takes advantage of both the "continuous" functionality of rigid channels based on which a large number of applications have been developed to date and the "programmable" functionality of digital microfluidics that permits electrical control of on-chip functions. In this work, we demonstrate for the first time programmable formation of virtual microfluidic channels and their continuous operation with pressure driven flows using an electrowetting platform. Experimental, theoretical, and numerical analyses of virtual channel formation with biologically relevant electrolyte solutions and electrically-programmable reconfiguration are presented. We demonstrate that the "wall-less" virtual channels can be formed reliably and rapidly, with propagation rates of 3.5-3.8 mm s(-1). Pressure driven transport in these virtual channels at flow rates up to 100 μL min(-1) is achievable without distortion of the channel shape. We further demonstrate that these virtual channels can be switched on-demand between multiple inputs and outputs. Ultimately, we envision a platform that would provide rapid prototyping of microfluidic concepts and would be capable of a vast library of functions and benefitting applications from clinical diagnostics in resource-limited environments to rapid system prototyping to high throughput pharmaceutical applications.

A Low-Power High-Speed Smart Sensor Design for Space Exploration Missions

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi

1997-01-01

A low-power high-speed smart sensor system based on a large format active pixel sensor (APS) integrated with a programmable neural processor for space exploration missions is presented. The concept of building an advanced smart sensing system is demonstrated by a system-level microchip design that is composed with an APS sensor, a programmable neural processor, and an embedded microprocessor in a SOI CMOS technology. This ultra-fast smart sensor system-on-a-chip design mimics what is inherent in biological vision systems. Moreover, it is programmable and capable of performing ultra-fast machine vision processing in all levels such as image acquisition, image fusion, image analysis, scene interpretation, and control functions. The system provides about one tera-operation-per-second computing power which is a two order-of-magnitude increase over that of state-of-the-art microcomputers. Its high performance is due to massively parallel computing structures, high data throughput rates, fast learning capabilities, and advanced VLSI system-on-a-chip implementation.

Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study.

PubMed

Rodríguez, Manuel; Magdaleno, Eduardo; Pérez, Fernando; García, Cristhian

2017-03-28

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation.

Automated Software Acceleration in Programmable Logic for an Efficient NFFT Algorithm Implementation: A Case Study

PubMed Central

Rodríguez, Manuel; Magdaleno, Eduardo; Pérez, Fernando; García, Cristhian

2017-01-01

Non-equispaced Fast Fourier transform (NFFT) is a very important algorithm in several technological and scientific areas such as synthetic aperture radar, computational photography, medical imaging, telecommunications, seismic analysis and so on. However, its computation complexity is high. In this paper, we describe an efficient NFFT implementation with a hardware coprocessor using an All-Programmable System-on-Chip (APSoC). This is a hybrid device that employs an Advanced RISC Machine (ARM) as Processing System with Programmable Logic for high-performance digital signal processing through parallelism and pipeline techniques. The algorithm has been coded in C language with pragma directives to optimize the architecture of the system. We have used the very novel Software Develop System-on-Chip (SDSoC) evelopment tool that simplifies the interface and partitioning between hardware and software. This provides shorter development cycles and iterative improvements by exploring several architectures of the global system. The computational results shows that hardware acceleration significantly outperformed the software based implementation. PMID:28350358

Perspective: Fabrication of integrated organ-on-a-chip via bioprinting.

PubMed

Yang, Qingzhen; Lian, Qin; Xu, Feng

2017-05-01

Organ-on-a-chip has emerged as a powerful platform with widespread applications in biomedical engineering, such as pathology studies and drug screening. However, the fabrication of organ-on-a-chip is still a challenging task due to its complexity. For an integrated organ-on-a-chip, it may contain four key elements, i.e., a microfluidic chip, live cells/microtissues that are cultured in this chip, components for stimulus loading to mature the microtissues, and sensors for results readout. Recently, bioprinting has been used for fabricating organ-on-a-chip as it enables the printing of multiple materials, including biocompatible materials and even live cells in a programmable manner with a high spatial resolution. Besides, all four elements for organ-on-a-chip could be printed in a single continuous procedure on one printer; in other words, the fabrication process is assembly free. In this paper, we discuss the recent advances of organ-on-a-chip fabrication by bioprinting. Light is shed on the printing strategies, materials, and biocompatibility. In addition, some specific bioprinted organs-on-chips are analyzed in detail. Because the bioprinted organ-on-a-chip is still in its early stage, significant efforts are still needed. Thus, the challenges presented together with possible solutions and future trends are also discussed.

Lab-on-a-chip technologies for genodermatoses: Recent progress and future perspectives.

PubMed

Hongzhou, Cui; Shuping, Guo; Wenju, Wang; Li, Li; Lulu, Wei; Linjun, Deng; Jingmin, Li; Xiaoli, Ren; Li, Bai

2017-02-01

In recent years, molecular biology has proven to be a great asset in our understanding of mechanisms in genodermatoses. However, bench to bedside translation research lags far behind. Advances in lab-on-a-chip technologies enabled programmable, reconfigurable, and scalable manipulation of a variety of laboratory procedures. Sample preparation, microfluidic reactions, and continuous monitoring systems can be integrated on a small chip. These advantages have attracted attention in various fields of clinical application including diagnosis of inherited skin diseases. This review lists an overview of the underlying genes and mutations and describes prospective application of lab-on-a-chip technologies as solutions to challenges for point-of-care genodematoses diagnosis. Copyright © 2016. Published by Elsevier B.V.

Binary/Analog CCD Correlator Development.

DTIC Science & Technology

1981-07-01

architecture , design and performance of a general purpose, 1,024-stage, programmable transversal filter implemented in CCD/NMOS technology is described. The device features programmability of the reference signal, the filter length and weighting coefficient resolution. Off-ship circuitry is minimized by incorporating both analog and digital support circuitry, on-chip. This results in a monolithic analog signal processing system that has the flexibility to be operated in nine programmable configurations, from 1,024-stages by 1-bit, to 128-stages by 8-bits. The versatility

A Digitally Programmable Cytomorphic Chip for Simulation of Arbitrary Biochemical Reaction Networks.

PubMed

Woo, Sung Sik; Kim, Jaewook; Sarpeshkar, Rahul

2018-04-01

Prior work has shown that compact analog circuits can faithfully represent and model fundamental biomolecular circuits via efficient log-domain cytomorphic transistor equivalents. Such circuits have emphasized basis functions that are dominant in genetic transcription and translation networks and deoxyribonucleic acid (DNA)-protein binding. Here, we report a system featuring digitally programmable 0.35 μm BiCMOS analog cytomorphic chips that enable arbitrary biochemical reaction networks to be exactly represented thus enabling compact and easy composition of protein networks as well. Since all biomolecular networks can be represented as chemical reaction networks, our protein networks also include the former genetic network circuits as a special case. The cytomorphic analog protein circuits use one fundamental association-dissociation-degradation building-block circuit that can be configured digitally to exactly represent any zeroth-, first-, and second-order reaction including loading, dynamics, nonlinearity, and interactions with other building-block circuits. To address a divergence issue caused by random variations in chip fabrication processes, we propose a unique way of performing computation based on total variables and conservation laws, which we instantiate at both the circuit and network levels. Thus, scalable systems that operate with finite error over infinite time can be built. We show how the building-block circuits can be composed to form various network topologies, such as cascade, fan-out, fan-in, loop, dimerization, or arbitrary networks using total variables. We demonstrate results from a system that combines interacting cytomorphic chips to simulate a cancer pathway and a glycolysis pathway. Both simulations are consistent with conventional software simulations. Our highly parallel digitally programmable analog cytomorphic systems can lead to a useful design, analysis, and simulation tool for studying arbitrary large-scale biological networks in systems and synthetic biology.

A digital pixel cell for address event representation image convolution processing

NASA Astrophysics Data System (ADS)

Camunas-Mesa, Luis; Acosta-Jimenez, Antonio; Serrano-Gotarredona, Teresa; Linares-Barranco, Bernabe

2005-06-01

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows for real-time virtual massive connectivity between huge number of neurons located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate events according to their information levels. Neurons with more information (activity, derivative of activities, contrast, motion, edges,...) generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. AER technology has been used and reported for the implementation of various type of image sensors or retinae: luminance with local agc, contrast retinae, motion retinae,... Also, there has been a proposal for realizing programmable kernel image convolution chips. Such convolution chips would contain an array of pixels that perform weighted addition of events. Once a pixel has added sufficient event contributions to reach a fixed threshold, the pixel fires an event, which is then routed out of the chip for further processing. Such convolution chips have been proposed to be implemented using pulsed current mode mixed analog and digital circuit techniques. In this paper we present a fully digital pixel implementation to perform the weighted additions and fire the events. This way, for a given technology, there is a fully digital implementation reference against which compare the mixed signal implementations. We have designed, implemented and tested a fully digital AER convolution pixel. This pixel will be used to implement a full AER convolution chip for programmable kernel image convolution processing.

Fundamental Studies on Aluminum Fuels

DTIC Science & Technology

1944-12-01

Isooctr.no 200 C. Additives in the Syster. Aluminum Dilaur- r.te Cyclohexp.ne 201 2. Metathesis (Double Decomposition ) of Aluminum So^pc -ith...changes of hydrolysis -ire reduced (p»47). It has a sharp melting point (p. 88) and x-r:ty diffraotion pattern (p.71 ) and upon partial...of decomposition products. (In the same «ay as by distillation an acaotrope is often produoed and has a constant boiling point). It muat be noted

Screw-actuated displacement micropumps for thermoplastic microfluidics.

PubMed

Han, J Y; Rahmanian, O D; Kendall, E L; Fleming, N; DeVoe, D L

2016-10-05

The fabrication of on-chip displacement pumps integrated into thermoplastic chips is explored as a simple and low cost method for achieving precise and programmable flow control for disposable microfluidic systems. The displacement pumps consist of stainless steel screws inserted into threaded ports machined into a thermoplastic substrate which also serve as on-chip reagent storage reservoirs. Three different methods for pump sealing are investigated to enable high pressure flows without leakage, and software-defined control of multiple pumps is demonstrated in a self-contained platform using a compact and self-contained microcontroller for operation. Using this system, flow rates ranging from 0.5-40 μl min -1 are demonstrated. The pumps are combined with on-chip burst valves to fully seal multiple reagents into fabricated chips while providing on-demand fluid distribution in a downstream microfluidic network, and demonstrated for the generation of size-tunable water-in-oil emulsions.

A photonic chip based frequency discriminator for a high performance microwave photonic link.

PubMed

Marpaung, David; Roeloffzen, Chris; Leinse, Arne; Hoekman, Marcel

2010-12-20

We report a high performance phase modulation direct detection microwave photonic link employing a photonic chip as a frequency discriminator. The photonic chip consists of five optical ring resonators (ORRs) which are fully programmable using thermo-optical tuning. In this discriminator a drop-port response of an ORR is cascaded with a through response of another ORR to yield a linear phase modulation (PM) to intensity modulation (IM) conversion. The balanced photonic link employing the PM to IM conversion exhibits high second-order and third-order input intercept points of + 46 dBm and + 36 dBm, respectively, which are simultaneously achieved at one bias point.

A 0.5 cm(3) four-channel 1.1 mW wireless biosignal interface with 20 m range.

PubMed

Morrison, Tim; Nagaraju, Manohar; Winslow, Brent; Bernard, Amy; Otis, Brian P

2014-02-01

This paper presents a self-contained, single-chip biosignal monitoring system with wireless programmability and telemetry interface suitable for mainstream healthcare applications. The system consists of low-noise front end amplifiers, ADC, MICS/ISM transmitter and infrared programming capability to configure the state of the chip. An on-chip packetizer ensures easy pairing with standard off-the-shelf receivers. The chip is realized in the IBM 130 nm CMOS process with an area of 2×2 mm(2). The entire system consumes 1.07 mW from a 1.2 V supply. It weighs 0.6 g including a zinc-air battery. The system has been extensively tested in in vivo biological experiments and requires minimal human interaction or calibration.

Reconfigurable lattice mesh designs for programmable photonic processors.

PubMed

Pérez, Daniel; Gasulla, Ivana; Capmany, José; Soref, Richard A

2016-05-30

We propose and analyse two novel mesh design geometries for the implementation of tunable optical cores in programmable photonic processors. These geometries are the hexagonal and the triangular lattice. They are compared here to a previously proposed square mesh topology in terms of a series of figures of merit that account for metrics that are relevant to on-chip integration of the mesh. We find that that the hexagonal mesh is the most suitable option of the three considered for the implementation of the reconfigurable optical core in the programmable processor.

A programmable microsystem using system-on-chip for real-time biotelemetry.

PubMed

Wang, Lei; Johannessen, Erik A; Hammond, Paul A; Cui, Li; Reid, Stuart W J; Cooper, Jonathan M; Cumming, David R S

2005-07-01

A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm x 5 mm silicon chip using a 0.6 microm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm x 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10(-3) using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power.

Radiation hard programmable delay line for LHCb calorimeter upgrade

NASA Astrophysics Data System (ADS)

Mauricio, J.; Gascón, D.; Vilasís, X.; Picatoste, E.; Machefert, F.; Lefrancois, J.; Duarte, O.; Beigbeder, C.

2014-01-01

This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) in order to shift the phase of the LHC clock (25 ns) in steps of 1ns, with less than 5 ps jitter and 23 ps of DNL. The delay lines will be integrated into ICECAL, the LHCb calorimeter front-end analog signal processing ASIC in the near future. The stringent noise requirements on the ASIC imply minimizing the noise contribution of digital components. This is accomplished by implementing the DLL in differential mode. To achieve the required radiation tolerance several techniques are applied: double guard rings between PMOS and NMOS transistors as well as glitch suppressors and TMR Registers. This 5.7 mm2 chip has been implemented in CMOS 0.35 μm technology.

A Novel Mu Rhythm-based Brain Computer Interface Design that uses a Programmable System on Chip.

PubMed

Joshi, Rohan; Saraswat, Prateek; Gajendran, Rudhram

2012-01-01

This paper describes the system design of a portable and economical mu rhythm based Brain Computer Interface which employs Cypress Semiconductors Programmable System on Chip (PSoC). By carrying out essential processing on the PSoC, the use of an extra computer is eliminated, resulting in considerable cost savings. Microsoft Visual Studio 2005 and PSoC Designer 5.01 are employed in developing the software for the system, the hardware being custom designed. In order to test the usability of the BCI, preliminary testing is carried out by training three subjects who were able to demonstrate control over their electroencephalogram by moving a cursor present at the center of the screen towards the indicated direction with an average accuracy greater than 70% and a bit communication rate of up to 7 bits/min.

A Novel Mu Rhythm-based Brain Computer Interface Design that uses a Programmable System on Chip

PubMed Central

Joshi, Rohan; Saraswat, Prateek; Gajendran, Rudhram

2012-01-01

This paper describes the system design of a portable and economical mu rhythm based Brain Computer Interface which employs Cypress Semiconductors Programmable System on Chip (PSoC). By carrying out essential processing on the PSoC, the use of an extra computer is eliminated, resulting in considerable cost savings. Microsoft Visual Studio 2005 and PSoC Designer 5.01 are employed in developing the software for the system, the hardware being custom designed. In order to test the usability of the BCI, preliminary testing is carried out by training three subjects who were able to demonstrate control over their electroencephalogram by moving a cursor present at the center of the screen towards the indicated direction with an average accuracy greater than 70% and a bit communication rate of up to 7 bits/min. PMID:23493871

VASP-4096: a very high performance programmable device for digital media processing applications

NASA Astrophysics Data System (ADS)

Krikelis, Argy

2001-03-01

Over the past few years, technology drivers for microprocessors have changed significantly. Media data delivery and processing--such as telecommunications, networking, video processing, speech recognition and 3D graphics--is increasing in importance and will soon dominate the processing cycles consumed in computer-based systems. This paper presents the architecture of the VASP-4096 processor. VASP-4096 provides high media performance with low energy consumption by integrating associative SIMD parallel processing with embedded microprocessor technology. The major innovations in the VASP-4096 is the integration of thousands of processing units in a single chip that are capable of support software programmable high-performance mathematical functions as well as abstract data processing. In addition to 4096 processing units, VASP-4096 integrates on a single chip a RISC controller that is an implementation of the SPARC architecture, 128 Kbytes of Data Memory, and I/O interfaces. The SIMD processing in VASP-4096 implements the ASProCore architecture, which is a proprietary implementation of SIMD processing, operates at 266 MHz with program instructions issued by the RISC controller. The device also integrates a 64-bit synchronous main memory interface operating at 133 MHz (double-data rate), and a 64- bit 66 MHz PCI interface. VASP-4096, compared with other processors architectures that support media processing, offers true performance scalability, support for deterministic and non-deterministic data processing on a single device, and software programmability that can be re- used in future chip generations.

Orientation-selective aVLSI spiking neurons.

PubMed

Liu, S C; Kramer, J; Indiveri, G; Delbrück, T; Burg, T; Douglas, R

2001-01-01

We describe a programmable multi-chip VLSI neuronal system that can be used for exploring spike-based information processing models. The system consists of a silicon retina, a PIC microcontroller, and a transceiver chip whose integrate-and-fire neurons are connected in a soft winner-take-all architecture. The circuit on this multi-neuron chip approximates a cortical microcircuit. The neurons can be configured for different computational properties by the virtual connections of a selected set of pixels on the silicon retina. The virtual wiring between the different chips is effected by an event-driven communication protocol that uses asynchronous digital pulses, similar to spikes in a neuronal system. We used the multi-chip spike-based system to synthesize orientation-tuned neurons using both a feedforward model and a feedback model. The performance of our analog hardware spiking model matched the experimental observations and digital simulations of continuous-valued neurons. The multi-chip VLSI system has advantages over computer neuronal models in that it is real-time, and the computational time does not scale with the size of the neuronal network.

CMOS array design automation techniques

NASA Technical Reports Server (NTRS)

Lombardi, T.; Feller, A.

1976-01-01

The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

Architectures for single-chip image computing

NASA Astrophysics Data System (ADS)

Gove, Robert J.

1992-04-01

This paper will focus on the architectures of VLSI programmable processing components for image computing applications. TI, the maker of industry-leading RISC, DSP, and graphics components, has developed an architecture for a new-generation of image processors capable of implementing a plurality of image, graphics, video, and audio computing functions. We will show that the use of a single-chip heterogeneous MIMD parallel architecture best suits this class of processors--those which will dominate the desktop multimedia, document imaging, computer graphics, and visualization systems of this decade.

77 FR 58473 - Minimum Technical Standards for Class II Gaming Systems and Equipment

Federal Register 2010, 2011, 2012, 2013, 2014

2012-09-21

... as printed advertising material that cannot be validated directly by a voucher system. Critical... on that component. EPROM. Erasable Programmable Read Only Memory--a non-volatile storage chip or...

Characterization of Nanomaterials Using Field Flow Fractionation and Single Particle Inductively Coupled Plasma Mass Spectrometery (FFF-ICP-MS and SP-ICP-MS): Scientific Operating Procedure SOP-C

DTIC Science & Technology

2015-04-01

monodisperse particles. ENPs in environmental samples will likely have much broader size distributions and thus FFF-ICP-MS was tested over a greater...Figure 6). Resolution is based on ICP-MS sensitivity, and will likely decrease as the difference in particle diameter decreases. Second, this...Alvarez. 2006. Antibacterial activity of fullerene water suspensions: Effects of preparation method and particle size. Environmental Science

Programmable Direct-Memory-Access Controller

NASA Technical Reports Server (NTRS)

Hendry, David F.

1990-01-01

Proposed programmable direct-memory-access controller (DMAC) operates with computer systems of 32000 series, which have 32-bit data buses and use addresses of 24 (or potentially 32) bits. Controller functions with or without help of central processing unit (CPU) and starts itself. Includes such advanced features as ability to compare two blocks of memory for equality and to search block of memory for specific value. Made as single very-large-scale integrated-circuit chip.

Integrated programmable photonic filter on the silicon-on-insulator platform.

PubMed

Liao, Shasha; Ding, Yunhong; Peucheret, Christophe; Yang, Ting; Dong, Jianji; Zhang, Xinliang

2014-12-29

We propose and demonstrate a silicon-on-insulator (SOI) on-chip programmable filter based on a four-tap finite impulse response structure. The photonic filter is programmable thanks to amplitude and phase modulation of each tap controlled by thermal heaters. We further demonstrate the tunability of the filter central wavelength, bandwidth and variable passband shape. The tuning range of the central wavelength is at least 42% of the free spectral range. The bandwidth tuning range is at least half of the free spectral range. Our scheme has distinct advantages of compactness, capability for integrating with electronics.

78 FR 75362 - Notice of Issuance of Final Determination Concerning Docave Computer Software

Federal Register 2010, 2011, 2012, 2013, 2014

2013-12-11

... in whole or in part of materials from another country or instrumentality, it has been substantially... programming of a foreign PROM (Programmable Read-Only Memory chip) in the United States substantially...

Lossless microwave photonic delay line using a ring resonator with an integrated semiconductor optical amplifier

NASA Astrophysics Data System (ADS)

Xie, Yiwei; Zhuang, Leimeng; Boller, Klaus-Jochen; Lowery, Arthur James

2017-06-01

Optical delay lines implemented in photonic integrated circuits (PICs) are essential for creating robust and low-cost optical signal processors on miniaturized chips. In particular, tunable delay lines enable a key feature of programmability for the on-chip processing functions. However, the previously investigated tunable delay lines are plagued by a severe drawback of delay-dependent loss due to the propagation loss in the constituent waveguides. In principle, a serial-connected amplifier can be used to compensate such losses or perform additional amplitude manipulation. However, this solution is generally unpractical as it introduces additional burden on chip area and power consumption, particularly for large-scale integrated PICs. Here, we report an integrated tunable delay line that overcomes the delay-dependent loss, and simultaneously allows for independent manipulation of group delay and amplitude responses. It uses a ring resonator with a tunable coupler and a semiconductor optical amplifier in the feedback path. A proof-of-concept device with a free spectral range of 11.5 GHz and a delay bandwidth in the order of 200 MHz is discussed in the context of microwave photonics and is experimentally demonstrated to be able to provide a lossless delay up to 1.1 to a 5 ns Gaussian pulse. The proposed device can be designed for different frequency scales with potential for applications across many other areas such as telecommunications, LIDAR, and spectroscopy, serving as a novel building block for creating chip-scale programmable optical signal processors.

A VLSI chip set for real time vector quantization of image sequences

NASA Technical Reports Server (NTRS)

Baker, Richard L.

1989-01-01

The architecture and implementation of a VLSI chip set that vector quantizes (VQ) image sequences in real time is described. The chip set forms a programmable Single-Instruction, Multiple-Data (SIMD) machine which can implement various vector quantization encoding structures. Its VQ codebook may contain unlimited number of codevectors, N, having dimension up to K = 64. Under a weighted least squared error criterion, the engine locates at video rates the best code vector in full-searched or large tree searched VQ codebooks. The ability to manipulate tree structured codebooks, coupled with parallelism and pipelining, permits searches in as short as O (log N) cycles. A full codebook search results in O(N) performance, compared to O(KN) for a Single-Instruction, Single-Data (SISD) machine. With this VLSI chip set, an entire video code can be built on a single board that permits realtime experimentation with very large codebooks.

Single board system for fuzzy inference

NASA Technical Reports Server (NTRS)

Symon, James R.; Watanabe, Hiroyuki

1991-01-01

The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.

System-Level Biochip for Impedance Sensing and Programmable Manipulation of Bladder Cancer Cells

PubMed Central

Chuang, Cheng-Hsin; Huang, Yao-Wei; Wu, Yao-Tung

2011-01-01

This paper develops a dielectrophoretic (DEP) chip with multi-layer electrodes and a micro-cavity array for programmable manipulations of cells and impedance measurement. The DEP chip consists of an ITO top electrode, flow chamber, middle electrode on an SU-8 surface, micro-cavity arrays of SU-8 and distributed electrodes at the bottom of the micro-cavity. Impedance sensing of single cells could be performed as follows: firstly, cells were trapped in a micro-cavity array by negative DEP force provided by top and middle electrodes; then, the impedance measurement for discrimination of different stage of bladder cancer cells was accomplished by the middle and bottom electrodes. After impedance sensing, the individual releasing of trapped cells was achieved by negative DEP force using the top and bottom electrodes in order to collect the identified cells once more. Both cell manipulations and impedance measurement had been integrated within a system controlled by a PC-based LabVIEW program. In the experiments, two different stages of bladder cancer cell lines (grade III: T24 and grade II: TSGH8301) were utilized for the demonstration of programmable manipulation and impedance sensing; as the results show, the lower-grade bladder cancer cells (TSGH8301) possess higher impedance than the higher-grade ones (T24). In general, the multi-step manipulations of cells can be easily programmed by controlling the electrical signal in our design, which provides an excellent platform technology for lab-on-a-chip (LOC) or a micro-total-analysis-system (Micro TAS). PMID:22346685

In situ synthesis of protein arrays.

PubMed

He, Mingyue; Stoevesandt, Oda; Taussig, Michael J

2008-02-01

In situ or on-chip protein array methods use cell free expression systems to produce proteins directly onto an immobilising surface from co-distributed or pre-arrayed DNA or RNA, enabling protein arrays to be created on demand. These methods address three issues in protein array technology: (i) efficient protein expression and availability, (ii) functional protein immobilisation and purification in a single step and (iii) protein on-chip stability over time. By simultaneously expressing and immobilising many proteins in parallel on the chip surface, the laborious and often costly processes of DNA cloning, expression and separate protein purification are avoided. Recently employed methods reviewed are PISA (protein in situ array) and NAPPA (nucleic acid programmable protein array) from DNA and puromycin-mediated immobilisation from mRNA.

Challenges and opportunities for translating medical microdevices: insights from the programmable bio-nano-chip

PubMed Central

McRae, Michael P; Simmons, Glennon; McDevitt, John T

2016-01-01

This perspective highlights the major challenges for the bioanalytical community, in particular the area of lab-on-a-chip sensors, as they relate to point-of-care diagnostics. There is a strong need for general-purpose and universal biosensing platforms that can perform multiplexed and multiclass assays on real-world clinical samples. However, the adoption of novel lab-on-a-chip/microfluidic devices has been slow as several key challenges remain for the translation of these new devices to clinical practice. A pipeline of promising medical microdevice technologies will be made possible by addressing the challenges of integration, failure to compete with cost and performance of existing technologies, requisite for new content, and regulatory approval and clinical adoption. PMID:27071710

VLSI architecture for a Reed-Solomon decoder

NASA Technical Reports Server (NTRS)

Hsu, In-Shek (Inventor); Truong, Trieu-Kie (Inventor)

1992-01-01

A basic single-chip building block for a Reed-Solomon (RS) decoder system is partitioned into a plurality of sections, the first of which consists of a plurality of syndrome subcells each of which contains identical standard-basis finite-field multipliers that are programmable between 10 and 8 bit operation. A desired number of basic building blocks may be assembled to provide a RS decoder of any syndrome subcell size that is programmable between 10 and 8 bit operation.

A wearable, low-power, health-monitoring instrumentation based on a Programmable System-on-Chip.

PubMed

Massot, Bertrand; Gehin, Claudine; Nocua, Ronald; Dittmar, Andre; McAdams, Eric

2009-01-01

Improvement in quality and efficiency of health and medicine, at home and in hospital, has become of paramount importance. The solution of this problem would require the continuous monitoring of several key patient parameters, including the assessment of autonomic nervous system (ANS) activity using non-invasive sensors, providing information for emotional, sensorial, cognitive and physiological analysis of the patient. Recent advances in embedded systems, microelectronics, sensors and wireless networking enable the design of wearable systems capable of such advanced health monitoring. The subject of this article is an ambulatory system comprising a small wrist device connected to several sensors for the detection of the autonomic nervous system activity. It affords monitoring of skin resistance, skin temperature and heart activity. It is also capable of recording the data on a removable media or sending it to computer via a wireless communication. The wrist device is based on a Programmable System-on-Chip (PSoC) from Cypress: PSoCs are mixed-signal arrays, with dynamic, configurable digital and analogical blocks and an 8-bit Microcontroller unit (MCU) core on a single chip. In this paper we present first of all the hardware and software architecture of the device, and then results obtained from initial experiments.

Application of programmable bio-nano-chip system for the quantitative detection of drugs of abuse in oral fluids.

PubMed

Christodoulides, Nicolaos; De La Garza, Richard; Simmons, Glennon W; McRae, Michael P; Wong, Jorge; Newton, Thomas F; Smith, Regina; Mahoney, James J; Hohenstein, Justin; Gomez, Sobeyda; Floriano, Pierre N; Talavera, Humberto; Sloan, Daniel J; Moody, David E; Andrenyak, David M; Kosten, Thomas R; Haque, Ahmed; McDevitt, John T

2015-08-01

There is currently a gap in on-site drug of abuse monitoring. Current detection methods involve invasive sampling of blood and urine specimens, or collection of oral fluid, followed by qualitative screening tests using immunochromatographic cartridges. While remote laboratories then may provide confirmation and quantitative assessment of a presumptive positive, this instrumentation is expensive and decoupled from the initial sampling making the current drug-screening program inefficient and costly. The authors applied a noninvasive oral fluid sampling approach integrated with the in-development chip-based Programmable bio-nano-chip (p-BNC) platform for the detection of drugs of abuse. The p-BNC assay methodology was applied for the detection of tetrahydrocannabinol, morphine, amphetamine, methamphetamine, cocaine, methadone and benzodiazepines, initially using spiked buffered samples and, ultimately, using oral fluid specimen collected from consented volunteers. Rapid (∼10min), sensitive detection (∼ng/mL) and quantitation of 12 drugs of abuse was demonstrated on the p-BNC platform. Furthermore, the system provided visibility to time-course of select drug and metabolite profiles in oral fluids; for the drug cocaine, three regions of slope were observed that, when combined with concentration measurements from this and prior impairment studies, information about cocaine-induced impairment may be revealed. This chip-based p-BNC detection modality has significant potential to be used in the future by law enforcement officers for roadside drug testing and to serve a variety of other settings, including outpatient and inpatient drug rehabilitation centers, emergency rooms, prisons, schools, and in the workplace. Copyright © 2015 Elsevier Ireland Ltd. All rights reserved.

Application of Programmable Bio-Nano-Chip System for the Quantitative Detection of Drugs of Abuse in Oral Fluids*

PubMed Central

Christodoulides, Nicolaos; De La Garza, Richard; Simmons, Glennon W.; McRae, Michael P.; Wong, Jorge; Newton, Thomas F.; Smith, Regina; Mahoney, James J.; Hohenstein, Justin; Gomez, Sobeyda; Floriano, Pierre N.; Talavera, Humberto; Sloan, Daniel J.; Moody, David E.; Andrenyak, David M.; Kosten, Thomas R.; Haque, Ahmed; McDevitt, John T.

2015-01-01

Objective There is currently a gap in on-site drug of abuse monitoring. Current detection methods involve invasive sampling of blood and urine specimens, or collection of oral fluid, followed by qualitative screening tests using immunochromatographic cartridges. While remote laboratories then may provide confirmation and quantitative assessment of a presumptive positive, this instrumentation is expensive and decoupled from the initial sampling making the current drug-screening program inefficient and costly. The authors applied a noninvasive oral fluid sampling approach integrated with the in-development chip-based Programmable Bio-Nano-Chip (p-BNC) platform for the detection of drugs of abuse. Method The p-BNC assay methodology was applied for the detection of tetrahydrocannabinol, morphine, amphetamine, methamphetamine, cocaine, methadone and benzodiazepines, initially using spiked buffered samples and, ultimately, using oral fluid specimen collected from consented volunteers. Results Rapid (~10 minutes), sensitive detection (~ng/ml) and quantitation of 12 drugs of abuse was demonstrated on the p-BNC platform. Furthermore, the system provided visibility to time-course of select drug and metabolite profiles in oral fluids; for the drug cocaine, three regions of slope were observed that, when combined with concentration measurements from this and prior impairment studies, information about cocaine-induced impairment may be revealed. Conclusions This chip-based p-BNC detection modality has significant potential to be used in the future by law enforcement officers for roadside drug testing and to serve a variety of other settings, including outpatient and inpatient drug rehabilitation centers, emergency rooms, prisons, schools, and in the workplace. PMID:26048639

Programmable bio-nano-chip system: a flexible point-of-care platform for bioscience and clinical measurements

PubMed Central

McRae, Michael. P.; Simmons, Glennon. W.; Wong, Jorge; Shadfan, Basil; Gopalkrishnan, Sanjiv; Christodoulides, Nicolaos

2015-01-01

The development of integrated instrumentation for universal bioassay systems serves as a key goal for the lab-on-a-chip community. The programmable bio-nano-chip (p-BNC) system is a versatile multiplexed and multiclass chemical- and bio-sensing system for bioscience and clinical measurements. The system is comprised of two main components, a disposable cartridge and a portable analyzer. The customizable single-use plastic cartridges, which now can be manufactured in high volumes using injection molding, are designed for analytical performance, ease of use, reproducibility, and low cost. These labcard devices implement high surface area nano-structured biomarker capture elements that enable high performance signaling and are index matched to real-world biological specimens. This detection modality, along with the convenience of on-chip fluid storage in blisters and self-contained waste, represents a standard process to digitize biological signatures at the point-of-care. A companion portable analyzer prototype has been developed to integrate fluid motivation, optical detection, and automated data analysis, and it serves as the human interface for complete assay automation. In this report, we provide a systems-level perspective of the p-BNC universal biosensing platform with an emphasis on flow control, device integration, and automation. To demonstrate the flexibility of the p-BNC, we distinguish diseased and non-case patients across three significant disease applications: prostate cancer, ovarian cancer, and acute myocardial infarction. Progress towards developing a rapid 7 minute myoglobin assay is presented using the fully automated p-BNC system. PMID:26308851

Artificial brains. A million spiking-neuron integrated circuit with a scalable communication network and interface.

PubMed

Merolla, Paul A; Arthur, John V; Alvarez-Icaza, Rodrigo; Cassidy, Andrew S; Sawada, Jun; Akopyan, Filipp; Jackson, Bryan L; Imam, Nabil; Guo, Chen; Nakamura, Yutaka; Brezzo, Bernard; Vo, Ivan; Esser, Steven K; Appuswamy, Rathinakumar; Taba, Brian; Amir, Arnon; Flickner, Myron D; Risk, William P; Manohar, Rajit; Modha, Dharmendra S

2014-08-08

Inspired by the brain's structure, we have developed an efficient, scalable, and flexible non-von Neumann architecture that leverages contemporary silicon technology. To demonstrate, we built a 5.4-billion-transistor chip with 4096 neurosynaptic cores interconnected via an intrachip network that integrates 1 million programmable spiking neurons and 256 million configurable synapses. Chips can be tiled in two dimensions via an interchip communication interface, seamlessly scaling the architecture to a cortexlike sheet of arbitrary size. The architecture is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification. With 400-pixel-by-240-pixel video input at 30 frames per second, the chip consumes 63 milliwatts. Copyright © 2014, American Association for the Advancement of Science.

Soft error evaluation and vulnerability analysis in Xilinx Zynq-7010 system-on chip

NASA Astrophysics Data System (ADS)

Du, Xuecheng; He, Chaohui; Liu, Shuhuan; Zhang, Yao; Li, Yonghong; Xiong, Ceng; Tan, Pengkang

2016-09-01

Radiation-induced soft errors are an increasingly important threat to the reliability of modern electronic systems. In order to evaluate system-on chip's reliability and soft error, the fault tree analysis method was used in this work. The system fault tree was constructed based on Xilinx Zynq-7010 All Programmable SoC. Moreover, the soft error rates of different components in Zynq-7010 SoC were tested by americium-241 alpha radiation source. Furthermore, some parameters that used to evaluate the system's reliability and safety were calculated using Isograph Reliability Workbench 11.0, such as failure rate, unavailability and mean time to failure (MTTF). According to fault tree analysis for system-on chip, the critical blocks and system reliability were evaluated through the qualitative and quantitative analysis.

Design of a Closed-Loop, Bidirectional Brain Machine Interface System With Energy Efficient Neural Feature Extraction and PID Control.

PubMed

Liu, Xilin; Zhang, Milin; Richardson, Andrew G; Lucas, Timothy H; Van der Spiegel, Jan

2017-08-01

This paper presents a bidirectional brain machine interface (BMI) microsystem designed for closed-loop neuroscience research, especially experiments in freely behaving animals. The system-on-chip (SoC) consists of 16-channel neural recording front-ends, neural feature extraction units, 16-channel programmable neural stimulator back-ends, in-channel programmable closed-loop controllers, global analog-digital converters (ADC), and peripheral circuits. The proposed neural feature extraction units includes 1) an ultra low-power neural energy extraction unit enabling a 64-step natural logarithmic domain frequency tuning, and 2) a current-mode action potential (AP) detection unit with time-amplitude window discriminator. A programmable proportional-integral-derivative (PID) controller has been integrated in each channel enabling a various of closed-loop operations. The implemented ADCs include a 10-bit voltage-mode successive approximation register (SAR) ADC for the digitization of the neural feature outputs and/or local field potential (LFP) outputs, and an 8-bit current-mode SAR ADC for the digitization of the action potential outputs. The multi-mode stimulator can be programmed to perform monopolar or bipolar, symmetrical or asymmetrical charge balanced stimulation with a maximum current of 4 mA in an arbitrary channel configuration. The chip has been fabricated in 0.18 μ m CMOS technology, occupying a silicon area of 3.7 mm 2 . The chip dissipates 56 μW/ch on average. General purpose low-power microcontroller with Bluetooth module are integrated in the system to provide wireless link and SoC configuration. Methods, circuit techniques and system topology proposed in this work can be used in a wide range of relevant neurophysiology research, especially closed-loop BMI experiments.

Programmable Bio-Nano-Chip Systems for Serum CA125 Quantification: Towards Ovarian Cancer Diagnostics at the Point-of-Care

PubMed Central

Raamanathan, Archana; Simmons, Glennon W.; Christodoulides, Nicolaos; Floriano, Pierre N.; Furmaga, Wieslaw B.; Redding, Spencer W.; Lu, Karen H.; Bast, Robert C.; McDevitt, John T.

2013-01-01

Point-of-care (POC) implementation of early detection and screening methodologies for ovarian cancer may enable improved survival rates through early intervention. Current laboratory-confined immunoanalyzers have long turnaround times and are often incompatible with multiplexing and POC implementation. Rapid, sensitive and multiplexable POC diagnostic platforms compatible with promising early detection approaches for ovarian cancer are needed. To this end, we report the adaptation of the programmable bio-nano-chip (p-BNC), an integrated, microfluidic, modular (Programmable) platform for CA125 serum quantitation, a biomarker prominently implicated in multi-modal and multi-marker screening approaches. In the p-BNC, CA125 from diseased sera (Bio) is sequestered and assessed with a fluorescence-based sandwich immunoassay, completed in the nano-nets (Nano) of sensitized agarose microbeads localized in individually addressable wells (Chip), housed in a microfluidic module, capable of integrating multiple sample, reagent and biowaste processing and handling steps. Antibody pairs that bind to distinct epitopes on CA125 were screened. To permit efficient biomarker sequestration in a 3-D microfluidic environment, the p-BNC operating variables (incubation times, flow rates and reagent concentrations) were tuned to deliver optimal analytical performance under 45 minutes. With short analysis times, competitive analytical performance (Inter- and intra-assay precision of 1.2% and 1.9% and LODs of 1.0 U/mL) was achieved on this mini-sensor ensemble. Further validation with sera of ovarian cancer patients (n=20) demonstrated excellent correlation (R2 = 0.97) with gold-standard ELISA. Building on the integration capabilities of novel microfluidic systems programmed for ovarian cancer, the rapid, precise and sensitive miniaturized p-BNC system shows strong promise for ovarian cancer diagnostics. PMID:22490510

Programmable bio-nano-chip systems for serum CA125 quantification: toward ovarian cancer diagnostics at the point-of-care.

PubMed

Raamanathan, Archana; Simmons, Glennon W; Christodoulides, Nicolaos; Floriano, Pierre N; Furmaga, Wieslaw B; Redding, Spencer W; Lu, Karen H; Bast, Robert C; McDevitt, John T

2012-05-01

Point-of-care (POC) implementation of early detection and screening methodologies for ovarian cancer may enable improved survival rates through early intervention. Current laboratory-confined immunoanalyzers have long turnaround times and are often incompatible with multiplexing and POC implementation. Rapid, sensitive, and multiplexable POC diagnostic platforms compatible with promising early detection approaches for ovarian cancer are needed. To this end, we report the adaptation of the programmable bio-nano-chip (p-BNC), an integrated, microfluidic, and modular (programmable) platform for CA125 serum quantitation, a biomarker prominently implicated in multimodal and multimarker screening approaches. In the p-BNCs, CA125 from diseased sera (Bio) is sequestered and assessed with a fluorescence-based sandwich immunoassay, completed in the nano-nets (Nano) of sensitized agarose microbeads localized in individually addressable wells (Chip), housed in a microfluidic module, capable of integrating multiple sample, reagent and biowaste processing, and handling steps. Antibody pairs that bind to distinct epitopes on CA125 were screened. To permit efficient biomarker sequestration in a three-dimensional microfluidic environment, the p-BNC operating variables (incubation times, flow rates, and reagent concentrations) were tuned to deliver optimal analytical performance under 45 minutes. With short analysis times, competitive analytical performance (inter- and intra-assay precision of 1.2% and 1.9% and limit of detection of 1.0 U/mL) was achieved on this minisensor ensemble. Furthermore, validation with sera of patients with ovarian cancer (n = 20) showed excellent correlation (R(2) = 0.97) with gold-standard ELISA. Building on the integration capabilities of novel microfluidic systems programmed for ovarian cancer, the rapid, precise, and sensitive miniaturized p-BNC system shows strong promise for ovarian cancer diagnostics.

Design of an MR image processing module on an FPGA chip

NASA Astrophysics Data System (ADS)

Li, Limin; Wyrwicz, Alice M.

2015-06-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments.

Design of an MR image processing module on an FPGA chip

PubMed Central

Li, Limin; Wyrwicz, Alice M.

2015-01-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments. PMID:25909646

Reconfigurable radio-frequency arbitrary waveforms synthesized in a silicon photonic chip.

PubMed

Wang, Jian; Shen, Hao; Fan, Li; Wu, Rui; Niu, Ben; Varghese, Leo T; Xuan, Yi; Leaird, Daniel E; Wang, Xi; Gan, Fuwan; Weiner, Andrew M; Qi, Minghao

2015-01-12

Photonic methods of radio-frequency waveform generation and processing can provide performance advantages and flexibility over electronic methods due to the ultrawide bandwidth offered by the optical carriers. However, bulk optics implementations suffer from the lack of integration and slow reconfiguration speed. Here we propose an architecture of integrated photonic radio-frequency generation and processing and implement it on a silicon chip fabricated in a semiconductor manufacturing foundry. Our device can generate programmable radio-frequency bursts or continuous waveforms with only the light source, electrical drives/controls and detectors being off-chip. It modulates an individual pulse in a radio-frequency burst within 4 ns, achieving a reconfiguration speed three orders of magnitude faster than thermal tuning. The on-chip optical delay elements offer an integrated approach to accurately manipulating individual radio-frequency waveform features without constraints set by the speed and timing jitter of electronics, and should find applications ranging from high-speed wireless to defence electronics.

Reconfigurable radio-frequency arbitrary waveforms synthesized in a silicon photonic chip

PubMed Central

Wang, Jian; Shen, Hao; Fan, Li; Wu, Rui; Niu, Ben; Varghese, Leo T.; Xuan, Yi; Leaird, Daniel E.; Wang, Xi; Gan, Fuwan; Weiner, Andrew M.; Qi, Minghao

2015-01-01

Photonic methods of radio-frequency waveform generation and processing can provide performance advantages and flexibility over electronic methods due to the ultrawide bandwidth offered by the optical carriers. However, bulk optics implementations suffer from the lack of integration and slow reconfiguration speed. Here we propose an architecture of integrated photonic radio-frequency generation and processing and implement it on a silicon chip fabricated in a semiconductor manufacturing foundry. Our device can generate programmable radio-frequency bursts or continuous waveforms with only the light source, electrical drives/controls and detectors being off-chip. It modulates an individual pulse in a radio-frequency burst within 4 ns, achieving a reconfiguration speed three orders of magnitude faster than thermal tuning. The on-chip optical delay elements offer an integrated approach to accurately manipulating individual radio-frequency waveform features without constraints set by the speed and timing jitter of electronics, and should find applications ranging from high-speed wireless to defence electronics. PMID:25581847

A Robust Strategy for Total Ionizing Dose Testing of Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Wilcox, Edward; Berg, Melanie; Friendlich, Mark; Lakeman, Joseph; KIm, Hak; Pellish, Jonathan; LaBel, Kenneth

2012-01-01

We present a novel method of FPGA TID testing that measures propagation delay between flip-flops operating at maximum speed. Measurement is performed on-chip at-speed and provides a key design metric when building system-critical synchronous designs.

Multi-GHz Synchronous Waveform Acquisition With Real-Time Pattern-Matching Trigger Generation

NASA Astrophysics Data System (ADS)

Kleinfelder, Stuart A.; Chiang, Shiuh-hua Wood; Huang, Wei

2013-10-01

A transient waveform capture and digitization circuit with continuous synchronous 2-GHz sampling capability and real-time programmable windowed trigger generation has been fabricated and tested. Designed in 0.25 μm CMOS, the digitizer contains a circular array of 128 sample and hold circuits for continuous sample acquisition, and attains 2-GHz sample speeds with over 800-MHz analog bandwidth. Sample clock generation is synchronous, combining a phase-locked loop for high-speed clock generation and a high-speed fully-differential shift register for distributing clocks to all 128 sample circuits. Using two comparators per sample, the sampled voltage levels are compared against two reference levels, a high threshold and a low threshold, that are set via per-comparator digital to analog converters (DACs). The 256 per-comparator 5-bit DACs compensate for comparator offsets and allow for fine reference level adjustment. The comparator results are matched in 8-sample-wide windows against up to 72 programmable patterns in real time using an on-chip programmable logic array. Each 8-sample trigger window is equivalent to 4 ns of acquisition, overlapped sample by sample in a circular fashion through the entire 128-sample array. The 72 pattern-matching trigger criteria can be programmed to be any combination of High-above the high threshold, Low-below the low threshold, Middle-between the two thresholds, or “Don't Care”-any state is accepted. A trigger pattern of “HLHLHLHL,” for example, watches for a waveform that is oscillating at about 1 GHz given the 2-GHz sample rate. A trigger is flagged in under 20 ns if there is a match, after which sampling is stopped, and on-chip digitization can proceed via 128 parallel 10-bit converters, or off-chip conversion can proceed via an analog readout. The chip exceeds 11 bits of dynamic range, nets over 800-MHz -3-dB bandwidth in a realistic system, and jitter in the PLL-based sampling clock has been measured to be about 1 part per million, RMS.

Programmable Nano-Bio-Chip Sensors: Analytical Meets Clinical

PubMed Central

Jokerst, Jesse V.; Floriano, Pierre N.; Christodoulides, Nicolaos; McDevitt, John T.; Jacobson, James W.; Bhagwandin, Bryon D.

2010-01-01

synopsis There have been many recent advances in the nano-bio-chip (NBC) analysis methodology with implications for a number of high-morbidity diseases including HIV, cancer, and heart disease. In their Feature article, Jesse V. Jokerst of The University of Texas at Austin; Pierre N. Floriano, Nicolaos Christodoulides, and John T. McDevitt of Rice University; and James W. Jacobson and Bryon D. Bhagwandin of LabNow, Inc. discuss the construction, capabilities, and advantages of NBCs. The cover shows arrays of NBCs. Images courtesy of Glennon Simmons/McDevitt Lab and Marcha Miller of The University of Texas at Austin. PMID:20128622

Design of the ANTARES LCM-DAQ board test bench using a FPGA-based system-on-chip approach

NASA Astrophysics Data System (ADS)

Anvar, S.; Kestener, P.; Le Provost, H.

2006-11-01

The System-on-Chip (SoC) approach consists in using state-of-the-art FPGA devices with embedded RISC processor cores, high-speed differential LVDS links and ready-to-use multi-gigabit transceivers allowing development of compact systems with substantial number of IO channels. Required performances are obtained through a subtle separation of tasks between closely cooperating programmable hardware logic and user-friendly software environment. We report about our experience in using the SoC approach for designing the production test bench of the off-shore readout system for the ANTARES neutrino experiment.

A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics†

PubMed Central

Muluneh, Melaku

2015-01-01

In recent years there has been great progress harnessing the small-feature size and programmability of integrated circuits (ICs) for biological applications, by building microfluidics directly on top of ICs. However, a major hurdle to the further development of this technology is the inherent size-mismatch between ICs (~mm) and microfluidic chips (~cm). Increasing the area of the ICs to match the size of the microfluidic chip, as has often been done in previous studies, leads to a waste of valuable space on the IC and an increase in fabrication cost (>100×). To address this challenge, we have developed a three dimensional PDMS chip that can straddle multiple length scales of hybrid IC/microfluidic chips. This approach allows millimeter-scale ICs, with no post-processing, to be integrated into a centimeter-sized PDMS chip. To fabricate this PDMS chip we use a combination of soft-lithography and laser micromachining. Soft lithography was used to define micrometer-scale fluid channels directly on the surface of the IC, allowing fluid to be controlled with high accuracy and brought into close proximity to sensors for highly sensitive measurements. Laser micromachining was used to create ~50 μm vias to connect these molded PDMS channels to a larger PDMS chip, which can connect multiple ICs and house fluid connections to the outside world. To demonstrate the utility of this approach, we built and demonstrated an in-flow magnetic cytometer that consisted of a 5 × 5 cm2 microfluidic chip that incorporated a commercial 565 × 1145 μm2 IC with a GMR sensing circuit. We additionally demonstrated the modularity of this approach by building a chip that incorporated two of these GMR chips connected in series. PMID:25284502

A multi-scale PDMS fabrication strategy to bridge the size mismatch between integrated circuits and microfluidics.

PubMed

Muluneh, Melaku; Issadore, David

2014-12-07

In recent years there has been great progress harnessing the small-feature size and programmability of integrated circuits (ICs) for biological applications, by building microfluidics directly on top of ICs. However, a major hurdle to the further development of this technology is the inherent size-mismatch between ICs (~mm) and microfluidic chips (~cm). Increasing the area of the ICs to match the size of the microfluidic chip, as has often been done in previous studies, leads to a waste of valuable space on the IC and an increase in fabrication cost (>100×). To address this challenge, we have developed a three dimensional PDMS chip that can straddle multiple length scales of hybrid IC/microfluidic chips. This approach allows millimeter-scale ICs, with no post-processing, to be integrated into a centimeter-sized PDMS chip. To fabricate this PDMS chip we use a combination of soft-lithography and laser micromachining. Soft lithography was used to define micrometer-scale fluid channels directly on the surface of the IC, allowing fluid to be controlled with high accuracy and brought into close proximity to sensors for highly sensitive measurements. Laser micromachining was used to create ~50 μm vias to connect these molded PDMS channels to a larger PDMS chip, which can connect multiple ICs and house fluid connections to the outside world. To demonstrate the utility of this approach, we built and demonstrated an in-flow magnetic cytometer that consisted of a 5 × 5 cm(2) microfluidic chip that incorporated a commercial 565 × 1145 μm(2) IC with a GMR sensing circuit. We additionally demonstrated the modularity of this approach by building a chip that incorporated two of these GMR chips connected in series.

Membrane lateral compressibility determined by NMR and x-ray diffraction: effect of acyl chain polyunsaturation.

PubMed Central

Koenig, B W; Strey, H H; Gawrisch, K

1997-01-01

The elastic area compressibility modulus, Ka, of lamellar liquid crystalline bilayers was determined by a new experimental approach using 2H-NMR order parameters of lipid hydrocarbon chains together with lamellar repeat spacings measured by x-ray diffraction. The combination of NMR and x-ray techniques yields accurate determination of lateral area per lipid molecule. Samples of saturated, monounsaturated, and polyunsaturated phospholipids were equilibrated with polyethylene glycol (PEG) 20,000 solutions in water at concentrations from 0 to 55 wt % PEG at 30 degrees C. This procedure is equivalent to applying 0 to 8 dyn/cm lateral pressure to the bilayers. The resulting reductions in area per lipid were measured with a resolution of +/-0.2 A2 and the fractional area decrease was proportional to applied lateral pressure. For 1,2-dimyristoyl(d54)-sn-glycero-3-phosphocholine, 1-stearoyl(d35)-2-oleoyl-sn-glycero-3-phosphocholine (SOPC-d35), and 1-stearoyl(d35)-2-docosahexaenoyl-sn-glycero-3-phosphocholine (SDPC-d35) cross-sectional areas per molecule in excess water of 59.5, 61.4, and 69.2 A2 and bilayer elastic area compressibility moduli of 141, 221, and 121 dyn/cm were determined, respectively. Combining NMR and x-ray results enables the determination of compressibility differences between saturated and unsaturated hydrocarbon chains. In mixed-chain SOPC-d35 both chains have similar compressibility moduli; however, in mixed-chain polyunsaturated SDPC-d35, the saturated stearic acid chain appears to be far less compressible than the polyunsaturated docosahexaenoic acid chain. Images FIGURE 3 FIGURE 5 PMID:9336191

On-chip wavelength multiplexed detection of cancer DNA biomarkers in blood

PubMed Central

Cai, H.; Stott, M. A.; Ozcelik, D.; Parks, J. W.; Hawkins, A. R.; Schmidt, H.

2016-01-01

We have developed an optofluidic analysis system that processes biomolecular samples starting from whole blood and then analyzes and identifies multiple targets on a silicon-based molecular detection platform. We demonstrate blood filtration, sample extraction, target enrichment, and fluorescent labeling using programmable microfluidic circuits. We detect and identify multiple targets using a spectral multiplexing technique based on wavelength-dependent multi-spot excitation on an antiresonant reflecting optical waveguide chip. Specifically, we extract two types of melanoma biomarkers, mutated cell-free nucleic acids —BRAFV600E and NRAS, from whole blood. We detect and identify these two targets simultaneously using the spectral multiplexing approach with up to a 96% success rate. These results point the way toward a full front-to-back chip-based optofluidic compact system for high-performance analysis of complex biological samples. PMID:28058082

A new VLSI architecture for a single-chip-type Reed-Solomon decoder

NASA Technical Reports Server (NTRS)

Hsu, I. S.; Truong, T. K.

1989-01-01

A new very large scale integration (VLSI) architecture for implementing Reed-Solomon (RS) decoders that can correct both errors and erasures is described. This new architecture implements a Reed-Solomon decoder by using replication of a single VLSI chip. It is anticipated that this single chip type RS decoder approach will save substantial development and production costs. It is estimated that reduction in cost by a factor of four is possible with this new architecture. Furthermore, this Reed-Solomon decoder is programmable between 8 bit and 10 bit symbol sizes. Therefore, both an 8 bit Consultative Committee for Space Data Systems (CCSDS) RS decoder and a 10 bit decoder are obtained at the same time, and when concatenated with a (15,1/6) Viterbi decoder, provide an additional 2.1-dB coding gain.

Programmable architecture for pixel level processing tasks in lightweight strapdown IR seekers

NASA Astrophysics Data System (ADS)

Coates, James L.

1993-06-01

Typical processing tasks associated with missile IR seeker applications are described, and a straw man suite of algorithms is presented. A fully programmable multiprocessor architecture is realized on a multimedia video processor (MVP) developed by Texas Instruments. The MVP combines the elements of RISC, floating point, advanced DSPs, graphics processors, display and acquisition control, RAM, and external memory. Front end pixel level tasks typical of missile interceptor applications, operating on 256 x 256 sensor imagery, can be processed at frame rates exceeding 100 Hz in a single MVP chip.

[The improved design of table operating box of digital subtraction angiography device].

PubMed

Qi, Xianying; Zhang, Minghai; Han, Fengtan; Tang, Feng; He, Lemin

2009-12-01

In this paper are analyzed the disadvantages of CGO-3000 digital subtraction angiography table Operating Box. The authors put forward a communication control scheme between single-chip microcomputer(SCM) and programmable logic controller(PLC). The details of hardware and software of communication are given.

Integrated imaging sensor systems with CMOS active pixel sensor technology

NASA Technical Reports Server (NTRS)

Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

2002-01-01

This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

78 FR 21387 - Notice of Issuance of Final Determination Concerning Printer and Fax Machine

Federal Register 2010, 2011, 2012, 2013, 2014

2013-04-10

... in part of materials from another country or instrumentality, it has been substantially transformed... loading the firmware onto the print engine. In determining whether the combining of parts or materials... foreign Programmable Read Only Memory Chip (``PROM'') in the United States substantially transformed the...

77 FR 34964 - Notice of Issuance of Final Determination Concerning Toshiba E-Studio Multi-Function Peripherals

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-12

... in part of materials from another country or instrumentality, it has been substantially transformed... the combining of parts or materials constitutes a substantial transformation, the determinative issue... States), the programming of a foreign PROM (Programmable Read-Only Memory chip) in the United States...

MAP3D: a media processor approach for high-end 3D graphics

NASA Astrophysics Data System (ADS)

Darsa, Lucia; Stadnicki, Steven; Basoglu, Chris

1999-12-01

Equator Technologies, Inc. has used a software-first approach to produce several programmable and advanced VLIW processor architectures that have the flexibility to run both traditional systems tasks and an array of media-rich applications. For example, Equator's MAP1000A is the world's fastest single-chip programmable signal and image processor targeted for digital consumer and office automation markets. The Equator MAP3D is a proposal for the architecture of the next generation of the Equator MAP family. The MAP3D is designed to achieve high-end 3D performance and a variety of customizable special effects by combining special graphics features with high performance floating-point and media processor architecture. As a programmable media processor, it offers the advantages of a completely configurable 3D pipeline--allowing developers to experiment with different algorithms and to tailor their pipeline to achieve the highest performance for a particular application. With the support of Equator's advanced C compiler and toolkit, MAP3D programs can be written in a high-level language. This allows the compiler to successfully find and exploit any parallelism in a programmer's code, thus decreasing the time to market of a given applications. The ability to run an operating system makes it possible to run concurrent applications in the MAP3D chip, such as video decoding while executing the 3D pipelines, so that integration of applications is easily achieved--using real-time decoded imagery for texturing 3D objects, for instance. This novel architecture enables an affordable, integrated solution for high performance 3D graphics.

FPGA implementation of ICA algorithm for blind signal separation and adaptive noise canceling.

PubMed

Kim, Chang-Min; Park, Hyung-Min; Kim, Taesu; Choi, Yoon-Kyung; Lee, Soo-Young

2003-01-01

An field programmable gate array (FPGA) implementation of independent component analysis (ICA) algorithm is reported for blind signal separation (BSS) and adaptive noise canceling (ANC) in real time. In order to provide enormous computing power for ICA-based algorithms with multipath reverberation, a special digital processor is designed and implemented in FPGA. The chip design fully utilizes modular concept and several chips may be put together for complex applications with a large number of noise sources. Experimental results with a fabricated test board are reported for ANC only, BSS only, and simultaneous ANC/BSS, which demonstrates successful speech enhancement in real environments in real time.

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

NASA Astrophysics Data System (ADS)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

The Level 0 Pixel Trigger system for the ALICE experiment

NASA Astrophysics Data System (ADS)

Aglieri Rinella, G.; Kluge, A.; Krivda, M.; ALICE Silicon Pixel Detector project

2007-01-01

The ALICE Silicon Pixel Detector contains 1200 readout chips. Fast-OR signals indicate the presence of at least one hit in the 8192 pixel matrix of each chip. The 1200 bits are transmitted every 100 ns on 120 data readout optical links using the G-Link protocol. The Pixel Trigger System extracts and processes them to deliver an input signal to the Level 0 trigger processor targeting a latency of 800 ns. The system is compact, modular and based on FPGA devices. The architecture allows the user to define and implement various trigger algorithms. The system uses advanced 12-channel parallel optical fiber modules operating at 1310 nm as optical receivers and 12 deserializer chips closely packed in small area receiver boards. Alternative solutions with multi-channel G-Link deserializers implemented directly in programmable hardware devices were investigated. The design of the system and the progress of the ALICE Pixel Trigger project are described in this paper.

Evaluation of a Programmable Voltage-Controlled MEMS Oscillator, Type SiT3701, Over a Wide Temperature Range

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2009-01-01

Semiconductor chips based on MEMS (Micro-Electro-Mechanical Systems) technology, such as sensors, transducers, and actuators, are becoming widely used in today s electronics due to their high performance, low power consumption, tolerance to shock and vibration, and immunity to electro-static discharge. In addition, the MEMS fabrication process allows for the miniaturization of individual chips as well as the integration of various electronic circuits into one module, such as system-on-a-chip. These measures would simplify overall system design, reduce parts count and interface, improve reliability, and reduce cost; and they would meet requirements of systems destined for use in space exploration missions. In this work, the performance of a recently-developed MEMS voltage-controlled oscillator was evaluated under a wide temperature range. Operation of this new commercial-off-the-shelf (COTS) device was also assessed under thermal cycling to address some operational conditions of the space environment

Bioprinting of 3D Convoluted Renal Proximal Tubules on Perfusable Chips

NASA Astrophysics Data System (ADS)

Homan, Kimberly A.; Kolesky, David B.; Skylar-Scott, Mark A.; Herrmann, Jessica; Obuobi, Humphrey; Moisan, Annie; Lewis, Jennifer A.

2016-10-01

Three-dimensional models of kidney tissue that recapitulate human responses are needed for drug screening, disease modeling, and, ultimately, kidney organ engineering. Here, we report a bioprinting method for creating 3D human renal proximal tubules in vitro that are fully embedded within an extracellular matrix and housed in perfusable tissue chips, allowing them to be maintained for greater than two months. Their convoluted tubular architecture is circumscribed by proximal tubule epithelial cells and actively perfused through the open lumen. These engineered 3D proximal tubules on chip exhibit significantly enhanced epithelial morphology and functional properties relative to the same cells grown on 2D controls with or without perfusion. Upon introducing the nephrotoxin, Cyclosporine A, the epithelial barrier is disrupted in a dose-dependent manner. Our bioprinting method provides a new route for programmably fabricating advanced human kidney tissue models on demand.

A monolithic integrated photonic microwave filter

NASA Astrophysics Data System (ADS)

Fandiño, Javier S.; Muñoz, Pascual; Doménech, David; Capmany, José

2017-02-01

Meeting the increasing demand for capacity in wireless networks requires the harnessing of higher regions in the radiofrequency spectrum, reducing cell size, as well as more compact, agile and power-efficient base stations that are capable of smoothly interfacing the radio and fibre segments. Fully functional microwave photonic chips are promising candidates in attempts to meet these goals. In recent years, many integrated microwave photonic chips have been reported in different technologies. To the best of our knowledge, none has monolithically integrated all the main active and passive optoelectronic components. Here, we report the first demonstration of a tunable microwave photonics filter that is monolithically integrated into an indium phosphide chip. The reconfigurable radiofrequency photonic filter includes all the necessary elements (for example, lasers, modulators and photodetectors), and its response can be tuned by means of control electric currents. This is an important step in demonstrating the feasibility of integrated and programmable microwave photonic processors.

Prototyping the HPDP Chip on STM 65 NM Process

NASA Astrophysics Data System (ADS)

Papadas, C.; Dramitinos, G.; Syed, M.; Helfers, T.; Dedes, G.; Schoellkopf, J.-P.; Dugoujon, L.

2011-08-01

Currently Astrium GmbH is involved in the of the High Performance Data Processor (HPDP) development programme for telecommunication applications under a DLR contract. The HPDP project targets the implementation of the commercially available reconfigurable array processor IP (XPP from the company PACT XPP Technologies) in a radiation hardened technology.In the current complementary development phase funded under the Greek Industry Incentive scheme, it is planned to prototype the HPDP chip in commercial STM 65 nm technology. In addition it is also planned to utilise the preliminary radiation hardened components of this library wherever possible.This abstract gives an overview of the HPDP chip architecture, the basic details of the STM 65 nm process and the design flow foreseen for the prototyping. The paper will discuss the development and integration issues involved in using the STM 65 nm process (also including the available preliminary radiation hardened components) for designs targeted to be used in space applications.

Bioprinting of 3D Convoluted Renal Proximal Tubules on Perfusable Chips

PubMed Central

Homan, Kimberly A.; Kolesky, David B.; Skylar-Scott, Mark A.; Herrmann, Jessica; Obuobi, Humphrey; Moisan, Annie; Lewis, Jennifer A.

2016-01-01

Three-dimensional models of kidney tissue that recapitulate human responses are needed for drug screening, disease modeling, and, ultimately, kidney organ engineering. Here, we report a bioprinting method for creating 3D human renal proximal tubules in vitro that are fully embedded within an extracellular matrix and housed in perfusable tissue chips, allowing them to be maintained for greater than two months. Their convoluted tubular architecture is circumscribed by proximal tubule epithelial cells and actively perfused through the open lumen. These engineered 3D proximal tubules on chip exhibit significantly enhanced epithelial morphology and functional properties relative to the same cells grown on 2D controls with or without perfusion. Upon introducing the nephrotoxin, Cyclosporine A, the epithelial barrier is disrupted in a dose-dependent manner. Our bioprinting method provides a new route for programmably fabricating advanced human kidney tissue models on demand. PMID:27725720

A dry-cooled AC quantum voltmeter

NASA Astrophysics Data System (ADS)

Schubert, M.; Starkloff, M.; Peiselt, K.; Anders, S.; Knipper, R.; Lee, J.; Behr, R.; Palafox, L.; Böck, A. C.; Schaidhammer, L.; Fleischmann, P. M.; Meyer, H.-G.

2016-10-01

The paper describes a dry-cooled AC quantum voltmeter system operated up to kilohertz frequencies and 7 V rms. A 10 V programmable Josephson voltage standard (PJVS) array was installed on a pulse tube cooler (PTC) driven with a 4 kW air-cooled compressor. The operating margins at 70 GHz frequencies were investigated in detail and found to exceed 1 mA Shapiro step width. A key factor for the successful chip operation was the low on-chip power consumption of 65 mW in total. A thermal interface between PJVS chip and PTC cold stage was used to avoid a significant chip overheating. By installing the cryocooled PJVS array into an AC quantum voltmeter setup, several calibration measurements of dc standards and calibrator ac voltages up to 2 kHz frequencies were carried out to demonstrate the full functionality. The results are discussed and compared to systems with standard liquid helium cooling. For dc voltages, a direct comparison measurement between the dry-cooled AC quantum voltmeter and a liquid-helium based 10 V PJVS shows an agreement better than 1 part in 1010.

Design of an MR image processing module on an FPGA chip.

PubMed

Li, Limin; Wyrwicz, Alice M

2015-06-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128×128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments. Copyright © 2015 Elsevier Inc. All rights reserved.

76 FR 4713 - Notice of Issuance of Final Determination Concerning the Engenio 7900 Storage System

Federal Register 2010, 2011, 2012, 2013, 2014

2011-01-26

... article which consists in whole or in part of materials from another country or instrumentality, it has... foreign PROM (Programmable Read-Only Memory chip) in the United States substantially transformed the PROM... creating a similar pattern. In determining whether the combining of parts or materials constitutes a...

Compact sub-nanosecond pulse seed source with diode laser driven by a high-speed circuit

NASA Astrophysics Data System (ADS)

Wang, Xiaoqian; Wang, Bo; Wang, Junhua; Cheng, Wenyong

2018-06-01

A compact sub-nanosecond pulse seed source with 1550 nm diode laser (DL) was obtained by employing a high-speed circuit. The circuit mainly consisted of a short pulse generator and a short pulse driver. The short pulse generator, making up of a complex programmable logic device (CPLD), a level translator, two programmable delay chips and an AND gate chip, output a triggering signal to control metal-oxide-semiconductor field-effect transistor (MOSFET) switch of the short pulse driver. The MOSFET switch with fast rising time and falling time both shorter than 1 ns drove the DL to emit short optical pulses. Performances of the pulse seed source were tested. The results showed that continuously adjustable repetition frequency ranging from 500 kHz to 100 MHz and pulse duration in the range of 538 ps to 10 ns were obtained, respectively. 537 μW output was obtained at the highest repetition frequency of 100 MHz with the shortest pulse duration of 538 ps. These seed pulses were injected into an fiber amplifier, and no optical pulse distortions were found.

FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

NASA Astrophysics Data System (ADS)

Alexanian, H.; Appelquist, G.; Bailly, P.; Benetta, R.; Berglund, S.; Bezamat, J.; Blouzon, F.; Bohm, C.; Breveglieri, L.; Brigati, S.; Cattaneo, P. W.; Dadda, L.; David, J.; Engström, M.; Genat, J. F.; Givoletti, M.; Goggi, V. G.; Gong, S.; Grieco, G. M.; Hansen, M.; Hentzell, H.; Holmberg, T.; Höglund, I.; Inkinen, S. J.; Kerek, A.; Landi, C.; Ledortz, O.; Lippi, M.; Lofstedt, B.; Lund-Jensen, B.; Maloberti, F.; Mutz, S.; Nayman, P.; Piuri, V.; Polesello, G.; Sami, M.; Savoy-Navarro, A.; Schwemling, P.; Stefanelli, R.; Sundblad, R.; Svensson, C.; Torelli, G.; Vanuxem, J. P.; Yamdagni, N.; Yuan, J.; Ödmark, A.; Fermi Collaboration

1995-02-01

We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed {A}/{D} converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design.

Design of transient light signal simulator based on FPGA

NASA Astrophysics Data System (ADS)

Kang, Jing; Chen, Rong-li; Wang, Hong

2014-11-01

A design scheme of transient light signal simulator based on Field Programmable gate Array (FPGA) was proposed in this paper. Based on the characteristics of transient light signals and measured feature points of optical intensity signals, a fitted curve was created in MATLAB. And then the wave data was stored in a programmed memory chip AT29C1024 by using SUPERPRO programmer. The control logic was realized inside one EP3C16 FPGA chip. Data readout, data stream cache and a constant current buck regulator for powering high-brightness LEDs were all controlled by FPGA. A 12-Bit multiplying CMOS digital-to-analog converter (DAC) DAC7545 and an amplifier OPA277 were used to convert digital signals to voltage signals. A voltage-controlled current source constituted by a NPN transistor and an operational amplifier controlled LED array diming to achieve simulation of transient light signal. LM3405A, 1A Constant Current Buck Regulator for Powering LEDs, was used to simulate strong background signal in space. Experimental results showed that the scheme as a transient light signal simulator can satisfy the requests of the design stably.

Universal lab-on-a-chip platform for complex, perfused 3D cell cultures

NASA Astrophysics Data System (ADS)

Sonntag, F.; Schmieder, F.; Ströbel, J.; Grünzner, S.; Busek, M.; Günther, K.; Steege, T.; Polk, C.; Klotzbach, U.

2016-03-01

The miniaturization, rapid prototyping and automation of lab-on-a-chip technology play nowadays a very important role. Lab-on-a-chip technology is successfully implemented not only for environmental analysis and medical diagnostics, but also as replacement of animals used for the testing of substances in the pharmaceutical and cosmetics industries. For that purpose the Fraunhofer IWS and partners developed a lab-on-a-chip platform for perfused cell-based assays in the last years, which includes different micropumps, valves, channels, reservoirs and customized cell culture modules. This technology is already implemented for the characterization of different human cell cultures and organoids, like skin, liver, endothelium, hair follicle and nephron. The advanced universal lab-on-a-chip platform for complex, perfused 3D cell cultures is divided into a multilayer basic chip with integrated micropump and application-specific 3D printed cell culture modules. Moreover a technology for surface modification of the printed cell culture modules by laser micro structuring and a complex and flexibly programmable controlling device based on an embedded Linux system was developed. A universal lab-on-a-chip platform with an optional oxygenator and a cell culture module for cubic scaffolds as well as first cell culture experiments within the cell culture device will be presented. The module is designed for direct interaction with robotic dispenser systems. This offers the opportunity to combine direct organ printing of cells and scaffolds with the microfluidic cell culture module. The characterization of the developed system was done by means of Micro-Particle Image Velocimetry (μPIV) and an optical oxygen measuring system.

All optical programmable logic array (PLA)

NASA Astrophysics Data System (ADS)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual mode input-output ports and programmable network interfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Khare, Surhud; Somasekhar, Dinesh; More, Ankit

Described is an apparatus which comprises: a Network-On-Chip fabric using crossbar switches, having distributed ingress and egress ports; and a dual-mode network interface coupled to at least one crossbar switch, the dual-mode network interface is to include: a dual-mode circuitry; a controller operable to: configure the dual-mode circuitry to transmit and receive differential signals via the egress and ingress ports, respectively, and configure the dual-mode circuitry to transmit and receive signal-ended signals via the egress and ingress ports, respectively.

A 1024×768-12μm Digital ROIC for uncooled microbolometer FPAs

NASA Astrophysics Data System (ADS)

Eminoglu, Selim

2017-02-01

This paper reports the development of a new digital microbolometer Readout Integrated Circuit (D-ROIC), called MT10212BD. It has a format of 1024 × 768 (XGA) and a pixel pitch of 12μm. MT10212BD is Mikro Tasarim's second 12μm pitch microbolometer ROIC, which is developed specifically for surface micro machined microbolometer detector arrays with small pixel pitch using high-TCR pixel materials, such as VOx and a Si. MT10212BD has an alldigital system on-chip architecture, which generates programmable timing and biasing, and performs 14-bit analog to digital conversion (ADC). The signal processing chain in the ROIC is composed of pixel bias circuitry, integrator based programmable gain amplifier followed by column parallel ADC circuitry. MT10212BD has a serial programming interface that can be used to configure the programmable ROIC features and to load the Non-Uniformity-Correction (NUC) date to the ROIC. MT10212BD has a total of 8 high-speed serial digital video outputs, which can be programmed to operate in the 2, 4, and 8-output modes and can support frames rates above 60 fps. The high-speed serial digital outputs supports data rates as high as 400 Mega-bits/s, when operated at 50 MHz system clock frequency. There is an on-chip phase-locked-loop (PLL) based timing circuitry to generate the high speed clocks used in the ROIC. The ROIC is designed to support pixel resistance values ranging from 30KΩ to 90kΩ, with a nominal value of 60KΩ. The ROIC has a globally programmable gain in the column readout, which can be adjusted based on the detector resistance value.

VLSI single-chip (255,223) Reed-Solomon encoder with interleaver

NASA Technical Reports Server (NTRS)

Hsu, In-Shek (Inventor); Deutsch, Leslie J. (Inventor); Truong, Trieu-Kie (Inventor); Reed, Irving S. (Inventor)

1990-01-01

The invention relates to a concatenated Reed-Solomon/convolutional encoding system consisting of a Reed-Solomon outer code and a convolutional inner code for downlink telemetry in space missions, and more particularly to a Reed-Solomon encoder with programmable interleaving of the information symbols and code correction symbols to combat error bursts in the Viterbi decoder.

77 FR 43104 - Notice of Issuance of Final Determination Concerning Certain Devices Known as “Pwn Plugs”

Federal Register 2010, 2011, 2012, 2013, 2014

2012-07-23

..., or (ii) in the case of an article which consists in whole or in part of materials from another... programming of a foreign PROM (Programmable Read-Only Memory chip) in the United States substantially... Plugs. ``The term `character' is defined as `one of the essentials of structure, form, materials, or...

The Department of Defense Very High Speed Integrated Circuit (VHSIC) Technology Availability Program Plan for the Committees on Armed Services United States Congress.

DTIC Science & Technology

1986-06-30

features of computer aided design systems and statistical quality control procedures that are generic to chip sets and processes. RADIATION HARDNESS -The...System PSP Programmable Signal Processor SSI Small Scale Integration ." TOW Tube Launched, Optically Tracked, Wire Guided TTL Transistor Transitor Logic

Unraveling Quantum Annealers using Classical Hardness

PubMed Central

Martin-Mayor, Victor; Hen, Itay

2015-01-01

Recent advances in quantum technology have led to the development and manufacturing of experimental programmable quantum annealing optimizers that contain hundreds of quantum bits. These optimizers, commonly referred to as ‘D-Wave’ chips, promise to solve practical optimization problems potentially faster than conventional ‘classical’ computers. Attempts to quantify the quantum nature of these chips have been met with both excitement and skepticism but have also brought up numerous fundamental questions pertaining to the distinguishability of experimental quantum annealers from their classical thermal counterparts. Inspired by recent results in spin-glass theory that recognize ‘temperature chaos’ as the underlying mechanism responsible for the computational intractability of hard optimization problems, we devise a general method to quantify the performance of quantum annealers on optimization problems suffering from varying degrees of temperature chaos: A superior performance of quantum annealers over classical algorithms on these may allude to the role that quantum effects play in providing speedup. We utilize our method to experimentally study the D-Wave Two chip on different temperature-chaotic problems and find, surprisingly, that its performance scales unfavorably as compared to several analogous classical algorithms. We detect, quantify and discuss several purely classical effects that possibly mask the quantum behavior of the chip. PMID:26483257

Microfluidic integration of parallel solid-phase liquid chromatography.

PubMed

Huft, Jens; Haynes, Charles A; Hansen, Carl L

2013-03-05

We report the development of a fully integrated microfluidic chromatography system based on a recently developed column geometry that allows for robust packing of high-performance separation columns in poly(dimethylsiloxane) microfluidic devices having integrated valves made by multilayer soft lithography (MSL). The combination of parallel high-performance separation columns and on-chip plumbing was used to achieve a fully integrated system for on-chip chromatography, including all steps of automated sample loading, programmable gradient generation, separation, fluorescent detection, and sample recovery. We demonstrate this system in the separation of fluorescently labeled DNA and parallel purification of reverse transcription polymerase chain reaction (RT-PCR) amplified variable regions of mouse immunoglobulin genes using a strong anion exchange (AEX) resin. Parallel sample recovery in an immiscible oil stream offers the advantage of low sample dilution and high recovery rates. The ability to perform nucleic acid size selection and recovery on subnanogram samples of DNA holds promise for on-chip genomics applications including sequencing library preparation, cloning, and sample fractionation for diagnostics.

A silicon central pattern generator controls locomotion in vivo.

PubMed

Vogelstein, R J; Tenore, F; Guevremont, L; Etienne-Cummings, R; Mushahwar, V K

2008-09-01

We present a neuromorphic silicon chip that emulates the activity of the biological spinal central pattern generator (CPG) and creates locomotor patterns to support walking. The chip implements ten integrate-and-fire silicon neurons and 190 programmable digital-to-analog converters that act as synapses. This architecture allows for each neuron to make synaptic connections to any of the other neurons as well as to any of eight external input signals and one tonic bias input. The chip's functionality is confirmed by a series of experiments in which it controls the motor output of a paralyzed animal in real-time and enables it to walk along a three-meter platform. The walking is controlled under closed-loop conditions with the aide of sensory feedback that is recorded from the animal's legs and fed into the silicon CPG. Although we and others have previously described biomimetic silicon locomotor control systems for robots, this is the first demonstration of a neuromorphic device that can replace some functions of the central nervous system in vivo.

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

PubMed

Feng, Lichen; Li, Zunchao; Wang, Yuanfa

2018-02-01

Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

Integrated bioassays in microfluidic devices: botulinum toxin assays.

PubMed

Mangru, Shakuntala; Bentz, Bryan L; Davis, Timothy J; Desai, Nitin; Stabile, Paul J; Schmidt, James J; Millard, Charles B; Bavari, Sina; Kodukula, Krishna

2005-12-01

A microfluidic assay was developed for screening botulinum neurotoxin serotype A (BoNT-A) by using a fluorescent resonance energy transfer (FRET) assay. Molded silicone microdevices with integral valves, pumps, and reagent reservoirs were designed and fabricated. Electrical and pneumatic control hardware were constructed, and software was written to automate the assay protocol and data acquisition. Detection was accomplished by fluorescence microscopy. The system was validated with a peptide inhibitor, running 2 parallel assays, as a feasibility demonstration. The small footprint of each bioreactor cell (0.5 cm2) and scalable fluidic architecture enabled many parallel assays on a single chip. The chip is programmable to run a dilution series in each lane, generating concentration-response data for multiple inhibitors. The assay results showed good agreement with the corresponding experiments done at a macroscale level. Although the system has been developed for BoNT-A screening, a wide variety of assays can be performed on the microfluidic chip with little or no modification.

Programmable optical processor chips: toward photonic RF filters with DSP-level flexibility and MHz-band selectivity

NASA Astrophysics Data System (ADS)

Xie, Yiwei; Geng, Zihan; Zhuang, Leimeng; Burla, Maurizio; Taddei, Caterina; Hoekman, Marcel; Leinse, Arne; Roeloffzen, Chris G. H.; Boller, Klaus-J.; Lowery, Arthur J.

2017-12-01

Integrated optical signal processors have been identified as a powerful engine for optical processing of microwave signals. They enable wideband and stable signal processing operations on miniaturized chips with ultimate control precision. As a promising application, such processors enables photonic implementations of reconfigurable radio frequency (RF) filters with wide design flexibility, large bandwidth, and high-frequency selectivity. This is a key technology for photonic-assisted RF front ends that opens a path to overcoming the bandwidth limitation of current digital electronics. Here, the recent progress of integrated optical signal processors for implementing such RF filters is reviewed. We highlight the use of a low-loss, high-index-contrast stoichiometric silicon nitride waveguide which promises to serve as a practical material platform for realizing high-performance optical signal processors and points toward photonic RF filters with digital signal processing (DSP)-level flexibility, hundreds-GHz bandwidth, MHz-band frequency selectivity, and full system integration on a chip scale.

The Panda Strip Asic: Pasta

NASA Astrophysics Data System (ADS)

Lai, A.

2018-01-01

PASTA is the 64 channel front-end chip, designed in a 110 nm CMOS technology to read out the strip sensors of the Micro Vertex Detector (MVD) of the PANDA experiment. This chip provides high resolution timestamp and deposited charge information by means of the time-over-threshold technique. Its working principle is based on a predecessor, the TOFPET ASIC, that was designed for medical applications. A general restructuring of the architecture was needed, in order to meet the specific requirements imposed by the physics programme of PANDA, especially in terms of radiation tolerance, spatial constraints, and readout in absence of a first level hardware trigger. The first revision of PASTA is currently under evaluation at the Forschungszentrum Jülich, where a data acquisition system dedicated to the MVD prototypes has been developed. This paper describes the main aspect of the chip design, gives an overview of the data acquisition system used for the verification, and shows the first results regarding the performance of PASTA.

Versatile all-digital time interval measuring system

NASA Astrophysics Data System (ADS)

Vyhlidal, David; Cech, Miroslav

2011-06-01

This paper describes a design and performance of a versatile all-digital time interval measuring system. The measurement method is based on an interpolation principle. In this principle the time interval is first roughly digitized by a coarse counter driven by a high stability reference clock and the fractions between the clock periods are measured by two Time-to-Digital Converter chips TDC-GPX manufactured by Acam messelectronic. Control circuits allow programmable customization of the system to satisfy many applications such as laser range finding, event counting, or time-of-flight measurements in various physics experiments. The system has two reference clocks inputs and two independent channels for measuring start and stop events. Only one 40 MHz reference is required for the measurement. The second reference can be, for example, 1 PPS (Pulse per Second) signal from a GPS (Global Positioning System) to time tag events. Time intervals are measured using the highest resolution mode of the TDC-GPX chips. The resolution of each chip is software programmable and is PLL (Phase Locked Loop) stabilized against temperature and voltage variations. The system can achieve a timing resolution better than 15 ps rms with up to 90 kHz repetition rate. The time interval measurement range is from 0 ps up to 1 second. The power consumption of the whole system is 18 W including an embedded computer board and an LCD (Liquid Crystal Display) screen. The embedded computer controls the whole system, collects and evaluates measurement data and with the display provides a user interface. The system is implemented using commercially available components.

An integrated circuit with transmit beamforming flip-chip bonded to a 2-D CMUT array for 3-D ultrasound imaging.

PubMed

Wygant, Ira O; Jamal, Nafis S; Lee, Hyunjoo J; Nikoozadeh, Amin; Oralkan, Omer; Karaman, Mustafa; Khuri-Yakub, Butrus T

2009-10-01

State-of-the-art 3-D medical ultrasound imaging requires transmitting and receiving ultrasound using a 2-D array of ultrasound transducers with hundreds or thousands of elements. A tight combination of the transducer array with integrated circuitry eliminates bulky cables connecting the elements of the transducer array to a separate system of electronics. Furthermore, preamplifiers located close to the array can lead to improved receive sensitivity. A combined IC and transducer array can lead to a portable, high-performance, and inexpensive 3-D ultrasound imaging system. This paper presents an IC flip-chip bonded to a 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array for 3-D ultrasound imaging. The IC includes a transmit beamformer that generates 25-V unipolar pulses with programmable focusing delays to 224 of the 256 transducer elements. One-shot circuits allow adjustment of the pulse widths for different ultrasound transducer center frequencies. For receiving reflected ultrasound signals, the IC uses the 32-elements along the array diagonals. The IC provides each receiving element with a low-noise 25-MHz-bandwidth transimpedance amplifier. Using a field-programmable gate array (FPGA) clocked at 100 MHz to operate the IC, the IC generated properly timed transmit pulses with 5-ns accuracy. With the IC flip-chip bonded to a CMUT array, we show that the IC can produce steered and focused ultrasound beams. We present 2-D and 3-D images of a wire phantom and 2-D orthogonal cross-sectional images (Bscans) of a latex heart phantom.

A wide-range programmable frequency synthesizer based on a finite state machine filter

NASA Astrophysics Data System (ADS)

Alser, Mohammed H.; Assaad, Maher M.; Hussin, Fawnizu A.

2013-11-01

In this article, an FPGA-based design and implementation of a fully digital wide-range programmable frequency synthesizer based on a finite state machine filter is presented. The advantages of the proposed architecture are that, it simultaneously generates a high frequency signal from a low frequency reference signal (i.e. synthesising), and synchronising the two signals (signals have the same phase, or a constant difference) without jitter accumulation issue. The architecture is portable and can be easily implemented for various platforms, such as FPGAs and integrated circuits. The frequency synthesizer circuit can be used as a part of SERDES devices in intra/inter chip communication in system-on-chip (SoC). The proposed circuit is designed using Verilog language and synthesized for the Altera DE2-70 development board, with the Cyclone II (EP2C35F672C6) device on board. Simulation and experimental results are included; they prove the synthesizing and tracking features of the proposed architecture. The generated clock signal frequency of a range from 19.8 MHz to 440 MHz is synchronized to the input reference clock with a frequency step of 0.12 MHz.

Dynamically programmable cache

NASA Astrophysics Data System (ADS)

Nakkar, Mouna; Harding, John A.; Schwartz, David A.; Franzon, Paul D.; Conte, Thomas

1998-10-01

Reconfigurable machines have recently been used as co- processors to accelerate the execution of certain algorithms or program subroutines. The problems with the above approach include high reconfiguration time and limited partial reconfiguration. By far the most critical problems are: (1) the small on-chip memory which results in slower execution time, and (2) small FPGA areas that cannot implement large subroutines. Dynamically Programmable Cache (DPC) is a novel architecture for embedded processors which offers solutions to the above problems. To solve memory access problems, DPC processors merge reconfigurable arrays with the data cache at various cache levels to create a multi-level reconfigurable machines. As a result DPC machines have both higher data accessibility and FPGA memory bandwidth. To solve the limited FPGA resource problem, DPC processors implemented multi-context switching (Virtualization) concept. Virtualization allows implementation of large subroutines with fewer FPGA cells. Additionally, DPC processors can parallelize the execution of several operations resulting in faster execution time. In this paper, the speedup improvement for DPC machines are shown to be 5X faster than an Altera FLEX10K FPGA chip and 2X faster than a Sun Ultral SPARC station for two different algorithms (convolution and motion estimation).

Evaluation of the uncertainties in the TLD radiosurgery postal dose system

NASA Astrophysics Data System (ADS)

Campos, L. T.; Leite, S. P.; de Almeida, C. E. V.; Magalhães, L. A. G.

2018-03-01

Stereotactic radiosurgery is a single-fraction radiation therapy procedure for treating intracranial lesions using a stereotactic apparatus and multiple narrow beams delivered through noncoplanar isocentric arcs. To guarantee a high quality standard, a comprehensive Quality Assurance programme is extremely important to ensure that the measured dose is consistent with the tolerance considered to improve treatment quality. The Radiological Science Laboratory operates a postal audit programme in SRT and SRS. The purpose of the programme is to verify the target localization accuracy in known geometry and the dosimetric conditions of the TPS. The programme works in such a way those thermoluminescence dosimeters, consisting of LiF chips, are sent to the centre where they are to be irradiated to a certain dose. The TLD are then returned, where they are evaluated and the absorbed dose is obtained from TLDs readings. The aim of the present work is estimate the uncertainties in the process of dose determination, using experimental data.

Programming Cell Adhesion for On-Chip Sequential Boolean Logic Functions.

PubMed

Qu, Xiangmeng; Wang, Shaopeng; Ge, Zhilei; Wang, Jianbang; Yao, Guangbao; Li, Jiang; Zuo, Xiaolei; Shi, Jiye; Song, Shiping; Wang, Lihua; Li, Li; Pei, Hao; Fan, Chunhai

2017-08-02

Programmable remodelling of cell surfaces enables high-precision regulation of cell behavior. In this work, we developed in vitro constructed DNA-based chemical reaction networks (CRNs) to program on-chip cell adhesion. We found that the RGD-functionalized DNA CRNs are entirely noninvasive when interfaced with the fluidic mosaic membrane of living cells. DNA toehold with different lengths could tunably alter the release kinetics of cells, which shows rapid release in minutes with the use of a 6-base toehold. We further demonstrated the realization of Boolean logic functions by using DNA strand displacement reactions, which include multi-input and sequential cell logic gates (AND, OR, XOR, and AND-OR). This study provides a highly generic tool for self-organization of biological systems.

Application of resist-profile-aware source optimization in 28 nm full chip optical proximity correction

NASA Astrophysics Data System (ADS)

Zhu, Jun; Zhang, David Wei; Kuo, Chinte; Wang, Qing; Wei, Fang; Zhang, Chenming; Chen, Han; He, Daquan; Hsu, Stephen D.

2017-07-01

As technology node shrinks, aggressive design rules for contact and other back end of line (BEOL) layers continue to drive the need for more effective full chip patterning optimization. Resist top loss is one of the major challenges for 28 nm and below technology nodes, which can lead to post-etch hotspots that are difficult to predict and eventually degrade the process window significantly. To tackle this problem, we used an advanced programmable illuminator (FlexRay) and Tachyon SMO (Source Mask Optimization) platform to make resistaware source optimization possible, and it is proved to greatly improve the imaging contrast, enhance focus and exposure latitude, and minimize resist top loss thus improving the yield.

A new electrowetting lab-on-a-chip platform based on programmable and virtual wall-less channels

NASA Astrophysics Data System (ADS)

Banerjee, Ananda; Kreit, Eric; Dhindsa, Manjeet; Heikenfeld, Jason; Papautsky, Ian

2011-02-01

Microscale liquid handling based on electrowetting has been previously demonstrated by several groups. Such liquid manipulation however is limited to control of individual droplets, aptly termed digital microfluidics. The inability to form continuous channels thus prevents conventional microfluidic sample manipulation and analysis approaches, such as electroosmosis and electrophoresis. In this paper, we discuss our recent progress on the development of electrowettingbased virtual channels. These channels can be created and reconfigured on-demand and preserve their shape without external stimulus. We also discuss recent progress towards demonstrating electroosmotic flows in such microchannels for fluid transport. This would permit a variety of basic functionalities in this new platform including sample transport and mixing between various functional areas of the chip.

Programmable synaptic devices for electronic neural nets

NASA Technical Reports Server (NTRS)

Moopenn, A.; Thakoor, A. P.

1990-01-01

The architecture, design, and operational characteristics of custom VLSI and thin film synaptic devices are described. The devices include CMOS-based synaptic chips containing 1024 reprogrammable synapses with a 6-bit dynamic range, and nonvolatile, write-once, binary synaptic arrays based on memory switching in hydrogenated amorphous silicon films. Their suitability for embodiment of fully parallel and analog neural hardware is discussed. Specifically, a neural network solution to an assignment problem of combinatorial global optimization, implemented in fully parallel hardware using the synaptic chips, is described. The network's ability to provide optimal and near optimal solutions over a time scale of few neuron time constants has been demonstrated and suggests a speedup improvement of several orders of magnitude over conventional search methods.

On-chip programmable ultra-wideband microwave photonic phase shifter and true time delay unit.

PubMed

Burla, Maurizio; Cortés, Luis Romero; Li, Ming; Wang, Xu; Chrostowski, Lukas; Azaña, José

2014-11-01

We proposed and experimentally demonstrated an ultra-broadband on-chip microwave photonic processor that can operate both as RF phase shifter (PS) and true-time-delay (TTD) line, with continuous tuning. The processor is based on a silicon dual-phase-shifted waveguide Bragg grating (DPS-WBG) realized with a CMOS compatible process. We experimentally demonstrated the generation of delay up to 19.4 ps over 10 GHz instantaneous bandwidth and a phase shift of approximately 160° over the bandwidth 22-29 GHz. The available RF measurement setup ultimately limits the phase shifting demonstration as the device is capable of providing up to 300° phase shift for RF frequencies over a record bandwidth approaching 1 THz.

Single chip lidar with discrete beam steering by digital micromirror device.

PubMed

Smith, Braden; Hellman, Brandon; Gin, Adley; Espinoza, Alonzo; Takashima, Yuzuru

2017-06-26

A novel method of beam steering enables a large field of view and reliable single chip light detection and ranging (lidar) by utilizing a mass-produced digital micromirror device (DMD). Using a short pulsed laser, the micromirrors' rotation is frozen in mid-transition, which forms a programmable blazed grating. The blazed grating efficiently redistributes the light to a single diffraction order, among several. We demonstrated time of flight measurements for five discrete angles using this beam steering method with a nano second 905nm laser and Si avalanche diode. A distance accuracy of < 1 cm over a 1 m distance range, a 48° full field of view, and a measurement rate of 3.34k points/s is demonstrated.

A Low-Cost CMOS Programmable Temperature Switch

PubMed Central

Li, Yunlong; Wu, Nanjian

2008-01-01

A novel uncalibrated CMOS programmable temperature switch with high temperature accuracy is presented. Its threshold temperature Tth can be programmed by adjusting the ratios of width and length of the transistors. The operating principles of the temperature switch circuit is theoretically explained. A floating gate neural MOS circuit is designed to compensate automatically the threshold temperature Tth variation that results form the process tolerance. The switch circuit is implemented in a standard 0.35 μm CMOS process. The temperature switch can be programmed to perform the switch operation at 16 different threshold temperature Tths from 45—120°C with a 5°C increment. The measurement shows a good consistency in the threshold temperatures. The chip core area is 0.04 mm2 and power consumption is 3.1 μA at 3.3V power supply. The advantages of the temperature switch are low power consumption, the programmable threshold temperature and the controllable hysteresis. PMID:27879871

Low Voltage Current-Reused Pseudo-Differential Programmable Gain Amplifier

NASA Astrophysics Data System (ADS)

Nguyen, Huy-Hieu; Lee, Jeong-Seon; Lee, Sang-Gug

This paper reports a current-reused pseudo-differential (CRPD) programmable gain amplifier (PGA) that demonstrates small size, low power, wide band, low noise, and high linearity operation with 4 control bits. Implemented in 0.18um CMOS technology, the PGA shows the gain range from -9.9 to 8.3dB with gain error of less than ±0.38dB. The IIP3, P1dB, and smallest 3-dB bandwidth are 10.5 to 27dBm, -9 to 9.5dBm, and 250MHz, respectively. The PGA occupies the chip area of 0.04mm2 and consumes only 460 µA from a 1.2V supply.

Self-Recovery Experiments in Extreme Environments Using a Field Programmable Transistor Array

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Keymeulen, Didier; Arslan, Tughrul; Duong, Vu; Zebulum, Ricardo; Ferguson, Ian; Guo, Xin

2004-01-01

Temperature and radiation tolerant electronics, as well as long life survivability are key capabilities required for future NASA missions. Current approaches to electronics for extreme environments focus on component level robustness and hardening. However, current technology can only ensure very limited lifetime in extreme environments. This paper describes novel experiments that allow adaptive in-situ circuit redesign/reconfiguration during operation in extreme temperature and radiation environments. This technology would complement material/device advancements and increase the mission capability to survive harsh environments. The approach is demonstrated on a mixed-signal programmable chip (FPTA-2), which recovers functionality for temperatures until 28 C and with total radiation dose up to 250kRad.

The initial characterization of a revised 10-Gsps analog-to-digital converter board for radio telescopes

NASA Astrophysics Data System (ADS)

Jiango, Homin; Liuo, Howard; Guzzino, Kim

2016-07-01

In this study, the design of a 4 bit, 10-gigasamples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was revised, manufactured, and tested. It is used for digitizing radio telescopes. An Adsantec ANST7120-KMA flash ADC chip was used, as in the original design. Associated with the field-programmable gate array platform developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the developed PCBA provides data acquisition systems with a wider bandwidth and simplifies the intermediate frequency section. The current version of the PCBA exhibits an analog bandwidth of up to 10 GHz (3 dB loss), and the chip exhibits an analog bandwidth of up to 18 GHz. This facilitates second and third Nyquist sampling. The following worstcase performance parameters were obtained from the revised PCBA at over 5 GHz: spurious-free dynamic range of 12 dB, signal-to-noise and distortion ratio of 2 dB, and effective number of bits of 0.7. The design bugs in the ADC chip caused the poor performance. The vendor created a new batch run and confirmed that the ADC chips of the new batch will meet the specifications addressed in its data sheet.

Automated microfluidic platform of bead-based electrochemical immunosensor integrated with bioreactor for continual monitoring of cell secreted biomarkers

NASA Astrophysics Data System (ADS)

Riahi, Reza; Shaegh, Seyed Ali Mousavi; Ghaderi, Masoumeh; Zhang, Yu Shrike; Shin, Su Ryon; Aleman, Julio; Massa, Solange; Kim, Duckjin; Dokmeci, Mehmet Remzi; Khademhosseini, Ali

2016-04-01

There is an increasing interest in developing microfluidic bioreactors and organs-on-a-chip platforms combined with sensing capabilities for continual monitoring of cell-secreted biomarkers. Conventional approaches such as ELISA and mass spectroscopy cannot satisfy the needs of continual monitoring as they are labor-intensive and not easily integrable with low-volume bioreactors. This paper reports on the development of an automated microfluidic bead-based electrochemical immunosensor for in-line measurement of cell-secreted biomarkers. For the operation of the multi-use immunosensor, disposable magnetic microbeads were used to immobilize biomarker-recognition molecules. Microvalves were further integrated in the microfluidic immunosensor chip to achieve programmable operations of the immunoassay including bead loading and unloading, binding, washing, and electrochemical sensing. The platform allowed convenient integration of the immunosensor with liver-on-chips to carry out continual quantification of biomarkers secreted from hepatocytes. Transferrin and albumin productions were monitored during a 5-day hepatotoxicity assessment in which human primary hepatocytes cultured in the bioreactor were treated with acetaminophen. Taken together, our unique microfluidic immunosensor provides a new platform for in-line detection of biomarkers in low volumes and long-term in vitro assessments of cellular functions in microfluidic bioreactors and organs-on-chips.

Automated microfluidic platform of bead-based electrochemical immunosensor integrated with bioreactor for continual monitoring of cell secreted biomarkers

PubMed Central

Riahi, Reza; Shaegh, Seyed Ali Mousavi; Ghaderi, Masoumeh; Zhang, Yu Shrike; Shin, Su Ryon; Aleman, Julio; Massa, Solange; Kim, Duckjin; Dokmeci, Mehmet Remzi; Khademhosseini, Ali

2016-01-01

There is an increasing interest in developing microfluidic bioreactors and organs-on-a-chip platforms combined with sensing capabilities for continual monitoring of cell-secreted biomarkers. Conventional approaches such as ELISA and mass spectroscopy cannot satisfy the needs of continual monitoring as they are labor-intensive and not easily integrable with low-volume bioreactors. This paper reports on the development of an automated microfluidic bead-based electrochemical immunosensor for in-line measurement of cell-secreted biomarkers. For the operation of the multi-use immunosensor, disposable magnetic microbeads were used to immobilize biomarker-recognition molecules. Microvalves were further integrated in the microfluidic immunosensor chip to achieve programmable operations of the immunoassay including bead loading and unloading, binding, washing, and electrochemical sensing. The platform allowed convenient integration of the immunosensor with liver-on-chips to carry out continual quantification of biomarkers secreted from hepatocytes. Transferrin and albumin productions were monitored during a 5-day hepatotoxicity assessment in which human primary hepatocytes cultured in the bioreactor were treated with acetaminophen. Taken together, our unique microfluidic immunosensor provides a new platform for in-line detection of biomarkers in low volumes and long-term in vitro assessments of cellular functions in microfluidic bioreactors and organs-on-chips. PMID:27098564

Low-cost TDRSS communications for NASA's long duration balloon project

NASA Technical Reports Server (NTRS)

Israel, David J.

1993-01-01

A new transponder and RF ground support equipment for the NASA Tracking and Data Relay Satellite System (TDRSS) intended to support long duration scientific balloon flights in Antarctica are described. The new balloon class transponder features a highly integrated spread spectrum receiver design based on programmable charge coupled device (CCD) correlators and digital signal processing chips. The correlator chip is a Lincoln Labs 4ABC with four CCD channels. The balloon transponder is capable of reporting an estimate of its input bit error rate using digital signal processing. The TDRSS user RF test set is based on a set of RF ground support equipment capable of providing both the RF communications and direct control and monitoring necessary for transponder testing and a two-way RF link for preflight testing.

Dynamically Reconfigurable Systolic Array Accelerator

NASA Technical Reports Server (NTRS)

Dasu, Aravind; Barnes, Robert

2012-01-01

A polymorphic systolic array framework has been developed that works in conjunction with an embedded microprocessor on a field-programmable gate array (FPGA), which allows for dynamic and complimentary scaling of acceleration levels of two algorithms active concurrently on the FPGA. Use is made of systolic arrays and a hardware-software co-design to obtain an efficient multi-application acceleration system. The flexible and simple framework allows hosting of a broader range of algorithms, and is extendable to more complex applications in the area of aerospace embedded systems. FPGA chips can be responsive to realtime demands for changing applications needs, but only if the electronic fabric can respond fast enough. This systolic array framework allows for rapid partial and dynamic reconfiguration of the chip in response to the real-time needs of scalability, and adaptability of executables.

Involvement in shared decision-making for patients in public specialist outpatient clinics in Hong Kong

PubMed Central

Xu, Richard H; Wong, Eliza LY

2017-01-01

Objective This study is a preliminary exploration of the association between patient involvement in decision-making and patient socioeconomic characteristics and experience in specialist outpatient clinics (SOPCs) in Hong Kong. Methods Cross-sectional telephone interviews were conducted using the Specialist Outpatient Experience Questionnaire (SOPEQ) in 26 Hospital Authority public SOPCs in Hong Kong. The SOPEQ was designed by The School of Public Health and Primary Care at The Chinese University of Hong Kong, fully taking into account both literature review and the local context of the public specialist outpatient system in Hong Kong. A total of 22,525 eligible participants were recruited for the study. Results There were 13,966 valid responses. The results indicated that the patients who had more involvement in decision-making were younger (odds ratio [OR] =2.10; 95% CI 1.75, 2.53), more highly educated (OR =1.67; 95% CI 1.45, 1.93), less likely to be receiving a government allowance (OR =0.61; 95% CI 0.57, 0.65), and less likely to be in the new case group (OR =0.84; 95% CI 0.78, 0.92). Participants living with their families (OR =3.38; 95% CI 2.03, 5.63) or who were unemployed (OR =1.10; 95% CI 1.01, 1.21) had a more decisive role in the decision- making process. Those participants who had been more involved in decision-making and wanted to continue being more involved had greater levels of satisfaction (mean =7.94; P<0.001) and a better health status (OR =0.49; 95% CI 0.41, 0.58). Conclusion Engaging patients in their health care management remains a challenge in improving patient-centered care. Our results suggest that patient engagement is associated with perceived health status and the experience of using a health service. Understanding patients’ characteristics and roles facilitates the development of preferred styles in the decision-making model. PMID:28331297

Software Techniques for Non-Von Neumann Architectures

DTIC Science & Technology

1990-01-01

Commtopo programmable Benes net.; hypercubic lattice for QCD Control CENTRALIZED Assign STATIC Memory :SHARED Synch UNIVERSAL Max-cpu 566 Proessor...boards (each = 4 floating point units, 2 multipliers) Cpu-size 32-bit floating point chips Perform 11.4 Gflops Market quantum chromodynamics ( QCD ...functions there should exist a capability to define hierarchies and lattices of complex objects. A complex object can be made up of a set of simple objects

Generic controller dedicated to telemetry-controlled microsystems.

PubMed

Sodagar, Amir M; Wise, Kensall D; Najafi, Khalil

2006-01-01

This paper introduces a generic controller designed for telemetry-controlled microsystems. This controller receives a data packet through a serial link carrying a command word and the associated data, and is capable of generating a variety of control/timing signals according to the definition of the received command. The flexible microprogrammed architecture of the controller allows for defining the commands functions in an on-chip mask-programmable read-only memory.

Evolvable Hardware for Space Applications

NASA Technical Reports Server (NTRS)

Lohn, Jason; Globus, Al; Hornby, Gregory; Larchev, Gregory; Kraus, William

2004-01-01

This article surveys the research of the Evolvable Systems Group at NASA Ames Research Center. Over the past few years, our group has developed the ability to use evolutionary algorithms in a variety of NASA applications ranging from spacecraft antenna design, fault tolerance for programmable logic chips, atomic force field parameter fitting, analog circuit design, and earth observing satellite scheduling. In some of these applications, evolutionary algorithms match or improve on human performance.

Real-Time Data Filtering and Compression in Wide Area Simulation Networks

DTIC Science & Technology

1992-10-02

Area Simulation Networks Achieving the real-time linkage among multiple , geographically-distant, local area networks that support distributed...November 1989, pp. 52-61. [IEEE85] IEEE/ANSI Standard 8802/3 "Carrier sense multiple access with collision detection (CSMA/CD) access method and...decoding/encoding of multiple bits. The hardware is programmable, easily adaptable and yields a high compression rate. A prototype 2-micron VLSI chip

Innovative Programmable Bio-Nano-Chip Digitizes Biology Using Sensors That Learn Bridging Biomarker Discovery and Clinical Implementation

PubMed Central

Christodoulides, Nicolaos J.; McRae, Michael P.; Abram, Timothy J.; Simmons, Glennon W.; McDevitt, John T.

2017-01-01

The lack of standard tools and methodologies and the absence of a streamlined multimarker approval process have hindered the translation rate of new biomarkers into clinical practice for a variety of diseases afflicting humankind. Advanced novel technologies with superior analytical performance and reduced reagent costs, like the programmable bio-nano-chip system featured in this article, have potential to change the delivery of healthcare. This universal platform system has the capacity to digitize biology, resulting in a sensor modality with a capacity to learn. With well-planned device design, development, and distribution plans, there is an opportunity to translate benchtop discoveries in the genomics, proteomics, metabolomics, and glycomics fields by transforming the information content of key biomarkers into actionable signatures that can empower physicians and patients for a better management of healthcare. While the process is complicated and will take some time, showcased here are three application areas for this flexible platform that combines biomarker content with minimally invasive or non-invasive sampling, such as brush biopsy for oral cancer risk assessment; serum, plasma, and small volumes of blood for the assessment of cardiac risk and wellness; and oral fluid sampling for drugs of abuse testing at the point of need. PMID:28589118

Location of Biomarkers and Reagents within Agarose Beads of a Programmable Bio-nano-chip

PubMed Central

Jokerst, Jesse V.; Chou, Jie; Camp, James P.; Wong, Jorge; Lennart, Alexis; Pollard, Amanda A.; Floriano, Pierre N.; Christodoulides, Nicolaos; Simmons, Glennon W.; Zhou, Yanjie; Ali, Mehnaaz F.

2012-01-01

The slow development of cost-effective medical microdevices with strong analytical performance characteristics is due to a lack of selective and efficient analyte capture and signaling. The recently developed programmable bio-nano-chip (PBNC) is a flexible detection device with analytical behavior rivaling established macroscopic methods. The PBNC system employs ≈300 μm-diameter bead sensors composed of agarose “nanonets” that populate a microelectromechanical support structure with integrated microfluidic elements. The beads are an efficient and selective protein-capture medium suitable for the analysis of complex fluid samples. Microscopy and computational studies probe the 3D interior of the beads. The relative contributions that the capture and detection of moieties, analyte size, and bead porosity make to signal distribution and intensity are reported. Agarose pore sizes ranging from 45 to 620 nm are examined and those near 140 nm provide optimal transport characteristics for rapid (<15 min) tests. The system exhibits efficient (99.5%) detection of bead-bound analyte along with low (≈2%) nonspecific immobilization of the detection probe for carcinoembryonic antigen assay. Furthermore, the role analyte dimensions play in signal distribution is explored, and enhanced methods for assay building that consider the unique features of biomarker size are offered. PMID:21290601

A programmable palm-size gas analyzer for use in micro-autonomous systems

NASA Astrophysics Data System (ADS)

Gordenker, Robert J. M.; Wise, Kensall D.

2012-06-01

Gas analysis systems having small size, low power, and high selectivity are badly needed for defense (detection of explosives and chemical warfare agents), homeland security, health care, and environmental applications. This paper presents a palm-size gas chromatography system having analysis times of 5-50sec, detection limits less than 1ppb, and an average power dissipation less than one watt. It uses no consumables. The three-chip fluidic system consists of a preconcentrator, a 25cm-3m separation column, and a chemi-resistive detector and is supported by a microcomputer and circuitry for programmable temperature control. The entire system, including the mini-pump and battery, occupies less than 200cc and is configured for use on autonomous robotic vehicles.

Overview of the DART project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berry, K.R.; Hansen, F.R.; Napolitano, L.M.

1992-01-01

DART (DSP Arrary for Reconfigurable Tasks) is a parallel architecture of two high-performance SDP (digital signal processing) chips with the flexibility to handle a wide range of real-time applications. Each of the 32-bit floating-point DSP processes in DART is programmable in a high-level languate ( C'' or Ada). We have added extensions to the real-time operating system used by DART in order to support parallel processor. The combination of high-level language programmability, a real-time operating system, and parallel processing support significantly reduces the development cost of application software for signal processing and control applications. We have demonstrated this capability bymore » using DART to reconstruct images in the prototype VIP (Video Imaging Projectile) groundstation.« less

Overview of the DART project

DOE Office of Scientific and Technical Information (OSTI.GOV)

Berry, K.R.; Hansen, F.R.; Napolitano, L.M.

1992-01-01

DART (DSP Arrary for Reconfigurable Tasks) is a parallel architecture of two high-performance SDP (digital signal processing) chips with the flexibility to handle a wide range of real-time applications. Each of the 32-bit floating-point DSP processes in DART is programmable in a high-level languate (``C`` or Ada). We have added extensions to the real-time operating system used by DART in order to support parallel processor. The combination of high-level language programmability, a real-time operating system, and parallel processing support significantly reduces the development cost of application software for signal processing and control applications. We have demonstrated this capability by usingmore » DART to reconstruct images in the prototype VIP (Video Imaging Projectile) groundstation.« less

A lab-on-chip for malaria diagnosis and surveillance

PubMed Central

2014-01-01

Background Access to timely and accurate diagnostic tests has a significant impact in the management of diseases of global concern such as malaria. While molecular diagnostics satisfy this need effectively in developed countries, barriers in technology, reagent storage, cost and expertise have hampered the introduction of these methods in developing countries. In this study a simple, lab-on-chip PCR diagnostic was created for malaria that overcomes these challenges. Methods The platform consists of a disposable plastic chip and a low-cost, portable, real-time PCR machine. The chip contains a desiccated hydrogel with reagents needed for Plasmodium specific PCR. Chips can be stored at room temperature and used on demand by rehydrating the gel with unprocessed blood, avoiding the need for sample preparation. These chips were run on a custom-built instrument containing a Peltier element for thermal cycling and a laser/camera setup for amplicon detection. Results This diagnostic was capable of detecting all Plasmodium species with a limit of detection for Plasmodium falciparum of 2 parasites/μL of blood. This exceeds the sensitivity of microscopy, the current standard for diagnosis in the field, by ten to fifty-fold. In a blind panel of 188 patient samples from a hyper-endemic region of malaria transmission in Uganda, the diagnostic had high sensitivity (97.4%) and specificity (93.8%) versus conventional real-time PCR. The test also distinguished the two most prevalent malaria species in mixed infections, P. falciparum and Plasmodium vivax. A second blind panel of 38 patient samples was tested on a streamlined instrument with LED-based excitation, achieving a sensitivity of 96.7% and a specificity of 100%. Conclusions These results describe the development of a lab-on-chip PCR diagnostic from initial concept to ready-for-manufacture design. This platform will be useful in front-line malaria diagnosis, elimination programmes, and clinical trials. Furthermore, test chips can be adapted to detect other pathogens for a differential diagnosis in the field. The flexibility, reliability, and robustness of this technology hold much promise for its use as a novel molecular diagnostic platform in developing countries. PMID:24885206

CHIP: Facilitating Interprofessional and Culturally Competent Patient Care Through Experiential Learning in China.

PubMed

Mu, Keli; Peck, Kirk; Jensen, Lou; Bracciano, Al; Carrico, Cathy; Feldhacker, Diana

2016-12-01

Health care professionals have advocated for educating culturally competent practitioners. Immersion in international experiences has an impact on student cultural competency and interprofessional development. The China Honors Interprofessional Program (CHIP) at a university in the Midwest is designed to increase students' cultural competency and interprofessional development. From 2009 to 2013, a total of 25 professional students including twelve occupational therapy students, ten physical therapy students and three nursing students were enrolled in the programme. Using a one group pre and posttest research design, this study evaluated the impact of CHIP on the participating students. Both quantitative and qualitative data were collected in the study. Findings of the study revealed that CHIP has impact on students' cultural competency and professional development including gaining appreciation and understanding of the contributions of other healthcare professionals and knowledge and skills in team work. The findings of the study suggested that international immersion experience such as CHIP is an important way to increase students' cultural competency and interprofessional knowledge and skills. Limitations of the study included the small sample in the study, indirect outcome measures and the possible celling effect of the instruments of the study. Future research studies should include a larger and more representative sample, direct outcome measures such as behaviour observation and more rigorous design such as prospective experimental comparison group design. Future research should also examine the long-term effects of international experience on the professional development of occupational therapy students. Copyright © 2016 John Wiley & Sons, Ltd. Copyright © 2016 John Wiley & Sons, Ltd.

Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

PubMed Central

Valente, Virgilio; Demosthenous, Andreas

2016-01-01

This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS) analysis. Each VR channel occupies an area of 0.48 mm2, is capable of an operational bandwidth of 8 MHz and a linear gain in the range between −6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μA. Each CR channel occupies an area of 0.21 mm2. The chip consumes between 530 μA and 690 μA per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis. PMID:27463721

Analyzing System on A Chip Single Event Upset Responses using Single Event Upset Data, Classical Reliability Models, and Space Environment Data

NASA Technical Reports Server (NTRS)

Berg, Melanie; LaBel, Kenneth; Campola, Michael; Xapsos, Michael

2017-01-01

We are investigating the application of classical reliability performance metrics combined with standard single event upset (SEU) analysis data. We expect to relate SEU behavior to system performance requirements. Our proposed methodology will provide better prediction of SEU responses in harsh radiation environments with confidence metrics. single event upset (SEU), single event effect (SEE), field programmable gate array devises (FPGAs)

A design method for high performance seismic data acquisition based on oversampling delta-sigma modulation

NASA Astrophysics Data System (ADS)

Gao, Shanghua; Xue, Bing

2017-04-01

The dynamic range of the currently most widely used 24-bit seismic data acquisition devices is 10-20 dB lower than that of broadband seismometers, and this can affect the completeness of seismic waveform recordings under certain conditions. However, this problem is not easy to solve because of the lack of analog to digital converter (ADC) chips with more than 24 bits in the market. So the key difficulties for higher-resolution data acquisition devices lie in achieving more than 24-bit ADC circuit. In the paper, we propose a method in which an adder, an integrator, a digital to analog converter chip, a field-programmable gate array, and an existing low-resolution ADC chip are used to build a third-order 16-bit oversampling delta-sigma modulator. This modulator is equipped with a digital decimation filter, thus forming a complete analog to digital converting circuit. Experimental results show that, within the 0.1-40 Hz frequency range, the circuit board's dynamic range reaches 158.2 dB, its resolution reaches 25.99 dB, and its linearity error is below 2.5 ppm, which is better than what is achieved by the commercial 24-bit ADC chips ADS1281 and CS5371. This demonstrates that the proposed method may alleviate or even solve the amplitude-limitation problem that broadband observation systems so commonly have to face during strong earthquakes.

Novel microwave photonic fractional Hilbert transformer using a ring resonator-based optical all-pass filter.

PubMed

Zhuang, Leimeng; Khan, Muhammad Rezaul; Beeker, Willem; Leinse, Arne; Heideman, René; Roeloffzen, Chris

2012-11-19

We propose and demonstrate a novel wideband microwave photonic fractional Hilbert transformer implemented using a ring resonator-based optical all-pass filter. The full programmability of the ring resonator allows variable and arbitrary fractional order of the Hilbert transformer. The performance analysis in both frequency and time domain validates that the proposed implementation provides a good approximation to an ideal fractional Hilbert transformer. This is also experimentally verified by an electrical S₂₁ response characterization performed on a waveguide realization of a ring resonator. The waveguide-based structure allows the proposed Hilbert transformer to be integrated together with other building blocks on a photonic integrated circuit to create various system-level functionalities for on-chip microwave photonic signal processors. As an example, a circuit consisting of a splitter and a ring resonator has been realized which can perform on-chip phase control of microwave signals generated by means of optical heterodyning, and simultaneous generation of in-phase and quadrature microwave signals for a wide frequency range. For these functionalities, this simple and on-chip solution is considered to be practical, particularly when operating together with a dual-frequency laser. To our best knowledge, this is the first-time on-chip demonstration where ring resonators are employed to perform phase control functionalities for optical generation of microwave signals by means of optical heterodyning.

Fault-Tolerant, Real-Time, Multi-Core Computer System

NASA Technical Reports Server (NTRS)

Gostelow, Kim P.

2012-01-01

A document discusses a fault-tolerant, self-aware, low-power, multi-core computer for space missions with thousands of simple cores, achieving speed through concurrency. The proposed machine decides how to achieve concurrency in real time, rather than depending on programmers. The driving features of the system are simple hardware that is modular in the extreme, with no shared memory, and software with significant runtime reorganizing capability. The document describes a mechanism for moving ongoing computations and data that is based on a functional model of execution. Because there is no shared memory, the processor connects to its neighbors through a high-speed data link. Messages are sent to a neighbor switch, which in turn forwards that message on to its neighbor until reaching the intended destination. Except for the neighbor connections, processors are isolated and independent of each other. The processors on the periphery also connect chip-to-chip, thus building up a large processor net. There is no particular topology to the larger net, as a function at each processor allows it to forward a message in the correct direction. Some chip-to-chip connections are not necessarily nearest neighbors, providing short cuts for some of the longer physical distances. The peripheral processors also provide the connections to sensors, actuators, radios, science instruments, and other devices with which the computer system interacts.

Dedicated hardware processor and corresponding system-on-chip design for real-time laser speckle imaging.

PubMed

Jiang, Chao; Zhang, Hongyan; Wang, Jia; Wang, Yaru; He, Heng; Liu, Rui; Zhou, Fangyuan; Deng, Jialiang; Li, Pengcheng; Luo, Qingming

2011-11-01

Laser speckle imaging (LSI) is a noninvasive and full-field optical imaging technique which produces two-dimensional blood flow maps of tissues from the raw laser speckle images captured by a CCD camera without scanning. We present a hardware-friendly algorithm for the real-time processing of laser speckle imaging. The algorithm is developed and optimized specifically for LSI processing in the field programmable gate array (FPGA). Based on this algorithm, we designed a dedicated hardware processor for real-time LSI in FPGA. The pipeline processing scheme and parallel computing architecture are introduced into the design of this LSI hardware processor. When the LSI hardware processor is implemented in the FPGA running at the maximum frequency of 130 MHz, up to 85 raw images with the resolution of 640×480 pixels can be processed per second. Meanwhile, we also present a system on chip (SOC) solution for LSI processing by integrating the CCD controller, memory controller, LSI hardware processor, and LCD display controller into a single FPGA chip. This SOC solution also can be used to produce an application specific integrated circuit for LSI processing.

A 256-channel, high throughput and precision time-to-digital converter with a decomposition encoding scheme in a Kintex-7 FPGA

NASA Astrophysics Data System (ADS)

Song, Z.; Wang, Y.; Kuang, J.

2018-05-01

Field Programmable Gate Arrays (FPGAs) made with 28 nm and more advanced process technology have great potentials for implementation of high precision time-to-digital convertors (TDC), because the delay cells in the tapped delay line (TDL) used for time interpolation are getting smaller and smaller. However, the bubble problems in the TDL status are becoming more complicated, which make it difficult to achieve TDCs on these chips with a high time precision. In this paper, we are proposing a novel decomposition encoding scheme, which not only can solve the bubble problem easily, but also has a high encoding efficiency. The potential of these chips to realize TDC can be fully released with the scheme. In a Xilinx Kintex-7 FPGA chip, we implemented a TDC system with 256 TDC channels, which doubles the number of TDC channels that our previous technique could achieve. Performances of all these TDC channels are evaluated. The average RMS time precision among them is 10.23 ps in the time-interval measurement range of (0–10 ns), and their measurement throughput reaches 277 M measures per second.

InGaAs/InP SPAD photon-counting module with auto-calibrated gate-width generation and remote control

NASA Astrophysics Data System (ADS)

Tosi, Alberto; Ruggeri, Alessandro; Bahgat Shehata, Andrea; Della Frera, Adriano; Scarcella, Carmelo; Tisa, Simone; Giudice, Andrea

2013-01-01

We present a photon-counting module based on InGaAs/InP SPAD (Single-Photon Avalanche Diode) for detecting single photons up to 1.7 μm. The module exploits a novel architecture for generating and calibrating the gate width, along with other functions (such as module supervision, counting and processing of detected photons, etc.). The gate width, i.e. the time interval when the SPAD is ON, is user-programmable in the range from 500 ps to 1.5 μs, by means of two different delay generation methods implemented with an FPGA (Field-Programmable Gate Array). In order to compensate chip-to-chip delay variation, an auto-calibration circuit picks out a combination of delays in order to match at best the selected gate width. The InGaAs/InP module accepts asynchronous and aperiodic signals and introduces very low timing jitter. Moreover the photon counting module provides other new features like a microprocessor for system supervision, a touch-screen for local user interface, and an Ethernet link for smart remote control. Thanks to the fullyprogrammable and configurable architecture, the overall instrument provides high system flexibility and can easily match all requirements set by many different applications requiring single photon-level sensitivity in the near infrared with very low photon timing jitter.

A reconfigurable continuous-flow fluidic routing fabric using a modular, scalable primitive.

PubMed

Silva, Ryan; Bhatia, Swapnil; Densmore, Douglas

2016-07-05

Microfluidic devices, by definition, are required to move liquids from one physical location to another. Given a finite and frequently fixed set of physical channels to route fluids, a primitive design element that allows reconfigurable routing of that fluid from any of n input ports to any n output ports will dramatically change the paradigms by which these chips are designed and applied. Furthermore, if these elements are "regular" regarding their design, the programming and fabrication of these elements becomes scalable. This paper presents such a design element called a transposer. We illustrate the design, fabrication and operation of a single transposer. We then scale this design to create a programmable fabric towards a general-purpose, reconfigurable microfluidic platform analogous to the Field Programmable Gate Array (FPGA) found in digital electronics.

A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring

NASA Astrophysics Data System (ADS)

Iwato, Hirofumi; Sakanushi, Keishi; Takeuchi, Yoshinori; Imai, Masaharu

To measure the detrusor pressure for diagnosing lower urinary tract symptoms, we designed a small-area and low-power System on a Chip (SoC). The SoC should be small and low power because it is encapsulated in tiny air-tight capsules which are simultaneously inserted in the urinary bladder and rectum for several days. Since the SoC is also required to be programmable, we designed an Application Specific Instruction set Processor (ASIP) for pressure measurement and wireless communication, and implemented almost required functions on the ASIP. The SoC was fabricated using a 0.18µm CMOS mixed-signal process and the chip size is 2.5×2.5mm2. Evaluation results show that the power consumption of the SoC is 93.5µW, and that it can operate the capsule for seven days with a tiny battery.

A CMOS Self-Contained Quadrature Signal Generator for SoC Impedance Spectroscopy.

PubMed

Márquez, Alejandro; Pérez-Bailón, Jorge; Calvo, Belén; Medrano, Nicolás; Martínez, Pedro A

2018-04-30

This paper presents a low-power fully integrated quadrature signal generator for system-on-chip (SoC) impedance spectroscopy applications. It has been designed in a 0.18 μm-1.8 V CMOS technology as a self-contained oscillator, without the need for an external reference clock. The frequency can be digitally tuned from 10 to 345 kHz with 12-bit accuracy and a relative mean error below 1.7%, thus supporting a wide range of impedance sensing applications. The proposal is experimentally validated in two impedance spectrometry examples, achieving good magnitude and phase recovery results compared to the results obtained using a commercial LCR-meter. Besides the wide frequency tuning range, the proposed programmable oscillator features a total power consumption lower than 0.77 mW and an active area of 0.129 mm², thus constituting a highly suitable choice as stimulation module for instrument-on-a-chip devices.

Slow Controls Using the Axiom M5235BCC

NASA Astrophysics Data System (ADS)

Hague, Tyler

2008-10-01

The Forward Vertex Detector group at PHENIX plans to adopt the Axiom M5235 Business Card Controller for use as slow controls. It is also being evaluated for slow controls on FermiLab e906. This controller features the Freescale MCF5235 microprocessor. It also has three parallel buses, these being the MCU port, BUS port, and enhanced Time Processing Unit (eTPU) port. The BUS port uses a chip select module with three external chip selects to communicate with peripherals. This will be used to communicate with and configure Field Programmable Gate Arrays (FPGAs). The controller also has an Ethernet port which can use several different protocols such as TCP and UDP. This will be used to transfer files with computers on a network. The M5235 Business Card Controller will be placed in a VME crate along with VME card and a Spartan-3 FPGA.

Smart image sensors: an emerging key technology for advanced optical measurement and microsystems

NASA Astrophysics Data System (ADS)

Seitz, Peter

1996-08-01

Optical microsystems typically include photosensitive devices, analog preprocessing circuitry and digital signal processing electronics. The advances in semiconductor technology have made it possible today to integrate all photosensitive and electronical devices on one 'smart image sensor' or photo-ASIC (application-specific integrated circuits containing photosensitive elements). It is even possible to provide each 'smart pixel' with additional photoelectronic functionality, without compromising the fill factor substantially. This technological capability is the basis for advanced cameras and optical microsystems showing novel on-chip functionality: Single-chip cameras with on- chip analog-to-digital converters for less than $10 are advertised; image sensors have been developed including novel functionality such as real-time selectable pixel size and shape, the capability of performing arbitrary convolutions simultaneously with the exposure, as well as variable, programmable offset and sensitivity of the pixels leading to image sensors with a dynamic range exceeding 150 dB. Smart image sensors have been demonstrated offering synchronous detection and demodulation capabilities in each pixel (lock-in CCD), and conventional image sensors are combined with an on-chip digital processor for complete, single-chip image acquisition and processing systems. Technological problems of the monolithic integration of smart image sensors include offset non-uniformities, temperature variations of electronic properties, imperfect matching of circuit parameters, etc. These problems can often be overcome either by designing additional compensation circuitry or by providing digital correction routines. Where necessary for technological or economic reasons, smart image sensors can also be combined with or realized as hybrids, making use of commercially available electronic components. It is concluded that the possibilities offered by custom smart image sensors will influence the design and the performance of future electronic imaging systems in many disciplines, reaching from optical metrology to machine vision on the factory floor and in robotics applications.

Neuromorphic VLSI vision system for real-time texture segregation.

PubMed

Shimonomura, Kazuhiro; Yagi, Tetsuya

2008-10-01

The visual system of the brain can perceive an external scene in real-time with extremely low power dissipation, although the response speed of an individual neuron is considerably lower than that of semiconductor devices. The neurons in the visual pathway generate their receptive fields using a parallel and hierarchical architecture. This architecture of the visual cortex is interesting and important for designing a novel perception system from an engineering perspective. The aim of this study is to develop a vision system hardware, which is designed inspired by a hierarchical visual processing in V1, for real time texture segregation. The system consists of a silicon retina, orientation chip, and field programmable gate array (FPGA) circuit. The silicon retina emulates the neural circuits of the vertebrate retina and exhibits a Laplacian-Gaussian-like receptive field. The orientation chip selectively aggregates multiple pixels of the silicon retina in order to produce Gabor-like receptive fields that are tuned to various orientations by mimicking the feed-forward model proposed by Hubel and Wiesel. The FPGA circuit receives the output of the orientation chip and computes the responses of the complex cells. Using this system, the neural images of simple cells were computed in real-time for various orientations and spatial frequencies. Using the orientation-selective outputs obtained from the multi-chip system, a real-time texture segregation was conducted based on a computational model inspired by psychophysics and neurophysiology. The texture image was filtered by the two orthogonally oriented receptive fields of the multi-chip system and the filtered images were combined to segregate the area of different texture orientation with the aid of FPGA. The present system is also useful for the investigation of the functions of the higher-order cells that can be obtained by combining the simple and complex cells.

The research of data acquisition system for Raman spectrometer

NASA Astrophysics Data System (ADS)

Cui, Xiao; Guo, Pan; Zhang, Yinchao; Chen, Siying; Chen, He; Chen, Wenbo

2011-11-01

Raman spectrometer has been widely used as an identification tool for analyzing material structure and composition in many fields. However, Raman scattering echo signal is very weak, about dozens of photons at most in one laser plus signal. Therefore, it is a great challenge to design a Raman spectrum data acquisition system which could accurately receive the weak echo signal. The system designed in this paper receives optical signals with the principle of photon counter and could detect single photon. The whole system consists of a photoelectric conversion module H7421-40 and a photo counting card including a field programmable gate array (FPGA) chip and a PCI9054 chip. The module H7421-40 including a PMT, an amplifier and a discriminator has high sensitivity on wavelength from 300nm to 720nm. The Center Wavelength is 580nm which is close to the excitation wavelength (532nm), QE 40% at peak wavelength, Count Sensitivity is 7.8*105(S-1PW-1) and Count Linearity is 1.5MHZ. In FPGA chip, the functions are divided into three parts: parameter setting module, controlling module, data collection and storage module. All the commands, parameters and data are transmitted between FPGA and computer by PCI9054 chip through the PCI interface. The result of experiment shows that the Raman spectrum data acquisition system is reasonable and efficient. There are three primary advantages of the data acquisition system: the first one is the high sensitivity with single photon detection capability; the second one is the high integrated level which means all the operation could be done by the photo counting card; and the last one is the high expansion ability because of the smart reconfigurability of FPGA chip.

SFERA: An Integrated Circuit for the Readout of X and gamma -Ray Detectors

NASA Astrophysics Data System (ADS)

Schembari, Filippo; Quaglia, Riccardo; Bellotti, Giovanni; Fiorini, Carlo

2016-06-01

In this work we present SFERA, a low-noise fully-programmable 16 channel readout ASIC designed for both Xand y-ray spectroscopy and imaging applications. The chip is designed to process signals coming from solid-state detectors and CMOS preamplifiers. The design has been guided by the use of Silicon Drift Detectors (SDDs) and CUBE charge sensitive amplifiers (CSAs), although we consider the ASIC sufficiently versatile to be used with other types of detectors. Five different gains are implemented, namely 2800 e-, 4400 e-, 10000 e-, 14000 e- and 20000 e-, considering the input connected to a 25 fF feedback capacitance CMOS preamplifier. Filter peaking times (tP) are also programmable among 0.5, 1, 2, 3, 4 and 6 μs. Each readout channel is the cascade of a 9th order semi-Gaussian shaping-amplifier (SA) and a peak detector (PKS), followed by a dedicated pile-up rejection (PUR) digital logic. Three data multiplexing strategies are implemented: the so-called polling X, intended for high-rate X-ray applications, the polling y, for scintillation light detection and the sparse, for signals derandomization. The spectroscopic characterization has shown an energy resolution of 122.1 eV FWHM on the Mn-Ku line of an 55Fe X-ray source using a 10 mm2 SDD cooled at -35 °C at 4 μs filter peaking time. The measured resolution is 130 eV at the peaking time of 500 ns. At 1 Mcps input count rate and 500 ns peaking time, we have measured 42% of processed events at the output of the ASIC after the PUR selection. Output data can be digitized on-chip by means of an embedded 12-bit successive-approximation ADC. The effective resolution of the data converter is 10.75-bit when operated at 4.5 MS/s. The chosen technology is the AMS 0.35 μm CMOS and the chip area occupancy is 5 × 5 mm2.

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

PubMed

Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

2016-01-30

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

PubMed Central

Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

2016-01-01

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system. PMID:26840316

A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

NASA Technical Reports Server (NTRS)

Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

2012-01-01

Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

Fast and Precise Emulation of Stochastic Biochemical Reaction Networks With Amplified Thermal Noise in Silicon Chips.

PubMed

Kim, Jaewook; Woo, Sung Sik; Sarpeshkar, Rahul

2018-04-01

The analysis and simulation of complex interacting biochemical reaction pathways in cells is important in all of systems biology and medicine. Yet, the dynamics of even a modest number of noisy or stochastic coupled biochemical reactions is extremely time consuming to simulate. In large part, this is because of the expensive cost of random number and Poisson process generation and the presence of stiff, coupled, nonlinear differential equations. Here, we demonstrate that we can amplify inherent thermal noise in chips to emulate randomness physically, thus alleviating these costs significantly. Concurrently, molecular flux in thermodynamic biochemical reactions maps to thermodynamic electronic current in a transistor such that stiff nonlinear biochemical differential equations are emulated exactly in compact, digitally programmable, highly parallel analog "cytomorphic" transistor circuits. For even small-scale systems involving just 80 stochastic reactions, our 0.35-μm BiCMOS chips yield a 311× speedup in the simulation time of Gillespie's stochastic algorithm over COPASI, a fast biochemical-reaction software simulator that is widely used in computational biology; they yield a 15 500× speedup over equivalent MATLAB stochastic simulations. The chip emulation results are consistent with these software simulations over a large range of signal-to-noise ratios. Most importantly, our physical emulation of Poisson chemical dynamics does not involve any inherently sequential processes and updates such that, unlike prior exact simulation approaches, they are parallelizable, asynchronous, and enable even more speedup for larger-size networks.

Real-time and label-free ring-resonator monitoring of solid-phase recombinase polymerase amplification.

PubMed

Sabaté Del Río, Jonathan; Steylaerts, Tim; Henry, Olivier Y F; Bienstman, Peter; Stakenborg, Tim; Van Roy, Wim; O'Sullivan, Ciara K

2015-11-15

In this work we present the use of a silicon-on-insulator (SOI) chip featuring an array of 64 optical ring resonators used as refractive index sensors for real-time and label-free DNA detection. Single ring functionalisation was achieved using a click reaction after precise nanolitre spotting of specific hexynyl-terminated DNA capture probes to link to an azido-silanised chip surface. To demonstrate detectability using the ring resonators and to optimise conditions for solid-phase amplification, hybridisation between short 25-mer single stranded DNA (ssDNA) fragments and a complementary capture probe immobilised on the surface of the ring resonators was carried out and detected through the shift in the resonant wavelength. Using the optimised conditions demonstrated via the solid-phase hybridisation, a 144-bp double stranded DNA (dsDNA) was then detected directly using recombinase and polymerase proteins through on-chip target amplification and solid-phase elongation of immobilised forward primers on specific rings, at a constant temperature of 37°C and in less than 60min, achieving a limit of detection of 7.8·10(-13)M (6·10(5) copies in 50µL). The use of an automatic liquid handler injection instrument connected to an integrated resealable chip interface (RCI) allowed programmable multiple injection protocols. Air plugs between different solutions were introduced to prevent intermixing and a proportional-integral-derivative (PID) temperature controller minimised temperature based drifts. Published by Elsevier B.V.

Hypersonic Transition Along Curved Surfaces in the Presence of Vortices and Their Control by Using Microtextured Surfaces

DTIC Science & Technology

2015-05-13

Bhagwandin, Pierre N. Floriano, Nico- laos Christodoulides, and John T. McDevitt, “Programmable nano- bio -chip sensors : Analytical meets clinical”, Analytical...superhydrophobic surfaces can be used in many technologies such as self-cleaning coatings for satellite dishes, solar energy panels, photovoltaics and...Design of hydrophobic surfaces for liquid droplet control”, NPG Asia Mater. 3, pp. 49–56 (2011). [15] K. Liu and L. Jiang, “ Bio -inspired self-cleaning

Clock jitter generator with picoseconds resolution

NASA Astrophysics Data System (ADS)

Jovanović, Goran; Stojčev, Mile; Nikolić, Tatjana

2013-06-01

The clock is one of the most critical signals in any synchronous system. As CMOS technology has scaled, supply voltages have dropped chip power consumption has increased and the effects of jitter due to clock frequency increase have become critical and jitter budget has become tighter. This article describes design and development of low-cost mixed-signal programmable jitter generator with high resolution. The digital technique is used for coarse-grain and an analogue technique for fine-grain clock phase shifting. Its structure allows injection of various random and deterministic jitter components in a controllable and programmable fashion. Each jitter component can be switched on or off. The jitter generator can be used in jitter tolerance test and jitter transfer function measurement of high-speed synchronous digital circuits. At operating system clock frequency of 220 MHz, a jitter with 4 ps resolution can be injected.

Programmable logic devices

NASA Astrophysics Data System (ADS)

Jacobs, J. L.

1993-04-01

Erasable programmable logic devices (EPLD's) were investigated to determine their advantages and/or disadvantages in Test Equipment Engineering applications. It was found that EPLD's performed as well as or better than identical circuits using standard transistor transistor logic (TTL). The chip count in these circuits was reduced, saving printed circuit board space and shortening fabrication and prove-in time. Troubleshooting circuits of EPLD's was also easier with 10 to 100 times fewer wires needed. The reduced number of integrated circuits (IC's) contributed to faster system speeds and an overall lower power consumption. In some cases changes to the circuit became software changes using EPLD's instead of hardware changes for standard logic. Using EPLD's was fairly easy; however, as with any new technology, a learning curve must be overcome before EPLD's can be used efficiently. The many benefits of EPLD's outweighed this initial inconvenience.

Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

PubMed

Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

2016-09-19

Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

Multi-DSP and FPGA based Multi-channel Direct IF/RF Digital receiver for atmospheric radar

NASA Astrophysics Data System (ADS)

Yasodha, Polisetti; Jayaraman, Achuthan; Kamaraj, Pandian; Durga rao, Meka; Thriveni, A.

2016-07-01

Modern phased array radars depend highly on digital signal processing (DSP) to extract the echo signal information and to accomplish reliability along with programmability and flexibility. The advent of ASIC technology has made various digital signal processing steps to be realized in one DSP chip, which can be programmed as per the application and can handle high data rates, to be used in the radar receiver to process the received signal. Further, recent days field programmable gate array (FPGA) chips, which can be re-programmed, also present an opportunity to utilize them to process the radar signal. A multi-channel direct IF/RF digital receiver (MCDRx) is developed at NARL, taking the advantage of high speed ADCs and high performance DSP chips/FPGAs, to be used for atmospheric radars working in HF/VHF bands. Multiple channels facilitate the radar t be operated in multi-receiver modes and also to obtain the wind vector with improved time resolution, without switching the antenna beam. MCDRx has six channels, implemented on a custom built digital board, which is realized using six numbers of ADCs for simultaneous processing of the six input signals, Xilinx vertex5 FPGA and Spartan6 FPGA, and two ADSPTS201 DSP chips, each of which performs one phase of processing. MCDRx unit interfaces with the data storage/display computer via two gigabit ethernet (GbE) links. One of the six channels is used for Doppler beam swinging (DBS) mode and the other five channels are used for multi-receiver mode operations, dedicatedly. Each channel has (i) ADC block, to digitize RF/IF signal, (ii) DDC block for digital down conversion of the digitized signal, (iii) decoding block to decode the phase coded signal, and (iv) coherent integration block for integrating the data preserving phase intact. ADC block consists of Analog devices make AD9467 16-bit ADCs, to digitize the input signal at 80 MSPS. The output of ADC is centered around (80 MHz - input frequency). The digitized data is fed to DDC block, which down converts the data to base-band. The DDC block has NCO, mixer and two chains of Bessel filters (fifth order cascaded integration comb filter, two FIR filters, two half band filters and programmable FIR filters) for in-phase (I) and Quadrature phase (Q) channels. The NCO has 32 bits and is set to match the output frequency of ADC. Further, DDC down samples (decimation) the data and reduces the data rate to 16 MSPS. This data is further decimated and the data rate is reduced down to 4/2/1/0.5/0.25/0.125/0.0625 MSPS for baud lengths 0.25/0.5/1/2/4/8/16 μs respectively. The down sampled data is then fed to decoding block, which performs cross correlation to achieve pulse compression of the binary-phase coded data to obtain better range resolution with maximum possible height coverage. This step improves the signal power by a factor equal to the length of the code. Coherent integration block integrates the decoded data coherently for successive pulses, which improves the signal to noise ratio and reduces the data volume. DDC, decoding and coherent integration blocks are implemented in Xilinx vertex5 FPGA. Till this point, function of all six channels is same for DBS mode and multi-receiver modes. Data from vertex5 FPGA is transferred to PC via GbE-1 interface for multi-modes or to two Analog devices make ADSP-TS201 DSP chips (A and B), via link port for DBS mode. ADSP-TS201 chips perform the normalization, DC removal, windowing, FFT computation and spectral averaging on the data, which is transferred to storage/display PC via GbE-2 interface for real-time data display and data storing. Physical layer of GbE interface is implemented in an external chip (Marvel 88E1111) and MAC layer is implemented internal to vertex5 FPGA. The MCDRx has total 4 GB of DDR2 memory for data storage. Spartan6 FPGA is used for generating timing signals, required for basic operation of the radar and testing of the MCDRx.

SNAVA-A real-time multi-FPGA multi-model spiking neural network simulation architecture.

PubMed

Sripad, Athul; Sanchez, Giovanny; Zapata, Mireya; Pirrone, Vito; Dorta, Taho; Cambria, Salvatore; Marti, Albert; Krishnamourthy, Karthikeyan; Madrenas, Jordi

2018-01-01

Spiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable and programmable parallel architecture that supports real-time, large-scale, multi-model SNN computation. This parallel architecture is implemented in modern Field-Programmable Gate Arrays (FPGAs) devices to provide high performance execution and flexibility to support large-scale SNN models. Flexibility is defined in terms of programmability, which allows easy synapse and neuron implementation. This has been achieved by using a special-purpose Processing Elements (PEs) for computing SNNs, and analyzing and customizing the instruction set according to the processing needs to achieve maximum performance with minimum resources. The parallel architecture is interfaced with customized Graphical User Interfaces (GUIs) to configure the SNN's connectivity, to compile the neuron-synapse model and to monitor SNN's activity. Our contribution intends to provide a tool that allows to prototype SNNs faster than on CPU/GPU architectures but significantly cheaper than fabricating a customized neuromorphic chip. This could be potentially valuable to the computational neuroscience and neuromorphic engineering communities. Copyright © 2017 Elsevier Ltd. All rights reserved.

Digitally programmable microfluidic automaton for multiscale combinatorial mixing and sample processing†

PubMed Central

Jensen, Erik C.; Stockton, Amanda M.; Chiesl, Thomas N.; Kim, Jungkyu; Bera, Abhisek; Mathies, Richard A.

2013-01-01

A digitally programmable microfluidic Automaton consisting of a 2-dimensional array of pneumatically actuated microvalves is programmed to perform new multiscale mixing and sample processing operations. Large (µL-scale) volume processing operations are enabled by precise metering of multiple reagents within individual nL-scale valves followed by serial repetitive transfer to programmed locations in the array. A novel process exploiting new combining valve concepts is developed for continuous rapid and complete mixing of reagents in less than 800 ms. Mixing, transfer, storage, and rinsing operations are implemented combinatorially to achieve complex assay automation protocols. The practical utility of this technology is demonstrated by performing automated serial dilution for quantitative analysis as well as the first demonstration of on-chip fluorescent derivatization of biomarker targets (carboxylic acids) for microchip capillary electrophoresis on the Mars Organic Analyzer. A language is developed to describe how unit operations are combined to form a microfluidic program. Finally, this technology is used to develop a novel microfluidic 6-sample processor for combinatorial mixing of large sets (>26 unique combinations) of reagents. The digitally programmable microfluidic Automaton is a versatile programmable sample processor for a wide range of process volumes, for multiple samples, and for different types of analyses. PMID:23172232

Lab on a chip for multiplexed immunoassays to detect bladder cancer using multifunctional dielectrophoretic manipulations.

PubMed

Chuang, Cheng-Hsin; Wu, Ting-Feng; Chen, Cheng-Ho; Chang, Kai-Chieh; Ju, Jing-Wei; Huang, Yao-Wei; Van Nhan, Vo

2015-07-21

A multiplexed immunosensor has been developed for the detection of specific biomarkers Galectin-1 (Gal-1) and Lactate Dehydrogenase B (LDH-B) present in different grades of bladder cancer cell lysates. In order to immobilize nanoprobes with different antibodies on a single chip we employed three-step programmable dielectrophoretic manipulations for focusing, guiding and trapping to enhance the fluorescent response and reduce the interference between the two antibody arrays. The chip consisted of a patterned indium tin oxide (ITO) electrode for sensing and a middle fish bone shaped gold electrode for focusing and guiding. Using ITO electrodes for the sensing area can effectively eliminate the background noise of fluorescence response as compared to metal electrodes. It was also observed that the three step manipulation increased fluorescence response after immunosensing by about 4.6 times as compared to utilizing DEP for just trapping the nanoprobes. Two different-grade bladder cancer cell lysates (grade I: RT4 and grade III: T24) were individually analyzed for detecting the protein expression levels of Gal-1 and LDH-B. The fluorescence intensity observed for Gal-1 is higher than that of LDH-B in the T24 cell lysate; however the response observed in RT4 is higher for LDH-B as compared to Gal-1. Thus we can effectively identify the different grades of bladder cancer cells. In addition, the platform for DEP manipulation developed in this study can enable real time detection of multiple analytes on a single chip and provide more practical benefits for clinical diagnosis.

A digital optical phase-locked loop for diode lasers based on field programmable gate array.

PubMed

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382∕MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad(2) and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

NASA Astrophysics Data System (ADS)

Xu, Zhouxiang; Zhang, Xian; Huang, Kaikai; Lu, Xuanhui

2012-09-01

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat note line width below 1 Hz, residual mean-square phase error of 0.14 rad2 and transition time of 100 μs under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.

Three Realizations and Comparison of Hardware for Piezoresistive Tactile Sensors

PubMed Central

Vidal-Verdú, Fernando; Oballe-Peinado, Óscar; Sánchez-Durán, José A.; Castellanos-Ramos, Julián; Navas-González, Rafael

2011-01-01

Tactile sensors are basically arrays of force sensors that are intended to emulate the skin in applications such as assistive robotics. Local electronics are usually implemented to reduce errors and interference caused by long wires. Realizations based on standard microcontrollers, Programmable Systems on Chip (PSoCs) and Field Programmable Gate Arrays (FPGAs) have been proposed by the authors for the case of piezoresistive tactile sensors. The solution employing FPGAs is especially relevant since their performance is closer to that of Application Specific Integrated Circuits (ASICs) than that of the other devices. This paper presents an implementation of such an idea for a specific sensor. For the purpose of comparison, the circuitry based on the other devices is also made for the same sensor. This paper discusses the implementation issues, provides details regarding the design of the hardware based on the three devices and compares them. PMID:22163797

A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

NASA Astrophysics Data System (ADS)

Szplet, R.; Kalisz, J.; Jachna, Z.

2009-02-01

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second.

Programmable micrometer-sized motor array based on live cells.

PubMed

Xie, Shuangxi; Wang, Xiaodong; Jiao, Niandong; Tung, Steve; Liu, Lianqing

2017-06-13

Trapping and transporting microorganisms with intrinsic motility are important tasks for biological, physical, and biomedical applications. However, fast swimming speed makes the manipulation of these organisms an inherently challenging task. In this study, we demonstrated that an optoelectrical technique, namely, optically induced dielectrophoresis (ODEP), could effectively trap and manipulate Chlamydomonas reinhardtii (C. reinhardtii) cells swimming at velocities faster than 100 μm s -1 . Furthermore, live C. reinhardtii cells trapped by ODEP can form a micrometer-sized motor array. The rotating frequency of the cells ranges from 50 to 120 rpm, which can be reversibly adjusted with a fast response speed by varying the optical intensity. Functional flagella have been demonstrated to play a decisive role in the rotation. The programmable cell array with a rotating motion can be used as a bio-micropump to drive the liquid flow in microfludic chips and may shed new light on bio-actuation.

Smart-Pixel Array Processors Based on Optimal Cellular Neural Networks for Space Sensor Applications

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi; Sheu, Bing J.; Venus, Holger; Sandau, Rainer

1997-01-01

A smart-pixel cellular neural network (CNN) with hardware annealing capability, digitally programmable synaptic weights, and multisensor parallel interface has been under development for advanced space sensor applications. The smart-pixel CNN architecture is a programmable multi-dimensional array of optoelectronic neurons which are locally connected with their local neurons and associated active-pixel sensors. Integration of the neuroprocessor in each processor node of a scalable multiprocessor system offers orders-of-magnitude computing performance enhancements for on-board real-time intelligent multisensor processing and control tasks of advanced small satellites. The smart-pixel CNN operation theory, architecture, design and implementation, and system applications are investigated in detail. The VLSI (Very Large Scale Integration) implementation feasibility was illustrated by a prototype smart-pixel 5x5 neuroprocessor array chip of active dimensions 1380 micron x 746 micron in a 2-micron CMOS technology.

Assurance of Complex Electronics. What Path Do We Take?

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled in software, such as communication protocols. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of "software-like" bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and "bugs" can be detected earlier in the development cycle, thus creating a development process for CE that will be easily maintained and configurable based on the device used.

Geo-Chip analysis reveals reduced functional diversity of the bacterial community at a dumping site for dredged Elbe sediment.

PubMed

Störmer, Rebecca; Wichels, Antje; Gerdts, Gunnar

2013-12-15

The dumping of dredged sediments represents a major stressor for coastal ecosystems. The impact on the ecosystem function is determined by its complexity not easy to assess. In the present study, we evaluated the potential of bacterial community analyses to act as ecological indicators in environmental monitoring programmes. We investigated the functional structure of bacterial communities, applying functional gene arrays (GeoChip4.2). The relationship between functional genes and environmental factors was analysed using distance-based multivariate multiple regression. Apparently, both the function and structure of the bacterial communities are impacted by dumping activities. The bacterial community at the dumping centre displayed a significant reduction of its entire functional diversity compared with that found at a reference site. DDX compounds separated bacterial communities of the dumping site from those of un-impacted sites. Thus, bacterial community analyses show great potential as ecological indicators in environmental monitoring. Copyright © 2013 Elsevier Ltd. All rights reserved.

System Design of One-chip Wave Particle Interaction Analyzer for SCOPE mission.

NASA Astrophysics Data System (ADS)

Fukuhara, Hajime; Ueda, Yoshikatsu; Kojima, Hiro; Yamakawa, Hiroshi

In past science spacecrafts such like GEOTAIL, we usually capture electric and magnetic field waveforms and observe energetic eletron and ion particles as velocity distributions by each sensor. We analyze plasma wave-particle interactions by these respective data and the discussions are sometimes restricted by the difference of time resolution and by the data loss in desired regions. One-chip Wave Particle Interaction Analyzer (OWPIA) conducts direct quantitative observations of wave-particle interaction by direct 'E dot v' calculation on-board. This new instruments have a capability to use all plasma waveform data and electron particle informations. In the OWPIA system, we have to calibrate the digital observation data and transform the same coordinate system. All necessary calculations are processed in Field Programmable Gate Array(FPGA). In our study, we introduce a basic concept of the OWPIA system and a optimization method for each calculation functions installed in FPGA. And we also discuss the process speed, the FPGA utilization efficiency, the total power consumption.

Multi-Agent Methods for the Configuration of Random Nanocomputers

NASA Technical Reports Server (NTRS)

Lawson, John W.

2004-01-01

As computational devices continue to shrink, the cost of manufacturing such devices is expected to grow exponentially. One alternative to the costly, detailed design and assembly of conventional computers is to place the nano-electronic components randomly on a chip. The price for such a trivial assembly process is that the resulting chip would not be programmable by conventional means. In this work, we show that such random nanocomputers can be adaptively programmed using multi-agent methods. This is accomplished through the optimization of an associated high dimensional error function. By representing each of the independent variables as a reinforcement learning agent, we are able to achieve convergence must faster than with other methods, including simulated annealing. Standard combinational logic circuits such as adders and multipliers are implemented in a straightforward manner. In addition, we show that the intrinsic flexibility of these adaptive methods allows the random computers to be reconfigured easily, making them reusable. Recovery from faults is also demonstrated.

Possibilities for mixed mode chip manufacturing in EUROPRACTICE

NASA Astrophysics Data System (ADS)

Das, C.

1997-02-01

EUROPRACTICE is an EC initiative under the ESPRIT programme which aims to stimulate the wider exploitation of state-of-the-art microelectronics technologies by European industry and to enhance European industrial competitiveness in the global market-place. Through EUROPRACTICE, the EC has created a range of Basic Services that offer users a cost-effective and flexible means of accessing three main microelectronics-based technologies: Application Specific Integrated Circuit (ASICs), Multi-Chip Modules (MCMs) and Microsystems. EUROPRACTICE Basic Services reduce the cost and risk for companies wishing to begin using these technologies. EUROPRACTICE offers a fully supported, low cost route for companies to design and fabricate ASICs for their individual applications. Low cost is achieved by consolidating designs from many users onto a single semiconductor wafer (MPW: Multi Project Wafer). The EUROPRACTICE IC Manufacturing Service (ICMS) offers a broad range of fabrication technologies including CMOS, BiCMOS and GaAs. The Service extends from enabling users to produce prototype ASICs for testing and evaluation, through to low-volume production runs.

Universal microfluidic automaton for autonomous sample processing: application to the Mars Organic Analyzer.

PubMed

Kim, Jungkyu; Jensen, Erik C; Stockton, Amanda M; Mathies, Richard A

2013-08-20

A fully integrated multilayer microfluidic chemical analyzer for automated sample processing and labeling, as well as analysis using capillary zone electrophoresis is developed and characterized. Using lifting gate microfluidic control valve technology, a microfluidic automaton consisting of a two-dimensional microvalve cellular array is fabricated with soft lithography in a format that enables facile integration with a microfluidic capillary electrophoresis device. The programmable sample processor performs precise mixing, metering, and routing operations that can be combined to achieve automation of complex and diverse assay protocols. Sample labeling protocols for amino acid, aldehyde/ketone and carboxylic acid analysis are performed automatically followed by automated transfer and analysis by the integrated microfluidic capillary electrophoresis chip. Equivalent performance to off-chip sample processing is demonstrated for each compound class; the automated analysis resulted in a limit of detection of ~16 nM for amino acids. Our microfluidic automaton provides a fully automated, portable microfluidic analysis system capable of autonomous analysis of diverse compound classes in challenging environments.

Research of vibration controlling based on programmable logic controller for electrostatic precipitator

NASA Astrophysics Data System (ADS)

Zhang, Zisheng; Li, Yanhu; Li, Jiaojiao; Liu, Zhiqiang; Li, Qing

2013-03-01

In order to improve the reliability, stability and automation of electrostatic precipitator, circuits of vibration motor for ESP and vibration control ladder diagram program are investigated using Schneider PLC with high performance and programming software of Twidosoft. Operational results show that after adopting PLC, vibration motor can run automatically; compared with traditional control system of vibration based on single-chip microcomputer, it has higher reliability, better stability and higher dust removal rate, when dust emission concentrations <= 50 mg m-3, providing a new method for vibration controlling of ESP.

A Reconfigurable Communications System for Small Spacecraft

NASA Technical Reports Server (NTRS)

Chu, Pong P.; Kifle, Muli

2004-01-01

Two trends of NASA missions are the use of multiple small spacecraft and the development of an integrated space network. To achieve these goals, a robust and agile communications system is needed. Advancements in field programmable gate array (FPGA) technology have made it possible to incorporate major communication and network functionalities in FPGA chips; thus this technology has great potential as the basis for a reconfigurable communications system. This report discusses the requirements of future space communications, reviews relevant issues, and proposes a methodology to design and construct a reconfigurable communications system for small scientific spacecraft.

The design and implementation of signal decomposition system of CL multi-wavelet transform based on DSP builder

NASA Astrophysics Data System (ADS)

Huang, Yan; Wang, Zhihui

2015-12-01

With the development of FPGA, DSP Builder is widely applied to design system-level algorithms. The algorithm of CL multi-wavelet is more advanced and effective than scalar wavelets in processing signal decomposition. Thus, a system of CL multi-wavelet based on DSP Builder is designed for the first time in this paper. The system mainly contains three parts: a pre-filtering subsystem, a one-level decomposition subsystem and a two-level decomposition subsystem. It can be converted into hardware language VHDL by the Signal Complier block that can be used in Quartus II. After analyzing the energy indicator, it shows that this system outperforms Daubenchies wavelet in signal decomposition. Furthermore, it has proved to be suitable for the implementation of signal fusion based on SoPC hardware, and it will become a solid foundation in this new field.

Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

NASA Astrophysics Data System (ADS)

Yussup, N.; Ibrahim, M. M.; Lombigit, L.; Rahman, N. A. A.; Zin, M. R. M.

2014-02-01

Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of data acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed.

Implementation of data acquisition interface using on-board field-programmable gate array (FPGA) universal serial bus (USB) link

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yussup, N.; Ibrahim, M. M.; Lombigit, L.

Typically a system consists of hardware as the controller and software which is installed in the personal computer (PC). In the effective nuclear detection, the hardware involves the detection setup and the electronics used, with the software consisting of analysis tools and graphical display on PC. A data acquisition interface is necessary to enable the communication between the controller hardware and PC. Nowadays, Universal Serial Bus (USB) has become a standard connection method for computer peripherals and has replaced many varieties of serial and parallel ports. However the implementation of USB is complex. This paper describes the implementation of datamore » acquisition interface between a field-programmable gate array (FPGA) board and a PC by exploiting the USB link of the FPGA board. The USB link is based on an FTDI chip which allows direct access of input and output to the Joint Test Action Group (JTAG) signals from a USB host and a complex programmable logic device (CPLD) with a 24 MHz clock input to the USB link. The implementation and results of using the USB link of FPGA board as the data interfacing are discussed.« less

Assimilation of Biophysical Neuronal Dynamics in Neuromorphic VLSI.

PubMed

Wang, Jun; Breen, Daniel; Akinin, Abraham; Broccard, Frederic; Abarbanel, Henry D I; Cauwenberghs, Gert

2017-12-01

Representing the biophysics of neuronal dynamics and behavior offers a principled analysis-by-synthesis approach toward understanding mechanisms of nervous system functions. We report on a set of procedures assimilating and emulating neurobiological data on a neuromorphic very large scale integrated (VLSI) circuit. The analog VLSI chip, NeuroDyn, features 384 digitally programmable parameters specifying for 4 generalized Hodgkin-Huxley neurons coupled through 12 conductance-based chemical synapses. The parameters also describe reversal potentials, maximal conductances, and spline regressed kinetic functions for ion channel gating variables. In one set of experiments, we assimilated membrane potential recorded from one of the neurons on the chip to the model structure upon which NeuroDyn was designed using the known current input sequence. We arrived at the programmed parameters except for model errors due to analog imperfections in the chip fabrication. In a related set of experiments, we replicated songbird individual neuron dynamics on NeuroDyn by estimating and configuring parameters extracted using data assimilation from intracellular neural recordings. Faithful emulation of detailed biophysical neural dynamics will enable the use of NeuroDyn as a tool to probe electrical and molecular properties of functional neural circuits. Neuroscience applications include studying the relationship between molecular properties of neurons and the emergence of different spike patterns or different brain behaviors. Clinical applications include studying and predicting effects of neuromodulators or neurodegenerative diseases on ion channel kinetics.

A Front-End Electronics Prototype Based on Gigabit Ethernet for the ATLAS Small-Strip Thin Gap Chamber

NASA Astrophysics Data System (ADS)

Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Wang, Xinxin; Geng, Tianru; Yang, Hang; Liu, Shengquan; Han, Liang; Jin, Ge

2017-06-01

A front-end electronics prototype for the ATLAS small-strip Thin Gap Chamber (sTGC) based on gigabit Ethernet has been developed. The prototype is designed to read out signals of pads, wires, and strips of the sTGC detector. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 field-programmable gate array (FPGA) used for the VMM2 configuration and the events storage, and a gigabit Ethernet transceiver PHY chip for interfacing with a computer. The VMM2 chip is designed for the readout of the Micromegas detector and sTGC detector, which is composed of 64 linear front-end channels. Each channel integrates a charge-sensitive amplifier, a shaper, several analog-to-digital converters, and other digital functions. For a bunch-crossing interval of 25 ns, events are continuously read out by the FPGA and forwarded to the computer. The interface between the computer and the prototype has been measured to reach an error-free rate of 900 Mb/s, therefore making a very effective use of the available bandwidth. Additionally, the computer can control several prototypes of this kind simultaneously via the Ethernet interface. At present, the prototype will be used for the sTGC performance test. The features of the prototype are described in detail.

A dipole-assisted solid-phase extraction microchip combined with inductively coupled plasma-mass spectrometry for online determination of trace heavy metals in natural water.

PubMed

Shih, Tsung-Ting; Hsu, I-Hsiang; Chen, Shun-Niang; Chen, Ping-Hung; Deng, Ming-Jay; Chen, Yu; Lin, Yang-Wei; Sun, Yuh-Chang

2015-01-21

We employed a polymeric material, poly(methyl methacrylate) (PMMA), for fabricating a microdevice and then implanted the chlorine (Cl)-containing solid-phase extraction (SPE) functionality into the PMMA chip to develop an innovative on-chip dipole-assisted SPE technique. Instead of the ion-ion interactions utilized in on-chip SPE techniques, the dipole-ion interactions between the highly electronegative C-Cl moieties in the channel interior and the positively charged metal ions were employed to facilitate the on-chip SPE procedures. Furthermore, to avoid labor-intensive manual manipulation, a programmable valve manifold was designed as an interface combining the dipole-assisted SPE microchip and inductively coupled plasma-mass spectrometry (ICP-MS) to achieve the fully automated operation. Under the optimized operation conditions for the established system, the detection limits for each analyte ion were obtained based on three times the standard deviation of seven measurements of the blank eluent solution. The limits ranged from 3.48 to 20.68 ng L(-1), suggesting that this technique appears uniquely suited for determining the levels of heavy metal ions in natural water. Indeed, a series of validation procedures demonstrated that the developed method could be satisfactorily applied to the determination of trace heavy metals in natural water. Remarkably, the developed device was durable enough to be reused more than 160 times without any loss in its analytical performance. To the best of our knowledge, this is the first study reporting on the combination of a dipole-assisted SPE microchip and elemental analysis instrument for the online determination of trace heavy metal ions.

Design and implementation of projects with Xilinx Zynq FPGA: a practical case

NASA Astrophysics Data System (ADS)

Travaglini, R.; D'Antone, I.; Meneghini, S.; Rignanese, L.; Zuffa, M.

The main advantage when using FPGAs with embedded processors is the availability of additional several high-performance resources in the same physical device. Moreover, the FPGA programmability allows for connect custom peripherals. Xilinx have designed a programmable device named Zynq-7000 (simply called Zynq in the following), which integrates programmable logic (identical to the other Xilinx "serie 7" devices) with a System on Chip (SOC) based on two embedded ARM processors. Since both parts are deeply connected, the designers benefit from performance of hardware SOC and flexibility of programmability as well. In this paper a design developed by the Electronic Design Department at the Bologna Division of INFN will be presented as a practical case of project based on Zynq device. It is developed by using a commercial board called ZedBoard hosting a FMC mezzanine with a 12-bit 500 MS/s ADC. The Zynq FPGA on the ZedBoard receives digital outputs from the ADC and send them to the acquisition PC, after proper formatting, through a Gigabit Ethernet link. The major focus of the paper will be about the methodology to develop a Zynq-based design with the Xilinx Vivado software, enlightening how to configure the SOC and connect it with the programmable logic. Firmware design techniques will be presented: in particular both VHDL and IP core based strategies will be discussed. Further, the procedure to develop software for the embedded processor will be presented. Finally, some debugging tools, like the embedded Logic Analyzer, will be shown. Advantages and disadvantages with respect to adopting FPGA without embedded processors will be discussed.

Creating an Assured Joint DOD and Interagency Interoperable Net-Centric Enterprise. Report of the Defense Science Board Task Force on Achieving Interoperability in a Net-Centric Environment

DTIC Science & Technology

2009-03-01

policy, elliptic curve public key cryptography using the 256 -bit prime modulus elliptic curve as specified in FIPS-186-2 and SHA - 256 are appropriate for...publications/fips/fips186-2/fips186-2-change1.pdf 76 I P ART I . CH A PT E R 5 Hashing via the Secure Hash Algorithm (using SHA - 256 and...lithography and processing techniques. Field programmable gate arrays ( FPGAs ) are a chip design of interest. These devices are extensively used in

Special purpose computer system with highly parallel pipelines for flow visualization using holography technology

NASA Astrophysics Data System (ADS)

Masuda, Nobuyuki; Sugie, Takashige; Ito, Tomoyoshi; Tanaka, Shinjiro; Hamada, Yu; Satake, Shin-ichi; Kunugi, Tomoaki; Sato, Kazuho

2010-12-01

We have designed a PC cluster system with special purpose computer boards for visualization of fluid flow using digital holographic particle tracking velocimetry (DHPTV). In this board, there is a Field Programmable Gate Array (FPGA) chip in which is installed a pipeline for calculating the intensity of an object from a hologram by fast Fourier transform (FFT). This cluster system can create 1024 reconstructed images from a 1024×1024-grid hologram in 0.77 s. It is expected that this system will contribute to the analysis of fluid flow using DHPTV.

CCD correlation techniques

NASA Technical Reports Server (NTRS)

Hewes, C. R.; Bosshart, P. W.; Eversole, W. L.; Dewit, M.; Buss, D. D.

1976-01-01

Two CCD techniques were discussed for performing an N-point sampled data correlation between an input signal and an electronically programmable reference function. The design and experimental performance of an implementation of the direct time correlator utilizing two analog CCDs and MOS multipliers on a single IC were evaluated. The performance of a CCD implementation of the chirp z transform was described, and the design of a new CCD integrated circuit for performing correlation by multiplication in the frequency domain was presented. This chip provides a discrete Fourier transform (DFT) or inverse DFT, multipliers, and complete support circuitry for the CCD CZT. The two correlation techniques are compared.

A Hardware Platform for Tuning of MEMS Devices Using Closed-Loop Frequency Response

NASA Technical Reports Server (NTRS)

Ferguson, Michael I.; MacDonald, Eric; Foor, David

2005-01-01

We report on the development of a hardware platform for integrated tuning and closed-loop operation of MEMS gyroscopes. The platform was developed and tested for the second generation JPL/Boeing Post-Resonator MEMS gyroscope. The control of this device is implemented through a digital design on a Field Programmable Gate Array (FPGA). A software interface allows the user to configure, calibrate, and tune the bias voltages on the micro-gyro. The interface easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip.

Aeroflex Technology as Class-Y Demonstrator

NASA Technical Reports Server (NTRS)

Suh, Jong-ook; Agarwal, Shri; Popelar, Scott

2014-01-01

Modern space field programmable gate array (FPGA) devices with increased functional density and operational frequency, such as Xilinx Virtex 4 (V4) and S (V5), are packaged in non-hermetic ceramic flip chip forms. These next generation space parts were not qualified to the MIL-PRF-38535 Qualified Manufacturer Listing (QML) class-V when they were released because class-V was only intended for hermetic parts. In order to bring Xilinx V5 type packages into the QML system, it was suggested that class-Y be set up as a new category. From 2010 through 2014, a JEDEC G12 task group developed screening and qualification requirements for Class-Y products. The Document Standardization Division of the Defense Logistics Agency (DLA) has completed an engineering practice study. In parallel with the class-Y efforts, the NASA Electronic Parts and Packaging (NEPP) program has funded JPL to study potential reliability issues of the class-Y products. The major hurdle of this task was the absence of adequate research samples. Figure 1-1 shows schematic diagrams of typical structures of class-Y type products. Typically, class-Y products are either in ceramic flip chip column grid array (CGA) or land grid array (LGA) form. In class-Y packages, underfill and heat spread adhesive materials are directly exposed to the spacecraft environment due to their non-hermeticity. One of the concerns originally raised was that the underfill material could degrade due to the spacecraft environment and negatively impact the reliability of the package. In order to study such issues, it was necessary to use ceramic daisy chain flip chip package samples so that continuity of flip chip solder bumps could be monitored during the reliability tests. However, none of the commercially available class-Y daisy chain parts had electrical connections through flip chip solder bumps; only solder columns were daisy chained, which made it impossible to test continuity of flip chip solder bumps without using extremely costly functional parts. Among space parts manufacturers who were interested in producing class-Y products, Aeroflex Microelectronic Solutions-HiRel had been developing assembly processes using their internal R&D classy type samples. In early 2012, JPL and Aeroflex initiated a collaboration to study reliability of the Aeroflex technology as a class-Y demonstrator.

Design of barrier bucket kicker control system

NASA Astrophysics Data System (ADS)

Ni, Fa-Fu; Wang, Yan-Yu; Yin, Jun; Zhou, De-Tai; Shen, Guo-Dong; Zheng, Yang-De.; Zhang, Jian-Chuan; Yin, Jia; Bai, Xiao; Ma, Xiao-Li

2018-05-01

The Heavy-Ion Research Facility in Lanzhou (HIRFL) contains two synchrotrons: the main cooler storage ring (CSRm) and the experimental cooler storage ring (CSRe). Beams are extracted from CSRm, and injected into CSRe. To apply the Barrier Bucket (BB) method on the CSRe beam accumulation, a new BB technology based kicker control system was designed and implemented. The controller of the system is implemented using an Advanced Reduced Instruction Set Computer (RISC) Machine (ARM) chip and a field-programmable gate array (FPGA) chip. Within the architecture, ARM is responsible for data presetting and floating number arithmetic processing. The FPGA computes the RF phase point of the two rings and offers more accurate control of the time delay. An online preliminary experiment on HIRFL was also designed to verify the functionalities of the control system. The result shows that the reference trigger point of two different sinusoidal RF signals for an arbitrary phase point was acquired with a matched phase error below 1° (approximately 2.1 ns), and the step delay time better than 2 ns were realized.

RASDR: Benchtop Demonstration of SDR for Radio Astronomy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vacaliuc, Bogdan; Oxley, Paul; Fields, David

The Society of Amateur Radio Astronomers (SARA) members present the benchtop version of RASDR, a Software Defined Radio (SDR) that is optimized for Radio Astronomy. RASDR has the potential to be a common digital receiver interface useful to many SARA members. This document describes the RASDR 0.0 , which provides digitized radio data to a backend computer through a USB 2.0 interface. A primary component of RASDR is the Lime Microsystems Femtocell chip which tunes from a 0.4-4 GHz center frequency with several selectable bandwidths from 0.75 MHz to 14 MHz. A second component is a board with a Complexmore » Programmable Logic Device (CPLD) chip that connects to the Femtocell and provides two USB connections to the backend computer. A third component is an analog balanced mixer up conversion section. Together these three components enable RASDR to tune from 0.015 MHz thru 3.8GHz of the radio frequency (RF) spectrum. We will demonstrate and discuss capabilities of the breadboard system and SARA members will be able to operate the unit hands-on throughout the workshop.« less

Image processing using Gallium Arsenide (GaAs) technology

NASA Technical Reports Server (NTRS)

Miller, Warner H.

1989-01-01

The need to increase the information return from space-borne imaging systems has increased in the past decade. The use of multi-spectral data has resulted in the need for finer spatial resolution and greater spectral coverage. Onboard signal processing will be necessary in order to utilize the available Tracking and Data Relay Satellite System (TDRSS) communication channel at high efficiency. A generally recognized approach to the increased efficiency of channel usage is through data compression techniques. The compression technique implemented is a differential pulse code modulation (DPCM) scheme with a non-uniform quantizer. The need to advance the state-of-the-art of onboard processing was recognized and a GaAs integrated circuit technology was chosen. An Adaptive Programmable Processor (APP) chip set was developed which is based on an 8-bit slice general processor. The reason for choosing the compression technique for the Multi-spectral Linear Array (MLA) instrument is described. Also a description is given of the GaAs integrated circuit chip set which will demonstrate that data compression can be performed onboard in real time at data rate in the order of 500 Mb/s.

Systems-on-chip approach for real-time simulation of wheel-rail contact laws

NASA Astrophysics Data System (ADS)

Mei, T. X.; Zhou, Y. J.

2013-04-01

This paper presents the development of a systems-on-chip approach to speed up the simulation of wheel-rail contact laws, which can be used to reduce the requirement for high-performance computers and enable simulation in real time for the use of hardware-in-loop for experimental studies of the latest vehicle dynamic and control technologies. The wheel-rail contact laws are implemented using a field programmable gate array (FPGA) device with a design that substantially outperforms modern general-purpose PC platforms or fixed architecture digital signal processor devices in terms of processing time, configuration flexibility and cost. In order to utilise the FPGA's parallel-processing capability, the operations in the contact laws algorithms are arranged in a parallel manner and multi-contact patches are tackled simultaneously in the design. The interface between the FPGA device and the host PC is achieved by using a high-throughput and low-latency Ethernet link. The development is based on FASTSIM algorithms, although the design can be adapted and expanded for even more computationally demanding tasks.

A Low-cost 4 Bit, 10 Giga-samples-per-second Analog-to-digital Converter Printed Circuit Board Assembly for FPGA-based Backends

NASA Astrophysics Data System (ADS)

Jiang, Homin; Yu, Chen-Yu; Kubo, Derek; Chen, Ming-Tang; Guzzino, Kim

2016-11-01

In this study, a 4 bit, 10 giga-samples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was designed, manufactured, and characterized for digitizing radio telescopes. For this purpose, an Adsantec ANST7120A-KMA flash ADC chip was used. Together with the field-programmable gate array platform, developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the PCBA enables data acquisition with a wide bandwidth and simplifies the intermediate frequency section. In the current version, the PCBA and the chip exhibit an analog bandwidth of 10 GHz (3 dB loss) and 20 GHz, respectively, which facilitates second, third, and even fourth Nyquist sampling. The following average performance parameters were obtained from the first and second Nyquist zones of the three boards: a spurious-free dynamic range of 31.35/30.45 dB, a signal-to-noise and distortion ratio of 22.95/21.83 dB, and an effective number of bits of 3.65/3.43, respectively.

A digital optical phase-locked loop for diode lasers based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xu Zhouxiang; Zhang Xian; Huang Kaikai

2012-09-15

We have designed and implemented a highly digital optical phase-locked loop (OPLL) for diode lasers in atom interferometry. The three parts of controlling circuit in this OPLL, including phase and frequency detector (PFD), loop filter and proportional integral derivative (PID) controller, are implemented in a single field programmable gate array chip. A structure type compatible with the model MAX9382/MCH12140 is chosen for PFD and pipeline and parallelism technology have been adapted in PID controller. Especially, high speed clock and twisted ring counter have been integrated in the most crucial part, the loop filter. This OPLL has the narrow beat notemore » line width below 1 Hz, residual mean-square phase error of 0.14 rad{sup 2} and transition time of 100 {mu}s under 10 MHz frequency step. A main innovation of this design is the completely digitalization of the whole controlling circuit in OPLL for diode lasers.« less

A programmable CCD driver circuit for multiphase CCD operation

NASA Technical Reports Server (NTRS)

Ewin, Audrey J.; Reed, Kenneth V.

1989-01-01

A programmable CCD (charge-coupled device) driver circuit was designed to drive CCDs in multiphased modes. The purpose of the drive electronics is to operate developmental CCD imaging arrays for NASA's tiltable moderate resolution imaging spectrometer (MODIS-T). Five objectives for the driver were considered during its design: (1) the circuit drives CCD electrode voltages between 0 V and +30 V to produce reasonable potential wells, (2) the driving sequence is started with one input signal, (3) the driving sequence is started with one input signal, (4) the circuit allows programming of frame sequences required by arrays of any size, (5) it produces interfacing signals for the CCD and the DTF (detector test facility). Simulation of the driver verified its function with the master clock running up to 10 MHz. This suggests a maximum rate of 400,000 pixels/s. Timing and packaging parameters were verified. The design uses 54 TTL (transistor-transistor logic) chips. Two versions of hardware were fabricated: wirewrap and printed circuit board. Both were verified functionally with a logic analyzer.

Filling the Assurance Gap on Complex Electronics

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled by software, such as communication protocols. For example, the James Webb Space Telescope will use Field Programmable Gate Arrays (FPGAs), which can have over a million logic gates, to send telemetry. System-on-chip (SoC) devices, another type of complex electronics, can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, mature software methodologies have been proposed, with slight modifications, to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and bugs can be detected earlier in the development cycle, thus creating a development process for CE that can be easily maintained and configurable based on the device used.

Software Process Assurance for Complex Electronics

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Complex Electronics (CE) now perform tasks that were previously handled in software, such as communication protocols. Many methods used to develop software bare a close resemblance to CE development. Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. With CE devices obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that used standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques were used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that was more easily maintained, consistent and configurable based on the device used.

Multipurpose silicon photonics signal processor core.

PubMed

Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José

2017-09-21

Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.

A programmable systolic array correlator as a trigger processor for electron pairs in rich (ring image Cherenkov) counters

NASA Astrophysics Data System (ADS)

Männer, R.

1989-12-01

This paper describes a systolic array processor for a ring image Cherenkov counter which is capable of identifying pairs of electron circles with a known radius and a certain minimum distance within 15 μs. The processor is a very flexible and fast device. It consists of 128 x 128 processing elements (PEs), where one PE is assigned to each pixel of the image. All PEs run synchronously at 40 MHz. The identification of electron circles is done by correlating the detector image with the proper circle circumference. Circle centers are found by peak detection in the correlation result. A second correlation with a circle disc allows circles of closed electron pairs to be rejected. The trigger decision is generated if a pseudo adder detects at least two remaining circles. The device is controlled by a freely programmable sequencer. A VLSI chip containing 8 x 8 PEs is being developed using a VENUS design system and will be produced in 2μ CMOS technology.

Media processors using a new microsystem architecture designed for the Internet era

NASA Astrophysics Data System (ADS)

Wyland, David C.

1999-12-01

The demands of digital image processing, communications and multimedia applications are growing more rapidly than traditional design methods can fulfill them. Previously, only custom hardware designs could provide the performance required to meet the demands of these applications. However, hardware design has reached a crisis point. Hardware design can no longer deliver a product with the required performance and cost in a reasonable time for a reasonable risk. Software based designs running on conventional processors can deliver working designs in a reasonable time and with low risk but cannot meet the performance requirements. What is needed is a media processing approach that combines very high performance, a simple programming model, complete programmability, short time to market and scalability. The Universal Micro System (UMS) is a solution to these problems. The UMS is a completely programmable (including I/O) system on a chip that combines hardware performance with the fast time to market, low cost and low risk of software designs.

Detecting Molecular Signatures of Life on Mars: the Life Marker Chip (lmc) Instrument

NASA Astrophysics Data System (ADS)

Derveni, Mariliza

In recent years, the rise of interest in planetary exploration and the emergence of Astrobiology as a promising field of research have lead to a number of programmes aiming to develop sensitive instruments for the detection of the molecular signatures of life in extreme environments. An antibody assay-based life detection instrument, the Life Marker Chip (LMC), is currently under development by a UK-lead international consortium for the European Space Agency's (ESA) ExoMars rover. This forms part of the joint ESA/NASA Mars exploration programme with the ExoMars Rover currently scheduled for launch in 2018. The organic molecules targeted for Life detection by the LMC are based on an assumption of "Earth-like" Life on Mars -extinct and/or extant. The molecular targets for the LMC have been chosen to represent markers of extinct Life, extant Life, abiotic chemistry (e.g. of meteoritic origin) and mission-borne Earth contamination. The LMC incorporates integrated liquid sample extraction and processing for dry Martian samples, which will be collected from up to 2m below the surface of Mars, where organic molecules, if present, are expected to be better preserved. The core technology of the LMC is a combination of optical evanescent waveguides, micro-fluidics, immuno-microarrays with fluorescent labels and CCD detector readout. Phage display recombinant antibody technology has been employed in order to acquire antibodies against a number of the LMC target molecules. The LMC hardware is currently in a breadboard phase of development. The recombinant antibody development for LMC targets is an on-going project, and testing of Earth-analogue Martian samples has been initiated

From neural-based object recognition toward microelectronic eyes

NASA Technical Reports Server (NTRS)

Sheu, Bing J.; Bang, Sa Hyun

1994-01-01

Engineering neural network systems are best known for their abilities to adapt to the changing characteristics of the surrounding environment by adjusting system parameter values during the learning process. Rapid advances in analog current-mode design techniques have made possible the implementation of major neural network functions in custom VLSI chips. An electrically programmable analog synapse cell with large dynamic range can be realized in a compact silicon area. New designs of the synapse cells, neurons, and analog processor are presented. A synapse cell based on Gilbert multiplier structure can perform the linear multiplication for back-propagation networks. A double differential-pair synapse cell can perform the Gaussian function for radial-basis network. The synapse cells can be biased in the strong inversion region for high-speed operation or biased in the subthreshold region for low-power operation. The voltage gain of the sigmoid-function neurons is externally adjustable which greatly facilitates the search of optimal solutions in certain networks. Various building blocks can be intelligently connected to form useful industrial applications. Efficient data communication is a key system-level design issue for large-scale networks. We also present analog neural processors based on perceptron architecture and Hopfield network for communication applications. Biologically inspired neural networks have played an important role towards the creation of powerful intelligent machines. Accuracy, limitations, and prospects of analog current-mode design of the biologically inspired vision processing chips and cellular neural network chips are key design issues.

Prototype of a gigabit data transmitter in 65 nm CMOS for DEPFET pixel detectors at Belle-II

NASA Astrophysics Data System (ADS)

Kishishita, T.; Krüger, H.; Hemperek, T.; Lemarenko, M.; Koch, M.; Gronewald, M.; Wermes, N.

2013-08-01

This paper describes the recent development of a gigabit data transmitter for the Belle-II pixel detector (PXD). The PXD is an innermost detector currently under development for the upgraded KEK-B factory in Japan. The PXD consists of two layers of DEPFET sensor modules located at 1.8 and 2.2 cm radii. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique: (a) SWITCHER for generating steering signals for the DEPFET sensors, (b) DCD for digitizing the signal currents, and (c) DHP for performing data processing and sending the data off the module to the back-end data handling hybrid via ∼ 40 cm Kapton flex and 12-15 m twisted pair (TWP) cables. To meet the requirements of the PXD data transmission, a prototype of the DHP data transmitter has been developed in a 65-nm standard CMOS technology. The transmitter test chip consists of current-mode logic (CML) drivers and a phase-locked loop (PLL) which generates a clock signal for a 1.6 Gbit/s output data stream from an 80 cm reference clock. A programmable pre-emphasis circuit is also implemented in the CML driver to compensate signal losses in the long cable by shaping the transmitted pulse response. The jitter performance was measured as 25 ps (1 σ distribution) by connecting the chip with 38 cm flex and 10 m TWP cables.

Design of 90×8 ROIC with pixel level digital TDI implementation for scanning type LWIR FPAs

NASA Astrophysics Data System (ADS)

Ceylan, Omer; Kayahan, Huseyin; Yazici, Melik; Gurbuz, Yasar

2013-06-01

Design of a 90×8 CMOS readout integrated circuit (ROIC) based on pixel level digital time delay integration (TDI) for scanning type LWIR focal plane arrays (FPAs) is presented. TDI is implemented on 8 pixels which improves the SNR of the system with a factor of √8. Oversampling rate of 3 improves the spatial resolution of the system. TDI operation is realized with a novel under-pixel analog-to-digital converter, which improves the noise performance of ROIC with a lower quantization noise. Since analog signal is converted to digital domain in-pixel, non-uniformities and inaccuracies due to analog signal routing over large chip area is eliminated. Contributions of each pixel for proper TDI operation are added in summation counters, no op-amps are used for summation, hence power consumption of ROIC is lower than its analog counterparts. Due to lack of multiple capacitors or summation amplifiers, ROIC occupies smaller chip area compared to its analog counterparts. ROIC is also superior to its digital counterparts due to novel digital TDI implementation in terms of power consumption, noise and chip area. ROIC supports bi-directional scan, multiple gain settings, bypass operation, automatic gain adjustment, pixel select/deselect, and is programmable through serial or parallel interface. Input referred noise of ROIC is less than 750 rms electrons, while power consumption is less than 20mW. ROIC is designed to perform both in room and cryogenic temperatures.

Ultrasound phase rotation beamforming on multi-core DSP.

PubMed

Ma, Jieming; Karadayi, Kerem; Ali, Murtaza; Kim, Yongmin

2014-01-01

Phase rotation beamforming (PRBF) is a commonly-used digital receive beamforming technique. However, due to its high computational requirement, it has traditionally been supported by hardwired architectures, e.g., application-specific integrated circuits (ASICs) or more recently field-programmable gate arrays (FPGAs). In this study, we investigated the feasibility of supporting software-based PRBF on a multi-core DSP. To alleviate the high computing requirement, the analog front-end (AFE) chips integrating quadrature demodulation in addition to analog-to-digital conversion were defined and used. With these new AFE chips, only delay alignment and phase rotation need to be performed by DSP, substantially reducing the computational load. We implemented the delay alignment and phase rotation modules on a Texas Instruments C6678 DSP with 8 cores. We found it takes 200 μs to beamform 2048 samples from 64 channels using 2 cores. With 4 cores, 20 million samples can be beamformed in one second. Therefore, ADC frequencies up to 40 MHz with 2:1 decimation in AFE chips or up to 20 MHz with no decimation can be supported as long as the ADC-to-DSP I/O requirement can be met. The remaining 4 cores can work on back-end processing tasks and applications, e.g., color Doppler or ultrasound elastography. One DSP being able to handle both beamforming and back-end processing could lead to low-power and low-cost ultrasound machines, benefiting ultrasound imaging in general, particularly portable ultrasound machines. Copyright © 2013 Elsevier B.V. All rights reserved.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Data Acquisition System for Silicon Ultra Fast Cameras for Electron and Gamma Sources in Medical Applications (sucima Imager)

NASA Astrophysics Data System (ADS)

Czermak, A.; Zalewska, A.; Dulny, B.; Sowicki, B.; Jastrząb, M.; Nowak, L.

2004-07-01

The needs for real time monitoring of the hadrontherapy beam intensity and profile as well as requirements for the fast dosimetry using Monolithic Active Pixel Sensors (MAPS) forced the SUCIMA collaboration to the design of the unique Data Acquisition System (DAQ SUCIMA Imager). The DAQ system has been developed on one of the most advanced XILINX Field Programmable Gate Array chip - VERTEX II. The dedicated multifunctional electronic board for the detector's analogue signals capture, their parallel digital processing and final data compression as well as transmission through the high speed USB 2.0 port has been prototyped and tested.

Does maltose influence on the elasticity of SOPC membrane?

NASA Astrophysics Data System (ADS)

Genova, J.; Zheliaskova, A.; Mitov, M. D.

2010-11-01

Thermally induced shape fluctuations of giant quasi-spherical lipid vesicles are used to study the influence of the disaccharide maltose, dissolved in the aqueous solution, on the curvature elasticity kc of a lipid membrane. The influence of the carbohydrate solute is investigated throughout a considerably wide interval of concentrations. The values of the bending elastic modulus for 200 mM and 400 mM of maltose in the water solution are obtained. The data for kc in presence of maltose is compared with previously obtained results for this constant for the most popular hydrocarbons: monosaccharides glucose and fructose and disaccharides sucrose and trehalose. It is shown that the presence of maltose, dissolved in the aqueous phase surrounding the membrane does not influence on the bending elasticity with the increase of its concentration in the aqueous solution. Up to our knowledge this is the first sugar that does not show decrease of the bending elastic modulus of the lipid membrane, when present in the water surrounding it in concentration up to 400mM.

Hot embossed polyethylene through-hole chips for bead-based microfluidic devices

PubMed Central

Chou, Jie; Du, Nan; Ou, Tina; Floriano, Pierre N.; Christodoulides, Nicolaos; McDevitt, John T.

2013-01-01

Over the past decade, there has been a growth of interest in the translation of microfluidic systems into real-world clinical practice, especially for use in point-of-care or near patient settings. While initial fabrication advances in microfluidics involved mainly the etching of silicon and glass, the economics of scaling of these materials is not amendable for point-of-care usage where single-test applications forces cost considerations to be kept low and throughput high. As such, a materials base more consistent with point-of-care needs is required. In this manuscript, the fabrication of a hot embossed, through-hole low-density polyethylene ensembles derived from an anisotropically etched silicon wafer is discussed. This semi-opaque polymer that can be easily sterilized and recycled provides low background noise for fluorescence measurements and yields more affordable cost than other thermoplastics commonly used for microfluidic applications such as cyclic olefin copolymer (COC). To fabrication through-hole microchips from this alternative material for microfluidics, a fabrication technique that uses a high-temperature, high-pressure resistant mold is described. This aluminum-based epoxy mold, serving as the positive master mold for embossing, is casted over etched arrays of pyramidal pits in a silicon wafer. Methods of surface treatment of the wafer prior to casting and PDMS casting of the epoxy are discussed to preserve the silicon wafer for future use. Changes in the thickness of polyethylene are observed for varying embossing temperatures. The methodology described herein can quickly fabricate 20 disposable, single use chips in less than 30 minutes with the ability to scale up 4x by using multiple molds simultaneously. When coupled as a platform supporting porous bead sensors, as in the recently developed Programmable Bio-Nano-Chip, this bead chip system can achieve limits of detection, for the cardiac biomarker C-reactive protein, of 0.3 ng/mL, thereby demonstrating the approach is compatible with high performance, real-world clinical measurements in the context of point-of-care testing. PMID:23183187

Exponential current pulse generation for efficient very high-impedance multisite stimulation.

PubMed

Ethier, S; Sawan, M

2011-02-01

We describe in this paper an intracortical current-pulse generator for high-impedance microstimulation. This dual-chip system features a stimuli generator and a high-voltage electrode driver. The stimuli generator produces flexible rising exponential pulses in addition to standard rectangular stimuli. This novel stimulation waveform is expected to provide superior energy efficiency for action potential triggering while releasing less toxic reduced ions in the cortical tissues. The proposed fully integrated electrode driver is used as the output stage where high-voltage supplies are generated on-chip to significantly increase the voltage compliance for stimulation through high-impedance electrode-tissue interfaces. The stimuli generator has been implemented in 0.18-μm CMOS technology while a 0.8-μm CMOS/DMOS process has been used to integrate the high-voltage output stage. Experimental results show that the rectangular pulses cover a range of 1.6 to 167.2 μA with a DNL and an INL of 0.098 and 0.163 least-significant bit, respectively. The maximal dynamic range of the generated exponential reaches 34.36 dB at full scale within an error of ± 0.5 dB while all of its parameters (amplitude, duration, and time constant) are independently programmable over wide ranges. This chip consumes a maximum of 88.3 μ W in the exponential mode. High-voltage supplies of 8.95 and -8.46 V are generated by the output stage, boosting the voltage swing up to 13.6 V for a load as high as 100 kΩ.

ASIC implementation of recursive scaled discrete cosine transform algorithm

NASA Astrophysics Data System (ADS)

On, Bill N.; Narasimhan, Sam; Huang, Victor K.

1994-05-01

A program to implement the Recursive Scaled Discrete Cosine Transform (DCT) algorithm as proposed by H. S. Hou has been undertaken at the Institute of Microelectronics. Implementation of the design was done using top-down design methodology with VHDL (VHSIC Hardware Description Language) for chip modeling. When the VHDL simulation has been satisfactorily completed, the design is synthesized into gates using a synthesis tool. The architecture of the design consists of two processing units together with a memory module for data storage and transpose. Each processing unit is composed of four pipelined stages which allow the internal clock to run at one-eighth (1/8) the speed of the pixel clock. Each stage operates on eight pixels in parallel. As the data flows through each stage, there are various adders and multipliers to transform them into the desired coefficients. The Scaled IDCT was implemented in a similar fashion with the adders and multipliers rearranged to perform the inverse DCT algorithm. The chip has been verified using Field Programmable Gate Array devices. The design is operational. The combination of fewer multiplications required and pipelined architecture give Hou's Recursive Scaled DCT good potential of achieving high performance at a low cost in using Very Large Scale Integration implementation.

Low-cost feedback-controlled syringe pressure pumps for microfluidics applications.

PubMed

Lake, John R; Heyde, Keith C; Ruder, Warren C

2017-01-01

Microfluidics are widely used in research ranging from bioengineering and biomedical disciplines to chemistry and nanotechnology. As such, there are a large number of options for the devices used to drive and control flow through microfluidic channels. Commercially available syringe pumps are probably the most commonly used instruments for this purpose, but are relatively high-cost and have inherent limitations due to their flow profiles when they are run open-loop. Here, we present a low-cost ($110) syringe pressure pump that uses feedback control to regulate the pressure into microfluidic chips. Using an open-source microcontroller board (Arduino), we demonstrate an easily operated and programmable syringe pump that can be run using either a PID or bang-bang control method. Through feedback control of the pressure at the inlets of two microfluidic geometries, we have shown stability of our device to within ±1% of the set point using a PID control method and within ±5% of the set point using a bang-bang control method with response times of less than 1 second. This device offers a low-cost option to drive and control well-regulated pressure-driven flow through microfluidic chips.

Low Power Near Field Communication Methods for RFID Applications of SIM Cards.

PubMed

Chen, Yicheng; Zheng, Zhaoxia; Gong, Mingyang; Yu, Fengqi

2017-04-14

Power consumption and communication distance have become crucial challenges for SIM card RFID (radio frequency identification) applications. The combination of long distance 2.45 GHz radio frequency (RF) technology and low power 2 kHz near distance communication is a workable scheme. In this paper, an ultra-low frequency 2 kHz near field communication (NFC) method suitable for SIM cards is proposed and verified in silicon. The low frequency transmission model based on electromagnetic induction is discussed. Different transmission modes are introduced and compared, which show that the baseband transmit mode has a better performance. The low-pass filter circuit and programmable gain amplifiers are applied for noise reduction and signal amplitude amplification. Digital-to-analog converters and comparators are used to judge the card approach and departure. A novel differential Manchester decoder is proposed to deal with the internal clock drift in range-controlled communication applications. The chip has been fully implemented in 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology, with a 330 µA work current and a 45 µA idle current. The low frequency chip can be integrated into a radio frequency SIM card for near field RFID applications.

A Fully-Implantable Cochlear Implant SoC with Piezoelectric Middle-Ear Sensor and Arbitrary Waveform Neural Stimulation.

PubMed

Yip, Marcus; Jin, Rui; Nakajima, Hideko Heidi; Stankovic, Konstantina M; Chandrakasan, Anantha P

2015-01-01

A system-on-chip for an invisible, fully-implantable cochlear implant is presented. Implantable acoustic sensing is achieved by interfacing the SoC to a piezoelectric sensor that detects the sound-induced motion of the middle ear. Measurements from human cadaveric ears demonstrate that the sensor can detect sounds between 40 and 90 dB SPL over the speech bandwidth. A highly-reconfigurable digital sound processor enables system power scalability by reconfiguring the number of channels, and provides programmable features to enable a patient-specific fit. A mixed-signal arbitrary waveform neural stimulator enables energy-optimal stimulation pulses to be delivered to the auditory nerve. The energy-optimal waveform is validated with in-vivo measurements from four human subjects which show a 15% to 35% energy saving over the conventional rectangular waveform. Prototyped in a 0.18 μ m high-voltage CMOS technology, the SoC in 8-channel mode consumes 572 μ W of power including stimulation. The SoC integrates implantable acoustic sensing, sound processing, and neural stimulation on one chip to minimize the implant size, and proof-of-concept is demonstrated with measurements from a human cadaver ear.

Ultrasensitive microfluidic solid-phase ELISA using an actuatable microwell-patterned PDMS chip.

PubMed

Wang, Tanyu; Zhang, Mohan; Dreher, Dakota D; Zeng, Yong

2013-11-07

Quantitative detection of low abundance proteins is of significant interest for biological and clinical applications. Here we report an integrated microfluidic solid-phase ELISA platform for rapid and ultrasensitive detection of proteins with a wide dynamic range. Compared to the existing microfluidic devices that perform affinity capture and enzyme-based optical detection in a constant channel volume, the key novelty of our design is two-fold. First, our system integrates a microwell-patterned assay chamber that can be pneumatically actuated to significantly reduce the volume of chemifluorescent reaction, markedly improving the sensitivity and speed of ELISA. Second, monolithic integration of on-chip pumps and the actuatable assay chamber allow programmable fluid delivery and effective mixing for rapid and sensitive immunoassays. Ultrasensitive microfluidic ELISA was demonstrated for insulin-like growth factor 1 receptor (IGF-1R) across at least five orders of magnitude with an extremely low detection limit of 21.8 aM. The microwell-based solid-phase ELISA strategy provides an expandable platform for developing the next-generation microfluidic immunoassay systems that integrate and automate digital and analog measurements to further improve the sensitivity, dynamic ranges, and reproducibility of proteomic analysis.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

NASA Astrophysics Data System (ADS)

De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing.

PubMed

De Matteis, M; De Blasi, M; Vallicelli, E A; Zannoni, M; Gervasi, M; Bau, A; Passerini, A; Baschirotto, A

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μm technology (12 mm 2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

On-chip skin color detection using a triple-well CMOS process

NASA Astrophysics Data System (ADS)

Boussaid, Farid; Chai, Douglas; Bouzerdoum, Abdesselam

2004-03-01

In this paper, a current-mode VLSI architecture enabling on read-out skin detection without the need for any on-chip memory elements is proposed. An important feature of the proposed architecture is that it removes the need for demosaicing. Color separation is achieved using the strong wavelength dependence of the absorption coefficient in silicon. This wavelength dependence causes a very shallow absorption of blue light and enables red light to penetrate deeply in silicon. A triple-well process, allowing a P-well to be placed inside an N-well, is chosen to fabricate three vertically integrated photodiodes acting as the RGB color detector for each pixel. Pixels of an input RGB image are classified as skin or non-skin pixels using a statistical skin color model, chosen to offer an acceptable trade-off between skin detection performance and implementation complexity. A single processing unit is used to classify all pixels of the input RGB image. This results in reduced mismatch and also in an increased pixel fill-factor. Furthermore, the proposed current-mode architecture is programmable, allowing external control of all classifier parameters to compensate for mismatch and changing lighting conditions.

A digitally controlled AGC loop circuitry for GNSS receiver chip with a binary weighted accurate dB-linear PGA

NASA Astrophysics Data System (ADS)

Gang, Jin; Yiqi, Zhuang; Yue, Yin; Miao, Cui

2015-03-01

A novel digitally controlled automatic gain control (AGC) loop circuitry for the global navigation satellite system (GNSS) receiver chip is presented. The entire AGC loop contains a programmable gain amplifier (PGA), an AGC circuit and an analog-to-digital converter (ADC), which is implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process and measured. A binary-weighted approach is proposed in the PGA to achieve wide dB-linear gain control with small gain error. With binary-weighted cascaded amplifiers for coarse gain control, and parallel binary-weighted trans-conductance amplifier array for fine gain control, the PGA can provide a 64 dB dynamic range from -4 to 60 dB in 1.14 dB gain steps with a less than 0.15 dB gain error. Based on the Gaussian noise statistic characteristic of the GNSS signal, a digital AGC circuit is also proposed with low area and fast settling. The feed-backward AGC loop occupies an area of 0.27 mm2 and settles within less than 165 μs while consuming an average current of 1.92 mA at 1.8 V.

Special-purpose computer for holography HORN-4 with recurrence algorithm

NASA Astrophysics Data System (ADS)

Shimobaba, Tomoyoshi; Hishinuma, Sinsuke; Ito, Tomoyoshi

2002-10-01

We designed and built a special-purpose computer for holography, HORN-4 (HOlographic ReconstructioN) using PLD (Programmable Logic Device) technology. HORN computers have a pipeline architecture. We use HORN-4 as an attached processor to enhance the performance of a general-purpose computer when it is used to generate holograms using a "recurrence formulas" algorithm developed by our previous paper. In the HORN-4 system, we designed the pipeline by adopting our "recurrence formulas" algorithm which can calculate the phase on a hologram. As the result, we could integrate the pipeline composed of 21 units into one PLD chip. The units in the pipeline consists of one BPU (Basic Phase Unit) unit and twenty CU (Cascade Unit) units. These CU units can compute twenty light intensities on a hologram plane at one time. By mounting two of the PLD chips on a PCI (Peripheral Component Interconnect) universal board, HORN-4 can calculate holograms at high speed of about 42 Gflops equivalent. The cost of HORN-4 board is about 1700 US dollar. We could obtain 800×600 grids hologram from a 3D-image composed of 415 points in about 0.45 sec with the HORN-4 system.

Low-cost feedback-controlled syringe pressure pumps for microfluidics applications

PubMed Central

Lake, John R.; Heyde, Keith C.

2017-01-01

Microfluidics are widely used in research ranging from bioengineering and biomedical disciplines to chemistry and nanotechnology. As such, there are a large number of options for the devices used to drive and control flow through microfluidic channels. Commercially available syringe pumps are probably the most commonly used instruments for this purpose, but are relatively high-cost and have inherent limitations due to their flow profiles when they are run open-loop. Here, we present a low-cost ($110) syringe pressure pump that uses feedback control to regulate the pressure into microfluidic chips. Using an open-source microcontroller board (Arduino), we demonstrate an easily operated and programmable syringe pump that can be run using either a PID or bang-bang control method. Through feedback control of the pressure at the inlets of two microfluidic geometries, we have shown stability of our device to within ±1% of the set point using a PID control method and within ±5% of the set point using a bang-bang control method with response times of less than 1 second. This device offers a low-cost option to drive and control well-regulated pressure-driven flow through microfluidic chips. PMID:28369134

A self-timed multipurpose delay sensor for Field Programmable Gate Arrays (FPGAs).

PubMed

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2013-12-20

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of  ±0.67 °C, over the range of 20-100 °C, employing 20 logic elements with a 2-point calibration.

A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs)

PubMed Central

Osuna, Carlos Gómez; Ituero, Pablo; López-Vallejo, Marisa

2014-01-01

This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor's measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of ±0.67 °C, over the range of 20–100 °C, employing 20 logic elements with a 2-point calibration. PMID:24361927

Software Process Assurance for Complex Electronics (SPACE)

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Complex Electronics (CE) are now programmed to perform tasks that were previously handled in software, such as communication protocols. Many of the methods used to develop software bare a close resemblance to CE development. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that looks at using standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques can be used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that will be more easily maintained, consistent and configurable based on the device used.

Design of resolution/power controllable Asynchronous Sigma-Delta Modulator

NASA Astrophysics Data System (ADS)

Deshmukh, Anita Arvind; Deshmukh, Raghvendra B.

2016-12-01

This paper presents the design of a Programmable Asynchronous Modulator (PAM) with field control of resolution and power. A novel variable hysteresis Schmitt Trigger (ST) is used for external programmability. Asynchronous Sigma-Delta Modulator (ASDM) implementation with external control voltages is proposed to supervise the resolution and power. This architecture with reduced circuit complexity considerably improves the earlier realizations by eliminating multiple current sources as well switched capacitor circuits and results in power saving up to 87 %. Proposed PAM design demonstrates an improved SNDR of 115 dB, DR of 96 dB, and power consumption below 280 μW. It illustrates Effective Number of Bits (ENOB) to 18.81 and Figure of Merit (FoM) to 0.15 fJ/conversion step. Modulator is implemented in Cadence UMC Hspice 0.18 μm CMOS analog technology. Off-chip PAM control for resolution/power performance has potential applications in battery operated ultra low power applications like IoT; where ADC is one of the major power consuming components. It offers the promise for an efficient performance with power saving.

Optoelectronic analogs of self-programming neural nets - Architecture and methodologies for implementing fast stochastic learning by simulated annealing

NASA Technical Reports Server (NTRS)

Farhat, Nabil H.

1987-01-01

Self-organization and learning is a distinctive feature of neural nets and processors that sets them apart from conventional approaches to signal processing. It leads to self-programmability which alleviates the problem of programming complexity in artificial neural nets. In this paper architectures for partitioning an optoelectronic analog of a neural net into distinct layers with prescribed interconnectivity pattern to enable stochastic learning by simulated annealing in the context of a Boltzmann machine are presented. Stochastic learning is of interest because of its relevance to the role of noise in biological neural nets. Practical considerations and methodologies for appreciably accelerating stochastic learning in such a multilayered net are described. These include the use of parallel optical computing of the global energy of the net, the use of fast nonvolatile programmable spatial light modulators to realize fast plasticity, optical generation of random number arrays, and an adaptive noisy thresholding scheme that also makes stochastic learning more biologically plausible. The findings reported predict optoelectronic chips that can be used in the realization of optical learning machines.

A high-resolution programmable Vernier delay generator based on carry chains in FPGA

NASA Astrophysics Data System (ADS)

Cui, Ke; Li, Xiangyu; Zhu, Rihong

2017-06-01

This paper presents an architecture of a high-resolution delay generator implemented in a single field programmable gate array chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in various physical instruments. The proposed delay generator contains the coarse delay step and the fine delay step to guarantee both large dynamic range and high resolution. The carry chains are organized in the Vernier delay loop style to fulfill the fine delay step with high precision and high linearity. The delay generator was implemented in the EP3SE110F1152I3 Stratix III device from Altera on a self-designed test board. Test results show that the obtained resolution is 38.6 ps, and the differential nonlinearity/integral nonlinearity is in the range of [-0.18 least significant bit (LSB), 0.24 LSB]/(-0.02 LSB, 0.01 LSB) under the nominal supply voltage of 1100 mV and environmental temperature of 2 0°C. The delay generator is rather efficient concerning resource cost, which uses only 668 look-up tables and 146 registers in total.

Pharmacokinetics-on-a-Chip Using Label-Free SERS Technique for Programmable Dual-Drug Analysis.

PubMed

Fei, Jiayuan; Wu, Lei; Zhang, Yizhi; Zong, Shenfei; Wang, Zhuyuan; Cui, Yiping

2017-06-23

Synergistic effects of dual or multiple drugs have attracted great attention in medical fields, especially in cancer therapies. We provide a programmable microfluidic platform for pharmacokinetic detection of multiple drugs in multiple cells. The well-designed microfluidic platform includes two 2 × 3 microarrays of cell chambers, two gradient generators, and several pneumatic valves. Through the combined use of valves and gradient generators, each chamber can be controlled to infuse different kinds of living cells and drugs with specific concentrations as needed. In our experiments, 6-mercaptopurine (6MP) and methimazole (MMI) were chosen as two drug models and their pharmacokinetic parameters in different living cells were monitored through intracellular SERS spectra, which reflected the molecular structure of these drugs. The dynamic change of SERS fingerprints from 6MP and MMI molecules were recorded during drug metabolism in living cells. The results indicated that both 6MP and MMI molecules were diffused into the cells within 4 min and excreted out after 36 h. Moreover, the intracellular distribution of these drugs was monitored through SERS mapping. Thus, our microfluidic platform simultaneously accomplishes the functions to monitor pharmacokinetic action, distribution, and fingerprint of multiple drugs in multiple cells. Owing to its real-time, rapid-speed, high-precision, and programmable capability of multiple-drug and multicell analysis, such a microfluidic platform has great potential in drug design and development.

A wideband software reconfigurable modem

NASA Astrophysics Data System (ADS)

Turner, J. H., Jr.; Vickers, H.

A wideband modem is described which provides signal processing capability for four Lx-band signals employing QPSK, MSK and PPM waveforms and employs a software reconfigurable architecture for maximum system flexibility and graceful degradation. The current processor uses a 2901 and two 8086 microprocessors per channel and performs acquisition, tracking, and data demodulation for JITDS, GPS, IFF and TACAN systems. The next generation processor will be implemented using a VHSIC chip set employing a programmable complex array vector processor module, a GP computer module, customized gate array modules, and a digital array correlator. This integrated processor has application to a wide number of diverse system waveforms, and will bring the benefits of VHSIC technology insertion into avionic antijam communications systems.

Physics of Failure Analysis of Xilinx Flip Chip CCGA Packages: Effects of Mission Environments on Properties of LP2 Underfill and ATI Lid Adhesive Materials

NASA Technical Reports Server (NTRS)

Suh, Jong-ook

2013-01-01

The Xilinx Virtex 4QV and 5QV (V4 and V5) are next-generation field-programmable gate arrays (FPGAs) for space applications. However, there have been concerns within the space community regarding the non-hermeticity of V4/V5 packages; polymeric materials such as the underfill and lid adhesive will be directly exposed to the space environment. In this study, reliability concerns associated with the non-hermeticity of V4/V5 packages were investigated by studying properties and behavior of the underfill and the lid adhesvie materials used in V4/V5 packages.

Implementation of image transmission server system using embedded Linux

NASA Astrophysics Data System (ADS)

Park, Jong-Hyun; Jung, Yeon Sung; Nam, Boo Hee

2005-12-01

In this paper, we performed the implementation of image transmission server system using embedded system that is for the specified object and easy to install and move. Since the embedded system has lower capability than the PC, we have to reduce the quantity of calculation of the baseline JPEG image compression and transmission. We used the Redhat Linux 9.0 OS at the host PC and the target board based on embedded Linux. The image sequences are obtained from the camera attached to the FPGA (Field Programmable Gate Array) board with ALTERA cooperation chip. For effectiveness and avoiding some constraints from the vendor's own, we made the device driver using kernel module.

Fast particles identification in programmable form at level-0 trigger by means of the 3D-Flow system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Crosetto, Dario B.

1998-10-30

The 3D-Flow Processor system is a new, technology-independent concept in very fast, real-time system architectures. Based on either an FPGA or an ASIC implementation, it can address, in a fully programmable manner, applications where commercially available processors would fail because of throughput requirements. Possible applications include filtering-algorithms (pattern recognition) from the input of multiple sensors, as well as moving any input validated by these filtering-algorithms to a single output channel. Both operations can easily be implemented on a 3D-Flow system to achieve a real-time processing system with a very short lag time. This system can be built either with off-the-shelfmore » FPGAs or, for higher data rates, with CMOS chips containing 4 to 16 processors each. The basic building block of the system, a 3D-Flow processor, has been successfully designed in VHDL code written in ''Generic HDL'' (mostly made of reusable blocks that are synthesizable in different technologies, or FPGAs), to produce a netlist for a four-processor ASIC featuring 0.35 micron CBA (Ceil Base Array) technology at 3.3 Volts, 884 mW power dissipation at 60 MHz and 63.75 mm sq. die size. The same VHDL code has been targeted to three FPGA manufacturers (Altera EPF10K250A, ORCA-Lucent Technologies 0R3T165 and Xilinx XCV1000). A complete set of software tools, the 3D-Flow System Manager, equally applicable to ASIC or FPGA implementations, has been produced to provide full system simulation, application development, real-time monitoring, and run-time fault recovery. Today's technology can accommodate 16 processors per chip in a medium size die, at a cost per processor of less than $5 based on the current silicon die/size technology cost.« less

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro

PubMed Central

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system. PMID:25346683

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro.

PubMed

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system.

Progress on CD-DVD laser microfabrication method to develop cell culture scaffolds integrating biomimetic characteristics

NASA Astrophysics Data System (ADS)

Hautefeuille, Mathieu; Vázquez-Victorio, Genaro; Cruz-Ramírez, Aaron; Cabriales, Lucia; Jiménez-Diaz, Edgar; Escutia-Guadarrama, Lidia; López-Aparicio, Jehú; Pérez-Calixto, Daniel; Cano-Jorge, Mariel; Nieto-Rivera, Brenda; Sánchez-Olvera, Raúl

2018-02-01

The development of organ-on-chip and biological scaffolds is currently requiring simpler methods to microstructure biocompatible materials in three dimensions, fabricate structural and functional elements in biomaterials or modify the physicochemical properties of desired substrates. With the aim of creating simple, cost-effective alternatives to conventional existing techniques to produce such platforms with very specific properties, a low-power CD-DVD laser pickup head was recycled and mounted on a programmable three-axis micro-displacement system in order to modify the surface of polymeric materials in a local fashion. Thanks to a specially-designed method using a strongly absorbing additive coating the materials of interest, it has been possible to establish and precisely control processes useful in microtechnology for biomedical applications and normally restricted to much less affordable high-power lasers. In this work, we present our latest progress regarding the application of our fabrication technique to the development of organ-on-chip platforms thanks to the simple integration of several biomimetic characteristics typically achieved with traditional, less cost-effective microtechnology methods in one step or through replica-molding. Our straightforward approach indeed enables great control of local laser microablation for true on-demand biomimetic micropatterned designs in several transparent polymers and hydrogels of tunable stiffness and is allowing integration of microfluidics, microelectronics, optical waveguides, surface microstructuring and even transfer of superficial protein micropatterns on a variety of biocompatible materials. The results presented here were validated using hepatic and fibroblasts cell lines to demonstrate the viability of our procedure for organ-on-chip development and show the impact of such features in cell culture.

Design and implementation of a programming circuit in radiation-hardened FPGA

NASA Astrophysics Data System (ADS)

Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

2011-08-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

Rapid prototyping of update algorithm of discrete Fourier transform for real-time signal processing

NASA Astrophysics Data System (ADS)

Kakad, Yogendra P.; Sherlock, Barry G.; Chatapuram, Krishnan V.; Bishop, Stephen

2001-10-01

An algorithm is developed in the companion paper, to update the existing DFT to represent the new data series that results when a new signal point is received. Updating the DFT in this way uses less computation than directly evaluating the DFT using the FFT algorithm, This reduces the computational order by a factor of log2 N. The algorithm is able to work in the presence of data window function, for use with rectangular window, the split triangular, Hanning, Hamming, and Blackman windows. In this paper, a hardware implementation of this algorithm, using FPGA technology, is outlined. Unlike traditional fully customized VLSI circuits, FPGAs represent a technical break through in the corresponding industry. The FPGA implements thousands of gates of logic in a single IC chip and it can be programmed by users at their site in a few seconds or less depending on the type of device used. The risk is low and the development time is short. The advantages have made FPGAs very popular for rapid prototyping of algorithms in the area of digital communication, digital signal processing, and image processing. Our paper addresses the related issues of implementation using hardware descriptive language in the development of the design and the subsequent downloading on the programmable hardware chip.

Remote monitoring and fault recovery for FPGA-based field controllers of telescope and instruments

NASA Astrophysics Data System (ADS)

Zhu, Yuhua; Zhu, Dan; Wang, Jianing

2012-09-01

As the increasing size and more and more functions, modern telescopes have widely used the control architecture, i.e. central control unit plus field controller. FPGA-based field controller has the advantages of field programmable, which provide a great convenience for modifying software and hardware of control system. It also gives a good platform for implementation of the new control scheme. Because of multi-controlled nodes and poor working environment in scattered locations, reliability and stability of the field controller should be fully concerned. This paper mainly describes how we use the FPGA-based field controller and Ethernet remote to construct monitoring system with multi-nodes. When failure appearing, the new FPGA chip does self-recovery first in accordance with prerecovery strategies. In case of accident, remote reconstruction for the field controller can be done through network intervention if the chip is not being restored. This paper also introduces the network remote reconstruction solutions of controller, the system structure and transport protocol as well as the implementation methods. The idea of hardware and software design is given based on the FPGA. After actual operation on the large telescopes, desired results have been achieved. The improvement increases system reliability and reduces workload of maintenance, showing good application and popularization.

A monolithic K-band phase-locked loop for microwave radar application

NASA Astrophysics Data System (ADS)

Zhou, Guangyao; Ma, Shunli; Li, Ning; Ye, Fan; Ren, Junyan

2017-02-01

A monolithic K-band phase-locked loop (PLL) for microwave radar application is proposed and implemented in this paper. By eliminating the tail transistor and using optimized high-Q LC-tank, the proposed voltage-controlled oscillator (VCO) achieves a tuning range of 18.4 to 23.3 GHz and reduced phase noise. Two cascaded current-mode logic (CML) divide-by-two frequency prescalers are implemented to bridge the frequency gap, in which inductor peaking technique is used in the first stage to further boost allowable input frequency. Six-stage TSPC divider chain is used to provide programmable division ratio from 64 to 127, and a second-order passive loop filter with 825 kHz bandwidth is also integrated on-chip to minimize required external components. The proposed PLL needs only approximately 18.2 μs settling time, and achieves a wide tuning range from 18.4 to 23.3 GHz, with a typical output power of ‑0.84 dBm and phase noise of ‑91.92 dBc/Hz @ 1 MHz. The chip is implemented in TSMC 65 nm CMOS process, and occupies an area of 0.56 mm2 without pads under a 1.2 V single voltage supply. Project supported by the National High-Tech Research and Development Program of China (No. 2013AA014101).

A neural network device for on-line particle identification in cosmic ray experiments

NASA Astrophysics Data System (ADS)

Scrimaglio, R.; Finetti, N.; D'Altorio, L.; Rantucci, E.; Raso, M.; Segreto, E.; Tassoni, A.; Cardarilli, G. C.

2004-05-01

On-line particle identification is one of the main goals of many experiments in space both for rare event studies and for optimizing measurements along the orbital trajectory. Neural networks can be a useful tool for signal processing and real time data analysis in such experiments. In this document we report on the performances of a programmable neural device which was developed in VLSI analog/digital technology. Neurons and synapses were accomplished by making use of Operational Transconductance Amplifier (OTA) structures. In this paper we report on the results of measurements performed in order to verify the agreement of the characteristic curves of each elementary cell with simulations and on the device performances obtained by implementing simple neural structures on the VLSI chip. A feed-forward neural network (Multi-Layer Perceptron, MLP) was implemented on the VLSI chip and trained to identify particles by processing the signals of two-dimensional position-sensitive Si detectors. The radiation monitoring device consisted of three double-sided silicon strip detectors. From the analysis of a set of simulated data it was found that the MLP implemented on the neural device gave results comparable with those obtained with the standard method of analysis confirming that the implemented neural network could be employed for real time particle identification.

Hot embossed polyethylene through-hole chips for bead-based microfluidic devices.

PubMed

Chou, Jie; Du, Nan; Ou, Tina; Floriano, Pierre N; Christodoulides, Nicolaos; McDevitt, John T

2013-04-15

Over the past decade, there has been a growth of interest in the translation of microfluidic systems into real-world clinical practice, especially for use in point-of-care or near patient settings. While initial fabrication advances in microfluidics involved mainly the etching of silicon and glass, the economics of scaling of these materials is not amendable for point-of-care usage where single-test applications force cost considerations to be kept low and throughput high. As such, materials base more consistent with point-of-care needs is required. In this manuscript, the fabrication of a hot embossed, through-hole low-density polyethylene ensembles derived from an anisotropically etched silicon wafer is discussed. This semi-opaque polymer that can be easily sterilized and recycled provides low background noise for fluorescence measurements and yields more affordable cost than other thermoplastics commonly used for microfluidic applications such as cyclic olefin copolymer (COC). To fabrication through-hole microchips from this alternative material for microfluidics, a fabrication technique that uses a high-temperature, high-pressure resistant mold is described. This aluminum-based epoxy mold, serving as the positive master mold for embossing, is casted over etched arrays of pyramidal pits in a silicon wafer. Methods of surface treatment of the wafer prior to casting and PDMS casting of the epoxy are discussed to preserve the silicon wafer for future use. Changes in the thickness of polyethylene are observed for varying embossing temperatures. The methodology described herein can quickly fabricate 20 disposable, single use chips in less than 30 min with the ability to scale up 4 times by using multiple molds simultaneously. When coupled as a platform supporting porous bead sensors, as in the recently developed Programmable Bio-Nano-Chip, this bead chip system can achieve limits of detection, for the cardiac biomarker C-reactive protein, of 0.3 ng/mL, thereby demonstrating that the approach is compatible with high performance, real-world clinical measurements in the context of point-of-care testing. Copyright © 2012 Elsevier B.V. All rights reserved.

5nsec Dead time multichannel scaling system for Mössbauer spectrometer

NASA Astrophysics Data System (ADS)

Verrastro, C.; Trombetta, G.; Pita, A.; Saragovi, C.; Duhalde, S.

1991-11-01

A PC programmable and fast multichannel scaling module has been designed to use a commercial Mössbauer spectrometer. This module is based on a 10 single chip 8 bits microcomputer (MC6805) and on a 35 fast ALU, which allows a high performance and low cost system. The module can operate in a stand-alone mode. Data analysis are performed in real time display, on XT/AT IBM PC or compatibles. The channels are ranged between 256 and 4096, the maximum number of counts is 232-1 per channel, the dwell time is 3 μsec and the dead time between channels is 5 nsec. A friendly software display the real time spectrum and offers menues with different options at each state.

Miniaturization of the atmospheric laser communication APT system

NASA Astrophysics Data System (ADS)

Sun, Wei; Ai, Yong; Yang, Jinling; Huang, Haibo

2003-09-01

The paper presents a scheme of the miniaturization of APT system and the design of the system based on the investigation of status in quo. It deals with the infrared image of the other terminal's beacon from the Charge Coupled Device (CCD) by the Complex Programmable Logic Device (CPLD). The result of the transaction is delivered to Single Chip Microcomputer (SCM), which controls the micro-servomotor. Subsequently, the precision drive system drives the optical system that uses only one light axis for signal beam and beacon to finish the acquisition, pointing, and tracking of the communication terminals. The anlayses of the APT system's error indicate that the tracking error limits in 70uRad with the weight of the system lighter than 8-kilogram.

Steering microtubule shuttle transport with dynamically controlled magnetic fields

DOE PAGES

Mahajan, K. D.; Ruan, G.; Dorcéna, C. J.; ...

2016-03-23

Nanoscale control of matter is critical to the design of integrated nanosystems. Here, we describe a method to dynamically control directionality of microtubule (MT) motion using programmable magnetic fields. MTs are combined with magnetic quantum dots (i.e., MagDots) that are manipulated by external magnetic fields provided by magnetic nanowires. MT shuttles thus undergo both ATP-driven and externally-directed motion with a fluorescence component that permits simultaneous visualization of shuttle motion. This technology is used to alter the trajectory of MTs in motion and to pin MT motion. Ultimately, such an approach could be used to evaluate the MT-kinesin transport system andmore » could serve as the basis for improved lab-on-a-chip technologies based on MT transport.« less

Image processing applications: From particle physics to society

NASA Astrophysics Data System (ADS)

Sotiropoulou, C.-L.; Luciano, P.; Gkaitatzis, S.; Citraro, S.; Giannetti, P.; Dell'Orso, M.

2017-01-01

We present an embedded system for extremely efficient real-time pattern recognition execution, enabling technological advancements with both scientific and social impact. It is a compact, fast, low consumption processing unit (PU) based on a combination of Field Programmable Gate Arrays (FPGAs) and the full custom associative memory chip. The PU has been developed for real time tracking in particle physics experiments, but delivers flexible features for potential application in a wide range of fields. It has been proposed to be used in accelerated pattern matching execution for Magnetic Resonance Fingerprinting (biomedical applications), in real time detection of space debris trails in astronomical images (space applications) and in brain emulation for image processing (cognitive image processing). We illustrate the potentiality of the PU for the new applications.

Low-complexity camera digital signal imaging for video document projection system

NASA Astrophysics Data System (ADS)

Hsia, Shih-Chang; Tsai, Po-Shien

2011-04-01

We present high-performance and low-complexity algorithms for real-time camera imaging applications. The main functions of the proposed camera digital signal processing (DSP) involve color interpolation, white balance, adaptive binary processing, auto gain control, and edge and color enhancement for video projection systems. A series of simulations demonstrate that the proposed method can achieve good image quality while keeping computation cost and memory requirements low. On the basis of the proposed algorithms, the cost-effective hardware core is developed using Verilog HDL. The prototype chip has been verified with one low-cost programmable device. The real-time camera system can achieve 1270 × 792 resolution with the combination of extra components and can demonstrate each DSP function.

The algebraic decoding of the (41, 21, 9) quadratic residue code

NASA Technical Reports Server (NTRS)

Reed, Irving S.; Truong, T. K.; Chen, Xuemin; Yin, Xiaowei

1992-01-01

A new algebraic approach for decoding the quadratic residue (QR) codes, in particular the (41, 21, 9) QR code is presented. The key ideas behind this decoding technique are a systematic application of the Sylvester resultant method to the Newton identities associated with the code syndromes to find the error-locator polynomial, and next a method for determining error locations by solving certain quadratic, cubic and quartic equations over GF(2 exp m) in a new way which uses Zech's logarithms for the arithmetic. The algorithms developed here are suitable for implementation in a programmable microprocessor or special-purpose VLSI chip. It is expected that the algebraic methods developed here can apply generally to other codes such as the BCH and Reed-Solomon codes.

Hardware platforms for MEMS gyroscope tuning based on evolutionary computation using open-loop and closed -loop frequency response

NASA Technical Reports Server (NTRS)

Keymeulen, Didier; Ferguson, Michael I.; Fink, Wolfgang; Oks, Boris; Peay, Chris; Terrile, Richard; Cheng, Yen; Kim, Dennis; MacDonald, Eric; Foor, David

2005-01-01

We propose a tuning method for MEMS gyroscopes based on evolutionary computation to efficiently increase the sensitivity of MEMS gyroscopes through tuning. The tuning method was tested for the second generation JPL/Boeing Post-resonator MEMS gyroscope using the measurement of the frequency response of the MEMS device in open-loop operation. We also report on the development of a hardware platform for integrated tuning and closed loop operation of MEMS gyroscopes. The control of this device is implemented through a digital design on a Field Programmable Gate Array (FPGA). The hardware platform easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip.

A fully reconfigurable photonic integrated signal processor

NASA Astrophysics Data System (ADS)

Liu, Weilin; Li, Ming; Guzzon, Robert S.; Norberg, Erik J.; Parker, John S.; Lu, Mingzhi; Coldren, Larry A.; Yao, Jianping

2016-03-01

Photonic signal processing has been considered a solution to overcome the inherent electronic speed limitations. Over the past few years, an impressive range of photonic integrated signal processors have been proposed, but they usually offer limited reconfigurability, a feature highly needed for the implementation of large-scale general-purpose photonic signal processors. Here, we report and experimentally demonstrate a fully reconfigurable photonic integrated signal processor based on an InP-InGaAsP material system. The proposed photonic signal processor is capable of performing reconfigurable signal processing functions including temporal integration, temporal differentiation and Hilbert transformation. The reconfigurability is achieved by controlling the injection currents to the active components of the signal processor. Our demonstration suggests great potential for chip-scale fully programmable all-optical signal processing.

Advanced system on a chip microelectronics for spacecraft and science instruments

NASA Astrophysics Data System (ADS)

Paschalidis, Nikolaos P.

2003-01-01

The explosive growth of the modern microelectronics field opens new horizons for the development of new lightweight, low power, and smart spacecraft and science instrumentation systems in the new millennium explorations. Although this growth is mostly driven by the commercial need for low power, portable and computationally intensive products, the applicability is obvious in the space sector. The additional difficulties needed to be overcome for applicability in space include radiation hardness for total ionizing dose and single event effects (SEE), and reliability. Additionally, this new capability introduces a whole new philosophy of design and R&D, with strong implications in organizational and inter-agency program management. One key component specifically developed towards low power, small size, highly autonomous spacecraft systems, is the smart sensor remote input/output (TRIO) chip. TRIO can interface to 32 transducers with current sources/sinks and voltage sensing. It includes front-end analog signal processing, a 10-bit ADC, memory, and standard serial and parallel I/Os. These functions are very useful for spacecraft and subsystems health and status monitoring, and control actions. The key contributions of the TRIO are feasibility of modular architectures, elimination of several miles of wire harnessing, and power savings by orders of magnitude. TRIO freely operates from a single power supply 2.5- 5.5 V with power dissipation <10 mW. This system on a chip device rapidly becomes a NASA and Commercial Space standard as it is already selected by thousands in several new millennium missions, including Europa Orbiter, Mars Surveyor Program, Solar Probe, Pluto Express, Stereo, Contour, Messenger, etc. In the Science Instrumentation field common instruments that can greatly take advantage of the new technologies are: energetic-particle/plasma and wave instruments, imagers, mass spectrometers, X-ray and UV spectrographs, magnetometers, laser rangefinding instruments, etc. Common measurements that apply to many of these instruments are precise time interval measurement and high resolution read-out of solid state detectors. A precise time interval measurement chip was specially developed that achieves ˜100 ps (×10 improvement) time resolution at a power dissipation ˜20 mW (×50 improvement), dead time ˜1.5 μs (×20 improvement), and chip die size 5 mm×5 mm versus two 20 cm×20 cm doubled sided boards. This device is selected as a key enabling technology for several NASA particle, delay line imaging, and laser range finding instruments onboard (NASA Image, Messenger, etc. missions). Another device with universal application is radiation energy read-out from solid state detectors. Multi-channel low-power and end-to-end sensor input—digital output is key for the new generation instruments. The readout channel comprises of a Charge Sensitive Preamplifier with a target sensitivity of ˜1 KeV FWHM at 20 pf detector capacitance, a Shaper Amplifier with programmable time constant/gain, and an ADC. The read-out chip together with the precise time interval chip comprises the essential elements of a common particle spectroscopy instrument. To mention some more applications fast-signal acquisition—and digitization is a very useful function for a category of instrument such as mass spectroscopy and profile laser rangefinding. The single chip approach includes a high bandwidth preamplifier, fast sampling ˜5 ns, analog memory ˜10K locations, 12-bit ADC and serial/parallel I/Os. The wealth of the applications proves the advanced microelectronics field as a key enabling technology for the new millennium space exploration.

CCD and photon-counting photometric observations of peculiar asteroids

NASA Astrophysics Data System (ADS)

Fulvio, D.; Blanco, C.; Cigna, M.; Gandolfi, D.

The photometric observational programme of main-belt asteroids undertaken, since 1980, at the Physics and Astronomy Department of Catania University, mainly by using photoelectric acquisition, has been extended to the Near-Earth Objects, because of the importance of their study to improve the knowledge of the mechanics and the physics of the inner Solar System. The wideness of the observational programme was pursued by using an expressly built CCD camera having a Kodak 4200 detector 2048x2048 pixel class 1, front-illuminated chip with 9 mu m pixel-size, equipped with BVRI Johnson filters. New observations of 4 Vesta, 27 Euterpe, 173 Ino, 182 Elsa, 849 Ara (carried out at M.G. Fracastoro Station of Catania Astrophysical Observatory), 984 Gretia, 3199 Nefertiti and 2004 UE (carried out at Asiago Station of Padova Astronomical Observatory) are presented. The improvement of the rotational period value (for 182 Elsa and 2004 UE it is the first determination), of the lightcurve amplitude and of the B-V colour index was obtained. For 4 Vesta indications on surface mineralogic morphology are deduced from the UBV photometric behaviour while for 182 Elsa, the H-G magnitude relation was carried out.

Nonreciprocal Microwave Signal Processing with a Field-Programmable Josephson Amplifier

NASA Astrophysics Data System (ADS)

Lecocq, F.; Ranzani, L.; Peterson, G. A.; Cicak, K.; Simmonds, R. W.; Teufel, J. D.; Aumentado, J.

2017-02-01

We report on the design and implementation of a field-programmable Josephson amplifier (FPJA)—a compact and lossless superconducting circuit that can be programmed in situ by a set of microwave drives to perform reciprocal and nonreciprocal frequency conversion and amplification. In this work, we demonstrate four modes of operation: frequency conversion (transmission of -0.5 dB, reflection of -30 dB), circulation (transmission of -0.5 dB, reflection of -30 dB, isolation of 30 dB), phase-preserving amplification (gain >20 dB , one photon of added noise) and directional phase-preserving amplification (reflection of -10 dB, forward gain of 18 dB, reverse isolation of 8 dB, one photon of added noise). The system exhibits quantitative agreement with the theoretical prediction. Based on a gradiometric superconducting quantum-interference device with Nb /Al -Al Ox/Nb Josephson junctions, the FPJA is first-order insensitive to flux noise and can be operated without magnetic shielding at low temperature. Owing to its flexible design and compatibility with existing superconducting fabrication techniques, the FPJA offers a straightforward route toward on-chip integration with superconducting quantum circuits such as qubits and microwave optomechanical systems.

Design and FPGA implementation for MAC layer of Ethernet PON

NASA Astrophysics Data System (ADS)

Zhu, Zengxi; Lin, Rujian; Chen, Jian; Ye, Jiajun; Chen, Xinqiao

2004-04-01

Ethernet passive optical network (EPON), which represents the convergence of low-cost, high-bandwidth and supporting multiple services, appears to be one of the best candidates for the next-generation access network. The work of standardizing EPON as a solution for access network is still underway in the IEEE802.3ah Ethernet in the first mile (EFM) task force. The final release is expected in 2004. Up to now, there has been no standard application specific integrated circuit (ASIC) chip available which fulfills the functions of media access control (MAC) layer of EPON. The MAC layer in EPON system has many functions, such as point-to-point emulation (P2PE), Ethernet MAC functionality, multi-point control protocol (MPCP), network operation, administration and maintenance (OAM) and link security. To implement those functions mentioned above, an embedded real-time operating system (RTOS) and a flexible programmable logic device (PLD) with an embedded processor are used. The software and hardware functions in MAC layer are realized through programming embedded microprocessor and field programmable gate array(FPGA). Finally, some experimental results are given in this paper. The method stated here can provide a valuable reference for developing EPON MAC layer ASIC.

The design and development of low- and high-voltage ASICs for space-borne CCD cameras

NASA Astrophysics Data System (ADS)

Waltham, N.; Morrissey, Q.; Clapp, M.; Bell, S.; Jones, L.; Torbet, M.

2017-12-01

The CCD remains the pre-eminent visible and UV wavelength image sensor in space science, Earth and planetary remote sensing. However, the design of space-qualified CCD readout electronics is a significant challenge with requirements for low-volume, low-mass, low-power, high-reliability and tolerance to space radiation. Space-qualified components are frequently unavailable and up-screened commercial components seldom meet project or international space agency requirements. In this paper, we describe an alternative approach of designing and space-qualifying a series of low- and high-voltage mixed-signal application-specific integrated circuits (ASICs), the ongoing development of two low-voltage ASICs with successful flight heritage, and two new high-voltage designs. A challenging sub-system of any CCD camera is the video processing and digitisation electronics. We describe recent developments to improve performance and tolerance to radiation-induced single event latchup of a CCD video processing ASIC originally developed for NASA's Solar Terrestrial Relations Observatory and Solar Dynamics Observatory. We also describe a programme to develop two high-voltage ASICs to address the challenges presented with generating a CCD's bias voltages and drive clocks. A 0.35 μm, 50 V tolerant, CMOS process has been used to combine standard low-voltage 3.3 V transistors with high-voltage 50 V diffused MOSFET transistors that enable output buffers to drive CCD bias drains, gates and clock electrodes directly. We describe a CCD bias voltage generator ASIC that provides 24 independent and programmable 0-32 V outputs. Each channel incorporates a 10-bit digital-to-analogue converter, provides current drive of up to 20 mA into loads of 10 μF, and includes current-limiting and short-circuit protection. An on-chip telemetry system with a 12-bit analogue-to-digital converter enables the outputs and multiple off-chip camera voltages to be monitored. The ASIC can drive one or more CCDs and replaces the many discrete components required in current cameras. We also describe a CCD clock driver ASIC that provides six independent and programmable drivers with high-current capacity. The device enables various CCD clock parameters to be programmed independently, for example the clock-low and clock-high voltage levels, and the clock-rise and clock-fall times, allowing configuration for serial clock frequencies in the range 0.1-2 MHz and image clock frequencies in the range 10-100 kHz. Finally, we demonstrate the impact and importance of this technology for the development of compact, high-performance and low-power integrated focal plane electronics.

Field programmable gate arrays-based number plate binarization and adjustment for automatic number plate recognition systems

NASA Astrophysics Data System (ADS)

Zhai, Xiaojun; Bensaali, Faycal; Sotudeh, Reza

2013-01-01

Number plate (NP) binarization and adjustment are important preprocessing stages in automatic number plate recognition (ANPR) systems and are used to link the number plate localization (NPL) and character segmentation stages. Successfully linking these two stages will improve the performance of the entire ANPR system. We present two optimized low-complexity NP binarization and adjustment algorithms. Efficient area/speed architectures based on the proposed algorithms are also presented and have been successfully implemented and tested using the Mentor Graphics RC240 FPGA development board, which together require only 9% of the available on-chip resources of a Virtex-4 FPGA, run with a maximum frequency of 95.8 MHz and are capable of processing one image in 0.07 to 0.17 ms.

A generic FPGA-based detector readout and real-time image processing board

NASA Astrophysics Data System (ADS)

Sarpotdar, Mayuresh; Mathew, Joice; Safonova, Margarita; Murthy, Jayant

2016-07-01

For space-based astronomical observations, it is important to have a mechanism to capture the digital output from the standard detector for further on-board analysis and storage. We have developed a generic (application- wise) field-programmable gate array (FPGA) board to interface with an image sensor, a method to generate the clocks required to read the image data from the sensor, and a real-time image processor system (on-chip) which can be used for various image processing tasks. The FPGA board is applied as the image processor board in the Lunar Ultraviolet Cosmic Imager (LUCI) and a star sensor (StarSense) - instruments developed by our group. In this paper, we discuss the various design considerations for this board and its applications in the future balloon and possible space flights.

A multi-modal stereo microscope based on a spatial light modulator.

PubMed

Lee, M P; Gibson, G M; Bowman, R; Bernet, S; Ritsch-Marte, M; Phillips, D B; Padgett, M J

2013-07-15

Spatial Light Modulators (SLMs) can emulate the classic microscopy techniques, including differential interference (DIC) contrast and (spiral) phase contrast. Their programmability entails the benefit of flexibility or the option to multiplex images, for single-shot quantitative imaging or for simultaneous multi-plane imaging (depth-of-field multiplexing). We report the development of a microscope sharing many of the previously demonstrated capabilities, within a holographic implementation of a stereo microscope. Furthermore, we use the SLM to combine stereo microscopy with a refocusing filter and with a darkfield filter. The instrument is built around a custom inverted microscope and equipped with an SLM which gives various imaging modes laterally displaced on the same camera chip. In addition, there is a wide angle camera for visualisation of a larger region of the sample.

The Design and Implementation of NASA's Advanced Flight Computing Module

NASA Technical Reports Server (NTRS)

Alkakaj, Leon; Straedy, Richard; Jarvis, Bruce

1995-01-01

This paper describes a working flight computer Multichip Module developed jointly by JPL and TRW under their respective research programs in a collaborative fashion. The MCM is fabricated by nCHIP and is packaged within a 2 by 4 inch Al package from Coors. This flight computer module is one of three modules under development by NASA's Advanced Flight Computer (AFC) program. Further development of the Mass Memory and the programmable I/O MCM modules will follow. The three building block modules will then be stacked into a 3D MCM configuration. The mass and volume of the flight computer MCM achieved at 89 grams and 1.5 cubic inches respectively, represent a major enabling technology for future deep space as well as commercial remote sensing applications.

Developments of FPGA-based digital back-ends for low frequency antenna arrays at Medicina radio telescopes

NASA Astrophysics Data System (ADS)

Naldi, G.; Bartolini, M.; Mattana, A.; Pupillo, G.; Hickish, J.; Foster, G.; Bianchi, G.; Lingua, A.; Monari, J.; Montebugnoli, S.; Perini, F.; Rusticelli, S.; Schiaffino, M.; Virone, G.; Zarb Adami, K.

In radio astronomy Field Programmable Gate Array (FPGA) technology is largely used for the implementation of digital signal processing techniques applied to antenna arrays. This is mainly due to the good trade-off among computing resources, power consumption and cost offered by FPGA chip compared to other technologies like ASIC, GPU and CPU. In the last years several digital backend systems based on such devices have been developed at the Medicina radio astronomical station (INAF-IRA, Bologna, Italy). Instruments like FX correlator, direct imager, beamformer, multi-beam system have been successfully designed and realized on CASPER (Collaboration for Astronomy Signal Processing and Electronics Research, https://casper.berkeley.edu) processing boards. In this paper we present the gained experience in this kind of applications.

A solution for measuring accurate reaction time to visual stimuli realized with a programmable microcontroller.

PubMed

Ohyanagi, Toshio; Sengoku, Yasuhito

2010-02-01

This article presents a new solution for measuring accurate reaction time (SMART) to visual stimuli. The SMART is a USB device realized with a Cypress Programmable System-on-Chip (PSoC) mixed-signal array programmable microcontroller. A brief overview of the hardware and firmware of the PSoC is provided, together with the results of three experiments. In Experiment 1, we investigated the timing accuracy of the SMART in measuring reaction time (RT) under different conditions of operating systems (OSs; Windows XP or Vista) and monitor displays (a CRT or an LCD). The results indicated that the timing error in measuring RT by the SMART was less than 2 msec, on average, under all combinations of OS and display and that the SMART was tolerant to jitter and noise. In Experiment 2, we tested the SMART with 8 participants. The results indicated that there was no significant difference among RTs obtained with the SMART under the different conditions of OS and display. In Experiment 3, we used Microsoft (MS) PowerPoint to present visual stimuli on the display. We found no significant difference in RTs obtained using MS DirectX technology versus using the PowerPoint file with the SMART. We are certain that the SMART is a simple and practical solution for measuring RTs accurately. Although there are some restrictions in using the SMART with RT paradigms, the SMART is capable of providing both researchers and health professionals working in clinical settings with new ways of using RT paradigms in their work.

A 11 mW 2.4 GHz 0.18 µm CMOS Transceivers for Wireless Sensor Networks.

PubMed

Hou, Bing; Chen, Hua; Wang, Zhiyu; Mo, Jiongjiong; Chen, Junli; Yu, Faxin; Wang, Wenbo

2017-01-24

In this paper, a low power transceiver for wireless sensor networks (WSN) is proposed. The system is designed with fully functional blocks including a receiver, a fractional-N frequency synthesizer, and a class-E transmitter, and it is optimized with a good balance among output power, sensitivity, power consumption, and silicon area. A transmitter and receiver (TX-RX) shared input-output matching network is used so that only one off-chip inductor is needed in the system. The power and area efficiency-oriented, fully-integrated frequency synthesizer is able to provide programmable output frequencies in the 2.4 GHz range while occupying a small silicon area. Implemented in a standard 0.18 μm RF Complementary Metal Oxide Semiconductor (CMOS) technology, the whole transceiver occupies a chip area of 0.5 mm² (1.2 mm² including bonding pads for a QFN package). Measurement results suggest that the design is able to work at amplitude shift keying (ASK)/on-off-keying (OOK) and FSK modes with up to 500 kbps data rate. With an input sensitivity of -60 dBm and an output power of 3 dBm, the receiver, transmitter and frequency synthesizer consumes 2.3 mW, 4.8 mW, and 3.9 mW from a 1.8 V supply voltage, respectively.

Integrated microfluidic technology for sub-lethal and behavioral marine ecotoxicity biotests

NASA Astrophysics Data System (ADS)

Huang, Yushi; Reyes Aldasoro, Constantino Carlos; Persoone, Guido; Wlodkowic, Donald

2015-06-01

Changes in behavioral traits exhibited by small aquatic invertebrates are increasingly postulated as ethically acceptable and more sensitive endpoints for detection of water-born ecotoxicity than conventional mortality assays. Despite importance of such behavioral biotests, their implementation is profoundly limited by the lack of appropriate biocompatible automation, integrated optoelectronic sensors, and the associated electronics and analysis algorithms. This work outlines development of a proof-of-concept miniaturized Lab-on-a-Chip (LOC) platform for rapid water toxicity tests based on changes in swimming patterns exhibited by Artemia franciscana (Artoxkit M™) nauplii. In contrast to conventionally performed end-point analysis based on counting numbers of dead/immobile specimens we performed a time-resolved video data analysis to dynamically assess impact of a reference toxicant on swimming pattern of A. franciscana. Our system design combined: (i) innovative microfluidic device keeping free swimming Artemia sp. nauplii under continuous microperfusion as a mean of toxin delivery; (ii) mechatronic interface for user-friendly fluidic actuation of the chip; and (iii) miniaturized video acquisition for movement analysis of test specimens. The system was capable of performing fully programmable time-lapse and video-microscopy of multiple samples for rapid ecotoxicity analysis. It enabled development of a user-friendly and inexpensive test protocol to dynamically detect sub-lethal behavioral end-points such as changes in speed of movement or distance traveled by each animal.

Rubus: A compiler for seamless and extensible parallelism.

PubMed

Adnan, Muhammad; Aslam, Faisal; Nawaz, Zubair; Sarwar, Syed Mansoor

2017-01-01

Nowadays, a typical processor may have multiple processing cores on a single chip. Furthermore, a special purpose processing unit called Graphic Processing Unit (GPU), originally designed for 2D/3D games, is now available for general purpose use in computers and mobile devices. However, the traditional programming languages which were designed to work with machines having single core CPUs, cannot utilize the parallelism available on multi-core processors efficiently. Therefore, to exploit the extraordinary processing power of multi-core processors, researchers are working on new tools and techniques to facilitate parallel programming. To this end, languages like CUDA and OpenCL have been introduced, which can be used to write code with parallelism. The main shortcoming of these languages is that programmer needs to specify all the complex details manually in order to parallelize the code across multiple cores. Therefore, the code written in these languages is difficult to understand, debug and maintain. Furthermore, to parallelize legacy code can require rewriting a significant portion of code in CUDA or OpenCL, which can consume significant time and resources. Thus, the amount of parallelism achieved is proportional to the skills of the programmer and the time spent in code optimizations. This paper proposes a new open source compiler, Rubus, to achieve seamless parallelism. The Rubus compiler relieves the programmer from manually specifying the low-level details. It analyses and transforms a sequential program into a parallel program automatically, without any user intervention. This achieves massive speedup and better utilization of the underlying hardware without a programmer's expertise in parallel programming. For five different benchmarks, on average a speedup of 34.54 times has been achieved by Rubus as compared to Java on a basic GPU having only 96 cores. Whereas, for a matrix multiplication benchmark the average execution speedup of 84 times has been achieved by Rubus on the same GPU. Moreover, Rubus achieves this performance without drastically increasing the memory footprint of a program.

MT6425CA: a 640 X 512-25μm CTIA ROIC for SWIR InGaAs detector arrays

NASA Astrophysics Data System (ADS)

Eminoglu, Selim; Mahsereci, Yigit Uygar; Altiner, Caglar; Akin, Tayfun

2012-06-01

This paper reports the development of a new CTIA ROIC (MT6425CA) suitable for SWIR InGaAs detector arrays. MT6425CA has a format of 640 × 512 with a pixel pitch of 25 μm and has a system-on-chip architecture, where all the critical timing and biasing for this ROIC are generated by programmable blocks on-chip. MT6425CA is a highly configurable and flexible ROIC, where many of its features can be programmed through a 3-wire serial interface allowing on-the-fly configuration of many ROIC features. The ROIC runs on 3.3V supply voltage at nominal clock speed of 10 MHz clock. It performs snapshot operation both using Integrate-Then-Read (ITR) and Integrate-While- Read (IWR) modes. The CTIA type pixel input circuitry has a full-well-capacity (FWC) of about 320,000e-, with an input referred read noise of less than 110e- at 300K. MT6425CA has programmable number of outputs, where 4, 2, or 1 output can be selected along with an analog reference for pseudo-differential operation. The integration time can be programmed up to 1s in steps of 0.1μs. The gain and offset in the ROIC can be programmed to adjust the output offset and voltage swing. ROIC dissipates less than 130mW from a 3.3V supply at full speed and full frame size with 4 outputs, providing both low-power and low-noise operation. MT6425CA is fabricated using a modern mixed-signal CMOS process on 200mm CMOS wafers with a high yield above 75%, yielding more than 50 working parts per wafer. It has been silicon verified, and tested parts are available either in wafer and die levels with a complete documentation including test reports and wafer maps. A USB based camera electronics and camera development platform with software are available to help customers to evaluate the imaging performance of MT6425CA in a fast and efficient way.

Detection of submicron-sized raft-like domains in membranes by small-angle neutron scattering

NASA Astrophysics Data System (ADS)

Pencer, J.; Mills, T.; Anghel, V.; Krueger, S.; Epand, R. M.; Katsaras, J.

2005-12-01

Using coarse grained models of heterogeneous vesicles we demonstrate the potential for small-angle neutron scattering (SANS) to detect and distinguish between two different categories of lateral segregation: 1) unilamellar vesicles (ULV) containing a single domain and 2) the formation of several small domains or “clusters” (~10 nm in radius) on a ULV. Exploiting the unique sensitivity of neutron scattering to differences between hydrogen and deuterium, we show that the liquid ordered (lo) DPPC-rich phase can be selectively labeled using chain deuterated dipalymitoyl phosphatidylcholine (dDPPC), which greatly facilitates the use of SANS to detect membrane domains. SANS experiments are then performed in order to detect and characterize, on nanometer length scales, lateral heterogeneities, or so-called “rafts”, in ~30 nm radius low polydispersity ULV made up of ternary mixtures of phospholipids and cholesterol. For 1:1:1 DOPC:DPPC:cholesterol (DDC) ULV we find evidence for the formation of lateral heterogeneities on cooling below 30 °C. These heterogeneities do not appear when DOPC is replaced by SOPC. Fits to the experimental data using coarse grained models show that, at room temperature, DDC ULV each exhibit approximately 30 domains with average radii of ~10 nm.

Cell-free study of F plasmid partition provides evidence for cargo transport by a diffusion-ratchet mechanism

PubMed Central

Vecchiarelli, Anthony G.; Hwang, Ling Chin; Mizuuchi, Kiyoshi

2013-01-01

Increasingly diverse types of cargo are being found to be segregated and positioned by ParA-type ATPases. Several minimalistic systems described in bacteria are self-organizing and are known to affect the transport of plasmids, protein machineries, and chromosomal loci. One well-studied model is the F plasmid partition system, SopABC. In vivo, SopA ATPase forms dynamic patterns on the nucleoid in the presence of the ATPase stimulator, SopB, which binds to the sopC site on the plasmid, demarcating it as the cargo. To understand the relationship between nucleoid patterning and plasmid transport, we established a cell-free system to study plasmid partition reactions in a DNA-carpeted flowcell. We observed depletion zones of the partition ATPase on the DNA carpet surrounding partition complexes. The findings favor a diffusion-ratchet model for plasmid motion whereby partition complexes create an ATPase concentration gradient and then climb up this gradient toward higher concentrations of the ATPase. Here, we report on the dynamic properties of the Sop system on a DNA-carpet substrate, which further support the proposed diffusion-ratchet mechanism. PMID:23479605

Effect of Salicylate on the Elasticity, Bending Stiffness, and Strength of SOPC Membranes

PubMed Central

Zhou, Yong; Raphael, Robert M.

2005-01-01

Salicylate is a small amphiphilic molecule which has diverse effects on membranes and membrane-mediated processes. We have utilized micropipette aspiration of giant unilamellar vesicles to determine salicylate's effects on lecithin membrane elasticity, bending rigidity, and strength. Salicylate effectively reduces the apparent area compressibility modulus and bending modulus of membranes in a dose-dependent manner at concentrations above 1 mM, but does not greatly alter the actual elastic compressibility modulus at the maximal tested concentration of 10 mM. The effect of salicylate on membrane strength was investigated using dynamic tension spectroscopy, which revealed that salicylate increases the frequency of spontaneous defect formation and lowers the energy barrier for unstable hole formation. The mechanical and dynamic tension experiments are consistent and support a picture in which salicylate disrupts membrane stability by decreasing membrane stiffness and membrane thickness. The tension-dependent partitioning of salicylate was utilized to calculate the molecular volume of salicylate in the membrane. The free energy of transfer for salicylate insertion into the membrane and the corresponding partition coefficient were also estimated, and indicated favorable salicylate-membrane interactions. The mechanical changes induced by salicylate may affect several biological processes, especially those associated with membrane curvature and permeability. PMID:15951377

Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores

NASA Astrophysics Data System (ADS)

Hayashi, Akihiro; Wada, Yasutaka; Watanabe, Takeshi; Sekiguchi, Takeshi; Mase, Masayoshi; Shirako, Jun; Kimura, Keiji; Kasahara, Hironori

Heterogeneous multicores have been attracting much attention to attain high performance keeping power consumption low in wide spread of areas. However, heterogeneous multicores force programmers very difficult programming. The long application program development period lowers product competitiveness. In order to overcome such a situation, this paper proposes a compilation framework which bridges a gap between programmers and heterogeneous multicores. In particular, this paper describes the compilation framework based on OSCAR compiler. It realizes coarse grain task parallel processing, data transfer using a DMA controller, power reduction control from user programs with DVFS and clock gating on various heterogeneous multicores from different vendors. This paper also evaluates processing performance and the power reduction by the proposed framework on a newly developed 15 core heterogeneous multicore chip named RP-X integrating 8 general purpose processor cores and 3 types of accelerator cores which was developed by Renesas Electronics, Hitachi, Tokyo Institute of Technology and Waseda University. The framework attains speedups up to 32x for an optical flow program with eight general purpose processor cores and four DRP(Dynamically Reconfigurable Processor) accelerator cores against sequential execution by a single processor core and 80% of power reduction for the real-time AAC encoding.

Configurable hardware integrate and fire neurons for sparse approximation.

PubMed

Shapero, Samuel; Rozell, Christopher; Hasler, Paul

2013-09-01

Sparse approximation is an important optimization problem in signal and image processing applications. A Hopfield-Network-like system of integrate and fire (IF) neurons is proposed as a solution, using the Locally Competitive Algorithm (LCA) to solve an overcomplete L1 sparse approximation problem. A scalable system architecture is described, including IF neurons with a nonlinear firing function, and current-based synapses to provide linear computation. A network of 18 neurons with 12 inputs is implemented on the RASP 2.9v chip, a Field Programmable Analog Array (FPAA) with directly programmable floating gate elements. Said system uses over 1400 floating gates, the largest system programmed on a FPAA to date. The circuit successfully reproduced the outputs of a digital optimization program, converging to within 4.8% RMS, and an objective cost only 1.7% higher on average. The active circuit consumed 559 μA of current at 2.4 V and converges on solutions in 25 μs, with measurement of the converged spike rate taking an additional 1 ms. Extrapolating the scaling trends to a N=1000 node system, the spiking LCA compares favorably with state-of-the-art digital solutions, and analog solutions using a non-spiking approach. Copyright © 2013 Elsevier Ltd. All rights reserved.

ELIPS: Toward a Sensor Fusion Processor on a Chip

NASA Technical Reports Server (NTRS)

Daud, Taher; Stoica, Adrian; Tyson, Thomas; Li, Wei-te; Fabunmi, James

1998-01-01

The paper presents the concept and initial tests from the hardware implementation of a low-power, high-speed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) processor is developed to seamlessly combine rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor in compact low power VLSI. The first demonstration of the ELIPS concept targets interceptor functionality; other applications, mainly in robotics and autonomous systems are considered for the future. The main assumption behind ELIPS is that fuzzy, rule-based and neural forms of computation can serve as the main primitives of an "intelligent" processor. Thus, in the same way classic processors are designed to optimize the hardware implementation of a set of fundamental operations, ELIPS is developed as an efficient implementation of computational intelligence primitives, and relies on a set of fuzzy set, fuzzy inference and neural modules, built in programmable analog hardware. The hardware programmability allows the processor to reconfigure into different machines, taking the most efficient hardware implementation during each phase of information processing. Following software demonstrations on several interceptor data, three important ELIPS building blocks (a fuzzy set preprocessor, a rule-based fuzzy system and a neural network) have been fabricated in analog VLSI hardware and demonstrated microsecond-processing times.

HALO: a reconfigurable image enhancement and multisensor fusion system

NASA Astrophysics Data System (ADS)

Wu, F.; Hickman, D. L.; Parker, Steve J.

2014-06-01

Contemporary high definition (HD) cameras and affordable infrared (IR) imagers are set to dramatically improve the effectiveness of security, surveillance and military vision systems. However, the quality of imagery is often compromised by camera shake, or poor scene visibility due to inadequate illumination or bad atmospheric conditions. A versatile vision processing system called HALO™ is presented that can address these issues, by providing flexible image processing functionality on a low size, weight and power (SWaP) platform. Example processing functions include video distortion correction, stabilisation, multi-sensor fusion and image contrast enhancement (ICE). The system is based around an all-programmable system-on-a-chip (SoC), which combines the computational power of a field-programmable gate array (FPGA) with the flexibility of a CPU. The FPGA accelerates computationally intensive real-time processes, whereas the CPU provides management and decision making functions that can automatically reconfigure the platform based on user input and scene content. These capabilities enable a HALO™ equipped reconnaissance or surveillance system to operate in poor visibility, providing potentially critical operational advantages in visually complex and challenging usage scenarios. The choice of an FPGA based SoC is discussed, and the HALO™ architecture and its implementation are described. The capabilities of image distortion correction, stabilisation, fusion and ICE are illustrated using laboratory and trials data.

A fractional-N frequency divider for multi-standard wireless transceiver fabricated in 0.18 μm CMOS process

NASA Astrophysics Data System (ADS)

Wang, Jiafeng; Fan, Xiangning; Shi, Xiaoyang; Wang, Zhigong

2017-12-01

With the rapid evolution of wireless communication technology, integrating various communication modes in a mobile terminal has become the popular trend. Because of this, multi-standard wireless technology is one of the hot spots in current research. This paper presents a wideband fractional-N frequency divider of the multi-standard wireless transceiver for many applications. High-speed divider-by-2 with traditional source-coupled-logic is designed for very wide band usage. Phase switching technique and a chain of divider-by-2/3 are applied to the programmable frequency divider with 0.5 step. The phase noise of the whole frequency synthesizer will be decreased by the narrower step of programmable frequency divider. Δ-Σ modulator is achieved by an improved MASH 1-1-1 structure. This structure has excellent performance in many ways, such as noise, spur and input dynamic range. Fabricated in TSMC 0.18μm CMOS process, the fractional-N frequency divider occupies a chip area of 1130 × 510 μm2 and it can correctly divide within the frequency range of 0.8-9 GHz. With 1.8 V supply voltage, its division ratio ranges from 62.5 to 254 and the total current consumption is 29 mA.

On Polymorphic Circuits and Their Design Using Evolutionary Algorithms

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo; Keymeulen, Didier; Lohn, Jason; Clancy, Daniel (Technical Monitor)

2002-01-01

This paper introduces the concept of polymorphic electronics (polytronics) - referring to electronics with superimposed built-in functionality. A function change does not require switches/reconfiguration as in traditional approaches. Instead the change comes from modifications in the characteristics of devices involved in the circuit, in response to controls such as temperature, power supply voltage (VDD), control signals, light, etc. The paper illustrates polytronic circuits in which the control is done by temperature, morphing signals, and VDD respectively. Polytronic circuits are obtained by evolutionary design/evolvable hardware techniques. These techniques are ideal for the polytronics design, a new area that lacks design guidelines, know-how,- yet the requirements/objectives are easy to specify and test. The circuits are evolved/synthesized in two different modes. The first mode explores an unstructured space, in which transistors can be interconnected freely in any arrangement (in simulations only). The second mode uses a Field Programmable Transistor Array (FPTA) model, and the circuit topology is sought as a mapping onto a programmable architecture (these experiments are performed both in simulations and on FPTA chips). The experiments demonstrated the synthesis. of polytronic circuits by evolution. The capacity of storing/hiding "extra" functions provides for watermark/invisible functionality, thus polytronics may find uses in intelligence/security applications.

A CMOS Neural Interface for a Multichannel Vestibular Prosthesis

PubMed Central

Hageman, Kristin N.; Kalayjian, Zaven K.; Tejada, Francisco; Chiang, Bryce; Rahman, Mehdi A.; Fridman, Gene Y.; Dai, Chenkai; Pouliquen, Philippe O.; Georgiou, Julio; Della Santina, Charles C.; Andreou, Andreas G.

2015-01-01

We present a high-voltage CMOS neural-interface chip for a multichannel vestibular prosthesis (MVP) that measures head motion and modulates vestibular nerve activity to restore vision- and posture-stabilizing reflexes. This application specific integrated circuit neural interface (ASIC-NI) chip was designed to work with a commercially available microcontroller, which controls the ASIC-NI via a fast parallel interface to deliver biphasic stimulation pulses with 9-bit programmable current amplitude via 16 stimulation channels. The chip was fabricated in the ONSemi C5 0.5 micron, high-voltage CMOS process and can accommodate compliance voltages up to 12 V, stimulating vestibular nerve branches using biphasic current pulses up to 1.45 ± 0.06 mA with durations as short as 10 µs/phase. The ASIC-NI includes a dedicated digital-to-analog converter for each channel, enabling it to perform complex multipolar stimulation. The ASIC-NI replaces discrete components that cover nearly half of the 2nd generation MVP (MVP2) printed circuit board, reducing the MVP system size by 48% and power consumption by 17%. Physiological tests of the ASIC-based MVP system (MVP2A) in a rhesus monkey produced reflexive eye movement responses to prosthetic stimulation similar to those observed when using the MVP2. Sinusoidal modulation of stimulus pulse rate from 68–130 pulses per second at frequencies from 0.1 to 5 Hz elicited appropriately-directed slow phase eye velocities ranging in amplitude from 1.9–16.7°/s for the MVP2 and 2.0–14.2°/s for the MVP2A. The eye velocities evoked by MVP2 and MVP2A showed no significant difference (t-test, p = 0.034), suggesting that the MVP2A achieves performance at least as good as the larger MVP2. PMID:25974945

Implementing inverted master-slave 3D semiconductor stack

DOE Office of Scientific and Technical Information (OSTI.GOV)

Coteus, Paul W.; Hall, Shawn A.; Takken, Todd E.

2016-03-08

A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap regionmore » defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.« less

Compression Debarking of Stored Wood Chips

Treesearch

James A. Mattson

1974-01-01

Two 750 ft. piles of unbarked chips were stored for 1 year to evaluate the effect of chip storage on the effectiveness of bark-chip separations-segregation methods under study. in processing stored chips suffered more wood loss than fresh chips.

On-chip visual perception of motion: a bio-inspired connectionist model on FPGA.

PubMed

Torres-Huitzil, César; Girau, Bernard; Castellanos-Sánchez, Claudio

2005-01-01

Visual motion provides useful information to understand the dynamics of a scene to allow intelligent systems interact with their environment. Motion computation is usually restricted by real time requirements that need the design and implementation of specific hardware architectures. In this paper, the design of hardware architecture for a bio-inspired neural model for motion estimation is presented. The motion estimation is based on a strongly localized bio-inspired connectionist model with a particular adaptation of spatio-temporal Gabor-like filtering. The architecture is constituted by three main modules that perform spatial, temporal, and excitatory-inhibitory connectionist processing. The biomimetic architecture is modeled, simulated and validated in VHDL. The synthesis results on a Field Programmable Gate Array (FPGA) device show the potential achievement of real-time performance at an affordable silicon area.

VizieR Online Data Catalog: Supernova rates from STRESS (Botticella+, 2008)

NASA Astrophysics Data System (ADS)

Botticella, M. T.; Riello, M.; Cappellaro, E.; Benetti, S.; Altavilla, G.; Pastorello, A.; Turatto, M.; Greggio, L.; Patat, F.; Valenti, S.; Zampieri, L.; Harutyunyan, A.; Pignata, G.; Taubenberger, S.

2008-04-01

Observations were carried out using the Wide Field Imager (WFI) at the 2.2m MPG/ESO telescope at La Silla, Chile. WFI is a mosaic camera consisting of 2x4 CCDs, each of 2048x4096 pixels, with a pixel scale of 0.238arcsec and a field of view of 34x33arcmin2. The individual chips are separated by gaps of 23.8arcsec and 14.3arcsec along right ascension and declination respectively, for a resulting filling factor of 95.9%. We performed observations in the B,V,R,I bands using the following ESO/WFI broad-band filters: B/99, B/123, V/89, Rc/162, Ic/lwp. The observing programme was distributed over a period of 6 years, from 1999 to 2005. (3 data files).

Witnessing eigenstates for quantum simulation of Hamiltonian spectra

PubMed Central

Santagati, Raffaele; Wang, Jianwei; Gentile, Antonio A.; Paesani, Stefano; Wiebe, Nathan; McClean, Jarrod R.; Morley-Short, Sam; Shadbolt, Peter J.; Bonneau, Damien; Silverstone, Joshua W.; Tew, David P.; Zhou, Xiaoqi; O’Brien, Jeremy L.; Thompson, Mark G.

2018-01-01

The efficient calculation of Hamiltonian spectra, a problem often intractable on classical machines, can find application in many fields, from physics to chemistry. We introduce the concept of an “eigenstate witness” and, through it, provide a new quantum approach that combines variational methods and phase estimation to approximate eigenvalues for both ground and excited states. This protocol is experimentally verified on a programmable silicon quantum photonic chip, a mass-manufacturable platform, which embeds entangled state generation, arbitrary controlled unitary operations, and projective measurements. Both ground and excited states are experimentally found with fidelities >99%, and their eigenvalues are estimated with 32 bits of precision. We also investigate and discuss the scalability of the approach and study its performance through numerical simulations of more complex Hamiltonians. This result shows promising progress toward quantum chemistry on quantum computers. PMID:29387796

Comparison of laser Doppler and laser speckle contrast imaging using a concurrent processing system

NASA Astrophysics Data System (ADS)

Sun, Shen; Hayes-Gill, Barrie R.; He, Diwei; Zhu, Yiqun; Huynh, Nam T.; Morgan, Stephen P.

2016-08-01

Full field laser Doppler imaging (LDI) and single exposure laser speckle contrast imaging (LSCI) are directly compared using a novel instrument which can concurrently image blood flow using both LDI and LSCI signal processing. Incorporating a commercial CMOS camera chip and a field programmable gate array (FPGA) the flow images of LDI and the contrast maps of LSCI are simultaneously processed by utilizing the same detected optical signals. The comparison was carried out by imaging a rotating diffuser. LDI has a linear response to the velocity. In contrast, LSCI is exposure time dependent and does not provide a linear response in the presence of static speckle. It is also demonstrated that the relationship between LDI and LSCI can be related through a power law which depends on the exposure time of LSCI.

Lensless transport-of-intensity phase microscopy and tomography with a color LED matrix

NASA Astrophysics Data System (ADS)

Zuo, Chao; Sun, Jiasong; Zhang, Jialin; Hu, Yan; Chen, Qian

2015-07-01

We demonstrate lens-less quantitative phase microscopy and diffraction tomography based on a compact on-chip platform, using only a CMOS image sensor and a programmable color LED array. Based on multi-wavelength transport-of- intensity phase retrieval and multi-angle illumination diffraction tomography, this platform offers high quality, depth resolved images with a lateral resolution of ˜3.7μm and an axial resolution of ˜5μm, over wide large imaging FOV of 24mm2. The resolution and FOV can be further improved by using a larger image sensors with small pixels straightforwardly. This compact, low-cost, robust, portable platform with a decent imaging performance may offer a cost-effective tool for telemedicine needs, or for reducing health care costs for point-of-care diagnostics in resource-limited environments.

Optoelectrofluidic platforms for chemistry and biology.

PubMed

Hwang, Hyundoo; Park, Je-Kyun

2011-01-07

Extraordinary advances in lab on a chip systems have been made on the basis of the development of micro/nanofluidics and its fusion with other technologies based on electrokinetics and optics. Optoelectrofluidic technology, which has been recently introduced as a new manipulation scheme, allows programmable manipulation of particles or fluids in microenvironments based on optically induced electrokinetics. Herein, the behaviour of particles or fluids can be controlled by inducing or perturbing electric fields on demand in an optical manner, which includes photochemical, photoconductive, and photothermal effects. This elegant scheme of the optoelectrofluidic platform has attracted attention in various fields of science and engineering. A lot of research on optoelectrofluidic manipulation technologies has been reported and the field has advanced rapidly, although some technical hurdles still remain. This review describes recent developments and future perspectives of optoelectrofluidic platforms for chemical and biological applications.

Attachment method for stacked integrated circuit (IC) chips

DOEpatents

Bernhardt, Anthony F.; Malba, Vincent

1999-01-01

An attachment method for stacked integrated circuit (IC) chips. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM.

Attachment method for stacked integrated circuit (IC) chips

DOEpatents

Bernhardt, A.F.; Malba, V.

1999-08-03

An attachment method for stacked integrated circuit (IC) chips is disclosed. The method involves connecting stacked chips, such as DRAM memory chips, to each other and/or to a circuit board. Pads on the individual chips are rerouted to form pads on the side of the chip, after which the chips are stacked on top of each other whereby desired interconnections to other chips or a circuit board can be accomplished via the side-located pads. The pads on the side of a chip are connected to metal lines on a flexible plastic tape (flex) by anisotropically conductive adhesive (ACA). Metal lines on the flex are likewise connected to other pads on chips and/or to pads on a circuit board. In the case of a stack of DRAM chips, pads to corresponding address lines on the various chips may be connected to the same metal line on the flex to form an address bus. This method has the advantage of reducing the number of connections required to be made to the circuit board due to bussing; the flex can accommodate dimensional variation in the alignment of chips in the stack; bonding of the ACA is accomplished at low temperature and is otherwise simpler and less expensive than solder bonding; chips can be bonded to the ACA all at once if the sides of the chips are substantially coplanar, as in the case for stacks of identical chips, such as DRAM. 12 figs.

An IO block array in a radiation-hardened SOI SRAM-based FPGA

NASA Astrophysics Data System (ADS)

Yan, Zhao; Lihua, Wu; Xiaowei, Han; Yan, Li; Qianli, Zhang; Liang, Chen; Guoquan, Zhang; Jianzhong, Li; Bo, Yang; Jiantou, Gao; Jian, Wang; Ming, Li; Guizhai, Liu; Feng, Zhang; Xufeng, Guo; Kai, Zhao; Chen, Stanley L.; Fang, Yu; Zhongli, Liu

2012-01-01

We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field-programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si), a dose survivability rate of 1.5 × 1011 rad(Si)/s, and a neutron fluence immunity of 1 × 1014 n/cm2.

Comparison of contamination of femoral heads and pre-processed bone chips during hip revision arthroplasty.

PubMed

Mathijssen, N M C; Sturm, P D; Pilot, P; Bloem, R M; Buma, P; Petit, P L; Schreurs, B W

2013-12-01

With bone impaction grafting, cancellous bone chips made from allograft femoral heads are impacted in a bone defect, which introduces an additional source of infection. The potential benefit of the use of pre-processed bone chips was investigated by comparing the bacterial contamination of bone chips prepared intraoperatively with the bacterial contamination of pre-processed bone chips at different stages in the surgical procedure. To investigate baseline contamination of the bone grafts, specimens were collected during 88 procedures before actual use or preparation of the bone chips: in 44 procedures intraoperatively prepared chips were used (Group A) and in the other 44 procedures pre-processed bone chips were used (Group B). In 64 of these procedures (32 using locally prepared bone chips and 32 using pre-processed bone chips) specimens were also collected later in the procedure to investigate contamination after use and preparation of the bone chips. In total, 8 procedures had one or more positive specimen(s) (12.5 %). Contamination rates were not significantly different between bone chips prepared at the operating theatre and pre-processed bone chips. In conclusion, there was no difference in bacterial contamination between bone chips prepared from whole femoral heads in the operating room and pre-processed bone chips, and therefore, both types of bone allografts are comparable with respect to risk of infection.

Repairable chip bonding/interconnect process

DOEpatents

Bernhardt, Anthony F.; Contolini, Robert J.; Malba, Vincent; Riddle, Robert A.

1997-01-01

A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

Novel tool wear monitoring method in milling difficult-to-machine materials using cutting chip formation

NASA Astrophysics Data System (ADS)

Zhang, P. P.; Guo, Y.; Wang, B.

2017-05-01

The main problems in milling difficult-to-machine materials are the high cutting temperature and rapid tool wear. However it is impossible to investigate tool wear in machining. Tool wear and cutting chip formation are two of the most important representations for machining efficiency and quality. The purpose of this paper is to develop the model of tool wear with cutting chip formation (width of chip and radian of chip) on difficult-to-machine materials. Thereby tool wear is monitored by cutting chip formation. A milling experiment on the machining centre with three sets cutting parameters was performed to obtain chip formation and tool wear. The experimental results show that tool wear increases gradually along with cutting process. In contrast, width of chip and radian of chip decrease. The model is developed by fitting the experimental data and formula transformations. The most of monitored errors of tool wear by the chip formation are less than 10%. The smallest error is 0.2%. Overall errors by the radian of chip are less than the ones by the width of chip. It is new way to monitor and detect tool wear by cutting chip formation in milling difficult-to-machine materials.

Expression and significance of CHIP in canine mammary gland tumors

PubMed Central

WANG, Huanan; YANG, Xu; JIN, Yipeng; PEI, Shimin; ZHANG, Di; MA, Wen; HUANG, Jian; QIU, Hengbin; ZHANG, Xinke; JIANG, Qiuyue; SUN, Weidong; ZHANG, Hong; LIN, Degui

2015-01-01

CHIP (Carboxy terminus of Hsc70 Interacting Protein) is an E3 ubiquitin ligase that can induce ubiquitination and degradation of several oncogenic proteins. The expression of CHIP is frequently lower in human breast cancer than in normal breast tissue. However, the expression and role of CHIP in the canine mammary gland tumor (CMGT) remain unclear. We investigated the potential correlation between CHIP expression and mammary gland tumor prognosis in female dogs. CHIP expression was measured in 54 dogs by immunohistochemistry and real-time RT-PCR. CHIP protein expression was significantly correlated with the histopathological diagnosis, outcome of disease and tumor classification. The transcriptional level of CHIP was significantly higher in normal tissues (P=0.001) and benign tumors (P=0.009) than it in malignant tumors. CHIP protein expression was significantly correlated with the transcriptional level of CHIP (P=0.0102). The log-rank test survival curves indicated that patients with low expression of CHIP had shorter overall periods of survival than those with higher CHIP protein expression (P=0.050). Our data suggest that CHIP may play an important role in the formation and development of CMGTs and serve as a valuable prognostic marker and potential target for genetic therapy. PMID:26156079

On-chip concentration of bacteria using a 3D dielectrophoretic chip and subsequent laser-based DNA extraction in the same chip

NASA Astrophysics Data System (ADS)

Cho, Yoon-Kyoung; Kim, Tae-hyeong; Lee, Jeong-Gun

2010-06-01

We report the on-chip concentration of bacteria using a dielectrophoretic (DEP) chip with 3D electrodes and subsequent laser-based DNA extraction in the same chip. The DEP chip has a set of interdigitated Au post electrodes with 50 µm height to generate a network of non-uniform electric fields for the efficient trapping by DEP. The metal post array was fabricated by photolithography and subsequent Ni and Au electroplating. Three model bacteria samples (Escherichia coli, Staphylococcus epidermidis, Streptococcus mutans) were tested and over 80-fold concentrations were achieved within 2 min. Subsequently, on-chip DNA extraction from the concentrated bacteria in the 3D DEP chip was performed by laser irradiation using the laser-irradiated magnetic bead system (LIMBS) in the same chip. The extracted DNA was analyzed with silicon chip-based real-time polymerase chain reaction (PCR). The total process of on-chip bacteria concentration and the subsequent DNA extraction can be completed within 10 min including the manual operation time.

3D printed high density, reversible, chip-to-chip microfluidic interconnects.

PubMed

Gong, Hua; Woolley, Adam T; Nordin, Gregory P

2018-02-13

Our latest developments in miniaturizing 3D printed microfluidics [Gong et al., Lab Chip, 2016, 16, 2450; Gong et al., Lab Chip, 2017, 17, 2899] offer the opportunity to fabricate highly integrated chips that measure only a few mm on a side. For such small chips, an interconnection method is needed to provide the necessary world-to-chip reagent and pneumatic connections. In this paper, we introduce simple integrated microgaskets (SIMs) and controlled-compression integrated microgaskets (CCIMs) to connect a small device chip to a larger interface chip that implements world-to-chip connections. SIMs or CCIMs are directly 3D printed as part of the device chip, and therefore no additional materials or components are required to make the connection to the larger 3D printed interface chip. We demonstrate 121 chip-to-chip interconnections in an 11 × 11 array for both SIMs and CCIMs with an areal density of 53 interconnections per mm 2 and show that they withstand fluid pressures of 50 psi. We further demonstrate their reusability by testing the devices 100 times without seal failure. Scaling experiments show that 20 × 20 interconnection arrays are feasible and that the CCIM areal density can be increased to 88 interconnections per mm 2 . We then show the utility of spatially distributed discrete CCIMs by using an interconnection chip with 28 chip-to-world interconnects to test 45 3D printed valves in a 9 × 5 array. Each valve is only 300 μm in diameter (the smallest yet reported for 3D printed valves). Every row of 5 valves is tested to at least 10 000 actuations, with one row tested to 1 000 000 actuations. In all cases, there is no sign of valve failure, and the CCIM interconnections prove an effective means of using a single interface chip to test a series of valve array chips.

Repairable chip bonding/interconnect process

DOEpatents

Bernhardt, A.F.; Contolini, R.J.; Malba, V.; Riddle, R.A.

1997-08-05

A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules is disclosed. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder. 10 figs.

A 1024-Channel CMOS Microelectrode Array With 26,400 Electrodes for Recording and Stimulation of Electrogenic Cells In Vitro

PubMed Central

Ballini, Marco; Müller, Jan; Livi, Paolo; Chen, Yihui; Frey, Urs; Stettler, Alexander; Shadmani, Amir; Viswam, Vijay; Jones, Ian Lloyd; Jäckel, David; Radivojevic, Milos; Lewandowska, Marta K.; Gong, Wei; Fiscella, Michele; Bakkum, Douglas J.; Heer, Flavio; Hierlemann, Andreas

2017-01-01

To advance our understanding of the functioning of neuronal ensembles, systems are needed to enable simultaneous recording from a large number of individual neurons at high spatiotemporal resolution and good signal-to-noise ratio. Moreover, stimulation capability is highly desirable for investigating, for example, plasticity and learning processes. Here, we present a microelectrode array (MEA) system on a single CMOS die for in vitro recording and stimulation. The system incorporates 26,400 platinum electrodes, fabricated by in-house post-processing, over a large sensing area (3.85 × 2.10 mm2) with sub-cellular spatial resolution (pitch of 17.5 μm). Owing to an area and power efficient implementation, we were able to integrate 1024 readout channels on chip to record extracellular signals from a user-specified selection of electrodes. These channels feature noise values of 2.4 μVrms in the action-potential band (300 Hz–10 kHz) and 5.4 μVrms in the local-field-potential band (1 Hz–300 Hz), and provide programmable gain (up to 78 dB) to accommodate various biological preparations. Amplified and filtered signals are digitized by 10 bit parallel single-slope ADCs at 20 kSamples/s. The system also includes 32 stimulation units, which can elicit neural spikes through either current or voltage pulses. The chip consumes only 75 mW in total, which obviates the need of active cooling even for sensitive cell cultures. PMID:28502989

Optical Characterization of Tissue Phantoms Using a Silicon Integrated fdNIRS System on Chip.

PubMed

Sthalekar, Chirag C; Miao, Yun; Koomson, Valencia Joyner

2017-04-01

An interface circuit with signal processing and digitizing circuits for a high frequency, large area avalanche photodiode (APD) has been integrated in a 130 nm BiCMOS chip. The system enables the absolute oximetry of tissue using frequency domain Near Infrared Spectroscopy (fdNIRS). The system measures the light absorbed and scattered by the tissue by measuring the reduction in the amplitude of signal and phase shift introduced between the light source and detector which are placed a finite distance away from each other. The received 80 MHz RF signal is downconverted to a low frequency and amplified using a heterodyning scheme. The front-end transimpedance amplifier has a 3-level programmable gain that increases the dynamic range to 60 dB. The phase difference between an identical reference channel and the optical channel is measured with a 0.5° accuracy. The detectable current range is [Formula: see text] and with a 40 A/W reponsivity using the APD, power levels as low as 500 pW can be detected. Measurements of the absorption and reduced scattering coefficients of solid tissue phantoms using this system are compared with those using a commercial instrument with differences within 30%. Measurement of a milk based liquid tissue phantom show an increase in absorption coefficient with addition of black ink. The miniaturized circuit serves as an efficiently scalable system for multi-site detection for applications in neonatal cerebral oximetry and optical mammography.

Many-core computing for space-based stereoscopic imaging

NASA Astrophysics Data System (ADS)

McCall, Paul; Torres, Gildo; LeGrand, Keith; Adjouadi, Malek; Liu, Chen; Darling, Jacob; Pernicka, Henry

The potential benefits of using parallel computing in real-time visual-based satellite proximity operations missions are investigated. Improvements in performance and relative navigation solutions over single thread systems can be achieved through multi- and many-core computing. Stochastic relative orbit determination methods benefit from the higher measurement frequencies, allowing them to more accurately determine the associated statistical properties of the relative orbital elements. More accurate orbit determination can lead to reduced fuel consumption and extended mission capabilities and duration. Inherent to the process of stereoscopic image processing is the difficulty of loading, managing, parsing, and evaluating large amounts of data efficiently, which may result in delays or highly time consuming processes for single (or few) processor systems or platforms. In this research we utilize the Single-Chip Cloud Computer (SCC), a fully programmable 48-core experimental processor, created by Intel Labs as a platform for many-core software research, provided with a high-speed on-chip network for sharing information along with advanced power management technologies and support for message-passing. The results from utilizing the SCC platform for the stereoscopic image processing application are presented in the form of Performance, Power, Energy, and Energy-Delay-Product (EDP) metrics. Also, a comparison between the SCC results and those obtained from executing the same application on a commercial PC are presented, showing the potential benefits of utilizing the SCC in particular, and any many-core platforms in general for real-time processing of visual-based satellite proximity operations missions.

Chip, Chip, Hooray!

ERIC Educational Resources Information Center

Kelly, Susan

2001-01-01

Presents a science laboratory using different brands of potato chips in which students test their oiliness, size, thickness, saltiness, quality, and cost, then analyze the results to determine the best chip. Gives a brief history of potato chips. (YDS)

Capillary-Driven Microfluidic Chips for Miniaturized Immunoassays: Efficient Fabrication and Sealing of Chips Using a "Chip-Olate" Process.

PubMed

Temiz, Yuksel; Delamarche, Emmanuel

2017-01-01

The fabrication of silicon-based microfluidic chips is invaluable in supporting the development of many microfluidic concepts for research in the life sciences and in vitro diagnostic applications such as the realization of miniaturized immunoassays using capillary-driven chips. While being extremely abundant, the literature covering microfluidic chip fabrication and assay development might not have addressed properly the challenge of fabricating microfluidic chips on a wafer level or the need for dicing wafers to release chips that need then to be further processed, cleaned, rinsed, and dried one by one. Here, we describe the "chip-olate" process wherein microfluidic structures are formed on a silicon wafer, followed by partial dicing, cleaning, and drying steps. Then, integration of reagents (if any) can be done, followed by lamination of a sealing cover. Breaking by hand the partially diced wafer yields individual chips ready for use.

A multi-year survey of stem-end chip defect in chipping potatoes (Solanum tuberosum L.)

USDA-ARS?s Scientific Manuscript database

One of the most serious tuber quality concerns of US chip potato growers is stem-end chip defect, which is defined as a localized post-fry discoloration in and adjacent to the vasculature on the stem end portion of potato chips. The incidence and severity of stem-end chip defect vary with growing lo...

CHIP promotes thyroid cancer proliferation via activation of the MAPK and AKT pathways

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Li; Liu, Lianyong; Department of Endocrinology, Shanghai Punan Hospital, Shanghai 200125

The carboxyl terminus of Hsp70-interacting protein (CHIP) is a U box-type ubiquitin ligase that plays crucial roles in various biological processes, including tumor progression. To date, the functional mechanism of CHIP in thyroid cancer remains unknown. Here, we obtained evidence of upregulation of CHIP in thyroid cancer tissues and cell lines. CHIP overexpression markedly enhanced thyroid cancer cell viability and colony formation in vitro and accelerated tumor growth in vivo. Conversely, CHIP knockdown impaired cell proliferation and tumor growth. Notably, CHIP promoted cell growth through activation of MAPK and AKT pathways, subsequently decreasing p27 and increasing cyclin D1 and p-FOXO3a expression. Ourmore » findings collectively indicate that CHIP functions as an oncogene in thyroid cancer, and is therefore a potential therapeutic target for this disease. - Highlights: • CHIP is significantly upregulated in thyroid cancer cells. • Overexpression of CHIP facilitates proliferation and tumorigenesis of thyroid cancer cells. • Silencing of CHIP inhibits the proliferation and tumorigenesis of thyroid cancer cells. • CHIP promotes thyroid cancer cell proliferation via activating the MAPK and AKT pathways.« less

A digitalized silicon microgyroscope based on embedded FPGA.

PubMed

Xia, Dunzhu; Yu, Cheng; Wang, Yuliang

2012-09-27

This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC) loop and software phase-locked loop (SPLL) based on the Coordinated Rotation Digital Computer (CORDIC) algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD) are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system.

A Digitalized Silicon Microgyroscope Based on Embedded FPGA

PubMed Central

Xia, Dunzhu; Yu, Cheng; Wang, Yuliang

2012-01-01

This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC) loop and software phase-locked loop (SPLL) based on the Coordinated Rotation Digital Computer (CORDIC) algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD) are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system. PMID:23201990

The MPGD-based photon detectors for the upgrade of COMPASS RICH-1

NASA Astrophysics Data System (ADS)

Alexeev, M.; Azevedo, C. D. R.; Birsa, R.; Bradamante, F.; Bressan, A.; Büchele, M.; Chiosso, M.; Ciliberti, P.; Dalla Torre, S.; Dasgupta, S.; Denisov, O.; Finger, M.; Finger, M.; Fischer, H.; Gobbo, B.; Gregori, M.; Hamar, G.; Herrmann, F.; Levorato, S.; Maggiora, A.; Makke, A.; Martin, A.; Menon, G.; Steiger, K.; Novy, J.; Panzieri, D.; Pereira, F. A. B.; Santos, C. A.; Sbrizzai, G.; Schopferer, S.; Slunecka, M.; Steiger, L.; Sulc, M.; Tessarotto, F.; Veloso, J. F. C. A.

2017-12-01

The RICH-1 Detector of the COMPASS experiment at CERN SPS has undergone an important upgrade for the 2016 physics run. Four new photon detectors, based on Micro Pattern Gaseous Detector technology and covering a total active area larger than 1.2 m2 have replaced the previously used MWPC-based photon detectors. The upgrade answers the challenging efficiency and stability quest for the new phase of the COMPASS spectrometer physics programme. The new detector architecture consists in a hybrid MPGD combination of two Thick Gas Electron Multipliers and a MicroMegas stage. Signals, extracted from the anode pad by capacitive coupling, are read-out by analog F-E based on the APV25 chip. The main aspects of the COMPASS RICH-1 photon detectors upgrade are presented focussing on detector design, engineering aspects, mass production, the quality assessment and assembly challenges of the MPGD components. The status of the detector commissioning is also presented.

A novel setup for wafer curvature measurement at very high heating rates.

PubMed

Islam, T; Zechner, J; Bernardoni, M; Nelhiebel, M; Pippan, R

2017-02-01

The curvature evolution of a thin film layer stack containing a top Al layer is measured during temperature cycles with very high heating rates. The temperature cycles are generated by means of programmable electrical power pulses applied to miniaturized polysilicon heater systems embedded inside a semiconductor chip and the curvature is measured by a fast wafer curvature measurement setup. Fast temperature cycles with heating duration of 100 ms are created to heat the specimen up to 270 °C providing an average heating rate of 2500 K/s. As a second approach, curvature measurement utilizing laser scanning Doppler vibrometry is also demonstrated which verifies the results obtained from the fast wafer curvature measurement setup. Film stresses calculated from the measured curvature values compare well to literature results, indicating that the new method can be used to measure curvature during fast temperature cycling.

Performance evaluation of heart sound cancellation in FPGA hardware implementation for electronic stethoscope.

PubMed

Chao, Chun-Tang; Maneetien, Nopadon; Wang, Chi-Jo; Chiou, Juing-Shian

2014-01-01

This paper presents the design and evaluation of the hardware circuit for electronic stethoscopes with heart sound cancellation capabilities using field programmable gate arrays (FPGAs). The adaptive line enhancer (ALE) was adopted as the filtering methodology to reduce heart sound attributes from the breath sounds obtained via the electronic stethoscope pickup. FPGAs were utilized to implement the ALE functions in hardware to achieve near real-time breath sound processing. We believe that such an implementation is unprecedented and crucial toward a truly useful, standalone medical device in outpatient clinic settings. The implementation evaluation with one Altera cyclone II-EP2C70F89 shows that the proposed ALE used 45% resources of the chip. Experiments with the proposed prototype were made using DE2-70 emulation board with recorded body signals obtained from online medical archives. Clear suppressions were observed in our experiments from both the frequency domain and time domain perspectives.

A digital receiver module with direct data acquisition for magnetic resonance imaging systems.

PubMed

Tang, Weinan; Sun, Hongyu; Wang, Weimin

2012-10-01

A digital receiver module for magnetic resonance imaging (MRI) with detailed hardware implementations is presented. The module is based on a direct sampling scheme using the latest mixed-signal circuit design techniques. A single field-programmable gate array chip is employed to perform software-based digital down conversion for radio frequency signals. The modular architecture of the receiver allows multiple acquisition channels to be implemented on a highly integrated printed circuit board. To maintain the phase coherence of the receiver and the exciter in the context of direct sampling, an effective phase synchronization method was proposed to achieve a phase deviation as small as 0.09°. The performance of the described receiver module was verified in the experiments for both low- and high-field (0.5 T and 1.5 T) MRI scanners and was compared to a modern commercial MRI receiver system.

Heavy-Ion Microbeam Fault Injection into SRAM-Based FPGA Implementations of Cryptographic Circuits

NASA Astrophysics Data System (ADS)

Li, Huiyun; Du, Guanghua; Shao, Cuiping; Dai, Liang; Xu, Guoqing; Guo, Jinlong

2015-06-01

Transistors hit by heavy ions may conduct transiently, thereby introducing transient logic errors. Attackers can exploit these abnormal behaviors and extract sensitive information from the electronic devices. This paper demonstrates an ion irradiation fault injection attack experiment into a cryptographic field-programmable gate-array (FPGA) circuit. The experiment proved that the commercial FPGA chip is vulnerable to low-linear energy transfer carbon irradiation, and the attack can cause the leakage of secret key bits. A statistical model is established to estimate the possibility of an effective fault injection attack on cryptographic integrated circuits. The model incorporates the effects from temporal, spatial, and logical probability of an effective attack on the cryptographic circuits. The rate of successful attack calculated from the model conforms well to the experimental results. This quantitative success rate model can help evaluate security risk for designers as well as for the third-party assessment organizations.

A low power low noise analog front end for portable healthcare system

NASA Astrophysics Data System (ADS)

Yanchao, Wang; Keren, Ke; Wenhui, Qin; Yajie, Qin; Ting, Yi; Zhiliang, Hong

2015-10-01

The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5-100 Hz) and the achieved noise efficient factor is 6.48. Project supported by the Science and Technology Commission of Shanghai Municipality (No. 13511501100), the State Key Laboratory Project of China (No. 11MS002), and the State Key Laboratory of ASIC & System, Fudan University.

Multidimensional quantum entanglement with large-scale integrated optics.

PubMed

Wang, Jianwei; Paesani, Stefano; Ding, Yunhong; Santagati, Raffaele; Skrzypczyk, Paul; Salavrakos, Alexia; Tura, Jordi; Augusiak, Remigiusz; Mančinska, Laura; Bacco, Davide; Bonneau, Damien; Silverstone, Joshua W; Gong, Qihuang; Acín, Antonio; Rottwitt, Karsten; Oxenløwe, Leif K; O'Brien, Jeremy L; Laing, Anthony; Thompson, Mark G

2018-04-20

The ability to control multidimensional quantum systems is central to the development of advanced quantum technologies. We demonstrate a multidimensional integrated quantum photonic platform able to generate, control, and analyze high-dimensional entanglement. A programmable bipartite entangled system is realized with dimensions up to 15 × 15 on a large-scale silicon photonics quantum circuit. The device integrates more than 550 photonic components on a single chip, including 16 identical photon-pair sources. We verify the high precision, generality, and controllability of our multidimensional technology, and further exploit these abilities to demonstrate previously unexplored quantum applications, such as quantum randomness expansion and self-testing on multidimensional states. Our work provides an experimental platform for the development of multidimensional quantum technologies. Copyright © 2018 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claim to original U.S. Government Works.

Upgrading the Digital Electronics of the PEP-II Bunch Current Monitors at the Stanford Linear Accelerator Center

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kline, Josh; /SLAC

2006-08-28

The testing of the upgrade prototype for the bunch current monitors (BCMs) in the PEP-II storage rings at the Stanford Linear Accelerator Center (SLAC) is the topic of this paper. Bunch current monitors are used to measure the charge in the electron/positron bunches traveling in particle storage rings. The BCMs in the PEP-II storage rings need to be upgraded because components of the current system have failed and are known to be failure prone with age, and several of the integrated chips are no longer produced making repairs difficult if not impossible. The main upgrade is replacing twelve old (1995)more » field programmable gate arrays (FPGAs) with a single Virtex II FPGA. The prototype was tested using computer synthesis tools, a commercial signal generator, and a fast pulse generator.« less

Optimised to Fail: Card Readers for Online Banking

NASA Astrophysics Data System (ADS)

Drimer, Saar; Murdoch, Steven J.; Anderson, Ross

The Chip Authentication Programme (CAP) has been introduced by banks in Europe to deal with the soaring losses due to online banking fraud. A handheld reader is used together with the customer’s debit card to generate one-time codes for both login and transaction authentication. The CAP protocol is not public, and was rolled out without any public scrutiny. We reverse engineered the UK variant of card readers and smart cards and here provide the first public description of the protocol. We found numerous weaknesses that are due to design errors such as reusing authentication tokens, overloading data semantics, and failing to ensure freshness of responses. The overall strategic error was excessive optimisation. There are also policy implications. The move from signature to PIN for authorising point-of-sale transactions shifted liability from banks to customers; CAP introduces the same problem for online banking. It may also expose customers to physical harm.

Low power, compact charge coupled device signal processing system

NASA Technical Reports Server (NTRS)

Bosshart, P. W.; Buss, D. D.; Eversole, W. L.; Hewes, C. R.; Mayer, D. J.

1980-01-01

A variety of charged coupled devices (CCDs) for performing programmable correlation for preprocessing environmental sensor data preparatory to its transmission to the ground were developed. A total of two separate ICs were developed and a third was evaluated. The first IC was a CCD chirp z transform IC capable of performing a 32 point DFT at frequencies to 1 MHz. All on chip circuitry operated as designed with the exception of the limited dynamic range caused by a fixed pattern noise due to interactions between the digital and analog circuits. The second IC developed was a 64 stage CCD analog/analog correlator for performing time domain correlation. Multiplier errors were found to be less than 1 percent at designed signal levels and less than 0.3 percent at the measured smaller levels. A prototype IC for performing time domain correlation was also evaluated.

Low-power chip-level optical interconnects based on bulk-silicon single-chip photonic transceivers

NASA Astrophysics Data System (ADS)

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Kim, Sun Ae; Oh, Jin Hyuk; Park, Jaegyu; Kim, Sanggi

2016-03-01

We present new scheme for chip-level photonic I/Os, based on monolithically integrated vertical photonic devices on bulk silicon, which increases the integration level of PICs to a complete photonic transceiver (TRx) including chip-level light source. A prototype of the single-chip photonic TRx based on a bulk silicon substrate demonstrated 20 Gb/s low power chip-level optical interconnects between fabricated chips, proving that this scheme can offer compact low-cost chip-level I/O solutions and have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, 3D-IC, and LAN/SAN/data-center and network applications.

Compact VLSI neural computer integrated with active pixel sensor for real-time ATR applications

NASA Astrophysics Data System (ADS)

Fang, Wai-Chi; Udomkesmalee, Gabriel; Alkalai, Leon

1997-04-01

A compact VLSI neural computer integrated with an active pixel sensor has been under development to mimic what is inherent in biological vision systems. This electronic eye- brain computer is targeted for real-time machine vision applications which require both high-bandwidth communication and high-performance computing for data sensing, synergy of multiple types of sensory information, feature extraction, target detection, target recognition, and control functions. The neural computer is based on a composite structure which combines Annealing Cellular Neural Network (ACNN) and Hierarchical Self-Organization Neural Network (HSONN). The ACNN architecture is a programmable and scalable multi- dimensional array of annealing neurons which are locally connected with their local neurons. Meanwhile, the HSONN adopts a hierarchical structure with nonlinear basis functions. The ACNN+HSONN neural computer is effectively designed to perform programmable functions for machine vision processing in all levels with its embedded host processor. It provides a two order-of-magnitude increase in computation power over the state-of-the-art microcomputer and DSP microelectronics. A compact current-mode VLSI design feasibility of the ACNN+HSONN neural computer is demonstrated by a 3D 16X8X9-cube neural processor chip design in a 2-micrometers CMOS technology. Integration of this neural computer as one slice of a 4'X4' multichip module into the 3D MCM based avionics architecture for NASA's New Millennium Program is also described.

Toward active-matrix lab-on-a-chip: programmable electrofluidic control enabled by arrayed oxide thin film transistors.

PubMed

Noh, Joo Hyon; Noh, Jiyong; Kreit, Eric; Heikenfeld, Jason; Rack, Philip D

2012-01-21

Agile micro- and nano-fluidic control is critical to numerous life science and chemical science synthesis as well as kinetic and thermodynamic studies. To this end, we have demonstrated the use of thin film transistor arrays as an active matrix addressing method to control an electrofluidic array. Because the active matrix method minimizes the number of control lines necessary (m + n lines for the m×n element array), the active matrix addressing method integrated with an electrofluidic platform can be a significant breakthrough for complex electrofluidic arrays (increased size or resolution) with enhanced function, agility and programmability. An amorphous indium gallium zinc oxide (a-IGZO) semiconductor active layer is used because of its high mobility of 1-15 cm(2) V(-1) s(-1), low-temperature processing and transparency for potential spectroscopy and imaging. Several electrofluidic functionalities are demonstrated using a simple 2 × 5 electrode array connected to a 2 × 5 IGZO thin film transistor array with the semiconductor channel width of 50 μm and mobility of 6.3 cm(2) V(-1) s(-1). Additionally, using the TFT device characteristics, active matrix addressing schemes are discussed as the geometry of the electrode array can be tailored to act as a storage capacitor element. Finally, requisite material and device parameters are discussed in context with a VGA scale active matrix addressed electrofluidic platform.

NASA Tech Briefs, October 2011

NASA Technical Reports Server (NTRS)

2011-01-01

Topics covered include: Laser Truss Sensor for Segmented Telescope Phasing; Qualifications of Bonding Process of Temperature Sensors to Deep-Space Missions; Optical Sensors for Monitoring Gamma and Neutron Radiation; Compliant Tactile Sensors; Cytometer on a Chip; Measuring Input Thresholds on an Existing Board; Scanning and Defocusing Properties of Microstrip Reflectarray Antennas; Cable Tester Box; Programmable Oscillator; Fault-Tolerant, Radiation-Hard DSP; Sub-Shot Noise Power Source for Microelectronics; Asynchronous Message Service Reference Implementation; Zero-Copy Objects System; Delay and Disruption Tolerant Networking MACHETE Model; Contact Graph Routing; Parallel Eclipse Project Checkout; Technique for Configuring an Actively Cooled Thermal Shield in a Flight System; Use of Additives to Improve Performance of Methyl Butyrate-Based Lithium-Ion Electrolytes; Li-Ion Cells Employing Electrolytes with Methyl Propionate and Ethyl Butyrate Co-Solvents; Improved Devices for Collecting Sweat for Chemical Analysis; Tissue Photolithography; Method for Impeding Degradation of Porous Silicon Structures; External Cooling Coupled to Reduced Extremity Pressure Device; A Zero-Gravity Cup for Drinking Beverages in Microgravity; Co-Flow Hollow Cathode Technology; Programmable Aperture with MEMS Microshutter Arrays; Polished Panel Optical Receiver for Simultaneous RF/Optical Telemetry with Large DSN Antennas; Adaptive System Modeling for Spacecraft Simulation; Lidar-Based Navigation Algorithm for Safe Lunar Landing; Tracking Object Existence From an Autonomous Patrol Vehicle; Rad-Hard, Miniaturized, Scalable, High-Voltage Switching Module for Power Applications; and Architecture for a 1-GHz Digital RADAR.

Study of heterogeneous and reconfigurable architectures in the communication domain

NASA Astrophysics Data System (ADS)

Feldkaemper, H. T.; Blume, H.; Noll, T. G.

2003-05-01

One of the most challenging design issues for next generations of (mobile) communication systems is fulfilling the computational demands while finding an appropriate trade-off between flexibility and implementation aspects, especially power consumption. Flexibility of modern architectures is desirable, e.g. concerning adaptation to new standards and reduction of time-to-market of a new product. Typical target architectures for future communication systems include embedded FPGAs, dedicated macros as well as programmable digital signal and control oriented processor cores as each of these has its specific advantages. These will be integrated as a System-on-Chip (SoC). For such a heterogeneous architecture a design space exploration and an appropriate partitioning plays a crucial role. On the exemplary vehicle of a Viterbi decoder as frequently used in communication systems we show which costs in terms of ATE complexity arise implementing typical components on different types of architecture blocks. A factor of about seven orders of magnitude spans between a physically optimised implementation and an implementation on a programmable DSP kernel. An implementation on an embedded FPGA kernel is in between these two representing an attractive compromise with high flexibility and low power consumption. Extending this comparison to further components, it is shown quantitatively that the cost ratio between different implementation alternatives is closely related to the operation to be performed. This information is essential for the appropriate partitioning of heterogeneous systems.

Effects of calcium supplements on the quality and acrylamide content of puffed shrimp chips.

PubMed

Chen, Tai-Yuan; Luo, Hsuan-Min; Hsu, Pang-Hung; Sung, Wen-Chieh

2016-01-01

The quality and acrylamide content of deep-fried and microwave-puffed shrimp chips fortified with 0.1%, 0.5%, or 1.0% calcium salts (calcium lactate, calcium carbonate, calcium citrate, or calcium acetate) were investigated. Microwave-puffed shrimp chips contained higher amounts of acrylamide (130.43 ppb) than did deep-fried shrimp chips. The greatest mitigation of acrylamide formation in overfried chips was obtained with 0.1% calcium lactate. All browning indexes of fortified shrimp chips, whether deep-fried or microwave-puffed, were reduced. L* values of microwave-puffed shrimp chips were higher than those of deep-fried shrimp chips, whereas a* and b* values and browning indexes were lower. Color differences (ΔE) between deep-fried puffed shrimp chips fortified with calcium salts and a control sample were higher than 5, and the sensory scores of shrimp chips were significantly decreased by the addition of calcium lactate. Copyright © 2015. Published by Elsevier B.V.

1H, 15N and 13C resonance assignments for free and IEEVD peptide-bound forms of the tetratricopeptide repeat domain from the human E3 ubiquitin ligase CHIP.

PubMed

Zhang, Huaqun; McGlone, Cameron; Mannion, Matthew M; Page, Richard C

2017-04-01

The ubiquitin ligase CHIP catalyzes covalent attachment of ubiquitin to unfolded proteins chaperoned by the heat shock proteins Hsp70/Hsc70 and Hsp90. CHIP interacts with Hsp70/Hsc70 and Hsp90 by binding of a C-terminal IEEVD motif found in Hsp70/Hsc70 and Hsp90 to the tetratricopeptide repeat (TPR) domain of CHIP. Although recruitment of heat shock proteins to CHIP via interaction with the CHIP-TPR domain is well established, alterations in structure and dynamics of CHIP upon binding are not well understood. In particular, the absence of a structure for CHIP-TPR in the free form presents a significant limitation upon studies seeking to rationally design inhibitors that may disrupt interactions between CHIP and heat shock proteins. Here we report the 1 H, 13 C, and 15 N backbone and side chain chemical shift assignments for CHIP-TPR in the free form, and backbone chemical shift assignments for CHIP-TPR in the IEEVD-bound form. The NMR resonance assignments will enable further studies examining the roles of dynamics and structure in regulating interactions between CHIP and the heat shock proteins Hsp70/Hsc70 and Hsp90.

ChIP and ChIP-Related Techniques: Expanding the Fields of Application and Improving ChIP Performance.

PubMed

Visa, Neus; Jordán-Pla, Antonio

2018-01-01

Protein-DNA interactions in vivo can be detected and quantified by chromatin immunoprecipitation (ChIP). ChIP has been instrumental for the advancement of epigenetics and has set the groundwork for the development of a number of ChIP-related techniques that have provided valuable information about the organization and function of genomes. Here, we provide an introduction to ChIP and discuss the applications of ChIP in different research areas. We also review some of the strategies that have been devised to improve ChIP performance.

Process for 3D chip stacking

DOEpatents

Malba, V.

1998-11-10

A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: (1) holding individual chips for batch processing, (2) depositing a dielectric passivation layer on the top and sidewalls of the chips, (3) opening vias in the dielectric, (4) forming the interconnects by laser pantography, and (5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume. 3 figs.

Process for 3D chip stacking

DOEpatents

Malba, Vincent

1998-01-01

A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: 1) holding individual chips for batch processing, 2) depositing a dielectric passivation layer on the top and sidewalls of the chips, 3) opening vias in the dielectric, 4) forming the interconnects by laser pantography, and 5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume.

The Ubiquitin Ligase CHIP Prevents SirT6 Degradation through Noncanonical Ubiquitination

PubMed Central

Ronnebaum, Sarah M.; Wu, Yaxu; McDonough, Holly

2013-01-01

The ubiquitin ligase CHIP (carboxyl terminus of Hsp70-interacting protein) regulates protein quality control, and CHIP deletion accelerates aging and reduces the life span in mice. Here, we reveal a mechanism for CHIP's influence on longevity by demonstrating that CHIP stabilizes the sirtuin family member SirT6, a lysine deacetylase/ADP ribosylase involved in DNA repair, metabolism, and longevity. In CHIP-deficient cells, SirT6 protein half-life is substantially reduced due to increased proteasome-mediated degradation, but CHIP overexpression in these cells increases SirT6 protein expression without affecting SirT6 transcription. CHIP noncanonically ubiquitinates SirT6 at K170, which stabilizes SirT6 and prevents SirT6 canonical ubiquitination by other ubiquitin ligases. In CHIP-depleted cells, SirT6 K170 mutation increases SirT6 half-life and prevents proteasome-mediated degradation. The global decrease in SirT6 expression in the absence of CHIP is associated with decreased SirT6 promoter occupancy, which increases histone acetylation and promotes downstream gene transcription in CHIP-depleted cells. Cells lacking CHIP are hypersensitive to DNA-damaging agents, but DNA repair and cell viability are rescued by enforced expression of SirT6. The discovery of this CHIP-SirT6 interaction represents a novel protein-stabilizing mechanism and defines an intersection between protein quality control and epigenetic regulation to influence pathways that regulate the biology of aging. PMID:24043303

[Preparation of poly(methyl acrylate) microfluidic chips surface-modified by hyperbranched polyamide ester and their application in the separation of biomolecules].

PubMed

Liu, Bing; Lin, Donge; Xu, Lin; Lei, Yanhui; Bo, Qianglong; Shou, Chongqi

2012-05-01

The surface of poly (methyl acrylate) (PMMA) microfluidic chips were modified using hyperbranched polyamide ester via chemical bonding. The contact angles of the modified chips were measured. The surface morphology was observed by scanning electron microscope (SEM) and stereo microscope. The results showed that the surface of the modified chips was coated by a dense, uniform, continuous, hydrophilic layer of hyperbranched polyamide ester. The hydrophilic of the chip surface was markedly improved. The contact angle of the chips modified decreased from 89.9 degrees to 29.5 degrees. The electro osmotic flow (EOF) in the modified microchannel was lower than that in the unmodified microchannel. Adenosine and L-lysine were detected and separated via the modified PMMA microfluidic chips. Compared with unmodified chips, the modified chips successfully separated the two biomolecules. The detection peaks were clear and sharp. The separation efficiencies of adenosine and L-lysine were 8.44 x 10(4) plates/m and 9.82 x 10(4) plates/m respectively, and the resolutions (Rs) was 5.31. The column efficiencies and resolutions of the modified chips were much higher than those of the unmodified chips. It was also observed that the modified chips possessed good reproducibility of migration time. This research may provide a new and effective method to improve the hydrophilicity of the PMMA surface and the application of PMMA microfluidic chips in the determination of trace biomolecules.

Millimeter-wave silicon-based ultra-wideband automotive radar transceivers

NASA Astrophysics Data System (ADS)

Jain, Vipul

Since the invention of the integrated circuit, the semiconductor industry has revolutionized the world in ways no one had ever anticipated. With the advent of silicon technologies, consumer electronics became light-weight and affordable and paved the way for an Information-Communication-Entertainment age. While silicon almost completely replaced compound semiconductors from these markets, it has been unable to compete in areas with more stringent requirements due to technology limitations. One of these areas is automotive radar sensors, which will enable next-generation collision-warning systems in automobiles. A low-cost implementation is absolutely essential for widespread use of these systems, which leads us to the subject of this dissertation---silicon-based solutions for automotive radars. This dissertation presents architectures and design techniques for mm-wave automotive radar transceivers. Several fully-integrated transceivers and receivers operating at 22-29 GHz and 77-81 GHz are demonstrated in both CMOS and SiGe BiCMOS technologies. Excellent performance is achieved indicating the suitability of silicon technologies for automotive radar sensors. The first CMOS 22-29-GHz pulse-radar receiver front-end for ultra-wideband radars is presented. The chip includes a low noise amplifier, I/Q mixers, quadrature voltage-controlled oscillators, pulse formers and variable-gain amplifiers. Fabricated in 0.18-mum CMOS, the receiver achieves a conversion gain of 35-38.1 dB and a noise figure of 5.5-7.4 dB. Integration of multi-mode multi-band transceivers on a single chip will enable next-generation low-cost automotive radar sensors. Two highly-integrated silicon ICs are designed in a 0.18-mum BiCMOS technology. These designs are also the first reported demonstrations of mm-wave circuits with high-speed digital circuits on the same chip. The first mm-wave dual-band frequency synthesizer and transceiver, operating in the 24-GHz and 77-GHz bands, are demonstrated. All circuits except the oscillators are shared between the two bands. A multi-functional injection-locked circuit is used after the oscillators to reconfigure the division ratio inside the phase-locked loop. The synthesizer is suitable for integration in automotive radar transceivers and heterodyne receivers for 94-GHz imaging applications. The transceiver chip includes a dual-band low noise amplifier, a shared downconversion chain, dual-band pulse formers, power amplifiers, a dual-band frequency synthesizer and a high-speed programmable baseband pulse generator. Radar functionality is demonstrated using loopback measurements.

CHIP involves in non-small cell lung cancer prognosis through VEGF pathway.

PubMed

Tingting, Qian; Jiao, Wang; Qingfeng, Wang; Yancheng, Liu; Shijun, Y U; Zhaoqi, Wang; Dongmei, Sun; ShiLong, Wang

2016-10-01

CHIP (c-terminal Hsp70-interacting protein) is an E3 ligase playing vital roles in various cancers. The VEGF pathway has become an important therapeutic target in non-small cell lung cancer (NSCLC). However, little is known about the role of CHIP and the relationship between CHIP and VEGF-VEGFR2 (VEGF receptor 2) pathway in NSCLC. In this study we aimed to investigate the clinical function of CHIP in NSCLC and explore the relevant regulatory mechanism. QRT-PCR was performed to detect CHIP expression in NSCLC tissues. The association of CHIP expression and clinical parameters was analyzed using the Chi-square test. Kaplan- Meier and Cox analyses were performed to identify the role of CHIP in the prognosis of NSCLC patients. ELISA test was used to detect the VEGF secretion of NSCLC cells and western blot were used to detected the protein expression of VEGFR2 in NSCLC cells. and the results revealed that CHIP expression was decreased in NSCLC tissues and significantly correlated with clinical stages, lymph node metastasis and distant metastasis (P<0.05). Moreover, Kaplan-Meier and Cox regression analyses showed that patients with negative expression of CHIP had a shorter survival time and CHIP could be an independent prognostic biomarker. In addition, ELISA tests showed that CHIP negatively regulated the secretion level of VEGF. Furthermore, western blot assay indicated that the VEGFR2 protein level was reduced after CHIP over-expression. Taken together, our findings demonstrate for the first time that CHIP may serve as a promising prognostic biomarker for NSCLC patients and it may be involved in NSCLC angiogenesis through regulating VEGF secretion and expression of VEGFR2. Copyright © 2016. Published by Elsevier Masson SAS.

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s.

PubMed

Kim, Gyungock; Park, Jeong Woo; Kim, In Gyoo; Kim, Sanghoon; Kim, Sanggi; Lee, Jong Moo; Park, Gun Sik; Joo, Jiho; Jang, Ki-Seok; Oh, Jin Hyuk; Kim, Sun Ae; Kim, Jong Hoon; Lee, Jun Young; Park, Jong Moon; Kim, Do-Won; Jeong, Deog-Kyoon; Hwang, Moon-Sang; Kim, Jeong-Kyoum; Park, Kyu-Sang; Chi, Han-Kyu; Kim, Hyun-Chang; Kim, Dong-Wook; Cho, Mu Hee

2011-12-19

We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

Genome-wide Target Enrichment-aided Chip Design: a 66 K SNP Chip for Cashmere Goat.

PubMed

Qiao, Xian; Su, Rui; Wang, Yang; Wang, Ruijun; Yang, Ting; Li, Xiaokai; Chen, Wei; He, Shiyang; Jiang, Yu; Xu, Qiwu; Wan, Wenting; Zhang, Yaolei; Zhang, Wenguang; Chen, Jiang; Liu, Bin; Liu, Xin; Fan, Yixing; Chen, Duoyuan; Jiang, Huaizhi; Fang, Dongming; Liu, Zhihong; Wang, Xiaowen; Zhang, Yanjun; Mao, Danqing; Wang, Zhiying; Di, Ran; Zhao, Qianjun; Zhong, Tao; Yang, Huanming; Wang, Jian; Wang, Wen; Dong, Yang; Chen, Xiaoli; Xu, Xun; Li, Jinquan

2017-08-17

Compared with the commercially available single nucleotide polymorphism (SNP) chip based on the Bead Chip technology, the solution hybrid selection (SHS)-based target enrichment SNP chip is not only design-flexible, but also cost-effective for genotype sequencing. In this study, we propose to design an animal SNP chip using the SHS-based target enrichment strategy for the first time. As an update to the international collaboration on goat research, a 66 K SNP chip for cashmere goat was created from the whole-genome sequencing data of 73 individuals. Verification of this 66 K SNP chip with the whole-genome sequencing data of 436 cashmere goats showed that the SNP call rates was between 95.3% and 99.8%. The average sequencing depth for target SNPs were 40X. The capture regions were shown to be 200 bp that flank target SNPs. This chip was further tested in a genome-wide association analysis of cashmere fineness (fiber diameter). Several top hit loci were found marginally associated with signaling pathways involved in hair growth. These results demonstrate that the 66 K SNP chip is a useful tool in the genomic analyses of cashmere goats. The successful chip design shows that the SHS-based target enrichment strategy could be applied to SNP chip design in other species.

Single chip camera active pixel sensor

NASA Technical Reports Server (NTRS)

Shaw, Timothy (Inventor); Pain, Bedabrata (Inventor); Olson, Brita (Inventor); Nixon, Robert H. (Inventor); Fossum, Eric R. (Inventor); Panicacci, Roger A. (Inventor); Mansoorian, Barmak (Inventor)

2003-01-01

A totally digital single chip camera includes communications to operate most of its structure in serial communication mode. The digital single chip camera include a D/A converter for converting an input digital word into an analog reference signal. The chip includes all of the necessary circuitry for operating the chip using a single pin.

Phosphorylation of CHIP at Ser20 by Cdk5 promotes tAIF-mediated neuronal death

PubMed Central

Kim, C; Yun, N; Lee, J; Youdim, M B H; Ju, C; Kim, W-K; Han, P-L; Oh, Y J

2016-01-01

Cyclin-dependent kinase 5 (Cdk5) is a proline-directed serine/threonine kinase and its dysregulation is implicated in neurodegenerative diseases. Likewise, C-terminus of Hsc70-interacting protein (CHIP) is linked to neurological disorders, serving as an E3 ubiquitin ligase for targeting damaged or toxic proteins for proteasomal degradation. Here, we demonstrate that CHIP is a novel substrate for Cdk5. Cdk5 phosphorylates CHIP at Ser20 via direct binding to a highly charged domain of CHIP. Co-immunoprecipitation and ubiquitination assays reveal that Cdk5-mediated phosphorylation disrupts the interaction between CHIP and truncated apoptosis-inducing factor (tAIF) without affecting CHIP's E3 ligase activity, resulting in the inhibition of CHIP-mediated degradation of tAIF. Lentiviral transduction assay shows that knockdown of Cdk5 or overexpression of CHIPS20A, but not CHIPWT, attenuates tAIF-mediated neuronal cell death induced by hydrogen peroxide. Thus, we conclude that Cdk5-mediated phosphorylation of CHIP negatively regulates its neuroprotective function, thereby contributing to neuronal cell death progression following neurotoxic stimuli. PMID:26206088

Fabrication and characterization of SPR chips with the modified bovine serum albumin

NASA Astrophysics Data System (ADS)

Chen, Xing; Zhang, Lu-lu; Cui, Da-fu

2016-03-01

A facile surface plasmon resonance (SPR) chip is developed for small molecule determination and analysis. The SPR chip was prepared based on a self assembling principle, in which the modified bovine serum albumin (BSA) was directly self-assembled onto the bare gold surface. The surface morphology of the chip with the modified BSA was investigated by atomic force microscopy (AFM) and its optical properties were characterized. The surface binding capacity of the bare facile SPR chip with a uniform morphology is 8 times of that of the bare control SPR chip. Based on the experiments of immune reaction between cortisol antibody and cortisol derivative, the sensitivity of the facile SPR chip with the modified BSA is much higher than that of the control SPR chip with the un-modified BSA. The facile SPR chip has been successfully used to detect small molecules. The lowest detection limit is 5 ng/mL with a linear range of 5—100 ng/mL for cortisol analysis. The novel facile SPR chip can also be applied to detect other small molecules.

Microfluidic valve array control system integrating a fluid demultiplexer circuit

NASA Astrophysics Data System (ADS)

Kawai, Kentaro; Arima, Kenta; Morita, Mizuho; Shoji, Shuichi

2015-06-01

This paper proposes an efficient control method for the large-scale integration of microvalves in microfluidic systems. The proposed method can control 2n individual microvalves with 2n + 2 control lines (where n is an integer). The on-chip valves are closed by applying pressure to a control line, similar to conventional pneumatic microvalves. Another control line closes gate valves between the control line to the on-chip valves and the on-chip valves themselves, to preserve the state of the on-chip valves. The remaining control lines select an activated gate valve. While the addressed gate valve is selected by the other control lines, the corresponding on-chip valve is actuated by applying input pressure to the control line to the on-chip valves. Using this method would substantially reduce the number of world-to-chip connectors and off-chip valve controllers. Experiments conducted using a fabricated 28 microvalve array device, comprising 256 individual on-chip valves controlled with 18 (2   ×   8 + 2) control lines, yielded switching speeds for the selected on-chip valve under 90 ms.

Development of low fat potato chips through microwave processing.

PubMed

Joshi, A; Rudra, S G; Sagar, V R; Raigond, P; Dutt, S; Singh, B; Singh, B P

2016-08-01

Since snacks high in fats are known to be a significant source of fat and energy intake, these have been put in high dietary restraint category. Therefore, an attempt was made to process potato chips through microwave processing without incorporation of any oil in potato chips. Microwave processing of potato chips was done using microwave power varying from 180 to 600 W using constant sample size. Among eleven different drying models, Parabolic model was found to be the best fit through non-linear regression analysis to illustrate drying kinetics of potato chips. The structural, textural and colour attributes of microwaved potato chips were similar to commercial fried potato chips. It was found that at 600 W after 2.5-3.0 min of processing, potato chips gained the fracturability and crispiness index as that of commercial fried chips. Microwave processing was found suitable for processing of potato chips with low fat content (~3.09 vs 35.5 % in commercial preparation) and with acceptable sensory scores (≥7.6 on 9.0 point on hedonic scale vs 8.0 of control preparation).

Advances in SELEX ES infrared detectors for space and astronomy

NASA Astrophysics Data System (ADS)

Knowles, P.; Hipwood, L.; Baker, I.; Weller, H.

2017-11-01

Selex ES produces a wide range of infrared detectors from mercury cadmium telluride (MCT) and triglycine sulfate (TGS), and has supplied both materials into space programmes spanning a period of over 40 years. Current development activities that underpin potential future space missions include large format arrays for near- and short-wave infrared (NIR and SWIR) incorporating radiation-hard designs and suppression of glow. Improved heterostructures are aimed at the reduction of dark currents and avalanche photodiodes (APDs), and parallel studies have been undertaken for low-stress MCT array mounts. Much of this development work has been supported by ESA, UK Space, and ESO, and some has been performed in collaboration with the UK Astronomy Technology Centre and E2V. This paper focuses on MCT heterostructure developments and novel design elements in silicon read-out chips (ROICs). The 2048 x 2048 element, 17um pitch ROIC for ESA's SWIR array development forms the basis for the largest cooled infrared detector manufactured in Europe. Selex ES MCT is grown by metal organic vapour phase epitaxy (MOVPE), currently on 75mm diameter GaAs substrates. The MCT die size of the SWIR array is 35mm square and only a single array can be printed on the 75mm diameter wafer, utilising only 28% of the wafer area. The situation for 100mm substrates is little better, allowing only 2 arrays and 31% utilisation. However, low cost GaAs substrates are readily available in 150mm diameter and the MCT growth is scalable to this size, offering the real possibility of 6 arrays per wafer with 42% utilisation. A similar 2k x 2k ROIC is the goal of ESA's NIR programme, which is currently in phase 2 with a 1k x 1k demonstrator, and a smaller 320 x 256 ROIC (SAPHIRA) has been designed for ESO for the adaptive optics application in the VLT Gravity instrument. All 3 chips have low noise source-follower architecture and are enabled for MCT APD arrays, which have been demonstrated by ESO to be capable of single photon detection. The possibility therefore exists in the near future of demonstrating a photon counting, 2k x 2k SWIR MCT detector manufactured on an affordable wafer scale of 6 arrays per wafer.

Design and qualification of the SEU/TD Radiation Monitor chip

NASA Technical Reports Server (NTRS)

Buehler, Martin G.; Blaes, Brent R.; Soli, George A.; Zamani, Nasser; Hicks, Kenneth A.

1992-01-01

This report describes the design, fabrication, and testing of the Single-Event Upset/Total Dose (SEU/TD) Radiation Monitor chip. The Radiation Monitor is scheduled to fly on the Mid-Course Space Experiment Satellite (MSX). The Radiation Monitor chip consists of a custom-designed 4-bit SRAM for heavy ion detection and three MOSFET's for monitoring total dose. In addition the Radiation Monitor chip was tested along with three diagnostic chips: the processor monitor and the reliability and fault chips. These chips revealed the quality of the CMOS fabrication process. The SEU/TD Radiation Monitor chip had an initial functional yield of 94.6 percent. Forty-three (43) SEU SRAM's and 14 Total Dose MOSFET's passed the hermeticity and final electrical tests and were delivered to LL.

Steaming Chips Facilitates Bark Removal

Treesearch

John R. Erickson

1976-01-01

Whole tree chipping is a productive and economical harvesting system. The resultant product, however, is barky chips. THis paper outlines a promising method for removing the bark particles from whole tree chips.

Lithographic chip identification: meeting the failure analysis challenge

NASA Astrophysics Data System (ADS)

Perkins, Lynn; Riddell, Kevin G.; Flack, Warren W.

1992-06-01

This paper describes a novel method using stepper photolithography to uniquely identify individual chips for permanent traceability. A commercially available 1X stepper is used to mark chips with an identifier or `serial number' which can be encoded with relevant information for the integrated circuit manufacturer. The permanent identification of individual chips can improve current methods of quality control, failure analysis, and inventory control. The need for this technology is escalating as manufacturers seek to provide six sigma quality control for their products and trace fabrication problems to their source. This need is especially acute for parts that fail after packaging and are returned to the manufacturer for analysis. Using this novel approach, failure analysis data can be tied back to a particular batch, wafer, or even a position within a wafer. Process control can be enhanced by identifying the root cause of chip failures. Chip identification also addresses manufacturers concerns with increasing incidences of chip theft. Since chips currently carry no identification other than the manufacturer's name and part number, recovery efforts are hampered by the inability to determine the sales history of a specific packaged chip. A definitive identifier or serial number for each chip would address this concern. The results of chip identification (patent pending) are easily viewed through a low power microscope. Batch number, wafer number, exposure step, and chip location within the exposure step can be recorded, as can dates and other items of interest. An explanation of the chip identification procedure and processing requirements are described. Experimental testing and results are presented, and potential applications are discussed.

An economic evaluation of a chlorhexidine chip for treating chronic periodontitis: the CHIP (chlorhexidine in periodontitis) study.

PubMed

Henke, C J; Villa, K F; Aichelmann-Reidy, M E; Armitage, G C; Eber, R M; Genco, R J; Killoy, W J; Miller, D P; Page, R C; Polson, A M; Ryder, M I; Silva, S J; Somerman, M J; Van Dyke, T E; Wolff, L F; Evans, C J; Finkelman, R D

2001-11-01

The authors previously suggested that an adjunctive, controlled-release chlorhexidine, or CHX, chip may reduce periodontal surgical needs at little additional cost. This article presents an economic analysis of the CHX chip in general dental practice. In a one-year prospective clinical trial, 484 chronic periodontitis patients in 52 general practices across the United States were treated with either scaling and root planing, or SRP, plus any therapy prescribed by treating, unblinded dentists; or SRP plus other therapy as above but including the CHX chip. Economic data were collected from bills, case report forms and 12-month treatment recommendations from blinded periodontist evaluators. Total dental charges were higher for SRP + CHX chip patients vs. SRP patients when CHX chip costs were included (P = .027) but lower when CHX chip costs were excluded (P = .012). About one-half of the CHX chip acquisition cost was offset by savings in other charges. SRP + CHX chip patients were about 50 percent less likely to undergo surgical procedures than were SRP patients (P = .021). At the end of the trial, periodontist evaluators recommended similar additional procedures for both groups: SRP, about 46 percent; maintenance, about 37 percent; surgery, 56 percent for SRP alone and 63 percent for SRP + CHX chip. Adjunctive CHX chip use for general-practice patients with periodontitis increased costs but reduced surgeries over one year. At study's end, periodontists recommended similar additional surgical treatment for both groups. In general practice, routine use of the CHX chip suggests that costs will be partially offset by reduced surgery over at least one year.

The Antitumor Effect of C-terminus of Hsp70-Interacting Protein via Degradation of c-Met in Small Cell Lung Cancer.

PubMed

Cho, Sung Ho; Kim, Jong In; Kim, Hyun Su; Park, Sung Dal; Jang, Kang Won

2017-06-01

The mesenchymal-epithelial transition factor (MET) receptor can be overexpressed in solid tumors, including small cell lung cancer (SCLC). However, the molecular mechanism regulating MET stability and turnover in SCLC remains undefined. One potential mechanism of MET regulation involves the C-terminus of Hsp70-interacting protein (CHIP), which targets heat shock protein 90-interacting proteins for ubiquitination and proteasomal degradation. In the present study, we investigated the functional effects of CHIP expression on MET regulation and the control of SCLC cell apoptosis and invasion. To evaluate the expression of CHIP and c-Met, which is a protein that in humans is encoded by the MET gene (the MET proto-oncogene), we examined the expression pattern of c-Met and CHIP in SCLC cell lines by western blotting. To investigate whether CHIP overexpression reduced cell proliferation and invasive activity in SCLC cell lines, we transfected cells with CHIP and performed a cell viability assay and cellular apoptosis assays. We found an inverse relationship between the expression of CHIP and MET in SCLC cell lines (n=5). CHIP destabilized the endogenous MET receptor in SCLC cell lines, indicating an essential role for CHIP in the regulation of MET degradation. In addition, CHIP inhibited MET-dependent pathways, and invasion, cell growth, and apoptosis were reduced by CHIP overexpression in SCLC cell lines. CHIP is capable of regulating SCLC cell apoptosis and invasion by inhibiting MET-mediated cytoskeletal and cell survival pathways in NCI-H69 cells. CHIP suppresses MET-dependent signaling, and regulates MET-mediated SCLC motility.

CHIP: A new modulator of human malignant disorders

PubMed Central

Shao, Qianqian; Yang, Gang; Zheng, Lianfang; Zhang, Taiping; Zhao, Yupei

2016-01-01

Carboxyl terminus of Hsc70-interacting protein (CHIP) is known as a chaperone-associated E3 for a variety of protein substrates. It acts as a link between molecular chaperones and ubiquitin–proteasome system. Involved in the process of protein clearance, CHIP plays a critical role in maintaining protein homeostasis in diverse conditions. Here, we provide a comprehensive review of our current understanding of CHIP and summarize recent advances in CHIP biology, with a focus on CHIP in the setting of malignancies. PMID:27007160

CHIP regulates bone mass by targeting multiple TRAF family members in bone marrow stromal cells.

PubMed

Wang, Tingyu; Li, Shan; Yi, Dan; Zhou, Guang-Qian; Chang, Zhijie; Ma, Peter X; Xiao, Guozhi; Chen, Di

2018-01-01

Carboxyl terminus of Hsp70-interacting protein (CHIP or STUB1) is an E3 ligase and regulates the stability of several proteins which are involved in different cellular functions. Our previous studies demonstrated that Chip deficient mice display bone loss phenotype due to increased osteoclast formation through enhancing TRAF6 activity in osteoclasts. In this study we provide novel evidence about the function of CHIP. We found that osteoblast differentiation and bone formation were also decreased in Chip KO mice. In bone marrow stromal (BMS) cells derived from Chip -/- mice, expression of a panel of osteoblast marker genes was significantly decreased. ALP activity and mineralized bone matrix formation were also reduced in Chip- deficient BMS cells. We also found that in addition to the regulation of TRAF6, CHIP also inhibits TNFα-induced NF-κB signaling through promoting TRAF2 and TRAF5 degradation. Specific deletion of Chip in BMS cells downregulated expression of osteoblast marker genes which could be reversed by the addition of NF-κB inhibitor. These results demonstrate that the osteopenic phenotype observed in Chip -/- mice was due to the combination of increased osteoclast formation and decreased osteoblast differentiation. Taken together, our findings indicate a significant role of CHIP in bone remodeling.

Silicon ball grid array chip carrier

DOEpatents

Palmer, David W.; Gassman, Richard A.; Chu, Dahwey

2000-01-01

A ball-grid-array integrated circuit (IC) chip carrier formed from a silicon substrate is disclosed. The silicon ball-grid-array chip carrier is of particular use with ICs having peripheral bond pads which can be reconfigured to a ball-grid-array. The use of a semiconductor substrate such as silicon for forming the ball-grid-array chip carrier allows the chip carrier to be fabricated on an IC process line with, at least in part, standard IC processes. Additionally, the silicon chip carrier can include components such as transistors, resistors, capacitors, inductors and sensors to form a "smart" chip carrier which can provide added functionality and testability to one or more ICs mounted on the chip carrier. Types of functionality that can be provided on the "smart" chip carrier include boundary-scan cells, built-in test structures, signal conditioning circuitry, power conditioning circuitry, and a reconfiguration capability. The "smart" chip carrier can also be used to form specialized or application-specific ICs (ASICs) from conventional ICs. Types of sensors that can be included on the silicon ball-grid-array chip carrier include temperature sensors, pressure sensors, stress sensors, inertia or acceleration sensors, and/or chemical sensors. These sensors can be fabricated by IC processes and can include microelectromechanical (MEM) devices.

Mobile Phone Chips Reduce Increases in EEG Brain Activity Induced by Mobile Phone-Emitted Electromagnetic Fields.

PubMed

Henz, Diana; Schöllhorn, Wolfgang I; Poeggeler, Burkhard

2018-01-01

Recent neurophysiological studies indicate that exposure to electromagnetic fields (EMFs) generated by mobile phone radiation can exert effects on brain activity. One technical solution to reduce effects of EMFs in mobile phone use is provided in mobile phone chips that are applied to mobile phones or attached to their surfaces. To date, there are no systematical studies on the effects of mobile phone chip application on brain activity and the underlying neural mechanisms. The present study investigated whether mobile phone chips that are applied to mobile phones reduce effects of EMFs emitted by mobile phone radiation on electroencephalographic (EEG) brain activity in a laboratory study. Thirty participants volunteered in the present study. Experimental conditions (mobile phone chip, placebo chip, no chip) were set up in a randomized within-subjects design. Spontaneous EEG was recorded before and after mobile phone exposure for two 2-min sequences at resting conditions. During mobile phone exposure, spontaneous EEG was recorded for 30 min during resting conditions, and 5 min during performance of an attention test (d2-R). Results showed increased activity in the theta, alpha, beta and gamma bands during EMF exposure in the placebo and no chip conditions. Application of the mobile phone chip reduced effects of EMFs on EEG brain activity and attentional performance significantly. Attentional performance level was maintained regarding number of edited characters. Further, a dipole analysis revealed different underlying activation patterns in the chip condition compared to the placebo chip and no chip conditions. Finally, a correlational analysis for the EEG frequency bands and electromagnetic high-frequency (HF) emission showed significant correlations in the placebo chip and no chip condition for the theta, alpha, beta, and gamma bands. In the chip condition, a significant correlation of HF with the theta and alpha bands, but not with the beta and gamma bands was shown. We hypothesize that a reduction of EEG beta and gamma activation constitutes the key neural mechanism in mobile phone chip use that supports the brain to a degree in maintaining its natural activity and performance level during mobile phone use.

Mobile Phone Chips Reduce Increases in EEG Brain Activity Induced by Mobile Phone-Emitted Electromagnetic Fields

PubMed Central

Henz, Diana; Schöllhorn, Wolfgang I.; Poeggeler, Burkhard

2018-01-01

Recent neurophysiological studies indicate that exposure to electromagnetic fields (EMFs) generated by mobile phone radiation can exert effects on brain activity. One technical solution to reduce effects of EMFs in mobile phone use is provided in mobile phone chips that are applied to mobile phones or attached to their surfaces. To date, there are no systematical studies on the effects of mobile phone chip application on brain activity and the underlying neural mechanisms. The present study investigated whether mobile phone chips that are applied to mobile phones reduce effects of EMFs emitted by mobile phone radiation on electroencephalographic (EEG) brain activity in a laboratory study. Thirty participants volunteered in the present study. Experimental conditions (mobile phone chip, placebo chip, no chip) were set up in a randomized within-subjects design. Spontaneous EEG was recorded before and after mobile phone exposure for two 2-min sequences at resting conditions. During mobile phone exposure, spontaneous EEG was recorded for 30 min during resting conditions, and 5 min during performance of an attention test (d2-R). Results showed increased activity in the theta, alpha, beta and gamma bands during EMF exposure in the placebo and no chip conditions. Application of the mobile phone chip reduced effects of EMFs on EEG brain activity and attentional performance significantly. Attentional performance level was maintained regarding number of edited characters. Further, a dipole analysis revealed different underlying activation patterns in the chip condition compared to the placebo chip and no chip conditions. Finally, a correlational analysis for the EEG frequency bands and electromagnetic high-frequency (HF) emission showed significant correlations in the placebo chip and no chip condition for the theta, alpha, beta, and gamma bands. In the chip condition, a significant correlation of HF with the theta and alpha bands, but not with the beta and gamma bands was shown. We hypothesize that a reduction of EEG beta and gamma activation constitutes the key neural mechanism in mobile phone chip use that supports the brain to a degree in maintaining its natural activity and performance level during mobile phone use. PMID:29670503

Effects of Verticillium dahliae infection on stem-end chip defect development in potatoes (Solanum tuberosum L.)

USDA-ARS?s Scientific Manuscript database

Potato chips are America's favorite snack food with annual retail sales of over $6 billion. Stem-end chip defect, which is characterized by discoloration of the vasculature and surrounding tissues at the tuber stem end portion of chips, is an important tuber quality concern for US chip production. T...

Method for protecting chip corners in wet chemical etching of wafers

DOEpatents

Hui, Wing C.

1994-01-01

The present invention is a corner protection mask design that protects chip corners from undercutting during anisotropic etching of wafers. The corner protection masks abut the chip corner point and extend laterally from segments along one or both corner sides of the corner point, forming lateral extensions. The protection mask then extends from the lateral extensions, parallel to the direction of the corner side of the chip and parallel to scribe lines, thus conserving wafer space. Unmasked bomb regions strategically formed in the protection mask facilitate the break-up of the protection mask during etching. Corner protection masks are useful for chip patterns with deep grooves and either large or small chip mask areas. Auxiliary protection masks form nested concentric frames that etch from the center outward are useful for small chip mask patterns. The protection masks also form self-aligning chip mask areas. The present invention is advantageous for etching wafers with thin film windows, microfine and micromechanical structures, and for forming chip structures more elaborate than presently possible.

Method for protecting chip corners in wet chemical etching of wafers

DOEpatents

Hui, W.C.

1994-02-15

The present invention is a corner protection mask design that protects chip corners from undercutting during anisotropic etching of wafers. The corner protection masks abut the chip corner point and extend laterally from segments along one or both corner sides of the corner point, forming lateral extensions. The protection mask then extends from the lateral extensions, parallel to the direction of the corner side of the chip and parallel to scribe lines, thus conserving wafer space. Unmasked bomb regions strategically formed in the protection mask facilitate the break-up of the protection mask during etching. Corner protection masks are useful for chip patterns with deep grooves and either large or small chip mask areas. Auxiliary protection masks form nested concentric frames that etch from the center outward are useful for small chip mask patterns. The protection masks also form self-aligning chip mask areas. The present invention is advantageous for etching wafers with thin film windows, microfine and micromechanical structures, and for forming chip structures more elaborate than presently possible. 63 figures.

CHIP is a novel tumor suppressor in pancreatic cancer and inhibits tumor growth through targeting EGFR

PubMed Central

Wang, Tianxiao; Yang, Jingxuan; Xu, Jianwei; Li, Jian; Cao, Zhe; Zhou, Li; You, Lei; Shu, Hong; Lu, Zhaohui; Li, Huihua; Li, Min; Zhang, Taiping; Zhao, Yupei

2014-01-01

Carboxyl terminus of heat shock protein 70-interacting protein (CHIP) is an E3 ubiquitin ligase that is involved in protein quality control and mediates several tumor-related proteins in many cancers, but the function of CHIP in pancreatic cancer is not known. Here we show that CHIP interacts and ubiquitinates epidermal growth factor receptor (EGFR) for proteasome-mediated degradation in pancreatic cancer cells, thereby inhibiting the activation of EGFR downstream pathways. CHIP suppressed cell proliferation, anchor-independent growth, invasion and migration, as well as enhanced apoptosis induced by erlotinib in vitro and in vivo. The expression of CHIP was decreased in pancreatic cancer tissues or sera. Low CHIP expression in tumor tissues was correlated with tumor differentiation and shorter overall survival. These observations indicate that CHIP serves as a novel tumor suppressor by down-regulating EGFR pathway in pancreatic cancer cells, decreased expression of CHIP was associated with poor prognosis in pancreatic cancer. PMID:24722501

Unraveling the CHIP:Hsp70 complex as an information processor for protein quality control.

PubMed

VanPelt, Jamie; Page, Richard C

2017-02-01

The CHIP:Hsp70 complex stands at the crossroads of the cellular protein quality control system. Hsp70 facilitates active refolding of misfolded client proteins, while CHIP directs ubiquitination of misfolded client proteins bound to Hsp70. The direct competition between CHIP and Hsp70 for the fate of misfolded proteins leads to the question: how does the CHIP:Hsp70 complex execute triage decisions that direct misfolded proteins for either refolding or degradation? The current body of literature points toward action of the CHIP:Hsp70 complex as an information processor that takes inputs in the form of client folding state, dynamics, and posttranslational modifications, then outputs either refolded or ubiquitinated client proteins. Herein we examine the CHIP:Hsp70 complex beginning with the structure and function of CHIP and Hsp70, followed by an examination of recent studies of the interactions and dynamics of the CHIP:Hsp70 complex. Copyright © 2016 Elsevier B.V. All rights reserved.

Microchannel cooling of face down bonded chips

DOEpatents

Bernhardt, A.F.

1993-06-08

Microchannel cooling is applied to flip-chip bonded integrated circuits, in a manner which maintains the advantages of flip-chip bonds, while overcoming the difficulties encountered in cooling the chips. The technique is suited to either multi chip integrated circuit boards in a plane, or to stacks of circuit boards in a three dimensional interconnect structure. Integrated circuit chips are mounted on a circuit board using flip-chip or control collapse bonds. A microchannel structure is essentially permanently coupled with the back of the chip. A coolant delivery manifold delivers coolant to the microchannel structure, and a seal consisting of a compressible elastomer is provided between the coolant delivery manifold and the microchannel structure. The integrated circuit chip and microchannel structure are connected together to form a replaceable integrated circuit module which can be easily decoupled from the coolant delivery manifold and the circuit board. The coolant supply manifolds may be disposed between the circuit boards in a stack and coupled to supplies of coolant through a side of the stack.

Lab-on-a-Chip Instrumentation and Method for Detecting Trace Organic and Bioorganic Molecules in Planetary Exploration: The Enceladus Organic Analyzer (EOA)

NASA Astrophysics Data System (ADS)

Butterworth, A.; Stockton, A. M.; Turin, P.; Ludlam, M.; Diaz-Aguado, M.; Kim, J.; Mathies, R. A.

2015-12-01

Lab-on-a-chip instrumentation is providing an ever more powerful in situ approach for detecting organic molecules relevant for chemical/biochemical evolution in our solar system obviating the cost, risk and long mission duration associated with sample return. Microfabricated analysis systems are particularly feasible when directly sampling from comet comae, or ejecta from icy moons, such as targeting organic molecules in plumes from Enceladus. Furthermore, the superb ppm to ppb sensitivity of chip analyzers, like the Enceladus Organic Analyzer (EOA), coupled with the ability to examine organics with a wide variety of functional groups enhance the probability of detecting organic molecules and determining whether they have a biological origin. The EOA is based on 20 years of research and development of microfabricated capillary electrophoresis (CE) analyzers at Berkeley that provide ppb sensitivity for a wide variety of organic molecules including amino acids, carboxylic acids, amines, aldehydes, ketones and polycyclic aromatic hydrocarbons [1]. Organic molecules are labeled with a fluorescent reagent according to their functional group in a programmable microfluidic processor [2,3] and then separated in a CE system followed by laser-induced fluorescence detection to determine molecular size and concentration. The EOA will be flown through Enceladus plumes and uses a specially designed impact plate/door to capture ice-particles. After closing the door, the material in the capture chamber is dissolved, labeled and analyzed by the microfabricated CE system. Only a few thousand 2 μm diameter particles containing ppm organic concentrations will provide an EOA detectable signal. If amino acids are detected, their chirality is determined because chirality is the best indicator of a biologically produced molecule. We have developed a flight design of this instrument for planetary exploration that is compact (16x16x12 cm), has low mass (3 kg), and requires very low power. [1] Skelley et al. (2005) PNAS USA, 102, 1041-1046. [2] Kim et al. (2013) Anal. Chem., 85, 7682-7688. [3] Mora et al. (2012) Electrophoresis, 33, 2624-2638. [4] Stockton et al. (2014) Second International Workshop on Instrumentation for Planetary Missions, NASA Greenbelt MD, Nov. 4-7, 2014.

An Analysis of the Effects of Chip-groove Geometry on Machining Performance Using Finite Element Methods

NASA Astrophysics Data System (ADS)

Ee, K. C.; Dillon, O. W.; Jawahir, I. S.

2004-06-01

This paper discusses the influence of major chip-groove parameters of a cutting tool on the chip formation process in orthogonal machining using finite element (FE) methods. In the FE formulation, a thermal elastic-viscoplastic material model is used together with a modified Johnson-Cook material law for the flow stress. The chip back-flow angle and the chip up-curl radius are calculated for a range of cutting conditions by varying the chip-groove parameters. The analysis provides greater understanding of the effectiveness of chip-groove configurations and points a way to correlate cutting conditions with tool-wear when machining with a grooved cutting tool.

46 CFR 148.325 - Wood chips; wood pellets; wood pulp pellets.

Code of Federal Regulations, 2014 CFR

2014-10-01

... 46 Shipping 5 2014-10-01 2014-10-01 false Wood chips; wood pellets; wood pulp pellets. 148.325... § 148.325 Wood chips; wood pellets; wood pulp pellets. (a) This part applies to wood chips and wood pulp... cargo hold. (b) No person may enter a cargo hold containing wood chips, wood pellets, or wood pulp...

46 CFR 148.325 - Wood chips; wood pellets; wood pulp pellets.

Code of Federal Regulations, 2012 CFR

2012-10-01

... 46 Shipping 5 2012-10-01 2012-10-01 false Wood chips; wood pellets; wood pulp pellets. 148.325... § 148.325 Wood chips; wood pellets; wood pulp pellets. (a) This part applies to wood chips and wood pulp... cargo hold. (b) No person may enter a cargo hold containing wood chips, wood pellets, or wood pulp...

46 CFR 148.325 - Wood chips; wood pellets; wood pulp pellets.

Code of Federal Regulations, 2013 CFR

2013-10-01

... 46 Shipping 5 2013-10-01 2013-10-01 false Wood chips; wood pellets; wood pulp pellets. 148.325... § 148.325 Wood chips; wood pellets; wood pulp pellets. (a) This part applies to wood chips and wood pulp... cargo hold. (b) No person may enter a cargo hold containing wood chips, wood pellets, or wood pulp...

Determining the Terminal Velocity of Wood and Bark Chips

Treesearch

John A. Sturos

1972-01-01

Designing an efficient air flotation segregator to segregate bark chips from wood chips requires that the terminal velocities be determined for various pulpwood species. The technique described here uses forced air in a vertical wind tunnel with the chip initially at rest on a stationary screen; when the terminal air velocity in reached, the chip begins to float. A...

Should whole-tree chips for fuel be dried before storage?

Treesearch

E. L. Springer

1979-01-01

Whole-tree chips deteriorate more rapidly than do clean, debarked chips and present a greater hazard for spontaneous ignition when stored in outdoor piles. To prevent ignition, the chips can be stored for only short periods of time and the frequent rotation of the storage piles results in high handling costs. Drying the chips prior to storage will prevent deterioration...

46 CFR 148.325 - Wood chips; wood pellets; wood pulp pellets.

Code of Federal Regulations, 2011 CFR

2011-10-01

... 46 Shipping 5 2011-10-01 2011-10-01 false Wood chips; wood pellets; wood pulp pellets. 148.325... § 148.325 Wood chips; wood pellets; wood pulp pellets. (a) This part applies to wood chips and wood pulp... cargo hold. (b) No person may enter a cargo hold containing wood chips, wood pellets, or wood pulp...

Immunolocalization of aquaporin CHIP in the guinea pig inner ear.

PubMed

Stanković, K M; Adams, J C; Brown, D

1995-12-01

Aquaporin CHIP (AQP-CHIP) is a water channel protein previously identified in red blood cells and water transporting epithelia. The inner ear is an organ of hearing and balance whose normal function depends critically on maintenance of fluid homeostasis. In this study, AQP-CHIP, or a close homologue, was found in specific cells of the inner ear, as assessed by immunocytochemistry with the use of affinity-purified polyclonal antibodies against AQP-CHIP.AQP-CHIP was predominantly found in fibrocytes in close association with bone, including most of the cells lining the bony labyrinth and in fibrocytes lining the endolymphatic duct and sac. AQP-CHIP-positive cells not directly apposing bone include cells under the basilar membrane, some type III fibrocytes of the spiral ligament, fibrocytes of the spiral limbus, and the trabecular perilymphatic tissue extending from the membranous to the bony labyrinth. AQP-CHIP was also found in the periosteum of the middle ear and cranial bones, as well as in chondrocytes of the oval window and stapes. The distribution of AQP-CHIP in the inner ear suggests that AQP-CHIP may have special significance for maintenance of bone and the basilar membrane, and for function of the spiral ligament.

Carboxyl Terminus of HSC70-interacting Protein (CHIP) Down-regulates NF-κB-inducing Kinase (NIK) and Suppresses NIK-induced Liver Injury*

PubMed Central

Jiang, Bijie; Shen, Hong; Chen, Zheng; Yin, Lei; Zan, Linsen; Rui, Liangyou

2015-01-01

Ser/Thr kinase NIK (NF-κB-inducing kinase) mediates the activation of the noncanonical NF-κB2 pathway, and it plays an important role in regulating immune cell development and liver homeostasis. NIK levels are extremely low in quiescent cells due to ubiquitin/proteasome-mediated degradation, and cytokines stimulate NIK activation through increasing NIK stability; however, regulation of NIK stability is not fully understood. Here we identified CHIP (carboxyl terminus of HSC70-interacting protein) as a new negative regulator of NIK. CHIP contains three N-terminal tetratricopeptide repeats (TPRs), a middle dimerization domain, and a C-terminal U-box. The U-box domain contains ubiquitin E3 ligase activity that promotes ubiquitination of CHIP-bound partners. We observed that CHIP bound to NIK via its TPR domain. In both HEK293 and primary hepatocytes, overexpression of CHIP markedly decreased NIK levels at least in part through increasing ubiquitination and degradation of NIK. Accordingly, CHIP suppressed NIK-induced activation of the noncanonical NF-κB2 pathway. CHIP also bound to TRAF3, and CHIP and TRAF3 acted coordinately to efficiently promote NIK degradation. The TPR but not the U-box domain was required for CHIP to promote NIK degradation. In mice, hepatocyte-specific overexpression of NIK resulted in liver inflammation and injury, leading to death, and liver-specific expression of CHIP reversed the detrimental effects of hepatic NIK. Our data suggest that CHIP/TRAF3/NIK interactions recruit NIK to E3 ligase complexes for ubiquitination and degradation, thus maintaining NIK at low levels. Defects in CHIP regulation of NIK may result in aberrant NIK activation in the liver, contributing to live injury, inflammation, and disease. PMID:25792747

WFC3/UVIS External CTE Monitor: Single-Chip CTE Measurements

NASA Astrophysics Data System (ADS)

Gosmeyer, C. M.; Baggett, S.

2016-12-01

We present the first results of single-chip measurements of charge transfer efficiency (CTE) in the UVIS channel of the Hubble Space Telescope Wide Field Camera 3 (HST/WFC3). This test was performed in Cycle 20 in two visits. In the first visit a field in the star cluster NGC 6583 was observed. In a second visit, the telescope returned to the field, but rotated by 180 degrees and with a shift in pointing that allowed the same stars to be imaged, near and far from the amplifiers, on the same chip of the two-chip UVIS field of-view. This dataset enables a measurement of CTE loss on each separate chip. The current CTE monitor measures CTE loss as an average of the two chips because it dithers by a chip-height to obtain observations of the same sources near and far from the amplifiers, instead of the more difficult to-schedule 180-degree rotation. We find that CTE loss is worse on Chip 1 than on Chip 2 across all cases for which we had data: short and long exposures and w! ith and without the pixel-based CTE correction. In the best case, for long exposures with the CTE correction applied, the max difference between the two chip's flux losses is 3%/2048 pixels. This case should apply for most science observations where the background is 12 e-/pixel. In the worst case of low-background short exposures, e.g. those without post-flash, the max difference between the two chips is 17% flux loss/2048 pixels. Uncertainties are <0.01% flux loss/2048 pixels. Because of the two chips' different CTE loss rates, we will consider adding this test as part of the routine yearly monitor and creating a chip-specific CTE correction software.

Bark Separation During Chipping With a Parallel Knife Chipper

Treesearch

John R. Erickson

1968-01-01

Five winter-cut northern species were chipped in a frozen and unfrozen condition with a parallel knife chipper. The degree of bark separation during chipping and a relative gradation of chip size are reported.

Delamination study of chip-to-chip bonding for a LIGA-based safety and arming system

NASA Astrophysics Data System (ADS)

Subramanian, Gowrishankar; Deeds, Michael; Cochran, Kevin R.; Raghavan, Raghu; Sandborn, Peter A.

1999-08-01

The development of a miniature underwater weapon safety and arming system requires reliable chip-to-chip bonding of die that contain microelectromechanical actuators and sensors fabricated using a LIGA MEMS fabrication process. Chip-to- chip bonding is associated for several different bond materials (indium solder, thermoplastic paste, thermoplastic film and epoxy film), and bonding configurations (with an alloy 42 spacer, silicon to ceramic, and silicon to silicon). Metrology using acoustic micro imaging has been developed to determine the fraction of delamination of samples.

High-density, fail-in-place switches for computer and data networks

DOE Office of Scientific and Technical Information (OSTI.GOV)

Coteus, Paul W.; Doany, Fuad E.; Hall, Shawn A.

A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards.

Comparison of edge chipping resistance of PFM and veneered zirconia specimens

PubMed Central

Quinn, Janet B.; Sundar, Veeraraghavan; Parry, Edward E.; Quinn, George D.

2011-01-01

Objectives To investigate the chipping resistance of veneered zirconia specimens and compare it to the chipping resistance of porcelain fused to metal (PFM) specimens. Methods Veneered zirconia and PFM bar specimens were prepared in clinically relevant thicknesses. The specimen edges were chipped with different magnitude forces, producing chips of various sizes. The range of sizes included small chips that did not penetrate all the way through the veneers to the substrates, and also chips that were very large and reached the zirconia or metal substrates. The relationship between force magnitude and chip size (edge distance) was graphed. The resulting curves were compared for the veneered zirconia and PFM specimens. Knoop hardness vs. force graphs for the veneers and substrates were also obtained. Results The zirconia and PFM veneer chipping data followed a power law (coefficient of determination, R2 > 0.93) as expected from the literature. The curves overlapped within the combined data scatter, indicating similar resistance to chipping. The chips made in both types of specimens detached and did not penetrate into the substrate when they reached the veneer/substrate intersections. The hardness–load curves for the veneers and substrates all exhibited an indentation size effect (ISE) at low loads. The Knoop hardness values with uncertainties of ±one standard deviation at 4 N loads for the metal, zirconia, and the metal and zirconia veneers are: (2.02 ± 0.08, 12.01 ± 0.39, 4.24 ± 0.16 and 4.36 ± 0.02 GPa), respectively, with no statistically significant difference between the veneers (Tukey pairwise comparison at 0.95 family confidence). Significance This work indicates that a similar resistance to chipping might be expected for veneered zirconia and PFM restorations, in spite of the large difference in substrate hardness. Differences in susceptibility to chip spalling were not detected, but the chips in both specimen types detached off the sides in a similar manner instead of extending into the substrates. PMID:19748115

E3 ligase CHIP and Hsc70 regulate Kv1.5 protein expression and function in mammalian cells.

PubMed

Li, Peili; Kurata, Yasutaka; Maharani, Nani; Mahati, Endang; Higaki, Katsumi; Hasegawa, Akira; Shirayoshi, Yasuaki; Yoshida, Akio; Kondo, Tatehito; Kurozawa, Youichi; Yamamoto, Kazuhiro; Ninomiya, Haruaki; Hisatome, Ichiro

2015-09-01

Kv1.5 confers ultra-rapid delayed-rectifier potassium channel current (IKur) which contributes to repolarization of the atrial action potential. Kv1.5 proteins, degraded via the ubiquitin-proteasome pathway, decreased in some atrial fibrillation patients. Carboxyl-terminus heat shock cognate 70-interacting protein (CHIP), an E3 ubiquitin ligase, is known to ubiquitinate short-lived proteins. Here, we investigated the roles of CHIP in Kv1.5 degradation to provide insights into the mechanisms of Kv1.5 decreases and treatments targeting Kv1.5 for atrial fibrillation. Coexpression of CHIP with Kv1.5 in HEK293 cells increased Kv1.5 protein ubiquitination and decreased the protein level. Immunofluorescence revealed decreases of Kv1.5 proteins in the endoplasmic reticulum and on the cell membrane. A siRNA against CHIP suppressed Kv1.5 protein ubiquitination and increased its protein level. CHIP mutants, lacking either the N-terminal tetratricopeptide region domain or the C-terminal U-box domain, failed to exert these effects on Kv1.5 proteins. Immunoprecipitation showed that CHIP formed complexes with Kv1.5 proteins and heat shock cognate protein 70 (Hsc70). Effects of Hsc70 on Kv1.5 were similar to CHIP by altering interaction of CHIP with Kv1.5 protein. Coexpression of CHIP and Hsc70 with Kv1.5 additionally enhanced Kv1.5 ubiquitination. Kv1.5 currents were decreased by overexpression of CHIP or Hsc70 but were increased by knockdown of CHIP or Hsc70 in HEK 293 cells stably expressing Kv1.5. These effects of CHIP and Hsc70 were also observed on endogenous Kv1.5 in HL-1 mouse cardiomyocytes, decreasing IKur and prolonging action potential duration. These results indicate that CHIP decreases the Kv1.5 protein level and functional channel by facilitating its degradation in concert with chaperone Hsc70. Copyright © 2015 Elsevier Ltd. All rights reserved.

Stability and Antioxidant Activity of Annatto (Bixa orellana L.) Tocotrienols During Frying and in Fried Tortilla Chips.

PubMed

Winkler-Moser, Jill K; Bakota, Erica L; Hwang, Hong-Sik

2018-02-01

Annatto tocotrienols (AnT3), which contain approximately 90% δ-tocotrienol (δ-T3), were added to mid-oleic sunflower oil used for frying tortilla chips over 3 d. The objectives were to evaluate their stability during frying, absorption by the fried food, and activity as antioxidants in frying oil and in tortilla chips during storage. AnT3 did not significantly affect the stability of the oil during frying or the sensory profiles of freshly fried chips. The naturally present α-tocopherol (α-T) in the oil degraded at a lower rate in the presence of AnT3, resulting in significantly higher α-T by the end of the frying study. Levels of tocopherols and tocotrienols in the chips mirrored oil levels. AnT3 did not affect the sensory profile of the chips after 1 wk of storage at 50 °C, but after 3 wk of storage, the control chips had higher levels of painty and rancid flavors compared to chips with AnT3. Headspace hexanal was also significantly higher in the control chips compared to the chips with AnT3 after 3 wk of storage. Annatto tocotrienols, containing primarily delta- and gamma-tocotrienols, were added to mid-oleic sunflower oil used for frying tortilla chips. The tocotrienols were absorbed by the chips along with the oil. They slowed the degradation of α tocopherol during frying, and reduced levels of painty and rancid flavor scores as well as headspace hexanal in chips that were stored for 3 wk at elevated temperatures. The results indicated that fried snack foods such as tortilla chips may be a suitable and convenient vehicle for enriching tocotrienols in the diet, and that tocotrienols may also enhance the shelf-life of fried foods. © 2018 Institute of Food Technologists®.

Consistent relationships between sensory properties of savory snack foods and calories influence food intake in rats.

PubMed

Swithers, S E; Doerflinger, A; Davidson, T L

2006-11-01

Determine the influence of experience with consistent or inconsistent relationships between the sensory properties of snack foods and their caloric consequences on the control of food intake or body weight in rats. Rats received plain and BBQ flavored potato chips as a dietary supplement, along with ad lib rat chow. For some rats the potato chips were a consistent source of high fat and high calories (regular potato chips). For other rats, the chips provided high fat and high calories on some occasions (regular potato chips) and provided no digestible fat and fewer calories at other times (light potato chips manufactured with a fat substitute). Thus, animals in the first group were given experiences that the sensory properties of potato chips were strong predictors of high calories, while animals in the second group were given experiences that the sensory properties of potato chips were not predictors of high calories. Juvenile and adult male Sprague-Dawley rats. Following exposure to varying potato chip-calorie contingencies, intake of a novel, high-fat snack food and subsequent chow intake were assessed. Body weight gain and body composition as measured by DEXA were also measured. In juvenile animals, exposure to a consistent relationship between potato chips and calories resulted in reduced chow intake, both when no chips were provided and following consumption of a novel high-fat, high-calorie snack chip. Long-term experience with these contingencies did not affect body weight gain or body composition in juveniles. In adult rats, exposure to an inconsistent relationship between potato chips and calories resulted in increased consumption of a novel high-fat, high-calorie snack chip premeal along with impaired compensation for the calories contained in the premeal. Consumption of foods in which the sensory properties are poor predictors of caloric consequences may alter subsequent food intake.

Ubiquitin ligase CHIP functions as an oncogene and activates the AKT signaling pathway in prostate cancer.

PubMed

Cheng, Li; Zang, Jin; Dai, Han-Jue; Li, Feng; Guo, Feng

2018-07-01

Carboxyl terminus of Hsc-70-interacting protein (CHIP) is an E3 ubiquitin ligase that induces the ubiquitination and degradation of numerous tumor-associated proteins and serves as a suppressor or promoter in tumor progression. To date, the molecular mechanism of CHIP in prostate cancer remains unknown. Therefore, the present study investigated the biological function of CHIP in prostate cancer cells and obtained evidence that CHIP expression is upregulated in prostate cancer tissues. The CHIP vector was introduced into DU145 cancer cells and the cell biological behaviour was examined through a series of experiments, including cell growth, cell apoptosis and migration and invasion assays. The results indicated that the overexpression of CHIP in DU145 prostatic cancer cells promoted cell proliferation through activation of the protein kinase B (AKT) signaling pathway, which subsequently increased cyclin D1 protein levels and decreased p21 and p27 protein levels. The overexpression of CHIP significantly increased the migration and invasion of the DU145 cells, which is possible due to activation of the AKT signaling pathway and upregulation of vimentin. The expression level of CHIP was observed to be increased in human prostate cancer tissues compared with the adjacent normal tissue. Furthermore, the CHIP expression level exhibited a positively association with the Gleason score of the patents. These findings indicate that CHIP functions as an oncogene in prostate cancer.

Technological and life cycle assessment of organics processing odour control technologies.

PubMed

Bindra, Navin; Dubey, Brajesh; Dutta, Animesh

2015-09-15

As more municipalities and communities across developed world look towards implementing organic waste management programmes or upgrading existing ones, composting facilities are emerging as a popular choice. However, odour from these facilities continues to be one of the most important concerns in terms of cost & effective mitigation. This paper provides a technological and life cycle assessment of some of the different odour control technologies and treatment methods that can be implemented in organics processing facilities. The technological assessment compared biofilters, packed tower wet scrubbers, fine mist wet scrubbers, activated carbon adsorption, thermal oxidization, oxidization chemicals and masking agents. The technologies/treatment methods were evaluated and compared based on a variety of operational, usage and cost parameters. Based on the technological assessment it was found that, biofilters and packed bed wet scrubbers are the most applicable odour control technologies for use in organics processing faculties. A life cycle assessment was then done to compare the environmental impacts of the packed-bed wet scrubber system, organic (wood-chip media) bio-filter and inorganic (synthetic media) bio-filter systems. Twelve impact categories were assessed; cumulative energy demand (CED), climate change, human toxicity, photochemical oxidant formation, metal depletion, fossil depletion, terrestrial acidification, freshwater eutrophication, marine eutrophication, terrestrial eco-toxicity, freshwater eco-toxicity and marine eco-toxicity. The results showed that for all impact categories the synthetic media biofilter had the highest environmental impact, followed by the wood chip media bio-filter system. The packed-bed system had the lowest environmental impact for all categories. Copyright © 2015 Elsevier B.V. All rights reserved.

Nitrogen removal in wood chip combined substrate baffled subsurface-flow constructed wetlands: impact of matrix arrangement and intermittent aeration.

PubMed

Li, Huai; Chi, Zifang; Yan, Baixing; Cheng, Long; Li, Jianzheng

2017-02-01

In this study, two lab-scale baffled subsurface-flow constructed wetlands (BSFCWs), including gravel-wood chips-slag and gravel-slag-wood chips, were operated at different intermittent aeration to evaluate the effect of artificial aeration and slow-released carbon source on the treatment efficiency of high-strength nitrogen wastewater. Results indicated that gravel-slag-wood chips extended aerobic/anaerobic alternating environment to gravel and slag zones and maintained anaerobic condition in the subsequent wood chip section. The order of gravel-slag-wood chip was more beneficial to pollutant removal. Sufficient carbon source supply resulted from wood-chip-framework substrate simultaneously obtained high removals of COD (97%), NH 4 + -N (95%), and TN (94%) in BSFCWs at 2 h aeration per day. The results suggest that intermittent aeration combined with wood chips could achieve high nitrogen removal in BSFCWs.

Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

NASA Astrophysics Data System (ADS)

Hashida, Takushi; Nagata, Makoto

Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

CHIP promotes thyroid cancer proliferation via activation of the MAPK and AKT pathways.

PubMed

Zhang, Li; Liu, Lianyong; He, Xiaohua; Shen, Yunling; Liu, Xuerong; Wei, Jing; Yu, Fang; Tian, Jianqing

2016-08-26

The carboxyl terminus of Hsp70-interacting protein (CHIP) is a U box-type ubiquitin ligase that plays crucial roles in various biological processes, including tumor progression. To date, the functional mechanism of CHIP in thyroid cancer remains unknown. Here, we obtained evidence of upregulation of CHIP in thyroid cancer tissues and cell lines. CHIP overexpression markedly enhanced thyroid cancer cell viability and colony formation in vitro and accelerated tumor growth in vivo. Conversely, CHIP knockdown impaired cell proliferation and tumor growth. Notably, CHIP promoted cell growth through activation of MAPK and AKT pathways, subsequently decreasing p27 and increasing cyclin D1 and p-FOXO3a expression. Our findings collectively indicate that CHIP functions as an oncogene in thyroid cancer, and is therefore a potential therapeutic target for this disease. Copyright © 2016 Elsevier Inc. All rights reserved.

Bi-level multilayered microelectronic device package with an integral window

DOEpatents

Peterson, Kenneth A.; Watson, Robert D.

2002-01-01

A bi-level, multilayered package with an integral window for housing a microelectronic device. The device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The multilayered package can be formed of a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the window being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded and oriented so that the light-sensitive side is optically accessible through the window. A second chip can be bonded to the backside of the first chip, with the second chip being wirebonded to the second level of the bi-level package. The result is a compact, low-profile package, having an integral window that can be hermetically-sealed.

Actuation of digital micro drops by electrowetting on open microfluidic chips fabricated in photolithography.

PubMed

Ko, Hyojin; Lee, Jeong Soo; Jung, Chan-Hee; Choi, Jae-Hak; Kwon, Oh-Sun; Shin, Kwanwoo

2014-08-01

Basic manipulations of discrete liquid drops on opened microfluidic chips based on electrowetting on dielectrics were described. While most developed microfluidic chips are closed systems equipped with a top plate to cover mechanically and to contact electrically to drop samples, our chips are opened systems with a single plate without any electric contact to drops directly. The chips consist of a linear array of patterned electrodes at 1.8 mm pitch was fabricated on a glass plate coated with thin hydrophobic and dielectric layers by using various methods including photolithography, spin coating and ion sputtering. Several actuations such as lateral oscillation, colliding mergence and translational motion for 3-10 μL water drops have been demonstrated satisfactory. All these kinetic performances of opened chips were similar to those of closed chip systems, indicating superiority of a none-contact method for the transport of drops on opened microfluidic chips actuated by using electrowetting technique.

Trapping and Collection of Lymphocytes Using Microspot Array Chip and Magnetic Beads

NASA Astrophysics Data System (ADS)

Hashioka, Shingi; Obata, Tsutomu; Tokimitsu, Yoshiharu; Fujiki, Satoshi; Nakazato, Hiroyoshi; Muraguchi, Atsushi; Kishi, Hiroyuki; Tanino, Katsumi

2006-04-01

A microspot array chip, which has microspots of a magnetic thin film patterned on a glass substrate, was fabricated for trapping individual cells and for measuring their cellular response. The chip was easily fabricated by conventional semiconductor fabrication techniques on a mass production level as a disposable medical device. When a solution of lymphocyte-bound-magnetic beads was poured into the magnetized chip, each lymphocyte was trapped on each microspot of the magnetic thin film. The trapped cells were easily recovered from the chip using a micromanipulator. The micro-spot array chip can be utilized for arraying live cells and for measuring the response of each cell. The chip will be useful for preparing on array of different kinds of cells and for analyzing cellular response at the single cell level. The chip will be particularly useful for detecting antigen-specific B-lymphocytes and antigen-specific antibody complementary deoxyribonucleic acid (cDNA).

27 CFR 19.331 - Use of oak chips in spirits and caramel in brandy and rum.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 27 Alcohol, Tobacco Products and Firearms 1 2012-04-01 2012-04-01 false Use of oak chips in... Storage of Distilled Spirits Use of Oak Chips and Caramel § 19.331 Use of oak chips in spirits and caramel in brandy and rum. A proprietor may add oak chips that have not been treated with any chemical to...

27 CFR 19.331 - Use of oak chips in spirits and caramel in brandy and rum.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 27 Alcohol, Tobacco Products and Firearms 1 2014-04-01 2014-04-01 false Use of oak chips in... Storage of Distilled Spirits Use of Oak Chips and Caramel § 19.331 Use of oak chips in spirits and caramel in brandy and rum. A proprietor may add oak chips that have not been treated with any chemical to...

27 CFR 19.331 - Use of oak chips in spirits and caramel in brandy and rum.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 27 Alcohol, Tobacco Products and Firearms 1 2011-04-01 2011-04-01 false Use of oak chips in... Storage of Distilled Spirits Use of Oak Chips and Caramel § 19.331 Use of oak chips in spirits and caramel in brandy and rum. A proprietor may add oak chips that have not been treated with any chemical to...

27 CFR 19.331 - Use of oak chips in spirits and caramel in brandy and rum.

Code of Federal Regulations, 2013 CFR

2013-04-01

... 27 Alcohol, Tobacco Products and Firearms 1 2013-04-01 2013-04-01 false Use of oak chips in... Storage of Distilled Spirits Use of Oak Chips and Caramel § 19.331 Use of oak chips in spirits and caramel in brandy and rum. A proprietor may add oak chips that have not been treated with any chemical to...

A novel three-dimensional bone chip organ culture.

PubMed

Kuttenberger, Johannes; Polska, Elzbieta; Schaefer, Birgit M

2013-07-01

The objective of this study was to develop a 3D bone chip organ culture model. We aimed to collect in vitro evidence of the ability of vital bone chips to promote new bone formation. We developed a 3D in vitro hypoxic bone chip organ culture model. Histology of the bone chips was performed before and after culture and immunohistochemistry after 3-week culture. The 3D culture supernatants were tested for the presence of pro-angiogenic growth factors, TGFβ1, GADPH, bone alkaline phosphatase, osteocalcin, osteonectin, osteopontin, bone sialoprotein and collagen type I. Histology after culture revealed bone chips in a matrix of fibrin remnants and a fibrous-appearing matter. Collagen type I- and IV-positive structures were also identified. Cells could be seen on the surface of the bone chips, with spindle-shaped cells bridging the bone chip particles. Pro-angiogenic growth factors and TGFβ1were detected in the 3D cell culture supernatants. The transcripts for osteocalcin, bone sialoprotein and collagen type I were revealed only via PCR. Our results indicate that bone chips in our 3D organ culture remain vital and may stimulate the growth of a bone-forming matrix. The use of autogenous bone chips for oral and maxillofacial bone augmentation procedures is widespread in clinical practice. The rationale for this is that if bone chips remain vital in vivo, they could provide an environment promoting new bone formation through growth factors and cells. This 3D culture method is an essential tool for investigating the behaviour of bone chips.

On-Chip Biomedical Imaging

PubMed Central

Göröcs, Zoltán; Ozcan, Aydogan

2012-01-01

Lab-on-a-chip systems have been rapidly emerging to pave the way toward ultra-compact, efficient, mass producible and cost-effective biomedical research and diagnostic tools. Although such microfluidic and micro electromechanical systems achieved high levels of integration, and are capable of performing various important tasks on the same chip, such as cell culturing, sorting and staining, they still rely on conventional microscopes for their imaging needs. Recently several alternative on-chip optical imaging techniques have been introduced, which have the potential to substitute conventional microscopes for various lab-on-a-chip applications. Here we present a critical review of these recently emerging on-chip biomedical imaging modalities, including contact shadow imaging, lensfree holographic microscopy, fluorescent on-chip microscopy and lensfree optical tomography. PMID:23558399

Smart vision chips: An overview

NASA Technical Reports Server (NTRS)

Koch, Christof

1994-01-01

This viewgraph presentation presents four working analog VLSI vision chips: (1) time-derivative retina, (2) zero-crossing chip, (3) resistive fuse, and (4) figure-ground chip; work in progress on computing motion and neuromorphic systems; and conceptual and practical lessons learned.

HPLC-Chip/MS Technology in Proteomic Profiling

NASA Astrophysics Data System (ADS)

Vollmer, Martin; van de Goor, Tom

HPLC-chip/MS is a novel nanoflow analytical technology conducted on a microfabricated chip that allows for highly efficient HPLC separation and superior sensitive MS detection of complex proteomic mixtures. This is possible through on-chip preconcentration and separation with fluidic connection made automatically in a leak-tight fashion. Minimum precolumn and postcolumn peak dispersion and uncompromised ease of use result in compounds eluting in bands of only a few nanoliters. The chip is fabricated out of bio-inert polyimide-containing channels and integrated chip structures, such as an electrospray emitter, columns, and frits manufactured by laser ablation technology. Meanwhile, a variety of HPLC-chips differing in design and stationary phase are commercially available, which provide a comprehensive solution for applications in proteomics, glycomics, biomarker, and pharmaceutical discovery. The HPLC-chip can also be easily integrated into a multidimensional separation workflow where different orthogonal separation techniques are combined to solve a highly complex separation problems. In this chapter, we describe in detail the methodological chip usage and functionality and its application in the elucidation of the protein profile of human nucleoli.

Lab-on a-Chip

NASA Technical Reports Server (NTRS)

2003-01-01

Helen Cole, the project manager for the Lab-on-a-Chip Applications Development program, and Lisa Monaco, the project scientist for the program, insert a lab on a chip into the Caliper 42 which is specialized equipment that controls processes on commercial chips to support development of lab-on-a-chip applications. The system has special microscopes and imaging systems, so scientists can process and study different types of fluid, chemical, and medical tests conducted on chips. For example, researchers have examined fluorescent bacteria as it flows through the chips' fluid channels or microfluidic capillaries. Researchers at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama, have been studying how the lab-on-a-chip technology can be used for microbial detection, water quality monitoring, and detecting biosignatures of past or present life on Mars. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for not only space applications, but for many Earth applications, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects.

PubMed

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Oh, Jin Hyuk; Kim, Sun Ae; Park, Jaegyu; Kim, Sanggi

2015-06-10

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications.

Modified precision-husky progrind H-3045 for chipping biomass

Treesearch

Dana Mitchell; Fernando Seixas; John Klepac

2008-01-01

A specific size of whole tree chip was needed to co-mill wood chips with coal. The specifications are stringent because chips must be mixed with coal, as opposed to a co-firing process. In co-firing, two raw products are conveyed separately to a boiler. In co-milling, such as at Alabama Power's Plant Gadsden, the chip and coal mix must pass through a series of...

Controlling the type and the form of chip when machining steel

NASA Astrophysics Data System (ADS)

Gruby, S. V.; Lasukov, A. A.; Nekrasov, R. Yu; Politsinsky, E. V.; Arkhipova, D. A.

2016-08-01

The type of the chip produced in the process of machining influences many factors of production process. Controlling the type of chip when cutting metals is important for producing swarf chips and for easing its utilization as well as for protecting the machined surface, cutting tool and the worker. In the given work we provide the experimental data on machining structural steel with implanted tool. The authors show that it is possible to control the chip formation process to produce the required type of chip by selecting the material for machining the tool surface.

GeneChip Resequencing of the Smallpox Virus Genome Can Identify Novel Strains: a Biodefense Application▿

PubMed Central

Sulaiman, Irshad M.; Tang, Kevin; Osborne, John; Sammons, Scott; Wohlhueter, Robert M.

2007-01-01

We developed a set of seven resequencing GeneChips, based on the complete genome sequences of 24 strains of smallpox virus (variola virus), for rapid characterization of this human-pathogenic virus. Each GeneChip was designed to analyze a divergent segment of approximately 30,000 bases of the smallpox virus genome. This study includes the hybridization results of 14 smallpox virus strains. Of the 14 smallpox virus strains hybridized, only 7 had sequence information included in the design of the smallpox virus resequencing GeneChips; similar information for the remaining strains was not tiled as a reference in these GeneChips. By use of variola virus-specific primers and long-range PCR, 22 overlapping amplicons were amplified to cover nearly the complete genome and hybridized with the smallpox virus resequencing GeneChip set. These GeneChips were successful in generating nucleotide sequences for all 14 of the smallpox virus strains hybridized. Analysis of the data indicated that the GeneChip resequencing by hybridization was fast and reproducible and that the smallpox virus resequencing GeneChips could differentiate the 14 smallpox virus strains characterized. This study also suggests that high-density resequencing GeneChips have potential biodefense applications and may be used as an alternate tool for rapid identification of smallpox virus in the future. PMID:17182757

Detection of solder bump defects on a flip chip using vibration analysis

NASA Astrophysics Data System (ADS)

Liu, Junchao; Shi, Tielin; Xia, Qi; Liao, Guanglan

2012-03-01

Flip chips are widely used in microelectronics packaging owing to the high demand of integration in IC fabrication. Solder bump defects on flip chips are difficult to detect, because the solder bumps are obscured by the chip and substrate. In this paper a nondestructive detection method combining ultrasonic excitation with vibration analysis is presented for detecting missing solder bumps, which is a typical defect in flip chip packaging. The flip chip analytical model is revised by considering the influence of spring mass on mechanical energy of the system. This revised model is then applied to estimate the flip chip resonance frequencies. We use an integrated signal generator and power amplifier together with an air-coupled ultrasonic transducer to excite the flip chips. The vibrations are measured by a laser scanning vibrometer to detect the resonance frequencies. A sensitivity coefficient is proposed to select the sensitive resonance frequency order for defect detection. Finite element simulation is also implemented for further investigation. The results of analytical computation, experiment, and simulation prove the efficacy of the revised flip chip analytical model and verify the effectiveness of this detection method. Therefore, it may provide a guide for the improvement and innovation of the flip chip on-line inspection systems.

A proposed holistic approach to on-chip, off-chip, test, and package interconnections

NASA Astrophysics Data System (ADS)

Bartelink, Dirk J.

1998-11-01

The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

Optimal use of tandem biotin and V5 tags in ChIP assays

PubMed Central

Kolodziej, Katarzyna E; Pourfarzad, Farzin; de Boer, Ernie; Krpic, Sanja; Grosveld, Frank; Strouboulis, John

2009-01-01

Background Chromatin immunoprecipitation (ChIP) assays coupled to genome arrays (Chip-on-chip) or massive parallel sequencing (ChIP-seq) lead to the genome wide identification of binding sites of chromatin associated proteins. However, the highly variable quality of antibodies and the availability of epitopes in crosslinked chromatin can compromise genomic ChIP outcomes. Epitope tags have often been used as more reliable alternatives. In addition, we have employed protein in vivo biotinylation tagging as a very high affinity alternative to antibodies. In this paper we describe the optimization of biotinylation tagging for ChIP and its coupling to a known epitope tag in providing a reliable and efficient alternative to antibodies. Results Using the biotin tagged erythroid transcription factor GATA-1 as example, we describe several optimization steps for the application of the high affinity biotin streptavidin system in ChIP. We find that the omission of SDS during sonication, the use of fish skin gelatin as blocking agent and choice of streptavidin beads can lead to significantly improved ChIP enrichments and lower background compared to antibodies. We also show that the V5 epitope tag performs equally well under the conditions worked out for streptavidin ChIP and that it may suffer less from the effects of formaldehyde crosslinking. Conclusion The combined use of the very high affinity biotin tag with the less sensitive to crosslinking V5 tag provides for a flexible ChIP platform with potential implications in ChIP sequencing outcomes. PMID:19196479

Development of a package-free transparent disposable biosensor chip for simultaneous measurements of blood constituents and investigation of its storage stability.

PubMed

Nakamura, Hideaki; Tohyama, Kana; Tanaka, Masanori; Shinohara, Shouji; Tokunaga, Yuichi; Kurusu, Fumiyo; Koide, Satoshi; Gotoh, Masao; Karube, Isao

2007-12-15

A package-free transparent disposable biosensor chip was developed by a screen-printing technique. The biosensor chip was fabricated by stacking a substrate with two carbon electrodes on its surface, a spacer consisting of a resist layer and an adhesive layer, and a cover. The structure of the chip keeps the interior of the reaction-detecting section airtight until use. The chip is equipped with double electrochemical measuring elements for the simultaneous measurement of multiple items, and the reagent layer was developed in sample-feeding path. The sample-inlet port and air-discharge port are simultaneously opened by longitudinally folding in two biosensor units with a notch as a boundary. Then the shape of the chip is changed to a V-shape. The reaction-detecting section of the chip has a 1.0 microl sample volume for one biosensor unit. Excellent results were obtained with the chip in initial simultaneous chronoamperometric measurements of both glucose (r=1.00) and lactate (r=0.998) in the same samples. The stability of the enzyme sensor signals of the chip was estimated at ambient atmosphere on 8 testing days during a 6-month period. The results were compared with those obtained for an unpackaged chip used as a control. The package-free chip proved to be twice as good as the control chip in terms of the reproducibility of slopes from 16 calibration curves (one calibration curve: 0, 100, 300, 500 mg dl(-1) glucose; n=3) and 4.6 times better in terms of the reproducibility of correlation coefficients from the 16 calibration curves.

The E3 ubiquitin ligase CHIP selectively regulates mutant epidermal growth factor receptor by ubiquitination and degradation.

PubMed

Chung, Chaeuk; Yoo, Geon; Kim, Tackhoon; Lee, Dahye; Lee, Choong-Sik; Cha, Hye Rim; Park, Yeon Hee; Moon, Jae Young; Jung, Sung Soo; Kim, Ju Ock; Lee, Jae Cheol; Kim, Sun Young; Park, Hee Sun; Park, Myoungrin; Park, Dong Il; Lim, Dae-Sik; Jang, Kang Won; Lee, Jeong Eun

2016-10-14

Somatic mutation in the tyrosine kinase domain of epidermal growth factor receptor (EGFR) is a decisive factor for the therapeutic response to EGFR tyrosine kinase inhibitors (EGFR-TKIs) in lung adenocarcinoma. The stability of mutant EGFR is maintained by various regulators, including heat shock protein 90 (Hsp90). The C terminus of Hsc70-interacting protein (CHIP) is a Hsp70/Hsp90 co-chaperone and exhibits E3 ubiquitin ligase activity. The high-affinity Hsp90-CHIP complex recognizes and selectively regulates their client proteins. CHIP also works with its own E3 ligase activity independently of Hsp70/Hsp90. Here, we investigated the role of CHIP in regulating EGFR in lung adenocarcinoma and also evaluated the specificity of CHIP's effects on mutant EGFR. In HEK 293T cells transfected with either WT EGFR or EGFR mutants, the overexpression of CHIP selectively decreased the expression of certain EGFR mutants (G719S, L747_E749del A750P and L858R) but not WT EGFR. In a pull-down assay, CHIP selectively interacted with EGFR mutants and simultaneously induced their ubiquitination and proteasomal degradation. The expressions of mutant EGFR in PC9 and H1975 were diminished by CHIP, while the expression of WT EGFR in A549 was nearly not affected. In addition, CHIP overexpression inhibited cell proliferation and xenograft's tumor growth of EGFR mutant cell lines, but not WT EGFR cell lines. EGFR mutant specific ubiquitination by CHIP may provide a crucial regulating mechanism for EGFR in lung adenocarcinoma. Our results suggest that CHIP can be novel therapeutic target for overcoming the EGFR TKI resistance. Copyright © 2016 Elsevier Inc. All rights reserved.

Digestibility and metabolizable energy values of processed cassava chips for growing and finishing pigs.

PubMed

Lokaewmanee, Kanda; Kanto, Uthai; Juttupornpong, Sukanya; Yamauchi, Koh-en

2011-02-01

Determinations of digestibility of dry matter (DM), digestible energy (DE), and metabolizable energy (ME) in cassava chips with different levels of crude fiber (CF) were measured in growing pigs (20 kg) and finishing pigs (60 kg). The treatments were (1) cassava starch (0% CF), (2) peeled cassava chips (2.5% CF), (3) non-peeled washed cassava chips (3.9% CF), and (4) non-peeled and non-washed cassava chips (5.2% CF). In the growing pigs, peeled cassava chips, non-peeled washed cassava chips, and non-peeled and non-washed cassava chips had DM digestibility of 87.51%, 78.63%, and 73.89%, respectively. Their DE was 3.69, 3.49, and 3.32 Mcal/kg DM, respectively (DE of cassava starch is 3.90 Mcal/kg DM). ME was 3.54, 3.35, and 3.19 Mcal/kg DM, respectively (ME of cassava starch is 3.74 Mcal/kg DM). On the other hand, in the finishing pigs, the digestibility of DM was 89.13%, 80.63%, and 76.13%, respectively. Their DE was 3.72, 3.53, and 3.43 Mcal/kg DM, respectively (DE of cassava starch is 3.91 Mcal/kg DM). ME was 3.57, 3.38, and 3.29 Mcal/kg DM, respectively (ME of cassava starch is 3.75 Mcal/kg DM). These values increased with decreasing CF content, and the peeled cassava chips had the highest values (P < 0.01). These suggest that the digestibility values of DM, DE, and ME of cassava chips is inversely related to the CF content in cassava chips. It is recommended that cassava chips be peeled for better nutrition for growing and finishing pigs.

How Well Is CHIP Addressing Health Care Access and Affordability for Children?

PubMed

Clemans-Cope, Lisa; Kenney, Genevieve; Waidmann, Timothy; Huntress, Michael; Anderson, Nathaniel

2015-01-01

We examine how access to care and care experiences under the Children's Health Insurance Program (CHIP) compared to private coverage and being uninsured in 10 states. We report on findings from a 2012 survey of CHIP enrollees in 10 states. We examined a range of health care access and use measures among CHIP enrollees. Comparisons of the experiences of established CHIP enrollees to the experiences of uninsured and privately insured children were used to estimate differences in children's health care. Children with CHIP coverage had substantially better access to care across a range of outcomes, other things being equal, particularly compared to those with no coverage. Compared to being uninsured, CHIP enrollees were more likely to have specialty and mental health visits and to receive prescription drugs; and their parents were much more likely to feel confident in meeting the child's health care needs and were less likely to have trouble finding providers. CHIP enrollees were less likely to have unmet needs, but 1 in 4 had at least 1 unmet need. Compared to being privately insured, CHIP enrollees had generally similar health care use and unmet needs. Additionally, CHIP enrollees had lower financial burden related to their health care needs. The findings were generally robust with respect to alternative specifications and subgroup analyses, and they corroborated findings of previous studies. Enrolling more of the uninsured children who are eligible for CHIP improved their access to a range of care, including specialty and mental health services, and reduced the financial burden of meeting their health care needs; however, we found room for improvement in CHIP enrollees' access to care. Copyright © 2015 Academic Pediatric Association. All rights reserved.

Carboxy terminus of heat shock protein (HSP) 70-interacting protein (CHIP) inhibits HSP70 in the heart.

PubMed

Zhao, Bijun; Sun, Guocheng; Feng, Guanli; Duan, Weixun; Zhu, Xiaoling; Chen, Shaoyang; Hou, Lichao; Jin, Zhenxiao; Yi, Dinghua

2012-12-01

Heat shock protein (HSP) 70 plays a critical role in protecting the heart from various stressor-induced cell injuries; the mechanism remains to be further understood. The present study aims to elucidate the effect of a probiotics-derived protein, LGG-derived protein p75 (LGP), in alleviating the ischemia/reperfusion (I/R)-induced heart injury. We treated rats with the I/R with or without preadministration with LGP. The levels of HSP70 and carboxy terminus of HSP70-interacting protein (CHIP) in the heart tissue were assessed by enzyme-linked immunosorbent assay (ELISA) and Western blotting. The effect of CHIP on suppression of HSP70 and the effect of LGP on suppression of CHIP were investigated with an I/R rat model and a cell culture model. The results showed that I/R-induced infarction in the heart could be alleviated by pretreatment with LGP. HSP70 was detected in naïve rat heart tissue extracts. I/R treatment significantly suppressed the level of HSP70 and increased the levels of CHIP in the heart. A complex of CHIP/HSP70 was detected in heart tissue extracts. The addition of recombinant CHIP to culture inhibited HSP70 in heart cells. LGP was bound CHIP in heart cells and prevented the CHIP from binding HSP70. In summary, I/R can suppress HSP70 and increase CHIP in heart cells. CHIP can suppress HSP70 that can be prevented by pretreatment with LGP. The results imply that CHIP may be a potential target in the prevention of I/R-induced heart cell injury.

Prediction of metabolism-induced hepatotoxicity on three-dimensional hepatic cell culture and enzyme microarrays.

PubMed

Yu, Kyeong-Nam; Nadanaciva, Sashi; Rana, Payal; Lee, Dong Woo; Ku, Bosung; Roth, Alexander D; Dordick, Jonathan S; Will, Yvonne; Lee, Moo-Yeal

2018-03-01

Human liver contains various oxidative and conjugative enzymes that can convert nontoxic parent compounds to toxic metabolites or, conversely, toxic parent compounds to nontoxic metabolites. Unlike primary hepatocytes, which contain myriad drug-metabolizing enzymes (DMEs), but are difficult to culture and maintain physiological levels of DMEs, immortalized hepatic cell lines used in predictive toxicity assays are easy to culture, but lack the ability to metabolize compounds. To address this limitation and predict metabolism-induced hepatotoxicity in high-throughput, we developed an advanced miniaturized three-dimensional (3D) cell culture array (DataChip 2.0) and an advanced metabolizing enzyme microarray (MetaChip 2.0). The DataChip is a functionalized micropillar chip that supports the Hep3B human hepatoma cell line in a 3D microarray format. The MetaChip is a microwell chip containing immobilized DMEs found in the human liver. As a proof of concept for generating compound metabolites in situ on the chip and rapidly assessing their toxicity, 22 model compounds were dispensed into the MetaChip and sandwiched with the DataChip. The IC 50 values obtained from the chip platform were correlated with rat LD 50 values, human C max values, and drug-induced liver injury categories to predict adverse drug reactions in vivo. As a result, the platform had 100% sensitivity, 86% specificity, and 93% overall predictivity at optimum cutoffs of IC 50 and C max values. Therefore, the DataChip/MetaChip platform could be used as a high-throughput, early stage, microscale alternative to conventional in vitro multi-well plate platforms and provide a rapid and inexpensive assessment of metabolism-induced toxicity at early phases of drug development.

The use of fruit extracts for production of apple chips with enhanced antioxidant activity

PubMed

Tarko, Tomasz; Duda-Chodak, Aleksandra; Semik-Szczurak, Dorota

Style and pace of life make consumers more willing to reach for snack products. This group of processed food includes, among others, fruit chips. Due to the increasing incidence of diseases associated with the excessive exposure to free radicals foods enriched with antioxidant compounds, eg. polyphenols, can be introduced into the sale. The aim of the study was to use the fruit extracts for the production of apple chips with enhanced antioxidant activity. ‘Golden Delicious’ variety of apple fruit was used to produce chips. Apple chips were prepared by slicing, soaking in a sugar solution and pre-drying in a microwave oven. Chips were enriched with extracts prepared from fruits of chokeberry, five-flavor berry, Cornelian cherry, woodland hawthorn, goji berry, Japanese quince and cranberry microcarpa. For this purpose, pre-dried apple slices were soaked (5 min) in ethanolic extract of fruits and then dried to achieve a 5% moisture content. Chips were sensory evaluated and their antioxidant activity and total polyphenols content were determined. All enriched apple chips were characterized by high antioxidant activity and a relatively high value of total polyphenols content. Chips soaked in extracts of five-flavor berry, cranberry and goji berry were characterized by the highest antioxidant potential. Samples obtained by using chokeberry and Cornelian cherry extracts showed the highest content of polyphenols. High sensory attractiveness of enriched chips was also showed. The chips with the addition of fiveflavor berry extract were exceptions. Their taste was not acceptable. Fruit extracts are a valuable material for chips enrichment. Taking into account all the analyzed differentiators, extracts of Japanese quince, goji berry and woodland hawthorn were found to be the best enriching additives. The chips soaked in extract of five-flavor berry, despite their high antioxidant activity, were disqualified due to very low score of sensory evaluation.

Loss of the Nuclear Pool of Ubiquitin Ligase CHIP/STUB1 in Breast Cancer Unleashes the MZF1-Cathepsin Pro-oncogenic Program.

PubMed

Luan, Haitao; Mohapatra, Bhopal; Bielecki, Timothy A; Mushtaq, Insha; Mirza, Sameer; Jennings, Tameka A; Clubb, Robert J; An, Wei; Ahmed, Dena; El-Ansari, Rokaya; Storck, Matthew D; Mishra, Nitish K; Guda, Chittibabu; Sheinin, Yuri M; Meza, Jane L; Raja, Srikumar; Rakha, Emad A; Band, Vimla; Band, Hamid

2018-05-15

CHIP/STUB1 ubiquitin ligase is a negative co-chaperone for HSP90/HSC70, and its expression is reduced or lost in several cancers, including breast cancer. Using an extensive and well-annotated breast cancer tissue collection, we identified the loss of nuclear but not cytoplasmic CHIP to predict more aggressive tumorigenesis and shorter patient survival, with loss of CHIP in two thirds of ErbB2 + and triple-negative breast cancers (TNBC) and in one third of ER + breast cancers. Reduced CHIP expression was seen in breast cancer patient-derived xenograft tumors and in ErbB2 + and TNBC cell lines. Ectopic CHIP expression in ErbB2 + lines suppressed in vitro oncogenic traits and in vivo xenograft tumor growth. An unbiased screen for CHIP-regulated nuclear transcription factors identified many candidates whose DNA-binding activity was up- or downregulated by CHIP. We characterized myeloid zinc finger 1 (MZF1) as a CHIP target, given its recently identified role as a positive regulator of cathepsin B/L (CTSB/L)-mediated tumor cell invasion downstream of ErbB2. We show that CHIP negatively regulates CTSB/L expression in ErbB2 + and other breast cancer cell lines. CTSB inhibition abrogates invasion and matrix degradation in vitro and halts ErbB2 + breast cancer cell line xenograft growth. We conclude that loss of CHIP remodels the cellular transcriptome to unleash critical pro-oncogenic pathways, such as the matrix-degrading enzymes of the cathepsin family, whose components can provide new therapeutic opportunities in breast and other cancers with loss of CHIP expression. Significance: These findings reveal a novel targetable pathway of breast oncogenesis unleashed by the loss of tumor suppressor ubiquitin ligase CHIP/STUB1. Cancer Res; 78(10); 2524-35. ©2018 AACR . ©2018 American Association for Cancer Research.

Fundamental study of microelectronic chip response under laser ultrasonic-interferometric inspection using C-scan method

NASA Astrophysics Data System (ADS)

Yang, Lei; Gong, Jie; Ume, I. Charles

2014-02-01

In modern surface mount packaging technologies, such as flip chips, chip scale packages, and ball grid arrays(BGA), chips are attached to the substrates/printed wiring board (PWB) using solder bump interconnections. The quality of solder bumps between the chips and the substrate/board is difficult to inspect. Laser ultrasonic-interferometric technique was proved to be a promising approach for solder bump inspection because of its noncontact and nondestructive characteristics. Different indicators extracted from received signals have been used to predict the potential defects, such as correlation coefficient, error ratio, frequency shifting, etc. However, the fundamental understanding of the chip behavior under laser ultrasonic inspection is still missing. Specifically, it is not sure whether the laser interferometer detected out-of-plane displacements were due to wave propagation or structural vibration when the chip was excited by pulsed laser. Plus, it is found that the received signals are chip dependent. Both challenges impede the interpretation of acquired signals. In this paper, a C-scan method was proposed to study the underlying phenomenon during laser ultrasonic inspection. The full chip was inspected. The response of the chip under laser excitation was visualized in a movie resulted from acquired signals. Specifically, a BGA chip was investigated to demonstrate the effectiveness of this method. By characterizing signals using discrete wavelet transform(DWT), both ultrasonic wave propagation and vibration were observed. Separation of them was successfully achieved using ideal band-pass filter and visualized in resultant movies, too. The observed ultrasonic waves were characterized and their respective speeds were measured by applying 2-D FFT. The C-scan method, combined with different digital signal processing techniques, was proved to be an very effective methodology to learn the behavior of chips under laser excitation. This general procedure can be applied to any unknown chip before inspection. A wealth of information can be provided by this learning procedure, which greatly benefits the interpretation of inspection signals afterwards.

Around Marshall

NASA Image and Video Library

2003-12-01

Helen Cole, the project manager for the Lab-on-a-Chip Applications Development program, and Lisa Monaco, the project scientist for the program, insert a lab on a chip into the Caliper 42 which is specialized equipment that controls processes on commercial chips to support development of lab-on-a-chip applications. The system has special microscopes and imaging systems, so scientists can process and study different types of fluid, chemical, and medical tests conducted on chips. For example, researchers have examined fluorescent bacteria as it flows through the chips' fluid channels or microfluidic capillaries. Researchers at NASA's Marshall Space Flight Center (MSFC) in Huntsville, Alabama, have been studying how the lab-on-a-chip technology can be used for microbial detection, water quality monitoring, and detecting biosignatures of past or present life on Mars. The Marshall Center team is also collaborating with scientists at other NASA centers and at universities to develop custom chip designs for not only space applications, but for many Earth applications, such as for detecting deadly microbes in heating and air systems. (NASA/MSFC/D.Stoffer)

Transportable GPU (General Processor Units) chip set technology for standard computer architectures

NASA Astrophysics Data System (ADS)

Fosdick, R. E.; Denison, H. C.

1982-11-01

The USAFR-developed GPU Chip Set has been utilized by Tracor to implement both USAF and Navy Standard 16-Bit Airborne Computer Architectures. Both configurations are currently being delivered into DOD full-scale development programs. Leadless Hermetic Chip Carrier packaging has facilitated implementation of both architectures on single 41/2 x 5 substrates. The CMOS and CMOS/SOS implementations of the GPU Chip Set have allowed both CPU implementations to use less than 3 watts of power each. Recent efforts by Tracor for USAF have included the definition of a next-generation GPU Chip Set that will retain the application-proven architecture of the current chip set while offering the added cost advantages of transportability across ISO-CMOS and CMOS/SOS processes and across numerous semiconductor manufacturers using a newly-defined set of common design rules. The Enhanced GPU Chip Set will increase speed by an approximate factor of 3 while significantly reducing chip counts and costs of standard CPU implementations.

Microchannel cooling of face down bonded chips

DOEpatents

Bernhardt, Anthony F.

1993-01-01

Microchannel cooling is applied to flip-chip bonded integrated circuits, in a manner which maintains the advantages of flip-chip bonds, while overcoming the difficulties encountered in cooling the chips. The technique is suited to either multichip integrated circuit boards in a plane, or to stacks of circuit boards in a three dimensional interconnect structure. Integrated circuit chips are mounted on a circuit board using flip-chip or control collapse bonds. A microchannel structure is essentially permanently coupled with the back of the chip. A coolant delivery manifold delivers coolant to the microchannel structure, and a seal consisting of a compressible elastomer is provided between the coolant delivery manifold and the microchannel structure. The integrated circuit chip and microchannel structure are connected together to form a replaceable integrated circuit module which can be easily decoupled from the coolant delivery manifold and the circuit board. The coolant supply manifolds may be disposed between the circuit boards in a stack and coupled to supplies of coolant through a side of the stack.

CHIP mediates down-regulation of nucleobindin-1 in preosteoblast cell line models.

PubMed

Xue, Fuying; Wu, Yanping; Zhao, Xinghui; Zhao, Taoran; Meng, Ying; Zhao, Zhanzhong; Guo, Junwei; Chen, Wei

2016-08-01

Nucleobindin-1 (NUCB1), also known as Calnuc, is a highly conserved, multifunctional protein widely expressed in tissues and cells. It contains two EF-hand motifs which have been shown to play a crucial role in binding Ca(2+) ions. In this study, we applied comparative two-dimensional gel electrophoresis to characterize differentially expressed proteins in HA-CHIP over-expressed and endogenous CHIP depleted MC3T3-E1 stable cell lines, identifying NUCB1 as a novel CHIP/Stub1 targeted protein. NUCB1 interacts with and is down-regulated by CHIP by both proteasomal dependent and independent pathways, suggesting that CHIP-mediated down-regulation of nucleobindin-1 might play a role in osteoblast differentiation. The chaperone protein Hsp70 was found to be important for CHIP and NUCB1 interaction as well as CHIP-mediated NUCB1 down-regulation. Our findings provide new insights into understanding the stability regulation of NUCB1. Copyright © 2016 Elsevier Inc. All rights reserved.

C-terminus of HSC70-Interacting Protein (CHIP) Inhibits Adipocyte Differentiation via Ubiquitin- and Proteasome-Mediated Degradation of PPARγ

PubMed Central

Kim, Jung-Hoon; Shin, Soyeon; Seo, Jinho; Lee, Eun-Woo; Jeong, Manhyung; Lee, Min-sik; Han, Hyun-Ji; Song, Jaewhan

2017-01-01

PPARγ (Peroxisome proliferator-activated receptor γ) is a nuclear receptor involved in lipid homeostasis and related metabolic diseases. Acting as a transcription factor, PPARγ is a master regulator for adipocyte differentiation. Here, we reveal that CHIP (C-terminus of HSC70-interacting protein) suppresses adipocyte differentiation by functioning as an E3 ligase of PPARγ. CHIP directly binds to and induces ubiquitylation of the PPARγ protein, leading to proteasome-dependent degradation. Stable overexpression or knockdown of CHIP inhibited or promoted adipogenesis, respectively, in 3T3-L1 cells. On the other hand, a CHIP mutant defective in E3 ligase could neither regulate PPARγ protein levels nor suppress adipogenesis, indicating the importance of CHIP-mediated ubiquitylation of PPARγ in adipocyte differentiation. Lastly, a CHIP null embryo fibroblast exhibited augmented adipocyte differentiation with increases in PPARγ and its target protein levels. In conclusion, CHIP acts as an E3 ligase of PPARγ, suppressing PPARγ-mediated adipogenesis. PMID:28059128

ChIP-seq.

PubMed

Kim, Tae Hoon; Dekker, Job

2018-05-01

Owing to its digital nature, ChIP-seq has become the standard method for genome-wide ChIP analysis. Using next-generation sequencing platforms (notably the Illumina Genome Analyzer), millions of short sequence reads can be obtained. The densities of recovered ChIP sequence reads along the genome are used to determine the binding sites of the protein. Although a relatively small amount of ChIP DNA is required for ChIP-seq, the current sequencing platforms still require amplification of the ChIP DNA by ligation-mediated PCR (LM-PCR). This protocol, which involves linker ligation followed by size selection, is the standard ChIP-seq protocol using an Illumina Genome Analyzer. The size-selected ChIP DNA is amplified by LM-PCR and size-selected for the second time. The purified ChIP DNA is then loaded into the Genome Analyzer. The ChIP DNA can also be processed in parallel for ChIP-chip results. © 2018 Cold Spring Harbor Laboratory Press.

Three dimensional, multi-chip module

DOEpatents

Bernhardt, A.F.; Petersen, R.W.

1993-08-31

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow dummy chips'' are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned on the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

Three dimensional, multi-chip module

DOEpatents

Bernhardt, Anthony F.; Petersen, Robert W.

1993-01-01

A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow "dummy chips" are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned o the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

Spectral Demultiplexing in Holographic and Fluorescent On-chip Microscopy

NASA Astrophysics Data System (ADS)

Sencan, Ikbal; Coskun, Ahmet F.; Sikora, Uzair; Ozcan, Aydogan

2014-01-01

Lensfree on-chip imaging and sensing platforms provide compact and cost-effective designs for various telemedicine and lab-on-a-chip applications. In this work, we demonstrate computational solutions for some of the challenges associated with (i) the use of broadband, partially-coherent illumination sources for on-chip holographic imaging, and (ii) multicolor detection for lensfree fluorescent on-chip microscopy. Specifically, we introduce spectral demultiplexing approaches that aim to digitally narrow the spectral content of broadband illumination sources (such as wide-band light emitting diodes or even sunlight) to improve spatial resolution in holographic on-chip microscopy. We also demonstrate the application of such spectral demultiplexing approaches for wide-field imaging of multicolor fluorescent objects on a chip. These computational approaches can be used to replace e.g., thin-film interference filters, gratings or other optical components used for spectral multiplexing/demultiplexing, which can form a desirable solution for cost-effective and compact wide-field microscopy and sensing needs on a chip.

Ubiquitinylation of α-Synuclein by Carboxyl Terminus Hsp70-Interacting Protein (CHIP) Is Regulated by Bcl-2-Associated Athanogene 5 (BAG5)

PubMed Central

Chau, Hien; Lozano, Andres M.; Hyman, Bradley T.; McLean, Pamela J.

2011-01-01

Parkinson's disease (PD) is a common neurodegenerative condition in which abnormalities in protein homeostasis, or proteostasis, may lead to accumulation of the protein α-synuclein (α-syn). Mutations within or multiplications of the gene encoding α-syn are known to cause genetic forms of PD and polymorphisms in the gene are recently established risk factors for idiopathic PD. α-syn is a major component of Lewy bodies, the intracellular proteinaceous inclusions which are pathological hallmarks of most forms of PD. Recent evidence demonstrates that α-syn can self associate into soluble oligomeric species and implicates these α-syn oligomers in cell death. We have previously shown that carboxyl terminus of Hsp70-interacting protein (CHIP), a co-chaperone molecule with E3 ubiquitin ligase activity, may reduce the levels of toxic α-syn oligomers. Here we demonstrate that α-syn is ubiquitinylated by CHIP both in vitro and in cells. We find that the products from ubiquitinylation by CHIP include both monoubiquitinylated and polyubiquitinylated forms of α-syn. We also demonstrate that CHIP and α-syn exist within a protein complex with the co-chaperone bcl-2-associated athanogene 5 (BAG5) in brain. The interaction of CHIP with BAG5 is mediated by Hsp70 which binds to the tetratricopeptide repeat domain of CHIP and the BAG domains of BAG5. The Hsp70-mediated association of BAG5 with CHIP results in inhibition of CHIP E3 ubiquitin ligase activity and subsequently reduces α-syn ubiquitinylation. Furthermore, we use a luciferase-based protein-fragment complementation assay of α-syn oligomerization to investigate regulation of α-syn oligomers by CHIP in living cells. We demonstrate that BAG5 mitigates the ability of CHIP to reduce α-syn oligomerization and that non-ubiquitinylated α-syn has an increased propensity for oligomerization. Thus, our results identify CHIP as an E3 ubiquitin ligase of α-syn and suggest a novel function for BAG5 as a modulator of CHIP E3 ubiquitin ligase activity with implications for CHIP-mediated regulation of α-syn oligomerization. PMID:21358815

Sea otter dental enamel is highly resistant to chipping due to its microstructure

PubMed Central

Ziscovici, Charles; Lucas, Peter W.; Constantino, Paul J.; Bromage, Timothy G.; van Casteren, Adam

2014-01-01

Dental enamel is prone to damage by chipping with large hard objects at forces that depend on chip size and enamel toughness. Experiments on modern human teeth have suggested that some ante-mortem chips on fossil hominin enamel were produced by bite forces near physiological maxima. Here, we show that equivalent chips in sea otter enamel require even higher forces than human enamel. Increased fracture resistance correlates with more intense enamel prism decussation, often seen also in some fossil hominins. It is possible therefore that enamel chips in such hominins may have formed at even greater forces than currently envisaged. PMID:25319817

Intelligent Computation for Optimal Fabrication Condition of a Protein Chip with Ni-Co Alloy-Coated Surface.

PubMed

Chang, Yaw-Jen; Chang, Cheng-Hao

2016-06-01

Based on the principle of immobilized metal affinity chromatography (IMAC), it has been found that a Ni-Co alloy-coated protein chip is able to immobilize functional proteins with a His-tag attached. In this study, an intelligent computational approach was developed to promote the performance and repeatability of a Ni-Co alloy-coated protein chip. This approach was launched out of L18 experiments. Based on the experimental data, the fabrication process model of a Ni-Co protein chip was established by using an artificial neural network, and then an optimal fabrication condition was obtained using the Taguchi genetic algorithm. The result was validated experimentally and compared with a nitrocellulose chip. Consequentially, experimental outcomes revealed that the Ni-Co alloy-coated chip, fabricated using the proposed approach, had the best performance and repeatability compared with the Ni-Co chips of an L18 orthogonal array design and the nitrocellulose chip. Moreover, the low fluorescent background of the chip surface gives a more precise fluorescent detection. Based on a small quantity of experiments, this proposed intelligent computation approach can significantly reduce the experimental cost and improve the product's quality. © 2015 Society for Laboratory Automation and Screening.

Multiple functions of the E3 ubiquitin ligase CHIP in immunity.

PubMed

Zhan, Shaohua; Wang, Tianxiao; Ge, Wei

2017-09-03

The carboxyl terminal of Hsp70-interacting protein (CHIP) is an E3 ubiquitin ligase that plays a pivotal role in the protein quality control system by shifting the balance of the folding-refolding machinery toward the degradative pathway. However, the precise mechanisms by which nonnative proteins are selected for degradation by CHIP either directly or indirectly via chaperone Hsp70 or Hsp90 are still not clear. In this review, we aim to provide a comprehensive model of the mechanism by which CHIP degrades its substrate in a chaperone-dependent or direct manner. In addition, through tight regulation of the protein level of its substrates, CHIP plays important roles in many physiological and pathological conditions, including cancers, neurological disorders, cardiac diseases, bone metabolism, immunity, and so on. Nonetheless, the precise mechanisms underlying the regulation of the immune system by CHIP are still poorly understood despite accumulating developments in our understanding of the regulatory roles of CHIP in both innate and adaptive immune responses. In this review, we also aim to provide a view of CHIP-mediated regulation of immune responses and the signaling pathways involved in the model described. Finally, we discuss the roles of CHIP in immune-related diseases.

Comparison of the performance of Ion Torrent chips in noninvasive prenatal trisomy detection.

PubMed

Wang, Yanlin; Wen, Zujia; Shen, Jiawei; Cheng, Weiwei; Li, Jun; Qin, Xiaolan; Ma, Duan; Shi, Yongyong

2014-07-01

Semiconductor high-throughput sequencing, represented by Ion Torrent PGM/Proton, proves to be feasible in the noninvasive prenatal diagnosis of fetal aneuploidies. It is commendable that, with less data and relevant cost also, an accurate result can be achieved owing to the high sensitivity and specificity of such kind of technology. We conducted a comparative analysis of the performance of four different Ion chips in detecting fetal chromosomal aneuploidies. Eight maternal plasma DNA samples, including four pregnancies with normal fetuses and four with trisomy 21 fetuses, were sequenced on Ion Torrent 314/316/318/PI chips, respectively. Results such as read mapped ratio, correlation coefficient and phred quality score were calculated and parallelly compared. All samples were correctly classified even with low-throughput chip, and, among the four chips, the 316 chip had the highest read mapped ratio, correlation coefficient, mean read length and phred quality score. All chips were well consistent with each other. Our results showed that all Ion chips are applicable in noninvasive prenatal fetal aneuploidy diagnosis. We recommend researchers or clinicians to use the appropriate chip with barcoding technology on the basis of the sample number.

Coverage and efficiency in current SNP chips

PubMed Central

Ha, Ngoc-Thuy; Freytag, Saskia; Bickeboeller, Heike

2014-01-01

To answer the question as to which commercial high-density SNP chip covers most of the human genome given a fixed budget, we compared the performance of 12 chips of different sizes released by Affymetrix and Illumina for the European, Asian, and African populations. These include Affymetrix' relatively new population-optimized arrays, whose SNP sets are each tailored toward a specific ethnicity. Our evaluation of the chips included the use of two measures, efficiency and cost–benefit ratio, which we developed as supplements to genetic coverage. Unlike coverage, these measures factor in the price of a chip or its substitute size (number of SNPs on chip), allowing comparisons to be drawn between differently priced chips. In this fashion, we identified the Affymetrix population-optimized arrays as offering the most cost-effective coverage for the Asian and African population. For the European population, we established the Illumina Human Omni 2.5-8 as the preferred choice. Interestingly, the Affymetrix chip tailored toward an Eastern Asian subpopulation performed well for all three populations investigated. However, our coverage estimates calculated for all chips proved much lower than those advertised by the producers. All our analyses were based on the 1000 Genome Project as reference population. PMID:24448550

Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects

PubMed Central

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Gyoo Kim, In; Hyuk Oh, Jin; Ae Kim, Sun; Park, Jaegyu; Kim, Sanggi

2015-01-01

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications. PMID:26061463

CoNNeCT Baseband Processor Module

NASA Technical Reports Server (NTRS)

Yamamoto, Clifford K; Jedrey, Thomas C.; Gutrich, Daniel G.; Goodpasture, Richard L.

2011-01-01

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

Novel processor architecture for onboard infrared sensors

NASA Astrophysics Data System (ADS)

Hihara, Hiroki; Iwasaki, Akira; Tamagawa, Nobuo; Kuribayashi, Mitsunobu; Hashimoto, Masanori; Mitsuyama, Yukio; Ochi, Hiroyuki; Onodera, Hidetoshi; Kanbara, Hiroyuki; Wakabayashi, Kazutoshi; Tada, Munehiro

2016-09-01

Infrared sensor system is a major concern for inter-planetary missions that investigate the nature and the formation processes of planets and asteroids. The infrared sensor system requires signal preprocessing functions that compensate for the intensity of infrared image sensors to get high quality data and high compression ratio through the limited capacity of transmission channels towards ground stations. For those implementations, combinations of Field Programmable Gate Arrays (FPGAs) and microprocessors are employed by AKATSUKI, the Venus Climate Orbiter, and HAYABUSA2, the asteroid probe. On the other hand, much smaller size and lower power consumption are demanded for future missions to accommodate more sensors. To fulfill this future demand, we developed a novel processor architecture which consists of reconfigurable cluster cores and programmable-logic cells with complementary atom switches. The complementary atom switches enable hardware programming without configuration memories, and thus soft-error on logic circuit connection is completely eliminated. This is a noteworthy advantage for space applications which cannot be found in conventional re-writable FPGAs. Almost one-tenth of lower power consumption is expected compared to conventional re-writable FPGAs because of the elimination of configuration memories. The proposed processor architecture can be reconfigured by behavioral synthesis with higher level language specification. Consequently, compensation functions are implemented in a single chip without accommodating program memories, which is accompanied with conventional microprocessors, while maintaining the comparable performance. This enables us to embed a processor element on each infrared signal detector output channel.

Digital algorithms for parallel pipelined single-detector homodyne fringe counting in laser interferometry

NASA Astrophysics Data System (ADS)

Rerucha, Simon; Sarbort, Martin; Hola, Miroslava; Cizek, Martin; Hucl, Vaclav; Cip, Ondrej; Lazar, Josef

2016-12-01

The homodyne detection with only a single detector represents a promising approach in the interferometric application which enables a significant reduction of the optical system complexity while preserving the fundamental resolution and dynamic range of the single frequency laser interferometers. We present the design, implementation and analysis of algorithmic methods for computational processing of the single-detector interference signal based on parallel pipelined processing suitable for real time implementation on a programmable hardware platform (e.g. the FPGA - Field Programmable Gate Arrays or the SoC - System on Chip). The algorithmic methods incorporate (a) the single detector signal (sine) scaling, filtering, demodulations and mixing necessary for the second (cosine) quadrature signal reconstruction followed by a conic section projection in Cartesian plane as well as (a) the phase unwrapping together with the goniometric and linear transformations needed for the scale linearization and periodic error correction. The digital computing scheme was designed for bandwidths up to tens of megahertz which would allow to measure the displacements at the velocities around half metre per second. The algorithmic methods were tested in real-time operation with a PC-based reference implementation that employed the advantage pipelined processing by balancing the computational load among multiple processor cores. The results indicate that the algorithmic methods are suitable for a wide range of applications [3] and that they are bringing the fringe counting interferometry closer to the industrial applications due to their optical setup simplicity and robustness, computational stability, scalability and also a cost-effectiveness.

45 CFR 155.302 - Options for conducting eligibility determinations.

Code of Federal Regulations, 2014 CFR

2014-10-01

...), provided that any contracting arrangement for eligibility determinations for Medicaid and CHIP is subject... section, subject to the standards in paragraph (d) of this section. (b) Medicaid and CHIP. Notwithstanding... and CHIP, rather than an eligibility determination for Medicaid and CHIP, provided that— (1) The...

45 CFR 155.302 - Options for conducting eligibility determinations.

Code of Federal Regulations, 2013 CFR

2013-10-01

...), provided that any contracting arrangement for eligibility determinations for Medicaid and CHIP is subject... section, subject to the standards in paragraph (d) of this section. (b) Medicaid and CHIP. Notwithstanding... and CHIP, rather than an eligibility determination for Medicaid and CHIP, provided that— (1) The...

Solid state lighting component

DOEpatents

Yuan, Thomas; Keller, Bernd; Ibbetson, James; Tarsa, Eric; Negley, Gerald

2010-10-26

An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips.

Solid state lighting component

DOEpatents

Yuan, Thomas; Keller, Bernd; Ibbetson, James; Tarsa, Eric; Negley, Gerald

2015-07-07

An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips.

Solid state lighting component

DOEpatents

Keller, Bernd; Ibbetson, James; Tarsa, Eric; Negley, Gerald; Yuan, Thomas

2012-07-10

An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips.

Thermal Hotspots in CPU Die and It's Future Architecture

NASA Astrophysics Data System (ADS)

Wang, Jian; Hu, Fu-Yuan

Owing to the increasing core frequency and chip integration and the limited die dimension, the power densities in CPU chip have been increasing fastly. The high temperature on chip resulted by power densities threats the processor's performance and chip's reliability. This paper analyzed the thermal hotspots in die and their properties. A new architecture of function units in die - - hot units distributed architecture is suggested to cope with the problems of high power densities for future processor chip.

Suitability of shredded tyres as a substitute for a landfill leachate collection medium.

PubMed

Park, Jae K; Edil, Tuncer B; Kim, Jae Y; Huh, Mock; Lee, Sung Ho; Lee, Jung Jun

2003-06-01

A series of tests were conducted to investigate the fate of heavy metals and gasoline components in a simulated landfill, consisting of a 30 cm thick clay liner and a leachate collection layer containing tyres as well as in two test cells installed in a landfill. Arsenic, selenium, mercury, barium, and lead concentrations were lower while zinc concentration was higher in the tank containing tyre-chips than the tank without tyre-chips. When samples were filtered, however, concentrations of zinc as well as other inorganics were lower in the tank containing tyre-chips, indicating that metals in the leachate exposed to tyre-chips travel more slowly in a subsurface environment due to filtering effect. In a test cell study, arsenic, cobalt, lead and nickel concentrations were lower in the cell containing tyre-chips than in the cell without tyre-chips, except iron and zinc. Both tests indicate that some inorganic contaminants are sorbed to tyre-chips. Gasoline components were also significantly sorbed by tyre-chips in field cell tests. Although tyre-chips are known to leach organic and inorganic contaminants, concentrations in field conditions will be lower than the reported experimental results since the tests were performed under worst-case scenarios. If tyre-chips are used in areas where contamination levels are high, then they can be used as a sorbent for environmental clean-up.

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

CHIP/Stub1 regulates the Warburg effect by promoting degradation of PKM2 in ovarian carcinoma.

PubMed

Shang, Y; He, J; Wang, Y; Feng, Q; Zhang, Y; Guo, J; Li, J; Li, S; Wang, Y; Yan, G; Ren, F; Shi, Y; Xu, J; Zeps, N; Zhai, Y; He, D; Chang, Z

2017-07-20

Tumor cells preferentially adopt aerobic glycolysis for their energy supply, a phenomenon known as the Warburg effect. It remains a matter of debate as to how the Warburg effect is regulated during tumor progression. Here, we show that CHIP (carboxyl terminus of Hsc70-interacting protein), a U-box E3 ligase, suppresses tumor progression in ovarian carcinomas by inhibiting aerobic glycolysis. While CHIP is downregulated in ovarian carcinoma, induced expression of CHIP results in significant inhibition of the tumor growth examined by in vitro and in vivo experiments. Reciprocally, depletion of CHIP leads to promotion of tumor growth. By a SiLAD proteomics analysis, we identified pyruvate kinase isoenzyme M2 (PKM2), a critical regulator of glycolysis in tumors, as a target that CHIP mediated for degradation. Accordingly, we show that CHIP regulates PKM2 protein stability and thereafter the energy metabolic processes. Depletion or knockout of CHIP increased the glycolytic products in both tumor and mouse embryonic fibroblast cells. Simultaneously, we observed that CHIP expression inversely correlated with PKM2 levels in human ovarian carcinomas. This study reveals a mechanism that the Warburg effect is regulated by CHIP through its function as an E3 ligase, which mediates the degradation of PKM2 during tumor progression. Our findings shed new light into understanding of ovarian carcinomas and may provide a new therapeutic strategy for ovarian cancer.

Rubus: A compiler for seamless and extensible parallelism

PubMed Central

Adnan, Muhammad; Aslam, Faisal; Sarwar, Syed Mansoor

2017-01-01

Nowadays, a typical processor may have multiple processing cores on a single chip. Furthermore, a special purpose processing unit called Graphic Processing Unit (GPU), originally designed for 2D/3D games, is now available for general purpose use in computers and mobile devices. However, the traditional programming languages which were designed to work with machines having single core CPUs, cannot utilize the parallelism available on multi-core processors efficiently. Therefore, to exploit the extraordinary processing power of multi-core processors, researchers are working on new tools and techniques to facilitate parallel programming. To this end, languages like CUDA and OpenCL have been introduced, which can be used to write code with parallelism. The main shortcoming of these languages is that programmer needs to specify all the complex details manually in order to parallelize the code across multiple cores. Therefore, the code written in these languages is difficult to understand, debug and maintain. Furthermore, to parallelize legacy code can require rewriting a significant portion of code in CUDA or OpenCL, which can consume significant time and resources. Thus, the amount of parallelism achieved is proportional to the skills of the programmer and the time spent in code optimizations. This paper proposes a new open source compiler, Rubus, to achieve seamless parallelism. The Rubus compiler relieves the programmer from manually specifying the low-level details. It analyses and transforms a sequential program into a parallel program automatically, without any user intervention. This achieves massive speedup and better utilization of the underlying hardware without a programmer’s expertise in parallel programming. For five different benchmarks, on average a speedup of 34.54 times has been achieved by Rubus as compared to Java on a basic GPU having only 96 cores. Whereas, for a matrix multiplication benchmark the average execution speedup of 84 times has been achieved by Rubus on the same GPU. Moreover, Rubus achieves this performance without drastically increasing the memory footprint of a program. PMID:29211758

Effect of autohydrolysis on the wettability, absorbility and further alkali impregnation of poplar wood chips.

PubMed

Xu, Ningpan; Liu, Wei; Hou, Qingxi; Wang, Peiyun; Yao, Zhirong

2016-09-01

Autohydrolysis with different severity factors was performed on poplar wood chips prior to pulping, and the wettability, absorbility and the following impregnation of NaOH solution for the poplar wood chips were then investigated. The results showed that after autohydrolysis pretreatment the porosity, shrinkage and fiber saturation point (FSP) of the poplar wood chips were increased, while the surface contact angle decreased as the severity factor was increased. The autohydrolyzed chips absorbed more NaOH in impregnation that resulted in a low NaOH concentration in the bulk impregnation liquor (i.e., the impregnation liquor outside wood chips), while the concentration in the entrapped liquor (i.e., the impregnation liquor inside wood chips) was increased. Autohydrolysis substantially improved the effectiveness of alkali impregnation. Copyright © 2016 Elsevier Ltd. All rights reserved.

Comparison of bone healing and outcomes between allogenous bone chip and hydroxyapatite chip grafts in open wedge high tibial osteotomy.

PubMed

Lee, O-Sung; Lee, Kyung Jae; Lee, Yong Seuk

2017-11-03

Allogenous bone chips and hydroxyapatite (HA) chips have been known as good options for filling an inevitable void after open wedge high tibial osteotomy (OWHTO). However, there are concerns regarding bone healing after the use of these grafts. The purpose of this study was to compare the bone healing represented by the osteoconductivity and absorbability between allogenous bone chips and HA chips in OWHTO. The outcomes of bone healing of 53 patients who received an allogenous bone chip graft and 41 patients who received an HA chip graft were retrospectively evaluated, and the results were compared between the two groups. Osteoconductivity and absorbability were serially evaluated for the assessment of bone healing at 6 weeks, 3 months, 6 months, and 1 year postoperatively. The osteoconductivity of the allogenous bone chips was greater than that of the HA chips at 6 weeks postoperatively (p < 0.05). However, there were no statistically significant differences from 3 months to 1 year postoperatively. The absorbability showed no statistically significant differences 6 weeks and 3 months after OWHTO; however, the allogenous bone chip group showed a greater absorbability at 6 months and 1 year postoperatively (42.8 ± 14.2 vs. 34.6 ± 13.8, p = 0.006 at 6 months postoperatively; 54.6 ± 14.4 vs. 43.0 ± 14.0, p < 0.001 at 1 year postoperatively). However, the two graft materials showed similar results of HKA angle, WBL ratio, posterior tibial slope.

Floating Chip Mounting System Driven by Repulsive Force of Permanent Magnets for Multiple On-Site SPR Immunoassay Measurements

PubMed Central

Horiuchi, Tsutomu; Tobita, Tatsuya; Miura, Toru; Iwasaki, Yuzuru; Seyama, Michiko; Inoue, Suzuyo; Takahashi, Jun-ichi; Haga, Tsuneyuki; Tamechika, Emi

2012-01-01

We have developed a measurement chip installation/removal mechanism for a surface plasmon resonance (SPR) immunoassay analysis instrument designed for frequent testing, which requires a rapid and easy technique for changing chips. The key components of the mechanism are refractive index matching gel coated on the rear of the SPR chip and a float that presses the chip down. The refractive index matching gel made it possible to optically couple the chip and the prism of the SPR instrument easily via elastic deformation with no air bubbles. The float has an autonomous attitude control function that keeps the chip parallel in relation to the SPR instrument by employing the repulsive force of permanent magnets between the float and a float guide located in the SPR instrument. This function is realized by balancing the upward elastic force of the gel and the downward force of the float, which experiences a leveling force from the float guide. This system makes it possible to start an SPR measurement immediately after chip installation and to remove the chip immediately after the measurement with a simple and easy method that does not require any fine adjustment. Our sensor chip, which we installed using this mounting system, successfully performed an immunoassay measurement on a model antigen (spiked human-IgG) in a model real sample (non-homogenized milk) that included many kinds of interfering foreign substances without any sample pre-treatment. The ease of the chip installation/removal operation and simple measurement procedure are suitable for frequent on-site agricultural, environmental and medical testing. PMID:23202030

Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments.

PubMed

Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

2015-08-18

In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a "one-sensor-one-packaging_technology" concept. The second one uses a standard flip-chip bonding technique. The first sensor is a "floating-concept", capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not "floating" but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

Protein Chips Compatible with MALDI Mass Spectrometry Prepared by Ambient Ion Landing.

PubMed

Pompach, Petr; Benada, Oldřich; Rosůlek, Michal; Darebná, Petra; Hausner, Jiří; Růžička, Viktor; Volný, Michael; Novák, Petr

2016-09-06

We present a technology that allows the preparation of matrix-assisted laser desorption/ionization (MALDI)-compatible protein chips by ambient ion landing of proteins and successive utilization of the resulting protein chips for the development of bioanalytical assays. These assays are based on the interaction between the immobilized protein and the sampled analyte directly on the protein chip and subsequent in situ analysis by MALDI mass spectrometry. The electrosprayed proteins are immobilized on dry metal and metal oxide surfaces, which are nonreactive under normal conditions. The ion landing of electrosprayed protein molecules is performed under atmospheric pressure by an automated ion landing apparatus that can manufacture protein chips with a predefined array of sample positions or any other geometry of choice. The protein chips prepared by this technique are fully compatible with MALDI ionization because the metal-based substrates are conductive and durable enough to be used directly as MALDI plates. Compared to other materials, the nonreactive surfaces show minimal nonspecific interactions with chemical species in the investigated sample and are thus an ideal substrate for selective protein chips. Three types of protein chips were used in this report to demonstrate the bioanalytical applications of ambient ion landing. The protein chips with immobilized proteolytic enzymes showed the usefulness for fast in situ peptide MALDI sequencing; the lectin-based protein chips showed the ability to enrich glycopeptides from complex mixtures with subsequent MALDI analysis, and the protein chips with immobilized antibodies were used for a novel immunoMALDI workflow that allowed the enrichment of antigens from the serum followed by highly specific MALDI detection.

42 CFR 431.998 - Difference resolution and appeal process.

Code of Federal Regulations, 2012 CFR

2012-10-01

... for Estimating Improper Payments in Medicaid and CHIP § 431.998 Difference resolution and appeal... care claims in Medicaid or CHIP within 20 business days after the disposition report of claims review... CHIP agencies with personnel that are responsible for Medicaid and CHIP policy and operations, the...

42 CFR 457.348 - Determinations of Children's Health Insurance Program eligibility by other insurance...

Code of Federal Regulations, 2012 CFR

2012-10-01

... insurance affordability program. (b) Provision of CHIP for individuals found eligible for CHIP by another insurance affordability program. If a State accepts final determinations of CHIP eligibility made by another... electronic account containing the determination of CHIP eligibility; and (2) Comply with the provisions of...

42 CFR 457.348 - Determinations of Children's Health Insurance Program eligibility by other insurance...

Code of Federal Regulations, 2014 CFR

2014-10-01

... insurance affordability program. (b) Provision of CHIP for individuals found eligible for CHIP by another insurance affordability program. If a State accepts final determinations of CHIP eligibility made by another... electronic account containing the determination of CHIP eligibility; and (2) Comply with the provisions of...