Modeling and simulation of floating gate nanocrystal FET devices and circuits

NASA Astrophysics Data System (ADS)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to nanocrystal charge has a strong effect on the memory characteristics. Also, the programming operation of the memory cell has been investigated. The tunneling rate from quantum well channel to quantum dot (nanocrystal) gate is calculated. The calculations include various memory parameters, wavefunctions, and energies of quantum well channel and quantum dot gate. The use of floating gate nanocrystal memory as a transistor with a programmable threshold voltage has been demonstrated. The incorporation of FG-NCFETs to design programmable integrated circuit building blocks has been discussed. This includes the design of programmable current and voltage reference circuits. Finally, we demonstrated the design of tunable gain op-amp incorporating FG-NCFETs. Programmable integrated circuit building blocks can be used in intelligent analog and digital systems.

Improvements of low-detection-limit filter-free fluorescence sensor developed by charge accumulation operation

NASA Astrophysics Data System (ADS)

Tanaka, Kiyotsugu; Choi, Yong Joon; Moriwaki, Yu; Hizawa, Takeshi; Iwata, Tatsuya; Dasai, Fumihiro; Kimura, Yasuyuki; Takahashi, Kazuhiro; Sawada, Kazuaki

2017-04-01

We developed a low-detection-limit filter-free fluorescence sensor by a charge accumulation technique. For charge accumulation, a floating diffusion amplifier (FDA), which included a floating diffusion capacitor, a transfer gate, and a source follower circuit, was used. To integrate CMOS circuits with the filter-free fluorescence sensor, we adopted a triple-well process to isolate transistors from the sensor on a single chip. We detected 0.1 nW fluorescence under the illumination of excitation light by 1.5 ms accumulation, which was one order of magnitude greater than that of a previous current detection sensor.

Ambipolar nonvolatile memory based on a quantum-dot transistor with a nanoscale floating gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Che, Yongli; Zhang, Yating, E-mail: yating@tju.edu.cn; Song, Xiaoxian

2016-07-04

Using only solution processing methods, we developed ambipolar quantum-dot (QD) transistor floating-gate memory (FGM) that uses Au nanoparticles as a floating gate. Because of the bipolarity of the active channel of PbSe QDs, the memory could easily trap holes or electrons in the floating gate by programming/erasing (P/E) operations, which could shift the threshold voltage both up and down. As a result, the memory exhibited good programmable memory characteristics: a large memory window (ΔV{sub th} ∼ 15 V) and a long retention time (>10{sup 5 }s). The magnitude of ΔV{sub th} depended on both P/E voltages and the bias voltage (V{sub DS}): ΔV{sub th}more » was a cubic function to V{sub P/E} and linearly depended on V{sub DS}. Therefore, this FGM based on a QD transistor is a promising alternative to its inorganic counterparts owing to its advantages of bipolarity, high mobility, low cost, and large-area production.« less

Parallel-Processing CMOS Circuitry for M-QAM and 8PSK TCM

NASA Technical Reports Server (NTRS)

Gray, Andrew; Lee, Dennis; Hoy, Scott; Fisher, Dave; Fong, Wai; Ghuman, Parminder

2009-01-01

There has been some additional development of parts reported in "Multi-Modulator for Bandwidth-Efficient Communication" (NPO-40807), NASA Tech Briefs, Vol. 32, No. 6 (June 2009), page 34. The focus was on 1) The generation of M-order quadrature amplitude modulation (M-QAM) and octonary-phase-shift-keying, trellis-coded modulation (8PSK TCM), 2) The use of square-root raised-cosine pulse-shaping filters, 3) A parallel-processing architecture that enables low-speed [complementary metal oxide/semiconductor (CMOS)] circuitry to perform the coding, modulation, and pulse-shaping computations at a high rate; and 4) Implementation of the architecture in a CMOS field-programmable gate array.

High-speed sorting of grains by color and surface texture

USDA-ARS?s Scientific Manuscript database

A high-speed, low-cost, image-based sorting device was developed to detect and separate grains with different colors/textures. The device directly combines a complementary metal–oxide–semiconductor (CMOS) color image sensor with a field-programmable gate array (FPGA) that was programmed to execute ...

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

PubMed

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

Hardware-based image processing for high-speed inspection of grains

USDA-ARS?s Scientific Manuscript database

A high-speed, low-cost, image-based sorting device was developed to detect and separate grains with slight color differences and small defects on grains The device directly combines a complementary metal–oxide–semiconductor (CMOS) color image sensor with a field-programmable gate array (FPGA) which...

Floating-Point Units and Algorithms for field-programmable gate arrays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Underwood, Keith D.; Hemmert, K. Scott

2005-11-01

The software that we are attempting to copyright is a package of floating-point unit descriptions and example algorithm implementations using those units for use in FPGAs. The floating point units are best-in-class implementations of add, multiply, divide, and square root floating-point operations. The algorithm implementations are sample (not highly flexible) implementations of FFT, matrix multiply, matrix vector multiply, and dot product. Together, one could think of the collection as an implementation of parts of the BLAS library or something similar to the FFTW packages (without the flexibility) for FPGAs. Results from this work has been published multiple times and wemore » are working on a publication to discuss the techniques we use to implement the floating-point units, For some more background, FPGAS are programmable hardware. "Programs" for this hardware are typically created using a hardware description language (examples include Verilog, VHDL, and JHDL). Our floating-point unit descriptions are written in JHDL, which allows them to include placement constraints that make them highly optimized relative to some other implementations of floating-point units. Many vendors (Nallatech from the UK, SRC Computers in the US) have similar implementations, but our implementations seem to be somewhat higher performance. Our algorithm implementations are written in VHDL and models of the floating-point units are provided in VHDL as well. FPGA "programs" make multiple "calls" (hardware instantiations) to libraries of intellectual property (IP), such as the floating-point unit library described here. These programs are then compiled using a tool called a synthesizer (such as a tool from Synplicity, Inc.). The compiled file is a netlist of gates and flip-flops. This netlist is then mapped to a particular type of FPGA by a mapper and then a place- and-route tool. These tools assign the gates in the netlist to specific locations on the specific type of FPGA chip used and constructs the required routes between them. The result is a "bitstream" that is analogous to a compiled binary. The bitstream is loaded into the FPGA to create a specific hardware configuration.« less

Single event upset susceptibilities of latchup immune CMOS process programmable gate arrays

NASA Astrophysics Data System (ADS)

Koga, R.; Crain, W. R.; Crawford, K. B.; Hansel, S. J.; Lau, D. D.; Tsubota, T. K.

Single event upsets (SEU) and latchup susceptibilities of complementary metal oxide semiconductor programmable gate arrays (CMOS PPGA's) were measured at the Lawrence Berkeley Laboratory 88-in. cyclotron facility with Xe (603 MeV), Cu (290 MeV), and Ar (180 MeV) ion beams. The PPGA devices tested were those which may be used in space. Most of the SEU measurements were taken with a newly constructed tester called the Bus Access Storage and Comparison System (BASACS) operating via a Macintosh II computer. When BASACS finds that an output does not match a prerecorded pattern, the state of all outputs, position in the test cycle, and other necessary information is transmitted and stored in the Macintosh. The upset rate was kept between 1 and 3 per second. After a sufficient number of errors are stored, the test is stopped and the total fluence of particles and total errors are recorded. The device power supply current was closely monitored to check for occurrence of latchup. Results of the tests are presented, indicating that some of the PPGA's are good candidates for selected space applications.

Neural dynamics in reconfigurable silicon.

PubMed

Basu, A; Ramakrishnan, S; Petre, C; Koziol, S; Brink, S; Hasler, P E

2010-10-01

A neuromorphic analog chip is presented that is capable of implementing massively parallel neural computations while retaining the programmability of digital systems. We show measurements from neurons with Hopf bifurcations and integrate and fire neurons, excitatory and inhibitory synapses, passive dendrite cables, coupled spiking neurons, and central pattern generators implemented on the chip. This chip provides a platform for not only simulating detailed neuron dynamics but also uses the same to interface with actual cells in applications such as a dynamic clamp. There are 28 computational analog blocks (CAB), each consisting of ion channels with tunable parameters, synapses, winner-take-all elements, current sources, transconductance amplifiers, and capacitors. There are four other CABs which have programmable bias generators. The programmability is achieved using floating gate transistors with on-chip programming control. The switch matrix for interconnecting the components in CABs also consists of floating-gate transistors. Emphasis is placed on replicating the detailed dynamics of computational neural models. Massive computational area efficiency is obtained by using the reconfigurable interconnect as synaptic weights, resulting in more than 50 000 possible 9-b accurate synapses in 9 mm(2).

Field programmable gate array-assigned complex-valued computation and its limits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bernard-Schwarz, Maria, E-mail: maria.bernardschwarz@ni.com; Institute of Applied Physics, TU Wien, Wiedner Hauptstrasse 8, 1040 Wien; Zwick, Wolfgang

We discuss how leveraging Field Programmable Gate Array (FPGA) technology as part of a high performance computing platform reduces latency to meet the demanding real time constraints of a quantum optics simulation. Implementations of complex-valued operations using fixed point numeric on a Virtex-5 FPGA compare favorably to more conventional solutions on a central processing unit. Our investigation explores the performance of multiple fixed point options along with a traditional 64 bits floating point version. With this information, the lowest execution times can be estimated. Relative error is examined to ensure simulation accuracy is maintained.

CMOS Image Sensor Using SOI-MOS/Photodiode Composite Photodetector Device

NASA Astrophysics Data System (ADS)

Uryu, Yuko; Asano, Tanemasa

2002-04-01

A new photodetector device composed of a lateral junction photodiode and a metal-oxide-semiconductor field-effect-transistor (MOSFET), in which the output of the diode is fed through the body of the MOSFET, has been investigated. It is shown that the silicon-on-insulator (SOI)-MOSFET amplifies the junction photodiode current due to the lateral bipolar action. It is also shown that the presence of the electrically floating gate enhances the current amplification factor of the SOI-MOSFET. The output current of this composite device linearly responds by four orders of illumination intensity. As an application of the composite device, a complementary-metal-oxide-semiconductor (CMOS) line sensor incorporating the composite device is fabricated and its operation is demonstrated. The output signal of the line sensor using the composite device was two times larger than that using the lateral photodiode.

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array—Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

PubMed Central

Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-01-01

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array—application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384. PMID:28672813

A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

PubMed

Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

2017-06-24

With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Depletion type floating gate p-channel MOS transistor for recording action potentials generated by cultured neurons.

PubMed

Cohen, Ariel; Spira, Micha E; Yitshaik, Shlomo; Borghs, Gustaaf; Shwartzglass, Ofer; Shappir, Joseph

2004-07-15

We report the realization of electrical coupling between neurons and depletion type floating gate (FG) p-channel MOS transistors. The devices were realized in a shortened 0.5 microm CMOS technology. Increased boron implant dose was used to form the depletion type devices. Post-CMOS processing steps were added to expose the devices sensing area. The neurons are coupled to the polycrystalline silicon (PS) FG through 420A thermal oxide in an area which is located over the thick field oxide away from the transistor. The combination of coupling area pad having a diameter of 10 or 15 microm and sensing transistor with W/L of 50/0.5 microm results in capacitive coupling ratio of the neuron signal of about 0.5 together with relatively large transistor transconductance. The combination of the FG structure with a depletion type device, leads to the following advantages. (a) No need for dc bias between the solution in which the neurons are cultured and the transistor with expected consequences to the neuron as well as the silicon die durability. (b) The sensing area of the neuron activity is separated from the active area of the transistor. Thus, it is possible to design the sensing area and the channel area separately. (c) The channel area, which is the most sensitive part of the transistor, can be insulated and shielded from the ionic solution in which the neurons are cultured. (d) There is an option to add a switching transistor to the FG and use the FG also for the neuron stimulation.

A clocked high-pass-filter-based offset cancellation technique for high-gain biomedical amplifiers

NASA Astrophysics Data System (ADS)

Pal, Dipankar; Goswami, Manish

2010-05-01

In this article, a simple offset cancellation technique based on a clocked high-pass filter with extremely low output offset is presented. The configuration uses the on-resistance of a complementary metal oxide semiconductor (CMOS) transmission gate (X-gate) and tunes the lower 3-dB cut-off frequency with a matched pair of floating capacitors. The results compare favourably with the more complex auto-zeroing and chopper stabilisation techniques of offset cancellation in terms of power dissipation, component count and bandwidth, while reporting inferior output noise performance. The design is suitable for use in biomedical amplifier systems for applications such as ENG-recording. The system is simulated in Spectre Cadence 5.1.41 using 0.6 μm CMOS technology and the total block gain is ∼83.0 dB while the phase error is <5°. The power consumption is 10.2 mW and the output offset obtained for an input monotone signal of 5 μVpp is 1.28 μV. The input-referred root mean square noise voltage between 1 and 5 kHz is 26.32 nV/√Hz.

Memory operations in Au nanoparticle single-electron transistors with floating gate electrodes

NASA Astrophysics Data System (ADS)

Azuma, Yasuo; Sakamoto, Masanori; Teranishi, Toshiharu; Majima, Yutaka

2016-11-01

Floating gate memory operations are demonstrated in a single-electron transistor (SET) fabricated by a chemical assembly using the Au nanogap electrodes and the chemisorbed Au nanoparticles. By applying pulse voltages to the control gate, phase shifts were clearly and stably observed both in the Coulomb oscillations and in the Coulomb diamonds. Writing and erasing operations on the floating gate memory were reproducibly observed, and the charges on the floating gate electrodes were maintained for at least 12 h. By considering the capacitance of the floating gate electrode, the number of electrons in the floating gate electrode was estimated as 260. Owing to the stability of the fabricated SET, these writing and erasing operations on the floating gate memory can be applied to reconfigurable SET circuits fabricated by a chemically assembled technique.

Nanoeletromechanical switch and logic circuits formed therefrom

DOEpatents

Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM

2010-05-18

A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.

Extraction of the gate capacitance coupling coefficient in floating gate non-volatile memories: Statistical study of the effect of mismatching between floating gate memory and reference transistor in dummy cell extraction methods

NASA Astrophysics Data System (ADS)

Rafhay, Quentin; Beug, M. Florian; Duane, Russell

2007-04-01

This paper presents an experimental comparison of dummy cell extraction methods of the gate capacitance coupling coefficient for floating gate non-volatile memory structures from different geometries and technologies. These results show the significant influence of mismatching floating gate devices and reference transistors on the extraction of the gate capacitance coupling coefficient. In addition, it demonstrates the accuracy of the new bulk bias dummy cell extraction method and the importance of the β function, introduced recently in [Duane R, Beug F, Mathewson A. Novel capacitance coupling coefficient measurement methodology for floating gate non-volatile memory devices. IEEE Electr Dev Lett 2005;26(7):507-9], to determine matching pairs of floating gate memory and reference transistor.

Single phase dynamic CMOS PLA using charge sharing technique

NASA Technical Reports Server (NTRS)

Dhong, Y. B.; Tsang, C. P.

1991-01-01

A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology. [Dual Injector Floating-gate MOS

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1977-01-01

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

Effects of floating gate structures on the two-dimensional electron gas density and electron mobility in AlGaN/AlN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Zhao, Jingtao; Zhao, Zhenguo; Chen, Zidong; Lin, Zhaojun; Xu, Fukai

2017-12-01

In this study, we have investigated the electrical properties of the AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs) with floating gate structures using the measured capacitancevoltage (C-V) and current-voltage (I-V) characteristics. It is found that the two-dimensional electron gas (2DEG) density under the central gate cannot be changed by the floating gate structures. However, the floating gate structures can cause the strain variation in the barrier layer, which lead to the non-uniform distribution of the polarization charges, then induce a polarization Coulomb field and scatter the 2DEG. More floating gate structures and closer distance between the floating gates and the central gate will result in stronger scattering effect of the 2DEG.

Evaluation of Magnetoresistive RAM for Space Applications

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2014-01-01

Magnetoresistive random-access memory (MRAM) is a non-volatile memory that exploits electronic spin, rather than charge, to store data. Instead of moving charge on and off a floating gate to alter the threshold voltage of a CMOS transistor (creating different bit states), MRAM uses magnetic fields to flip the polarization of a ferromagnetic material thus switching its resistance and bit state. These polarized states are immune to radiation-induced upset, thus making MRAM very attractive for space application. These magnetic memory elements also have infinite data retention and erase/program endurance. Presented here are results of reliability testing of two space-qualified MRAM products from Aeroflex and Honeywell.

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2005-01-01

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

A CMOS Pressure Sensor Tag Chip for Passive Wireless Applications

PubMed Central

Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

2015-01-01

This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of −20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation. PMID:25806868

A CMOS pressure sensor tag chip for passive wireless applications.

PubMed

Deng, Fangming; He, Yigang; Li, Bing; Zuo, Lei; Wu, Xiang; Fu, Zhihui

2015-03-23

This paper presents a novel monolithic pressure sensor tag for passive wireless applications. The proposed pressure sensor tag is based on an ultra-high frequency RFID system. The pressure sensor element is implemented in the 0.18 µm CMOS process and the membrane gap is formed by sacrificial layer release, resulting in a sensitivity of 1.2 fF/kPa within the range from 0 to 600 kPa. A three-stage rectifier adopts a chain of auxiliary floating rectifier cells to boost the gate voltage of the switching transistors, resulting in a power conversion efficiency of 53% at the low input power of -20 dBm. The capacitive sensor interface, using phase-locked loop archietcture, employs fully-digital blocks, which results in a 7.4 bits resolution and 0.8 µW power dissipation at 0.8 V supply voltage. The proposed passive wireless pressure sensor tag costs a total 3.2 µW power dissipation.

Silicon-gate CMOS/SOS processing

NASA Technical Reports Server (NTRS)

Ramondetta, P.

1979-01-01

Major silicon-gate CMOS/SOS processes are described. Sapphire substrate preparation is also discussed, as well as the following process variations: (1) the double epi process; and (2) ion implantation.

An LMS Programming Scheme and Floating-Gate Technology Enabled Trimmer-Less and Low Voltage Flame Detection Sensor.

PubMed

Iglesias-Rojas, Juan Carlos; Gomez-Castañeda, Felipe; Moreno-Cadenas, Jose Antonio

2017-06-14

In this paper, a Least Mean Square (LMS) programming scheme is used to set the offset voltage of two operational amplifiers that were built using floating-gate transistors, enabling a 0.95 V RMS trimmer-less flame detection sensor. The programming scheme is capable of setting the offset voltage over a wide range of values by means of electron injection. The flame detection sensor consists of two programmable offset operational amplifiers; the first amplifier serves as a 26 μV offset voltage follower, whereas the second amplifier acts as a programmable trimmer-less voltage comparator. Both amplifiers form the proposed sensor, whose principle of functionality is based on the detection of the electrical changes produced by the flame ionization. The experimental results show that it is possible to measure the presence of a flame accurately after programming the amplifiers with a maximum of 35 LMS-algorithm iterations. Current commercial flame detectors are mainly used in absorption refrigerators and large industrial gas heaters, where a high voltage AC source and several mechanical trimmings are used in order to accurately measure the presence of the flame.

An LMS Programming Scheme and Floating-Gate Technology Enabled Trimmer-Less and Low Voltage Flame Detection Sensor

PubMed Central

Iglesias-Rojas, Juan Carlos; Gomez-Castañeda, Felipe; Moreno-Cadenas, Jose Antonio

2017-01-01

In this paper, a Least Mean Square (LMS) programming scheme is used to set the offset voltage of two operational amplifiers that were built using floating-gate transistors, enabling a 0.95 VRMS trimmer-less flame detection sensor. The programming scheme is capable of setting the offset voltage over a wide range of values by means of electron injection. The flame detection sensor consists of two programmable offset operational amplifiers; the first amplifier serves as a 26 μV offset voltage follower, whereas the second amplifier acts as a programmable trimmer-less voltage comparator. Both amplifiers form the proposed sensor, whose principle of functionality is based on the detection of the electrical changes produced by the flame ionization. The experimental results show that it is possible to measure the presence of a flame accurately after programming the amplifiers with a maximum of 35 LMS-algorithm iterations. Current commercial flame detectors are mainly used in absorption refrigerators and large industrial gas heaters, where a high voltage AC source and several mechanical trimmings are used in order to accurately measure the presence of the flame. PMID:28613250

Investigation of field induced trapping on floating gates

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1975-01-01

The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

NASA Astrophysics Data System (ADS)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Highly sensitive and area-efficient CMOS image sensor using a PMOSFET-type photodetector with a built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Kim, Kyoung-Do; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2007-02-01

In this paper, a new CMOS image sensor is presented, which uses a PMOSFET-type photodetector with a transfer gate that has a high and variable sensitivity. The proposed CMOS image sensor has been fabricated using a 0.35 μm 2-poly 4- metal standard CMOS technology and is composed of a 256 × 256 array of 7.05 × 7.10 μm pixels. The unit pixel has a configuration of a pseudo 3-transistor active pixel sensor (APS) with the PMOSFET-type photodetector with a transfer gate, which has a function of conventional 4-transistor APS. The generated photocurrent is controlled by the transfer gate of the PMOSFET-type photodetector. The maximum responsivity of the photodetector is larger than 1.0 × 10 3 A/W without any optical lens. Fabricated 256 × 256 CMOS image sensor exhibits a good response to low-level illumination as low as 5 lux.

A new CMOS SiGeC avalanche photo-diode pixel for IR sensing

NASA Astrophysics Data System (ADS)

Augusto, Carlos; Forester, Lynn; Diniz, Pedro C.

2009-05-01

Near-infra-red sensing with silicon is limited by the bandgap of silicon, corresponding to a maximum wavelength of absorption of 1.1 μm. A new type of CMOS sensor is presented, which uses a SiGeC epitaxial film in conjunction with novel device architecture to extend absorption into the infra-red. The SiGeC film composition and thickness determine the spectrum of absorption; in particular for SiGeC superlattices, the layer ordering to create pseudo direct bandgaps is the critical parameter. In this new device architecture, the p-type SiGeC film is grown on an active region surrounded by STI, linked to the S/D region of an adjacent NMOS, under the STI by a floating N-Well. On a n-type active, a P-I-N device is formed, and on a p-type active, a P-I-P device is formed, each sensing different regions of the spectrum. The SiGeC films can be biased for avalanche operation, as the required vertical electric field is confined to the region near the heterojunction interface, thereby not affecting the gate oxide of the adjacent NMOS. With suitable heterojunction and doping profiles, the avalanche region can also be bandgap engineered, allowing for avalanche breakdown voltages that are compatible with CMOS devices.

A fail-safe CMOS logic gate

NASA Technical Reports Server (NTRS)

Bobin, V.; Whitaker, S.

1990-01-01

This paper reports a design technique to make Complex CMOS Gates fail-safe for a class of faults. Two classes of faults are defined. The fail-safe design presented has limited fault-tolerance capability. Multiple faults are also covered.

Design rules for RCA self-aligned silicon-gate CMOS/SOS process

NASA Technical Reports Server (NTRS)

1977-01-01

The CMOS/SOS design rules prepared by the RCA Solid State Technology Center (SSTC) are described. These rules specify the spacing and width requirements for each of the six design levels, the seventh level being used to define openings in the passivation level. An associated report, entitled Silicon-Gate CMOS/SOS Processing, provides further insight into the usage of these rules.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Dielectrophoresis-Assisted Integration of 1024 Carbon Nanotube Sensors into a CMOS Microsystem.

PubMed

Seichepine, Florent; Rothe, Jörg; Dudina, Alexandra; Hierlemann, Andreas; Frey, Urs

2017-05-01

Carbon-nanotube (CNT)-based sensors offer the potential to detect single-molecule events and picomolar analyte concentrations. An important step toward applications of such nanosensors is their integration in large arrays. The availability of large arrays would enable multiplexed and parallel sensing, and the simultaneously obtained sensor signals would facilitate statistical analysis. A reliable method to fabricate an array of 1024 CNT-based sensors on a fully processed complementary-metal-oxide-semiconductor microsystem is presented. A high-yield process for the deposition of CNTs from a suspension by means of liquid-coupled floating-electrode dielectrophoresis (DEP), which yielded 80% of the sensor devices featuring between one and five CNTs, is developed. The mechanism of floating-electrode DEP on full arrays and individual devices to understand its self-limiting behavior is studied. The resistance distributions across the array of CNT devices with respect to different DEP parameters are characterized. The CNT devices are then operated as liquid-gated CNT field-effect-transistors (LG-CNTFET) in liquid environment. Current dependency to the gate voltage of up to two orders of magnitude is recorded. Finally, the sensors are validated by studying the pH dependency of the LG-CNTFET conductance and it is demonstrated that 73% of the CNT sensors of a given microsystem show a resistance decrease upon increasing the pH value. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Non-Faradaic Electrochemical Detection of Exocytosis from Mast and Chromaffin Cells Using Floating-Gate MOS Transistors.

PubMed

Jayant, Krishna; Singhai, Amit; Cao, Yingqiu; Phelps, Joshua B; Lindau, Manfred; Holowka, David A; Baird, Barbara A; Kan, Edwin C

2015-12-21

We present non-faradaic electrochemical recordings of exocytosis from populations of mast and chromaffin cells using chemoreceptive neuron MOS (CνMOS) transistors. In comparison to previous cell-FET-biosensors, the CνMOS features control (CG), sensing (SG) and floating gates (FG), allows the quiescent point to be independently controlled, is CMOS compatible and physically isolates the transistor channel from the electrolyte for stable long-term recordings. We measured exocytosis from RBL-2H3 mast cells sensitized by IgE (bound to high-affinity surface receptors FcεRI) and stimulated using the antigen DNP-BSA. Quasi-static I-V measurements reflected a slow shift in surface potential () which was dependent on extracellular calcium ([Ca]o) and buffer strength, which suggests sensitivity to protons released during exocytosis. Fluorescent imaging of dextran-labeled vesicle release showed evidence of a similar time course, while un-sensitized cells showed no response to stimulation. Transient recordings revealed fluctuations with a rapid rise and slow decay. Chromaffin cells stimulated with high KCl showed both slow shifts and extracellular action potentials exhibiting biphasic and inverted capacitive waveforms, indicative of varying ion-channel distributions across the cell-transistor junction. Our approach presents a facile method to simultaneously monitor exocytosis and ion channel activity with high temporal sensitivity without the need for redox chemistry.

Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

NASA Astrophysics Data System (ADS)

Hong, Augustin Jinwoo

Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

Non-Faradaic Electrochemical Detection of Exocytosis from Mast and Chromaffin Cells Using Floating-Gate MOS Transistors

PubMed Central

Jayant, Krishna; Singhai, Amit; Cao, Yingqiu; Phelps, Joshua B.; Lindau, Manfred; Holowka, David A.; Baird, Barbara A.; Kan, Edwin C.

2015-01-01

We present non-faradaic electrochemical recordings of exocytosis from populations of mast and chromaffin cells using chemoreceptive neuron MOS (CνMOS) transistors. In comparison to previous cell-FET-biosensors, the CνMOS features control (CG), sensing (SG) and floating gates (FG), allows the quiescent point to be independently controlled, is CMOS compatible and physically isolates the transistor channel from the electrolyte for stable long-term recordings. We measured exocytosis from RBL-2H3 mast cells sensitized by IgE (bound to high-affinity surface receptors FcεRI) and stimulated using the antigen DNP-BSA. Quasi-static I-V measurements reflected a slow shift in surface potential () which was dependent on extracellular calcium ([Ca]o) and buffer strength, which suggests sensitivity to protons released during exocytosis. Fluorescent imaging of dextran-labeled vesicle release showed evidence of a similar time course, while un-sensitized cells showed no response to stimulation. Transient recordings revealed fluctuations with a rapid rise and slow decay. Chromaffin cells stimulated with high KCl showed both slow shifts and extracellular action potentials exhibiting biphasic and inverted capacitive waveforms, indicative of varying ion-channel distributions across the cell-transistor junction. Our approach presents a facile method to simultaneously monitor exocytosis and ion channel activity with high temporal sensitivity without the need for redox chemistry. PMID:26686301

Configurable hardware integrate and fire neurons for sparse approximation.

PubMed

Shapero, Samuel; Rozell, Christopher; Hasler, Paul

2013-09-01

Sparse approximation is an important optimization problem in signal and image processing applications. A Hopfield-Network-like system of integrate and fire (IF) neurons is proposed as a solution, using the Locally Competitive Algorithm (LCA) to solve an overcomplete L1 sparse approximation problem. A scalable system architecture is described, including IF neurons with a nonlinear firing function, and current-based synapses to provide linear computation. A network of 18 neurons with 12 inputs is implemented on the RASP 2.9v chip, a Field Programmable Analog Array (FPAA) with directly programmable floating gate elements. Said system uses over 1400 floating gates, the largest system programmed on a FPAA to date. The circuit successfully reproduced the outputs of a digital optimization program, converging to within 4.8% RMS, and an objective cost only 1.7% higher on average. The active circuit consumed 559 μA of current at 2.4 V and converges on solutions in 25 μs, with measurement of the converged spike rate taking an additional 1 ms. Extrapolating the scaling trends to a N=1000 node system, the spiking LCA compares favorably with state-of-the-art digital solutions, and analog solutions using a non-spiking approach. Copyright © 2013 Elsevier Ltd. All rights reserved.

A 0.18 μm CMOS low-power radiation sensor for asynchronous event-driven UWB wireless transmission

NASA Astrophysics Data System (ADS)

Bastianini, S.; Crepaldi, M.; Demarchi, D.; Gabrielli, A.; Lolli, M.; Margotti, A.; Villani, G.; Zhang, Z.; Zoccoli, G.

2013-12-01

The paper describes the design of a readout element, proposed as a radiation monitor, which implements an embedded sensor based on a floating-gate transistor. The paper shows the design of a microelectronic circuit composed of a sensor, an oscillator, a modulator, a transmitter and an integrated antenna. A prototype chip has recently been fabricated and tested exploiting a commercial 180 nm, four metal CMOS technology. Simulation results of the entire behavior of the circuit before submission are presented along with some measurements of the actual chip response. In addition, preliminary tests of the performance of the Ultra-Wide Band transmission via the integrated antenna are summarized. As the complete chip prototype area is less than 1 mm2, the chip fits a large variety of applications, from spot radiation monitoring systems in medicine to punctual measurements of radiation level in High-Energy Physics experiments. A sensitivity of 1 mV/rad was estimated within an absorbed dose range up to 10 krad and a total power consumption of about 165 μW.

Radiation Issues and Applications of Floating Gate Memories

NASA Technical Reports Server (NTRS)

Scheick, L. Z.; Nguyen, D. N.

2000-01-01

The radiation effects that affect various systems that comprise floating gate memories are presented. The wear-out degradation results of unirradiated flash memories are compared to irradiated flash memories. The procedure analyzes the failure to write and erase caused by wear-out and degradation of internal charge pump circuits. A method is described for characterizing the radiation effects of the floating gate itself. The rate dependence, stopping power dependence, SEU susceptibility and applications of floating gate in radiation environment are presented. The ramifications for dosimetry and cell failure are discussed as well as for the long term use aspects of non-volatile memories.

A SPAD-based 3D imager with in-pixel TDC for 145ps-accuracy ToF measurement

NASA Astrophysics Data System (ADS)

Vornicu, I.; Carmona-Galán, R.; Rodríguez-Vázquez, Á.

2015-03-01

The design and measurements of a CMOS 64 × 64 Single-Photon Avalanche-Diode (SPAD) array with in-pixel Time-to-Digital Converter (TDC) are presented. This paper thoroughly describes the imager at architectural and circuit level with particular emphasis on the characterization of the SPAD-detector ensemble. It is aimed to 2D imaging and 3D image reconstruction in low light environments. It has been fabricated in a standard 0.18μm CMOS process, i. e. without high voltage or low noise features. In these circumstances, we are facing a high number of dark counts and low photon detection efficiency. Several techniques have been applied to ensure proper functionality, namely: i) time-gated SPAD front-end with fast active-quenching/recharge circuit featuring tunable dead-time, ii) reverse start-stop scheme, iii) programmable time resolution of the TDC based on a novel pseudo-differential voltage controlled ring oscillator with fast start-up, iv) a global calibration scheme against temperature and process variation. Measurements results of individual SPAD-TDC ensemble jitter, array uniformity and time resolution programmability are also provided.

Operation and biasing for single device equivalent to CMOS

DOEpatents

Welch, James D.

2001-01-01

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of field induced carriers. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents. Operation of the gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems under typical bias schemes is described, and simple demonstrative five mask fabrication procedures for the inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing

PubMed Central

Bravo, Ignacio; Baliñas, Javier; Gardel, Alfredo; Lázaro, José L.; Espinosa, Felipe; García, Jorge

2011-01-01

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

A semi-floating gate memory based on van der Waals heterostructures for quasi-non-volatile applications

NASA Astrophysics Data System (ADS)

Liu, Chunsen; Yan, Xiao; Song, Xiongfei; Ding, Shijin; Zhang, David Wei; Zhou, Peng

2018-05-01

As conventional circuits based on field-effect transistors are approaching their physical limits due to quantum phenomena, semi-floating gate transistors have emerged as an alternative ultrafast and silicon-compatible technology. Here, we show a quasi-non-volatile memory featuring a semi-floating gate architecture with band-engineered van der Waals heterostructures. This two-dimensional semi-floating gate memory demonstrates 156 times longer refresh time with respect to that of dynamic random access memory and ultrahigh-speed writing operations on nanosecond timescales. The semi-floating gate architecture greatly enhances the writing operation performance and is approximately 106 times faster than other memories based on two-dimensional materials. The demonstrated characteristics suggest that the quasi-non-volatile memory has the potential to bridge the gap between volatile and non-volatile memory technologies and decrease the power consumption required for frequent refresh operations, enabling a high-speed and low-power random access memory.

Efficient design of CMOS TSC checkers

NASA Technical Reports Server (NTRS)

Biddappa, Anita; Shamanna, Manjunath K.; Maki, Gary; Whitaker, Sterling

1990-01-01

This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes.

Ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory

NASA Astrophysics Data System (ADS)

Han, Jinhua; Wang, Wei; Ying, Jun; Xie, Wenfa

2014-01-01

An ambipolar organic thin-film transistor-based nano-floating-gate nonvolatile memory was demonstrated, with discrete distributed gold nanoparticles, tetratetracontane (TTC), pentacene as the floating-gate layer, tunneling layer, and active layer, respectively. The electron traps at the TTC/pentacene interface were significantly suppressed, which resulted in an ambipolar operation in present memory. As both electrons and holes were supplied in the channel and trapped in the floating-gate by programming/erasing operations, respectively, i.e., one type of charge carriers was used to overwrite the other, trapped, one, a large memory window, extending on both sides of the initial threshold voltage, was realized.

Fault tolerant system based on IDDQ testing

NASA Astrophysics Data System (ADS)

Guibane, Badi; Hamdi, Belgacem; Mtibaa, Abdellatif; Bensalem, Brahim

2018-06-01

Offline test is essential to ensure good manufacturing quality. However, for permanent or transient faults that occur during the use of the integrated circuit in an application, an online integrated test is needed as well. This procedure should ensure the detection and possibly the correction or the masking of these faults. This requirement of self-correction is sometimes necessary, especially in critical applications that require high security such as automotive, space or biomedical applications. We propose a fault-tolerant design for analogue and mixed-signal design complementary metal oxide (CMOS) circuits based on the quiescent current supply (IDDQ) testing. A defect can cause an increase in current consumption. IDDQ testing technique is based on the measurement of power supply current to distinguish between functional and failed circuits. The technique has been an effective testing method for detecting physical defects such as gate-oxide shorts, floating gates (open) and bridging defects in CMOS integrated circuits. An architecture called BICS (Built In Current Sensor) is used for monitoring the supply current (IDDQ) of the connected integrated circuit. If the measured current is not within the normal range, a defect is signalled and the system switches connection from the defective to a functional integrated circuit. The fault-tolerant technique is composed essentially by a double mirror built-in current sensor, allowing the detection of abnormal current consumption and blocks allowing the connection to redundant circuits, if a defect occurs. Spices simulations are performed to valid the proposed design.

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

NASA Astrophysics Data System (ADS)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Solution-processed nanoparticle super-float-gated organic field-effect transistor as un-cooled ultraviolet and infrared photon counter.

PubMed

Yuan, Yongbo; Dong, Qingfeng; Yang, Bin; Guo, Fawen; Zhang, Qi; Han, Ming; Huang, Jinsong

2013-01-01

High sensitivity photodetectors in ultraviolet (UV) and infrared (IR) range have broad civilian and military applications. Here we report on an un-cooled solution-processed UV-IR photon counter based on modified organic field-effect transistors. This type of UV detectors have light absorbing zinc oxide nanoparticles (NPs) sandwiched between two gate dielectric layers as a floating gate. The photon-generated charges on the floating gate cause high resistance regions in the transistor channel and tune the source-drain output current. This "super-float-gating" mechanism enables very high sensitivity photodetectors with a minimum detectable ultraviolet light intensity of 2.6 photons/μm(2)s at room temperature as well as photon counting capability. Based on same mechansim, infrared photodetectors with lead sulfide NPs as light absorbing materials have also been demonstrated.

G(sup 4)FET Implementations of Some Logic Circuits

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

A Fully Reconfigurable Low-Noise Biopotential Sensing Amplifier With 1.96 Noise Efficiency Factor.

PubMed

Tzu-Yun Wang; Min-Rui Lai; Twigg, Christopher M; Sheng-Yu Peng

2014-06-01

A fully reconfigurable biopotential sensing amplifier utilizing floating-gate transistors is presented in this paper. By using the complementary differential pairs along with the current reuse technique, the theoretical limit for the noise efficiency factor of the proposed amplifier is below 1.5. Without consuming any extra power, floating-gate transistors are employed to program the low-frequency cutoff corner of the amplifier and to implement the common-mode feedback. A concept proving prototype chip was designed and fabricated in a 0.35 μm CMOS process occupying 0.17 mm (2) silicon area. With a supply voltage of 2.5 V, the measured midband gain is 40.7 dB and the measured input-referred noise is 2.8 μVrms. The chip was tested under several configurations with the amplifier bandwidth being programmed to 100 Hz, 1 kHz , and 10 kHz. The measured noise efficiency factors in these bandwidth settings are 1.96, 2.01, and 2.25, respectively, which are among the best numbers reported to date. The measured common-mode rejection and the supply rejection are above 70 dB . When the bandwidth is configured to be 10 kHz, the dynamic range measured at 1 kHz is 60 dB with total harmonic distortion less than 0.1%. The proposed amplifier is also demonstrated by recording electromyography (EMG), electrocardiography (ECG), electrooculography (EOG), and electroencephalography (EEG) signals from human bodies.

High-Speed Scanning Interferometer Using CMOS Image Sensor and FPGA Based on Multifrequency Phase-Tracking Detection

NASA Technical Reports Server (NTRS)

Ohara, Tetsuo

2012-01-01

A sub-aperture stitching optical interferometer can provide a cost-effective solution for an in situ metrology tool for large optics; however, the currently available technologies are not suitable for high-speed and real-time continuous scan. NanoWave s SPPE (Scanning Probe Position Encoder) has been proven to exhibit excellent stability and sub-nanometer precision with a large dynamic range. This same technology can transform many optical interferometers into real-time subnanometer precision tools with only minor modification. The proposed field-programmable gate array (FPGA) signal processing concept, coupled with a new-generation, high-speed, mega-pixel CMOS (complementary metal-oxide semiconductor) image sensor, enables high speed (>1 m/s) and real-time continuous surface profiling that is insensitive to variation of pixel sensitivity and/or optical transmission/reflection. This is especially useful for large optics surface profiling.

Semiconductor systems utilizing materials that form rectifying junctions in both N and P-type doping regions, whether metallurgically or field induced, and methods of use

DOEpatents

Welch, James D.

2000-01-01

Disclosed are semiconductor systems, such as integrated circuits utilizing Schotky barrier and/or diffused junction technology, which semiconductor systems incorporate material(s) that form rectifying junctions in both metallurgically and/or field induced N and P-type doping regions, and methods of their use. Disclosed are Schottky barrier based inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems and which can be operated as modulators, N and P-channel MOSFETS and CMOS formed therefrom, and (MOS) gate voltage controlled rectification direction and gate voltage controlled switching devices, and use of such material(s) to block parasitic current flow pathways. Simple demonstrative five mask fabrication procedures for inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to multiple device CMOS systems are also presented.

Electron lithography STAR design guidelines. Part 2: The design of a STAR for space applications

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Newman, W.

1982-01-01

The STAR design system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computr programs to place, route, and display designs implemented with cells from the library. Also described is the development of a radiation-hard array designed for the STAR system. The design is based on the CMOS silicon gate technology developed by SANDIA National Laboratories. The design rules used are given as well as the model parameters developed for the basic array element. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

An Intelligent Architecture Based on Field Programmable Gate Arrays Designed to Detect Moving Objects by Using Principal Component Analysis

PubMed Central

Bravo, Ignacio; Mazo, Manuel; Lázaro, José L.; Gardel, Alfredo; Jiménez, Pedro; Pizarro, Daniel

2010-01-01

This paper presents a complete implementation of the Principal Component Analysis (PCA) algorithm in Field Programmable Gate Array (FPGA) devices applied to high rate background segmentation of images. The classical sequential execution of different parts of the PCA algorithm has been parallelized. This parallelization has led to the specific development and implementation in hardware of the different stages of PCA, such as computation of the correlation matrix, matrix diagonalization using the Jacobi method and subspace projections of images. On the application side, the paper presents a motion detection algorithm, also entirely implemented on the FPGA, and based on the developed PCA core. This consists of dynamically thresholding the differences between the input image and the one obtained by expressing the input image using the PCA linear subspace previously obtained as a background model. The proposal achieves a high ratio of processed images (up to 120 frames per second) and high quality segmentation results, with a completely embedded and reliable hardware architecture based on commercial CMOS sensors and FPGA devices. PMID:22163406

An intelligent architecture based on Field Programmable Gate Arrays designed to detect moving objects by using Principal Component Analysis.

PubMed

Bravo, Ignacio; Mazo, Manuel; Lázaro, José L; Gardel, Alfredo; Jiménez, Pedro; Pizarro, Daniel

2010-01-01

This paper presents a complete implementation of the Principal Component Analysis (PCA) algorithm in Field Programmable Gate Array (FPGA) devices applied to high rate background segmentation of images. The classical sequential execution of different parts of the PCA algorithm has been parallelized. This parallelization has led to the specific development and implementation in hardware of the different stages of PCA, such as computation of the correlation matrix, matrix diagonalization using the Jacobi method and subspace projections of images. On the application side, the paper presents a motion detection algorithm, also entirely implemented on the FPGA, and based on the developed PCA core. This consists of dynamically thresholding the differences between the input image and the one obtained by expressing the input image using the PCA linear subspace previously obtained as a background model. The proposal achieves a high ratio of processed images (up to 120 frames per second) and high quality segmentation results, with a completely embedded and reliable hardware architecture based on commercial CMOS sensors and FPGA devices.

High-Performance Complementary Transistors and Medium-Scale Integrated Circuits Based on Carbon Nanotube Thin Films.

PubMed

Yang, Yingjun; Ding, Li; Han, Jie; Zhang, Zhiyong; Peng, Lian-Mao

2017-04-25

Solution-derived carbon nanotube (CNT) network films with high semiconducting purity are suitable materials for the wafer-scale fabrication of field-effect transistors (FETs) and integrated circuits (ICs). However, it is challenging to realize high-performance complementary metal-oxide semiconductor (CMOS) FETs with high yield and stability on such CNT network films, and this difficulty hinders the development of CNT-film-based ICs. In this work, we developed a doping-free process for the fabrication of CMOS FETs based on solution-processed CNT network films, in which the polarity of the FETs was controlled using Sc or Pd as the source/drain contacts to selectively inject carriers into the channels. The fabricated top-gated CMOS FETs showed high symmetry between the characteristics of n- and p-type devices and exhibited high-performance uniformity and excellent scalability down to a gate length of 1 μm. Many common types of CMOS ICs, including typical logic gates, sequential circuits, and arithmetic units, were constructed based on CNT films, and the fabricated ICs exhibited rail-to-rail outputs because of the high noise margin of CMOS circuits. In particular, 4-bit full adders consisting of 132 CMOS FETs were realized with 100% yield, thereby demonstrating that this CMOS technology shows the potential to advance the development of medium-scale CNT-network-film-based ICs.

Novel CMOS photosensor with a gate-body tied NMOSFET structure

NASA Astrophysics Data System (ADS)

Kook, Youn-Jae; Jeong, Jae-Hun; Park, Young-June; Min, Hong-Shick

2000-07-01

A novel CMOS photosensor with a gate-body tied NMOSFET structure realized in the triple is well presented. The photocurrent is amplified by the lateral and vertical BJT action, which results in two different output photocurrents, which can be used for different applications within a pixel. The lateral action results in the drain current with a higher sensitivity at low light intensity. And the vertical action results in the collector current with uniform responsivity over wider range of the light intensity. The proposed photosensor in compatible with CMOS circuits.

Novel Si-Ge-C Superlattices for More than Moore CMOS

DTIC Science & Technology

2016-03-31

diodes can be entirely formed by epitaxial growth, CMOS Active Pixel Sensors can be made with Fully-Depleted SOI CMOS . One important advantage of...a NMOS Transfer Gate (TG), which could be part of a 4T pixel APS. PPDs are preferred in CMOS image sensors for the ability of the pinning layer to...than Moore” with the creation of active photonic devices monolithically integrated with CMOS . Applications include Multispectral CMOS Image Sensors

Nonvolatile memory with Co-SiO2 core-shell nanocrystals as charge storage nodes in floating gate

NASA Astrophysics Data System (ADS)

Liu, Hai; Ferrer, Domingo A.; Ferdousi, Fahmida; Banerjee, Sanjay K.

2009-11-01

In this letter, we reported nanocrystal floating gate memory with Co-SiO2 core-shell nanocrystal charge storage nodes. By using a water-in-oil microemulsion scheme, Co-SiO2 core-shell nanocrystals were synthesized and closely packed to achieve high density matrix in the floating gate without aggregation. The insulator shell also can help to increase the thermal stability of the nanocrystal metal core during the fabrication process to improve memory performance.

Fault handling schemes in electronic systems with specific application to radiation tolerance and VLSI design

NASA Technical Reports Server (NTRS)

Attia, John Okyere

1993-01-01

Naturally occurring space radiation particles can produce transient and permanent changes in the electrical properties of electronic devices and systems. In this work, the transient radiation effects on DRAM and CMOS SRAM were considered. In addition, the effect of total ionizing dose radiation of the switching times of CMOS logic gates were investigated. Effects of transient radiation on the column and cell of MOS dynamic memory cell was simulated using SPICE. It was found that the critical charge of the bitline was higher than that of the cell. In addition, the critical charge of the combined cell-bitline was found to be dependent on the gate voltage of the access transistor. In addition, the effect of total ionizing dose radiation on the switching times of CMOS logic gate was obtained. The results of this work indicate that, the rise time of CMOS logic gates increases, while the fall time decreases with an increase in total ionizing dose radiation. Also, by increasing the size of the P-channel transistor with respect to that of the N-channel transistor, the propagation delay of CMOS logic gate can be made to decrease with, or be independent of an increase in total ionizing dose radiation. Furthermore, a method was developed for replacing polysilicon feedback resistance of SRAMs with a switched capacitor network. A switched capacitor SRAM was implemented using MOS Technology. The critical change of the switched capacitor SRAM has a very large critical charge. The results of this work indicate that switched capacitor SRAM is a viable alternative to SRAM with polysilicon feedback resistance.

RAD hard PROM design study

NASA Technical Reports Server (NTRS)

1981-01-01

The results of a preliminary study on the design of a radiation hardened fusible link programmable read-only memory (PROM) are presented. Various fuse technologies and the effects of radiation on MOS integrated circuits are surveyed. A set of design rules allowing the fabrication of a radiation hardened PROM using a Si-gate CMOS process is defined. A preliminary cell layout was completed and the programming concept defined. A block diagram is used to describe the circuit components required for a 4 K design. A design goal data sheet giving target values for the AC, DC, and radiation parameters of the circuit is presented.

Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

NASA Astrophysics Data System (ADS)

Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

2016-10-01

The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

Observation of ambipolar switching in a silver nanoparticle single-electron transistor with multiple molecular floating gates

NASA Astrophysics Data System (ADS)

Yamamoto, Makoto; Shinohara, Shuhei; Tamada, Kaoru; Ishii, Hisao; Noguchi, Yutaka

2016-03-01

Ambipolar switching behavior was observed in a silver nanoparticle (AgNP)-based single-electron transistor (SET) with tetra-tert-butyl copper phthalocyanine (ttbCuPc) as a molecular floating gate. Depending on the wavelength of the incident light, the stability diagram shifted to the negative and positive directions along the gate voltage axis. These results were explained by the photoinduced charging of ttbCuPc molecules in the vicinity of AgNPs. Moreover, multiple device states were induced by the light irradiation at a wavelength of 600 nm, suggesting that multiple ttbCuPc molecules individually worked as a floating gate.

A CMOS active pixel sensor for retinal stimulation

NASA Astrophysics Data System (ADS)

Prydderch, Mark L.; French, Marcus J.; Mathieson, Keith; Adams, Christopher; Gunning, Deborah; Laudanski, Jonathan; Morrison, James D.; Moodie, Alan R.; Sinclair, James

2006-02-01

Degenerative photoreceptor diseases, such as age-related macular degeneration and retinitis pigmentosa, are the most common causes of blindness in the western world. A potential cure is to use a microelectronic retinal prosthesis to provide electrical stimulation to the remaining healthy retinal cells. We describe a prototype CMOS Active Pixel Sensor capable of detecting a visual scene and translating it into a train of electrical pulses for stimulation of the retina. The sensor consists of a 10 x 10 array of 100 micron square pixels fabricated on a 0.35 micron CMOS process. Light incident upon each pixel is converted into output current pulse trains with a frequency related to the light intensity. These outputs are connected to a biocompatible microelectrode array for contact to the retinal cells. The flexible design allows experimentation with signal amplitudes and frequencies in order to determine the most appropriate stimulus for the retina. Neural processing in the retina can be studied by using the sensor in conjunction with a Field Programmable Gate Array (FPGA) programmed to behave as a neural network. The sensor has been integrated into a test system designed for studying retinal response. We present the most recent results obtained from this sensor.

Cycle of charge carrier states with formation and extinction of a floating gate in an ambipolar tetracyanoquaterthienoquinoid-based field-effect transistor

NASA Astrophysics Data System (ADS)

Itoh, Takuro; Toyota, Taro; Higuchi, Hiroyuki; Matsushita, Michio M.; Suzuki, Kentaro; Sugawara, Tadashi

2017-03-01

A tetracyanoquaterthienoquinoid (TCT4Q)-based field effect transistor is characterized by the ambipolar transfer characteristics and the facile shift of the threshold voltage induced by the bias stress. The trapping and detrapping kinetics of charge carriers was investigated in detail by the temperature dependence of the decay of source-drain current (ISD). We found a repeatable formation of a molecular floating gate is derived from a 'charge carrier-and-gate' cycle comprising four stages, trapping of mobile carriers, formation of a floating gate, induction of oppositely charged mobile carriers, and recombination between mobile and trapped carriers to restore the initial state.

Direct probing of electron and hole trapping into nano-floating-gate in organic field-effect transistor nonvolatile memories

NASA Astrophysics Data System (ADS)

Cui, Ze-Qun; Wang, Shun; Chen, Jian-Mei; Gao, Xu; Dong, Bin; Chi, Li-Feng; Wang, Sui-Dong

2015-03-01

Electron and hole trapping into the nano-floating-gate of a pentacene-based organic field-effect transistor nonvolatile memory is directly probed by Kelvin probe force microscopy. The probing is straightforward and non-destructive. The measured surface potential change can quantitatively profile the charge trapping, and the surface characterization results are in good accord with the corresponding device behavior. Both electrons and holes can be trapped into the nano-floating-gate, with a preference of electron trapping than hole trapping. The trapped charge quantity has an approximately linear relation with the programming/erasing gate bias, indicating that the charge trapping in the device is a field-controlled process.

BiCMOS circuit technology for a 704 MHz ATM switch LSI

NASA Astrophysics Data System (ADS)

Ohtomo, Yusuke; Yasuda, Sadayuki; Togashi, Minoru; Ino, Masayuki; Tanabe, Yasuyuki; Inoue, Jun-Ichi; Nogawa, Masafumi; Hino, Shigeki

1994-05-01

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 micron BiCMOS technology. The LSI, composed of CMOS 15 K gate LOGIC, 8 Kb RAM, 1 Kb FIFO and ECL 1.6 K gate LOGIC, achieved an operation speed of 704-MHz with power dissipation of 7.2 W.

The effects of transistor source-to-gate bridging faults in complex CMOS gates

NASA Astrophysics Data System (ADS)

Visweswaran, G. S.; Ali, Akhtar-Uz-Zaman M.; Lala, Parag K.; Hartmann, Carlos R. P.

1991-06-01

A study of the effect of gate-to-source bridging faults in the pull-up section of a complex CMOS gate is presented. The manifestation of these faults depends on the resistance value of the connection causing the bridging. It is shown that such faults manifest themselves either as stuck-at or stuck-open faults and can be detected by tests for stuck-at and stuck-open faults generated for the equivalent logic current. It is observed that for transistor channel lengths larger than 1 microns there exists a range of values of the bridging resistance for which the fault behaves as a pseudo-stuck-open fault.

Floating gate transistors as biosensors (Conference Presentation)

NASA Astrophysics Data System (ADS)

Frisbie, C. Daniel

2016-11-01

Electrolyte gated transistors (EGTs) are a sub-class of thin film transistors that are extremely promising for biological sensing applications. These devices employ a solid electrolyte as the gate insulator; the very large capacitance of the electrolyte results in low voltage operation and high transconductance or gain. This talk will describe the fabrication of floating gate EGTs and their use as ricin sensors. The critical performance metrics for EGTs compared with other types of TFTs will also be reviewed.

Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.

PubMed

Bae, Jong-Ho; Lee, Jong-Ho

2016-05-01

A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.

High Performance Transparent Transistor Memory Devices Using Nano-Floating Gate of Polymer/ZnO Nanocomposites

NASA Astrophysics Data System (ADS)

Shih, Chien-Chung; Lee, Wen-Ya; Chiu, Yu-Cheng; Hsu, Han-Wen; Chang, Hsuan-Chun; Liu, Cheng-Liang; Chen, Wen-Chang

2016-02-01

Nano-floating gate memory devices (NFGM) using metal nanoparticles (NPs) covered with an insulating polymer have been considered as a promising electronic device for the next-generation nonvolatile organic memory applications NPs. However, the transparency of the device with metal NPs is restricted to 60~70% due to the light absorption in the visible region caused by the surface plasmon resonance effects of metal NPs. To address this issue, we demonstrate a novel NFGM using the blends of hole-trapping poly (9-(4-vinylphenyl) carbazole) (PVPK) and electron-trapping ZnO NPs as the charge storage element. The memory devices exhibited a remarkably programmable memory window up to 60 V during the program/erase operations, which was attributed to the trapping/detrapping of charge carriers in ZnO NPs/PVPK composite. Furthermore, the devices showed the long-term retention time (>105 s) and WRER test (>200 cycles), indicating excellent electrical reliability and stability. Additionally, the fabricated transistor memory devices exhibited a relatively high transparency of 90% at the wavelength of 500 nm based on the spray-coated PEDOT:PSS as electrode, suggesting high potential for transparent organic electronic memory devices.

Spin switches for compact implementation of neuron and synapse

NASA Astrophysics Data System (ADS)

Quang Diep, Vinh; Sutton, Brian; Behin-Aein, Behtash; Datta, Supriyo

2014-06-01

Nanomagnets driven by spin currents provide a natural implementation for a neuron and a synapse: currents allow convenient summation of multiple inputs, while the magnet provides the threshold function. The objective of this paper is to explore the possibility of a hardware neural network implementation using a spin switch (SS) as its basic building block. SS is a recently proposed device based on established technology with a transistor-like gain and input-output isolation. This allows neural networks to be constructed with purely passive interconnections without intervening clocks or amplifiers. The weights for the neural network are conveniently adjusted through analog voltages that can be stored in a non-volatile manner in an underlying CMOS layer using a floating gate low dropout voltage regulator. The operation of a multi-layer SS neural network designed for character recognition is demonstrated using a standard simulation model based on coupled Landau-Lifshitz-Gilbert equations, one for each magnet in the network.

Electron lithography STAR design guidelines. Part 1: The STAR user design manual

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Newman, W.

1982-01-01

The STAR system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computer programs to place, route, and display designs implemented with cells from the library. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

A CMOS silicon spin qubit

PubMed Central

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; De Franceschi, S.

2016-01-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform. PMID:27882926

A CMOS silicon spin qubit

NASA Astrophysics Data System (ADS)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

A CMOS silicon spin qubit.

PubMed

Maurand, R; Jehl, X; Kotekar-Patil, D; Corna, A; Bohuslavskyi, H; Laviéville, R; Hutin, L; Barraud, S; Vinet, M; Sanquer, M; De Franceschi, S

2016-11-24

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

A 5 nW Quasi-Linear CMOS Hot-Electron Injector for Self-Powered Monitoring of Biomechanical Strain Variations.

PubMed

Zhou, Liang; Abraham, Adam C; Tang, Simon Y; Chakrabartty, Shantanu

2016-12-01

Piezoelectricity-driven hot-electron injectors (p-HEI) are used for self-powered monitoring of mechanical activity in biomechanical implants and structures. Previously reported p-HEI devices operate by harvesting energy from a piezoelectric transducer to generate current and voltage references which are then used for initiating and controlling the process of hot-electron injection. As a result, the minimum energy required to activate the device is limited by the power requirements of the reference circuits. In this paper we present a p-HEI device that operates by directly exploiting the self-limiting capability of an energy transducer when driving the process of hot-electron injection in a pMOS floating-gate transistor. As a result, the p-HEI device can activate itself at input power levels less than 5 nW. Using a prototype fabricated in a 0.5- [Formula: see text] bulk CMOS process we validate the functionality of the proposed injector and show that for a fixed input power, its dynamics is quasi-linear with respect to time. The paper also presents measurement results using a cadaver phantom where the fabricated p-HEI device has been integrated with a piezoelectric transducer and is used for self-powered monitoring of mechanical activity.

MOSFET Electric-Charge Sensor

NASA Technical Reports Server (NTRS)

Robinson, Paul A., Jr.

1988-01-01

Charged-particle probe compact and consumes little power. Proposed modification enables metal oxide/semiconductor field-effect transistor (MOSFET) to act as detector of static electric charges or energetic charged particles. Thickened gate insulation acts as control structure. During measurements metal gate allowed to "float" to potential of charge accumulated in insulation. Stack of modified MOSFET'S constitutes detector of energetic charged particles. Each gate "floats" to potential induced by charged-particle beam penetrating its layer.

Analog Module Architecture for Space-Qualified Field-Programmable Mixed-Signal Arrays

NASA Technical Reports Server (NTRS)

Edwards, R. Timothy; Strohbehn, Kim; Jaskulek, Steven E.; Katz, Richard

1999-01-01

Spacecraft require all manner of both digital and analog circuits. Onboard digital systems are constructed almost exclusively from field-programmable gate array (FPGA) circuits providing numerous advantages over discrete design including high integration density, high reliability, fast turn-around design cycle time, lower mass, volume, and power consumption, and lower parts acquisition and flight qualification costs. Analog and mixed-signal circuits perform tasks ranging from housekeeping to signal conditioning and processing. These circuits are painstakingly designed and built using discrete components due to a lack of options for field-programmability. FPAA (Field-Programmable Analog Array) and FPMA (Field-Programmable Mixed-signal Array) parts exist but not in radiation-tolerant technology and not necessarily in an architecture optimal for the design of analog circuits for spaceflight applications. This paper outlines an architecture proposed for an FPAA fabricated in an existing commercial digital CMOS process used to make radiation-tolerant antifuse-based FPGA devices. The primary concerns are the impact of the technology and the overall array architecture on the flexibility of programming, the bandwidth available for high-speed analog circuits, and the accuracy of the components for high-performance applications.

Material parameters from frequency dispersion simulation of floating gate memory with Ge nanocrystals in HfO2

NASA Astrophysics Data System (ADS)

Palade, C.; Lepadatu, A. M.; Slav, A.; Lazanu, S.; Teodorescu, V. S.; Stoica, T.; Ciurea, M. L.

2018-01-01

Trilayer memory capacitors with Ge nanocrystals (NCs) floating gate in HfO2 were obtained by magnetron sputtering deposition on p-type Si substrate followed by rapid thermal annealing at relatively low temperature of 600 °C. The frequency dispersion of capacitance and resistance was measured in accumulation regime of Al/HfO2 gate oxide/Ge NCs in HfO2 floating gate/HfO2 tunnel oxide/SiOx/p-Si/Al memory capacitors. For simulation of the frequency dispersion a complex circuit model was used considering an equivalent parallel RC circuit for each layer of the trilayer structure. A series resistance due to metallic contacts and Si substrate was necessary to be included in the model. A very good fit to the experimental data was obtained and the parameters of each layer in the memory capacitor, i.e. capacitances and resistances were determined and in turn the intrinsic material parameters, i.e. dielectric constants and resistivities of layers were evaluated. The results are very important for the study and optimization of the hysteresis behaviour of floating gate memories based on NCs embedded in oxide.

95. Photocopied August 1978. CRIBS BEING FLOATED INTO PLACE FOR ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

95. Photocopied August 1978. CRIBS BEING FLOATED INTO PLACE FOR THE CONSTRUCTION OF THE SECOND SET (NOS. 13-16) OF COMPENSATING GATES. NOTE THE ORIGINAL FOUR GATES IN THE BACKGROUND, MAY 14, 1915. (587) - Michigan Lake Superior Power Company, Portage Street, Sault Ste. Marie, Chippewa County, MI

Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2015-07-21

Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing

NASA Astrophysics Data System (ADS)

Bilal, Bisma; Ahmed, Suhaib; Kakkar, Vipan

2018-02-01

The challenges which the CMOS technology is facing toward the end of the technology roadmap calls for an investigation of various logical and technological solutions to CMOS at the nano scale. Two such paradigms which are considered in this paper are the reversible logic and the quantum-dot cellular automata (QCA) nanotechnology. Firstly, a new 3 × 3 reversible and universal gate, RG-QCA, is proposed and implemented in QCA technology using conventional 3-input majority voter based logic. Further the gate is optimized by using explicit interaction of cells and this optimized gate is then used to design an optimized modular full adder in QCA. Another configuration of RG-QCA gate, CRG-QCA, is then proposed which is a 4 × 4 gate and includes the fault tolerant characteristics and parity preserving nature. The proposed CRG-QCA gate is then tested to design a fault tolerant full adder circuit. Extensive comparisons of gate and adder circuits are drawn with the existing literature and it is envisaged that our proposed designs perform better and are cost efficient in QCA technology.

A reliable ground bounce noise reduction technique for nanoscale CMOS circuits

NASA Astrophysics Data System (ADS)

Sharma, Vijay Kumar; Pattanaik, Manisha

2015-11-01

Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.

20-GFLOPS QR processor on a Xilinx Virtex-E FPGA

NASA Astrophysics Data System (ADS)

Walke, Richard L.; Smith, Robert W. M.; Lightbody, Gaye

2000-11-01

Adaptive beamforming can play an important role in sensor array systems in countering directional interference. In high-sample rate systems, such as radar and comms, the calculation of adaptive weights is a very computational task that requires highly parallel solutions. For systems where low power consumption and volume are important the only viable implementation is as an Application Specific Integrated Circuit (ASIC). However, the rapid advancement of Field Programmable Gate Array (FPGA) technology is enabling highly credible re-programmable solutions. In this paper we present the implementation of a scalable linear array processor for weight calculation using QR decomposition. We employ floating-point arithmetic with mantissa size optimized to the target application to minimize component size, and implement them as relationally placed macros (RPMs) on Xilinx Virtex FPGAs to achieve predictable dense layout and high-speed operation. We present results that show that 20GFLOPS of sustained computation on a single XCV3200E-8 Virtex-E FPGA is possible. We also describe the parameterized implementation of the floating-point operators and QR-processor, and the design methodology that enables us to rapidly generate complex FPGA implementations using the industry standard hardware description language VHDL.

Solution processed molecular floating gate for flexible flash memories

NASA Astrophysics Data System (ADS)

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-10-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices.

Solution processed molecular floating gate for flexible flash memories

PubMed Central

Zhou, Ye; Han, Su-Ting; Yan, Yan; Huang, Long-Biao; Zhou, Li; Huang, Jing; Roy, V. A. L.

2013-01-01

Solution processed fullerene (C60) molecular floating gate layer has been employed in low voltage nonvolatile memory device on flexible substrates. We systematically studied the charge trapping mechanism of the fullerene floating gate for both p-type pentacene and n-type copper hexadecafluorophthalocyanine (F16CuPc) semiconductor in a transistor based flash memory architecture. The devices based on pentacene as semiconductor exhibited both hole and electron trapping ability, whereas devices with F16CuPc trapped electrons alone due to abundant electron density. All the devices exhibited large memory window, long charge retention time, good endurance property and excellent flexibility. The obtained results have great potential for application in large area flexible electronic devices. PMID:24172758

CMOS image sensor with lateral electric field modulation pixels for fluorescence lifetime imaging with sub-nanosecond time response

NASA Astrophysics Data System (ADS)

Li, Zhuo; Seo, Min-Woong; Kagawa, Keiichiro; Yasutomi, Keita; Kawahito, Shoji

2016-04-01

This paper presents the design and implementation of a time-resolved CMOS image sensor with a high-speed lateral electric field modulation (LEFM) gating structure for time domain fluorescence lifetime measurement. Time-windowed signal charge can be transferred from a pinned photodiode (PPD) to a pinned storage diode (PSD) by turning on a pair of transfer gates, which are situated beside the channel. Unwanted signal charge can be drained from the PPD to the drain by turning on another pair of gates. The pixel array contains 512 (V) × 310 (H) pixels with 5.6 × 5.6 µm2 pixel size. The imager chip was fabricated using 0.11 µm CMOS image sensor process technology. The prototype sensor has a time response of 150 ps at 374 nm. The fill factor of the pixels is 5.6%. The usefulness of the prototype sensor is demonstrated for fluorescence lifetime imaging through simulation and measurement results.

Regenerative switching CMOS system

DOEpatents

Welch, James D.

1998-01-01

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

Regenerative switching CMOS system

DOEpatents

Welch, J.D.

1998-06-02

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

A Method for Estimating the Probability of Floating Gate Prompt Charge Loss in a Radiation Environment

NASA Technical Reports Server (NTRS)

Edmonds, L. D.

2016-01-01

Since advancing technology has been producing smaller structures in electronic circuits, the floating gates in modern flash memories are becoming susceptible to prompt charge loss from ionizing radiation environments found in space. A method for estimating the risk of a charge-loss event is given.

A Method for Estimating the Probability of Floating Gate Prompt Charge Loss in a Radiation Environment

NASA Technical Reports Server (NTRS)

Edmonds, L. D.

2016-01-01

Because advancing technology has been producing smaller structures in electronic circuits, the floating gates in modern flash memories are becoming susceptible to prompt charge loss from ionizing radiation environments found in space. A method for estimating the risk of a charge-loss event is given.

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Wei, E-mail: wwei99@jlu.edu.cn; Han, Jinhua; Ying, Jun

2014-09-22

Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm{sup 2}/V s. The unidirectional shift of turn-on voltage (V{sub on}) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V{sub P}/V{sub E}) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered moleculemore » orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm{sup 2}/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V{sub P}/V{sub E} of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V{sub on} shift. As a result, an enlarged memory window of 28.6 V at the V{sub P}/V{sub E} of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.« less

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Macleod, Todd C.; Ho, Fat D.

2006-01-01

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

PubMed Central

Khan, Z. N.; Ahmed, S.; Ali, M.

2016-01-01

Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

A fully on-chip fast-transient NMOS low dropout voltage regulator with quasi floating gate pass element

NASA Astrophysics Data System (ADS)

Wang, Han; Gou, Chao; Luo, Kai

2017-04-01

This paper presents a fully on-chip NMOS low-dropout regulator (LDO) for portable applications with quasi floating gate pass element and fast transient response. The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump, which allows the charge pump to be a small economical circuit with small silicon area. In addition, a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient. The proposed LDO has been implemented in a 0.35 μm BCD process. From experimental results, the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and {I}{{Q}} of 395 μA. Under full-range load current step, the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV, respectively.

High-κ gate dielectrics: Current status and materials properties considerations

NASA Astrophysics Data System (ADS)

Wilk, G. D.; Wallace, R. M.; Anthony, J. M.

2001-05-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward successful integration into the expected processing conditions for future CMOS technologies, especially due to their tendency to form at interfaces with Si (e.g. silicates). These pseudobinary systems also thereby enable the use of other high-κ materials by serving as an interfacial high-κ layer. While work is ongoing, much research is still required, as it is clear that any material which is to replace SiO2 as the gate dielectric faces a formidable challenge. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Physical implication of transition voltage in organic nano-floating-gate nonvolatile memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Shun; Gao, Xu, E-mail: wangsd@suda.edu.cn, E-mail: gaoxu@suda.edu.cn; Zhong, Ya-Nan

High-performance pentacene-based organic field-effect transistor nonvolatile memories, using polystyrene as a tunneling dielectric and Au nanoparticles as a nano-floating-gate, show parallelogram-like transfer characteristics with a featured transition point. The transition voltage at the transition point corresponds to a threshold electric field in the tunneling dielectric, over which stored electrons in the nano-floating-gate will start to leak out. The transition voltage can be modulated depending on the bias configuration and device structure. For p-type active layers, optimized transition voltage should be on the negative side of but close to the reading voltage, which can simultaneously achieve a high ON/OFF ratio andmore » good memory retention.« less

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1977-01-01

Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.

Mk x Nk gated CMOS imager

NASA Astrophysics Data System (ADS)

Janesick, James; Elliott, Tom; Andrews, James; Tower, John; Bell, Perry; Teruya, Alan; Kimbrough, Joe; Bishop, Jeanne

2014-09-01

Our paper will describe a recently designed Mk x Nk x 10 um pixel CMOS gated imager intended to be first employed at the LLNL National Ignition Facility (NIF). Fabrication involves stitching MxN 1024x1024x10 um pixel blocks together into a monolithic imager (where M = 1, 2, . .10 and N = 1, 2, . . 10). The imager has been designed for either NMOS or PMOS pixel fabrication using a base 0.18 um/3.3V CMOS process. Details behind the design are discussed with emphasis on a custom global reset feature which erases the imager of unwanted charge in ~1 us during the fusion ignition process followed by an exposure to obtain useful data. Performance data generated by prototype imagers designed similar to the Mk x Nk sensor is presented.

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

PubMed Central

Pérez Suárez, Santiago T.; Travieso González, Carlos M.; Alonso Hernández, Jesús B.

2013-01-01

This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA) using fixed point format. The FPGA design is based on the System Generator from Xilinx, which is a design tool over Simulink of Matlab. System Generator allows one to design in a fast and flexible way. It uses low level details of the circuits and the functionality of the system can be fully tested. System Generator can be used to check the architecture and to analyse the effect of the number of bits on the system performance. Finally the System Generator design is compiled for the Xilinx Integrated System Environment (ISE) and the system is described using a hardware description language. In ISE the circuits are managed with high level details and physical performances are obtained. In the Conclusions section, some modifications are proposed to improve the methodology and to ensure portability across FPGA manufacturers.

High-resolution depth profiling using a range-gated CMOS SPAD quanta image sensor.

PubMed

Ren, Ximing; Connolly, Peter W R; Halimi, Abderrahim; Altmann, Yoann; McLaughlin, Stephen; Gyongy, Istvan; Henderson, Robert K; Buller, Gerald S

2018-03-05

A CMOS single-photon avalanche diode (SPAD) quanta image sensor is used to reconstruct depth and intensity profiles when operating in a range-gated mode used in conjunction with pulsed laser illumination. By designing the CMOS SPAD array to acquire photons within a pre-determined temporal gate, the need for timing circuitry was avoided and it was therefore possible to have an enhanced fill factor (61% in this case) and a frame rate (100,000 frames per second) that is more difficult to achieve in a SPAD array which uses time-correlated single-photon counting. When coupled with appropriate image reconstruction algorithms, millimeter resolution depth profiles were achieved by iterating through a sequence of temporal delay steps in synchronization with laser illumination pulses. For photon data with high signal-to-noise ratios, depth images with millimeter scale depth uncertainty can be estimated using a standard cross-correlation approach. To enhance the estimation of depth and intensity images in the sparse photon regime, we used a bespoke clustering-based image restoration strategy, taking into account the binomial statistics of the photon data and non-local spatial correlations within the scene. For sparse photon data with total exposure times of 75 ms or less, the bespoke algorithm can reconstruct depth images with millimeter scale depth uncertainty at a stand-off distance of approximately 2 meters. We demonstrate a new approach to single-photon depth and intensity profiling using different target scenes, taking full advantage of the high fill-factor, high frame rate and large array format of this range-gated CMOS SPAD array.

Characterizations of and Radiation Effects in Several Emerging CMOS Technologies

NASA Astrophysics Data System (ADS)

Shufeng Ren

As the conventional scaling of Si based CMOS is approaching its limit at 7 nm technology node, many perceive that the adoption of novel materials and/or device structures are inevitable to keep Moore's law going. High mobility channel materials such as III-V compound semiconductors or Ge are considered promising to replace Si in order to achieve high performance as well as low power consumption. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, GaAs, InGaAs, GaSb, etc) to replace Si CMOS technology. Therefore novel high-k dielectrics, such as epitaxially grown crystalline oxides, have been explored to be incorporated onto the high mobility channel materials. Moreover, to enable continued scaling, extremely scaled devices structures such as nanowire gate-all-around structure are needed in the near future. Moreover, as the CMOS industry moves into the 7 nm node and beyond, novel lithography techniques such as EUV are believed to be adopted soon, which can bring radiation damage to CMOS devices and circuit during the fabrication process. Therefore radiation hardening technology in future generations of CMOS devices has again become an interesting research topic to deal with the possible process-induced damage as well as damage caused by operating in radiation harsh environment such as outer space, nuclear plant, etc. In this thesis, the electrical properties of a few selected emerging novel CMOS devices are investigated, which include InGaAs based extremely scaled ultra-thin body nanowire gate-all-around MOSFETs, GOI (Ge On Insulator) CMOS with recessed channel and source/drain, GaAs MOSFETs with crystalline La based gate stack, and crystalline SrTiO3, are investigated to extend our understanding of their electrical characteristics, underlying physical mechanisms, and material properties. Furthermore, the radiation responses of these aforementioned novel devices are thoroughly investigated, with a focus on the total ionizing dose (TID) effect, to understand the associated physical mechanisms, and to help to inspire ideas to improve radiation immunity of these novel devices. The experimental methods used in this thesis research include the measurements of C-V, I-V characteristics, where novel gate stack and interface characterization techniques are employed, such as AC Gm method, 1/f low frequency noise method, inelastic electron tunneling spectroscopy (IETS) for chemical bonding and defects detection, and carrier transport modeling. Sentaurus TCAD simulations are also carried out to obtain more physical insight in the complex, extremely scaled, device structures.

Spin switches for compact implementation of neuron and synapse

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quang Diep, Vinh, E-mail: vdiep@purdue.edu; Sutton, Brian; Datta, Supriyo

2014-06-02

Nanomagnets driven by spin currents provide a natural implementation for a neuron and a synapse: currents allow convenient summation of multiple inputs, while the magnet provides the threshold function. The objective of this paper is to explore the possibility of a hardware neural network implementation using a spin switch (SS) as its basic building block. SS is a recently proposed device based on established technology with a transistor-like gain and input-output isolation. This allows neural networks to be constructed with purely passive interconnections without intervening clocks or amplifiers. The weights for the neural network are conveniently adjusted through analog voltagesmore » that can be stored in a non-volatile manner in an underlying CMOS layer using a floating gate low dropout voltage regulator. The operation of a multi-layer SS neural network designed for character recognition is demonstrated using a standard simulation model based on coupled Landau-Lifshitz-Gilbert equations, one for each magnet in the network.« less

A hybrid magnetic/complementary metal oxide semiconductor three-context memory bit cell for non-volatile circuit design

NASA Astrophysics Data System (ADS)

Jovanović, B.; Brum, R. M.; Torres, L.

2014-04-01

After decades of continued scaling to the beat of Moore's law, it now appears that conventional silicon based devices are approaching their physical limits. In today's deep-submicron nodes, a number of short-channel and quantum effects are emerging that affect the manufacturing process, as well as, the functionality of the microelectronic systems-on-chip. Spintronics devices that exploit both the intrinsic spin of the electron and its associated magnetic moment, in addition to its fundamental electronic charge, are promising solutions to circumvent these scaling threats. Being compatible with the CMOS technology, such devices offer a promising synergy of radiation immunity, infinite endurance, non-volatility, increased density, etc. In this paper, we present a hybrid (magnetic/CMOS) cell that is able to store and process data both electrically and magnetically. The cell is based on perpendicular spin-transfer torque magnetic tunnel junctions (STT-MTJs) and is suitable for use in magnetic random access memories and reprogrammable computing (non-volatile registers, processor cache memories, magnetic field-programmable gate arrays, etc). To demonstrate the potential our hybrid cell, we physically implemented a small hybrid memory block using 45 nm × 45 nm round MTJs for the magnetic part and 28 nm fully depleted silicon on insulator (FD-SOI) technology for the CMOS part. We also report the cells measured performances in terms of area, robustness, read/write speed and energy consumption.

III-V/Ge MOS device technologies for low power integrated systems

NASA Astrophysics Data System (ADS)

Takagi, S.; Noguchi, M.; Kim, M.; Kim, S.-H.; Chang, C.-Y.; Yokoyama, M.; Nishi, K.; Zhang, R.; Ke, M.; Takenaka, M.

2016-11-01

CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V n-MOSFETs on Si. We also demonstrate planar-type InGaAs and Ge/strained SOI TFETs. The defect-less p+-n source junction formation with steep impurity profiles is a key for high performance TFET operation.

Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2

NASA Astrophysics Data System (ADS)

Martin, Dominik; Yurchuk, Ekaterina; Müller, Stefan; Müller, Johannes; Paul, Jan; Sundquist, Jonas; Slesazeck, Stefan; Schlösser, Till; van Bentum, Ralf; Trentzsch, Martin; Schröder, Uwe; Mikolajick, Thomas

2013-10-01

Throughout the 22 nm technology node HfO2 is established as a reliable gate dielectric in contemporary complementary metal oxide semiconductor (CMOS) technology. The working principle of ferroelectric field effect transistors FeFET has also been demonstrated for some time for dielectric materials like Pb[ZrxTi1-x]O3 and SrBi2Ta2O9. However, integrating these into contemporary downscaled CMOS technology nodes is not trivial due to the necessity of an extremely thick gate stack. Recent developments have shown HfO2 to have ferroelectric properties, given the proper doping. Moreover, these doped HfO2 thin films only require layer thicknesses similar to the ones already in use in CMOS technology. This work will show how the incorporation of Si induces ferroelectricity in HfO2 based capacitor structures and finally demonstrate non-volatile storage in nFeFETs down to a gate length of 100 nm. A memory window of 0.41 V can be retained after 20,000 switching cycles. Retention can be extrapolated to 10 years.

The operation of 0.35 μm partially depleted SOI CMOS technology in extreme environments

NASA Astrophysics Data System (ADS)

Li, Ying; Niu, Guofu; Cressler, John D.; Patel, Jagdish; Liu, S. T.; Reed, Robert A.; Mojarradi, Mohammad M.; Blalock, Benjamin J.

2003-06-01

We evaluate the usefulness of partially depleted SOI CMOS devices fabricated in a 0.35 μm technology on UNIBOND material for electronics applications requiring robust operation under extreme environment conditions consisting of low and/or high temperature, and under substantial radiation exposure. The threshold voltage, effective mobility, and the impact ionization parameters were determined across temperature for both the nFETs and the pFETs. The radiation response was characterized using threshold voltage shifts of both the front-gate and back-gate transistors. These results suggest that this 0.35 μm partially depleted SOI CMOS technology is suitable for operation across a wide range of extreme environment conditions consisting of: cryogenic temperatures down to 86 K, elevated temperatures up to 573 K, and under radiation exposure to 1.3 Mrad(Si) total dose.

Unified random access memory (URAM) by integration of a nanocrystal floating gate for nonvolatile memory and a partially depleted floating body for capacitorless 1T-DRAM

NASA Astrophysics Data System (ADS)

Ryu, Seong-Wan; Han, Jin-Woo; Kim, Chung-Jin; Kim, Sungho; Choi, Yang-Kyu

2009-03-01

This paper describes a unified memory (URAM) that utilizes a nanocrystal SOI MOSFET for multi-functional applications of both nonvolatile memory (NVM) and capacitorless 1T-DRAM. By using a discrete storage node (Ag nanocrystal) as the floating gate of the NVM, high defect immunity and 2-bit/cell operation were achieved. The embedded nanocrystal NVM also showed 1T-DRAM operation (program/erase time = 100 ns) characteristics, which were realized by storing holes in the floating body of the SOI MOSFET, without requiring an external capacitor. Three-bit/cell operation was accomplished for different applications - 2-bits for nonvolatility and 1-bit for fast operation.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Floating-gate memory based on an organic metal-insulator-semiconductor capacitor

NASA Astrophysics Data System (ADS)

William, S.; Mabrook, M. F.; Taylor, D. M.

2009-08-01

A floating gate memory element is described which incorporates an evaporated gold film embedded in the gate dielectric of a metal-insulator-semiconductor capacitor based on poly(3-hexylthiophene). On exceeding a critical amplitude in the voltage sweep, hysteresis is observed in the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the device. The anticlockwise hysteresis in C-V is consistent with strong electron trapping during the positive cycle but little hole trapping during the negative cycle. We argue that the clockwise hysteresis observed in the negative cycle of the I-V plot, arises from leakage of trapped holes through the underlying insulator to the control gate.

Single layer of Ge quantum dots in HfO2 for floating gate memory capacitors.

PubMed

Lepadatu, A M; Palade, C; Slav, A; Maraloiu, A V; Lazanu, S; Stoica, T; Logofatu, C; Teodorescu, V S; Ciurea, M L

2017-04-28

High performance trilayer memory capacitors with a floating gate of a single layer of Ge quantum dots (QDs) in HfO 2 were fabricated using magnetron sputtering followed by rapid thermal annealing (RTA). The layer sequence of the capacitors is gate HfO 2 /floating gate of single layer of Ge QDs in HfO 2 /tunnel HfO 2 /p-Si wafers. Both Ge and HfO 2 are nanostructured by RTA at moderate temperatures of 600-700 °C. By nanostructuring at 600 °C, the formation of a single layer of well separated Ge QDs with diameters of 2-3 nm at a density of 4-5 × 10 15 m -2 is achieved in the floating gate (intermediate layer). The Ge QDs inside the intermediate layer are arranged in a single layer and are separated from each other by HfO 2 nanocrystals (NCs) about 8 nm in diameter with a tetragonal/orthorhombic structure. The Ge QDs in the single layer are located at the crossing of the HfO 2 NCs boundaries. In the intermediate layer, besides Ge QDs, a part of the Ge atoms is segregated by RTA at the HfO 2 NCs boundaries, while another part of the Ge atoms is present inside the HfO 2 lattice stabilizing the tetragonal/orthorhombic structure. The fabricated capacitors show a memory window of 3.8 ± 0.5 V and a capacitance-time characteristic with 14% capacitance decay in the first 3000-4000 s followed by a very slow capacitance decrease extrapolated to 50% after 10 years. This high performance is mainly due to the floating gate of a single layer of well separated Ge QDs in HfO 2 , distanced from the Si substrate by the tunnel oxide layer with a precise thickness.

A Real-Time Marker-Based Visual Sensor Based on a FPGA and a Soft Core Processor

PubMed Central

Tayara, Hilal; Ham, Woonchul; Chong, Kil To

2016-01-01

This paper introduces a real-time marker-based visual sensor architecture for mobile robot localization and navigation. A hardware acceleration architecture for post video processing system was implemented on a field-programmable gate array (FPGA). The pose calculation algorithm was implemented in a System on Chip (SoC) with an Altera Nios II soft-core processor. For every frame, single pass image segmentation and Feature Accelerated Segment Test (FAST) corner detection were used for extracting the predefined markers with known geometries in FPGA. Coplanar PosIT algorithm was implemented on the Nios II soft-core processor supplied with floating point hardware for accelerating floating point operations. Trigonometric functions have been approximated using Taylor series and cubic approximation using Lagrange polynomials. Inverse square root method has been implemented for approximating square root computations. Real time results have been achieved and pixel streams have been processed on the fly without any need to buffer the input frame for further implementation. PMID:27983714

A Real-Time Marker-Based Visual Sensor Based on a FPGA and a Soft Core Processor.

PubMed

Tayara, Hilal; Ham, Woonchul; Chong, Kil To

2016-12-15

This paper introduces a real-time marker-based visual sensor architecture for mobile robot localization and navigation. A hardware acceleration architecture for post video processing system was implemented on a field-programmable gate array (FPGA). The pose calculation algorithm was implemented in a System on Chip (SoC) with an Altera Nios II soft-core processor. For every frame, single pass image segmentation and Feature Accelerated Segment Test (FAST) corner detection were used for extracting the predefined markers with known geometries in FPGA. Coplanar PosIT algorithm was implemented on the Nios II soft-core processor supplied with floating point hardware for accelerating floating point operations. Trigonometric functions have been approximated using Taylor series and cubic approximation using Lagrange polynomials. Inverse square root method has been implemented for approximating square root computations. Real time results have been achieved and pixel streams have been processed on the fly without any need to buffer the input frame for further implementation.

Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

2010-10-01

Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Zheming; Yoshii, Kazutomo; Finkel, Hal

Open Computing Language (OpenCL) is a high-level language that enables software programmers to explore Field Programmable Gate Arrays (FPGAs) for application acceleration. The Intel FPGA software development kit (SDK) for OpenCL allows a user to specify applications at a high level and explore the performance of low-level hardware acceleration. In this report, we present the FPGA performance and power consumption results of the single-precision floating-point vector add OpenCL kernel using the Intel FPGA SDK for OpenCL on the Nallatech 385A FPGA board. The board features an Arria 10 FPGA. We evaluate the FPGA implementations using the compute unit duplication andmore » kernel vectorization optimization techniques. On the Nallatech 385A FPGA board, the maximum compute kernel bandwidth we achieve is 25.8 GB/s, approximately 76% of the peak memory bandwidth. The power consumption of the FPGA device when running the kernels ranges from 29W to 42W.« less

Multiplexed charge-locking device for large arrays of quantum devices

NASA Astrophysics Data System (ADS)

Puddy, R. K.; Smith, L. W.; Al-Taie, H.; Chong, C. H.; Farrer, I.; Griffiths, J. P.; Ritchie, D. A.; Kelly, M. J.; Pepper, M.; Smith, C. G.

2015-10-01

We present a method of forming and controlling large arrays of gate-defined quantum devices. The method uses an on-chip, multiplexed charge-locking system and helps to overcome the restraints imposed by the number of wires available in cryostat measurement systems. The device architecture that we describe here utilises a multiplexer-type scheme to lock charge onto gate electrodes. The design allows access to and control of gates whose total number exceeds that of the available electrical contacts and enables the formation, modulation and measurement of large arrays of quantum devices. We fabricate such devices on n-type GaAs/AlGaAs substrates and investigate the stability of the charge locked on to the gates. Proof-of-concept is shown by measurement of the Coulomb blockade peaks of a single quantum dot formed by a floating gate in the device. The floating gate is seen to drift by approximately one Coulomb oscillation per hour.

MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

NASA Astrophysics Data System (ADS)

Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

2014-10-01

Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity

PubMed Central

Zhang, Fan; Niu, Hanben

2016-01-01

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 107 when illuminated by a 405-nm diode laser and 1/1.4 × 104 when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e− rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena. PMID:27367699

A 75-ps Gated CMOS Image Sensor with Low Parasitic Light Sensitivity.

PubMed

Zhang, Fan; Niu, Hanben

2016-06-29

In this study, a 40 × 48 pixel global shutter complementary metal-oxide-semiconductor (CMOS) image sensor with an adjustable shutter time as low as 75 ps was implemented using a 0.5-μm mixed-signal CMOS process. The implementation consisted of a continuous contact ring around each p+/n-well photodiode in the pixel array in order to apply sufficient light shielding. The parasitic light sensitivity of the in-pixel storage node was measured to be 1/8.5 × 10⁷ when illuminated by a 405-nm diode laser and 1/1.4 × 10⁴ when illuminated by a 650-nm diode laser. The pixel pitch was 24 μm, the size of the square p+/n-well photodiode in each pixel was 7 μm per side, the measured random readout noise was 217 e(-) rms, and the measured dynamic range of the pixel of the designed chip was 5500:1. The type of gated CMOS image sensor (CIS) that is proposed here can be used in ultra-fast framing cameras to observe non-repeatable fast-evolving phenomena.

Radiation-hardened transistor and integrated circuit

DOEpatents

Ma, Kwok K.

2007-11-20

A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Nanocrystal floating gate memory with solution-processed indium-zinc-tin-oxide channel and colloidal silver nanocrystals

NASA Astrophysics Data System (ADS)

Hu, Quanli; Ha, Sang-Hyub; Lee, Hyun Ho; Yoon, Tae-Sik

2011-12-01

A nanocrystal (NC) floating gate memory with solution-processed indium-zinc-tin-oxide (IZTO) channel and silver (Ag) NCs embedded in thin gate dielectric layer (SiO2(30 nm)/Al2O3(3 nm)) was fabricated. Both the IZTO channel and colloidal Ag NC layers were prepared by spin-coating and subsequent annealing, and dip-coating process, respectively. A threshold voltage shift up to ~0.9 V, corresponding to the electron density of 6.5 × 1011 cm-2, at gate pulsing <=10 V was achieved by the charging of high density NCs. These results present the successful non-volatile memory characteristics of an oxide-semiconductor transistor fabricated through solution processes.

Electron-beam-evaporated thin films of hafnium dioxide for fabricating electronic devices

DOE PAGES

Xiao, Zhigang; Kisslinger, Kim

2015-06-17

Thin films of hafnium dioxide (HfO 2) are widely used as the gate oxide in fabricating integrated circuits because of their high dielectric constants. In this paper, the authors report the growth of thin films of HfO 2 using e-beam evaporation, and the fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuits using this HfO 2 thin film as the gate oxide. The authors analyzed the thin films using high-resolution transmission electron microscopy and electron diffraction, thereby demonstrating that the e-beam-evaporation-grown HfO 2 film has a polycrystalline structure and forms an excellent interface with silicon. Accordingly, we fabricated 31-stage CMOS ringmore » oscillator to test the quality of the HfO 2 thin film as the gate oxide, and obtained excellent rail-to-rail oscillation waveforms from it, denoting that the HfO 2 thin film functioned very well as the gate oxide.« less

Two CMOS gate arrays for the EPACT experiment

DOE Office of Scientific and Technical Information (OSTI.GOV)

Winkert, G.

1992-08-01

Two semicustom CMOS digital gate arrays are described in this paper which have been developed for the Energetic Particles: Acceleration, Composition, and Transport (EPACT) experiment. The first device, the 'Event Counters: 16 by 24-bit' (EC1624), implements sixteen 24-bit ripple counters and has flexible counting and readout options. The second device, the 'Serial Transmitter/Receiver' (SXR), is a multi-personality chip that can be used at either end of a serial, synchronous communications data link. It can be configured as a master in a central control unit, or as one of many slaves within remote assemblies. Together a network of SXRs allows formore » commanding and verification of distributed control signals. Both gate arrays are radiation hardened and qualified for space flight use. The architecture of each chip is presented and the benefits to the experiment summarized.« less

Energy-band engineering for tunable memory characteristics through controlled doping of reduced graphene oxide.

PubMed

Han, Su-Ting; Zhou, Ye; Yang, Qing Dan; Zhou, Li; Huang, Long-Biao; Yan, Yan; Lee, Chun-Sing; Roy, Vellaisamy A L

2014-02-25

Tunable memory characteristics are used in multioperational mode circuits where memory cells with various functionalities are needed in one combined device. It is always a challenge to obtain control over threshold voltage for multimode operation. On this regard, we use a strategy of shifting the work function of reduced graphene oxide (rGO) in a controlled manner through doping gold chloride (AuCl3) and obtained a gradient increase of rGO work function. By inserting doped rGO as floating gate, a controlled threshold voltage (Vth) shift has been achieved in both p- and n-type low voltage flexible memory devices with large memory window (up to 4 times for p-type and 8 times for n-type memory devices) in comparison with pristine rGO floating gate memory devices. By proper energy band engineering, we demonstrated a flexible floating gate memory device with larger memory window and controlled threshold voltage shifts.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1980-01-01

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro

PubMed Central

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system. PMID:25346683

A CMOS IC-based multisite measuring system for stimulation and recording in neural preparations in vitro.

PubMed

Tateno, Takashi; Nishikawa, Jun

2014-01-01

In this report, we describe the system integration of a complementary metal oxide semiconductor (CMOS) integrated circuit (IC) chip, capable of both stimulation and recording of neurons or neural tissues, to investigate electrical signal propagation within cellular networks in vitro. The overall system consisted of three major subunits: a 5.0 × 5.0 mm CMOS IC chip, a reconfigurable logic device (field-programmable gate array, FPGA), and a PC. To test the system, microelectrode arrays (MEAs) were used to extracellularly measure the activity of cultured rat cortical neurons and mouse cortical slices. The MEA had 64 bidirectional (stimulation and recording) electrodes. In addition, the CMOS IC chip was equipped with dedicated analog filters, amplification stages, and a stimulation buffer. Signals from the electrodes were sampled at 15.6 kHz with 16-bit resolution. The measured input-referred circuitry noise was 10.1 μ V root mean square (10 Hz to 100 kHz), which allowed reliable detection of neural signals ranging from several millivolts down to approximately 33 μ Vpp. Experiments were performed involving the stimulation of neurons with several spatiotemporal patterns and the recording of the triggered activity. An advantage over current MEAs, as demonstrated by our experiments, includes the ability to stimulate (voltage stimulation, 5-bit resolution) spatiotemporal patterns in arbitrary subsets of electrodes. Furthermore, the fast stimulation reset mechanism allowed us to record neuronal signals from a stimulating electrode around 3 ms after stimulation. We demonstrate that the system can be directly applied to, for example, auditory neural prostheses in conjunction with an acoustic sensor and a sound processing system.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

NASA Astrophysics Data System (ADS)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG in the form of PVD TaN was investigated along with high-k blocking dielectric. The material properties of TaN metal and high-k / low-k dielectric engineering were systematically studied. And the resulting memory structures exhibit excellent memory characteristics and scalability of the metal FG down to ˜1nm, which is promising in order to reduce the unwanted FG-FG interferences. In the later part of the study, the thermal stability of the combined stack was examined and various approaches to improve the stability and understand the cause of instability were explored. The performance of the high-k IPD metal FG memory structure was observed to degrade with higher annealing conditions and the deteriorated behavior was attributed to the leakage instability of the high-k /TaN capacitor. While the degradation is pronounced in both MIM and MIS capacitors, a higher leakage increment was seen in MIM, which was attributed to the higher degree of dielectric crystallization. In an attempt to improve the thermal stability, the trade-off in using amorphous interlayers to reduce the enhanced dielectric crystallization on metal was highlighted. Also, the effect of oxygen vacancies and grain growth on the dielectric leakage was studied through a multi-deposition-multi-anneal technique. Multi step deposition and annealing in a more electronegative ambient was observed to have a positive impact on the dielectric performance.

Postirradiation Effects In Integrated Circuits

NASA Technical Reports Server (NTRS)

Shaw, David C.; Barnes, Charles E.

1993-01-01

Two reports discuss postirradiation effects in integrated circuits. Presents examples of postirradiation measurements of performances of integrated circuits of five different types: dual complementary metal oxide/semiconductor (CMOS) flip-flop; CMOS analog multiplier; two CMOS multiplying digital-to-analog converters; electrically erasable programmable read-only memory; and semiconductor/oxide/semiconductor octal buffer driver.

Non-Faradaic electrochemical detection of protein interactions by integrated neuromorphic CMOS sensors.

PubMed

Jacquot, Blake C; Muñoz, Nini; Branch, Darren W; Kan, Edwin C

2008-05-15

Electronic detection of the binding event between biotinylated bovine serum albumen (BSA) and streptavidin is demonstrated with the chemoreceptive neuron MOS (CnuMOS) device. Differing from the ion-sensitive field-effect transistors (ISFET), CnuMOS, with the potential of the extended floating gate determined by both the sensing and control gates in a neuromorphic style, can provide protein detection without requiring analyte reference electrodes. In comparison with the microelectrode arrays, measurements are gathered through purely capacitive, non-Faradaic interactions across insulating interfaces. By using a (3-glycidoxypropyl)trimethoxysilane (3-GPS) self-assembled monolayer (SAM) as a simple covalent link for attaching proteins to a silicon dioxide sensing surface, a fully integrated, electrochemical detection platform is realized for protein interactions through monotone large-signal measurements or small-signal impedance spectroscopy. Calibration curves were created to coordinate the sensor response with ellipsometric measurements taken on witness samples. By monitoring the film thickness of streptavidin capture, a sensitivity of 25ng/cm2 or 2A of film thickness was demonstrated. With an improved noise floor the sensor can detect down to 2ng/(cm2mV) based on the calibration curve. AC measurements are shown to significantly reduce long-term sensor drift. Finally, a noise analysis of electrochemical data indicates 1/f(alpha) behavior with a noise floor beginning at approximately 1Hz.

Defect-sensitivity analysis of an SEU immune CMOS logic family

NASA Technical Reports Server (NTRS)

Ingermann, Erik H.; Frenzel, James F.

1992-01-01

Fault testing of resistive manufacturing defects is done on a recently developed single event upset immune logic family. Resistive ranges and delay times are compared with those of traditional CMOS logic. Reaction of the logic to these defects is observed for a NOR gate, and an evaluation of its ability to cope with them is determined.

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

NASA Astrophysics Data System (ADS)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

Performance of PHOTONIS' low light level CMOS imaging sensor for long range observation

NASA Astrophysics Data System (ADS)

Bourree, Loig E.

2014-05-01

Identification of potential threats in low-light conditions through imaging is commonly achieved through closed-circuit television (CCTV) and surveillance cameras by combining the extended near infrared (NIR) response (800-10000nm wavelengths) of the imaging sensor with NIR LED or laser illuminators. Consequently, camera systems typically used for purposes of long-range observation often require high-power lasers in order to generate sufficient photons on targets to acquire detailed images at night. While these systems may adequately identify targets at long-range, the NIR illumination needed to achieve such functionality can easily be detected and therefore may not be suitable for covert applications. In order to reduce dependency on supplemental illumination in low-light conditions, the frame rate of the imaging sensors may be reduced to increase the photon integration time and thus improve the signal to noise ratio of the image. However, this may hinder the camera's ability to image moving objects with high fidelity. In order to address these particular drawbacks, PHOTONIS has developed a CMOS imaging sensor (CIS) with a pixel architecture and geometry designed specifically to overcome these issues in low-light level imaging. By combining this CIS with field programmable gate array (FPGA)-based image processing electronics, PHOTONIS has achieved low-read noise imaging with enhanced signal-to-noise ratio at quarter moon illumination, all at standard video frame rates. The performance of this CIS is discussed herein and compared to other commercially available CMOS and CCD for long-range observation applications.

Parallel Processing of Broad-Band PPM Signals

NASA Technical Reports Server (NTRS)

Gray, Andrew; Kang, Edward; Lay, Norman; Vilnrotter, Victor; Srinivasan, Meera; Lee, Clement

2010-01-01

A parallel-processing algorithm and a hardware architecture to implement the algorithm have been devised for timeslot synchronization in the reception of pulse-position-modulated (PPM) optical or radio signals. As in the cases of some prior algorithms and architectures for parallel, discrete-time, digital processing of signals other than PPM, an incoming broadband signal is divided into multiple parallel narrower-band signals by means of sub-sampling and filtering. The number of parallel streams is chosen so that the frequency content of the narrower-band signals is low enough to enable processing by relatively-low speed complementary metal oxide semiconductor (CMOS) electronic circuitry. The algorithm and architecture are intended to satisfy requirements for time-varying time-slot synchronization and post-detection filtering, with correction of timing errors independent of estimation of timing errors. They are also intended to afford flexibility for dynamic reconfiguration and upgrading. The architecture is implemented in a reconfigurable CMOS processor in the form of a field-programmable gate array. The algorithm and its hardware implementation incorporate three separate time-varying filter banks for three distinct functions: correction of sub-sample timing errors, post-detection filtering, and post-detection estimation of timing errors. The design of the filter bank for correction of timing errors, the method of estimating timing errors, and the design of a feedback-loop filter are governed by a host of parameters, the most critical one, with regard to processing very broadband signals with CMOS hardware, being the number of parallel streams (equivalently, the rate-reduction parameter).

Disturb-Free Three-Dimensional Vertical Floating Gate NAND with Separated-Sidewall Control Gate

NASA Astrophysics Data System (ADS)

Seo, Moon-Sik; Endoh, Tetsuo

2012-02-01

Recently, the three-dimensional (3D) vertical floating gate (FG) type NAND cell arrays with the sidewall control gate (SCG) structure are receiving attention to overcome the reliability issues of charge trap (CT) type 3D NAND. In order to achieve the multilevel cell (MLC) operation for lower bit cost in 3D NAND, it is important to eliminate reliability issues, such as the Vth distribution with interference and disturbance problems and Vth shift with retention issues. In this paper, we intensively investigated the disturbance problems of the 3D vertical FG type NAND cell with separated-sidewall control gate (S-SCG) structure for the reliable MLC operation. Above all, we successfully demonstrate the fully suppressed disturbance problems, such as indirect programming of the unselected cells, hot electron injection of the edge cells and direct influence to the neighboring passing cells, by using the S-SCG with 30 nm pillar size.

CMOS minimal array

NASA Astrophysics Data System (ADS)

Janesick, James; Cheng, John; Bishop, Jeanne; Andrews, James T.; Tower, John; Walker, Jeff; Grygon, Mark; Elliot, Tom

2006-08-01

A high performance prototype CMOS imager is introduced. Test data is reviewed for different array formats that utilize 3T photo diode, 5T pinned photo diode and 6T photo gate CMOS pixel architectures. The imager allows several readout modes including progressive scan, snap and windowed operation. The new imager is built on different silicon substrates including very high resistivity epitaxial wafers for deep depletion operation. Data products contained in this paper focus on sensor's read noise, charge capacity, charge transfer efficiency, thermal dark current, RTS dark spikes, QE, pixel cross- talk and on-chip analog circuitry performance.

FLOAT OPERATED RADIAL GATE INSTALLATION. WASTEWAY NO. 1. WELLTONMOHAWK CANAL ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

FLOAT OPERATED RADIAL GATE INSTALLATION. WASTEWAY NO. 1. WELLTON-MOHAWK CANAL - STA. 99+23.50. United States Department of the Interior, Bureau of Reclamation; Gila Project, Arizona, Wellton-Mohawk Division. Drawing No. 50-D-2497, dated March 8, 1949, Denver Colorado. Sheet 1 of 7 - Wellton-Mohawk Irrigation System, Wasteway No. 1, Wellton-Mohawk Canal, North side of Wellton-Mohawk Canal, bounded by Gila River to North & the Union Pacific Railroad & Gila Mountains to south, Wellton, Yuma County, AZ

FLOAT OPERATED RADIAL GATE HOIST ASSEMBLY LIST OF PARTS ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

FLOAT OPERATED RADIAL GATE HOIST ASSEMBLY - LIST OF PARTS - BASE-CRANK. WASTEWAY NO. 1. WELLTON-MOHAWK CANAL - STA. 99+23.50. United States Department of the Interior, Bureau of Reclamation; Gila Project, Arizona, Wellton-Mohawk Division. Drawing No. 50-D-2511, dated May 3, 1949, Denver Colorado. Sheet 1 of 2 - Wellton-Mohawk Irrigation System, Wasteway No. 1, Wellton-Mohawk Canal, North side of Wellton-Mohawk Canal, bounded by Gila River to North & the Union Pacific Railroad & Gila Mountains to south, Wellton, Yuma County, AZ

Cmos spdt switch for wlan applications

NASA Astrophysics Data System (ADS)

Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

2015-04-01

WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

Two-dimensional molybdenum disulphide nanosheet-covered metal nanoparticle array as a floating gate in multi-functional flash memories

NASA Astrophysics Data System (ADS)

Han, Su-Ting; Zhou, Ye; Chen, Bo; Zhou, Li; Yan, Yan; Zhang, Hua; Roy, V. A. L.

2015-10-01

Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure.Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure. Electronic supplementary information (ESI) available: Energy-dispersive X-ray spectroscopy (EDS) spectra of the metal NPs, SEM image of MoS2 on Au NPs, erasing operations of the metal NPs-MoS2 memory device, transfer characteristics of the standard FET devices and Ag NP devices under programming operation, tapping-mode AFM height image of the fabricated MoS2 film for pristine MoS2 flash memory, gate signals used for programming the Au NPs-MoS2 and Pt NPs-MoS2 flash memories, and data levels recorded for 100 sequential cycles. See DOI: 10.1039/c5nr05054e

Performance study of double SOI image sensors

NASA Astrophysics Data System (ADS)

Miyoshi, T.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Hara, K.; Ikegami, Y.; Kurachi, I.; Nishimura, R.; Ono, S.; Tauchi, K.; Tsuboyama, T.; Yamada, M.

2018-02-01

Double silicon-on-insulator (DSOI) sensors composed of two thin silicon layers and one thick silicon layer have been developed since 2011. The thick substrate consists of high resistivity silicon with p-n junctions while the thin layers are used as SOI-CMOS circuitry and as shielding to reduce the back-gate effect and crosstalk between the sensor and the circuitry. In 2014, a high-resolution integration-type pixel sensor, INTPIX8, was developed based on the DSOI concept. This device is fabricated using a Czochralski p-type (Cz-p) substrate in contrast to a single SOI (SSOI) device having a single thin silicon layer and a Float Zone p-type (FZ-p) substrate. In the present work, X-ray spectra of both DSOI and SSOI sensors were obtained using an Am-241 radiation source at four gain settings. The gain of the DSOI sensor was found to be approximately three times that of the SSOI device because the coupling capacitance is reduced by the DSOI structure. An X-ray imaging demonstration was also performed and high spatial resolution X-ray images were obtained.

Attentional gating models of object substitution masking.

PubMed

Põder, Endel

2013-11-01

Di Lollo, Enns, and Rensink (2000) proposed the computational model of object substitution (CMOS) to explain their experimental results with sparse visual maskers. This model supposedly is based on reentrant hypotheses testing in the visual system, and the modeled experiments are believed to demonstrate these reentrant processes in human vision. In this study, I analyze the main assumptions of this model. I argue that CMOS is a version of the attentional gating model and that its relationship with reentrant processing is rather illusory. The fit of this model to the data indicates that reentrant hypotheses testing is not necessary for the explanation of object substitution masking (OSM). Further, the original CMOS cannot predict some important aspects of the experimental data. I test 2 new models incorporating an unselective processing (divided attention) stage; these models are more consistent with data from OSM experiments. My modeling shows that the apparent complexity of OSM can be reduced to a few simple and well-known mechanisms of perception and memory. PsycINFO Database Record (c) 2013 APA, all rights reserved.

A 190 mV start-up and 59.2% efficiency CMOS gate boosting voltage doubler charge pump in 0.18 µm standard CMOS process for energy harvesting

NASA Astrophysics Data System (ADS)

Yoshida, Minori; Miyaji, Kousuke

2018-04-01

A start-up charge pump circuit for an extremely low input voltage (V IN) is proposed and demonstrated. The proposed circuit uses an inverter level shifter to generate a 2V IN voltage swing to the gate of both main NMOS and PMOS power transistors in a charge pump to reduce the channel resistance. The proposed circuit is fully implemented in a standard 0.18 µm CMOS process, and the measurement result shows that a minimum input voltage of 190 mV is achieved and output power increases by 181% compared with the conventional forward-body-bias scheme at a 300 mV input voltage. The proposed scheme achieves a maximum efficiency of 59.2% when the input voltage is 390 mV and the output current is 320 nA. The proposed circuit is suitable as a start-up circuit in ultralow power energy harvesting power management applications to boost-up from below threshold voltage.

Degradation of CMOS image sensors in deep-submicron technology due to γ-irradiation

NASA Astrophysics Data System (ADS)

Rao, Padmakumar R.; Wang, Xinyang; Theuwissen, Albert J. P.

2008-09-01

In this work, radiation induced damage mechanisms in deep submicron technology is resolved using finger gated-diodes (FGDs) as a radiation sensitive tool. It is found that these structures are simple yet efficient structures to resolve radiation induced damage in advanced CMOS processes. The degradation of the CMOS image sensors in deep-submicron technology due to γ-ray irradiation is studied by developing a model for the spectral response of the sensor and also by the dark-signal degradation as a function of STI (shallow-trench isolation) parameters. It is found that threshold shifts in the gate-oxide/silicon interface as well as minority carrier life-time variations in the silicon bulk are minimal. The top-layer material properties and the photodiode Si-SiO2 interface quality are degraded due to γ-ray irradiation. Results further suggest that p-well passivated structures are inevitable for radiation-hard designs. It was found that high electrical fields in submicron technologies pose a threat to high quality imaging in harsh environments.

A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices.

PubMed

Hashemi, S Saeid; Sawan, Mohamad; Savaria, Yvon

2012-08-01

We present, in this paper, a new full-wave CMOS rectifier dedicated for wirelessly-powered low-voltage biomedical implants. It uses bootstrapped capacitors to reduce the effective threshold voltage of selected MOS switches. It achieves a significant increase in its overall power efficiency and low voltage-drop. Therefore, the rectifier is good for applications with low-voltage power supplies and large load current. The rectifier topology does not require complex circuit design. The highest voltages available in the circuit are used to drive the gates of selected transistors in order to reduce leakage current and to lower their channel on-resistance, while having high transconductance. The proposed rectifier was fabricated using the standard TSMC 0.18 μm CMOS process. When connected to a sinusoidal source of 3.3 V peak amplitude, it allows improving the overall power efficiency by 11% compared to the best recently published results given by a gate cross-coupled-based structure.

A CMOS-Compatible, Low-Noise ISFET Based on High Efficiency Ion-Modulated Lateral-Bipolar Conduction

PubMed Central

Chang, Sheng-Ren; Chen, Hsin

2009-01-01

Ion-sensitive, field-effect transistors (ISFET) have been useful biosensors in many applications. However, the signal-to-noise ratio of the ISFET is limited by its intrinsic, low-frequency noise. This paper presents an ISFET capable of utilizing lateral-bipolar conduction to reduce low-frequency noise. With a particular layout design, the conduction efficiency is further enhanced. Moreover, the ISFET is compatible with the standard CMOS technology. All materials above the gate-oxide are removed by simple, die-level post-CMOS process, allowing ions to modulate the lateral-bipolar current directly. By varying the gate-to-bulk voltage, the operation mode of the ISFET is controlled effectively, so is the noise performance measured and compared. Finally, the biasing conditions preferable for different low-noise applications are identified. Under the identified biasing condition, the signal-to-noise ratio of the ISFET as a pH sensor is proved to be improved by more than five times. PMID:22408508

Design of transient light signal simulator based on FPGA

NASA Astrophysics Data System (ADS)

Kang, Jing; Chen, Rong-li; Wang, Hong

2014-11-01

A design scheme of transient light signal simulator based on Field Programmable gate Array (FPGA) was proposed in this paper. Based on the characteristics of transient light signals and measured feature points of optical intensity signals, a fitted curve was created in MATLAB. And then the wave data was stored in a programmed memory chip AT29C1024 by using SUPERPRO programmer. The control logic was realized inside one EP3C16 FPGA chip. Data readout, data stream cache and a constant current buck regulator for powering high-brightness LEDs were all controlled by FPGA. A 12-Bit multiplying CMOS digital-to-analog converter (DAC) DAC7545 and an amplifier OPA277 were used to convert digital signals to voltage signals. A voltage-controlled current source constituted by a NPN transistor and an operational amplifier controlled LED array diming to achieve simulation of transient light signal. LM3405A, 1A Constant Current Buck Regulator for Powering LEDs, was used to simulate strong background signal in space. Experimental results showed that the scheme as a transient light signal simulator can satisfy the requests of the design stably.

High performance pipelined multiplier with fast carry-save adder

NASA Technical Reports Server (NTRS)

Wu, Angus

1990-01-01

A high-performance pipelined multiplier is described. Its high performance results from the fast carry-save adder basic cell which has a simple structure and is suitable for the Gate Forest semi-custom environment. The carry-save adder computes the sum and carry within two gate delay. Results show that the proposed adder can operate at 200 MHz for a 2-micron CMOS process; better performance is expected in a Gate Forest realization.

The fabrication of a programmable via using phase-change material in CMOS-compatible technology.

PubMed

Chen, Kuan-Neng; Krusin-Elbaum, Lia

2010-04-02

We demonstrate an energy-efficient programmable via concept using indirectly heated phase-change material. This via structure has maximum phase-change volume to achieve a minimum on resistance for high performance logic applications. Process development and material investigations for this device structure are reported. The device concept is successfully demonstrated in a standard CMOS-compatible technology capable of multiple cycles between on/off states for reconfigurable applications.

Comparison of laser Doppler and laser speckle contrast imaging using a concurrent processing system

NASA Astrophysics Data System (ADS)

Sun, Shen; Hayes-Gill, Barrie R.; He, Diwei; Zhu, Yiqun; Huynh, Nam T.; Morgan, Stephen P.

2016-08-01

Full field laser Doppler imaging (LDI) and single exposure laser speckle contrast imaging (LSCI) are directly compared using a novel instrument which can concurrently image blood flow using both LDI and LSCI signal processing. Incorporating a commercial CMOS camera chip and a field programmable gate array (FPGA) the flow images of LDI and the contrast maps of LSCI are simultaneously processed by utilizing the same detected optical signals. The comparison was carried out by imaging a rotating diffuser. LDI has a linear response to the velocity. In contrast, LSCI is exposure time dependent and does not provide a linear response in the presence of static speckle. It is also demonstrated that the relationship between LDI and LSCI can be related through a power law which depends on the exposure time of LSCI.

Statistical Anomalies of Bitflips in SRAMs to Discriminate SBUs From MCUs

NASA Astrophysics Data System (ADS)

Clemente, Juan Antonio; Franco, Francisco J.; Villa, Francesca; Baylac, Maud; Rey, Solenne; Mecha, Hortensia; Agapito, Juan A.; Puchner, Helmut; Hubert, Guillaume; Velazco, Raoul

2016-08-01

Recently, the occurrence of multiple events in static tests has been investigated by checking the statistical distribution of the difference between the addresses of the words containing bitflips. That method has been successfully applied to Field Programmable Gate Arrays (FPGAs) and the original authors indicate that it is also valid for SRAMs. This paper presents a modified methodology that is based on checking the XORed addresses with bitflips, rather than on the difference. Irradiation tests on CMOS 130 & 90 nm SRAMs with 14-MeV neutrons have been performed to validate this methodology. Results in high-altitude environments are also presented and cross-checked with theoretical predictions. In addition, this methodology has also been used to detect modifications in the organization of said memories. Theoretical predictions have been validated with actual data provided by the manufacturer.

UVPROM dosimetry, microdosimetry and applications to SEU and extreme value theory

NASA Astrophysics Data System (ADS)

Scheick, Leif Zebediah

A new method is described for characterizing a device in terms of the statistical distribution of first failures. The method is based on the erasure of a commercial Ultra- Violet erasable Programmable Read Only Memory (UVPROM). The method of readout would be used on a spacecraft or in other restrictive radiation environments. The measurement of the charge remaining on the floating gate is used to determine absorbed dose. The method of determining dose does not require the detector to be destroyed or erased nor does it effect the ability for taking further measurements. This is compared to extreme value theory applied to the statistical distributions that apply to this device. This technique predicts the threshold of Single Event Effects (SEE), like anomalous changes in erasure time in programmable devices due to high microdose energy-deposition events. This technique also allows for advanced non-destructive, screening of a single microelectronic devices for predictable response in a stressful, i.e. radiation, environments.

Highly reliable top-gated thin-film transistor memory with semiconducting, tunneling, charge-trapping, and blocking layers all of flexible polymers.

PubMed

Wang, Wei; Hwang, Sun Kak; Kim, Kang Lib; Lee, Ju Han; Cho, Suk Man; Park, Cheolmin

2015-05-27

The core components of a floating-gate organic thin-film transistor nonvolatile memory (OTFT-NVM) include the semiconducting channel layer, tunneling layer, floating-gate layer, and blocking layer, besides three terminal electrodes. In this study, we demonstrated OTFT-NVMs with all four constituent layers made of polymers based on consecutive spin-coating. Ambipolar charges injected and trapped in a polymer electret charge-controlling layer upon gate program and erase field successfully allowed for reliable bistable channel current levels at zero gate voltage. We have observed that the memory performance, in particular the reliability of a device, significantly depends upon the thickness of both blocking and tunneling layers, and with an optimized layer thickness and materials selection, our device exhibits a memory window of 15.4 V, on/off current ratio of 2 × 10(4), read and write endurance cycles over 100, and time-dependent data retention of 10(8) s, even when fabricated on a mechanically flexible plastic substrate.

Rewritable ghost floating gates by tunnelling triboelectrification for two-dimensional electronics

PubMed Central

Kim, Seongsu; Kim, Tae Yun; Lee, Kang Hyuck; Kim, Tae-Ho; Cimini, Francesco Arturo; Kim, Sung Kyun; Hinchet, Ronan; Kim, Sang-Woo; Falconi, Christian

2017-01-01

Gates can electrostatically control charges inside two-dimensional materials. However, integrating independent gates typically requires depositing and patterning suitable insulators and conductors. Moreover, after manufacturing, gates are unchangeable. Here we introduce tunnelling triboelectrification for localizing electric charges in very close proximity of two-dimensional materials. As representative materials, we use chemical vapour deposition graphene deposited on a SiO2/Si substrate. The triboelectric charges, generated by friction with a Pt-coated atomic force microscope tip and injected through defects, are trapped at the air–SiO2 interface underneath graphene and act as ghost floating gates. Tunnelling triboelectrification uniquely permits to create, modify and destroy p and n regions at will with the spatial resolution of atomic force microscopes. As a proof of concept, we draw rewritable p/n+ and p/p+ junctions with resolutions as small as 200 nm. Our results open the way to time-variant two-dimensional electronics where conductors, p and n regions can be defined on demand. PMID:28649986

Rewritable ghost floating gates by tunnelling triboelectrification for two-dimensional electronics

NASA Astrophysics Data System (ADS)

Kim, Seongsu; Kim, Tae Yun; Lee, Kang Hyuck; Kim, Tae-Ho; Cimini, Francesco Arturo; Kim, Sung Kyun; Hinchet, Ronan; Kim, Sang-Woo; Falconi, Christian

2017-06-01

Gates can electrostatically control charges inside two-dimensional materials. However, integrating independent gates typically requires depositing and patterning suitable insulators and conductors. Moreover, after manufacturing, gates are unchangeable. Here we introduce tunnelling triboelectrification for localizing electric charges in very close proximity of two-dimensional materials. As representative materials, we use chemical vapour deposition graphene deposited on a SiO2/Si substrate. The triboelectric charges, generated by friction with a Pt-coated atomic force microscope tip and injected through defects, are trapped at the air-SiO2 interface underneath graphene and act as ghost floating gates. Tunnelling triboelectrification uniquely permits to create, modify and destroy p and n regions at will with the spatial resolution of atomic force microscopes. As a proof of concept, we draw rewritable p/n+ and p/p+ junctions with resolutions as small as 200 nm. Our results open the way to time-variant two-dimensional electronics where conductors, p and n regions can be defined on demand.

Photoresponses in Gold Nanoparticle Single-Electron Transistors with Molecular Floating Gates

NASA Astrophysics Data System (ADS)

Noguchi, Yutaka; Yamamoto, Makoto; Ishii, Hisao; Ueda, Rieko; Terui, Toshifumi; Imazu, Keisuke; Tamada, Kaoru; Sakano, Takeshi; Matsuda, Kenji

2013-11-01

We have proposed a simple method of activating advanced functions in single-electron transistors (SETs) based on the specific properties of individual molecules. As a prototype, we fabricated a copper phthalocyanine (CuPc)-doped SET. The device consists of a gold-nanoparticle (GNP)-based SET doped with CuPc as a photoresponsive floating gate. In this paper, we report the details of the photoresponses of the CuPc-doped SET, such as conductance switching, sensitivity to the wavelength of the incident light, and multiple induced states.

Upsets in Erased Floating Gate Cells With High-Energy Protons

DOE PAGES

Gerardin, S.; Bagatin, M.; Paccagnella, A.; ...

2017-01-01

We discuss upsets in erased floating gate cells, due to large threshold voltage shifts, using statistical distributions collected on a large number of memory cells. The spread in the neutral threshold voltage appears to be too low to quantitatively explain the experimental observations in terms of simple charge loss, at least in SLC devices. The possibility that memories exposed to high energy protons and heavy ions exhibit negative charge transfer between programmed and erased cells is investigated, although the analysis does not provide conclusive support to this hypothesis.

High speed CMOS acquisition system based on FPGA embedded image processing for electro-optical measurements

NASA Astrophysics Data System (ADS)

Rosu-Hamzescu, Mihnea; Polonschii, Cristina; Oprea, Sergiu; Popescu, Dragos; David, Sorin; Bratu, Dumitru; Gheorghiu, Eugen

2018-06-01

Electro-optical measurements, i.e., optical waveguides and plasmonic based electrochemical impedance spectroscopy (P-EIS), are based on the sensitive dependence of refractive index of electro-optical sensors on surface charge density, modulated by an AC electrical field applied to the sensor surface. Recently, P-EIS has emerged as a new analytical tool that can resolve local impedance with high, optical spatial resolution, without using microelectrodes. This study describes a high speed image acquisition and processing system for electro-optical measurements, based on a high speed complementary metal-oxide semiconductor (CMOS) sensor and a field-programmable gate array (FPGA) board. The FPGA is used to configure CMOS parameters, as well as to receive and locally process the acquired images by performing Fourier analysis for each pixel, deriving the real and imaginary parts of the Fourier coefficients for the AC field frequencies. An AC field generator, for single or multi-sine signals, is synchronized with the high speed acquisition system for phase measurements. The system was successfully used for real-time angle-resolved electro-plasmonic measurements from 30 Hz up to 10 kHz, providing results consistent to ones obtained by a conventional electrical impedance approach. The system was able to detect amplitude variations with a relative variation of ±1%, even for rather low sampling rates per period (i.e., 8 samples per period). The PC (personal computer) acquisition and control software allows synchronized acquisition for multiple FPGA boards, making it also suitable for simultaneous angle-resolved P-EIS imaging.

The GaN trench gate MOSFET with floating islands: High breakdown voltage and improved BFOM

NASA Astrophysics Data System (ADS)

Shen, Lingyan; Müller, Stephan; Cheng, Xinhong; Zhang, Dongliang; Zheng, Li; Xu, Dawei; Yu, Yuehui; Meissner, Elke; Erlbacher, Tobias

2018-02-01

A novel GaN trench gate (TG) MOSFET with P-type floating islands (FLI) in drift region, which can suppress the electric field peak at bottom of gate trench during the blocking state and prevent premature breakdown in gate oxide, is proposed and investigated by TCAD simulations. The influence of thickness, position, doping concentration and length of the FLI on breakdown voltage (BV) and specific on-resistance (Ron_sp) is studied, providing useful guidelines for design of this new type of device. Using optimized parameters for the FLI, GaN FLI TG-MOSFET obtains a BV as high as 2464 V with a Ron_sp of 3.0 mΩ cm2. Compared to the conventional GaN TG-MOSFET with the same structure parameters, the Baliga figure of merit (BFOM) is enhanced by 150%, getting closer to theoretical limit for GaN devices.

Flexible CMOS-Like Circuits Based on Printed P-Type and N-Type Carbon Nanotube Thin-Film Transistors.

PubMed

Zhang, Xiang; Zhao, Jianwen; Dou, Junyan; Tange, Masayoshi; Xu, Weiwei; Mo, Lixin; Xie, Jianjun; Xu, Wenya; Ma, Changqi; Okazaki, Toshiya; Cui, Zheng

2016-09-01

P-type and n-type top-gate carbon nanotube thin-film transistors (TFTs) can be selectively and simultaneously fabricated on the same polyethylene terephthalate (PET) substrate by tuning the types of polymer-sorted semiconducting single-walled carbon nanotube (sc-SWCNT) inks, along with low temperature growth of HfO 2 thin films as shared dielectric layers. Both the p-type and n-type TFTs show good electrical properties with on/off ratio of ≈10 5 , mobility of ≈15 cm 2 V -1 s -1 , and small hysteresis. Complementary metal oxide semiconductor (CMOS)-like logic gates and circuits based on as-prepared p-type and n-type TFTs have been achieved. Flexible CMOS-like inverters exhibit large noise margin of 84% at low voltage (1/2 V dd = 1.5 V) and maximum voltage gain of 30 at V dd of 1.5 V and low power consumption of 0.1 μW. Both of the noise margin and voltage gain are one of the best values reported for flexible CMOS-like inverters at V dd less than 2 V. The printed CMOS-like inverters work well at 10 kHz with 2% voltage loss and delay time of ≈15 μs. A 3-stage ring oscillator has also been demonstrated on PET substrates and the oscillation frequency of 3.3 kHz at V dd of 1 V is achieved. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Hybrid CMOS/Molecular Integrated Circuits

NASA Astrophysics Data System (ADS)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

A Low Power and High Throughput Self Synchronous FPGA Using 65nm CMOS with Throughput Optimization by Pipeline Alignment

NASA Astrophysics Data System (ADS)

Stefan Devlin, Benjamin; Nakura, Toru; Ikeda, Makoto; Asada, Kunihiro

We detail a self synchronous field programmable gate array (SSFPGA) with dual-pipeline (DP) architecture to conceal pre-charge time for dynamic logic, and its throughput optimization by using pipeline alignment implemented on benchmark circuits. A self synchronous LUT (SSLUT) consists of a three input tree-type structure with 8bits of SRAM for programming. A self synchronous switch box (SSSB) consists of both pass transistors and buffers to route signals, with 12bits of SRAM. One common block with one SSLUT and one SSSB occupies 2.2Mλ2 area with 35bits of SRAM, and the prototype SSFPGA with 34 × 30 (1020) blocks is designed and fabricated using 65nm CMOS. Measured results show at 1.2V 430MHz and 647MHz operation for a 3bit ripple carry adder, without and with throughput optimization, respectively. We find that using the proposed pipeline alignment techniques we can perform at maximum throughput of 647MHz in various benchmarks on the SSFPGA. We demonstrate up to 56.1 times throughput improvement with our pipeline alignment techniques. The pipeline alignment is carried out within the number of logic elements in the array and pipeline buffers in the switching matrix.

High-speed line-scan camera with digital time delay integration

NASA Astrophysics Data System (ADS)

Bodenstorfer, Ernst; Fürtler, Johannes; Brodersen, Jörg; Mayer, Konrad J.; Eckel, Christian; Gravogl, Klaus; Nachtnebel, Herbert

2007-02-01

Dealing with high-speed image acquisition and processing systems, the speed of operation is often limited by the amount of available light, due to short exposure times. Therefore, high-speed applications often use line-scan cameras, based on charge-coupled device (CCD) sensors with time delayed integration (TDI). Synchronous shift and accumulation of photoelectric charges on the CCD chip - according to the objects' movement - result in a longer effective exposure time without introducing additional motion blur. This paper presents a high-speed color line-scan camera based on a commercial complementary metal oxide semiconductor (CMOS) area image sensor with a Bayer filter matrix and a field programmable gate array (FPGA). The camera implements a digital equivalent to the TDI effect exploited with CCD cameras. The proposed design benefits from the high frame rates of CMOS sensors and from the possibility of arbitrarily addressing the rows of the sensor's pixel array. For the digital TDI just a small number of rows are read out from the area sensor which are then shifted and accumulated according to the movement of the inspected objects. This paper gives a detailed description of the digital TDI algorithm implemented on the FPGA. Relevant aspects for the practical application are discussed and key features of the camera are listed.

AC signal characterization for optimization of a CMOS single-electron pump

NASA Astrophysics Data System (ADS)

Murray, Roy; Perron, Justin K.; Stewart, M. D., Jr.; Zimmerman, Neil M.

2018-02-01

Pumping single electrons at a set rate is being widely pursued as an electrical current standard. Semiconductor charge pumps have been pursued in a variety of modes, including single gate ratchet, a variety of 2-gate ratchet pumps, and 2-gate turnstiles. Whether pumping with one or two AC signals, lower error rates can result from better knowledge of the properties of the AC signal at the device. In this work, we operated a CMOS single-electron pump with a 2-gate ratchet style measurement and used the results to characterize and optimize our two AC signals. Fitting this data at various frequencies revealed both a difference in signal path length and attenuation between our two AC lines. Using this data, we corrected for the difference in signal path length and attenuation by applying an offset in both the phase and the amplitude at the signal generator. Operating the device as a turnstile while using the optimized parameters determined from the 2-gate ratchet measurement led to much flatter, more robust charge pumping plateaus. This method was useful in tuning our device up for optimal charge pumping, and may prove useful to the semiconductor quantum dot community to determine signal attenuation and path differences at the device.

Performance of a 512 x 512 Gated CMOS Imager with a 250 ps Exposure Time

DOE Office of Scientific and Technical Information (OSTI.GOV)

Teruya, A T; Moody, J D; Hsing, W W

2012-10-01

We describe the performance of a 512x512 gated CMOS read out integrated circuit (ROIC) with a 250 ps exposure time. A low-skew, H-tree trigger distribution system is used to locally generate individual pixel gates in each 8x8 neighborhood of the ROIC. The temporal width of the gate is voltage controlled and user selectable via a precision potentiometer. The gating implementation was first validated in optical tests of a 64x64 pixel prototype ROIC developed as a proof-of-concept during the early phases of the development program. The layout of the H-Tree addresses each quadrant of the ROIC independently and admits operation ofmore » the ROIC in two modes. If “common mode” triggering is used, the camera provides a single 512x512 image. If independent triggers are used, the camera can provide up to four 256x256 images with a frame separation set by the trigger intervals. The ROIC design includes small (sub-pixel) optical photodiode structures to allow test and characterization of the ROIC using optical sources prior to bump bonding. Reported test results were obtained using short pulse, second harmonic Ti:Sapphire laser systems operating at λ~ 400 nm at sub-ps pulse widths.« less

CAOS-CMOS camera.

PubMed

Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

2016-06-13

Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

NASA Astrophysics Data System (ADS)

Ishii, Yuichiro; Tanaka, Miki; Yabuuchi, Makoto; Sawada, Yohei; Tanaka, Shinji; Nii, Koji; Lu, Tien Yu; Huang, Chun Hsien; Sian Chen, Shou; Tse Kuo, Yu; Lung, Ching Cheng; Cheng, Osbert

2018-04-01

We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (I read) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (V min) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

A CMOS matrix for extracting MOSFET parameters before and after irradiation

NASA Technical Reports Server (NTRS)

Blaes, B. R.; Buehler, M. G.; Lin, Y.-S.; Hicks, K. A.

1988-01-01

An addressable matrix of 16 n- and 16 p-MOSFETs was designed to extract the dc MOSFET parameters for all dc gate bias conditions before and after irradiation. The matrix contains four sets of MOSFETs, each with four different geometries that can be biased independently. Thus the worst-case bias scenarios can be determined. The MOSFET matrix was fabricated at a silicon foundry using a radiation-soft CMOS p-well LOCOS process. Co-60 irradiation results for the n-MOSFETs showed a threshold-voltage shift of -3 mV/krad(Si), whereas the p-MOSFETs showed a shift of 21 mV/krad(Si). The worst-case threshold-voltage shift occurred for the n-MOSFETs, with a gate bias of 5 V during the anneal. For the p-MOSFETs, biasing did not affect the shift in the threshold voltage. A parasitic MOSFET dominated the leakage of the n-MOSFET biased with 5 V on the gate during irradiation. Co-60 test results for other parameters are also presented.

Fundamental performance differences between CMOS and CCD imagers, part IV

NASA Astrophysics Data System (ADS)

Janesick, James; Pinter, Jeff; Potter, Robert; Elliott, Tom; Andrews, James; Tower, John; Grygon, Mark; Keller, Dave

2010-07-01

This paper is a continuation of past papers written on fundamental performance differences of scientific CMOS and CCD imagers. New characterization results presented below include: 1). a new 1536 × 1536 × 8μm 5TPPD pixel CMOS imager, 2). buried channel MOSFETs for random telegraph noise (RTN) and threshold reduction, 3) sub-electron noise pixels, 4) 'MIM pixel' for pixel sensitivity (V/e-) control, 5) '5TPPD RING pixel' for large pixel, high-speed charge transfer applications, 6) pixel-to-pixel blooming control, 7) buried channel photo gate pixels and CMOSCCDs, 8) substrate bias for deep depletion CMOS imagers, 9) CMOS dark spikes and dark current issues and 10) high energy radiation damage test data. Discussions are also given to a 1024 × 1024 × 16 um 5TPPD pixel imager currently in fabrication and new stitched CMOS imagers that are in the design phase including 4k × 4k × 10 μm and 10k × 10k × 10 um imager formats.

3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate

NASA Astrophysics Data System (ADS)

Oh, Jae-Sub; Yang, Seong-Dong; Lee, Sang-Youl; Kim, Young-Su; Kang, Min-Ho; Lim, Sung-Kyu; Lee, Hi-Deok; Lee, Ga-Won

2013-08-01

In this paper, a gate-all-around bandgap-engineered silicon-oxide-nitride-oxide-silicon device with a vertical silicon pillar structure and a Ti metal gate are demonstrated for a potential solution to overcome the scaling-down of flash memory device. The devices were fabricated using CMOS-compatible technology and exhibited well-behaved memory characteristics in terms of the program/erase window, retention, and endurance properties. Moreover, the integration of the Ti metal gate demonstrated a significant improvement in the erase characteristics due to the efficient suppression of the electron back tunneling through the blocking oxide.

CMOS Imager Has Better Cross-Talk and Full-Well Performance

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas J.

2011-01-01

A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.

Field Programmable Gate Array Control of Power Systems in Graduate Student Laboratories

DTIC Science & Technology

2008-03-01

NAVAL POSTGRADUATE SCHOOL MONTEREY, CALIFORNIA THESIS Approved for public release; distribution is unlimited FIELD PROGRAMMABLE...REPORT TYPE AND DATES COVERED Master’s Thesis 4. TITLE AND SUBTITLE Field Programmable Gate Array Control of Power Systems in Graduate Student...Electronics curriculum track is the development of a design center that explores Field Programmable Gate Array (FPGA) control of power electronics

Environmental Effects on Data Retention in Flash Cells

NASA Technical Reports Server (NTRS)

Katz, Rich; Flowers, David; Bergevin, Keith

2017-01-01

Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Antifuse technology, prevalent in non-volatile field programmable gate arrays (FPGAs), will eventually be phased out as new devices have not been developed for approximately a decade. The reliance on flash technology presents a long-term reliability issue for both DoD and NASA safety- and mission-critical applications. A thorough understanding of the data retention failure modes and statistics associated with Flash data retention is of vital concern to the fuze safety community. A key retention parameter for a flash cell is the threshold voltage (VTH), which is an indirect indicator of the amount of charge stored on the cells floating gate. This paper will present the results of our on-going tests: long-term storage at 150 C for a small population of devices, neutron radiation exposure, electrostatic discharge (ESD) testing, and the trends of large populations (over 300 devices for each condition) exposed to three difference temperatures: 25 C, 125 C, and 150 C.

Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for AdvancedCMOS Devices

PubMed Central

Suzuki, Masamichi

2012-01-01

A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3) high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT) of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al) atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process. PMID:28817057

A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

PubMed

Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

2016-08-01

This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process.

A CMOS Time-Resolved Fluorescence Lifetime Analysis Micro-System

PubMed Central

Rae, Bruce R.; Muir, Keith R.; Gong, Zheng; McKendry, Jonathan; Girkin, John M.; Gu, Erdan; Renshaw, David; Dawson, Martin D.; Henderson, Robert K.

2009-01-01

We describe a CMOS-based micro-system for time-resolved fluorescence lifetime analysis. It comprises a 16 × 4 array of single-photon avalanche diodes (SPADs) fabricated in 0.35 μm high-voltage CMOS technology with in-pixel time-gated photon counting circuitry and a second device incorporating an 8 × 8 AlInGaN blue micro-pixellated light-emitting diode (micro-LED) array bump-bonded to an equivalent array of LED drivers realized in a standard low-voltage 0.35 μm CMOS technology, capable of producing excitation pulses with a width of 777 ps (FWHM). This system replaces instrumentation based on lasers, photomultiplier tubes, bulk optics and discrete electronics with a PC-based micro-system. Demonstrator lifetime measurements of colloidal quantum dot and Rhodamine samples are presented. PMID:22291564

Numerical model of a single nanocrystal devoted to the study of disordered nanocrystal floating gates of new flash memories

NASA Astrophysics Data System (ADS)

Leroy, Yann; Armeanu, Dumitru; Cordan, Anne-Sophie

2011-05-01

The improvement of our model concerning a single nanocrystal that belongs to a nanocrystal floating gate of a flash memory is presented. In order to extend the gate voltage range applicability of the model, the 3D continuum of states of either metallic or semiconducting electrodes is discretized into 2D subbands. Such an approach gives precise information about the mechanisms behind the charging or release processes of the nanocrystal. Then, the self-energy and screening effects of an electron within the nanocrystal are evaluated and introduced in the model. This enables a better determination of the operating point of the nanocrystal memory. The impact of those improvements on the charging or release time of the nanocrystal is discussed.

Verilog-A Device Models for Cryogenic Temperature Operation of Bulk Silicon CMOS Devices

NASA Technical Reports Server (NTRS)

Akturk, Akin; Potbhare, Siddharth; Goldsman, Neil; Holloway, Michael

2012-01-01

Verilog-A based cryogenic bulk CMOS (complementary metal oxide semiconductor) compact models are built for state-of-the-art silicon CMOS processes. These models accurately predict device operation at cryogenic temperatures down to 4 K. The models are compatible with commercial circuit simulators. The models extend the standard BSIM4 [Berkeley Short-channel IGFET (insulated-gate field-effect transistor ) Model] type compact models by re-parameterizing existing equations, as well as adding new equations that capture the physics of device operation at cryogenic temperatures. These models will allow circuit designers to create optimized, reliable, and robust circuits operating at cryogenic temperatures.

Mechanistic analysis of temperature-dependent current conduction through thin tunnel oxide in n+-polySi/SiO2/n+-Si structures

NASA Astrophysics Data System (ADS)

Samanta, Piyas

2017-09-01

We present a detailed investigation on temperature-dependent current conduction through thin tunnel oxides grown on degenerately doped n-type silicon (n+-Si) under positive bias ( VG ) on heavily doped n-type polycrystalline silicon (n+-polySi) gate in metal-oxide-semiconductor devices. The leakage current measured between 298 and 573 K and at oxide fields ranging from 6 to 10 MV/cm is primarily attributed to Poole-Frenkel (PF) emission of trapped electrons from the neutral electron traps located in the silicon dioxide (SiO2) band gap in addition to Fowler-Nordheim (FN) tunneling of electrons from n+-Si acting as the drain node in FLOating gate Tunnel OXide Electrically Erasable Programmable Read-Only Memory devices. Process-induced neutral electron traps are located at 0.18 eV and 0.9 eV below the SiO2 conduction band. Throughout the temperature range studied here, PF emission current IPF dominates FN electron tunneling current IFN at oxide electric fields Eox between 6 and 10 MV/cm. A physics based new analytical formula has been developed for FN tunneling of electrons from the accumulation layer of degenerate semiconductors at a wide range of temperatures incorporating the image force barrier rounding effect. FN tunneling has been formulated in the framework of Wentzel-Kramers-Brilloiun taking into account the correction factor due to abrupt variation of the energy barrier at the cathode/oxide interface. The effect of interfacial and near-interfacial trapped-oxide charges on FN tunneling has also been investigated in detail at positive VG . The mechanism of leakage current conduction through SiO2 films plays a crucial role in simulation of time-dependent dielectric breakdown of the memory devices and to precisely predict the normal operating field or applied floating gate (FG) voltage for lifetime projection of the devices. In addition, we present theoretical results showing the effect of drain doping concentration on the FG leakage current.

A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA

NASA Astrophysics Data System (ADS)

Zhujia, Chen; Haigang, Yang; Fei, Liu; Yu, Wang

2011-10-01

A fast-locking all-digital delay-locked loop (ADDLL) is proposed for the DDR SDRAM controller interface in a field programmable gate array (FPGA). The ADDLL performs a 90° phase-shift so that the data strobe (DQS) can enlarge the data valid window in order to minimize skew. In order to further reduce the locking time and to prevent the harmonic locking problem, a time-to-digital converter (TDC) is proposed. A duty cycle corrector (DCC) is also designed in the ADDLL to adjust the output duty cycle to 50%. The ADDLL, implemented in a commercial 0.13 μm CMOS process, occupies a total of 0.017 mm2 of active area. Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps. The time interval error (TIE) of the proposed circuit is 60.7 ps.

Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics

NASA Astrophysics Data System (ADS)

Seto, Daisaku; Watanabe, Minoru

2015-09-01

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 × 104 times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and high-speed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation.

Theory of the synchronous motion of an array of floating flap gates oscillating wave surge converter

NASA Astrophysics Data System (ADS)

Michele, Simone; Sammarco, Paolo; d'Errico, Michele

2016-08-01

We consider a finite array of floating flap gates oscillating wave surge converter (OWSC) in water of constant depth. The diffraction and radiation potentials are solved in terms of elliptical coordinates and Mathieu functions. Generated power and capture width ratio of a single gate excited by incoming waves are given in terms of the radiated wave amplitude in the far field. Similar to the case of axially symmetric absorbers, the maximum power extracted is shown to be directly proportional to the incident wave characteristics: energy flux, angle of incidence and wavelength. Accordingly, the capture width ratio is directly proportional to the wavelength, thus giving a design estimate of the maximum efficiency of the system. We then compare the array and the single gate in terms of energy production. For regular waves, we show that excitation of the out-of-phase natural modes of the array increases the power output, while in the case of random seas we show that the array and the single gate achieve the same efficiency.

Oleyl group-functionalized insulating gate transistors for measuring extracellular pH of floating cells

NASA Astrophysics Data System (ADS)

Imaizumi, Yuki; Goda, Tatsuro; Toya, Yutaro; Matsumoto, Akira; Miyahara, Yuji

2016-01-01

The extracellular ionic microenvironment has a close relationship to biological activities such as by cellular respiration, cancer development, and immune response. A system composed of ion-sensitive field-effect transistors (ISFET), cells, and program-controlled fluidics has enabled the acquisition of real-time information about the integrity of the cell membrane via pH measurement. Here we aimed to extend this system toward floating cells such as T lymphocytes for investigating complement activation and pharmacokinetics through alternations in the plasma membrane integrity. We functionalized the surface of tantalum oxide gate insulator of ISFET with oleyl-tethered phosphonic acid for interacting with the plasma membranes of floating cells without affecting the cell signaling. The surface modification was characterized by X-ray photoelectron spectroscopy and water contact angle measurements. The Nernst response of -37.8 mV/pH was obtained for the surface-modified ISFET at 37 °C. The oleyl group-functionalized gate insulator successfully captured Jurkat T cells in a fluidic condition without acute cytotoxicity. The system was able to record the time course of pH changes at the cells/ISFET interface during the process of instant addition and withdrawal of ammonium chloride. Further, the plasma membrane injury of floating cells after exposure by detergent Triton™ X-100 was successfully determined using the modified ISFET with enhanced sensitivity as compared with conventional hemolysis assays.

Oleyl group-functionalized insulating gate transistors for measuring extracellular pH of floating cells

PubMed Central

Imaizumi, Yuki; Goda, Tatsuro; Toya, Yutaro; Matsumoto, Akira; Miyahara, Yuji

2016-01-01

Abstract The extracellular ionic microenvironment has a close relationship to biological activities such as by cellular respiration, cancer development, and immune response. A system composed of ion-sensitive field-effect transistors (ISFET), cells, and program-controlled fluidics has enabled the acquisition of real-time information about the integrity of the cell membrane via pH measurement. Here we aimed to extend this system toward floating cells such as T lymphocytes for investigating complement activation and pharmacokinetics through alternations in the plasma membrane integrity. We functionalized the surface of tantalum oxide gate insulator of ISFET with oleyl-tethered phosphonic acid for interacting with the plasma membranes of floating cells without affecting the cell signaling. The surface modification was characterized by X-ray photoelectron spectroscopy and water contact angle measurements. The Nernst response of −37.8 mV/pH was obtained for the surface-modified ISFET at 37 °C. The oleyl group-functionalized gate insulator successfully captured Jurkat T cells in a fluidic condition without acute cytotoxicity. The system was able to record the time course of pH changes at the cells/ISFET interface during the process of instant addition and withdrawal of ammonium chloride. Further, the plasma membrane injury of floating cells after exposure by detergent Triton™ X-100 was successfully determined using the modified ISFET with enhanced sensitivity as compared with conventional hemolysis assays. PMID:27877886

Off-line wafer level reliability control: unique measurement method to monitor the lifetime indicator of gate oxide validated within bipolar/CMOS/DMOS technology

NASA Astrophysics Data System (ADS)

Gagnard, Xavier; Bonnaud, Olivier

2000-08-01

We have recently published a paper on a new rapid method for the determination of the lifetime of the gate oxide involved in a Bipolar/CMOS/DMOS technology (BCD). Because this previous method was based on a current measurement with gate voltage as a parameter needing several stress voltages, it was applied only by lot sampling. Thus, we tried to find an indicator in order to monitor the gate oxide lifetime during the wafer level parametric test and involving only one measurement of the device on each wafer test cell. Using the Weibull law and Crook model, combined with our recent model, we have developed a new test method needing only one electrical measurement of MOS capacitor to monitor the quality of the gate oxide. Based also on a current measurement, the parameter is the lifetime indicator of the gate oxide. From the analysis of several wafers, we gave evidence of the possibility to detect a low performance wafer, which corresponds to the infantile failure on the Weibull plot. In order to insert this new method in the BCD parametric program, a parametric flowchart was established. This type of measurement is an important challenges, because the actual measurements, breakdown charge, Qbd, and breakdown electric field, Ebd, at parametric level and Ebd and interface states density, Dit during the process cannot guarantee the gate oxide lifetime all along fabrication process. This indicator measurement is the only one, which predicts the lifetime decrease.

Electrical overstress in AlGaN/GaN HEMTs: study of degradation processes

NASA Astrophysics Data System (ADS)

Kuzmík, J.; Pogany, D.; Gornik, E.; Javorka, P.; Kordoš, P.

2004-02-01

We study degradation mechanisms in 50 μm gate width/0.45 μm length AlGaN/GaN HEMTs after electrical overstresses. One hundred nanosecond long rectangular current pulses are applied on the drain contact keeping either both of the source and gate grounded or the source grounded and gate floating. Source-drain pulsed I- V characteristics show similar shape for both connections. After the HEMT undergoes the source-drain breakdown, a negative differential resistance region transits into a low voltage/high current region. Changes in the Schottky contact dc I- V characteristics and in the source and drain ohmic contacts are investigated as a function of the current stress level and are related to the HEMT dc performance. Catastrophic HEMT degradation was observed after Istress=1.65 A in case of the 'gate floating' connection due to ohmic contacts burnout. In case of the 'gate grounded' connection, Istress=0.45 A was sufficient for the gate failure showing a high gate susceptibility to overstress. Backside transient interferometric mapping technique experiment reveals a current filament formation under both HEMT stress connections. Infrared camera observations lead to conclusion that the filament formation together with a consequent high-density electron flow is responsible for a dark spot formation and gradual ohmic contact degradation.

Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)

DOEpatents

Asaad, Sameh W; Bellofatto, Ralph E; Brezzo, Bernard; Haymes, Charles L; Kapur, Mohit; Parker, Benjamin D; Roewer, Thomas; Tierno, Jose A

2014-01-28

A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.

A novel double gate metal source/drain Schottky MOSFET as an inverter

NASA Astrophysics Data System (ADS)

Loan, Sajad A.; Kumar, Sunil; Alamoud, Abdulrahman M.

2016-03-01

In this work, we propose and simulate a novel structure of a double gate metal source/drain (MSD) Schottky MOSFET. The novelty of the proposed device is that it realizes a complete CMOS inverter action, which is actually being realized by the combination of two n and p type MOS transistors in the conventional CMOS technology. Therefore, the use of this device will significantly reduce the transistor count in implementing combinational and sequential circuits. Further, there is a significant reduction in the number of junctions and regions in the proposed device in comparison to the conventional CMOS inverter. Therefore, the proposed device is compact and can consume less power. The proposed device has been named as Sajad-Sunil-Schottky (SSS) device. The mixed mode circuit analysis of the proposed SSS device has shown that a CMOS inverter action with high logic level (VOH) and low logic level (VOL) as ∼VDD and ∼ground respectively. A two dimensional calibrated simulation study using the experimental data has revealed that the proposed SSS device in n and p type modes have subthreshold slopes (S) of 130 mV/decade and 85 mV/decade respectively and have reasonable high ION and ION/IOFF ratio's. Furthermore, it has been proved that such a device action cannot be realised by folding the conventional doped n and p MOS transistors.

Study of drain-extended NMOS under electrostatic discharge stress in 28 nm and 40 nm CMOS process

NASA Astrophysics Data System (ADS)

Wang, Weihuai; Jin, Hao; Dong, Shurong; Zhong, Lei; Han, Yan

2016-02-01

Researches on the electrostatic discharge (ESD) performance of drain-extended NMOS (DeNMOS) under the state-of-the-art 28 nm and 40 nm bulk CMOS process are performed in this paper. Three distinguishing phases of avalanche breakdown stage, depletion region push-out stage and parasitic NPN turn on stage of the gate-grounded DeNMOS (GG-DeNMOS) fabricated under 28 nm CMOS process measured with transmission line pulsing (TLP) test are analyzed through TCAD simulations and tape-out silicon verification detailedly. Damage mechanisms and failure spots of GG-DeNMOS under both CMOS processes are thermal breakdown of drain junction. Improvements based on the basic structure adjustments can increase the GG-DeNMOS robustness from original 2.87 mA/μm to the highest 5.41 mA/μm. Under 40 nm process, parameter adjustments based on the basic structure have no significant benefits on the robustness improvements. By inserting P+ segments in the N+ implantation of drain or an entire P+ strip between the N+ implantation of drain and polysilicon gate to form the typical DeMOS-SCR (silicon-controlled rectifier) structure, the ESD robustness can be enhanced from 1.83 mA/μm to 8.79 mA/μm and 29.78 mA/μm, respectively.

Design, development, fabrication and delivery of register and multiplexer units. [CMOS monolithic chip development

NASA Technical Reports Server (NTRS)

Feller, A.; Lombardi, T.

1978-01-01

Several approaches for implementing the register and multiplexer unit into two CMOS monolithic chip types were evaluated. The CMOS standard cell array technique was selected and implemented. Using this design automation technology, two LSI CMOS arrays were designed, fabricated, packaged, and tested for proper static, functional, and dynamic operation. One of the chip types, multiplexer register type 1, is fabricated on a 0.143 x 0.123 inch chip. It uses nine standard cell types for a total of 54 standard cells. This involves more than 350 transistors and has the functional equivalent of 111 gates. The second chip, multiplexer register type 2, is housed on a 0.12 x 0.12 inch die. It uses 13 standard cell types, for a total of 42 standard cells. It contains more than 300 transistors, the functional equivalent of 112 gates. All of the hermetically sealed units were initially screened for proper functional operation. The static leakage and the dynamic leakage were measured. Dynamic measurements were made and recorded. At 10 V, 14 megabit shifting rates were measured on multiplexer register type 1. At 5 V these units shifted data at a 6.6 MHz rate. The units were designed to operate over the 3 to 15 V operating range and over a temperature range of -55 to 125 C.

Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

NASA Astrophysics Data System (ADS)

Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

2016-05-01

In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

CMOS-compatible batch processing of monolayer MoS2 MOSFETs

NASA Astrophysics Data System (ADS)

Xiong, Kuanchen; Kim, Hyun; Marstell, Roderick J.; Göritz, Alexander; Wipf, Christian; Li, Lei; Park, Ji-Hoon; Luo, Xi; Wietstruck, Matthias; Madjar, Asher; Strandwitz, Nicholas C.; Kaynak, Mehmet; Lee, Young Hee; Hwang, James C. M.

2018-04-01

Thousands of high-performance 2D metal-oxide-semiconductor field effect transistors (MOSFETs) were fabricated on wafer-scale chemical vapor deposited MoS2 with fully-CMOS-compatible processes such as photolithography and aluminum metallurgy. The yield was greater than 50% in terms of effective gate control with less-than-10 V threshold voltage, even for MOSFETs having deep-submicron gate length. The large number of fabricated MOSFETs allowed statistics to be gathered and the main yield limiter to be attributed to the weak adhesion between the transferred MoS2 and the substrate. With cut-off frequencies approaching the gigahertz range, the performances of the MOSFETs were comparable to that of state-of-the-art MoS2 MOSFETs, whether the MoS2 was grown by a thin-film process or exfoliated from a bulk crystal.

Charge Transfer Inefficiency in Pinned Photodiode CMOS image sensors: Simple Montecarlo modeling and experimental measurement based on a pulsed storage-gate method

NASA Astrophysics Data System (ADS)

Pelamatti, Alice; Goiffon, Vincent; Chabane, Aziouz; Magnan, Pierre; Virmontois, Cédric; Saint-Pé, Olivier; de Boisanger, Michel Breart

2016-11-01

The charge transfer time represents the bottleneck in terms of temporal resolution in Pinned Photodiode (PPD) CMOS image sensors. This work focuses on the modeling and estimation of this key parameter. A simple numerical model of charge transfer in PPDs is presented. The model is based on a Montecarlo simulation and takes into account both charge diffusion in the PPD and the effect of potential obstacles along the charge transfer path. This work also presents a new experimental approach for the estimation of the charge transfer time, called pulsed Storage Gate (SG) method. This method, which allows reproduction of a ;worst-case; transfer condition, is based on dedicated SG pixel structures and is particularly suitable to compare transfer efficiency performances for different pixel geometries.

Charge transfer efficiency improvement of 4T pixel for high speed CMOS image sensor

NASA Astrophysics Data System (ADS)

Jin, Xiangliang; Liu, Weihui; Yang, Hongjiao; Tang, Lizhen; Yang, Jia

2015-03-01

The charge transfer efficiency improvement method is proposed by optimizing the electrical potential distribution along the transfer path from the PPD to the FD. In this work, we present a non-uniform doped transfer transistor channel, with the adjustments to the overlap length between the CPIA layer and the transfer gate, and the overlap length between the SEN layer and transfer gate. Theory analysis and TCAD simulation results show that the density of the residual charge reduces from 1e11 /cm3 to 1e9 /cm3, and the transfer time reduces from 500 ns to 143 ns, and the charge transfer efficiency is about 77 e-/ns. This optimizing design effectively improves the charge transfer efficiency of 4T pixel and the performance of 4T high speed CMOS image sensor.

Integrated imaging sensor systems with CMOS active pixel sensor technology

NASA Technical Reports Server (NTRS)

Yang, G.; Cunningham, T.; Ortiz, M.; Heynssens, J.; Sun, C.; Hancock, B.; Seshadri, S.; Wrigley, C.; McCarty, K.; Pain, B.

2002-01-01

This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.

Step-gate polysilicon nanowires field effect transistor compatible with CMOS technology for label-free DNA biosensor.

PubMed

Wenga, G; Jacques, E; Salaün, A-C; Rogel, R; Pichon, L; Geneste, F

2013-02-15

Currently, detection of DNA hybridization using fluorescence-based detection technique requires expensive optical systems and complex bioinformatics tools. Hence, the development of new low cost devices that enable direct and highly sensitive detection stimulates a lot of research efforts. Particularly, devices based on silicon nanowires are emerging as ultrasensitive electrical sensors for the direct detection of biological species thanks to their high surface to volume ratio. In this study, we propose innovative devices using step-gate polycrystalline silicon nanowire FET (poly-Si NW FETs), achieved with simple and low cost fabrication process, and used as ultrasensitive electronic sensor for DNA hybridization. The poly-SiNWs are synthesized using the sidewall spacer formation technique. The detailed fabrication procedure for a step-gate NWFET sensor is described in this paper. No-complementary and complementary DNA sequences were clearly discriminated and detection limit to 1 fM range is observed. This first result using this nano-device is promising for the development of low cost and ultrasensitive polysilicon nanowires based DNA sensors compatible with the CMOS technology. Copyright © 2012 Elsevier B.V. All rights reserved.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1982-01-01

The procedure used to generate MEBES masks and produce test wafers from the 10X Mann 1600 Pattern Generator Tape using existing CAD utility programs and the MEBES machine in the RCA Solid State Technology Center are described. The test vehicle used is the MSFC-designed SC102 Solar House Timing Circuit. When transforming the Mann 1600 tapes into MEBES tapes, extreme care is required in order to obtain accurate minimum linewidths when working with two different coding systems because the minimum grid sizes may be different for the two systems. The minimum grid sizes are 0.025 mil for MSFC Mann 1600 and 0.02 mil for MEBES. Some snapping to the next grid is therefore inevitable, and the results of this snapping effect are significant when submicron lines are present. However, no problem was noticed in the SC102 circuit because its minimum linewidth is 0.3 mil (7.6 microns). MEBES masks were fabricated and wafers were processed using the silicon-gate CMOS/SOS and aluminum-gate COS/MOS processing.

A high-speed two-frame, 1-2 ns gated X-ray CMOS imager used as a hohlraum diagnostic on the National Ignition Facility (invited).

PubMed

Chen, Hui; Palmer, N; Dayton, M; Carpenter, A; Schneider, M B; Bell, P M; Bradley, D K; Claus, L D; Fang, L; Hilsabeck, T; Hohenberger, M; Jones, O S; Kilkenny, J D; Kimmel, M W; Robertson, G; Rochau, G; Sanchez, M O; Stahoviak, J W; Trotter, D C; Porter, J L

2016-11-01

A novel x-ray imager, which takes time-resolved gated images along a single line-of-sight, has been successfully implemented at the National Ignition Facility (NIF). This Gated Laser Entrance Hole diagnostic, G-LEH, incorporates a high-speed multi-frame CMOS x-ray imager developed by Sandia National Laboratories to upgrade the existing Static X-ray Imager diagnostic at NIF. The new diagnostic is capable of capturing two laser-entrance-hole images per shot on its 1024 × 448 pixels photo-detector array, with integration times as short as 1.6 ns per frame. Since its implementation on NIF, the G-LEH diagnostic has successfully acquired images from various experimental campaigns, providing critical new information for understanding the hohlraum performance in inertial confinement fusion (ICF) experiments, such as the size of the laser entrance hole vs. time, the growth of the laser-heated gold plasma bubble, the change in brightness of inner beam spots due to time-varying cross beam energy transfer, and plasma instability growth near the hohlraum wall.

Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

NASA Astrophysics Data System (ADS)

McConkey, M. L.

1984-12-01

A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

Endurance degradation and lifetime model of p-channel floating gate flash memory device with 2T structure

NASA Astrophysics Data System (ADS)

Wei, Jiaxing; Liu, Siyang; Liu, Xiaoqiang; Sun, Weifeng; Liu, Yuwei; Liu, Xiaohong; Hou, Bo

2017-08-01

The endurance degradation mechanisms of p-channel floating gate flash memory device with two-transistor (2T) structure are investigated in detail in this work. With the help of charge pumping (CP) measurements and Sentaurus TCAD simulations, the damages in the drain overlap region along the tunnel oxide interface caused by band-to-band (BTB) tunneling programming and the damages in the channel region resulted from Fowler-Nordheim (FN) tunneling erasure are verified respectively. Furthermore, the lifetime model of endurance characteristic is extracted, which can extrapolate the endurance degradation tendency and predict the lifetime of the device.

A Radiation-Tolerant, Low-Power Non-Volatile Memory Based on Silicon Nanocrystal Quantum Dots

NASA Technical Reports Server (NTRS)

Bell, L. D.; Boer, E. A.; Ostraat, M. L.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; deBlauwe, J.; Green, M. L.

2001-01-01

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO2 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled in program/erase threshold voltage swing was seen during 100,000 program and erase cycles. Additional near-term goals for this project include extensive testing for radiation hardness and the development of artificial layered tunnel barrier heterostructures which have the potential for large speed enhancements for read/write of nanocrystal memory elements, compared with conventional flash devices. Additional information is contained in the original extended abstract.

Pushing the Material Limits in High Kappa Dielectrics on High Carrier Mobility Semiconductors for Science/Technology Beyond Si CMOS and More

DTIC Science & Technology

2014-01-28

In0.53Ga0.47As, with an Al2O3 cap, were employed as a gate dielectric. 15. SUBJECT TERMS CMOS, Magneto-optical imaging , Nanotechnology, Indium Gallium ...2012. 2. “ Thermodynamic stability of MBE-HfO2 on In0.53Ga0.47As”, T. D. Lin, P. Chang, W. C. Lee, M. L. Huang, C. A. Lin, J. Kwo, and M. Hong

A novel productivity-driven logic element for field-programmable devices

NASA Astrophysics Data System (ADS)

Marconi, Thomas; Bertels, Koen; Gaydadjiev, Georgi

2014-06-01

Although various techniques have been proposed for power reduction in field-programmable devices (FPDs), they are still all based on conventional logic elements (LEs). In the conventional LE, the output of the combinational logic (e.g. the look-up table (LUT) in many field-programmable gate arrays (FPGAs)) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel productivity-driven LE with reduced number of transitions. The differences between our LE and the conventional LE are in the FFs-type used and the internal LE organisation. In our LEs, DFFs have been replaced by T flip-flops with the T input permanently connected to logic value 1. Instead of connecting the output of the combinational logic to the FF input, we use it as the FF clock. The proposed LE has been validated via Simulation Program with Integrated Circuit Emphasis (SPICE) simulations for a 45-nm Complementary Metal-Oxide-Semiconductor (CMOS) technology as well as via a real Computer-Aided Design (CAD) tools on a real FPGA using the standard Microelectronic Center of North Carolina (MCNC) benchmark circuits. The experimental results show that FPDs using our proposal not only have 48% lower total power but also run 17% faster than conventional FPDs on average.

A new curvature compensation technique for CMOS voltage reference using |VGS| and ΔVBE

NASA Astrophysics Data System (ADS)

Xuemin, Li; Mao, Ye; Gongyuan, Zhao; Yun, Zhang; Yiqiang, Zhao

2016-05-01

A new mixed curvature compensation technique for CMOS voltage reference is presented, which resorts to two sub-references with complementary temperature characteristics. The first sub-reference is the source-gate voltage |VGS|p of a PMOS transistor working in the saturated region. The second sub-reference is the weighted sum of gate-source voltages |VGS|n of NMOS transistors in the subthreshold region and the difference between two base-emitter voltages ΔVBE of bipolar junction transistors (BJTs). The voltage reference implemented utilizing the proposed curvature compensation technique exhibits a low temperature coefficient and occupies a small silicon area. The proposed technique was verified in 0.18 μm standard CMOS process technology. The performance of the circuit has been measured. The measured results show a temperature coefficient as low as 12.7 ppm/°C without trimming, over a temperature range from -40 to 120 °C, and the current consumption is 50 μA at room temperature. The measured power-supply rejection ratio (PSRR) is -31.2 dB @ 100 kHz. The circuit occupies an area of 0.045 mm2. Project supported by the National Natural Science Foundation of China (No. 61376032).

CMOS array design automation techniques

NASA Technical Reports Server (NTRS)

Lombardi, T.; Feller, A.

1976-01-01

The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

Selective Conversion from p-Type to n-Type of Printed Bottom-Gate Carbon Nanotube Thin-Film Transistors and Application in Complementary Metal-Oxide-Semiconductor Inverters.

PubMed

Xu, Qiqi; Zhao, Jianwen; Pecunia, Vincenzo; Xu, Wenya; Zhou, Chunshan; Dou, Junyan; Gu, Weibing; Lin, Jian; Mo, Lixin; Zhao, Yanfei; Cui, Zheng

2017-04-12

The fabrication of printed high-performance and environmentally stable n-type single-walled carbon nanotube (SWCNT) transistors and their integration into complementary (i.e., complementary metal-oxide-semiconductor, CMOS) circuits are widely recognized as key to achieving the full potential of carbon nanotube electronics. Here, we report a simple, efficient, and robust method to convert the polarity of SWCNT thin-film transistors (TFTs) using cheap and readily available ethanolamine as an electron doping agent. Printed p-type bottom-gate SWCNT TFTs can be selectively converted into n-type by deposition of ethanolamine inks on the transistor active region via aerosol jet printing. Resulted n-type TFTs show excellent electrical properties with an on/off ratio of 10 6 , effective mobility up to 30 cm 2 V -1 s -1 , small hysteresis, and small subthreshold swing (90-140 mV dec -1 ), which are superior compared to the original p-type SWCNT devices. The n-type SWCNT TFTs also show good stability in air, and any deterioration of performance due to shelf storage can be fully recovered by a short low-temperature annealing. The easy polarity conversion process allows construction of CMOS circuitry. As an example, CMOS inverters were fabricated using printed p-type and n-type TFTs and exhibited a large noise margin (50 and 103% of 1/2 V dd = 1 V) and a voltage gain as high as 30 (at V dd = 1 V). Additionally, the CMOS inverters show full rail-to-rail output voltage swing and low power dissipation (0.1 μW at V dd = 1 V). The new method paves the way to construct fully functional complex CMOS circuitry by printed TFTs.

Microdot - A Four-Bit Microcontroller Designed for Distributed Low-End Computing in Satellites

NASA Astrophysics Data System (ADS)

2002-03-01

Many satellites are an integrated collection of sensors and actuators that require dedicated real-time control. For single processor systems, additional sensors require an increase in computing power and speed to provide the multi-tasking capability needed to service each sensor. Faster processors cost more and consume more power, which taxes a satellite's power resources and may lead to shorter satellite lifetimes. An alternative design approach is a distributed network of small and low power microcontrollers designed for space that handle the computing requirements of each individual sensor and actuator. The design of microdot, a four-bit microcontroller for distributed low-end computing, is presented. The design is based on previous research completed at the Space Electronics Branch, Air Force Research Laboratory (AFRL/VSSE) at Kirtland AFB, NM, and the Air Force Institute of Technology at Wright-Patterson AFB, OH. The Microdot has 29 instructions and a 1K x 4 instruction memory. The distributed computing architecture is based on the Philips Semiconductor I2C Serial Bus Protocol. A prototype was implemented and tested using an Altera Field Programmable Gate Array (FPGA). The prototype was operable to 9.1 MHz. The design was targeted for fabrication in a radiation-hardened-by-design gate-array cell library for the TSMC 0.35 micrometer CMOS process.

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

NASA Astrophysics Data System (ADS)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

Stretchable carbon nanotube charge-trap floating-gate memory and logic devices for wearable electronics.

PubMed

Son, Donghee; Koo, Ja Hoon; Song, Jun-Kyul; Kim, Jaemin; Lee, Mincheol; Shim, Hyung Joon; Park, Minjoon; Lee, Minbaek; Kim, Ji Hoon; Kim, Dae-Hyeong

2015-05-26

Electronics for wearable applications require soft, flexible, and stretchable materials and designs to overcome the mechanical mismatch between the human body and devices. A key requirement for such wearable electronics is reliable operation with high performance and robustness during various deformations induced by motions. Here, we present materials and device design strategies for the core elements of wearable electronics, such as transistors, charge-trap floating-gate memory units, and various logic gates, with stretchable form factors. The use of semiconducting carbon nanotube networks designed for integration with charge traps and ultrathin dielectric layers meets the performance requirements as well as reliability, proven by detailed material and electrical characterizations using statistics. Serpentine interconnections and neutral mechanical plane layouts further enhance the deformability required for skin-based systems. Repetitive stretching tests and studies in mechanics corroborate the validity of the current approaches.

Phase-to-intensity conversion of magnonic spin currents and application to the design of a majority gate

PubMed Central

Brächer, T.; Heussner, F.; Pirro, P.; Meyer, T.; Fischer, T.; Geilen, M.; Heinz, B.; Lägel, B.; Serga, A. A.; Hillebrands, B.

2016-01-01

Magnonic spin currents in the form of spin waves and their quanta, magnons, are a promising candidate for a new generation of wave-based logic devices beyond CMOS, where information is encoded in the phase of travelling spin-wave packets. The direct readout of this phase on a chip is of vital importance to couple magnonic circuits to conventional CMOS electronics. Here, we present the conversion of the spin-wave phase into a spin-wave intensity by local non-adiabatic parallel pumping in a microstructure. This conversion takes place within the spin-wave system itself and the resulting spin-wave intensity can be conveniently transformed into a DC voltage. We also demonstrate how the phase-to-intensity conversion can be used to extract the majority information from an all-magnonic majority gate. This conversion method promises a convenient readout of the magnon phase in future magnon-based devices. PMID:27905539

Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems

DOEpatents

Welch, James D.

2003-09-23

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of applied gate voltage field induced carriers in essentially intrinsic, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, and containing a single metallurgical doping type, and functional combinations thereof. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents utilizing material(s) which form rectifying junctions with both N and P-type semiconductor whether metallurigically or field induced.

Heterointegration of Dissimilar Materials

DTIC Science & Technology

2015-07-28

computing capabilities. This has been possible due to the aggressive scaling undertaken by the Si industry for complementary metal oxide semiconductor...current due to quantum mechanical tunneling. After years of research and development, Hf- based gate dielectric with metal gates is now being used in CMOS...the oxide in this study was 1ML or ~3.9 Å/ min. The native SiO2 was removed using a low temperature process involving the deposition of Sr metal

Controllable Hysteresis and Threshold Voltage of Single-Walled Carbon Nano-tube Transistors with Ferroelectric Polymer Top-Gate Insulators

PubMed Central

Sun, Yi-Lin; Xie, Dan; Xu, Jian-Long; Zhang, Cheng; Dai, Rui-Xuan; Li, Xian; Meng, Xiang-Jian; Zhu, Hong-Wei

2016-01-01

Double-gated field effect transistors have been fabricated using the SWCNT networks as channel layer and the organic ferroelectric P(VDF-TrFE) film spin-coated as top gate insulators. Standard photolithography process has been adopted to achieve the patterning of organic P(VDF-TrFE) films and top-gate electrodes, which is compatible with conventional CMOS process technology. An effective way for modulating the threshold voltage in the channel of P(VDF-TrFE) top-gate transistors under polarization has been reported. The introduction of functional P(VDF-TrFE) gate dielectric also provides us an alternative method to suppress the initial hysteresis of SWCNT networks and obtain a controllable ferroelectric hysteresis behavior. Applied bottom gate voltage has been found to be another effective way to highly control the threshold voltage of the networked SWCNTs based FETs by electrostatic doping effect. PMID:26980284

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

PubMed

Haque, M Samiul; Ali, S Zeeshan; Guha, P K; Oei, S P; Park, J; Maeng, S; Teo, K B K; Udrea, F; Milne, W I

2008-11-01

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

Study of proton radiation effects among diamond and rectangular gate MOSFET layouts

NASA Astrophysics Data System (ADS)

Seixas, L. E., Jr.; Finco, S.; Silveira, M. A. G.; Medina, N. H.; Gimenez, S. P.

2017-01-01

This paper describes an experimental comparative study of proton ionizing radiation effects between the metal-oxide-semiconductor (MOS) Field Effect Transistors (MOSFETs) implemented with hexagonal gate shapes (diamond) and their respective counterparts designed with the classical rectangular ones, regarding the same gate areas, channel widths and geometrical ratios (W/L). The devices were manufactured by using the 350 nm bulk complementary MOS (CMOS) integrated circuits technology. The diamond MOSFET with α angles higher or equal to 90° tends to present a smaller vulnerability to the high doses ionizing radiation than those observed in the typical rectangular MOSFET counterparts.

Low-latency optical parallel adder based on a binary decision diagram with wavelength division multiplexing scheme

NASA Astrophysics Data System (ADS)

Shinya, A.; Ishihara, T.; Inoue, K.; Nozaki, K.; Kita, S.; Notomi, M.

2018-02-01

We propose an optical parallel adder based on a binary decision diagram that can calculate simply by propagating light through electrically controlled optical pass gates. The CARRY and CARRY operations are multiplexed in one circuit by a wavelength division multiplexing scheme to reduce the number of optical elements, and only a single gate constitutes the critical path for one digit calculation. The processing time reaches picoseconds per digit when we use a 100-μm-long optical path gates, which is ten times faster than a CMOS circuit.

Nonvolatile floating gate organic memory device based on pentacene/CdSe quantum dot heterojuction

NASA Astrophysics Data System (ADS)

Shin, Ik-Soo; Kim, Jung-Min; Jeun, Jun-Ho; Yoo, Seok-Hyun; Ge, Ziyi; Hong, Jong-In; Ho Bang, Jin; Kim, Yong-Sang

2012-04-01

An organic floating-gate memory device using CdSe quantum dots (QDs) as a charge-trapping element was fabricated. CdSe QDs were localized beneath a pentacene without any tunneling insulator, and the QD layer played a role as hole-trapping sites. The band bending formed at the junction between pentacene and QD layers inhibited back-injection of holes trapped in CdSe into pentacene, which appeared as a hysteretic capacitance-voltage response during the operation of the device. Nearly, 60% of trapped charge was sustained even after 104 s in programmed state, and this long retention time can be potentially useful in practical applications of non-volatile memory.

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters.

PubMed

Luo, Hao; Liang, Lingyan; Cao, Hongtao; Dai, Mingzhi; Lu, Yicheng; Wang, Mei

2015-08-12

For ultrathin semiconductor channels, the surface and interface nature are vital and often dominate the bulk properties to govern the field-effect behaviors. High-performance thin-film transistors (TFTs) rely on the well-defined interface between the channel and gate dielectric, featuring negligible charge trap states and high-speed carrier transport with minimum carrier scattering characters. The passivation process on the back-channel surface of the bottom-gate TFTs is indispensable for suppressing the surface states and blocking the interactions between the semiconductor channel and the surrounding atmosphere. We report a dielectric layer for passivation of the back-channel surface of 20 nm thick tin monoxide (SnO) TFTs to achieve ambipolar operation and complementary metal oxide semiconductor (CMOS) like logic devices. This chemical passivation reduces the subgap states of the ultrathin channel, which offers an opportunity to facilitate the Fermi level shifting upward upon changing the polarity of the gate voltage. With the advent of n-type inversion along with the pristine p-type conduction, it is now possible to realize ambipolar operation using only one channel layer. The CMOS-like logic inverters based on ambipolar SnO TFTs were also demonstrated. Large inverter voltage gains (>100) in combination with wide noise margins are achieved due to high and balanced electron and hole mobilities. The passivation also improves the long-term stability of the devices. The ability to simultaneously achieve field-effect inversion, electrical stability, and logic function in those devices can open up possibilities for the conventional back-channel surface passivation in the CMOS-like electronics.

Towards a portable Raman spectrometer using a concave grating and a time-gated CMOS SPAD.

PubMed

Li, Zhiyun; Deen, M Jamal

2014-07-28

A low-cost, compact Raman spectrometer suitable for the on-line water monitoring applications is explored. A custom-designed concave grating for wavelength selection was fabricated and tested. The detection of the Raman signal is accomplished with a time-gated single photon avalanche diode (TG-SPAD). A fixed gate window of 3.5ns is designed and applied to the TG-SPAD. The temporal resolution of the SPAD was ~60ps when tested with a 7ps, 532nm solid-state laser. To test the efficiency of the gating in fluorescence signal suppression, different detection windows (3ns-0.25ns) within the 3.5ns gate window are used to measure the Raman spectra of Rhodamine B. Strong Raman peaks are resolved with this low-cost system.

An SEU immune logic family

NASA Technical Reports Server (NTRS)

Canaris, J.

1991-01-01

A new logic family, which is immune to single event upsets, is described. Members of the logic family are capable of recovery, regardless of the shape of the upsetting event. Glitch propagation from an upset node is also blocked. Logic diagrams for an Inverter, Nor, Nand, and Complex Gates are provided. The logic family can be implemented in a standard, commercial CMOS process with no additional masks. DC, transient, static power, upset recovery and layout characteristics of the new family, based on a commercial 1 micron CMOS N-Well process, are described.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory

NASA Astrophysics Data System (ADS)

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-01

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory.

PubMed

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-23

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

Defense Industrial Base Assessment: U.S. Integrated Circuit Design and Fabrication Capability

DTIC Science & Technology

2009-05-01

in the U.S for the period 2003-2006, with projections to 2011.6 The resulting draft OTE survey was field tested for accuracy and usability with a...custom application specific integrated circuits (ASICs) to field programmable gate arrays (FPGAs). Companies of all sizes can manufacture these IC...able to design one-time Electronically Programmable Gate Arrays (EPGAs) while nine are able to design Field Programmable Gate Arrays (FPGAs). Eight

Radiation induced failures of complementary metal oxide semiconductor containing pacemakers: a potentially lethal complication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lewin, A.A.; Serago, C.F.; Schwade, J.G.

1984-10-01

New multi-programmable pacemakers frequently employ complementary metal oxide semiconductors (CMOS). This circuitry appears more sensitive to the effects of ionizing radiation when compared to the semiconductor circuits used in older pacemakers. A case of radiation induced runaway pacemaker in a CMOS device is described. Because of this and other recent reports of radiation therapy-induced CMOS type pacemaker failure, these pacemakers should not be irradiated. If necessary, the pacemaker can be shielded or moved to a site which can be shielded before institution of radiation therapy. This is done to prevent damage to the CMOS circuit and the life threatening arrythmiasmore » which may result from such damage.« less

RHrFPGA Radiation-Hardened Re-programmable Field-Programmable Gate Array

NASA Technical Reports Server (NTRS)

Sanders, A. B.; LaBel, K. A.; McCabe, J. F.; Gardner, G. A.; Lintz, J.; Ross, C.; Golke, K.; Burns, B.; Carts, M. A.; Kim, H. S.

2004-01-01

Viewgraphs on the development of the Radiation-Hardened Re-programmable Field-Programmable Gate Array (RHrFPGA) are presented. The topics include: 1) Radiation Test Suite; 2) Testing Interface; 3) Test Configuration; 4) Facilities; 5) Test Programs; 6) Test Procedure; and 7) Test Results. A summary of heavy ion and proton testing is also included.

The prospects of transition metal dichalcogenides for ultimately scaled CMOS

NASA Astrophysics Data System (ADS)

Thiele, S.; Kinberger, W.; Granzner, R.; Fiori, G.; Schwierz, F.

2018-05-01

MOSFET gate length scaling has been a main source of progress in digital electronics for decades. Today, researchers still spend considerable efforts on reducing the gate length and on developing ultimately scaled MOSFETs, thereby exploring both new device architectures and alternative channel materials beyond Silicon such as two-dimensional TMDs (transition metal dichalcogenide). On the other hand, the envisaged scaling scenario for the next 15 years has undergone a significant change recently. While the 2013 ITRS edition required a continuation of aggressive gate length scaling for at least another 15 years, the 2015 edition of the ITRS suggests a deceleration and eventually a levelling off of gate length scaling and puts more emphasis on alternative options such as pitch scaling to keep Moore's Law alive. In the present paper, future CMOS scaling is discussed in the light of emerging two-dimensional MOSFET channel, in particular two-dimensional TMDs. To this end, the scaling scenarios of the 2013 and 2015 ITRS editions are considered and the scaling potential of TMD MOSFETs is investigated by means of quantum-mechanical device simulations. It is shown that for ultimately scaled MOSFETs as required in the 2013 ITRS, the heavy carrier effective masses of the Mo- and W-based TMDs are beneficial for the suppression of direct source-drain tunneling, while to meet the significantly relaxed scaling targets of the 2016 ITRS heavy-effective-mass channels are not needed.

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

On gate stack scalability of double-gate negative-capacitance FET with ferroelectric HfO2 for energy efficient sub-0.2 V operation

NASA Astrophysics Data System (ADS)

Jang, Kyungmin; Saraya, Takuya; Kobayashi, Masaharu; Hiramoto, Toshiro

2018-02-01

We have investigated the gate stack scalability and energy efficiency of double-gate negative-capacitance FET (DGNCFET) with a CMOS-compatible ferroelectric HfO2 (FE:HfO2). Analytic model-based simulation is conducted to investigate the impacts of ferroelectric characteristic of FE:HfO2 and gate stack thickness on the I on/I off ratio of DGNCFET. DGNCFET has wider design window for the gate stack where higher I on/I off ratio can be achieved than DG classical MOSFET. Under a process-induced constraint with sub-10 nm gate length (L g), FE:HfO2-based DGNCFET still has a design point for high I on/I off ratio. With an optimized gate stack thickness for sub-10 nm L g, FE:HfO2-based DGNCFET has 2.5× higher energy efficiency than DG classical MOSFET even at ultralow operation voltage of sub-0.2 V.

Wasteway, intake side. The floatoperated radial gates are housed behind ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

Wasteway, intake side. The float-operated radial gates are housed behind the concrete (below water level), view to the northwest - Wellton-Mohawk Irrigation System, Wasteway No. 1, Wellton-Mohawk Canal, North side of Wellton-Mohawk Canal, bounded by Gila River to North & the Union Pacific Railroad & Gila Mountains to south, Wellton, Yuma County, AZ

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System

PubMed Central

Yang, Jong-Ryul; Lee, Woo-Jae; Han, Seong-Tae

2016-01-01

A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC) offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s. PMID:26950128

Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System.

PubMed

Yang, Jong-Ryul; Lee, Woo-Jae; Han, Seong-Tae

2016-03-02

A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS) detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC) offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s.

Al203 thin films on Silicon and Germanium substrates for CMOS and flash memory applications

NASA Astrophysics Data System (ADS)

Gopalan, Sundararaman; Dutta, Shibesh; Ramesh, Sivaramakrishnan; Prathapan, Ragesh; Sreehari G., S.

2017-07-01

As scaling of device dimensions has continued, it has become necessary to replace traditional SiO2 with high dielectric constant materials in the conventional CMOS devices. In addition, use of metal gate electrodes and Germanium substrates may have to be used in order to address leakage and mobility issues. Al2O3 is one of the potential candidates both for CMOS and as a blocking dielectric for Flash memory applications owing to its low leakage. In this study, the effects of sputtering conditions and post-deposition annealing conditions on the electrical and reliability characteristics of MOS capacitors using Al2O3 films on Si and Ge substrates with Aluminium gate electrodes have been presented. It was observed that higher sputtering power resulted in larger flat-band voltage (Vfb) shifts, more hysteresis, higher interface state density (Dit) and a poorer reliability. Wit was also found that while a short duration high temperature annealing improves film characteristics, a long duration anneal even at 800C was found to be detrimental to MOS characteristics. Finally, the electronic conduction mechanism in Al2O3 films was also studied. It was observed that the conduction mechanism varied depending on the annealing condition, thickness of film and electric field.

Magnetic tunnel junction based spintronic logic devices

NASA Astrophysics Data System (ADS)

Lyle, Andrew Paul

The International Technology Roadmap for Semiconductors (ITRS) predicts that complimentary metal oxide semiconductor (CMOS) based technologies will hit their last generation on or near the 16 nm node, which we expect to reach by the year 2025. Thus future advances in computational power will not be realized from ever-shrinking device sizes, but rather by 'outside the box' designs and new physics, including molecular or DNA based computation, organics, magnonics, or spintronic. This dissertation investigates magnetic logic devices for post-CMOS computation. Three different architectures were studied, each relying on a different magnetic mechanism to compute logic functions. Each design has it benefits and challenges that must be overcome. This dissertation focuses on pushing each design from the drawing board to a realistic logic technology. The first logic architecture is based on electrically connected magnetic tunnel junctions (MTJs) that allow direct communication between elements without intermediate sensing amplifiers. Two and three input logic gates, which consist of two and three MTJs connected in parallel, respectively were fabricated and are compared. The direct communication is realized by electrically connecting the output in series with the input and applying voltage across the series connections. The logic gates rely on the fact that a change in resistance at the input modulates the voltage that is needed to supply the critical current for spin transfer torque switching the output. The change in resistance at the input resulted in a voltage margin of 50--200 mV and 250--300 mV for the closest input states for the three and two input designs, respectively. The two input logic gate realizes the AND, NAND, NOR, and OR logic functions. The three input logic function realizes the Majority, AND, NAND, NOR, and OR logic operations. The second logic architecture utilizes magnetostatically coupled nanomagnets to compute logic functions, which is the basis of Magnetic Quantum Cellular Automata (MQCA). MQCA has the potential to be thousands of times more energy efficient than CMOS technology. While interesting, these systems are academic unless they can be interfaced into current technologies. This dissertation pushed past a major hurdle by experimentally demonstrating a spintronic input/output (I/O) interface for the magnetostatically coupled nanomagnets by incorporating MTJs. This spintronic interface allows individual nanomagnets to be programmed using spin transfer torque and read using magneto resistance structure. Additionally the spintronic interface allows statistical data on the reliability of the magnetic coupling utilized for data propagation to be easily measured. The integration of spintronics and MQCA for an electrical interface to achieve a magnetic logic device with low power creates a competitive post-CMOS logic device. The final logic architecture that was studied used MTJs to compute logic functions and magnetic domain walls to communicate between gates. Simulations were used to optimize the design of this architecture. Spin transfer torque was used to compute logic function at each MTJ gate and was used to drive the domain walls. The design demonstrated that multiple nanochannels could be connected to each MTJ to realize fan-out from the logic gates. As a result this logic scheme eliminates the need for intermediate reads and conversions to pass information from one logic gate to another.

Cargo Movement Operations System (CMOS). Draft Software Programmer’s Manual

DTIC Science & Technology

1990-07-12

NO ( ] COMMENT DISPOSITION: ACCEPT [ ] REJECT [ ] COMMENT STATUS: OPEN [ ] CLOSED [ ] Cmnt Page Paragraph No. No. Number Comment 1. 3-4 3.2 Change...reader in locating pertinent information. CMOS PMO ACCEPTS COMMENT: YES [ ] NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO ( ] COMMENT DISPOSITION: COMMENT...NO [ ] ERCI ACCEPTS COMMENT: YES [ ] NO [ ] COMMENT DISPOSITION: COMMENT STATUS: OPEN ( ] CLOSED [ ] ORIGINATOR CONTROL NUMBER: SPM-0006 PROGRAM

Real-time system for measuring three-dimensional shape of solder bump array by focus using varifocal mirror

NASA Astrophysics Data System (ADS)

Ishii, Akira; Tai, Haruka; Mitsudo, Jun

2007-10-01

This paper describes a real-time system for measuring the three-dimensional shape of solder bumps arrayed on an LSI chip-size-package (CSP) board presented for inspection based on the shape-from-focus technique. It uses a copper-alloy mirror deformed by a piezoelectric actuator as a varifocal mirror enabling a simple, fast, precise focusing mechanism without moving parts to be built. A practical measuring speed of 1.69 s/package for a small CSP board (4 x 4 mm2) was achieved by incorporating an exclusive field programmable gate array processor to calculate focus measure and by constructing a domed array of LEDs as a high-intensity, uniform illumination system so that a fast (150 fps) and high-resolution (1024 x 1024 pixels/frame) CMOS image sensor could be used. Accurate measurements of bump height were also achieved with errors of 10 μm (2σ) meeting the requirements for testing the coplanarity of a bump array.

Programmable synaptic chip for electronic neural networks

NASA Technical Reports Server (NTRS)

Moopenn, A.; Langenbacher, H.; Thakoor, A. P.; Khanna, S. K.

1988-01-01

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

Refrigerant directly cooled capacitors

DOEpatents

Hsu, John S [Oak Ridge, TN; Seiber, Larry E [Oak Ridge, TN; Marlino, Laura D [Oak Ridge, TN; Ayers, Curtis W [Kingston, TN

2007-09-11

The invention is a direct contact refrigerant cooling system using a refrigerant floating loop having a refrigerant and refrigeration devices. The cooling system has at least one hermetic container disposed in the refrigerant floating loop. The hermetic container has at least one electronic component selected from the group consisting of capacitors, power electronic switches and gating signal module. The refrigerant is in direct contact with the electronic component.

The floating-gate non-volatile semiconductor memory--from invention to the digital age.

PubMed

Sze, S M

2012-10-01

In the past 45 years (from 1967 to 2012), the non-volatile semiconductor memory (NVSM) has emerged from a floating-gate concept to the prime technology driver of the largest industry in the world-the electronics industry. In this paper, we briefly review the historical development of NVSM and project its future trends to the year 2020. In addition, we consider NVSM's wide-range of applications from the digital cellular phone to tablet computer to digital television. As the device dimension is scaled down to the deca-nanometer regime, we expect that many innovations will be made to meet the scaling challenges, and NVSM-inspired technology will continue to enrich and improve our lives for decades to come.

ESD protection design for advanced CMOS

NASA Astrophysics Data System (ADS)

Huang, Jin B.; Wang, Gewen

2001-10-01

ESD effects in integrated circuits have become a major concern as today's technologies shrink to sub-micron/deep- sub-micron dimensions. The thinner gate oxide and shallower junction depth used in the advanced technologies make them very vulnerable to ESD damages. The advanced techniques like silicidation and STI (shallow trench insulation) used for improving other device performances make ESD design even more challenging. For non-silicided technologies, a certain DCGS (drain contact to gate edge spacing) is needed to achieve ESD hardness for nMOS output drivers and nMOS protection transistors. The typical DCGS values are 4-5um and 2-3um for 0.5um and 0.25um CMOS, respectively. The silicidation reduces the ballast resistance provided by DCGS with at least a factor of 10. As a result, scaling of the ESD performance with device width is lost and even zero ESD performance is reported for standard silicided devices. The device level ESD design is focused in this paper, which includes GGNMOS (gate grounded NMOS) and GCNMOS (gate coupled NMOS). The device level ESD testing including TLP (transmission line pulse) is given. Several ESD issues caused by advanced technologies have been pointed out. The possible solutions have been developed and summarized including silicide blocking, process optimization, back-end ballasting, and new protection scheme, dummy gate/n-well resistor ballsting, etc. Some of them require process cost increase, and others provide novel, compact, and simple design but involving royalty/IP (intellectual property) issue. Circuit level ESD design and layout design considerations are covered. The top-level ESD protection strategies are also given.

Experimental demonstration of a real-time high-throughput digital DC blocker for compensating ADC imperfections in optical fast-OFDM receivers.

PubMed

Zhang, Lu; Ouyang, Xing; Shao, Xiaopeng; Zhao, Jian

2016-06-27

Performance degradation induced by the DC components at the output of real-time analogue-to-digital converter (ADC) is experimentally investigated for optical fast-OFDM receiver. To compensate this degradation, register transfer level (RTL) circuits for real-time digital DC blocker with 20GS/s throughput are proposed and implemented in field programmable gate array (FPGA). The performance of the proposed real-time digital DC blocker is experimentally investigated in a 15Gb/s optical fast-OFDM system with intensity modulation and direct detection over 40 km standard single-mode fibre. The results show that the fixed-point DC blocker has negligible performance penalty compared to the offline floating point one, and can overcome the error floor of the fast OFDM receiver caused by the DC components from the real-time ADC output.

Multi-level Capacitive Memory Effect in Metal/Oxide/Floating-Schottky Junction

NASA Astrophysics Data System (ADS)

Choi, Gahyun; Jung, Sungchul; Yoon, Hoon Hahn; Jeon, Youngeun; Park*, Kibog

2015-03-01

A memory computing (memcomputing) system can store and process information at the same physical location simultaneously. The essential components of memcomputing are passive devices with memory functionality, such as memristor, memcapacitor, and meminductor. We report the realization of a Schottky contact memcapacitor compatible with the current Si CMOS technology. Our memcapacitor is formed by depositing a stack of metal and oxide thin films on top of a Schottky contact. Here, the metal electrode of the Schottky contact is floating. The working principle of our memcapacitor is based on the fact that the depletion width of the Schottky contact varies according to the amount of charge stored in the floating metal electrode. The voltage pulse applied across the Metal/Oxide/Floating-Schottky junction controls charge flow in the Schottky contact and determines the amount of charge stored eventually. It is demonstrated experimentally that our memcapacitor exhibits hysteresis behaviors in capacitance-voltage curves and possesses multiple capacitance values that are switchable by the applied voltage pulse. Supported by NRF in South Korea (2013R1A1A2007070).

Self-powered monitoring of repeated head impacts using time-dilation energy measurement circuit.

PubMed

Feng, Tao; Aono, Kenji; Covassin, Tracey; Chakrabartty, Shantanu

2015-04-01

Due to the current epidemic levels of sport-related concussions (SRC) in the U.S., there is a pressing need for technologies that can facilitate long-term and continuous monitoring of head impacts. Existing helmet-sensor technology is inconsistent, inaccurate, and is not economically or logistically practical for large-scale human studies. In this paper, we present the design of a miniature, battery-less, self-powered sensor that can be embedded inside sport helmets and can continuously monitor and store different spatial and temporal statistics of the helmet impacts. At the core of the proposed sensor is a novel time-dilation circuit that allows measurement of a wide-range of impact energies. In this paper an array of linear piezo-floating-gate (PFG) injectors has been used for self-powered sensing and storage of linear and rotational head-impact statistics. The stored statistics are then retrieved using a plug-and-play reader and has been used for offline data analysis. We report simulation and measurement results validating the functionality of the time-dilation circuit for different levels of impact energies. Also, using prototypes of linear PFG integrated circuits fabricated in a 0.5 μm CMOS process, we demonstrate the functionality of the proposed helmet-sensors using controlled drop tests.

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Coupling Two-Dimensional MoTe2 and InGaZnO Thin-Film Materials for Hybrid PN Junction and CMOS Inverters.

PubMed

Lee, Han Sol; Choi, Kyunghee; Kim, Jin Sung; Yu, Sanghyuck; Ko, Kyeong Rok; Im, Seongil

2017-05-10

We report the fabrication of hybrid PN junction diode and complementary (CMOS) inverters, where 2D p-type MoTe 2 and n-type thin film InGaZnO (IGZO) are coupled for each device process. IGZO thin film was initially patterned by conventional photolithography either for n-type material in a PN diode or for n-channel of top-gate field-effect transistors (FET) in CMOS inverter. The hybrid PN junction diode shows a good ideality factor of 1.57 and quite a high ON/OFF rectification ratio of ∼3 × 10 4 . Under photons, our hybrid PN diode appeared somewhat stable only responding to high-energy photons of blue and ultraviolet. Our 2D nanosheet-oxide film hybrid CMOS inverter exhibits voltage gains as high as ∼40 at 5 V, low power consumption less than around a few nW at 1 V, and ∼200 μs switching dynamics.

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.

PubMed

Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

2016-01-30

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.

All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement

PubMed Central

Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi

2016-01-01

This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of −20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system. PMID:26840316

CMOS-micromachined, two-dimenisional transistor arrays for neural recording and stimulation.

PubMed

Lin, J S; Chang, S R; Chang, C H; Lu, S C; Chen, H

2007-01-01

In-plane microelectrode arrays have proven to be useful tools for studying the connectivities and the functions of neural tissues. However, seldom microelectrode arrays are monolithically-integrated with signal-processing circuits, without which the maximum number of electrodes is limited by the compromise with routing complexity and interferences. This paper proposes a CMOS-compatible, two-dimensional array of oxide-semiconductor field-effect transistors(OSFETs), capable of both recording and stimulating neuronal activities. The fabrication of the OSFETs not only requires simply die-level, post-CMOS micromachining process, but also retains metal layers for monolithic integration with signal-processing circuits. A CMOS microsystem containing the OSFET arrays and gain-programmable recording circuits has been fabricated and tested. The preliminary testing results are presented and discussed.

Programmable ion-sensitive transistor interfaces. II. Biomolecular sensing and manipulation.

PubMed

Jayant, Krishna; Auluck, Kshitij; Funke, Mary; Anwar, Sharlin; Phelps, Joshua B; Gordon, Philip H; Rajwade, Shantanu R; Kan, Edwin C

2013-07-01

The chemoreceptive neuron metal-oxide-semiconductor transistor described in the preceding paper is further used to monitor the adsorption and interaction of DNA molecules and subsequently manipulate the adsorbed biomolecules with injected static charge. Adsorption of DNA molecules onto poly-L-lysine-coated sensing gates (SGs) modulates the floating gate (FG) potential ψ(O), which is reflected as a threshold voltage shift measured from the control gate (CG) V(th_CG). The asymmetric capacitive coupling between the CG and SG to the FG results in V(th_CG) amplification. The electric field in the SG oxide E(SG_ox) is fundamentally different when we drive the current readout with V(CG) and V(ref) (i.e., the potential applied to the CG and reference electrode, respectively). The V(CG)-driven readout induces a larger E(SG_ox), leading to a larger V(th_CG) shift when DNA is present. Simulation studies indicate that the counterion screening within the DNA membrane is responsible for this effect. The DNA manipulation mechanism is enabled by tunneling electrons (program) or holes (erase) onto FGs to produce repulsive or attractive forces. Programming leads to repulsion and eventual desorption of DNA, while erasing reestablishes adsorption. We further show that injected holes or electrons prior to DNA addition either aids or disrupts the immobilization process, which can be used for addressable sensor interfaces. To further substantiate DNA manipulation, we used impedance spectroscopy with a split ac-dc technique to reveal the net interface impedance before and after charge injection.

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

PubMed

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Beyond CMOS computing with spin and polarization

NASA Astrophysics Data System (ADS)

Manipatruni, Sasikanth; Nikonov, Dmitri E.; Young, Ian A.

2018-04-01

Spintronic and multiferroic systems are leading candidates for achieving attojoule-class logic gates for computing, thereby enabling the continuation of Moore's law for transistor scaling. However, shifting the materials focus of computing towards oxides and topological materials requires a holistic approach addressing energy, stochasticity and complexity.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mamaluy, Denis; Gao, Xujiao; Tierney, Brian David

We created a highly efficient, universal 3D quant um transport simulator. We demonstrated that the simulator scales linearly - both with the problem size (N) and number of CPUs, which presents an important break-through in the field of computational nanoelectronics. It allowed us, for the first time, to accurately simulate and optim ize a large number of realistic nanodevices in a much shorter time, when compared to other methods/codes such as RGF[%7EN 2.333 ]/KNIT, KWANT, and QTBM[%7EN 3 ]/NEMO5. In order to determine the best-in-class for different beyond-CMOS paradigms, we performed rigorous device optimization for high-performance logic devices at 6-,more » 5- and 4-nm gate lengths. We have discovered that there exists a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs). We have found that, at room temperatures, all FETs, irre spective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths.« less

Introduction of performance boosters like Ge as channel material for the future of CMOS

DOE Office of Scientific and Technical Information (OSTI.GOV)

Samia, Slimani, E-mail: slimani.samia@gmail.com; Laboratoire de Modélisation et Méthodes de calcul LMMC,20002 Saida; Bouaza, Djellouli, E-mail: djelbou@hotmail.fr

High mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. Ge is one of new attractive channel materials that require CMOS scaling For future technology nodes and future high performance P-MOSFETS, we have studied a nanoscale SOI DG MOSFETs using quantum simulation approach on DG MOSFETs within the variation of Ge channel concentration and in the presence of source and drain doping by replacing Silicon in the channel by Ge using various dielectric constant. The use of high mobility channel (like Ge) to maximize the MOSFET IDsat and simultaneously circumventmore » the poor electrostatic control to suppress short-channel effects and enhance source injection velocity. The leakage current (I{sub off}) can be controlled by different gates oxide thickness more ever the required threshold voltage (V{sub TH}) can be achieved by keeping gate work function and altering the doping channel.« less

100-nm gate lithography for double-gate transistors

NASA Astrophysics Data System (ADS)

Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

2001-09-01

The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics.

PubMed

Wei, Liping; Yan, Wenrong; Ho, Derek

2017-12-04

Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices.

Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics

PubMed Central

Yan, Wenrong; Ho, Derek

2017-01-01

Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices. PMID:29207568

Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

PubMed Central

Pavunny, Shojan P.; Scott, James F.; Katiyar, Ram S.

2014-01-01

A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS) specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS), bipolar (Bi) and BiCMOS chips applications, is presented in this review article. PMID:28788589

High kappa Dielectrics on InGaAs and GaN - Growth, Interfacial Structural Studies, and Surface Fermi Level Unpinning

DTIC Science & Technology

2011-04-20

ALD-Al2O3 and in-situ MBE-Al2O3/ Ga2O3 (Gd2O3) [GGO] as the gate dielectrics. The advances of the InGaAs MOSFETs achieved will enable future CMOS...and GaN MOSFETs:  High-performance self-aligned inversion-channel In0.53Ga0.47As and In0.75Ga0.25As MOSFET’s with Al2O3/ Ga2O3 (Gd2O3) as gate... Ga2O3 (Gd2O3) as gate dielectrics Key accomplishments in devices of 1m gate length: High drain current of 1.23 mA/m High transcoductance of 714

Investigation of impact of post-metallization annealing on reliability of 65 nm NOR floating-gate flash memories

NASA Astrophysics Data System (ADS)

Chiu, Shengfen; Xu, Yue; Ji, Xiaoli; Yan, Feng

2016-12-01

This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65 nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.

Gate-driven pure spin current in graphene

NASA Astrophysics Data System (ADS)

Lin, Xiaoyang; Su, Li; Zhang, Youguang; Bournel, Arnaud; Zhang, Yue; Klein, Jacques-Olivier; Zhao, Weisheng; Fert, Albert

An important challenge of spin current based devices is to realize long-distance transport and efficient manipulation of pure spin current without frequent spin-charge conversions. Here, the mechanism of gate-driven pure spin current in graphene is presented. Such a mechanism relies on the electrical gating of conductivity and spin diffusion length in graphene. The gate-driven feature is adopted to realize the pure spin current demultiplexing operation, which enables gate-controllable distribution of the pure spin current into graphene branches. Compared with Elliot-Yafet spin relaxation mechanism, D'yakonov-Perel spin relaxation mechanism results in more appreciable demultiplexing performance, which also implies a feasible strategy to characterize the spin relaxation mechanisms. The unique feature of the pure spin current demultiplexing operation would pave a way for ultra-low power spin logic beyond CMOS. Supported by the NSFC (61627813, 51602013) and the 111 project (B16001).

Wire like link for cycle reproducible and cycle accurate hardware accelerator

DOEpatents

Asaad, Sameh; Kapur, Mohit; Parker, Benjamin D

2015-04-07

First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.

Field programmable gate arrays: Evaluation report for space-flight application

NASA Technical Reports Server (NTRS)

Sandoe, Mike; Davarpanah, Mike; Soliman, Kamal; Suszko, Steven; Mackey, Susan

1992-01-01

Field Programmable Gate Arrays commonly called FPGA's are the newer generation of field programmable devices and offer more flexibility in the logic modules they incorporate and in how they are interconnected. The flexibility, the number of logic building blocks available, and the high gate densities achievable are why users find FPGA's attractive. These attributes are important in reducing product development costs and shortening the development cycle. The aerospace community is interested in incorporating this new generation of field programmable technology in space applications. To this end, a consortium was formed to evaluate the quality, reliability, and radiation performance of FPGA's. This report presents the test results on FPGA parts provided by ACTEL Corporation.

Nonvolatile memory thin film transistors using CdSe/ZnS quantum dot-poly(methyl methacrylate) composite layer formed by a two-step spin coating technique

NASA Astrophysics Data System (ADS)

Chen, Ying-Chih; Huang, Chun-Yuan; Yu, Hsin-Chieh; Su, Yan-Kuin

2012-08-01

The nonvolatile memory thin film transistors (TFTs) using a core/shell CdSe/ZnS quantum dot (QD)-poly(methyl methacrylate) (PMMA) composite layer as the floating gate have been demonstrated, with the device configuration of n+-Si gate/SiO2 insulator/QD-PMMA composite layer/pentacene channel/Au source-drain being proposed. To achieve the QD-PMMA composite layer, a two-step spin coating technique was used to successively deposit QD-PMMA composite and PMMA on the insulator. After the processes, the variation of crystal quality and surface morphology of the subsequent pentacene films characterized by x-ray diffraction spectra and atomic force microscopy was correlated to the two-step spin coating. The crystalline size of pentacene was improved from 147.9 to 165.2 Å, while the degree of structural disorder was decreased from 4.5% to 3.1% after the adoption of this technique. In pentacene-based TFTs, the improvement of the performance was also significant, besides the appearances of strong memory characteristics. The memory behaviors were attributed to the charge storage/discharge effect in QD-PMMA composite layer. Under the programming and erasing operations, programmable memory devices with the memory window (Δ Vth) = 23 V and long retention time were obtained.

Materials properties of hafnium and zirconium silicates: Metal interdiffusion and dopant penetration studies

NASA Astrophysics Data System (ADS)

Quevedo Lopez, Manuel Angel

Hafnium and Zirconium based gate dielectrics are considered potential candidates to replace SiO2 or SiON as the gate dielectric in CMOS processing. Furthermore, the addition of nitrogen into this pseudo-binary alloy has been shown to improve their thermal stability, electrical properties, and reduce dopant penetration. Because CMOS processing requires high temperature anneals (up to 1050°C), it is important to understand the diffusion properties of any metal associated with the gate dielectric in silicon at these temperatures. In addition, dopant penetration from the doped polysilicon gate into the Si channel at these temperatures must also be studied. Impurity outdiffusion (Hf, Zr) from the dielectric, or dopant (B, As, P) penetration through the dielectric into the channel region would likely result in deleterious effects upon the carrier mobility. In this dissertation extensive thermal stability studies of alternate gate dielectric candidates ZrSixOy and HfSixO y are presented. Dopant penetration studies from doped-polysilicon through HfSixOy and HfSixOyNz are also presented. Rutherford Backscattering Spectroscopy (RBS), Heavy Ion RBS (HI-RBS), X-ray Photoelectron Spectroscopy (XPS), High Resolution Transmission Electron Microscopy (HR-TEM), and Time of Flight and Dynamic Secondary Ion Mass Spectroscopy (ToF-SIMS, D-SIMS) methods were used to characterize these materials. The dopant diffusivity is calculated by modeling of the dopant profiles in the Si substrate. In this disseration is reported that Hf silicate films are more stable than Zr silicate films, from the metal interdiffusion point of view. On the other hand, dopant (B, As, and P) penetration is observed for HfSixO y films. However, the addition of nitrogen to the Hf - Si - O systems improves the dopant penetration properties of the resulting HfSi xOyNz films.

Multifunctional Logic Gate Controlled by Temperature

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

Implementation of Basic and Universal Gates In a single Circuit Based On Quantum-dot Cellular Automata Using Multi-Layer Crossbar Wire

NASA Astrophysics Data System (ADS)

Bhowmik, Dhrubajyoti; Saha, Apu Kr; Dutta, Paramartha; Nandi, Supratim

2017-08-01

Quantum-dot Cellular Automata (QCA) is one of the most substitutes developing nanotechnologies for electronic circuits, as a result of lower force utilization, higher speed and smaller size in correlation with CMOS innovation. The essential devices, a Quantum-dot cell can be utilized to logic gates and wires. As it is the key building block on nanotechnology circuits. By applying simple gates, the hardware requirements for a QCA circuit can be decreased and circuits can be less complex as far as level, delay and cell check. This article exhibits an unobtrusive methodology for actualizing novel upgraded simple and universal gates, which can be connected to outline numerous variations of complex QCA circuits. Proposed gates are straightforward in structure and capable as far as implementing any digital circuits. The main aim is to build all basic and universal gates in a simple circuit with and without crossbar-wire. Simulation results and physical relations affirm its handiness in actualizing each advanced circuit.

Fabrication of arrayed Si nanowire-based nano-floating gate memory devices on flexible plastics.

PubMed

Yoon, Changjoon; Jeon, Youngin; Yun, Junggwon; Kim, Sangsig

2012-01-01

Arrayed Si nanowire (NW)-based nano-floating gate memory (NFGM) devices with Pt nanoparticles (NPs) embedded in Al2O3 gate layers are successfully constructed on flexible plastics by top-down approaches. Ten arrayed Si NW-based NFGM devices are positioned on the first level. Cross-linked poly-4-vinylphenol (PVP) layers are spin-coated on them as isolation layers between the first and second level, and another ten devices are stacked on the cross-linked PVP isolation layers. The electrical characteristics of the representative Si NW-based NFGM devices on the first and second levels exhibit threshold voltage shifts, indicating the trapping and detrapping of electrons in their NPs nodes. They have an average threshold voltage shift of 2.5 V with good retention times of more than 5 x 10(4) s. Moreover, most of the devices successfully retain their electrical characteristics after about one thousand bending cycles. These well-arrayed and stacked Si NW-based NFGM devices demonstrate the potential of nanowire-based devices for large-scale integration.

Reduction of CMOS Image Sensor Read Noise to Enable Photon Counting.

PubMed

Guidash, Michael; Ma, Jiaju; Vogelsang, Thomas; Endsley, Jay

2016-04-09

Recent activity in photon counting CMOS image sensors (CIS) has been directed to reduction of read noise. Many approaches and methods have been reported. This work is focused on providing sub 1 e(-) read noise by design and operation of the binary and small signal readout of photon counting CIS. Compensation of transfer gate feed-through was used to provide substantially reduced CDS time and source follower (SF) bandwidth. SF read noise was reduced by a factor of 3 with this method. This method can be applied broadly to CIS devices to reduce the read noise for small signals to enable use as a photon counting sensor.

Nanosecond monolithic CMOS readout cell

DOEpatents

Souchkov, Vitali V.

2004-08-24

A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

Error analysis and prevention of cosmic ion-induced soft errors in static CMOS RAMs

NASA Astrophysics Data System (ADS)

Diehl, S. E.; Ochoa, A., Jr.; Dressendorfer, P. V.; Koga, P.; Kolasinski, W. A.

1982-12-01

Cosmic ray interactions with memory cells are known to cause temporary, random, bit errors in some designs. The sensitivity of polysilicon gate CMOS static RAM designs to logic upset by impinging ions has been studied using computer simulations and experimental heavy ion bombardment. Results of the simulations are confirmed by experimental upset cross-section data. Analytical models have been extended to determine and evaluate design modifications which reduce memory cell sensitivity to cosmic ions. A simple design modification, the addition of decoupling resistance in the feedback path, is shown to produce static RAMs immune to cosmic ray-induced bit errors.

Simulation and measurement of total ionizing dose radiation induced image lag increase in pinned photodiode CMOS image sensors

NASA Astrophysics Data System (ADS)

Liu, Jing; Chen, Wei; Wang, Zujun; Xue, Yuanyuan; Yao, Zhibin; He, Baoping; Ma, Wuying; Jin, Junshan; Sheng, Jiangkun; Dong, Guantao

2017-06-01

This paper presents an investigation of total ionizing dose (TID) induced image lag sources in pinned photodiodes (PPD) CMOS image sensors based on radiation experiments and TCAD simulation. The radiation experiments have been carried out at the Cobalt -60 gamma-ray source. The experimental results show the image lag degradation is more and more serious with increasing TID. Combining with the TCAD simulation results, we can confirm that the junction of PPD and transfer gate (TG) is an important region forming image lag during irradiation. These simulations demonstrate that TID can generate a potential pocket leading to incomplete transfer.

A time-resolved image sensor for tubeless streak cameras

NASA Astrophysics Data System (ADS)

Yasutomi, Keita; Han, SangMan; Seo, Min-Woong; Takasawa, Taishi; Kagawa, Keiichiro; Kawahito, Shoji

2014-03-01

This paper presents a time-resolved CMOS image sensor with draining-only modulation (DOM) pixels for tube-less streak cameras. Although the conventional streak camera has high time resolution, the device requires high voltage and bulky system due to the structure with a vacuum tube. The proposed time-resolved imager with a simple optics realize a streak camera without any vacuum tubes. The proposed image sensor has DOM pixels, a delay-based pulse generator, and a readout circuitry. The delay-based pulse generator in combination with an in-pixel logic allows us to create and to provide a short gating clock to the pixel array. A prototype time-resolved CMOS image sensor with the proposed pixel is designed and implemented using 0.11um CMOS image sensor technology. The image array has 30(Vertical) x 128(Memory length) pixels with the pixel pitch of 22.4um. .

Si light-emitting device in integrated photonic CMOS ICs

NASA Astrophysics Data System (ADS)

Xu, Kaikai; Snyman, Lukas W.; Aharoni, Herzl

2017-07-01

The motivation for integrated Si optoelectronics is the creation of low-cost photonics for mass-market applications. Especially, the growing demand for sensitive biochemical sensors in the environmental control or medicine leads to the development of integrated high resolution sensors. Here CMOS-compatible Si light-emitting device structures are presented for investigating the effect of various depletion layer profiles and defect engineering on the photonic transition in the 1.4-2.8 eV. A novel Si device is proposed to realize both a two-terminal Si-diode light-emitting device and a three-terminal Si gate-controlled diode light-emitting device in the same device structure. In addition to the spectral analysis, differences between two-terminal and three-terminal devices are discussed, showing the light emission efficiency change. The proposed Si optical source may find potential applications in micro-photonic systems and micro-optoelectro-mechanical systems (MOEMS) in CMOS integrated circuitry.

A wideband CMOS single-ended low noise amplifier employing negative resistance technique

NASA Astrophysics Data System (ADS)

Guo, Benqing; Chen, Hongpeng; Wang, Xuebing; Chen, Jun; Li, Yueyue; Jin, Haiyan; Yang, Yongjun

2018-02-01

A wideband common-gate CMOS low noise amplifier with negative resistance technique is proposed. A novel single-ended negative resistance structure is employed to improve gain and noise of the LNA. The inductor resonating is adopted at the input stage and load stage to meet wideband matching and compensate gain roll-off at higher frequencies. Implemented in a 0.18 μm CMOS technology, the proposed LNA demonstrates in simulations a maximal gain of 16.4 dB across the 3 dB bandwidth of 0.2-3 GHz. The in-band noise figure of 3.4-4.7 dB is obtained while the IIP3 of 5.3-6.8 dBm and IIP2 of 12.5-17.2 dBm are post-simulated in the designed frequency band. The LNA core consumes a power dissipation of 3.8 mW under a 1.5 V power supply.

Optical, analog and digital domain architectural considerations for visual communications

NASA Astrophysics Data System (ADS)

Metz, W. A.

2008-01-01

The end of the performance entitlement historically achieved by classic scaling of CMOS devices is within sight, driven ultimately by fundamental limits. Performance entitlements predicted by classic CMOS scaling have progressively failed to be realized in recent process generations due to excessive leakage, increasing interconnect delays and scaling of gate dielectrics. Prior to reaching fundamental limits, trends in technology, architecture and economics will pressure the industry to adopt new paradigms. A likely response is to repartition system functions away from digital implementations and into new architectures. Future architectures for visual communications will require extending the implementation into the optical and analog processing domains. The fundamental properties of these domains will in turn give rise to new architectural concepts. The limits of CMOS scaling and impact on architectures will be briefly reviewed. Alternative approaches in the optical, electronic and analog domains will then be examined for advantages, architectural impact and drawbacks.

Push the flash floating gate memories toward the future low energy application

NASA Astrophysics Data System (ADS)

Della Marca, V.; Just, G.; Regnier, A.; Ogier, J.-L.; Simola, R.; Niel, S.; Postel-Pellerin, J.; Lalande, F.; Masoero, L.; Molas, G.

2013-01-01

In this paper the energy consumption of flash floating gate cell, during a channel hot electron operation, is investigated. We characterize the device using different ramp and box pulses on control gate, to find the best solution to have low energy consumption and good cell performances. We use a new dynamic method to measure the drain current absorption in order to evaluate the impact of different bias conditions, and to study the cell behavior. The programming window and the energy consumption are considered as fundamental parameters. Using this dynamic technique, three zones of work are found; it is possible to optimize the drain voltage during the programming operation to minimize the energy consumption. Moreover, the cell's performances are improved using the CHISEL effect, with a reverse body bias. After the study concerning the programming pulses adjusting, we show the results obtained by increasing the channel doping dose parameter. Considering a channel hot electron programming operation, it is important to focus our attention on the bitline leakage consumption contribution. We measured it for the unselected bitline cells, and we show the effects of the lightly doped drain implantation energy on the leakage current. In this way the impact of gate induced drain leakage in band-to-band tunneling regime decreases, improving the cell's performances in a memory array.

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2018-03-01

In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.

Automatic Digital Hardware Synthesis

DTIC Science & Technology

1990-09-01

VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate array (FPGAI using...process of translating VHDL to PALASM, a hardware synthesis language. The PALASM description is then directly implemented into a field programmable gate...allows the engineer to use VHDL to create and validate a design, and then to implement it in a gate array. The development of software o translate VHDL

Differential-Mode Biosensor Using Dual Extended-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Choi, Jinhyeon; Lee, Hee Ho; Ahn, Jungil; Seo, Sang-Ho; Shin, Jang-Kyoo

2012-06-01

In this paper, we present a differential-mode biosensor using dual extended-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), which possesses the advantages of both the extended-gate structure and the differential-mode operation. The extended-gate MOSFET was fabricated using a 0.6 µm standard complementary metal oxide semiconductor (CMOS) process. The Au extended gate is the sensing gate on which biomolecules are immobilized, while the Pt extended gate is the dummy gate for use in the differential-mode detection circuit. The differential-mode operation offers many advantages such as insensitivity to the variation of temperature and light, as well as low noise. The outputs were measured using a semiconductor parameter analyzer in a phosphate buffered saline (PBS; pH 7.4) solution. A standard Ag/AgCl reference electrode was used to apply the gate bias. We measured the variation of output voltage with time, temperature, and light intensity. The bindings of self-assembled monolayer (SAM), streptavidin, and biotin caused a variation in the output voltage of the differential-mode detection circuit and this was confirmed by surface plasmon resonance (SPR) experiment. Biotin molecules could be detected up to a concentration of as low as 0.001 µg/ml.

Low-voltage all-inorganic perovskite quantum dot transistor memory

NASA Astrophysics Data System (ADS)

Chen, Zhiliang; Zhang, Yating; Zhang, Heng; Yu, Yu; Song, Xiaoxian; Zhang, Haiting; Cao, Mingxuan; Che, Yongli; Jin, Lufan; Li, Yifan; Li, Qingyan; Dai, Haitao; Yang, Junbo; Yao, Jianquan

2018-05-01

An all-inorganic cesium lead halide quantum dot (QD) based Au nanoparticle (NP) floating-gate memory with a solution processed layer-by-layer method is demonstrated. Easy synthesis at room temperature and excellent stability make all-inorganic CsPbBr3 perovskite QDs suitable as a semiconductor layer in low voltage nonvolatile transistor memory. The bipolarity of QDs has both electrons and holes stored in the Au NP floating gate, resulting in bidirectional shifts of initial threshold voltage according to the applied programing and erasing pulses. Under low operation voltage (±5 V), the memory achieved a great memory window (˜2.4 V), long retention time (>105 s), and stable endurance properties after 200 cycles. So the proposed memory device based on CsPbBr3 perovskite QDs has a great potential in the flash memory market.

Paranoia.Ada: A diagnostic program to evaluate Ada floating-point arithmetic

NASA Technical Reports Server (NTRS)

Hjermstad, Chris

1986-01-01

Many essential software functions in the mission critical computer resource application domain depend on floating point arithmetic. Numerically intensive functions associated with the Space Station project, such as emphemeris generation or the implementation of Kalman filters, are likely to employ the floating point facilities of Ada. Paranoia.Ada appears to be a valuabe program to insure that Ada environments and their underlying hardware exhibit the precision and correctness required to satisfy mission computational requirements. As a diagnostic tool, Paranoia.Ada reveals many essential characteristics of an Ada floating point implementation. Equipped with such knowledge, programmers need not tremble before the complex task of floating point computation.

CMOS gate array characterization procedures

NASA Astrophysics Data System (ADS)

Spratt, James P.

1993-09-01

Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate

NASA Astrophysics Data System (ADS)

Ahmad, Nabihah; Hakimi Mokhtar, Ahmad; Othman, Nurmiza binti; Fhong Soon, Chin; Rahman, Ab Al Hadi Ab

2017-08-01

Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2×2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160μm x 420.3μm (67.25 mm2). This design achieved a low power consumption of 122.85μW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.

SRAM Based Re-programmable FPGA for Space Applications

NASA Technical Reports Server (NTRS)

Wang, J. J.; Sun, J. S.; Cronquist, B. E.; McCollum, J. L.; Speers, T. M.; Plants, W. C.; Katz, R. B.

1999-01-01

An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

3-D Observation of dopant distribution at NAND flash memory floating gate using Atom probe tomography

NASA Astrophysics Data System (ADS)

Lee, Ji-hyun; Chae, Byeong-Kyu; Kim, Joong-Jeong; Lee, Sun Young; Park, Chan Gyung

2015-01-01

Dopant control becomes more difficult and critical as silicon devices become smaller. We observed the dopant distribution in a thermally annealed polysilicon gate using Transmission Electron Microscopy (TEM) and Atom probe tomography (APT). Phosphorus was doped at the silicon-nitride-diffusion-barrier-layer-covered polycrystalline silicon gate. Carbon also incorporated at the gate for the enhancement of operation uniformity. The impurity distribution was observed using atom probe tomography. The carbon atoms had segregated at grain boundaries and suppressed silicon grain growth. Phosphorus atoms, on the other hand, tended to pile-up at the interface. A 1-nm-thick diffusion barrier effectively blocked P atom out-diffusion. [Figure not available: see fulltext.

Energy efficient circuit design using nanoelectromechanical relays

NASA Astrophysics Data System (ADS)

Venkatasubramanian, Ramakrishnan

Nano-electromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behave like an ideal switch. Recent advances in planar fabrication technology have demonstrated that microelectromechanical (MEMS) scale miniature relays could be manufactured reliably and could be used to build fully functional, complex integrated circuits. The zero leakage operation of relays has renewed the interest in relay based low power logic design. This dissertation explores circuit architectures using NEM relays and NEMS-CMOS heterogeneous integration. Novel circuit topologies for sequential logic, memory, and power management circuits have been proposed taking into consideration the NEM relay device properties and optimizing for energy efficiency and area. In nanoscale electromechanical devices, dispersion forces like Van der Waals' force (vdW) affect the pull-in stability of the relay devices significantly. Verilog-A electromechanical model of the suspended gate relay operating at 1V with a nominal air gap of 5 - 10nm has been developed taking into account all the electrical, mechanical and dispersion effects. This dissertation explores different relay based latch and flip-flop topologies. It has been shown that as few as 4 relay cells could be used to build flip-flops. An integrated voltage doubler based flip flop that improves the performance by 2X by overdriving Vgb has been proposed. Three NEM relay based parallel readout memory bitcell architectures have been proposed that have faster access time, and remove the reliability issues associated with previously reported serial readout architectures. A paradigm shift in design of power switches using NEM relays is proposed. An interesting property of the relay device is that the ON state resistance (Ron) of the NEM relay switch is constant and is insensitive to the gate slew rate. This coupled with infinite OFF state resistance (Roff ) offers significant area and power advantages over CMOS. This dissertation demonstrates NEM relay based charge pump and NEM-CMOS heterogeneous discontinuous conduction mode (DCM) buck regulator and the results are compared against a standard commercial 0.35μm CMOS implementation. It is shown that NEM-CMOS heterogeneous DC-DC converter has an area savings of 60% over CMOS and achieves an overall higher efficiency over CMOS, with a peak efficiency of 94.3% at 100mA. NEM relays offers unprecedented 10X-30X energy efficiency improvement in logic design for low frequency operation and has the potential to break the CMOS efficiency barrier in power electronic circuits as well. The practical aspects of NEM Relay integration are evaluated and algorithms for synthesis and development of large NEM relay based logic circuits are explored.

A 50Mbit/Sec. CMOS Video Linestore System

NASA Astrophysics Data System (ADS)

Jeung, Yeun C.

1988-10-01

This paper reports the architecture, design and test results of a CMOS single chip programmable video linestore system which has 16-bit data words with 1024 bit depth. The delay is fully programmable from 9 to 1033 samples by a 10 bit binary control word. The large 16 bit data word width makes the chip useful for a wide variety of digital video signal processing applications such as DPCM coding, High-Definition TV, and Video scramblers/descramblers etc. For those applications, the conventional large fixed-length shift register or static RAM scheme is not very popular because of its lack of versatility, high power consumption, and required support circuitry. The very high throughput of 50Mbit/sec is made possible by a highly parallel, pipelined dynamic memory architecture implemented in a 2-um N-well CMOS technology. The basic cell of the programmable video linestore chip is an four transistor dynamic RAM element. This cell comprises the majority of the chip's real estate, consumes no static power, and gives good noise immunity to the simply designed sense amplifier. The chip design was done using Bellcore's version of the MULGA virtual grid symbolic layout system. The chip contains approximately 90,000 transistors in an area of 6.5 x 7.5 square mm and the I/Os are TTL compatible. The chip is packaged in a 68-pin leadless ceramic chip carrier package.

Multifunctional Logic Gate Controlled by Supply Voltage

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Zebulum, Ricardo

2005-01-01

A complementary metal oxide/semiconductor (CMOS) electronic circuit functions as a NAND gate at a power-supply potential (V(sub dd)) of 3.3 V and as NOR gate for V(sub dd) = 1.8 V. In the intermediate V(sub dd) range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics -- a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of V(sub dd).

Trends in Implementation: The Intensive Partnerships for Effective Teaching through 2013-2014. Executive Summary

ERIC Educational Resources Information Center

RAND Corporation, 2016

2016-01-01

Can districts and charter management organizations (CMOs) use contemporary ideas about teacher evaluation, management, and support to spark big improvements in student outcomes? To answer this question, the Bill & Melinda Gates Foundation launched the Intensive Partnerships for Effective Teaching initiative with seven sites across the country…

An inherent curvature-compensated voltage reference using non-linearity of gate coupling coefficient

NASA Astrophysics Data System (ADS)

Hande, Vinayak; Shojaei Baghini, Maryam

2015-08-01

A novel current-mode voltage reference circuit which is capable of generating sub-1 V output voltage is presented. The proposed architecture exhibits the inherent curvature compensation ability. The curvature compensation is achieved by utilizing the non-linear behavior of gate coupling coefficient to compensate non-linear temperature dependence of base-emitter voltage. We have also utilized the developments in CMOS process to reduce power and area consumption. The proposed voltage reference is analyzed theoretically and compared with other existing methods. The circuit is designed and simulated in 180 nm mixed-mode CMOS UMC technology which gives a reference level of 246 mV. The minimum required supply voltage is 1 V with maximum current drawn of 9.24 μA. A temperature coefficient of 9 ppm/°C is achieved over -25 to 125 °C temperature range. The reference voltage varies by ±11 mV across process corners. The reference circuit shows the line sensitivity of 0.9 mV/V with area consumption of 100 × 110 μm2

Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.

PubMed

Yu, T; Sejnowski, T J; Cauwenberghs, G

2011-10-01

We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers

PubMed Central

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Abstract Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlOx), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers. PMID:28634499

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

PubMed

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

MOSFET Power Controller

NASA Technical Reports Server (NTRS)

Mitchell, J.; Jones, K.

1986-01-01

High current and voltage controlled remotely. Remote Power Conroller includes two series-connected banks of parallel-connected MOSFET's to withstand high current and voltage. Voltage sharing between switch banks, low-impedance, gate-drive circuits used. Provided controlled range for turn on. Individually trimmable to insure simultaneous switching within few nanoseconds during both turn on and turn off. Control circuit for each switch bank and over-current trip circuit float independently and supplied power via transformer T1 from inverter. Control of floating stages by optocouplers.

Event-driven charge-coupled device design and applications therefor

NASA Technical Reports Server (NTRS)

Doty, John P. (Inventor); Ricker, Jr., George R. (Inventor); Burke, Barry E. (Inventor); Prigozhin, Gregory Y. (Inventor)

2005-01-01

An event-driven X-ray CCD imager device uses a floating-gate amplifier or other non-destructive readout device to non-destructively sense a charge level in a charge packet associated with a pixel. The output of the floating-gate amplifier is used to identify each pixel that has a charge level above a predetermined threshold. If the charge level is above a predetermined threshold the charge in the triggering charge packet and in the charge packets from neighboring pixels need to be measured accurately. A charge delay register is included in the event-driven X-ray CCD imager device to enable recovery of the charge packets from neighboring pixels for accurate measurement. When a charge packet reaches the end of the charge delay register, control logic either dumps the charge packet, or steers the charge packet to a charge FIFO to preserve it if the charge packet is determined to be a packet that needs accurate measurement. A floating-diffusion amplifier or other low-noise output stage device, which converts charge level to a voltage level with high precision, provides final measurement of the charge packets. The voltage level is eventually digitized by a high linearity ADC.

Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

NASA Astrophysics Data System (ADS)

Liaw, Yue-Gie; Chen, Chii-Wen; Liao, Wen-Shiang; Wang, Mu-Chun; Zou, Xuecheng

2018-05-01

Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of Id-Vg characteristics, threshold voltage (Vt), and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance (RSD), channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance (Gm) and drive current.

Gate-Driven Pure Spin Current in Graphene

NASA Astrophysics Data System (ADS)

Lin, Xiaoyang; Su, Li; Si, Zhizhong; Zhang, Youguang; Bournel, Arnaud; Zhang, Yue; Klein, Jacques-Olivier; Fert, Albert; Zhao, Weisheng

2017-09-01

The manipulation of spin current is a promising solution for low-power devices beyond CMOS. However, conventional methods, such as spin-transfer torque or spin-orbit torque for magnetic tunnel junctions, suffer from large power consumption due to frequent spin-charge conversions. An important challenge is, thus, to realize long-distance transport of pure spin current, together with efficient manipulation. Here, the mechanism of gate-driven pure spin current in graphene is presented. Such a mechanism relies on the electrical gating of carrier-density-dependent conductivity and spin-diffusion length in graphene. The gate-driven feature is adopted to realize the pure spin-current demultiplexing operation, which enables gate-controllable distribution of the pure spin current into graphene branches. Compared with the Elliott-Yafet spin-relaxation mechanism, the D'yakonov-Perel spin-relaxation mechanism results in more appreciable demultiplexing performance. The feature of the pure spin-current demultiplexing operation will allow a number of logic functions to be cascaded without spin-charge conversions and open a route for future ultra-low-power devices.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Toward spin-based Magneto Logic Gate in Graphene

NASA Astrophysics Data System (ADS)

Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Zutic, Igor; Krivorotov, Ilya; Sham, Lu; Kawakami, Roland

Graphene has emerged as a leading candidate for spintronic applications due to its long spin diffusion length at room temperature. A universal magnetologic gate (MLG) based on spin transport in graphene has been recently proposed as the building block of a logic circuit which could replace the current CMOS technology. This MLG has five ferromagnetic electrodes contacting a graphene channel and can be considered as two three-terminal XOR logic gates. Here we demonstrate this XOR logic gate operation in such a device. This was achieved by systematically tuning the injection current bias to balance the spin polarization efficiency of the two inputs, and offset voltage in the detection circuit to obtain binary outputs. The output is a current which corresponds to different logic states: zero current is logic `0', and nonzero current is logic `1'. We find improved performance could be achieved by reducing device size and optimizing the contacts.

A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA.

PubMed

Ahmad, Peer Zahoor; Quadri, S M K; Ahmad, Firdous; Bahar, Ali Newaz; Wani, Ghulam Mohammad; Tantary, Shafiq Maqbool

2017-12-01

Quantum-dot cellular automata, is an extremely small size and a powerless nanotechnology. It is the possible alternative to current CMOS technology. Reversible QCA logic is the most important issue at present time to reduce power losses. This paper presents a novel reversible logic gate called the F-Gate. It is simplest in design and a powerful technique to implement reversible logic. A systematic approach has been used to implement a novel single layer reversible Full-Adder, Full-Subtractor and a Full Adder-Subtractor using the F-Gate. The proposed Full Adder-Subtractor has achieved significant improvements in terms of overall circuit parameters among the most previously cost-efficient designs that exploit the inevitable nano-level issues to perform arithmetic computing. The proposed designs have been authenticated and simulated using QCADesigner tool ver. 2.0.3.

A Discussion of Using a Reconfigurable Processor to Implement the Discrete Fourier Transform

NASA Technical Reports Server (NTRS)

White, Michael J.

2004-01-01

This paper presents the design and implementation of the Discrete Fourier Transform (DFT) algorithm on a reconfigurable processor system. While highly applicable to many engineering problems, the DFT is an extremely computationally intensive algorithm. Consequently, the eventual goal of this work is to enhance the execution of a floating-point precision DFT algorithm by off loading the algorithm from the computing system. This computing system, within the context of this research, is a typical high performance desktop computer with an may of field programmable gate arrays (FPGAs). FPGAs are hardware devices that are configured by software to execute an algorithm. If it is desired to change the algorithm, the software is changed to reflect the modification, then download to the FPGA, which is then itself modified. This paper will discuss methodology for developing the DFT algorithm to be implemented on the FPGA. We will discuss the algorithm, the FPGA code effort, and the results to date.

Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies

NASA Astrophysics Data System (ADS)

Vishnoi, U.; Noll, T. G.

2012-09-01

The COordinate Rotate DIgital Computer (CORDIC) algorithm is a well known versatile approach and is widely applied in today's SoCs for especially but not restricted to digital communications. Dedicated CORDIC blocks can be implemented in deep sub-micron CMOS technologies at very low area and energy costs and are attractive to be used as hardware accelerators for Application Specific Instruction Processors (ASIPs). Thereby, overcoming the well known energy vs. flexibility conflict. Optimizing Global Navigation Satellite System (GNSS) receivers to reduce the hardware complexity is an important research topic at present. In such receivers CORDIC accelerators can be used for digital baseband processing (fixed-point) and in Position-Velocity-Time estimation (floating-point). A micro architecture well suited to such applications is presented. This architecture is parameterized according to the wordlengths as well as the number of iterations and can be easily extended for floating point data format. Moreover, area can be traded for throughput by partially or even fully unrolling the iterations, whereby the degree of pipelining is organized with one CORDIC iteration per cycle. From the architectural description, the macro layout can be generated fully automatically using an in-house datapath generator tool. Since the adders and shifters play an important role in optimizing the CORDIC block, they must be carefully optimized for high area and energy efficiency in the underlying technology. So, for this purpose carry-select adders and logarithmic shifters have been chosen. Device dimensioning was automatically optimized with respect to dynamic and static power, area and performance using the in-house tool. The fully sequential CORDIC block for fixed-point digital baseband processing features a wordlength of 16 bits, requires 5232 transistors, which is implemented in a 40-nm CMOS technology and occupies a silicon area of 1560 μm2 only. Maximum clock frequency from circuit simulation of extracted netlist is 768 MHz under typical, and 463 MHz under worst case technology and application corner conditions, respectively. Simulated dynamic power dissipation is 0.24 uW MHz-1 at 0.9 V; static power is 38 uW in slow corner, 65 uW in typical corner and 518 uW in fast corner, respectively. The latter can be reduced by 43% in a 40-nm CMOS technology using 0.5 V reverse-backbias. These features are compared with the results from different design styles as well as with an implementation in 28-nm CMOS technology. It is interesting that in the latter case area scales as expected, but worst case performance and energy do not scale well anymore.

Wavelength dependence and multiple-induced states in photoresponses of copper phthalocyanine-doped gold nanoparticle single-electron device

NASA Astrophysics Data System (ADS)

Yamamoto, Makoto; Ueda, Rieko; Terui, Toshifumi; Imazu, Keisuke; Tamada, Kaoru; Sakano, Takeshi; Matsuda, Kenji; Ishii, Hisao; Noguchi, Yutaka

2014-01-01

We have proposed a gold nanoparticle (GNP)-based single-electron transistor (SET) doped with a dye molecule, where the molecule works as a photoresponsive floating gate. Here, we examined the source-drain current (I_{\\text{SD}}) at a constant drain voltage under light irradiation with various wavelengths ranging from 400 to 700 nm. Current change was enhanced at the wavelengths of 600 and 700 nm, corresponding to the optical absorption band of the doped molecule (copper phthalocyanine: CuPc). Moreover, several peaks appear in the histograms of I_{\\text{SD}} during light irradiation, indicating that multiple discrete states were induced in the device. The results suggest that the current change was initiated by the light absorption of CuPc and multiple CuPc molecules near the GNP working as a floating gate. Molecular doping can activate advanced device functions in GNP-based SETs.

Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

NASA Astrophysics Data System (ADS)

Chambonneau, Maxime; Souiki-Figuigui, Sarra; Chiquet, Philippe; Della Marca, Vincenzo; Postel-Pellerin, Jérémy; Canet, Pierre; Portal, Jean-Michel; Grojo, David

2017-04-01

We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables us to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, and defectivity) and for considerable developments in the growing field of ultrafast microelectronics.

A fast and low-power microelectromechanical system-based non-volatile memory device

PubMed Central

Lee, Sang Wook; Park, Seung Joo; Campbell, Eleanor E. B.; Park, Yung Woo

2011-01-01

Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices. PMID:21364559

Models for Total-Dose Radiation Effects in Non-Volatile Memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Campbell, Philip Montgomery; Wix, Steven D.

The objective of this work is to develop models to predict radiation effects in non- volatile memory: flash memory and ferroelectric RAM. In flash memory experiments have found that the internal high-voltage generators (charge pumps) are the most sensitive to radiation damage. Models are presented for radiation effects in charge pumps that demonstrate the experimental results. Floating gate models are developed for the memory cell in two types of flash memory devices by Intel and Samsung. These models utilize Fowler-Nordheim tunneling and hot electron injection to charge and erase the floating gate. Erase times are calculated from the models andmore » compared with experimental results for different radiation doses. FRAM is less sensitive to radiation than flash memory, but measurements show that above 100 Krad FRAM suffers from a large increase in leakage current. A model for this effect is developed which compares closely with the measurements.« less

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement

PubMed Central

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates. PMID:26763827

Study of the enhancement-mode AlGaN/GaN high electron mobility transistor with split floating gates

NASA Astrophysics Data System (ADS)

Wang, Hui; Wang, Ning; Jiang, Ling-Li; Zhao, Hai-Yue; Lin, Xin-Peng; Yu, Hong-Yu

2017-11-01

In this work, the charge storage based split floating gates (FGs) enhancement mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs) are studied. The simulation results reveal that under certain density of two dimensional electron gas, the variation tendency of the threshold voltage (Vth) with the variation of the blocking dielectric thickness depends on the FG charge density. It is found that when the length sum and isolating spacing sum of the FGs both remain unchanged, the Vth shall decrease with the increasing FGs number but maintaining the device as E-mode. It is also reported that for the FGs HEMT, the failure of a FG will lead to the decrease of Vth as well as the increase of drain current, and the failure probability can be improved significantly with the increase of FGs number.

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement.

PubMed

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates.

Reduced distribution of threshold voltage shift in double layer NiSi2 nanocrystals for nano-floating gate memory applications.

PubMed

Choi, Sungjin; Lee, Junhyuk; Kim, Donghyoun; Oh, Seulki; Song, Wangyu; Choi, Seonjun; Choi, Eunsuk; Lee, Seung-Beck

2011-12-01

We report on the fabrication and capacitance-voltage characteristics of double layer nickel-silicide nanocrystals with Si3N4 interlayer tunnel barrier for nano-floating gate memory applications. Compared with devices using SiO2 interlayer, the use of Si3N4 interlayer separation reduced the average size (4 nm) and distribution (+/- 2.5 nm) of NiSi2 nanocrystal (NC) charge traps by more than 50% and giving a two fold increase in NC density to 2.3 x 10(12) cm(-2). The increased density and reduced NC size distribution resulted in a significantly decrease in the distribution of the device C-V characteristics. For each program voltage, the distribution of the shift in the threshold voltage was reduced by more than 50% on average to less than 0.7 V demonstrating possible multi-level-cell operation.

Optimization of pentacene double floating gate memories based on charge injection regulated by SAM functionalization

NASA Astrophysics Data System (ADS)

Li, S.; Guérin, D.; Lenfant, S.; Lmimouni, K.

2018-02-01

Pentacene based double nano-floating gate memories (NFGM) by using gold nanoparticles (Au NPs) and reduced graphene oxide (rGO) sheets as charge trapping layers are prepared and demonstrated. Particularly, the NFGM chemically treated by 2,3,4,5,6-pentafluorobenzenethiol (PFBT) self-assembled monolayers (SAM) exhibits excellent memory performances, including high mobility of 0.23 cm2V-1s-1, the large memory window of 51 V, and the stable retention property more than 108 s. Comparing the performances of NFGM without treating with PFBT SAM, the improving performances of the memory devices by SAM modification are explained by the increase of charge injection, which could be further investigated by XPS and UPS. In particular, the results highlight the utility of SAM modulations and controlling of charge transport in the development of organic transistor memories.

Quantitative Analysis of Charge Injection and Discharging of Si Nanocrystals and Arrays by Electrostatic Force Microscopy

NASA Technical Reports Server (NTRS)

Bell, L. D.; Boer, E.; Ostraat, M.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.

2000-01-01

NASA requirements for computing and memory for microspacecraft emphasize high density, low power, small size, and radiation hardness. The distributed nature of storage elements in nanocrystal floating-gate memories leads to intrinsic fault tolerance and radiation hardness. Conventional floating-gate non-volatile memories are more susceptible to radiation damage. Nanocrystal-based memories also offer the possibility of faster, lower power operation. In the pursuit of filling these requirements, the following tasks have been accomplished: (1) Si nanocrystal charging has been accomplished with conducting-tip AFM; (2) Both individual nanocrystals on an oxide surface and nanocrystals formed by implantation have been charged; (3) Discharging is consistent with tunneling through a field-lowered oxide barrier; (4) Modeling of the response of the AFM to trapped charge has allowed estimation of the quantity of trapped charge; and (5) Initial attempts to fabricate competitive nanocrystal non-volatile memories have been extremely successful.

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

NASA Astrophysics Data System (ADS)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors complicates the use of feedback circuits. Thus feedback is generally not used in the front-end of our digital process CMOS receivers.

Thin Film Complementary Metal Oxide Semiconductor (CMOS) Device Using a Single-Step Deposition of the Channel Layer

PubMed Central

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wang, Zhenwei; Hedhili, M. N.; Wang, Q. X.; Alshareef, H. N.

2014-01-01

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n- and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350°C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications. PMID:24728223

BIMOS transistor solutions for ESD protection in FD-SOI UTBB CMOS technology

NASA Astrophysics Data System (ADS)

Galy, Philippe; Athanasiou, S.; Cristoloveanu, S.

2016-01-01

We evaluate the Electro-Static Discharge (ESD) protection capability of BIpolar MOS (BIMOS) transistors integrated in ultrathin silicon film for 28 nm Fully Depleted SOI (FD-SOI) Ultra Thin Body and BOX (UTBB) high-k metal gate technology. Using as a reference our measurements in hybrid bulk-SOI structures, we extend the BIMOS design towards the ultrathin silicon film. Detailed study and pragmatic evaluations are done based on 3D TCAD simulation with standard physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope AVS method). These preliminary 3D TACD results are very encouraging in terms of ESD protection efficiency in advanced FD-SOI CMOS.

Radiation tolerant 1 micron CMOS technology

NASA Astrophysics Data System (ADS)

Crevel, P.; Rodde, K.

1991-03-01

Starting from a standard one micron Complementary Metal Oxide Semiconductor (CMOS) for high density, low power memory applications, the degree of radiation tolerance of the baseline process is evaluated. Implemented process modifications to improve latchup sensitivity under heavy ion irradiation as well as total dose effects without changing layout rules are described. By changing doping profiles in Metal Nitride Oxide Semiconductors (MNOS) and P-channel MOS (PMOS) device regions, it is possible to guarantee data sheet specification of a 64 K low power static RAM for total gamma dose up to 35 krad (Si) (and even higher values for the gate array family) without latch up for Linear Energy Transfer LET up to 115 MeV/(mg/cm squared).

Study of Reversible Logic Synthesis with Application in SOC: A Review

NASA Astrophysics Data System (ADS)

Sharma, Chinmay; Pahuja, Hitesh; Dadhwal, Mandeep; Singh, Balwinder

2017-08-01

The prime concern in today’s SOC designs is the power dissipation which increases with technology scaling. The reversible logic possesses very high potential in reducing power dissipation in these designs. It finds its application in latest research fields such as DNA computing, quantum computing, ultra-low power CMOS design and nanotechnology. The reversible circuits can be easily designed using the conventional CMOS technology at a cost of a garbage output which maintains the reversibility. The purpose of this paper is to provide an overview of the developments that have occurred till date in this concept and how the new reversible logic gates are used to design the logic functions.

Reduction of CMOS Image Sensor Read Noise to Enable Photon Counting

PubMed Central

Guidash, Michael; Ma, Jiaju; Vogelsang, Thomas; Endsley, Jay

2016-01-01

Recent activity in photon counting CMOS image sensors (CIS) has been directed to reduction of read noise. Many approaches and methods have been reported. This work is focused on providing sub 1 e− read noise by design and operation of the binary and small signal readout of photon counting CIS. Compensation of transfer gate feed-through was used to provide substantially reduced CDS time and source follower (SF) bandwidth. SF read noise was reduced by a factor of 3 with this method. This method can be applied broadly to CIS devices to reduce the read noise for small signals to enable use as a photon counting sensor. PMID:27070625

Nanowire FET Based Neural Element for Robotic Tactile Sensing Skin

PubMed Central

Taube Navaraj, William; García Núñez, Carlos; Shakthivel, Dhayalan; Vinciguerra, Vincenzo; Labeau, Fabrice; Gregory, Duncan H.; Dahiya, Ravinder

2017-01-01

This paper presents novel Neural Nanowire Field Effect Transistors (υ-NWFETs) based hardware-implementable neural network (HNN) approach for tactile data processing in electronic skin (e-skin). The viability of Si nanowires (NWs) as the active material for υ-NWFETs in HNN is explored through modeling and demonstrated by fabricating the first device. Using υ-NWFETs to realize HNNs is an interesting approach as by printing NWs on large area flexible substrates it will be possible to develop a bendable tactile skin with distributed neural elements (for local data processing, as in biological skin) in the backplane. The modeling and simulation of υ-NWFET based devices show that the overlapping areas between individual gates and the floating gate determines the initial synaptic weights of the neural network - thus validating the working of υ-NWFETs as the building block for HNN. The simulation has been further extended to υ-NWFET based circuits and neuronal computation system and this has been validated by interfacing it with a transparent tactile skin prototype (comprising of 6 × 6 ITO based capacitive tactile sensors array) integrated on the palm of a 3D printed robotic hand. In this regard, a tactile data coding system is presented to detect touch gesture and the direction of touch. Following these simulation studies, a four-gated υ-NWFET is fabricated with Pt/Ti metal stack for gates, source and drain, Ni floating gate, and Al2O3 high-k dielectric layer. The current-voltage characteristics of fabricated υ-NWFET devices confirm the dependence of turn-off voltages on the (synaptic) weight of each gate. The presented υ-NWFET approach is promising for a neuro-robotic tactile sensory system with distributed computing as well as numerous futuristic applications such as prosthetics, and electroceuticals. PMID:28979183

Development of III-V p-MOSFETs with high-kappa gate stack for future CMOS applications

NASA Astrophysics Data System (ADS)

Nagaiah, Padmaja

As the semiconductor industry approaches the limits of traditional silicon CMOS scaling, non-silicon materials and new device architectures are gradually being introduced to improve Si integrated circuit performance and continue transistor scaling. Recently, the replacement of SiO2 with a high-k material (HfO2) as gate dielectric has essentially removed one of the biggest advantages of Si as channel material. As a result, alternate high mobility materials are being considered to replace Si in the channel to achieve higher drive currents and switching speeds. III-V materials in particular have become of great interest as channel materials, owing to their superior electron transport properties. However, there are several critical challenges that need to be addressed before III-V based CMOS can replace Si CMOS technology. Some of these challenges include development of a high quality, thermally stable gate dielectric/III-V interface, and improvement in III-V p-channel hole mobility to complement the n-channel mobility, low source/drain resistance and integration onto Si substrate. In this thesis, we would be addressing the first two issues i.e. the development high performance III-V p-channels and obtaining high quality III-V/high-k interface. We start with using the device architecture of the already established InGaAs n-channels as a baseline to understand the effect of remote scattering from the high-k oxide and oxide/semiconductor interface on channel transport properties such as electron mobility and channel electron concentration. Temperature dependent Hall electron mobility measurements were performed to separate various scattering induced mobility limiting factors. Dependence of channel mobility on proximity of the channel to the oxide interface, oxide thickness, annealing conditions are discussed. The results from this work will be used in the design of the p-channel MOSFETs. Following this, InxGa1-xAs (x>0.53) is chosen as channel material for developing p-channel MOSFETs. Band engineering, strain induced valence band splitting and quantum confinement is used to improve channel hole mobility. Experimental results on the Hall hole mobility is presented for InxGa1-xAs channels with varying In content, thickness of the quantum well and temperature. Then, high mobility InxGa 1-xAs heterostructure thus obtained are integrated with in-situ deposited high-k gate oxide required for high performance p-MOSFET and discuss the challenges associated with the gated structure and draw conclusions on this material system. Antimonide based channel materials such as GaSb and InxGa 1-xSb are explored for III-V based p-MOSFETs in last two chapters. Options for Sb based strained QW channels to obtain maximum hole mobility by varying the strain, channel and barrier material, thickness of the layers etc. is discussed followed by the growth of these Sb channels on GaAs and InP substrates using molecular beam epitaxy. The physical properties of the structures such as the heterostructure quality, alloy content and surface roughness are examined via TEM, XRD and AFM. Following this, electrical measurement results on Hall hole mobility is presented. The effect of strain, alloy content, temperature and thickness on channel mobility and concentration is reported. Development of GaSb n- and p-MOS capacitor structures with in-situ deposited HfO2 gate oxide dielectric using in-situ deposited amorphous Si (a-Si) interface passivation layer (IPL) to improve the interface quality of high-k oxide and (In)GaSb surface is presented. In-situ deposited gate oxides such as Al2O3 and combination oxide of Al 2O3 and HfO2 with and without the a-Si IPL are also explored as alternate gate dielectrics. Subsequently, MOS capacitor structures using buried InGaSb QWs are demonstrated. Development of an inversion type bulk GaSb with implanted source-drain contacts and in-situ deposited gate oxide HfO2 gate oxide is discussed. The merits of biaxial compressive strain is demonstrated on strained surface and buried channel In0.36 Ga0.64Sb QW MOSFETs with thin top barrier and in-situ deposited a-Si IPL and high-k HfO2 as well as combination Al 2O3+HfO2 gate stacks and ex-situ atomic layer deposited (ALD) combination gate oxide and with thin 2 nm InAs surface passivation layer is presented. Finally, summary of the salient results from the different chapters is provided with recommendations for future research.

A simple laser locking system based on a field-programmable gate array.

PubMed

Jørgensen, N B; Birkmose, D; Trelborg, K; Wacker, L; Winter, N; Hilliard, A J; Bason, M G; Arlt, J J

2016-07-01

Frequency stabilization of laser light is crucial in both scientific and industrial applications. Technological developments now allow analog laser stabilization systems to be replaced with digital electronics such as field-programmable gate arrays, which have recently been utilized to develop such locking systems. We have developed a frequency stabilization system based on a field-programmable gate array, with emphasis on hardware simplicity, which offers a user-friendly alternative to commercial and previous home-built solutions. Frequency modulation, lock-in detection, and a proportional-integral-derivative controller are programmed on the field-programmable gate array and only minimal additional components are required to frequency stabilize a laser. The locking system is administered from a host-computer which provides comprehensive, long-distance control through a versatile interface. Various measurements were performed to characterize the system. The linewidth of the locked laser was measured to be 0.7 ± 0.1 MHz with a settling time of 10 ms. The system can thus fully match laser systems currently in use for atom trapping and cooling applications.

A simple laser locking system based on a field-programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jørgensen, N. B.; Birkmose, D.; Trelborg, K.

Frequency stabilization of laser light is crucial in both scientific and industrial applications. Technological developments now allow analog laser stabilization systems to be replaced with digital electronics such as field-programmable gate arrays, which have recently been utilized to develop such locking systems. We have developed a frequency stabilization system based on a field-programmable gate array, with emphasis on hardware simplicity, which offers a user-friendly alternative to commercial and previous home-built solutions. Frequency modulation, lock-in detection, and a proportional-integral-derivative controller are programmed on the field-programmable gate array and only minimal additional components are required to frequency stabilize a laser. The lockingmore » system is administered from a host-computer which provides comprehensive, long-distance control through a versatile interface. Various measurements were performed to characterize the system. The linewidth of the locked laser was measured to be 0.7 ± 0.1 MHz with a settling time of 10 ms. The system can thus fully match laser systems currently in use for atom trapping and cooling applications.« less

Paying for Scale: Results of a Symposium on CMO Finance

ERIC Educational Resources Information Center

Lake, Robin; Demeritt, Allison

2011-01-01

In April 2010, the Center on Reinventing Public Education (CRPE) and the Bill & Melinda Gates Foundation convened a group of researchers and financial analysts to discuss how to better understand the financing and sustainability of Charter Management Organizations (CMOs). The goals of the meeting were twofold: (1) to suggest a set of common ways…

Experimental Study of Floating-Gate-Type Metal-Oxide-Semiconductor Capacitors with Nanosize Triangular Cross-Sectional Tunnel Areas for Low Operating Voltage Flash Memory Application

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Guo, Ruofeng; Kamei, Takahiro; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Hayashida, Tetsuro; Sakamoto, Kunihiro; Ogura, Atsushi; Masahara, Meishoku

2012-06-01

The floating-gate (FG)-type metal-oxide-semiconductor (MOS) capacitors with planar (planar-MOS) and three-dimensional (3D) nanosize triangular cross-sectional tunnel areas (3D-MOS) have successfully been fabricated by introducing rapid thermal oxidation (RTO) and postdeposition annealing (PDA), and their electrical characteristics between the control gate (CG) and FG have been systematically compared. It was experimentally found in both planar- and 3D-MOS capacitors that the uniform and higher breakdown voltages are obtained by introducing RTO owing to the high-quality thermal oxide formation on the surface and etched edge regions of the n+ polycrystalline silicon (poly-Si) FG, and the leakage current is highly suppressed after PDA owing to the improved quality of the tetraethylorthosilicate (TEOS) silicon dioxide (SiO2) between CG and FG. Moreover, a lower breakdown voltage between CG and FG was obtained in the fabricated 3D-MOS capacitors as compared with that of planar-MOS capacitors thanks to the enhanced local electric field at the tips of triangular tunnel areas. The developed nanosize triangular cross-sectional tunnel area is useful for the fabrication of low operating voltage flash memories.

Semantically Aware Foundation Environment (SAFE) for Clean-Slate Design of Resilient, Adaptive Secure Hosts (CRASH)

DTIC Science & Technology

2016-02-01

system consists of a high-fidelity hardware simulation using field programmable gate arrays (FPGAs), with a set of runtime services (ConcreteWare...perimeter protection, patch, and pray” is not aligned with the threat. Programmers will not bail us out of this situation (by writing defect free code...hosted on a Field Programmable Gate Array (FPGA), with a set of runtime services (concreteware) running on the hardware. Secure applications can be

Area efficient layout design of CMOS circuit for high-density ICs

NASA Astrophysics Data System (ADS)

Mishra, Vimal Kumar; Chauhan, R. K.

2018-01-01

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

270GHz SiGe BiCMOS manufacturing process platform for mmWave applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Preisler, Edward J.; Talor, George; Yan, Zhixin; Booth, Roger; Zheng, Jie; Chaudhry, Samir; Howard, David; Racanelli, Marco

2011-11-01

TowerJazz has been offering the high volume commercial SiGe BiCMOS process technology platform, SBC18, for more than a decade. In this paper, we describe the TowerJazz SBC18H3 SiGe BiCMOS process which integrates a production ready 240GHz FT / 270 GHz FMAX SiGe HBT on a 1.8V/3.3V dual gate oxide CMOS process in the SBC18 technology platform. The high-speed NPNs in SBC18H3 process have demonstrated NFMIN of ~2dB at 40GHz, a BVceo of 1.6V and a dc current gain of 1200. This state-of-the-art process also comes with P-I-N diodes with high isolation and low insertion losses, Schottky diodes capable of exceeding cut-off frequencies of 1THz, high density stacked MIM capacitors, MOS and high performance junction varactors characterized up to 50GHz, thick upper metal layers for inductors, and various resistors such as low value and high value unsilicided poly resistors, metal and nwell resistors. Applications of the SBC18H3 platform for millimeter-wave products for automotive radars, phased array radars and Wband imaging are presented.

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

NASA Astrophysics Data System (ADS)

Kumar, Manoj; Pratap, Yogesh; Haldar, Subhasis; Gupta, Mridula; Gupta, R. S.

2017-12-01

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported, to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The I ON/I OFF of ISE-CGAA-SB-MOSFET increases by 1177 times and offers steeper subthreshold slope (~60 mV/decade). However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat Duen

2005-01-01

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

Development of a Self Aligned CMOS Process for Flash Lamp Annealed Polycrystalline Silicon TFTs

NASA Astrophysics Data System (ADS)

Bischoff, Paul

The emerging active matrix liquid crystal (AMLCD) display market requires a high performing semiconductor material to meet rising standards of operation. Currently amorphous silicon (a-Si) dominates the market but it does not have the required mobility for it to be used in AMLCD manufacturing. Other materials have been developed including crystallizing a-Si into poly-silicon. A new approach to crystallization through the use of flash lamp annealing (FLA) decreases manufacturing time and greatly improves carrier mobility. Previous work on FLA silicon for the use in CMOS transistors revealed significant lateral dopant diffusion into the channel greatly increasing the minimum channel length required for a working device. This was further confounded by the gate overlap due to misalignment during lithography patterning steps. Through the use of furnace dopant activation instead of FLA dopant activation and a self aligned gate the minimum size transistor can be greatly reduced. A new lithography mask and process flow were developed for the furnace annealing and self aligned gate. Fabrication of the self aligned devices resulted in oxidation of the Molybdenum self aligned gate. Further development is needed to successfully manufacture these devices. Non-self aligned transistors were made simultaneously with self aligned devices and used the furnace activation. These devices showed an increase in sheet resistance from 250 O to 800 O and lower mobility from 380 to 40.2 V/cm2s. The lower mobility can be contributed to an increase in implanted trap density indicating furnace annealing is an inferior activation method over FLA. The minimum transistor size however was reduced from 20 to 5 mum. With improvements in the self aligned process high performing small devices can be manufactured.

Review on analog/radio frequency performance of advanced silicon MOSFETs

NASA Astrophysics Data System (ADS)

Passi, Vikram; Raskin, Jean-Pierre

2017-12-01

Aggressive gate-length downscaling of the metal-oxide-semiconductor field-effect transistor (MOSFET) has been the main stimulus for the growth of the integrated circuit industry. This downscaling, which has proved beneficial to digital circuits, is primarily the result of the need for improved circuit performance and cost reduction and has resulted in tremendous reduction of the carrier transit time across the channel, thereby resulting in very high cut-off frequencies. It is only in recent decades that complementary metal-oxide-semiconductor (CMOS) field-effect transistor (FET) has been considered as the radio frequency (RF) technology of choice. In this review, the status of the digital, analog and RF figures of merit (FoM) of silicon-based FETs is presented. State-of-the-art devices with very good performance showing low values of drain-induced barrier lowering, sub-threshold swing, high values of gate transconductance, Early voltage, cut-off frequencies, and low minimum noise figure, and good low-frequency noise characteristic values are reported. The dependence of these FoM on the device gate length is also shown, helping the readers to understand the trends and challenges faced by shorter CMOS nodes. Device performance boosters including silicon-on-insulator substrates, multiple-gate architectures, strain engineering, ultra-thin body and buried-oxide and also III-V and 2D materials are discussed, highlighting the transistor characteristics that are influenced by these boosters. A brief comparison of the two main contenders in continuing Moore’s law, ultra-thin body buried-oxide and fin field-effect transistors are also presented. The authors would like to mention that despite extensive research carried out in the semiconductor industry, silicon-based MOSFET will continue to be the driving force in the foreseeable future.

A reconfigurable medically cohesive biomedical front-end with ΣΔ ADC in 0.18µm CMOS.

PubMed

Jha, Pankaj; Patra, Pravanjan; Naik, Jairaj; Acharya, Amit; Rajalakshmi, P; Singh, Shiv Govind; Dutta, Ashudeb

2015-08-01

This paper presents a generic programmable analog front-end (AFE) for acquisition and digitization of various biopotential signals. This includes a lead-off detection circuit, an ultra-low current capacitively coupled signal conditioning stage with programmable gain and bandwidth, a new mixed signal automatic gain control (AGC) mechanism and a medically cohesive reconfigurable ΣΔ ADC. The full system is designed in UMC 0.18μm CMOS. The AFE achieves an overall linearity of more 10 bits with 0.47μW power consumption. The ADC provides 2(nd) order noise-shaping while using single integrator and an ENOB of ~11 bits with 5μW power consumption. The system was successfully verified for various ECG signals from PTB database. This system is intended for portable batteryless u-Healthcare devices.

Synthesis and electron storage characteristics of isolated silver nanodots on/embedded in Al 2O 3 gate dielectric

NASA Astrophysics Data System (ADS)

Wang, Q.; Song, Z. T.; Liu, W. L.; Lin, C. L.; Wang, T. H.

2004-05-01

Monolayer-isolated silver (Ag) nanodots with the average diameter down to 7 nm are synthesized on Al 2O 3/Si substrate by vacuum electron-beam evaporation followed by annealing at 400 °C in N 2 ambient. Metal-insulator-silicon (MIS) structures with Ag nanodots embedded in Al 2O 3 gate dielectric are fabricated. Clear electron storage effect with the flatband voltage shift of 1.3 eV is observed through capacitance-conductance and conductance-voltage measurements. Our results demonstrate the feasibility of applying Ag nanodots for nanocrystal floating-gate memory devices.

Design of a Ferroelectric Programmable Logic Gate Array

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

2003-01-01

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

Co-integration of nano-scale vertical- and horizontal-channel metal-oxide-semiconductor field-effect transistors for low power CMOS technology.

PubMed

Sun, Min-Chul; Kim, Garam; Kim, Sang Wan; Kim, Hyun Woo; Kim, Hyungjin; Lee, Jong-Ho; Shin, Hyungcheol; Park, Byung-Gook

2012-07-01

In order to extend the conventional low power Si CMOS technology beyond the 20-nm node without SOI substrates, we propose a novel co-integration scheme to build horizontal- and vertical-channel MOSFETs together and verify the idea using TCAD simulations. From the fabrication viewpoint, it is highlighted that this scheme provides additional vertical devices with good scalability by adding a few steps to the conventional CMOS process flow for fin formation. In addition, the benefits of the co-integrated vertical devices are investigated using a TCAD device simulation. From this study, it is confirmed that the vertical device shows improved off-current control and a larger drive current when the body dimension is less than 20 nm, due to the electric field coupling effect at the double-gated channel. Finally, the benefits from the circuit design viewpoint, such as the larger midpoint gain and beta and lower power consumption, are confirmed by the mixed-mode circuit simulation study.

Vertical resonant tunneling transistors with molecular quantum dots for large-scale integration.

PubMed

Hayakawa, Ryoma; Chikyow, Toyohiro; Wakayama, Yutaka

2017-08-10

Quantum molecular devices have a potential for the construction of new data processing architectures that cannot be achieved using current complementary metal-oxide-semiconductor (CMOS) technology. The relevant basic quantum transport properties have been examined by specific methods such as scanning probe and break-junction techniques. However, these methodologies are not compatible with current CMOS applications, and the development of practical molecular devices remains a persistent challenge. Here, we demonstrate a new vertical resonant tunneling transistor for large-scale integration. The transistor channel is comprised of a MOS structure with C 60 molecules as quantum dots, and the structure behaves like a double tunnel junction. Notably, the transistors enabled the observation of stepwise drain currents, which originated from resonant tunneling via the discrete molecular orbitals. Applying side-gate voltages produced depletion layers in Si substrates, to achieve effective modulation of the drain currents and obvious peak shifts in the differential conductance curves. Our device configuration thus provides a promising means of integrating molecular functions into future CMOS applications.

An IO block array in a radiation-hardened SOI SRAM-based FPGA

NASA Astrophysics Data System (ADS)

Yan, Zhao; Lihua, Wu; Xiaowei, Han; Yan, Li; Qianli, Zhang; Liang, Chen; Guoquan, Zhang; Jianzhong, Li; Bo, Yang; Jiantou, Gao; Jian, Wang; Ming, Li; Guizhai, Liu; Feng, Zhang; Xufeng, Guo; Kai, Zhao; Chen, Stanley L.; Fang, Yu; Zhongli, Liu

2012-01-01

We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field-programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si), a dose survivability rate of 1.5 × 1011 rad(Si)/s, and a neutron fluence immunity of 1 × 1014 n/cm2.

Convolutional Neural Network on Embedded Linux(trademark) System-on-Chip: A Methodology and Performance Benchmark

DTIC Science & Technology

2016-05-01

A9 CPU and 15 W for the i7 CPU. A method of accelerating this computation is by using a customized hardware unit called a field- programmable gate...implementation of custom logic to accelerate com- putational workloads. This FPGA fabric, in addition to the standard programmable logic, contains 220...chip; field- programmable gate array Daniel Gebhardt U U U U 18 (619) 553-2786 INITIAL DISTRIBUTION 84300 Library (2) 85300 Archive/Stock (1

Convolutional Neural Network on Embedded Linux System-on-Chip: A Methodology and Performance Benchmark

DTIC Science & Technology

2016-05-01

A9 CPU and 15 W for the i7 CPU. A method of accelerating this computation is by using a customized hardware unit called a field- programmable gate...implementation of custom logic to accelerate com- putational workloads. This FPGA fabric, in addition to the standard programmable logic, contains 220...chip; field- programmable gate array Daniel Gebhardt U U U U 18 (619) 553-2786 INITIAL DISTRIBUTION 84300 Library (2) 85300 Archive/Stock (1

An Undergraduate Course and Laboratory in Digital Signal Processing with Field Programmable Gate Arrays

ERIC Educational Resources Information Center

Meyer-Base, U.; Vera, A.; Meyer-Base, A.; Pattichis, M. S.; Perry, R. J.

2010-01-01

In this paper, an innovative educational approach to introducing undergraduates to both digital signal processing (DSP) and field programmable gate array (FPGA)-based design in a one-semester course and laboratory is described. While both DSP and FPGA-based courses are currently present in different curricula, this integrated approach reduces the…

Evaluation of the FIR Example using Xilinx Vivado High-Level Synthesis Compiler

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jin, Zheming; Finkel, Hal; Yoshii, Kazutomo

Compared to central processing units (CPUs) and graphics processing units (GPUs), field programmable gate arrays (FPGAs) have major advantages in reconfigurability and performance achieved per watt. This development flow has been augmented with high-level synthesis (HLS) flow that can convert programs written in a high-level programming language to Hardware Description Language (HDL). Using high-level programming languages such as C, C++, and OpenCL for FPGA-based development could allow software developers, who have little FPGA knowledge, to take advantage of the FPGA-based application acceleration. This improves developer productivity and makes the FPGA-based acceleration accessible to hardware and software developers. Xilinx Vivado HLSmore » compiler is a high-level synthesis tool that enables C, C++ and System C specification to be directly targeted into Xilinx FPGAs without the need to create RTL manually. The white paper [1] published recently by Xilinx uses a finite impulse response (FIR) example to demonstrate the variable-precision features in the Vivado HLS compiler and the resource and power benefits of converting floating point to fixed point for a design. To get a better understanding of variable-precision features in terms of resource usage and performance, this report presents the experimental results of evaluating the FIR example using Vivado HLS 2017.1 and a Kintex Ultrascale FPGA. In addition, we evaluated the half-precision floating-point data type against the double-precision and single-precision data type and present the detailed results.« less

Field-Programmable Gate Array-based fluxgate magnetometer with digital integration

NASA Astrophysics Data System (ADS)

Butta, Mattia; Janosek, Michal; Ripka, Pavel

2010-05-01

In this paper, a digital magnetometer based on printed circuit board fluxgate is presented. The fluxgate is pulse excited and the signal is extracted by gate integration. We investigate the possibility to perform integration on very narrow gates (typically 500 ns) by using digital techniques. The magnetometer is based on field-programmable gate array (FPGA) card: we will show all the advantages and disadvantages, given by digitalization of fluxgate output voltage by means of analog-to-digital converter on FPGA card, as well as digitalization performed by external digitizer. Due to very narrow gate, it is shown that a magnetometer entirely based on a FPGA card is preferable, because it avoids noise due to trigger instability. Both open loop and feedback operative mode are described and achieved results are presented.

Design and Analysis of CMOS-Compatible III-V Compound Electron-Hole Bilayer Tunneling Field-Effect Transistor for Ultra-Low-Power Applications.

PubMed

Kim, Sung Yoon; Seo, Jae Hwa; Yoon, Young Jun; Lee, Ho-Young; Lee, Seong Min; Cho, Seongjae; Kang, In Man

2015-10-01

In this work, we design and analyze complementary metal-oxide-semiconductor (CMOS)-compatible III-V compound electron-hole bilayer (EHB) tunneling field-effect transistors (TFETs) by using two-dimensional (2D) technology computer-aided design (TCAD) simulations. A recently proposed EHB TFET exploits a bias-induced band-to-band tunneling (BTBT) across the electron-hole bilayer by an electric field from the top and bottom gates. This is in contrast to conventional planar p(+)-p(-)-n TFETs, which utilize BTBT across the source-to-channel junction. We applied III-V compound semiconductor materials to the EHB TFETs in order to enhance the current drivability and switching performance. Devices based on various compound semiconductor materials have been designed and analyzed in terms of their primary DC characteristics. In addition, the operational principles were validated by close examination of the electron concentrations and energy-band diagrams under various operation conditions. The simulation results of the optimally designed In0.533Ga0.47As EHB TFET show outstanding performance, with an on-state current (Ion) of 249.5 μA/μm, subthreshold swing (S) of 11.4 mV/dec, and threshold voltage (Vth) of 50 mV at VDS = 0.5 V. Based on the DC-optimized InGaAs EHB TFET, the CMOS inverter circuit was simulated in views of static and dynamic behaviors of the p-channel device with exchanges between top and bottom gates or between source and drain electrodes maintaining the device structure.

Programming time-multiplexed reconfigurable hardware using a scalable neuromorphic compiler.

PubMed

Minkovich, Kirill; Srinivasa, Narayan; Cruz-Albrecht, Jose M; Cho, Youngkwan; Nogin, Aleksey

2012-06-01

Scalability and connectivity are two key challenges in designing neuromorphic hardware that can match biological levels. In this paper, we describe a neuromorphic system architecture design that addresses an approach to meet these challenges using traditional complementary metal-oxide-semiconductor (CMOS) hardware. A key requirement in realizing such neural architectures in hardware is the ability to automatically configure the hardware to emulate any neural architecture or model. The focus for this paper is to describe the details of such a programmable front-end. This programmable front-end is composed of a neuromorphic compiler and a digital memory, and is designed based on the concept of synaptic time-multiplexing (STM). The neuromorphic compiler automatically translates any given neural architecture to hardware switch states and these states are stored in digital memory to enable desired neural architectures. STM enables our proposed architecture to address scalability and connectivity using traditional CMOS hardware. We describe the details of the proposed design and the programmable front-end, and provide examples to illustrate its capabilities. We also provide perspectives for future extensions and potential applications.

A Content-Addressable Memory structure using quantum cells in nanotechnology with energy dissipation analysis

NASA Astrophysics Data System (ADS)

Sadoghifar, Ali; Heikalabad, Saeed Rasouli

2018-05-01

Quantum-dot cellular automata is one of the recent new technologies at the nanoscale that can be a suitable replacement for CMOS technology. The circuits constructed in QCA technology have desirable features such as low power consumption, high speed and small size. These features can be more distinct in memory structures. In this paper, we design a new structure for content addressable memory cell in QCA. For this purpose, first, a unique gate is introduced for mask operation in QCA and then this gate is used to improve the performance of CAM. These structures are evaluated with QCADesigner simulator.

Redundant single event upset supression system

DOEpatents

Hoff, James R.

2006-04-04

CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further as a memory that can overcome the effects of radiation. As an SR-flip flop, the invention can be altered into any known type of latch or flip-flop by the application of external logic, thereby extending radiation tolerance to devices previously incapable of radiation tolerance. Numerous registers can be logically connected and replicated thereby being electronically configured to operate as a redundant circuit.

Addressable Inverter Matrix Tests Integrated-Circuit Wafer

NASA Technical Reports Server (NTRS)

Buehler, Martin G.

1988-01-01

Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

Design of the Detector II: A CMOS Gate Array for the Study of Concurrent Error Detection Techniques.

DTIC Science & Technology

1987-07-01

detection schemes and temporary failures. The circuit consists- or of six different adders with concurrent error detection schemes . The error detection... schemes are - simple duplication, duplication with functional dual implementation, duplication with different &I [] .6implementations, two-rail encoding...THE SYSTEM. .. .... ...... ...... ...... 5 7. DESIGN OF CED SCHEMES .. ... ...... ...... ........ 7 7.1 Simple Duplication

Noise Reduction Techniques and Scaling Effects towards Photon Counting CMOS Image Sensors

PubMed Central

Boukhayma, Assim; Peizerat, Arnaud; Enz, Christian

2016-01-01

This paper presents an overview of the read noise in CMOS image sensors (CISs) based on four-transistors (4T) pixels, column-level amplification and correlated multiple sampling. Starting from the input-referred noise analytical formula, process level optimizations, device choices and circuit techniques at the pixel and column level of the readout chain are derived and discussed. The noise reduction techniques that can be implemented at the column and pixel level are verified by transient noise simulations, measurement and results from recently-published low noise CIS. We show how recently-reported process refinement, leading to the reduction of the sense node capacitance, can be combined with an optimal in-pixel source follower design to reach a sub-0.3erms- read noise at room temperature. This paper also discusses the impact of technology scaling on the CIS read noise. It shows how designers can take advantage of scaling and how the Metal-Oxide-Semiconductor (MOS) transistor gate leakage tunneling current appears as a challenging limitation. For this purpose, both simulation results of the gate leakage current and 1/f noise data reported from different foundries and technology nodes are used.

Giant Gating Tunability of Optical Refractive Index in Transition Metal Dichalcogenide Monolayers.

PubMed

Yu, Yiling; Yu, Yifei; Huang, Lujun; Peng, Haowei; Xiong, Liwei; Cao, Linyou

2017-06-14

We report that the refractive index of transition metal dichacolgenide (TMDC) monolayers, such as MoS 2 , WS 2 , and WSe 2 , can be substantially tuned by >60% in the imaginary part and >20% in the real part around exciton resonances using complementary metal-oxide-semiconductor (CMOS) compatible electrical gating. This giant tunablility is rooted in the dominance of excitonic effects in the refractive index of the monolayers and the strong susceptibility of the excitons to the influence of injected charge carriers. The tunability mainly results from the effects of injected charge carriers to broaden the spectral width of excitonic interband transitions and to facilitate the interconversion of neutral and charged excitons. The other effects of the injected charge carriers, such as renormalizing bandgap and changing exciton binding energy, only play negligible roles. We also demonstrate that the atomically thin monolayers, when combined with photonic structures, can enable the efficiencies of optical absorption (reflection) tuned from 40% (60%) to 80% (20%) due to the giant tunability of the refractive index. This work may pave the way toward the development of field-effect photonics in which the optical functionality can be controlled with CMOS circuits.

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

NASA Astrophysics Data System (ADS)

Aytar, Oktay; Tangel, Ali; Afacan, Engin

2017-11-01

This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/-0.22 LSB of DNL and +0.01/-0.44 LSB of INL, layout area of 0.27 mm2, and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.

An energy and cost efficient majority-based RAM cell in quantum-dot cellular automata

NASA Astrophysics Data System (ADS)

Khosroshahy, Milad Bagherian; Moaiyeri, Mohammad Hossein; Navi, Keivan; Bagherzadeh, Nader

Nanotechnologies, notably quantum-dot cellular automata, have achieved major attentions for their prominent features as compared to the conventional CMOS circuitry. Quantum-dot cellular automata, particularly owning to its considerable reduction in size, high switching speed and ultra-low energy consumption, is considered as a potential alternative for the CMOS technology. As the memory unit is one of the most essential components in a digital system, designing a well-optimized QCA random access memory (RAM) cell is an important area of research. In this paper, a new five-input majority gate is presented which is suitable for implementing efficient single-layer QCA circuits. In addition, a new RAM cell with set and reset capabilities is designed based on the proposed majority gate, which has an efficient and low-energy structure. The functionality, performance and energy consumption of the proposed designs are evaluated based on the QCADesigner and QCAPro tools. According to the simulation results, the proposed RAM design leads to on average 38% lower total energy dissipation, 25% smaller area, 20% lower cell count, 28% lower delay and 60% lower QCA cost as compared to its previous counterparts.

Issues of nanoelectronics: a possible roadmap.

PubMed

Wang, Kang L

2002-01-01

In this review, we will discuss a possible roadmap in scaling a nanoelectronic device from today's CMOS technology to the ultimate limit when the device fails. In other words, at the limit, CMOS will have a severe short channel effect, significant power dissipation in its quiescent (standby) state, and problems related to other essential characteristics. Efforts to use structures such as the double gate, vertical surround gate, and SOI to improve the gate control have continually been made. Other types of structures using SiGe source/drain, asymmetric Schottky source/drain, and the like will be investigated as viable structures to achieve ultimate CMOS. In reaching its scaling limit, tunneling will be an issue for CMOS. The tunneling current through the gate oxide and between the source and drain will limit the device operation. When tunneling becomes significant, circuits may incorporate tunneling devices with CMOS to further increase the functionality per device count. We will discuss both the top-down and bottom-up approaches in attaining the nanometer scale and eventually the atomic scale. Self-assembly is used as a bottom-up approach. The state of the art is reviewed, and the challenges of the multiple-step processing in using the self-assembly approach are outlined. Another facet of the scaling trend is to decrease the number of electrons in devices, ultimately leading to single electrons. If the size of a single-electron device is scaled in such a way that the Coulomb self-energy is higher than the thermal energy (at room temperature), a single-electron device will be able to operate at room temperature. In principle, the speed of the device will be fast as long as the capacitance of the load is also scaled accordingly. The single-electron device will have a small drive current, and thus the load capacitance, including those of interconnects and fanouts, must be small to achieve a reasonable speed. However, because the increase in the density (and/or functionality) of integrated circuits is the principal driver, the wiring or interconnects will increase and become the bottleneck for the design of future high-density and high-functionality circuits, particularly for single-electron devices. Furthermore, the massive interconnects needed in the architecture used today will result in an increase in load capacitance. Thus for single-electron device circuits, it is critical to have minimal interconnect loads. And new types of architectures with minimal numbers of global interconnects will be needed. Cellular automata, which need only nearest-neighbor interconnects, are discussed as a plausible example. Other architectures such as neural networks are also possible. Examples of signal processing using cellular automata are discussed. Quantum computing and information processing are based on quantum mechanical descriptions of individual particles correlated among each other. A quantum bit or qubit is described as a linear superposition of the wave functions of a two-state system, for example, the spin of a particle. With the interaction of two qubits, they are connected in a "wireless fashion" using wave functions via quantum mechanical interaction, referred to as entanglement. The interconnection by the nonlocality of wave functions affords a massive parallel nature for computing or so-called quantum parallelism. We will describe the potential and solid-state implementations of quantum computing and information, using electron spin and/or nuclear spin in Si and Ge. Group IV elements have a long coherent time and other advantages. The example of using SiGe for g factor engineering will be described.

Note: All-digital CMOS MOS-capacitor-based pulse-shrinking mechanism suitable for time-to-digital converters

NASA Astrophysics Data System (ADS)

Chen, Chun-Chi; Hwang, Chorng-Sii; Lin, You-Ting; Liu, Keng-Chih

2015-12-01

This paper presents an all-digital CMOS pulse-shrinking mechanism suitable for time-to-digital converters (TDCs). A simple MOS capacitor is used as a pulse-shrinking cell to perform time attenuation for time resolving. Compared with a previous pulse-shrinking mechanism, the proposed mechanism provides an appreciably improved temporal resolution with high linearity. Furthermore, the use of a binary-weighted pulse-shrinking unit with scaled MOS capacitors is proposed for achieving a programmable resolution. A TDC involving the proposed mechanism was fabricated using a TSMC (Taiwan Semiconductor Manufacturing Company) 0.18-μm CMOS process, and it has a small area of nearly 0.02 mm2 and an integral nonlinearity error of ±0.8 LSB for a resolution of 24 ps.

Systems and methods for detecting a failure event in a field programmable gate array

NASA Technical Reports Server (NTRS)

Ng, Tak-Kwong (Inventor); Herath, Jeffrey A. (Inventor)

2009-01-01

An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.

Programmable Schottky Junctions Based on Ferroelectric Gated MoS2 Transistors

NASA Astrophysics Data System (ADS)

Xiao, Zhiyong; Song, Jingfeng; Drcharme, Stephen; Hong, Xia

We report a programmable Schottky junction based on MoS2 field effect transistors with a SiO2 back gate and a ferroelectric copolymer poly(vinylidene-fluoride-trifluorethylene) (PVDF) top gate. We fabricated mechanically exfoliated single layer MoS2 flakes into two point devices via e-beam lithography, and deposited on the top of the devices ~20 nm PVDF thin films. The polarization of the PVDF layer is controlled locally by conducting atomic force microscopy. The devices exhibit linear ID-VD characteristics when the ferroelectric gate is uniformly polarized in one direction. We then polarized the gate into two domains with opposite polarization directions, and observed that the ID-VD characteristics of the MoS2 channel can be modulated between linear and rectified behaviors depending on the back gate voltage. The nonlinear ID-VD relation emerges when half of the channel is in the semiconductor phase while the other half is in the metallic phase, and it can be well described by the thermionic emission model with a Schottky barrier of ~0.5 eV. The Schottky junction can be erased by re-write the entire channel in the uniform polarization state. Our study facilitates the development of programmable, multifunctional nanoelectronics based on layered 2D TMDs..

On the use of programmable hardware and reduced numerical precision in earth-system modeling.

PubMed

Düben, Peter D; Russell, Francis P; Niu, Xinyu; Luk, Wayne; Palmer, T N

2015-09-01

Programmable hardware, in particular Field Programmable Gate Arrays (FPGAs), promises a significant increase in computational performance for simulations in geophysical fluid dynamics compared with CPUs of similar power consumption. FPGAs allow adjusting the representation of floating-point numbers to specific application needs. We analyze the performance-precision trade-off on FPGA hardware for the two-scale Lorenz '95 model. We scale the size of this toy model to that of a high-performance computing application in order to make meaningful performance tests. We identify the minimal level of precision at which changes in model results are not significant compared with a maximal precision version of the model and find that this level is very similar for cases where the model is integrated for very short or long intervals. It is therefore a useful approach to investigate model errors due to rounding errors for very short simulations (e.g., 50 time steps) to obtain a range for the level of precision that can be used in expensive long-term simulations. We also show that an approach to reduce precision with increasing forecast time, when model errors are already accumulated, is very promising. We show that a speed-up of 1.9 times is possible in comparison to FPGA simulations in single precision if precision is reduced with no strong change in model error. The single-precision FPGA setup shows a speed-up of 2.8 times in comparison to our model implementation on two 6-core CPUs for large model setups.

Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around

NASA Astrophysics Data System (ADS)

Guerfi, Youssouf; Larrieu, Guilhem

2016-04-01

Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires' suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.

Three-Function Logic Gate Controlled by Analog Voltage

NASA Technical Reports Server (NTRS)

Zebulum, Ricardo; Stoica, Adrian

2006-01-01

The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If multifunctional gates like this circuit were used in the place of the configurable logic blocks of present commercial FPGAs, it would be possible to change the functions of the resulting digital systems within shorter times. For example, by changing a single control voltage, one could change the function of thousands of FPGA cells within nanoseconds. In contrast, typically, the reconfiguration in a conventional FPGA by use of bits downloaded from look-up tables via a digital bus takes microseconds.

Microdose Induced Data Loss on Floating Gate Memories

NASA Technical Reports Server (NTRS)

Guertin, Steven M.; Nguyen, Duc M.; Patterson, Jeffrey D.

2006-01-01

Heavy ion irradiation of flash memories shows loss of stored data. The fluence dependence is indicative of microdose effects. Other qualitative factors identifying the effect as microdose are discussed. The data is presented, and compared to statistical results of a microdose target-based model.

Investing the effectiveness of retention performance in a non-volatile floating gate memory device with a core-shell structure of CdSe nanoparticles

NASA Astrophysics Data System (ADS)

Lee, Dong-Hoon; Kim, Jung-Min; Lim, Ki-Tae; Cho, Hyeong Jun; Bang, Jin Ho; Kim, Yong-Sang

2016-03-01

In this paper, we empirically investigate the retention performance of organic non-volatile floating gate memory devices with CdSe nanoparticles (NPs) as charge trapping elements. Core-structured CdSe NPs or core-shell-structured ZnS/CdSe NPs were mixed in PMMA and their performance in pentacene based device was compared. The NPs and self-organized thin tunneling PMMA inside the devices exhibited hysteresis by trapping hole during capacitance-voltage characterization. Despite of core-structured NPs showing a larger memory window, the retention time was too short to be adopted by an industry. By contrast core-shell structured NPs showed an improved retention time of >10000 seconds than core-structure NCs. Based on these results and the energy band structure, we propose the retention mechanism of each NPs. This investigation of retention performance provides a comparative and systematic study of the charging/discharging behaviors of NPs based memory devices. [Figure not available: see fulltext.

Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

NASA Astrophysics Data System (ADS)

Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

The pathway for CMOS technology beyond the 5-nm technology node remains unclear for both physical and technological reasons. A new transistor paradigm is required. A LET (Marmon et. al., Front. Phys. 2016, 4, No. 8) offers electronic-optical hybridization at the component level, and is capable of continuing Moore's law to the quantum scale. A LET overcomes a FET's fabrication complexity, e.g., physical gate and doping, by employing optical gating and photoconductivity, while multiple independent, optical gates readily realize unique functionalities. We report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs, incorporating an M-S-M structure, show output and transfer characteristics resembling advanced FETs, e.g., on/off ratios up to 106 with a source-drain voltage of 1.43V, gate-power of 260nW, and a subthreshold swing of 0.3nW/decade (excluding losses). A LET has potential for high-switching (THz) speeds and extremely low-switching energies (aJ) in the ballistic transport region. Our work offers new electronic-optical integration strategies for high speed and low energy computing approaches, which could potentially be extended to other materials and devices.

Effects of Heavy Ion Exposure on Nanocrystal Nonvolatile Memory

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; Suhail, Mohammed; Kuhn, Peter; Prinz, Erwin; Kim, Hak; LaBel, Kenneth A.

2004-01-01

We have irradiated engineering samples of Freescale 4M nonvolatile memories with heavy ions. They use Silicon nanocrystals as the storage element, rather than the more common floating gate. The irradiations were performed using the Texas A&M University cyclotron Single Event Effects Test Facility. The chips were tested in the static mode, and in the dynamic read mode, dynamic write (program) mode, and dynamic erase mode. All the errors observed appeared to be due to single, isolated bits, even in the program and erase modes. These errors appeared to be related to the micro-dose mechanism. All the errors corresponded to the loss of electrons from a programmed cell. The underlying physical mechanisms will be discussed in more detail later. There were no errors, which could be attributed to malfunctions of the control circuits. At the highest LET used in the test (85 MeV/mg/sq cm), however, there appeared to be a failure due to gate rupture. Failure analysis is being conducted to confirm this conclusion. There was no unambiguous evidence of latchup under any test conditions. Generally, the results on the nanocrystal technology compare favorably with results on currently available commercial floating gate technology, indicating that the technology is promising for future space applications, both civilian and military.

Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks.

PubMed

Zhao, Yudan; Li, Qunqing; Xiao, Xiaoyang; Li, Guanhong; Jin, Yuanhao; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan

2016-02-23

We have proposed and fabricated stable and repeatable, flexible, single-walled carbon nanotube (SWCNT) thin film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) integrated circuits based on a three-dimensional (3D) structure. Two layers of SWCNT-TFT devices were stacked, where one layer served as n-type devices and the other one served as p-type devices. On the basis of this method, it is able to save at least half of the area required to construct an inverter and make large-scale and high-density integrated CMOS circuits easier to design and manufacture. The 3D flexible CMOS inverter gain can be as high as 40, and the total noise margin is more than 95%. Moreover, the input and output voltage of the inverter are exactly matched for cascading. 3D flexible CMOS NOR, NAND logic gates, and 15-stage ring oscillators were fabricated on PI substrates with high performance as well. Stable electrical properties of these circuits can be obtained with bending radii as small as 3.16 mm, which shows that such a 3D structure is a reliable architecture and suitable for carbon nanotube electrical applications in complex flexible and wearable electronic devices.

Single Event Analysis and Fault Injection Techniques Targeting Complex Designs Implemented in Xilinx-Virtex Family Field Programmable Gate Array (FPGA) Devices

NASA Technical Reports Server (NTRS)

Berg, Melanie D.; LaBel, Kenneth; Kim, Hak

2014-01-01

An informative session regarding SRAM FPGA basics. Presenting a framework for fault injection techniques applied to Xilinx Field Programmable Gate Arrays (FPGAs). Introduce an overlooked time component that illustrates fault injection is impractical for most real designs as a stand-alone characterization tool. Demonstrate procedures that benefit from fault injection error analysis.

Radiation-Hard SpaceWire/Gigabit Ethernet-Compatible Transponder

NASA Technical Reports Server (NTRS)

Katzman, Vladimir

2012-01-01

A radiation-hard transponder was developed utilizing submicron/nanotechnology from IBM. The device consumes low power and has a low fabrication cost. This device utilizes a Plug-and-Play concept, and can be integrated into intra-satellite networks, supporting SpaceWire and Gigabit Ethernet I/O. A space-qualified, 100-pin package also was developed, allowing space-qualified (class K) transponders to be delivered within a six-month time frame. The novel, optical, radiation-tolerant transponder was implemented as a standalone board, containing the transponder ASIC (application specific integrated circuit) and optical module, with an FPGA (field-programmable gate array) friendly parallel interface. It features improved radiation tolerance; high-data-rate, low-power consumption; and advanced functionality. The transponder utilizes a patented current mode logic library of radiation-hardened-by-architecture cells. The transponder was developed, fabricated, and radhard tested up to 1 MRad. It was fabricated using 90-nm CMOS (complementary metal oxide semiconductor) 9 SF process from IBM, and incorporates full BIT circuitry, allowing a loop back test. The low-speed parallel LVCMOS (lowvoltage complementary metal oxide semiconductor) bus is compatible with Actel FPGA. The output LVDS (low-voltage differential signaling) interface operates up to 1.5 Gb/s. Built-in CDR (clock-data recovery) circuitry provides robust synchronization and incorporates two alarm signals such as synch loss and signal loss. The ultra-linear peak detector scheme allows on-line control of the amplitude of the input signal. Power consumption is less than 300 mW. The developed transponder with a 1.25 Gb/s serial data rate incorporates a 10-to-1 serializer with an internal clock multiplication unit and a 10-1 deserializer with internal clock and data recovery block, which can operate with 8B10B encoded signals. Three loop-back test modes are provided to facilitate the built-in-test functionality. The design is based on a proprietary library of differential current switching logic cells implemented in the standard 90-nm CMOS 9SF technology from IBM. The proprietary low-power LVDS physical interface is fully compatible with the SpaceWire standard, and can be directly connected to the SFP MSA (small form factor pluggable Multiple Source Agreement) optical transponder. The low-speed parallel interfaces are fully compatible with the standard 1.8 V CMOS input/output devices. The utilized proprietary annular CMOS layout structures provide TID tolerance above 1.2 MRad. The complete chip consumes less than 150 mW of power from a single 1.8-V positive supply source.

Complementary Metal-Oxide-Silicon (CMOS)-Memristor Hybrid Nanoelectronics for Advanced Encryption Standard (AES) Encryption

DTIC Science & Technology

2016-04-01

with Al top electrodes and Cu bottom electrodes. ................... 9 Figure 4. SPICE netlist structure...memory elements play a part in logic gate. 4.4.2 Simulation SPICE Simulation Program for Integrated Circuits Emphasis ( SPICE ) is a general-purpose...analog circuit simulator that was developed at the Electronics Research Laboratory of the University of California, Berkeley [6]. In 1975, SPICE

A Control System and Streaming DAQ Platform with Image-Based Trigger for X-ray Imaging

NASA Astrophysics Data System (ADS)

Stevanovic, Uros; Caselle, Michele; Cecilia, Angelica; Chilingaryan, Suren; Farago, Tomas; Gasilov, Sergey; Herth, Armin; Kopmann, Andreas; Vogelgesang, Matthias; Balzer, Matthias; Baumbach, Tilo; Weber, Marc

2015-06-01

High-speed X-ray imaging applications play a crucial role for non-destructive investigations of the dynamics in material science and biology. On-line data analysis is necessary for quality assurance and data-driven feedback, leading to a more efficient use of a beam time and increased data quality. In this article we present a smart camera platform with embedded Field Programmable Gate Array (FPGA) processing that is able to stream and process data continuously in real-time. The setup consists of a Complementary Metal-Oxide-Semiconductor (CMOS) sensor, an FPGA readout card, and a readout computer. It is seamlessly integrated in a new custom experiment control system called Concert that provides a more efficient way of operating a beamline by integrating device control, experiment process control, and data analysis. The potential of the embedded processing is demonstrated by implementing an image-based trigger. It records the temporal evolution of physical events with increased speed while maintaining the full field of view. The complete data acquisition system, with Concert and the smart camera platform was successfully integrated and used for fast X-ray imaging experiments at KIT's synchrotron radiation facility ANKA.

Compact universal logic gates realized using quantization of current in nanodevices.

PubMed

Zhang, Wancheng; Wu, Nan-Jian; Yang, Fuhua

2007-12-12

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

Robust integration schemes for junction-based modulators in a 200mm CMOS compatible silicon photonic platform (Conference Presentation)

NASA Astrophysics Data System (ADS)

Szelag, Bertrand; Abraham, Alexis; Brision, Stéphane; Gindre, Paul; Blampey, Benjamin; Myko, André; Olivier, Segolene; Kopp, Christophe

2017-05-01

Silicon photonic is becoming a reality for next generation communication system addressing the increasing needs of HPC (High Performance Computing) systems and datacenters. CMOS compatible photonic platforms are developed in many foundries integrating passive and active devices. The use of existing and qualified microelectronics process guarantees cost efficient and mature photonic technologies. Meanwhile, photonic devices have their own fabrication constraints, not similar to those of cmos devices, which can affect their performances. In this paper, we are addressing the integration of PN junction Mach Zehnder modulator in a 200mm CMOS compatible photonic platform. Implantation based device characteristics are impacted by many process variations among which screening layer thickness, dopant diffusion, implantation mask overlay. CMOS devices are generally quite robust with respect to these processes thanks to dedicated design rules. For photonic devices, the situation is different since, most of the time, doped areas must be carefully located within waveguides and CMOS solutions like self-alignment to the gate cannot be applied. In this work, we present different robust integration solutions for junction-based modulators. A simulation setup has been built in order to optimize of the process conditions. It consist in a Mathlab interface coupling process and device electro-optic simulators in order to run many iterations. Illustrations of modulator characteristic variations with process parameters are done using this simulation setup. Parameters under study are, for instance, X and Y direction lithography shifts, screening oxide and slab thicknesses. A robust process and design approach leading to a pn junction Mach Zehnder modulator insensitive to lithography misalignment is then proposed. Simulation results are compared with experimental datas. Indeed, various modulators have been fabricated with different process conditions and integration schemes. Extensive electro-optic characterization of these components will be presented.

CMOS-compatible spintronic devices: a review

NASA Astrophysics Data System (ADS)

Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

2016-11-01

For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

Design of polarization imaging system based on CIS and FPGA

NASA Astrophysics Data System (ADS)

Zeng, Yan-an; Liu, Li-gang; Yang, Kun-tao; Chang, Da-ding

2008-02-01

As polarization is an important characteristic of light, polarization image detecting is a new image detecting technology of combining polarimetric and image processing technology. Contrasting traditional image detecting in ray radiation, polarization image detecting could acquire a lot of very important information which traditional image detecting couldn't. Polarization image detecting will be widely used in civilian field and military field. As polarization image detecting could resolve some problem which couldn't be resolved by traditional image detecting, it has been researched widely around the world. The paper introduces polarization image detecting in physical theory at first, then especially introduces image collecting and polarization image process based on CIS (CMOS image sensor) and FPGA. There are two parts including hardware and software for polarization imaging system. The part of hardware include drive module of CMOS image sensor, VGA display module, SRAM access module and the real-time image data collecting system based on FPGA. The circuit diagram and PCB was designed. Stokes vector and polarization angle computing method are analyzed in the part of software. The float multiply of Stokes vector is optimized into just shift and addition operation. The result of the experiment shows that real time image collecting system could collect and display image data from CMOS image sensor in real-time.

Image Accumulation in Pixel Detector Gated by Late External Trigger Signal and its Application in Imaging Activation Analysis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jakubek, J.; Cejnarova, A.; Platkevic, M.

Single quantum counting pixel detectors of Medipix type are starting to be used in various radiographic applications. Compared to standard devices for digital imaging (such as CCDs or CMOS sensors) they present significant advantages: direct conversion of radiation to electric signal, energy sensitivity, noiseless image integration, unlimited dynamic range, absolute linearity. In this article we describe usage of the pixel device TimePix for image accumulation gated by late trigger signal. Demonstration of the technique is given on imaging coincidence instrumental neutron activation analysis (Imaging CINAA). This method allows one to determine concentration and distribution of certain preselected element in anmore » inspected sample.« less

Roll Angle Estimation Using Thermopiles for a Flight Controlled Mortar

DTIC Science & Technology

2012-06-01

Using Xilinx’s System generator, the entire design was implemented at a relatively high level within Malab’s Simulink. This allowed VHDL code to...thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA). These results demonstrate the...accurately estimated by processing the thermopile data with a Recursive Least Squares (RLS) filter implemented on a field programmable gate array (FPGA

Design of barrier bucket kicker control system

NASA Astrophysics Data System (ADS)

Ni, Fa-Fu; Wang, Yan-Yu; Yin, Jun; Zhou, De-Tai; Shen, Guo-Dong; Zheng, Yang-De.; Zhang, Jian-Chuan; Yin, Jia; Bai, Xiao; Ma, Xiao-Li

2018-05-01

The Heavy-Ion Research Facility in Lanzhou (HIRFL) contains two synchrotrons: the main cooler storage ring (CSRm) and the experimental cooler storage ring (CSRe). Beams are extracted from CSRm, and injected into CSRe. To apply the Barrier Bucket (BB) method on the CSRe beam accumulation, a new BB technology based kicker control system was designed and implemented. The controller of the system is implemented using an Advanced Reduced Instruction Set Computer (RISC) Machine (ARM) chip and a field-programmable gate array (FPGA) chip. Within the architecture, ARM is responsible for data presetting and floating number arithmetic processing. The FPGA computes the RF phase point of the two rings and offers more accurate control of the time delay. An online preliminary experiment on HIRFL was also designed to verify the functionalities of the control system. The result shows that the reference trigger point of two different sinusoidal RF signals for an arbitrary phase point was acquired with a matched phase error below 1° (approximately 2.1 ns), and the step delay time better than 2 ns were realized.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Underwood, Keith D; Ulmer, Craig D.; Thompson, David

Field programmable gate arrays (FPGAs) have been used as alternative computational de-vices for over a decade; however, they have not been used for traditional scientific com-puting due to their perceived lack of floating-point performance. In recent years, there hasbeen a surge of interest in alternatives to traditional microprocessors for high performancecomputing. Sandia National Labs began two projects to determine whether FPGAs wouldbe a suitable alternative to microprocessors for high performance scientific computing and,if so, how they should be integrated into the system. We present results that indicate thatFPGAs could have a significant impact on future systems. FPGAs have thepotentialtohave ordermore » of magnitude levels of performance wins on several key algorithms; however,there are serious questions as to whether the system integration challenge can be met. Fur-thermore, there remain challenges in FPGA programming and system level reliability whenusing FPGA devices.4 AcknowledgmentArun Rodrigues provided valuable support and assistance in the use of the Structural Sim-ulation Toolkit within an FPGA context. Curtis Janssen and Steve Plimpton provided valu-able insights into the workings of two Sandia applications (MPQC and LAMMPS, respec-tively).5« less

Fast, multi-channel real-time processing of signals with microsecond latency using graphics processing units.

PubMed

Rath, N; Kato, S; Levesque, J P; Mauel, M E; Navratil, G A; Peng, Q

2014-04-01

Fast, digital signal processing (DSP) has many applications. Typical hardware options for performing DSP are field-programmable gate arrays (FPGAs), application-specific integrated DSP chips, or general purpose personal computer systems. This paper presents a novel DSP platform that has been developed for feedback control on the HBT-EP tokamak device. The system runs all signal processing exclusively on a Graphics Processing Unit (GPU) to achieve real-time performance with latencies below 8 μs. Signals are transferred into and out of the GPU using PCI Express peer-to-peer direct-memory-access transfers without involvement of the central processing unit or host memory. Tests were performed on the feedback control system of the HBT-EP tokamak using forty 16-bit floating point inputs and outputs each and a sampling rate of up to 250 kHz. Signals were digitized by a D-TACQ ACQ196 module, processing done on an NVIDIA GTX 580 GPU programmed in CUDA, and analog output was generated by D-TACQ AO32CPCI modules.

Active vibration control of a full scale aircraft wing using a reconfigurable controller

NASA Astrophysics Data System (ADS)

Prakash, Shashikala; Renjith Kumar, T. G.; Raja, S.; Dwarakanathan, D.; Subramani, H.; Karthikeyan, C.

2016-01-01

This work highlights the design of a Reconfigurable Active Vibration Control (AVC) System for aircraft structures using adaptive techniques. The AVC system with a multichannel capability is realized using Filtered-X Least Mean Square algorithm (FxLMS) on Xilinx Virtex-4 Field Programmable Gate Array (FPGA) platform in Very High Speed Integrated Circuits Hardware Description Language, (VHDL). The HDL design is made based on Finite State Machine (FSM) model with Floating point Intellectual Property (IP) cores for arithmetic operations. The use of FPGA facilitates to modify the system parameters even during runtime depending on the changes in user's requirements. The locations of the control actuators are optimized based on dynamic modal strain approach using genetic algorithm (GA). The developed system has been successfully deployed for the AVC testing of the full-scale wing of an all composite two seater transport aircraft. Several closed loop configurations like single channel and multi-channel control have been tested. The experimental results from the studies presented here are very encouraging. They demonstrate the usefulness of the system's reconfigurability for real time applications.

Hafnium silicate and hafnium silicon oxynitride gate dielectrics for strained Si_xGe_1-x: Interface stability

NASA Astrophysics Data System (ADS)

Addepalli, Swarna; Sivasubramani, Prasanna; El-Bouanani, Mohamed; Kim, Moon; Gnade, Bruce; Wallace, Robert

2003-03-01

Strained Si_xGe_1-x layers have gained considerable attention due to hole mobility enhancement, and ease of integration with Si-based CMOS technology. The deposition of stable high-κ dielectrics [1] such as hafnium silicate and hafnium silicon oxynitride in direct contact with SiGe would simultaneously improve the capacitance of the gate stack and lower the leakage current for high performance SiGe devices. However, the oxidation of the Si_xGe_1-x substrate either during dielectric deposition or post-deposition processing would degrade device performance due to the thermodynamic instability of germanium oxide [2,3]. Results from XPS, HR-TEM, and C-V, and I-V analyses after various annealing treatments will be presented for hafnium silicate and hafnium silicon oxynitride films deposited on strained Si_xGe_1-x(100), and correlated with dielectric-Si_xGe_1-x(100) interface stability. Implications to the introduction of these oxides as viable gate dielectric candidates for SiGe-based CMOS technology will be discussed. This work is supported by DARPA through SPAWAR Grant No. N66001-00-1-8928, and the Texas Advanced Technology Program. References: [1] G. D. Wilk, R. M. Wallace and J. M. Anthony, Journal of Applied Physics, 89, 5243 (2001) [2] W. S. Liu, J .S. Chen, M.-A. Nicolet, V. Arbet-Engels, K. L. Wang, Journal of Applied Physics, 72, 4444 (1992), and, Applied Physics Letters, 62, 3321 (1993) [3] W. S. Liu, M. -A. Nicolet, H. -H. Park, B. -H. Koak, J. -W. Lee, Journal of Applied Physics, 78, 2631 (1995)

A novel high-performance high-frequency SOI MESFET by the damped electric field

NASA Astrophysics Data System (ADS)

Orouji, Ali A.; Khayatian, Ahmad; Keshavarzi, Parviz

2016-06-01

In this paper, we introduce a novel silicon-on-insulator (SOI) metal-semiconductor field-effect-transistor (MESFET) using the damped electric field (DEF). The proposed structure is geometrically symmetric and compatible with common SOI CMOS fabrication processes. It has two additional oxide regions under the side gates in order to improve DC and RF characteristics of the DEF structure due to changes in the electrical potential, the electrical field distributions, and rearrangement of the charge carriers. Improvement of device performance is investigated by two-dimensional and two-carrier simulation of fundamental parameters such as breakdown voltage (VBR), drain current (ID), output power density (Pmax), transconductance (gm), gate-drain and gate-source capacitances, cut-off frequency (fT), unilateral power gain (U), current gain (h21), maximum available gain (MAG), and minimum noise figure (Fmin). The results show that proposed structure operates with higher performances in comparison with the similar conventional SOI structure.

Architecture and applications of a high resolution gated SPAD image sensor

PubMed Central

Burri, Samuel; Maruyama, Yuki; Michalet, Xavier; Regazzoni, Francesco; Bruschini, Claudio; Charbon, Edoardo

2014-01-01

We present the architecture and three applications of the largest resolution image sensor based on single-photon avalanche diodes (SPADs) published to date. The sensor, fabricated in a high-voltage CMOS process, has a resolution of 512 × 128 pixels and a pitch of 24 μm. The fill-factor of 5% can be increased to 30% with the use of microlenses. For precise control of the exposure and for time-resolved imaging, we use fast global gating signals to define exposure windows as small as 4 ns. The uniformity of the gate edges location is ∼140 ps (FWHM) over the whole array, while in-pixel digital counting enables frame rates as high as 156 kfps. Currently, our camera is used as a highly sensitive sensor with high temporal resolution, for applications ranging from fluorescence lifetime measurements to fluorescence correlation spectroscopy and generation of true random numbers. PMID:25090572

A Physics-Based Engineering Methodology for Calculating Soft Error Rates of Bulk CMOS and SiGe Heterojunction Bipolar Transistor Integrated Circuits

NASA Astrophysics Data System (ADS)

Fulkerson, David E.

2010-02-01

This paper describes a new methodology for characterizing the electrical behavior and soft error rate (SER) of CMOS and SiGe HBT integrated circuits that are struck by ions. A typical engineering design problem is to calculate the SER of a critical path that commonly includes several circuits such as an input buffer, several logic gates, logic storage, clock tree circuitry, and an output buffer. Using multiple 3D TCAD simulations to solve this problem is too costly and time-consuming for general engineering use. The new and simple methodology handles the problem with ease by simple SPICE simulations. The methodology accurately predicts the measured threshold linear energy transfer (LET) of a bulk CMOS SRAM. It solves for circuit currents and voltage spikes that are close to those predicted by expensive 3D TCAD simulations. It accurately predicts the measured event cross-section vs. LET curve of an experimental SiGe HBT flip-flop. The experimental cross section vs. frequency behavior and other subtle effects are also accurately predicted.

Annual Conference on Nuclear and Space Radiation Effects, 14th, College of William and Mary, Williamsburg, Va., July 12-15, 1977, Proceedings

NASA Technical Reports Server (NTRS)

Stahl, R. H.

1977-01-01

Topics related to processing and hardness assurance are considered, taking into account the radiation hardening of CMOS technologies, technological advances in the manufacture of radiation-hardened CMOS integrated circuits, CMOS hardness assurance through process controls and optimized design procedures, the application of operational amplifiers to hardened systems, a hard off-the-shelf SG1524 pulse width modulator, and the gamma-induced voltage breakdown anomaly in a Schottky diode. Basic mechanisms are examined, giving attention to chemical and structural aspects of the irradiation behavior of SiO2 films on silicon, experimental observations of the chemistry of the SiO2/Si interface, leakage current phenomena in irradiated SOS devices, the avalanche injection of holes into SiO2, the low-temperature radiation response of Al2O3 gate insulators, and neutron damage mechanisms in silicon at 10 K. Other subjects discussed are related to radiation effects in devices and circuits, space radiation effects, and aspects of simulation, energy deposition, and dosimetry.

A comprehensive model on field-effect pnpn devices (Z2-FET)

NASA Astrophysics Data System (ADS)

Taur, Yuan; Lacord, Joris; Parihar, Mukta Singh; Wan, Jing; Martinie, Sebastien; Lee, Kyunghwa; Bawedin, Maryline; Barbe, Jean-Charles; Cristoloveanu, Sorin

2017-08-01

A comprehensive model for field-effect pnpn devices (Z2-FET) is presented. It is based on three current continuity equations coupled to two MOS equations. The model reproduces the characteristic S-shaped I-V curve when the device is driven by a current source. The negative resistance region at intermediate currents occurs as the center junction undergoes a steep transition from reverse to forward bias. Also playing a vital role are the mix and match of the minority carrier diffusion current and the generation recombination current. Physical insights to the key mechanisms at work are gained by regional approximations of the model, from which analytical expressions for the maximum and minimum voltages at the switching points are derived. From 1981 to 2001, he was with the Silicon Technology Department of IBM Thomas J. Watson Research Center, Yorktown Heights, New York, where he was Manager of Exploratory Devices and Processes. Areas in which he has worked and published include latchup-free 1-um CMOS, self-aligned TiSi2, 0.5-um CMOS and BiCMOS, shallow trench isolation, 0.25-um CMOS with n+/p + poly gates, SOI, low-temperature CMOS, and 0.1-um CMOS. Since October 2001, he has been a professor in the Department of Electrical and Computer Engineering, University of California, San Diego. Dr. Yuan Taur was elected a Fellow of the IEEE in 1998. He has served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011. He authored or co-authored over 200 technical papers and holds 14 U.S. patents. He co-authored a book, ;Fundamentals of Modern VLSI Devices,; published by Cambridge University Press in 1998. The 2nd edition was published in 2009. Dr. Yuan Taur received IEEE Electron Devices Society's J. J. Ebers Award in 2012 ;for contributions to the advancement of several generations of CMOS process technologies.;

152. Photographic copy of original construction drawing dated October 24, ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

152. Photographic copy of original construction drawing dated October 24, 1930 (from Record Group 115, Denver Branch of the National Archives, Denver). 60 x 12 RING GATE CONTROL; FLOAT WELL ASSEMBLY AND COVER HOIST STEM-CONNECTION ROD-SLEEVE. - Owyhee Dam, Across Owyhee River, Nyssa, Malheur County, OR

Design of 2.4Ghz CMOS Floating Active Inductor LNA using 130nm Technology

NASA Astrophysics Data System (ADS)

Muhamad, M.; Soin, N.; Ramiah, H.

2018-03-01

This paper presents about design and optimization of CMOS active inductor integrated circuit. This active inductor implements using Silterra 0.13μm technology and simulated using Cadence Virtuoso and Spectre RF. The center frequency for this active inductor is at 2.4 GHz which follow IEEE 802.11 b/g/n standard. To reduce the chip size of silicon, active inductor is used instead of passive inductor at low noise amplifier LNA circuit. This inductor test and analyse by low noise amplifier circuit. Comparison between active with passive inductor based on LNA circuit has been performed. Result shown that the active inductor has significantly reduce the chip size with 73 % area without sacrificing the noise figure and gain of LNA which is the most important criteria in LNA. The best low noise amplifier provides a power gain (S21) of 20.7 dB with noise figure (NF) of 2.1dB.

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II-VI Tunnel Insulators

NASA Astrophysics Data System (ADS)

Suarez, E.; Gogna, M.; Al-Amoody, F.; Karmakar, S.; Ayers, J.; Heller, E.; Jain, F.

2010-07-01

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn0.95Mg0.05S/ZnS tunnel insulators. The GeO x -cladded Ge and SiO x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II-VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II-VI stack serves both as a tunnel insulator and a high- κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si3N4 and SiO2 layers grown by plasma- enhanced chemical vapor deposition.

A MODFET dc model with improved pinchoff and saturation characteristics

NASA Astrophysics Data System (ADS)

Rohdin, Hans; Roblin, Patrick

1986-05-01

An improved analytical dc model for the MODFET is proposed which uses a new approximation of the two-dimensional electron gas concentration versus gate-to-channel voltage, a ratio which models both the subthreshold region and the gradual saturation of carriers due to the onset of AlGaAs charge modulation. A two-region Grebene-Ghandi model with a floating boundary is used for the channel. A maximum transconductance and a finite intrinsic output conductance in the saturated region are predicted, in agreement with experimental observations. The model is shown to approach the saturated velocity model in the limit of very short gate lengths, and to approach the classical gradual channel model in the limit of very long gate lengths.

Efficient Multiplexer FPGA Block Structures Based on G4FETs

NASA Technical Reports Server (NTRS)

Vatan, Farrokh; Fijany, Amir

2009-01-01

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

Millimeter-Wave Voltage-Controlled Oscillators in 0.13-micrometer CMOS Technology

DTIC Science & Technology

2006-06-01

controlled oscillators. Varactor , transistor, and in- ductor designs are optimized to reduce the parasitic capacitances. An investigation of tradeoff between...quality factor and tuning range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between 0.18 and 0.24 m result both good...millimeter wave, MOS varactor , quality factor, transmission line, voltage-controlled oscillator (VCO). I. INTRODUCTION WITH THE RAPID advance of high

Scaling and application of commercial, feature-rich, modular mixed-signal technology platforms for large format ROICs

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Racanelli, Marco; Howard, David; Miyagi, Glenn; Bowler, Mark; Jordan, Scott; Zhang, Tao; Krieger, William

2010-04-01

Today's modular, mixed-signal CMOS process platforms are excellent choices for manufacturing of highly integrated, large-format read out integrated circuits (ROICs). Platform features, that can be used for both cooled and un-cooled ROIC applications, can include (1) quality passives such as 4fFμm2 stacked MIM capacitors for linearity and higher density capacitance per pixel, 1kOhm high-value poly-silicon resistors, 2.8μm thick metals for efficient power distribution and reduced I-R drop; (2) analog active devices such as low noise single gate 3.3V, and 1.8V/3.3V or 1.8V/5V dual gate configurations, 40V LDMOS FETs, and NPN and PNP devices, deep n-well for substrate isolation for analog blocks and digital logic; (3) tools to assist the circuit designer such as models for cryogenic temperatures, CAD assistance for metal density uniformity determination, statistical, X-sigma and PCM-based models for corner validation and to simulate design sensitivity, and (4) sub-field stitching for large die. The TowerJazz platform of technology for 0.50μm, 0.25μm and 0.18μm CMOS nodes, with features as described above, is described in detail in this paper.

Software Techniques for Non-Von Neumann Architectures

DTIC Science & Technology

1990-01-01

Commtopo programmable Benes net.; hypercubic lattice for QCD Control CENTRALIZED Assign STATIC Memory :SHARED Synch UNIVERSAL Max-cpu 566 Proessor...boards (each = 4 floating point units, 2 multipliers) Cpu-size 32-bit floating point chips Perform 11.4 Gflops Market quantum chromodynamics ( QCD ...functions there should exist a capability to define hierarchies and lattices of complex objects. A complex object can be made up of a set of simple objects

NEPP Update of Independent Single Event Upset Field Programmable Gate Array Testing

NASA Technical Reports Server (NTRS)

Berg, Melanie; Label, Kenneth; Campola, Michael; Pellish, Jonathan

2017-01-01

This presentation provides a NASA Electronic Parts and Packaging (NEPP) Program update of independent Single Event Upset (SEU) Field Programmable Gate Array (FPGA) testing including FPGA test guidelines, Microsemi RTG4 heavy-ion results, Xilinx Kintex-UltraScale heavy-ion results, Xilinx UltraScale+ single event effect (SEE) test plans, development of a new methodology for characterizing SEU system response, and NEPP involvement with FPGA security and trust.

Initial Single Event Effects Testing of the Xilinx Virtex-4 Field Programmable Gate Array

NASA Technical Reports Server (NTRS)

Allen, Gregory R.; Swift, Gary M.; Carmichael, C.; Tseng, C.

2007-01-01

We present initial results for the thin epitaxial Xilinx Virtex-4 Fie ld Programmable Gate Array (FPGA), and compare to previous results ob tained for the Virtex-II and Virtex-II Pro. The data presented was a cquired through a consortium based effort with the common goal of pr oviding the space community with data and mitigation methods for the use of Xilinx FPGAs in space.

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

NASA Astrophysics Data System (ADS)

Suarez, Ernesto; Chan, Pik-Yiu; Lingalugari, Murali; Ayers, John E.; Heller, Evan; Jain, Faquir

2013-11-01

This paper describes the use of II-VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II-VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

Time-Gated Raman Spectroscopy for Quantitative Determination of Solid-State Forms of Fluorescent Pharmaceuticals.

PubMed

Lipiäinen, Tiina; Pessi, Jenni; Movahedi, Parisa; Koivistoinen, Juha; Kurki, Lauri; Tenhunen, Mari; Yliruusi, Jouko; Juppo, Anne M; Heikkonen, Jukka; Pahikkala, Tapio; Strachan, Clare J

2018-04-03

Raman spectroscopy is widely used for quantitative pharmaceutical analysis, but a common obstacle to its use is sample fluorescence masking the Raman signal. Time-gating provides an instrument-based method for rejecting fluorescence through temporal resolution of the spectral signal and allows Raman spectra of fluorescent materials to be obtained. An additional practical advantage is that analysis is possible in ambient lighting. This study assesses the efficacy of time-gated Raman spectroscopy for the quantitative measurement of fluorescent pharmaceuticals. Time-gated Raman spectroscopy with a 128 × (2) × 4 CMOS SPAD detector was applied for quantitative analysis of ternary mixtures of solid-state forms of the model drug, piroxicam (PRX). Partial least-squares (PLS) regression allowed quantification, with Raman-active time domain selection (based on visual inspection) improving performance. Model performance was further improved by using kernel-based regularized least-squares (RLS) regression with greedy feature selection in which the data use in both the Raman shift and time dimensions was statistically optimized. Overall, time-gated Raman spectroscopy, especially with optimized data analysis in both the spectral and time dimensions, shows potential for sensitive and relatively routine quantitative analysis of photoluminescent pharmaceuticals during drug development and manufacturing.

Monte Carlo simulations of spin transport in a strained nanoscale InGaAs field effect transistor

NASA Astrophysics Data System (ADS)

Thorpe, B.; Kalna, K.; Langbein, F. C.; Schirmer, S.

2017-12-01

Spin-based logic devices could operate at a very high speed with a very low energy consumption and hold significant promise for quantum information processing and metrology. We develop a spintronic device simulator by combining an in-house developed, experimentally verified, ensemble self-consistent Monte Carlo device simulator with spin transport based on a Bloch equation model and a spin-orbit interaction Hamiltonian accounting for Dresselhaus and Rashba couplings. It is employed to simulate a spin field effect transistor operating under externally applied voltages on a gate and a drain. In particular, we simulate electron spin transport in a 25 nm gate length In0.7Ga0.3As metal-oxide-semiconductor field-effect transistor with a CMOS compatible architecture. We observe a non-uniform decay of the net magnetization between the source and the gate and a magnetization recovery effect due to spin refocusing induced by a high electric field between the gate and the drain. We demonstrate a coherent control of the polarization vector of the drain current via the source-drain and gate voltages, and show that the magnetization of the drain current can be increased twofold by the strain induced into the channel.

The Euro-Argo education web site: using Argo data to teach data analysis and marine science

NASA Astrophysics Data System (ADS)

Byfield, Valborg; Scheurle, Carolyn; Gould, John; Macama, Emina; King, Brian

2013-04-01

The Euro-Argo education website (www.euroargo-edu.org) aims to make Argo and its data accessible to a non-specialist audience. The site is centred on a selection of floats, which have been chosen because of the insight they provide into key oceanographic processes, the physical and biogeochemical characteristics of different ocean regions around the world, and the role of the ocean in the global climate system. The float selection is a vehicle for teaching data analysis skills, linking these to current topics in the ocean and climate sciences. Each float in the selection has its own page, which provides access to the float data, data plots, background information on the ocean region in which the float can be found, and questions to guide data interpretation. Hidden 'model answers' allow users to check their understanding by comparing their own answers to those provided. The interactive component of the site also includes a series of quizzes, designed to teach data interpretation skills. These start at a basic level and take the students step by step through the most common ways to plot oceanographic data in space and time. More general background information covers the main aspects of the Argo programme, its history and applications, and basic technical information about the floats and sensors. 'World Tour' pages linked to the float selection provide information about the main ocean regions and link information from the Argo programme to oceanographic information from other sources such as satellite observations. The site is primarily aimed at young people between 11 and 18 years of age. However experience from using selected material from the site during science open days shows that children as young as 8-9 and adults of all ages also enjoy the challenge of using and interpreting the Argo data in different contexts.

A CMOS Luminescence Intensity and Lifetime Dual Sensor Based on Multicycle Charge Modulation.

PubMed

Fu, Guoqing; Sonkusale, Sameer R

2018-06-01

Luminescence plays an important role in many scientific and industrial applications. This paper proposes a novel complementary metal-oxide-semiconductor (CMOS) sensor chip that can realize both luminescence intensity and lifetime sensing. To enable high sensitivity, we propose parasitic insensitive multicycle charge modulation scheme for low-light lifetime extraction benefiting from simplicity, accuracy, and compatibility with deeply scaled CMOS process. The designed in-pixel capacitive transimpedance amplifier (CTIA) based structure is able to capture the weak luminescence-induced voltage signal by accumulating photon-generated charges in 25 discrete gated 10-ms time windows and 10-μs pulsewidth. A pinned photodiode on chip with 1.04 pA dark current is utilized for luminescence detection. The proposed CTIA-based circuitry can achieve 2.1-mV/(nW/cm 2 ) responsivity and 4.38-nW/cm 2 resolution at 630 nm wavelength for intensity measurement and 45-ns resolution for lifetime measurement. The sensor chip is employed for measuring time constants and luminescence lifetimes of an InGaN-based white light-emitting diode at different wavelengths. In addition, we demonstrate accurate measurement of the lifetime of an oxygen sensitive chromophore with sensitivity to oxygen concentration of 7.5%/ppm and 6%/ppm in both intensity and lifetime domain. This CMOS-enabled oxygen sensor was then employed to test water quality from different sources (tap water, lakes, and rivers).

How small can MOSFETs get?

NASA Astrophysics Data System (ADS)

Risch, Lothar

2001-10-01

Scaling of CMOS technology made possible the key appliances of our information technology society, like the PC, mobile communication, and the internet. Reduction of feature sizes for semiconductor devices continued according to Moore's law for the last 25 years in order to achieve higher integration densities, higher speed, lower power consumption, and lower costs. But now, as we approach the sub 100 nm regime, several roadblocks have been predicted for the next generations down to 35 nm. The latest ITRS roadmap 99 describes in detail the challenges which have to be addressed for the future CMOS technology nodes, regarding lithography, metallization, power dissipation, and circuit design. Also for the MOSFET, performance degradation is a big issue. Because this is not a limitation from basic physical laws, novel architectures for MOSFETs will be needed to improve again the electrical characteristics and thus pave the way to much smaller transistors than expected in the past. 25 nm CMOS seems to be feasible using very thin silicon substrates on insulator. Further improvements down to 10 nm are very likely with two gates for the control of the charge carriers. So, it is very likely that CMOS will not end with today's roadmap at 35 nm or even before, but may continue with non bulk devices and fully depleted channels. Finally, tunnelling from source to drain will set an end to the reduction of channel length, which is estimated to be below 5 nm.

Advanced, High Power, Next Scale, Wave Energy Conversion Device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mekhiche, Mike; Dufera, Hiz; Montagna, Deb

2012-10-29

The project conducted under DOE contract DE‐EE0002649 is defined as the Advanced, High Power, Next Scale, Wave Energy Converter. The overall project is split into a seven‐stage, gated development program. The work conducted under the DOE contract is OPT Stage Gate III work and a portion of Stage Gate IV work of the seven stage product development process. The project effort includes Full Concept Design & Prototype Assembly Testing building on our existing PowerBuoy technology to deliver a device with much increased power delivery. Scaling‐up from 150kW to 500kW power generating capacity required changes in the PowerBuoy design that addressedmore » cost reduction and mass manufacturing by implementing a Design for Manufacturing (DFM) approach. The design changes also focused on reducing PowerBuoy Installation, Operation and Maintenance (IO&M) costs which are essential to reducing the overall cost of energy. In this design, changes to the core PowerBuoy technology were implemented to increase capability and reduce both CAPEX and OPEX costs. OPT conceptually envisaged moving from a floating structure to a seabed structure. The design change from a floating structure to seabed structure would provide the implementation of stroke‐ unlimited Power Take‐Off (PTO) which has a potential to provide significant power delivery improvement and transform the wave energy industry if proven feasible.« less

The Development of III-V Semiconductor MOSFETs for Future CMOS Applications

NASA Astrophysics Data System (ADS)

Greene, Andrew M.

Alternative channel materials with superior transport properties over conventional strained silicon are required for supply voltage scaling in low power complementary metal-oxide-semiconductor (CMOS) integrated circuits. Group III-V compound semiconductor systems offer a potential solution due to their high carrier mobility, low carrier effective mass and large injection velocity. The enhancement in transistor drive current at a lower overdrive voltage allows for the scaling of supply voltage while maintaining high switching performance. This thesis focuses on overcoming several material and processing challenges associated with III-V semiconductor development including a low thermal processing budget, high interface trap state density (Dit), low resistance source/drain contacts and growth on lattice mismatched substrates. Non-planar In0.53Ga0.47As FinFETs were developed using both "gate-first" and "gate-last" fabrication methods for n-channel MOSFETs. Electron beam lithography and anisotropic plasma etching processes were optimized to create highly scaled fins with near vertical sidewalls. Plasma damage was removed using a wet etch process and improvements in gate efficiency were characterized on MOS capacitor structures. A two-step, selective removal of the pre-grown n+ contact layer was developed for "gate-last" recess etching. The final In0.53Ga 0.47As FinFET devices demonstrated an ION = 70 mA/mm, I ON/IOFF ratio = 15,700 and sub-threshold swing = 210 mV/dec. Bulk GaSb and strained In0.36Ga0.64Sb quantum well (QW) heterostructures were developed for p-channel MOSFETs. Dit was reduced to 2 - 3 x 1012 cm-2eV-1 using an InAs surface layer, (NH4)2S passivation and atomic layer deposition (ALD) of Al2O3. A self-aligned "gate-first" In0.36Ga0.64Sb MOSFET fabrication process was invented using a "T-shaped" electron beam resist patterning stack and intermetallic source/drain contacts. Ni contacts annealed at 300°C demonstrated an ION = 166 mA/mm, ION/IOFF ratio = 1,500 and sub-threshold swing = 340 mV/dec. Split C-V measurements were used to extract an effective channel mobility of muh* = 300 cm2/Vs at Ns = 2 x 1012 cm -2. "Gate-last" MOSFETs grown with an epitaxial p + contact layer were fabricated using selective gate-recess etching techniques. A parasitic "n-channel" limited ION/I OFF ratio and sub-threshold swing, most likely due to effects from the InAs surface layer.

Direct protein detection with a nano-interdigitated array gate MOSFET.

PubMed

Tang, Xiaohui; Jonas, Alain M; Nysten, Bernard; Demoustier-Champagne, Sophie; Blondeau, Franoise; Prévot, Pierre-Paul; Pampin, Rémi; Godfroid, Edmond; Iñiguez, Benjamin; Colinge, Jean-Pierre; Raskin, Jean-Pierre; Flandre, Denis; Bayot, Vincent

2009-08-15

A new protein sensor is demonstrated by replacing the gate of a metal oxide semiconductor field effect transistor (MOSFET) with a nano-interdigitated array (nIDA). The sensor is able to detect the binding reaction of a typical antibody Ixodes ricinus immunosuppressor (anti-Iris) protein at a concentration lower than 1 ng/ml. The sensor exhibits a high selectivity and reproducible specific detection. We provide a simple model that describes the behavior of the sensor and explains the origin of its high sensitivity. The simulated and experimental results indicate that the drain current of nIDA-gate MOSFET sensor is significantly increased with the successive binding of the thiol layer, Iris and anti-Iris protein layers. It is found that the sensor detection limit can be improved by well optimizing the geometrical parameters of nIDA-gate MOSFET. This nanobiosensor, with real-time and label-free capabilities, can easily be used for the detection of other proteins, DNA, virus and cancer markers. Moreover, an on-chip associated electronics nearby the sensor can be integrated since its fabrication is compatible with complementary metal oxide semiconductor (CMOS) technology.

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

PubMed Central

Long, Rathnait D.; McIntyre, Paul C.

2012-01-01

The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

The Pr 2O 3/Si(0 0 1) interface studied by synchrotron radiation photo-electron spectroscopy

NASA Astrophysics Data System (ADS)

Schmeißer, D.; Müssig, H.-J.

2003-10-01

Pr 2O 3 is currently under consideration as a potential replacement for SiO 2 as the gate-dielectric material for sub-0.1 μm complementary metal-oxide-semiconductor (CMOS) technology. We studied the Pr 2O 3/Si(0 0 1) interface by a non-destructive depth profiling using synchrotron radiation photoelectron spectroscopy. Our data suggests that there is no silicide formation at the interface. Based on reported results, a chemical reactive interface exists, consisting of a mixed Si-Pr oxide such as (Pr 2O 3) x(SiO 2) 1- x, i.e. as a silicate phase with variable silicon content. This pseudo-binary alloy at the interface offers large flexibility toward successful integration of Pr 2O 3 into future CMOS technologies.

Development of a radiation-hard CMOS process

NASA Technical Reports Server (NTRS)

Power, W. L.

1983-01-01

It is recommended that various techniques be investigated which appear to have the potential for improving the radiation hardness of CMOS devices for prolonged space flight mission. The three key recommended processing techniques are: (1) making the gate oxide thin. It has been shown that radiation degradation is proportional to the cube of oxide thickness so that a relatively small reduction in thickness can greatly improve radiation resistance; (2) cleanliness and contamination control; and (3) to investigate different oxide growth (low temperature dry, TCE and HCL). All three produce high quality clean oxides, which are more radiation tolerant. Technique 2 addresses the reduction of metallic contamination. Technique 3 will produce a higher quality oxide by using slow growth rate conditions, and will minimize the effects of any residual sodium contamination through the introduction of hydrogen and chlorine into the oxide during growth.

Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits

NASA Astrophysics Data System (ADS)

Strangio, S.; Palestri, P.; Lanuzza, M.; Esseni, D.; Crupi, F.; Selmi, L.

2017-02-01

In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against a conventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits, which are commonly identified as representative of the digital logic environment. 28T and 24T topologies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated. Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solution. The extracted delays and energy characteristics are post-processed and translated into figures-of-merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (for the same device technology platform) and to the different technology platforms (for the same full-adder topology) are presented and discussed.

Aptamer-Binding Directed DNA Origami Pattern for Logic Gates.

PubMed

Yang, Jing; Jiang, Shuoxing; Liu, Xiangrong; Pan, Linqiang; Zhang, Cheng

2016-12-14

In this study, an aptamer-substrate strategy is introduced to control programmable DNA origami pattern. Combined with DNA aptamer-substrate binding and DNAzyme-cutting, small DNA tiles were specifically controlled to fill into the predesigned DNA origami frame. Here, a set of DNA logic gates (OR, YES, and AND) are performed in response to the stimuli of adenosine triphosphate (ATP) and cocaine. The experimental results are confirmed by AFM imaging and time-dependent fluorescence changes, demonstrating that the geometric patterns are regulated in a controllable and programmable manner. Our approach provides a new platform for engineering programmable origami nanopatterns and constructing complex DNA nanodevices.

Single-Event Effect (SEE) Survey of Advanced Reconfigurable Field Programmable Gate Arrays: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

NASA Technical Reports Server (NTRS)

Allen, Gregory

2011-01-01

The NEPP Reconfigurable Field-Programmable Gate Array (FPGA) task has been charged to evaluate reconfigurable FPGA technologies for use in space. Under this task, the Xilinx single-event-immune, reconfigurable FPGA (SIRF) XQR5VFX130 device was evaluated for SEE. Additionally, the Altera Stratix-IV and SiliconBlue iCE65 were screened for single-event latchup (SEL).

Implementing a Microcontroller Watchdog with a Field-Programmable Gate Array (FPGA)

NASA Technical Reports Server (NTRS)

Straka, Bartholomew

2013-01-01

Reliability is crucial to safety. Redundancy of important system components greatly enhances reliability and hence safety. Field-Programmable Gate Arrays (FPGAs) are useful for monitoring systems and handling the logic necessary to keep them running with minimal interruption when individual components fail. A complete microcontroller watchdog with logic for failure handling can be implemented in a hardware description language (HDL.). HDL-based designs are vendor-independent and can be used on many FPGAs with low overhead.

Anomalous annealing of floating gate errors due to heavy ion irradiation

NASA Astrophysics Data System (ADS)

Yin, Yanan; Liu, Jie; Sun, Youmei; Hou, Mingdong; Liu, Tianqi; Ye, Bing; Ji, Qinggang; Luo, Jie; Zhao, Peixiong

2018-03-01

Using the heavy ions provided by the Heavy Ion Research Facility in Lanzhou (HIRFL), the annealing of heavy-ion induced floating gate (FG) errors in 34 nm and 25 nm NAND Flash memories has been studied. The single event upset (SEU) cross section of FG and the evolution of the errors after irradiation depending on the ion linear energy transfer (LET) values, data pattern and feature size of the device are presented. Different rates of annealing for different ion LET and different pattern are observed in 34 nm and 25 nm memories. The variation of the percentage of different error patterns in 34 nm and 25 nm memories with annealing time shows that the annealing of FG errors induced by heavy-ion in memories will mainly take place in the cells directly hit under low LET ion exposure and other cells affected by heavy ions when the ion LET is higher. The influence of Multiple Cell Upsets (MCUs) on the annealing of FG errors is analyzed. MCUs with high error multiplicity which account for the majority of the errors can induce a large percentage of annealed errors.

Design of a radiation tolerant system for total ionizing dose monitoring using floating gate and RadFET dosimeters

NASA Astrophysics Data System (ADS)

Ferraro, R.; Danzeca, S.; Brucoli, M.; Masi, A.; Brugger, M.; Dilillo, L.

2017-04-01

The need for upgrading the Total Ionizing Dose (TID) measurement resolution of the current version of the Radiation Monitoring system for the LHC complex has driven the research of new TID sensors. The sensors being developed nowadays can be defined as Systems On Chip (SOC) with both analog and digital circuitries embedded in the same silicon. A radiation tolerant TID Monitoring System (TIDMon) has been designed to allow the placement of the entire dosimeter readout electronics in very harsh environments such as calibration rooms and even in the mixed radiation field such as the one of the LHC complex. The objective of the TIDMon is to measure the effect of the TID on the new prototype of Floating Gate Dosimeter (FGDOS) without using long cables and with a reliable measurement system. This work introduces the architecture of the TIDMon, the radiation tolerance techniques applied on the controlling electronics as well as the design choices adopted for the system. Finally, results of several tests of TIDMon under different radiation environments such as gamma rays or mixed radiation field at CHARM are presented.

The Gates Malaria Partnership: a consortium approach to malaria research and capacity development.

PubMed

Greenwood, Brian; Bhasin, Amit; Targett, Geoffrey

2012-05-01

Recently, there has been a major increase in financial support for malaria control. Most of these funds have, appropriately, been spent on the tools needed for effective prevention and treatment of malaria such as insecticide-treated bed nets, indoor residual spraying and artemisinin combination therapy. There has been less investment in the training of the scientists from malaria-endemic countries needed to support these large and increasingly complex malaria control programmes, especially in Africa. In 2000, with support from the Bill & Melinda Gates Foundation, the Gates Malaria Partnership was established to support postgraduate training of African scientists wishing to pursue a career in malaria research. The programme had three research capacity development components: a PhD fellowship programme, a postdoctoral fellowship programme and a laboratory infrastructure programme. During an 8-year period, 36 African PhD students and six postdoctoral fellows were supported, and two research laboratories were built in Tanzania. Some of the lessons learnt during this project--such as the need to improve PhD supervision in African universities and to provide better support for postdoctoral fellows--are now being applied to a successor malaria research capacity development programme, the Malaria Capacity Development Consortium, and may be of interest to other groups involved in improving postgraduate training in health sciences in African universities. © 2012 Blackwell Publishing Ltd.

Flexible low-voltage organic transistors with high thermal stability at 250 °C.

PubMed

Yokota, Tomoyuki; Kuribara, Kazunori; Tokuhara, Takeyoshi; Zschieschang, Ute; Klauk, Hagen; Takimiya, Kazuo; Sadamitsu, Yuji; Hamada, Masahiro; Sekitani, Tsuyoshi; Someya, Takao

2013-07-19

Low-operating-voltage flexible organic thin-film transistors with high thermal stability using DPh-DNTT and SAM gate dielectrics are reported. The mobility of the transistors are decreased by 23% after heating to 250 °C for 30 min. Furthermore, flexible organic pseudo-CMOS inverter circuits, which are functional after heating to 200 °C, are demonstrated. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Gaining Insight Into Femtosecond-scale CMOS Effects using FPGAs

DTIC Science & Technology

2015-03-24

paths or detecting gross path delay faults , but for characterizing subtle aging effects, there is a need to isolate very short paths and detect very...data using COTS FPGAs and novel self-test. Hardware experiments using a 28 nm FPGA demonstrate isolation of small sets of transistors, detection of...hold the static configuration data specifying the LUT function. A set of inverters drive the SRAM contents into a pass-gate multiplexor tree; we

A Robust High-Performance GPS L1 Receiver with Single-stage Quadrature Redio-Frequency Circuit

NASA Astrophysics Data System (ADS)

Liu, Jianghua; Xu, Weilin; Wan, Qinq; Liu, Tianci

2018-03-01

A low power current reuse single-stage quadrature raido-frequency part (SQRF) is proposed for GPS L1 receiver in 180nm CMOS process. The proposed circuit consists of LNA, Mixer, QVCO, is called the QLMV cell. A two blocks stacked topology is adopted in this design. The parallel QVCO and mixer placed on the top forms the upper stacked block, and the LNA placed on the bottom forms the other stacked block. The two blocks share the current and achieve low power performance. To improve the stability, a float current source is proposed. The float current isolated the local oscillation signal and the input RF signal, which bring the whole circuit robust high-performance. The result shows conversion gain is 34 dB, noise figure is three dB, the phase noise is -110 dBc/Hz at 1MHz and IIP3 is -20 dBm. The proposed circuit dissipated 1.7mW with 1 V supply voltage.

Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays

NASA Technical Reports Server (NTRS)

Allen, Gregory; Edmonds, Larry D.; Swift, Gary; Carmichael, Carl; Tseng, Chen Wei; Heldt, Kevin; Anderson, Scott Arlo; Coe, Michael

2010-01-01

We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilins Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.

Universal programmable logic gate and routing method

NASA Technical Reports Server (NTRS)

Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Mojarradi, Mohammad M. (Inventor); Fijany, Amir (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Toomarian, Nikzad (Inventor)

2009-01-01

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

Low mass MEMS/NEMS switch for a substitute of CMOS transistor using single-walled carbon nanotube thin film

NASA Astrophysics Data System (ADS)

Jang, Min-Woo

Power dissipation is a key factor for mobile devices and other low power applications. Complementary metal oxide semiconductor (CMOS) is the dominant integrated circuit (IC) technology responsible for a large part of this power dissipation. As the minimum feature size of CMOS devices enters into the sub 50 nanometer (nm) regime, power dissipation becomes much worse due to intrinsic physical limits. Many approaches have been studied to reduce power dissipation of deeply scaled CMOS ICs. One possible candidate is the electrostatic electromechanical switch, which could be fabricated with conventional CMOS processing techniques. They have critical advantages compared to CMOS devices such as almost zero standby leakage in the off-state due to the absence of a pn junction and a gate oxide, as well as excellent drive current in the on-state due to a metallic channel. Despite their excellent standby power dissipation, the electrostatic MEMS/NEMS switches have not been considered as a viable replacement for CMOS devices due to their large mechanical delay. Moreover, previous literature reveals that their pull-in voltage and switching speed are strongly proportional to each other. This reduces their potential advantage. However, in this work, we theoretically and experimentally demonstrated that the use of single-walled carbon nanotube (SWNT) with very low mass density and strong mechanical properties could provide a route to move off of the conventional trend with respect to the pull-in voltage / switching speed tradeoff observed in the literature. We fabricated 2-terminal fixed- beam switches with aligned composite SWNT thin films. In this work, layer-by-layer (LbL) self-assembly and dielectrophoresis were selected for aligned-composite SWNT thin film deposition. The dense membranes were successfully patterned to form submicron beams by e-beam lithography and oxygen plasma etching. Fixed-fixed beam switches using these membranes successfully operated with approximately 600 psec switching delay and as low as a 3 V dc pull-in. From this we confirmed that the SWNT-based thin films have the potential to make fast MEMS switches with a low operation voltage due to its low mass density and high stiffness. However, the copolymer caused a serious reliability issue and a copolymer-free SWNT film deposition method was developed by replacing positive copolymer with a dispersion of positively functionalized SWNTs. The electrical and physical properties of pure single-walled carbon nanotube thin films deposited through a copolymer-free LbL self-assembly process are then discussed. The film thickness was proportional to the number of dipping cycles. The film resistivity was estimated as 2.19x10-3 Ω-cm after thermal treatments were performed. The estimated specific contact resistance to gold electrodes was 6.33x10-9 Ω-m2 from contact chain measurements. The fabricated 3-terminal MEMS switches using these films functioned as a beam for multiple switching cycles with a 4.5V pull-in voltage, which was operated like a 2-input NAND gate. The SWNT-based thin film switch is promising for a variety of applications to high-end nanoelectronics and high- performance MEMS/NEMS.

Enhancing Learning Effectiveness in Digital Design Courses through the Use of Programmable Logic Boards

ERIC Educational Resources Information Center

Zhu, Yi; Weng, T.; Cheng, Chung-Kuan

2009-01-01

Incorporating programmable logic devices (PLD) in digital design courses has become increasingly popular. The advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), have been discussed before. However, previous studies have focused on the experiences from the point of view of the…

Loss analysis and optimum design of a highly efficient and compact CMOS DC–DC converter with novel transistor layout using 60 nm multipillar-type vertical body channel MOSFET

NASA Astrophysics Data System (ADS)

Itoh, Kazuki; Endoh, Tetsuo

2018-04-01

In this paper, we present a novel transistor layout of multi pillar-type vertical body-channel (BC) MOSFET for cascode power switches for improving the efficiency and compactness of CMOS DC–DC converters. The proposed layout features a stacked and multifingered layout to suppress the loss due to parasitic components such as diffusion resistance and contact resistance. In addition, the loss of each MOSFET, which configures cascode power switches, is analyzed, and it is revealed that the total optimum gate width and loss with the high-side (HS) n-type MOSFET topology are 27 and 16% smaller than those with the HS p-type MOSFET topology, respectively. Moreover, a circuit simulation of 2.0 to 0.8 V, 100 MHz CMOS DC–DC converters with the proposed layout is carried out by using experimentally extracted models of BSIM4 60 nm vertical BC MOSFETs. The peak efficiency of the HS n-type MOSFET converter with the proposed layout is 90.1%, which is 6.0% higher than that with the conventional layout.

Single-channel recordings of RyR1 at microsecond resolution in CMOS-suspended membranes.

PubMed

Hartel, Andreas J W; Ong, Peijie; Schroeder, Indra; Giese, M Hunter; Shekar, Siddharth; Clarke, Oliver B; Zalk, Ran; Marks, Andrew R; Hendrickson, Wayne A; Shepard, Kenneth L

2018-02-20

Single-channel recordings are widely used to explore functional properties of ion channels. Typically, such recordings are performed at bandwidths of less than 10 kHz because of signal-to-noise considerations, limiting the temporal resolution available for studying fast gating dynamics to greater than 100 µs. Here we present experimental methods that directly integrate suspended lipid bilayers with high-bandwidth, low-noise transimpedance amplifiers based on complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) technology to achieve bandwidths in excess of 500 kHz and microsecond temporal resolution. We use this CMOS-integrated bilayer system to study the type 1 ryanodine receptor (RyR1), a Ca 2+ -activated intracellular Ca 2+ -release channel located on the sarcoplasmic reticulum. We are able to distinguish multiple closed states not evident with lower bandwidth recordings, suggesting the presence of an additional Ca 2+ binding site, distinct from the site responsible for activation. An extended beta distribution analysis of our high-bandwidth data can be used to infer closed state flicker events as fast as 35 ns. These events are in the range of single-file ion translocations.

Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier.

PubMed

Yang, Jong-Ryul; Han, Seong-Tae; Baek, Donghyun

2017-09-09

We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m² input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB.

Differential CMOS Sub-Terahertz Detector with Subthreshold Amplifier

PubMed Central

Han, Seong-Tae; Baek, Donghyun

2017-01-01

We propose a differential-type complementary metal-oxide-semiconductor (CMOS) sub-terahertz (THz) detector with a subthreshold preamplifier. The proposed detector improves the voltage responsivity and effective signal-to-noise ratio (SNR) using the subthreshold preamplifier, which is located between the differential detector device and main amplifier. The overall noise of the detector for the THz imaging system is reduced by the preamplifier because it diminishes the noise contribution of the main amplifier. The subthreshold preamplifier is self-biased by the output DC voltage of the detector core and has a dummy structure that cancels the DC offsets generated by the preamplifier itself. The 200 GHz detector fabricated using 0.25 μm CMOS technology includes a low drop-out regulator, current reference blocks, and an integrated antenna. A voltage responsivity of 2020 kV/W and noise equivalent power of 76 pW/√Hz are achieved using the detector at a gate bias of 0.5 V, respectively. The effective SNR at a 103 Hz chopping frequency is 70.9 dB with a 0.7 W/m2 input signal power density. The dynamic range of the raster-scanned THz image is 44.59 dB. PMID:28891927

Energy reduction through voltage scaling and lightweight checking

NASA Astrophysics Data System (ADS)

Kadric, Edin

As the semiconductor roadmap reaches smaller feature sizes and the end of Dennard Scaling, design goals change, and managing the power envelope often dominates delay minimization. Voltage scaling remains a powerful tool to reduce energy. We find that it results in about 60% geomean energy reduction on top of other common low-energy optimizations with 22nm CMOS technology. However, when voltage is reduced, it becomes easier for noise and particle strikes to upset a node, potentially causing Silent Data Corruption (SDC). The 60% energy reduction, therefore, comes with a significant drop in reliability. Duplication with checking and triple-modular redundancy are traditional approaches used to combat transient errors, but spending 2--3x the energy for redundant computation can diminish or reverse the benefits of voltage scaling. As an alternative, we explore the opportunity to use checking operations that are cheaper than the base computation they are guarding. We devise a classification system for applications and their lightweight checking characteristics. In particular, we identify and evaluate the effectiveness of lightweight checks in a broad set of common tasks in scientific computing and signal processing. We find that the lightweight checks cost only a fraction of the base computation (0-25%) and allow us to recover the reliability losses from voltage scaling. Overall, we show about 50% net energy reduction without compromising reliability compared to operation at the nominal voltage. We use FPGAs (Field-Programmable Gate Arrays) in our work, although the same ideas can be applied to different systems. On top of voltage scaling, we explore other common low-energy techniques for FPGAs: transmission gates, gate boosting, power gating, low-leakage (high-Vth) processes, and dual-V dd architectures. We do not scale voltage for memories, so lower voltages help us reduce logic and interconnect energy, but not memory energy. At lower voltages, memories become dominant, and we get diminishing returns from continuing to scale voltage. To ensure that memories do not become a bottleneck, we also design an energy-robust FPGA memory architecture, which attempts to minimize communication energy due to mismatches between application and architecture. We do this alongside application parallelism tuning. We show our techniques on a wide range of applications, including a large real-time system used for Wide-Area Motion Imaging (WAMI).

Simulation of planar single-gate Si tunnel FET with average subthreshold swing of less than 60 mV/decade for 0.3 V operation

NASA Astrophysics Data System (ADS)

Kukita, Kentaro; Uechi, Tadayoshi; Shimokawa, Junji; Goto, Masakazu; Yokota, Yoshinori; Kawanaka, Shigeru; Tanamoto, Tetsufumi; Tanimoto, Hiroyoshi; Takagi, Shinichi

2018-04-01

Planar single-gate (SG) silicon (Si) tunnel field effect transistors (TFETs) are attracting interest for ultra-low voltage operation and CMOS applications. For the achievement of subthreshold swing (S.S.) less than thermal limit of Si MOSFETs (S.S. = 60 mV/decade at 300 K), previous studies have proposed the formation of a pocket region, which needs very difficult implantation process. In this work, a planar SG Si TFET without pocket was proposed by using the technology computer-aided design (TCAD) simulations. An average S.S. of less than 60 mV/decade for 0.3 V (= V gs = V ds) operation was obtained. It is found that both low average S.S. (= 27.8 mV/decade) and high on-current I on (= 3.8 µA/µm) are achieved without pocket doping by scaling the equivalent oxide thickness (EOT) and increasing the gate-to-source overlap length L ov.

Hardware architecture for projective model calculation and false match refining using random sample consensus algorithm

NASA Astrophysics Data System (ADS)

Azimi, Ehsan; Behrad, Alireza; Ghaznavi-Ghoushchi, Mohammad Bagher; Shanbehzadeh, Jamshid

2016-11-01

The projective model is an important mapping function for the calculation of global transformation between two images. However, its hardware implementation is challenging because of a large number of coefficients with different required precisions for fixed point representation. A VLSI hardware architecture is proposed for the calculation of a global projective model between input and reference images and refining false matches using random sample consensus (RANSAC) algorithm. To make the hardware implementation feasible, it is proved that the calculation of the projective model can be divided into four submodels comprising two translations, an affine model and a simpler projective mapping. This approach makes the hardware implementation feasible and considerably reduces the required number of bits for fixed point representation of model coefficients and intermediate variables. The proposed hardware architecture for the calculation of a global projective model using the RANSAC algorithm was implemented using Verilog hardware description language and the functionality of the design was validated through several experiments. The proposed architecture was synthesized by using an application-specific integrated circuit digital design flow utilizing 180-nm CMOS technology as well as a Virtex-6 field programmable gate array. Experimental results confirm the efficiency of the proposed hardware architecture in comparison with software implementation.

Atomic switches: atomic-movement-controlled nanodevices for new types of computing

PubMed Central

Hino, Takami; Hasegawa, Tsuyoshi; Terabe, Kazuya; Tsuruoka, Tohru; Nayak, Alpana; Ohno, Takeo; Aono, Masakazu

2011-01-01

Atomic switches are nanoionic devices that control the diffusion of metal cations and their reduction/oxidation processes in the switching operation to form/annihilate a metal atomic bridge, which is a conductive path between two electrodes in the on-state. In contrast to conventional semiconductor devices, atomic switches can provide a highly conductive channel even if their size is of nanometer order. In addition to their small size and low on-resistance, their nonvolatility has enabled the development of new types of programmable devices, which may achieve all the required functions on a single chip. Three-terminal atomic switches have also been developed, in which the formation and annihilation of a metal atomic bridge between a source electrode and a drain electrode are controlled by a third (gate) electrode. Three-terminal atomic switches are expected to enhance the development of new types of logic circuits, such as nonvolatile logic. The recent development of atomic switches that use a metal oxide as the ionic conductive material has enabled the integration of atomic switches with complementary metal-oxide-semiconductor (CMOS) devices, which will facilitate the commercialization of atomic switches. The novel characteristics of atomic switches, such as their learning and photosensing abilities, are also introduced in the latter part of this review. PMID:27877376

Fabrication of Nano-Crossbar Resistive Switching Memory Based on the Copper-Tantalum Pentoxide-Platinum Device Structure

NASA Astrophysics Data System (ADS)

Olga Gneri, Paula; Jardim, Marcos

Resistive switching memory has been of interest lately not only for its simple metal-insulator-metal (MIM) structure but also for its promising ease of scalability an integration into current CMOS technologies like the Field Programmable Gate Arrays and other non-volatile memory applications. There are several resistive switching MIM combinations but under this scope of research, attention will be paid to the bipolar resistive switching characteristics and fabrication of Tantalum Pentaoxide sandwiched between platinum and copper. By changing the polarity of the voltage bias, this metal-insulator-metal (MIM) device can be switched between a high resistive state (OFF) and low resistive state (ON). The change in states is induced by an electrochemical metallization process, which causes a formation or dissolution of Cu metal filamentary paths in the Tantalum Pentaoxide insulator. There is very little thorough experimental information about the Cu-Ta 2O5-Pt switching characteristics when scaled to nanometer dimensions. In this light, the MIM structure was fabricated in a two-dimensional crossbar format. Also, with the limited available resources, a multi-spacer technique was formulated to localize the active device area in this MIM configuration to less than 20nm. This step is important in understanding the switching characteristics and reliability of this structure when scaled to nanometer dimensions.

Design and implementation of a programming circuit in radiation-hardened FPGA

NASA Astrophysics Data System (ADS)

Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

2011-08-01

We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

Distributed Motor Controller (DMC) for Operation in Extreme Environments

NASA Technical Reports Server (NTRS)

McKinney, Colin M.; Yager, Jeremy A.; Mojarradi, Mohammad M.; Some, Rafi; Sirota, Allen; Kopf, Ted; Stern, Ryan; Hunter, Don

2012-01-01

This paper presents an extreme environment capable Distributed Motor Controller (DMC) module suitable for operation with a distributed architecture of future spacecraft systems. This motor controller is designed to be a bus-based electronics module capable of operating a single Brushless DC motor in extreme space environments: temperature (-120 C to +85 C required, -180 C to +100 C stretch goal); radiation (>;20K required, >;100KRad stretch goal); >;360 cycles of operation. Achieving this objective will result in a scalable modular configuration for motor control with enhanced reliability that will greatly lower cost during the design, fabrication and ATLO phases of future missions. Within the heart of the DMC lies a pair of cold-capable Application Specific Integrated Circuits (ASICs) and a Field Programmable Gate Array (FPGA) that enable its miniaturization and operation in extreme environments. The ASICs are fabricated in the IBM 0.5 micron Silicon Germanium (SiGe) BiCMOS process and are comprised of Analog circuitry to provide telemetry information, sensor interface, and health and status of DMC. The FPGA contains logic to provide motor control, status monitoring and spacecraft interface. The testing and characterization of these ASICs have yielded excellent functionality in cold temperatures (-135 C). The DMC module has demonstrated successful operation of a motor at temperature.

Real-time machine vision system using FPGA and soft-core processor

NASA Astrophysics Data System (ADS)

Malik, Abdul Waheed; Thörnberg, Benny; Meng, Xiaozhou; Imran, Muhammad

2012-06-01

This paper presents a machine vision system for real-time computation of distance and angle of a camera from reference points in the environment. Image pre-processing, component labeling and feature extraction modules were modeled at Register Transfer (RT) level and synthesized for implementation on field programmable gate arrays (FPGA). The extracted image component features were sent from the hardware modules to a soft-core processor, MicroBlaze, for computation of distance and angle. A CMOS imaging sensor operating at a clock frequency of 27MHz was used in our experiments to produce a video stream at the rate of 75 frames per second. Image component labeling and feature extraction modules were running in parallel having a total latency of 13ms. The MicroBlaze was interfaced with the component labeling and feature extraction modules through Fast Simplex Link (FSL). The latency for computing distance and angle of camera from the reference points was measured to be 2ms on the MicroBlaze, running at 100 MHz clock frequency. In this paper, we present the performance analysis, device utilization and power consumption for the designed system. The FPGA based machine vision system that we propose has high frame speed, low latency and a power consumption that is much lower compared to commercially available smart camera solutions.

NASA Tech Briefs, July 2007

NASA Technical Reports Server (NTRS)

2007-01-01

Topics covered include: Miniature Intelligent Sensor Module; "Smart" Sensor Module; Portable Apparatus for Electrochemical Sensing of Ethylene; Increasing Linear Dynamic Range of a CMOS Image Sensor; Flight Qualified Micro Sun Sensor; Norbornene-Based Polymer Electrolytes for Lithium Cells; Making Single-Source Precursors of Ternary Semiconductors; Water-Free Proton-Conducting Membranes for Fuel Cells; Mo/Ti Diffusion Bonding for Making Thermoelectric Devices; Photodetectors on Coronagraph Mask for Pointing Control; High-Energy-Density, Low-Temperature Li/CFx Primary Cells; G4-FETs as Universal and Programmable Logic Gates; Fabrication of Buried Nanochannels From Nanowire Patterns; Diamond Smoothing Tools; Infrared Imaging System for Studying Brain Function; Rarefying Spectra of Whispering-Gallery-Mode Resonators; Large-Area Permanent-Magnet ECR Plasma Source; Slot-Antenna/Permanent-Magnet Device for Generating Plasma; Fiber-Optic Strain Gauge With High Resolution And Update Rate; Broadband Achromatic Telecentric Lens; Temperature-Corrected Model of Turbulence in Hot Jet Flows; Enhanced Elliptic Grid Generation; Automated Knowledge Discovery From Simulators; Electro-Optical Modulator Bias Control Using Bipolar Pulses; Generative Representations for Automated Design of Robots; Mars-Approach Navigation Using In Situ Orbiters; Efficient Optimization of Low-Thrust Spacecraft Trajectories; Cylindrical Asymmetrical Capacitors for Use in Outer Space; Protecting Against Faults in JPL Spacecraft; Algorithm Optimally Allocates Actuation of a Spacecraft; and Radar Interferometer for Topographic Mapping of Glaciers and Ice Sheets.

Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation.

PubMed

Dutta, Sourav; Zografos, Odysseas; Gurunarayanan, Surya; Radu, Iuliana; Soree, Bart; Catthoor, Francky; Naeemi, Azad

2017-12-19

Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality - the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 μm 2 for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.

Measurement of charge transfer potential barrier in pinned photodiode CMOS image sensors

NASA Astrophysics Data System (ADS)

Chen, Cao; Bing, Zhang; Junfeng, Wang; Longsheng, Wu

2016-05-01

The charge transfer potential barrier (CTPB) formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode (PPD) CMOS image sensors (CIS), and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was performed in detail on the principle of the proposed method. Application of the measurements on a prototype PPD-CIS chip with an array of 160 × 160 pixels is demonstrated. Such a method intends to shine new light on the guidance for the lag-free and high-speed sensors optimization based on PPD devices. Project supported by the National Defense Pre-Research Foundation of China (No. 51311050301095).

Nonvolatile flip-flop based on pseudo-spin-transistor architecture and its nonvolatile power-gating applications for low-power CMOS logic

NASA Astrophysics Data System (ADS)

Yamamoto, Shuu'ichirou; Shuto, Yusuke; Sugahara, Satoshi

2013-07-01

We computationally analyzed performance and power-gating (PG) ability of a new nonvolatile delay flip-flop (NV-DFF) based on pseudo-spin-MOSFET (PS-MOSFET) architecture using spin-transfer-torque magnetic tunnel junctions (STT-MTJs). The high-performance energy-efficient PG operations of the NV-DFF can be achieved owing to its cell structure employing PS-MOSFETs that can electrically separate the STT-MTJs from the ordinary DFF part of the NV-DFF. This separation also makes it possible that the break-even time (BET) of the NV-DFF is designed by the size of the PS-MOSFETs without performance degradation of the normal DFF operations. The effect of the area occupation ratio of the NV-DFFs to a CMOS logic system on the BET was also analyzed. Although the optimized BET was varied depending on the area occupation ratio, energy-efficient fine-grained PG with a BET of several sub-microseconds was revealed to be achieved. We also proposed microprocessors and system-on-chip (SoC) devices using nonvolatile hierarchical-memory systems wherein NV-DFF and nonvolatile static random access memory (NV-SRAM) circuits are used as fundamental building blocks. Contribution to the Topical Issue “International Semiconductor Conference Dresden-Grenoble - ISCDG 2012”, Edited by Gérard Ghibaudo, Francis Balestra and Simon Deleonibus.

Product assurance technology for procuring reliable, radiation-hard, custom LSI/VLSI electronics

NASA Technical Reports Server (NTRS)

Buehler, M. G.; Allen, R. A.; Blaes, B. R.; Hicks, K. A.; Jennings, G. A.; Lin, Y.-S.; Pina, C. A.; Sayah, H. R.; Zamani, N.

1989-01-01

Advanced measurement methods using microelectronic test chips are described. These chips are intended to be used in acquiring the data needed to qualify Application Specific Integrated Circuits (ASIC's) for space use. Efforts were focused on developing the technology for obtaining custom IC's from CMOS/bulk silicon foundries. A series of test chips were developed: a parametric test strip, a fault chip, a set of reliability chips, and the CRRES (Combined Release and Radiation Effects Satellite) chip, a test circuit for monitoring space radiation effects. The technical accomplishments of the effort include: (1) development of a fault chip that contains a set of test structures used to evaluate the density of various process-induced defects; (2) development of new test structures and testing techniques for measuring gate-oxide capacitance, gate-overlap capacitance, and propagation delay; (3) development of a set of reliability chips that are used to evaluate failure mechanisms in CMOS/bulk: interconnect and contact electromigration and time-dependent dielectric breakdown; (4) development of MOSFET parameter extraction procedures for evaluating subthreshold characteristics; (5) evaluation of test chips and test strips on the second CRRES wafer run; (6) two dedicated fabrication runs for the CRRES chip flight parts; and (7) publication of two papers: one on the split-cross bridge resistor and another on asymmetrical SRAM (static random access memory) cells for single-event upset analysis.

Fully industrialised single photon avalanche diodes

NASA Astrophysics Data System (ADS)

Pellegrini, S.; Rae, B.

2017-05-01

Single Photon Avalanche diodes (SPADs) were first realized more than five decades ago[1][1], and have now been industrialized for mass production in the 130 nm CMOS technology node by STMicroelectronics (STM). In this paper we present the latest STM SPAD with an excellent NIR photon detection probability (>5% at 850nm), a dark count rate median of 100 cps at room temperature and a low breakdown voltage of 14.2V. The dead time of the SPAD is approximately 25 ns, leading to a maximum count rate of 40 Mcps. Thanks to the 130 nm gate length of the CMOS technology used and the associated high digital gate density, complex digital signal processing can be implemented allowing fully integrated systems to be realized. The low bias required by the SPAD makes it possible for voltage generation to be achieved on-chip (e.g. charge pumped). We introduce our first generation time-of-flight system (VL6180) based on the STM SPAD technology, which is capable of ranging up to 60 cm in 60 ms. Ranging capabilities and accuracy are measured using a set of moving targets with reflectance of 5%, 17% and 88% in a fully automated test bed. To the best of our knowledge this was the first high volume SPAD-based device. To our knowledge this is the first time details of SPAD performance over production volumes and lifetime have been presented.

Real-Time Spaceborne Synthetic Aperture Radar Float-Point Imaging System Using Optimized Mapping Methodology and a Multi-Node Parallel Accelerating Technique

PubMed Central

Li, Bingyi; Chen, Liang; Yu, Wenyue; Xie, Yizhuang; Bian, Mingming; Zhang, Qingjun; Pang, Long

2018-01-01

With the development of satellite load technology and very large-scale integrated (VLSI) circuit technology, on-board real-time synthetic aperture radar (SAR) imaging systems have facilitated rapid response to disasters. A key goal of the on-board SAR imaging system design is to achieve high real-time processing performance under severe size, weight, and power consumption constraints. This paper presents a multi-node prototype system for real-time SAR imaging processing. We decompose the commonly used chirp scaling (CS) SAR imaging algorithm into two parts according to the computing features. The linearization and logic-memory optimum allocation methods are adopted to realize the nonlinear part in a reconfigurable structure, and the two-part bandwidth balance method is used to realize the linear part. Thus, float-point SAR imaging processing can be integrated into a single Field Programmable Gate Array (FPGA) chip instead of relying on distributed technologies. A single-processing node requires 10.6 s and consumes 17 W to focus on 25-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384. The design methodology of the multi-FPGA parallel accelerating system under the real-time principle is introduced. As a proof of concept, a prototype with four processing nodes and one master node is implemented using a Xilinx xc6vlx315t FPGA. The weight and volume of one single machine are 10 kg and 32 cm × 24 cm × 20 cm, respectively, and the power consumption is under 100 W. The real-time performance of the proposed design is demonstrated on Chinese Gaofen-3 stripmap continuous imaging. PMID:29495637

Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation

NASA Astrophysics Data System (ADS)

Koike, Hiroki; Ohsawa, Takashi; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2015-04-01

A spintronic-based power-gated micro-processing unit (MPU) is proposed. It includes a power control circuit activated by the newly supported power-off instruction for the deep-sleep mode. These means enable the power-off procedure for the MPU to be executed appropriately. A test chip was designed and fabricated using 90 nm CMOS and an additional 100 nm MTJ process; it was successfully operated. The guideline of the energy reduction effects for this MPU was presented, using the estimation based on the measurement results of the test chip. The result shows that a large operation energy reduction of 1/28 can be achieved when the operation duty is 10%, under the condition of a sufficient number of idle clock cycles.

An Evaluation of Flash Cells Used in Critical Applications

NASA Technical Reports Server (NTRS)

Katz, Rich; Flowers, David; Bergevin, Keith

2016-01-01

Due to the common use of Flash technology in many commercial and industrial Programmable Logic Devices (PLDs) such as FPGAs and mixed-signal microcontrollers, flash technology is being utilized in fuzed munition applications. This presents a long-term reliability issue for both DoD and NASA safety- and mission-critical applications. A thorough understanding of the data retention failure modes and statistics associated with Flash data retention is of vital concern to the fuze safety community. A key retention parameter for a flash cell is the threshold voltage (VTH), which is an indirect indicator of the amount of charge stored on the cells floating gate. Initial test results based on a study of charge loss in flash cells in an FPGA device is presented. Statistical data taken from a small sample set indicates quantifiable charge loss for devices stored at both room temperature and 150 C. Initial evaluation of the distribution of threshold voltage in a large sample set (800 devices) is presented. The magnitude of charge loss from exposure to electrostatic discharge and electromagnetic fields is measured and presented. Simulated data (and measured data as available) resultant from harsh-environment testing (neutron, heavy ion, EMP) is presented.

Metallorganic chemical vapor deposition and atomic layer deposition approaches for the growth of hafnium-based thin films from dialkylamide precursors for advanced CMOS gate stack applications

NASA Astrophysics Data System (ADS)

Consiglio, Steven P.

To continue the rapid progress of the semiconductor industry as described by Moore's Law, the feasibility of new material systems for front end of the line (FEOL) process technologies needs to be investigated, since the currently employed polysilicon/SiO2-based transistor system is reaching its fundamental scaling limits. Revolutionary breakthroughs in complementary-metal-oxide-semiconductor (CMOS) technology were recently announced by Intel Corporation and International Business Machines Corporation (IBM), with both organizations revealing significant progress in the implementation of hafnium-based high-k dielectrics along with metal gates. This announcement was heralded by Gordon Moore as "...the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s." Accordingly, the study described herein focuses on the growth of Hf-based dielectrics and Hf-based metal gates using chemical vapor-based deposition methods, specifically metallorganic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). A family of Hf source complexes that has received much attention recently due to their desirable properties for implementation in wafer scale manufacturing is the Hf dialkylamide precursors. These precursors are room temperature liquids and possess sufficient volatility and desirable decomposition characteristics for both MOCVD and ALD processing. Another benefit of using these sources is the existence of chemically compatible Si dialkylamide sources as co-precursors for use in Hf silicate growth. The first part of this study investigates properties of MOCVD-deposited HfO2 and HfSixOy using dimethylamido Hf and Si precursor sources using a customized MOCVD reactor. The second part of this study involves a study of wet and dry surface pre-treatments for ALD growth of HfO2 using tetrakis(ethylmethylamido)hafnium in a wafer scale manufacturing environment. The third part of this study is an investigation of the properties of conductive HfN grown via plasma-assisted atomic layer deposition (PA-ALD) using tetrakis(ethylmethylamido)hafnium on a modified commercially available wafer processing tool. Key properties of these materials for use as gate stack replacement materials are addressed and future directions for further characterization and novel material investigations are proposed.

A Compression Algorithm for Field Programmable Gate Arrays in the Space Environment

DTIC Science & Technology

2011-12-01

Bit 1 ,Bit 0P  . (V.3) Equation (V.3) is implemented with a string of XOR gates and Bit Basher blocks, as shown in Figure 31. As discussed in...5], the string of Bit Basher blocks are used to separate each 35-bit value into 35 one-bit values, and the string of XOR gates is used to

Qualification Strategies of Field Programmable Gate Arrays (FPGAs) for Space Application

NASA Technical Reports Server (NTRS)

Sheldon, Douglas; Schone, Harald

2005-01-01

This viewgraph document reviews the issue of using Field Programmable Gate Arrays (FPGAs) in Space Application, and the some of the strategies for qualifying the FPGA. Qualification and risk management of such complex systems requires new approaches. The paper presents a matrix approach to qualification has been presented that: - Complements historical specifications - Highlights the importance of device physics as a cornerstone to qualification. - Provides levels of risk management that expressly document trade offs. - Stresses the role of the FPGA vendor as team member in the development of modern spacecraft.

A software framework for pipelined arithmetic algorithms in field programmable gate arrays

NASA Astrophysics Data System (ADS)

Kim, J. B.; Won, E.

2018-03-01

Pipelined algorithms implemented in field programmable gate arrays are extensively used for hardware triggers in the modern experimental high energy physics field and the complexity of such algorithms increases rapidly. For development of such hardware triggers, algorithms are developed in C++, ported to hardware description language for synthesizing firmware, and then ported back to C++ for simulating the firmware response down to the single bit level. We present a C++ software framework which automatically simulates and generates hardware description language code for pipelined arithmetic algorithms.

An integrated interface for peripheral neural system recording and stimulation: system design, electrical tests and in-vivo results.

PubMed

Carboni, Caterina; Bisoni, Lorenzo; Carta, Nicola; Puddu, Roberto; Raspopovic, Stanisa; Navarro, Xavier; Raffo, Luigi; Barbaro, Massimo

2016-04-01

The prototype of an electronic bi-directional interface between the Peripheral Nervous System (PNS) and a neuro-controlled hand prosthesis is presented. The system is composed of 2 integrated circuits: a standard CMOS device for neural recording and a HVCMOS device for neural stimulation. The integrated circuits have been realized in 2 different 0.35μ m CMOS processes available from ams. The complete system incorporates 8 channels each including the analog front-end, the A/D conversion, based on a sigma delta architecture and a programmable stimulation module implemented as a 5-bit current DAC; two voltage boosters supply the output stimulation stage with a programmable voltage scalable up to 17V. Successful in-vivo experiments with rats having a TIME electrode implanted in the sciatic nerve were carried out, showing the capability of recording neural signals in the tens of microvolts, with a global noise of 7μ V r m s , and to selectively elicit the tibial and plantar muscles using different active sites of the electrode.

Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator

PubMed Central

Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

2016-01-01

The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (<100 Hz) with a capacitor of merely 6 fF, which is hosted in an FG metal-oxide-semiconductor field-effect transistor. The FG-LIF neuron also has the advantage of low operation power (<30 pW/spike). Finally, the proposed circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex. PMID:27242416

Molecular sensing using monolayer floating gate, fully depleted SOI MOSFET acting as an exponential transducer.

PubMed

Takulapalli, Bharath R

2010-02-23

Field-effect transistor-based chemical sensors fall into two broad categories based on the principle of signal transduction-chemiresistor or Schottky-type devices and MOSFET or inversion-type devices. In this paper, we report a new inversion-type device concept-fully depleted exponentially coupled (FDEC) sensor, using molecular monolayer floating gate fully depleted silicon on insulator (SOI) MOSFET. Molecular binding at the chemical-sensitive surface lowers the threshold voltage of the device inversion channel due to a unique capacitive charge-coupling mechanism involving interface defect states, causing an exponential increase in the inversion channel current. This response of the device is in opposite direction when compared to typical MOSFET-type sensors, wherein inversion current decreases in a conventional n-channel sensor device upon addition of negative charge to the chemical-sensitive device surface. The new sensor architecture enables ultrahigh sensitivity along with extraordinary selectivity. We propose the new sensor concept with the aid of analytical equations and present results from our experiments in liquid phase and gas phase to demonstrate the new principle of signal transduction. We present data from numerical simulations to further support our theory.

Pulse transmission transmitter including a higher order time derivate filter

DOEpatents

Dress, Jr., William B.; Smith, Stephen F.

2003-09-23

Systems and methods for pulse-transmission low-power communication modes are disclosed. A pulse transmission transmitter includes: a clock; a pseudorandom polynomial generator coupled to the clock, the pseudorandom polynomial generator having a polynomial load input; an exclusive-OR gate coupled to the pseudorandom polynomial generator, the exclusive-OR gate having a serial data input; a programmable delay circuit coupled to both the clock and the exclusive-OR gate; a pulse generator coupled to the programmable delay circuit; and a higher order time derivative filter coupled to the pulse generator. The systems and methods significantly reduce lower-frequency emissions from pulse transmission spread-spectrum communication modes, which reduces potentially harmful interference to existing radio frequency services and users and also simultaneously permit transmission of multiple data bits by utilizing specific pulse shapes.

Slowing DNA Translocation in a Nanofluidic Field-Effect Transistor.

PubMed

Liu, Yifan; Yobas, Levent

2016-04-26

Here, we present an experimental demonstration of slowing DNA translocation across a nanochannel by modulating the channel surface charge through an externally applied gate bias. The experiments were performed on a nanofluidic field-effect transistor, which is a monolithic integrated platform featuring a 50 nm-diameter in-plane alumina nanocapillary whose entire length is surrounded by a gate electrode. The field-effect transistor behavior was validated on the gating of ionic conductance and protein transport. The gating of DNA translocation was subsequently studied by measuring discrete current dips associated with single λ-DNA translocation events under a source-to-drain bias of 1 V. The translocation speeds under various gate bias conditions were extracted by fitting event histograms of the measured translocation time to the first passage time distributions obtained from a simple 1D biased diffusion model. A positive gate bias was observed to slow the translocation of single λ-DNA chains markedly; the translocation speed was reduced by an order of magnitude from 18.4 mm/s obtained under a floating gate down to 1.33 mm/s under a positive gate bias of 9 V. Therefore, a dynamic and flexible regulation of the DNA translocation speed, which is vital for single-molecule sequencing, can be achieved on this device by simply tuning the gate bias. The device is realized in a conventional semiconductor microfabrication process without the requirement of advanced lithography, and can be potentially further developed into a compact electronic single-molecule sequencer.

Graphene field-effect devices

NASA Astrophysics Data System (ADS)

Echtermeyer, T. J.; Lemme, M. C.; Bolten, J.; Baus, M.; Ramsteiner, M.; Kurz, H.

2007-09-01

In this article, graphene is investigated with respect to its electronic properties when introduced into field effect devices (FED). With the exception of manual graphene deposition, conventional top-down CMOS-compatible processes are applied. Few and monolayer graphene sheets are characterized by scanning electron microscopy, atomic force microscopy and Raman spectroscopy. The electrical properties of monolayer graphene sandwiched between two silicon dioxide films are studied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from double-gated Graphene-FEDs and silicon metal-oxide-semiconductor field-effect-transistors (MOSFETs).

ISITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI (Very Large Scale Integrated) Circuits

DTIC Science & Technology

1989-12-01

rows and columns should be minimized. There are two methodologies for achieving this objective, namely, logic minimization to I I I 15 I A B C D E T...type and N-type polysilicon (Figure 2.5( b )) and interconnecting the gates with metal at a later I processing step. The two layers of aluminum available...polysiliconI ...... .. ... .. .. . .. ... .. ... .. I N polysilicon Iii~~iiiiiiii~~iiiiii (a) ( b ) 3 Figure 2.5. Controlling the Threshold Voltage in

Towards a Minimal Architecture for a Printable, Modular, and Robust Sensing Skin

DTIC Science & Technology

2014-04-27

hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for...the total logic complexity and reduce sensor throughput. The final selection can be made to balance these effects given a specific application. Sensor...Company (TSMC)’s 65-nm GPLUSTC CMOS standard cells. Table II shows the number of gates (standard cells) and flip -flops generated for the given number of

A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience

NASA Astrophysics Data System (ADS)

Li, Y.-Q.; Wang, H.-B.; Liu, R.; Chen, L.; Nofal, I.; Shi, S.-T.; He, A.-L.; Guo, G.; Baeg, S. H.; Wen, S.-J.; Wong, R.; Chen, M.; Wu, Q.

2017-06-01

A flip-flop circuit hardened against soft errors is presented in this paper. This design is an improved version of Quatro for further enhanced soft-error resilience by integrating the guard-gate technique. The proposed design, as well as reference Quatro and regular flip-flops, was implemented and manufactured in a 65-nm CMOS bulk technology. Experimental characterization results of their alpha and heavy ions soft-error rates verified the superior hardening performance of the proposed design over the other two circuits.

CNES developments of key detection technologies to prepare next generation focal planes for high resolution Earth observation

NASA Astrophysics Data System (ADS)

Materne, A.; Virmontois, C.; Bardoux, A.; Gimenez, T.; Biffi, J. M.; Laubier, D.; Delvit, J. M.

2014-10-01

This paper describes the activities managed by CNES (French National Space Agency) for the development of focal planes for next generation of optical high resolution Earth observation satellites, in low sun-synchronous orbit. CNES has launched a new programme named OTOS, to increase the level of readiness (TRL) of several key technologies for high resolution Earth observation satellites. The OTOS programme includes several actions in the field of detection and focal planes: a new generation of CCD and CMOS image sensors, updated analog front-end electronics and analog-to-digital converters. The main features that must be achieved on focal planes for high resolution Earth Observation, are: readout speed, signal to noise ratio at low light level, anti-blooming efficiency, geometric stability, MTF and line of sight stability. The next steps targeted are presented in comparison to the in-flight measured performance of the PLEIADES satellites launched in 2011 and 2012. The high resolution panchromatic channel is still based upon Backside illuminated (BSI) CCDs operated in Time Delay Integration (TDI). For the multispectral channel, the main evolution consists in moving to TDI mode and the competition is open with the concurrent development of a CCD solution versus a CMOS solution. New CCDs will be based upon several process blocks under evaluation on the e2v 6 inches BSI wafer manufacturing line. The OTOS strategy for CMOS image sensors investigates on one hand custom TDI solutions within a similar approach to CCDs, and, on the other hand, investigates ways to take advantage of existing performance of off-the-shelf 2D arrays CMOS image sensors. We present the characterization results obtained from test vehicles designed for custom TDI operation on several CIS technologies and results obtained before and after radiation on snapshot 2D arrays from the CMOSIS CMV family.

SU-E-T-64: A Programmable Moving Insert for the ArcCHECK Phantom for Dose Verification of Respiratory-Gated VMAT

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gaede, S; Jordan, K; Western University, London, ON

Purpose: To present a customized programmable moving insert for the ArcCHECK™ phantom that can, in a single delivery, check both entrance dosimetry, while simultaneously verifying the delivery of respiratory-gated VMAT. Methods: The cylindrical motion phantom uses a computer-controlled stepping motor to move an insert inside a stationery sleeve. Insert motion is programmable and can include rotational motion in addition to linear motion along the axis of the cylinder. The sleeve fits securely in the bore of the ArcCHECK™. Interchangeable inserts, including an A1SL chamber, optically-stimulated luminescence dosimeters, radiochromic film, or 3D gels, allow this combination to be used for commissioning,more » routine quality assurance, and patient-specific dosimetric verification of respiratory-gated VMAT. Before clinical implementation, the effect of a moving insert on the ArcCHECK™ measurements was considered. First, the measured dose to the ArcCHECK™ containing multiple inserts in the static position was compared to the calculated dose during multiple VMAT treatment deliveries. Then, dose was measured under both sinusoidal and real-patient motion conditions to determine any effect of the moving inserts on the ArcCHECK™ measurements. Finally, dose was measured during gated VMAT delivery to the same inserts under the same motion conditions to examine any effect of various beam “on-and-off” and dose rate ramp “up-and-down”. Multiple comparisons between measured and calculated dose to different inserts were also considered. Results: The pass rate for the static delivery exceeded 98% for all measurements (3%/3mm), suggesting a valid setup for entrance dosimetry. The pass rate was not altered for any measurement delivered under motion conditions. A similar Result was observed under gated VMAT conditions, including agreement of measured and calculated dose to the various inserts. Conclusion: Incorporating a programmable moving insert within the ArcCHECK™ phantom provides an efficient verification of respiratory-gated VMAT delivery that is useful during commissioning, routine quality assurance, and patient-specific dose verification. Prototype phantom development and testing was performed in collaboration with Modus Medical Devices Inc. (London, ON). No financial support was granted.« less

Toward a distributed free-floating wireless implantable neural recording system.

PubMed

Pyungwoo Yeon; Xingyuan Tong; Byunghun Lee; Mirbozorgi, Abdollah; Ash, Bruce; Eckhardt, Helmut; Ghovanloo, Maysam

2016-08-01

To understand the complex correlations between neural networks across different regions in the brain and their functions at high spatiotemporal resolution, a tool is needed for obtaining long-term single unit activity (SUA) across the entire brain area. The concept and preliminary design of a distributed free-floating wireless implantable neural recording (FF-WINeR) system are presented, which can enabling SUA acquisition by dispersedly implanting tens to hundreds of untethered 1 mm3 neural recording probes, floating with the brain and operating wirelessly across the cortical surface. For powering FF-WINeR probes, a 3-coil link with an intermediate high-Q resonator provides a minimum S21 of -22.22 dB (in the body medium) and -21.23 dB (in air) at 2.8 cm coil separation, which translates to 0.76%/759 μW and 0.6%/604 μW of power transfer efficiency (PTE) / power delivered to a 9 kΩ load (PDL), in body and air, respectively. A mock-up FF-WINeR is implemented to explore microassembly method of the 1×1 mm2 micromachined silicon die with a bonding wire-wound coil and a tungsten micro-wire electrode. Circuit design methods to fit the active circuitry in only 0.96 mm2 of die area in a 130 nm standard CMOS process, and satisfy the strict power and performance requirements (in simulations) are discussed.

Valleytronics in merging Dirac cones: All-electric-controlled valley filter, valve, and universal reversible logic gate

NASA Astrophysics Data System (ADS)

Ang, Yee Sin; Yang, Shengyuan A.; Zhang, C.; Ma, Zhongshui; Ang, L. K.

2017-12-01

Despite much anticipation of valleytronics as a candidate to replace the aging complementary metal-oxide-semiconductor (CMOS) based information processing, its progress is severely hindered by the lack of practical ways to manipulate valley polarization all electrically in an electrostatic setting. Here, we propose a class of all-electric-controlled valley filter, valve, and logic gate based on the valley-contrasting transport in a merging Dirac cones system. The central mechanism of these devices lies on the pseudospin-assisted quantum tunneling which effectively quenches the transport of one valley when its pseudospin configuration mismatches that of a gate-controlled scattering region. The valley polarization can be abruptly switched into different states and remains stable over semi-infinite gate-voltage windows. Colossal tunneling valley-pseudomagnetoresistance ratio of over 10 000 % can be achieved in a valley-valve setup. We further propose a valleytronic-based logic gate capable of covering all 16 types of two-input Boolean logics. Remarkably, the valley degree of freedom can be harnessed to resurrect logical reversibility in two-input universal Boolean gate. The (2 +1 ) polarization states (two distinct valleys plus a null polarization) reestablish one-to-one input-to-output mapping, a crucial requirement for logical reversibility, and significantly reduce the complexity of reversible circuits. Our results suggest that the synergy of valleytronics and digital logics may provide new paradigms for valleytronic-based information processing and reversible computing.

The Contribution of a Particular "Kids in Parks" Programme to the Professional Development of Teachers

ERIC Educational Resources Information Center

Ferreira, J. G.

2014-01-01

This article considers the possible contribution of the "kids in parks" programme offered at Golden Gate Highlands National Park to the professional development of teachers. Focus group interviews were held with teachers who participated in the programme, and an interview with open-ended questions was held with a learning facilitator…

Expanding Access, Participation, and Success in International Baccalaureate Programmes: Year 1 Documentation Report

ERIC Educational Resources Information Center

Corcoran, Thomas B.; Gerry, Gail B.

2010-01-01

In fall 2009, the Bill and Melinda Gates Foundation funded a three-year project (IB Access Project) with International Baccalaureate (IB) to increase participation of minority students and students in poverty in the Middle Years Programme (MYP) and Diploma Programme (DP). The IB Access Project seeks to do four things: (1) Improve teacher practice…

Demonstration of a wireless driven MEMS pond skater that uses EWOD technology

NASA Astrophysics Data System (ADS)

Mita, Y.; Li, Y.; Kubota, M.; Morishita, S.; Parkes, W.; Haworth, L. I.; Flynn, B. W.; Terry, J. G.; Tang, T.-B.; Ruthven, A. D.; Smith, S.; Walton, A. J.

2009-07-01

A silicon swimming robot or pond skating device has been demonstrated. It floats on liquid surfaces using surface tension and is capable of movement using electrowetting on dielectric (EWOD) based propulsion. Its dimensions are 6 × 9 mm and the driving mechanism involves first trapping air bubbles within the liquid onto the hydrophobic surface of the device. The air bubbles are then moved using EWOD, which provides the propulsion. The device employs a recently reported TaO EWOD technology enabling a driving voltage of ≈15 V, which is low enough for RF power transmission, thus facilitating wire-free movement. A wired version has been measured to move 1.35 mm in 168 ms (a speed of 8 mm s -1). This low voltage-EWOD (<15 V) device, fabricated using a CMOS compatible process, is believed to be the world's smallest swimming MEMS device that has no mechanical moving parts. The paper also reports results of EWOD droplet operation driven by wireless power transmission and demonstrates that such a wireless design can be successfully mounted on a floating EWOD device to produce movement.

Two-color detection with charge sensitive infrared phototransistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Sunmi, E-mail: kimsunmi@iis.u-tokyo.ac.jp; Kajihara, Yusuke; Komiyama, Susumu

2015-11-02

Highly sensitive two-color detection is demonstrated at wavelengths of 9 μm and 14.5 μm by using a charge sensitive infrared phototransistor fabricated in a triple GaAs/AlGaAs quantum well (QW) crystal. Two differently thick QWs (7 nm- and 9 nm-thicknesses) serve as photosensitive floating gates for the respective wavelengths via intersubband excitation: The excitation in the QWs is sensed by a third QW, which works as a conducting source-drain channel in the photosensitive transistor. The two spectral bands of detection are shown to be controlled by front-gate biasing, providing a hint for implementing voltage tunable ultra-highly sensitive detectors.

Construction and Characterization of a Compact, Portable, Low-Cost Colorimeter for the Chemistry Lab

ERIC Educational Resources Information Center

Clippard, Carrie M.; Hughes, William; Chohan, Balwant S.; Sykes, Danny G.

2016-01-01

A low-cost and portable colorimeter was constructed featuring a low-voltage programmable color light sensor-to-frequency converter, a CMOS 8-bit microcontroller, and an LCD display. The instrument has successfully facilitated the introduction and application of spectroscopy to groups of middle school, high school, and undergraduate students. A…

Design of a 0.13-μm CMOS cascade expandable ΣΔ modulator for multi-standard RF telecom systems

NASA Astrophysics Data System (ADS)

Morgado, Alonso; del Río, Rocío; de la Rosa, José M.

2007-05-01

This paper reports a 130-nm CMOS programmable cascade ΣΔ modulator for multi-standard wireless terminals, capable of operating on three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuit- level in order to adapt its performance to the different standards specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.

Nanocharacterization Challenges in a Changing Microelectronics Landscape

NASA Astrophysics Data System (ADS)

Brilloüt, Michel

2011-11-01

As the microelectronics industry enters the "nano"-era new challenges emerge. Traditional scaling of the MOS transistor faces major obstacles in fulfilling "Moore's law". New features like strain and new materials (e.g. high k—metal gate stack) are introduced in order to sustain performance increases. For a better electrostatic control, devices will use the third dimension, e.g., in gate-all-around nanowire structures. Due to the escalating cost and complexity of sub-28 nm technologies fewer industrial players can afford the development and production of advanced CMOS processes and many companies acknowledge the fact that the value in products can also be obtained in using more diversified non-digital technologies (the so-called "More-than-Moore" domain). This evolving landscape brings new requirements—discussed in this paper—in terms of physical characterization of technologies and devices.

Germanium CMOS potential from material and process perspectives: Be more positive about germanium

NASA Astrophysics Data System (ADS)

Toriumi, Akira; Nishimura, Tomonori

2018-01-01

CMOS miniaturization is now approaching the sub-10 nm level, and further downscaling is expected. This size scaling will end sooner or later, however, because the typical size is approaching the atomic distance level in crystalline Si. In addition, it is said that electron transport in FETs is ballistic or nearly ballistic, which means that the injection velocity at the virtual source is a physical parameter relevant for estimating the driving current. Channel-materials with higher carrier mobility than Si are nonetheless needed, and the carrier mobility in the channels is a parameter important with regard to increasing the injection velocity. Although the density of states in the channel has not been discussed often, it too is relevant for estimating the channel current. Both the mobility and the density of states are in principle related to the effective mass of the carrier. From this device physics viewpoint, we expect germanium (Ge) CMOS to be promising for scaling beyond the Si CMOS limit because the bulk mobility values of electrons and holes in Ge are much higher than those of electrons and holes in Si, and the electron effective mass in Ge is not much less than that in III-V compounds. There is a debate that Ge should be used for p-MOSFETs and III-V compounds for n-MOSFETs, but considering that the variability or nonuniformity of the FET performance in today’s CMOS LSIs is a big challenge, it seems that much more attention should be paid to the simplicity of the material design and of the processing steps. Nevertheless, Ge faces a number of challenges even in case that only the FET level is concerned. One of the big problems with Ge CMOS technology has been its poor performance in n-MOSFETs. While the hole mobility in p-FETs has been improved, the electron mobility in the inversion layer of Ge FETs remains a serious concern. If this is due to the inherent properties of Ge, only p-MOSFETs might be used for device applications. To make Ge CMOS devices practically viable, we need to understand why electron mobility is severely degraded in the inversion layer in Ge n-channel MOSFETs and to find out how it can be increased. In the Si CMOS technology, the SiO2/Si interface has long been investigated and cannot be ignored even after the introduction of high-k gate stack technology. In that sense, the GeO2/Ge interface should be intensively studied to make the best of Ge’s advantages. Therefore we first discuss the GeO2/Ge interface with regard to its physical and electrical characteristics. When we regard Ge as a channel material beyond Si for high performance ULSIs, we also have to seriously consider the gate stack scalability and reliability. The source/drain engineering, as well as the gate stack formation, is another challenge in Ge MOSFET design. Both the higher metal/Ge contact resistance and the larger p/n junction leakage current may be the consequences of Ge’s intrinsic properties because they are derived from the strong Fermi-level pinning and the narrow energy band gap, respectively. Even if the carrier transport in the channel may be ideally ballistic, these properties should degrade FET properties. The narrower energy band gap of Ge is often addressed, but the higher dielectric constant of Ge is rarely discussed. This is also the case for most of the other high-mobility materials. The dielectric constant is directly and negatively related to short-channel effects, and we have not been able to provide a substantial solution to overcome this hardship. We have to keep this in mind for the short-channel FET operation. Although a number of problems remain to be solved, in this paper, we view the current status of Ge FET technology positively. A number of (but not all) Ge-related challenges have been overcome in the past 10 years, which seems to be a good time to summarize the status of Ge technology, particularly materials engineering aspects rather than device integration issues. Since we cannot cover all of the results published to date, we mainly discuss fundamental aspects based on our experimental results. Remaining challenges are also addressed but not comprehensively. Integration issues are not discussed in this review. Finally, new types of electron devices utilizing Ge’s advantages are briefly introduced on the basis of our experimental results.

All optical programmable logic array (PLA)

NASA Astrophysics Data System (ADS)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Photonic Programmable Tele-Cloning Network.

PubMed

Li, Wei; Chen, Ming-Cheng

2016-06-29

The concept of quantum teleportation allows an unknown quantum states to be broadcasted and processed in a distributed quantum network. The quantum information injected into the network can be diluted to distant multi-copies by quantum cloning and processed by arbitrary quantum logic gates which were programed in advance in the network quantum state. A quantum network combines simultaneously these fundamental quantum functions could lead to new intriguing applications. Here we propose a photonic programmable telecloning network based on a four-photon interferometer. The photonic network serves as quantum gate, quantum cloning and quantum teleportation and features experimental advantage of high brightness by photon recycling.

TID Effects of High-Z Material Spot Shields on FPGA Using MPTB Data

NASA Technical Reports Server (NTRS)

Hardage, Donna (Technical Monitor); Crain, S. H.; Mazur, J. E.; Looper, M. D.

2003-01-01

An experiment on the Microelectronics and Photonics Test Bed (MPTB) was testing lield programmable gate arrays using spot shields to extend the life of some of the devices being tested. It was expected that the unshielded parts would fail from a total ionizing dose (TID) and yet the opposite occurred. The data show that the devices failing from the TID effects are those with the spot shields attached. This effort is to determine the mechanism by which the environment is interacting with the high-Z material to enhance the TID in these field programmable gate arrays.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array.

PubMed

Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Liang, Futian; Jin, Ge

2015-01-01

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability.

Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong (Inventor); Herath, Jeffrey A. (Inventor)

2010-01-01

An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.

Note: The design of thin gap chamber simulation signal source based on field programmable gate array

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hu, Kun; Wang, Xu; Li, Feng

The Thin Gap Chamber (TGC) is an important part of ATLAS detector and LHC accelerator. Targeting the feature of the output signal of TGC detector, we have designed a simulation signal source. The core of the design is based on field programmable gate array, randomly outputting 256-channel simulation signals. The signal is generated by true random number generator. The source of randomness originates from the timing jitter in ring oscillators. The experimental results show that the random number is uniform in histogram, and the whole system has high reliability.